/* Block size X: 32 */
__global__ void fct_ale_a2(const int maxLevels, const int * __restrict__ nLevels, const int * __restrict__ elementNodes, double2 * __restrict__ UV_rhs, const double * __restrict__ fct_ttf_max, const double * __restrict__ fct_ttf_min)
{
const unsigned int element_index = (blockIdx.x * maxLevels);
const unsigned int element_node0_index = (elementNodes[(blockIdx.x * 3)] - 1) * maxLevels;
const unsigned int element_node1_index = (elementNodes[(blockIdx.x * 3) + 1] - 1) * maxLevels;
const unsigned int element_node2_index = (elementNodes[(blockIdx.x * 3) + 2] - 1) * maxLevels;
for ( unsigned int level = threadIdx.x; level < maxLevels + 1; level += 32 )
{
if ( level < nLevels[blockIdx.x] - 1 )
{
double2 temp = make_double2(0.0, 0.0);
temp.x = fmax(fct_ttf_max[element_node0_index + level], fct_ttf_max[element_node1_index + level]);
temp.x = fmax(temp.x, fct_ttf_max[element_node2_index + level]);
temp.y = fmin(fct_ttf_min[element_node0_index + level], fct_ttf_min[element_node1_index + level]);
temp.y = fmin(temp.y, fct_ttf_min[element_node2_index + level]);
UV_rhs[element_index + level] = temp;
}
else if ( level < maxLevels - 1 )
{
UV_rhs[element_index + level] = make_double2(-1.e+3, 1.e+3);
}
}
}
	.file	"tmpxft_00296e4c_00000000-6_fct_ale_a2.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2010:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2010:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z50__device_stub__Z10fct_ale_a2iPKiS0_P7double2PKdS4_iPKiS0_P7double2PKdS4_
	.type	_Z50__device_stub__Z10fct_ale_a2iPKiS0_P7double2PKdS4_iPKiS0_P7double2PKdS4_, @function
_Z50__device_stub__Z10fct_ale_a2iPKiS0_P7double2PKdS4_iPKiS0_P7double2PKdS4_:
.LFB2032:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movl	%edi, 12(%rsp)
	leaq	72(%rsp), %rdi
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	12(%rsp), %rax
	movq	%rsi, 16(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rax, 120(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	48(%rsp), %rax
	movq	%rdx, 24(%rsp)
	leaq	56(%rsp), %rdx
	movq	%rcx, 32(%rsp)
	leaq	64(%rsp), %rcx
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%r8, 40(%rsp)
	movq	%r9, 48(%rsp)
	movq	%rax, 72(%rsp)
	movl	$1, 80(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	64(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z10fct_ale_a2iPKiS0_P7double2PKdS4_(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 208
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L2:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2032:
	.size	_Z50__device_stub__Z10fct_ale_a2iPKiS0_P7double2PKdS4_iPKiS0_P7double2PKdS4_, .-_Z50__device_stub__Z10fct_ale_a2iPKiS0_P7double2PKdS4_iPKiS0_P7double2PKdS4_
	.globl	_Z10fct_ale_a2iPKiS0_P7double2PKdS4_
	.type	_Z10fct_ale_a2iPKiS0_P7double2PKdS4_, @function
_Z10fct_ale_a2iPKiS0_P7double2PKdS4_:
.LFB2033:
	.cfi_startproc
	endbr64
	jmp	_Z50__device_stub__Z10fct_ale_a2iPKiS0_P7double2PKdS4_iPKiS0_P7double2PKdS4_
	.cfi_endproc
.LFE2033:
	.size	_Z10fct_ale_a2iPKiS0_P7double2PKdS4_, .-_Z10fct_ale_a2iPKiS0_P7double2PKdS4_
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z10fct_ale_a2iPKiS0_P7double2PKdS4_"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2035:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z10fct_ale_a2iPKiS0_P7double2PKdS4_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2035:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
/* Block size X: 32 */
__global__ void fct_ale_a2(const int maxLevels, const int * __restrict__ nLevels, const int * __restrict__ elementNodes, double2 * __restrict__ UV_rhs, const double * __restrict__ fct_ttf_max, const double * __restrict__ fct_ttf_min)
{
const unsigned int element_index = (blockIdx.x * maxLevels);
const unsigned int element_node0_index = (elementNodes[(blockIdx.x * 3)] - 1) * maxLevels;
const unsigned int element_node1_index = (elementNodes[(blockIdx.x * 3) + 1] - 1) * maxLevels;
const unsigned int element_node2_index = (elementNodes[(blockIdx.x * 3) + 2] - 1) * maxLevels;
for ( unsigned int level = threadIdx.x; level < maxLevels + 1; level += 32 )
{
if ( level < nLevels[blockIdx.x] - 1 )
{
double2 temp = make_double2(0.0, 0.0);
temp.x = fmax(fct_ttf_max[element_node0_index + level], fct_ttf_max[element_node1_index + level]);
temp.x = fmax(temp.x, fct_ttf_max[element_node2_index + level]);
temp.y = fmin(fct_ttf_min[element_node0_index + level], fct_ttf_min[element_node1_index + level]);
temp.y = fmin(temp.y, fct_ttf_min[element_node2_index + level]);
UV_rhs[element_index + level] = temp;
}
else if ( level < maxLevels - 1 )
{
UV_rhs[element_index + level] = make_double2(-1.e+3, 1.e+3);
}
}
}
	.text
	.file	"fct_ale_a2.hip"
	.globl	_Z25__device_stub__fct_ale_a2iPKiS0_P15HIP_vector_typeIdLj2EEPKdS5_ # -- Begin function _Z25__device_stub__fct_ale_a2iPKiS0_P15HIP_vector_typeIdLj2EEPKdS5_
	.type	_Z25__device_stub__fct_ale_a2iPKiS0_P15HIP_vector_typeIdLj2EEPKdS5_,@function
_Z25__device_stub__fct_ale_a2iPKiS0_P15HIP_vector_typeIdLj2EEPKdS5_: # @_Z25__device_stub__fct_ale_a2iPKiS0_P15HIP_vector_typeIdLj2EEPKdS5_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	4(%rsp), %rax
	movl	%edi, (%rax)
	leaq	56(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	48(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	40(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	32(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	24(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z10fct_ale_a2iPKiS0_P15HIP_vector_typeIdLj2EEPKdS5_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z25__device_stub__fct_ale_a2iPKiS0_P15HIP_vector_typeIdLj2EEPKdS5_, .Lfunc_end0-_Z25__device_stub__fct_ale_a2iPKiS0_P15HIP_vector_typeIdLj2EEPKdS5_
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z10fct_ale_a2iPKiS0_P15HIP_vector_typeIdLj2EEPKdS5_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z10fct_ale_a2iPKiS0_P15HIP_vector_typeIdLj2EEPKdS5_,@object # @_Z10fct_ale_a2iPKiS0_P15HIP_vector_typeIdLj2EEPKdS5_
	.section	.rodata,"a",@progbits
	.globl	_Z10fct_ale_a2iPKiS0_P15HIP_vector_typeIdLj2EEPKdS5_
	.p2align	3, 0x0
_Z10fct_ale_a2iPKiS0_P15HIP_vector_typeIdLj2EEPKdS5_:
	.quad	_Z25__device_stub__fct_ale_a2iPKiS0_P15HIP_vector_typeIdLj2EEPKdS5_
	.size	_Z10fct_ale_a2iPKiS0_P15HIP_vector_typeIdLj2EEPKdS5_, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z10fct_ale_a2iPKiS0_P15HIP_vector_typeIdLj2EEPKdS5_"
	.size	.L__unnamed_1, 53

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z25__device_stub__fct_ale_a2iPKiS0_P15HIP_vector_typeIdLj2EEPKdS5_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z10fct_ale_a2iPKiS0_P15HIP_vector_typeIdLj2EEPKdS5_
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z10fct_ale_a2iPKiS0_P15HIP_vector_typeIdLj2EEPKdS5_ ; -- Begin function _Z10fct_ale_a2iPKiS0_P15HIP_vector_typeIdLj2EEPKdS5_
	.globl	_Z10fct_ale_a2iPKiS0_P15HIP_vector_typeIdLj2EEPKdS5_
	.p2align	8
	.type	_Z10fct_ale_a2iPKiS0_P15HIP_vector_typeIdLj2EEPKdS5_,@function
_Z10fct_ale_a2iPKiS0_P15HIP_vector_typeIdLj2EEPKdS5_: ; @_Z10fct_ale_a2iPKiS0_P15HIP_vector_typeIdLj2EEPKdS5_
; %bb.0:
	s_load_b32 s17, s[0:1], 0x0
	s_mov_b32 s2, exec_lo
	s_waitcnt lgkmcnt(0)
	s_add_i32 s14, s17, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	v_cmpx_gt_u32_e64 s14, v0
	s_cbranch_execz .LBB0_9
; %bb.1:                                ; %.lr.ph
	s_load_b256 s[4:11], s[0:1], 0x8
	s_mul_i32 s2, s15, 3
	s_mov_b32 s3, 0
	s_mov_b32 s12, s15
	s_lshl_b64 s[18:19], s[2:3], 2
	v_mov_b32_e32 v6, 0
	s_waitcnt lgkmcnt(0)
	s_add_u32 s18, s6, s18
	s_addc_u32 s19, s7, s19
	s_load_b32 s13, s[18:19], 0x0
	s_mov_b32 s19, s3
	s_add_i32 s18, s2, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_lshl_b64 s[18:19], s[18:19], 2
	s_waitcnt lgkmcnt(0)
	s_add_i32 s15, s13, -1
	s_add_u32 s18, s6, s18
	s_addc_u32 s19, s7, s19
	s_add_i32 s2, s2, 2
	s_load_b32 s13, s[18:19], 0x0
	s_lshl_b64 s[18:19], s[2:3], 2
	s_waitcnt lgkmcnt(0)
	s_add_i32 s16, s13, -1
	s_add_u32 s6, s6, s18
	s_addc_u32 s7, s7, s19
	s_mov_b32 s13, s3
	s_load_b32 s2, s[6:7], 0x0
	s_lshl_b64 s[6:7], s[12:13], 2
	s_mul_i32 s13, s16, s17
	s_waitcnt lgkmcnt(0)
	s_add_i32 s18, s2, -1
	s_add_u32 s4, s4, s6
	s_addc_u32 s5, s5, s7
	s_mul_i32 s2, s12, s17
	s_load_b32 s4, s[4:5], 0x0
	s_load_b64 s[0:1], s[0:1], 0x28
	s_mul_i32 s12, s15, s17
	s_mul_i32 s15, s18, s17
	s_add_i32 s17, s17, -1
	s_waitcnt lgkmcnt(0)
	s_add_i32 s16, s4, -1
.LBB0_2:                                ; =>This Inner Loop Header: Depth=1
	s_mov_b32 s18, 0
	s_mov_b32 s19, exec_lo
                                        ; implicit-def: $sgpr6_sgpr7
                                        ; implicit-def: $sgpr4_sgpr5
	v_cmpx_le_u32_e64 s16, v0
	s_xor_b32 s19, exec_lo, s19
; %bb.3:                                ;   in Loop: Header=BB0_2 Depth=1
	v_cmp_gt_u32_e32 vcc_lo, s17, v0
	s_mov_b32 s4, 0
	s_mov_b32 s6, 0
	s_mov_b32 s5, 0xc08f4000
	s_mov_b32 s7, 0x408f4000
	s_and_b32 s18, vcc_lo, exec_lo
; %bb.4:                                ; %Flow
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_saveexec_b32 s19, s19
	v_dual_mov_b32 v3, s6 :: v_dual_mov_b32 v4, s7
	v_dual_mov_b32 v1, s4 :: v_dual_mov_b32 v2, s5
	s_xor_b32 exec_lo, exec_lo, s19
	s_cbranch_execz .LBB0_6
; %bb.5:                                ;   in Loop: Header=BB0_2 Depth=1
	v_add_nc_u32_e32 v5, s12, v0
	s_or_b32 s18, s18, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 3, v[5:6]
	v_add_nc_u32_e32 v5, s13, v0
	v_lshlrev_b64 v[3:4], 3, v[5:6]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v7, vcc_lo, s10, v1
	v_add_co_ci_u32_e32 v8, vcc_lo, s11, v2, vcc_lo
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	v_add_co_u32 v9, vcc_lo, s10, v3
	v_add_co_ci_u32_e32 v10, vcc_lo, s11, v4, vcc_lo
	v_add_co_u32 v3, vcc_lo, s0, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
	global_load_b64 v[7:8], v[7:8], off
	global_load_b64 v[1:2], v[1:2], off
	global_load_b64 v[9:10], v[9:10], off
	global_load_b64 v[3:4], v[3:4], off
	v_add_nc_u32_e32 v5, s15, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[11:12], 3, v[5:6]
	v_add_co_u32 v13, vcc_lo, s10, v11
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v14, vcc_lo, s11, v12, vcc_lo
	v_add_co_u32 v11, vcc_lo, s0, v11
	v_add_co_ci_u32_e32 v12, vcc_lo, s1, v12, vcc_lo
	global_load_b64 v[13:14], v[13:14], off
	global_load_b64 v[11:12], v[11:12], off
	s_waitcnt vmcnt(5)
	v_max_f64 v[7:8], v[7:8], v[7:8]
	s_waitcnt vmcnt(4)
	v_max_f64 v[1:2], v[1:2], v[1:2]
	s_waitcnt vmcnt(3)
	v_max_f64 v[9:10], v[9:10], v[9:10]
	s_waitcnt vmcnt(2)
	v_max_f64 v[3:4], v[3:4], v[3:4]
	s_waitcnt vmcnt(1)
	v_max_f64 v[13:14], v[13:14], v[13:14]
	s_waitcnt vmcnt(0)
	v_max_f64 v[11:12], v[11:12], v[11:12]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_max_f64 v[7:8], v[7:8], v[9:10]
	v_min_f64 v[3:4], v[1:2], v[3:4]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_max_f64 v[1:2], v[7:8], v[13:14]
	v_min_f64 v[3:4], v[3:4], v[11:12]
.LBB0_6:                                ; %Flow53
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s19
	s_and_saveexec_b32 s4, s18
	s_cbranch_execz .LBB0_8
; %bb.7:                                ; %.sink.split
                                        ;   in Loop: Header=BB0_2 Depth=1
	v_add_nc_u32_e32 v5, s2, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[7:8], 4, v[5:6]
	v_add_co_u32 v7, vcc_lo, s8, v7
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v8, vcc_lo, s9, v8, vcc_lo
	global_store_b128 v[7:8], v[1:4], off
.LBB0_8:                                ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s4
	v_add_nc_u32_e32 v0, 32, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_le_u32_e32 vcc_lo, s14, v0
	s_or_b32 s3, vcc_lo, s3
	s_and_not1_b32 exec_lo, exec_lo, s3
	s_cbranch_execnz .LBB0_2
.LBB0_9:                                ; %Flow55
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z10fct_ale_a2iPKiS0_P15HIP_vector_typeIdLj2EEPKdS5_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 48
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 15
		.amdhsa_next_free_sgpr 20
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z10fct_ale_a2iPKiS0_P15HIP_vector_typeIdLj2EEPKdS5_, .Lfunc_end0-_Z10fct_ale_a2iPKiS0_P15HIP_vector_typeIdLj2EEPKdS5_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 684
; NumSgprs: 22
; NumVgprs: 15
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 22
; NumVGPRsForWavesPerEU: 15
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     by_value
      - .actual_access:  read_only
        .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .actual_access:  read_only
        .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .actual_access:  write_only
        .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .actual_access:  read_only
        .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .actual_access:  read_only
        .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 48
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z10fct_ale_a2iPKiS0_P15HIP_vector_typeIdLj2EEPKdS5_
    .private_segment_fixed_size: 0
    .sgpr_count:     22
    .sgpr_spill_count: 0
    .symbol:         _Z10fct_ale_a2iPKiS0_P15HIP_vector_typeIdLj2EEPKdS5_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     15
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
