/*
 * gpu_physical_model.c
 *
 *  Created on: Jan 24, 2016
 *      Author: sled
 */

//
// Physical model GPU implementation
//
#include <unistd.h>
#include <stdlib.h>
#include <math.h>

#define THREADS_PER_BLOCK		128

// CUDA kernel declaration
__global__ void cuda_physical_model_kernel(double g, double K, double vx_0, double vy_0, double vz_0, double *x, double *y, double *z, int N);

// C/C++ Wrapper
void gpu_physical_model_compute(double g, double K, double vx_0, double vy_0, double vz_0, double *x, double *y, double *z, int N)
{
	// Device memory
	double *dev_x;
	double *dev_y;
	double *dev_z;

	size_t size = N * sizeof(double);

	// Allocated device memory
	cudaMalloc((void **)&dev_x, size);
	cudaMalloc((void **)&dev_y, size);
	cudaMalloc((void **)&dev_z, size);

	// Upload data to device memory
	cudaMemcpy(dev_x, x, size, cudaMemcpyHostToDevice);
	cudaMemcpy(dev_y, y, size, cudaMemcpyHostToDevice);
	cudaMemcpy(dev_z, z, size, cudaMemcpyHostToDevice);

	cuda_physical_model_kernel<<<((N + THREADS_PER_BLOCK - 1) / THREADS_PER_BLOCK), THREADS_PER_BLOCK>>>(g, K, vx_0, vy_0, vz_0, dev_x, dev_y, dev_z, N);

	cudaMemcpy(x, dev_x, size, cudaMemcpyDeviceToHost);
	cudaMemcpy(y, dev_y, size, cudaMemcpyDeviceToHost);
	cudaMemcpy(z, dev_z, size, cudaMemcpyDeviceToHost);

	cudaFree(dev_x);
	cudaFree(dev_y);
	cudaFree(dev_z);
}

// GPU memory buffers are filled with computed physical states 3D components
__global__ void cuda_physical_model_kernel(double g, double K, double vx_0, double vy_0, double vz_0, double *x, double *y, double *z, int N)
{
	int idx = threadIdx.x + (blockDim.x *blockIdx.x);

	if (idx == 0)
		return;

	if (idx < N) {
		x[idx] = x[0] + (vx_0 / K) * (1.0 - exp(-K * idx)/K);
		y[idx] = y[0] + ((g + K * vy_0) / (K * K)) * (1.0 - exp(-K * idx)) - (g * idx) / K;
		z[idx] = z[0] + (vz_0 / K) * (1.0 - exp(-K * idx)/K);
	}
}




	.file	"tmpxft_0032af08_00000000-6_gpu_physical_model.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2024:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2024:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z56__device_stub__Z26cuda_physical_model_kerneldddddPdS_S_idddddPdS_S_i
	.type	_Z56__device_stub__Z26cuda_physical_model_kerneldddddPdS_S_idddddPdS_S_i, @function
_Z56__device_stub__Z26cuda_physical_model_kerneldddddPdS_S_idddddPdS_S_i:
.LFB2046:
	.cfi_startproc
	endbr64
	subq	$232, %rsp
	.cfi_def_cfa_offset 240
	movq	%rdi, 32(%rsp)
	leaq	96(%rsp), %rdi
	movq	%rsi, 24(%rsp)
	leaq	108(%rsp), %rsi
	movq	%rdx, 16(%rsp)
	leaq	80(%rsp), %rdx
	movl	%ecx, 12(%rsp)
	leaq	88(%rsp), %rcx
	movsd	%xmm0, 72(%rsp)
	movsd	%xmm1, 64(%rsp)
	movsd	%xmm2, 56(%rsp)
	movsd	%xmm3, 48(%rsp)
	movsd	%xmm4, 40(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 216(%rsp)
	xorl	%eax, %eax
	leaq	72(%rsp), %rax
	movl	$1, 104(%rsp)
	movq	%rax, 144(%rsp)
	leaq	64(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	56(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 208(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 96(%rsp)
	movq	%rax, 108(%rsp)
	movl	$1, 116(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	88(%rsp)
	.cfi_def_cfa_offset 248
	leaq	_Z26cuda_physical_model_kerneldddddPdS_S_i(%rip), %rdi
	pushq	88(%rsp)
	.cfi_def_cfa_offset 256
	movq	124(%rsp), %rcx
	movl	132(%rsp), %r8d
	movq	112(%rsp), %rsi
	movl	120(%rsp), %edx
	leaq	160(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 248
	popq	%rdx
	.cfi_def_cfa_offset 240
.L2:
	movq	216(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$232, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2046:
	.size	_Z56__device_stub__Z26cuda_physical_model_kerneldddddPdS_S_idddddPdS_S_i, .-_Z56__device_stub__Z26cuda_physical_model_kerneldddddPdS_S_idddddPdS_S_i
	.globl	_Z26cuda_physical_model_kerneldddddPdS_S_i
	.type	_Z26cuda_physical_model_kerneldddddPdS_S_i, @function
_Z26cuda_physical_model_kerneldddddPdS_S_i:
.LFB2047:
	.cfi_startproc
	endbr64
	jmp	_Z56__device_stub__Z26cuda_physical_model_kerneldddddPdS_S_idddddPdS_S_i
	.cfi_endproc
.LFE2047:
	.size	_Z26cuda_physical_model_kerneldddddPdS_S_i, .-_Z26cuda_physical_model_kerneldddddPdS_S_i
	.globl	_Z26gpu_physical_model_computedddddPdS_S_i
	.type	_Z26gpu_physical_model_computedddddPdS_S_i, @function
_Z26gpu_physical_model_computedddddPdS_S_i:
.LFB2021:
	.cfi_startproc
	endbr64
	pushq	%r14
	.cfi_def_cfa_offset 16
	.cfi_offset 14, -16
	pushq	%r13
	.cfi_def_cfa_offset 24
	.cfi_offset 13, -24
	movq	%rdx, %r13
	pushq	%r12
	.cfi_def_cfa_offset 32
	.cfi_offset 12, -32
	movq	%rdi, %r12
	pushq	%rbp
	.cfi_def_cfa_offset 40
	.cfi_offset 6, -40
	movq	%rsi, %rbp
	pushq	%rbx
	.cfi_def_cfa_offset 48
	.cfi_offset 3, -48
	movl	%ecx, %ebx
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	movsd	%xmm0, 40(%rsp)
	leaq	56(%rsp), %rdi
	movsd	%xmm1, 32(%rsp)
	movsd	%xmm2, 24(%rsp)
	movsd	%xmm3, 16(%rsp)
	movsd	%xmm4, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	movslq	%ecx, %rax
	leaq	0(,%rax,8), %r14
	movq	%r14, %rsi
	call	cudaMalloc@PLT
	leaq	64(%rsp), %rdi
	movq	%r14, %rsi
	call	cudaMalloc@PLT
	leaq	72(%rsp), %rdi
	movq	%r14, %rsi
	call	cudaMalloc@PLT
	movq	56(%rsp), %rdi
	movq	%r14, %rdx
	movq	%r12, %rsi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	movq	64(%rsp), %rdi
	movq	%r14, %rdx
	movq	%rbp, %rsi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	movq	72(%rsp), %rdi
	movq	%r14, %rdx
	movq	%r13, %rsi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	leal	127(%rbx), %eax
	movl	$128, %ecx
	xorl	%r9d, %r9d
	cltd
	xorl	%r8d, %r8d
	idivl	%ecx
	movl	$33554433, %edx
	movl	$1, %ecx
	salq	$7, %rdx
	movl	%eax, 80(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 84(%rsp)
	movq	80(%rsp), %rdi
	movl	88(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	movsd	8(%rsp), %xmm4
	movsd	16(%rsp), %xmm3
	testl	%eax, %eax
	movsd	24(%rsp), %xmm2
	movsd	32(%rsp), %xmm1
	movsd	40(%rsp), %xmm0
	jne	.L9
	movq	72(%rsp), %rdx
	movq	64(%rsp), %rsi
	movl	%ebx, %ecx
	movq	56(%rsp), %rdi
	call	_Z56__device_stub__Z26cuda_physical_model_kerneldddddPdS_S_idddddPdS_S_i
.L9:
	movq	56(%rsp), %rsi
	movl	$2, %ecx
	movq	%r14, %rdx
	movq	%r12, %rdi
	call	cudaMemcpy@PLT
	movq	64(%rsp), %rsi
	movq	%r14, %rdx
	movq	%rbp, %rdi
	movl	$2, %ecx
	call	cudaMemcpy@PLT
	movq	72(%rsp), %rsi
	movq	%r14, %rdx
	movq	%r13, %rdi
	movl	$2, %ecx
	call	cudaMemcpy@PLT
	movq	56(%rsp), %rdi
	call	cudaFree@PLT
	movq	64(%rsp), %rdi
	call	cudaFree@PLT
	movq	72(%rsp), %rdi
	call	cudaFree@PLT
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L10
	call	__stack_chk_fail@PLT
.L10:
	addq	$112, %rsp
	.cfi_def_cfa_offset 48
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%rbp
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r13
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2021:
	.size	_Z26gpu_physical_model_computedddddPdS_S_i, .-_Z26gpu_physical_model_computedddddPdS_S_i
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z26cuda_physical_model_kerneldddddPdS_S_i"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2049:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z26cuda_physical_model_kerneldddddPdS_S_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2049:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

/*
 * gpu_physical_model.c
 *
 *  Created on: Jan 24, 2016
 *      Author: sled
 */

//
// Physical model GPU implementation
//

#include <hip/hip_runtime.h>
#include <unistd.h>
#include <stdlib.h>
#include <math.h>

#define THREADS_PER_BLOCK		128

// CUDA kernel declaration
__global__ void cuda_physical_model_kernel(double g, double K, double vx_0, double vy_0, double vz_0, double *x, double *y, double *z, int N);

// C/C++ Wrapper
void gpu_physical_model_compute(double g, double K, double vx_0, double vy_0, double vz_0, double *x, double *y, double *z, int N)
{
	// Device memory
	double *dev_x;
	double *dev_y;
	double *dev_z;

	size_t size = N * sizeof(double);

	// Allocated device memory
	hipMalloc((void **)&dev_x, size);
	hipMalloc((void **)&dev_y, size);
	hipMalloc((void **)&dev_z, size);

	// Upload data to device memory
	hipMemcpy(dev_x, x, size, hipMemcpyHostToDevice);
	hipMemcpy(dev_y, y, size, hipMemcpyHostToDevice);
	hipMemcpy(dev_z, z, size, hipMemcpyHostToDevice);

	cuda_physical_model_kernel<<<((N + THREADS_PER_BLOCK - 1) / THREADS_PER_BLOCK), THREADS_PER_BLOCK>>>(g, K, vx_0, vy_0, vz_0, dev_x, dev_y, dev_z, N);

	hipMemcpy(x, dev_x, size, hipMemcpyDeviceToHost);
	hipMemcpy(y, dev_y, size, hipMemcpyDeviceToHost);
	hipMemcpy(z, dev_z, size, hipMemcpyDeviceToHost);

	hipFree(dev_x);
	hipFree(dev_y);
	hipFree(dev_z);
}

// GPU memory buffers are filled with computed physical states 3D components
__global__ void cuda_physical_model_kernel(double g, double K, double vx_0, double vy_0, double vz_0, double *x, double *y, double *z, int N)
{
	int idx = threadIdx.x + (blockDim.x *blockIdx.x);

	if (idx == 0)
		return;

	if (idx < N) {
		x[idx] = x[0] + (vx_0 / K) * (1.0 - exp(-K * idx)/K);
		y[idx] = y[0] + ((g + K * vy_0) / (K * K)) * (1.0 - exp(-K * idx)) - (g * idx) / K;
		z[idx] = z[0] + (vz_0 / K) * (1.0 - exp(-K * idx)/K);
	}
}




	.text
	.file	"gpu_physical_model.hip"
	.globl	_Z26gpu_physical_model_computedddddPdS_S_i # -- Begin function _Z26gpu_physical_model_computedddddPdS_S_i
	.type	_Z26gpu_physical_model_computedddddPdS_S_i,@function
_Z26gpu_physical_model_computedddddPdS_S_i: # @_Z26gpu_physical_model_computedddddPdS_S_i
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$88, %rsp
	.cfi_def_cfa_offset 144
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%rdx, 80(%rsp)                  # 8-byte Spill
	movq	%rsi, %r12
	movq	%rdi, %rbp
	movsd	%xmm4, 72(%rsp)                 # 8-byte Spill
	movsd	%xmm3, 64(%rsp)                 # 8-byte Spill
	movsd	%xmm2, 56(%rsp)                 # 8-byte Spill
	movsd	%xmm1, 48(%rsp)                 # 8-byte Spill
	movsd	%xmm0, 40(%rsp)                 # 8-byte Spill
	movl	%ecx, 36(%rsp)                  # 4-byte Spill
	movslq	%ecx, %r13
	leaq	(,%r13,8), %r14
	leaq	24(%rsp), %r15
	movq	%r15, %rdi
	movq	%r14, %rsi
	callq	hipMalloc
	leaq	16(%rsp), %rbx
	movq	%rbx, %rdi
	movq	%r14, %rsi
	callq	hipMalloc
	leaq	8(%rsp), %rdi
	movq	%r14, %rsi
	callq	hipMalloc
	movq	(%r15), %rdi
	movq	%rbp, %rsi
	movq	%r14, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%rbx), %rdi
	movq	80(%rsp), %rbx                  # 8-byte Reload
	movq	%r12, %rsi
	movq	%r14, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	8(%rsp), %rax
	movq	(%rax), %rdi
	movq	%rbx, %rsi
	movq	%r14, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	leal	127(%r13), %eax
	addl	$254, %r13d
	testl	%eax, %eax
	cmovnsl	%eax, %r13d
	sarl	$7, %r13d
	btsq	$32, %r13
	movabsq	$4294967296, %rdx               # imm = 0x100000000
	orq	$128, %rdx
	movq	%r13, %rdi
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB0_2
# %bb.1:
	movq	24(%rsp), %rdi
	movq	16(%rsp), %rsi
	movq	8(%rsp), %rdx
	movsd	40(%rsp), %xmm0                 # 8-byte Reload
                                        # xmm0 = mem[0],zero
	movsd	48(%rsp), %xmm1                 # 8-byte Reload
                                        # xmm1 = mem[0],zero
	movsd	56(%rsp), %xmm2                 # 8-byte Reload
                                        # xmm2 = mem[0],zero
	movsd	64(%rsp), %xmm3                 # 8-byte Reload
                                        # xmm3 = mem[0],zero
	movsd	72(%rsp), %xmm4                 # 8-byte Reload
                                        # xmm4 = mem[0],zero
	movl	36(%rsp), %ecx                  # 4-byte Reload
	callq	_Z41__device_stub__cuda_physical_model_kerneldddddPdS_S_i
.LBB0_2:
	movq	24(%rsp), %rsi
	movq	%rbp, %rdi
	movq	%r14, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	movq	16(%rsp), %rsi
	movq	%r12, %rdi
	movq	%r14, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	movq	8(%rsp), %rsi
	movq	%rbx, %rdi
	movq	%r14, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	movq	24(%rsp), %rdi
	callq	hipFree
	movq	16(%rsp), %rdi
	callq	hipFree
	movq	8(%rsp), %rdi
	callq	hipFree
	addq	$88, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z26gpu_physical_model_computedddddPdS_S_i, .Lfunc_end0-_Z26gpu_physical_model_computedddddPdS_S_i
	.cfi_endproc
                                        # -- End function
	.globl	_Z41__device_stub__cuda_physical_model_kerneldddddPdS_S_i # -- Begin function _Z41__device_stub__cuda_physical_model_kerneldddddPdS_S_i
	.type	_Z41__device_stub__cuda_physical_model_kerneldddddPdS_S_i,@function
_Z41__device_stub__cuda_physical_model_kerneldddddPdS_S_i: # @_Z41__device_stub__cuda_physical_model_kerneldddddPdS_S_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$208, %rsp
	.cfi_def_cfa_offset 256
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	88(%rsp), %rax
	movsd	%xmm0, (%rax)
	leaq	80(%rsp), %r8
	movsd	%xmm1, (%r8)
	leaq	72(%rsp), %r9
	movsd	%xmm2, (%r9)
	leaq	64(%rsp), %r10
	movsd	%xmm3, (%r10)
	leaq	56(%rsp), %r11
	movsd	%xmm4, (%r11)
	leaq	48(%rsp), %r14
	movq	%rdi, (%r14)
	leaq	40(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	32(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	12(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	128(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%r8, 8(%rbx)
	movq	%r9, 16(%rbx)
	movq	%r10, 24(%rbx)
	movq	%r11, 32(%rbx)
	movq	%r14, 40(%rbx)
	movq	%rdi, 48(%rbx)
	movq	%rsi, 56(%rbx)
	movq	%rdx, 64(%rbx)
	leaq	112(%rsp), %r14
	leaq	96(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z26cuda_physical_model_kerneldddddPdS_S_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$224, %rsp
	.cfi_adjust_cfa_offset -224
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z41__device_stub__cuda_physical_model_kerneldddddPdS_S_i, .Lfunc_end1-_Z41__device_stub__cuda_physical_model_kerneldddddPdS_S_i
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z26cuda_physical_model_kerneldddddPdS_S_i, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z26cuda_physical_model_kerneldddddPdS_S_i,@object # @_Z26cuda_physical_model_kerneldddddPdS_S_i
	.section	.rodata,"a",@progbits
	.globl	_Z26cuda_physical_model_kerneldddddPdS_S_i
	.p2align	3, 0x0
_Z26cuda_physical_model_kerneldddddPdS_S_i:
	.quad	_Z41__device_stub__cuda_physical_model_kerneldddddPdS_S_i
	.size	_Z26cuda_physical_model_kerneldddddPdS_S_i, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z26cuda_physical_model_kerneldddddPdS_S_i"
	.size	.L__unnamed_1, 43

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z41__device_stub__cuda_physical_model_kerneldddddPdS_S_i
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z26cuda_physical_model_kerneldddddPdS_S_i
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z26cuda_physical_model_kerneldddddPdS_S_i ; -- Begin function _Z26cuda_physical_model_kerneldddddPdS_S_i
	.globl	_Z26cuda_physical_model_kerneldddddPdS_S_i
	.p2align	8
	.type	_Z26cuda_physical_model_kerneldddddPdS_S_i,@function
_Z26cuda_physical_model_kerneldddddPdS_S_i: ; @_Z26cuda_physical_model_kerneldddddPdS_S_i
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x54
	s_load_b32 s3, s[0:1], 0x40
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	v_cmp_ne_u32_e32 vcc_lo, 0, v1
	v_cmp_gt_i32_e64 s2, s3, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, vcc_lo, s2
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_2
; %bb.1:
	v_cvt_f64_i32_e32 v[2:3], v1
	s_load_b512 s[4:19], s[0:1], 0x0
	s_mov_b32 s0, 0x652b82fe
	s_mov_b32 s1, 0x3ff71547
	s_mov_b32 s2, 0x6a5dcb37
	s_mov_b32 s3, 0x3e5ade15
	v_mov_b32_e32 v30, 0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[4:5], -s[6:7], v[2:3]
	v_mul_f64 v[6:7], v[4:5], s[0:1]
	s_mov_b32 s0, 0xfefa39ef
	s_mov_b32 s1, 0xbfe62e42
	v_cmp_nlt_f64_e32 vcc_lo, 0x40900000, v[4:5]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f64_e32 v[6:7], v[6:7]
	v_fma_f64 v[8:9], v[6:7], s[0:1], v[4:5]
	s_mov_b32 s0, 0x3b39803f
	s_mov_b32 s1, 0xbc7abc9e
	v_cvt_i32_f64_e32 v0, v[6:7]
	s_delay_alu instid0(VALU_DEP_2)
	v_fma_f64 v[8:9], v[6:7], s[0:1], v[8:9]
	s_mov_b32 s0, 0xfca7ab0c
	s_mov_b32 s1, 0x3e928af3
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[10:11], v[8:9], s[2:3], s[0:1]
	s_mov_b32 s0, 0x623fde64
	s_mov_b32 s1, 0x3ec71dee
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[10:11], v[8:9], v[10:11], s[0:1]
	s_mov_b32 s0, 0x7c89e6b0
	s_mov_b32 s1, 0x3efa0199
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[10:11], v[8:9], v[10:11], s[0:1]
	s_mov_b32 s0, 0x14761f6e
	s_mov_b32 s1, 0x3f2a01a0
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[10:11], v[8:9], v[10:11], s[0:1]
	s_mov_b32 s0, 0x1852b7b0
	s_mov_b32 s1, 0x3f56c16c
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[10:11], v[8:9], v[10:11], s[0:1]
	s_mov_b32 s0, 0x11122322
	s_mov_b32 s1, 0x3f811111
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[10:11], v[8:9], v[10:11], s[0:1]
	s_mov_b32 s0, 0x555502a1
	s_mov_b32 s1, 0x3fa55555
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[10:11], v[8:9], v[10:11], s[0:1]
	s_mov_b32 s0, 0x55555511
	s_mov_b32 s1, 0x3fc55555
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[10:11], v[8:9], v[10:11], s[0:1]
	s_mov_b32 s0, 11
	s_mov_b32 s1, 0x3fe00000
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[10:11], v[8:9], v[10:11], s[0:1]
	v_cmp_ngt_f64_e64 s0, 0xc090cc00, v[4:5]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[10:11], v[8:9], v[10:11], 1.0
	v_fma_f64 v[6:7], v[8:9], v[10:11], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ldexp_f64 v[6:7], v[6:7], v0
	v_cndmask_b32_e32 v0, 0x7ff00000, v7, vcc_lo
	s_and_b32 vcc_lo, s0, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v4, 0, v6, vcc_lo
	v_div_scale_f64 v[6:7], null, s[6:7], s[6:7], s[8:9]
	v_cndmask_b32_e64 v5, 0, v0, s0
	v_div_scale_f64 v[18:19], vcc_lo, s[8:9], s[6:7], s[8:9]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_div_scale_f64 v[8:9], null, s[6:7], s[6:7], v[4:5]
	v_rcp_f64_e32 v[10:11], v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_rcp_f64_e32 v[12:13], v[8:9]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[14:15], -v[6:7], v[10:11], 1.0
	v_fma_f64 v[16:17], -v[8:9], v[12:13], 1.0
	v_fma_f64 v[10:11], v[10:11], v[14:15], v[10:11]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[12:13], v[12:13], v[16:17], v[12:13]
	v_fma_f64 v[14:15], -v[6:7], v[10:11], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[16:17], -v[8:9], v[12:13], 1.0
	v_fma_f64 v[10:11], v[10:11], v[14:15], v[10:11]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[12:13], v[12:13], v[16:17], v[12:13]
	v_mul_f64 v[16:17], v[18:19], v[10:11]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[6:7], -v[6:7], v[16:17], v[18:19]
	v_div_fmas_f64 v[6:7], v[6:7], v[10:11], v[16:17]
	v_mov_b32_e32 v11, s5
	v_div_scale_f64 v[14:15], s0, v[4:5], s[6:7], v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_3)
	s_mov_b32 vcc_lo, s0
	v_mov_b32_e32 v10, s4
	v_mul_f64 v[16:17], v[2:3], s[4:5]
	s_load_b64 s[0:1], s[14:15], 0x0
	v_ashrrev_i32_e32 v2, 31, v1
	v_fma_f64 v[10:11], s[6:7], s[10:11], v[10:11]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 3, v[1:2]
	v_div_fixup_f64 v[6:7], v[6:7], s[6:7], s[8:9]
	v_mul_f64 v[20:21], v[14:15], v[12:13]
	v_fma_f64 v[8:9], -v[8:9], v[20:21], v[14:15]
	s_delay_alu instid0(VALU_DEP_1)
	v_div_fmas_f64 v[8:9], v[8:9], v[12:13], v[20:21]
	v_mul_f64 v[12:13], s[6:7], s[6:7]
	v_div_scale_f64 v[20:21], null, s[6:7], s[6:7], v[16:17]
	v_add_co_u32 v2, vcc_lo, s14, v0
	v_add_co_ci_u32_e32 v3, vcc_lo, s15, v1, vcc_lo
	v_div_fixup_f64 v[8:9], v[8:9], s[6:7], v[4:5]
	v_div_scale_f64 v[14:15], null, v[12:13], v[12:13], v[10:11]
	v_rcp_f64_e32 v[22:23], v[20:21]
	v_add_f64 v[4:5], -v[4:5], 1.0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[8:9], -v[8:9], 1.0
	v_rcp_f64_e32 v[18:19], v[14:15]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_fma_f64 v[6:7], v[6:7], v[8:9], s[0:1]
	v_div_scale_f64 v[28:29], s0, v[16:17], s[6:7], v[16:17]
	global_store_b64 v[2:3], v[6:7], off
	global_load_b64 v[2:3], v30, s[16:17]
	v_fma_f64 v[6:7], -v[14:15], v[18:19], 1.0
	v_fma_f64 v[6:7], v[18:19], v[6:7], v[18:19]
	v_fma_f64 v[18:19], -v[20:21], v[22:23], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[24:25], -v[14:15], v[6:7], 1.0
	v_fma_f64 v[18:19], v[22:23], v[18:19], v[22:23]
	v_div_scale_f64 v[22:23], vcc_lo, v[10:11], v[12:13], v[10:11]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[6:7], v[6:7], v[24:25], v[6:7]
	v_fma_f64 v[24:25], -v[20:21], v[18:19], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[26:27], v[22:23], v[6:7]
	v_fma_f64 v[18:19], v[18:19], v[24:25], v[18:19]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[14:15], -v[14:15], v[26:27], v[22:23]
	v_mul_f64 v[22:23], v[28:29], v[18:19]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fmas_f64 v[6:7], v[14:15], v[6:7], v[26:27]
	v_fma_f64 v[14:15], -v[20:21], v[22:23], v[28:29]
	s_mov_b32 vcc_lo, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fixup_f64 v[6:7], v[6:7], v[12:13], v[10:11]
	v_div_fmas_f64 v[10:11], v[14:15], v[18:19], v[22:23]
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[2:3], v[6:7], v[4:5], v[2:3]
	v_div_fixup_f64 v[4:5], v[10:11], s[6:7], v[16:17]
	v_div_scale_f64 v[6:7], null, s[6:7], s[6:7], s[12:13]
	v_add_co_u32 v10, vcc_lo, s16, v0
	v_add_co_ci_u32_e32 v11, vcc_lo, s17, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[2:3], v[2:3], -v[4:5]
	v_rcp_f64_e32 v[4:5], v[6:7]
	global_store_b64 v[10:11], v[2:3], off
	global_load_b64 v[2:3], v30, s[18:19]
	v_fma_f64 v[10:11], -v[6:7], v[4:5], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[4:5], v[4:5], v[10:11], v[4:5]
	v_fma_f64 v[10:11], -v[6:7], v[4:5], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f64 v[4:5], v[4:5], v[10:11], v[4:5]
	v_div_scale_f64 v[10:11], vcc_lo, s[12:13], s[6:7], s[12:13]
	v_mul_f64 v[12:13], v[10:11], v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[6:7], -v[6:7], v[12:13], v[10:11]
	v_div_fmas_f64 v[4:5], v[6:7], v[4:5], v[12:13]
	v_add_co_u32 v0, vcc_lo, s18, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s19, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_div_fixup_f64 v[4:5], v[4:5], s[6:7], s[12:13]
	s_waitcnt vmcnt(0)
	v_fma_f64 v[2:3], v[4:5], v[8:9], v[2:3]
	global_store_b64 v[0:1], v[2:3], off
.LBB0_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z26cuda_physical_model_kerneldddddPdS_S_i
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 328
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 31
		.amdhsa_next_free_sgpr 20
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z26cuda_physical_model_kerneldddddPdS_S_i, .Lfunc_end0-_Z26cuda_physical_model_kerneldddddPdS_S_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1260
; NumSgprs: 22
; NumVgprs: 31
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 3
; NumSGPRsForWavesPerEU: 22
; NumVGPRsForWavesPerEU: 31
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .offset:         0
        .size:           8
        .value_kind:     by_value
      - .offset:         8
        .size:           8
        .value_kind:     by_value
      - .offset:         16
        .size:           8
        .value_kind:     by_value
      - .offset:         24
        .size:           8
        .value_kind:     by_value
      - .offset:         32
        .size:           8
        .value_kind:     by_value
      - .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         48
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         56
        .size:           8
        .value_kind:     global_buffer
      - .offset:         64
        .size:           4
        .value_kind:     by_value
      - .offset:         72
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         76
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         80
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         84
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         86
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         88
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         90
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         92
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         94
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         112
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         120
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         128
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         136
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 328
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z26cuda_physical_model_kerneldddddPdS_S_i
    .private_segment_fixed_size: 0
    .sgpr_count:     22
    .sgpr_spill_count: 0
    .symbol:         _Z26cuda_physical_model_kerneldddddPdS_S_i.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     31
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
