#include <stdio.h>
#include <iostream>
#include <chrono>
#include <iomanip>

using namespace std;

__global__
void convert(char *input, char *output, int len, int step)
{
	int index = blockIdx.x * blockDim.x + threadIdx.x;
	//if (index < size) *(output + (2 - index % 3) * len + index / 3) = *(input+index);

    char * oR = output + index * step, *oG = oR + len, *oB = oG + len;
    const char *iPos = (const char *)input + index * step * 3;

    for(int i = 0; i < step; i += 1){
        *(oB++) = *(iPos++);
        *(oG++) = *(iPos++);
        *(oR++) = *(iPos++);
    }
}


extern "C" void rgbConvert(char* input, int size, unsigned char * pBuffer){
    int len = size / 3;
    char * cinput = (char *) pBuffer;
    char * coutput = (char *) pBuffer + size;
    int block = 128;
    int thread = 128;

    cudaMemcpy(pBuffer, input, size, cudaMemcpyHostToDevice );
    cudaMemset(pBuffer + len * 6, 0, len);

    cudaDeviceSynchronize();

    if(len/block/thread > 0){
        convert<<<len/block/thread, thread>>>(cinput, coutput, len, block);
        convert<<<len%(block*thread), 1>>>(cinput + len/block/thread*block*thread*3, coutput + len/block/thread*block*thread, len, 1);
    }else{
        convert<<<len%(block*thread), 1>>>(cinput , coutput , len, 1);
    }


    cudaDeviceSynchronize();

}


__global__
void convertBack(char *input, char *output, int len, int step)
{
	int index = blockIdx.x * blockDim.x + threadIdx.x;
	//if (index < size) *(output + (2 - index % 3) * len + index / 3) = *(input+index);

    char * iR = input + index * step , *iG = iR + len, *iB = iG + len;
    char *oPos = output + index * step * 3;

    for (int i = 0; i < step; i++){
        *(oPos++) = *(iB++);
        *(oPos++) = *(iG++);
        *(oPos++) = *(iR++);
    }
}


extern "C" void rgbConvertBack(int len, unsigned char * pBuffer){

    int block = 128;
    int thread = 128;

    char * cinput = (char *) pBuffer;
    char * coutput = (char *) pBuffer + len * 4;

    if(len/block/thread > 0){
        convertBack<<<len/block/thread, thread>>>(cinput, coutput, len, thread);
        convertBack<<<len%(block*thread), 1>>>(cinput + len/block/thread*block*thread, coutput + len/block/thread*block*thread*3, len, 1);
    }else{
        convertBack<<<len%(block*thread), 1>>>(cinput, coutput, len, 1);
    }
    cudaDeviceSynchronize();
}


__global__
void convert128(char *input, char *output, int len, int step)
{
	int index = blockIdx.x * blockDim.x + threadIdx.x;
	//if (index < size) *(output + (2 - index % 3) * len + index / 3) = *(input+index);

    char * oR = output + index * step, *oG = oR + len, *oB = oG + len;
    const char *iPos = (const char *)input + index * step * 3;

    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);
    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);
    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);
    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);

    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);
    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);
    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);
    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);

    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);
    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);
    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);
    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);

    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);
    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);
    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);
    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);

    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
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    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
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    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);
    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);

    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);
    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);
    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);
    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);

    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);
    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);
    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);
    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);

    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);
    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);
    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);
    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);

    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
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    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);
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    *(oG++) = *(iPos++);
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    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);

    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
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    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
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    *(oG++) = *(iPos++);
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    *(oB++) = *(iPos++);
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    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
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    *(oG++) = *(iPos++);
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        *(oB++) = *(iPos++);
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        *(oB++) = *(iPos++);
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        *(oB++) = *(iPos++);
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    *(oG++) = *(iPos++);
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    *(oG++) = *(iPos++);
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    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
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    *(oR++) = *(iPos++);

        *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
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    *(oG++) = *(iPos++);
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    *(oB++) = *(iPos++);
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    *(oR++) = *(iPos++);

    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);
    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
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    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
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    *(oR++) = *(iPos++);

    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);
    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);
    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);
    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);

    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);
    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);
    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);
    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);

        *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);
    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);
    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);
    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);

    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);
    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);
    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);
    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);

    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);
    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);
    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);
    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);

    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);
    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);
    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);
    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);
}

/*
int main(){

    int size = 1811520*3;
	char * input = (char*) malloc(size);
	memset(input, 2, size);

    char* output = rgbConvert(input, size);
    cudaFree(output);
	return EXIT_SUCCESS;

}
*/
	.file	"tmpxft_0026d1a2_00000000-6_rgbConverter.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4018:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE4018:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z30__device_stub__Z7convertPcS_iiPcS_ii
	.type	_Z30__device_stub__Z7convertPcS_iiPcS_ii, @function
_Z30__device_stub__Z7convertPcS_iiPcS_ii:
.LFB4040:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z7convertPcS_ii(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L2:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4040:
	.size	_Z30__device_stub__Z7convertPcS_iiPcS_ii, .-_Z30__device_stub__Z7convertPcS_iiPcS_ii
	.globl	_Z7convertPcS_ii
	.type	_Z7convertPcS_ii, @function
_Z7convertPcS_ii:
.LFB4041:
	.cfi_startproc
	endbr64
	jmp	_Z30__device_stub__Z7convertPcS_iiPcS_ii
	.cfi_endproc
.LFE4041:
	.size	_Z7convertPcS_ii, .-_Z7convertPcS_ii
	.globl	rgbConvert
	.type	rgbConvert, @function
rgbConvert:
.LFB4014:
	.cfi_startproc
	endbr64
	movl	%esi, %eax
	pushq	%r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	movl	$3, %ecx
	pushq	%r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	movq	%rdx, %r12
	cltd
	idivl	%ecx
	pushq	%rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	movslq	%esi, %rdx
	subq	$40, %rsp
	.cfi_def_cfa_offset 80
	movl	%esi, %ebp
	movl	$1, %ecx
	movq	%rdi, %rsi
	movq	%r12, %rdi
	leaq	(%r12,%rdx), %r13
	movl	%eax, %ebx
	call	cudaMemcpy@PLT
	imull	$6, %ebx, %edi
	xorl	%esi, %esi
	movslq	%ebx, %rdx
	movslq	%edi, %rdi
	addq	%r12, %rdi
	call	cudaMemset@PLT
	call	cudaDeviceSynchronize@PLT
	cmpl	$49151, %ebp
	jle	.L9
	movl	%ebx, %ebp
	movl	$33554433, %edx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	sarl	$14, %ebp
	salq	$7, %rdx
	movabsq	$4294967297, %rax
	movl	$1, %ecx
	movq	%rax, 12(%rsp)
	movl	16(%rsp), %esi
	movl	%ebp, 8(%rsp)
	movq	8(%rsp), %rdi
	movq	%rdx, 20(%rsp)
	movl	$1, 28(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L10
	movl	$128, %ecx
	movl	%ebx, %edx
	movq	%r13, %rsi
	movq	%r12, %rdi
	call	_Z30__device_stub__Z7convertPcS_iiPcS_ii
.L10:
	movl	%ebx, %eax
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$1, %ecx
	movabsq	$4294967297, %rdx
	andl	$16383, %eax
	movl	$1, 28(%rsp)
	movq	%rdx, 12(%rsp)
	movl	16(%rsp), %esi
	movl	%eax, 8(%rsp)
	movq	8(%rsp), %rdi
	movq	%rdx, 20(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L12
	imull	$49152, %ebp, %edi
	movl	%ebp, %esi
	movl	$1, %ecx
	movl	%ebx, %edx
	sall	$14, %esi
	movslq	%esi, %rsi
	movslq	%edi, %rdi
	addq	%r13, %rsi
	addq	%r12, %rdi
	jmp	.L15
.L9:
	movl	%ebx, %eax
	movl	$16384, %esi
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	cltd
	movl	$1, 28(%rsp)
	movabsq	$4294967297, %rcx
	idivl	%esi
	movq	%rcx, 12(%rsp)
	movl	16(%rsp), %esi
	movq	%rcx, 20(%rsp)
	movl	%edx, 8(%rsp)
	movq	8(%rsp), %rdi
	movq	%rcx, %rdx
	movl	$1, %ecx
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L12
	movl	$1, %ecx
	movl	%ebx, %edx
	movq	%r13, %rsi
	movq	%r12, %rdi
.L15:
	call	_Z30__device_stub__Z7convertPcS_iiPcS_ii
.L12:
	addq	$40, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	cudaDeviceSynchronize@PLT
	.cfi_endproc
.LFE4014:
	.size	rgbConvert, .-rgbConvert
	.globl	_Z35__device_stub__Z11convertBackPcS_iiPcS_ii
	.type	_Z35__device_stub__Z11convertBackPcS_iiPcS_ii, @function
_Z35__device_stub__Z11convertBackPcS_iiPcS_ii:
.LFB4042:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L16
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z11convertBackPcS_ii(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L16:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L18
	call	__stack_chk_fail@PLT
.L18:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4042:
	.size	_Z35__device_stub__Z11convertBackPcS_iiPcS_ii, .-_Z35__device_stub__Z11convertBackPcS_iiPcS_ii
	.globl	_Z11convertBackPcS_ii
	.type	_Z11convertBackPcS_ii, @function
_Z11convertBackPcS_ii:
.LFB4043:
	.cfi_startproc
	endbr64
	jmp	_Z35__device_stub__Z11convertBackPcS_iiPcS_ii
	.cfi_endproc
.LFE4043:
	.size	_Z11convertBackPcS_ii, .-_Z11convertBackPcS_ii
	.globl	rgbConvertBack
	.type	rgbConvertBack, @function
rgbConvertBack:
.LFB4015:
	.cfi_startproc
	endbr64
	pushq	%r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	movq	%rsi, %r13
	pushq	%r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	leal	0(,%rdi,4), %r12d
	pushq	%rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	movslq	%r12d, %r12
	pushq	%rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	addq	%rsi, %r12
	movl	%edi, %ebx
	subq	$40, %rsp
	.cfi_def_cfa_offset 80
	cmpl	$16383, %edi
	jle	.L22
	movl	%edi, %ebp
	movl	$33554433, %edx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	sarl	$14, %ebp
	salq	$7, %rdx
	movabsq	$4294967297, %rax
	movl	$1, %ecx
	movq	%rax, 12(%rsp)
	movl	16(%rsp), %esi
	movl	%ebp, 8(%rsp)
	movq	8(%rsp), %rdi
	movq	%rdx, 20(%rsp)
	movl	$1, 28(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L23
	movl	$128, %ecx
	movl	%ebx, %edx
	movq	%r12, %rsi
	movq	%r13, %rdi
	call	_Z35__device_stub__Z11convertBackPcS_iiPcS_ii
.L23:
	movl	%ebx, %eax
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$1, %ecx
	movabsq	$4294967297, %rdx
	andl	$16383, %eax
	movl	$1, 28(%rsp)
	movq	%rdx, 12(%rsp)
	movl	16(%rsp), %esi
	movl	%eax, 8(%rsp)
	movq	8(%rsp), %rdi
	movq	%rdx, 20(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L25
	imull	$49152, %ebp, %esi
	sall	$14, %ebp
	movl	$1, %ecx
	movl	%ebx, %edx
	movslq	%ebp, %rdi
	addq	%r13, %rdi
	movslq	%esi, %rsi
	addq	%r12, %rsi
	jmp	.L28
.L22:
	movl	%edi, %eax
	movl	$16384, %esi
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	cltd
	movl	$1, 28(%rsp)
	movabsq	$4294967297, %rcx
	idivl	%esi
	movq	%rcx, 12(%rsp)
	movl	16(%rsp), %esi
	movq	%rcx, 20(%rsp)
	movl	%edx, 8(%rsp)
	movq	8(%rsp), %rdi
	movq	%rcx, %rdx
	movl	$1, %ecx
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L25
	movl	$1, %ecx
	movl	%ebx, %edx
	movq	%r12, %rsi
	movq	%r13, %rdi
.L28:
	call	_Z35__device_stub__Z11convertBackPcS_iiPcS_ii
.L25:
	addq	$40, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	cudaDeviceSynchronize@PLT
	.cfi_endproc
.LFE4015:
	.size	rgbConvertBack, .-rgbConvertBack
	.globl	_Z34__device_stub__Z10convert128PcS_iiPcS_ii
	.type	_Z34__device_stub__Z10convert128PcS_iiPcS_ii, @function
_Z34__device_stub__Z10convert128PcS_iiPcS_ii:
.LFB4044:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L29
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z10convert128PcS_ii(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L29:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L31
	call	__stack_chk_fail@PLT
.L31:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4044:
	.size	_Z34__device_stub__Z10convert128PcS_iiPcS_ii, .-_Z34__device_stub__Z10convert128PcS_iiPcS_ii
	.globl	_Z10convert128PcS_ii
	.type	_Z10convert128PcS_ii, @function
_Z10convert128PcS_ii:
.LFB4045:
	.cfi_startproc
	endbr64
	jmp	_Z34__device_stub__Z10convert128PcS_iiPcS_ii
	.cfi_endproc
.LFE4045:
	.size	_Z10convert128PcS_ii, .-_Z10convert128PcS_ii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z10convert128PcS_ii"
.LC1:
	.string	"_Z11convertBackPcS_ii"
.LC2:
	.string	"_Z7convertPcS_ii"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4047:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z10convert128PcS_ii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC1(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z11convertBackPcS_ii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC2(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z7convertPcS_ii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE4047:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include <stdio.h>
#include <iostream>
#include <chrono>
#include <iomanip>

using namespace std;

__global__
void convert(char *input, char *output, int len, int step)
{
	int index = blockIdx.x * blockDim.x + threadIdx.x;
	//if (index < size) *(output + (2 - index % 3) * len + index / 3) = *(input+index);

    char * oR = output + index * step, *oG = oR + len, *oB = oG + len;
    const char *iPos = (const char *)input + index * step * 3;

    for(int i = 0; i < step; i += 1){
        *(oB++) = *(iPos++);
        *(oG++) = *(iPos++);
        *(oR++) = *(iPos++);
    }
}


extern "C" void rgbConvert(char* input, int size, unsigned char * pBuffer){
    int len = size / 3;
    char * cinput = (char *) pBuffer;
    char * coutput = (char *) pBuffer + size;
    int block = 128;
    int thread = 128;

    hipMemcpy(pBuffer, input, size, hipMemcpyHostToDevice );
    hipMemset(pBuffer + len * 6, 0, len);

    hipDeviceSynchronize();

    if(len/block/thread > 0){
        convert<<<len/block/thread, thread>>>(cinput, coutput, len, block);
        convert<<<len%(block*thread), 1>>>(cinput + len/block/thread*block*thread*3, coutput + len/block/thread*block*thread, len, 1);
    }else{
        convert<<<len%(block*thread), 1>>>(cinput , coutput , len, 1);
    }


    hipDeviceSynchronize();

}


__global__
void convertBack(char *input, char *output, int len, int step)
{
	int index = blockIdx.x * blockDim.x + threadIdx.x;
	//if (index < size) *(output + (2 - index % 3) * len + index / 3) = *(input+index);

    char * iR = input + index * step , *iG = iR + len, *iB = iG + len;
    char *oPos = output + index * step * 3;

    for (int i = 0; i < step; i++){
        *(oPos++) = *(iB++);
        *(oPos++) = *(iG++);
        *(oPos++) = *(iR++);
    }
}


extern "C" void rgbConvertBack(int len, unsigned char * pBuffer){

    int block = 128;
    int thread = 128;

    char * cinput = (char *) pBuffer;
    char * coutput = (char *) pBuffer + len * 4;

    if(len/block/thread > 0){
        convertBack<<<len/block/thread, thread>>>(cinput, coutput, len, thread);
        convertBack<<<len%(block*thread), 1>>>(cinput + len/block/thread*block*thread, coutput + len/block/thread*block*thread*3, len, 1);
    }else{
        convertBack<<<len%(block*thread), 1>>>(cinput, coutput, len, 1);
    }
    hipDeviceSynchronize();
}


__global__
void convert128(char *input, char *output, int len, int step)
{
	int index = blockIdx.x * blockDim.x + threadIdx.x;
	//if (index < size) *(output + (2 - index % 3) * len + index / 3) = *(input+index);

    char * oR = output + index * step, *oG = oR + len, *oB = oG + len;
    const char *iPos = (const char *)input + index * step * 3;

    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);
    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);
    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);
    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);

    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);
    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);
    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);
    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);

    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);
    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);
    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);
    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);

    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);
    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);
    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);
    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);

    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);
    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);
    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);
    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);

    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);
    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);
    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);
    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);

    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);
    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);
    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);
    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);

    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);
    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);
    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);
    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);

    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);
    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);
    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);
    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);

    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);
    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);
    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);
    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);

    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);
    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);
    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);
    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);

    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);
    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);
    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);
    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);

        *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);
    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);
    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);
    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);

    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);
    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);
    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);
    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);

    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);
    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);
    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);
    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);

    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);
    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);
    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);
    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);

        *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);
    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);
    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);
    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);

    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);
    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);
    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);
    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);

    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);
    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);
    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);
    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);

    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);
    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);
    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);
    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);

        *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);
    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);
    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);
    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);

    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);
    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);
    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);
    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);

    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);
    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);
    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);
    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);

    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);
    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);
    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);
    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);

        *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);
    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);
    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);
    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);

    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);
    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);
    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);
    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);

    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);
    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);
    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);
    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);

    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);
    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);
    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);
    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);

        *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);
    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);
    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);
    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);

    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);
    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);
    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);
    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);

    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);
    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);
    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);
    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);

    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);
    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);
    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);
    *(oB++) = *(iPos++);
    *(oG++) = *(iPos++);
    *(oR++) = *(iPos++);
}

/*
int main(){

    int size = 1811520*3;
	char * input = (char*) malloc(size);
	memset(input, 2, size);

    char* output = rgbConvert(input, size);
    cudaFree(output);
	return EXIT_SUCCESS;

}
*/
	.text
	.file	"rgbConverter.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z22__device_stub__convertPcS_ii # -- Begin function _Z22__device_stub__convertPcS_ii
	.type	_Z22__device_stub__convertPcS_ii,@function
_Z22__device_stub__convertPcS_ii:       # @_Z22__device_stub__convertPcS_ii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7convertPcS_ii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z22__device_stub__convertPcS_ii, .Lfunc_end0-_Z22__device_stub__convertPcS_ii
	.cfi_endproc
                                        # -- End function
	.globl	rgbConvert                      # -- Begin function rgbConvert
	.type	rgbConvert,@function
rgbConvert:                             # @rgbConvert
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movq	%rdx, %rbx
	movq	%rdi, %rax
	movabsq	$4294967296, %r12               # imm = 0x100000000
	movslq	%esi, %r13
	imulq	$1431655766, %r13, %r14         # imm = 0x55555556
	movq	%r14, %rcx
	shrq	$63, %rcx
	shrq	$32, %r14
	addl	%ecx, %r14d
	leaq	(%rdx,%r13), %r15
	movq	%rdx, %rdi
	movq	%rax, %rsi
	movq	%r13, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	leal	(%r14,%r14), %eax
	leal	(%rax,%rax,2), %eax
	movslq	%eax, %rdi
	addq	%rbx, %rdi
	movslq	%r14d, %rdx
	xorl	%esi, %esi
	callq	hipMemset
	callq	hipDeviceSynchronize
	cmpl	$49152, %r13d                   # imm = 0xC000
	jl	.LBB1_5
# %bb.1:
	imulq	$715827883, %r13, %r13          # imm = 0x2AAAAAAB
	movq	%r13, %rax
	shrq	$63, %rax
	sarq	$45, %r13
	addl	%eax, %r13d
	movl	%r13d, %edi
	orq	%r12, %rdi
	leaq	128(%r12), %rdx
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_3
# %bb.2:
	movq	%rbx, %rdi
	movq	%r15, %rsi
	movl	%r14d, %edx
	movl	$128, %ecx
	callq	_Z22__device_stub__convertPcS_ii
.LBB1_3:
	movl	%r14d, %edi
	andl	$16383, %edi                    # imm = 0x3FFF
	orq	%r12, %rdi
	incq	%r12
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_7
# %bb.4:
	shll	$14, %r13d
	leal	(%r13,%r13,2), %eax
	addq	%rax, %rbx
	addq	%r13, %r15
	jmp	.LBB1_6
.LBB1_5:
	leal	16383(%r14), %eax
	testl	%r14d, %r14d
	cmovnsl	%r14d, %eax
	andl	$-16384, %eax                   # imm = 0xC000
	movl	%r14d, %edi
	subl	%eax, %edi
	orq	%r12, %rdi
	incq	%r12
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_7
.LBB1_6:
	movq	%rbx, %rdi
	movq	%r15, %rsi
	movl	%r14d, %edx
	movl	$1, %ecx
	callq	_Z22__device_stub__convertPcS_ii
.LBB1_7:
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	hipDeviceSynchronize            # TAILCALL
.Lfunc_end1:
	.size	rgbConvert, .Lfunc_end1-rgbConvert
	.cfi_endproc
                                        # -- End function
	.globl	_Z26__device_stub__convertBackPcS_ii # -- Begin function _Z26__device_stub__convertBackPcS_ii
	.type	_Z26__device_stub__convertBackPcS_ii,@function
_Z26__device_stub__convertBackPcS_ii:   # @_Z26__device_stub__convertBackPcS_ii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z11convertBackPcS_ii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z26__device_stub__convertBackPcS_ii, .Lfunc_end2-_Z26__device_stub__convertBackPcS_ii
	.cfi_endproc
                                        # -- End function
	.globl	rgbConvertBack                  # -- Begin function rgbConvertBack
	.type	rgbConvertBack,@function
rgbConvertBack:                         # @rgbConvertBack
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movq	%rsi, %r14
	movl	%edi, %ebx
	movabsq	$4294967296, %r12               # imm = 0x100000000
	leal	(,%rbx,4), %eax
	movslq	%eax, %r15
	addq	%rsi, %r15
	leal	16383(%rbx), %r13d
	testl	%edi, %edi
	cmovnsl	%edi, %r13d
	cmpl	$16384, %edi                    # imm = 0x4000
	jl	.LBB3_5
# %bb.1:
	sarl	$14, %r13d
	movl	%r13d, %edi
	orq	%r12, %rdi
	leaq	128(%r12), %rdx
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB3_3
# %bb.2:
	movq	%r14, %rdi
	movq	%r15, %rsi
	movl	%ebx, %edx
	movl	$128, %ecx
	callq	_Z26__device_stub__convertBackPcS_ii
.LBB3_3:
	movl	%ebx, %edi
	andl	$16383, %edi                    # imm = 0x3FFF
	orq	%r12, %rdi
	incq	%r12
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB3_7
# %bb.4:
	shll	$14, %r13d
	addq	%r13, %r14
	leal	(%r13,%r13,2), %eax
	addq	%rax, %r15
	jmp	.LBB3_6
.LBB3_5:
	andl	$-16384, %r13d                  # imm = 0xC000
	movl	%ebx, %eax
	subl	%r13d, %eax
	movl	%eax, %edi
	orq	%r12, %rdi
	incq	%r12
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB3_7
.LBB3_6:
	movq	%r14, %rdi
	movq	%r15, %rsi
	movl	%ebx, %edx
	movl	$1, %ecx
	callq	_Z26__device_stub__convertBackPcS_ii
.LBB3_7:
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	hipDeviceSynchronize            # TAILCALL
.Lfunc_end3:
	.size	rgbConvertBack, .Lfunc_end3-rgbConvertBack
	.cfi_endproc
                                        # -- End function
	.globl	_Z25__device_stub__convert128PcS_ii # -- Begin function _Z25__device_stub__convert128PcS_ii
	.type	_Z25__device_stub__convert128PcS_ii,@function
_Z25__device_stub__convert128PcS_ii:    # @_Z25__device_stub__convert128PcS_ii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z10convert128PcS_ii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end4:
	.size	_Z25__device_stub__convert128PcS_ii, .Lfunc_end4-_Z25__device_stub__convert128PcS_ii
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB5_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB5_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z7convertPcS_ii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z11convertBackPcS_ii, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z10convert128PcS_ii, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end5:
	.size	__hip_module_ctor, .Lfunc_end5-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB6_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB6_2:
	retq
.Lfunc_end6:
	.size	__hip_module_dtor, .Lfunc_end6-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z7convertPcS_ii,@object        # @_Z7convertPcS_ii
	.section	.rodata,"a",@progbits
	.globl	_Z7convertPcS_ii
	.p2align	3, 0x0
_Z7convertPcS_ii:
	.quad	_Z22__device_stub__convertPcS_ii
	.size	_Z7convertPcS_ii, 8

	.type	_Z11convertBackPcS_ii,@object   # @_Z11convertBackPcS_ii
	.globl	_Z11convertBackPcS_ii
	.p2align	3, 0x0
_Z11convertBackPcS_ii:
	.quad	_Z26__device_stub__convertBackPcS_ii
	.size	_Z11convertBackPcS_ii, 8

	.type	_Z10convert128PcS_ii,@object    # @_Z10convert128PcS_ii
	.globl	_Z10convert128PcS_ii
	.p2align	3, 0x0
_Z10convert128PcS_ii:
	.quad	_Z25__device_stub__convert128PcS_ii
	.size	_Z10convert128PcS_ii, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z7convertPcS_ii"
	.size	.L__unnamed_1, 17

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z11convertBackPcS_ii"
	.size	.L__unnamed_2, 22

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z10convert128PcS_ii"
	.size	.L__unnamed_3, 21

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z22__device_stub__convertPcS_ii
	.addrsig_sym _Z26__device_stub__convertBackPcS_ii
	.addrsig_sym _Z25__device_stub__convert128PcS_ii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z7convertPcS_ii
	.addrsig_sym _Z11convertBackPcS_ii
	.addrsig_sym _Z10convert128PcS_ii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z7convertPcS_ii        ; -- Begin function _Z7convertPcS_ii
	.globl	_Z7convertPcS_ii
	.p2align	8
	.type	_Z7convertPcS_ii,@function
_Z7convertPcS_ii:                       ; @_Z7convertPcS_ii
; %bb.0:
	s_load_b64 s[2:3], s[0:1], 0x10
	s_waitcnt lgkmcnt(0)
	s_cmp_lt_i32 s3, 1
	s_cbranch_scc1 .LBB0_3
; %bb.1:                                ; %.lr.ph.preheader
	s_load_b32 s4, s[0:1], 0x24
	s_waitcnt lgkmcnt(0)
	s_and_b32 s4, s4, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
	s_load_b128 s[4:7], s[0:1], 0x0
	s_ashr_i32 s1, s2, 31
	s_mov_b32 s0, s2
	v_mul_lo_u32 v0, v1, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshl_add_u32 v1, v0, 1, v0
	v_ashrrev_i32_e32 v3, 31, v0
	v_ashrrev_i32_e32 v4, 31, v1
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v2, vcc_lo, s6, v0
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
	v_add_co_u32 v0, vcc_lo, s4, v1
	v_add_co_ci_u32_e32 v1, vcc_lo, s5, v4, vcc_lo
	s_lshl_b64 s[4:5], s[0:1], 1
.LBB0_2:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	global_load_u8 v6, v[0:1], off
	v_add_co_u32 v4, vcc_lo, v2, s4
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
	s_add_i32 s3, s3, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s3, 0
	s_waitcnt vmcnt(0)
	global_store_b8 v[4:5], v6, off
	global_load_u8 v6, v[0:1], off offset:1
	v_add_co_u32 v4, vcc_lo, v2, s0
	v_add_co_ci_u32_e32 v5, vcc_lo, s1, v3, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b8 v[4:5], v6, off
	global_load_u8 v6, v[0:1], off offset:2
	v_add_co_u32 v4, vcc_lo, v2, 1
	v_add_co_ci_u32_e32 v5, vcc_lo, 0, v3, vcc_lo
	v_add_co_u32 v0, vcc_lo, v0, 3
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b8 v[2:3], v6, off
	v_dual_mov_b32 v2, v4 :: v_dual_mov_b32 v3, v5
	s_cbranch_scc0 .LBB0_2
.LBB0_3:                                ; %._crit_edge
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7convertPcS_ii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 7
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z7convertPcS_ii, .Lfunc_end0-_Z7convertPcS_ii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 276
; NumSgprs: 18
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z11convertBackPcS_ii   ; -- Begin function _Z11convertBackPcS_ii
	.globl	_Z11convertBackPcS_ii
	.p2align	8
	.type	_Z11convertBackPcS_ii,@function
_Z11convertBackPcS_ii:                  ; @_Z11convertBackPcS_ii
; %bb.0:
	s_load_b64 s[2:3], s[0:1], 0x10
	s_waitcnt lgkmcnt(0)
	s_cmp_lt_i32 s3, 1
	s_cbranch_scc1 .LBB1_3
; %bb.1:                                ; %.lr.ph.preheader
	s_load_b32 s4, s[0:1], 0x24
	s_waitcnt lgkmcnt(0)
	s_and_b32 s4, s4, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
	s_load_b128 s[4:7], s[0:1], 0x0
	s_ashr_i32 s1, s2, 31
	s_mov_b32 s0, s2
	v_mul_lo_u32 v0, v1, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshl_add_u32 v1, v0, 1, v0
	v_ashrrev_i32_e32 v3, 31, v0
	v_ashrrev_i32_e32 v4, 31, v1
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v2, vcc_lo, s4, v0
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
	v_add_co_u32 v0, vcc_lo, s6, v1
	v_add_co_ci_u32_e32 v1, vcc_lo, s7, v4, vcc_lo
	s_lshl_b64 s[4:5], s[0:1], 1
.LBB1_2:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_add_co_u32 v4, vcc_lo, v2, s4
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
	s_add_i32 s3, s3, -1
	s_cmp_eq_u32 s3, 0
	global_load_u8 v6, v[4:5], off
	v_add_co_u32 v4, vcc_lo, v2, s0
	v_add_co_ci_u32_e32 v5, vcc_lo, s1, v3, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b8 v[0:1], v6, off
	global_load_u8 v4, v[4:5], off
	s_waitcnt vmcnt(0)
	global_store_b8 v[0:1], v4, off offset:1
	global_load_u8 v6, v[2:3], off
	v_add_co_u32 v2, vcc_lo, v2, 1
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
	v_add_co_u32 v4, vcc_lo, v0, 3
	v_add_co_ci_u32_e32 v5, vcc_lo, 0, v1, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b8 v[0:1], v6, off offset:2
	v_dual_mov_b32 v0, v4 :: v_dual_mov_b32 v1, v5
	s_cbranch_scc0 .LBB1_2
.LBB1_3:                                ; %._crit_edge
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z11convertBackPcS_ii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 7
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z11convertBackPcS_ii, .Lfunc_end1-_Z11convertBackPcS_ii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 276
; NumSgprs: 18
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z10convert128PcS_ii    ; -- Begin function _Z10convert128PcS_ii
	.globl	_Z10convert128PcS_ii
	.p2align	8
	.type	_Z10convert128PcS_ii,@function
_Z10convert128PcS_ii:                   ; @_Z10convert128PcS_ii
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x24
	s_load_b64 s[4:5], s[0:1], 0x10
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_load_b128 s[0:3], s[0:1], 0x0
	v_mul_lo_u32 v2, v1, s5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshl_add_u32 v0, v2, 1, v2
	v_ashrrev_i32_e32 v3, 31, v2
	v_ashrrev_i32_e32 v1, 31, v0
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v0, vcc_lo, s0, v0
	s_ashr_i32 s0, s4, 31
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	v_add_co_u32 v2, vcc_lo, s2, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
	global_load_u8 v8, v[0:1], off
	v_add_co_u32 v4, vcc_lo, v2, s4
	v_add_co_ci_u32_e32 v5, vcc_lo, s0, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v6, vcc_lo, v4, s4
	v_add_co_ci_u32_e32 v7, vcc_lo, s0, v5, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b8 v[6:7], v8, off
	global_load_u8 v8, v[0:1], off offset:1
	s_waitcnt vmcnt(0)
	global_store_b8 v[4:5], v8, off
	global_load_u8 v8, v[0:1], off offset:2
	s_waitcnt vmcnt(0)
	global_store_b8 v[2:3], v8, off
	global_load_u8 v8, v[0:1], off offset:3
	s_waitcnt vmcnt(0)
	global_store_b8 v[6:7], v8, off offset:1
	global_load_u8 v8, v[0:1], off offset:4
	s_waitcnt vmcnt(0)
	global_store_b8 v[4:5], v8, off offset:1
	global_load_u8 v8, v[0:1], off offset:5
	s_waitcnt vmcnt(0)
	global_store_b8 v[2:3], v8, off offset:1
	global_load_u8 v8, v[0:1], off offset:6
	s_waitcnt vmcnt(0)
	global_store_b8 v[6:7], v8, off offset:2
	global_load_u8 v8, v[0:1], off offset:7
	s_waitcnt vmcnt(0)
	global_store_b8 v[4:5], v8, off offset:2
	global_load_u8 v8, v[0:1], off offset:8
	s_waitcnt vmcnt(0)
	global_store_b8 v[2:3], v8, off offset:2
	global_load_u8 v8, v[0:1], off offset:9
	s_waitcnt vmcnt(0)
	global_store_b8 v[6:7], v8, off offset:3
	global_load_u8 v8, v[0:1], off offset:10
	s_waitcnt vmcnt(0)
	global_store_b8 v[4:5], v8, off offset:3
	global_load_u8 v8, v[0:1], off offset:11
	s_waitcnt vmcnt(0)
	global_store_b8 v[2:3], v8, off offset:3
	global_load_u8 v8, v[0:1], off offset:12
	s_waitcnt vmcnt(0)
	global_store_b8 v[6:7], v8, off offset:4
	global_load_u8 v8, v[0:1], off offset:13
	s_waitcnt vmcnt(0)
	global_store_b8 v[4:5], v8, off offset:4
	global_load_u8 v8, v[0:1], off offset:14
	s_waitcnt vmcnt(0)
	global_store_b8 v[2:3], v8, off offset:4
	global_load_u8 v8, v[0:1], off offset:15
	s_waitcnt vmcnt(0)
	global_store_b8 v[6:7], v8, off offset:5
	global_load_u8 v8, v[0:1], off offset:16
	s_waitcnt vmcnt(0)
	global_store_b8 v[4:5], v8, off offset:5
	global_load_u8 v8, v[0:1], off offset:17
	s_waitcnt vmcnt(0)
	global_store_b8 v[2:3], v8, off offset:5
	global_load_u8 v8, v[0:1], off offset:18
	s_waitcnt vmcnt(0)
	global_store_b8 v[6:7], v8, off offset:6
	global_load_u8 v8, v[0:1], off offset:19
	s_waitcnt vmcnt(0)
	global_store_b8 v[4:5], v8, off offset:6
	global_load_u8 v8, v[0:1], off offset:20
	s_waitcnt vmcnt(0)
	global_store_b8 v[2:3], v8, off offset:6
	global_load_u8 v8, v[0:1], off offset:21
	s_waitcnt vmcnt(0)
	global_store_b8 v[6:7], v8, off offset:7
	global_load_u8 v8, v[0:1], off offset:22
	s_waitcnt vmcnt(0)
	global_store_b8 v[4:5], v8, off offset:7
	global_load_u8 v8, v[0:1], off offset:23
	s_waitcnt vmcnt(0)
	global_store_b8 v[2:3], v8, off offset:7
	global_load_u8 v8, v[0:1], off offset:24
	s_waitcnt vmcnt(0)
	global_store_b8 v[6:7], v8, off offset:8
	global_load_u8 v8, v[0:1], off offset:25
	s_waitcnt vmcnt(0)
	global_store_b8 v[4:5], v8, off offset:8
	global_load_u8 v8, v[0:1], off offset:26
	s_waitcnt vmcnt(0)
	global_store_b8 v[2:3], v8, off offset:8
	global_load_u8 v8, v[0:1], off offset:27
	s_waitcnt vmcnt(0)
	global_store_b8 v[6:7], v8, off offset:9
	global_load_u8 v8, v[0:1], off offset:28
	s_waitcnt vmcnt(0)
	global_store_b8 v[4:5], v8, off offset:9
	global_load_u8 v8, v[0:1], off offset:29
	s_waitcnt vmcnt(0)
	global_store_b8 v[2:3], v8, off offset:9
	global_load_u8 v8, v[0:1], off offset:30
	s_waitcnt vmcnt(0)
	global_store_b8 v[6:7], v8, off offset:10
	global_load_u8 v8, v[0:1], off offset:31
	s_waitcnt vmcnt(0)
	global_store_b8 v[4:5], v8, off offset:10
	global_load_u8 v8, v[0:1], off offset:32
	s_waitcnt vmcnt(0)
	global_store_b8 v[2:3], v8, off offset:10
	global_load_u8 v8, v[0:1], off offset:33
	s_waitcnt vmcnt(0)
	global_store_b8 v[6:7], v8, off offset:11
	global_load_u8 v8, v[0:1], off offset:34
	s_waitcnt vmcnt(0)
	global_store_b8 v[4:5], v8, off offset:11
	global_load_u8 v8, v[0:1], off offset:35
	s_waitcnt vmcnt(0)
	global_store_b8 v[2:3], v8, off offset:11
	global_load_u8 v8, v[0:1], off offset:36
	s_waitcnt vmcnt(0)
	global_store_b8 v[6:7], v8, off offset:12
	global_load_u8 v8, v[0:1], off offset:37
	s_waitcnt vmcnt(0)
	global_store_b8 v[4:5], v8, off offset:12
	global_load_u8 v8, v[0:1], off offset:38
	s_waitcnt vmcnt(0)
	global_store_b8 v[2:3], v8, off offset:12
	global_load_u8 v8, v[0:1], off offset:39
	s_waitcnt vmcnt(0)
	global_store_b8 v[6:7], v8, off offset:13
	global_load_u8 v8, v[0:1], off offset:40
	s_waitcnt vmcnt(0)
	global_store_b8 v[4:5], v8, off offset:13
	global_load_u8 v8, v[0:1], off offset:41
	s_waitcnt vmcnt(0)
	global_store_b8 v[2:3], v8, off offset:13
	global_load_u8 v8, v[0:1], off offset:42
	s_waitcnt vmcnt(0)
	global_store_b8 v[6:7], v8, off offset:14
	global_load_u8 v8, v[0:1], off offset:43
	s_waitcnt vmcnt(0)
	global_store_b8 v[4:5], v8, off offset:14
	global_load_u8 v8, v[0:1], off offset:44
	s_waitcnt vmcnt(0)
	global_store_b8 v[2:3], v8, off offset:14
	global_load_u8 v8, v[0:1], off offset:45
	s_waitcnt vmcnt(0)
	global_store_b8 v[6:7], v8, off offset:15
	global_load_u8 v8, v[0:1], off offset:46
	s_waitcnt vmcnt(0)
	global_store_b8 v[4:5], v8, off offset:15
	global_load_u8 v8, v[0:1], off offset:47
	s_waitcnt vmcnt(0)
	global_store_b8 v[2:3], v8, off offset:15
	global_load_u8 v8, v[0:1], off offset:48
	s_waitcnt vmcnt(0)
	global_store_b8 v[6:7], v8, off offset:16
	global_load_u8 v8, v[0:1], off offset:49
	s_waitcnt vmcnt(0)
	global_store_b8 v[4:5], v8, off offset:16
	global_load_u8 v8, v[0:1], off offset:50
	s_waitcnt vmcnt(0)
	global_store_b8 v[2:3], v8, off offset:16
	global_load_u8 v8, v[0:1], off offset:51
	s_waitcnt vmcnt(0)
	global_store_b8 v[6:7], v8, off offset:17
	global_load_u8 v8, v[0:1], off offset:52
	s_waitcnt vmcnt(0)
	global_store_b8 v[4:5], v8, off offset:17
	global_load_u8 v8, v[0:1], off offset:53
	s_waitcnt vmcnt(0)
	global_store_b8 v[2:3], v8, off offset:17
	global_load_u8 v8, v[0:1], off offset:54
	s_waitcnt vmcnt(0)
	global_store_b8 v[6:7], v8, off offset:18
	global_load_u8 v8, v[0:1], off offset:55
	s_waitcnt vmcnt(0)
	global_store_b8 v[4:5], v8, off offset:18
	global_load_u8 v8, v[0:1], off offset:56
	s_waitcnt vmcnt(0)
	global_store_b8 v[2:3], v8, off offset:18
	global_load_u8 v8, v[0:1], off offset:57
	s_waitcnt vmcnt(0)
	global_store_b8 v[6:7], v8, off offset:19
	global_load_u8 v8, v[0:1], off offset:58
	s_waitcnt vmcnt(0)
	global_store_b8 v[4:5], v8, off offset:19
	global_load_u8 v8, v[0:1], off offset:59
	s_waitcnt vmcnt(0)
	global_store_b8 v[2:3], v8, off offset:19
	global_load_u8 v8, v[0:1], off offset:60
	s_waitcnt vmcnt(0)
	global_store_b8 v[6:7], v8, off offset:20
	global_load_u8 v8, v[0:1], off offset:61
	s_waitcnt vmcnt(0)
	global_store_b8 v[4:5], v8, off offset:20
	global_load_u8 v8, v[0:1], off offset:62
	s_waitcnt vmcnt(0)
	global_store_b8 v[2:3], v8, off offset:20
	global_load_u8 v8, v[0:1], off offset:63
	s_waitcnt vmcnt(0)
	global_store_b8 v[6:7], v8, off offset:21
	global_load_u8 v8, v[0:1], off offset:64
	s_waitcnt vmcnt(0)
	global_store_b8 v[4:5], v8, off offset:21
	global_load_u8 v8, v[0:1], off offset:65
	s_waitcnt vmcnt(0)
	global_store_b8 v[2:3], v8, off offset:21
	global_load_u8 v8, v[0:1], off offset:66
	s_waitcnt vmcnt(0)
	global_store_b8 v[6:7], v8, off offset:22
	global_load_u8 v8, v[0:1], off offset:67
	s_waitcnt vmcnt(0)
	global_store_b8 v[4:5], v8, off offset:22
	global_load_u8 v8, v[0:1], off offset:68
	s_waitcnt vmcnt(0)
	global_store_b8 v[2:3], v8, off offset:22
	global_load_u8 v8, v[0:1], off offset:69
	s_waitcnt vmcnt(0)
	global_store_b8 v[6:7], v8, off offset:23
	global_load_u8 v8, v[0:1], off offset:70
	s_waitcnt vmcnt(0)
	global_store_b8 v[4:5], v8, off offset:23
	global_load_u8 v8, v[0:1], off offset:71
	s_waitcnt vmcnt(0)
	global_store_b8 v[2:3], v8, off offset:23
	global_load_u8 v8, v[0:1], off offset:72
	s_waitcnt vmcnt(0)
	global_store_b8 v[6:7], v8, off offset:24
	global_load_u8 v8, v[0:1], off offset:73
	s_waitcnt vmcnt(0)
	global_store_b8 v[4:5], v8, off offset:24
	global_load_u8 v8, v[0:1], off offset:74
	s_waitcnt vmcnt(0)
	global_store_b8 v[2:3], v8, off offset:24
	global_load_u8 v8, v[0:1], off offset:75
	s_waitcnt vmcnt(0)
	global_store_b8 v[6:7], v8, off offset:25
	global_load_u8 v8, v[0:1], off offset:76
	s_waitcnt vmcnt(0)
	global_store_b8 v[4:5], v8, off offset:25
	global_load_u8 v8, v[0:1], off offset:77
	s_waitcnt vmcnt(0)
	global_store_b8 v[2:3], v8, off offset:25
	global_load_u8 v8, v[0:1], off offset:78
	s_waitcnt vmcnt(0)
	global_store_b8 v[6:7], v8, off offset:26
	global_load_u8 v8, v[0:1], off offset:79
	s_waitcnt vmcnt(0)
	global_store_b8 v[4:5], v8, off offset:26
	global_load_u8 v8, v[0:1], off offset:80
	s_waitcnt vmcnt(0)
	global_store_b8 v[2:3], v8, off offset:26
	global_load_u8 v8, v[0:1], off offset:81
	s_waitcnt vmcnt(0)
	global_store_b8 v[6:7], v8, off offset:27
	global_load_u8 v8, v[0:1], off offset:82
	s_waitcnt vmcnt(0)
	global_store_b8 v[4:5], v8, off offset:27
	global_load_u8 v8, v[0:1], off offset:83
	s_waitcnt vmcnt(0)
	global_store_b8 v[2:3], v8, off offset:27
	global_load_u8 v8, v[0:1], off offset:84
	s_waitcnt vmcnt(0)
	global_store_b8 v[6:7], v8, off offset:28
	global_load_u8 v8, v[0:1], off offset:85
	s_waitcnt vmcnt(0)
	global_store_b8 v[4:5], v8, off offset:28
	global_load_u8 v8, v[0:1], off offset:86
	s_waitcnt vmcnt(0)
	global_store_b8 v[2:3], v8, off offset:28
	global_load_u8 v8, v[0:1], off offset:87
	s_waitcnt vmcnt(0)
	global_store_b8 v[6:7], v8, off offset:29
	global_load_u8 v8, v[0:1], off offset:88
	s_waitcnt vmcnt(0)
	global_store_b8 v[4:5], v8, off offset:29
	global_load_u8 v8, v[0:1], off offset:89
	s_waitcnt vmcnt(0)
	global_store_b8 v[2:3], v8, off offset:29
	global_load_u8 v8, v[0:1], off offset:90
	s_waitcnt vmcnt(0)
	global_store_b8 v[6:7], v8, off offset:30
	global_load_u8 v8, v[0:1], off offset:91
	s_waitcnt vmcnt(0)
	global_store_b8 v[4:5], v8, off offset:30
	global_load_u8 v8, v[0:1], off offset:92
	s_waitcnt vmcnt(0)
	global_store_b8 v[2:3], v8, off offset:30
	global_load_u8 v8, v[0:1], off offset:93
	s_waitcnt vmcnt(0)
	global_store_b8 v[6:7], v8, off offset:31
	global_load_u8 v8, v[0:1], off offset:94
	s_waitcnt vmcnt(0)
	global_store_b8 v[4:5], v8, off offset:31
	global_load_u8 v8, v[0:1], off offset:95
	s_waitcnt vmcnt(0)
	global_store_b8 v[2:3], v8, off offset:31
	global_load_u8 v8, v[0:1], off offset:96
	s_waitcnt vmcnt(0)
	global_store_b8 v[6:7], v8, off offset:32
	global_load_u8 v8, v[0:1], off offset:97
	s_waitcnt vmcnt(0)
	global_store_b8 v[4:5], v8, off offset:32
	global_load_u8 v8, v[0:1], off offset:98
	s_waitcnt vmcnt(0)
	global_store_b8 v[2:3], v8, off offset:32
	global_load_u8 v8, v[0:1], off offset:99
	s_waitcnt vmcnt(0)
	global_store_b8 v[6:7], v8, off offset:33
	global_load_u8 v8, v[0:1], off offset:100
	s_waitcnt vmcnt(0)
	global_store_b8 v[4:5], v8, off offset:33
	global_load_u8 v8, v[0:1], off offset:101
	s_waitcnt vmcnt(0)
	global_store_b8 v[2:3], v8, off offset:33
	global_load_u8 v8, v[0:1], off offset:102
	s_waitcnt vmcnt(0)
	global_store_b8 v[6:7], v8, off offset:34
	global_load_u8 v8, v[0:1], off offset:103
	s_waitcnt vmcnt(0)
	global_store_b8 v[4:5], v8, off offset:34
	global_load_u8 v8, v[0:1], off offset:104
	s_waitcnt vmcnt(0)
	global_store_b8 v[2:3], v8, off offset:34
	global_load_u8 v8, v[0:1], off offset:105
	s_waitcnt vmcnt(0)
	global_store_b8 v[6:7], v8, off offset:35
	global_load_u8 v8, v[0:1], off offset:106
	s_waitcnt vmcnt(0)
	global_store_b8 v[4:5], v8, off offset:35
	global_load_u8 v8, v[0:1], off offset:107
	s_waitcnt vmcnt(0)
	global_store_b8 v[2:3], v8, off offset:35
	global_load_u8 v8, v[0:1], off offset:108
	s_waitcnt vmcnt(0)
	global_store_b8 v[6:7], v8, off offset:36
	global_load_u8 v8, v[0:1], off offset:109
	s_waitcnt vmcnt(0)
	global_store_b8 v[4:5], v8, off offset:36
	global_load_u8 v8, v[0:1], off offset:110
	s_waitcnt vmcnt(0)
	global_store_b8 v[2:3], v8, off offset:36
	global_load_u8 v8, v[0:1], off offset:111
	s_waitcnt vmcnt(0)
	global_store_b8 v[6:7], v8, off offset:37
	global_load_u8 v8, v[0:1], off offset:112
	s_waitcnt vmcnt(0)
	global_store_b8 v[4:5], v8, off offset:37
	global_load_u8 v8, v[0:1], off offset:113
	s_waitcnt vmcnt(0)
	global_store_b8 v[2:3], v8, off offset:37
	global_load_u8 v8, v[0:1], off offset:114
	s_waitcnt vmcnt(0)
	global_store_b8 v[6:7], v8, off offset:38
	global_load_u8 v8, v[0:1], off offset:115
	s_waitcnt vmcnt(0)
	global_store_b8 v[4:5], v8, off offset:38
	global_load_u8 v8, v[0:1], off offset:116
	s_waitcnt vmcnt(0)
	global_store_b8 v[2:3], v8, off offset:38
	global_load_u8 v8, v[0:1], off offset:117
	s_waitcnt vmcnt(0)
	global_store_b8 v[6:7], v8, off offset:39
	global_load_u8 v8, v[0:1], off offset:118
	s_waitcnt vmcnt(0)
	global_store_b8 v[4:5], v8, off offset:39
	global_load_u8 v8, v[0:1], off offset:119
	s_waitcnt vmcnt(0)
	global_store_b8 v[2:3], v8, off offset:39
	global_load_u8 v8, v[0:1], off offset:120
	s_waitcnt vmcnt(0)
	global_store_b8 v[6:7], v8, off offset:40
	global_load_u8 v8, v[0:1], off offset:121
	s_waitcnt vmcnt(0)
	global_store_b8 v[4:5], v8, off offset:40
	global_load_u8 v8, v[0:1], off offset:122
	s_waitcnt vmcnt(0)
	global_store_b8 v[2:3], v8, off offset:40
	global_load_u8 v8, v[0:1], off offset:123
	s_waitcnt vmcnt(0)
	global_store_b8 v[6:7], v8, off offset:41
	global_load_u8 v8, v[0:1], off offset:124
	s_waitcnt vmcnt(0)
	global_store_b8 v[4:5], v8, off offset:41
	global_load_u8 v8, v[0:1], off offset:125
	s_waitcnt vmcnt(0)
	global_store_b8 v[2:3], v8, off offset:41
	global_load_u8 v8, v[0:1], off offset:126
	s_waitcnt vmcnt(0)
	global_store_b8 v[6:7], v8, off offset:42
	global_load_u8 v8, v[0:1], off offset:127
	s_waitcnt vmcnt(0)
	global_store_b8 v[4:5], v8, off offset:42
	global_load_u8 v8, v[0:1], off offset:128
	s_waitcnt vmcnt(0)
	global_store_b8 v[2:3], v8, off offset:42
	global_load_u8 v8, v[0:1], off offset:129
	s_waitcnt vmcnt(0)
	global_store_b8 v[6:7], v8, off offset:43
	global_load_u8 v8, v[0:1], off offset:130
	s_waitcnt vmcnt(0)
	global_store_b8 v[4:5], v8, off offset:43
	global_load_u8 v8, v[0:1], off offset:131
	s_waitcnt vmcnt(0)
	global_store_b8 v[2:3], v8, off offset:43
	global_load_u8 v8, v[0:1], off offset:132
	s_waitcnt vmcnt(0)
	global_store_b8 v[6:7], v8, off offset:44
	global_load_u8 v8, v[0:1], off offset:133
	s_waitcnt vmcnt(0)
	global_store_b8 v[4:5], v8, off offset:44
	global_load_u8 v8, v[0:1], off offset:134
	s_waitcnt vmcnt(0)
	global_store_b8 v[2:3], v8, off offset:44
	global_load_u8 v8, v[0:1], off offset:135
	s_waitcnt vmcnt(0)
	global_store_b8 v[6:7], v8, off offset:45
	global_load_u8 v8, v[0:1], off offset:136
	s_waitcnt vmcnt(0)
	global_store_b8 v[4:5], v8, off offset:45
	global_load_u8 v8, v[0:1], off offset:137
	s_waitcnt vmcnt(0)
	global_store_b8 v[2:3], v8, off offset:45
	global_load_u8 v8, v[0:1], off offset:138
	s_waitcnt vmcnt(0)
	global_store_b8 v[6:7], v8, off offset:46
	global_load_u8 v8, v[0:1], off offset:139
	s_waitcnt vmcnt(0)
	global_store_b8 v[4:5], v8, off offset:46
	global_load_u8 v8, v[0:1], off offset:140
	s_waitcnt vmcnt(0)
	global_store_b8 v[2:3], v8, off offset:46
	global_load_u8 v8, v[0:1], off offset:141
	s_waitcnt vmcnt(0)
	global_store_b8 v[6:7], v8, off offset:47
	global_load_u8 v8, v[0:1], off offset:142
	s_waitcnt vmcnt(0)
	global_store_b8 v[4:5], v8, off offset:47
	global_load_u8 v8, v[0:1], off offset:143
	s_waitcnt vmcnt(0)
	global_store_b8 v[2:3], v8, off offset:47
	global_load_u8 v8, v[0:1], off offset:144
	s_waitcnt vmcnt(0)
	global_store_b8 v[6:7], v8, off offset:48
	global_load_u8 v8, v[0:1], off offset:145
	s_waitcnt vmcnt(0)
	global_store_b8 v[4:5], v8, off offset:48
	global_load_u8 v8, v[0:1], off offset:146
	s_waitcnt vmcnt(0)
	global_store_b8 v[2:3], v8, off offset:48
	global_load_u8 v8, v[0:1], off offset:147
	s_waitcnt vmcnt(0)
	global_store_b8 v[6:7], v8, off offset:49
	global_load_u8 v8, v[0:1], off offset:148
	s_waitcnt vmcnt(0)
	global_store_b8 v[4:5], v8, off offset:49
	global_load_u8 v8, v[0:1], off offset:149
	s_waitcnt vmcnt(0)
	global_store_b8 v[2:3], v8, off offset:49
	global_load_u8 v8, v[0:1], off offset:150
	s_waitcnt vmcnt(0)
	global_store_b8 v[6:7], v8, off offset:50
	global_load_u8 v8, v[0:1], off offset:151
	s_waitcnt vmcnt(0)
	global_store_b8 v[4:5], v8, off offset:50
	global_load_u8 v8, v[0:1], off offset:152
	s_waitcnt vmcnt(0)
	global_store_b8 v[2:3], v8, off offset:50
	global_load_u8 v8, v[0:1], off offset:153
	s_waitcnt vmcnt(0)
	global_store_b8 v[6:7], v8, off offset:51
	global_load_u8 v8, v[0:1], off offset:154
	s_waitcnt vmcnt(0)
	global_store_b8 v[4:5], v8, off offset:51
	global_load_u8 v8, v[0:1], off offset:155
	s_waitcnt vmcnt(0)
	global_store_b8 v[2:3], v8, off offset:51
	global_load_u8 v8, v[0:1], off offset:156
	s_waitcnt vmcnt(0)
	global_store_b8 v[6:7], v8, off offset:52
	global_load_u8 v8, v[0:1], off offset:157
	s_waitcnt vmcnt(0)
	global_store_b8 v[4:5], v8, off offset:52
	global_load_u8 v8, v[0:1], off offset:158
	s_waitcnt vmcnt(0)
	global_store_b8 v[2:3], v8, off offset:52
	global_load_u8 v8, v[0:1], off offset:159
	s_waitcnt vmcnt(0)
	global_store_b8 v[6:7], v8, off offset:53
	global_load_u8 v8, v[0:1], off offset:160
	s_waitcnt vmcnt(0)
	global_store_b8 v[4:5], v8, off offset:53
	global_load_u8 v8, v[0:1], off offset:161
	s_waitcnt vmcnt(0)
	global_store_b8 v[2:3], v8, off offset:53
	global_load_u8 v8, v[0:1], off offset:162
	s_waitcnt vmcnt(0)
	global_store_b8 v[6:7], v8, off offset:54
	global_load_u8 v8, v[0:1], off offset:163
	s_waitcnt vmcnt(0)
	global_store_b8 v[4:5], v8, off offset:54
	global_load_u8 v8, v[0:1], off offset:164
	s_waitcnt vmcnt(0)
	global_store_b8 v[2:3], v8, off offset:54
	global_load_u8 v8, v[0:1], off offset:165
	s_waitcnt vmcnt(0)
	global_store_b8 v[6:7], v8, off offset:55
	global_load_u8 v8, v[0:1], off offset:166
	s_waitcnt vmcnt(0)
	global_store_b8 v[4:5], v8, off offset:55
	global_load_u8 v8, v[0:1], off offset:167
	s_waitcnt vmcnt(0)
	global_store_b8 v[2:3], v8, off offset:55
	global_load_u8 v8, v[0:1], off offset:168
	s_waitcnt vmcnt(0)
	global_store_b8 v[6:7], v8, off offset:56
	global_load_u8 v8, v[0:1], off offset:169
	s_waitcnt vmcnt(0)
	global_store_b8 v[4:5], v8, off offset:56
	global_load_u8 v8, v[0:1], off offset:170
	s_waitcnt vmcnt(0)
	global_store_b8 v[2:3], v8, off offset:56
	global_load_u8 v8, v[0:1], off offset:171
	s_waitcnt vmcnt(0)
	global_store_b8 v[6:7], v8, off offset:57
	global_load_u8 v8, v[0:1], off offset:172
	s_waitcnt vmcnt(0)
	global_store_b8 v[4:5], v8, off offset:57
	global_load_u8 v8, v[0:1], off offset:173
	s_waitcnt vmcnt(0)
	global_store_b8 v[2:3], v8, off offset:57
	global_load_u8 v8, v[0:1], off offset:174
	s_waitcnt vmcnt(0)
	global_store_b8 v[6:7], v8, off offset:58
	global_load_u8 v8, v[0:1], off offset:175
	s_waitcnt vmcnt(0)
	global_store_b8 v[4:5], v8, off offset:58
	global_load_u8 v8, v[0:1], off offset:176
	s_waitcnt vmcnt(0)
	global_store_b8 v[2:3], v8, off offset:58
	global_load_u8 v8, v[0:1], off offset:177
	s_waitcnt vmcnt(0)
	global_store_b8 v[6:7], v8, off offset:59
	global_load_u8 v8, v[0:1], off offset:178
	s_waitcnt vmcnt(0)
	global_store_b8 v[4:5], v8, off offset:59
	global_load_u8 v8, v[0:1], off offset:179
	s_waitcnt vmcnt(0)
	global_store_b8 v[2:3], v8, off offset:59
	global_load_u8 v8, v[0:1], off offset:180
	s_waitcnt vmcnt(0)
	global_store_b8 v[6:7], v8, off offset:60
	global_load_u8 v8, v[0:1], off offset:181
	s_waitcnt vmcnt(0)
	global_store_b8 v[4:5], v8, off offset:60
	global_load_u8 v8, v[0:1], off offset:182
	s_waitcnt vmcnt(0)
	global_store_b8 v[2:3], v8, off offset:60
	global_load_u8 v8, v[0:1], off offset:183
	s_waitcnt vmcnt(0)
	global_store_b8 v[6:7], v8, off offset:61
	global_load_u8 v8, v[0:1], off offset:184
	s_waitcnt vmcnt(0)
	global_store_b8 v[4:5], v8, off offset:61
	global_load_u8 v8, v[0:1], off offset:185
	s_waitcnt vmcnt(0)
	global_store_b8 v[2:3], v8, off offset:61
	global_load_u8 v8, v[0:1], off offset:186
	s_waitcnt vmcnt(0)
	global_store_b8 v[6:7], v8, off offset:62
	global_load_u8 v8, v[0:1], off offset:187
	s_waitcnt vmcnt(0)
	global_store_b8 v[4:5], v8, off offset:62
	global_load_u8 v8, v[0:1], off offset:188
	s_waitcnt vmcnt(0)
	global_store_b8 v[2:3], v8, off offset:62
	global_load_u8 v8, v[0:1], off offset:189
	s_waitcnt vmcnt(0)
	global_store_b8 v[6:7], v8, off offset:63
	global_load_u8 v8, v[0:1], off offset:190
	s_waitcnt vmcnt(0)
	global_store_b8 v[4:5], v8, off offset:63
	global_load_u8 v8, v[0:1], off offset:191
	s_waitcnt vmcnt(0)
	global_store_b8 v[2:3], v8, off offset:63
	global_load_u8 v8, v[0:1], off offset:192
	s_waitcnt vmcnt(0)
	global_store_b8 v[6:7], v8, off offset:64
	global_load_u8 v8, v[0:1], off offset:193
	s_waitcnt vmcnt(0)
	global_store_b8 v[4:5], v8, off offset:64
	global_load_u8 v8, v[0:1], off offset:194
	s_waitcnt vmcnt(0)
	global_store_b8 v[2:3], v8, off offset:64
	global_load_u8 v8, v[0:1], off offset:195
	s_waitcnt vmcnt(0)
	global_store_b8 v[6:7], v8, off offset:65
	global_load_u8 v8, v[0:1], off offset:196
	s_waitcnt vmcnt(0)
	global_store_b8 v[4:5], v8, off offset:65
	global_load_u8 v8, v[0:1], off offset:197
	s_waitcnt vmcnt(0)
	global_store_b8 v[2:3], v8, off offset:65
	global_load_u8 v8, v[0:1], off offset:198
	s_waitcnt vmcnt(0)
	global_store_b8 v[6:7], v8, off offset:66
	global_load_u8 v8, v[0:1], off offset:199
	s_waitcnt vmcnt(0)
	global_store_b8 v[4:5], v8, off offset:66
	global_load_u8 v8, v[0:1], off offset:200
	s_waitcnt vmcnt(0)
	global_store_b8 v[2:3], v8, off offset:66
	global_load_u8 v8, v[0:1], off offset:201
	s_waitcnt vmcnt(0)
	global_store_b8 v[6:7], v8, off offset:67
	global_load_u8 v8, v[0:1], off offset:202
	s_waitcnt vmcnt(0)
	global_store_b8 v[4:5], v8, off offset:67
	global_load_u8 v8, v[0:1], off offset:203
	s_waitcnt vmcnt(0)
	global_store_b8 v[2:3], v8, off offset:67
	global_load_u8 v8, v[0:1], off offset:204
	s_waitcnt vmcnt(0)
	global_store_b8 v[6:7], v8, off offset:68
	global_load_u8 v8, v[0:1], off offset:205
	s_waitcnt vmcnt(0)
	global_store_b8 v[4:5], v8, off offset:68
	global_load_u8 v8, v[0:1], off offset:206
	s_waitcnt vmcnt(0)
	global_store_b8 v[2:3], v8, off offset:68
	global_load_u8 v8, v[0:1], off offset:207
	s_waitcnt vmcnt(0)
	global_store_b8 v[6:7], v8, off offset:69
	global_load_u8 v8, v[0:1], off offset:208
	s_waitcnt vmcnt(0)
	global_store_b8 v[4:5], v8, off offset:69
	global_load_u8 v8, v[0:1], off offset:209
	s_waitcnt vmcnt(0)
	global_store_b8 v[2:3], v8, off offset:69
	global_load_u8 v8, v[0:1], off offset:210
	s_waitcnt vmcnt(0)
	global_store_b8 v[6:7], v8, off offset:70
	global_load_u8 v8, v[0:1], off offset:211
	s_waitcnt vmcnt(0)
	global_store_b8 v[4:5], v8, off offset:70
	global_load_u8 v8, v[0:1], off offset:212
	s_waitcnt vmcnt(0)
	global_store_b8 v[2:3], v8, off offset:70
	global_load_u8 v8, v[0:1], off offset:213
	s_waitcnt vmcnt(0)
	global_store_b8 v[6:7], v8, off offset:71
	global_load_u8 v8, v[0:1], off offset:214
	s_waitcnt vmcnt(0)
	global_store_b8 v[4:5], v8, off offset:71
	global_load_u8 v8, v[0:1], off offset:215
	s_waitcnt vmcnt(0)
	global_store_b8 v[2:3], v8, off offset:71
	global_load_u8 v8, v[0:1], off offset:216
	s_waitcnt vmcnt(0)
	global_store_b8 v[6:7], v8, off offset:72
	global_load_u8 v8, v[0:1], off offset:217
	s_waitcnt vmcnt(0)
	global_store_b8 v[4:5], v8, off offset:72
	global_load_u8 v8, v[0:1], off offset:218
	s_waitcnt vmcnt(0)
	global_store_b8 v[2:3], v8, off offset:72
	global_load_u8 v8, v[0:1], off offset:219
	s_waitcnt vmcnt(0)
	global_store_b8 v[6:7], v8, off offset:73
	global_load_u8 v8, v[0:1], off offset:220
	s_waitcnt vmcnt(0)
	global_store_b8 v[4:5], v8, off offset:73
	global_load_u8 v8, v[0:1], off offset:221
	s_waitcnt vmcnt(0)
	global_store_b8 v[2:3], v8, off offset:73
	global_load_u8 v8, v[0:1], off offset:222
	s_waitcnt vmcnt(0)
	global_store_b8 v[6:7], v8, off offset:74
	global_load_u8 v8, v[0:1], off offset:223
	s_waitcnt vmcnt(0)
	global_store_b8 v[4:5], v8, off offset:74
	global_load_u8 v8, v[0:1], off offset:224
	s_waitcnt vmcnt(0)
	global_store_b8 v[2:3], v8, off offset:74
	global_load_u8 v8, v[0:1], off offset:225
	s_waitcnt vmcnt(0)
	global_store_b8 v[6:7], v8, off offset:75
	global_load_u8 v8, v[0:1], off offset:226
	s_waitcnt vmcnt(0)
	global_store_b8 v[4:5], v8, off offset:75
	global_load_u8 v8, v[0:1], off offset:227
	s_waitcnt vmcnt(0)
	global_store_b8 v[2:3], v8, off offset:75
	global_load_u8 v8, v[0:1], off offset:228
	s_waitcnt vmcnt(0)
	global_store_b8 v[6:7], v8, off offset:76
	global_load_u8 v8, v[0:1], off offset:229
	s_waitcnt vmcnt(0)
	global_store_b8 v[4:5], v8, off offset:76
	global_load_u8 v8, v[0:1], off offset:230
	s_waitcnt vmcnt(0)
	global_store_b8 v[2:3], v8, off offset:76
	global_load_u8 v8, v[0:1], off offset:231
	s_waitcnt vmcnt(0)
	global_store_b8 v[6:7], v8, off offset:77
	global_load_u8 v8, v[0:1], off offset:232
	s_waitcnt vmcnt(0)
	global_store_b8 v[4:5], v8, off offset:77
	global_load_u8 v8, v[0:1], off offset:233
	s_waitcnt vmcnt(0)
	global_store_b8 v[2:3], v8, off offset:77
	global_load_u8 v8, v[0:1], off offset:234
	s_waitcnt vmcnt(0)
	global_store_b8 v[6:7], v8, off offset:78
	global_load_u8 v8, v[0:1], off offset:235
	s_waitcnt vmcnt(0)
	global_store_b8 v[4:5], v8, off offset:78
	global_load_u8 v8, v[0:1], off offset:236
	s_waitcnt vmcnt(0)
	global_store_b8 v[2:3], v8, off offset:78
	global_load_u8 v8, v[0:1], off offset:237
	s_waitcnt vmcnt(0)
	global_store_b8 v[6:7], v8, off offset:79
	global_load_u8 v8, v[0:1], off offset:238
	s_waitcnt vmcnt(0)
	global_store_b8 v[4:5], v8, off offset:79
	global_load_u8 v8, v[0:1], off offset:239
	s_waitcnt vmcnt(0)
	global_store_b8 v[2:3], v8, off offset:79
	global_load_u8 v8, v[0:1], off offset:240
	s_waitcnt vmcnt(0)
	global_store_b8 v[6:7], v8, off offset:80
	global_load_u8 v8, v[0:1], off offset:241
	s_waitcnt vmcnt(0)
	global_store_b8 v[4:5], v8, off offset:80
	global_load_u8 v8, v[0:1], off offset:242
	s_waitcnt vmcnt(0)
	global_store_b8 v[2:3], v8, off offset:80
	global_load_u8 v8, v[0:1], off offset:243
	s_waitcnt vmcnt(0)
	global_store_b8 v[6:7], v8, off offset:81
	global_load_u8 v8, v[0:1], off offset:244
	s_waitcnt vmcnt(0)
	global_store_b8 v[4:5], v8, off offset:81
	global_load_u8 v8, v[0:1], off offset:245
	s_waitcnt vmcnt(0)
	global_store_b8 v[2:3], v8, off offset:81
	global_load_u8 v8, v[0:1], off offset:246
	s_waitcnt vmcnt(0)
	global_store_b8 v[6:7], v8, off offset:82
	global_load_u8 v8, v[0:1], off offset:247
	s_waitcnt vmcnt(0)
	global_store_b8 v[4:5], v8, off offset:82
	global_load_u8 v8, v[0:1], off offset:248
	s_waitcnt vmcnt(0)
	global_store_b8 v[2:3], v8, off offset:82
	global_load_u8 v8, v[0:1], off offset:249
	s_waitcnt vmcnt(0)
	global_store_b8 v[6:7], v8, off offset:83
	global_load_u8 v8, v[0:1], off offset:250
	s_waitcnt vmcnt(0)
	global_store_b8 v[4:5], v8, off offset:83
	global_load_u8 v8, v[0:1], off offset:251
	s_waitcnt vmcnt(0)
	global_store_b8 v[2:3], v8, off offset:83
	global_load_u8 v8, v[0:1], off offset:252
	s_waitcnt vmcnt(0)
	global_store_b8 v[6:7], v8, off offset:84
	global_load_u8 v8, v[0:1], off offset:253
	s_waitcnt vmcnt(0)
	global_store_b8 v[4:5], v8, off offset:84
	global_load_u8 v8, v[0:1], off offset:254
	s_waitcnt vmcnt(0)
	global_store_b8 v[2:3], v8, off offset:84
	global_load_u8 v8, v[0:1], off offset:255
	s_waitcnt vmcnt(0)
	global_store_b8 v[6:7], v8, off offset:85
	global_load_u8 v8, v[0:1], off offset:256
	s_waitcnt vmcnt(0)
	global_store_b8 v[4:5], v8, off offset:85
	global_load_u8 v8, v[0:1], off offset:257
	s_waitcnt vmcnt(0)
	global_store_b8 v[2:3], v8, off offset:85
	global_load_u8 v8, v[0:1], off offset:258
	s_waitcnt vmcnt(0)
	global_store_b8 v[6:7], v8, off offset:86
	global_load_u8 v8, v[0:1], off offset:259
	s_waitcnt vmcnt(0)
	global_store_b8 v[4:5], v8, off offset:86
	global_load_u8 v8, v[0:1], off offset:260
	s_waitcnt vmcnt(0)
	global_store_b8 v[2:3], v8, off offset:86
	global_load_u8 v8, v[0:1], off offset:261
	s_waitcnt vmcnt(0)
	global_store_b8 v[6:7], v8, off offset:87
	global_load_u8 v8, v[0:1], off offset:262
	s_waitcnt vmcnt(0)
	global_store_b8 v[4:5], v8, off offset:87
	global_load_u8 v8, v[0:1], off offset:263
	s_waitcnt vmcnt(0)
	global_store_b8 v[2:3], v8, off offset:87
	global_load_u8 v8, v[0:1], off offset:264
	s_waitcnt vmcnt(0)
	global_store_b8 v[6:7], v8, off offset:88
	global_load_u8 v8, v[0:1], off offset:265
	s_waitcnt vmcnt(0)
	global_store_b8 v[4:5], v8, off offset:88
	global_load_u8 v8, v[0:1], off offset:266
	s_waitcnt vmcnt(0)
	global_store_b8 v[2:3], v8, off offset:88
	global_load_u8 v8, v[0:1], off offset:267
	s_waitcnt vmcnt(0)
	global_store_b8 v[6:7], v8, off offset:89
	global_load_u8 v8, v[0:1], off offset:268
	s_waitcnt vmcnt(0)
	global_store_b8 v[4:5], v8, off offset:89
	global_load_u8 v8, v[0:1], off offset:269
	s_waitcnt vmcnt(0)
	global_store_b8 v[2:3], v8, off offset:89
	global_load_u8 v8, v[0:1], off offset:270
	s_waitcnt vmcnt(0)
	global_store_b8 v[6:7], v8, off offset:90
	global_load_u8 v8, v[0:1], off offset:271
	s_waitcnt vmcnt(0)
	global_store_b8 v[4:5], v8, off offset:90
	global_load_u8 v8, v[0:1], off offset:272
	s_waitcnt vmcnt(0)
	global_store_b8 v[2:3], v8, off offset:90
	global_load_u8 v8, v[0:1], off offset:273
	s_waitcnt vmcnt(0)
	global_store_b8 v[6:7], v8, off offset:91
	global_load_u8 v8, v[0:1], off offset:274
	s_waitcnt vmcnt(0)
	global_store_b8 v[4:5], v8, off offset:91
	global_load_u8 v8, v[0:1], off offset:275
	s_waitcnt vmcnt(0)
	global_store_b8 v[2:3], v8, off offset:91
	global_load_u8 v8, v[0:1], off offset:276
	s_waitcnt vmcnt(0)
	global_store_b8 v[6:7], v8, off offset:92
	global_load_u8 v8, v[0:1], off offset:277
	s_waitcnt vmcnt(0)
	global_store_b8 v[4:5], v8, off offset:92
	global_load_u8 v8, v[0:1], off offset:278
	s_waitcnt vmcnt(0)
	global_store_b8 v[2:3], v8, off offset:92
	global_load_u8 v8, v[0:1], off offset:279
	s_waitcnt vmcnt(0)
	global_store_b8 v[6:7], v8, off offset:93
	global_load_u8 v8, v[0:1], off offset:280
	s_waitcnt vmcnt(0)
	global_store_b8 v[4:5], v8, off offset:93
	global_load_u8 v8, v[0:1], off offset:281
	s_waitcnt vmcnt(0)
	global_store_b8 v[2:3], v8, off offset:93
	global_load_u8 v8, v[0:1], off offset:282
	s_waitcnt vmcnt(0)
	global_store_b8 v[6:7], v8, off offset:94
	global_load_u8 v8, v[0:1], off offset:283
	s_waitcnt vmcnt(0)
	global_store_b8 v[4:5], v8, off offset:94
	global_load_u8 v8, v[0:1], off offset:284
	s_waitcnt vmcnt(0)
	global_store_b8 v[2:3], v8, off offset:94
	global_load_u8 v8, v[0:1], off offset:285
	s_waitcnt vmcnt(0)
	global_store_b8 v[6:7], v8, off offset:95
	global_load_u8 v8, v[0:1], off offset:286
	s_waitcnt vmcnt(0)
	global_store_b8 v[4:5], v8, off offset:95
	global_load_u8 v8, v[0:1], off offset:287
	s_waitcnt vmcnt(0)
	global_store_b8 v[2:3], v8, off offset:95
	global_load_u8 v8, v[0:1], off offset:288
	s_waitcnt vmcnt(0)
	global_store_b8 v[6:7], v8, off offset:96
	global_load_u8 v8, v[0:1], off offset:289
	s_waitcnt vmcnt(0)
	global_store_b8 v[4:5], v8, off offset:96
	global_load_u8 v8, v[0:1], off offset:290
	s_waitcnt vmcnt(0)
	global_store_b8 v[2:3], v8, off offset:96
	global_load_u8 v8, v[0:1], off offset:291
	s_waitcnt vmcnt(0)
	global_store_b8 v[6:7], v8, off offset:97
	global_load_u8 v8, v[0:1], off offset:292
	s_waitcnt vmcnt(0)
	global_store_b8 v[4:5], v8, off offset:97
	global_load_u8 v8, v[0:1], off offset:293
	s_waitcnt vmcnt(0)
	global_store_b8 v[2:3], v8, off offset:97
	global_load_u8 v8, v[0:1], off offset:294
	s_waitcnt vmcnt(0)
	global_store_b8 v[6:7], v8, off offset:98
	global_load_u8 v8, v[0:1], off offset:295
	s_waitcnt vmcnt(0)
	global_store_b8 v[4:5], v8, off offset:98
	global_load_u8 v8, v[0:1], off offset:296
	s_waitcnt vmcnt(0)
	global_store_b8 v[2:3], v8, off offset:98
	global_load_u8 v8, v[0:1], off offset:297
	s_waitcnt vmcnt(0)
	global_store_b8 v[6:7], v8, off offset:99
	global_load_u8 v8, v[0:1], off offset:298
	s_waitcnt vmcnt(0)
	global_store_b8 v[4:5], v8, off offset:99
	global_load_u8 v8, v[0:1], off offset:299
	s_waitcnt vmcnt(0)
	global_store_b8 v[2:3], v8, off offset:99
	global_load_u8 v8, v[0:1], off offset:300
	s_waitcnt vmcnt(0)
	global_store_b8 v[6:7], v8, off offset:100
	global_load_u8 v8, v[0:1], off offset:301
	s_waitcnt vmcnt(0)
	global_store_b8 v[4:5], v8, off offset:100
	global_load_u8 v8, v[0:1], off offset:302
	s_waitcnt vmcnt(0)
	global_store_b8 v[2:3], v8, off offset:100
	global_load_u8 v8, v[0:1], off offset:303
	s_waitcnt vmcnt(0)
	global_store_b8 v[6:7], v8, off offset:101
	global_load_u8 v8, v[0:1], off offset:304
	s_waitcnt vmcnt(0)
	global_store_b8 v[4:5], v8, off offset:101
	global_load_u8 v8, v[0:1], off offset:305
	s_waitcnt vmcnt(0)
	global_store_b8 v[2:3], v8, off offset:101
	global_load_u8 v8, v[0:1], off offset:306
	s_waitcnt vmcnt(0)
	global_store_b8 v[6:7], v8, off offset:102
	global_load_u8 v8, v[0:1], off offset:307
	s_waitcnt vmcnt(0)
	global_store_b8 v[4:5], v8, off offset:102
	global_load_u8 v8, v[0:1], off offset:308
	s_waitcnt vmcnt(0)
	global_store_b8 v[2:3], v8, off offset:102
	global_load_u8 v8, v[0:1], off offset:309
	s_waitcnt vmcnt(0)
	global_store_b8 v[6:7], v8, off offset:103
	global_load_u8 v8, v[0:1], off offset:310
	s_waitcnt vmcnt(0)
	global_store_b8 v[4:5], v8, off offset:103
	global_load_u8 v8, v[0:1], off offset:311
	s_waitcnt vmcnt(0)
	global_store_b8 v[2:3], v8, off offset:103
	global_load_u8 v8, v[0:1], off offset:312
	s_waitcnt vmcnt(0)
	global_store_b8 v[6:7], v8, off offset:104
	global_load_u8 v8, v[0:1], off offset:313
	s_waitcnt vmcnt(0)
	global_store_b8 v[4:5], v8, off offset:104
	global_load_u8 v8, v[0:1], off offset:314
	s_waitcnt vmcnt(0)
	global_store_b8 v[2:3], v8, off offset:104
	global_load_u8 v8, v[0:1], off offset:315
	s_waitcnt vmcnt(0)
	global_store_b8 v[6:7], v8, off offset:105
	global_load_u8 v8, v[0:1], off offset:316
	s_waitcnt vmcnt(0)
	global_store_b8 v[4:5], v8, off offset:105
	global_load_u8 v8, v[0:1], off offset:317
	s_waitcnt vmcnt(0)
	global_store_b8 v[2:3], v8, off offset:105
	global_load_u8 v8, v[0:1], off offset:318
	s_waitcnt vmcnt(0)
	global_store_b8 v[6:7], v8, off offset:106
	global_load_u8 v8, v[0:1], off offset:319
	s_waitcnt vmcnt(0)
	global_store_b8 v[4:5], v8, off offset:106
	global_load_u8 v8, v[0:1], off offset:320
	s_waitcnt vmcnt(0)
	global_store_b8 v[2:3], v8, off offset:106
	global_load_u8 v8, v[0:1], off offset:321
	s_waitcnt vmcnt(0)
	global_store_b8 v[6:7], v8, off offset:107
	global_load_u8 v8, v[0:1], off offset:322
	s_waitcnt vmcnt(0)
	global_store_b8 v[4:5], v8, off offset:107
	global_load_u8 v8, v[0:1], off offset:323
	s_waitcnt vmcnt(0)
	global_store_b8 v[2:3], v8, off offset:107
	global_load_u8 v8, v[0:1], off offset:324
	s_waitcnt vmcnt(0)
	global_store_b8 v[6:7], v8, off offset:108
	global_load_u8 v8, v[0:1], off offset:325
	s_waitcnt vmcnt(0)
	global_store_b8 v[4:5], v8, off offset:108
	global_load_u8 v8, v[0:1], off offset:326
	s_waitcnt vmcnt(0)
	global_store_b8 v[2:3], v8, off offset:108
	global_load_u8 v8, v[0:1], off offset:327
	s_waitcnt vmcnt(0)
	global_store_b8 v[6:7], v8, off offset:109
	global_load_u8 v8, v[0:1], off offset:328
	s_waitcnt vmcnt(0)
	global_store_b8 v[4:5], v8, off offset:109
	global_load_u8 v8, v[0:1], off offset:329
	s_waitcnt vmcnt(0)
	global_store_b8 v[2:3], v8, off offset:109
	global_load_u8 v8, v[0:1], off offset:330
	s_waitcnt vmcnt(0)
	global_store_b8 v[6:7], v8, off offset:110
	global_load_u8 v8, v[0:1], off offset:331
	s_waitcnt vmcnt(0)
	global_store_b8 v[4:5], v8, off offset:110
	global_load_u8 v8, v[0:1], off offset:332
	s_waitcnt vmcnt(0)
	global_store_b8 v[2:3], v8, off offset:110
	global_load_u8 v8, v[0:1], off offset:333
	s_waitcnt vmcnt(0)
	global_store_b8 v[6:7], v8, off offset:111
	global_load_u8 v8, v[0:1], off offset:334
	s_waitcnt vmcnt(0)
	global_store_b8 v[4:5], v8, off offset:111
	global_load_u8 v8, v[0:1], off offset:335
	s_waitcnt vmcnt(0)
	global_store_b8 v[2:3], v8, off offset:111
	global_load_u8 v8, v[0:1], off offset:336
	s_waitcnt vmcnt(0)
	global_store_b8 v[6:7], v8, off offset:112
	global_load_u8 v8, v[0:1], off offset:337
	s_waitcnt vmcnt(0)
	global_store_b8 v[4:5], v8, off offset:112
	global_load_u8 v8, v[0:1], off offset:338
	s_waitcnt vmcnt(0)
	global_store_b8 v[2:3], v8, off offset:112
	global_load_u8 v8, v[0:1], off offset:339
	s_waitcnt vmcnt(0)
	global_store_b8 v[6:7], v8, off offset:113
	global_load_u8 v8, v[0:1], off offset:340
	s_waitcnt vmcnt(0)
	global_store_b8 v[4:5], v8, off offset:113
	global_load_u8 v8, v[0:1], off offset:341
	s_waitcnt vmcnt(0)
	global_store_b8 v[2:3], v8, off offset:113
	global_load_u8 v8, v[0:1], off offset:342
	s_waitcnt vmcnt(0)
	global_store_b8 v[6:7], v8, off offset:114
	global_load_u8 v8, v[0:1], off offset:343
	s_waitcnt vmcnt(0)
	global_store_b8 v[4:5], v8, off offset:114
	global_load_u8 v8, v[0:1], off offset:344
	s_waitcnt vmcnt(0)
	global_store_b8 v[2:3], v8, off offset:114
	global_load_u8 v8, v[0:1], off offset:345
	s_waitcnt vmcnt(0)
	global_store_b8 v[6:7], v8, off offset:115
	global_load_u8 v8, v[0:1], off offset:346
	s_waitcnt vmcnt(0)
	global_store_b8 v[4:5], v8, off offset:115
	global_load_u8 v8, v[0:1], off offset:347
	s_waitcnt vmcnt(0)
	global_store_b8 v[2:3], v8, off offset:115
	global_load_u8 v8, v[0:1], off offset:348
	s_waitcnt vmcnt(0)
	global_store_b8 v[6:7], v8, off offset:116
	global_load_u8 v8, v[0:1], off offset:349
	s_waitcnt vmcnt(0)
	global_store_b8 v[4:5], v8, off offset:116
	global_load_u8 v8, v[0:1], off offset:350
	s_waitcnt vmcnt(0)
	global_store_b8 v[2:3], v8, off offset:116
	global_load_u8 v8, v[0:1], off offset:351
	s_waitcnt vmcnt(0)
	global_store_b8 v[6:7], v8, off offset:117
	global_load_u8 v8, v[0:1], off offset:352
	s_waitcnt vmcnt(0)
	global_store_b8 v[4:5], v8, off offset:117
	global_load_u8 v8, v[0:1], off offset:353
	s_waitcnt vmcnt(0)
	global_store_b8 v[2:3], v8, off offset:117
	global_load_u8 v8, v[0:1], off offset:354
	s_waitcnt vmcnt(0)
	global_store_b8 v[6:7], v8, off offset:118
	global_load_u8 v8, v[0:1], off offset:355
	s_waitcnt vmcnt(0)
	global_store_b8 v[4:5], v8, off offset:118
	global_load_u8 v8, v[0:1], off offset:356
	s_waitcnt vmcnt(0)
	global_store_b8 v[2:3], v8, off offset:118
	global_load_u8 v8, v[0:1], off offset:357
	s_waitcnt vmcnt(0)
	global_store_b8 v[6:7], v8, off offset:119
	global_load_u8 v8, v[0:1], off offset:358
	s_waitcnt vmcnt(0)
	global_store_b8 v[4:5], v8, off offset:119
	global_load_u8 v8, v[0:1], off offset:359
	s_waitcnt vmcnt(0)
	global_store_b8 v[2:3], v8, off offset:119
	global_load_u8 v8, v[0:1], off offset:360
	s_waitcnt vmcnt(0)
	global_store_b8 v[6:7], v8, off offset:120
	global_load_u8 v8, v[0:1], off offset:361
	s_waitcnt vmcnt(0)
	global_store_b8 v[4:5], v8, off offset:120
	global_load_u8 v8, v[0:1], off offset:362
	s_waitcnt vmcnt(0)
	global_store_b8 v[2:3], v8, off offset:120
	global_load_u8 v8, v[0:1], off offset:363
	s_waitcnt vmcnt(0)
	global_store_b8 v[6:7], v8, off offset:121
	global_load_u8 v8, v[0:1], off offset:364
	s_waitcnt vmcnt(0)
	global_store_b8 v[4:5], v8, off offset:121
	global_load_u8 v8, v[0:1], off offset:365
	s_waitcnt vmcnt(0)
	global_store_b8 v[2:3], v8, off offset:121
	global_load_u8 v8, v[0:1], off offset:366
	s_waitcnt vmcnt(0)
	global_store_b8 v[6:7], v8, off offset:122
	global_load_u8 v8, v[0:1], off offset:367
	s_waitcnt vmcnt(0)
	global_store_b8 v[4:5], v8, off offset:122
	global_load_u8 v8, v[0:1], off offset:368
	s_waitcnt vmcnt(0)
	global_store_b8 v[2:3], v8, off offset:122
	global_load_u8 v8, v[0:1], off offset:369
	s_waitcnt vmcnt(0)
	global_store_b8 v[6:7], v8, off offset:123
	global_load_u8 v8, v[0:1], off offset:370
	s_waitcnt vmcnt(0)
	global_store_b8 v[4:5], v8, off offset:123
	global_load_u8 v8, v[0:1], off offset:371
	s_waitcnt vmcnt(0)
	global_store_b8 v[2:3], v8, off offset:123
	global_load_u8 v8, v[0:1], off offset:372
	s_waitcnt vmcnt(0)
	global_store_b8 v[6:7], v8, off offset:124
	global_load_u8 v8, v[0:1], off offset:373
	s_waitcnt vmcnt(0)
	global_store_b8 v[4:5], v8, off offset:124
	global_load_u8 v8, v[0:1], off offset:374
	s_waitcnt vmcnt(0)
	global_store_b8 v[2:3], v8, off offset:124
	global_load_u8 v8, v[0:1], off offset:375
	s_waitcnt vmcnt(0)
	global_store_b8 v[6:7], v8, off offset:125
	global_load_u8 v8, v[0:1], off offset:376
	s_waitcnt vmcnt(0)
	global_store_b8 v[4:5], v8, off offset:125
	global_load_u8 v8, v[0:1], off offset:377
	s_waitcnt vmcnt(0)
	global_store_b8 v[2:3], v8, off offset:125
	global_load_u8 v8, v[0:1], off offset:378
	s_waitcnt vmcnt(0)
	global_store_b8 v[6:7], v8, off offset:126
	global_load_u8 v8, v[0:1], off offset:379
	s_waitcnt vmcnt(0)
	global_store_b8 v[4:5], v8, off offset:126
	global_load_u8 v8, v[0:1], off offset:380
	s_waitcnt vmcnt(0)
	global_store_b8 v[2:3], v8, off offset:126
	global_load_u8 v8, v[0:1], off offset:381
	s_waitcnt vmcnt(0)
	global_store_b8 v[6:7], v8, off offset:127
	global_load_u8 v6, v[0:1], off offset:382
	s_waitcnt vmcnt(0)
	global_store_b8 v[4:5], v6, off offset:127
	global_load_u8 v0, v[0:1], off offset:383
	s_waitcnt vmcnt(0)
	global_store_b8 v[2:3], v0, off offset:127
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z10convert128PcS_ii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 9
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_Z10convert128PcS_ii, .Lfunc_end2-_Z10convert128PcS_ii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 7836
; NumSgprs: 18
; NumVgprs: 9
; ScratchSize: 0
; MemoryBound: 1
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 9
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z7convertPcS_ii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z7convertPcS_ii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     7
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z11convertBackPcS_ii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z11convertBackPcS_ii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     7
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z10convert128PcS_ii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z10convert128PcS_ii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     9
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
