#include "includes.h"
__global__ void ComputeRobustnessMask( const float3* __restrict__ rawImgRef, const float3* __restrict__ rawImgMoved, float4* __restrict__ robustnessMask, cudaTextureObject_t texUV, int imgWidth, int imgHeight, int imgPitch, int maskPitch, float alpha, float beta, float thresholdM)
{
int pxX = blockIdx.x * blockDim.x + threadIdx.x;
int pxY = blockIdx.y * blockDim.y + threadIdx.y;

extern __shared__ float3 pixelsRef[];
int sharedOffset = 3 * 3 * (threadIdx.y * blockDim.x + threadIdx.x);

if (pxX >= imgWidth - 1|| pxY >= imgHeight - 1 || pxX < 1 || pxY < 1)
return;

float3 meanRef = make_float3(0, 0, 0);
float3 meanMoved = make_float3(0, 0, 0);
float3 stdRef = make_float3(0, 0, 0);
float3 stdMoved = make_float3(0, 0, 0);
float3 dist = make_float3(0, 0, 0);
float3 sigma = make_float3(0, 0, 0);

float2 shiftf = tex2D<float2>(texUV, ((float)pxX + 0.5f) / (float)imgWidth, ((float)pxY + 0.5f) / (float)imgHeight);
float2 maxShift = shiftf;
float2 minShift = shiftf;

for (int y = -2; y <= 2; y++)
{
for (int x = -2; x <= 2; x++)
{
float2 s = tex2D<float2>(texUV, ((float)pxX + x + 0.5f) / (float)imgWidth, ((float)pxY + y + 0.5f) / (float)imgHeight);
maxShift.x = fmaxf(s.x, shiftf.x);
maxShift.y = fmaxf(s.y, shiftf.y);
minShift.x = fminf(s.x, shiftf.x);
minShift.y = fminf(s.y, shiftf.y);
}
}

int2 shift;
//half resolution image:
shift.x = roundf(shiftf.x * 0.5f);
shift.y = roundf(shiftf.y * 0.5f);

for (int y = -1; y <= 1; y++)
{
for (int x = -1; x <= 1; x++)
{
float3 p = *(((float3*)((char*)rawImgRef + imgPitch * (pxY + y))) + pxX + x);
pixelsRef[sharedOffset + (y + 1) * 3 + (x + 1)] = p;

meanRef.x += p.x;
meanRef.y += p.y;
meanRef.z += p.z;

int ppy = min(max(pxY + shift.y + y, 0), imgHeight - 1);
int ppx = min(max(pxX + shift.x + x, 0), imgWidth - 1);
p = *(((float3*)((char*)rawImgMoved + imgPitch * (ppy))) + ppx);
meanMoved.x += p.x;
meanMoved.y += p.y;
meanMoved.z += p.z;
}
}
meanRef.x /= 9.0f;
meanRef.y /= 9.0f;
meanRef.z /= 9.0f;
meanMoved.x /= 9.0f;
meanMoved.y /= 9.0f;
meanMoved.z /= 9.0f;

float meandist = fabs(meanRef.x - meanMoved.x) + fabs(meanRef.y - meanMoved.y) + fabs(meanRef.z - meanMoved.z);
meandist /= 3.0f;
maxShift.x *= 0.5f * meandist;
maxShift.y *= 0.5f * meandist;
minShift.x *= 0.5f * meandist;
minShift.y *= 0.5f * meandist;

float M = sqrtf((maxShift.x - minShift.x) * (maxShift.x - minShift.x) + (maxShift.y - minShift.y) * (maxShift.y - minShift.y));

for (int y = -1; y <= 1; y++)
{
for (int x = -1; x <= 1; x++)
{
int p = sharedOffset + (y + 1) * 3 + (x + 1);
stdRef.x += (pixelsRef[p].x - meanRef.x) * (pixelsRef[p].x - meanRef.x);
stdRef.y += (pixelsRef[p].y - meanRef.y) * (pixelsRef[p].y - meanRef.y);
stdRef.z += (pixelsRef[p].z - meanRef.z) * (pixelsRef[p].z - meanRef.z);
}
}

stdRef.x = sqrtf(stdRef.x / 9.0f);
stdRef.y = sqrtf(stdRef.y / 9.0f);
stdRef.z = sqrtf(stdRef.z / 9.0f);

float3 sigmaMD;
sigmaMD.x = sqrtf(alpha * meanRef.x + beta);
sigmaMD.y = sqrtf(alpha * meanRef.y + beta) / sqrtf(2.0f); //we have two green pixels averaged --> devide by sqrtf(2);
sigmaMD.z = sqrtf(alpha * meanRef.z + beta);

dist.x = fabs(meanRef.x - meanMoved.x);
dist.y = fabs(meanRef.y - meanMoved.y);
dist.z = fabs(meanRef.z - meanMoved.z);

sigma.x = fmaxf(sigmaMD.x, stdRef.x);
sigma.y = fmaxf(sigmaMD.y, stdRef.y);
sigma.z = fmaxf(sigmaMD.z, stdRef.z);

dist.x = dist.x * (stdRef.x * stdRef.x / (stdRef.x * stdRef.x + sigmaMD.x * sigmaMD.x));
dist.y = dist.y * (stdRef.y * stdRef.y / (stdRef.y * stdRef.y + sigmaMD.y * sigmaMD.y));
dist.z = dist.z * (stdRef.z * stdRef.z / (stdRef.z * stdRef.z + sigmaMD.z * sigmaMD.z));/**/

float4 mask;
float s = 1.5f;
if (M > thresholdM)
s = 0;

const float t = 0.12f;
mask.x = fmaxf(fminf(s * exp(-dist.x * dist.x / (sigma.x * sigma.x)) - t, 1.0f), 0.0f);
mask.y = fmaxf(fminf(s * exp(-dist.y * dist.y / (sigma.y * sigma.y)) - t, 1.0f), 0.0f);
mask.z = fmaxf(fminf(s * exp(-dist.z * dist.z / (sigma.z * sigma.z)) - t, 1.0f), 0.0f);
mask.w = M;

*(((float4*)((char*)robustnessMask + maskPitch * pxY)) + pxX) = mask;
}
	.file	"tmpxft_0023b489_00000000-6_ComputeRobustnessMask.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2010:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2010:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z67__device_stub__Z21ComputeRobustnessMaskPK6float3S1_P6float4yiiiifffPK6float3S1_P6float4yiiiifff
	.type	_Z67__device_stub__Z21ComputeRobustnessMaskPK6float3S1_P6float4yiiiifffPK6float3S1_P6float4yiiiifff, @function
_Z67__device_stub__Z21ComputeRobustnessMaskPK6float3S1_P6float4yiiiifffPK6float3S1_P6float4yiiiifff:
.LFB2032:
	.cfi_startproc
	endbr64
	subq	$232, %rsp
	.cfi_def_cfa_offset 240
	movq	%rcx, 24(%rsp)
	leaq	72(%rsp), %rcx
	movl	%r8d, 20(%rsp)
	movl	%r9d, 16(%rsp)
	movss	%xmm0, 12(%rsp)
	movss	%xmm1, 8(%rsp)
	movss	%xmm2, 4(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 216(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movq	%rdi, 40(%rsp)
	leaq	80(%rsp), %rdi
	movq	%rax, 128(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	56(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	240(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	248(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	4(%rsp), %rax
	movq	%rsi, 48(%rsp)
	leaq	92(%rsp), %rsi
	movq	%rdx, 56(%rsp)
	leaq	64(%rsp), %rdx
	movq	%rax, 208(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 80(%rsp)
	movl	$1, 88(%rsp)
	movq	%rax, 92(%rsp)
	movl	$1, 100(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	72(%rsp)
	.cfi_def_cfa_offset 248
	leaq	_Z21ComputeRobustnessMaskPK6float3S1_P6float4yiiiifff(%rip), %rdi
	pushq	72(%rsp)
	.cfi_def_cfa_offset 256
	movq	108(%rsp), %rcx
	movl	116(%rsp), %r8d
	movq	96(%rsp), %rsi
	movl	104(%rsp), %edx
	leaq	144(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 248
	popq	%rdx
	.cfi_def_cfa_offset 240
.L2:
	movq	216(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$232, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2032:
	.size	_Z67__device_stub__Z21ComputeRobustnessMaskPK6float3S1_P6float4yiiiifffPK6float3S1_P6float4yiiiifff, .-_Z67__device_stub__Z21ComputeRobustnessMaskPK6float3S1_P6float4yiiiifffPK6float3S1_P6float4yiiiifff
	.globl	_Z21ComputeRobustnessMaskPK6float3S1_P6float4yiiiifff
	.type	_Z21ComputeRobustnessMaskPK6float3S1_P6float4yiiiifff, @function
_Z21ComputeRobustnessMaskPK6float3S1_P6float4yiiiifff:
.LFB2033:
	.cfi_startproc
	endbr64
	jmp	_Z67__device_stub__Z21ComputeRobustnessMaskPK6float3S1_P6float4yiiiifffPK6float3S1_P6float4yiiiifff
	.cfi_endproc
.LFE2033:
	.size	_Z21ComputeRobustnessMaskPK6float3S1_P6float4yiiiifff, .-_Z21ComputeRobustnessMaskPK6float3S1_P6float4yiiiifff
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z21ComputeRobustnessMaskPK6float3S1_P6float4yiiiifff"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2035:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z21ComputeRobustnessMaskPK6float3S1_P6float4yiiiifff(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2035:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void ComputeRobustnessMask( const float3* __restrict__ rawImgRef, const float3* __restrict__ rawImgMoved, float4* __restrict__ robustnessMask, hipTextureObject_t texUV, int imgWidth, int imgHeight, int imgPitch, int maskPitch, float alpha, float beta, float thresholdM)
{
int pxX = blockIdx.x * blockDim.x + threadIdx.x;
int pxY = blockIdx.y * blockDim.y + threadIdx.y;

extern __shared__ float3 pixelsRef[];
int sharedOffset = 3 * 3 * (threadIdx.y * blockDim.x + threadIdx.x);

if (pxX >= imgWidth - 1|| pxY >= imgHeight - 1 || pxX < 1 || pxY < 1)
return;

float3 meanRef = make_float3(0, 0, 0);
float3 meanMoved = make_float3(0, 0, 0);
float3 stdRef = make_float3(0, 0, 0);
float3 stdMoved = make_float3(0, 0, 0);
float3 dist = make_float3(0, 0, 0);
float3 sigma = make_float3(0, 0, 0);

float2 shiftf = tex2D<float2>(texUV, ((float)pxX + 0.5f) / (float)imgWidth, ((float)pxY + 0.5f) / (float)imgHeight);
float2 maxShift = shiftf;
float2 minShift = shiftf;

for (int y = -2; y <= 2; y++)
{
for (int x = -2; x <= 2; x++)
{
float2 s = tex2D<float2>(texUV, ((float)pxX + x + 0.5f) / (float)imgWidth, ((float)pxY + y + 0.5f) / (float)imgHeight);
maxShift.x = fmaxf(s.x, shiftf.x);
maxShift.y = fmaxf(s.y, shiftf.y);
minShift.x = fminf(s.x, shiftf.x);
minShift.y = fminf(s.y, shiftf.y);
}
}

int2 shift;
//half resolution image:
shift.x = roundf(shiftf.x * 0.5f);
shift.y = roundf(shiftf.y * 0.5f);

for (int y = -1; y <= 1; y++)
{
for (int x = -1; x <= 1; x++)
{
float3 p = *(((float3*)((char*)rawImgRef + imgPitch * (pxY + y))) + pxX + x);
pixelsRef[sharedOffset + (y + 1) * 3 + (x + 1)] = p;

meanRef.x += p.x;
meanRef.y += p.y;
meanRef.z += p.z;

int ppy = min(max(pxY + shift.y + y, 0), imgHeight - 1);
int ppx = min(max(pxX + shift.x + x, 0), imgWidth - 1);
p = *(((float3*)((char*)rawImgMoved + imgPitch * (ppy))) + ppx);
meanMoved.x += p.x;
meanMoved.y += p.y;
meanMoved.z += p.z;
}
}
meanRef.x /= 9.0f;
meanRef.y /= 9.0f;
meanRef.z /= 9.0f;
meanMoved.x /= 9.0f;
meanMoved.y /= 9.0f;
meanMoved.z /= 9.0f;

float meandist = fabs(meanRef.x - meanMoved.x) + fabs(meanRef.y - meanMoved.y) + fabs(meanRef.z - meanMoved.z);
meandist /= 3.0f;
maxShift.x *= 0.5f * meandist;
maxShift.y *= 0.5f * meandist;
minShift.x *= 0.5f * meandist;
minShift.y *= 0.5f * meandist;

float M = sqrtf((maxShift.x - minShift.x) * (maxShift.x - minShift.x) + (maxShift.y - minShift.y) * (maxShift.y - minShift.y));

for (int y = -1; y <= 1; y++)
{
for (int x = -1; x <= 1; x++)
{
int p = sharedOffset + (y + 1) * 3 + (x + 1);
stdRef.x += (pixelsRef[p].x - meanRef.x) * (pixelsRef[p].x - meanRef.x);
stdRef.y += (pixelsRef[p].y - meanRef.y) * (pixelsRef[p].y - meanRef.y);
stdRef.z += (pixelsRef[p].z - meanRef.z) * (pixelsRef[p].z - meanRef.z);
}
}

stdRef.x = sqrtf(stdRef.x / 9.0f);
stdRef.y = sqrtf(stdRef.y / 9.0f);
stdRef.z = sqrtf(stdRef.z / 9.0f);

float3 sigmaMD;
sigmaMD.x = sqrtf(alpha * meanRef.x + beta);
sigmaMD.y = sqrtf(alpha * meanRef.y + beta) / sqrtf(2.0f); //we have two green pixels averaged --> devide by sqrtf(2);
sigmaMD.z = sqrtf(alpha * meanRef.z + beta);

dist.x = fabs(meanRef.x - meanMoved.x);
dist.y = fabs(meanRef.y - meanMoved.y);
dist.z = fabs(meanRef.z - meanMoved.z);

sigma.x = fmaxf(sigmaMD.x, stdRef.x);
sigma.y = fmaxf(sigmaMD.y, stdRef.y);
sigma.z = fmaxf(sigmaMD.z, stdRef.z);

dist.x = dist.x * (stdRef.x * stdRef.x / (stdRef.x * stdRef.x + sigmaMD.x * sigmaMD.x));
dist.y = dist.y * (stdRef.y * stdRef.y / (stdRef.y * stdRef.y + sigmaMD.y * sigmaMD.y));
dist.z = dist.z * (stdRef.z * stdRef.z / (stdRef.z * stdRef.z + sigmaMD.z * sigmaMD.z));/**/

float4 mask;
float s = 1.5f;
if (M > thresholdM)
s = 0;

const float t = 0.12f;
mask.x = fmaxf(fminf(s * exp(-dist.x * dist.x / (sigma.x * sigma.x)) - t, 1.0f), 0.0f);
mask.y = fmaxf(fminf(s * exp(-dist.y * dist.y / (sigma.y * sigma.y)) - t, 1.0f), 0.0f);
mask.z = fmaxf(fminf(s * exp(-dist.z * dist.z / (sigma.z * sigma.z)) - t, 1.0f), 0.0f);
mask.w = M;

*(((float4*)((char*)robustnessMask + maskPitch * pxY)) + pxX) = mask;
}
	.text
	.file	"ComputeRobustnessMask.hip"
	.globl	_Z36__device_stub__ComputeRobustnessMaskPK15HIP_vector_typeIfLj3EES2_PS_IfLj4EEP13__hip_textureiiiifff # -- Begin function _Z36__device_stub__ComputeRobustnessMaskPK15HIP_vector_typeIfLj3EES2_PS_IfLj4EEP13__hip_textureiiiifff
	.type	_Z36__device_stub__ComputeRobustnessMaskPK15HIP_vector_typeIfLj3EES2_PS_IfLj4EEP13__hip_textureiiiifff,@function
_Z36__device_stub__ComputeRobustnessMaskPK15HIP_vector_typeIfLj3EES2_PS_IfLj4EEP13__hip_textureiiiifff: # @_Z36__device_stub__ComputeRobustnessMaskPK15HIP_vector_typeIfLj3EES2_PS_IfLj4EEP13__hip_textureiiiifff
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$208, %rsp
	.cfi_def_cfa_offset 256
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	72(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	64(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	56(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	48(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	28(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	24(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	20(%rsp), %r9
	movss	%xmm0, (%r9)
	leaq	16(%rsp), %r10
	movss	%xmm1, (%r10)
	leaq	12(%rsp), %r11
	movss	%xmm2, (%r11)
	leaq	112(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	256(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	264(%rsp), %rax
	movq	%rax, 56(%rbx)
	movq	%r9, 64(%rbx)
	movq	%r10, 72(%rbx)
	movq	%r11, 80(%rbx)
	leaq	96(%rsp), %r14
	leaq	80(%rsp), %r15
	leaq	40(%rsp), %r12
	leaq	32(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z21ComputeRobustnessMaskPK15HIP_vector_typeIfLj3EES2_PS_IfLj4EEP13__hip_textureiiiifff, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$224, %rsp
	.cfi_adjust_cfa_offset -224
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z36__device_stub__ComputeRobustnessMaskPK15HIP_vector_typeIfLj3EES2_PS_IfLj4EEP13__hip_textureiiiifff, .Lfunc_end0-_Z36__device_stub__ComputeRobustnessMaskPK15HIP_vector_typeIfLj3EES2_PS_IfLj4EEP13__hip_textureiiiifff
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z21ComputeRobustnessMaskPK15HIP_vector_typeIfLj3EES2_PS_IfLj4EEP13__hip_textureiiiifff, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z21ComputeRobustnessMaskPK15HIP_vector_typeIfLj3EES2_PS_IfLj4EEP13__hip_textureiiiifff,@object # @_Z21ComputeRobustnessMaskPK15HIP_vector_typeIfLj3EES2_PS_IfLj4EEP13__hip_textureiiiifff
	.section	.rodata,"a",@progbits
	.globl	_Z21ComputeRobustnessMaskPK15HIP_vector_typeIfLj3EES2_PS_IfLj4EEP13__hip_textureiiiifff
	.p2align	3, 0x0
_Z21ComputeRobustnessMaskPK15HIP_vector_typeIfLj3EES2_PS_IfLj4EEP13__hip_textureiiiifff:
	.quad	_Z36__device_stub__ComputeRobustnessMaskPK15HIP_vector_typeIfLj3EES2_PS_IfLj4EEP13__hip_textureiiiifff
	.size	_Z21ComputeRobustnessMaskPK15HIP_vector_typeIfLj3EES2_PS_IfLj4EEP13__hip_textureiiiifff, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z21ComputeRobustnessMaskPK15HIP_vector_typeIfLj3EES2_PS_IfLj4EEP13__hip_textureiiiifff"
	.size	.L__unnamed_1, 88

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z36__device_stub__ComputeRobustnessMaskPK15HIP_vector_typeIfLj3EES2_PS_IfLj4EEP13__hip_textureiiiifff
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z21ComputeRobustnessMaskPK15HIP_vector_typeIfLj3EES2_PS_IfLj4EEP13__hip_textureiiiifff
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z21ComputeRobustnessMaskPK15HIP_vector_typeIfLj3EES2_PS_IfLj4EEP13__hip_textureiiiifff ; -- Begin function _Z21ComputeRobustnessMaskPK15HIP_vector_typeIfLj3EES2_PS_IfLj4EEP13__hip_textureiiiifff
	.globl	_Z21ComputeRobustnessMaskPK15HIP_vector_typeIfLj3EES2_PS_IfLj4EEP13__hip_textureiiiifff
	.p2align	8
	.type	_Z21ComputeRobustnessMaskPK15HIP_vector_typeIfLj3EES2_PS_IfLj4EEP13__hip_textureiiiifff,@function
_Z21ComputeRobustnessMaskPK15HIP_vector_typeIfLj3EES2_PS_IfLj4EEP13__hip_textureiiiifff: ; @_Z21ComputeRobustnessMaskPK15HIP_vector_typeIfLj3EES2_PS_IfLj4EEP13__hip_textureiiiifff
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x4c
	s_load_b128 s[20:23], s[0:1], 0x20
	v_and_b32_e32 v8, 0x3ff, v0
	s_mov_b32 s4, exec_lo
	s_waitcnt lgkmcnt(0)
	s_and_b32 s34, s2, 0xffff
	s_add_i32 s3, s20, -1
	s_mul_i32 s33, s14, s34
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v1, s33, v8
	v_cmpx_gt_i32_e64 s3, v1
	s_cbranch_execz .LBB0_11
; %bb.1:
	v_bfe_u32 v0, v0, 10, 10
	s_lshr_b32 s2, s2, 16
	s_load_b128 s[24:27], s[0:1], 0x30
	s_waitcnt lgkmcnt(0)
	s_add_i32 s27, s21, -1
	v_mad_u64_u32 v[3:4], null, s15, s2, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_min_i32_e32 v2, v1, v3
	v_cmp_gt_i32_e32 vcc_lo, s27, v3
	v_cmp_lt_i32_e64 s2, 0, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, s2, vcc_lo
	s_and_b32 exec_lo, exec_lo, s2
	s_cbranch_execz .LBB0_11
; %bb.2:
	v_cvt_f32_i32_e32 v2, v1
	v_cvt_f32_i32_e32 v4, v3
	v_cvt_f32_i32_e32 v6, s20
	v_cvt_f32_i32_e32 v7, s21
	s_load_b256 s[4:11], s[0:1], 0x0
	v_add_f32_e32 v5, 0.5, v2
	v_dual_add_f32 v9, 0.5, v4 :: v_dual_add_f32 v2, 2.0, v2
	v_mul_u32_u24_e32 v0, s34, v0
	v_add_f32_e32 v4, 2.0, v4
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_div_scale_f32 v10, null, v6, v6, v5
	v_div_scale_f32 v11, null, v7, v7, v9
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_lo_u32 v0, 0x6c, v0
	v_rcp_f32_e32 v12, v10
	v_add_f32_e32 v2, 0.5, v2
	s_delay_alu instid0(VALU_DEP_3)
	v_rcp_f32_e32 v13, v11
	s_waitcnt lgkmcnt(0)
	s_clause 0x1
	s_load_b128 s[28:31], s[10:11], 0x30
	s_load_b32 s1, s[10:11], 0x28
	s_waitcnt_depctr 0xfff
	v_fma_f32 v14, -v10, v12, 1.0
	v_fma_f32 v15, -v11, v13, 1.0
	s_load_b256 s[12:19], s[10:11], 0x0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v12, v14, v12
	v_div_scale_f32 v16, vcc_lo, v5, v6, v5
	v_div_scale_f32 v14, s0, v9, v7, v9
	v_fmac_f32_e32 v13, v15, v13
	v_mul_f32_e32 v15, v16, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v17, v14, v13
	v_fma_f32 v18, -v10, v15, v16
	s_waitcnt lgkmcnt(0)
	s_bitcmp0_b32 s30, 20
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v19, -v11, v17, v14
	v_fmac_f32_e32 v15, v18, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v17, v19, v13
	v_fma_f32 v10, -v10, v15, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v11, -v11, v17, v14
	v_div_fmas_f32 v10, v10, v12, v15
	s_mov_b32 vcc_lo, s0
	s_cselect_b32 s0, -1, 0
	s_bitcmp0_b32 s28, 15
	v_div_fmas_f32 v11, v11, v13, v17
	s_cselect_b32 vcc_lo, -1, 0
	s_bfe_u32 s2, s14, 0xe000e
	v_cvt_f32_u32_e32 v13, s1
	s_add_i32 s2, s2, 1
	v_div_fixup_f32 v9, v11, v7, v9
	v_add_f32_e32 v11, 0.5, v4
	v_cvt_f32_u32_e32 v4, s2
	v_div_scale_f32 v14, null, v6, v6, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_cndmask_b32_e32 v16, 1.0, v4, vcc_lo
	v_div_fixup_f32 v4, v10, v6, v5
	v_cndmask_b32_e32 v10, 1.0, v13, vcc_lo
	v_rcp_f32_e32 v13, v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v17, v16
	v_mul_f32_e32 v18, v4, v10
	v_rcp_f32_e32 v19, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(TRANS32_DEP_3)
	v_floor_f32_e32 v18, v18
	v_fma_f32 v22, -v14, v13, 1.0
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v18, v19, v18
	v_div_scale_f32 v12, null, v7, v7, v11
	v_div_scale_f32 v21, vcc_lo, v11, v7, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v4, v4, v18, s0
	v_rcp_f32_e32 v15, v12
	s_waitcnt_depctr 0xfff
	v_fma_f32 v20, -v12, v15, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v15, v20, v15
	v_fmac_f32_e32 v13, v22, v13
	v_div_scale_f32 v20, s1, v2, v6, v2
	v_mul_f32_e32 v22, v21, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v18, -v12, v22, v21
	v_dual_mul_f32 v5, v9, v16 :: v_dual_fmac_f32 v22, v18, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_floor_f32_e32 v5, v5
	v_fma_f32 v12, -v12, v22, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v12, v12, v15, v22
	s_mov_b32 vcc_lo, s1
	v_div_fixup_f32 v7, v12, v7, v11
	v_mul_f32_e32 v5, v17, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v5, v9, v5, s0
	v_mul_f32_e32 v9, v20, v13
	image_sample_lz v[4:5], v[4:5], s[12:19], s[28:31] dmask:0x3 dim:SQ_RSRC_IMG_2D
	v_fma_f32 v23, -v14, v9, v20
	v_fmac_f32_e32 v9, v23, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v14, -v14, v9, v20
	v_div_fmas_f32 v9, v14, v13, v9
	v_add_nc_u32_e32 v14, -1, v3
	v_mul_u32_u24_e32 v13, 0x6c, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_div_fixup_f32 v2, v9, v6, v2
	v_mul_f32_e32 v6, v16, v7
	v_mul_lo_u32 v18, s22, v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v9, v10, v2
	v_floor_f32_e32 v6, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_floor_f32_e32 v9, v9
	v_dual_mul_f32 v6, v17, v6 :: v_dual_mul_f32 v9, v19, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v7, v7, v6, s0
	v_cndmask_b32_e64 v6, v2, v9, s0
	v_mov_b32_e32 v2, 0
	image_sample_lz v[6:7], v[6:7], s[12:19], s[28:31] dmask:0x3 dim:SQ_RSRC_IMG_2D
	v_mov_b32_e32 v14, v2
	v_mov_b32_e32 v15, v2
	s_waitcnt vmcnt(1)
	v_mul_f32_e32 v9, 0.5, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_trunc_f32_e32 v10, v9
	v_dual_mul_f32 v11, 0.5, v5 :: v_dual_sub_f32 v12, v9, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_trunc_f32_e32 v20, v11
	v_cmp_ge_f32_e64 s0, |v12|, 0.5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v16, v11, v20
	v_cndmask_b32_e64 v12, 0, 1.0, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_cmp_ge_f32_e64 s0, |v16|, 0.5
	v_add3_u32 v16, v0, v13, 0
	v_mov_b32_e32 v0, v2
	v_bfi_b32 v9, 0x7fffffff, v12, v9
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v12, 0, 1.0, s0
	s_mov_b32 s0, -1
	v_add_f32_e32 v19, v10, v9
	v_mad_u64_u32 v[9:10], null, v1, 12, s[4:5]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_bfi_b32 v11, 0x7fffffff, v12, v11
	v_mov_b32_e32 v12, v2
	v_cvt_i32_f32_e32 v13, v19
	v_mov_b32_e32 v19, v16
	v_mov_b32_e32 v17, v2
	v_add_f32_e32 v11, v20, v11
	v_add_co_u32 v20, vcc_lo, v9, -4
	v_add_nc_u32_e32 v8, v8, v13
	v_add_co_ci_u32_e32 v21, vcc_lo, -1, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cvt_i32_f32_e32 v22, v11
	v_mov_b32_e32 v13, v2
	v_add3_u32 v23, v8, s33, -1
.LBB0_3:                                ; %.preheader228
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_4 Depth 2
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add3_u32 v8, s0, v3, v22
	v_ashrrev_i32_e32 v9, 31, v18
	v_mov_b32_e32 v24, v23
	s_mov_b32 s1, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_maxmin_i32 v8, v8, 0, s27
	v_mul_lo_u32 v10, v8, s22
	v_add_co_u32 v8, vcc_lo, v20, v18
	v_add_co_ci_u32_e32 v9, vcc_lo, v21, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v11, 31, v10
	v_add_co_u32 v10, vcc_lo, s6, v10
	v_add_co_ci_u32_e32 v11, vcc_lo, s7, v11, vcc_lo
.LBB0_4:                                ;   Parent Loop BB0_3 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_maxmin_i32 v25, v24, 0, s3
	s_delay_alu instid0(VALU_DEP_1)
	v_mad_i64_i32 v[28:29], null, v25, 12, v[10:11]
	global_load_b96 v[25:27], v[8:9], off offset:-8
	global_load_b96 v[28:30], v[28:29], off
	v_add_co_u32 v8, vcc_lo, v8, 12
	v_add_nc_u32_e32 v31, s1, v19
	v_add_nc_u32_e32 v24, 1, v24
	v_add_co_ci_u32_e32 v9, vcc_lo, 0, v9, vcc_lo
	s_add_i32 s1, s1, 12
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s1, 36
	s_waitcnt vmcnt(1)
	v_dual_add_f32 v15, v15, v25 :: v_dual_add_f32 v14, v14, v26
	s_waitcnt vmcnt(0)
	v_dual_add_f32 v17, v17, v27 :: v_dual_add_f32 v12, v12, v29
	v_dual_add_f32 v13, v13, v28 :: v_dual_add_f32 v0, v0, v30
	ds_store_2addr_b32 v31, v25, v26 offset1:1
	ds_store_b32 v31, v27 offset:8
	s_cbranch_scc0 .LBB0_4
; %bb.5:                                ;   in Loop: Header=BB0_3 Depth=1
	v_add_nc_u32_e32 v19, 36, v19
	v_add_nc_u32_e32 v18, s22, v18
	s_add_i32 s0, s0, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s0, 2
	s_cbranch_scc0 .LBB0_3
; %bb.6:
	v_div_scale_f32 v8, null, 0x41100000, 0x41100000, v15
	v_div_scale_f32 v9, null, 0x41100000, 0x41100000, v14
	v_div_scale_f32 v10, null, 0x41100000, 0x41100000, v17
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rcp_f32_e32 v11, v8
	v_rcp_f32_e32 v18, v9
	v_div_scale_f32 v20, vcc_lo, v15, 0x41100000, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(TRANS32_DEP_3)
	v_rcp_f32_e32 v19, v10
	v_div_scale_f32 v21, s0, v14, 0x41100000, v14
	v_div_scale_f32 v25, s1, v17, 0x41100000, v17
	v_fma_f32 v22, -v8, v11, 1.0
	s_waitcnt_depctr 0xfff
	v_fma_f32 v23, -v9, v18, 1.0
	v_fma_f32 v24, -v10, v19, 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_fmac_f32 v11, v22, v11 :: v_dual_fmac_f32 v18, v23, v18
	v_fmac_f32_e32 v19, v24, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v22, v20, v11 :: v_dual_mul_f32 v23, v21, v18
	v_fma_f32 v26, -v8, v22, v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v27, -v9, v23, v21
	v_dual_fmac_f32 v22, v26, v11 :: v_dual_fmac_f32 v23, v27, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v8, -v8, v22, v20
	v_fma_f32 v9, -v9, v23, v21
	s_delay_alu instid0(VALU_DEP_2)
	v_div_fmas_f32 v11, v8, v11, v22
	v_mov_b32_e32 v8, 0
	v_mul_f32_e32 v24, v25, v19
	s_mov_b32 vcc_lo, s0
	s_mov_b32 s0, -1
	v_div_fixup_f32 v15, v11, 0x41100000, v15
	v_div_fmas_f32 v18, v9, v18, v23
	v_fma_f32 v28, -v10, v24, v25
	s_mov_b32 vcc_lo, s1
	v_mov_b32_e32 v9, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_div_fixup_f32 v14, v18, 0x41100000, v14
	v_fmac_f32_e32 v24, v28, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v10, -v10, v24, v25
	v_div_fmas_f32 v10, v10, v19, v24
	s_delay_alu instid0(VALU_DEP_1)
	v_div_fixup_f32 v11, v10, 0x41100000, v17
	v_mov_b32_e32 v10, 0
.LBB0_7:                                ; %.preheader
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_8 Depth 2
	s_mov_b32 s1, 0
.LBB0_8:                                ;   Parent Loop BB0_7 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	v_add_nc_u32_e32 v19, s1, v16
	s_add_i32 s1, s1, 12
	ds_load_2addr_b32 v[17:18], v19 offset1:1
	ds_load_b32 v19, v19 offset:8
	s_cmp_eq_u32 s1, 36
	s_waitcnt lgkmcnt(1)
	v_dual_sub_f32 v18, v18, v14 :: v_dual_sub_f32 v17, v17, v15
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v19, v19, v11 :: v_dual_fmac_f32 v10, v17, v17
	v_dual_fmac_f32 v9, v18, v18 :: v_dual_fmac_f32 v8, v19, v19
	s_cbranch_scc0 .LBB0_8
; %bb.9:                                ;   in Loop: Header=BB0_7 Depth=1
	v_add_nc_u32_e32 v16, 36, v16
	s_add_i32 s0, s0, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s0, 2
	s_cbranch_scc0 .LBB0_7
; %bb.10:
	v_div_scale_f32 v16, null, 0x41100000, 0x41100000, v13
	v_div_scale_f32 v17, null, 0x41100000, 0x41100000, v12
	v_div_scale_f32 v18, null, 0x41100000, 0x41100000, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rcp_f32_e32 v19, v16
	v_rcp_f32_e32 v20, v17
	v_div_scale_f32 v22, vcc_lo, v13, 0x41100000, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(TRANS32_DEP_3)
	v_rcp_f32_e32 v21, v18
	v_div_scale_f32 v23, s0, v12, 0x41100000, v12
	v_div_scale_f32 v27, s1, v0, 0x41100000, v0
	v_div_scale_f32 v28, null, 0x41100000, 0x41100000, v10
	v_fma_f32 v24, -v16, v19, 1.0
	s_delay_alu instid0(TRANS32_DEP_2) | instskip(SKIP_1) | instid1(TRANS32_DEP_1)
	v_fma_f32 v25, -v17, v20, 1.0
	v_div_scale_f32 v32, s2, v10, 0x41100000, v10
	v_fma_f32 v26, -v18, v21, 1.0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_fmac_f32 v19, v24, v19 :: v_dual_fmac_f32 v20, v25, v20
	v_dual_max_f32 v4, v4, v4 :: v_dual_max_f32 v7, v7, v7
	v_dual_max_f32 v5, v5, v5 :: v_dual_mul_f32 v24, v22, v19
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_mul_f32 v25, v23, v20 :: v_dual_max_f32 v6, v6, v6
	v_fma_f32 v29, -v16, v24, v22
	v_fmac_f32_e32 v21, v26, v21
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v30, -v17, v25, v23
	v_fmac_f32_e32 v24, v29, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_mul_f32 v26, v27, v21 :: v_dual_fmac_f32 v25, v30, v20
	v_div_scale_f32 v29, null, 0x41100000, 0x41100000, v9
	v_fma_f32 v16, -v16, v24, v22
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f32 v31, -v18, v26, v27
	v_fma_f32 v17, -v17, v25, v23
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_fmas_f32 v16, v16, v19, v24
	s_mov_b32 vcc_lo, s0
	v_div_fmas_f32 v17, v17, v20, v25
	s_mov_b32 vcc_lo, s1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_div_fixup_f32 v13, v16, 0x41100000, v13
	v_rcp_f32_e32 v20, v28
	v_div_scale_f32 v16, s0, v9, 0x41100000, v9
	v_div_fixup_f32 v12, v17, 0x41100000, v12
	v_sub_f32_e32 v13, v15, v13
	v_fma_f32 v15, v15, s24, s25
	v_fmac_f32_e32 v26, v31, v21
	v_div_scale_f32 v17, null, 0x41100000, 0x41100000, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_sub_f32 v12, v14, v12 :: v_dual_mul_f32 v23, 0x4f800000, v15
	v_fma_f32 v18, -v18, v26, v27
	v_fma_f32 v14, v14, s24, s25
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_rcp_f32_e32 v22, v17
	v_add_f32_e64 v19, |v13|, |v12|
	v_cmp_gt_f32_e64 s3, 0xf800000, v15
	v_div_fmas_f32 v18, v18, v21, v26
	v_mul_f32_e32 v25, 0x4f800000, v14
	v_cmp_gt_f32_e64 s4, 0xf800000, v14
	v_rcp_f32_e32 v21, v29
	v_cndmask_b32_e64 v15, v15, v23, s3
	v_div_fixup_f32 v0, v18, 0x41100000, v0
	v_div_scale_f32 v18, s1, v8, 0x41100000, v8
	v_cndmask_b32_e64 v14, v14, v25, s4
	v_fma_f32 v25, -v28, v20, 1.0
	s_delay_alu instid0(VALU_DEP_4)
	v_sub_f32_e32 v0, v11, v0
	v_fma_f32 v11, v11, s24, s25
	v_fma_f32 v27, -v17, v22, 1.0
	v_sqrt_f32_e32 v31, v14
	v_fmac_f32_e32 v20, v25, v20
	v_add_f32_e64 v19, v19, |v0|
	v_mul_f32_e32 v26, 0x4f800000, v11
	v_cmp_gt_f32_e64 s5, 0xf800000, v11
	v_sqrt_f32_e32 v30, v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_scale_f32 v24, null, 0x40400000, 0x40400000, v19
	v_rcp_f32_e32 v23, v24
	s_waitcnt_depctr 0xfff
	v_add_nc_u32_e32 v36, -1, v30
	v_fma_f32 v25, -v24, v23, 1.0
	v_dual_fmac_f32 v22, v27, v22 :: v_dual_mul_f32 v27, v32, v20
	v_cndmask_b32_e64 v11, v11, v26, s5
	v_fma_f32 v26, -v29, v21, 1.0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_fmac_f32 v23, v25, v23 :: v_dual_mul_f32 v34, v18, v22
	v_fma_f32 v39, -v28, v27, v32
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sqrt_f32_e32 v25, v11
	v_fmac_f32_e32 v21, v26, v21
	v_div_scale_f32 v26, vcc_lo, v19, 0x40400000, v19
	v_fma_f32 v42, -v17, v34, v18
	v_add_nc_u32_e32 v37, -1, v31
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mul_f32_e32 v33, v16, v21
	v_mul_f32_e32 v35, v26, v23
	v_dual_fmac_f32 v27, v39, v20 :: v_dual_add_nc_u32 v38, 1, v31
	v_fmac_f32_e32 v34, v42, v22
	v_fma_f32 v43, -v37, v31, v14
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
	v_fma_f32 v40, -v24, v35, v26
	v_fma_f32 v41, -v29, v33, v16
	v_fma_f32 v44, -v38, v31, v14
	v_fma_f32 v17, -v17, v34, v18
	v_cmp_ge_f32_e64 s6, 0, v43
	v_fmac_f32_e32 v33, v41, v21
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v31, v31, v37, s6
	v_fmac_f32_e32 v35, v40, v23
	v_fma_f32 v16, -v29, v33, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v24, -v24, v35, v26
	v_fma_f32 v26, -v28, v27, v32
	v_div_fmas_f32 v23, v24, v23, v35
	s_mov_b32 vcc_lo, s2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_fmas_f32 v20, v26, v20, v27
	s_mov_b32 vcc_lo, s0
	v_div_fixup_f32 v19, v23, 0x40400000, v19
	v_div_fmas_f32 v16, v16, v21, v33
	v_cmp_lt_f32_e32 vcc_lo, 0, v44
	v_div_fixup_f32 v10, v20, 0x41100000, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_div_fixup_f32 v9, v16, 0x41100000, v9
	v_cndmask_b32_e32 v20, v31, v38, vcc_lo
	s_mov_b32 vcc_lo, s1
	v_mul_f32_e32 v21, 0x4f800000, v10
	v_div_fmas_f32 v17, v17, v22, v34
	v_mul_f32_e32 v24, 0x4f800000, v9
	v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v9
	v_cmp_gt_f32_e64 s0, 0xf800000, v10
	v_cmp_class_f32_e64 s1, v14, 0x260
	v_div_fixup_f32 v8, v17, 0x41100000, v8
	v_dual_cndmask_b32 v9, v9, v24 :: v_dual_add_nc_u32 v16, 1, v30
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v10, v10, v21, s0
	v_mul_f32_e32 v21, 0x4f800000, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f32 v24, -v16, v30, v15
	v_sqrt_f32_e32 v17, v9
	s_waitcnt_depctr 0xfff
	v_dual_mul_f32 v18, 0x37800000, v20 :: v_dual_add_nc_u32 v27, -1, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v18, v20, v18, s4
	v_sqrt_f32_e32 v20, v10
	v_add_nc_u32_e32 v32, 1, v17
	v_fma_f32 v33, -v27, v17, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v14, v18, v14, s1
	v_cmp_gt_f32_e64 s1, 0xf800000, v8
	v_fma_f32 v18, -v36, v30, v15
	v_div_scale_f32 v22, null, 0x3fb504f3, 0x3fb504f3, v14
	s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v26, -1, v20
	v_cndmask_b32_e64 v8, v8, v21, s1
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_rcp_f32_e32 v21, v22
	v_add_nc_u32_e32 v28, 1, v20
	v_fma_f32 v29, -v26, v20, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sqrt_f32_e32 v31, v8
	v_fma_f32 v34, -v28, v20, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_ge_f32_e64 s2, 0, v29
	v_cndmask_b32_e64 v20, v20, v26, s2
	v_cmp_ge_f32_e64 s2, 0, v33
	v_fma_f32 v26, -v32, v17, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v17, v17, v27, s2
	v_cmp_lt_f32_e64 s2, 0, v34
	v_cndmask_b32_e64 v20, v20, v28, s2
	v_cmp_ge_f32_e64 s2, 0, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v27, 0x37800000, v20
	v_cndmask_b32_e64 v18, v30, v36, s2
	v_cmp_lt_f32_e64 s2, 0, v26
	v_fma_f32 v26, -v22, v21, 1.0
	v_add_nc_u32_e32 v30, -1, v31
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v17, v17, v32, s2
	v_dual_fmac_f32 v21, v26, v21 :: v_dual_add_nc_u32 v26, 1, v31
	v_cndmask_b32_e64 v20, v20, v27, s0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f32 v27, -v30, v31, v8
	v_mul_f32_e32 v29, 0x37800000, v17
	v_div_scale_f32 v28, s2, v14, 0x3fb504f3, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_cndmask_b32_e32 v17, v17, v29, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v10, 0x260
	v_dual_cndmask_b32 v10, v20, v10 :: v_dual_add_nc_u32 v29, -1, v25
	v_cmp_class_f32_e64 vcc_lo, v9, 0x260
	v_cndmask_b32_e32 v9, v17, v9, vcc_lo
	v_cmp_lt_f32_e32 vcc_lo, 0, v24
	v_cndmask_b32_e32 v16, v18, v16, vcc_lo
	v_fma_f32 v18, -v26, v31, v8
	v_cmp_ge_f32_e32 vcc_lo, 0, v27
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_dual_mul_f32 v17, v28, v21 :: v_dual_mul_f32 v24, 0x37800000, v16
	v_cndmask_b32_e32 v20, v31, v30, vcc_lo
	v_cmp_lt_f32_e32 vcc_lo, 0, v18
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f32 v27, -v22, v17, v28
	v_cndmask_b32_e64 v16, v16, v24, s3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_dual_cndmask_b32 v18, v20, v26 :: v_dual_fmac_f32 v17, v27, v21
	v_fma_f32 v20, -v29, v25, v11
	v_cmp_class_f32_e64 vcc_lo, v15, 0x260
	v_dual_cndmask_b32 v15, v16, v15 :: v_dual_add_nc_u32 v24, 1, v25
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cmp_ge_f32_e32 vcc_lo, 0, v20
	v_fma_f32 v16, -v22, v17, v28
	v_fma_f32 v22, -v24, v25, v11
	v_dual_cndmask_b32 v20, v25, v29 :: v_dual_mul_f32 v25, v10, v10
	s_mov_b32 vcc_lo, s2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_div_fmas_f32 v16, v16, v21, v17
	v_cmp_lt_f32_e32 vcc_lo, 0, v22
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_fma_f32 v21, v15, v15, v25
	v_mul_f32_e32 v17, 0x37800000, v18
	v_div_fixup_f32 v14, v16, 0x3fb504f3, v14
	v_cndmask_b32_e32 v20, v20, v24, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_div_scale_f32 v16, null, v21, v21, v25
	v_cndmask_b32_e64 v17, v18, v17, s1
	v_cmp_class_f32_e64 vcc_lo, v8, 0x260
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mul_f32_e32 v24, 0x37800000, v20
	v_rcp_f32_e32 v18, v16
	s_delay_alu instid0(VALU_DEP_1)
	v_cndmask_b32_e64 v20, v20, v24, s5
	s_waitcnt_depctr 0xfff
	v_fma_f32 v24, -v16, v18, 1.0
	v_max_f32_e32 v29, v6, v4
	v_min_f32_e32 v4, v6, v4
	v_max_f32_e32 v6, v7, v5
	s_delay_alu instid0(VALU_DEP_4)
	v_dual_min_f32 v5, v7, v5 :: v_dual_fmac_f32 v18, v24, v18
	v_cndmask_b32_e32 v8, v17, v8, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v11, 0x260
	v_dual_mul_f32 v22, v9, v9 :: v_dual_mul_f32 v7, 0.5, v19
	v_max_f32_e32 v9, v14, v9
	v_cndmask_b32_e32 v11, v20, v11, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_fma_f32 v26, v14, v14, v22
	v_div_scale_f32 v30, vcc_lo, v25, v21, v25
	v_mul_f32_e32 v5, v5, v7
	v_mul_f32_e32 v4, v4, v7
	v_div_scale_f32 v17, null, v26, v26, v22
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mul_f32_e32 v33, v30, v18
	v_fma_f32 v5, v6, v7, -v5
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f32 v4, v29, v7, -v4
	v_rcp_f32_e32 v27, v17
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v23, -v16, v33, v30
	v_mul_f32_e32 v5, v5, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v33, v23, v18
	v_dual_fmac_f32 v5, v4, v4 :: v_dual_max_f32 v10, v15, v10
	s_waitcnt_depctr 0xfff
	v_fma_f32 v31, -v17, v27, 1.0
	v_mul_f32_e32 v20, v8, v8
	v_fma_f32 v16, -v16, v33, v30
	v_max_f32_e32 v8, v11, v8
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_mul_f32 v10, v10, v10 :: v_dual_fmac_f32 v27, v31, v27
	v_fma_f32 v28, v11, v11, v20
	v_div_scale_f32 v31, s0, v22, v26, v22
	v_div_fmas_f32 v16, v16, v18, v33
	s_mov_b32 vcc_lo, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_div_scale_f32 v24, null, v28, v28, v20
	v_mul_f32_e32 v34, v31, v27
	v_div_scale_f32 v23, s1, v20, v28, v20
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_rcp_f32_e32 v32, v24
	v_div_fixup_f32 v16, v16, v21, v25
	v_fma_f32 v19, -v17, v34, v31
	v_cmp_gt_f32_e64 s0, 0xf800000, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v34, v19, v27
	s_waitcnt_depctr 0xfff
	v_fma_f32 v35, -v24, v32, 1.0
	v_fma_f32 v6, -v17, v34, v31
	v_fmac_f32_e32 v32, v35, v32
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_fmas_f32 v6, v6, v27, v34
	s_mov_b32 vcc_lo, s1
	v_mul_f32_e32 v19, v23, v32
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fixup_f32 v6, v6, v26, v22
	v_fma_f32 v7, -v24, v19, v23
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e64 v6, |v12|, v6
	v_fmac_f32_e32 v19, v7, v32
	v_mul_f32_e64 v7, |v13|, v16
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_mul_f32_e64 v4, v6, -v6
	v_mul_f32_e32 v6, v9, v9
	v_fma_f32 v13, -v24, v19, v23
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f32_e64 v7, v7, -v7
	v_div_scale_f32 v11, null, v6, v6, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_div_fmas_f32 v13, v13, v32, v19
	v_div_scale_f32 v12, null, v10, v10, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rcp_f32_e32 v14, v11
	v_div_fixup_f32 v13, v13, v28, v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v9, v12
	v_mul_f32_e64 v0, |v0|, v13
	v_mul_f32_e32 v13, 0x4f800000, v5
	s_waitcnt_depctr 0xfff
	v_fma_f32 v17, -v11, v14, 1.0
	v_mul_f32_e64 v0, v0, -v0
	v_fma_f32 v15, -v12, v9, 1.0
	v_mul_f32_e32 v8, v8, v8
	v_cndmask_b32_e64 v5, v5, v13, s0
	v_div_scale_f32 v13, vcc_lo, v7, v10, v7
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v9, v15, v9
	v_div_scale_f32 v16, null, v8, v8, v0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sqrt_f32_e32 v19, v5
	v_mul_f32_e32 v18, v13, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
	v_rcp_f32_e32 v15, v16
	s_waitcnt_depctr 0xfff
	v_add_nc_u32_e32 v23, -1, v19
	v_fma_f32 v20, -v12, v18, v13
	v_fma_f32 v21, -v16, v15, 1.0
	v_fmac_f32_e32 v18, v20, v9
	v_div_scale_f32 v20, s2, v0, v8, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v15, v21, v15
	v_fmac_f32_e32 v14, v17, v14
	v_div_scale_f32 v17, s1, v4, v6, v4
	v_fma_f32 v12, -v12, v18, v13
	v_mul_f32_e32 v13, v20, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fmas_f32 v9, v12, v9, v18
	v_fma_f32 v12, -v16, v13, v20
	v_mul_f32_e32 v22, v17, v14
	v_fma_f32 v18, -v23, v19, v5
	s_mov_b32 vcc_lo, s1
	v_div_fixup_f32 v7, v9, v10, v7
	v_fmac_f32_e32 v13, v12, v15
	v_fma_f32 v21, -v11, v22, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v12, -v16, v13, v20
	v_fmac_f32_e32 v22, v21, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v11, -v11, v22, v17
	v_div_fmas_f32 v9, v11, v14, v22
	v_cmp_ge_f32_e32 vcc_lo, 0, v18
	v_add_nc_u32_e32 v11, 1, v19
	v_mul_f32_e32 v14, 0x3fb8aa3b, v7
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_div_fixup_f32 v4, v9, v6, v4
	v_cndmask_b32_e32 v10, v19, v23, vcc_lo
	s_mov_b32 vcc_lo, s2
	v_fma_f32 v9, 0x3fb8aa3b, v7, -v14
	v_div_fmas_f32 v6, v12, v15, v13
	v_rndne_f32_e32 v12, v14
	v_mul_f32_e32 v13, 0x3fb8aa3b, v4
	v_fma_f32 v15, -v11, v19, v5
	v_fmac_f32_e32 v9, 0x32a5705f, v7
	v_div_fixup_f32 v0, v6, v8, v0
	v_sub_f32_e32 v6, v14, v12
	v_rndne_f32_e32 v14, v13
	v_cmp_lt_f32_e32 vcc_lo, 0, v15
	v_fma_f32 v8, 0x3fb8aa3b, v4, -v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_add_f32 v6, v6, v9 :: v_dual_sub_f32 v9, v13, v14
	v_cndmask_b32_e32 v10, v10, v11, vcc_lo
	v_fmac_f32_e32 v8, 0x32a5705f, v4
	v_cmp_class_f32_e64 vcc_lo, v5, 0x260
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v15, 0x37800000, v10
	v_exp_f32_e32 v17, v6
	v_add_f32_e32 v6, v9, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v9, v10, v15, s0
	v_cvt_i32_f32_e32 v10, v12
	v_exp_f32_e32 v12, v6
	s_delay_alu instid0(VALU_DEP_2)
	v_cndmask_b32_e32 v6, v9, v5, vcc_lo
	v_cvt_i32_f32_e32 v5, v14
	s_delay_alu instid0(TRANS32_DEP_2) | instid1(VALU_DEP_3)
	v_ldexp_f32 v9, v17, v10
	s_delay_alu instid0(VALU_DEP_3)
	v_cmp_lt_f32_e32 vcc_lo, s26, v6
	s_waitcnt_depctr 0xfff
	v_ldexp_f32 v5, v12, v5
	v_cndmask_b32_e64 v10, 0x3fc00000, 0, vcc_lo
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v7
	v_cndmask_b32_e32 v9, 0, v9, vcc_lo
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v4
	v_dual_mul_f32 v16, 0x3fb8aa3b, v0 :: v_dual_cndmask_b32 v5, 0, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_fma_f32 v11, 0x3fb8aa3b, v0, -v16
	v_rndne_f32_e32 v13, v16
	v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v7
	v_fmac_f32_e32 v11, 0x32a5705f, v0
	v_cndmask_b32_e32 v7, 0x7f800000, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v8, v16, v13
	v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v4
	v_fmaak_f32 v7, v10, v7, 0xbdf5c28f
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_add_f32_e32 v8, v8, v11
	v_cvt_i32_f32_e32 v11, v13
	v_cndmask_b32_e32 v4, 0x7f800000, v5, vcc_lo
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v0
	v_exp_f32_e32 v8, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmaak_f32 v4, v10, v4, 0xbdf5c28f
	v_minmax_f32 v4, v4, 1.0, 0
	s_waitcnt_depctr 0xfff
	v_ldexp_f32 v8, v8, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_cndmask_b32_e32 v5, 0, v8, vcc_lo
	v_mul_lo_u32 v8, v3, s23
	v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v0
	v_minmax_f32 v3, v7, 1.0, 0
	v_cndmask_b32_e32 v0, 0x7f800000, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v7, 31, v8
	v_fmaak_f32 v5, v10, v0, 0xbdf5c28f
	v_lshlrev_b64 v[0:1], 4, v[1:2]
	v_add_co_u32 v2, vcc_lo, s8, v8
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_ci_u32_e32 v7, vcc_lo, s9, v7, vcc_lo
	v_minmax_f32 v5, v5, 1.0, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v0, vcc_lo, v2, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, v7, v1, vcc_lo
	global_store_b128 v[0:1], v[3:6], off
.LBB0_11:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z21ComputeRobustnessMaskPK15HIP_vector_typeIfLj3EES2_PS_IfLj4EEP13__hip_textureiiiifff
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 320
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 45
		.amdhsa_next_free_sgpr 35
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z21ComputeRobustnessMaskPK15HIP_vector_typeIfLj3EES2_PS_IfLj4EEP13__hip_textureiiiifff, .Lfunc_end0-_Z21ComputeRobustnessMaskPK15HIP_vector_typeIfLj3EES2_PS_IfLj4EEP13__hip_textureiiiifff
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 4540
; NumSgprs: 37
; NumVgprs: 45
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 4
; VGPRBlocks: 5
; NumSGPRsForWavesPerEU: 37
; NumVGPRsForWavesPerEU: 45
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .actual_access:  read_only
        .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .actual_access:  read_only
        .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .actual_access:  write_only
        .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         36
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     by_value
      - .offset:         44
        .size:           4
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     by_value
      - .offset:         52
        .size:           4
        .value_kind:     by_value
      - .offset:         56
        .size:           4
        .value_kind:     by_value
      - .offset:         64
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         68
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         72
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         76
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         78
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         80
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         82
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         84
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         86
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         112
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         120
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         128
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         184
        .size:           4
        .value_kind:     hidden_dynamic_lds_size
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 320
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z21ComputeRobustnessMaskPK15HIP_vector_typeIfLj3EES2_PS_IfLj4EEP13__hip_textureiiiifff
    .private_segment_fixed_size: 0
    .sgpr_count:     37
    .sgpr_spill_count: 0
    .symbol:         _Z21ComputeRobustnessMaskPK15HIP_vector_typeIfLj3EES2_PS_IfLj4EEP13__hip_textureiiiifff.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     45
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
