#include <cuda_runtime.h>
#include <stdio.h>

#define N 256

__global__ void matrix_vector_multi_gpu_1_1(float *A_d, float *B_d, float *C_d)
{
	int i,j;

	for(j=0;j<N;j++){
		A_d[j] = 0.0F;
		for(i=0;i<N;i++) {
		 A_d[j] = A_d[j]+B_d[j*N+i]*C_d[i];
		 }
	}
}

__global__ void matrix_vector_multi_gpu_1_1_sh(float *A_d, float *B_d, float *C_d)
{
	int i;

	__shared__ float tmp_c[N];

	tmp_c[threadIdx.x] = C_d[threadIdx.x];
	__syncthreads();

	A_d[threadIdx.x] = 0.0F;

	for(i=0;i<N;i++){
		A_d[threadIdx.x] = A_d[threadIdx.x] + B_d[threadIdx.x*N+1]*tmp_c[i];
	}
}

int main(int argc, char **argv)
{
    // set up device
    int dev = 0;

    unsigned int t, travdirtime; 

    int i,j;
    float A[N], B[N*N], C[N];
    float *A_d, *B_d, *C_d;

    dim3 blocks(1,1,1);
    dim3 threads(1,1,1);

    for(j=0;j<N;j++) {
        for(i=0;i<N;i++) {
	   B[j*N+i] = ((float)j)/256.0;
	   }
    }	   

    for(j=0;j<N;j++)
	C[j] = 1.0F;
	
    cudaMalloc((void **)&A_d, N*sizeof(float));
    cudaMalloc((void **)&B_d, N*N*sizeof(float));
    cudaMalloc((void **)&C_d, N*sizeof(float));

    cudaMemcpy(A_d, A, N*sizeof(float), cudaMemcpyHostToDevice);
    cudaMemcpy(B_d, B, N*N*sizeof(float), cudaMemcpyHostToDevice);
    cudaMemcpy(C_d, C, N*sizeof(float), cudaMemcpyHostToDevice);

    matrix_vector_multi_gpu_1_1<<<blocks, threads>>>(A_d, B_d, C_d);
    matrix_vector_multi_gpu_1_1_sh<<<blocks, threads>>>(A_d, B_d, C_d);

    cudaFree(A_d);
    cudaFree(B_d);
    cudaFree(C_d);

    return EXIT_SUCCESS;
}

	.file	"tmpxft_0020127c_00000000-6_1.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2030:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z51__device_stub__Z27matrix_vector_multi_gpu_1_1PfS_S_PfS_S_
	.type	_Z51__device_stub__Z27matrix_vector_multi_gpu_1_1PfS_S_PfS_S_, @function
_Z51__device_stub__Z27matrix_vector_multi_gpu_1_1PfS_S_PfS_S_:
.LFB2052:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z27matrix_vector_multi_gpu_1_1PfS_S_(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L2:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2052:
	.size	_Z51__device_stub__Z27matrix_vector_multi_gpu_1_1PfS_S_PfS_S_, .-_Z51__device_stub__Z27matrix_vector_multi_gpu_1_1PfS_S_PfS_S_
	.globl	_Z27matrix_vector_multi_gpu_1_1PfS_S_
	.type	_Z27matrix_vector_multi_gpu_1_1PfS_S_, @function
_Z27matrix_vector_multi_gpu_1_1PfS_S_:
.LFB2053:
	.cfi_startproc
	endbr64
	jmp	_Z51__device_stub__Z27matrix_vector_multi_gpu_1_1PfS_S_PfS_S_
	.cfi_endproc
.LFE2053:
	.size	_Z27matrix_vector_multi_gpu_1_1PfS_S_, .-_Z27matrix_vector_multi_gpu_1_1PfS_S_
	.globl	_Z54__device_stub__Z30matrix_vector_multi_gpu_1_1_shPfS_S_PfS_S_
	.type	_Z54__device_stub__Z30matrix_vector_multi_gpu_1_1_shPfS_S_PfS_S_, @function
_Z54__device_stub__Z30matrix_vector_multi_gpu_1_1_shPfS_S_PfS_S_:
.LFB2054:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L8
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z30matrix_vector_multi_gpu_1_1_shPfS_S_(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L8:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L10
	call	__stack_chk_fail@PLT
.L10:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2054:
	.size	_Z54__device_stub__Z30matrix_vector_multi_gpu_1_1_shPfS_S_PfS_S_, .-_Z54__device_stub__Z30matrix_vector_multi_gpu_1_1_shPfS_S_PfS_S_
	.globl	_Z30matrix_vector_multi_gpu_1_1_shPfS_S_
	.type	_Z30matrix_vector_multi_gpu_1_1_shPfS_S_, @function
_Z30matrix_vector_multi_gpu_1_1_shPfS_S_:
.LFB2055:
	.cfi_startproc
	endbr64
	jmp	_Z54__device_stub__Z30matrix_vector_multi_gpu_1_1_shPfS_S_PfS_S_
	.cfi_endproc
.LFE2055:
	.size	_Z30matrix_vector_multi_gpu_1_1_shPfS_S_, .-_Z30matrix_vector_multi_gpu_1_1_shPfS_S_
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	pushq	%rbx
	.cfi_def_cfa_offset 24
	.cfi_offset 3, -24
	leaq	-262144(%rsp), %r11
	.cfi_def_cfa 11, 262168
.LPSRL0:
	subq	$4096, %rsp
	orq	$0, (%rsp)
	cmpq	%r11, %rsp
	jne	.LPSRL0
	.cfi_def_cfa_register 7
	subq	$2120, %rsp
	.cfi_def_cfa_offset 264288
	movss	.LC0(%rip), %xmm1
	xorl	%edx, %edx
	movq	%fs:40, %rax
	movq	%rax, 264248(%rsp)
	movabsq	$4294967297, %rax
	movl	$1, 40(%rsp)
	leaq	2104(%rsp), %rcx
	movl	$1, 52(%rsp)
	movq	%rcx, %rbx
	movq	%rax, 32(%rsp)
	movq	%rax, 44(%rsp)
.L14:
	cvtsi2ssl	%edx, %xmm0
	xorl	%eax, %eax
	mulss	%xmm1, %xmm0
.L15:
	movss	%xmm0, (%rcx,%rax,4)
	incq	%rax
	cmpq	$256, %rax
	jne	.L15
	incl	%edx
	addq	$1024, %rcx
	cmpl	$256, %edx
	jne	.L14
	movss	.LC1(%rip), %xmm0
	xorl	%eax, %eax
.L16:
	leaq	1080(%rsp), %rbp
	movss	%xmm0, 0(%rbp,%rax,4)
	incq	%rax
	cmpq	$256, %rax
	jne	.L16
	leaq	8(%rsp), %rdi
	movl	$1024, %esi
	call	cudaMalloc@PLT
	leaq	16(%rsp), %rdi
	movl	$262144, %esi
	call	cudaMalloc@PLT
	leaq	24(%rsp), %rdi
	movl	$1024, %esi
	call	cudaMalloc@PLT
	movq	8(%rsp), %rdi
	leaq	56(%rsp), %rsi
	movl	$1, %ecx
	movl	$1024, %edx
	call	cudaMemcpy@PLT
	movq	16(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbx, %rsi
	movl	$262144, %edx
	call	cudaMemcpy@PLT
	movq	24(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbp, %rsi
	movl	$1024, %edx
	call	cudaMemcpy@PLT
	movl	52(%rsp), %ecx
	movl	40(%rsp), %esi
	xorl	%r9d, %r9d
	movq	44(%rsp), %rdx
	movq	32(%rsp), %rdi
	xorl	%r8d, %r8d
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L17
	movq	24(%rsp), %rdx
	movq	16(%rsp), %rsi
	movq	8(%rsp), %rdi
	call	_Z51__device_stub__Z27matrix_vector_multi_gpu_1_1PfS_S_PfS_S_
.L17:
	movl	52(%rsp), %ecx
	movq	44(%rsp), %rdx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	32(%rsp), %rdi
	movl	40(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L18
	movq	24(%rsp), %rdx
	movq	16(%rsp), %rsi
	movq	8(%rsp), %rdi
	call	_Z54__device_stub__Z30matrix_vector_multi_gpu_1_1_shPfS_S_PfS_S_
.L18:
	movq	8(%rsp), %rdi
	call	cudaFree@PLT
	movq	16(%rsp), %rdi
	call	cudaFree@PLT
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	movq	264248(%rsp), %rax
	subq	%fs:40, %rax
	je	.L19
	call	__stack_chk_fail@PLT
.L19:
	addq	$264264, %rsp
	.cfi_def_cfa_offset 24
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2027:
	.size	main, .-main
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC2:
	.string	"_Z30matrix_vector_multi_gpu_1_1_shPfS_S_"
.LC3:
	.string	"_Z27matrix_vector_multi_gpu_1_1PfS_S_"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2057:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC2(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z30matrix_vector_multi_gpu_1_1_shPfS_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC3(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z27matrix_vector_multi_gpu_1_1PfS_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2057:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst4,"aM",@progbits,4
	.align 4
.LC0:
	.long	998244352
	.align 4
.LC1:
	.long	1065353216
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <hip/hip_runtime.h>
#include <stdio.h>

#define N 256

__global__ void matrix_vector_multi_gpu_1_1(float *A_d, float *B_d, float *C_d)
{
	int i,j;

	for(j=0;j<N;j++){
		A_d[j] = 0.0F;
		for(i=0;i<N;i++) {
		 A_d[j] = A_d[j]+B_d[j*N+i]*C_d[i];
		 }
	}
}

__global__ void matrix_vector_multi_gpu_1_1_sh(float *A_d, float *B_d, float *C_d)
{
	int i;

	__shared__ float tmp_c[N];

	tmp_c[threadIdx.x] = C_d[threadIdx.x];
	__syncthreads();

	A_d[threadIdx.x] = 0.0F;

	for(i=0;i<N;i++){
		A_d[threadIdx.x] = A_d[threadIdx.x] + B_d[threadIdx.x*N+1]*tmp_c[i];
	}
}

int main(int argc, char **argv)
{
    // set up device
    int dev = 0;

    unsigned int t, travdirtime; 

    int i,j;
    float A[N], B[N*N], C[N];
    float *A_d, *B_d, *C_d;

    dim3 blocks(1,1,1);
    dim3 threads(1,1,1);

    for(j=0;j<N;j++) {
        for(i=0;i<N;i++) {
	   B[j*N+i] = ((float)j)/256.0;
	   }
    }	   

    for(j=0;j<N;j++)
	C[j] = 1.0F;
	
    hipMalloc((void **)&A_d, N*sizeof(float));
    hipMalloc((void **)&B_d, N*N*sizeof(float));
    hipMalloc((void **)&C_d, N*sizeof(float));

    hipMemcpy(A_d, A, N*sizeof(float), hipMemcpyHostToDevice);
    hipMemcpy(B_d, B, N*N*sizeof(float), hipMemcpyHostToDevice);
    hipMemcpy(C_d, C, N*sizeof(float), hipMemcpyHostToDevice);

    matrix_vector_multi_gpu_1_1<<<blocks, threads>>>(A_d, B_d, C_d);
    matrix_vector_multi_gpu_1_1_sh<<<blocks, threads>>>(A_d, B_d, C_d);

    hipFree(A_d);
    hipFree(B_d);
    hipFree(C_d);

    return EXIT_SUCCESS;
}

	.text
	.file	"1.hip"
	.globl	_Z42__device_stub__matrix_vector_multi_gpu_1_1PfS_S_ # -- Begin function _Z42__device_stub__matrix_vector_multi_gpu_1_1PfS_S_
	.type	_Z42__device_stub__matrix_vector_multi_gpu_1_1PfS_S_,@function
_Z42__device_stub__matrix_vector_multi_gpu_1_1PfS_S_: # @_Z42__device_stub__matrix_vector_multi_gpu_1_1PfS_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z27matrix_vector_multi_gpu_1_1PfS_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z42__device_stub__matrix_vector_multi_gpu_1_1PfS_S_, .Lfunc_end0-_Z42__device_stub__matrix_vector_multi_gpu_1_1PfS_S_
	.cfi_endproc
                                        # -- End function
	.globl	_Z45__device_stub__matrix_vector_multi_gpu_1_1_shPfS_S_ # -- Begin function _Z45__device_stub__matrix_vector_multi_gpu_1_1_shPfS_S_
	.type	_Z45__device_stub__matrix_vector_multi_gpu_1_1_shPfS_S_,@function
_Z45__device_stub__matrix_vector_multi_gpu_1_1_shPfS_S_: # @_Z45__device_stub__matrix_vector_multi_gpu_1_1_shPfS_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z30matrix_vector_multi_gpu_1_1_shPfS_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z45__device_stub__matrix_vector_multi_gpu_1_1_shPfS_S_, .Lfunc_end1-_Z45__device_stub__matrix_vector_multi_gpu_1_1_shPfS_S_
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0                          # -- Begin function main
.LCPI2_0:
	.quad	0x3f70000000000000              # double 0.00390625
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r12
	.cfi_def_cfa_offset 32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	subq	$264232, %rsp                   # imm = 0x40828
	.cfi_def_cfa_offset 264272
	.cfi_offset %rbx, -40
	.cfi_offset %r12, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	2080(%rsp), %rax
	xorl	%ecx, %ecx
	movsd	.LCPI2_0(%rip), %xmm0           # xmm0 = mem[0],zero
.LBB2_1:                                # %.preheader32
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB2_2 Depth 2
	xorps	%xmm1, %xmm1
	cvtsi2sd	%ecx, %xmm1
	mulsd	%xmm0, %xmm1
	cvtsd2ss	%xmm1, %xmm1
	xorl	%edx, %edx
.LBB2_2:                                #   Parent Loop BB2_1 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movss	%xmm1, (%rax,%rdx,4)
	incq	%rdx
	cmpq	$256, %rdx                      # imm = 0x100
	jne	.LBB2_2
# %bb.3:                                #   in Loop: Header=BB2_1 Depth=1
	incq	%rcx
	addq	$1024, %rax                     # imm = 0x400
	cmpq	$256, %rcx                      # imm = 0x100
	jne	.LBB2_1
# %bb.4:                                # %.preheader.preheader
	xorl	%eax, %eax
.LBB2_5:                                # %.preheader
                                        # =>This Inner Loop Header: Depth=1
	movl	$1065353216, 32(%rsp,%rax,4)    # imm = 0x3F800000
	incq	%rax
	cmpq	$256, %rax                      # imm = 0x100
	jne	.LBB2_5
# %bb.6:
	movabsq	$4294967297, %rbx               # imm = 0x100000001
	leaq	24(%rsp), %r14
	movl	$1024, %esi                     # imm = 0x400
	movq	%r14, %rdi
	callq	hipMalloc
	leaq	16(%rsp), %r15
	movl	$262144, %esi                   # imm = 0x40000
	movq	%r15, %rdi
	callq	hipMalloc
	leaq	8(%rsp), %r12
	movl	$1024, %esi                     # imm = 0x400
	movq	%r12, %rdi
	callq	hipMalloc
	movq	(%r14), %rdi
	leaq	1056(%rsp), %rsi
	movl	$1024, %edx                     # imm = 0x400
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%r15), %rdi
	leaq	2080(%rsp), %rsi
	movl	$262144, %edx                   # imm = 0x40000
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%r12), %rdi
	leaq	32(%rsp), %rsi
	movl	$1024, %edx                     # imm = 0x400
	movl	$1, %ecx
	callq	hipMemcpy
	movq	%rbx, %rdi
	movl	$1, %esi
	movq	%rbx, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_8
# %bb.7:
	movq	24(%rsp), %rdi
	movq	16(%rsp), %rsi
	movq	8(%rsp), %rdx
	callq	_Z42__device_stub__matrix_vector_multi_gpu_1_1PfS_S_
.LBB2_8:
	movq	%rbx, %rdi
	movl	$1, %esi
	movq	%rbx, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_10
# %bb.9:
	movq	24(%rsp), %rdi
	movq	16(%rsp), %rsi
	movq	8(%rsp), %rdx
	callq	_Z45__device_stub__matrix_vector_multi_gpu_1_1_shPfS_S_
.LBB2_10:
	movq	24(%rsp), %rdi
	callq	hipFree
	movq	16(%rsp), %rdi
	callq	hipFree
	movq	8(%rsp), %rdi
	callq	hipFree
	xorl	%eax, %eax
	addq	$264232, %rsp                   # imm = 0x40828
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	main, .Lfunc_end2-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB3_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB3_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z27matrix_vector_multi_gpu_1_1PfS_S_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z30matrix_vector_multi_gpu_1_1_shPfS_S_, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end3:
	.size	__hip_module_ctor, .Lfunc_end3-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB4_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB4_2:
	retq
.Lfunc_end4:
	.size	__hip_module_dtor, .Lfunc_end4-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z27matrix_vector_multi_gpu_1_1PfS_S_,@object # @_Z27matrix_vector_multi_gpu_1_1PfS_S_
	.section	.rodata,"a",@progbits
	.globl	_Z27matrix_vector_multi_gpu_1_1PfS_S_
	.p2align	3, 0x0
_Z27matrix_vector_multi_gpu_1_1PfS_S_:
	.quad	_Z42__device_stub__matrix_vector_multi_gpu_1_1PfS_S_
	.size	_Z27matrix_vector_multi_gpu_1_1PfS_S_, 8

	.type	_Z30matrix_vector_multi_gpu_1_1_shPfS_S_,@object # @_Z30matrix_vector_multi_gpu_1_1_shPfS_S_
	.globl	_Z30matrix_vector_multi_gpu_1_1_shPfS_S_
	.p2align	3, 0x0
_Z30matrix_vector_multi_gpu_1_1_shPfS_S_:
	.quad	_Z45__device_stub__matrix_vector_multi_gpu_1_1_shPfS_S_
	.size	_Z30matrix_vector_multi_gpu_1_1_shPfS_S_, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z27matrix_vector_multi_gpu_1_1PfS_S_"
	.size	.L__unnamed_1, 38

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z30matrix_vector_multi_gpu_1_1_shPfS_S_"
	.size	.L__unnamed_2, 41

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z42__device_stub__matrix_vector_multi_gpu_1_1PfS_S_
	.addrsig_sym _Z45__device_stub__matrix_vector_multi_gpu_1_1_shPfS_S_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z27matrix_vector_multi_gpu_1_1PfS_S_
	.addrsig_sym _Z30matrix_vector_multi_gpu_1_1_shPfS_S_
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z27matrix_vector_multi_gpu_1_1PfS_S_ ; -- Begin function _Z27matrix_vector_multi_gpu_1_1PfS_S_
	.globl	_Z27matrix_vector_multi_gpu_1_1PfS_S_
	.p2align	8
	.type	_Z27matrix_vector_multi_gpu_1_1PfS_S_,@function
_Z27matrix_vector_multi_gpu_1_1PfS_S_:  ; @_Z27matrix_vector_multi_gpu_1_1PfS_S_
; %bb.0:
	s_clause 0x1
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b64 s[0:1], s[0:1], 0x10
	v_mov_b32_e32 v0, 0
	s_mov_b32 s3, 0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s2, s3
.LBB0_1:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_2 Depth 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_lshl_b64 s[8:9], s[2:3], 2
	v_mov_b32_e32 v1, 0
	s_waitcnt lgkmcnt(0)
	s_add_u32 s8, s4, s8
	s_addc_u32 s9, s5, s9
	s_mov_b64 s[10:11], 0
	global_store_b32 v0, v0, s[8:9]
.LBB0_2:                                ;   Parent Loop BB0_1 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_add_u32 s12, s6, s10
	s_addc_u32 s13, s7, s11
	s_add_u32 s14, s0, s10
	s_addc_u32 s15, s1, s11
	s_clause 0x1
	global_load_b32 v2, v0, s[12:13]
	global_load_b32 v3, v0, s[14:15]
	s_add_u32 s10, s10, 4
	s_addc_u32 s11, s11, 0
	s_cmpk_lg_i32 s10, 0x400
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v1, v2, v3
	global_store_b32 v0, v1, s[8:9]
	s_cbranch_scc1 .LBB0_2
; %bb.3:                                ;   in Loop: Header=BB0_1 Depth=1
	s_add_i32 s2, s2, 1
	s_add_u32 s6, s6, 0x400
	s_addc_u32 s7, s7, 0
	s_cmpk_lg_i32 s2, 0x100
	s_cbranch_scc1 .LBB0_1
; %bb.4:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z27matrix_vector_multi_gpu_1_1PfS_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 24
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 4
		.amdhsa_next_free_sgpr 16
		.amdhsa_reserve_vcc 0
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z27matrix_vector_multi_gpu_1_1PfS_S_, .Lfunc_end0-_Z27matrix_vector_multi_gpu_1_1PfS_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 176
; NumSgprs: 16
; NumVgprs: 4
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 1
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 16
; NumVGPRsForWavesPerEU: 4
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z30matrix_vector_multi_gpu_1_1_shPfS_S_ ; -- Begin function _Z30matrix_vector_multi_gpu_1_1_shPfS_S_
	.globl	_Z30matrix_vector_multi_gpu_1_1_shPfS_S_
	.p2align	8
	.type	_Z30matrix_vector_multi_gpu_1_1_shPfS_S_,@function
_Z30matrix_vector_multi_gpu_1_1_shPfS_S_: ; @_Z30matrix_vector_multi_gpu_1_1_shPfS_S_
; %bb.0:
	s_clause 0x1
	s_load_b64 s[2:3], s[0:1], 0x10
	s_load_b128 s[4:7], s[0:1], 0x0
	v_dual_mov_b32 v4, 0 :: v_dual_lshlrev_b32 v5, 2, v0
	v_lshlrev_b32_e32 v2, 10, v0
	s_mov_b32 s0, 0
	s_waitcnt lgkmcnt(0)
	global_load_b32 v6, v5, s[2:3]
	v_add_co_u32 v0, s1, s4, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e64 v1, null, s5, 0, s1
	v_add_co_u32 v2, s1, s6, v2
	v_add_co_ci_u32_e64 v3, null, s7, 0, s1
	s_waitcnt vmcnt(0)
	ds_store_b32 v5, v6
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	global_store_b32 v5, v4, s[4:5]
.LBB1_1:                                ; =>This Inner Loop Header: Depth=1
	global_load_b32 v5, v[2:3], off offset:4
	v_mov_b32_e32 v6, s0
	s_add_i32 s0, s0, 4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmpk_lg_i32 s0, 0x400
	ds_load_b32 v6, v6
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_fmac_f32_e32 v4, v5, v6
	global_store_b32 v[0:1], v4, off
	s_cbranch_scc1 .LBB1_1
; %bb.2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z30matrix_vector_multi_gpu_1_1_shPfS_S_
		.amdhsa_group_segment_fixed_size 1024
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 24
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 7
		.amdhsa_next_free_sgpr 8
		.amdhsa_reserve_vcc 0
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z30matrix_vector_multi_gpu_1_1_shPfS_S_, .Lfunc_end1-_Z30matrix_vector_multi_gpu_1_1_shPfS_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 184
; NumSgprs: 8
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 1024 bytes/workgroup (compile time only)
; SGPRBlocks: 0
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 8
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 24
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z27matrix_vector_multi_gpu_1_1PfS_S_
    .private_segment_fixed_size: 0
    .sgpr_count:     16
    .sgpr_spill_count: 0
    .symbol:         _Z27matrix_vector_multi_gpu_1_1PfS_S_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     4
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
    .group_segment_fixed_size: 1024
    .kernarg_segment_align: 8
    .kernarg_segment_size: 24
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z30matrix_vector_multi_gpu_1_1_shPfS_S_
    .private_segment_fixed_size: 0
    .sgpr_count:     8
    .sgpr_spill_count: 0
    .symbol:         _Z30matrix_vector_multi_gpu_1_1_shPfS_S_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     7
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
