#define COALESCED_NUM 16
#define blockDimX 128
#define blockDimY 1
#define gridDimX (gridDim.x)
#define gridDimY (gridDim.y)
#define idx (blockIdx.x*blockDimX+threadIdx.x)
#define idy (blockIdx.y*blockDimY+threadIdx.y)
#define bidy (blockIdx.y)
#define bidx (blockIdx.x)
#define tidx (threadIdx.x)
#define tidy (threadIdx.y)
#define merger_y 16
#define coalesced_idy (bidy/(COALESCED_NUM/(merger_y*blockDimY))*COALESCED_NUM)
#define A(y,x) A[(y)*WIDTH_A+(x)]
#define B(y,x) B[(y)*WIDTH_B+(x)]
#define C(y,x) C[(y)*WIDTH_C+(x)]
#define WIDTH_C 2048
#define WIDTH_B 2048
#define WIDTH_A 2048
__global__ void matmul(float * A, float * B, float * C, int width, int height)
{
	__shared__ float shared_0[16][17];
	int i;
	float sum_0;
	float sum_1;
	float sum_2;
	float sum_3;
	float sum_4;
	float sum_5;
	float sum_6;
	float sum_7;
	float sum_8;
	float sum_9;
	float sum_10;
	float sum_11;
	float sum_12;
	float sum_13;
	float sum_14;
	float sum_15;
	sum_0=0;
	sum_1=0;
	sum_2=0;
	sum_3=0;
	sum_4=0;
	sum_5=0;
	sum_6=0;
	sum_7=0;
	sum_8=0;
	sum_9=0;
	sum_10=0;
	sum_11=0;
	sum_12=0;
	sum_13=0;
	sum_14=0;
	sum_15=0;
	for (i=0; i<width; i=(i+16))
	{
		int it_1;
		shared_0[((tidx%16)+0)][(tidx/16)]=A(((((bidy*16)+tidy)+(tidx/16))+0), (i+(tidx%16)));
		shared_0[((tidx%16)+0)][(tidx/16)]=A(((((bidy*16)+tidy)+(tidx/16))+8), (i+(tidx%16)));
		__syncthreads();
		#pragma unroll 
		for (it_1=0; it_1<16; it_1=(it_1+1))
		{
			float a_0;
			float a_1;
			float a_2;
			float a_3;
			float a_4;
			float a_5;
			float a_6;
			float a_7;
			float a_8;
			float a_9;
			float a_10;
			float a_11;
			float a_12;
			float a_13;
			float a_14;
			float a_15;
			float b;
			a_0=shared_0[it_1][0];
			a_1=shared_0[it_1][1];
			a_2=shared_0[it_1][2];
			a_3=shared_0[it_1][3];
			a_4=shared_0[it_1][4];
			a_5=shared_0[it_1][5];
			a_6=shared_0[it_1][6];
			a_7=shared_0[it_1][7];
			a_8=shared_0[it_1][8];
			a_9=shared_0[it_1][9];
			a_10=shared_0[it_1][10];
			a_11=shared_0[it_1][11];
			a_12=shared_0[it_1][12];
			a_13=shared_0[it_1][13];
			a_14=shared_0[it_1][14];
			a_15=shared_0[it_1][15];
			b=B((it_1+i), idx);
			sum_0+=(a_0*b);
			sum_1+=(a_1*b);
			sum_2+=(a_2*b);
			sum_3+=(a_3*b);
			sum_4+=(a_4*b);
			sum_5+=(a_5*b);
			sum_6+=(a_6*b);
			sum_7+=(a_7*b);
			sum_8+=(a_8*b);
			sum_9+=(a_9*b);
			sum_10+=(a_10*b);
			sum_11+=(a_11*b);
			sum_12+=(a_12*b);
			sum_13+=(a_13*b);
			sum_14+=(a_14*b);
			sum_15+=(a_15*b);
		}
		__syncthreads();
	}
	{
		C((((bidy*16)+tidy)+0), idx)=sum_0;
	}
	{
		C((((bidy*16)+tidy)+1), idx)=sum_1;
	}
	{
		C((((bidy*16)+tidy)+2), idx)=sum_2;
	}
	{
		C((((bidy*16)+tidy)+3), idx)=sum_3;
	}
	{
		C((((bidy*16)+tidy)+4), idx)=sum_4;
	}
	{
		C((((bidy*16)+tidy)+5), idx)=sum_5;
	}
	{
		C((((bidy*16)+tidy)+6), idx)=sum_6;
	}
	{
		C((((bidy*16)+tidy)+7), idx)=sum_7;
	}
	{
		C((((bidy*16)+tidy)+8), idx)=sum_8;
	}
	{
		C((((bidy*16)+tidy)+9), idx)=sum_9;
	}
	{
		C((((bidy*16)+tidy)+10), idx)=sum_10;
	}
	{
		C((((bidy*16)+tidy)+11), idx)=sum_11;
	}
	{
		C((((bidy*16)+tidy)+12), idx)=sum_12;
	}
	{
		C((((bidy*16)+tidy)+13), idx)=sum_13;
	}
	{
		C((((bidy*16)+tidy)+14), idx)=sum_14;
	}
	{
		C((((bidy*16)+tidy)+15), idx)=sum_15;
	}
}

	.file	"tmpxft_00240c78_00000000-6_gcompiler_matmul_THREADBLOCK_X_8__THREAD_Y_16_.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2010:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2010:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z31__device_stub__Z6matmulPfS_S_iiPfS_S_ii
	.type	_Z31__device_stub__Z6matmulPfS_S_iiPfS_S_ii, @function
_Z31__device_stub__Z6matmulPfS_S_iiPfS_S_ii:
.LFB2032:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	32(%rsp), %rdx
	movl	%ecx, 4(%rsp)
	leaq	40(%rsp), %rcx
	movl	%r8d, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	40(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z6matmulPfS_S_ii(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 176
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L2:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2032:
	.size	_Z31__device_stub__Z6matmulPfS_S_iiPfS_S_ii, .-_Z31__device_stub__Z6matmulPfS_S_iiPfS_S_ii
	.globl	_Z6matmulPfS_S_ii
	.type	_Z6matmulPfS_S_ii, @function
_Z6matmulPfS_S_ii:
.LFB2033:
	.cfi_startproc
	endbr64
	jmp	_Z31__device_stub__Z6matmulPfS_S_iiPfS_S_ii
	.cfi_endproc
.LFE2033:
	.size	_Z6matmulPfS_S_ii, .-_Z6matmulPfS_S_ii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z6matmulPfS_S_ii"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2035:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z6matmulPfS_S_ii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2035:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#define COALESCED_NUM 16
#define blockDimX 128
#define blockDimY 1
#define gridDimX (gridDim.x)
#define gridDimY (gridDim.y)
#define idx (blockIdx.x*blockDimX+threadIdx.x)
#define idy (blockIdx.y*blockDimY+threadIdx.y)
#define bidy (blockIdx.y)
#define bidx (blockIdx.x)
#define tidx (threadIdx.x)
#define tidy (threadIdx.y)
#define merger_y 16
#define coalesced_idy (bidy/(COALESCED_NUM/(merger_y*blockDimY))*COALESCED_NUM)
#define A(y,x) A[(y)*WIDTH_A+(x)]
#define B(y,x) B[(y)*WIDTH_B+(x)]
#define C(y,x) C[(y)*WIDTH_C+(x)]
#define WIDTH_C 2048
#define WIDTH_B 2048
#define WIDTH_A 2048
__global__ void matmul(float * A, float * B, float * C, int width, int height)
{
	__shared__ float shared_0[16][17];
	int i;
	float sum_0;
	float sum_1;
	float sum_2;
	float sum_3;
	float sum_4;
	float sum_5;
	float sum_6;
	float sum_7;
	float sum_8;
	float sum_9;
	float sum_10;
	float sum_11;
	float sum_12;
	float sum_13;
	float sum_14;
	float sum_15;
	sum_0=0;
	sum_1=0;
	sum_2=0;
	sum_3=0;
	sum_4=0;
	sum_5=0;
	sum_6=0;
	sum_7=0;
	sum_8=0;
	sum_9=0;
	sum_10=0;
	sum_11=0;
	sum_12=0;
	sum_13=0;
	sum_14=0;
	sum_15=0;
	for (i=0; i<width; i=(i+16))
	{
		int it_1;
		shared_0[((tidx%16)+0)][(tidx/16)]=A(((((bidy*16)+tidy)+(tidx/16))+0), (i+(tidx%16)));
		shared_0[((tidx%16)+0)][(tidx/16)]=A(((((bidy*16)+tidy)+(tidx/16))+8), (i+(tidx%16)));
		__syncthreads();
		#pragma unroll 
		for (it_1=0; it_1<16; it_1=(it_1+1))
		{
			float a_0;
			float a_1;
			float a_2;
			float a_3;
			float a_4;
			float a_5;
			float a_6;
			float a_7;
			float a_8;
			float a_9;
			float a_10;
			float a_11;
			float a_12;
			float a_13;
			float a_14;
			float a_15;
			float b;
			a_0=shared_0[it_1][0];
			a_1=shared_0[it_1][1];
			a_2=shared_0[it_1][2];
			a_3=shared_0[it_1][3];
			a_4=shared_0[it_1][4];
			a_5=shared_0[it_1][5];
			a_6=shared_0[it_1][6];
			a_7=shared_0[it_1][7];
			a_8=shared_0[it_1][8];
			a_9=shared_0[it_1][9];
			a_10=shared_0[it_1][10];
			a_11=shared_0[it_1][11];
			a_12=shared_0[it_1][12];
			a_13=shared_0[it_1][13];
			a_14=shared_0[it_1][14];
			a_15=shared_0[it_1][15];
			b=B((it_1+i), idx);
			sum_0+=(a_0*b);
			sum_1+=(a_1*b);
			sum_2+=(a_2*b);
			sum_3+=(a_3*b);
			sum_4+=(a_4*b);
			sum_5+=(a_5*b);
			sum_6+=(a_6*b);
			sum_7+=(a_7*b);
			sum_8+=(a_8*b);
			sum_9+=(a_9*b);
			sum_10+=(a_10*b);
			sum_11+=(a_11*b);
			sum_12+=(a_12*b);
			sum_13+=(a_13*b);
			sum_14+=(a_14*b);
			sum_15+=(a_15*b);
		}
		__syncthreads();
	}
	{
		C((((bidy*16)+tidy)+0), idx)=sum_0;
	}
	{
		C((((bidy*16)+tidy)+1), idx)=sum_1;
	}
	{
		C((((bidy*16)+tidy)+2), idx)=sum_2;
	}
	{
		C((((bidy*16)+tidy)+3), idx)=sum_3;
	}
	{
		C((((bidy*16)+tidy)+4), idx)=sum_4;
	}
	{
		C((((bidy*16)+tidy)+5), idx)=sum_5;
	}
	{
		C((((bidy*16)+tidy)+6), idx)=sum_6;
	}
	{
		C((((bidy*16)+tidy)+7), idx)=sum_7;
	}
	{
		C((((bidy*16)+tidy)+8), idx)=sum_8;
	}
	{
		C((((bidy*16)+tidy)+9), idx)=sum_9;
	}
	{
		C((((bidy*16)+tidy)+10), idx)=sum_10;
	}
	{
		C((((bidy*16)+tidy)+11), idx)=sum_11;
	}
	{
		C((((bidy*16)+tidy)+12), idx)=sum_12;
	}
	{
		C((((bidy*16)+tidy)+13), idx)=sum_13;
	}
	{
		C((((bidy*16)+tidy)+14), idx)=sum_14;
	}
	{
		C((((bidy*16)+tidy)+15), idx)=sum_15;
	}
}

	.text
	.file	"gcompiler_matmul_THREADBLOCK_X_8__THREAD_Y_16_.hip"
	.globl	_Z21__device_stub__matmulPfS_S_ii # -- Begin function _Z21__device_stub__matmulPfS_S_ii
	.type	_Z21__device_stub__matmulPfS_S_ii,@function
_Z21__device_stub__matmulPfS_S_ii:      # @_Z21__device_stub__matmulPfS_S_ii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	4(%rsp), %rdx
	movl	%ecx, (%rdx)
	movq	%rsp, %rcx
	movl	%r8d, (%rcx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z6matmulPfS_S_ii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z21__device_stub__matmulPfS_S_ii, .Lfunc_end0-_Z21__device_stub__matmulPfS_S_ii
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z6matmulPfS_S_ii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z6matmulPfS_S_ii,@object       # @_Z6matmulPfS_S_ii
	.section	.rodata,"a",@progbits
	.globl	_Z6matmulPfS_S_ii
	.p2align	3, 0x0
_Z6matmulPfS_S_ii:
	.quad	_Z21__device_stub__matmulPfS_S_ii
	.size	_Z6matmulPfS_S_ii, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z6matmulPfS_S_ii"
	.size	.L__unnamed_1, 18

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z21__device_stub__matmulPfS_S_ii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z6matmulPfS_S_ii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z6matmulPfS_S_ii       ; -- Begin function _Z6matmulPfS_S_ii
	.globl	_Z6matmulPfS_S_ii
	.p2align	8
	.type	_Z6matmulPfS_S_ii,@function
_Z6matmulPfS_S_ii:                      ; @_Z6matmulPfS_S_ii
; %bb.0:
	s_clause 0x2
	s_load_b32 s2, s[0:1], 0x18
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b64 s[0:1], s[0:1], 0x10
	v_and_b32_e32 v2, 0x3ff, v0
	v_bfe_u32 v20, v0, 10, 10
	s_mov_b32 s3, 0
	s_delay_alu instid0(VALU_DEP_2)
	v_lshl_add_u32 v21, s14, 7, v2
	s_waitcnt lgkmcnt(0)
	s_cmp_gt_i32 s2, 0
	s_cbranch_scc1 .LBB0_2
; %bb.1:                                ; %.._crit_edge_crit_edge
	v_bfe_u32 v1, v0, 10, 10
	v_lshl_add_u32 v0, s14, 7, v2
	s_mov_b32 s8, 0
	s_branch .LBB0_3
.LBB0_2:
	s_mov_b32 s3, -1
                                        ; implicit-def: $sgpr8
                                        ; implicit-def: $vgpr1
                                        ; implicit-def: $vgpr0
.LBB0_3:                                ; %Flow301
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s3
	s_cbranch_vccnz .LBB0_7
; %bb.4:                                ; %.lr.ph
	v_lshrrev_b32_e32 v1, 4, v2
	s_lshl_b32 s3, s15, 4
	v_dual_mov_b32 v3, 0 :: v_dual_and_b32 v2, 15, v2
	v_mov_b32_e32 v24, 0x404
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_add3_u32 v4, s3, v20, v1
	v_lshlrev_b32_e32 v1, 2, v1
	v_dual_mov_b32 v13, 0 :: v_dual_add_nc_u32 v0, 0x7800, v21
	v_dual_mov_b32 v22, 0 :: v_dual_mov_b32 v23, 0x3fc
	v_lshl_or_b32 v4, v4, 11, v2
	v_dual_mov_b32 v25, 0x40c :: v_dual_mov_b32 v12, 0
	v_dual_mov_b32 v26, 0x414 :: v_dual_mov_b32 v15, 0
	v_dual_mov_b32 v27, 0x41c :: v_dual_mov_b32 v14, 0
	v_mad_u32_u24 v28, 0x44, v2, v1
	v_dual_mov_b32 v16, 0 :: v_dual_add_nc_u32 v29, 0x4000, v4
	v_dual_mov_b32 v30, 0x424 :: v_dual_mov_b32 v17, 0
	v_dual_mov_b32 v31, 0x42c :: v_dual_mov_b32 v18, 0
	v_dual_mov_b32 v32, 0x434 :: v_dual_mov_b32 v19, 0
	v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v5, 0
	v_dual_mov_b32 v6, 0 :: v_dual_mov_b32 v7, 0
	v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v9, 0
	v_dual_mov_b32 v11, 0 :: v_dual_mov_b32 v10, 0
	s_mov_b32 s3, 0
.LBB0_5:                                ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_dual_mov_b32 v1, v3 :: v_dual_add_nc_u32 v2, s3, v29
	s_add_i32 s3, s3, 16
	s_cmp_lt_i32 s3, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[33:34], 2, v[2:3]
	v_add_nc_u32_e32 v2, 0xffff8800, v0
	v_lshlrev_b64 v[35:36], 2, v[0:1]
	v_lshlrev_b64 v[37:38], 2, v[2:3]
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_u32 v33, vcc_lo, s4, v33
	v_add_co_ci_u32_e32 v34, vcc_lo, s5, v34, vcc_lo
	v_add_nc_u32_e32 v2, 0xffff9000, v0
	v_add_co_u32 v57, vcc_lo, s6, v35
	global_load_b32 v63, v[33:34], off
	v_add_co_ci_u32_e32 v58, vcc_lo, s7, v36, vcc_lo
	v_lshlrev_b64 v[35:36], 2, v[2:3]
	v_add_nc_u32_e32 v2, 0xffff9800, v0
	v_add_co_u32 v33, vcc_lo, s6, v37
	v_add_co_ci_u32_e32 v34, vcc_lo, s7, v38, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[37:38], 2, v[2:3]
	v_add_nc_u32_e32 v2, 0xffffa000, v0
	v_add_co_u32 v35, vcc_lo, s6, v35
	v_add_co_ci_u32_e32 v36, vcc_lo, s7, v36, vcc_lo
	v_lshlrev_b64 v[39:40], 2, v[2:3]
	v_add_nc_u32_e32 v2, 0xffffa800, v0
	v_add_co_u32 v37, vcc_lo, s6, v37
	v_add_co_ci_u32_e32 v38, vcc_lo, s7, v38, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[41:42], 2, v[2:3]
	v_add_nc_u32_e32 v2, 0xffffb000, v0
	v_add_co_u32 v39, vcc_lo, s6, v39
	v_add_co_ci_u32_e32 v40, vcc_lo, s7, v40, vcc_lo
	v_lshlrev_b64 v[43:44], 2, v[2:3]
	v_add_nc_u32_e32 v2, 0xffffb800, v0
	v_add_co_u32 v41, vcc_lo, s6, v41
	v_add_co_ci_u32_e32 v42, vcc_lo, s7, v42, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[45:46], 2, v[2:3]
	v_add_nc_u32_e32 v2, 0xffffc000, v0
	v_add_co_u32 v43, vcc_lo, s6, v43
	v_add_co_ci_u32_e32 v44, vcc_lo, s7, v44, vcc_lo
	v_lshlrev_b64 v[47:48], 2, v[2:3]
	v_add_nc_u32_e32 v2, 0xffffc800, v0
	v_add_co_u32 v45, vcc_lo, s6, v45
	v_add_co_ci_u32_e32 v46, vcc_lo, s7, v46, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[49:50], 2, v[2:3]
	v_add_nc_u32_e32 v2, 0xffffd000, v0
	v_add_co_u32 v47, vcc_lo, s6, v47
	v_add_co_ci_u32_e32 v48, vcc_lo, s7, v48, vcc_lo
	v_lshlrev_b64 v[51:52], 2, v[2:3]
	v_add_nc_u32_e32 v2, 0xffffd800, v0
	v_add_co_u32 v49, vcc_lo, s6, v49
	v_add_co_ci_u32_e32 v50, vcc_lo, s7, v50, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[53:54], 2, v[2:3]
	v_add_nc_u32_e32 v2, 0xffffe000, v0
	v_add_co_u32 v51, vcc_lo, s6, v51
	v_add_co_ci_u32_e32 v52, vcc_lo, s7, v52, vcc_lo
	v_lshlrev_b64 v[55:56], 2, v[2:3]
	v_add_nc_u32_e32 v2, 0xffffe800, v0
	v_add_co_u32 v53, vcc_lo, s6, v53
	v_add_co_ci_u32_e32 v54, vcc_lo, s7, v54, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[59:60], 2, v[2:3]
	v_add_nc_u32_e32 v2, 0xfffff000, v0
	v_add_co_u32 v55, vcc_lo, s6, v55
	v_add_co_ci_u32_e32 v56, vcc_lo, s7, v56, vcc_lo
	v_lshlrev_b64 v[61:62], 2, v[2:3]
	v_add_co_u32 v59, vcc_lo, s6, v59
	v_add_co_ci_u32_e32 v60, vcc_lo, s7, v60, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v61, vcc_lo, s6, v61
	v_add_co_ci_u32_e32 v62, vcc_lo, s7, v62, vcc_lo
	s_waitcnt vmcnt(0)
	ds_store_b32 v28, v63
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_clause 0xd
	global_load_b32 v83, v[33:34], off
	global_load_b32 v89, v[35:36], off
	global_load_b32 v90, v[37:38], off
	global_load_b32 v91, v[39:40], off
	global_load_b32 v92, v[41:42], off
	global_load_b32 v93, v[43:44], off
	global_load_b32 v94, v[45:46], off
	global_load_b32 v95, v[47:48], off
	global_load_b32 v96, v[49:50], off
	global_load_b32 v97, v[51:52], off
	global_load_b32 v98, v[53:54], off
	global_load_b32 v99, v[55:56], off
	global_load_b32 v100, v[59:60], off
	global_load_b32 v101, v[61:62], off
	v_add_nc_u32_e32 v2, 0xfffff800, v0
	ds_load_b128 v[33:36], v22
	ds_load_b128 v[37:40], v22 offset:16
	ds_load_b128 v[41:44], v22 offset:32
	ds_load_b128 v[45:48], v22 offset:48
	v_lshlrev_b64 v[1:2], 2, v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s6, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
	global_load_b32 v102, v[1:2], off
	ds_load_2addr_b32 v[1:2], v22 offset0:17 offset1:18
	ds_load_2addr_b32 v[61:62], v22 offset0:19 offset1:20
	ds_load_2addr_b32 v[63:64], v22 offset0:21 offset1:22
	ds_load_2addr_b32 v[65:66], v22 offset0:23 offset1:24
	ds_load_2addr_b32 v[67:68], v22 offset0:25 offset1:26
	ds_load_2addr_b32 v[69:70], v22 offset0:27 offset1:28
	ds_load_2addr_b32 v[71:72], v22 offset0:29 offset1:30
	ds_load_2addr_b32 v[73:74], v22 offset0:31 offset1:32
	ds_load_2addr_b64 v[49:52], v22 offset0:17 offset1:18
	ds_load_2addr_b64 v[53:56], v22 offset0:19 offset1:20
	global_load_b32 v103, v[57:58], off
	ds_load_2addr_b64 v[57:60], v22 offset0:21 offset1:22
	s_waitcnt vmcnt(15) lgkmcnt(14)
	v_fmac_f32_e32 v13, v34, v83
	s_waitcnt lgkmcnt(13)
	v_dual_fmac_f32 v19, v40, v83 :: v_dual_add_nc_u32 v0, 0x8000, v0
	v_fmac_f32_e32 v15, v36, v83
	s_waitcnt lgkmcnt(12)
	v_fmac_f32_e32 v5, v42, v83
	s_waitcnt vmcnt(14) lgkmcnt(10)
	v_fmac_f32_e32 v13, v2, v89
	v_fmac_f32_e32 v7, v44, v83
	v_fmac_f32_e32 v14, v35, v83
	v_fmac_f32_e32 v9, v46, v83
	v_fmac_f32_e32 v11, v47, v83
	s_waitcnt lgkmcnt(7)
	v_fmac_f32_e32 v19, v66, v89
	s_waitcnt lgkmcnt(5)
	v_dual_fmac_f32 v7, v70, v89 :: v_dual_fmac_f32 v12, v33, v83
	ds_load_2addr_b64 v[33:36], v22 offset0:23 offset1:24
	ds_load_2addr_b32 v[75:76], v22 offset0:51 offset1:52
	ds_load_2addr_b32 v[77:78], v22 offset0:53 offset1:54
	s_waitcnt vmcnt(13) lgkmcnt(4)
	v_fmac_f32_e32 v19, v56, v90
	ds_load_2addr_b32 v[79:80], v22 offset0:55 offset1:56
	ds_load_2addr_b32 v[81:82], v22 offset0:57 offset1:58
	v_fmac_f32_e32 v17, v38, v83
	s_waitcnt lgkmcnt(5)
	v_dual_fmac_f32 v18, v39, v83 :: v_dual_fmac_f32 v7, v60, v90
	v_dual_fmac_f32 v4, v41, v83 :: v_dual_fmac_f32 v9, v72, v89
	v_dual_fmac_f32 v6, v43, v83 :: v_dual_fmac_f32 v11, v73, v89
	v_fmac_f32_e32 v8, v45, v83
	v_fmac_f32_e32 v10, v48, v83
	v_dual_fmac_f32 v5, v68, v89 :: v_dual_fmac_f32 v16, v37, v83
	ds_load_2addr_b32 v[83:84], v22 offset0:59 offset1:60
	ds_load_2addr_b32 v[85:86], v22 offset0:61 offset1:62
	ds_load_2addr_b32 v[87:88], v22 offset0:63 offset1:64
	ds_load_b128 v[37:40], v22 offset:272
	v_fmac_f32_e32 v13, v50, v90
	v_dual_fmac_f32 v5, v58, v90 :: v_dual_fmac_f32 v12, v1, v89
	ds_load_2addr_b32 v[1:2], v22 offset0:65 offset1:66
	v_fmac_f32_e32 v15, v62, v89
	v_fmac_f32_e32 v17, v64, v89
	s_waitcnt vmcnt(12) lgkmcnt(5)
	v_dual_fmac_f32 v18, v65, v89 :: v_dual_fmac_f32 v19, v82, v91
	ds_load_b128 v[41:44], v22 offset:288
	ds_load_b128 v[45:48], v22 offset:304
	v_dual_fmac_f32 v15, v52, v90 :: v_dual_fmac_f32 v14, v61, v89
	v_dual_fmac_f32 v17, v54, v90 :: v_dual_fmac_f32 v16, v63, v89
	v_fmac_f32_e32 v6, v69, v89
	ds_load_2addr_b32 v[61:62], v22 offset0:85 offset1:86
	v_fmac_f32_e32 v9, v34, v90
	s_waitcnt lgkmcnt(6)
	v_dual_fmac_f32 v7, v86, v91 :: v_dual_fmac_f32 v8, v71, v89
	v_dual_fmac_f32 v11, v35, v90 :: v_dual_fmac_f32 v10, v74, v89
	v_dual_fmac_f32 v13, v76, v91 :: v_dual_fmac_f32 v4, v67, v89
	v_dual_fmac_f32 v15, v78, v91 :: v_dual_fmac_f32 v12, v49, v90
	v_dual_fmac_f32 v17, v80, v91 :: v_dual_fmac_f32 v14, v51, v90
	ds_load_b128 v[49:52], v22 offset:320
	v_dual_fmac_f32 v18, v55, v90 :: v_dual_fmac_f32 v5, v84, v91
	s_waitcnt vmcnt(11) lgkmcnt(2)
	v_dual_fmac_f32 v6, v59, v90 :: v_dual_fmac_f32 v7, v48, v92
	v_dual_fmac_f32 v13, v38, v92 :: v_dual_fmac_f32 v4, v57, v90
	s_delay_alu instid0(VALU_DEP_3)
	v_fmac_f32_e32 v5, v46, v92
	ds_load_2addr_b32 v[57:58], v22 offset0:87 offset1:88
	ds_load_2addr_b32 v[59:60], v22 offset0:89 offset1:90
	ds_load_2addr_b32 v[63:64], v22 offset0:91 offset1:92
	ds_load_2addr_b32 v[65:66], v22 offset0:93 offset1:94
	ds_load_2addr_b32 v[67:68], v22 offset0:95 offset1:96
	ds_load_2addr_b32 v[69:70], v22 offset0:97 offset1:98
	ds_load_2addr_b32 v[71:72], v22 offset0:99 offset1:100
	v_dual_fmac_f32 v9, v88, v91 :: v_dual_fmac_f32 v8, v33, v90
	v_dual_fmac_f32 v11, v1, v91 :: v_dual_fmac_f32 v10, v36, v90
	ds_load_2addr_b64 v[33:36], v22 offset0:51 offset1:52
	v_dual_fmac_f32 v16, v53, v90 :: v_dual_fmac_f32 v19, v44, v92
	ds_load_2addr_b64 v[53:56], v22 offset0:53 offset1:54
	v_dual_fmac_f32 v15, v40, v92 :: v_dual_fmac_f32 v12, v75, v91
	s_waitcnt vmcnt(10) lgkmcnt(10)
	v_dual_fmac_f32 v13, v62, v93 :: v_dual_fmac_f32 v18, v81, v91
	v_dual_fmac_f32 v17, v42, v92 :: v_dual_fmac_f32 v14, v77, v91
	v_fmac_f32_e32 v16, v79, v91
	v_fmac_f32_e32 v4, v83, v91
	ds_load_2addr_b32 v[73:74], v22 offset0:119 offset1:120
	ds_load_2addr_b32 v[75:76], v22 offset0:121 offset1:122
	s_waitcnt lgkmcnt(6)
	v_dual_fmac_f32 v6, v85, v91 :: v_dual_fmac_f32 v7, v68, v93
	v_dual_fmac_f32 v11, v51, v92 :: v_dual_fmac_f32 v10, v2, v91
	v_dual_fmac_f32 v15, v58, v93 :: v_dual_fmac_f32 v12, v37, v92
	v_dual_fmac_f32 v14, v39, v92 :: v_dual_fmac_f32 v19, v64, v93
	ds_load_2addr_b64 v[37:40], v22 offset0:55 offset1:56
	v_dual_fmac_f32 v17, v60, v93 :: v_dual_fmac_f32 v16, v41, v92
	s_waitcnt vmcnt(9) lgkmcnt(4)
	v_dual_fmac_f32 v13, v34, v94 :: v_dual_fmac_f32 v18, v43, v92
	s_waitcnt lgkmcnt(3)
	v_fmac_f32_e32 v19, v56, v94
	ds_load_2addr_b64 v[41:44], v22 offset0:57 offset1:58
	v_fmac_f32_e32 v6, v47, v92
	ds_load_2addr_b32 v[77:78], v22 offset0:123 offset1:124
	ds_load_2addr_b32 v[79:80], v22 offset0:125 offset1:126
	ds_load_2addr_b32 v[81:82], v22 offset0:127 offset1:128
	ds_load_2addr_b32 v[1:2], v22 offset0:129 offset1:130
	ds_load_2addr_b32 v[83:84], v22 offset0:131 offset1:132
	ds_load_2addr_b32 v[85:86], v22 offset0:133 offset1:134
	v_dual_fmac_f32 v5, v66, v93 :: v_dual_fmac_f32 v4, v45, v92
	ds_load_b128 v[45:48], v22 offset:544
	v_dual_fmac_f32 v9, v50, v92 :: v_dual_fmac_f32 v8, v87, v91
	v_dual_fmac_f32 v15, v36, v94 :: v_dual_fmac_f32 v12, v61, v93
	s_waitcnt vmcnt(8) lgkmcnt(10)
	v_dual_fmac_f32 v13, v74, v95 :: v_dual_fmac_f32 v14, v57, v93
	v_fmac_f32_e32 v17, v54, v94
	s_waitcnt lgkmcnt(9)
	v_dual_fmac_f32 v15, v76, v95 :: v_dual_fmac_f32 v16, v59, v93
	v_dual_fmac_f32 v9, v70, v93 :: v_dual_fmac_f32 v8, v49, v92
	v_dual_fmac_f32 v11, v71, v93 :: v_dual_fmac_f32 v10, v52, v92
	ds_load_b128 v[49:52], v22 offset:560
	v_fmac_f32_e32 v18, v63, v93
	s_waitcnt lgkmcnt(6)
	v_dual_fmac_f32 v12, v33, v94 :: v_dual_fmac_f32 v19, v80, v95
	v_fmac_f32_e32 v14, v35, v94
	ds_load_b128 v[33:36], v22 offset:576
	s_waitcnt vmcnt(7) lgkmcnt(2)
	v_fmac_f32_e32 v13, v46, v96
	v_dual_fmac_f32 v17, v78, v95 :: v_dual_fmac_f32 v16, v53, v94
	v_dual_fmac_f32 v15, v48, v96 :: v_dual_fmac_f32 v18, v55, v94
	ds_load_b128 v[53:56], v22 offset:592
	ds_load_2addr_b32 v[61:62], v22 offset0:153 offset1:154
	ds_load_2addr_b32 v[63:64], v22 offset0:155 offset1:156
	v_dual_fmac_f32 v5, v38, v94 :: v_dual_fmac_f32 v4, v65, v93
	v_dual_fmac_f32 v7, v40, v94 :: v_dual_fmac_f32 v6, v67, v93
	ds_load_2addr_b32 v[65:66], v22 offset0:157 offset1:158
	ds_load_2addr_b32 v[67:68], v22 offset0:159 offset1:160
	ds_load_2addr_b32 v[87:88], v22 offset0:161 offset1:162
	v_fmac_f32_e32 v9, v42, v94
	v_dual_fmac_f32 v7, v2, v95 :: v_dual_fmac_f32 v8, v69, v93
	ds_load_2addr_b32 v[69:70], v22 offset0:163 offset1:164
	v_dual_fmac_f32 v11, v43, v94 :: v_dual_fmac_f32 v10, v72, v93
	ds_load_2addr_b32 v[71:72], v22 offset0:165 offset1:166
	s_waitcnt lgkmcnt(8)
	v_dual_fmac_f32 v6, v39, v94 :: v_dual_fmac_f32 v7, v36, v96
	v_fmac_f32_e32 v12, v73, v95
	v_fmac_f32_e32 v14, v75, v95
	v_dual_fmac_f32 v5, v82, v95 :: v_dual_fmac_f32 v4, v37, v94
	ds_load_2addr_b32 v[89:90], v22 offset0:167 offset1:168
	ds_load_2addr_b64 v[37:40], v22 offset0:85 offset1:86
	ds_load_2addr_b64 v[57:60], v22 offset0:89 offset1:90
	v_fmac_f32_e32 v19, v52, v96
	v_fmac_f32_e32 v5, v34, v96
	v_dual_fmac_f32 v9, v84, v95 :: v_dual_fmac_f32 v8, v41, v94
	v_dual_fmac_f32 v11, v85, v95 :: v_dual_fmac_f32 v10, v44, v94
	ds_load_2addr_b64 v[41:44], v22 offset0:87 offset1:88
	s_waitcnt vmcnt(6) lgkmcnt(10)
	v_fmac_f32_e32 v13, v62, v97
	s_waitcnt lgkmcnt(9)
	v_dual_fmac_f32 v15, v64, v97 :: v_dual_fmac_f32 v12, v45, v96
	s_waitcnt lgkmcnt(7)
	v_dual_fmac_f32 v14, v47, v96 :: v_dual_fmac_f32 v19, v68, v97
	ds_load_2addr_b64 v[45:48], v22 offset0:91 offset1:92
	ds_load_2addr_b32 v[73:74], v22 offset0:187 offset1:188
	ds_load_2addr_b32 v[75:76], v22 offset0:189 offset1:190
	v_dual_fmac_f32 v18, v79, v95 :: v_dual_fmac_f32 v17, v50, v96
	v_fmac_f32_e32 v16, v77, v95
	s_waitcnt lgkmcnt(9)
	v_dual_fmac_f32 v4, v81, v95 :: v_dual_fmac_f32 v5, v88, v97
	ds_load_2addr_b32 v[77:78], v22 offset0:191 offset1:192
	s_waitcnt lgkmcnt(9)
	v_dual_fmac_f32 v6, v1, v95 :: v_dual_fmac_f32 v7, v70, v97
	ds_load_2addr_b32 v[1:2], v22 offset0:193 offset1:194
	ds_load_2addr_b32 v[79:80], v22 offset0:195 offset1:196
	ds_load_2addr_b32 v[81:82], v22 offset0:197 offset1:198
	v_dual_fmac_f32 v9, v54, v96 :: v_dual_fmac_f32 v8, v83, v95
	v_dual_fmac_f32 v11, v55, v96 :: v_dual_fmac_f32 v10, v86, v95
	s_waitcnt vmcnt(5) lgkmcnt(8)
	v_dual_fmac_f32 v4, v33, v96 :: v_dual_fmac_f32 v5, v58, v98
	v_dual_fmac_f32 v6, v35, v96 :: v_dual_fmac_f32 v7, v60, v98
	ds_load_2addr_b32 v[83:84], v22 offset0:199 offset1:200
	ds_load_2addr_b32 v[85:86], v22 offset0:201 offset1:202
	ds_load_b128 v[33:36], v22 offset:816
	v_dual_fmac_f32 v9, v72, v97 :: v_dual_fmac_f32 v8, v53, v96
	v_dual_fmac_f32 v11, v89, v97 :: v_dual_fmac_f32 v10, v56, v96
	ds_load_b128 v[53:56], v22 offset:848
	v_dual_fmac_f32 v17, v66, v97 :: v_dual_fmac_f32 v16, v49, v96
	v_fmac_f32_e32 v13, v38, v98
	v_dual_fmac_f32 v15, v40, v98 :: v_dual_fmac_f32 v12, v61, v97
	v_fmac_f32_e32 v14, v63, v97
	s_waitcnt lgkmcnt(11)
	v_dual_fmac_f32 v18, v51, v96 :: v_dual_fmac_f32 v19, v44, v98
	ds_load_b128 v[49:52], v22 offset:832
	ds_load_2addr_b32 v[61:62], v22 offset0:221 offset1:222
	v_fmac_f32_e32 v17, v42, v98
	s_waitcnt vmcnt(4) lgkmcnt(11)
	v_dual_fmac_f32 v13, v74, v99 :: v_dual_fmac_f32 v16, v65, v97
	s_waitcnt lgkmcnt(10)
	v_dual_fmac_f32 v15, v76, v99 :: v_dual_fmac_f32 v12, v37, v98
	s_waitcnt lgkmcnt(9)
	v_dual_fmac_f32 v14, v39, v98 :: v_dual_fmac_f32 v17, v78, v99
	ds_load_b128 v[37:40], v22 offset:864
	ds_load_2addr_b32 v[63:64], v22 offset0:223 offset1:224
	ds_load_2addr_b32 v[65:66], v22 offset0:225 offset1:226
	s_waitcnt lgkmcnt(11)
	v_dual_fmac_f32 v18, v67, v97 :: v_dual_fmac_f32 v19, v2, v99
	ds_load_2addr_b32 v[67:68], v22 offset0:227 offset1:228
	s_waitcnt lgkmcnt(10)
	v_dual_fmac_f32 v6, v69, v97 :: v_dual_fmac_f32 v7, v82, v99
	ds_load_2addr_b32 v[69:70], v22 offset0:229 offset1:230
	v_dual_fmac_f32 v4, v87, v97 :: v_dual_fmac_f32 v5, v80, v99
	ds_load_2addr_b32 v[87:88], v22 offset0:231 offset1:232
	ds_load_2addr_b32 v[91:92], v22 offset0:233 offset1:234
	v_dual_fmac_f32 v9, v46, v98 :: v_dual_fmac_f32 v8, v71, v97
	v_fmac_f32_e32 v11, v47, v98
	s_waitcnt vmcnt(3) lgkmcnt(9)
	v_fmac_f32_e32 v5, v54, v100
	v_dual_fmac_f32 v10, v90, v97 :: v_dual_fmac_f32 v7, v56, v100
	s_waitcnt lgkmcnt(8)
	v_dual_fmac_f32 v18, v43, v98 :: v_dual_fmac_f32 v19, v52, v100
	v_dual_fmac_f32 v4, v57, v98 :: v_dual_fmac_f32 v9, v84, v99
	v_dual_fmac_f32 v6, v59, v98 :: v_dual_fmac_f32 v11, v85, v99
	ds_load_2addr_b32 v[71:72], v22 offset0:235 offset1:236
	s_waitcnt lgkmcnt(7)
	v_dual_fmac_f32 v8, v45, v98 :: v_dual_fmac_f32 v9, v38, v100
	v_dual_fmac_f32 v10, v48, v98 :: v_dual_fmac_f32 v11, v39, v100
	v_dual_fmac_f32 v13, v34, v100 :: v_dual_fmac_f32 v16, v41, v98
	v_fmac_f32_e32 v17, v50, v100
	ds_load_2addr_b64 v[41:44], v22 offset0:119 offset1:120
	ds_load_2addr_b64 v[45:48], v22 offset0:121 offset1:122
	v_dual_fmac_f32 v15, v36, v100 :: v_dual_fmac_f32 v12, v73, v99
	s_waitcnt vmcnt(2)
	v_dual_fmac_f32 v13, v62, v101 :: v_dual_fmac_f32 v14, v75, v99
	ds_load_2addr_b64 v[57:60], v22 offset0:123 offset1:124
	s_waitcnt lgkmcnt(6)
	v_dual_fmac_f32 v16, v77, v99 :: v_dual_fmac_f32 v5, v70, v101
	v_dual_fmac_f32 v12, v33, v100 :: v_dual_fmac_f32 v17, v66, v101
	s_waitcnt lgkmcnt(5)
	v_dual_fmac_f32 v18, v1, v99 :: v_dual_fmac_f32 v7, v88, v101
	v_dual_fmac_f32 v15, v64, v101 :: v_dual_fmac_f32 v14, v35, v100
	v_fmac_f32_e32 v19, v68, v101
	ds_load_2addr_b64 v[33:36], v22 offset0:125 offset1:126
	ds_load_2addr_b32 v[73:74], v23 offset1:1
	ds_load_2addr_b32 v[1:2], v24 offset1:1
	s_waitcnt lgkmcnt(7)
	v_dual_fmac_f32 v16, v49, v100 :: v_dual_fmac_f32 v9, v92, v101
	s_waitcnt vmcnt(1) lgkmcnt(5)
	v_dual_fmac_f32 v18, v51, v100 :: v_dual_fmac_f32 v13, v42, v102
	ds_load_2addr_b32 v[49:50], v25 offset1:1
	ds_load_2addr_b32 v[51:52], v26 offset1:1
	v_dual_fmac_f32 v4, v79, v99 :: v_dual_fmac_f32 v15, v44, v102
	ds_load_2addr_b32 v[75:76], v27 offset1:1
	ds_load_2addr_b32 v[77:78], v30 offset1:1
	ds_load_2addr_b32 v[79:80], v31 offset1:1
	v_dual_fmac_f32 v6, v81, v99 :: v_dual_fmac_f32 v11, v71, v101
	ds_load_2addr_b32 v[81:82], v32 offset1:1
	s_waitcnt lgkmcnt(10)
	v_dual_fmac_f32 v8, v83, v99 :: v_dual_fmac_f32 v17, v46, v102
	v_dual_fmac_f32 v10, v86, v99 :: v_dual_fmac_f32 v19, v48, v102
	s_waitcnt lgkmcnt(9)
	v_dual_fmac_f32 v4, v53, v100 :: v_dual_fmac_f32 v5, v58, v102
	v_dual_fmac_f32 v6, v55, v100 :: v_dual_fmac_f32 v7, v60, v102
	s_waitcnt lgkmcnt(8)
	v_dual_fmac_f32 v8, v37, v100 :: v_dual_fmac_f32 v9, v34, v102
	v_dual_fmac_f32 v10, v40, v100 :: v_dual_fmac_f32 v11, v35, v102
	s_waitcnt vmcnt(0) lgkmcnt(7)
	v_dual_fmac_f32 v12, v61, v101 :: v_dual_fmac_f32 v13, v74, v103
	s_waitcnt lgkmcnt(6)
	v_dual_fmac_f32 v14, v63, v101 :: v_dual_fmac_f32 v15, v2, v103
	s_waitcnt lgkmcnt(5)
	v_dual_fmac_f32 v16, v65, v101 :: v_dual_fmac_f32 v17, v50, v103
	s_waitcnt lgkmcnt(4)
	v_dual_fmac_f32 v18, v67, v101 :: v_dual_fmac_f32 v19, v52, v103
	s_waitcnt lgkmcnt(3)
	v_dual_fmac_f32 v4, v69, v101 :: v_dual_fmac_f32 v5, v76, v103
	s_waitcnt lgkmcnt(2)
	v_dual_fmac_f32 v6, v87, v101 :: v_dual_fmac_f32 v7, v78, v103
	s_waitcnt lgkmcnt(1)
	v_dual_fmac_f32 v8, v91, v101 :: v_dual_fmac_f32 v9, v80, v103
	s_waitcnt lgkmcnt(0)
	v_dual_fmac_f32 v10, v72, v101 :: v_dual_fmac_f32 v11, v81, v103
	v_fmac_f32_e32 v12, v41, v102
	v_fmac_f32_e32 v14, v43, v102
	v_fmac_f32_e32 v16, v45, v102
	v_fmac_f32_e32 v18, v47, v102
	v_fmac_f32_e32 v4, v57, v102
	v_fmac_f32_e32 v6, v59, v102
	v_fmac_f32_e32 v8, v33, v102
	v_fmac_f32_e32 v10, v36, v102
	v_fmac_f32_e32 v12, v73, v103
	v_fmac_f32_e32 v14, v1, v103
	v_fmac_f32_e32 v16, v49, v103
	v_fmac_f32_e32 v18, v51, v103
	v_fmac_f32_e32 v4, v75, v103
	v_fmac_f32_e32 v6, v77, v103
	v_fmac_f32_e32 v8, v79, v103
	v_fmac_f32_e32 v10, v82, v103
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB0_5
; %bb.6:                                ; %Flow
	v_dual_mov_b32 v1, v20 :: v_dual_mov_b32 v0, v21
	s_branch .LBB0_8
.LBB0_7:
	v_dual_mov_b32 v12, s8 :: v_dual_mov_b32 v13, s8
	v_dual_mov_b32 v14, s8 :: v_dual_mov_b32 v15, s8
	v_dual_mov_b32 v16, s8 :: v_dual_mov_b32 v17, s8
	v_dual_mov_b32 v18, s8 :: v_dual_mov_b32 v19, s8
	v_dual_mov_b32 v4, s8 :: v_dual_mov_b32 v5, s8
	v_dual_mov_b32 v6, s8 :: v_dual_mov_b32 v7, s8
	v_dual_mov_b32 v8, s8 :: v_dual_mov_b32 v9, s8
	v_dual_mov_b32 v11, s8 :: v_dual_mov_b32 v10, s8
.LBB0_8:                                ; %._crit_edge
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_mov_b32 v1, 0 :: v_dual_lshlrev_b32 v2, 11, v1
	s_lshl_b32 s2, s15, 15
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_add3_u32 v0, s2, v2, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_mov_b32_e32 v3, v1
	v_mov_b32_e32 v21, v1
	v_mov_b32_e32 v23, v1
	v_dual_mov_b32 v27, v1 :: v_dual_add_nc_u32 v22, 0x1800, v0
	v_add_nc_u32_e32 v2, 0x800, v0
	v_lshlrev_b64 v[24:25], 2, v[0:1]
	v_add_nc_u32_e32 v20, 0x1000, v0
	v_add_nc_u32_e32 v26, 0x2000, v0
	v_lshlrev_b64 v[22:23], 2, v[22:23]
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	v_dual_mov_b32 v29, v1 :: v_dual_add_nc_u32 v28, 0x2800, v0
	v_lshlrev_b64 v[20:21], 2, v[20:21]
	v_add_co_u32 v24, vcc_lo, s0, v24
	v_add_co_ci_u32_e32 v25, vcc_lo, s1, v25, vcc_lo
	v_add_co_u32 v2, vcc_lo, s0, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
	v_add_co_u32 v20, vcc_lo, s0, v20
	v_lshlrev_b64 v[26:27], 2, v[26:27]
	v_dual_mov_b32 v31, v1 :: v_dual_add_nc_u32 v30, 0x3000, v0
	v_add_co_ci_u32_e32 v21, vcc_lo, s1, v21, vcc_lo
	v_add_co_u32 v22, vcc_lo, s0, v22
	v_lshlrev_b64 v[28:29], 2, v[28:29]
	v_dual_mov_b32 v33, v1 :: v_dual_add_nc_u32 v32, 0x3800, v0
	v_add_co_ci_u32_e32 v23, vcc_lo, s1, v23, vcc_lo
	v_add_co_u32 v26, vcc_lo, s0, v26
	v_lshlrev_b64 v[30:31], 2, v[30:31]
	v_add_co_ci_u32_e32 v27, vcc_lo, s1, v27, vcc_lo
	v_add_co_u32 v28, vcc_lo, s0, v28
	v_lshlrev_b64 v[32:33], 2, v[32:33]
	v_add_co_ci_u32_e32 v29, vcc_lo, s1, v29, vcc_lo
	v_dual_mov_b32 v35, v1 :: v_dual_add_nc_u32 v34, 0x4000, v0
	v_add_co_u32 v30, vcc_lo, s0, v30
	v_add_co_ci_u32_e32 v31, vcc_lo, s1, v31, vcc_lo
	v_dual_mov_b32 v37, v1 :: v_dual_add_nc_u32 v36, 0x4800, v0
	v_add_co_u32 v32, vcc_lo, s0, v32
	v_lshlrev_b64 v[34:35], 2, v[34:35]
	v_add_co_ci_u32_e32 v33, vcc_lo, s1, v33, vcc_lo
	s_clause 0x7
	global_store_b32 v[24:25], v12, off
	global_store_b32 v[2:3], v13, off
	global_store_b32 v[20:21], v14, off
	global_store_b32 v[22:23], v15, off
	global_store_b32 v[26:27], v16, off
	global_store_b32 v[28:29], v17, off
	global_store_b32 v[30:31], v18, off
	global_store_b32 v[32:33], v19, off
	v_dual_mov_b32 v13, v1 :: v_dual_add_nc_u32 v12, 0x5000, v0
	v_lshlrev_b64 v[2:3], 2, v[36:37]
	v_dual_mov_b32 v17, v1 :: v_dual_add_nc_u32 v16, 0x5800, v0
	v_add_co_u32 v14, vcc_lo, s0, v34
	s_delay_alu instid0(VALU_DEP_4)
	v_lshlrev_b64 v[12:13], 2, v[12:13]
	v_dual_mov_b32 v19, v1 :: v_dual_add_nc_u32 v18, 0x6000, v0
	v_add_co_ci_u32_e32 v15, vcc_lo, s1, v35, vcc_lo
	v_add_co_u32 v2, vcc_lo, s0, v2
	v_lshlrev_b64 v[16:17], 2, v[16:17]
	v_dual_mov_b32 v21, v1 :: v_dual_add_nc_u32 v20, 0x6800, v0
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
	v_add_co_u32 v12, vcc_lo, s0, v12
	v_lshlrev_b64 v[18:19], 2, v[18:19]
	v_dual_mov_b32 v23, v1 :: v_dual_add_nc_u32 v22, 0x7000, v0
	v_add_co_ci_u32_e32 v13, vcc_lo, s1, v13, vcc_lo
	v_add_co_u32 v16, vcc_lo, s0, v16
	v_lshlrev_b64 v[20:21], 2, v[20:21]
	v_add_nc_u32_e32 v0, 0x7800, v0
	v_add_co_ci_u32_e32 v17, vcc_lo, s1, v17, vcc_lo
	v_add_co_u32 v18, vcc_lo, s0, v18
	v_lshlrev_b64 v[22:23], 2, v[22:23]
	v_add_co_ci_u32_e32 v19, vcc_lo, s1, v19, vcc_lo
	v_add_co_u32 v20, vcc_lo, s0, v20
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	v_add_co_ci_u32_e32 v21, vcc_lo, s1, v21, vcc_lo
	v_add_co_u32 v22, vcc_lo, s0, v22
	v_add_co_ci_u32_e32 v23, vcc_lo, s1, v23, vcc_lo
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_u32 v0, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	s_clause 0x7
	global_store_b32 v[14:15], v4, off
	global_store_b32 v[2:3], v5, off
	global_store_b32 v[12:13], v6, off
	global_store_b32 v[16:17], v7, off
	global_store_b32 v[18:19], v8, off
	global_store_b32 v[20:21], v9, off
	global_store_b32 v[22:23], v11, off
	global_store_b32 v[0:1], v10, off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z6matmulPfS_S_ii
		.amdhsa_group_segment_fixed_size 1088
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 32
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 104
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z6matmulPfS_S_ii, .Lfunc_end0-_Z6matmulPfS_S_ii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 3788
; NumSgprs: 18
; NumVgprs: 104
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 1088 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 12
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 104
; Occupancy: 12
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
    .group_segment_fixed_size: 1088
    .kernarg_segment_align: 8
    .kernarg_segment_size: 32
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z6matmulPfS_S_ii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z6matmulPfS_S_ii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     104
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
