#include <stdio.h>
#include <stdlib.h>
#include <unistd.h>
#include <time.h>
#include <cuda.h>
#include <math.h>


__global__ void kernel_func(int *ccurrent, int *cnext,int arraysize)
{
	int row = blockIdx.y * blockDim.y + threadIdx.y;// get the row number
	int col = blockIdx.x * blockDim.x + threadIdx.x;// get the col number
	if(row >= arraysize || col >= arraysize)return;// check if the dimensions are over the dims of the array
	/*Because the ccurent array is a flattened 2d array we access each element ccurent[(row * arraysize) + column]*/
	int neighbours = 0;//start checking the neighbours
	if((col-1) < 0){if(ccurrent[row * arraysize + (arraysize -1)] == 1 )neighbours++;}//West neighbour
    else if(ccurrent[row * arraysize +(col-1)] == 1 )neighbours++;//west

    if((row+1) > (arraysize-1))//South-West neighbour
    {
     	if((col-1) < 0){if(ccurrent[(arraysize-1)] == 1)neighbours++;}
      	else if(ccurrent[(col-1)] == 1)neighbours++;
    }
    else if((col-1) < 0){if(ccurrent[(row+1) * arraysize + (arraysize-1)] == 1)neighbours++;}//sw
    else if(ccurrent[(row+1) * arraysize +(col-1)] == 1 )neighbours++;//sw
                
    if((row+1) > arraysize-1){if(ccurrent[col] == 1)neighbours++;}//South neighbour
    else if(ccurrent[(row+1) * arraysize + col] == 1 )neighbours++;//s
                
    if((row+1) > (arraysize-1))//South- East neighbour
    {
        if((col+1) > (arraysize-1)){if(ccurrent[0] == 1)neighbours++;}
    	else if(ccurrent[col+1] == 1)neighbours++;
    }
    else if((col+1) > (arraysize-1)){if(ccurrent[(row+1) * arraysize] == 1)neighbours++;}//se
    else if(ccurrent[(row+1) * arraysize + col+1] == 1 )neighbours++;//se
                
    if((col+1) > (arraysize-1)){if(ccurrent[row * arraysize] == 1)neighbours++;}//East neighbour
    else if(ccurrent[row * arraysize + col+1] == 1 )neighbours++;//e

    if((row-1) < 0)//North- East neighbour
    {
    	if((col+1) > (arraysize-1) ){if(ccurrent[(arraysize-1) * arraysize] == 1)neighbours++;}
        else if(ccurrent[(arraysize-1)* arraysize + col+1] == 1)neighbours++;
    }
    else if((col+1) > arraysize-1){if(ccurrent[(row-1) * arraysize] == 1)neighbours++;}//ne
    else if(ccurrent[(row-1) * arraysize + col+1] == 1 )neighbours++;//ne
                
    if((row-1) < 0){if(ccurrent[(arraysize-1)* arraysize + col])neighbours++;}//North neighbour
    else if(ccurrent[(row-1) * arraysize + col] == 1) neighbours++;//n
                
    if((row-1) < 0)//North- West neighbour
    {
    	if((col-1) < 0 ){if(ccurrent[(arraysize-1) * arraysize + arraysize-1] == 1)neighbours++;}
        else if(ccurrent[(arraysize-1) * arraysize + col-1] == 1)neighbours++;
    }
    else if((col-1) < 0){if(ccurrent[(row-1) * arraysize + arraysize-1] == 1)neighbours++;}//nw
    else if(ccurrent[(row-1) * arraysize + col-1] == 1 )neighbours++;//nw
                   
    if(ccurrent[row * arraysize +col] == 0)
    {
    	if(neighbours == 3)cnext[row * arraysize + col]=1;//If the array[row][col] = 1 check the number of neighbours and set the next value 
        else cnext[row * arraysize + col] = 0;
    }
    if(ccurrent[row * arraysize + col] == 1)
    {
    	if(neighbours>1 && neighbours<4)cnext[row * arraysize + col] = 1;
    	else cnext[row * arraysize + col] = 0;
    }
}


__global__ void kernel_checksimilarity(int *ccurrent, int *cnext, int arraysize, int *dsame, int *ddead)
{
	int row = blockIdx.y * blockDim.y + threadIdx.y;// get the row number
	int col = blockIdx.x * blockDim.x + threadIdx.x;// get the col number
	if(row >= arraysize || col >= arraysize)return;// check if the dimensions are over the dims of the array
	if(ccurrent[row * arraysize + col] != cnext[row * arraysize + col]) *dsame = 0;
	if(cnext[row * arraysize + col] == 1)*ddead = 0;
}



int main(int argc, char *argv[])
{
	srand(time(NULL));
	unsigned int i, j, arraysize = 50,check = 31;
	int *same , *dead;
	int *dsame = NULL, *ddead = NULL;
	same = (int*)malloc(sizeof(int));
	dead = (int*)malloc(sizeof(int));
	cudaMalloc(&dsame,sizeof(int));
	cudaMalloc(&ddead,sizeof(int));
	unsigned long generations = 50;
	char c;
	while((c = getopt (argc, argv, "g:s:")) != -1)
	{
		switch(c)
		{
			case 'g':
				generations = atoi(optarg);
				break;
			case 's':
				arraysize = atoi(optarg);
				break;
			default:
				break;
		}		
	}
	//Host mallocs and initialization of the arrays
	int *currentdata = (int*)malloc(arraysize * arraysize * sizeof(int));
	int **current = (int**)malloc(arraysize * sizeof(int*));
	int *nextdata = (int*)malloc(arraysize *arraysize * sizeof(int));
	int **next = (int**)malloc(arraysize * sizeof(int*));
	for (i = 0; i < arraysize; ++i)
	{
		current[i] = &(currentdata[i*arraysize]);
		next[i] = &(nextdata[i*arraysize]);
	}
	for (i = 0; i < arraysize; ++i)
	{
		for (j= 0; j < arraysize; ++j)
		{
			current[i][j] = rand()%2;
			next[i][j] = 0;
			//printf("%d ", current[i][j]);
		}
		//printf("\n");
	}
	//Device mallocs and transfer HostToDevice
	int *ccurrent = NULL;
	cudaMalloc(&ccurrent,(arraysize * arraysize * sizeof(int)));
	int *cnext = NULL;
	cudaMalloc(&cnext,(arraysize * arraysize * sizeof(int)));
	cudaMemcpy(ccurrent, currentdata, (arraysize * arraysize * sizeof(int)), cudaMemcpyHostToDevice);
	cudaMemcpy(cnext, nextdata, (arraysize * arraysize * sizeof(int)), cudaMemcpyHostToDevice);
	int *ctemp;
	//dim3 dimBlock(block_size, block_size);
	//dim3 dimGrid((arraysize + dimBlock.x - 1) / dimBlock.x,(arraysize + dimBlock.y - 1) / dimBlock.y);
	
	cudaDeviceProp myCUDA;
	if (cudaGetDeviceProperties(&myCUDA, 0) == cudaSuccess)
	{
	    printf("Using device %d: ", 0);
	    printf("%s; global mem: %dΒ; compute v%d.%d; clock: %d kHz\n",myCUDA.name, (int)myCUDA.totalGlobalMem, (int)myCUDA.major,(int)myCUDA.minor, (int)myCUDA.clockRate);
	}
	int threadsPerBlock = myCUDA.maxThreadsPerBlock;
	int temp = (int)sqrt(threadsPerBlock);
	printf("Maximum threads per block dimension = %d\n",temp);
	dim3 dimBlock(temp, temp);
	dim3 dimGrid((arraysize + dimBlock.x - 1) / dimBlock.x,(arraysize + dimBlock.y - 1) / dimBlock.y);
	float ttime;
	cudaEvent_t start, stop;//Start the clock

	cudaEventCreate(&start);
	cudaEventCreate(&stop);
	cudaEventRecord(start, 0);
	for (i = 0; i < generations; ++i)
	{
		kernel_func<<<dimGrid, dimBlock>>>(ccurrent,cnext,arraysize);//call the Device function
		cudaDeviceSynchronize();
		if((i%check) == 0)
		{
			*same = 1;
			*dead = 1;
			cudaMemcpy(dsame, same, sizeof(int), cudaMemcpyHostToDevice);
			cudaMemcpy(ddead, dead, sizeof(int), cudaMemcpyHostToDevice);
			kernel_checksimilarity<<<dimGrid,dimBlock>>>(ccurrent,cnext,arraysize,dsame,ddead);
			cudaDeviceSynchronize();
			cudaMemcpy(same, dsame, sizeof(int), cudaMemcpyDeviceToHost);
			cudaMemcpy(dead, ddead, sizeof(int), cudaMemcpyDeviceToHost);
			if((*same == 1) || (*dead == 1))break;
		}
		ctemp = ccurrent;//Change the arrays for the next generation
		ccurrent = cnext;
		cnext = ctemp;
		/*cudaMemcpy(currentdata, ccurrent, (arraysize * arraysize * sizeof(int)), cudaMemcpyDeviceToHost);//DevicetoHost transfer
		printf("In generation %d\n",i);
		for ( k = 0; k < arraysize; ++k)//print the array
		{
			for (j = 0; j < arraysize; ++j)
			{
				printf("%d ",current[k][j]);
			}
			printf("\n");
		}*/
	}
	cudaEventRecord(stop, 0);//stop the clock
	cudaEventSynchronize(stop);
	cudaEventElapsedTime(&ttime, start, stop);
	printf("\nProcess exited at generation: %d with arraysize: %d x %d, after:  %3.1f ms \n", i, arraysize, arraysize,ttime);
	if(*dead == 1)printf("Exited earlier because all cells are dead.\n");
	if(*same == 1)printf("Exited earlier because current and next generations are the same.\n");
	/*printf("Last version of the array\n");
	cudaMemcpy(currentdata, ccurrent, (arraysize * arraysize * sizeof(int)), cudaMemcpyDeviceToHost);
	for ( i = 0; i < arraysize; ++i)
	{
		for (j = 0; j < arraysize; ++j)
		{
			printf("%d ",current[i][j]);
		}
		printf("\n");
	}*/
	//Free the allocated memory

	cudaFree(ccurrent);
	cudaFree(cnext);
	cudaFree(dsame);
	cudaFree(ddead);
	free(same);
	free(dead);
	free(nextdata);
	free(next);
	free(currentdata);
	free(current);
	return 0;
}
	.file	"tmpxft_00315aaa_00000000-6_CUDA_game_of_life.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2043:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2043:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z34__device_stub__Z11kernel_funcPiS_iPiS_i
	.type	_Z34__device_stub__Z11kernel_funcPiS_iPiS_i, @function
_Z34__device_stub__Z11kernel_funcPiS_iPiS_i:
.LFB2065:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z11kernel_funcPiS_i(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L2:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2065:
	.size	_Z34__device_stub__Z11kernel_funcPiS_iPiS_i, .-_Z34__device_stub__Z11kernel_funcPiS_iPiS_i
	.globl	_Z11kernel_funcPiS_i
	.type	_Z11kernel_funcPiS_i, @function
_Z11kernel_funcPiS_i:
.LFB2066:
	.cfi_startproc
	endbr64
	jmp	_Z34__device_stub__Z11kernel_funcPiS_iPiS_i
	.cfi_endproc
.LFE2066:
	.size	_Z11kernel_funcPiS_i, .-_Z11kernel_funcPiS_i
	.globl	_Z49__device_stub__Z22kernel_checksimilarityPiS_iS_S_PiS_iS_S_
	.type	_Z49__device_stub__Z22kernel_checksimilarityPiS_iS_S_PiS_iS_S_, @function
_Z49__device_stub__Z22kernel_checksimilarityPiS_iS_S_PiS_iS_S_:
.LFB2067:
	.cfi_startproc
	endbr64
	subq	$168, %rsp
	.cfi_def_cfa_offset 176
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movl	%edx, 28(%rsp)
	leaq	48(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	56(%rsp), %rcx
	movq	%r8, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 152(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 112(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	28(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 144(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L8
	pushq	56(%rsp)
	.cfi_def_cfa_offset 184
	leaq	_Z22kernel_checksimilarityPiS_iS_S_(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 192
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 184
	popq	%rdx
	.cfi_def_cfa_offset 176
.L8:
	movq	152(%rsp), %rax
	subq	%fs:40, %rax
	je	.L10
	call	__stack_chk_fail@PLT
.L10:
	addq	$168, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2067:
	.size	_Z49__device_stub__Z22kernel_checksimilarityPiS_iS_S_PiS_iS_S_, .-_Z49__device_stub__Z22kernel_checksimilarityPiS_iS_S_PiS_iS_S_
	.globl	_Z22kernel_checksimilarityPiS_iS_S_
	.type	_Z22kernel_checksimilarityPiS_iS_S_, @function
_Z22kernel_checksimilarityPiS_iS_S_:
.LFB2068:
	.cfi_startproc
	endbr64
	jmp	_Z49__device_stub__Z22kernel_checksimilarityPiS_iS_S_PiS_iS_S_
	.cfi_endproc
.LFE2068:
	.size	_Z22kernel_checksimilarityPiS_iS_S_, .-_Z22kernel_checksimilarityPiS_iS_S_
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"g:s:"
.LC1:
	.string	"Using device %d: "
.LC2:
	.string	"%s; global mem: %d\316\222; compute v%d.%d; clock: %d kHz\n"
.LC3:
	.string	"Maximum threads per block dimension = %d\n"
.LC4:
	.string	"\nProcess exited at generation: %d with arraysize: %d x %d, after:  %3.1f ms \n"
.LC5:
	.string	"Exited earlier because all cells are dead.\n"
.LC6:
	.string	"Exited earlier because current and next generations are the same.\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2040:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	leaq	.LC0(%rip), %r15
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	movq	%rsi, %r14
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movl	%edi, %r13d
	xorl	%edi, %edi
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movl	$50, %ebx
	subq	$1176, %rsp
	.cfi_def_cfa_offset 1232
	movq	%fs:40, %rax
	movq	%rax, 1160(%rsp)
	xorl	%eax, %eax
	call	time@PLT
	movl	%eax, %edi
	call	srand@PLT
	xorl	%r9d, %r9d
	movl	$4, %edi
	movq	%r9, 56(%rsp)
	movq	%r9, 64(%rsp)
	call	malloc@PLT
	movl	$4, %edi
	movq	%rax, %r12
	call	malloc@PLT
	leaq	56(%rsp), %rdi
	movl	$4, %esi
	movq	%rax, %rbp
	call	cudaMalloc@PLT
	leaq	64(%rsp), %rdi
	movl	$4, %esi
	call	cudaMalloc@PLT
	movq	$50, 40(%rsp)
.L14:
	movq	%r15, %rdx
	movq	%r14, %rsi
	movl	%r13d, %edi
	call	getopt@PLT
	cmpb	$-1, %al
	je	.L39
	cmpb	$103, %al
	je	.L15
	cmpb	$115, %al
	jne	.L14
	movq	optarg(%rip), %rdi
	call	atoi@PLT
	movl	%eax, %ebx
	jmp	.L14
.L15:
	movq	optarg(%rip), %rdi
	call	atoi@PLT
	cltq
	movq	%rax, 40(%rsp)
	jmp	.L14
.L39:
	movl	%ebx, %r13d
	movl	%ebx, %r14d
	imull	%ebx, %r13d
	salq	$3, %r14
	leaq	0(,%r13,4), %rax
	movq	%rax, %rdi
	movq	%rax, 8(%rsp)
	call	malloc@PLT
	movq	%r14, %rdi
	movq	%rax, 16(%rsp)
	call	malloc@PLT
	movq	8(%rsp), %rdi
	movq	%rax, 24(%rsp)
	call	malloc@PLT
	movq	%r14, %rdi
	movq	%rax, 32(%rsp)
	call	malloc@PLT
	xorl	%ecx, %ecx
	xorl	%edx, %edx
	movq	%rax, %r14
.L19:
	cmpl	%ebx, %edx
	jnb	.L40
	movl	%ecx, %eax
	movq	16(%rsp), %rsi
	movq	24(%rsp), %rdi
	addl	%ebx, %ecx
	salq	$2, %rax
	addq	%rax, %rsi
	movq	%rsi, (%rdi,%rdx,8)
	movq	32(%rsp), %rsi
	addq	%rsi, %rax
	movq	%rax, (%r14,%rdx,8)
	incq	%rdx
	jmp	.L19
.L40:
	xorl	%r13d, %r13d
.L21:
	cmpl	%ebx, %r13d
	jnb	.L41
	xorl	%r15d, %r15d
.L22:
	call	rand@PLT
	movq	24(%rsp), %rcx
	xorl	%r8d, %r8d
	cltd
	movq	(%rcx,%r13,8), %rdi
	movl	$2, %ecx
	idivl	%ecx
	movq	(%r14,%r13,8), %rax
	movl	%r8d, (%rax,%r15,4)
	movl	%edx, (%rdi,%r15,4)
	incq	%r15
	cmpl	%ebx, %r15d
	jb	.L22
	incq	%r13
	jmp	.L21
.L41:
	xorl	%esi, %esi
	leaq	72(%rsp), %rdi
	leaq	128(%rsp), %r13
	movq	%rsi, 72(%rsp)
	movq	8(%rsp), %rsi
	call	cudaMalloc@PLT
	xorl	%edi, %edi
	movq	8(%rsp), %rsi
	movq	%rdi, 80(%rsp)
	leaq	80(%rsp), %rdi
	call	cudaMalloc@PLT
	movq	8(%rsp), %rdx
	movq	16(%rsp), %rsi
	movl	$1, %ecx
	movq	72(%rsp), %rdi
	call	cudaMemcpy@PLT
	movq	32(%rsp), %rsi
	movq	80(%rsp), %rdi
	movl	$1, %ecx
	movq	8(%rsp), %rdx
	call	cudaMemcpy@PLT
	xorl	%esi, %esi
	movq	%r13, %rdi
	call	cudaGetDeviceProperties_v2@PLT
	testl	%eax, %eax
	jne	.L23
	xorl	%edx, %edx
	leaq	.LC1(%rip), %rsi
	movl	$2, %edi
	call	__printf_chk@PLT
	movq	%r13, %rdx
	movl	$2, %edi
	leaq	.LC2(%rip), %rsi
	pushq	%rax
	.cfi_def_cfa_offset 1240
	movl	484(%rsp), %eax
	pushq	%rax
	.cfi_def_cfa_offset 1248
	movl	508(%rsp), %r9d
	xorl	%eax, %eax
	movl	504(%rsp), %r8d
	movl	432(%rsp), %ecx
	call	__printf_chk@PLT
	popq	%rdx
	.cfi_def_cfa_offset 1240
	popq	%rcx
	.cfi_def_cfa_offset 1232
.L23:
	cvtsi2sdl	448(%rsp), %xmm0
	xorl	%r15d, %r15d
	call	sqrt@PLT
	leaq	.LC3(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	cvttsd2sil	%xmm0, %r13d
	movl	%r13d, %edx
	call	__printf_chk@PLT
	leal	-1(%rbx,%r13), %eax
	xorl	%edx, %edx
	leaq	88(%rsp), %rdi
	divl	%r13d
	movl	$1, 112(%rsp)
	movl	$1, 124(%rsp)
	movl	%eax, 116(%rsp)
	movl	%eax, 120(%rsp)
	call	cudaEventCreate@PLT
	leaq	96(%rsp), %rdi
	call	cudaEventCreate@PLT
	movq	88(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
.L24:
	movq	40(%rsp), %rcx
	movl	%r15d, %eax
	cmpq	%rcx, %rax
	jnb	.L31
	movl	%r13d, 104(%rsp)
	movl	112(%rsp), %ecx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	116(%rsp), %rdi
	movl	124(%rsp), %esi
	movl	%r13d, 108(%rsp)
	movq	104(%rsp), %rdx
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L25
	movq	80(%rsp), %rsi
	movq	72(%rsp), %rdi
	movl	%ebx, %edx
	call	_Z34__device_stub__Z11kernel_funcPiS_iPiS_i
.L25:
	call	cudaDeviceSynchronize@PLT
	movl	%r15d, %eax
	movl	$31, %ecx
	xorl	%edx, %edx
	divl	%ecx
	testl	%edx, %edx
	je	.L26
.L32:
	movq	72(%rsp), %rax
	movq	80(%rsp), %rdx
	incl	%r15d
	movq	%rdx, 72(%rsp)
	movq	%rax, 80(%rsp)
	jmp	.L24
.L26:
	movl	$1, (%r12)
	movq	56(%rsp), %rdi
	movl	$1, %ecx
	movq	%r12, %rsi
	movl	$1, 0(%rbp)
	movl	$4, %edx
	call	cudaMemcpy@PLT
	movq	64(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbp, %rsi
	movl	$4, %edx
	call	cudaMemcpy@PLT
	movl	112(%rsp), %ecx
	movl	124(%rsp), %esi
	xorl	%r9d, %r9d
	movq	104(%rsp), %rdx
	movq	116(%rsp), %rdi
	xorl	%r8d, %r8d
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L27
	movq	64(%rsp), %r8
	movq	56(%rsp), %rcx
	movl	%ebx, %edx
	movq	80(%rsp), %rsi
	movq	72(%rsp), %rdi
	call	_Z49__device_stub__Z22kernel_checksimilarityPiS_iS_S_PiS_iS_S_
.L27:
	call	cudaDeviceSynchronize@PLT
	movq	56(%rsp), %rsi
	movl	$2, %ecx
	movq	%r12, %rdi
	movl	$4, %edx
	call	cudaMemcpy@PLT
	movq	64(%rsp), %rsi
	movl	$2, %ecx
	movq	%rbp, %rdi
	movl	$4, %edx
	call	cudaMemcpy@PLT
	cmpl	$1, (%r12)
	jne	.L28
.L31:
	movq	96(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movq	96(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movq	96(%rsp), %rdx
	movq	88(%rsp), %rsi
	leaq	52(%rsp), %rdi
	call	cudaEventElapsedTime@PLT
	movl	%ebx, %r8d
	movl	%ebx, %ecx
	movl	%r15d, %edx
	leaq	.LC4(%rip), %rsi
	movl	$2, %edi
	movb	$1, %al
	cvtss2sd	52(%rsp), %xmm0
	call	__printf_chk@PLT
	cmpl	$1, 0(%rbp)
	jne	.L30
	leaq	.LC5(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	jmp	.L30
.L28:
	cmpl	$1, 0(%rbp)
	jne	.L32
	jmp	.L31
.L30:
	cmpl	$1, (%r12)
	jne	.L34
	leaq	.LC6(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
.L34:
	movq	72(%rsp), %rdi
	call	cudaFree@PLT
	movq	80(%rsp), %rdi
	call	cudaFree@PLT
	movq	56(%rsp), %rdi
	call	cudaFree@PLT
	movq	64(%rsp), %rdi
	call	cudaFree@PLT
	movq	%r12, %rdi
	call	free@PLT
	movq	%rbp, %rdi
	call	free@PLT
	movq	32(%rsp), %rdi
	call	free@PLT
	movq	%r14, %rdi
	call	free@PLT
	movq	16(%rsp), %rdi
	call	free@PLT
	movq	24(%rsp), %rdi
	call	free@PLT
	movq	1160(%rsp), %rax
	subq	%fs:40, %rax
	je	.L35
	call	__stack_chk_fail@PLT
.L35:
	addq	$1176, %rsp
	.cfi_def_cfa_offset 56
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2040:
	.size	main, .-main
	.section	.rodata.str1.1
.LC7:
	.string	"_Z22kernel_checksimilarityPiS_iS_S_"
.LC8:
	.string	"_Z11kernel_funcPiS_i"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2070:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC7(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z22kernel_checksimilarityPiS_iS_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC8(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z11kernel_funcPiS_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2070:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <stdio.h>
#include <stdlib.h>
#include <unistd.h>
#include <time.h>
#include <hip/hip_runtime.h>
#include <math.h>


__global__ void kernel_func(int *ccurrent, int *cnext,int arraysize)
{
	int row = blockIdx.y * blockDim.y + threadIdx.y;// get the row number
	int col = blockIdx.x * blockDim.x + threadIdx.x;// get the col number
	if(row >= arraysize || col >= arraysize)return;// check if the dimensions are over the dims of the array
	/*Because the ccurent array is a flattened 2d array we access each element ccurent[(row * arraysize) + column]*/
	int neighbours = 0;//start checking the neighbours
	if((col-1) < 0){if(ccurrent[row * arraysize + (arraysize -1)] == 1 )neighbours++;}//West neighbour
    else if(ccurrent[row * arraysize +(col-1)] == 1 )neighbours++;//west

    if((row+1) > (arraysize-1))//South-West neighbour
    {
     	if((col-1) < 0){if(ccurrent[(arraysize-1)] == 1)neighbours++;}
      	else if(ccurrent[(col-1)] == 1)neighbours++;
    }
    else if((col-1) < 0){if(ccurrent[(row+1) * arraysize + (arraysize-1)] == 1)neighbours++;}//sw
    else if(ccurrent[(row+1) * arraysize +(col-1)] == 1 )neighbours++;//sw
                
    if((row+1) > arraysize-1){if(ccurrent[col] == 1)neighbours++;}//South neighbour
    else if(ccurrent[(row+1) * arraysize + col] == 1 )neighbours++;//s
                
    if((row+1) > (arraysize-1))//South- East neighbour
    {
        if((col+1) > (arraysize-1)){if(ccurrent[0] == 1)neighbours++;}
    	else if(ccurrent[col+1] == 1)neighbours++;
    }
    else if((col+1) > (arraysize-1)){if(ccurrent[(row+1) * arraysize] == 1)neighbours++;}//se
    else if(ccurrent[(row+1) * arraysize + col+1] == 1 )neighbours++;//se
                
    if((col+1) > (arraysize-1)){if(ccurrent[row * arraysize] == 1)neighbours++;}//East neighbour
    else if(ccurrent[row * arraysize + col+1] == 1 )neighbours++;//e

    if((row-1) < 0)//North- East neighbour
    {
    	if((col+1) > (arraysize-1) ){if(ccurrent[(arraysize-1) * arraysize] == 1)neighbours++;}
        else if(ccurrent[(arraysize-1)* arraysize + col+1] == 1)neighbours++;
    }
    else if((col+1) > arraysize-1){if(ccurrent[(row-1) * arraysize] == 1)neighbours++;}//ne
    else if(ccurrent[(row-1) * arraysize + col+1] == 1 )neighbours++;//ne
                
    if((row-1) < 0){if(ccurrent[(arraysize-1)* arraysize + col])neighbours++;}//North neighbour
    else if(ccurrent[(row-1) * arraysize + col] == 1) neighbours++;//n
                
    if((row-1) < 0)//North- West neighbour
    {
    	if((col-1) < 0 ){if(ccurrent[(arraysize-1) * arraysize + arraysize-1] == 1)neighbours++;}
        else if(ccurrent[(arraysize-1) * arraysize + col-1] == 1)neighbours++;
    }
    else if((col-1) < 0){if(ccurrent[(row-1) * arraysize + arraysize-1] == 1)neighbours++;}//nw
    else if(ccurrent[(row-1) * arraysize + col-1] == 1 )neighbours++;//nw
                   
    if(ccurrent[row * arraysize +col] == 0)
    {
    	if(neighbours == 3)cnext[row * arraysize + col]=1;//If the array[row][col] = 1 check the number of neighbours and set the next value 
        else cnext[row * arraysize + col] = 0;
    }
    if(ccurrent[row * arraysize + col] == 1)
    {
    	if(neighbours>1 && neighbours<4)cnext[row * arraysize + col] = 1;
    	else cnext[row * arraysize + col] = 0;
    }
}


__global__ void kernel_checksimilarity(int *ccurrent, int *cnext, int arraysize, int *dsame, int *ddead)
{
	int row = blockIdx.y * blockDim.y + threadIdx.y;// get the row number
	int col = blockIdx.x * blockDim.x + threadIdx.x;// get the col number
	if(row >= arraysize || col >= arraysize)return;// check if the dimensions are over the dims of the array
	if(ccurrent[row * arraysize + col] != cnext[row * arraysize + col]) *dsame = 0;
	if(cnext[row * arraysize + col] == 1)*ddead = 0;
}



int main(int argc, char *argv[])
{
	srand(time(NULL));
	unsigned int i, j, arraysize = 50,check = 31;
	int *same , *dead;
	int *dsame = NULL, *ddead = NULL;
	same = (int*)malloc(sizeof(int));
	dead = (int*)malloc(sizeof(int));
	hipMalloc(&dsame,sizeof(int));
	hipMalloc(&ddead,sizeof(int));
	unsigned long generations = 50;
	char c;
	while((c = getopt (argc, argv, "g:s:")) != -1)
	{
		switch(c)
		{
			case 'g':
				generations = atoi(optarg);
				break;
			case 's':
				arraysize = atoi(optarg);
				break;
			default:
				break;
		}		
	}
	//Host mallocs and initialization of the arrays
	int *currentdata = (int*)malloc(arraysize * arraysize * sizeof(int));
	int **current = (int**)malloc(arraysize * sizeof(int*));
	int *nextdata = (int*)malloc(arraysize *arraysize * sizeof(int));
	int **next = (int**)malloc(arraysize * sizeof(int*));
	for (i = 0; i < arraysize; ++i)
	{
		current[i] = &(currentdata[i*arraysize]);
		next[i] = &(nextdata[i*arraysize]);
	}
	for (i = 0; i < arraysize; ++i)
	{
		for (j= 0; j < arraysize; ++j)
		{
			current[i][j] = rand()%2;
			next[i][j] = 0;
			//printf("%d ", current[i][j]);
		}
		//printf("\n");
	}
	//Device mallocs and transfer HostToDevice
	int *ccurrent = NULL;
	hipMalloc(&ccurrent,(arraysize * arraysize * sizeof(int)));
	int *cnext = NULL;
	hipMalloc(&cnext,(arraysize * arraysize * sizeof(int)));
	hipMemcpy(ccurrent, currentdata, (arraysize * arraysize * sizeof(int)), hipMemcpyHostToDevice);
	hipMemcpy(cnext, nextdata, (arraysize * arraysize * sizeof(int)), hipMemcpyHostToDevice);
	int *ctemp;
	//dim3 dimBlock(block_size, block_size);
	//dim3 dimGrid((arraysize + dimBlock.x - 1) / dimBlock.x,(arraysize + dimBlock.y - 1) / dimBlock.y);
	
	hipDeviceProp_t myCUDA;
	if (hipGetDeviceProperties(&myCUDA, 0) == hipSuccess)
	{
	    printf("Using device %d: ", 0);
	    printf("%s; global mem: %dΒ; compute v%d.%d; clock: %d kHz\n",myCUDA.name, (int)myCUDA.totalGlobalMem, (int)myCUDA.major,(int)myCUDA.minor, (int)myCUDA.clockRate);
	}
	int threadsPerBlock = myCUDA.maxThreadsPerBlock;
	int temp = (int)sqrt(threadsPerBlock);
	printf("Maximum threads per block dimension = %d\n",temp);
	dim3 dimBlock(temp, temp);
	dim3 dimGrid((arraysize + dimBlock.x - 1) / dimBlock.x,(arraysize + dimBlock.y - 1) / dimBlock.y);
	float ttime;
	hipEvent_t start, stop;//Start the clock

	hipEventCreate(&start);
	hipEventCreate(&stop);
	hipEventRecord(start, 0);
	for (i = 0; i < generations; ++i)
	{
		kernel_func<<<dimGrid, dimBlock>>>(ccurrent,cnext,arraysize);//call the Device function
		hipDeviceSynchronize();
		if((i%check) == 0)
		{
			*same = 1;
			*dead = 1;
			hipMemcpy(dsame, same, sizeof(int), hipMemcpyHostToDevice);
			hipMemcpy(ddead, dead, sizeof(int), hipMemcpyHostToDevice);
			kernel_checksimilarity<<<dimGrid,dimBlock>>>(ccurrent,cnext,arraysize,dsame,ddead);
			hipDeviceSynchronize();
			hipMemcpy(same, dsame, sizeof(int), hipMemcpyDeviceToHost);
			hipMemcpy(dead, ddead, sizeof(int), hipMemcpyDeviceToHost);
			if((*same == 1) || (*dead == 1))break;
		}
		ctemp = ccurrent;//Change the arrays for the next generation
		ccurrent = cnext;
		cnext = ctemp;
		/*cudaMemcpy(currentdata, ccurrent, (arraysize * arraysize * sizeof(int)), cudaMemcpyDeviceToHost);//DevicetoHost transfer
		printf("In generation %d\n",i);
		for ( k = 0; k < arraysize; ++k)//print the array
		{
			for (j = 0; j < arraysize; ++j)
			{
				printf("%d ",current[k][j]);
			}
			printf("\n");
		}*/
	}
	hipEventRecord(stop, 0);//stop the clock
	hipEventSynchronize(stop);
	hipEventElapsedTime(&ttime, start, stop);
	printf("\nProcess exited at generation: %d with arraysize: %d x %d, after:  %3.1f ms \n", i, arraysize, arraysize,ttime);
	if(*dead == 1)printf("Exited earlier because all cells are dead.\n");
	if(*same == 1)printf("Exited earlier because current and next generations are the same.\n");
	/*printf("Last version of the array\n");
	cudaMemcpy(currentdata, ccurrent, (arraysize * arraysize * sizeof(int)), cudaMemcpyDeviceToHost);
	for ( i = 0; i < arraysize; ++i)
	{
		for (j = 0; j < arraysize; ++j)
		{
			printf("%d ",current[i][j]);
		}
		printf("\n");
	}*/
	//Free the allocated memory

	hipFree(ccurrent);
	hipFree(cnext);
	hipFree(dsame);
	hipFree(ddead);
	free(same);
	free(dead);
	free(nextdata);
	free(next);
	free(currentdata);
	free(current);
	return 0;
}
	.text
	.file	"CUDA_game_of_life.hip"
	.globl	_Z26__device_stub__kernel_funcPiS_i # -- Begin function _Z26__device_stub__kernel_funcPiS_i
	.type	_Z26__device_stub__kernel_funcPiS_i,@function
_Z26__device_stub__kernel_funcPiS_i:    # @_Z26__device_stub__kernel_funcPiS_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z11kernel_funcPiS_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z26__device_stub__kernel_funcPiS_i, .Lfunc_end0-_Z26__device_stub__kernel_funcPiS_i
	.cfi_endproc
                                        # -- End function
	.globl	_Z37__device_stub__kernel_checksimilarityPiS_iS_S_ # -- Begin function _Z37__device_stub__kernel_checksimilarityPiS_iS_S_
	.type	_Z37__device_stub__kernel_checksimilarityPiS_iS_S_,@function
_Z37__device_stub__kernel_checksimilarityPiS_iS_S_: # @_Z37__device_stub__kernel_checksimilarityPiS_iS_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	40(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	32(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z22kernel_checksimilarityPiS_iS_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z37__device_stub__kernel_checksimilarityPiS_iS_S_, .Lfunc_end1-_Z37__device_stub__kernel_checksimilarityPiS_iS_S_
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$1592, %rsp                     # imm = 0x638
	.cfi_def_cfa_offset 1648
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%rsi, %rbx
	movl	%edi, %ebp
	xorl	%r12d, %r12d
	xorl	%edi, %edi
	callq	time
	movl	%eax, %edi
	callq	srand
	leaq	48(%rsp), %r14
	movq	%r12, (%r14)
	leaq	40(%rsp), %r15
	movq	%r12, (%r15)
	movl	$4, %edi
	callq	malloc
	movq	%rax, 88(%rsp)                  # 8-byte Spill
	movl	$4, %edi
	callq	malloc
	movq	%rax, 80(%rsp)                  # 8-byte Spill
	movl	$4, %esi
	movq	%r14, %rdi
	callq	hipMalloc
	movl	$4, %esi
	movq	%r15, %rdi
	callq	hipMalloc
	movl	$.L.str, %edx
	movl	%ebp, %edi
	movq	%rbx, %rsi
	callq	getopt
	shll	$24, %eax
	cmpl	$-16777216, %eax                # imm = 0xFF000000
	jne	.LBB2_2
# %bb.1:
	movl	$50, %r15d
	movl	$50, %eax
	movq	%rax, 32(%rsp)                  # 8-byte Spill
	jmp	.LBB2_8
.LBB2_2:                                # %.lr.ph.preheader
	movl	$50, %ecx
	movq	%rcx, 32(%rsp)                  # 8-byte Spill
	movl	$50, %r15d
.LBB2_3:                                # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	sarl	$24, %eax
	cmpl	$115, %eax
	je	.LBB2_6
# %bb.4:                                # %.lr.ph
                                        #   in Loop: Header=BB2_3 Depth=1
	cmpl	$103, %eax
	jne	.LBB2_7
# %bb.5:                                #   in Loop: Header=BB2_3 Depth=1
	movq	optarg(%rip), %rdi
	callq	atoi
	cltq
	movq	%rax, 32(%rsp)                  # 8-byte Spill
	jmp	.LBB2_7
.LBB2_6:                                #   in Loop: Header=BB2_3 Depth=1
	movq	optarg(%rip), %rdi
	callq	atoi
	movl	%eax, %r15d
.LBB2_7:                                #   in Loop: Header=BB2_3 Depth=1
	movl	$.L.str, %edx
	movl	%ebp, %edi
	movq	%rbx, %rsi
	callq	getopt
	shll	$24, %eax
	cmpl	$-16777216, %eax                # imm = 0xFF000000
	jne	.LBB2_3
.LBB2_8:                                # %._crit_edge
	movl	%r15d, %ebx
	imull	%ebx, %ebx
	shlq	$2, %rbx
	movq	%rbx, %rdi
	callq	malloc
	movq	%rax, 64(%rsp)                  # 8-byte Spill
	movl	%r15d, %r14d
	leaq	(,%r14,8), %r13
	movq	%r13, %rdi
	callq	malloc
	movq	%rax, %r12
	movq	%rbx, %rdi
	callq	malloc
	movq	%rax, 56(%rsp)                  # 8-byte Spill
	movq	%r13, %rdi
	callq	malloc
	movq	%rax, %rbp
	testl	%r15d, %r15d
	je	.LBB2_16
# %bb.9:                                # %.lr.ph114.preheader
	xorl	%eax, %eax
	xorl	%ecx, %ecx
	movq	64(%rsp), %rdi                  # 8-byte Reload
	movq	56(%rsp), %r8                   # 8-byte Reload
.LBB2_10:                               # %.lr.ph114
                                        # =>This Inner Loop Header: Depth=1
	movl	%eax, %edx
	leaq	(%rdi,%rdx,4), %rsi
	movq	%rsi, (%r12,%rcx,8)
	leaq	(%r8,%rdx,4), %rdx
	movq	%rdx, (%rbp,%rcx,8)
	incq	%rcx
	addl	%r14d, %eax
	cmpq	%rcx, %r14
	jne	.LBB2_10
# %bb.11:                               # %.preheader105
	testq	%r14, %r14
	je	.LBB2_16
# %bb.12:                               # %.preheader.preheader
	xorl	%r15d, %r15d
.LBB2_13:                               # %.preheader
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB2_14 Depth 2
	xorl	%r13d, %r13d
.LBB2_14:                               #   Parent Loop BB2_13 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	callq	rand
	movl	%eax, %ecx
	shrl	$31, %ecx
	addl	%eax, %ecx
	andl	$-2, %ecx
	subl	%ecx, %eax
	movq	(%r12,%r15,8), %rcx
	movl	%eax, (%rcx,%r13,4)
	movq	(%rbp,%r15,8), %rax
	movl	$0, (%rax,%r13,4)
	incq	%r13
	cmpq	%r13, %r14
	jne	.LBB2_14
# %bb.15:                               #   in Loop: Header=BB2_13 Depth=1
	incq	%r15
	cmpq	%r14, %r15
	jne	.LBB2_13
.LBB2_16:                               # %._crit_edge117
	xorl	%eax, %eax
	leaq	16(%rsp), %r15
	movq	%rax, (%r15)
	movq	%r15, %rdi
	movq	%rbx, %rsi
	callq	hipMalloc
	leaq	8(%rsp), %r13
	xorl	%eax, %eax
	movq	%rax, (%r13)
	movq	%r13, %rdi
	movq	%rbx, %rsi
	callq	hipMalloc
	movq	(%r15), %rdi
	movq	64(%rsp), %rsi                  # 8-byte Reload
	movq	%rbx, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%r13), %rdi
	movq	56(%rsp), %rsi                  # 8-byte Reload
	movq	%rbx, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	120(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipGetDevicePropertiesR0600
	testl	%eax, %eax
	jne	.LBB2_18
# %bb.17:
	movl	$.L.str.1, %edi
	xorl	%esi, %esi
	xorl	%eax, %eax
	callq	printf
	leaq	120(%rsp), %rsi
	movl	360(%rsi), %ecx
	movl	364(%rsi), %r8d
	movl	288(%rsi), %edx
	movl	348(%rsi), %r9d
	movl	$.L.str.2, %edi
	xorl	%eax, %eax
	callq	printf
.LBB2_18:
	cvtsi2sdl	440(%rsp), %xmm0
	xorpd	%xmm1, %xmm1
	ucomisd	%xmm1, %xmm0
	jb	.LBB2_20
# %bb.19:
	sqrtsd	%xmm0, %xmm0
	jmp	.LBB2_21
.LBB2_20:                               # %call.sqrt
	callq	sqrt
.LBB2_21:                               # %.split
	cvttsd2si	%xmm0, %r13d
	xorl	%ebx, %ebx
	movl	$.L.str.3, %edi
	movl	%r13d, %esi
	xorl	%eax, %eax
	callq	printf
	leal	(%r14,%r13), %eax
	decl	%eax
	xorl	%edx, %edx
	divl	%r13d
                                        # kill: def $eax killed $eax def $rax
	movq	%rax, 24(%rsp)                  # 8-byte Spill
	leaq	104(%rsp), %r15
	movq	%r15, %rdi
	callq	hipEventCreate
	leaq	72(%rsp), %rdi
	callq	hipEventCreate
	movq	(%r15), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	cmpq	$0, 32(%rsp)                    # 8-byte Folded Reload
	je	.LBB2_31
# %bb.22:                               # %.lr.ph120.preheader
	movq	%r13, %rax
	shlq	$32, %rax
	orq	%r13, %rax
	movq	%rax, 96(%rsp)                  # 8-byte Spill
	movq	24(%rsp), %rcx                  # 8-byte Reload
	movq	%rcx, %rax
	shlq	$32, %rax
	orq	%rcx, %rax
	movq	%rax, 24(%rsp)                  # 8-byte Spill
	xorl	%ebx, %ebx
	movq	80(%rsp), %r13                  # 8-byte Reload
.LBB2_23:                               # %.lr.ph120
                                        # =>This Inner Loop Header: Depth=1
	movq	24(%rsp), %rdi                  # 8-byte Reload
	movl	$1, %esi
	movq	96(%rsp), %rdx                  # 8-byte Reload
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_25
# %bb.24:                               #   in Loop: Header=BB2_23 Depth=1
	movq	16(%rsp), %rdi
	movq	8(%rsp), %rsi
	movl	%r14d, %edx
	callq	_Z26__device_stub__kernel_funcPiS_i
.LBB2_25:                               #   in Loop: Header=BB2_23 Depth=1
	movl	%ebx, %eax
	imulq	$138547333, %rax, %rax          # imm = 0x8421085
	shrq	$32, %rax
	movl	%ebx, %ecx
	subl	%eax, %ecx
	shrl	%ecx
	addl	%eax, %ecx
	shrl	$4, %ecx
	movl	%ecx, %r15d
	shll	$5, %r15d
	subl	%ecx, %r15d
	callq	hipDeviceSynchronize
	cmpl	%ebx, %r15d
	jne	.LBB2_30
# %bb.26:                               #   in Loop: Header=BB2_23 Depth=1
	movq	88(%rsp), %r15                  # 8-byte Reload
	movl	$1, %eax
	movl	%eax, (%r15)
	movl	%eax, (%r13)
	movq	48(%rsp), %rdi
	movl	$4, %edx
	movq	%r15, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	40(%rsp), %rdi
	movl	$4, %edx
	movq	%r13, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	24(%rsp), %rdi                  # 8-byte Reload
	movl	$1, %esi
	movq	96(%rsp), %rdx                  # 8-byte Reload
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_28
# %bb.27:                               #   in Loop: Header=BB2_23 Depth=1
	movq	16(%rsp), %rdi
	movq	8(%rsp), %rsi
	movq	48(%rsp), %rcx
	movq	40(%rsp), %r8
	movl	%r14d, %edx
	callq	_Z37__device_stub__kernel_checksimilarityPiS_iS_S_
.LBB2_28:                               #   in Loop: Header=BB2_23 Depth=1
	callq	hipDeviceSynchronize
	movq	48(%rsp), %rsi
	movl	$4, %edx
	movq	%r15, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movq	40(%rsp), %rsi
	movl	$4, %edx
	movq	%r13, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	cmpl	$1, (%r15)
	je	.LBB2_31
# %bb.29:                               #   in Loop: Header=BB2_23 Depth=1
	cmpl	$1, (%r13)
	je	.LBB2_31
.LBB2_30:                               #   in Loop: Header=BB2_23 Depth=1
	movq	16(%rsp), %rax
	movq	8(%rsp), %rcx
	movq	%rcx, 16(%rsp)
	movq	%rax, 8(%rsp)
	incl	%ebx
	cmpq	%rbx, 32(%rsp)                  # 8-byte Folded Reload
	ja	.LBB2_23
.LBB2_31:                               # %._crit_edge121
	movq	72(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	72(%rsp), %rdi
	callq	hipEventSynchronize
	movq	104(%rsp), %rsi
	movq	72(%rsp), %rdx
	leaq	116(%rsp), %r15
	movq	%r15, %rdi
	callq	hipEventElapsedTime
	xorps	%xmm0, %xmm0
	cvtss2sd	(%r15), %xmm0
	movl	$.L.str.4, %edi
	movl	%ebx, %esi
	movl	%r14d, %edx
	movl	%r14d, %ecx
	movb	$1, %al
	callq	printf
	movq	80(%rsp), %r14                  # 8-byte Reload
	cmpl	$1, (%r14)
	jne	.LBB2_33
# %bb.32:
	movl	$.Lstr, %edi
	callq	puts@PLT
.LBB2_33:
	movq	88(%rsp), %rbx                  # 8-byte Reload
	cmpl	$1, (%rbx)
	jne	.LBB2_35
# %bb.34:
	movl	$.Lstr.1, %edi
	callq	puts@PLT
.LBB2_35:
	movq	16(%rsp), %rdi
	callq	hipFree
	movq	8(%rsp), %rdi
	callq	hipFree
	movq	48(%rsp), %rdi
	callq	hipFree
	movq	40(%rsp), %rdi
	callq	hipFree
	movq	%rbx, %rdi
	callq	free
	movq	%r14, %rdi
	callq	free
	movq	56(%rsp), %rdi                  # 8-byte Reload
	callq	free
	movq	%rbp, %rdi
	callq	free
	movq	64(%rsp), %rdi                  # 8-byte Reload
	callq	free
	movq	%r12, %rdi
	callq	free
	xorl	%eax, %eax
	addq	$1592, %rsp                     # imm = 0x638
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	main, .Lfunc_end2-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB3_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB3_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z11kernel_funcPiS_i, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z22kernel_checksimilarityPiS_iS_S_, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end3:
	.size	__hip_module_ctor, .Lfunc_end3-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB4_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB4_2:
	retq
.Lfunc_end4:
	.size	__hip_module_dtor, .Lfunc_end4-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z11kernel_funcPiS_i,@object    # @_Z11kernel_funcPiS_i
	.section	.rodata,"a",@progbits
	.globl	_Z11kernel_funcPiS_i
	.p2align	3, 0x0
_Z11kernel_funcPiS_i:
	.quad	_Z26__device_stub__kernel_funcPiS_i
	.size	_Z11kernel_funcPiS_i, 8

	.type	_Z22kernel_checksimilarityPiS_iS_S_,@object # @_Z22kernel_checksimilarityPiS_iS_S_
	.globl	_Z22kernel_checksimilarityPiS_iS_S_
	.p2align	3, 0x0
_Z22kernel_checksimilarityPiS_iS_S_:
	.quad	_Z37__device_stub__kernel_checksimilarityPiS_iS_S_
	.size	_Z22kernel_checksimilarityPiS_iS_S_, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"g:s:"
	.size	.L.str, 5

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"Using device %d: "
	.size	.L.str.1, 18

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"%s; global mem: %d\316\222; compute v%d.%d; clock: %d kHz\n"
	.size	.L.str.2, 53

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"Maximum threads per block dimension = %d\n"
	.size	.L.str.3, 42

	.type	.L.str.4,@object                # @.str.4
.L.str.4:
	.asciz	"\nProcess exited at generation: %d with arraysize: %d x %d, after:  %3.1f ms \n"
	.size	.L.str.4, 78

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z11kernel_funcPiS_i"
	.size	.L__unnamed_1, 21

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z22kernel_checksimilarityPiS_iS_S_"
	.size	.L__unnamed_2, 36

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.type	.Lstr,@object                   # @str
	.section	.rodata.str1.1,"aMS",@progbits,1
.Lstr:
	.asciz	"Exited earlier because all cells are dead."
	.size	.Lstr, 43

	.type	.Lstr.1,@object                 # @str.1
.Lstr.1:
	.asciz	"Exited earlier because current and next generations are the same."
	.size	.Lstr.1, 66

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z26__device_stub__kernel_funcPiS_i
	.addrsig_sym _Z37__device_stub__kernel_checksimilarityPiS_iS_S_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z11kernel_funcPiS_i
	.addrsig_sym _Z22kernel_checksimilarityPiS_iS_S_
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z11kernel_funcPiS_i    ; -- Begin function _Z11kernel_funcPiS_i
	.globl	_Z11kernel_funcPiS_i
	.p2align	8
	.type	_Z11kernel_funcPiS_i,@function
_Z11kernel_funcPiS_i:                   ; @_Z11kernel_funcPiS_i
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x24
	s_load_b32 s16, s[0:1], 0x10
	v_bfe_u32 v1, v0, 10, 10
	v_and_b32_e32 v0, 0x3ff, v0
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s2, 16
	s_and_b32 s2, s2, 0xffff
	v_mad_u64_u32 v[4:5], null, s15, s3, v[1:2]
	v_mad_u64_u32 v[2:3], null, s14, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mov_b32_e32 v5, v2
	v_max_i32_e32 v0, v4, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e64 s16, v0
	s_cbranch_execz .LBB0_59
; %bb.1:
	v_add_nc_u32_e32 v6, -1, v2
	v_cmp_gt_i32_e32 vcc_lo, 1, v2
	v_mul_lo_u32 v0, v4, s16
	s_add_i32 s8, s16, -1
	s_load_b128 s[4:7], s[0:1], 0x0
	v_cmp_lt_i32_e64 s0, 0, v2
	v_cndmask_b32_e64 v1, v6, s8, vcc_lo
	v_cmp_gt_i32_e64 s1, s8, v4
	v_cmp_le_i32_e64 s2, s8, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v7, v1, v0
	v_ashrrev_i32_e32 v8, 31, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[7:8], 2, v[7:8]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v7, vcc_lo, s4, v7
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v8, vcc_lo, s5, v8, vcc_lo
	global_load_b32 v1, v[7:8], off
	s_waitcnt vmcnt(0)
	v_cmp_eq_u32_e32 vcc_lo, 1, v1
	v_cndmask_b32_e64 v10, 1, 2, vcc_lo
	s_and_saveexec_b32 s3, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s3, exec_lo, s3
	s_cbranch_execz .LBB0_7
; %bb.2:
	v_cndmask_b32_e64 v10, 1, 2, vcc_lo
	s_and_saveexec_b32 s9, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s9, exec_lo, s9
; %bb.3:
	v_mov_b32_e32 v7, 0
; %bb.4:                                ; %Flow252
	s_and_not1_saveexec_b32 s10, s9
; %bb.5:
	s_ashr_i32 s9, s8, 31
	s_delay_alu instid0(SALU_CYCLE_1)
	v_dual_mov_b32 v6, s8 :: v_dual_mov_b32 v7, s9
; %bb.6:                                ; %Flow253
	s_or_b32 exec_lo, exec_lo, s10
.LBB0_7:                                ; %Flow256
	s_or_saveexec_b32 s3, s3
	v_add_nc_u32_e32 v8, s16, v0
	s_xor_b32 exec_lo, exec_lo, s3
	s_cbranch_execz .LBB0_13
; %bb.8:
	s_and_saveexec_b32 s9, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s9, exec_lo, s9
; %bb.9:
	v_add_nc_u32_e32 v6, v8, v6
	s_delay_alu instid0(VALU_DEP_1)
	v_ashrrev_i32_e32 v7, 31, v6
; %bb.10:                               ; %Flow254
	s_and_not1_saveexec_b32 s9, s9
; %bb.11:
	v_add_nc_u32_e32 v6, s8, v8
	s_delay_alu instid0(VALU_DEP_1)
	v_ashrrev_i32_e32 v7, 31, v6
; %bb.12:                               ; %Flow255
	s_or_b32 exec_lo, exec_lo, s9
.LBB0_13:
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_or_b32 exec_lo, exec_lo, s3
	v_lshlrev_b64 v[6:7], 2, v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v6, s3, s4, v6
	v_add_co_ci_u32_e64 v7, s3, s5, v7, s3
	global_load_b32 v11, v[6:7], off
	s_and_saveexec_b32 s3, s1
; %bb.14:
	v_add3_u32 v5, v0, s16, v2
; %bb.15:
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v6, 31, v5
	v_cmp_gt_i32_e64 s3, s8, v2
	v_lshlrev_b64 v[5:6], 2, v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v5, s1, s4, v5
	v_add_co_ci_u32_e64 v6, s1, s5, v6, s1
	v_cmp_le_i32_e64 s1, s8, v2
	global_load_b32 v12, v[5:6], off
                                        ; implicit-def: $vgpr5_vgpr6
	s_and_saveexec_b32 s9, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s9, exec_lo, s9
	s_cbranch_execz .LBB0_19
; %bb.16:
	v_dual_mov_b32 v6, s5 :: v_dual_mov_b32 v5, s4
	s_and_saveexec_b32 s10, s3
; %bb.17:
	v_ashrrev_i32_e32 v3, 31, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[5:6], 2, v[2:3]
	v_add_co_u32 v1, s2, s4, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e64 v3, s2, s5, v6, s2
	v_add_co_u32 v5, s2, v1, 4
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v6, s2, 0, v3, s2
; %bb.18:                               ; %Flow248
	s_or_b32 exec_lo, exec_lo, s10
                                        ; implicit-def: $vgpr8
.LBB0_19:                               ; %Flow251
	s_and_not1_saveexec_b32 s3, s9
	s_cbranch_execz .LBB0_25
; %bb.20:
                                        ; implicit-def: $vgpr5_vgpr6
	s_and_saveexec_b32 s2, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s9, exec_lo, s2
; %bb.21:
	v_ashrrev_i32_e32 v9, 31, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[5:6], 2, v[8:9]
                                        ; implicit-def: $vgpr8
	v_add_co_u32 v5, s2, s4, v5
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v6, s2, s5, v6, s2
; %bb.22:                               ; %Flow249
	s_and_not1_saveexec_b32 s9, s9
; %bb.23:
	v_add_nc_u32_e32 v5, v8, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v6, 31, v5
	v_lshlrev_b64 v[5:6], 2, v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v1, s2, s4, v5
	v_add_co_ci_u32_e64 v3, s2, s5, v6, s2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v5, s2, v1, 4
	v_add_co_ci_u32_e64 v6, s2, 0, v3, s2
; %bb.24:                               ; %Flow250
	s_or_b32 exec_lo, exec_lo, s9
.LBB0_25:
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s3
	global_load_b32 v9, v[5:6], off
                                        ; implicit-def: $vgpr7_vgpr8
	s_and_saveexec_b32 s2, s1
	s_xor_b32 s3, exec_lo, s2
; %bb.26:
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[5:6], 2, v[0:1]
	v_add_co_u32 v7, s2, s4, v5
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v8, s2, s5, v6, s2
; %bb.27:                               ; %Flow247
	s_or_saveexec_b32 s3, s3
	v_add_nc_u32_e32 v5, v0, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_ashrrev_i32_e32 v6, 31, v5
	s_xor_b32 exec_lo, exec_lo, s3
; %bb.28:
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[7:8], 2, v[5:6]
	v_add_co_u32 v1, s2, s4, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e64 v3, s2, s5, v8, s2
	v_add_co_u32 v7, s2, v1, 4
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v8, s2, 0, v3, s2
; %bb.29:
	s_or_b32 exec_lo, exec_lo, s3
	global_load_b32 v13, v[7:8], off
	v_add_nc_u32_e32 v14, -1, v4
	v_cmp_lt_i32_e64 s2, 0, v4
                                        ; implicit-def: $vgpr3_vgpr4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_saveexec_b32 s3, s2
	s_xor_b32 s9, exec_lo, s3
	s_cbranch_execz .LBB0_35
; %bb.30:
	v_mul_lo_u32 v7, v14, s16
                                        ; implicit-def: $vgpr3_vgpr4
	s_and_saveexec_b32 s3, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s10, exec_lo, s3
; %bb.31:
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v8, 31, v7
	v_lshlrev_b64 v[3:4], 2, v[7:8]
                                        ; implicit-def: $vgpr7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v3, s3, s4, v3
	v_add_co_ci_u32_e64 v4, s3, s5, v4, s3
; %bb.32:                               ; %Flow242
	s_and_not1_saveexec_b32 s10, s10
; %bb.33:
	v_add_nc_u32_e32 v3, v7, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v4, 31, v3
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v1, s3, s4, v3
	v_add_co_ci_u32_e64 v4, s3, s5, v4, s3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v3, s3, v1, 4
	v_add_co_ci_u32_e64 v4, s3, 0, v4, s3
; %bb.34:                               ; %Flow243
	s_or_b32 exec_lo, exec_lo, s10
.LBB0_35:                               ; %Flow246
	s_and_not1_saveexec_b32 s3, s9
	s_cbranch_execz .LBB0_41
; %bb.36:
	s_mul_i32 s10, s8, s16
                                        ; implicit-def: $sgpr12_sgpr13
	s_and_saveexec_b32 s9, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s1, exec_lo, s9
; %bb.37:
	s_ashr_i32 s11, s10, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[12:13], s[10:11], 2
	s_add_u32 s12, s4, s12
	s_addc_u32 s13, s5, s13
; %bb.38:                               ; %Flow244
	s_or_saveexec_b32 s9, s1
	v_dual_mov_b32 v3, s12 :: v_dual_mov_b32 v4, s13
	s_xor_b32 exec_lo, exec_lo, s9
; %bb.39:
	v_add_nc_u32_e32 v3, s10, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v4, 31, v3
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v1, s1, s4, v3
	v_add_co_ci_u32_e64 v4, s1, s5, v4, s1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v3, s1, v1, 4
	v_add_co_ci_u32_e64 v4, s1, 0, v4, s1
; %bb.40:                               ; %Flow245
	s_or_b32 exec_lo, exec_lo, s9
.LBB0_41:
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s3
	global_load_b32 v4, v[3:4], off
                                        ; implicit-def: $sgpr3
	s_and_saveexec_b32 s1, s2
	s_xor_b32 s9, exec_lo, s1
	s_cbranch_execz .LBB0_43
; %bb.42:
	v_mad_u64_u32 v[7:8], null, v14, s16, v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v8, 31, v7
	v_lshlrev_b64 v[7:8], 2, v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v7, s1, s4, v7
	v_add_co_ci_u32_e64 v8, s1, s5, v8, s1
	global_load_b32 v1, v[7:8], off
	s_waitcnt vmcnt(0)
	v_cmp_eq_u32_e64 s1, 1, v1
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 s3, s1, exec_lo
.LBB0_43:                               ; %Flow241
	s_and_not1_saveexec_b32 s9, s9
	s_cbranch_execz .LBB0_45
; %bb.44:
	v_mad_u64_u32 v[7:8], null, s8, s16, v[2:3]
	s_and_not1_b32 s3, s3, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v8, 31, v7
	v_lshlrev_b64 v[7:8], 2, v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v7, s1, s4, v7
	v_add_co_ci_u32_e64 v8, s1, s5, v8, s1
	global_load_b32 v1, v[7:8], off
	s_waitcnt vmcnt(0)
	v_cmp_ne_u32_e64 s1, 0, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s1, s1, exec_lo
	s_or_b32 s3, s3, s1
.LBB0_45:
	s_or_b32 exec_lo, exec_lo, s9
	s_and_saveexec_b32 s1, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s1, exec_lo, s1
	s_cbranch_execz .LBB0_49
; %bb.46:
	s_and_saveexec_b32 s2, s0
; %bb.47:
	v_mad_u64_u32 v[0:1], null, v14, s16, v[2:3]
; %bb.48:                               ; %Flow236
	s_or_b32 exec_lo, exec_lo, s2
                                        ; implicit-def: $vgpr2_vgpr3
.LBB0_49:                               ; %Flow240
	s_and_not1_saveexec_b32 s1, s1
	s_cbranch_execz .LBB0_55
; %bb.50:
                                        ; implicit-def: $vgpr0
	s_and_saveexec_b32 s2, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s0, exec_lo, s2
; %bb.51:
	v_mad_u64_u32 v[0:1], null, s8, s16, v[2:3]
; %bb.52:                               ; %Flow237
	s_and_not1_saveexec_b32 s0, s0
; %bb.53:
	s_mul_i32 s16, s16, s16
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v0, s16
; %bb.54:                               ; %Flow238
	s_or_b32 exec_lo, exec_lo, s0
.LBB0_55:
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_or_b32 exec_lo, exec_lo, s1
	v_ashrrev_i32_e32 v1, 31, v0
	v_cndmask_b32_e64 v7, 0, 1, vcc_lo
	s_waitcnt vmcnt(3)
	v_cmp_eq_u32_e32 vcc_lo, 1, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_lshlrev_b64 v[2:3], 2, v[0:1]
	v_lshlrev_b64 v[0:1], 2, v[5:6]
	v_cndmask_b32_e64 v8, 0, 1, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 1, v11
	v_add_co_u32 v5, s0, s4, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e64 v6, s0, s5, v3, s0
	v_add_co_u32 v2, s0, s4, v0
	v_add_co_ci_u32_e64 v3, s0, s5, v1, s0
	v_cndmask_b32_e32 v7, v7, v10, vcc_lo
	s_clause 0x1
	global_load_b32 v5, v[5:6], off offset:-4
	global_load_b32 v6, v[2:3], off
	s_waitcnt vmcnt(3)
	v_cmp_eq_u32_e32 vcc_lo, 1, v13
	s_mov_b32 s0, exec_lo
	v_cndmask_b32_e64 v10, 0, 1, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 1, v9
	v_add_co_ci_u32_e32 v7, vcc_lo, v7, v8, vcc_lo
	s_waitcnt vmcnt(2)
	v_cmp_eq_u32_e32 vcc_lo, 1, v4
	v_cndmask_b32_e64 v8, 0, 1, s3
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, v7, v10, vcc_lo
	s_waitcnt vmcnt(1)
	v_cmp_eq_u32_e32 vcc_lo, 1, v5
	v_add_co_ci_u32_e32 v4, vcc_lo, v4, v8, vcc_lo
	s_waitcnt vmcnt(0)
	v_cmpx_eq_u32_e32 0, v6
	s_cbranch_execz .LBB0_57
; %bb.56:                               ; %.sink.split
	v_add_co_u32 v5, vcc_lo, s6, v0
	v_add_co_ci_u32_e32 v6, vcc_lo, s7, v1, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 3, v4
	v_cndmask_b32_e64 v7, 0, 1, vcc_lo
	global_store_b32 v[5:6], v7, off
.LBB0_57:
	s_or_b32 exec_lo, exec_lo, s0
	global_load_b32 v2, v[2:3], off
	s_waitcnt vmcnt(0)
	v_cmp_eq_u32_e32 vcc_lo, 1, v2
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_59
; %bb.58:                               ; %.sink.split224
	v_and_b32_e32 v2, -2, v4
	v_add_co_u32 v0, vcc_lo, s6, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_3)
	v_cmp_eq_u32_e32 vcc_lo, 2, v2
	v_cndmask_b32_e64 v2, 0, 1, vcc_lo
	global_store_b32 v[0:1], v2, off
.LBB0_59:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z11kernel_funcPiS_i
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 15
		.amdhsa_next_free_sgpr 17
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z11kernel_funcPiS_i, .Lfunc_end0-_Z11kernel_funcPiS_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1684
; NumSgprs: 19
; NumVgprs: 15
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 19
; NumVGPRsForWavesPerEU: 15
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z22kernel_checksimilarityPiS_iS_S_ ; -- Begin function _Z22kernel_checksimilarityPiS_iS_S_
	.globl	_Z22kernel_checksimilarityPiS_iS_S_
	.p2align	8
	.type	_Z22kernel_checksimilarityPiS_iS_S_,@function
_Z22kernel_checksimilarityPiS_iS_S_:    ; @_Z22kernel_checksimilarityPiS_iS_S_
; %bb.0:
	s_clause 0x1
	s_load_b32 s3, s[0:1], 0x34
	s_load_b32 s2, s[0:1], 0x10
	v_bfe_u32 v2, v0, 10, 10
	v_and_b32_e32 v3, 0x3ff, v0
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s4, s3, 16
	s_and_b32 s3, s3, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[0:1], null, s15, s4, v[2:3]
	v_mad_u64_u32 v[1:2], null, s14, s3, v[3:4]
	s_mov_b32 s3, exec_lo
	v_max_i32_e32 v2, v0, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e64 s2, v2
	s_cbranch_execz .LBB1_5
; %bb.1:
	s_load_b128 s[4:7], s[0:1], 0x0
	v_mad_u64_u32 v[2:3], null, v0, s2, v[1:2]
	s_load_b128 s[0:3], s[0:1], 0x18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[0:1], 2, v[2:3]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s4, v0
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
	v_add_co_u32 v0, vcc_lo, s6, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
	s_mov_b32 s4, exec_lo
	global_load_b32 v2, v[2:3], off
	global_load_b32 v3, v[0:1], off
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u32_e64 v2, v3
	s_cbranch_execz .LBB1_3
; %bb.2:
	v_mov_b32_e32 v2, 0
	global_store_b32 v2, v2, s[0:1]
	global_load_b32 v2, v[0:1], off
.LBB1_3:
	s_or_b32 exec_lo, exec_lo, s4
	s_waitcnt vmcnt(0)
	v_cmp_eq_u32_e32 vcc_lo, 1, v2
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB1_5
; %bb.4:
	v_mov_b32_e32 v0, 0
	global_store_b32 v0, v0, s[2:3]
.LBB1_5:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z22kernel_checksimilarityPiS_iS_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 5
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z22kernel_checksimilarityPiS_iS_S_, .Lfunc_end1-_Z22kernel_checksimilarityPiS_iS_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 268
; NumSgprs: 18
; NumVgprs: 5
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 5
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z11kernel_funcPiS_i
    .private_segment_fixed_size: 0
    .sgpr_count:     19
    .sgpr_spill_count: 0
    .symbol:         _Z11kernel_funcPiS_i.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     15
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         44
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         52
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         54
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         56
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         58
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         60
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         62
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         104
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 296
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z22kernel_checksimilarityPiS_iS_S_
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z22kernel_checksimilarityPiS_iS_S_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     5
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
