#include "includes.h"

#define tileSize 32

//function for data initialization
void initialization( double *M,  double *N, int arow, int acol, int brow, int bcol);
//(for Debugging) prints out the input data
void printInput( double *M,  double *N, int arow, int acol, int brow,  int bcol);
//(for Debugging) prints out the output data
void printOutput( double *P_C,  double *P_G, int arow, int bcol);

//GPU kernels




__global__
__global__ void matrixMultiplication(double* M, double* N, double* P, int widthAHeightB, int heightA, int widthB) {

int Mstart=widthAHeightB*tileSize*blockIdx.y;
int Mend=Mstart+ widthAHeightB - 1;
int mstep=tileSize;
int Nstart=tileSize*blockIdx.x;
int nstep=tileSize*widthB;
double temp=0;

__shared__ double Ms[tileSize][tileSize];
__shared__ double Ns[tileSize][tileSize];

//area where the tiles fits without "cutting"
if(Mstart < (heightA/tileSize)*tileSize*widthAHeightB && Nstart%widthB < (widthB/tileSize)*tileSize ){
for(int m=Mstart,n=Nstart;m<Mend;m+=mstep,n+=nstep){
Ms[threadIdx.y][threadIdx.x]=M[m+widthAHeightB*threadIdx.y+threadIdx.x];
Ns[threadIdx.y][threadIdx.x]=N[n+widthB*threadIdx.y+threadIdx.x];
__syncthreads();


for (int i = 0; i < tileSize; ++i) {
temp += Ms[threadIdx.y][i] * Ns[i][threadIdx.x];
}
__syncthreads();

}
} else {//the rest of the matrix
for(int m=Mstart,n=Nstart;m<=Mend;m+=mstep,n+=nstep){

if(m%widthAHeightB + threadIdx.x < widthAHeightB && blockIdx.y*tileSize + threadIdx.y < heightA){
Ms[threadIdx.y][threadIdx.x]=M[m+widthAHeightB*threadIdx.y+threadIdx.x];
}
else{
Ms[threadIdx.y][threadIdx.x]=0.0;
}

if((n/widthB) + threadIdx.y < widthAHeightB && blockIdx.x*tileSize + threadIdx.x < widthB){
Ns[threadIdx.y][threadIdx.x]=N[n+widthB*threadIdx.y+threadIdx.x];
}
else{
Ns[threadIdx.y][threadIdx.x]=0.0;
}
__syncthreads();


for (int i = 0; i < tileSize; ++i) {
temp += Ms[threadIdx.y][i] * Ns[i][threadIdx.x];
}
__syncthreads();

}
}



if(blockIdx.y*tileSize + threadIdx.y < heightA && blockIdx.x*tileSize + threadIdx.x < widthB){
P[widthB * tileSize * blockIdx.y + tileSize * blockIdx.x + widthB * threadIdx.y + threadIdx.x] = temp;
}
}
	.file	"tmpxft_0033bc63_00000000-6_matrixMultiplication.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2010:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2010:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z47__device_stub__Z20matrixMultiplicationPdS_S_iiiPdS_S_iii
	.type	_Z47__device_stub__Z20matrixMultiplicationPdS_S_iiiPdS_S_iii, @function
_Z47__device_stub__Z20matrixMultiplicationPdS_S_iiiPdS_S_iii:
.LFB2032:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	56(%rsp), %rdx
	movl	%ecx, 20(%rsp)
	leaq	64(%rsp), %rcx
	movl	%r8d, 16(%rsp)
	movl	%r9d, 12(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	64(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z20matrixMultiplicationPdS_S_iii(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 208
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L2:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2032:
	.size	_Z47__device_stub__Z20matrixMultiplicationPdS_S_iiiPdS_S_iii, .-_Z47__device_stub__Z20matrixMultiplicationPdS_S_iiiPdS_S_iii
	.globl	_Z20matrixMultiplicationPdS_S_iii
	.type	_Z20matrixMultiplicationPdS_S_iii, @function
_Z20matrixMultiplicationPdS_S_iii:
.LFB2033:
	.cfi_startproc
	endbr64
	jmp	_Z47__device_stub__Z20matrixMultiplicationPdS_S_iiiPdS_S_iii
	.cfi_endproc
.LFE2033:
	.size	_Z20matrixMultiplicationPdS_S_iii, .-_Z20matrixMultiplicationPdS_S_iii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z20matrixMultiplicationPdS_S_iii"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2035:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z20matrixMultiplicationPdS_S_iii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2035:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include "includes.h"

#define tileSize 32

//function for data initialization
void initialization( double *M,  double *N, int arow, int acol, int brow, int bcol);
//(for Debugging) prints out the input data
void printInput( double *M,  double *N, int arow, int acol, int brow,  int bcol);
//(for Debugging) prints out the output data
void printOutput( double *P_C,  double *P_G, int arow, int bcol);

//GPU kernels




__global__
__global__ void matrixMultiplication(double* M, double* N, double* P, int widthAHeightB, int heightA, int widthB) {

int Mstart=widthAHeightB*tileSize*blockIdx.y;
int Mend=Mstart+ widthAHeightB - 1;
int mstep=tileSize;
int Nstart=tileSize*blockIdx.x;
int nstep=tileSize*widthB;
double temp=0;

__shared__ double Ms[tileSize][tileSize];
__shared__ double Ns[tileSize][tileSize];

//area where the tiles fits without "cutting"
if(Mstart < (heightA/tileSize)*tileSize*widthAHeightB && Nstart%widthB < (widthB/tileSize)*tileSize ){
for(int m=Mstart,n=Nstart;m<Mend;m+=mstep,n+=nstep){
Ms[threadIdx.y][threadIdx.x]=M[m+widthAHeightB*threadIdx.y+threadIdx.x];
Ns[threadIdx.y][threadIdx.x]=N[n+widthB*threadIdx.y+threadIdx.x];
__syncthreads();


for (int i = 0; i < tileSize; ++i) {
temp += Ms[threadIdx.y][i] * Ns[i][threadIdx.x];
}
__syncthreads();

}
} else {//the rest of the matrix
for(int m=Mstart,n=Nstart;m<=Mend;m+=mstep,n+=nstep){

if(m%widthAHeightB + threadIdx.x < widthAHeightB && blockIdx.y*tileSize + threadIdx.y < heightA){
Ms[threadIdx.y][threadIdx.x]=M[m+widthAHeightB*threadIdx.y+threadIdx.x];
}
else{
Ms[threadIdx.y][threadIdx.x]=0.0;
}

if((n/widthB) + threadIdx.y < widthAHeightB && blockIdx.x*tileSize + threadIdx.x < widthB){
Ns[threadIdx.y][threadIdx.x]=N[n+widthB*threadIdx.y+threadIdx.x];
}
else{
Ns[threadIdx.y][threadIdx.x]=0.0;
}
__syncthreads();


for (int i = 0; i < tileSize; ++i) {
temp += Ms[threadIdx.y][i] * Ns[i][threadIdx.x];
}
__syncthreads();

}
}



if(blockIdx.y*tileSize + threadIdx.y < heightA && blockIdx.x*tileSize + threadIdx.x < widthB){
P[widthB * tileSize * blockIdx.y + tileSize * blockIdx.x + widthB * threadIdx.y + threadIdx.x] = temp;
}
}
	.text
	.file	"matrixMultiplication.hip"
	.globl	_Z35__device_stub__matrixMultiplicationPdS_S_iii # -- Begin function _Z35__device_stub__matrixMultiplicationPdS_S_iii
	.type	_Z35__device_stub__matrixMultiplicationPdS_S_iii,@function
_Z35__device_stub__matrixMultiplicationPdS_S_iii: # @_Z35__device_stub__matrixMultiplicationPdS_S_iii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	20(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	16(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	12(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z20matrixMultiplicationPdS_S_iii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z35__device_stub__matrixMultiplicationPdS_S_iii, .Lfunc_end0-_Z35__device_stub__matrixMultiplicationPdS_S_iii
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z20matrixMultiplicationPdS_S_iii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z20matrixMultiplicationPdS_S_iii,@object # @_Z20matrixMultiplicationPdS_S_iii
	.section	.rodata,"a",@progbits
	.globl	_Z20matrixMultiplicationPdS_S_iii
	.p2align	3, 0x0
_Z20matrixMultiplicationPdS_S_iii:
	.quad	_Z35__device_stub__matrixMultiplicationPdS_S_iii
	.size	_Z20matrixMultiplicationPdS_S_iii, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z20matrixMultiplicationPdS_S_iii"
	.size	.L__unnamed_1, 34

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z35__device_stub__matrixMultiplicationPdS_S_iii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z20matrixMultiplicationPdS_S_iii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z20matrixMultiplicationPdS_S_iii ; -- Begin function _Z20matrixMultiplicationPdS_S_iii
	.globl	_Z20matrixMultiplicationPdS_S_iii
	.p2align	8
	.type	_Z20matrixMultiplicationPdS_S_iii,@function
_Z20matrixMultiplicationPdS_S_iii:      ; @_Z20matrixMultiplicationPdS_S_iii
; %bb.0:
	s_clause 0x1
	s_load_b128 s[4:7], s[0:1], 0x18
	s_load_b128 s[8:11], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_ashr_i32 s2, s5, 31
	s_lshl_b32 s3, s4, 5
	s_lshr_b32 s2, s2, 27
	s_mul_i32 s7, s3, s15
	s_add_i32 s2, s5, s2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_ashr_i32 s2, s2, 5
	s_mul_i32 s2, s3, s2
	s_lshl_b32 s3, s14, 5
	s_cmp_ge_i32 s7, s2
	s_cselect_b32 s12, -1, 0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s12
	s_cbranch_vccnz .LBB0_2
; %bb.1:
	s_ashr_i32 s2, s6, 31
	s_ashr_i32 s16, s3, 31
	s_add_i32 s12, s6, s2
	s_add_i32 s17, s3, s16
	s_xor_b32 s12, s12, s2
	s_xor_b32 s17, s17, s16
	v_cvt_f32_u32_e32 v1, s12
	s_sub_i32 s14, 0, s12
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v1, v1
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v1, 0x4f7ffffe, v1
	v_cvt_u32_f32_e32 v1, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s13, v1
	s_mul_i32 s14, s14, s13
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_hi_u32 s14, s13, s14
	s_add_i32 s13, s13, s14
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_hi_u32 s13, s17, s13
	s_mul_i32 s13, s13, s12
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_sub_i32 s13, s17, s13
	s_sub_i32 s14, s13, s12
	s_cmp_ge_u32 s13, s12
	s_cselect_b32 s13, s14, s13
	s_delay_alu instid0(SALU_CYCLE_1)
	s_sub_i32 s14, s13, s12
	s_cmp_ge_u32 s13, s12
	s_cselect_b32 s12, s14, s13
	s_lshr_b32 s2, s2, 27
	s_xor_b32 s12, s12, s16
	s_add_i32 s2, s6, s2
	s_sub_i32 s12, s12, s16
	s_and_not1_b32 s2, s2, 31
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_ge_i32 s12, s2
	s_mov_b32 s2, -1
	s_cselect_b32 s12, -1, 0
	s_branch .LBB0_3
.LBB0_2:
	s_mov_b32 s2, 0
.LBB0_3:                                ; %Flow135
	s_add_i32 s13, s7, s4
	s_and_not1_b32 vcc_lo, exec_lo, s12
	s_lshl_b32 s12, s6, 5
	s_cbranch_vccnz .LBB0_13
; %bb.4:
	s_cmp_lt_i32 s4, 1
	s_cbranch_scc1 .LBB0_14
; %bb.5:                                ; %.lr.ph
	s_ashr_i32 s2, s4, 31
	s_ashr_i32 s14, s6, 31
	s_add_i32 s16, s4, s2
	s_add_i32 s17, s6, s14
	s_xor_b32 s16, s16, s2
	s_xor_b32 s17, s17, s14
	v_cvt_f32_u32_e32 v1, s16
	v_cvt_f32_u32_e32 v2, s17
	v_bfe_u32 v14, v0, 10, 10
	v_dual_mov_b32 v4, 0 :: v_dual_and_b32 v3, 0x3ff, v0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_rcp_iflag_f32_e32 v1, v1
	v_rcp_iflag_f32_e32 v2, v2
	v_mov_b32_e32 v7, 0
	v_lshlrev_b32_e32 v15, 8, v14
	v_dual_mov_b32 v5, 0 :: v_dual_add_nc_u32 v12, s3, v3
	v_lshlrev_b32_e32 v11, 3, v3
	v_lshl_add_u32 v6, s15, 5, v14
	v_mad_u64_u32 v[8:9], null, v14, s4, v[3:4]
	s_delay_alu instid0(TRANS32_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_dual_mul_f32 v1, 0x4f7ffffe, v1 :: v_dual_mul_f32 v2, 0x4f7ffffe, v2
	v_mad_u64_u32 v[9:10], null, v14, s6, v[3:4]
	s_sub_i32 s18, 0, s16
	v_cvt_u32_f32_e32 v1, v1
	s_delay_alu instid0(VALU_DEP_3)
	v_cvt_u32_f32_e32 v2, v2
	s_sub_i32 s19, 0, s17
	v_cmp_le_u32_e64 s2, s5, v6
	v_cmp_gt_u32_e32 vcc_lo, s6, v12
	v_readfirstlane_b32 s20, v1
	v_readfirstlane_b32 s21, v2
	v_dual_mov_b32 v1, v4 :: v_dual_mov_b32 v2, v5
	v_or_b32_e32 v16, 0x2000, v11
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	s_mul_i32 s18, s18, s20
	s_mul_i32 s19, s19, s21
	v_add_nc_u32_e32 v17, v15, v11
	s_mul_hi_u32 s18, s20, s18
	v_add_nc_u32_e32 v18, v16, v15
	s_mul_hi_u32 s19, s21, s19
	s_add_i32 s18, s20, s18
	s_add_i32 s19, s21, s19
	s_xor_b32 s20, s2, -1
	s_mov_b32 s21, s3
	s_mov_b32 s22, s7
.LBB0_6:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_11 Depth 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
	s_ashr_i32 s2, s22, 31
	v_mov_b32_e32 v11, v5
	s_add_i32 s23, s22, s2
	v_mov_b32_e32 v10, v4
	s_xor_b32 s23, s23, s2
	s_mul_hi_u32 s24, s23, s18
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s24, s24, s16
	s_sub_i32 s23, s23, s24
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_sub_i32 s24, s23, s16
	s_cmp_ge_u32 s23, s16
	s_cselect_b32 s23, s24, s23
	s_sub_i32 s24, s23, s16
	s_cmp_ge_u32 s23, s16
	s_cselect_b32 s23, s24, s23
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b32 s23, s23, s2
	s_sub_i32 s2, s23, s2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v6, s2, v3
	v_cmp_gt_u32_e64 s2, s4, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, s2, s20
	s_and_saveexec_b32 s23, s2
	s_cbranch_execz .LBB0_8
; %bb.7:                                ;   in Loop: Header=BB0_6 Depth=1
	v_add_nc_u32_e32 v6, s22, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[10:11], 3, v[6:7]
	v_add_co_u32 v10, s2, s8, v10
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v11, s2, s9, v11, s2
	global_load_b64 v[10:11], v[10:11], off
.LBB0_8:                                ;   in Loop: Header=BB0_6 Depth=1
	s_or_b32 exec_lo, exec_lo, s23
	s_ashr_i32 s2, s21, 31
	v_mov_b32_e32 v12, 0
	s_add_i32 s23, s21, s2
	s_waitcnt vmcnt(0)
	ds_store_b64 v17, v[10:11]
	s_xor_b32 s23, s23, s2
	s_xor_b32 s2, s2, s14
	s_mul_hi_u32 s24, s23, s19
	v_mov_b32_e32 v13, 0
	s_mul_i32 s25, s24, s17
	s_delay_alu instid0(SALU_CYCLE_1)
	s_sub_i32 s23, s23, s25
	s_add_i32 s25, s24, 1
	s_sub_i32 s26, s23, s17
	s_cmp_ge_u32 s23, s17
	s_cselect_b32 s24, s25, s24
	s_cselect_b32 s23, s26, s23
	s_add_i32 s25, s24, 1
	s_cmp_ge_u32 s23, s17
	s_cselect_b32 s23, s25, s24
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b32 s23, s23, s2
	s_sub_i32 s2, s23, s2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v6, s2, v14
	v_cmp_gt_u32_e64 s2, s4, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, vcc_lo, s2
	s_and_saveexec_b32 s23, s2
	s_cbranch_execz .LBB0_10
; %bb.9:                                ;   in Loop: Header=BB0_6 Depth=1
	v_add_nc_u32_e32 v6, s21, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[10:11], 3, v[6:7]
	v_add_co_u32 v10, s2, s10, v10
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v11, s2, s11, v11, s2
	global_load_b64 v[12:13], v[10:11], off
.LBB0_10:                               ;   in Loop: Header=BB0_6 Depth=1
	s_or_b32 exec_lo, exec_lo, s23
	v_mov_b32_e32 v6, v16
	s_mov_b32 s2, 0
	s_waitcnt vmcnt(0)
	ds_store_b64 v18, v[12:13]
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
.LBB0_11:                               ;   Parent Loop BB0_6 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_add_nc_u32_e32 v12, s2, v15
	s_add_i32 s2, s2, 8
	ds_load_b64 v[10:11], v6
	ds_load_b64 v[12:13], v12
	v_add_nc_u32_e32 v6, 0x100, v6
	s_cmpk_eq_i32 s2, 0x100
	s_waitcnt lgkmcnt(0)
	v_fma_f64 v[1:2], v[12:13], v[10:11], v[1:2]
	s_cbranch_scc0 .LBB0_11
; %bb.12:                               ;   in Loop: Header=BB0_6 Depth=1
	s_add_i32 s22, s22, 32
	s_add_i32 s21, s21, s12
	s_cmp_ge_i32 s22, s13
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc0 .LBB0_6
	s_branch .LBB0_15
.LBB0_13:
                                        ; implicit-def: $vgpr1_vgpr2
	s_branch .LBB0_16
.LBB0_14:
	v_mov_b32_e32 v1, 0
	v_mov_b32_e32 v2, 0
.LBB0_15:                               ; %Flow131
	s_mov_b32 s2, 0
.LBB0_16:                               ; %Flow136
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s2
	s_cbranch_vccnz .LBB0_22
; %bb.17:                               ; %.preheader
	v_mov_b32_e32 v1, 0
	v_mov_b32_e32 v2, 0
	s_add_i32 s13, s13, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_ge_i32 s7, s13
	s_cbranch_scc1 .LBB0_22
; %bb.18:                               ; %.lr.ph88
	v_dual_mov_b32 v1, 0 :: v_dual_and_b32 v6, 0x3ff, v0
	v_bfe_u32 v9, v0, 10, 10
	v_mov_b32_e32 v2, 0
	s_mov_b32 s2, s3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b32_e32 v10, 3, v6
	v_lshlrev_b32_e32 v7, 8, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or_b32_e32 v8, 0x2000, v10
	v_mad_u64_u32 v[3:4], null, v9, s4, v[6:7]
	v_mad_u64_u32 v[4:5], null, v9, s6, v[6:7]
	v_dual_mov_b32 v6, 0 :: v_dual_add_nc_u32 v9, v7, v10
	s_delay_alu instid0(VALU_DEP_4)
	v_add_nc_u32_e32 v10, v8, v7
.LBB0_19:                               ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_20 Depth 2
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v5, s7, v3
	s_mov_b32 s4, 0
	v_lshlrev_b64 v[11:12], 3, v[5:6]
	v_add_nc_u32_e32 v5, s2, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[13:14], 3, v[5:6]
	v_add_co_u32 v11, vcc_lo, s8, v11
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_co_ci_u32_e32 v12, vcc_lo, s9, v12, vcc_lo
	v_mov_b32_e32 v5, v8
	v_add_co_u32 v13, vcc_lo, s10, v13
	v_add_co_ci_u32_e32 v14, vcc_lo, s11, v14, vcc_lo
	global_load_b64 v[11:12], v[11:12], off
	global_load_b64 v[13:14], v[13:14], off
	s_waitcnt vmcnt(1)
	ds_store_b64 v9, v[11:12]
	s_waitcnt vmcnt(0)
	ds_store_b64 v10, v[13:14]
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
.LBB0_20:                               ;   Parent Loop BB0_19 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_add_nc_u32_e32 v13, s4, v7
	s_add_i32 s4, s4, 8
	ds_load_b64 v[11:12], v5
	ds_load_b64 v[13:14], v13
	v_add_nc_u32_e32 v5, 0x100, v5
	s_cmpk_eq_i32 s4, 0x100
	s_waitcnt lgkmcnt(0)
	v_fma_f64 v[1:2], v[13:14], v[11:12], v[1:2]
	s_cbranch_scc0 .LBB0_20
; %bb.21:                               ;   in Loop: Header=BB0_19 Depth=1
	s_add_i32 s7, s7, 32
	s_add_i32 s2, s2, s12
	s_cmp_ge_i32 s7, s13
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc0 .LBB0_19
.LBB0_22:                               ; %.loopexit
	v_bfe_u32 v3, v0, 10, 10
	v_and_b32_e32 v0, 0x3ff, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshl_add_u32 v4, s15, 5, v3
	v_add_nc_u32_e32 v0, s3, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_u32_e32 vcc_lo, s5, v4
	v_cmp_gt_u32_e64 s2, s6, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, vcc_lo, s2
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_24
; %bb.23:
	s_load_b64 s[0:1], s[0:1], 0x10
	v_mul_lo_u32 v3, v3, s6
	s_mul_i32 s12, s12, s15
	v_mov_b32_e32 v4, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v3, v0, v3, s12
	v_lshlrev_b64 v[3:4], 3, v[3:4]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, s0, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
	global_store_b64 v[3:4], v[1:2], off
.LBB0_24:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z20matrixMultiplicationPdS_S_iii
		.amdhsa_group_segment_fixed_size 16384
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 36
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 19
		.amdhsa_next_free_sgpr 27
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z20matrixMultiplicationPdS_S_iii, .Lfunc_end0-_Z20matrixMultiplicationPdS_S_iii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1448
; NumSgprs: 29
; NumVgprs: 19
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 16384 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 29
; NumVGPRsForWavesPerEU: 19
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     by_value
    .group_segment_fixed_size: 16384
    .kernarg_segment_align: 8
    .kernarg_segment_size: 36
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z20matrixMultiplicationPdS_S_iii
    .private_segment_fixed_size: 0
    .sgpr_count:     29
    .sgpr_spill_count: 0
    .symbol:         _Z20matrixMultiplicationPdS_S_iii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     19
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
