/**************
* HydroCuda model
*
* HBV hydrological model
* using cuda
***************/

#include <math.h>

__global__ void hbv_dynamic( float *q    ,
                             float *etr  ,
                             float *qin  ,
                             float *qlz  ,
                             float *qq   ,
                             float *qi   ,
                             float *qcf  ,
                             float *sp   ,
                             float *inet ,
                             float *qdr  ,
                             float *pp   ,
                             float *etp  ,
                             float *sm   ,
                             float *fc   ,
                             float *vlz  ,
                             float *vuz  ,
                             float *cflux,
                             float *icf  ,
                             float *beta ,
                             float *lp   ,
                             float *perc ,
                             float *uzl  ,
                             float *klz  ,
                             float *ki   ,
                             float *kq   )
{
  const int i = blockDim.x*blockDim.y*blockIdx.y*gridDim.x + 
                blockDim.x*blockDim.y*blockIdx.x + blockDim.x*threadIdx.y + threadIdx.x;
  // In flows
  if (pp[i] > icf[i]){
		qin[i] = pp[i] - icf[i];
	}
	else {
		qin[i] = 0.f;
	}
  etr[i]  = min(icf[i], etp[i]);
  // State variables
  sm[i]   = sm[i] + qin[i];
  qdr[i]  = max(sm[i] - fc[i], 0.f);
  sm[i]   = sm[i] - qdr[i];
  inet[i] = qin[i] - qdr[i];
  sp[i]   = pow(sm[i] / fc[i], beta[i]) * inet[i];
  sm[i]   = sm[i] - sp[i];
  // Evapotranspirations
  etp[i]  = etp[i] - etr[i];
  etr[i]  = min(min(sm[i] * etp[i] / (lp[i] * fc[i]), etp[i]), sm[i]);
  sm[i]   = sm[i] - etr[i];
  // Volume states
  vlz[i]  = vlz[i] + min(perc[i], qdr[i] + sp[i]);
  vuz[i]  = vuz[i] + max(0.f, qdr[i] + sp[i] - perc[i]);
  // Capillar flow
  qcf[i]  = cflux[i] * (fc[i] - sm[i]) / fc[i];
  sm[i]   = sm[i] + min(vuz[i], qcf[i]);
  vuz[i]  = max(vuz[i] - qcf[i], 0.f);
  // Quick and inter flow
  qq[i]   = max(kq[i] * (vuz[i] - uzl[i]), 0.f);
  qi[i]   = ki[i] * min(uzl[i], vuz[i]);
  // Base flow
  qlz[i]  = klz[i] * vlz[i];
  // Final flow
  q[i]    = qlz[i] + qi[i] + qq[i];
  
}


	.file	"tmpxft_00325211_00000000-6_hbv.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2010:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2010:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z79__device_stub__Z11hbv_dynamicPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_PfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_
	.type	_Z79__device_stub__Z11hbv_dynamicPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_PfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_, @function
_Z79__device_stub__Z11hbv_dynamicPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_PfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_:
.LFB2032:
	.cfi_startproc
	endbr64
	subq	$488, %rsp
	.cfi_def_cfa_offset 496
	movq	496(%rsp), %rax
	movq	%rdi, 200(%rsp)
	leaq	224(%rsp), %rdi
	movq	%rsi, 192(%rsp)
	leaq	236(%rsp), %rsi
	movq	%rax, 152(%rsp)
	movq	504(%rsp), %rax
	movq	%rdx, 184(%rsp)
	leaq	208(%rsp), %rdx
	movq	%rax, 144(%rsp)
	movq	512(%rsp), %rax
	movq	%rcx, 176(%rsp)
	leaq	216(%rsp), %rcx
	movq	%rax, 136(%rsp)
	movq	520(%rsp), %rax
	movq	%r8, 168(%rsp)
	movq	%rax, 128(%rsp)
	movq	528(%rsp), %rax
	movq	%r9, 160(%rsp)
	movq	%rax, 120(%rsp)
	movq	536(%rsp), %rax
	movq	%rax, 112(%rsp)
	movq	544(%rsp), %rax
	movq	%rax, 104(%rsp)
	movq	552(%rsp), %rax
	movq	%rax, 96(%rsp)
	movq	560(%rsp), %rax
	movq	%rax, 88(%rsp)
	movq	568(%rsp), %rax
	movq	%rax, 80(%rsp)
	movq	576(%rsp), %rax
	movq	%rax, 72(%rsp)
	movq	584(%rsp), %rax
	movq	%rax, 64(%rsp)
	movq	592(%rsp), %rax
	movq	%rax, 56(%rsp)
	movq	600(%rsp), %rax
	movq	%rax, 48(%rsp)
	movq	608(%rsp), %rax
	movq	%rax, 40(%rsp)
	movq	616(%rsp), %rax
	movq	%rax, 32(%rsp)
	movq	624(%rsp), %rax
	movq	%rax, 24(%rsp)
	movq	632(%rsp), %rax
	movq	%rax, 16(%rsp)
	movq	640(%rsp), %rax
	movq	%rax, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 472(%rsp)
	xorl	%eax, %eax
	leaq	200(%rsp), %rax
	movq	%rax, 272(%rsp)
	leaq	192(%rsp), %rax
	movq	%rax, 280(%rsp)
	leaq	184(%rsp), %rax
	movq	%rax, 288(%rsp)
	leaq	176(%rsp), %rax
	movq	%rax, 296(%rsp)
	leaq	168(%rsp), %rax
	movq	%rax, 304(%rsp)
	leaq	160(%rsp), %rax
	movq	%rax, 312(%rsp)
	leaq	152(%rsp), %rax
	movq	%rax, 320(%rsp)
	leaq	144(%rsp), %rax
	movq	%rax, 328(%rsp)
	leaq	136(%rsp), %rax
	movq	%rax, 336(%rsp)
	leaq	128(%rsp), %rax
	movq	%rax, 344(%rsp)
	leaq	120(%rsp), %rax
	movq	%rax, 352(%rsp)
	leaq	112(%rsp), %rax
	movq	%rax, 360(%rsp)
	leaq	104(%rsp), %rax
	movq	%rax, 368(%rsp)
	leaq	96(%rsp), %rax
	movq	%rax, 376(%rsp)
	leaq	88(%rsp), %rax
	movq	%rax, 384(%rsp)
	leaq	80(%rsp), %rax
	movq	%rax, 392(%rsp)
	leaq	72(%rsp), %rax
	movq	%rax, 400(%rsp)
	leaq	64(%rsp), %rax
	movq	%rax, 408(%rsp)
	leaq	56(%rsp), %rax
	movq	%rax, 416(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 424(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 432(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 440(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 448(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 456(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 464(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 224(%rsp)
	movl	$1, 232(%rsp)
	movq	%rax, 236(%rsp)
	movl	$1, 244(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	216(%rsp)
	.cfi_def_cfa_offset 504
	leaq	_Z11hbv_dynamicPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_(%rip), %rdi
	pushq	216(%rsp)
	.cfi_def_cfa_offset 512
	movq	252(%rsp), %rcx
	movl	260(%rsp), %r8d
	movq	240(%rsp), %rsi
	movl	248(%rsp), %edx
	leaq	288(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 504
	popq	%rdx
	.cfi_def_cfa_offset 496
.L2:
	movq	472(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$488, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2032:
	.size	_Z79__device_stub__Z11hbv_dynamicPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_PfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_, .-_Z79__device_stub__Z11hbv_dynamicPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_PfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_
	.globl	_Z11hbv_dynamicPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_
	.type	_Z11hbv_dynamicPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_, @function
_Z11hbv_dynamicPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_:
.LFB2033:
	.cfi_startproc
	endbr64
	jmp	_Z79__device_stub__Z11hbv_dynamicPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_PfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_
	.cfi_endproc
.LFE2033:
	.size	_Z11hbv_dynamicPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_, .-_Z11hbv_dynamicPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z11hbv_dynamicPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2035:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z11hbv_dynamicPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2035:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

/**************
* HydroCuda model
*
* HBV hydrological model
* using cuda
***************/


#include <hip/hip_runtime.h>
#include <math.h>

__global__ void hbv_dynamic( float *q    ,
                             float *etr  ,
                             float *qin  ,
                             float *qlz  ,
                             float *qq   ,
                             float *qi   ,
                             float *qcf  ,
                             float *sp   ,
                             float *inet ,
                             float *qdr  ,
                             float *pp   ,
                             float *etp  ,
                             float *sm   ,
                             float *fc   ,
                             float *vlz  ,
                             float *vuz  ,
                             float *cflux,
                             float *icf  ,
                             float *beta ,
                             float *lp   ,
                             float *perc ,
                             float *uzl  ,
                             float *klz  ,
                             float *ki   ,
                             float *kq   )
{
  const int i = blockDim.x*blockDim.y*blockIdx.y*gridDim.x + 
                blockDim.x*blockDim.y*blockIdx.x + blockDim.x*threadIdx.y + threadIdx.x;
  // In flows
  if (pp[i] > icf[i]){
		qin[i] = pp[i] - icf[i];
	}
	else {
		qin[i] = 0.f;
	}
  etr[i]  = min(icf[i], etp[i]);
  // State variables
  sm[i]   = sm[i] + qin[i];
  qdr[i]  = max(sm[i] - fc[i], 0.f);
  sm[i]   = sm[i] - qdr[i];
  inet[i] = qin[i] - qdr[i];
  sp[i]   = pow(sm[i] / fc[i], beta[i]) * inet[i];
  sm[i]   = sm[i] - sp[i];
  // Evapotranspirations
  etp[i]  = etp[i] - etr[i];
  etr[i]  = min(min(sm[i] * etp[i] / (lp[i] * fc[i]), etp[i]), sm[i]);
  sm[i]   = sm[i] - etr[i];
  // Volume states
  vlz[i]  = vlz[i] + min(perc[i], qdr[i] + sp[i]);
  vuz[i]  = vuz[i] + max(0.f, qdr[i] + sp[i] - perc[i]);
  // Capillar flow
  qcf[i]  = cflux[i] * (fc[i] - sm[i]) / fc[i];
  sm[i]   = sm[i] + min(vuz[i], qcf[i]);
  vuz[i]  = max(vuz[i] - qcf[i], 0.f);
  // Quick and inter flow
  qq[i]   = max(kq[i] * (vuz[i] - uzl[i]), 0.f);
  qi[i]   = ki[i] * min(uzl[i], vuz[i]);
  // Base flow
  qlz[i]  = klz[i] * vlz[i];
  // Final flow
  q[i]    = qlz[i] + qi[i] + qq[i];
  
}


	.text
	.file	"hbv.hip"
	.globl	_Z26__device_stub__hbv_dynamicPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_ # -- Begin function _Z26__device_stub__hbv_dynamicPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_
	.type	_Z26__device_stub__hbv_dynamicPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_,@function
_Z26__device_stub__hbv_dynamicPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_: # @_Z26__device_stub__hbv_dynamicPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$304, %rsp                      # imm = 0x130
	.cfi_def_cfa_offset 352
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	352(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	360(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	368(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	376(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	384(%rsp), %rax
	movq	%rax, 80(%rbx)
	leaq	392(%rsp), %rax
	movq	%rax, 88(%rbx)
	leaq	400(%rsp), %rax
	movq	%rax, 96(%rbx)
	leaq	408(%rsp), %rax
	movq	%rax, 104(%rbx)
	leaq	416(%rsp), %rax
	movq	%rax, 112(%rbx)
	leaq	424(%rsp), %rax
	movq	%rax, 120(%rbx)
	leaq	432(%rsp), %rax
	movq	%rax, 128(%rbx)
	leaq	440(%rsp), %rax
	movq	%rax, 136(%rbx)
	leaq	448(%rsp), %rax
	movq	%rax, 144(%rbx)
	leaq	456(%rsp), %rax
	movq	%rax, 152(%rbx)
	leaq	464(%rsp), %rax
	movq	%rax, 160(%rbx)
	leaq	472(%rsp), %rax
	movq	%rax, 168(%rbx)
	leaq	480(%rsp), %rax
	movq	%rax, 176(%rbx)
	leaq	488(%rsp), %rax
	movq	%rax, 184(%rbx)
	leaq	496(%rsp), %rax
	movq	%rax, 192(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z11hbv_dynamicPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$320, %rsp                      # imm = 0x140
	.cfi_adjust_cfa_offset -320
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z26__device_stub__hbv_dynamicPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_, .Lfunc_end0-_Z26__device_stub__hbv_dynamicPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z11hbv_dynamicPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z11hbv_dynamicPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_,@object # @_Z11hbv_dynamicPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_
	.section	.rodata,"a",@progbits
	.globl	_Z11hbv_dynamicPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_
	.p2align	3, 0x0
_Z11hbv_dynamicPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_:
	.quad	_Z26__device_stub__hbv_dynamicPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_
	.size	_Z11hbv_dynamicPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z11hbv_dynamicPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_"
	.size	.L__unnamed_1, 66

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z26__device_stub__hbv_dynamicPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z11hbv_dynamicPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z11hbv_dynamicPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_ ; -- Begin function _Z11hbv_dynamicPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_
	.globl	_Z11hbv_dynamicPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_
	.p2align	8
	.type	_Z11hbv_dynamicPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_,@function
_Z11hbv_dynamicPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_: ; @_Z11hbv_dynamicPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0xc8
	s_load_b32 s3, s[0:1], 0xd4
	v_bfe_u32 v1, v0, 10, 10
	v_and_b32_e32 v0, 0x3ff, v0
	s_clause 0x1
	s_load_b512 s[52:67], s[0:1], 0x40
	s_load_b512 s[36:51], s[0:1], 0x80
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s2, s2, s15
	s_lshr_b32 s4, s3, 16
	s_add_i32 s2, s2, s14
	s_load_b512 s[8:23], s[0:1], 0x0
	v_mad_u64_u32 v[2:3], null, s2, s4, v[1:2]
	s_and_b32 s2, s3, 0xffff
	s_load_b64 s[0:1], s[0:1], 0xc0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[3:4], null, v2, s2, v[0:1]
	s_mov_b32 s2, 0x3e76c4e1
	v_ashrrev_i32_e32 v4, 31, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[3:4]
	v_add_co_u32 v2, vcc_lo, s56, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s57, v1, vcc_lo
	v_add_co_u32 v4, vcc_lo, s38, v0
	v_add_co_ci_u32_e32 v5, vcc_lo, s39, v1, vcc_lo
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v6, vcc_lo, s12, v0
	global_load_b32 v2, v[2:3], off
	global_load_b32 v3, v[4:5], off
	v_add_co_ci_u32_e32 v7, vcc_lo, s13, v1, vcc_lo
	s_waitcnt vmcnt(0)
	v_sub_f32_e32 v8, v2, v3
	v_cmp_gt_f32_e32 vcc_lo, v2, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_cndmask_b32_e32 v2, 0, v8, vcc_lo
	v_add_co_u32 v8, vcc_lo, s58, v0
	v_add_co_ci_u32_e32 v9, vcc_lo, s59, v1, vcc_lo
	global_store_b32 v[6:7], v2, off
	global_load_b32 v2, v[8:9], off
	global_load_b32 v3, v[4:5], off
	v_add_co_u32 v10, vcc_lo, s10, v0
	v_add_co_ci_u32_e32 v11, vcc_lo, s11, v1, vcc_lo
	s_waitcnt vmcnt(0)
	v_dual_max_f32 v2, v2, v2 :: v_dual_max_f32 v3, v3, v3
	s_delay_alu instid0(VALU_DEP_1)
	v_min_f32_e32 v4, v3, v2
	v_add_co_u32 v2, vcc_lo, s60, v0
	v_add_co_ci_u32_e32 v3, vcc_lo, s61, v1, vcc_lo
	global_store_b32 v[10:11], v4, off
	global_load_b32 v4, v[2:3], off
	global_load_b32 v5, v[6:7], off
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v12, v4, v5
	v_add_co_u32 v4, vcc_lo, s62, v0
	v_add_co_ci_u32_e32 v5, vcc_lo, s63, v1, vcc_lo
	global_store_b32 v[2:3], v12, off
	global_load_b32 v13, v[4:5], off
	s_waitcnt vmcnt(0)
	v_sub_f32_e32 v14, v12, v13
	v_add_co_u32 v12, vcc_lo, s54, v0
	v_add_co_ci_u32_e32 v13, vcc_lo, s55, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_3)
	v_max_f32_e32 v14, 0, v14
	global_store_b32 v[12:13], v14, off
	global_load_b32 v15, v[2:3], off
	s_waitcnt vmcnt(0)
	v_sub_f32_e32 v14, v15, v14
	global_store_b32 v[2:3], v14, off
	global_load_b32 v14, v[6:7], off
	global_load_b32 v15, v[12:13], off
	v_add_co_u32 v6, vcc_lo, s52, v0
	v_add_co_ci_u32_e32 v7, vcc_lo, s53, v1, vcc_lo
	s_waitcnt vmcnt(0)
	v_sub_f32_e32 v14, v14, v15
	global_store_b32 v[6:7], v14, off
	global_load_b32 v15, v[2:3], off
	global_load_b32 v16, v[4:5], off
	v_add_co_u32 v6, vcc_lo, s40, v0
	v_add_co_ci_u32_e32 v7, vcc_lo, s41, v1, vcc_lo
	global_load_b32 v6, v[6:7], off
	s_waitcnt vmcnt(1)
	v_div_scale_f32 v7, null, v16, v16, v15
	v_div_scale_f32 v19, vcc_lo, v15, v16, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v17, v7
	s_waitcnt_depctr 0xfff
	v_fma_f32 v18, -v7, v17, 1.0
	v_fmac_f32_e32 v17, v18, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v18, v19, v17
	v_fma_f32 v20, -v7, v18, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v18, v20, v17
	v_fma_f32 v7, -v7, v18, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v7, v7, v17, v18
	v_div_fixup_f32 v7, v7, v16, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_cmp_neq_f32_e32 vcc_lo, 1.0, v7
	s_waitcnt vmcnt(0)
	v_cndmask_b32_e32 v6, 1.0, v6, vcc_lo
	v_cmp_neq_f32_e32 vcc_lo, 0, v6
	v_cndmask_b32_e32 v7, 1.0, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_frexp_mant_f32_e64 v15, |v7|
	v_cmp_lt_f32_e64 s6, |v7|, 1.0
	v_cmp_eq_f32_e64 s4, 0, v7
	v_cmp_gt_f32_e32 vcc_lo, 0x3f2aaaab, v15
	v_cndmask_b32_e64 v16, 0, 1, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ldexp_f32 v15, v15, v16
	v_add_f32_e32 v16, 1.0, v15
	v_add_f32_e32 v18, -1.0, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v17, v16
	v_add_f32_e32 v20, -1.0, v16
	v_sub_f32_e32 v15, v15, v20
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v19, v18, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v21, v16, v19
	v_fma_f32 v16, v19, v16, -v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v16, v19, v15
	v_add_f32_e32 v15, v21, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v20, v18, v15 :: v_dual_sub_f32 v21, v15, v21
	v_sub_f32_e32 v18, v18, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v16, v21, v16 :: v_dual_sub_f32 v15, v18, v15
	v_add_f32_e32 v15, v16, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v15, v20, v15
	v_mul_f32_e32 v15, v17, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v16, v19, v15
	v_sub_f32_e32 v17, v16, v19
	v_mul_f32_e32 v18, v16, v16
	v_cmp_neq_f32_e64 s5, v6, |v6|
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v15, v15, v17
	v_fma_f32 v17, v16, v16, -v18
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	s_xor_b32 s5, s5, s6
	v_add_f32_e32 v19, v15, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v17, v16, v19
	v_add_f32_e32 v19, v18, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmaak_f32 v20, s2, v19, 0x3e91f4c4
	v_sub_f32_e32 v18, v19, v18
	v_dual_fmaak_f32 v20, v19, v20, 0x3ecccdef :: v_dual_sub_f32 v17, v17, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v21, v19, v20
	v_fma_f32 v18, v19, v20, -v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v18, v17, v20
	v_add_f32_e32 v20, v21, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v21, v20, v21 :: v_dual_add_f32 v22, 0x3f2aaaaa, v20
	v_dual_sub_f32 v18, v18, v21 :: v_dual_add_f32 v21, 0xbf2aaaaa, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v23, v16, v19 :: v_dual_add_f32 v18, 0x31739010, v18
	v_fma_f32 v24, v19, v16, -v23
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v24, v19, v15
	v_ldexp_f32 v15, v15, 1
	v_fmac_f32_e32 v24, v17, v16
	v_ldexp_f32 v16, v16, 1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v19, v23, v24 :: v_dual_sub_f32 v20, v20, v21
	v_add_f32_e32 v18, v18, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v17, v22, v18
	v_sub_f32_e32 v20, v22, v17
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v21, v19, v17
	v_sub_f32_e32 v22, v19, v23
	v_add_f32_e32 v18, v18, v20
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v20, v19, v17, -v21
	v_sub_f32_e32 v22, v24, v22
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v20, v19, v18
	v_frexp_exp_i32_f32_e32 v18, v7
	v_fmac_f32_e32 v20, v22, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_subrev_co_ci_u32_e32 v17, vcc_lo, 0, v18, vcc_lo
	v_add_f32_e32 v18, v21, v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_f32_i32_e32 v17, v17
	v_add_f32_e32 v19, v16, v18
	v_sub_f32_e32 v21, v18, v21
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v22, 0x3f317218, v17
	v_sub_f32_e32 v16, v19, v16
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v20, v20, v21
	v_fma_f32 v21, 0x3f317218, v17, -v22
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v16, v18, v16
	v_add_f32_e32 v15, v15, v20
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmamk_f32 v17, v17, 0xb102e308, v21
	v_dual_add_f32 v15, v15, v16 :: v_dual_add_f32 v16, v22, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v18, v19, v15
	v_sub_f32_e32 v22, v16, v22
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_add_f32 v20, v16, v18 :: v_dual_sub_f32 v19, v18, v19
	v_sub_f32_e32 v17, v17, v22
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v21, v20, v16
	v_sub_f32_e32 v15, v15, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v23, v20, v21
	v_dual_sub_f32 v18, v18, v21 :: v_dual_add_f32 v19, v17, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v16, v16, v23
	v_add_f32_e32 v16, v18, v16
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v18, v19, v17
	v_add_f32_e32 v16, v19, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v19, v19, v18
	v_sub_f32_e32 v15, v15, v18
	v_add_f32_e32 v21, v20, v16
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v17, v17, v19
	v_dual_sub_f32 v18, v21, v20 :: v_dual_add_f32 v15, v15, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v16, v16, v18
	v_add_f32_e32 v15, v15, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v16, v21, v15
	v_dual_sub_f32 v17, v16, v21 :: v_dual_mul_f32 v18, v6, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v15, v15, v17
	v_fma_f32 v16, v6, v16, -v18
	v_cmp_class_f32_e64 vcc_lo, v18, 0x204
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v16, v6, v15
	v_add_f32_e32 v15, v18, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v17, v15, v18, vcc_lo
	v_sub_f32_e32 v15, v15, v18
	v_cmp_eq_f32_e32 vcc_lo, 0x42b17218, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v15, v16, v15
	v_cndmask_b32_e64 v19, 0, 0x37000000, vcc_lo
	v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v17|
	v_sub_f32_e32 v20, v17, v19
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v15, 0, v15, vcc_lo
	v_trunc_f32_e32 v17, v6
	v_mul_f32_e32 v21, 0x3fb8aa3b, v20
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v20
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v15, v19, v15
	v_fma_f32 v22, 0x3fb8aa3b, v20, -v21
	v_rndne_f32_e32 v23, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_fmamk_f32 v22, v20, 0x32a5705f, v22 :: v_dual_sub_f32 v21, v21, v23
	v_cvt_i32_f32_e32 v18, v23
	v_add_f32_e32 v21, v21, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_exp_f32_e32 v21, v21
	s_waitcnt_depctr 0xfff
	v_ldexp_f32 v16, v21, v18
	v_mul_f32_e32 v18, 0.5, v6
	v_cndmask_b32_e32 v16, 0, v16, vcc_lo
	v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v20
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_trunc_f32_e32 v21, v18
	v_cndmask_b32_e32 v16, 0x7f800000, v16, vcc_lo
	v_cmp_eq_f32_e32 vcc_lo, v17, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_neq_f32_e64 s2, v21, v18
	v_fma_f32 v15, v16, v15, v16
	v_cmp_eq_f32_e64 s3, 0x7f800000, v16
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, vcc_lo, s2
	v_cndmask_b32_e64 v17, 1.0, v7, s2
	v_cndmask_b32_e64 v19, 0, v7, s2
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v15, v15, v16, s3
	v_cmp_gt_f32_e64 s3, 0, v6
	v_cndmask_b32_e64 v16, |v6|, 0, s5
	v_cmp_class_f32_e64 s2, v7, 0x204
	v_bfi_b32 v15, 0x7fffffff, v15, v17
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b32 s3, s3, s4
	v_cndmask_b32_e64 v17, 0x7f800000, 0, s3
	v_cmp_eq_f32_e64 s3, |v7|, 1.0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cndmask_b32_e32 v18, 0x7fc00000, v15, vcc_lo
	v_cmp_gt_f32_e32 vcc_lo, 0, v7
	v_bfi_b32 v17, 0x7fffffff, v17, v19
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v16, v16, |v7|, s3
	v_cndmask_b32_e32 v15, v15, v18, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v6, 0x204
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v15, v15, v16, vcc_lo
	s_or_b32 vcc_lo, s4, s2
	v_cndmask_b32_e32 v15, v15, v17, vcc_lo
	v_cmp_o_f32_e32 vcc_lo, v7, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v15, 0x7fc00000, v15, vcc_lo
	v_add_co_u32 v6, vcc_lo, s22, v0
	v_add_co_ci_u32_e32 v7, vcc_lo, s23, v1, vcc_lo
	v_mul_f32_e32 v16, v14, v15
	global_store_b32 v[6:7], v16, off
	global_load_b32 v16, v[2:3], off
	s_waitcnt vmcnt(0)
	v_fma_f32 v14, -v14, v15, v16
	global_store_b32 v[2:3], v14, off
	global_load_b32 v14, v[8:9], off
	global_load_b32 v15, v[10:11], off
	s_waitcnt vmcnt(0)
	v_sub_f32_e32 v16, v14, v15
	v_add_co_u32 v14, vcc_lo, s42, v0
	v_add_co_ci_u32_e32 v15, vcc_lo, s43, v1, vcc_lo
	global_store_b32 v[8:9], v16, off
	global_load_b32 v8, v[2:3], off
	global_load_b32 v9, v[14:15], off
	global_load_b32 v14, v[4:5], off
	s_waitcnt vmcnt(2)
	v_mul_f32_e32 v15, v16, v8
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v9, v9, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f32 v14, null, v9, v9, v15
	v_div_scale_f32 v19, vcc_lo, v15, v9, v15
	v_rcp_f32_e32 v17, v14
	s_waitcnt_depctr 0xfff
	v_fma_f32 v18, -v14, v17, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v17, v18, v17
	v_mul_f32_e32 v18, v19, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v20, -v14, v18, v19
	v_fmac_f32_e32 v18, v20, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v14, -v14, v18, v19
	v_div_fmas_f32 v14, v14, v17, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f32 v9, v14, v9, v15
	v_min3_f32 v8, v9, v16, v8
	global_store_b32 v[10:11], v8, off
	global_load_b32 v9, v[2:3], off
	s_waitcnt vmcnt(0)
	v_sub_f32_e32 v10, v9, v8
	v_add_co_u32 v8, vcc_lo, s44, v0
	v_add_co_ci_u32_e32 v9, vcc_lo, s45, v1, vcc_lo
	global_store_b32 v[2:3], v10, off
	global_load_b32 v14, v[12:13], off
	global_load_b32 v15, v[6:7], off
	global_load_b32 v16, v[8:9], off
	v_add_co_u32 v10, vcc_lo, s64, v0
	v_add_co_ci_u32_e32 v11, vcc_lo, s65, v1, vcc_lo
	global_load_b32 v17, v[10:11], off
	s_waitcnt vmcnt(1)
	v_dual_add_f32 v14, v14, v15 :: v_dual_max_f32 v15, v16, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_min_f32_e32 v14, v15, v14
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v14, v17, v14
	global_store_b32 v[10:11], v14, off
	global_load_b32 v12, v[12:13], off
	global_load_b32 v13, v[6:7], off
	global_load_b32 v8, v[8:9], off
	v_add_co_u32 v6, vcc_lo, s66, v0
	v_add_co_ci_u32_e32 v7, vcc_lo, s67, v1, vcc_lo
	global_load_b32 v9, v[6:7], off
	s_waitcnt vmcnt(2)
	v_add_f32_e32 v12, v12, v13
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v8, v12, v8
	v_max_f32_e32 v8, 0, v8
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f32_e32 v12, v9, v8
	v_add_co_u32 v8, vcc_lo, s36, v0
	v_add_co_ci_u32_e32 v9, vcc_lo, s37, v1, vcc_lo
	global_store_b32 v[6:7], v12, off
	global_load_b32 v12, v[4:5], off
	global_load_b32 v4, v[2:3], off
	global_load_b32 v5, v[8:9], off
	s_waitcnt vmcnt(1)
	v_sub_f32_e32 v4, v12, v4
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v8, v5, v4
	v_div_scale_f32 v4, null, v12, v12, v8
	v_div_scale_f32 v13, vcc_lo, v8, v12, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v5, v4
	s_waitcnt_depctr 0xfff
	v_fma_f32 v9, -v4, v5, 1.0
	v_fmac_f32_e32 v5, v9, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v9, v13, v5
	v_fma_f32 v14, -v4, v9, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v9, v14, v5
	v_fma_f32 v4, -v4, v9, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_div_fmas_f32 v9, v4, v5, v9
	v_add_co_u32 v4, vcc_lo, s20, v0
	v_add_co_ci_u32_e32 v5, vcc_lo, s21, v1, vcc_lo
	v_div_fixup_f32 v8, v9, v12, v8
	global_store_b32 v[4:5], v8, off
	global_load_b32 v9, v[6:7], off
	global_load_b32 v12, v[2:3], off
	s_waitcnt vmcnt(1)
	v_max_f32_e32 v9, v9, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_min_f32_e32 v8, v9, v8
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v8, v12, v8
	global_store_b32 v[2:3], v8, off
	global_load_b32 v2, v[6:7], off
	global_load_b32 v3, v[4:5], off
	s_waitcnt vmcnt(0)
	v_sub_f32_e32 v4, v2, v3
	v_add_co_u32 v2, vcc_lo, s46, v0
	v_add_co_ci_u32_e32 v3, vcc_lo, s47, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_3)
	v_max_f32_e32 v8, 0, v4
	v_add_co_u32 v4, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v5, vcc_lo, s1, v1, vcc_lo
	global_store_b32 v[6:7], v8, off
	global_load_b32 v9, v[2:3], off
	global_load_b32 v4, v[4:5], off
	s_waitcnt vmcnt(1)
	v_sub_f32_e32 v5, v8, v9
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v8, v4, v5
	v_add_co_u32 v4, vcc_lo, s16, v0
	v_add_co_ci_u32_e32 v5, vcc_lo, s17, v1, vcc_lo
	v_max_f32_e32 v8, 0, v8
	global_store_b32 v[4:5], v8, off
	global_load_b32 v6, v[6:7], off
	global_load_b32 v7, v[2:3], off
	v_add_co_u32 v2, vcc_lo, s50, v0
	v_add_co_ci_u32_e32 v3, vcc_lo, s51, v1, vcc_lo
	global_load_b32 v8, v[2:3], off
	s_waitcnt vmcnt(1)
	v_dual_max_f32 v2, v6, v6 :: v_dual_max_f32 v3, v7, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_min_f32_e32 v6, v3, v2
	v_add_co_u32 v2, vcc_lo, s18, v0
	v_add_co_ci_u32_e32 v3, vcc_lo, s19, v1, vcc_lo
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v8, v8, v6
	v_add_co_u32 v6, vcc_lo, s48, v0
	v_add_co_ci_u32_e32 v7, vcc_lo, s49, v1, vcc_lo
	global_store_b32 v[2:3], v8, off
	global_load_b32 v8, v[6:7], off
	global_load_b32 v9, v[10:11], off
	v_add_co_u32 v6, vcc_lo, s14, v0
	v_add_co_ci_u32_e32 v7, vcc_lo, s15, v1, vcc_lo
	v_add_co_u32 v0, vcc_lo, s8, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s9, v1, vcc_lo
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v10, v8, v9
	global_store_b32 v[6:7], v10, off
	global_load_b32 v2, v[2:3], off
	global_load_b32 v3, v[4:5], off
	s_waitcnt vmcnt(1)
	v_fmac_f32_e32 v2, v8, v9
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f32_e32 v2, v2, v3
	global_store_b32 v[0:1], v2, off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z11hbv_dynamicPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 456
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 25
		.amdhsa_next_free_sgpr 68
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z11hbv_dynamicPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_, .Lfunc_end0-_Z11hbv_dynamicPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 2744
; NumSgprs: 70
; NumVgprs: 25
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 8
; VGPRBlocks: 3
; NumSGPRsForWavesPerEU: 70
; NumVGPRsForWavesPerEU: 25
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         48
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         56
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         64
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         72
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         80
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         88
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         96
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         104
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         112
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         120
        .size:           8
        .value_kind:     global_buffer
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        .value_kind:     hidden_block_count_x
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        .size:           4
        .value_kind:     hidden_block_count_y
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        .size:           4
        .value_kind:     hidden_block_count_z
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    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 456
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z11hbv_dynamicPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_
    .private_segment_fixed_size: 0
    .sgpr_count:     70
    .sgpr_spill_count: 0
    .symbol:         _Z11hbv_dynamicPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     25
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
