#include <stdio.h>
#include <math.h>

#define CUDA_CALL(c) \
    do {                                            \
        cudaError_t res = c;                        \
        if (res != cudaSuccess) {                   \
            fprintf(stderr, "error at line %d: %s \n", __LINE__, cudaGetErrorString(res));    \
            exit(EXIT_FAILURE);                     \
        }                                           \
    } while (0)

// Problem dimension
#define STENCIL_SIZE (16 * 1024 * 1024)
#define RADIUS (3)
#define NUM_CHANNELS (4)

#define BLOCK_SIZE (32)

// Given the pixel index and channel, return the position of the
// element in the 1D array.
static __device__ __host__ int getIndex(int index, int channel)
{
    return index * NUM_CHANNELS + channel;
}

static __constant__ int weight[RADIUS * 2 + 1] = {
    1, 2, 3, 4, 3, 2, 1
};
static __constant__ int denominator = 16;

__global__ void stencilKernel(unsigned char *in,
                              int numPixels,
                              unsigned char *out)
{
    int i = blockIdx.x * blockDim.x + threadIdx.x;
    int radius, channel;
    int outLocal[NUM_CHANNELS] = { 0 };

    if (i < RADIUS) {
        return;
    }

    if (i >= numPixels - RADIUS) {
        return;
    }

    for (radius = -RADIUS; radius <= RADIUS; ++radius) {
        for (channel = 0; channel < NUM_CHANNELS; ++channel) {
            outLocal[channel] += (int)in[getIndex(i + radius, channel)] * weight[RADIUS + radius];
        }
    }

    for (channel = 0; channel < NUM_CHANNELS; ++channel) {
        out[getIndex(i, channel)] = (unsigned char)(outLocal[channel] / denominator);
    }
}

static void stencilGpu(unsigned char *in,
                       int numPixels,
                       unsigned char *out)
{
    unsigned char *inGPU;
    unsigned char *outGPU;
    size_t arraySize;

    arraySize = numPixels * NUM_CHANNELS * sizeof(unsigned char);

    CUDA_CALL(cudaMalloc(&inGPU, arraySize));
    CUDA_CALL(cudaMalloc(&outGPU, arraySize));

    CUDA_CALL(cudaMemcpy(inGPU, in, arraySize, cudaMemcpyHostToDevice));

    stencilKernel<<<ceil((float)numPixels / BLOCK_SIZE), BLOCK_SIZE>>>(inGPU, numPixels, outGPU);
    CUDA_CALL(cudaGetLastError());
    CUDA_CALL(cudaDeviceSynchronize());

    CUDA_CALL(cudaMemcpy(out, outGPU, arraySize, cudaMemcpyDeviceToHost));

    CUDA_CALL(cudaFree(inGPU));
    CUDA_CALL(cudaFree(outGPU));
}

int main()
{
    unsigned char *in;
    unsigned char *outGPU;
    size_t arraySize = STENCIL_SIZE * NUM_CHANNELS * sizeof(unsigned char);

    in = (unsigned char *)malloc(arraySize);
    outGPU = (unsigned char *)malloc(arraySize);
    if (in == NULL || outGPU == NULL) {
        fprintf(stderr, "Allocation failed\n");
        exit(EXIT_FAILURE);
    }

    stencilGpu(in, STENCIL_SIZE, outGPU);

    free(in);
    free(outGPU);

    return 0;
}

	.file	"tmpxft_002e40df_00000000-6_stencil0_orig.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2032:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2032:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z36__device_stub__Z13stencilKernelPhiS_PhiS_
	.type	_Z36__device_stub__Z13stencilKernelPhiS_PhiS_, @function
_Z36__device_stub__Z13stencilKernelPhiS_PhiS_:
.LFB2054:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movl	%esi, 20(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z13stencilKernelPhiS_(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L2:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2054:
	.size	_Z36__device_stub__Z13stencilKernelPhiS_PhiS_, .-_Z36__device_stub__Z13stencilKernelPhiS_PhiS_
	.globl	_Z13stencilKernelPhiS_
	.type	_Z13stencilKernelPhiS_, @function
_Z13stencilKernelPhiS_:
.LFB2055:
	.cfi_startproc
	endbr64
	jmp	_Z36__device_stub__Z13stencilKernelPhiS_PhiS_
	.cfi_endproc
.LFE2055:
	.size	_Z13stencilKernelPhiS_, .-_Z13stencilKernelPhiS_
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"Allocation failed\n"
.LC1:
	.string	"error at line %d: %s \n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2029:
	.cfi_startproc
	endbr64
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	movl	$67108864, %edi
	pushq	%rbx
	.cfi_def_cfa_offset 24
	.cfi_offset 3, -24
	subq	$56, %rsp
	.cfi_def_cfa_offset 80
	movq	%fs:40, %rax
	movq	%rax, 40(%rsp)
	xorl	%eax, %eax
	call	malloc@PLT
	movl	$67108864, %edi
	movq	%rax, %rbp
	call	malloc@PLT
	testq	%rbp, %rbp
	je	.L21
	movq	%rax, %rbx
	testq	%rax, %rax
	jne	.L9
.L21:
	movq	stderr(%rip), %rdi
	leaq	.LC0(%rip), %rdx
	movl	$2, %esi
	xorl	%eax, %eax
	call	__fprintf_chk@PLT
	jmp	.L23
.L9:
	movq	%rsp, %rdi
	movl	$67108864, %esi
	call	cudaMalloc@PLT
	movl	%eax, %edi
	testl	%eax, %eax
	je	.L11
	call	cudaGetErrorString@PLT
	movl	$69, %ecx
	movq	%rax, %r8
.L24:
	movq	stderr(%rip), %rdi
	leaq	.LC1(%rip), %rdx
	movl	$2, %esi
	xorl	%eax, %eax
	call	__fprintf_chk@PLT
.L23:
	movl	$1, %edi
	call	exit@PLT
.L11:
	leaq	8(%rsp), %rdi
	movl	$67108864, %esi
	call	cudaMalloc@PLT
	movl	%eax, %edi
	testl	%eax, %eax
	je	.L12
	call	cudaGetErrorString@PLT
	movl	$70, %ecx
	movq	%rax, %r8
	jmp	.L24
.L12:
	movq	(%rsp), %rdi
	movl	$1, %ecx
	movl	$67108864, %edx
	movq	%rbp, %rsi
	call	cudaMemcpy@PLT
	movl	%eax, %edi
	testl	%eax, %eax
	je	.L13
	call	cudaGetErrorString@PLT
	movl	$72, %ecx
	movq	%rax, %r8
	jmp	.L24
.L13:
	movl	$134217729, %edx
	movl	$8193, %edi
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	salq	$5, %rdx
	salq	$19, %rdi
	movl	$1, %ecx
	movl	$1, %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L14
	movq	8(%rsp), %rdx
	movq	(%rsp), %rdi
	movl	$16777216, %esi
	call	_Z36__device_stub__Z13stencilKernelPhiS_PhiS_
.L14:
	call	cudaGetLastError@PLT
	movl	%eax, %edi
	testl	%eax, %eax
	je	.L15
	call	cudaGetErrorString@PLT
	movl	$75, %ecx
	movq	%rax, %r8
	jmp	.L24
.L15:
	call	cudaDeviceSynchronize@PLT
	movl	%eax, %edi
	testl	%eax, %eax
	je	.L16
	call	cudaGetErrorString@PLT
	movl	$76, %ecx
	movq	%rax, %r8
	jmp	.L24
.L16:
	movq	8(%rsp), %rsi
	movq	%rbx, %rdi
	movl	$2, %ecx
	movl	$67108864, %edx
	call	cudaMemcpy@PLT
	movl	%eax, %edi
	testl	%eax, %eax
	je	.L17
	call	cudaGetErrorString@PLT
	movl	$78, %ecx
	movq	%rax, %r8
	jmp	.L24
.L17:
	movq	(%rsp), %rdi
	call	cudaFree@PLT
	movl	%eax, %edi
	testl	%eax, %eax
	je	.L18
	call	cudaGetErrorString@PLT
	movl	$80, %ecx
	movq	%rax, %r8
	jmp	.L24
.L18:
	movq	8(%rsp), %rdi
	call	cudaFree@PLT
	movl	%eax, %edi
	testl	%eax, %eax
	je	.L19
	call	cudaGetErrorString@PLT
	movl	$81, %ecx
	movq	%rax, %r8
	jmp	.L24
.L19:
	movq	%rbp, %rdi
	call	free@PLT
	movq	%rbx, %rdi
	call	free@PLT
	movq	40(%rsp), %rax
	subq	%fs:40, %rax
	je	.L20
	call	__stack_chk_fail@PLT
.L20:
	addq	$56, %rsp
	.cfi_def_cfa_offset 24
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2029:
	.size	main, .-main
	.section	.rodata.str1.1
.LC2:
	.string	"_Z13stencilKernelPhiS_"
.LC3:
	.string	"weight"
.LC4:
	.string	"denominator"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2057:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC2(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z13stencilKernelPhiS_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC3(%rip), %rdx
	movl	$28, %r9d
	leaq	_ZL6weight(%rip), %rsi
	pushq	$1
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC4(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$4, %r9d
	leaq	_ZL11denominator(%rip), %rsi
	call	__cudaRegisterVar@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2057:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.local	_ZL11denominator
	.comm	_ZL11denominator,4,4
	.local	_ZL6weight
	.comm	_ZL6weight,28,16
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include <stdio.h>
#include <math.h>

#define CUDA_CALL(c) \
    do {                                            \
        hipError_t res = c;                        \
        if (res != hipSuccess) {                   \
            fprintf(stderr, "error at line %d: %s \n", __LINE__, hipGetErrorString(res));    \
            exit(EXIT_FAILURE);                     \
        }                                           \
    } while (0)

// Problem dimension
#define STENCIL_SIZE (16 * 1024 * 1024)
#define RADIUS (3)
#define NUM_CHANNELS (4)

#define BLOCK_SIZE (32)

// Given the pixel index and channel, return the position of the
// element in the 1D array.
static __device__ __host__ int getIndex(int index, int channel)
{
    return index * NUM_CHANNELS + channel;
}

static __constant__ int weight[RADIUS * 2 + 1] = {
    1, 2, 3, 4, 3, 2, 1
};
static __constant__ int denominator = 16;

__global__ void stencilKernel(unsigned char *in,
                              int numPixels,
                              unsigned char *out)
{
    int i = blockIdx.x * blockDim.x + threadIdx.x;
    int radius, channel;
    int outLocal[NUM_CHANNELS] = { 0 };

    if (i < RADIUS) {
        return;
    }

    if (i >= numPixels - RADIUS) {
        return;
    }

    for (radius = -RADIUS; radius <= RADIUS; ++radius) {
        for (channel = 0; channel < NUM_CHANNELS; ++channel) {
            outLocal[channel] += (int)in[getIndex(i + radius, channel)] * weight[RADIUS + radius];
        }
    }

    for (channel = 0; channel < NUM_CHANNELS; ++channel) {
        out[getIndex(i, channel)] = (unsigned char)(outLocal[channel] / denominator);
    }
}

static void stencilGpu(unsigned char *in,
                       int numPixels,
                       unsigned char *out)
{
    unsigned char *inGPU;
    unsigned char *outGPU;
    size_t arraySize;

    arraySize = numPixels * NUM_CHANNELS * sizeof(unsigned char);

    CUDA_CALL(hipMalloc(&inGPU, arraySize));
    CUDA_CALL(hipMalloc(&outGPU, arraySize));

    CUDA_CALL(hipMemcpy(inGPU, in, arraySize, hipMemcpyHostToDevice));

    stencilKernel<<<ceil((float)numPixels / BLOCK_SIZE), BLOCK_SIZE>>>(inGPU, numPixels, outGPU);
    CUDA_CALL(hipGetLastError());
    CUDA_CALL(hipDeviceSynchronize());

    CUDA_CALL(hipMemcpy(out, outGPU, arraySize, hipMemcpyDeviceToHost));

    CUDA_CALL(hipFree(inGPU));
    CUDA_CALL(hipFree(outGPU));
}

int main()
{
    unsigned char *in;
    unsigned char *outGPU;
    size_t arraySize = STENCIL_SIZE * NUM_CHANNELS * sizeof(unsigned char);

    in = (unsigned char *)malloc(arraySize);
    outGPU = (unsigned char *)malloc(arraySize);
    if (in == NULL || outGPU == NULL) {
        fprintf(stderr, "Allocation failed\n");
        exit(EXIT_FAILURE);
    }

    stencilGpu(in, STENCIL_SIZE, outGPU);

    free(in);
    free(outGPU);

    return 0;
}

	.text
	.file	"stencil0_orig.hip"
	.globl	_Z28__device_stub__stencilKernelPhiS_ # -- Begin function _Z28__device_stub__stencilKernelPhiS_
	.type	_Z28__device_stub__stencilKernelPhiS_,@function
_Z28__device_stub__stencilKernelPhiS_:  # @_Z28__device_stub__stencilKernelPhiS_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	12(%rsp), %rcx
	movl	%esi, (%rcx)
	leaq	32(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z13stencilKernelPhiS_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z28__device_stub__stencilKernelPhiS_, .Lfunc_end0-_Z28__device_stub__stencilKernelPhiS_
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%r14
	.cfi_def_cfa_offset 16
	pushq	%rbx
	.cfi_def_cfa_offset 24
	subq	$24, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -24
	.cfi_offset %r14, -16
	movl	$67108864, %edi                 # imm = 0x4000000
	callq	malloc
	movq	%rax, %rbx
	movl	$67108864, %edi                 # imm = 0x4000000
	callq	malloc
	testq	%rbx, %rbx
	je	.LBB1_13
# %bb.1:
	movq	%rax, %r14
	testq	%rax, %rax
	je	.LBB1_13
# %bb.2:
	leaq	16(%rsp), %rdi
	movl	$67108864, %esi                 # imm = 0x4000000
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB1_14
# %bb.3:
	leaq	8(%rsp), %rdi
	movl	$67108864, %esi                 # imm = 0x4000000
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB1_15
# %bb.4:
	movq	16(%rsp), %rdi
	movl	$67108864, %edx                 # imm = 0x4000000
	movq	%rbx, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	testl	%eax, %eax
	jne	.LBB1_16
# %bb.5:
	movabsq	$4294967328, %rdx               # imm = 0x100000020
	leaq	524256(%rdx), %rdi
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_7
# %bb.6:
	movq	16(%rsp), %rdi
	movq	8(%rsp), %rdx
	movl	$16777216, %esi                 # imm = 0x1000000
	callq	_Z28__device_stub__stencilKernelPhiS_
.LBB1_7:
	callq	hipGetLastError
	testl	%eax, %eax
	jne	.LBB1_17
# %bb.8:
	callq	hipDeviceSynchronize
	testl	%eax, %eax
	jne	.LBB1_18
# %bb.9:
	movq	8(%rsp), %rsi
	movl	$67108864, %edx                 # imm = 0x4000000
	movq	%r14, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	testl	%eax, %eax
	jne	.LBB1_19
# %bb.10:
	movq	16(%rsp), %rdi
	callq	hipFree
	testl	%eax, %eax
	jne	.LBB1_20
# %bb.11:
	movq	8(%rsp), %rdi
	callq	hipFree
	testl	%eax, %eax
	jne	.LBB1_21
# %bb.12:                               # %_ZL10stencilGpuPhiS_.exit
	movq	%rbx, %rdi
	callq	free
	movq	%r14, %rdi
	callq	free
	xorl	%eax, %eax
	addq	$24, %rsp
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	retq
.LBB1_13:
	.cfi_def_cfa_offset 48
	movq	stderr(%rip), %rcx
	movl	$.L.str, %edi
	movl	$18, %esi
	movl	$1, %edx
	callq	fwrite@PLT
	jmp	.LBB1_23
.LBB1_14:
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.1, %esi
	movq	%rbx, %rdi
	movl	$71, %edx
	jmp	.LBB1_22
.LBB1_15:
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.1, %esi
	movq	%rbx, %rdi
	movl	$72, %edx
	jmp	.LBB1_22
.LBB1_16:
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.1, %esi
	movq	%rbx, %rdi
	movl	$74, %edx
	jmp	.LBB1_22
.LBB1_17:
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.1, %esi
	movq	%rbx, %rdi
	movl	$77, %edx
	jmp	.LBB1_22
.LBB1_18:
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.1, %esi
	movq	%rbx, %rdi
	movl	$78, %edx
	jmp	.LBB1_22
.LBB1_19:
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.1, %esi
	movq	%rbx, %rdi
	movl	$80, %edx
	jmp	.LBB1_22
.LBB1_20:
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.1, %esi
	movq	%rbx, %rdi
	movl	$82, %edx
	jmp	.LBB1_22
.LBB1_21:
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.1, %esi
	movq	%rbx, %rdi
	movl	$83, %edx
.LBB1_22:
	movq	%rax, %rcx
	xorl	%eax, %eax
	callq	fprintf
.LBB1_23:
	movl	$1, %edi
	callq	exit
.Lfunc_end1:
	.size	main, .Lfunc_end1-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z13stencilKernelPhiS_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z13stencilKernelPhiS_,@object  # @_Z13stencilKernelPhiS_
	.section	.rodata,"a",@progbits
	.globl	_Z13stencilKernelPhiS_
	.p2align	3, 0x0
_Z13stencilKernelPhiS_:
	.quad	_Z28__device_stub__stencilKernelPhiS_
	.size	_Z13stencilKernelPhiS_, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"Allocation failed\n"
	.size	.L.str, 19

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"error at line %d: %s \n"
	.size	.L.str.1, 23

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z13stencilKernelPhiS_"
	.size	.L__unnamed_1, 23

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z28__device_stub__stencilKernelPhiS_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z13stencilKernelPhiS_
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z13stencilKernelPhiS_  ; -- Begin function _Z13stencilKernelPhiS_
	.globl	_Z13stencilKernelPhiS_
	.p2align	8
	.type	_Z13stencilKernelPhiS_,@function
_Z13stencilKernelPhiS_:                 ; @_Z13stencilKernelPhiS_
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x24
	s_load_b32 s3, s[0:1], 0x8
	s_mov_b32 s6, -3
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_add_i32 s3, s3, -3
	v_mad_u64_u32 v[4:5], null, s15, s2, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_lt_i32_e32 vcc_lo, 2, v4
	v_cmp_gt_i32_e64 s2, s3, v4
	s_and_b32 s2, vcc_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_7
; %bb.1:                                ; %.preheader23.preheader
	s_load_b64 s[8:9], s[0:1], 0x0
	s_mov_b32 s12, 0
	v_lshl_add_u32 v5, v4, 2, -12
	s_mov_b32 s13, s12
	s_mov_b32 s14, s12
	s_mov_b32 s15, s12
	v_dual_mov_b32 v0, s12 :: v_dual_mov_b32 v1, s13
	v_dual_mov_b32 v2, s14 :: v_dual_mov_b32 v3, s15
.LBB0_2:                                ; %.preheader23
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_3 Depth 2
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, _ZL6weight@rel32@lo+16
	s_addc_u32 s3, s3, _ZL6weight@rel32@hi+24
	s_ashr_i32 s7, s6, 31
	v_ashrrev_i32_e32 v7, 31, v5
	s_lshl_b64 s[4:5], s[6:7], 2
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v6, vcc_lo, s8, v5
	s_add_u32 s2, s4, s2
	s_addc_u32 s3, s5, s3
	v_add_co_ci_u32_e32 v7, vcc_lo, s9, v7, vcc_lo
	s_load_b32 s5, s[2:3], 0x0
	s_mov_b64 s[10:11], 0
.LBB0_3:                                ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v8, vcc_lo, v6, s10
	v_add_co_ci_u32_e32 v9, vcc_lo, s11, v7, vcc_lo
	s_cmp_eq_u32 s10, 1
	s_cselect_b32 vcc_lo, -1, 0
	global_load_u8 v11, v[8:9], off
	v_cndmask_b32_e32 v8, v0, v1, vcc_lo
	s_cmp_eq_u32 s10, 2
	s_cselect_b32 s2, -1, 0
	s_cmp_eq_u32 s10, 3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v8, v8, v2, s2
	s_cselect_b32 s3, -1, 0
	s_cmp_eq_u32 s10, 0
	s_cselect_b32 s4, -1, 0
	v_cndmask_b32_e64 v8, v8, v3, s3
	s_add_u32 s10, s10, 1
	s_addc_u32 s11, s11, 0
	s_cmp_lg_u32 s10, 4
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_mad_u64_u32 v[9:10], null, s5, v11, v[8:9]
	s_delay_alu instid0(VALU_DEP_1)
	v_cndmask_b32_e64 v3, v3, v9, s3
	v_cndmask_b32_e64 v2, v2, v9, s2
	v_cndmask_b32_e32 v1, v1, v9, vcc_lo
	v_cndmask_b32_e64 v0, v0, v9, s4
	s_cbranch_scc1 .LBB0_3
; %bb.4:                                ;   in Loop: Header=BB0_2 Depth=1
	v_add_nc_u32_e32 v5, 4, v5
	s_add_i32 s6, s6, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s6, 4
	s_cbranch_scc0 .LBB0_2
; %bb.5:                                ; %.preheader
	s_load_b64 s[0:1], s[0:1], 0x10
	v_lshlrev_b32_e32 v4, 2, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v5, 31, v4
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v4, vcc_lo, s0, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
	s_mov_b64 s[0:1], 0
.LBB0_6:                                ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s0, 1
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s0, 2
	v_cndmask_b32_e32 v6, v0, v1, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s0, 3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v6, v6, v2, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	v_cndmask_b32_e32 v6, v6, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v7, 31, v6
	v_lshrrev_b32_e32 v7, 28, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v8, v6, v7
	v_add_co_u32 v6, vcc_lo, v4, s0
	v_add_co_ci_u32_e32 v7, vcc_lo, s1, v5, vcc_lo
	v_lshrrev_b32_e32 v8, 4, v8
	s_add_u32 s0, s0, 1
	s_addc_u32 s1, s1, 0
	s_cmp_lg_u32 s0, 4
	global_store_b8 v[6:7], v8, off
	s_cbranch_scc1 .LBB0_6
.LBB0_7:                                ; %.loopexit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z13stencilKernelPhiS_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 12
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z13stencilKernelPhiS_, .Lfunc_end0-_Z13stencilKernelPhiS_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 512
; NumSgprs: 18
; NumVgprs: 12
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 12
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	_ZL6weight,@object              ; @_ZL6weight
	.section	.rodata,"a",@progbits
	.p2align	4, 0x0
_ZL6weight:
	.long	1                               ; 0x1
	.long	2                               ; 0x2
	.long	3                               ; 0x3
	.long	4                               ; 0x4
	.long	3                               ; 0x3
	.long	2                               ; 0x2
	.long	1                               ; 0x1
	.size	_ZL6weight, 28

	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z13stencilKernelPhiS_
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z13stencilKernelPhiS_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     12
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
