/**************************************************
*******PROGRAM FOR ARRAY REDUCTION IN CUDA*********
***************************************************
* EXTERNAL PROGRAMS INCLUDED:			  *
*						  *
* SUMS UPTO 2^24 INTS BEFORE REACHING BLOCK LIMIT *
* ARRAY MUST CONTAIN POWER OF TWO ELEMENTS	  *
* PROGRAM INCLUDES INTS,FLOATS AND DOUBS          *
*						  *
* Call INTS: cuda_asum_intm(ipt/opt array, N#s)   *
* Call FLTS: cuda_asum_fltm(ipt/opt array, N#s)   *
* Call DOUBS: cuda_asum_doubm(ipt/opt array, N#s) *
*						  *
***************************************************/

// *** INCLUDED LIBRARIES*** //
#include <stdio.h>
#include <stdlib.h>
#include <iostream>
#include <cuda.h>

// ***CUDA ERROR HANDLER*** //
#define CUDA_CALL(x) do { if((x) != cudaSuccess) { \
printf("Error at %s:%d\n",__FILE__,__LINE__);\
return EXIT_FAILURE;}} while(0)

// ********************************************************************* //
// **********************INTEGER ARRAY SUMMATION************************ //
// ********************************************************************* //

// ****************************************** //
// ***INTEGERS DEVICE SIDE KERNEL PROGRAM**** //
// ****************************************** //
template <unsigned int blockSize>
__global__ void cuda_asum_int(int *d_idat, int *d_odat)
{
	extern __shared__ int sdata[];

	//LOAD ELEMENT FROM GLOBAL TO SHARED MEM
	unsigned int tid = threadIdx.x;
	unsigned int i = blockIdx.x * (blockDim.x * 2) + tid;
	
	sdata[tid] = d_idat[i] + d_idat[i + blockDim.x];
	__syncthreads();

	//REDUCTION
	if (blockSize >= 512) 
	{
		if (tid < 256) {sdata[tid] += sdata[tid + 256];} __syncthreads();
	}
        if (blockSize >= 256)
        {
                if (tid < 128) {sdata[tid] += sdata[tid + 128];} __syncthreads();
        }
        if (blockSize >= 128)
        {
                if (tid < 64) {sdata[tid] += sdata[tid + 64];} __syncthreads();
        }
     
	if (tid < 32)
	{
		if (blockSize >= 64) sdata[tid] += sdata[tid + 32];
		if (blockSize >= 32) sdata[tid] += sdata[tid + 16]; 
		if (blockSize >= 16) sdata[tid] += sdata[tid + 8];
		if (blockSize >= 8) sdata[tid] += sdata[tid + 4]; 
		if (blockSize >= 4) sdata[tid] += sdata[tid + 2]; 
		if (blockSize >= 2) sdata[tid] += sdata[tid + 1]; 
	}

	//WRITE RESULT TO GLOB MEM
	if(tid == 0) d_odat[blockIdx.x] = sdata[0];
}

// ****************************************** //
// ***INTS HOST SIDE KERNEL CALLER PROGRAM*** //
// ****************************************** //

//DEVICE ARRAY (d_idat) NEEDS TO BE DEFINED IN PARENT PROGRAM
extern void cuda_asum_intm(int *d_idat, int N_elem) //sqrt(N_elem) must be an int
{

	//THREAD AND BLOCK SIZES
	unsigned int THREAD_SIZE = 512/2;
	unsigned int BLOCK_SIZE = N_elem/512;
	unsigned int FINAL_THREAD;
	
        if (N_elem > 512)
        {
	//SUM THE ARRAY THROUGH MULTIPLE KERNEL CALLS
	while(BLOCK_SIZE > 1)
	{
		//RUN REDUCTIONS
		switch (THREAD_SIZE)
			{
			case 512:
				cuda_asum_int<512><<<BLOCK_SIZE,THREAD_SIZE,512*sizeof(int)>>>(d_idat,d_idat); break;
                        case 256:
                                cuda_asum_int<256><<<BLOCK_SIZE,THREAD_SIZE,256*sizeof(int)>>>(d_idat,d_idat); break;
                        case 128:
                                cuda_asum_int<128><<<BLOCK_SIZE,THREAD_SIZE,128*sizeof(int)>>>(d_idat,d_idat); break;
                        case 64:
                                cuda_asum_int< 64><<<BLOCK_SIZE,THREAD_SIZE,64*sizeof(int)>>>(d_idat,d_idat); break;
                        case 32:
                                cuda_asum_int< 32><<<BLOCK_SIZE,THREAD_SIZE,32*sizeof(int)>>>(d_idat,d_idat); break;
                        case 16:
                                cuda_asum_int< 16><<<BLOCK_SIZE,THREAD_SIZE,16*sizeof(int)>>>(d_idat,d_idat); break;
                        case 8:
                                cuda_asum_int<  8><<<BLOCK_SIZE,THREAD_SIZE,8*sizeof(int)>>>(d_idat,d_idat); break;
                        case 4:
                                cuda_asum_int<  4><<<BLOCK_SIZE,THREAD_SIZE,4*sizeof(int)>>>(d_idat,d_idat); break;
                        case 2:
                                cuda_asum_int<  2><<<BLOCK_SIZE,THREAD_SIZE,2*sizeof(int)>>>(d_idat,d_idat); break;
                        case 1:
                                cuda_asum_int<  1><<<BLOCK_SIZE,THREAD_SIZE,1*sizeof(int)>>>(d_idat,d_idat); break;
			}
		//cuda_asum_int<<<BLOCK_SIZE,THREAD_SIZE,512*sizeof(int)>>>(d_idat,d_idat);
		FINAL_THREAD = BLOCK_SIZE;
		BLOCK_SIZE = BLOCK_SIZE/512;
	}
        } else {
                FINAL_THREAD = (unsigned int)N_elem;
        }

	THREAD_SIZE = FINAL_THREAD/2;
	BLOCK_SIZE = 1;
        //RUN REDUCTIONS
        switch (THREAD_SIZE)
        	{
                case 512:
                	cuda_asum_int<512><<<BLOCK_SIZE,THREAD_SIZE,512*sizeof(int)>>>(d_idat,d_idat); break;
                case 256:
                        cuda_asum_int<256><<<BLOCK_SIZE,THREAD_SIZE,256*sizeof(int)>>>(d_idat,d_idat); break;
                case 128:
                        cuda_asum_int<128><<<BLOCK_SIZE,THREAD_SIZE,128*sizeof(int)>>>(d_idat,d_idat); break;
                case 64:
                        cuda_asum_int< 64><<<BLOCK_SIZE,THREAD_SIZE,64*sizeof(int)>>>(d_idat,d_idat); break;
                case 32:
                        cuda_asum_int< 32><<<BLOCK_SIZE,THREAD_SIZE,32*sizeof(int)>>>(d_idat,d_idat); break;
                case 16:
                        cuda_asum_int< 16><<<BLOCK_SIZE,THREAD_SIZE,16*sizeof(int)>>>(d_idat,d_idat); break;
                case 8:
                        cuda_asum_int<  8><<<BLOCK_SIZE,THREAD_SIZE,8*sizeof(int)>>>(d_idat,d_idat); break;
                case 4:
                        cuda_asum_int<  4><<<BLOCK_SIZE,THREAD_SIZE,4*sizeof(int)>>>(d_idat,d_idat); break;
                case 2:
                        cuda_asum_int<  2><<<BLOCK_SIZE,THREAD_SIZE,2*sizeof(int)>>>(d_idat,d_idat); break;
                case 1:
                        cuda_asum_int<  1><<<BLOCK_SIZE,THREAD_SIZE,1*sizeof(int)>>>(d_idat,d_idat); break;
                }

}

// ********************************************************************* //
// ************************FLOAT ARRAY SUMMATION************************ //
// ********************************************************************* //

// ****************************************** //
// ****FLOATS DEVICE SIDE KERNEL PROGRAM***** //
// ****************************************** //
template <unsigned int blockSizeflt>
__global__ void cuda_asum_flt(float *d_idat, float *d_odat)
{
        extern __shared__ float sdataf[];

        //LOAD ELEMENT FROM GLOBAL TO SHARED MEM
        unsigned int tid = threadIdx.x;
        unsigned int i = blockIdx.x * (blockDim.x * 2) + tid;

        sdataf[tid] = d_idat[i] + d_idat[i + blockDim.x];
        __syncthreads();

        //REDUCTION
        if (blockSizeflt >= 1024)
        {
                if (tid < 512) {sdataf[tid] += sdataf[tid + 512];} __syncthreads();
        }
        if (blockSizeflt >= 512)
        {
                if (tid < 256) {sdataf[tid] += sdataf[tid + 256];} __syncthreads();
        }	
        if (blockSizeflt >= 256)
        {
                if (tid < 128) {sdataf[tid] += sdataf[tid + 128];} __syncthreads();
        }

        if (tid < 64)
        {
		if (blockSizeflt >= 128) sdataf[tid] += sdataf[tid + 64];__syncthreads();
                if (blockSizeflt >= 64) sdataf[tid] += sdataf[tid + 32];__syncthreads();
                if (blockSizeflt >= 32) sdataf[tid] += sdataf[tid + 16];__syncthreads();
                if (blockSizeflt >= 16) sdataf[tid] += sdataf[tid + 8];__syncthreads();
                if (blockSizeflt >= 8) sdataf[tid] += sdataf[tid + 4];__syncthreads();
                if (blockSizeflt >= 4) sdataf[tid] += sdataf[tid + 2];__syncthreads();
		if (blockSizeflt >= 2) sdataf[tid] += sdataf[tid + 1];__syncthreads();
        }
        //WRITE RESULT TO GLOB MEM
        if(tid == 0) d_odat[blockIdx.x] = sdataf[0];
}

// ****************************************** //
// **FLOATS HOST SIDE KERNEL CALLER PROGRAM** //
// ****************************************** //

//DEVICE ARRAY (d_idat) NEEDS TO BE DEFINED IN PARENT PROGRAM
extern void cuda_asum_fltm(float *d_idat, int N_elem,int MAX_THREADS) //sqrt(N_elem) must be an int
{
	
        //THREAD AND BLOCK SIZES
        unsigned int THREAD_SIZE = MAX_THREADS;
        unsigned int BLOCK_SIZE = N_elem/(MAX_THREADS*2);
        unsigned int FINAL_THREAD;

        if (N_elem > THREAD_SIZE)
        {
        	//SUM THE ARRAY THROUGH MULTIPLE KERNEL CALLS
        	while(BLOCK_SIZE > 1)
        	{
        	        //RUN REDUCTIONS
        	        switch (THREAD_SIZE)
        	                {
        	                case 1024:
        	                        cuda_asum_flt<1024><<<BLOCK_SIZE,THREAD_SIZE,1024*sizeof(int)>>>(d_idat,d_idat); break;
				case 512:
        	                        cuda_asum_flt<512><<<BLOCK_SIZE,THREAD_SIZE,512*sizeof(int)>>>(d_idat,d_idat); break;
        	                case 256:
        	                        cuda_asum_flt<256><<<BLOCK_SIZE,THREAD_SIZE,256*sizeof(int)>>>(d_idat,d_idat); break;
        	                case 128:
        	                        cuda_asum_flt<128><<<BLOCK_SIZE,THREAD_SIZE,128*sizeof(int)>>>(d_idat,d_idat); break;
        	                case 64:
        	                        cuda_asum_flt< 64><<<BLOCK_SIZE,THREAD_SIZE,64*sizeof(int)>>>(d_idat,d_idat); break;
        	                case 32:
        	                        cuda_asum_flt< 32><<<BLOCK_SIZE,THREAD_SIZE,32*sizeof(int)>>>(d_idat,d_idat); break;
        	                case 16:
        	                        cuda_asum_flt< 16><<<BLOCK_SIZE,THREAD_SIZE,16*sizeof(int)>>>(d_idat,d_idat); break;
        	                case 8:
        	                        cuda_asum_flt<  8><<<BLOCK_SIZE,THREAD_SIZE,8*sizeof(int)>>>(d_idat,d_idat); break;
        	                case 4:
        	                        cuda_asum_flt<  4><<<BLOCK_SIZE,THREAD_SIZE,4*sizeof(int)>>>(d_idat,d_idat); break;
        	                case 2:
        	                        cuda_asum_flt<  2><<<BLOCK_SIZE,THREAD_SIZE,2*sizeof(int)>>>(d_idat,d_idat); break;
        	                case 1:
        	                        cuda_asum_flt<  1><<<BLOCK_SIZE,THREAD_SIZE,1*sizeof(int)>>>(d_idat,d_idat); break;
        	                }
        	        FINAL_THREAD = BLOCK_SIZE;
        	        BLOCK_SIZE = BLOCK_SIZE/1024;
        	}
	} else {
		FINAL_THREAD = (unsigned int)N_elem/2;
	}
        THREAD_SIZE = FINAL_THREAD/2;
        BLOCK_SIZE = 1;
        //RUN REDUCTIONS
        switch (THREAD_SIZE)
                {
                case 1024:
                        cuda_asum_flt<1024><<<BLOCK_SIZE,THREAD_SIZE,1024*sizeof(int)>>>(d_idat,d_idat); break;
                case 512:
                        cuda_asum_flt<512><<<BLOCK_SIZE,THREAD_SIZE,512*sizeof(int)>>>(d_idat,d_idat); break;
                case 256:
                        cuda_asum_flt<256><<<BLOCK_SIZE,THREAD_SIZE,256*sizeof(int)>>>(d_idat,d_idat); break;
                case 128:
                        cuda_asum_flt<128><<<BLOCK_SIZE,THREAD_SIZE,128*sizeof(int)>>>(d_idat,d_idat); break;
                case 64:
                        cuda_asum_flt< 64><<<BLOCK_SIZE,THREAD_SIZE,64*sizeof(int)>>>(d_idat,d_idat); break;
                case 32:
                        cuda_asum_flt< 32><<<BLOCK_SIZE,THREAD_SIZE,32*sizeof(int)>>>(d_idat,d_idat); break;
                case 16:
                        cuda_asum_flt< 16><<<BLOCK_SIZE,THREAD_SIZE,16*sizeof(int)>>>(d_idat,d_idat); break;
                case 8:
                        cuda_asum_flt< 8><<<BLOCK_SIZE,THREAD_SIZE,8*sizeof(int)>>>(d_idat,d_idat); break;
                case 4:
                        cuda_asum_flt<  4><<<BLOCK_SIZE,THREAD_SIZE,4*sizeof(int)>>>(d_idat,d_idat); break;
                case 2:
                        cuda_asum_flt<  2><<<BLOCK_SIZE,THREAD_SIZE,2*sizeof(int)>>>(d_idat,d_idat); break;
                case 1:
                        cuda_asum_flt<  1><<<BLOCK_SIZE,THREAD_SIZE,1*sizeof(int)>>>(d_idat,d_idat); break;
                }
}

// ********************************************************************* //
// ***********************DOUBLE ARRAY SUMMATION************************ //
// ********************************************************************* //

// ****************************************** //
// ****DOUBLES DEVICE SIDE KERNEL PROGRAM**** //
// ****************************************** //

template <unsigned int blockSizedoub>
__global__ void cuda_asum_doub(double *d_idat, double *d_odat)
{
        extern __shared__ double sdatad[];

        //LOAD ELEMENT FROM GLOBAL TO SHARED MEM
        unsigned int tid = threadIdx.x;
        unsigned int i = blockIdx.x * (blockDim.x * 2) + tid;

        sdatad[tid] = d_idat[i] + d_idat[i + blockDim.x];
        __syncthreads();

        //REDUCTION
        if (blockSizedoub >= 512)
        {
                if (tid < 256) {sdatad[tid] += sdatad[tid + 256];} __syncthreads();
        }
        if (blockSizedoub >= 256)
        {
                if (tid < 128) {sdatad[tid] += sdatad[tid + 128];} __syncthreads();
        }
        if (blockSizedoub >= 128)
        {
                if (tid < 64) {sdatad[tid] += sdatad[tid + 64];} __syncthreads();
        }

        if (tid < 32)
        {
                if (blockSizedoub >= 64) sdatad[tid] += sdatad[tid + 32];
                if (blockSizedoub >= 32) sdatad[tid] += sdatad[tid + 16];
                if (blockSizedoub >= 16) sdatad[tid] += sdatad[tid + 8];
                if (blockSizedoub >= 8) sdatad[tid] += sdatad[tid + 4];
                if (blockSizedoub >= 4) sdatad[tid] += sdatad[tid + 2];
                if (blockSizedoub >= 2) sdatad[tid] += sdatad[tid + 1];
        }

        //WRITE RESULT TO GLOB MEM
        if(tid == 0) d_odat[blockIdx.x] = sdatad[0];
}

// ****************************************** //
// *DOUBLES HOST SIDE KERNEL CALLER PROGRAM** //
// ****************************************** //

//DEVICE ARRAY (d_idat) NEEDS TO BE DEFINED IN PARENT PROGRAM
extern void cuda_asum_doubm(double *d_idat, double N_elem) //sqrt(N_elem) must be an int
{

        //THREAD AND BLOCK SIZES
        unsigned int THREAD_SIZE = 512/2;
        unsigned int BLOCK_SIZE = N_elem/512;
        unsigned int FINAL_THREAD;

        if (N_elem > 512)
        {
        	//SUM THE ARRAY THROUGH MULTIPLE KERNEL CALLS
        	while(BLOCK_SIZE > 1)
        	{
        	        //RUN REDUCTIONS
        	        switch (THREAD_SIZE)
        	                {
        	                case 512:
               		                cuda_asum_doub<512><<<BLOCK_SIZE,THREAD_SIZE,512*sizeof(double)>>>(d_idat,d_idat); break;
                	        case 256:
                	                cuda_asum_doub<256><<<BLOCK_SIZE,THREAD_SIZE,256*sizeof(double)>>>(d_idat,d_idat); break;
                	        case 128:
                	                cuda_asum_doub<128><<<BLOCK_SIZE,THREAD_SIZE,128*sizeof(double)>>>(d_idat,d_idat); break;
                	        case 64:
                	                cuda_asum_doub< 64><<<BLOCK_SIZE,THREAD_SIZE,64*sizeof(double)>>>(d_idat,d_idat); break;
                	        case 32:
                	                cuda_asum_doub< 32><<<BLOCK_SIZE,THREAD_SIZE,32*sizeof(double)>>>(d_idat,d_idat); break;
                	        case 16:
                	                cuda_asum_doub< 16><<<BLOCK_SIZE,THREAD_SIZE,16*sizeof(double)>>>(d_idat,d_idat); break;
                	        case 8:
                	                cuda_asum_doub<  8><<<BLOCK_SIZE,THREAD_SIZE,8*sizeof(double)>>>(d_idat,d_idat); break;
                	        case 4:
                	                cuda_asum_doub<  4><<<BLOCK_SIZE,THREAD_SIZE,4*sizeof(double)>>>(d_idat,d_idat); break;
                	        case 2:
                	                cuda_asum_doub<  2><<<BLOCK_SIZE,THREAD_SIZE,2*sizeof(double)>>>(d_idat,d_idat); break;
                	        case 1:
                	                cuda_asum_doub<  1><<<BLOCK_SIZE,THREAD_SIZE,1*sizeof(double)>>>(d_idat,d_idat); break;
                	        }
                	//cuda_asum_int<<<BLOCK_SIZE,THREAD_SIZE,512*sizeof(int)>>>(d_idat,d_idat);
                	FINAL_THREAD = BLOCK_SIZE;
                	BLOCK_SIZE = BLOCK_SIZE/512;
        	}
        } else {
                FINAL_THREAD = (unsigned int)N_elem;
        }

	// THIS SECTION BEGINS WITH THREADS NEEDED ARE LESS THAN MAXIMUM BLOCK SIZE
        THREAD_SIZE = FINAL_THREAD/2;
        BLOCK_SIZE = 1;
        //RUN REDUCTIONS
        switch (THREAD_SIZE)
                {
                case 512:
                        cuda_asum_doub<512><<<BLOCK_SIZE,THREAD_SIZE,512*sizeof(double)>>>(d_idat,d_idat); break;
                case 256:
                        cuda_asum_doub<256><<<BLOCK_SIZE,THREAD_SIZE,256*sizeof(double)>>>(d_idat,d_idat); break;
                case 128:
                        cuda_asum_doub<128><<<BLOCK_SIZE,THREAD_SIZE,128*sizeof(double)>>>(d_idat,d_idat); break;
                case 64:
                        cuda_asum_doub< 64><<<BLOCK_SIZE,THREAD_SIZE,64*sizeof(double)>>>(d_idat,d_idat); break;
                case 32:
                        cuda_asum_doub< 32><<<BLOCK_SIZE,THREAD_SIZE,32*sizeof(double)>>>(d_idat,d_idat); break;
                case 16:
                        cuda_asum_doub< 16><<<BLOCK_SIZE,THREAD_SIZE,16*sizeof(double)>>>(d_idat,d_idat); break;
                case 8:
                        cuda_asum_doub<  8><<<BLOCK_SIZE,THREAD_SIZE,8*sizeof(double)>>>(d_idat,d_idat); break;
                case 4:
                        cuda_asum_doub<  4><<<BLOCK_SIZE,THREAD_SIZE,4*sizeof(double)>>>(d_idat,d_idat); break;
                case 2:
                        cuda_asum_doub<  2><<<BLOCK_SIZE,THREAD_SIZE,2*sizeof(double)>>>(d_idat,d_idat); break;
                case 1:
                        cuda_asum_doub<  1><<<BLOCK_SIZE,THREAD_SIZE,1*sizeof(double)>>>(d_idat,d_idat); break;
                }

}


	.file	"tmpxft_0027e9be_00000000-6_cuda_reduction.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3646:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3646:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.type	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0, @function
_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0:
.LFB4381:
	.cfi_startproc
	jmp	cudaLaunchKernel@PLT
	.cfi_endproc
.LFE4381:
	.size	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0, .-_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	.type	_ZL44__device_stub__Z14cuda_asum_doubILj1EEvPdS0_PdS_, @function
_ZL44__device_stub__Z14cuda_asum_doubILj1EEvPdS0_PdS_:
.LFB3728:
	.cfi_startproc
	subq	$88, %rsp
	.cfi_def_cfa_offset 96
	movq	%rdi, 8(%rsp)
	leaq	24(%rsp), %rcx
	leaq	16(%rsp), %rdx
	movq	%rsi, (%rsp)
	leaq	32(%rsp), %rdi
	leaq	44(%rsp), %rsi
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 40(%rsp)
	movq	%rax, 56(%rsp)
	movq	%rsp, %rax
	movq	%rax, 64(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 32(%rsp)
	movq	%rax, 44(%rsp)
	movl	$1, 52(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L3
	pushq	24(%rsp)
	.cfi_def_cfa_offset 104
	leaq	_Z14cuda_asum_doubILj1EEvPdS0_(%rip), %rdi
	pushq	24(%rsp)
	.cfi_def_cfa_offset 112
	movq	60(%rsp), %rcx
	movl	68(%rsp), %r8d
	movq	48(%rsp), %rsi
	movl	56(%rsp), %edx
	leaq	72(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 104
	popq	%rdx
	.cfi_def_cfa_offset 96
.L3:
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L5
	call	__stack_chk_fail@PLT
.L5:
	addq	$88, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3728:
	.size	_ZL44__device_stub__Z14cuda_asum_doubILj1EEvPdS0_PdS_, .-_ZL44__device_stub__Z14cuda_asum_doubILj1EEvPdS0_PdS_
	.type	_ZL44__device_stub__Z14cuda_asum_doubILj2EEvPdS0_PdS_, @function
_ZL44__device_stub__Z14cuda_asum_doubILj2EEvPdS0_PdS_:
.LFB3726:
	.cfi_startproc
	subq	$88, %rsp
	.cfi_def_cfa_offset 96
	movq	%rdi, 8(%rsp)
	leaq	24(%rsp), %rcx
	leaq	16(%rsp), %rdx
	movq	%rsi, (%rsp)
	leaq	32(%rsp), %rdi
	leaq	44(%rsp), %rsi
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 40(%rsp)
	movq	%rax, 56(%rsp)
	movq	%rsp, %rax
	movq	%rax, 64(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 32(%rsp)
	movq	%rax, 44(%rsp)
	movl	$1, 52(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L8
	pushq	24(%rsp)
	.cfi_def_cfa_offset 104
	leaq	_Z14cuda_asum_doubILj2EEvPdS0_(%rip), %rdi
	pushq	24(%rsp)
	.cfi_def_cfa_offset 112
	movq	60(%rsp), %rcx
	movl	68(%rsp), %r8d
	movq	48(%rsp), %rsi
	movl	56(%rsp), %edx
	leaq	72(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 104
	popq	%rdx
	.cfi_def_cfa_offset 96
.L8:
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L10
	call	__stack_chk_fail@PLT
.L10:
	addq	$88, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3726:
	.size	_ZL44__device_stub__Z14cuda_asum_doubILj2EEvPdS0_PdS_, .-_ZL44__device_stub__Z14cuda_asum_doubILj2EEvPdS0_PdS_
	.type	_ZL44__device_stub__Z14cuda_asum_doubILj4EEvPdS0_PdS_, @function
_ZL44__device_stub__Z14cuda_asum_doubILj4EEvPdS0_PdS_:
.LFB3724:
	.cfi_startproc
	subq	$88, %rsp
	.cfi_def_cfa_offset 96
	movq	%rdi, 8(%rsp)
	leaq	24(%rsp), %rcx
	leaq	16(%rsp), %rdx
	movq	%rsi, (%rsp)
	leaq	32(%rsp), %rdi
	leaq	44(%rsp), %rsi
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 40(%rsp)
	movq	%rax, 56(%rsp)
	movq	%rsp, %rax
	movq	%rax, 64(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 32(%rsp)
	movq	%rax, 44(%rsp)
	movl	$1, 52(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L12
	pushq	24(%rsp)
	.cfi_def_cfa_offset 104
	leaq	_Z14cuda_asum_doubILj4EEvPdS0_(%rip), %rdi
	pushq	24(%rsp)
	.cfi_def_cfa_offset 112
	movq	60(%rsp), %rcx
	movl	68(%rsp), %r8d
	movq	48(%rsp), %rsi
	movl	56(%rsp), %edx
	leaq	72(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 104
	popq	%rdx
	.cfi_def_cfa_offset 96
.L12:
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L14
	call	__stack_chk_fail@PLT
.L14:
	addq	$88, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3724:
	.size	_ZL44__device_stub__Z14cuda_asum_doubILj4EEvPdS0_PdS_, .-_ZL44__device_stub__Z14cuda_asum_doubILj4EEvPdS0_PdS_
	.type	_ZL44__device_stub__Z14cuda_asum_doubILj8EEvPdS0_PdS_, @function
_ZL44__device_stub__Z14cuda_asum_doubILj8EEvPdS0_PdS_:
.LFB3722:
	.cfi_startproc
	subq	$88, %rsp
	.cfi_def_cfa_offset 96
	movq	%rdi, 8(%rsp)
	leaq	24(%rsp), %rcx
	leaq	16(%rsp), %rdx
	movq	%rsi, (%rsp)
	leaq	32(%rsp), %rdi
	leaq	44(%rsp), %rsi
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 40(%rsp)
	movq	%rax, 56(%rsp)
	movq	%rsp, %rax
	movq	%rax, 64(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 32(%rsp)
	movq	%rax, 44(%rsp)
	movl	$1, 52(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L16
	pushq	24(%rsp)
	.cfi_def_cfa_offset 104
	leaq	_Z14cuda_asum_doubILj8EEvPdS0_(%rip), %rdi
	pushq	24(%rsp)
	.cfi_def_cfa_offset 112
	movq	60(%rsp), %rcx
	movl	68(%rsp), %r8d
	movq	48(%rsp), %rsi
	movl	56(%rsp), %edx
	leaq	72(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 104
	popq	%rdx
	.cfi_def_cfa_offset 96
.L16:
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L18
	call	__stack_chk_fail@PLT
.L18:
	addq	$88, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3722:
	.size	_ZL44__device_stub__Z14cuda_asum_doubILj8EEvPdS0_PdS_, .-_ZL44__device_stub__Z14cuda_asum_doubILj8EEvPdS0_PdS_
	.type	_ZL45__device_stub__Z14cuda_asum_doubILj16EEvPdS0_PdS_, @function
_ZL45__device_stub__Z14cuda_asum_doubILj16EEvPdS0_PdS_:
.LFB3720:
	.cfi_startproc
	subq	$88, %rsp
	.cfi_def_cfa_offset 96
	movq	%rdi, 8(%rsp)
	leaq	24(%rsp), %rcx
	leaq	16(%rsp), %rdx
	movq	%rsi, (%rsp)
	leaq	32(%rsp), %rdi
	leaq	44(%rsp), %rsi
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 40(%rsp)
	movq	%rax, 56(%rsp)
	movq	%rsp, %rax
	movq	%rax, 64(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 32(%rsp)
	movq	%rax, 44(%rsp)
	movl	$1, 52(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L20
	pushq	24(%rsp)
	.cfi_def_cfa_offset 104
	leaq	_Z14cuda_asum_doubILj16EEvPdS0_(%rip), %rdi
	pushq	24(%rsp)
	.cfi_def_cfa_offset 112
	movq	60(%rsp), %rcx
	movl	68(%rsp), %r8d
	movq	48(%rsp), %rsi
	movl	56(%rsp), %edx
	leaq	72(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 104
	popq	%rdx
	.cfi_def_cfa_offset 96
.L20:
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L22
	call	__stack_chk_fail@PLT
.L22:
	addq	$88, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3720:
	.size	_ZL45__device_stub__Z14cuda_asum_doubILj16EEvPdS0_PdS_, .-_ZL45__device_stub__Z14cuda_asum_doubILj16EEvPdS0_PdS_
	.type	_ZL45__device_stub__Z14cuda_asum_doubILj32EEvPdS0_PdS_, @function
_ZL45__device_stub__Z14cuda_asum_doubILj32EEvPdS0_PdS_:
.LFB3718:
	.cfi_startproc
	subq	$88, %rsp
	.cfi_def_cfa_offset 96
	movq	%rdi, 8(%rsp)
	leaq	24(%rsp), %rcx
	leaq	16(%rsp), %rdx
	movq	%rsi, (%rsp)
	leaq	32(%rsp), %rdi
	leaq	44(%rsp), %rsi
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 40(%rsp)
	movq	%rax, 56(%rsp)
	movq	%rsp, %rax
	movq	%rax, 64(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 32(%rsp)
	movq	%rax, 44(%rsp)
	movl	$1, 52(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L24
	pushq	24(%rsp)
	.cfi_def_cfa_offset 104
	leaq	_Z14cuda_asum_doubILj32EEvPdS0_(%rip), %rdi
	pushq	24(%rsp)
	.cfi_def_cfa_offset 112
	movq	60(%rsp), %rcx
	movl	68(%rsp), %r8d
	movq	48(%rsp), %rsi
	movl	56(%rsp), %edx
	leaq	72(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 104
	popq	%rdx
	.cfi_def_cfa_offset 96
.L24:
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L26
	call	__stack_chk_fail@PLT
.L26:
	addq	$88, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3718:
	.size	_ZL45__device_stub__Z14cuda_asum_doubILj32EEvPdS0_PdS_, .-_ZL45__device_stub__Z14cuda_asum_doubILj32EEvPdS0_PdS_
	.type	_ZL45__device_stub__Z14cuda_asum_doubILj64EEvPdS0_PdS_, @function
_ZL45__device_stub__Z14cuda_asum_doubILj64EEvPdS0_PdS_:
.LFB3716:
	.cfi_startproc
	subq	$88, %rsp
	.cfi_def_cfa_offset 96
	movq	%rdi, 8(%rsp)
	leaq	24(%rsp), %rcx
	leaq	16(%rsp), %rdx
	movq	%rsi, (%rsp)
	leaq	32(%rsp), %rdi
	leaq	44(%rsp), %rsi
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 40(%rsp)
	movq	%rax, 56(%rsp)
	movq	%rsp, %rax
	movq	%rax, 64(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 32(%rsp)
	movq	%rax, 44(%rsp)
	movl	$1, 52(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L28
	pushq	24(%rsp)
	.cfi_def_cfa_offset 104
	leaq	_Z14cuda_asum_doubILj64EEvPdS0_(%rip), %rdi
	pushq	24(%rsp)
	.cfi_def_cfa_offset 112
	movq	60(%rsp), %rcx
	movl	68(%rsp), %r8d
	movq	48(%rsp), %rsi
	movl	56(%rsp), %edx
	leaq	72(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 104
	popq	%rdx
	.cfi_def_cfa_offset 96
.L28:
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L30
	call	__stack_chk_fail@PLT
.L30:
	addq	$88, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3716:
	.size	_ZL45__device_stub__Z14cuda_asum_doubILj64EEvPdS0_PdS_, .-_ZL45__device_stub__Z14cuda_asum_doubILj64EEvPdS0_PdS_
	.type	_ZL46__device_stub__Z14cuda_asum_doubILj128EEvPdS0_PdS_, @function
_ZL46__device_stub__Z14cuda_asum_doubILj128EEvPdS0_PdS_:
.LFB3714:
	.cfi_startproc
	subq	$88, %rsp
	.cfi_def_cfa_offset 96
	movq	%rdi, 8(%rsp)
	leaq	24(%rsp), %rcx
	leaq	16(%rsp), %rdx
	movq	%rsi, (%rsp)
	leaq	32(%rsp), %rdi
	leaq	44(%rsp), %rsi
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 40(%rsp)
	movq	%rax, 56(%rsp)
	movq	%rsp, %rax
	movq	%rax, 64(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 32(%rsp)
	movq	%rax, 44(%rsp)
	movl	$1, 52(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L32
	pushq	24(%rsp)
	.cfi_def_cfa_offset 104
	leaq	_Z14cuda_asum_doubILj128EEvPdS0_(%rip), %rdi
	pushq	24(%rsp)
	.cfi_def_cfa_offset 112
	movq	60(%rsp), %rcx
	movl	68(%rsp), %r8d
	movq	48(%rsp), %rsi
	movl	56(%rsp), %edx
	leaq	72(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 104
	popq	%rdx
	.cfi_def_cfa_offset 96
.L32:
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L34
	call	__stack_chk_fail@PLT
.L34:
	addq	$88, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3714:
	.size	_ZL46__device_stub__Z14cuda_asum_doubILj128EEvPdS0_PdS_, .-_ZL46__device_stub__Z14cuda_asum_doubILj128EEvPdS0_PdS_
	.type	_ZL46__device_stub__Z14cuda_asum_doubILj512EEvPdS0_PdS_, @function
_ZL46__device_stub__Z14cuda_asum_doubILj512EEvPdS0_PdS_:
.LFB3710:
	.cfi_startproc
	subq	$88, %rsp
	.cfi_def_cfa_offset 96
	movq	%rdi, 8(%rsp)
	leaq	24(%rsp), %rcx
	leaq	16(%rsp), %rdx
	movq	%rsi, (%rsp)
	leaq	32(%rsp), %rdi
	leaq	44(%rsp), %rsi
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 40(%rsp)
	movq	%rax, 56(%rsp)
	movq	%rsp, %rax
	movq	%rax, 64(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 32(%rsp)
	movq	%rax, 44(%rsp)
	movl	$1, 52(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L36
	pushq	24(%rsp)
	.cfi_def_cfa_offset 104
	leaq	_Z14cuda_asum_doubILj512EEvPdS0_(%rip), %rdi
	pushq	24(%rsp)
	.cfi_def_cfa_offset 112
	movq	60(%rsp), %rcx
	movl	68(%rsp), %r8d
	movq	48(%rsp), %rsi
	movl	56(%rsp), %edx
	leaq	72(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 104
	popq	%rdx
	.cfi_def_cfa_offset 96
.L36:
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L38
	call	__stack_chk_fail@PLT
.L38:
	addq	$88, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3710:
	.size	_ZL46__device_stub__Z14cuda_asum_doubILj512EEvPdS0_PdS_, .-_ZL46__device_stub__Z14cuda_asum_doubILj512EEvPdS0_PdS_
	.type	_ZL43__device_stub__Z13cuda_asum_intILj1EEvPiS0_PiS_, @function
_ZL43__device_stub__Z13cuda_asum_intILj1EEvPiS0_PiS_:
.LFB3686:
	.cfi_startproc
	subq	$88, %rsp
	.cfi_def_cfa_offset 96
	movq	%rdi, 8(%rsp)
	leaq	24(%rsp), %rcx
	leaq	16(%rsp), %rdx
	movq	%rsi, (%rsp)
	leaq	32(%rsp), %rdi
	leaq	44(%rsp), %rsi
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 40(%rsp)
	movq	%rax, 56(%rsp)
	movq	%rsp, %rax
	movq	%rax, 64(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 32(%rsp)
	movq	%rax, 44(%rsp)
	movl	$1, 52(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L40
	pushq	24(%rsp)
	.cfi_def_cfa_offset 104
	leaq	_Z13cuda_asum_intILj1EEvPiS0_(%rip), %rdi
	pushq	24(%rsp)
	.cfi_def_cfa_offset 112
	movq	60(%rsp), %rcx
	movl	68(%rsp), %r8d
	movq	48(%rsp), %rsi
	movl	56(%rsp), %edx
	leaq	72(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 104
	popq	%rdx
	.cfi_def_cfa_offset 96
.L40:
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L42
	call	__stack_chk_fail@PLT
.L42:
	addq	$88, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3686:
	.size	_ZL43__device_stub__Z13cuda_asum_intILj1EEvPiS0_PiS_, .-_ZL43__device_stub__Z13cuda_asum_intILj1EEvPiS0_PiS_
	.type	_ZL43__device_stub__Z13cuda_asum_intILj2EEvPiS0_PiS_, @function
_ZL43__device_stub__Z13cuda_asum_intILj2EEvPiS0_PiS_:
.LFB3684:
	.cfi_startproc
	subq	$88, %rsp
	.cfi_def_cfa_offset 96
	movq	%rdi, 8(%rsp)
	leaq	24(%rsp), %rcx
	leaq	16(%rsp), %rdx
	movq	%rsi, (%rsp)
	leaq	32(%rsp), %rdi
	leaq	44(%rsp), %rsi
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 40(%rsp)
	movq	%rax, 56(%rsp)
	movq	%rsp, %rax
	movq	%rax, 64(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 32(%rsp)
	movq	%rax, 44(%rsp)
	movl	$1, 52(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L44
	pushq	24(%rsp)
	.cfi_def_cfa_offset 104
	leaq	_Z13cuda_asum_intILj2EEvPiS0_(%rip), %rdi
	pushq	24(%rsp)
	.cfi_def_cfa_offset 112
	movq	60(%rsp), %rcx
	movl	68(%rsp), %r8d
	movq	48(%rsp), %rsi
	movl	56(%rsp), %edx
	leaq	72(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 104
	popq	%rdx
	.cfi_def_cfa_offset 96
.L44:
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L46
	call	__stack_chk_fail@PLT
.L46:
	addq	$88, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3684:
	.size	_ZL43__device_stub__Z13cuda_asum_intILj2EEvPiS0_PiS_, .-_ZL43__device_stub__Z13cuda_asum_intILj2EEvPiS0_PiS_
	.type	_ZL43__device_stub__Z13cuda_asum_intILj4EEvPiS0_PiS_, @function
_ZL43__device_stub__Z13cuda_asum_intILj4EEvPiS0_PiS_:
.LFB3682:
	.cfi_startproc
	subq	$88, %rsp
	.cfi_def_cfa_offset 96
	movq	%rdi, 8(%rsp)
	leaq	24(%rsp), %rcx
	leaq	16(%rsp), %rdx
	movq	%rsi, (%rsp)
	leaq	32(%rsp), %rdi
	leaq	44(%rsp), %rsi
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 40(%rsp)
	movq	%rax, 56(%rsp)
	movq	%rsp, %rax
	movq	%rax, 64(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 32(%rsp)
	movq	%rax, 44(%rsp)
	movl	$1, 52(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L48
	pushq	24(%rsp)
	.cfi_def_cfa_offset 104
	leaq	_Z13cuda_asum_intILj4EEvPiS0_(%rip), %rdi
	pushq	24(%rsp)
	.cfi_def_cfa_offset 112
	movq	60(%rsp), %rcx
	movl	68(%rsp), %r8d
	movq	48(%rsp), %rsi
	movl	56(%rsp), %edx
	leaq	72(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 104
	popq	%rdx
	.cfi_def_cfa_offset 96
.L48:
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L50
	call	__stack_chk_fail@PLT
.L50:
	addq	$88, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3682:
	.size	_ZL43__device_stub__Z13cuda_asum_intILj4EEvPiS0_PiS_, .-_ZL43__device_stub__Z13cuda_asum_intILj4EEvPiS0_PiS_
	.type	_ZL43__device_stub__Z13cuda_asum_intILj8EEvPiS0_PiS_, @function
_ZL43__device_stub__Z13cuda_asum_intILj8EEvPiS0_PiS_:
.LFB3680:
	.cfi_startproc
	subq	$88, %rsp
	.cfi_def_cfa_offset 96
	movq	%rdi, 8(%rsp)
	leaq	24(%rsp), %rcx
	leaq	16(%rsp), %rdx
	movq	%rsi, (%rsp)
	leaq	32(%rsp), %rdi
	leaq	44(%rsp), %rsi
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 40(%rsp)
	movq	%rax, 56(%rsp)
	movq	%rsp, %rax
	movq	%rax, 64(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 32(%rsp)
	movq	%rax, 44(%rsp)
	movl	$1, 52(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L52
	pushq	24(%rsp)
	.cfi_def_cfa_offset 104
	leaq	_Z13cuda_asum_intILj8EEvPiS0_(%rip), %rdi
	pushq	24(%rsp)
	.cfi_def_cfa_offset 112
	movq	60(%rsp), %rcx
	movl	68(%rsp), %r8d
	movq	48(%rsp), %rsi
	movl	56(%rsp), %edx
	leaq	72(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 104
	popq	%rdx
	.cfi_def_cfa_offset 96
.L52:
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L54
	call	__stack_chk_fail@PLT
.L54:
	addq	$88, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3680:
	.size	_ZL43__device_stub__Z13cuda_asum_intILj8EEvPiS0_PiS_, .-_ZL43__device_stub__Z13cuda_asum_intILj8EEvPiS0_PiS_
	.type	_ZL44__device_stub__Z13cuda_asum_intILj16EEvPiS0_PiS_, @function
_ZL44__device_stub__Z13cuda_asum_intILj16EEvPiS0_PiS_:
.LFB3678:
	.cfi_startproc
	subq	$88, %rsp
	.cfi_def_cfa_offset 96
	movq	%rdi, 8(%rsp)
	leaq	24(%rsp), %rcx
	leaq	16(%rsp), %rdx
	movq	%rsi, (%rsp)
	leaq	32(%rsp), %rdi
	leaq	44(%rsp), %rsi
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 40(%rsp)
	movq	%rax, 56(%rsp)
	movq	%rsp, %rax
	movq	%rax, 64(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 32(%rsp)
	movq	%rax, 44(%rsp)
	movl	$1, 52(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L56
	pushq	24(%rsp)
	.cfi_def_cfa_offset 104
	leaq	_Z13cuda_asum_intILj16EEvPiS0_(%rip), %rdi
	pushq	24(%rsp)
	.cfi_def_cfa_offset 112
	movq	60(%rsp), %rcx
	movl	68(%rsp), %r8d
	movq	48(%rsp), %rsi
	movl	56(%rsp), %edx
	leaq	72(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 104
	popq	%rdx
	.cfi_def_cfa_offset 96
.L56:
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L58
	call	__stack_chk_fail@PLT
.L58:
	addq	$88, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3678:
	.size	_ZL44__device_stub__Z13cuda_asum_intILj16EEvPiS0_PiS_, .-_ZL44__device_stub__Z13cuda_asum_intILj16EEvPiS0_PiS_
	.type	_ZL44__device_stub__Z13cuda_asum_intILj32EEvPiS0_PiS_, @function
_ZL44__device_stub__Z13cuda_asum_intILj32EEvPiS0_PiS_:
.LFB3676:
	.cfi_startproc
	subq	$88, %rsp
	.cfi_def_cfa_offset 96
	movq	%rdi, 8(%rsp)
	leaq	24(%rsp), %rcx
	leaq	16(%rsp), %rdx
	movq	%rsi, (%rsp)
	leaq	32(%rsp), %rdi
	leaq	44(%rsp), %rsi
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 40(%rsp)
	movq	%rax, 56(%rsp)
	movq	%rsp, %rax
	movq	%rax, 64(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 32(%rsp)
	movq	%rax, 44(%rsp)
	movl	$1, 52(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L60
	pushq	24(%rsp)
	.cfi_def_cfa_offset 104
	leaq	_Z13cuda_asum_intILj32EEvPiS0_(%rip), %rdi
	pushq	24(%rsp)
	.cfi_def_cfa_offset 112
	movq	60(%rsp), %rcx
	movl	68(%rsp), %r8d
	movq	48(%rsp), %rsi
	movl	56(%rsp), %edx
	leaq	72(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 104
	popq	%rdx
	.cfi_def_cfa_offset 96
.L60:
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L62
	call	__stack_chk_fail@PLT
.L62:
	addq	$88, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3676:
	.size	_ZL44__device_stub__Z13cuda_asum_intILj32EEvPiS0_PiS_, .-_ZL44__device_stub__Z13cuda_asum_intILj32EEvPiS0_PiS_
	.type	_ZL44__device_stub__Z13cuda_asum_intILj64EEvPiS0_PiS_, @function
_ZL44__device_stub__Z13cuda_asum_intILj64EEvPiS0_PiS_:
.LFB3674:
	.cfi_startproc
	subq	$88, %rsp
	.cfi_def_cfa_offset 96
	movq	%rdi, 8(%rsp)
	leaq	24(%rsp), %rcx
	leaq	16(%rsp), %rdx
	movq	%rsi, (%rsp)
	leaq	32(%rsp), %rdi
	leaq	44(%rsp), %rsi
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 40(%rsp)
	movq	%rax, 56(%rsp)
	movq	%rsp, %rax
	movq	%rax, 64(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 32(%rsp)
	movq	%rax, 44(%rsp)
	movl	$1, 52(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L64
	pushq	24(%rsp)
	.cfi_def_cfa_offset 104
	leaq	_Z13cuda_asum_intILj64EEvPiS0_(%rip), %rdi
	pushq	24(%rsp)
	.cfi_def_cfa_offset 112
	movq	60(%rsp), %rcx
	movl	68(%rsp), %r8d
	movq	48(%rsp), %rsi
	movl	56(%rsp), %edx
	leaq	72(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 104
	popq	%rdx
	.cfi_def_cfa_offset 96
.L64:
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L66
	call	__stack_chk_fail@PLT
.L66:
	addq	$88, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3674:
	.size	_ZL44__device_stub__Z13cuda_asum_intILj64EEvPiS0_PiS_, .-_ZL44__device_stub__Z13cuda_asum_intILj64EEvPiS0_PiS_
	.type	_ZL45__device_stub__Z13cuda_asum_intILj128EEvPiS0_PiS_, @function
_ZL45__device_stub__Z13cuda_asum_intILj128EEvPiS0_PiS_:
.LFB3672:
	.cfi_startproc
	subq	$88, %rsp
	.cfi_def_cfa_offset 96
	movq	%rdi, 8(%rsp)
	leaq	24(%rsp), %rcx
	leaq	16(%rsp), %rdx
	movq	%rsi, (%rsp)
	leaq	32(%rsp), %rdi
	leaq	44(%rsp), %rsi
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 40(%rsp)
	movq	%rax, 56(%rsp)
	movq	%rsp, %rax
	movq	%rax, 64(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 32(%rsp)
	movq	%rax, 44(%rsp)
	movl	$1, 52(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L68
	pushq	24(%rsp)
	.cfi_def_cfa_offset 104
	leaq	_Z13cuda_asum_intILj128EEvPiS0_(%rip), %rdi
	pushq	24(%rsp)
	.cfi_def_cfa_offset 112
	movq	60(%rsp), %rcx
	movl	68(%rsp), %r8d
	movq	48(%rsp), %rsi
	movl	56(%rsp), %edx
	leaq	72(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 104
	popq	%rdx
	.cfi_def_cfa_offset 96
.L68:
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L70
	call	__stack_chk_fail@PLT
.L70:
	addq	$88, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3672:
	.size	_ZL45__device_stub__Z13cuda_asum_intILj128EEvPiS0_PiS_, .-_ZL45__device_stub__Z13cuda_asum_intILj128EEvPiS0_PiS_
	.type	_ZL45__device_stub__Z13cuda_asum_intILj512EEvPiS0_PiS_, @function
_ZL45__device_stub__Z13cuda_asum_intILj512EEvPiS0_PiS_:
.LFB3668:
	.cfi_startproc
	subq	$88, %rsp
	.cfi_def_cfa_offset 96
	movq	%rdi, 8(%rsp)
	leaq	24(%rsp), %rcx
	leaq	16(%rsp), %rdx
	movq	%rsi, (%rsp)
	leaq	32(%rsp), %rdi
	leaq	44(%rsp), %rsi
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 40(%rsp)
	movq	%rax, 56(%rsp)
	movq	%rsp, %rax
	movq	%rax, 64(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 32(%rsp)
	movq	%rax, 44(%rsp)
	movl	$1, 52(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L72
	pushq	24(%rsp)
	.cfi_def_cfa_offset 104
	leaq	_Z13cuda_asum_intILj512EEvPiS0_(%rip), %rdi
	pushq	24(%rsp)
	.cfi_def_cfa_offset 112
	movq	60(%rsp), %rcx
	movl	68(%rsp), %r8d
	movq	48(%rsp), %rsi
	movl	56(%rsp), %edx
	leaq	72(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 104
	popq	%rdx
	.cfi_def_cfa_offset 96
.L72:
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L74
	call	__stack_chk_fail@PLT
.L74:
	addq	$88, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3668:
	.size	_ZL45__device_stub__Z13cuda_asum_intILj512EEvPiS0_PiS_, .-_ZL45__device_stub__Z13cuda_asum_intILj512EEvPiS0_PiS_
	.type	_Z37__wrapper__device_stub_cuda_asum_doubILj256EEvRPdS1_.isra.0, @function
_Z37__wrapper__device_stub_cuda_asum_doubILj256EEvRPdS1_.isra.0:
.LFB4382:
	.cfi_startproc
	subq	$88, %rsp
	.cfi_def_cfa_offset 96
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	xorl	%eax, %eax
	movq	%rsp, %rax
	movq	%rdi, (%rsp)
	leaq	24(%rsp), %rcx
	movq	%rax, 56(%rsp)
	leaq	8(%rsp), %rax
	leaq	16(%rsp), %rdx
	movq	%rsi, 8(%rsp)
	leaq	32(%rsp), %rdi
	leaq	44(%rsp), %rsi
	movq	%rax, 64(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 32(%rsp)
	movl	$1, 40(%rsp)
	movq	%rax, 44(%rsp)
	movl	$1, 52(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L76
	pushq	24(%rsp)
	.cfi_def_cfa_offset 104
	leaq	_Z14cuda_asum_doubILj256EEvPdS0_(%rip), %rdi
	pushq	24(%rsp)
	.cfi_def_cfa_offset 112
	movq	60(%rsp), %rcx
	movl	68(%rsp), %r8d
	movq	48(%rsp), %rsi
	movl	56(%rsp), %edx
	leaq	72(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 104
	popq	%rdx
	.cfi_def_cfa_offset 96
.L76:
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L78
	call	__stack_chk_fail@PLT
.L78:
	addq	$88, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4382:
	.size	_Z37__wrapper__device_stub_cuda_asum_doubILj256EEvRPdS1_.isra.0, .-_Z37__wrapper__device_stub_cuda_asum_doubILj256EEvRPdS1_.isra.0
	.section	.text._Z14cuda_asum_doubILj256EEvPdS0_,"axG",@progbits,_Z14cuda_asum_doubILj256EEvPdS0_,comdat
	.weak	_Z14cuda_asum_doubILj256EEvPdS0_
	.type	_Z14cuda_asum_doubILj256EEvPdS0_, @function
_Z14cuda_asum_doubILj256EEvPdS0_:
.LFB4053:
	.cfi_startproc
	endbr64
	jmp	_Z37__wrapper__device_stub_cuda_asum_doubILj256EEvRPdS1_.isra.0
	.cfi_endproc
.LFE4053:
	.size	_Z14cuda_asum_doubILj256EEvPdS0_, .-_Z14cuda_asum_doubILj256EEvPdS0_
	.text
	.type	_Z36__wrapper__device_stub_cuda_asum_fltILj1EEvRPfS1_.isra.0, @function
_Z36__wrapper__device_stub_cuda_asum_fltILj1EEvRPfS1_.isra.0:
.LFB4383:
	.cfi_startproc
	subq	$88, %rsp
	.cfi_def_cfa_offset 96
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	xorl	%eax, %eax
	movq	%rsp, %rax
	movq	%rdi, (%rsp)
	leaq	24(%rsp), %rcx
	movq	%rax, 56(%rsp)
	leaq	8(%rsp), %rax
	leaq	16(%rsp), %rdx
	movq	%rsi, 8(%rsp)
	leaq	32(%rsp), %rdi
	leaq	44(%rsp), %rsi
	movq	%rax, 64(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 32(%rsp)
	movl	$1, 40(%rsp)
	movq	%rax, 44(%rsp)
	movl	$1, 52(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L81
	pushq	24(%rsp)
	.cfi_def_cfa_offset 104
	leaq	_Z13cuda_asum_fltILj1EEvPfS0_(%rip), %rdi
	pushq	24(%rsp)
	.cfi_def_cfa_offset 112
	movq	60(%rsp), %rcx
	movl	68(%rsp), %r8d
	movq	48(%rsp), %rsi
	movl	56(%rsp), %edx
	leaq	72(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 104
	popq	%rdx
	.cfi_def_cfa_offset 96
.L81:
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L83
	call	__stack_chk_fail@PLT
.L83:
	addq	$88, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4383:
	.size	_Z36__wrapper__device_stub_cuda_asum_fltILj1EEvRPfS1_.isra.0, .-_Z36__wrapper__device_stub_cuda_asum_fltILj1EEvRPfS1_.isra.0
	.section	.text._Z13cuda_asum_fltILj1EEvPfS0_,"axG",@progbits,_Z13cuda_asum_fltILj1EEvPfS0_,comdat
	.weak	_Z13cuda_asum_fltILj1EEvPfS0_
	.type	_Z13cuda_asum_fltILj1EEvPfS0_, @function
_Z13cuda_asum_fltILj1EEvPfS0_:
.LFB4051:
	.cfi_startproc
	endbr64
	jmp	_Z36__wrapper__device_stub_cuda_asum_fltILj1EEvRPfS1_.isra.0
	.cfi_endproc
.LFE4051:
	.size	_Z13cuda_asum_fltILj1EEvPfS0_, .-_Z13cuda_asum_fltILj1EEvPfS0_
	.text
	.type	_Z36__wrapper__device_stub_cuda_asum_fltILj2EEvRPfS1_.isra.0, @function
_Z36__wrapper__device_stub_cuda_asum_fltILj2EEvRPfS1_.isra.0:
.LFB4384:
	.cfi_startproc
	subq	$88, %rsp
	.cfi_def_cfa_offset 96
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	xorl	%eax, %eax
	movq	%rsp, %rax
	movq	%rdi, (%rsp)
	leaq	24(%rsp), %rcx
	movq	%rax, 56(%rsp)
	leaq	8(%rsp), %rax
	leaq	16(%rsp), %rdx
	movq	%rsi, 8(%rsp)
	leaq	32(%rsp), %rdi
	leaq	44(%rsp), %rsi
	movq	%rax, 64(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 32(%rsp)
	movl	$1, 40(%rsp)
	movq	%rax, 44(%rsp)
	movl	$1, 52(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L86
	pushq	24(%rsp)
	.cfi_def_cfa_offset 104
	leaq	_Z13cuda_asum_fltILj2EEvPfS0_(%rip), %rdi
	pushq	24(%rsp)
	.cfi_def_cfa_offset 112
	movq	60(%rsp), %rcx
	movl	68(%rsp), %r8d
	movq	48(%rsp), %rsi
	movl	56(%rsp), %edx
	leaq	72(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 104
	popq	%rdx
	.cfi_def_cfa_offset 96
.L86:
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L88
	call	__stack_chk_fail@PLT
.L88:
	addq	$88, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4384:
	.size	_Z36__wrapper__device_stub_cuda_asum_fltILj2EEvRPfS1_.isra.0, .-_Z36__wrapper__device_stub_cuda_asum_fltILj2EEvRPfS1_.isra.0
	.section	.text._Z13cuda_asum_fltILj2EEvPfS0_,"axG",@progbits,_Z13cuda_asum_fltILj2EEvPfS0_,comdat
	.weak	_Z13cuda_asum_fltILj2EEvPfS0_
	.type	_Z13cuda_asum_fltILj2EEvPfS0_, @function
_Z13cuda_asum_fltILj2EEvPfS0_:
.LFB4050:
	.cfi_startproc
	endbr64
	jmp	_Z36__wrapper__device_stub_cuda_asum_fltILj2EEvRPfS1_.isra.0
	.cfi_endproc
.LFE4050:
	.size	_Z13cuda_asum_fltILj2EEvPfS0_, .-_Z13cuda_asum_fltILj2EEvPfS0_
	.text
	.type	_Z36__wrapper__device_stub_cuda_asum_fltILj4EEvRPfS1_.isra.0, @function
_Z36__wrapper__device_stub_cuda_asum_fltILj4EEvRPfS1_.isra.0:
.LFB4385:
	.cfi_startproc
	subq	$88, %rsp
	.cfi_def_cfa_offset 96
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	xorl	%eax, %eax
	movq	%rsp, %rax
	movq	%rdi, (%rsp)
	leaq	24(%rsp), %rcx
	movq	%rax, 56(%rsp)
	leaq	8(%rsp), %rax
	leaq	16(%rsp), %rdx
	movq	%rsi, 8(%rsp)
	leaq	32(%rsp), %rdi
	leaq	44(%rsp), %rsi
	movq	%rax, 64(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 32(%rsp)
	movl	$1, 40(%rsp)
	movq	%rax, 44(%rsp)
	movl	$1, 52(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L91
	pushq	24(%rsp)
	.cfi_def_cfa_offset 104
	leaq	_Z13cuda_asum_fltILj4EEvPfS0_(%rip), %rdi
	pushq	24(%rsp)
	.cfi_def_cfa_offset 112
	movq	60(%rsp), %rcx
	movl	68(%rsp), %r8d
	movq	48(%rsp), %rsi
	movl	56(%rsp), %edx
	leaq	72(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 104
	popq	%rdx
	.cfi_def_cfa_offset 96
.L91:
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L93
	call	__stack_chk_fail@PLT
.L93:
	addq	$88, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4385:
	.size	_Z36__wrapper__device_stub_cuda_asum_fltILj4EEvRPfS1_.isra.0, .-_Z36__wrapper__device_stub_cuda_asum_fltILj4EEvRPfS1_.isra.0
	.section	.text._Z13cuda_asum_fltILj4EEvPfS0_,"axG",@progbits,_Z13cuda_asum_fltILj4EEvPfS0_,comdat
	.weak	_Z13cuda_asum_fltILj4EEvPfS0_
	.type	_Z13cuda_asum_fltILj4EEvPfS0_, @function
_Z13cuda_asum_fltILj4EEvPfS0_:
.LFB4049:
	.cfi_startproc
	endbr64
	jmp	_Z36__wrapper__device_stub_cuda_asum_fltILj4EEvRPfS1_.isra.0
	.cfi_endproc
.LFE4049:
	.size	_Z13cuda_asum_fltILj4EEvPfS0_, .-_Z13cuda_asum_fltILj4EEvPfS0_
	.text
	.type	_Z36__wrapper__device_stub_cuda_asum_fltILj8EEvRPfS1_.isra.0, @function
_Z36__wrapper__device_stub_cuda_asum_fltILj8EEvRPfS1_.isra.0:
.LFB4386:
	.cfi_startproc
	subq	$88, %rsp
	.cfi_def_cfa_offset 96
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	xorl	%eax, %eax
	movq	%rsp, %rax
	movq	%rdi, (%rsp)
	leaq	24(%rsp), %rcx
	movq	%rax, 56(%rsp)
	leaq	8(%rsp), %rax
	leaq	16(%rsp), %rdx
	movq	%rsi, 8(%rsp)
	leaq	32(%rsp), %rdi
	leaq	44(%rsp), %rsi
	movq	%rax, 64(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 32(%rsp)
	movl	$1, 40(%rsp)
	movq	%rax, 44(%rsp)
	movl	$1, 52(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L96
	pushq	24(%rsp)
	.cfi_def_cfa_offset 104
	leaq	_Z13cuda_asum_fltILj8EEvPfS0_(%rip), %rdi
	pushq	24(%rsp)
	.cfi_def_cfa_offset 112
	movq	60(%rsp), %rcx
	movl	68(%rsp), %r8d
	movq	48(%rsp), %rsi
	movl	56(%rsp), %edx
	leaq	72(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 104
	popq	%rdx
	.cfi_def_cfa_offset 96
.L96:
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L98
	call	__stack_chk_fail@PLT
.L98:
	addq	$88, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4386:
	.size	_Z36__wrapper__device_stub_cuda_asum_fltILj8EEvRPfS1_.isra.0, .-_Z36__wrapper__device_stub_cuda_asum_fltILj8EEvRPfS1_.isra.0
	.section	.text._Z13cuda_asum_fltILj8EEvPfS0_,"axG",@progbits,_Z13cuda_asum_fltILj8EEvPfS0_,comdat
	.weak	_Z13cuda_asum_fltILj8EEvPfS0_
	.type	_Z13cuda_asum_fltILj8EEvPfS0_, @function
_Z13cuda_asum_fltILj8EEvPfS0_:
.LFB4048:
	.cfi_startproc
	endbr64
	jmp	_Z36__wrapper__device_stub_cuda_asum_fltILj8EEvRPfS1_.isra.0
	.cfi_endproc
.LFE4048:
	.size	_Z13cuda_asum_fltILj8EEvPfS0_, .-_Z13cuda_asum_fltILj8EEvPfS0_
	.text
	.type	_Z36__wrapper__device_stub_cuda_asum_fltILj16EEvRPfS1_.isra.0, @function
_Z36__wrapper__device_stub_cuda_asum_fltILj16EEvRPfS1_.isra.0:
.LFB4387:
	.cfi_startproc
	subq	$88, %rsp
	.cfi_def_cfa_offset 96
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	xorl	%eax, %eax
	movq	%rsp, %rax
	movq	%rdi, (%rsp)
	leaq	24(%rsp), %rcx
	movq	%rax, 56(%rsp)
	leaq	8(%rsp), %rax
	leaq	16(%rsp), %rdx
	movq	%rsi, 8(%rsp)
	leaq	32(%rsp), %rdi
	leaq	44(%rsp), %rsi
	movq	%rax, 64(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 32(%rsp)
	movl	$1, 40(%rsp)
	movq	%rax, 44(%rsp)
	movl	$1, 52(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L101
	pushq	24(%rsp)
	.cfi_def_cfa_offset 104
	leaq	_Z13cuda_asum_fltILj16EEvPfS0_(%rip), %rdi
	pushq	24(%rsp)
	.cfi_def_cfa_offset 112
	movq	60(%rsp), %rcx
	movl	68(%rsp), %r8d
	movq	48(%rsp), %rsi
	movl	56(%rsp), %edx
	leaq	72(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 104
	popq	%rdx
	.cfi_def_cfa_offset 96
.L101:
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L103
	call	__stack_chk_fail@PLT
.L103:
	addq	$88, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4387:
	.size	_Z36__wrapper__device_stub_cuda_asum_fltILj16EEvRPfS1_.isra.0, .-_Z36__wrapper__device_stub_cuda_asum_fltILj16EEvRPfS1_.isra.0
	.section	.text._Z13cuda_asum_fltILj16EEvPfS0_,"axG",@progbits,_Z13cuda_asum_fltILj16EEvPfS0_,comdat
	.weak	_Z13cuda_asum_fltILj16EEvPfS0_
	.type	_Z13cuda_asum_fltILj16EEvPfS0_, @function
_Z13cuda_asum_fltILj16EEvPfS0_:
.LFB4047:
	.cfi_startproc
	endbr64
	jmp	_Z36__wrapper__device_stub_cuda_asum_fltILj16EEvRPfS1_.isra.0
	.cfi_endproc
.LFE4047:
	.size	_Z13cuda_asum_fltILj16EEvPfS0_, .-_Z13cuda_asum_fltILj16EEvPfS0_
	.text
	.type	_Z36__wrapper__device_stub_cuda_asum_fltILj32EEvRPfS1_.isra.0, @function
_Z36__wrapper__device_stub_cuda_asum_fltILj32EEvRPfS1_.isra.0:
.LFB4388:
	.cfi_startproc
	subq	$88, %rsp
	.cfi_def_cfa_offset 96
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	xorl	%eax, %eax
	movq	%rsp, %rax
	movq	%rdi, (%rsp)
	leaq	24(%rsp), %rcx
	movq	%rax, 56(%rsp)
	leaq	8(%rsp), %rax
	leaq	16(%rsp), %rdx
	movq	%rsi, 8(%rsp)
	leaq	32(%rsp), %rdi
	leaq	44(%rsp), %rsi
	movq	%rax, 64(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 32(%rsp)
	movl	$1, 40(%rsp)
	movq	%rax, 44(%rsp)
	movl	$1, 52(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L106
	pushq	24(%rsp)
	.cfi_def_cfa_offset 104
	leaq	_Z13cuda_asum_fltILj32EEvPfS0_(%rip), %rdi
	pushq	24(%rsp)
	.cfi_def_cfa_offset 112
	movq	60(%rsp), %rcx
	movl	68(%rsp), %r8d
	movq	48(%rsp), %rsi
	movl	56(%rsp), %edx
	leaq	72(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 104
	popq	%rdx
	.cfi_def_cfa_offset 96
.L106:
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L108
	call	__stack_chk_fail@PLT
.L108:
	addq	$88, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4388:
	.size	_Z36__wrapper__device_stub_cuda_asum_fltILj32EEvRPfS1_.isra.0, .-_Z36__wrapper__device_stub_cuda_asum_fltILj32EEvRPfS1_.isra.0
	.section	.text._Z13cuda_asum_fltILj32EEvPfS0_,"axG",@progbits,_Z13cuda_asum_fltILj32EEvPfS0_,comdat
	.weak	_Z13cuda_asum_fltILj32EEvPfS0_
	.type	_Z13cuda_asum_fltILj32EEvPfS0_, @function
_Z13cuda_asum_fltILj32EEvPfS0_:
.LFB4046:
	.cfi_startproc
	endbr64
	jmp	_Z36__wrapper__device_stub_cuda_asum_fltILj32EEvRPfS1_.isra.0
	.cfi_endproc
.LFE4046:
	.size	_Z13cuda_asum_fltILj32EEvPfS0_, .-_Z13cuda_asum_fltILj32EEvPfS0_
	.text
	.type	_Z36__wrapper__device_stub_cuda_asum_fltILj64EEvRPfS1_.isra.0, @function
_Z36__wrapper__device_stub_cuda_asum_fltILj64EEvRPfS1_.isra.0:
.LFB4389:
	.cfi_startproc
	subq	$88, %rsp
	.cfi_def_cfa_offset 96
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	xorl	%eax, %eax
	movq	%rsp, %rax
	movq	%rdi, (%rsp)
	leaq	24(%rsp), %rcx
	movq	%rax, 56(%rsp)
	leaq	8(%rsp), %rax
	leaq	16(%rsp), %rdx
	movq	%rsi, 8(%rsp)
	leaq	32(%rsp), %rdi
	leaq	44(%rsp), %rsi
	movq	%rax, 64(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 32(%rsp)
	movl	$1, 40(%rsp)
	movq	%rax, 44(%rsp)
	movl	$1, 52(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L111
	pushq	24(%rsp)
	.cfi_def_cfa_offset 104
	leaq	_Z13cuda_asum_fltILj64EEvPfS0_(%rip), %rdi
	pushq	24(%rsp)
	.cfi_def_cfa_offset 112
	movq	60(%rsp), %rcx
	movl	68(%rsp), %r8d
	movq	48(%rsp), %rsi
	movl	56(%rsp), %edx
	leaq	72(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 104
	popq	%rdx
	.cfi_def_cfa_offset 96
.L111:
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L113
	call	__stack_chk_fail@PLT
.L113:
	addq	$88, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4389:
	.size	_Z36__wrapper__device_stub_cuda_asum_fltILj64EEvRPfS1_.isra.0, .-_Z36__wrapper__device_stub_cuda_asum_fltILj64EEvRPfS1_.isra.0
	.section	.text._Z13cuda_asum_fltILj64EEvPfS0_,"axG",@progbits,_Z13cuda_asum_fltILj64EEvPfS0_,comdat
	.weak	_Z13cuda_asum_fltILj64EEvPfS0_
	.type	_Z13cuda_asum_fltILj64EEvPfS0_, @function
_Z13cuda_asum_fltILj64EEvPfS0_:
.LFB4045:
	.cfi_startproc
	endbr64
	jmp	_Z36__wrapper__device_stub_cuda_asum_fltILj64EEvRPfS1_.isra.0
	.cfi_endproc
.LFE4045:
	.size	_Z13cuda_asum_fltILj64EEvPfS0_, .-_Z13cuda_asum_fltILj64EEvPfS0_
	.text
	.type	_Z36__wrapper__device_stub_cuda_asum_fltILj128EEvRPfS1_.isra.0, @function
_Z36__wrapper__device_stub_cuda_asum_fltILj128EEvRPfS1_.isra.0:
.LFB4390:
	.cfi_startproc
	subq	$88, %rsp
	.cfi_def_cfa_offset 96
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	xorl	%eax, %eax
	movq	%rsp, %rax
	movq	%rdi, (%rsp)
	leaq	24(%rsp), %rcx
	movq	%rax, 56(%rsp)
	leaq	8(%rsp), %rax
	leaq	16(%rsp), %rdx
	movq	%rsi, 8(%rsp)
	leaq	32(%rsp), %rdi
	leaq	44(%rsp), %rsi
	movq	%rax, 64(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 32(%rsp)
	movl	$1, 40(%rsp)
	movq	%rax, 44(%rsp)
	movl	$1, 52(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L116
	pushq	24(%rsp)
	.cfi_def_cfa_offset 104
	leaq	_Z13cuda_asum_fltILj128EEvPfS0_(%rip), %rdi
	pushq	24(%rsp)
	.cfi_def_cfa_offset 112
	movq	60(%rsp), %rcx
	movl	68(%rsp), %r8d
	movq	48(%rsp), %rsi
	movl	56(%rsp), %edx
	leaq	72(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 104
	popq	%rdx
	.cfi_def_cfa_offset 96
.L116:
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L118
	call	__stack_chk_fail@PLT
.L118:
	addq	$88, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4390:
	.size	_Z36__wrapper__device_stub_cuda_asum_fltILj128EEvRPfS1_.isra.0, .-_Z36__wrapper__device_stub_cuda_asum_fltILj128EEvRPfS1_.isra.0
	.section	.text._Z13cuda_asum_fltILj128EEvPfS0_,"axG",@progbits,_Z13cuda_asum_fltILj128EEvPfS0_,comdat
	.weak	_Z13cuda_asum_fltILj128EEvPfS0_
	.type	_Z13cuda_asum_fltILj128EEvPfS0_, @function
_Z13cuda_asum_fltILj128EEvPfS0_:
.LFB4044:
	.cfi_startproc
	endbr64
	jmp	_Z36__wrapper__device_stub_cuda_asum_fltILj128EEvRPfS1_.isra.0
	.cfi_endproc
.LFE4044:
	.size	_Z13cuda_asum_fltILj128EEvPfS0_, .-_Z13cuda_asum_fltILj128EEvPfS0_
	.text
	.type	_Z36__wrapper__device_stub_cuda_asum_fltILj256EEvRPfS1_.isra.0, @function
_Z36__wrapper__device_stub_cuda_asum_fltILj256EEvRPfS1_.isra.0:
.LFB4391:
	.cfi_startproc
	subq	$88, %rsp
	.cfi_def_cfa_offset 96
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	xorl	%eax, %eax
	movq	%rsp, %rax
	movq	%rdi, (%rsp)
	leaq	24(%rsp), %rcx
	movq	%rax, 56(%rsp)
	leaq	8(%rsp), %rax
	leaq	16(%rsp), %rdx
	movq	%rsi, 8(%rsp)
	leaq	32(%rsp), %rdi
	leaq	44(%rsp), %rsi
	movq	%rax, 64(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 32(%rsp)
	movl	$1, 40(%rsp)
	movq	%rax, 44(%rsp)
	movl	$1, 52(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L121
	pushq	24(%rsp)
	.cfi_def_cfa_offset 104
	leaq	_Z13cuda_asum_fltILj256EEvPfS0_(%rip), %rdi
	pushq	24(%rsp)
	.cfi_def_cfa_offset 112
	movq	60(%rsp), %rcx
	movl	68(%rsp), %r8d
	movq	48(%rsp), %rsi
	movl	56(%rsp), %edx
	leaq	72(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 104
	popq	%rdx
	.cfi_def_cfa_offset 96
.L121:
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L123
	call	__stack_chk_fail@PLT
.L123:
	addq	$88, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4391:
	.size	_Z36__wrapper__device_stub_cuda_asum_fltILj256EEvRPfS1_.isra.0, .-_Z36__wrapper__device_stub_cuda_asum_fltILj256EEvRPfS1_.isra.0
	.section	.text._Z13cuda_asum_fltILj256EEvPfS0_,"axG",@progbits,_Z13cuda_asum_fltILj256EEvPfS0_,comdat
	.weak	_Z13cuda_asum_fltILj256EEvPfS0_
	.type	_Z13cuda_asum_fltILj256EEvPfS0_, @function
_Z13cuda_asum_fltILj256EEvPfS0_:
.LFB4043:
	.cfi_startproc
	endbr64
	jmp	_Z36__wrapper__device_stub_cuda_asum_fltILj256EEvRPfS1_.isra.0
	.cfi_endproc
.LFE4043:
	.size	_Z13cuda_asum_fltILj256EEvPfS0_, .-_Z13cuda_asum_fltILj256EEvPfS0_
	.text
	.type	_Z36__wrapper__device_stub_cuda_asum_fltILj512EEvRPfS1_.isra.0, @function
_Z36__wrapper__device_stub_cuda_asum_fltILj512EEvRPfS1_.isra.0:
.LFB4392:
	.cfi_startproc
	subq	$88, %rsp
	.cfi_def_cfa_offset 96
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	xorl	%eax, %eax
	movq	%rsp, %rax
	movq	%rdi, (%rsp)
	leaq	24(%rsp), %rcx
	movq	%rax, 56(%rsp)
	leaq	8(%rsp), %rax
	leaq	16(%rsp), %rdx
	movq	%rsi, 8(%rsp)
	leaq	32(%rsp), %rdi
	leaq	44(%rsp), %rsi
	movq	%rax, 64(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 32(%rsp)
	movl	$1, 40(%rsp)
	movq	%rax, 44(%rsp)
	movl	$1, 52(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L126
	pushq	24(%rsp)
	.cfi_def_cfa_offset 104
	leaq	_Z13cuda_asum_fltILj512EEvPfS0_(%rip), %rdi
	pushq	24(%rsp)
	.cfi_def_cfa_offset 112
	movq	60(%rsp), %rcx
	movl	68(%rsp), %r8d
	movq	48(%rsp), %rsi
	movl	56(%rsp), %edx
	leaq	72(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 104
	popq	%rdx
	.cfi_def_cfa_offset 96
.L126:
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L128
	call	__stack_chk_fail@PLT
.L128:
	addq	$88, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4392:
	.size	_Z36__wrapper__device_stub_cuda_asum_fltILj512EEvRPfS1_.isra.0, .-_Z36__wrapper__device_stub_cuda_asum_fltILj512EEvRPfS1_.isra.0
	.section	.text._Z13cuda_asum_fltILj512EEvPfS0_,"axG",@progbits,_Z13cuda_asum_fltILj512EEvPfS0_,comdat
	.weak	_Z13cuda_asum_fltILj512EEvPfS0_
	.type	_Z13cuda_asum_fltILj512EEvPfS0_, @function
_Z13cuda_asum_fltILj512EEvPfS0_:
.LFB4042:
	.cfi_startproc
	endbr64
	jmp	_Z36__wrapper__device_stub_cuda_asum_fltILj512EEvRPfS1_.isra.0
	.cfi_endproc
.LFE4042:
	.size	_Z13cuda_asum_fltILj512EEvPfS0_, .-_Z13cuda_asum_fltILj512EEvPfS0_
	.text
	.type	_Z36__wrapper__device_stub_cuda_asum_fltILj1024EEvRPfS1_.isra.0, @function
_Z36__wrapper__device_stub_cuda_asum_fltILj1024EEvRPfS1_.isra.0:
.LFB4393:
	.cfi_startproc
	subq	$88, %rsp
	.cfi_def_cfa_offset 96
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	xorl	%eax, %eax
	movq	%rsp, %rax
	movq	%rdi, (%rsp)
	leaq	24(%rsp), %rcx
	movq	%rax, 56(%rsp)
	leaq	8(%rsp), %rax
	leaq	16(%rsp), %rdx
	movq	%rsi, 8(%rsp)
	leaq	32(%rsp), %rdi
	leaq	44(%rsp), %rsi
	movq	%rax, 64(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 32(%rsp)
	movl	$1, 40(%rsp)
	movq	%rax, 44(%rsp)
	movl	$1, 52(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L131
	pushq	24(%rsp)
	.cfi_def_cfa_offset 104
	leaq	_Z13cuda_asum_fltILj1024EEvPfS0_(%rip), %rdi
	pushq	24(%rsp)
	.cfi_def_cfa_offset 112
	movq	60(%rsp), %rcx
	movl	68(%rsp), %r8d
	movq	48(%rsp), %rsi
	movl	56(%rsp), %edx
	leaq	72(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 104
	popq	%rdx
	.cfi_def_cfa_offset 96
.L131:
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L133
	call	__stack_chk_fail@PLT
.L133:
	addq	$88, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4393:
	.size	_Z36__wrapper__device_stub_cuda_asum_fltILj1024EEvRPfS1_.isra.0, .-_Z36__wrapper__device_stub_cuda_asum_fltILj1024EEvRPfS1_.isra.0
	.section	.text._Z13cuda_asum_fltILj1024EEvPfS0_,"axG",@progbits,_Z13cuda_asum_fltILj1024EEvPfS0_,comdat
	.weak	_Z13cuda_asum_fltILj1024EEvPfS0_
	.type	_Z13cuda_asum_fltILj1024EEvPfS0_, @function
_Z13cuda_asum_fltILj1024EEvPfS0_:
.LFB4041:
	.cfi_startproc
	endbr64
	jmp	_Z36__wrapper__device_stub_cuda_asum_fltILj1024EEvRPfS1_.isra.0
	.cfi_endproc
.LFE4041:
	.size	_Z13cuda_asum_fltILj1024EEvPfS0_, .-_Z13cuda_asum_fltILj1024EEvPfS0_
	.text
	.type	_Z36__wrapper__device_stub_cuda_asum_intILj256EEvRPiS1_.isra.0, @function
_Z36__wrapper__device_stub_cuda_asum_intILj256EEvRPiS1_.isra.0:
.LFB4394:
	.cfi_startproc
	subq	$88, %rsp
	.cfi_def_cfa_offset 96
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	xorl	%eax, %eax
	movq	%rsp, %rax
	movq	%rdi, (%rsp)
	leaq	24(%rsp), %rcx
	movq	%rax, 56(%rsp)
	leaq	8(%rsp), %rax
	leaq	16(%rsp), %rdx
	movq	%rsi, 8(%rsp)
	leaq	32(%rsp), %rdi
	leaq	44(%rsp), %rsi
	movq	%rax, 64(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 32(%rsp)
	movl	$1, 40(%rsp)
	movq	%rax, 44(%rsp)
	movl	$1, 52(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L136
	pushq	24(%rsp)
	.cfi_def_cfa_offset 104
	leaq	_Z13cuda_asum_intILj256EEvPiS0_(%rip), %rdi
	pushq	24(%rsp)
	.cfi_def_cfa_offset 112
	movq	60(%rsp), %rcx
	movl	68(%rsp), %r8d
	movq	48(%rsp), %rsi
	movl	56(%rsp), %edx
	leaq	72(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 104
	popq	%rdx
	.cfi_def_cfa_offset 96
.L136:
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L138
	call	__stack_chk_fail@PLT
.L138:
	addq	$88, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4394:
	.size	_Z36__wrapper__device_stub_cuda_asum_intILj256EEvRPiS1_.isra.0, .-_Z36__wrapper__device_stub_cuda_asum_intILj256EEvRPiS1_.isra.0
	.section	.text._Z13cuda_asum_intILj256EEvPiS0_,"axG",@progbits,_Z13cuda_asum_intILj256EEvPiS0_,comdat
	.weak	_Z13cuda_asum_intILj256EEvPiS0_
	.type	_Z13cuda_asum_intILj256EEvPiS0_, @function
_Z13cuda_asum_intILj256EEvPiS0_:
.LFB4032:
	.cfi_startproc
	endbr64
	jmp	_Z36__wrapper__device_stub_cuda_asum_intILj256EEvRPiS1_.isra.0
	.cfi_endproc
.LFE4032:
	.size	_Z13cuda_asum_intILj256EEvPiS0_, .-_Z13cuda_asum_intILj256EEvPiS0_
	.section	.text._Z14cuda_asum_doubILj1EEvPdS0_,"axG",@progbits,_Z14cuda_asum_doubILj1EEvPdS0_,comdat
	.weak	_Z14cuda_asum_doubILj1EEvPdS0_
	.type	_Z14cuda_asum_doubILj1EEvPdS0_, @function
_Z14cuda_asum_doubILj1EEvPdS0_:
.LFB4061:
	.cfi_startproc
	endbr64
	jmp	_ZL44__device_stub__Z14cuda_asum_doubILj1EEvPdS0_PdS_
	.cfi_endproc
.LFE4061:
	.size	_Z14cuda_asum_doubILj1EEvPdS0_, .-_Z14cuda_asum_doubILj1EEvPdS0_
	.section	.text._Z13cuda_asum_intILj512EEvPiS0_,"axG",@progbits,_Z13cuda_asum_intILj512EEvPiS0_,comdat
	.weak	_Z13cuda_asum_intILj512EEvPiS0_
	.type	_Z13cuda_asum_intILj512EEvPiS0_, @function
_Z13cuda_asum_intILj512EEvPiS0_:
.LFB4031:
	.cfi_startproc
	endbr64
	jmp	_ZL45__device_stub__Z13cuda_asum_intILj512EEvPiS0_PiS_
	.cfi_endproc
.LFE4031:
	.size	_Z13cuda_asum_intILj512EEvPiS0_, .-_Z13cuda_asum_intILj512EEvPiS0_
	.section	.text._Z13cuda_asum_intILj128EEvPiS0_,"axG",@progbits,_Z13cuda_asum_intILj128EEvPiS0_,comdat
	.weak	_Z13cuda_asum_intILj128EEvPiS0_
	.type	_Z13cuda_asum_intILj128EEvPiS0_, @function
_Z13cuda_asum_intILj128EEvPiS0_:
.LFB4033:
	.cfi_startproc
	endbr64
	jmp	_ZL45__device_stub__Z13cuda_asum_intILj128EEvPiS0_PiS_
	.cfi_endproc
.LFE4033:
	.size	_Z13cuda_asum_intILj128EEvPiS0_, .-_Z13cuda_asum_intILj128EEvPiS0_
	.section	.text._Z13cuda_asum_intILj64EEvPiS0_,"axG",@progbits,_Z13cuda_asum_intILj64EEvPiS0_,comdat
	.weak	_Z13cuda_asum_intILj64EEvPiS0_
	.type	_Z13cuda_asum_intILj64EEvPiS0_, @function
_Z13cuda_asum_intILj64EEvPiS0_:
.LFB4034:
	.cfi_startproc
	endbr64
	jmp	_ZL44__device_stub__Z13cuda_asum_intILj64EEvPiS0_PiS_
	.cfi_endproc
.LFE4034:
	.size	_Z13cuda_asum_intILj64EEvPiS0_, .-_Z13cuda_asum_intILj64EEvPiS0_
	.section	.text._Z13cuda_asum_intILj32EEvPiS0_,"axG",@progbits,_Z13cuda_asum_intILj32EEvPiS0_,comdat
	.weak	_Z13cuda_asum_intILj32EEvPiS0_
	.type	_Z13cuda_asum_intILj32EEvPiS0_, @function
_Z13cuda_asum_intILj32EEvPiS0_:
.LFB4035:
	.cfi_startproc
	endbr64
	jmp	_ZL44__device_stub__Z13cuda_asum_intILj32EEvPiS0_PiS_
	.cfi_endproc
.LFE4035:
	.size	_Z13cuda_asum_intILj32EEvPiS0_, .-_Z13cuda_asum_intILj32EEvPiS0_
	.section	.text._Z13cuda_asum_intILj16EEvPiS0_,"axG",@progbits,_Z13cuda_asum_intILj16EEvPiS0_,comdat
	.weak	_Z13cuda_asum_intILj16EEvPiS0_
	.type	_Z13cuda_asum_intILj16EEvPiS0_, @function
_Z13cuda_asum_intILj16EEvPiS0_:
.LFB4036:
	.cfi_startproc
	endbr64
	jmp	_ZL44__device_stub__Z13cuda_asum_intILj16EEvPiS0_PiS_
	.cfi_endproc
.LFE4036:
	.size	_Z13cuda_asum_intILj16EEvPiS0_, .-_Z13cuda_asum_intILj16EEvPiS0_
	.section	.text._Z13cuda_asum_intILj8EEvPiS0_,"axG",@progbits,_Z13cuda_asum_intILj8EEvPiS0_,comdat
	.weak	_Z13cuda_asum_intILj8EEvPiS0_
	.type	_Z13cuda_asum_intILj8EEvPiS0_, @function
_Z13cuda_asum_intILj8EEvPiS0_:
.LFB4037:
	.cfi_startproc
	endbr64
	jmp	_ZL43__device_stub__Z13cuda_asum_intILj8EEvPiS0_PiS_
	.cfi_endproc
.LFE4037:
	.size	_Z13cuda_asum_intILj8EEvPiS0_, .-_Z13cuda_asum_intILj8EEvPiS0_
	.section	.text._Z13cuda_asum_intILj4EEvPiS0_,"axG",@progbits,_Z13cuda_asum_intILj4EEvPiS0_,comdat
	.weak	_Z13cuda_asum_intILj4EEvPiS0_
	.type	_Z13cuda_asum_intILj4EEvPiS0_, @function
_Z13cuda_asum_intILj4EEvPiS0_:
.LFB4038:
	.cfi_startproc
	endbr64
	jmp	_ZL43__device_stub__Z13cuda_asum_intILj4EEvPiS0_PiS_
	.cfi_endproc
.LFE4038:
	.size	_Z13cuda_asum_intILj4EEvPiS0_, .-_Z13cuda_asum_intILj4EEvPiS0_
	.section	.text._Z13cuda_asum_intILj2EEvPiS0_,"axG",@progbits,_Z13cuda_asum_intILj2EEvPiS0_,comdat
	.weak	_Z13cuda_asum_intILj2EEvPiS0_
	.type	_Z13cuda_asum_intILj2EEvPiS0_, @function
_Z13cuda_asum_intILj2EEvPiS0_:
.LFB4039:
	.cfi_startproc
	endbr64
	jmp	_ZL43__device_stub__Z13cuda_asum_intILj2EEvPiS0_PiS_
	.cfi_endproc
.LFE4039:
	.size	_Z13cuda_asum_intILj2EEvPiS0_, .-_Z13cuda_asum_intILj2EEvPiS0_
	.section	.text._Z13cuda_asum_intILj1EEvPiS0_,"axG",@progbits,_Z13cuda_asum_intILj1EEvPiS0_,comdat
	.weak	_Z13cuda_asum_intILj1EEvPiS0_
	.type	_Z13cuda_asum_intILj1EEvPiS0_, @function
_Z13cuda_asum_intILj1EEvPiS0_:
.LFB4040:
	.cfi_startproc
	endbr64
	jmp	_ZL43__device_stub__Z13cuda_asum_intILj1EEvPiS0_PiS_
	.cfi_endproc
.LFE4040:
	.size	_Z13cuda_asum_intILj1EEvPiS0_, .-_Z13cuda_asum_intILj1EEvPiS0_
	.section	.text._Z14cuda_asum_doubILj512EEvPdS0_,"axG",@progbits,_Z14cuda_asum_doubILj512EEvPdS0_,comdat
	.weak	_Z14cuda_asum_doubILj512EEvPdS0_
	.type	_Z14cuda_asum_doubILj512EEvPdS0_, @function
_Z14cuda_asum_doubILj512EEvPdS0_:
.LFB4052:
	.cfi_startproc
	endbr64
	jmp	_ZL46__device_stub__Z14cuda_asum_doubILj512EEvPdS0_PdS_
	.cfi_endproc
.LFE4052:
	.size	_Z14cuda_asum_doubILj512EEvPdS0_, .-_Z14cuda_asum_doubILj512EEvPdS0_
	.section	.text._Z14cuda_asum_doubILj128EEvPdS0_,"axG",@progbits,_Z14cuda_asum_doubILj128EEvPdS0_,comdat
	.weak	_Z14cuda_asum_doubILj128EEvPdS0_
	.type	_Z14cuda_asum_doubILj128EEvPdS0_, @function
_Z14cuda_asum_doubILj128EEvPdS0_:
.LFB4054:
	.cfi_startproc
	endbr64
	jmp	_ZL46__device_stub__Z14cuda_asum_doubILj128EEvPdS0_PdS_
	.cfi_endproc
.LFE4054:
	.size	_Z14cuda_asum_doubILj128EEvPdS0_, .-_Z14cuda_asum_doubILj128EEvPdS0_
	.section	.text._Z14cuda_asum_doubILj64EEvPdS0_,"axG",@progbits,_Z14cuda_asum_doubILj64EEvPdS0_,comdat
	.weak	_Z14cuda_asum_doubILj64EEvPdS0_
	.type	_Z14cuda_asum_doubILj64EEvPdS0_, @function
_Z14cuda_asum_doubILj64EEvPdS0_:
.LFB4055:
	.cfi_startproc
	endbr64
	jmp	_ZL45__device_stub__Z14cuda_asum_doubILj64EEvPdS0_PdS_
	.cfi_endproc
.LFE4055:
	.size	_Z14cuda_asum_doubILj64EEvPdS0_, .-_Z14cuda_asum_doubILj64EEvPdS0_
	.section	.text._Z14cuda_asum_doubILj32EEvPdS0_,"axG",@progbits,_Z14cuda_asum_doubILj32EEvPdS0_,comdat
	.weak	_Z14cuda_asum_doubILj32EEvPdS0_
	.type	_Z14cuda_asum_doubILj32EEvPdS0_, @function
_Z14cuda_asum_doubILj32EEvPdS0_:
.LFB4056:
	.cfi_startproc
	endbr64
	jmp	_ZL45__device_stub__Z14cuda_asum_doubILj32EEvPdS0_PdS_
	.cfi_endproc
.LFE4056:
	.size	_Z14cuda_asum_doubILj32EEvPdS0_, .-_Z14cuda_asum_doubILj32EEvPdS0_
	.section	.text._Z14cuda_asum_doubILj16EEvPdS0_,"axG",@progbits,_Z14cuda_asum_doubILj16EEvPdS0_,comdat
	.weak	_Z14cuda_asum_doubILj16EEvPdS0_
	.type	_Z14cuda_asum_doubILj16EEvPdS0_, @function
_Z14cuda_asum_doubILj16EEvPdS0_:
.LFB4057:
	.cfi_startproc
	endbr64
	jmp	_ZL45__device_stub__Z14cuda_asum_doubILj16EEvPdS0_PdS_
	.cfi_endproc
.LFE4057:
	.size	_Z14cuda_asum_doubILj16EEvPdS0_, .-_Z14cuda_asum_doubILj16EEvPdS0_
	.section	.text._Z14cuda_asum_doubILj8EEvPdS0_,"axG",@progbits,_Z14cuda_asum_doubILj8EEvPdS0_,comdat
	.weak	_Z14cuda_asum_doubILj8EEvPdS0_
	.type	_Z14cuda_asum_doubILj8EEvPdS0_, @function
_Z14cuda_asum_doubILj8EEvPdS0_:
.LFB4058:
	.cfi_startproc
	endbr64
	jmp	_ZL44__device_stub__Z14cuda_asum_doubILj8EEvPdS0_PdS_
	.cfi_endproc
.LFE4058:
	.size	_Z14cuda_asum_doubILj8EEvPdS0_, .-_Z14cuda_asum_doubILj8EEvPdS0_
	.section	.text._Z14cuda_asum_doubILj4EEvPdS0_,"axG",@progbits,_Z14cuda_asum_doubILj4EEvPdS0_,comdat
	.weak	_Z14cuda_asum_doubILj4EEvPdS0_
	.type	_Z14cuda_asum_doubILj4EEvPdS0_, @function
_Z14cuda_asum_doubILj4EEvPdS0_:
.LFB4059:
	.cfi_startproc
	endbr64
	jmp	_ZL44__device_stub__Z14cuda_asum_doubILj4EEvPdS0_PdS_
	.cfi_endproc
.LFE4059:
	.size	_Z14cuda_asum_doubILj4EEvPdS0_, .-_Z14cuda_asum_doubILj4EEvPdS0_
	.section	.text._Z14cuda_asum_doubILj2EEvPdS0_,"axG",@progbits,_Z14cuda_asum_doubILj2EEvPdS0_,comdat
	.weak	_Z14cuda_asum_doubILj2EEvPdS0_
	.type	_Z14cuda_asum_doubILj2EEvPdS0_, @function
_Z14cuda_asum_doubILj2EEvPdS0_:
.LFB4060:
	.cfi_startproc
	endbr64
	jmp	_ZL44__device_stub__Z14cuda_asum_doubILj2EEvPdS0_PdS_
	.cfi_endproc
.LFE4060:
	.size	_Z14cuda_asum_doubILj2EEvPdS0_, .-_Z14cuda_asum_doubILj2EEvPdS0_
	.text
	.globl	_Z14cuda_asum_intmPii
	.type	_Z14cuda_asum_intmPii, @function
_Z14cuda_asum_intmPii:
.LFB3637:
	.cfi_startproc
	endbr64
	pushq	%r12
	.cfi_def_cfa_offset 16
	.cfi_offset 12, -16
	pushq	%rbp
	.cfi_def_cfa_offset 24
	.cfi_offset 6, -24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset 3, -32
	movq	%rdi, %rbx
	subq	$32, %rsp
	.cfi_def_cfa_offset 64
	cmpl	$512, %esi
	jle	.L164
	movabsq	$4294967552, %r12
	movl	%esi, %ebp
	sarl	$9, %ebp
.L161:
	cmpl	$1, %ebp
	jbe	.L164
	movl	%ebp, 8(%rsp)
	xorl	%r9d, %r9d
	movl	$1024, %r8d
	movq	%r12, %rdx
	movabsq	$4294967297, %rax
	movl	$1, %ecx
	movq	%r12, 20(%rsp)
	movq	%rax, 12(%rsp)
	movq	8(%rsp), %rdi
	movl	16(%rsp), %esi
	movl	$1, 28(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L162
	movq	%rbx, %rsi
	movq	%rbx, %rdi
	call	_Z36__wrapper__device_stub_cuda_asum_intILj256EEvRPiS1_.isra.0
.L162:
	movl	%ebp, %esi
	shrl	$9, %ebp
	jmp	.L161
.L164:
	shrl	%esi
	cmpl	$32, %esi
	je	.L165
	ja	.L166
	cmpl	$4, %esi
	je	.L167
	ja	.L168
	cmpl	$1, %esi
	je	.L169
	cmpl	$2, %esi
	je	.L170
	jmp	.L159
.L168:
	cmpl	$8, %esi
	je	.L172
	cmpl	$16, %esi
	je	.L173
	jmp	.L159
.L166:
	cmpl	$256, %esi
	je	.L174
	ja	.L175
	cmpl	$64, %esi
	je	.L176
	cmpl	$128, %esi
	je	.L177
	jmp	.L159
.L175:
	cmpl	$512, %esi
	jne	.L159
	movl	$8388609, %edx
	xorl	%r9d, %r9d
	movl	$1, %ecx
	movabsq	$4294967297, %rdi
	salq	$9, %rdx
	movl	$2048, %r8d
	movl	$1, %esi
	movl	$1, 28(%rsp)
	movq	%rdx, 20(%rsp)
	movq	%rdi, 8(%rsp)
	movl	$1, 16(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L159
	addq	$32, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 32
	movq	%rbx, %rsi
	movq	%rbx, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	jmp	_ZL45__device_stub__Z13cuda_asum_intILj512EEvPiS0_PiS_
.L174:
	.cfi_restore_state
	movl	$16777217, %edx
	xorl	%r9d, %r9d
	movl	$1, %ecx
	movabsq	$4294967297, %rdi
	salq	$8, %rdx
	movl	$1024, %r8d
	movl	$1, %esi
	movl	$1, 28(%rsp)
	movq	%rdx, 20(%rsp)
	movq	%rdi, 8(%rsp)
	movl	$1, 16(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L159
	addq	$32, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 32
	movq	%rbx, %rsi
	movq	%rbx, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	jmp	_Z36__wrapper__device_stub_cuda_asum_intILj256EEvRPiS1_.isra.0
.L177:
	.cfi_restore_state
	movl	$33554433, %edx
	xorl	%r9d, %r9d
	movl	$1, %ecx
	movabsq	$4294967297, %rdi
	salq	$7, %rdx
	movl	$512, %r8d
	movl	$1, %esi
	movl	$1, 28(%rsp)
	movq	%rdx, 20(%rsp)
	movq	%rdi, 8(%rsp)
	movl	$1, 16(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L159
	addq	$32, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 32
	movq	%rbx, %rsi
	movq	%rbx, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	jmp	_ZL45__device_stub__Z13cuda_asum_intILj128EEvPiS0_PiS_
.L176:
	.cfi_restore_state
	movl	$67108865, %edx
	xorl	%r9d, %r9d
	movl	$1, %ecx
	movabsq	$4294967297, %rdi
	salq	$6, %rdx
	movl	$256, %r8d
	movl	$1, %esi
	movl	$1, 28(%rsp)
	movq	%rdx, 20(%rsp)
	movq	%rdi, 8(%rsp)
	movl	$1, 16(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L159
	addq	$32, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 32
	movq	%rbx, %rsi
	movq	%rbx, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	jmp	_ZL44__device_stub__Z13cuda_asum_intILj64EEvPiS0_PiS_
.L165:
	.cfi_restore_state
	movl	$134217729, %edx
	xorl	%r9d, %r9d
	movl	$1, %ecx
	movabsq	$4294967297, %rdi
	salq	$5, %rdx
	movl	$128, %r8d
	movl	$1, %esi
	movl	$1, 28(%rsp)
	movq	%rdx, 20(%rsp)
	movq	%rdi, 8(%rsp)
	movl	$1, 16(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L159
	addq	$32, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 32
	movq	%rbx, %rsi
	movq	%rbx, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	jmp	_ZL44__device_stub__Z13cuda_asum_intILj32EEvPiS0_PiS_
.L173:
	.cfi_restore_state
	movl	$268435457, %edx
	xorl	%r9d, %r9d
	movl	$1, %ecx
	movabsq	$4294967297, %rdi
	salq	$4, %rdx
	movl	$64, %r8d
	movl	$1, %esi
	movl	$1, 28(%rsp)
	movq	%rdx, 20(%rsp)
	movq	%rdi, 8(%rsp)
	movl	$1, 16(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L159
	addq	$32, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 32
	movq	%rbx, %rsi
	movq	%rbx, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	jmp	_ZL44__device_stub__Z13cuda_asum_intILj16EEvPiS0_PiS_
.L172:
	.cfi_restore_state
	movl	$536870913, %edx
	xorl	%r9d, %r9d
	movl	$1, %ecx
	movabsq	$4294967297, %rdi
	salq	$3, %rdx
	movl	$32, %r8d
	movl	$1, %esi
	movl	$1, 28(%rsp)
	movq	%rdx, 20(%rsp)
	movq	%rdi, 8(%rsp)
	movl	$1, 16(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L159
	addq	$32, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 32
	movq	%rbx, %rsi
	movq	%rbx, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	jmp	_ZL43__device_stub__Z13cuda_asum_intILj8EEvPiS0_PiS_
.L167:
	.cfi_restore_state
	movl	$1073741825, %edx
	xorl	%r9d, %r9d
	movl	$1, %ecx
	movabsq	$4294967297, %rdi
	salq	$2, %rdx
	movl	$16, %r8d
	movl	$1, %esi
	movl	$1, 28(%rsp)
	movq	%rdx, 20(%rsp)
	movq	%rdi, 8(%rsp)
	movl	$1, 16(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L159
	addq	$32, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 32
	movq	%rbx, %rsi
	movq	%rbx, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	jmp	_ZL43__device_stub__Z13cuda_asum_intILj4EEvPiS0_PiS_
.L170:
	.cfi_restore_state
	movl	$2147483649, %edx
	xorl	%r9d, %r9d
	movl	$1, %ecx
	movabsq	$4294967297, %rdi
	addq	%rdx, %rdx
	movl	$8, %r8d
	movl	$1, %esi
	movl	$1, 28(%rsp)
	movq	%rdx, 20(%rsp)
	movq	%rdi, 8(%rsp)
	movl	$1, 16(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L159
	addq	$32, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 32
	movq	%rbx, %rsi
	movq	%rbx, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	jmp	_ZL43__device_stub__Z13cuda_asum_intILj2EEvPiS0_PiS_
.L169:
	.cfi_restore_state
	xorl	%r9d, %r9d
	movl	$4, %r8d
	movabsq	$4294967297, %rdi
	movl	$1, %ecx
	movq	%rdi, %rdx
	movl	$1, %esi
	movq	%rdi, 20(%rsp)
	movl	$1, 28(%rsp)
	movq	%rdi, 8(%rsp)
	movl	$1, 16(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L159
	addq	$32, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 32
	movq	%rbx, %rsi
	movq	%rbx, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	jmp	_ZL43__device_stub__Z13cuda_asum_intILj1EEvPiS0_PiS_
.L159:
	.cfi_restore_state
	addq	$32, %rsp
	.cfi_def_cfa_offset 32
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3637:
	.size	_Z14cuda_asum_intmPii, .-_Z14cuda_asum_intmPii
	.globl	_Z14cuda_asum_fltmPfii
	.type	_Z14cuda_asum_fltmPfii, @function
_Z14cuda_asum_fltmPfii:
.LFB3640:
	.cfi_startproc
	endbr64
	pushq	%r12
	.cfi_def_cfa_offset 16
	.cfi_offset 12, -16
	movl	%esi, %ecx
	pushq	%rbp
	.cfi_def_cfa_offset 24
	.cfi_offset 6, -24
	shrl	%ecx
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset 3, -32
	movq	%rdi, %rbx
	subq	$32, %rsp
	.cfi_def_cfa_offset 64
	cmpl	%esi, %edx
	jnb	.L218
	movl	%esi, %eax
	movl	%edx, %r12d
	leal	(%rdx,%rdx), %esi
	cltd
	idivl	%esi
	movl	%eax, %ebp
.L191:
	cmpl	$1, %ebp
	jbe	.L218
	cmpl	$32, %r12d
	je	.L192
	jg	.L193
	cmpl	$4, %r12d
	je	.L194
	jg	.L195
	cmpl	$1, %r12d
	je	.L196
	cmpl	$2, %r12d
	je	.L197
	jmp	.L198
.L195:
	cmpl	$8, %r12d
	je	.L199
	cmpl	$16, %r12d
	je	.L200
	jmp	.L198
.L193:
	cmpl	$256, %r12d
	je	.L201
	jg	.L202
	cmpl	$64, %r12d
	je	.L203
	cmpl	$128, %r12d
	je	.L204
	jmp	.L198
.L202:
	cmpl	$512, %r12d
	je	.L205
	cmpl	$1024, %r12d
	jne	.L198
	movl	%ebp, 8(%rsp)
	movl	$4194305, %edx
	xorl	%r9d, %r9d
	movl	$1, %ecx
	movabsq	$4294967297, %rax
	salq	$10, %rdx
	movl	$4096, %r8d
	movl	$1, 28(%rsp)
	movq	%rax, 12(%rsp)
	movq	8(%rsp), %rdi
	movl	16(%rsp), %esi
	movq	%rdx, 20(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L198
	movq	%rbx, %rsi
	movq	%rbx, %rdi
	call	_Z36__wrapper__device_stub_cuda_asum_fltILj1024EEvRPfS1_.isra.0
	jmp	.L198
.L205:
	movl	%ebp, 8(%rsp)
	movl	$8388609, %edx
	xorl	%r9d, %r9d
	movl	$1, %ecx
	movabsq	$4294967297, %rax
	salq	$9, %rdx
	movl	$2048, %r8d
	movl	$1, 28(%rsp)
	movq	%rax, 12(%rsp)
	movq	8(%rsp), %rdi
	movl	16(%rsp), %esi
	movq	%rdx, 20(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L198
	movq	%rbx, %rsi
	movq	%rbx, %rdi
	call	_Z36__wrapper__device_stub_cuda_asum_fltILj512EEvRPfS1_.isra.0
	jmp	.L198
.L201:
	movl	%ebp, 8(%rsp)
	movl	$16777217, %edx
	xorl	%r9d, %r9d
	movl	$1, %ecx
	movabsq	$4294967297, %rax
	salq	$8, %rdx
	movl	$1024, %r8d
	movl	$1, 28(%rsp)
	movq	%rax, 12(%rsp)
	movq	8(%rsp), %rdi
	movl	16(%rsp), %esi
	movq	%rdx, 20(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L198
	movq	%rbx, %rsi
	movq	%rbx, %rdi
	call	_Z36__wrapper__device_stub_cuda_asum_fltILj256EEvRPfS1_.isra.0
	jmp	.L198
.L204:
	movl	%ebp, 8(%rsp)
	movl	$33554433, %edx
	xorl	%r9d, %r9d
	movl	$1, %ecx
	movabsq	$4294967297, %rax
	salq	$7, %rdx
	movl	$512, %r8d
	movl	$1, 28(%rsp)
	movq	%rax, 12(%rsp)
	movq	8(%rsp), %rdi
	movl	16(%rsp), %esi
	movq	%rdx, 20(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L198
	movq	%rbx, %rsi
	movq	%rbx, %rdi
	call	_Z36__wrapper__device_stub_cuda_asum_fltILj128EEvRPfS1_.isra.0
	jmp	.L198
.L203:
	movl	%ebp, 8(%rsp)
	movl	$67108865, %edx
	xorl	%r9d, %r9d
	movl	$1, %ecx
	movabsq	$4294967297, %rax
	salq	$6, %rdx
	movl	$256, %r8d
	movl	$1, 28(%rsp)
	movq	%rax, 12(%rsp)
	movq	8(%rsp), %rdi
	movl	16(%rsp), %esi
	movq	%rdx, 20(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L198
	movq	%rbx, %rsi
	movq	%rbx, %rdi
	call	_Z36__wrapper__device_stub_cuda_asum_fltILj64EEvRPfS1_.isra.0
	jmp	.L198
.L192:
	movl	%ebp, 8(%rsp)
	movl	$134217729, %edx
	xorl	%r9d, %r9d
	movl	$1, %ecx
	movabsq	$4294967297, %rax
	salq	$5, %rdx
	movl	$128, %r8d
	movl	$1, 28(%rsp)
	movq	%rax, 12(%rsp)
	movq	8(%rsp), %rdi
	movl	16(%rsp), %esi
	movq	%rdx, 20(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L198
	movq	%rbx, %rsi
	movq	%rbx, %rdi
	call	_Z36__wrapper__device_stub_cuda_asum_fltILj32EEvRPfS1_.isra.0
	jmp	.L198
.L200:
	movl	%ebp, 8(%rsp)
	movl	$268435457, %edx
	xorl	%r9d, %r9d
	movl	$1, %ecx
	movabsq	$4294967297, %rax
	salq	$4, %rdx
	movl	$64, %r8d
	movl	$1, 28(%rsp)
	movq	%rax, 12(%rsp)
	movq	8(%rsp), %rdi
	movl	16(%rsp), %esi
	movq	%rdx, 20(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L198
	movq	%rbx, %rsi
	movq	%rbx, %rdi
	call	_Z36__wrapper__device_stub_cuda_asum_fltILj16EEvRPfS1_.isra.0
	jmp	.L198
.L199:
	movl	%ebp, 8(%rsp)
	movl	$536870913, %edx
	xorl	%r9d, %r9d
	movl	$1, %ecx
	movabsq	$4294967297, %rax
	salq	$3, %rdx
	movl	$32, %r8d
	movl	$1, 28(%rsp)
	movq	%rax, 12(%rsp)
	movq	8(%rsp), %rdi
	movl	16(%rsp), %esi
	movq	%rdx, 20(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L198
	movq	%rbx, %rsi
	movq	%rbx, %rdi
	call	_Z36__wrapper__device_stub_cuda_asum_fltILj8EEvRPfS1_.isra.0
	jmp	.L198
.L194:
	movl	%ebp, 8(%rsp)
	movl	$1073741825, %edx
	xorl	%r9d, %r9d
	movl	$1, %ecx
	movabsq	$4294967297, %rax
	salq	$2, %rdx
	movl	$16, %r8d
	movl	$1, 28(%rsp)
	movq	%rax, 12(%rsp)
	movq	8(%rsp), %rdi
	movl	16(%rsp), %esi
	movq	%rdx, 20(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L198
	movq	%rbx, %rsi
	movq	%rbx, %rdi
	call	_Z36__wrapper__device_stub_cuda_asum_fltILj4EEvRPfS1_.isra.0
	jmp	.L198
.L197:
	movl	%ebp, 8(%rsp)
	movl	$2147483649, %edx
	xorl	%r9d, %r9d
	movl	$1, %ecx
	movabsq	$4294967297, %rax
	addq	%rdx, %rdx
	movl	$8, %r8d
	movl	$1, 28(%rsp)
	movq	%rax, 12(%rsp)
	movq	8(%rsp), %rdi
	movl	16(%rsp), %esi
	movq	%rdx, 20(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L198
	movq	%rbx, %rsi
	movq	%rbx, %rdi
	call	_Z36__wrapper__device_stub_cuda_asum_fltILj2EEvRPfS1_.isra.0
	jmp	.L198
.L196:
	movl	%ebp, 8(%rsp)
	xorl	%r9d, %r9d
	movl	$1, %ecx
	movabsq	$4294967297, %rdx
	movq	%rdx, 12(%rsp)
	movq	8(%rsp), %rdi
	movl	$4, %r8d
	movl	16(%rsp), %esi
	movq	%rdx, 20(%rsp)
	movl	$1, 28(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L198
	movq	%rbx, %rsi
	movq	%rbx, %rdi
	call	_Z36__wrapper__device_stub_cuda_asum_fltILj1EEvRPfS1_.isra.0
.L198:
	movl	%ebp, %ecx
	shrl	$10, %ebp
	jmp	.L191
.L218:
	movl	%ecx, %eax
	shrl	%eax
	cmpl	$32, %eax
	je	.L219
	ja	.L220
	cmpl	$4, %eax
	je	.L221
	ja	.L222
	cmpl	$1, %eax
	je	.L223
	cmpl	$2, %eax
	je	.L224
	jmp	.L189
.L222:
	cmpl	$8, %eax
	je	.L226
	cmpl	$16, %eax
	je	.L227
	jmp	.L189
.L220:
	cmpl	$256, %eax
	je	.L228
	ja	.L229
	cmpl	$64, %eax
	je	.L230
	cmpl	$128, %eax
	je	.L231
	jmp	.L189
.L229:
	cmpl	$512, %eax
	je	.L232
	cmpl	$1024, %eax
	jne	.L189
	movl	$4194305, %edx
	xorl	%r9d, %r9d
	movl	$1, %ecx
	movabsq	$4294967297, %rdi
	salq	$10, %rdx
	movl	$4096, %r8d
	movl	$1, %esi
	movl	$1, 28(%rsp)
	movq	%rdx, 20(%rsp)
	movq	%rdi, 8(%rsp)
	movl	$1, 16(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L189
	addq	$32, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 32
	movq	%rbx, %rsi
	movq	%rbx, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	jmp	_Z36__wrapper__device_stub_cuda_asum_fltILj1024EEvRPfS1_.isra.0
.L232:
	.cfi_restore_state
	movl	$8388609, %edx
	xorl	%r9d, %r9d
	movl	$1, %ecx
	movabsq	$4294967297, %rdi
	salq	$9, %rdx
	movl	$2048, %r8d
	movl	$1, %esi
	movl	$1, 28(%rsp)
	movq	%rdx, 20(%rsp)
	movq	%rdi, 8(%rsp)
	movl	$1, 16(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L189
	addq	$32, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 32
	movq	%rbx, %rsi
	movq	%rbx, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	jmp	_Z36__wrapper__device_stub_cuda_asum_fltILj512EEvRPfS1_.isra.0
.L228:
	.cfi_restore_state
	movl	$16777217, %edx
	xorl	%r9d, %r9d
	movl	$1, %ecx
	movabsq	$4294967297, %rdi
	salq	$8, %rdx
	movl	$1024, %r8d
	movl	$1, %esi
	movl	$1, 28(%rsp)
	movq	%rdx, 20(%rsp)
	movq	%rdi, 8(%rsp)
	movl	$1, 16(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L189
	addq	$32, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 32
	movq	%rbx, %rsi
	movq	%rbx, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	jmp	_Z36__wrapper__device_stub_cuda_asum_fltILj256EEvRPfS1_.isra.0
.L231:
	.cfi_restore_state
	movl	$33554433, %edx
	xorl	%r9d, %r9d
	movl	$1, %ecx
	movabsq	$4294967297, %rdi
	salq	$7, %rdx
	movl	$512, %r8d
	movl	$1, %esi
	movl	$1, 28(%rsp)
	movq	%rdx, 20(%rsp)
	movq	%rdi, 8(%rsp)
	movl	$1, 16(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L189
	addq	$32, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 32
	movq	%rbx, %rsi
	movq	%rbx, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	jmp	_Z36__wrapper__device_stub_cuda_asum_fltILj128EEvRPfS1_.isra.0
.L230:
	.cfi_restore_state
	movl	$67108865, %edx
	xorl	%r9d, %r9d
	movl	$1, %ecx
	movabsq	$4294967297, %rdi
	salq	$6, %rdx
	movl	$256, %r8d
	movl	$1, %esi
	movl	$1, 28(%rsp)
	movq	%rdx, 20(%rsp)
	movq	%rdi, 8(%rsp)
	movl	$1, 16(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L189
	addq	$32, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 32
	movq	%rbx, %rsi
	movq	%rbx, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	jmp	_Z36__wrapper__device_stub_cuda_asum_fltILj64EEvRPfS1_.isra.0
.L219:
	.cfi_restore_state
	movl	$134217729, %edx
	xorl	%r9d, %r9d
	movl	$1, %ecx
	movabsq	$4294967297, %rdi
	salq	$5, %rdx
	movl	$128, %r8d
	movl	$1, %esi
	movl	$1, 28(%rsp)
	movq	%rdx, 20(%rsp)
	movq	%rdi, 8(%rsp)
	movl	$1, 16(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L189
	addq	$32, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 32
	movq	%rbx, %rsi
	movq	%rbx, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	jmp	_Z36__wrapper__device_stub_cuda_asum_fltILj32EEvRPfS1_.isra.0
.L227:
	.cfi_restore_state
	movl	$268435457, %edx
	xorl	%r9d, %r9d
	movl	$1, %ecx
	movabsq	$4294967297, %rdi
	salq	$4, %rdx
	movl	$64, %r8d
	movl	$1, %esi
	movl	$1, 28(%rsp)
	movq	%rdx, 20(%rsp)
	movq	%rdi, 8(%rsp)
	movl	$1, 16(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L189
	addq	$32, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 32
	movq	%rbx, %rsi
	movq	%rbx, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	jmp	_Z36__wrapper__device_stub_cuda_asum_fltILj16EEvRPfS1_.isra.0
.L226:
	.cfi_restore_state
	movl	$536870913, %edx
	xorl	%r9d, %r9d
	movl	$1, %ecx
	movabsq	$4294967297, %rdi
	salq	$3, %rdx
	movl	$32, %r8d
	movl	$1, %esi
	movl	$1, 28(%rsp)
	movq	%rdx, 20(%rsp)
	movq	%rdi, 8(%rsp)
	movl	$1, 16(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L189
	addq	$32, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 32
	movq	%rbx, %rsi
	movq	%rbx, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	jmp	_Z36__wrapper__device_stub_cuda_asum_fltILj8EEvRPfS1_.isra.0
.L221:
	.cfi_restore_state
	movl	$1073741825, %edx
	xorl	%r9d, %r9d
	movl	$1, %ecx
	movabsq	$4294967297, %rdi
	salq	$2, %rdx
	movl	$16, %r8d
	movl	$1, %esi
	movl	$1, 28(%rsp)
	movq	%rdx, 20(%rsp)
	movq	%rdi, 8(%rsp)
	movl	$1, 16(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L189
	addq	$32, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 32
	movq	%rbx, %rsi
	movq	%rbx, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	jmp	_Z36__wrapper__device_stub_cuda_asum_fltILj4EEvRPfS1_.isra.0
.L224:
	.cfi_restore_state
	movl	$2147483649, %edx
	xorl	%r9d, %r9d
	movl	$1, %ecx
	movabsq	$4294967297, %rdi
	addq	%rdx, %rdx
	movl	$8, %r8d
	movl	$1, %esi
	movl	$1, 28(%rsp)
	movq	%rdx, 20(%rsp)
	movq	%rdi, 8(%rsp)
	movl	$1, 16(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L189
	addq	$32, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 32
	movq	%rbx, %rsi
	movq	%rbx, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	jmp	_Z36__wrapper__device_stub_cuda_asum_fltILj2EEvRPfS1_.isra.0
.L223:
	.cfi_restore_state
	xorl	%r9d, %r9d
	movl	$4, %r8d
	movabsq	$4294967297, %rdi
	movl	$1, %ecx
	movq	%rdi, %rdx
	movl	$1, %esi
	movq	%rdi, 20(%rsp)
	movl	$1, 28(%rsp)
	movq	%rdi, 8(%rsp)
	movl	$1, 16(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L189
	addq	$32, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 32
	movq	%rbx, %rsi
	movq	%rbx, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	jmp	_Z36__wrapper__device_stub_cuda_asum_fltILj1EEvRPfS1_.isra.0
.L189:
	.cfi_restore_state
	addq	$32, %rsp
	.cfi_def_cfa_offset 32
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3640:
	.size	_Z14cuda_asum_fltmPfii, .-_Z14cuda_asum_fltmPfii
	.globl	_Z15cuda_asum_doubmPdd
	.type	_Z15cuda_asum_doubmPdd, @function
_Z15cuda_asum_doubmPdd:
.LFB3643:
	.cfi_startproc
	endbr64
	pushq	%r12
	.cfi_def_cfa_offset 16
	.cfi_offset 12, -16
	pushq	%rbp
	.cfi_def_cfa_offset 24
	.cfi_offset 6, -24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset 3, -32
	movq	%rdi, %rbx
	subq	$32, %rsp
	.cfi_def_cfa_offset 64
	comisd	.LC0(%rip), %xmm0
	jbe	.L276
	mulsd	.LC1(%rip), %xmm0
	movabsq	$4294967552, %r12
	cvttsd2siq	%xmm0, %rbp
.L248:
	cmpl	$1, %ebp
	jbe	.L251
	movl	%ebp, 8(%rsp)
	xorl	%r9d, %r9d
	movl	$2048, %r8d
	movq	%r12, %rdx
	movabsq	$4294967297, %rax
	movl	$1, %ecx
	movq	%r12, 20(%rsp)
	movq	%rax, 12(%rsp)
	movq	8(%rsp), %rdi
	movl	16(%rsp), %esi
	movl	$1, 28(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L249
	movq	%rbx, %rsi
	movq	%rbx, %rdi
	call	_Z37__wrapper__device_stub_cuda_asum_doubILj256EEvRPdS1_.isra.0
.L249:
	movl	%ebp, %eax
	shrl	$9, %ebp
	jmp	.L248
.L276:
	cvttsd2siq	%xmm0, %rax
.L251:
	shrl	%eax
	cmpl	$32, %eax
	je	.L252
	ja	.L253
	cmpl	$4, %eax
	je	.L254
	ja	.L255
	cmpl	$1, %eax
	je	.L256
	cmpl	$2, %eax
	je	.L257
	jmp	.L245
.L255:
	cmpl	$8, %eax
	je	.L259
	cmpl	$16, %eax
	je	.L260
	jmp	.L245
.L253:
	cmpl	$256, %eax
	je	.L261
	ja	.L262
	cmpl	$64, %eax
	je	.L263
	cmpl	$128, %eax
	je	.L264
	jmp	.L245
.L262:
	cmpl	$512, %eax
	jne	.L245
	movl	$8388609, %edx
	xorl	%r9d, %r9d
	movl	$1, %ecx
	movabsq	$4294967297, %rdi
	salq	$9, %rdx
	movl	$4096, %r8d
	movl	$1, %esi
	movl	$1, 28(%rsp)
	movq	%rdx, 20(%rsp)
	movq	%rdi, 8(%rsp)
	movl	$1, 16(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L245
	addq	$32, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 32
	movq	%rbx, %rsi
	movq	%rbx, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	jmp	_ZL46__device_stub__Z14cuda_asum_doubILj512EEvPdS0_PdS_
.L261:
	.cfi_restore_state
	movl	$16777217, %edx
	xorl	%r9d, %r9d
	movl	$1, %ecx
	movabsq	$4294967297, %rdi
	salq	$8, %rdx
	movl	$2048, %r8d
	movl	$1, %esi
	movl	$1, 28(%rsp)
	movq	%rdx, 20(%rsp)
	movq	%rdi, 8(%rsp)
	movl	$1, 16(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L245
	addq	$32, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 32
	movq	%rbx, %rsi
	movq	%rbx, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	jmp	_Z37__wrapper__device_stub_cuda_asum_doubILj256EEvRPdS1_.isra.0
.L264:
	.cfi_restore_state
	movl	$33554433, %edx
	xorl	%r9d, %r9d
	movl	$1, %ecx
	movabsq	$4294967297, %rdi
	salq	$7, %rdx
	movl	$1024, %r8d
	movl	$1, %esi
	movl	$1, 28(%rsp)
	movq	%rdx, 20(%rsp)
	movq	%rdi, 8(%rsp)
	movl	$1, 16(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L245
	addq	$32, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 32
	movq	%rbx, %rsi
	movq	%rbx, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	jmp	_ZL46__device_stub__Z14cuda_asum_doubILj128EEvPdS0_PdS_
.L263:
	.cfi_restore_state
	movl	$67108865, %edx
	xorl	%r9d, %r9d
	movl	$1, %ecx
	movabsq	$4294967297, %rdi
	salq	$6, %rdx
	movl	$512, %r8d
	movl	$1, %esi
	movl	$1, 28(%rsp)
	movq	%rdx, 20(%rsp)
	movq	%rdi, 8(%rsp)
	movl	$1, 16(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L245
	addq	$32, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 32
	movq	%rbx, %rsi
	movq	%rbx, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	jmp	_ZL45__device_stub__Z14cuda_asum_doubILj64EEvPdS0_PdS_
.L252:
	.cfi_restore_state
	movl	$134217729, %edx
	xorl	%r9d, %r9d
	movl	$1, %ecx
	movabsq	$4294967297, %rdi
	salq	$5, %rdx
	movl	$256, %r8d
	movl	$1, %esi
	movl	$1, 28(%rsp)
	movq	%rdx, 20(%rsp)
	movq	%rdi, 8(%rsp)
	movl	$1, 16(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L245
	addq	$32, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 32
	movq	%rbx, %rsi
	movq	%rbx, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	jmp	_ZL45__device_stub__Z14cuda_asum_doubILj32EEvPdS0_PdS_
.L260:
	.cfi_restore_state
	movl	$268435457, %edx
	xorl	%r9d, %r9d
	movl	$1, %ecx
	movabsq	$4294967297, %rdi
	salq	$4, %rdx
	movl	$128, %r8d
	movl	$1, %esi
	movl	$1, 28(%rsp)
	movq	%rdx, 20(%rsp)
	movq	%rdi, 8(%rsp)
	movl	$1, 16(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L245
	addq	$32, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 32
	movq	%rbx, %rsi
	movq	%rbx, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	jmp	_ZL45__device_stub__Z14cuda_asum_doubILj16EEvPdS0_PdS_
.L259:
	.cfi_restore_state
	movl	$536870913, %edx
	xorl	%r9d, %r9d
	movl	$1, %ecx
	movabsq	$4294967297, %rdi
	salq	$3, %rdx
	movl	$64, %r8d
	movl	$1, %esi
	movl	$1, 28(%rsp)
	movq	%rdx, 20(%rsp)
	movq	%rdi, 8(%rsp)
	movl	$1, 16(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L245
	addq	$32, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 32
	movq	%rbx, %rsi
	movq	%rbx, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	jmp	_ZL44__device_stub__Z14cuda_asum_doubILj8EEvPdS0_PdS_
.L254:
	.cfi_restore_state
	movl	$1073741825, %edx
	xorl	%r9d, %r9d
	movl	$1, %ecx
	movabsq	$4294967297, %rdi
	salq	$2, %rdx
	movl	$32, %r8d
	movl	$1, %esi
	movl	$1, 28(%rsp)
	movq	%rdx, 20(%rsp)
	movq	%rdi, 8(%rsp)
	movl	$1, 16(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L245
	addq	$32, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 32
	movq	%rbx, %rsi
	movq	%rbx, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	jmp	_ZL44__device_stub__Z14cuda_asum_doubILj4EEvPdS0_PdS_
.L257:
	.cfi_restore_state
	movl	$2147483649, %edx
	xorl	%r9d, %r9d
	movl	$1, %ecx
	movabsq	$4294967297, %rdi
	addq	%rdx, %rdx
	movl	$16, %r8d
	movl	$1, %esi
	movl	$1, 28(%rsp)
	movq	%rdx, 20(%rsp)
	movq	%rdi, 8(%rsp)
	movl	$1, 16(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L245
	addq	$32, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 32
	movq	%rbx, %rsi
	movq	%rbx, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	jmp	_ZL44__device_stub__Z14cuda_asum_doubILj2EEvPdS0_PdS_
.L256:
	.cfi_restore_state
	xorl	%r9d, %r9d
	movl	$8, %r8d
	movabsq	$4294967297, %rdi
	movl	$1, %ecx
	movq	%rdi, %rdx
	movl	$1, %esi
	movq	%rdi, 20(%rsp)
	movl	$1, 28(%rsp)
	movq	%rdi, 8(%rsp)
	movl	$1, 16(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L245
	addq	$32, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 32
	movq	%rbx, %rsi
	movq	%rbx, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	jmp	_ZL44__device_stub__Z14cuda_asum_doubILj1EEvPdS0_PdS_
.L245:
	.cfi_restore_state
	addq	$32, %rsp
	.cfi_def_cfa_offset 32
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3643:
	.size	_Z15cuda_asum_doubmPdd, .-_Z15cuda_asum_doubmPdd
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC2:
	.string	"_Z14cuda_asum_doubILj1EEvPdS0_"
.LC3:
	.string	"_Z14cuda_asum_doubILj2EEvPdS0_"
.LC4:
	.string	"_Z14cuda_asum_doubILj4EEvPdS0_"
.LC5:
	.string	"_Z14cuda_asum_doubILj8EEvPdS0_"
.LC6:
	.string	"_Z14cuda_asum_doubILj16EEvPdS0_"
.LC7:
	.string	"_Z14cuda_asum_doubILj32EEvPdS0_"
.LC8:
	.string	"_Z14cuda_asum_doubILj64EEvPdS0_"
.LC9:
	.string	"_Z14cuda_asum_doubILj128EEvPdS0_"
.LC10:
	.string	"_Z14cuda_asum_doubILj256EEvPdS0_"
.LC11:
	.string	"_Z14cuda_asum_doubILj512EEvPdS0_"
.LC12:
	.string	"_Z13cuda_asum_fltILj1EEvPfS0_"
.LC13:
	.string	"_Z13cuda_asum_fltILj2EEvPfS0_"
.LC14:
	.string	"_Z13cuda_asum_fltILj4EEvPfS0_"
.LC15:
	.string	"_Z13cuda_asum_fltILj8EEvPfS0_"
.LC16:
	.string	"_Z13cuda_asum_fltILj16EEvPfS0_"
.LC17:
	.string	"_Z13cuda_asum_fltILj32EEvPfS0_"
.LC18:
	.string	"_Z13cuda_asum_fltILj64EEvPfS0_"
.LC19:
	.string	"_Z13cuda_asum_fltILj128EEvPfS0_"
.LC20:
	.string	"_Z13cuda_asum_fltILj256EEvPfS0_"
.LC21:
	.string	"_Z13cuda_asum_fltILj512EEvPfS0_"
.LC22:
	.string	"_Z13cuda_asum_fltILj1024EEvPfS0_"
.LC23:
	.string	"_Z13cuda_asum_intILj1EEvPiS0_"
.LC24:
	.string	"_Z13cuda_asum_intILj2EEvPiS0_"
.LC25:
	.string	"_Z13cuda_asum_intILj4EEvPiS0_"
.LC26:
	.string	"_Z13cuda_asum_intILj8EEvPiS0_"
.LC27:
	.string	"_Z13cuda_asum_intILj16EEvPiS0_"
.LC28:
	.string	"_Z13cuda_asum_intILj32EEvPiS0_"
.LC29:
	.string	"_Z13cuda_asum_intILj64EEvPiS0_"
.LC30:
	.string	"_Z13cuda_asum_intILj128EEvPiS0_"
.LC31:
	.string	"_Z13cuda_asum_intILj256EEvPiS0_"
.LC32:
	.string	"_Z13cuda_asum_intILj512EEvPiS0_"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3731:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC2(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z14cuda_asum_doubILj1EEvPdS0_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC3(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z14cuda_asum_doubILj2EEvPdS0_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC4(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z14cuda_asum_doubILj4EEvPdS0_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC5(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z14cuda_asum_doubILj8EEvPdS0_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC6(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z14cuda_asum_doubILj16EEvPdS0_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC7(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z14cuda_asum_doubILj32EEvPdS0_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC8(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z14cuda_asum_doubILj64EEvPdS0_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC9(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z14cuda_asum_doubILj128EEvPdS0_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	leaq	.LC10(%rip), %rdx
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	_Z14cuda_asum_doubILj256EEvPdS0_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC11(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z14cuda_asum_doubILj512EEvPdS0_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC12(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z13cuda_asum_fltILj1EEvPfS0_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC13(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z13cuda_asum_fltILj2EEvPfS0_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC14(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z13cuda_asum_fltILj4EEvPfS0_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC15(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z13cuda_asum_fltILj8EEvPfS0_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC16(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z13cuda_asum_fltILj16EEvPfS0_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC17(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z13cuda_asum_fltILj32EEvPfS0_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	leaq	.LC18(%rip), %rdx
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	_Z13cuda_asum_fltILj64EEvPfS0_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC19(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z13cuda_asum_fltILj128EEvPfS0_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC20(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z13cuda_asum_fltILj256EEvPfS0_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC21(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z13cuda_asum_fltILj512EEvPfS0_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC22(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z13cuda_asum_fltILj1024EEvPfS0_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC23(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z13cuda_asum_intILj1EEvPiS0_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC24(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z13cuda_asum_intILj2EEvPiS0_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC25(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z13cuda_asum_intILj4EEvPiS0_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	leaq	.LC26(%rip), %rdx
	pushq	$0
	.cfi_def_cfa_offset 24
	movq	%rdx, %rcx
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	_Z13cuda_asum_intILj8EEvPiS0_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC27(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z13cuda_asum_intILj16EEvPiS0_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC28(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z13cuda_asum_intILj32EEvPiS0_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC29(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z13cuda_asum_intILj64EEvPiS0_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC30(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z13cuda_asum_intILj128EEvPiS0_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC31(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z13cuda_asum_intILj256EEvPiS0_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC32(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z13cuda_asum_intILj512EEvPiS0_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3731:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst8,"aM",@progbits,8
	.align 8
.LC0:
	.long	0
	.long	1082130432
	.align 8
.LC1:
	.long	0
	.long	1063256064
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

/**************************************************
*******PROGRAM FOR ARRAY REDUCTION IN CUDA*********
***************************************************
* EXTERNAL PROGRAMS INCLUDED:			  *
*						  *
* SUMS UPTO 2^24 INTS BEFORE REACHING BLOCK LIMIT *
* ARRAY MUST CONTAIN POWER OF TWO ELEMENTS	  *
* PROGRAM INCLUDES INTS,FLOATS AND DOUBS          *
*						  *
* Call INTS: cuda_asum_intm(ipt/opt array, N#s)   *
* Call FLTS: cuda_asum_fltm(ipt/opt array, N#s)   *
* Call DOUBS: cuda_asum_doubm(ipt/opt array, N#s) *
*						  *
***************************************************/

// *** INCLUDED LIBRARIES*** //
#include <stdio.h>
#include <stdlib.h>
#include <iostream>
#include <hip/hip_runtime.h>

// ***CUDA ERROR HANDLER*** //
#define CUDA_CALL(x) do { if((x) != hipSuccess) { \
printf("Error at %s:%d\n",__FILE__,__LINE__);\
return EXIT_FAILURE;}} while(0)

// ********************************************************************* //
// **********************INTEGER ARRAY SUMMATION************************ //
// ********************************************************************* //

// ****************************************** //
// ***INTEGERS DEVICE SIDE KERNEL PROGRAM**** //
// ****************************************** //
template <unsigned int blockSize>
__global__ void cuda_asum_int(int *d_idat, int *d_odat)
{
	extern __shared__ int sdata[];

	//LOAD ELEMENT FROM GLOBAL TO SHARED MEM
	unsigned int tid = threadIdx.x;
	unsigned int i = blockIdx.x * (blockDim.x * 2) + tid;
	
	sdata[tid] = d_idat[i] + d_idat[i + blockDim.x];
	__syncthreads();

	//REDUCTION
	if (blockSize >= 512) 
	{
		if (tid < 256) {sdata[tid] += sdata[tid + 256];} __syncthreads();
	}
        if (blockSize >= 256)
        {
                if (tid < 128) {sdata[tid] += sdata[tid + 128];} __syncthreads();
        }
        if (blockSize >= 128)
        {
                if (tid < 64) {sdata[tid] += sdata[tid + 64];} __syncthreads();
        }
     
	if (tid < 32)
	{
		if (blockSize >= 64) sdata[tid] += sdata[tid + 32];
		if (blockSize >= 32) sdata[tid] += sdata[tid + 16]; 
		if (blockSize >= 16) sdata[tid] += sdata[tid + 8];
		if (blockSize >= 8) sdata[tid] += sdata[tid + 4]; 
		if (blockSize >= 4) sdata[tid] += sdata[tid + 2]; 
		if (blockSize >= 2) sdata[tid] += sdata[tid + 1]; 
	}

	//WRITE RESULT TO GLOB MEM
	if(tid == 0) d_odat[blockIdx.x] = sdata[0];
}

// ****************************************** //
// ***INTS HOST SIDE KERNEL CALLER PROGRAM*** //
// ****************************************** //

//DEVICE ARRAY (d_idat) NEEDS TO BE DEFINED IN PARENT PROGRAM
extern void cuda_asum_intm(int *d_idat, int N_elem) //sqrt(N_elem) must be an int
{

	//THREAD AND BLOCK SIZES
	unsigned int THREAD_SIZE = 512/2;
	unsigned int BLOCK_SIZE = N_elem/512;
	unsigned int FINAL_THREAD;
	
        if (N_elem > 512)
        {
	//SUM THE ARRAY THROUGH MULTIPLE KERNEL CALLS
	while(BLOCK_SIZE > 1)
	{
		//RUN REDUCTIONS
		switch (THREAD_SIZE)
			{
			case 512:
				cuda_asum_int<512><<<BLOCK_SIZE,THREAD_SIZE,512*sizeof(int)>>>(d_idat,d_idat); break;
                        case 256:
                                cuda_asum_int<256><<<BLOCK_SIZE,THREAD_SIZE,256*sizeof(int)>>>(d_idat,d_idat); break;
                        case 128:
                                cuda_asum_int<128><<<BLOCK_SIZE,THREAD_SIZE,128*sizeof(int)>>>(d_idat,d_idat); break;
                        case 64:
                                cuda_asum_int< 64><<<BLOCK_SIZE,THREAD_SIZE,64*sizeof(int)>>>(d_idat,d_idat); break;
                        case 32:
                                cuda_asum_int< 32><<<BLOCK_SIZE,THREAD_SIZE,32*sizeof(int)>>>(d_idat,d_idat); break;
                        case 16:
                                cuda_asum_int< 16><<<BLOCK_SIZE,THREAD_SIZE,16*sizeof(int)>>>(d_idat,d_idat); break;
                        case 8:
                                cuda_asum_int<  8><<<BLOCK_SIZE,THREAD_SIZE,8*sizeof(int)>>>(d_idat,d_idat); break;
                        case 4:
                                cuda_asum_int<  4><<<BLOCK_SIZE,THREAD_SIZE,4*sizeof(int)>>>(d_idat,d_idat); break;
                        case 2:
                                cuda_asum_int<  2><<<BLOCK_SIZE,THREAD_SIZE,2*sizeof(int)>>>(d_idat,d_idat); break;
                        case 1:
                                cuda_asum_int<  1><<<BLOCK_SIZE,THREAD_SIZE,1*sizeof(int)>>>(d_idat,d_idat); break;
			}
		//cuda_asum_int<<<BLOCK_SIZE,THREAD_SIZE,512*sizeof(int)>>>(d_idat,d_idat);
		FINAL_THREAD = BLOCK_SIZE;
		BLOCK_SIZE = BLOCK_SIZE/512;
	}
        } else {
                FINAL_THREAD = (unsigned int)N_elem;
        }

	THREAD_SIZE = FINAL_THREAD/2;
	BLOCK_SIZE = 1;
        //RUN REDUCTIONS
        switch (THREAD_SIZE)
        	{
                case 512:
                	cuda_asum_int<512><<<BLOCK_SIZE,THREAD_SIZE,512*sizeof(int)>>>(d_idat,d_idat); break;
                case 256:
                        cuda_asum_int<256><<<BLOCK_SIZE,THREAD_SIZE,256*sizeof(int)>>>(d_idat,d_idat); break;
                case 128:
                        cuda_asum_int<128><<<BLOCK_SIZE,THREAD_SIZE,128*sizeof(int)>>>(d_idat,d_idat); break;
                case 64:
                        cuda_asum_int< 64><<<BLOCK_SIZE,THREAD_SIZE,64*sizeof(int)>>>(d_idat,d_idat); break;
                case 32:
                        cuda_asum_int< 32><<<BLOCK_SIZE,THREAD_SIZE,32*sizeof(int)>>>(d_idat,d_idat); break;
                case 16:
                        cuda_asum_int< 16><<<BLOCK_SIZE,THREAD_SIZE,16*sizeof(int)>>>(d_idat,d_idat); break;
                case 8:
                        cuda_asum_int<  8><<<BLOCK_SIZE,THREAD_SIZE,8*sizeof(int)>>>(d_idat,d_idat); break;
                case 4:
                        cuda_asum_int<  4><<<BLOCK_SIZE,THREAD_SIZE,4*sizeof(int)>>>(d_idat,d_idat); break;
                case 2:
                        cuda_asum_int<  2><<<BLOCK_SIZE,THREAD_SIZE,2*sizeof(int)>>>(d_idat,d_idat); break;
                case 1:
                        cuda_asum_int<  1><<<BLOCK_SIZE,THREAD_SIZE,1*sizeof(int)>>>(d_idat,d_idat); break;
                }

}

// ********************************************************************* //
// ************************FLOAT ARRAY SUMMATION************************ //
// ********************************************************************* //

// ****************************************** //
// ****FLOATS DEVICE SIDE KERNEL PROGRAM***** //
// ****************************************** //
template <unsigned int blockSizeflt>
__global__ void cuda_asum_flt(float *d_idat, float *d_odat)
{
        extern __shared__ float sdataf[];

        //LOAD ELEMENT FROM GLOBAL TO SHARED MEM
        unsigned int tid = threadIdx.x;
        unsigned int i = blockIdx.x * (blockDim.x * 2) + tid;

        sdataf[tid] = d_idat[i] + d_idat[i + blockDim.x];
        __syncthreads();

        //REDUCTION
        if (blockSizeflt >= 1024)
        {
                if (tid < 512) {sdataf[tid] += sdataf[tid + 512];} __syncthreads();
        }
        if (blockSizeflt >= 512)
        {
                if (tid < 256) {sdataf[tid] += sdataf[tid + 256];} __syncthreads();
        }	
        if (blockSizeflt >= 256)
        {
                if (tid < 128) {sdataf[tid] += sdataf[tid + 128];} __syncthreads();
        }

        if (tid < 64)
        {
		if (blockSizeflt >= 128) sdataf[tid] += sdataf[tid + 64];__syncthreads();
                if (blockSizeflt >= 64) sdataf[tid] += sdataf[tid + 32];__syncthreads();
                if (blockSizeflt >= 32) sdataf[tid] += sdataf[tid + 16];__syncthreads();
                if (blockSizeflt >= 16) sdataf[tid] += sdataf[tid + 8];__syncthreads();
                if (blockSizeflt >= 8) sdataf[tid] += sdataf[tid + 4];__syncthreads();
                if (blockSizeflt >= 4) sdataf[tid] += sdataf[tid + 2];__syncthreads();
		if (blockSizeflt >= 2) sdataf[tid] += sdataf[tid + 1];__syncthreads();
        }
        //WRITE RESULT TO GLOB MEM
        if(tid == 0) d_odat[blockIdx.x] = sdataf[0];
}

// ****************************************** //
// **FLOATS HOST SIDE KERNEL CALLER PROGRAM** //
// ****************************************** //

//DEVICE ARRAY (d_idat) NEEDS TO BE DEFINED IN PARENT PROGRAM
extern void cuda_asum_fltm(float *d_idat, int N_elem,int MAX_THREADS) //sqrt(N_elem) must be an int
{
	
        //THREAD AND BLOCK SIZES
        unsigned int THREAD_SIZE = MAX_THREADS;
        unsigned int BLOCK_SIZE = N_elem/(MAX_THREADS*2);
        unsigned int FINAL_THREAD;

        if (N_elem > THREAD_SIZE)
        {
        	//SUM THE ARRAY THROUGH MULTIPLE KERNEL CALLS
        	while(BLOCK_SIZE > 1)
        	{
        	        //RUN REDUCTIONS
        	        switch (THREAD_SIZE)
        	                {
        	                case 1024:
        	                        cuda_asum_flt<1024><<<BLOCK_SIZE,THREAD_SIZE,1024*sizeof(int)>>>(d_idat,d_idat); break;
				case 512:
        	                        cuda_asum_flt<512><<<BLOCK_SIZE,THREAD_SIZE,512*sizeof(int)>>>(d_idat,d_idat); break;
        	                case 256:
        	                        cuda_asum_flt<256><<<BLOCK_SIZE,THREAD_SIZE,256*sizeof(int)>>>(d_idat,d_idat); break;
        	                case 128:
        	                        cuda_asum_flt<128><<<BLOCK_SIZE,THREAD_SIZE,128*sizeof(int)>>>(d_idat,d_idat); break;
        	                case 64:
        	                        cuda_asum_flt< 64><<<BLOCK_SIZE,THREAD_SIZE,64*sizeof(int)>>>(d_idat,d_idat); break;
        	                case 32:
        	                        cuda_asum_flt< 32><<<BLOCK_SIZE,THREAD_SIZE,32*sizeof(int)>>>(d_idat,d_idat); break;
        	                case 16:
        	                        cuda_asum_flt< 16><<<BLOCK_SIZE,THREAD_SIZE,16*sizeof(int)>>>(d_idat,d_idat); break;
        	                case 8:
        	                        cuda_asum_flt<  8><<<BLOCK_SIZE,THREAD_SIZE,8*sizeof(int)>>>(d_idat,d_idat); break;
        	                case 4:
        	                        cuda_asum_flt<  4><<<BLOCK_SIZE,THREAD_SIZE,4*sizeof(int)>>>(d_idat,d_idat); break;
        	                case 2:
        	                        cuda_asum_flt<  2><<<BLOCK_SIZE,THREAD_SIZE,2*sizeof(int)>>>(d_idat,d_idat); break;
        	                case 1:
        	                        cuda_asum_flt<  1><<<BLOCK_SIZE,THREAD_SIZE,1*sizeof(int)>>>(d_idat,d_idat); break;
        	                }
        	        FINAL_THREAD = BLOCK_SIZE;
        	        BLOCK_SIZE = BLOCK_SIZE/1024;
        	}
	} else {
		FINAL_THREAD = (unsigned int)N_elem/2;
	}
        THREAD_SIZE = FINAL_THREAD/2;
        BLOCK_SIZE = 1;
        //RUN REDUCTIONS
        switch (THREAD_SIZE)
                {
                case 1024:
                        cuda_asum_flt<1024><<<BLOCK_SIZE,THREAD_SIZE,1024*sizeof(int)>>>(d_idat,d_idat); break;
                case 512:
                        cuda_asum_flt<512><<<BLOCK_SIZE,THREAD_SIZE,512*sizeof(int)>>>(d_idat,d_idat); break;
                case 256:
                        cuda_asum_flt<256><<<BLOCK_SIZE,THREAD_SIZE,256*sizeof(int)>>>(d_idat,d_idat); break;
                case 128:
                        cuda_asum_flt<128><<<BLOCK_SIZE,THREAD_SIZE,128*sizeof(int)>>>(d_idat,d_idat); break;
                case 64:
                        cuda_asum_flt< 64><<<BLOCK_SIZE,THREAD_SIZE,64*sizeof(int)>>>(d_idat,d_idat); break;
                case 32:
                        cuda_asum_flt< 32><<<BLOCK_SIZE,THREAD_SIZE,32*sizeof(int)>>>(d_idat,d_idat); break;
                case 16:
                        cuda_asum_flt< 16><<<BLOCK_SIZE,THREAD_SIZE,16*sizeof(int)>>>(d_idat,d_idat); break;
                case 8:
                        cuda_asum_flt< 8><<<BLOCK_SIZE,THREAD_SIZE,8*sizeof(int)>>>(d_idat,d_idat); break;
                case 4:
                        cuda_asum_flt<  4><<<BLOCK_SIZE,THREAD_SIZE,4*sizeof(int)>>>(d_idat,d_idat); break;
                case 2:
                        cuda_asum_flt<  2><<<BLOCK_SIZE,THREAD_SIZE,2*sizeof(int)>>>(d_idat,d_idat); break;
                case 1:
                        cuda_asum_flt<  1><<<BLOCK_SIZE,THREAD_SIZE,1*sizeof(int)>>>(d_idat,d_idat); break;
                }
}

// ********************************************************************* //
// ***********************DOUBLE ARRAY SUMMATION************************ //
// ********************************************************************* //

// ****************************************** //
// ****DOUBLES DEVICE SIDE KERNEL PROGRAM**** //
// ****************************************** //

template <unsigned int blockSizedoub>
__global__ void cuda_asum_doub(double *d_idat, double *d_odat)
{
        extern __shared__ double sdatad[];

        //LOAD ELEMENT FROM GLOBAL TO SHARED MEM
        unsigned int tid = threadIdx.x;
        unsigned int i = blockIdx.x * (blockDim.x * 2) + tid;

        sdatad[tid] = d_idat[i] + d_idat[i + blockDim.x];
        __syncthreads();

        //REDUCTION
        if (blockSizedoub >= 512)
        {
                if (tid < 256) {sdatad[tid] += sdatad[tid + 256];} __syncthreads();
        }
        if (blockSizedoub >= 256)
        {
                if (tid < 128) {sdatad[tid] += sdatad[tid + 128];} __syncthreads();
        }
        if (blockSizedoub >= 128)
        {
                if (tid < 64) {sdatad[tid] += sdatad[tid + 64];} __syncthreads();
        }

        if (tid < 32)
        {
                if (blockSizedoub >= 64) sdatad[tid] += sdatad[tid + 32];
                if (blockSizedoub >= 32) sdatad[tid] += sdatad[tid + 16];
                if (blockSizedoub >= 16) sdatad[tid] += sdatad[tid + 8];
                if (blockSizedoub >= 8) sdatad[tid] += sdatad[tid + 4];
                if (blockSizedoub >= 4) sdatad[tid] += sdatad[tid + 2];
                if (blockSizedoub >= 2) sdatad[tid] += sdatad[tid + 1];
        }

        //WRITE RESULT TO GLOB MEM
        if(tid == 0) d_odat[blockIdx.x] = sdatad[0];
}

// ****************************************** //
// *DOUBLES HOST SIDE KERNEL CALLER PROGRAM** //
// ****************************************** //

//DEVICE ARRAY (d_idat) NEEDS TO BE DEFINED IN PARENT PROGRAM
extern void cuda_asum_doubm(double *d_idat, double N_elem) //sqrt(N_elem) must be an int
{

        //THREAD AND BLOCK SIZES
        unsigned int THREAD_SIZE = 512/2;
        unsigned int BLOCK_SIZE = N_elem/512;
        unsigned int FINAL_THREAD;

        if (N_elem > 512)
        {
        	//SUM THE ARRAY THROUGH MULTIPLE KERNEL CALLS
        	while(BLOCK_SIZE > 1)
        	{
        	        //RUN REDUCTIONS
        	        switch (THREAD_SIZE)
        	                {
        	                case 512:
               		                cuda_asum_doub<512><<<BLOCK_SIZE,THREAD_SIZE,512*sizeof(double)>>>(d_idat,d_idat); break;
                	        case 256:
                	                cuda_asum_doub<256><<<BLOCK_SIZE,THREAD_SIZE,256*sizeof(double)>>>(d_idat,d_idat); break;
                	        case 128:
                	                cuda_asum_doub<128><<<BLOCK_SIZE,THREAD_SIZE,128*sizeof(double)>>>(d_idat,d_idat); break;
                	        case 64:
                	                cuda_asum_doub< 64><<<BLOCK_SIZE,THREAD_SIZE,64*sizeof(double)>>>(d_idat,d_idat); break;
                	        case 32:
                	                cuda_asum_doub< 32><<<BLOCK_SIZE,THREAD_SIZE,32*sizeof(double)>>>(d_idat,d_idat); break;
                	        case 16:
                	                cuda_asum_doub< 16><<<BLOCK_SIZE,THREAD_SIZE,16*sizeof(double)>>>(d_idat,d_idat); break;
                	        case 8:
                	                cuda_asum_doub<  8><<<BLOCK_SIZE,THREAD_SIZE,8*sizeof(double)>>>(d_idat,d_idat); break;
                	        case 4:
                	                cuda_asum_doub<  4><<<BLOCK_SIZE,THREAD_SIZE,4*sizeof(double)>>>(d_idat,d_idat); break;
                	        case 2:
                	                cuda_asum_doub<  2><<<BLOCK_SIZE,THREAD_SIZE,2*sizeof(double)>>>(d_idat,d_idat); break;
                	        case 1:
                	                cuda_asum_doub<  1><<<BLOCK_SIZE,THREAD_SIZE,1*sizeof(double)>>>(d_idat,d_idat); break;
                	        }
                	//cuda_asum_int<<<BLOCK_SIZE,THREAD_SIZE,512*sizeof(int)>>>(d_idat,d_idat);
                	FINAL_THREAD = BLOCK_SIZE;
                	BLOCK_SIZE = BLOCK_SIZE/512;
        	}
        } else {
                FINAL_THREAD = (unsigned int)N_elem;
        }

	// THIS SECTION BEGINS WITH THREADS NEEDED ARE LESS THAN MAXIMUM BLOCK SIZE
        THREAD_SIZE = FINAL_THREAD/2;
        BLOCK_SIZE = 1;
        //RUN REDUCTIONS
        switch (THREAD_SIZE)
                {
                case 512:
                        cuda_asum_doub<512><<<BLOCK_SIZE,THREAD_SIZE,512*sizeof(double)>>>(d_idat,d_idat); break;
                case 256:
                        cuda_asum_doub<256><<<BLOCK_SIZE,THREAD_SIZE,256*sizeof(double)>>>(d_idat,d_idat); break;
                case 128:
                        cuda_asum_doub<128><<<BLOCK_SIZE,THREAD_SIZE,128*sizeof(double)>>>(d_idat,d_idat); break;
                case 64:
                        cuda_asum_doub< 64><<<BLOCK_SIZE,THREAD_SIZE,64*sizeof(double)>>>(d_idat,d_idat); break;
                case 32:
                        cuda_asum_doub< 32><<<BLOCK_SIZE,THREAD_SIZE,32*sizeof(double)>>>(d_idat,d_idat); break;
                case 16:
                        cuda_asum_doub< 16><<<BLOCK_SIZE,THREAD_SIZE,16*sizeof(double)>>>(d_idat,d_idat); break;
                case 8:
                        cuda_asum_doub<  8><<<BLOCK_SIZE,THREAD_SIZE,8*sizeof(double)>>>(d_idat,d_idat); break;
                case 4:
                        cuda_asum_doub<  4><<<BLOCK_SIZE,THREAD_SIZE,4*sizeof(double)>>>(d_idat,d_idat); break;
                case 2:
                        cuda_asum_doub<  2><<<BLOCK_SIZE,THREAD_SIZE,2*sizeof(double)>>>(d_idat,d_idat); break;
                case 1:
                        cuda_asum_doub<  1><<<BLOCK_SIZE,THREAD_SIZE,1*sizeof(double)>>>(d_idat,d_idat); break;
                }

}


	.text
	.file	"cuda_reduction.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z14cuda_asum_intmPii           # -- Begin function _Z14cuda_asum_intmPii
	.type	_Z14cuda_asum_intmPii,@function
_Z14cuda_asum_intmPii:                  # @_Z14cuda_asum_intmPii
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%esi, %ebp
	movq	%rdi, %rbx
	cmpl	$513, %esi                      # imm = 0x201
	jl	.LBB0_1
# %bb.2:                                # %.preheader
	cmpl	$1024, %ebp                     # imm = 0x400
	jb	.LBB0_36
# %bb.3:                                # %.lr.ph.preheader
	movabsq	$4294967297, %r12               # imm = 0x100000001
	leaq	255(%r12), %r14
	movl	%ebp, %r15d
.LBB0_4:                                # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	shrl	$9, %r15d
	leaq	(%r12,%r15), %rdi
	decq	%rdi
	movl	$1024, %r8d                     # imm = 0x400
	movl	$1, %esi
	movq	%r14, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB0_6
# %bb.5:                                #   in Loop: Header=BB0_4 Depth=1
	movq	%rbx, %rdi
	movq	%rbx, %rsi
	callq	_Z28__device_stub__cuda_asum_intILj256EEvPiS0_
.LBB0_6:                                #   in Loop: Header=BB0_4 Depth=1
	cmpl	$524287, %ebp                   # imm = 0x7FFFF
	movl	%r15d, %ebp
	ja	.LBB0_4
	jmp	.LBB0_7
.LBB0_1:
	movl	%ebp, %r15d
.LBB0_7:                                # %.loopexit
	shrl	%r15d
	cmpl	$31, %r15d
	jg	.LBB0_13
# %bb.8:                                # %.loopexit
	leal	-1(%r15), %eax
	cmpl	$7, %eax
	ja	.LBB0_9
# %bb.12:                               # %.loopexit
	jmpq	*.LJTI0_0(,%rax,8)
.LBB0_35:
	movabsq	$4294967297, %rdi               # imm = 0x100000001
	movl	$4, %r8d
	movl	$1, %esi
	movq	%rdi, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB0_36
# %bb.37:
	movq	%rbx, %rdi
	movq	%rbx, %rsi
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z28__device_stub__cuda_asum_intILj1EEvPiS0_ # TAILCALL
.LBB0_13:                               # %.loopexit
	.cfi_def_cfa_offset 48
	cmpl	$127, %r15d
	jle	.LBB0_14
# %bb.18:                               # %.loopexit
	cmpl	$128, %r15d
	je	.LBB0_25
# %bb.19:                               # %.loopexit
	cmpl	$256, %r15d                     # imm = 0x100
	je	.LBB0_23
# %bb.20:                               # %.loopexit
	cmpl	$512, %r15d                     # imm = 0x200
	jne	.LBB0_36
# %bb.21:
	movabsq	$4294967297, %rdi               # imm = 0x100000001
	leaq	511(%rdi), %rdx
	movl	$2048, %r8d                     # imm = 0x800
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB0_36
# %bb.22:
	movq	%rbx, %rdi
	movq	%rbx, %rsi
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z28__device_stub__cuda_asum_intILj512EEvPiS0_ # TAILCALL
.LBB0_14:                               # %.loopexit
	.cfi_def_cfa_offset 48
	cmpl	$32, %r15d
	je	.LBB0_27
# %bb.15:                               # %.loopexit
	cmpl	$64, %r15d
	jne	.LBB0_36
# %bb.16:
	movabsq	$4294967297, %rdi               # imm = 0x100000001
	leaq	63(%rdi), %rdx
	movl	$256, %r8d                      # imm = 0x100
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB0_36
# %bb.17:
	movq	%rbx, %rdi
	movq	%rbx, %rsi
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z28__device_stub__cuda_asum_intILj64EEvPiS0_ # TAILCALL
.LBB0_9:                                # %.loopexit
	.cfi_def_cfa_offset 48
	cmpl	$16, %r15d
	jne	.LBB0_36
# %bb.10:
	movabsq	$4294967297, %rdi               # imm = 0x100000001
	leaq	15(%rdi), %rdx
	movl	$64, %r8d
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB0_36
# %bb.11:
	movq	%rbx, %rdi
	movq	%rbx, %rsi
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z28__device_stub__cuda_asum_intILj16EEvPiS0_ # TAILCALL
.LBB0_31:
	.cfi_def_cfa_offset 48
	movabsq	$4294967297, %rdi               # imm = 0x100000001
	leaq	3(%rdi), %rdx
	movl	$16, %r8d
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB0_36
# %bb.32:
	movq	%rbx, %rdi
	movq	%rbx, %rsi
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z28__device_stub__cuda_asum_intILj4EEvPiS0_ # TAILCALL
.LBB0_33:
	.cfi_def_cfa_offset 48
	movabsq	$4294967297, %rdi               # imm = 0x100000001
	leaq	1(%rdi), %rdx
	movl	$8, %r8d
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB0_36
# %bb.34:
	movq	%rbx, %rdi
	movq	%rbx, %rsi
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z28__device_stub__cuda_asum_intILj2EEvPiS0_ # TAILCALL
.LBB0_29:
	.cfi_def_cfa_offset 48
	movabsq	$4294967297, %rdi               # imm = 0x100000001
	leaq	7(%rdi), %rdx
	movl	$32, %r8d
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB0_36
# %bb.30:
	movq	%rbx, %rdi
	movq	%rbx, %rsi
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z28__device_stub__cuda_asum_intILj8EEvPiS0_ # TAILCALL
.LBB0_27:
	.cfi_def_cfa_offset 48
	movabsq	$4294967297, %rdi               # imm = 0x100000001
	leaq	31(%rdi), %rdx
	movl	$128, %r8d
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB0_36
# %bb.28:
	movq	%rbx, %rdi
	movq	%rbx, %rsi
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z28__device_stub__cuda_asum_intILj32EEvPiS0_ # TAILCALL
.LBB0_25:
	.cfi_def_cfa_offset 48
	movabsq	$4294967297, %rdi               # imm = 0x100000001
	leaq	127(%rdi), %rdx
	movl	$512, %r8d                      # imm = 0x200
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB0_36
# %bb.26:
	movq	%rbx, %rdi
	movq	%rbx, %rsi
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z28__device_stub__cuda_asum_intILj128EEvPiS0_ # TAILCALL
.LBB0_23:
	.cfi_def_cfa_offset 48
	movabsq	$4294967297, %rdi               # imm = 0x100000001
	leaq	255(%rdi), %rdx
	movl	$1024, %r8d                     # imm = 0x400
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	je	.LBB0_24
.LBB0_36:                               # %.loopexit.thread
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB0_24:
	.cfi_def_cfa_offset 48
	movq	%rbx, %rdi
	movq	%rbx, %rsi
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z28__device_stub__cuda_asum_intILj256EEvPiS0_ # TAILCALL
.Lfunc_end0:
	.size	_Z14cuda_asum_intmPii, .Lfunc_end0-_Z14cuda_asum_intmPii
	.cfi_endproc
	.section	.rodata,"a",@progbits
	.p2align	3, 0x0
.LJTI0_0:
	.quad	.LBB0_35
	.quad	.LBB0_33
	.quad	.LBB0_36
	.quad	.LBB0_31
	.quad	.LBB0_36
	.quad	.LBB0_36
	.quad	.LBB0_36
	.quad	.LBB0_29
                                        # -- End function
	.section	.text._Z28__device_stub__cuda_asum_intILj512EEvPiS0_,"axG",@progbits,_Z28__device_stub__cuda_asum_intILj512EEvPiS0_,comdat
	.weak	_Z28__device_stub__cuda_asum_intILj512EEvPiS0_ # -- Begin function _Z28__device_stub__cuda_asum_intILj512EEvPiS0_
	.type	_Z28__device_stub__cuda_asum_intILj512EEvPiS0_,@function
_Z28__device_stub__cuda_asum_intILj512EEvPiS0_: # @_Z28__device_stub__cuda_asum_intILj512EEvPiS0_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	16(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z13cuda_asum_intILj512EEvPiS0_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z28__device_stub__cuda_asum_intILj512EEvPiS0_, .Lfunc_end1-_Z28__device_stub__cuda_asum_intILj512EEvPiS0_
	.cfi_endproc
                                        # -- End function
	.section	.text._Z28__device_stub__cuda_asum_intILj256EEvPiS0_,"axG",@progbits,_Z28__device_stub__cuda_asum_intILj256EEvPiS0_,comdat
	.weak	_Z28__device_stub__cuda_asum_intILj256EEvPiS0_ # -- Begin function _Z28__device_stub__cuda_asum_intILj256EEvPiS0_
	.type	_Z28__device_stub__cuda_asum_intILj256EEvPiS0_,@function
_Z28__device_stub__cuda_asum_intILj256EEvPiS0_: # @_Z28__device_stub__cuda_asum_intILj256EEvPiS0_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	16(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z13cuda_asum_intILj256EEvPiS0_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z28__device_stub__cuda_asum_intILj256EEvPiS0_, .Lfunc_end2-_Z28__device_stub__cuda_asum_intILj256EEvPiS0_
	.cfi_endproc
                                        # -- End function
	.section	.text._Z28__device_stub__cuda_asum_intILj128EEvPiS0_,"axG",@progbits,_Z28__device_stub__cuda_asum_intILj128EEvPiS0_,comdat
	.weak	_Z28__device_stub__cuda_asum_intILj128EEvPiS0_ # -- Begin function _Z28__device_stub__cuda_asum_intILj128EEvPiS0_
	.type	_Z28__device_stub__cuda_asum_intILj128EEvPiS0_,@function
_Z28__device_stub__cuda_asum_intILj128EEvPiS0_: # @_Z28__device_stub__cuda_asum_intILj128EEvPiS0_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	16(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z13cuda_asum_intILj128EEvPiS0_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	_Z28__device_stub__cuda_asum_intILj128EEvPiS0_, .Lfunc_end3-_Z28__device_stub__cuda_asum_intILj128EEvPiS0_
	.cfi_endproc
                                        # -- End function
	.section	.text._Z28__device_stub__cuda_asum_intILj64EEvPiS0_,"axG",@progbits,_Z28__device_stub__cuda_asum_intILj64EEvPiS0_,comdat
	.weak	_Z28__device_stub__cuda_asum_intILj64EEvPiS0_ # -- Begin function _Z28__device_stub__cuda_asum_intILj64EEvPiS0_
	.type	_Z28__device_stub__cuda_asum_intILj64EEvPiS0_,@function
_Z28__device_stub__cuda_asum_intILj64EEvPiS0_: # @_Z28__device_stub__cuda_asum_intILj64EEvPiS0_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	16(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z13cuda_asum_intILj64EEvPiS0_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end4:
	.size	_Z28__device_stub__cuda_asum_intILj64EEvPiS0_, .Lfunc_end4-_Z28__device_stub__cuda_asum_intILj64EEvPiS0_
	.cfi_endproc
                                        # -- End function
	.section	.text._Z28__device_stub__cuda_asum_intILj32EEvPiS0_,"axG",@progbits,_Z28__device_stub__cuda_asum_intILj32EEvPiS0_,comdat
	.weak	_Z28__device_stub__cuda_asum_intILj32EEvPiS0_ # -- Begin function _Z28__device_stub__cuda_asum_intILj32EEvPiS0_
	.type	_Z28__device_stub__cuda_asum_intILj32EEvPiS0_,@function
_Z28__device_stub__cuda_asum_intILj32EEvPiS0_: # @_Z28__device_stub__cuda_asum_intILj32EEvPiS0_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	16(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z13cuda_asum_intILj32EEvPiS0_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end5:
	.size	_Z28__device_stub__cuda_asum_intILj32EEvPiS0_, .Lfunc_end5-_Z28__device_stub__cuda_asum_intILj32EEvPiS0_
	.cfi_endproc
                                        # -- End function
	.section	.text._Z28__device_stub__cuda_asum_intILj16EEvPiS0_,"axG",@progbits,_Z28__device_stub__cuda_asum_intILj16EEvPiS0_,comdat
	.weak	_Z28__device_stub__cuda_asum_intILj16EEvPiS0_ # -- Begin function _Z28__device_stub__cuda_asum_intILj16EEvPiS0_
	.type	_Z28__device_stub__cuda_asum_intILj16EEvPiS0_,@function
_Z28__device_stub__cuda_asum_intILj16EEvPiS0_: # @_Z28__device_stub__cuda_asum_intILj16EEvPiS0_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	16(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z13cuda_asum_intILj16EEvPiS0_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end6:
	.size	_Z28__device_stub__cuda_asum_intILj16EEvPiS0_, .Lfunc_end6-_Z28__device_stub__cuda_asum_intILj16EEvPiS0_
	.cfi_endproc
                                        # -- End function
	.section	.text._Z28__device_stub__cuda_asum_intILj8EEvPiS0_,"axG",@progbits,_Z28__device_stub__cuda_asum_intILj8EEvPiS0_,comdat
	.weak	_Z28__device_stub__cuda_asum_intILj8EEvPiS0_ # -- Begin function _Z28__device_stub__cuda_asum_intILj8EEvPiS0_
	.type	_Z28__device_stub__cuda_asum_intILj8EEvPiS0_,@function
_Z28__device_stub__cuda_asum_intILj8EEvPiS0_: # @_Z28__device_stub__cuda_asum_intILj8EEvPiS0_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	16(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z13cuda_asum_intILj8EEvPiS0_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end7:
	.size	_Z28__device_stub__cuda_asum_intILj8EEvPiS0_, .Lfunc_end7-_Z28__device_stub__cuda_asum_intILj8EEvPiS0_
	.cfi_endproc
                                        # -- End function
	.section	.text._Z28__device_stub__cuda_asum_intILj4EEvPiS0_,"axG",@progbits,_Z28__device_stub__cuda_asum_intILj4EEvPiS0_,comdat
	.weak	_Z28__device_stub__cuda_asum_intILj4EEvPiS0_ # -- Begin function _Z28__device_stub__cuda_asum_intILj4EEvPiS0_
	.type	_Z28__device_stub__cuda_asum_intILj4EEvPiS0_,@function
_Z28__device_stub__cuda_asum_intILj4EEvPiS0_: # @_Z28__device_stub__cuda_asum_intILj4EEvPiS0_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	16(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z13cuda_asum_intILj4EEvPiS0_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end8:
	.size	_Z28__device_stub__cuda_asum_intILj4EEvPiS0_, .Lfunc_end8-_Z28__device_stub__cuda_asum_intILj4EEvPiS0_
	.cfi_endproc
                                        # -- End function
	.section	.text._Z28__device_stub__cuda_asum_intILj2EEvPiS0_,"axG",@progbits,_Z28__device_stub__cuda_asum_intILj2EEvPiS0_,comdat
	.weak	_Z28__device_stub__cuda_asum_intILj2EEvPiS0_ # -- Begin function _Z28__device_stub__cuda_asum_intILj2EEvPiS0_
	.type	_Z28__device_stub__cuda_asum_intILj2EEvPiS0_,@function
_Z28__device_stub__cuda_asum_intILj2EEvPiS0_: # @_Z28__device_stub__cuda_asum_intILj2EEvPiS0_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	16(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z13cuda_asum_intILj2EEvPiS0_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end9:
	.size	_Z28__device_stub__cuda_asum_intILj2EEvPiS0_, .Lfunc_end9-_Z28__device_stub__cuda_asum_intILj2EEvPiS0_
	.cfi_endproc
                                        # -- End function
	.section	.text._Z28__device_stub__cuda_asum_intILj1EEvPiS0_,"axG",@progbits,_Z28__device_stub__cuda_asum_intILj1EEvPiS0_,comdat
	.weak	_Z28__device_stub__cuda_asum_intILj1EEvPiS0_ # -- Begin function _Z28__device_stub__cuda_asum_intILj1EEvPiS0_
	.type	_Z28__device_stub__cuda_asum_intILj1EEvPiS0_,@function
_Z28__device_stub__cuda_asum_intILj1EEvPiS0_: # @_Z28__device_stub__cuda_asum_intILj1EEvPiS0_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	16(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z13cuda_asum_intILj1EEvPiS0_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end10:
	.size	_Z28__device_stub__cuda_asum_intILj1EEvPiS0_, .Lfunc_end10-_Z28__device_stub__cuda_asum_intILj1EEvPiS0_
	.cfi_endproc
                                        # -- End function
	.text
	.globl	_Z14cuda_asum_fltmPfii          # -- Begin function _Z14cuda_asum_fltmPfii
	.type	_Z14cuda_asum_fltmPfii,@function
_Z14cuda_asum_fltmPfii:                 # @_Z14cuda_asum_fltmPfii
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$72, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%esi, %r14d
	movq	%rdi, %rbx
	cmpl	%edx, %esi
	jbe	.LBB11_36
# %bb.1:                                # %.preheader
	movl	%edx, %r15d
	leal	(%r15,%r15), %ecx
	movl	%r14d, %eax
	cltd
	idivl	%ecx
	cmpl	$2, %eax
	jb	.LBB11_68
# %bb.2:                                # %.lr.ph.preheader
	movabsq	$4294967297, %r12               # imm = 0x100000001
	leal	-1(%r15), %ebp
	leaq	15(%r12), %rcx
	movq	%rcx, 8(%rsp)                   # 8-byte Spill
	leaq	31(%r12), %rcx
	movq	%rcx, (%rsp)                    # 8-byte Spill
	leaq	1(%r12), %rcx
	movq	%rcx, 64(%rsp)                  # 8-byte Spill
	leaq	3(%r12), %rcx
	movq	%rcx, 56(%rsp)                  # 8-byte Spill
	leaq	7(%r12), %r13
	leaq	63(%r12), %rcx
	movq	%rcx, 48(%rsp)                  # 8-byte Spill
	leaq	127(%r12), %rcx
	movq	%rcx, 40(%rsp)                  # 8-byte Spill
	leaq	255(%r12), %rcx
	movq	%rcx, 32(%rsp)                  # 8-byte Spill
	leaq	511(%r12), %rcx
	movq	%rcx, 24(%rsp)                  # 8-byte Spill
	leaq	1023(%r12), %rcx
	movq	%rcx, 16(%rsp)                  # 8-byte Spill
.LBB11_3:                               # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	movl	%eax, %r14d
	cmpl	$63, %r15d
	jg	.LBB11_9
# %bb.4:                                # %.lr.ph
                                        #   in Loop: Header=BB11_3 Depth=1
	cmpl	$7, %ebp
	ja	.LBB11_5
# %bb.69:                               # %.lr.ph
                                        #   in Loop: Header=BB11_3 Depth=1
	jmpq	*.LJTI11_0(,%rbp,8)
.LBB11_33:                              #   in Loop: Header=BB11_3 Depth=1
	movl	%r14d, %eax
	leaq	(%r12,%rax), %rdi
	decq	%rdi
	movl	$4, %r8d
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB11_35
# %bb.34:                               #   in Loop: Header=BB11_3 Depth=1
	movq	%rbx, %rdi
	movq	%rbx, %rsi
	callq	_Z28__device_stub__cuda_asum_fltILj1EEvPfS0_
	jmp	.LBB11_35
.LBB11_9:                               # %.lr.ph
                                        #   in Loop: Header=BB11_3 Depth=1
	cmpl	$255, %r15d
	jle	.LBB11_10
# %bb.14:                               # %.lr.ph
                                        #   in Loop: Header=BB11_3 Depth=1
	cmpl	$256, %r15d                     # imm = 0x100
	je	.LBB11_21
# %bb.15:                               # %.lr.ph
                                        #   in Loop: Header=BB11_3 Depth=1
	cmpl	$512, %r15d                     # imm = 0x200
	je	.LBB11_19
# %bb.16:                               # %.lr.ph
                                        #   in Loop: Header=BB11_3 Depth=1
	cmpl	$1024, %r15d                    # imm = 0x400
	jne	.LBB11_35
# %bb.17:                               #   in Loop: Header=BB11_3 Depth=1
	movl	%r14d, %eax
	leaq	(%r12,%rax), %rdi
	decq	%rdi
	movl	$4096, %r8d                     # imm = 0x1000
	movl	$1, %esi
	movq	16(%rsp), %rdx                  # 8-byte Reload
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB11_35
# %bb.18:                               #   in Loop: Header=BB11_3 Depth=1
	movq	%rbx, %rdi
	movq	%rbx, %rsi
	callq	_Z28__device_stub__cuda_asum_fltILj1024EEvPfS0_
	jmp	.LBB11_35
.LBB11_5:                               # %.lr.ph
                                        #   in Loop: Header=BB11_3 Depth=1
	cmpl	$16, %r15d
	je	.LBB11_25
# %bb.6:                                # %.lr.ph
                                        #   in Loop: Header=BB11_3 Depth=1
	cmpl	$32, %r15d
	jne	.LBB11_35
# %bb.7:                                #   in Loop: Header=BB11_3 Depth=1
	movl	%r14d, %eax
	leaq	(%r12,%rax), %rdi
	decq	%rdi
	movl	$128, %r8d
	movl	$1, %esi
	movq	(%rsp), %rdx                    # 8-byte Reload
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB11_35
# %bb.8:                                #   in Loop: Header=BB11_3 Depth=1
	movq	%rbx, %rdi
	movq	%rbx, %rsi
	callq	_Z28__device_stub__cuda_asum_fltILj32EEvPfS0_
	jmp	.LBB11_35
.LBB11_10:                              # %.lr.ph
                                        #   in Loop: Header=BB11_3 Depth=1
	cmpl	$64, %r15d
	je	.LBB11_23
# %bb.11:                               # %.lr.ph
                                        #   in Loop: Header=BB11_3 Depth=1
	cmpl	$128, %r15d
	jne	.LBB11_35
# %bb.12:                               #   in Loop: Header=BB11_3 Depth=1
	movl	%r14d, %eax
	leaq	(%r12,%rax), %rdi
	decq	%rdi
	movl	$512, %r8d                      # imm = 0x200
	movl	$1, %esi
	movq	40(%rsp), %rdx                  # 8-byte Reload
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB11_35
# %bb.13:                               #   in Loop: Header=BB11_3 Depth=1
	movq	%rbx, %rdi
	movq	%rbx, %rsi
	callq	_Z28__device_stub__cuda_asum_fltILj128EEvPfS0_
	jmp	.LBB11_35
.LBB11_27:                              #   in Loop: Header=BB11_3 Depth=1
	movl	%r14d, %eax
	leaq	(%r12,%rax), %rdi
	decq	%rdi
	movl	$32, %r8d
	movl	$1, %esi
	movq	%r13, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB11_35
# %bb.28:                               #   in Loop: Header=BB11_3 Depth=1
	movq	%rbx, %rdi
	movq	%rbx, %rsi
	callq	_Z28__device_stub__cuda_asum_fltILj8EEvPfS0_
	jmp	.LBB11_35
.LBB11_31:                              #   in Loop: Header=BB11_3 Depth=1
	movl	%r14d, %eax
	leaq	(%r12,%rax), %rdi
	decq	%rdi
	movl	$8, %r8d
	movl	$1, %esi
	movq	64(%rsp), %rdx                  # 8-byte Reload
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB11_35
# %bb.32:                               #   in Loop: Header=BB11_3 Depth=1
	movq	%rbx, %rdi
	movq	%rbx, %rsi
	callq	_Z28__device_stub__cuda_asum_fltILj2EEvPfS0_
	jmp	.LBB11_35
.LBB11_29:                              #   in Loop: Header=BB11_3 Depth=1
	movl	%r14d, %eax
	leaq	(%r12,%rax), %rdi
	decq	%rdi
	movl	$16, %r8d
	movl	$1, %esi
	movq	56(%rsp), %rdx                  # 8-byte Reload
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB11_35
# %bb.30:                               #   in Loop: Header=BB11_3 Depth=1
	movq	%rbx, %rdi
	movq	%rbx, %rsi
	callq	_Z28__device_stub__cuda_asum_fltILj4EEvPfS0_
	jmp	.LBB11_35
.LBB11_23:                              #   in Loop: Header=BB11_3 Depth=1
	movl	%r14d, %eax
	leaq	(%r12,%rax), %rdi
	decq	%rdi
	movl	$256, %r8d                      # imm = 0x100
	movl	$1, %esi
	movq	48(%rsp), %rdx                  # 8-byte Reload
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB11_35
# %bb.24:                               #   in Loop: Header=BB11_3 Depth=1
	movq	%rbx, %rdi
	movq	%rbx, %rsi
	callq	_Z28__device_stub__cuda_asum_fltILj64EEvPfS0_
	jmp	.LBB11_35
.LBB11_19:                              #   in Loop: Header=BB11_3 Depth=1
	movl	%r14d, %eax
	leaq	(%r12,%rax), %rdi
	decq	%rdi
	movl	$2048, %r8d                     # imm = 0x800
	movl	$1, %esi
	movq	24(%rsp), %rdx                  # 8-byte Reload
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB11_35
# %bb.20:                               #   in Loop: Header=BB11_3 Depth=1
	movq	%rbx, %rdi
	movq	%rbx, %rsi
	callq	_Z28__device_stub__cuda_asum_fltILj512EEvPfS0_
	jmp	.LBB11_35
.LBB11_21:                              #   in Loop: Header=BB11_3 Depth=1
	movl	%r14d, %eax
	leaq	(%r12,%rax), %rdi
	decq	%rdi
	movl	$1024, %r8d                     # imm = 0x400
	movl	$1, %esi
	movq	32(%rsp), %rdx                  # 8-byte Reload
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB11_35
# %bb.22:                               #   in Loop: Header=BB11_3 Depth=1
	movq	%rbx, %rdi
	movq	%rbx, %rsi
	callq	_Z28__device_stub__cuda_asum_fltILj256EEvPfS0_
	jmp	.LBB11_35
.LBB11_25:                              #   in Loop: Header=BB11_3 Depth=1
	movl	%r14d, %eax
	leaq	(%r12,%rax), %rdi
	decq	%rdi
	movl	$64, %r8d
	movl	$1, %esi
	movq	8(%rsp), %rdx                   # 8-byte Reload
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB11_35
# %bb.26:                               #   in Loop: Header=BB11_3 Depth=1
	movq	%rbx, %rdi
	movq	%rbx, %rsi
	callq	_Z28__device_stub__cuda_asum_fltILj16EEvPfS0_
.LBB11_35:                              #   in Loop: Header=BB11_3 Depth=1
	movl	%r14d, %eax
	shrl	$10, %eax
	cmpl	$2047, %r14d                    # imm = 0x7FF
	ja	.LBB11_3
	jmp	.LBB11_37
.LBB11_36:
	shrl	%r14d
.LBB11_37:                              # %.loopexit
	shrl	%r14d
	cmpl	$63, %r14d
	jg	.LBB11_43
# %bb.38:                               # %.loopexit
	leal	-1(%r14), %eax
	cmpl	$7, %eax
	ja	.LBB11_39
# %bb.70:                               # %.loopexit
	jmpq	*.LJTI11_1(,%rax,8)
.LBB11_67:
	movabsq	$4294967297, %rdi               # imm = 0x100000001
	movl	$4, %r8d
	movl	$1, %esi
	movq	%rdi, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB11_68
# %bb.71:
	movq	%rbx, %rdi
	movq	%rbx, %rsi
	addq	$72, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z28__device_stub__cuda_asum_fltILj1EEvPfS0_ # TAILCALL
.LBB11_43:                              # %.loopexit
	.cfi_def_cfa_offset 128
	cmpl	$255, %r14d
	jle	.LBB11_44
# %bb.48:                               # %.loopexit
	cmpl	$256, %r14d                     # imm = 0x100
	je	.LBB11_55
# %bb.49:                               # %.loopexit
	cmpl	$512, %r14d                     # imm = 0x200
	je	.LBB11_53
# %bb.50:                               # %.loopexit
	cmpl	$1024, %r14d                    # imm = 0x400
	jne	.LBB11_68
# %bb.51:
	movabsq	$4294967297, %rdi               # imm = 0x100000001
	leaq	1023(%rdi), %rdx
	movl	$4096, %r8d                     # imm = 0x1000
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB11_68
# %bb.52:
	movq	%rbx, %rdi
	movq	%rbx, %rsi
	addq	$72, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z28__device_stub__cuda_asum_fltILj1024EEvPfS0_ # TAILCALL
.LBB11_39:                              # %.loopexit
	.cfi_def_cfa_offset 128
	cmpl	$16, %r14d
	je	.LBB11_59
# %bb.40:                               # %.loopexit
	cmpl	$32, %r14d
	jne	.LBB11_68
# %bb.41:
	movabsq	$4294967297, %rdi               # imm = 0x100000001
	leaq	31(%rdi), %rdx
	movl	$128, %r8d
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB11_68
# %bb.42:
	movq	%rbx, %rdi
	movq	%rbx, %rsi
	addq	$72, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z28__device_stub__cuda_asum_fltILj32EEvPfS0_ # TAILCALL
.LBB11_44:                              # %.loopexit
	.cfi_def_cfa_offset 128
	cmpl	$64, %r14d
	je	.LBB11_57
# %bb.45:                               # %.loopexit
	cmpl	$128, %r14d
	jne	.LBB11_68
# %bb.46:
	movabsq	$4294967297, %rdi               # imm = 0x100000001
	leaq	127(%rdi), %rdx
	movl	$512, %r8d                      # imm = 0x200
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB11_68
# %bb.47:
	movq	%rbx, %rdi
	movq	%rbx, %rsi
	addq	$72, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z28__device_stub__cuda_asum_fltILj128EEvPfS0_ # TAILCALL
.LBB11_61:
	.cfi_def_cfa_offset 128
	movabsq	$4294967297, %rdi               # imm = 0x100000001
	leaq	7(%rdi), %rdx
	movl	$32, %r8d
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB11_68
# %bb.62:
	movq	%rbx, %rdi
	movq	%rbx, %rsi
	addq	$72, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z28__device_stub__cuda_asum_fltILj8EEvPfS0_ # TAILCALL
.LBB11_65:
	.cfi_def_cfa_offset 128
	movabsq	$4294967297, %rdi               # imm = 0x100000001
	leaq	1(%rdi), %rdx
	movl	$8, %r8d
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB11_68
# %bb.66:
	movq	%rbx, %rdi
	movq	%rbx, %rsi
	addq	$72, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z28__device_stub__cuda_asum_fltILj2EEvPfS0_ # TAILCALL
.LBB11_63:
	.cfi_def_cfa_offset 128
	movabsq	$4294967297, %rdi               # imm = 0x100000001
	leaq	3(%rdi), %rdx
	movl	$16, %r8d
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB11_68
# %bb.64:
	movq	%rbx, %rdi
	movq	%rbx, %rsi
	addq	$72, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z28__device_stub__cuda_asum_fltILj4EEvPfS0_ # TAILCALL
.LBB11_57:
	.cfi_def_cfa_offset 128
	movabsq	$4294967297, %rdi               # imm = 0x100000001
	leaq	63(%rdi), %rdx
	movl	$256, %r8d                      # imm = 0x100
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB11_68
# %bb.58:
	movq	%rbx, %rdi
	movq	%rbx, %rsi
	addq	$72, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z28__device_stub__cuda_asum_fltILj64EEvPfS0_ # TAILCALL
.LBB11_53:
	.cfi_def_cfa_offset 128
	movabsq	$4294967297, %rdi               # imm = 0x100000001
	leaq	511(%rdi), %rdx
	movl	$2048, %r8d                     # imm = 0x800
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB11_68
# %bb.54:
	movq	%rbx, %rdi
	movq	%rbx, %rsi
	addq	$72, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z28__device_stub__cuda_asum_fltILj512EEvPfS0_ # TAILCALL
.LBB11_55:
	.cfi_def_cfa_offset 128
	movabsq	$4294967297, %rdi               # imm = 0x100000001
	leaq	255(%rdi), %rdx
	movl	$1024, %r8d                     # imm = 0x400
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB11_68
# %bb.56:
	movq	%rbx, %rdi
	movq	%rbx, %rsi
	addq	$72, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z28__device_stub__cuda_asum_fltILj256EEvPfS0_ # TAILCALL
.LBB11_59:
	.cfi_def_cfa_offset 128
	movabsq	$4294967297, %rdi               # imm = 0x100000001
	leaq	15(%rdi), %rdx
	movl	$64, %r8d
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	je	.LBB11_60
.LBB11_68:                              # %.loopexit.thread
	addq	$72, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB11_60:
	.cfi_def_cfa_offset 128
	movq	%rbx, %rdi
	movq	%rbx, %rsi
	addq	$72, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z28__device_stub__cuda_asum_fltILj16EEvPfS0_ # TAILCALL
.Lfunc_end11:
	.size	_Z14cuda_asum_fltmPfii, .Lfunc_end11-_Z14cuda_asum_fltmPfii
	.cfi_endproc
	.section	.rodata,"a",@progbits
	.p2align	3, 0x0
.LJTI11_0:
	.quad	.LBB11_33
	.quad	.LBB11_31
	.quad	.LBB11_35
	.quad	.LBB11_29
	.quad	.LBB11_35
	.quad	.LBB11_35
	.quad	.LBB11_35
	.quad	.LBB11_27
.LJTI11_1:
	.quad	.LBB11_67
	.quad	.LBB11_65
	.quad	.LBB11_68
	.quad	.LBB11_63
	.quad	.LBB11_68
	.quad	.LBB11_68
	.quad	.LBB11_68
	.quad	.LBB11_61
                                        # -- End function
	.section	.text._Z28__device_stub__cuda_asum_fltILj1024EEvPfS0_,"axG",@progbits,_Z28__device_stub__cuda_asum_fltILj1024EEvPfS0_,comdat
	.weak	_Z28__device_stub__cuda_asum_fltILj1024EEvPfS0_ # -- Begin function _Z28__device_stub__cuda_asum_fltILj1024EEvPfS0_
	.type	_Z28__device_stub__cuda_asum_fltILj1024EEvPfS0_,@function
_Z28__device_stub__cuda_asum_fltILj1024EEvPfS0_: # @_Z28__device_stub__cuda_asum_fltILj1024EEvPfS0_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	16(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z13cuda_asum_fltILj1024EEvPfS0_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end12:
	.size	_Z28__device_stub__cuda_asum_fltILj1024EEvPfS0_, .Lfunc_end12-_Z28__device_stub__cuda_asum_fltILj1024EEvPfS0_
	.cfi_endproc
                                        # -- End function
	.section	.text._Z28__device_stub__cuda_asum_fltILj512EEvPfS0_,"axG",@progbits,_Z28__device_stub__cuda_asum_fltILj512EEvPfS0_,comdat
	.weak	_Z28__device_stub__cuda_asum_fltILj512EEvPfS0_ # -- Begin function _Z28__device_stub__cuda_asum_fltILj512EEvPfS0_
	.type	_Z28__device_stub__cuda_asum_fltILj512EEvPfS0_,@function
_Z28__device_stub__cuda_asum_fltILj512EEvPfS0_: # @_Z28__device_stub__cuda_asum_fltILj512EEvPfS0_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	16(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z13cuda_asum_fltILj512EEvPfS0_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end13:
	.size	_Z28__device_stub__cuda_asum_fltILj512EEvPfS0_, .Lfunc_end13-_Z28__device_stub__cuda_asum_fltILj512EEvPfS0_
	.cfi_endproc
                                        # -- End function
	.section	.text._Z28__device_stub__cuda_asum_fltILj256EEvPfS0_,"axG",@progbits,_Z28__device_stub__cuda_asum_fltILj256EEvPfS0_,comdat
	.weak	_Z28__device_stub__cuda_asum_fltILj256EEvPfS0_ # -- Begin function _Z28__device_stub__cuda_asum_fltILj256EEvPfS0_
	.type	_Z28__device_stub__cuda_asum_fltILj256EEvPfS0_,@function
_Z28__device_stub__cuda_asum_fltILj256EEvPfS0_: # @_Z28__device_stub__cuda_asum_fltILj256EEvPfS0_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	16(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z13cuda_asum_fltILj256EEvPfS0_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end14:
	.size	_Z28__device_stub__cuda_asum_fltILj256EEvPfS0_, .Lfunc_end14-_Z28__device_stub__cuda_asum_fltILj256EEvPfS0_
	.cfi_endproc
                                        # -- End function
	.section	.text._Z28__device_stub__cuda_asum_fltILj128EEvPfS0_,"axG",@progbits,_Z28__device_stub__cuda_asum_fltILj128EEvPfS0_,comdat
	.weak	_Z28__device_stub__cuda_asum_fltILj128EEvPfS0_ # -- Begin function _Z28__device_stub__cuda_asum_fltILj128EEvPfS0_
	.type	_Z28__device_stub__cuda_asum_fltILj128EEvPfS0_,@function
_Z28__device_stub__cuda_asum_fltILj128EEvPfS0_: # @_Z28__device_stub__cuda_asum_fltILj128EEvPfS0_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	16(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z13cuda_asum_fltILj128EEvPfS0_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end15:
	.size	_Z28__device_stub__cuda_asum_fltILj128EEvPfS0_, .Lfunc_end15-_Z28__device_stub__cuda_asum_fltILj128EEvPfS0_
	.cfi_endproc
                                        # -- End function
	.section	.text._Z28__device_stub__cuda_asum_fltILj64EEvPfS0_,"axG",@progbits,_Z28__device_stub__cuda_asum_fltILj64EEvPfS0_,comdat
	.weak	_Z28__device_stub__cuda_asum_fltILj64EEvPfS0_ # -- Begin function _Z28__device_stub__cuda_asum_fltILj64EEvPfS0_
	.type	_Z28__device_stub__cuda_asum_fltILj64EEvPfS0_,@function
_Z28__device_stub__cuda_asum_fltILj64EEvPfS0_: # @_Z28__device_stub__cuda_asum_fltILj64EEvPfS0_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	16(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z13cuda_asum_fltILj64EEvPfS0_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end16:
	.size	_Z28__device_stub__cuda_asum_fltILj64EEvPfS0_, .Lfunc_end16-_Z28__device_stub__cuda_asum_fltILj64EEvPfS0_
	.cfi_endproc
                                        # -- End function
	.section	.text._Z28__device_stub__cuda_asum_fltILj32EEvPfS0_,"axG",@progbits,_Z28__device_stub__cuda_asum_fltILj32EEvPfS0_,comdat
	.weak	_Z28__device_stub__cuda_asum_fltILj32EEvPfS0_ # -- Begin function _Z28__device_stub__cuda_asum_fltILj32EEvPfS0_
	.type	_Z28__device_stub__cuda_asum_fltILj32EEvPfS0_,@function
_Z28__device_stub__cuda_asum_fltILj32EEvPfS0_: # @_Z28__device_stub__cuda_asum_fltILj32EEvPfS0_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	16(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z13cuda_asum_fltILj32EEvPfS0_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end17:
	.size	_Z28__device_stub__cuda_asum_fltILj32EEvPfS0_, .Lfunc_end17-_Z28__device_stub__cuda_asum_fltILj32EEvPfS0_
	.cfi_endproc
                                        # -- End function
	.section	.text._Z28__device_stub__cuda_asum_fltILj16EEvPfS0_,"axG",@progbits,_Z28__device_stub__cuda_asum_fltILj16EEvPfS0_,comdat
	.weak	_Z28__device_stub__cuda_asum_fltILj16EEvPfS0_ # -- Begin function _Z28__device_stub__cuda_asum_fltILj16EEvPfS0_
	.type	_Z28__device_stub__cuda_asum_fltILj16EEvPfS0_,@function
_Z28__device_stub__cuda_asum_fltILj16EEvPfS0_: # @_Z28__device_stub__cuda_asum_fltILj16EEvPfS0_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	16(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z13cuda_asum_fltILj16EEvPfS0_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end18:
	.size	_Z28__device_stub__cuda_asum_fltILj16EEvPfS0_, .Lfunc_end18-_Z28__device_stub__cuda_asum_fltILj16EEvPfS0_
	.cfi_endproc
                                        # -- End function
	.section	.text._Z28__device_stub__cuda_asum_fltILj8EEvPfS0_,"axG",@progbits,_Z28__device_stub__cuda_asum_fltILj8EEvPfS0_,comdat
	.weak	_Z28__device_stub__cuda_asum_fltILj8EEvPfS0_ # -- Begin function _Z28__device_stub__cuda_asum_fltILj8EEvPfS0_
	.type	_Z28__device_stub__cuda_asum_fltILj8EEvPfS0_,@function
_Z28__device_stub__cuda_asum_fltILj8EEvPfS0_: # @_Z28__device_stub__cuda_asum_fltILj8EEvPfS0_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	16(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z13cuda_asum_fltILj8EEvPfS0_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end19:
	.size	_Z28__device_stub__cuda_asum_fltILj8EEvPfS0_, .Lfunc_end19-_Z28__device_stub__cuda_asum_fltILj8EEvPfS0_
	.cfi_endproc
                                        # -- End function
	.section	.text._Z28__device_stub__cuda_asum_fltILj4EEvPfS0_,"axG",@progbits,_Z28__device_stub__cuda_asum_fltILj4EEvPfS0_,comdat
	.weak	_Z28__device_stub__cuda_asum_fltILj4EEvPfS0_ # -- Begin function _Z28__device_stub__cuda_asum_fltILj4EEvPfS0_
	.type	_Z28__device_stub__cuda_asum_fltILj4EEvPfS0_,@function
_Z28__device_stub__cuda_asum_fltILj4EEvPfS0_: # @_Z28__device_stub__cuda_asum_fltILj4EEvPfS0_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	16(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z13cuda_asum_fltILj4EEvPfS0_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end20:
	.size	_Z28__device_stub__cuda_asum_fltILj4EEvPfS0_, .Lfunc_end20-_Z28__device_stub__cuda_asum_fltILj4EEvPfS0_
	.cfi_endproc
                                        # -- End function
	.section	.text._Z28__device_stub__cuda_asum_fltILj2EEvPfS0_,"axG",@progbits,_Z28__device_stub__cuda_asum_fltILj2EEvPfS0_,comdat
	.weak	_Z28__device_stub__cuda_asum_fltILj2EEvPfS0_ # -- Begin function _Z28__device_stub__cuda_asum_fltILj2EEvPfS0_
	.type	_Z28__device_stub__cuda_asum_fltILj2EEvPfS0_,@function
_Z28__device_stub__cuda_asum_fltILj2EEvPfS0_: # @_Z28__device_stub__cuda_asum_fltILj2EEvPfS0_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	16(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z13cuda_asum_fltILj2EEvPfS0_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end21:
	.size	_Z28__device_stub__cuda_asum_fltILj2EEvPfS0_, .Lfunc_end21-_Z28__device_stub__cuda_asum_fltILj2EEvPfS0_
	.cfi_endproc
                                        # -- End function
	.section	.text._Z28__device_stub__cuda_asum_fltILj1EEvPfS0_,"axG",@progbits,_Z28__device_stub__cuda_asum_fltILj1EEvPfS0_,comdat
	.weak	_Z28__device_stub__cuda_asum_fltILj1EEvPfS0_ # -- Begin function _Z28__device_stub__cuda_asum_fltILj1EEvPfS0_
	.type	_Z28__device_stub__cuda_asum_fltILj1EEvPfS0_,@function
_Z28__device_stub__cuda_asum_fltILj1EEvPfS0_: # @_Z28__device_stub__cuda_asum_fltILj1EEvPfS0_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	16(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z13cuda_asum_fltILj1EEvPfS0_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end22:
	.size	_Z28__device_stub__cuda_asum_fltILj1EEvPfS0_, .Lfunc_end22-_Z28__device_stub__cuda_asum_fltILj1EEvPfS0_
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0                          # -- Begin function _Z15cuda_asum_doubmPdd
.LCPI23_0:
	.quad	0x4080000000000000              # double 512
.LCPI23_1:
	.quad	0x3f60000000000000              # double 0.001953125
	.text
	.globl	_Z15cuda_asum_doubmPdd
	.type	_Z15cuda_asum_doubmPdd,@function
_Z15cuda_asum_doubmPdd:                 # @_Z15cuda_asum_doubmPdd
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r12
	.cfi_def_cfa_offset 32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	pushq	%rax
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -40
	.cfi_offset %r12, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movq	%rdi, %rbx
	ucomisd	.LCPI23_0(%rip), %xmm0
	jbe	.LBB23_6
# %bb.1:                                # %.preheader
	mulsd	.LCPI23_1(%rip), %xmm0
	cvttsd2si	%xmm0, %rax
	cmpl	$2, %eax
	jb	.LBB23_36
# %bb.2:                                # %.lr.ph.preheader
	movabsq	$4294967297, %r12               # imm = 0x100000001
	leaq	255(%r12), %r14
.LBB23_3:                               # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	movl	%eax, %r15d
	movl	%eax, %eax
	leaq	(%r12,%rax), %rdi
	decq	%rdi
	movl	$2048, %r8d                     # imm = 0x800
	movl	$1, %esi
	movq	%r14, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB23_5
# %bb.4:                                #   in Loop: Header=BB23_3 Depth=1
	movq	%rbx, %rdi
	movq	%rbx, %rsi
	callq	_Z29__device_stub__cuda_asum_doubILj256EEvPdS0_
.LBB23_5:                               #   in Loop: Header=BB23_3 Depth=1
	movl	%r15d, %eax
	shrl	$9, %eax
	cmpl	$1023, %r15d                    # imm = 0x3FF
	ja	.LBB23_3
	jmp	.LBB23_7
.LBB23_6:
	cvttsd2si	%xmm0, %r15
.LBB23_7:                               # %.loopexit
	shrl	%r15d
	cmpl	$31, %r15d
	jg	.LBB23_13
# %bb.8:                                # %.loopexit
	leal	-1(%r15), %eax
	cmpl	$7, %eax
	ja	.LBB23_9
# %bb.12:                               # %.loopexit
	jmpq	*.LJTI23_0(,%rax,8)
.LBB23_35:
	movabsq	$4294967297, %rdi               # imm = 0x100000001
	movl	$8, %r8d
	movl	$1, %esi
	movq	%rdi, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB23_36
# %bb.37:
	movq	%rbx, %rdi
	movq	%rbx, %rsi
	addq	$8, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	_Z29__device_stub__cuda_asum_doubILj1EEvPdS0_ # TAILCALL
.LBB23_13:                              # %.loopexit
	.cfi_def_cfa_offset 48
	cmpl	$127, %r15d
	jle	.LBB23_14
# %bb.18:                               # %.loopexit
	cmpl	$128, %r15d
	je	.LBB23_25
# %bb.19:                               # %.loopexit
	cmpl	$256, %r15d                     # imm = 0x100
	je	.LBB23_23
# %bb.20:                               # %.loopexit
	cmpl	$512, %r15d                     # imm = 0x200
	jne	.LBB23_36
# %bb.21:
	movabsq	$4294967297, %rdi               # imm = 0x100000001
	leaq	511(%rdi), %rdx
	movl	$4096, %r8d                     # imm = 0x1000
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB23_36
# %bb.22:
	movq	%rbx, %rdi
	movq	%rbx, %rsi
	addq	$8, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	_Z29__device_stub__cuda_asum_doubILj512EEvPdS0_ # TAILCALL
.LBB23_14:                              # %.loopexit
	.cfi_def_cfa_offset 48
	cmpl	$32, %r15d
	je	.LBB23_27
# %bb.15:                               # %.loopexit
	cmpl	$64, %r15d
	jne	.LBB23_36
# %bb.16:
	movabsq	$4294967297, %rdi               # imm = 0x100000001
	leaq	63(%rdi), %rdx
	movl	$512, %r8d                      # imm = 0x200
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB23_36
# %bb.17:
	movq	%rbx, %rdi
	movq	%rbx, %rsi
	addq	$8, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	_Z29__device_stub__cuda_asum_doubILj64EEvPdS0_ # TAILCALL
.LBB23_9:                               # %.loopexit
	.cfi_def_cfa_offset 48
	cmpl	$16, %r15d
	jne	.LBB23_36
# %bb.10:
	movabsq	$4294967297, %rdi               # imm = 0x100000001
	leaq	15(%rdi), %rdx
	movl	$128, %r8d
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB23_36
# %bb.11:
	movq	%rbx, %rdi
	movq	%rbx, %rsi
	addq	$8, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	_Z29__device_stub__cuda_asum_doubILj16EEvPdS0_ # TAILCALL
.LBB23_31:
	.cfi_def_cfa_offset 48
	movabsq	$4294967297, %rdi               # imm = 0x100000001
	leaq	3(%rdi), %rdx
	movl	$32, %r8d
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB23_36
# %bb.32:
	movq	%rbx, %rdi
	movq	%rbx, %rsi
	addq	$8, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	_Z29__device_stub__cuda_asum_doubILj4EEvPdS0_ # TAILCALL
.LBB23_33:
	.cfi_def_cfa_offset 48
	movabsq	$4294967297, %rdi               # imm = 0x100000001
	leaq	1(%rdi), %rdx
	movl	$16, %r8d
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB23_36
# %bb.34:
	movq	%rbx, %rdi
	movq	%rbx, %rsi
	addq	$8, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	_Z29__device_stub__cuda_asum_doubILj2EEvPdS0_ # TAILCALL
.LBB23_29:
	.cfi_def_cfa_offset 48
	movabsq	$4294967297, %rdi               # imm = 0x100000001
	leaq	7(%rdi), %rdx
	movl	$64, %r8d
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB23_36
# %bb.30:
	movq	%rbx, %rdi
	movq	%rbx, %rsi
	addq	$8, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	_Z29__device_stub__cuda_asum_doubILj8EEvPdS0_ # TAILCALL
.LBB23_27:
	.cfi_def_cfa_offset 48
	movabsq	$4294967297, %rdi               # imm = 0x100000001
	leaq	31(%rdi), %rdx
	movl	$256, %r8d                      # imm = 0x100
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB23_36
# %bb.28:
	movq	%rbx, %rdi
	movq	%rbx, %rsi
	addq	$8, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	_Z29__device_stub__cuda_asum_doubILj32EEvPdS0_ # TAILCALL
.LBB23_25:
	.cfi_def_cfa_offset 48
	movabsq	$4294967297, %rdi               # imm = 0x100000001
	leaq	127(%rdi), %rdx
	movl	$1024, %r8d                     # imm = 0x400
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB23_36
# %bb.26:
	movq	%rbx, %rdi
	movq	%rbx, %rsi
	addq	$8, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	_Z29__device_stub__cuda_asum_doubILj128EEvPdS0_ # TAILCALL
.LBB23_23:
	.cfi_def_cfa_offset 48
	movabsq	$4294967297, %rdi               # imm = 0x100000001
	leaq	255(%rdi), %rdx
	movl	$2048, %r8d                     # imm = 0x800
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	je	.LBB23_24
.LBB23_36:                              # %.loopexit.thread
	addq	$8, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.LBB23_24:
	.cfi_def_cfa_offset 48
	movq	%rbx, %rdi
	movq	%rbx, %rsi
	addq	$8, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	_Z29__device_stub__cuda_asum_doubILj256EEvPdS0_ # TAILCALL
.Lfunc_end23:
	.size	_Z15cuda_asum_doubmPdd, .Lfunc_end23-_Z15cuda_asum_doubmPdd
	.cfi_endproc
	.section	.rodata,"a",@progbits
	.p2align	3, 0x0
.LJTI23_0:
	.quad	.LBB23_35
	.quad	.LBB23_33
	.quad	.LBB23_36
	.quad	.LBB23_31
	.quad	.LBB23_36
	.quad	.LBB23_36
	.quad	.LBB23_36
	.quad	.LBB23_29
                                        # -- End function
	.section	.text._Z29__device_stub__cuda_asum_doubILj512EEvPdS0_,"axG",@progbits,_Z29__device_stub__cuda_asum_doubILj512EEvPdS0_,comdat
	.weak	_Z29__device_stub__cuda_asum_doubILj512EEvPdS0_ # -- Begin function _Z29__device_stub__cuda_asum_doubILj512EEvPdS0_
	.type	_Z29__device_stub__cuda_asum_doubILj512EEvPdS0_,@function
_Z29__device_stub__cuda_asum_doubILj512EEvPdS0_: # @_Z29__device_stub__cuda_asum_doubILj512EEvPdS0_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	16(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z14cuda_asum_doubILj512EEvPdS0_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end24:
	.size	_Z29__device_stub__cuda_asum_doubILj512EEvPdS0_, .Lfunc_end24-_Z29__device_stub__cuda_asum_doubILj512EEvPdS0_
	.cfi_endproc
                                        # -- End function
	.section	.text._Z29__device_stub__cuda_asum_doubILj256EEvPdS0_,"axG",@progbits,_Z29__device_stub__cuda_asum_doubILj256EEvPdS0_,comdat
	.weak	_Z29__device_stub__cuda_asum_doubILj256EEvPdS0_ # -- Begin function _Z29__device_stub__cuda_asum_doubILj256EEvPdS0_
	.type	_Z29__device_stub__cuda_asum_doubILj256EEvPdS0_,@function
_Z29__device_stub__cuda_asum_doubILj256EEvPdS0_: # @_Z29__device_stub__cuda_asum_doubILj256EEvPdS0_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	16(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z14cuda_asum_doubILj256EEvPdS0_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end25:
	.size	_Z29__device_stub__cuda_asum_doubILj256EEvPdS0_, .Lfunc_end25-_Z29__device_stub__cuda_asum_doubILj256EEvPdS0_
	.cfi_endproc
                                        # -- End function
	.section	.text._Z29__device_stub__cuda_asum_doubILj128EEvPdS0_,"axG",@progbits,_Z29__device_stub__cuda_asum_doubILj128EEvPdS0_,comdat
	.weak	_Z29__device_stub__cuda_asum_doubILj128EEvPdS0_ # -- Begin function _Z29__device_stub__cuda_asum_doubILj128EEvPdS0_
	.type	_Z29__device_stub__cuda_asum_doubILj128EEvPdS0_,@function
_Z29__device_stub__cuda_asum_doubILj128EEvPdS0_: # @_Z29__device_stub__cuda_asum_doubILj128EEvPdS0_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	16(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z14cuda_asum_doubILj128EEvPdS0_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end26:
	.size	_Z29__device_stub__cuda_asum_doubILj128EEvPdS0_, .Lfunc_end26-_Z29__device_stub__cuda_asum_doubILj128EEvPdS0_
	.cfi_endproc
                                        # -- End function
	.section	.text._Z29__device_stub__cuda_asum_doubILj64EEvPdS0_,"axG",@progbits,_Z29__device_stub__cuda_asum_doubILj64EEvPdS0_,comdat
	.weak	_Z29__device_stub__cuda_asum_doubILj64EEvPdS0_ # -- Begin function _Z29__device_stub__cuda_asum_doubILj64EEvPdS0_
	.type	_Z29__device_stub__cuda_asum_doubILj64EEvPdS0_,@function
_Z29__device_stub__cuda_asum_doubILj64EEvPdS0_: # @_Z29__device_stub__cuda_asum_doubILj64EEvPdS0_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	16(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z14cuda_asum_doubILj64EEvPdS0_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end27:
	.size	_Z29__device_stub__cuda_asum_doubILj64EEvPdS0_, .Lfunc_end27-_Z29__device_stub__cuda_asum_doubILj64EEvPdS0_
	.cfi_endproc
                                        # -- End function
	.section	.text._Z29__device_stub__cuda_asum_doubILj32EEvPdS0_,"axG",@progbits,_Z29__device_stub__cuda_asum_doubILj32EEvPdS0_,comdat
	.weak	_Z29__device_stub__cuda_asum_doubILj32EEvPdS0_ # -- Begin function _Z29__device_stub__cuda_asum_doubILj32EEvPdS0_
	.type	_Z29__device_stub__cuda_asum_doubILj32EEvPdS0_,@function
_Z29__device_stub__cuda_asum_doubILj32EEvPdS0_: # @_Z29__device_stub__cuda_asum_doubILj32EEvPdS0_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	16(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z14cuda_asum_doubILj32EEvPdS0_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end28:
	.size	_Z29__device_stub__cuda_asum_doubILj32EEvPdS0_, .Lfunc_end28-_Z29__device_stub__cuda_asum_doubILj32EEvPdS0_
	.cfi_endproc
                                        # -- End function
	.section	.text._Z29__device_stub__cuda_asum_doubILj16EEvPdS0_,"axG",@progbits,_Z29__device_stub__cuda_asum_doubILj16EEvPdS0_,comdat
	.weak	_Z29__device_stub__cuda_asum_doubILj16EEvPdS0_ # -- Begin function _Z29__device_stub__cuda_asum_doubILj16EEvPdS0_
	.type	_Z29__device_stub__cuda_asum_doubILj16EEvPdS0_,@function
_Z29__device_stub__cuda_asum_doubILj16EEvPdS0_: # @_Z29__device_stub__cuda_asum_doubILj16EEvPdS0_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	16(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z14cuda_asum_doubILj16EEvPdS0_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end29:
	.size	_Z29__device_stub__cuda_asum_doubILj16EEvPdS0_, .Lfunc_end29-_Z29__device_stub__cuda_asum_doubILj16EEvPdS0_
	.cfi_endproc
                                        # -- End function
	.section	.text._Z29__device_stub__cuda_asum_doubILj8EEvPdS0_,"axG",@progbits,_Z29__device_stub__cuda_asum_doubILj8EEvPdS0_,comdat
	.weak	_Z29__device_stub__cuda_asum_doubILj8EEvPdS0_ # -- Begin function _Z29__device_stub__cuda_asum_doubILj8EEvPdS0_
	.type	_Z29__device_stub__cuda_asum_doubILj8EEvPdS0_,@function
_Z29__device_stub__cuda_asum_doubILj8EEvPdS0_: # @_Z29__device_stub__cuda_asum_doubILj8EEvPdS0_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	16(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z14cuda_asum_doubILj8EEvPdS0_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end30:
	.size	_Z29__device_stub__cuda_asum_doubILj8EEvPdS0_, .Lfunc_end30-_Z29__device_stub__cuda_asum_doubILj8EEvPdS0_
	.cfi_endproc
                                        # -- End function
	.section	.text._Z29__device_stub__cuda_asum_doubILj4EEvPdS0_,"axG",@progbits,_Z29__device_stub__cuda_asum_doubILj4EEvPdS0_,comdat
	.weak	_Z29__device_stub__cuda_asum_doubILj4EEvPdS0_ # -- Begin function _Z29__device_stub__cuda_asum_doubILj4EEvPdS0_
	.type	_Z29__device_stub__cuda_asum_doubILj4EEvPdS0_,@function
_Z29__device_stub__cuda_asum_doubILj4EEvPdS0_: # @_Z29__device_stub__cuda_asum_doubILj4EEvPdS0_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	16(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z14cuda_asum_doubILj4EEvPdS0_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end31:
	.size	_Z29__device_stub__cuda_asum_doubILj4EEvPdS0_, .Lfunc_end31-_Z29__device_stub__cuda_asum_doubILj4EEvPdS0_
	.cfi_endproc
                                        # -- End function
	.section	.text._Z29__device_stub__cuda_asum_doubILj2EEvPdS0_,"axG",@progbits,_Z29__device_stub__cuda_asum_doubILj2EEvPdS0_,comdat
	.weak	_Z29__device_stub__cuda_asum_doubILj2EEvPdS0_ # -- Begin function _Z29__device_stub__cuda_asum_doubILj2EEvPdS0_
	.type	_Z29__device_stub__cuda_asum_doubILj2EEvPdS0_,@function
_Z29__device_stub__cuda_asum_doubILj2EEvPdS0_: # @_Z29__device_stub__cuda_asum_doubILj2EEvPdS0_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	16(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z14cuda_asum_doubILj2EEvPdS0_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end32:
	.size	_Z29__device_stub__cuda_asum_doubILj2EEvPdS0_, .Lfunc_end32-_Z29__device_stub__cuda_asum_doubILj2EEvPdS0_
	.cfi_endproc
                                        # -- End function
	.section	.text._Z29__device_stub__cuda_asum_doubILj1EEvPdS0_,"axG",@progbits,_Z29__device_stub__cuda_asum_doubILj1EEvPdS0_,comdat
	.weak	_Z29__device_stub__cuda_asum_doubILj1EEvPdS0_ # -- Begin function _Z29__device_stub__cuda_asum_doubILj1EEvPdS0_
	.type	_Z29__device_stub__cuda_asum_doubILj1EEvPdS0_,@function
_Z29__device_stub__cuda_asum_doubILj1EEvPdS0_: # @_Z29__device_stub__cuda_asum_doubILj1EEvPdS0_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	16(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z14cuda_asum_doubILj1EEvPdS0_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end33:
	.size	_Z29__device_stub__cuda_asum_doubILj1EEvPdS0_, .Lfunc_end33-_Z29__device_stub__cuda_asum_doubILj1EEvPdS0_
	.cfi_endproc
                                        # -- End function
	.text
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB34_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB34_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z13cuda_asum_intILj512EEvPiS0_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z13cuda_asum_intILj256EEvPiS0_, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z13cuda_asum_intILj128EEvPiS0_, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z13cuda_asum_intILj64EEvPiS0_, %esi
	movl	$.L__unnamed_4, %edx
	movl	$.L__unnamed_4, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z13cuda_asum_intILj32EEvPiS0_, %esi
	movl	$.L__unnamed_5, %edx
	movl	$.L__unnamed_5, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z13cuda_asum_intILj16EEvPiS0_, %esi
	movl	$.L__unnamed_6, %edx
	movl	$.L__unnamed_6, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z13cuda_asum_intILj8EEvPiS0_, %esi
	movl	$.L__unnamed_7, %edx
	movl	$.L__unnamed_7, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z13cuda_asum_intILj4EEvPiS0_, %esi
	movl	$.L__unnamed_8, %edx
	movl	$.L__unnamed_8, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z13cuda_asum_intILj2EEvPiS0_, %esi
	movl	$.L__unnamed_9, %edx
	movl	$.L__unnamed_9, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z13cuda_asum_intILj1EEvPiS0_, %esi
	movl	$.L__unnamed_10, %edx
	movl	$.L__unnamed_10, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z13cuda_asum_fltILj1024EEvPfS0_, %esi
	movl	$.L__unnamed_11, %edx
	movl	$.L__unnamed_11, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z13cuda_asum_fltILj512EEvPfS0_, %esi
	movl	$.L__unnamed_12, %edx
	movl	$.L__unnamed_12, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z13cuda_asum_fltILj256EEvPfS0_, %esi
	movl	$.L__unnamed_13, %edx
	movl	$.L__unnamed_13, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z13cuda_asum_fltILj128EEvPfS0_, %esi
	movl	$.L__unnamed_14, %edx
	movl	$.L__unnamed_14, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z13cuda_asum_fltILj64EEvPfS0_, %esi
	movl	$.L__unnamed_15, %edx
	movl	$.L__unnamed_15, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z13cuda_asum_fltILj32EEvPfS0_, %esi
	movl	$.L__unnamed_16, %edx
	movl	$.L__unnamed_16, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z13cuda_asum_fltILj16EEvPfS0_, %esi
	movl	$.L__unnamed_17, %edx
	movl	$.L__unnamed_17, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z13cuda_asum_fltILj8EEvPfS0_, %esi
	movl	$.L__unnamed_18, %edx
	movl	$.L__unnamed_18, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z13cuda_asum_fltILj4EEvPfS0_, %esi
	movl	$.L__unnamed_19, %edx
	movl	$.L__unnamed_19, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z13cuda_asum_fltILj2EEvPfS0_, %esi
	movl	$.L__unnamed_20, %edx
	movl	$.L__unnamed_20, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z13cuda_asum_fltILj1EEvPfS0_, %esi
	movl	$.L__unnamed_21, %edx
	movl	$.L__unnamed_21, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z14cuda_asum_doubILj512EEvPdS0_, %esi
	movl	$.L__unnamed_22, %edx
	movl	$.L__unnamed_22, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z14cuda_asum_doubILj256EEvPdS0_, %esi
	movl	$.L__unnamed_23, %edx
	movl	$.L__unnamed_23, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z14cuda_asum_doubILj128EEvPdS0_, %esi
	movl	$.L__unnamed_24, %edx
	movl	$.L__unnamed_24, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z14cuda_asum_doubILj64EEvPdS0_, %esi
	movl	$.L__unnamed_25, %edx
	movl	$.L__unnamed_25, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z14cuda_asum_doubILj32EEvPdS0_, %esi
	movl	$.L__unnamed_26, %edx
	movl	$.L__unnamed_26, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z14cuda_asum_doubILj16EEvPdS0_, %esi
	movl	$.L__unnamed_27, %edx
	movl	$.L__unnamed_27, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z14cuda_asum_doubILj8EEvPdS0_, %esi
	movl	$.L__unnamed_28, %edx
	movl	$.L__unnamed_28, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z14cuda_asum_doubILj4EEvPdS0_, %esi
	movl	$.L__unnamed_29, %edx
	movl	$.L__unnamed_29, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z14cuda_asum_doubILj2EEvPdS0_, %esi
	movl	$.L__unnamed_30, %edx
	movl	$.L__unnamed_30, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z14cuda_asum_doubILj1EEvPdS0_, %esi
	movl	$.L__unnamed_31, %edx
	movl	$.L__unnamed_31, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end34:
	.size	__hip_module_ctor, .Lfunc_end34-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB35_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB35_2:
	retq
.Lfunc_end35:
	.size	__hip_module_dtor, .Lfunc_end35-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z13cuda_asum_intILj512EEvPiS0_,@object # @_Z13cuda_asum_intILj512EEvPiS0_
	.section	.rodata._Z13cuda_asum_intILj512EEvPiS0_,"aG",@progbits,_Z13cuda_asum_intILj512EEvPiS0_,comdat
	.weak	_Z13cuda_asum_intILj512EEvPiS0_
	.p2align	3, 0x0
_Z13cuda_asum_intILj512EEvPiS0_:
	.quad	_Z28__device_stub__cuda_asum_intILj512EEvPiS0_
	.size	_Z13cuda_asum_intILj512EEvPiS0_, 8

	.type	_Z13cuda_asum_intILj256EEvPiS0_,@object # @_Z13cuda_asum_intILj256EEvPiS0_
	.section	.rodata._Z13cuda_asum_intILj256EEvPiS0_,"aG",@progbits,_Z13cuda_asum_intILj256EEvPiS0_,comdat
	.weak	_Z13cuda_asum_intILj256EEvPiS0_
	.p2align	3, 0x0
_Z13cuda_asum_intILj256EEvPiS0_:
	.quad	_Z28__device_stub__cuda_asum_intILj256EEvPiS0_
	.size	_Z13cuda_asum_intILj256EEvPiS0_, 8

	.type	_Z13cuda_asum_intILj128EEvPiS0_,@object # @_Z13cuda_asum_intILj128EEvPiS0_
	.section	.rodata._Z13cuda_asum_intILj128EEvPiS0_,"aG",@progbits,_Z13cuda_asum_intILj128EEvPiS0_,comdat
	.weak	_Z13cuda_asum_intILj128EEvPiS0_
	.p2align	3, 0x0
_Z13cuda_asum_intILj128EEvPiS0_:
	.quad	_Z28__device_stub__cuda_asum_intILj128EEvPiS0_
	.size	_Z13cuda_asum_intILj128EEvPiS0_, 8

	.type	_Z13cuda_asum_intILj64EEvPiS0_,@object # @_Z13cuda_asum_intILj64EEvPiS0_
	.section	.rodata._Z13cuda_asum_intILj64EEvPiS0_,"aG",@progbits,_Z13cuda_asum_intILj64EEvPiS0_,comdat
	.weak	_Z13cuda_asum_intILj64EEvPiS0_
	.p2align	3, 0x0
_Z13cuda_asum_intILj64EEvPiS0_:
	.quad	_Z28__device_stub__cuda_asum_intILj64EEvPiS0_
	.size	_Z13cuda_asum_intILj64EEvPiS0_, 8

	.type	_Z13cuda_asum_intILj32EEvPiS0_,@object # @_Z13cuda_asum_intILj32EEvPiS0_
	.section	.rodata._Z13cuda_asum_intILj32EEvPiS0_,"aG",@progbits,_Z13cuda_asum_intILj32EEvPiS0_,comdat
	.weak	_Z13cuda_asum_intILj32EEvPiS0_
	.p2align	3, 0x0
_Z13cuda_asum_intILj32EEvPiS0_:
	.quad	_Z28__device_stub__cuda_asum_intILj32EEvPiS0_
	.size	_Z13cuda_asum_intILj32EEvPiS0_, 8

	.type	_Z13cuda_asum_intILj16EEvPiS0_,@object # @_Z13cuda_asum_intILj16EEvPiS0_
	.section	.rodata._Z13cuda_asum_intILj16EEvPiS0_,"aG",@progbits,_Z13cuda_asum_intILj16EEvPiS0_,comdat
	.weak	_Z13cuda_asum_intILj16EEvPiS0_
	.p2align	3, 0x0
_Z13cuda_asum_intILj16EEvPiS0_:
	.quad	_Z28__device_stub__cuda_asum_intILj16EEvPiS0_
	.size	_Z13cuda_asum_intILj16EEvPiS0_, 8

	.type	_Z13cuda_asum_intILj8EEvPiS0_,@object # @_Z13cuda_asum_intILj8EEvPiS0_
	.section	.rodata._Z13cuda_asum_intILj8EEvPiS0_,"aG",@progbits,_Z13cuda_asum_intILj8EEvPiS0_,comdat
	.weak	_Z13cuda_asum_intILj8EEvPiS0_
	.p2align	3, 0x0
_Z13cuda_asum_intILj8EEvPiS0_:
	.quad	_Z28__device_stub__cuda_asum_intILj8EEvPiS0_
	.size	_Z13cuda_asum_intILj8EEvPiS0_, 8

	.type	_Z13cuda_asum_intILj4EEvPiS0_,@object # @_Z13cuda_asum_intILj4EEvPiS0_
	.section	.rodata._Z13cuda_asum_intILj4EEvPiS0_,"aG",@progbits,_Z13cuda_asum_intILj4EEvPiS0_,comdat
	.weak	_Z13cuda_asum_intILj4EEvPiS0_
	.p2align	3, 0x0
_Z13cuda_asum_intILj4EEvPiS0_:
	.quad	_Z28__device_stub__cuda_asum_intILj4EEvPiS0_
	.size	_Z13cuda_asum_intILj4EEvPiS0_, 8

	.type	_Z13cuda_asum_intILj2EEvPiS0_,@object # @_Z13cuda_asum_intILj2EEvPiS0_
	.section	.rodata._Z13cuda_asum_intILj2EEvPiS0_,"aG",@progbits,_Z13cuda_asum_intILj2EEvPiS0_,comdat
	.weak	_Z13cuda_asum_intILj2EEvPiS0_
	.p2align	3, 0x0
_Z13cuda_asum_intILj2EEvPiS0_:
	.quad	_Z28__device_stub__cuda_asum_intILj2EEvPiS0_
	.size	_Z13cuda_asum_intILj2EEvPiS0_, 8

	.type	_Z13cuda_asum_intILj1EEvPiS0_,@object # @_Z13cuda_asum_intILj1EEvPiS0_
	.section	.rodata._Z13cuda_asum_intILj1EEvPiS0_,"aG",@progbits,_Z13cuda_asum_intILj1EEvPiS0_,comdat
	.weak	_Z13cuda_asum_intILj1EEvPiS0_
	.p2align	3, 0x0
_Z13cuda_asum_intILj1EEvPiS0_:
	.quad	_Z28__device_stub__cuda_asum_intILj1EEvPiS0_
	.size	_Z13cuda_asum_intILj1EEvPiS0_, 8

	.type	_Z13cuda_asum_fltILj1024EEvPfS0_,@object # @_Z13cuda_asum_fltILj1024EEvPfS0_
	.section	.rodata._Z13cuda_asum_fltILj1024EEvPfS0_,"aG",@progbits,_Z13cuda_asum_fltILj1024EEvPfS0_,comdat
	.weak	_Z13cuda_asum_fltILj1024EEvPfS0_
	.p2align	3, 0x0
_Z13cuda_asum_fltILj1024EEvPfS0_:
	.quad	_Z28__device_stub__cuda_asum_fltILj1024EEvPfS0_
	.size	_Z13cuda_asum_fltILj1024EEvPfS0_, 8

	.type	_Z13cuda_asum_fltILj512EEvPfS0_,@object # @_Z13cuda_asum_fltILj512EEvPfS0_
	.section	.rodata._Z13cuda_asum_fltILj512EEvPfS0_,"aG",@progbits,_Z13cuda_asum_fltILj512EEvPfS0_,comdat
	.weak	_Z13cuda_asum_fltILj512EEvPfS0_
	.p2align	3, 0x0
_Z13cuda_asum_fltILj512EEvPfS0_:
	.quad	_Z28__device_stub__cuda_asum_fltILj512EEvPfS0_
	.size	_Z13cuda_asum_fltILj512EEvPfS0_, 8

	.type	_Z13cuda_asum_fltILj256EEvPfS0_,@object # @_Z13cuda_asum_fltILj256EEvPfS0_
	.section	.rodata._Z13cuda_asum_fltILj256EEvPfS0_,"aG",@progbits,_Z13cuda_asum_fltILj256EEvPfS0_,comdat
	.weak	_Z13cuda_asum_fltILj256EEvPfS0_
	.p2align	3, 0x0
_Z13cuda_asum_fltILj256EEvPfS0_:
	.quad	_Z28__device_stub__cuda_asum_fltILj256EEvPfS0_
	.size	_Z13cuda_asum_fltILj256EEvPfS0_, 8

	.type	_Z13cuda_asum_fltILj128EEvPfS0_,@object # @_Z13cuda_asum_fltILj128EEvPfS0_
	.section	.rodata._Z13cuda_asum_fltILj128EEvPfS0_,"aG",@progbits,_Z13cuda_asum_fltILj128EEvPfS0_,comdat
	.weak	_Z13cuda_asum_fltILj128EEvPfS0_
	.p2align	3, 0x0
_Z13cuda_asum_fltILj128EEvPfS0_:
	.quad	_Z28__device_stub__cuda_asum_fltILj128EEvPfS0_
	.size	_Z13cuda_asum_fltILj128EEvPfS0_, 8

	.type	_Z13cuda_asum_fltILj64EEvPfS0_,@object # @_Z13cuda_asum_fltILj64EEvPfS0_
	.section	.rodata._Z13cuda_asum_fltILj64EEvPfS0_,"aG",@progbits,_Z13cuda_asum_fltILj64EEvPfS0_,comdat
	.weak	_Z13cuda_asum_fltILj64EEvPfS0_
	.p2align	3, 0x0
_Z13cuda_asum_fltILj64EEvPfS0_:
	.quad	_Z28__device_stub__cuda_asum_fltILj64EEvPfS0_
	.size	_Z13cuda_asum_fltILj64EEvPfS0_, 8

	.type	_Z13cuda_asum_fltILj32EEvPfS0_,@object # @_Z13cuda_asum_fltILj32EEvPfS0_
	.section	.rodata._Z13cuda_asum_fltILj32EEvPfS0_,"aG",@progbits,_Z13cuda_asum_fltILj32EEvPfS0_,comdat
	.weak	_Z13cuda_asum_fltILj32EEvPfS0_
	.p2align	3, 0x0
_Z13cuda_asum_fltILj32EEvPfS0_:
	.quad	_Z28__device_stub__cuda_asum_fltILj32EEvPfS0_
	.size	_Z13cuda_asum_fltILj32EEvPfS0_, 8

	.type	_Z13cuda_asum_fltILj16EEvPfS0_,@object # @_Z13cuda_asum_fltILj16EEvPfS0_
	.section	.rodata._Z13cuda_asum_fltILj16EEvPfS0_,"aG",@progbits,_Z13cuda_asum_fltILj16EEvPfS0_,comdat
	.weak	_Z13cuda_asum_fltILj16EEvPfS0_
	.p2align	3, 0x0
_Z13cuda_asum_fltILj16EEvPfS0_:
	.quad	_Z28__device_stub__cuda_asum_fltILj16EEvPfS0_
	.size	_Z13cuda_asum_fltILj16EEvPfS0_, 8

	.type	_Z13cuda_asum_fltILj8EEvPfS0_,@object # @_Z13cuda_asum_fltILj8EEvPfS0_
	.section	.rodata._Z13cuda_asum_fltILj8EEvPfS0_,"aG",@progbits,_Z13cuda_asum_fltILj8EEvPfS0_,comdat
	.weak	_Z13cuda_asum_fltILj8EEvPfS0_
	.p2align	3, 0x0
_Z13cuda_asum_fltILj8EEvPfS0_:
	.quad	_Z28__device_stub__cuda_asum_fltILj8EEvPfS0_
	.size	_Z13cuda_asum_fltILj8EEvPfS0_, 8

	.type	_Z13cuda_asum_fltILj4EEvPfS0_,@object # @_Z13cuda_asum_fltILj4EEvPfS0_
	.section	.rodata._Z13cuda_asum_fltILj4EEvPfS0_,"aG",@progbits,_Z13cuda_asum_fltILj4EEvPfS0_,comdat
	.weak	_Z13cuda_asum_fltILj4EEvPfS0_
	.p2align	3, 0x0
_Z13cuda_asum_fltILj4EEvPfS0_:
	.quad	_Z28__device_stub__cuda_asum_fltILj4EEvPfS0_
	.size	_Z13cuda_asum_fltILj4EEvPfS0_, 8

	.type	_Z13cuda_asum_fltILj2EEvPfS0_,@object # @_Z13cuda_asum_fltILj2EEvPfS0_
	.section	.rodata._Z13cuda_asum_fltILj2EEvPfS0_,"aG",@progbits,_Z13cuda_asum_fltILj2EEvPfS0_,comdat
	.weak	_Z13cuda_asum_fltILj2EEvPfS0_
	.p2align	3, 0x0
_Z13cuda_asum_fltILj2EEvPfS0_:
	.quad	_Z28__device_stub__cuda_asum_fltILj2EEvPfS0_
	.size	_Z13cuda_asum_fltILj2EEvPfS0_, 8

	.type	_Z13cuda_asum_fltILj1EEvPfS0_,@object # @_Z13cuda_asum_fltILj1EEvPfS0_
	.section	.rodata._Z13cuda_asum_fltILj1EEvPfS0_,"aG",@progbits,_Z13cuda_asum_fltILj1EEvPfS0_,comdat
	.weak	_Z13cuda_asum_fltILj1EEvPfS0_
	.p2align	3, 0x0
_Z13cuda_asum_fltILj1EEvPfS0_:
	.quad	_Z28__device_stub__cuda_asum_fltILj1EEvPfS0_
	.size	_Z13cuda_asum_fltILj1EEvPfS0_, 8

	.type	_Z14cuda_asum_doubILj512EEvPdS0_,@object # @_Z14cuda_asum_doubILj512EEvPdS0_
	.section	.rodata._Z14cuda_asum_doubILj512EEvPdS0_,"aG",@progbits,_Z14cuda_asum_doubILj512EEvPdS0_,comdat
	.weak	_Z14cuda_asum_doubILj512EEvPdS0_
	.p2align	3, 0x0
_Z14cuda_asum_doubILj512EEvPdS0_:
	.quad	_Z29__device_stub__cuda_asum_doubILj512EEvPdS0_
	.size	_Z14cuda_asum_doubILj512EEvPdS0_, 8

	.type	_Z14cuda_asum_doubILj256EEvPdS0_,@object # @_Z14cuda_asum_doubILj256EEvPdS0_
	.section	.rodata._Z14cuda_asum_doubILj256EEvPdS0_,"aG",@progbits,_Z14cuda_asum_doubILj256EEvPdS0_,comdat
	.weak	_Z14cuda_asum_doubILj256EEvPdS0_
	.p2align	3, 0x0
_Z14cuda_asum_doubILj256EEvPdS0_:
	.quad	_Z29__device_stub__cuda_asum_doubILj256EEvPdS0_
	.size	_Z14cuda_asum_doubILj256EEvPdS0_, 8

	.type	_Z14cuda_asum_doubILj128EEvPdS0_,@object # @_Z14cuda_asum_doubILj128EEvPdS0_
	.section	.rodata._Z14cuda_asum_doubILj128EEvPdS0_,"aG",@progbits,_Z14cuda_asum_doubILj128EEvPdS0_,comdat
	.weak	_Z14cuda_asum_doubILj128EEvPdS0_
	.p2align	3, 0x0
_Z14cuda_asum_doubILj128EEvPdS0_:
	.quad	_Z29__device_stub__cuda_asum_doubILj128EEvPdS0_
	.size	_Z14cuda_asum_doubILj128EEvPdS0_, 8

	.type	_Z14cuda_asum_doubILj64EEvPdS0_,@object # @_Z14cuda_asum_doubILj64EEvPdS0_
	.section	.rodata._Z14cuda_asum_doubILj64EEvPdS0_,"aG",@progbits,_Z14cuda_asum_doubILj64EEvPdS0_,comdat
	.weak	_Z14cuda_asum_doubILj64EEvPdS0_
	.p2align	3, 0x0
_Z14cuda_asum_doubILj64EEvPdS0_:
	.quad	_Z29__device_stub__cuda_asum_doubILj64EEvPdS0_
	.size	_Z14cuda_asum_doubILj64EEvPdS0_, 8

	.type	_Z14cuda_asum_doubILj32EEvPdS0_,@object # @_Z14cuda_asum_doubILj32EEvPdS0_
	.section	.rodata._Z14cuda_asum_doubILj32EEvPdS0_,"aG",@progbits,_Z14cuda_asum_doubILj32EEvPdS0_,comdat
	.weak	_Z14cuda_asum_doubILj32EEvPdS0_
	.p2align	3, 0x0
_Z14cuda_asum_doubILj32EEvPdS0_:
	.quad	_Z29__device_stub__cuda_asum_doubILj32EEvPdS0_
	.size	_Z14cuda_asum_doubILj32EEvPdS0_, 8

	.type	_Z14cuda_asum_doubILj16EEvPdS0_,@object # @_Z14cuda_asum_doubILj16EEvPdS0_
	.section	.rodata._Z14cuda_asum_doubILj16EEvPdS0_,"aG",@progbits,_Z14cuda_asum_doubILj16EEvPdS0_,comdat
	.weak	_Z14cuda_asum_doubILj16EEvPdS0_
	.p2align	3, 0x0
_Z14cuda_asum_doubILj16EEvPdS0_:
	.quad	_Z29__device_stub__cuda_asum_doubILj16EEvPdS0_
	.size	_Z14cuda_asum_doubILj16EEvPdS0_, 8

	.type	_Z14cuda_asum_doubILj8EEvPdS0_,@object # @_Z14cuda_asum_doubILj8EEvPdS0_
	.section	.rodata._Z14cuda_asum_doubILj8EEvPdS0_,"aG",@progbits,_Z14cuda_asum_doubILj8EEvPdS0_,comdat
	.weak	_Z14cuda_asum_doubILj8EEvPdS0_
	.p2align	3, 0x0
_Z14cuda_asum_doubILj8EEvPdS0_:
	.quad	_Z29__device_stub__cuda_asum_doubILj8EEvPdS0_
	.size	_Z14cuda_asum_doubILj8EEvPdS0_, 8

	.type	_Z14cuda_asum_doubILj4EEvPdS0_,@object # @_Z14cuda_asum_doubILj4EEvPdS0_
	.section	.rodata._Z14cuda_asum_doubILj4EEvPdS0_,"aG",@progbits,_Z14cuda_asum_doubILj4EEvPdS0_,comdat
	.weak	_Z14cuda_asum_doubILj4EEvPdS0_
	.p2align	3, 0x0
_Z14cuda_asum_doubILj4EEvPdS0_:
	.quad	_Z29__device_stub__cuda_asum_doubILj4EEvPdS0_
	.size	_Z14cuda_asum_doubILj4EEvPdS0_, 8

	.type	_Z14cuda_asum_doubILj2EEvPdS0_,@object # @_Z14cuda_asum_doubILj2EEvPdS0_
	.section	.rodata._Z14cuda_asum_doubILj2EEvPdS0_,"aG",@progbits,_Z14cuda_asum_doubILj2EEvPdS0_,comdat
	.weak	_Z14cuda_asum_doubILj2EEvPdS0_
	.p2align	3, 0x0
_Z14cuda_asum_doubILj2EEvPdS0_:
	.quad	_Z29__device_stub__cuda_asum_doubILj2EEvPdS0_
	.size	_Z14cuda_asum_doubILj2EEvPdS0_, 8

	.type	_Z14cuda_asum_doubILj1EEvPdS0_,@object # @_Z14cuda_asum_doubILj1EEvPdS0_
	.section	.rodata._Z14cuda_asum_doubILj1EEvPdS0_,"aG",@progbits,_Z14cuda_asum_doubILj1EEvPdS0_,comdat
	.weak	_Z14cuda_asum_doubILj1EEvPdS0_
	.p2align	3, 0x0
_Z14cuda_asum_doubILj1EEvPdS0_:
	.quad	_Z29__device_stub__cuda_asum_doubILj1EEvPdS0_
	.size	_Z14cuda_asum_doubILj1EEvPdS0_, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z13cuda_asum_intILj512EEvPiS0_"
	.size	.L__unnamed_1, 32

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z13cuda_asum_intILj256EEvPiS0_"
	.size	.L__unnamed_2, 32

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z13cuda_asum_intILj128EEvPiS0_"
	.size	.L__unnamed_3, 32

	.type	.L__unnamed_4,@object           # @3
.L__unnamed_4:
	.asciz	"_Z13cuda_asum_intILj64EEvPiS0_"
	.size	.L__unnamed_4, 31

	.type	.L__unnamed_5,@object           # @4
.L__unnamed_5:
	.asciz	"_Z13cuda_asum_intILj32EEvPiS0_"
	.size	.L__unnamed_5, 31

	.type	.L__unnamed_6,@object           # @5
.L__unnamed_6:
	.asciz	"_Z13cuda_asum_intILj16EEvPiS0_"
	.size	.L__unnamed_6, 31

	.type	.L__unnamed_7,@object           # @6
.L__unnamed_7:
	.asciz	"_Z13cuda_asum_intILj8EEvPiS0_"
	.size	.L__unnamed_7, 30

	.type	.L__unnamed_8,@object           # @7
.L__unnamed_8:
	.asciz	"_Z13cuda_asum_intILj4EEvPiS0_"
	.size	.L__unnamed_8, 30

	.type	.L__unnamed_9,@object           # @8
.L__unnamed_9:
	.asciz	"_Z13cuda_asum_intILj2EEvPiS0_"
	.size	.L__unnamed_9, 30

	.type	.L__unnamed_10,@object          # @9
.L__unnamed_10:
	.asciz	"_Z13cuda_asum_intILj1EEvPiS0_"
	.size	.L__unnamed_10, 30

	.type	.L__unnamed_11,@object          # @10
.L__unnamed_11:
	.asciz	"_Z13cuda_asum_fltILj1024EEvPfS0_"
	.size	.L__unnamed_11, 33

	.type	.L__unnamed_12,@object          # @11
.L__unnamed_12:
	.asciz	"_Z13cuda_asum_fltILj512EEvPfS0_"
	.size	.L__unnamed_12, 32

	.type	.L__unnamed_13,@object          # @12
.L__unnamed_13:
	.asciz	"_Z13cuda_asum_fltILj256EEvPfS0_"
	.size	.L__unnamed_13, 32

	.type	.L__unnamed_14,@object          # @13
.L__unnamed_14:
	.asciz	"_Z13cuda_asum_fltILj128EEvPfS0_"
	.size	.L__unnamed_14, 32

	.type	.L__unnamed_15,@object          # @14
.L__unnamed_15:
	.asciz	"_Z13cuda_asum_fltILj64EEvPfS0_"
	.size	.L__unnamed_15, 31

	.type	.L__unnamed_16,@object          # @15
.L__unnamed_16:
	.asciz	"_Z13cuda_asum_fltILj32EEvPfS0_"
	.size	.L__unnamed_16, 31

	.type	.L__unnamed_17,@object          # @16
.L__unnamed_17:
	.asciz	"_Z13cuda_asum_fltILj16EEvPfS0_"
	.size	.L__unnamed_17, 31

	.type	.L__unnamed_18,@object          # @17
.L__unnamed_18:
	.asciz	"_Z13cuda_asum_fltILj8EEvPfS0_"
	.size	.L__unnamed_18, 30

	.type	.L__unnamed_19,@object          # @18
.L__unnamed_19:
	.asciz	"_Z13cuda_asum_fltILj4EEvPfS0_"
	.size	.L__unnamed_19, 30

	.type	.L__unnamed_20,@object          # @19
.L__unnamed_20:
	.asciz	"_Z13cuda_asum_fltILj2EEvPfS0_"
	.size	.L__unnamed_20, 30

	.type	.L__unnamed_21,@object          # @20
.L__unnamed_21:
	.asciz	"_Z13cuda_asum_fltILj1EEvPfS0_"
	.size	.L__unnamed_21, 30

	.type	.L__unnamed_22,@object          # @21
.L__unnamed_22:
	.asciz	"_Z14cuda_asum_doubILj512EEvPdS0_"
	.size	.L__unnamed_22, 33

	.type	.L__unnamed_23,@object          # @22
.L__unnamed_23:
	.asciz	"_Z14cuda_asum_doubILj256EEvPdS0_"
	.size	.L__unnamed_23, 33

	.type	.L__unnamed_24,@object          # @23
.L__unnamed_24:
	.asciz	"_Z14cuda_asum_doubILj128EEvPdS0_"
	.size	.L__unnamed_24, 33

	.type	.L__unnamed_25,@object          # @24
.L__unnamed_25:
	.asciz	"_Z14cuda_asum_doubILj64EEvPdS0_"
	.size	.L__unnamed_25, 32

	.type	.L__unnamed_26,@object          # @25
.L__unnamed_26:
	.asciz	"_Z14cuda_asum_doubILj32EEvPdS0_"
	.size	.L__unnamed_26, 32

	.type	.L__unnamed_27,@object          # @26
.L__unnamed_27:
	.asciz	"_Z14cuda_asum_doubILj16EEvPdS0_"
	.size	.L__unnamed_27, 32

	.type	.L__unnamed_28,@object          # @27
.L__unnamed_28:
	.asciz	"_Z14cuda_asum_doubILj8EEvPdS0_"
	.size	.L__unnamed_28, 31

	.type	.L__unnamed_29,@object          # @28
.L__unnamed_29:
	.asciz	"_Z14cuda_asum_doubILj4EEvPdS0_"
	.size	.L__unnamed_29, 31

	.type	.L__unnamed_30,@object          # @29
.L__unnamed_30:
	.asciz	"_Z14cuda_asum_doubILj2EEvPdS0_"
	.size	.L__unnamed_30, 31

	.type	.L__unnamed_31,@object          # @30
.L__unnamed_31:
	.asciz	"_Z14cuda_asum_doubILj1EEvPdS0_"
	.size	.L__unnamed_31, 31

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z28__device_stub__cuda_asum_intILj512EEvPiS0_
	.addrsig_sym _Z28__device_stub__cuda_asum_intILj256EEvPiS0_
	.addrsig_sym _Z28__device_stub__cuda_asum_intILj128EEvPiS0_
	.addrsig_sym _Z28__device_stub__cuda_asum_intILj64EEvPiS0_
	.addrsig_sym _Z28__device_stub__cuda_asum_intILj32EEvPiS0_
	.addrsig_sym _Z28__device_stub__cuda_asum_intILj16EEvPiS0_
	.addrsig_sym _Z28__device_stub__cuda_asum_intILj8EEvPiS0_
	.addrsig_sym _Z28__device_stub__cuda_asum_intILj4EEvPiS0_
	.addrsig_sym _Z28__device_stub__cuda_asum_intILj2EEvPiS0_
	.addrsig_sym _Z28__device_stub__cuda_asum_intILj1EEvPiS0_
	.addrsig_sym _Z28__device_stub__cuda_asum_fltILj1024EEvPfS0_
	.addrsig_sym _Z28__device_stub__cuda_asum_fltILj512EEvPfS0_
	.addrsig_sym _Z28__device_stub__cuda_asum_fltILj256EEvPfS0_
	.addrsig_sym _Z28__device_stub__cuda_asum_fltILj128EEvPfS0_
	.addrsig_sym _Z28__device_stub__cuda_asum_fltILj64EEvPfS0_
	.addrsig_sym _Z28__device_stub__cuda_asum_fltILj32EEvPfS0_
	.addrsig_sym _Z28__device_stub__cuda_asum_fltILj16EEvPfS0_
	.addrsig_sym _Z28__device_stub__cuda_asum_fltILj8EEvPfS0_
	.addrsig_sym _Z28__device_stub__cuda_asum_fltILj4EEvPfS0_
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	.addrsig_sym _Z29__device_stub__cuda_asum_doubILj128EEvPdS0_
	.addrsig_sym _Z29__device_stub__cuda_asum_doubILj64EEvPdS0_
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	.addrsig_sym _Z29__device_stub__cuda_asum_doubILj8EEvPdS0_
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	.addrsig_sym __hip_module_dtor
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	.addrsig_sym _Z13cuda_asum_intILj256EEvPiS0_
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	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.section	.text._Z13cuda_asum_intILj512EEvPiS0_,"axG",@progbits,_Z13cuda_asum_intILj512EEvPiS0_,comdat
	.protected	_Z13cuda_asum_intILj512EEvPiS0_ ; -- Begin function _Z13cuda_asum_intILj512EEvPiS0_
	.globl	_Z13cuda_asum_intILj512EEvPiS0_
	.p2align	8
	.type	_Z13cuda_asum_intILj512EEvPiS0_,@function
_Z13cuda_asum_intILj512EEvPiS0_:        ; @_Z13cuda_asum_intILj512EEvPiS0_
; %bb.0:
	s_clause 0x1
	s_load_b32 s5, s[0:1], 0x1c
	s_load_b128 s[0:3], s[0:1], 0x0
	s_mov_b32 s4, s15
	s_waitcnt lgkmcnt(0)
	s_and_b32 s5, s5, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s6, s15, s5
	v_lshl_add_u32 v1, s6, 1, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[1:2]
	v_add_nc_u32_e32 v1, s5, v1
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v3, vcc_lo, s0, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	s_clause 0x1
	global_load_b32 v3, v[3:4], off
	global_load_b32 v2, v[1:2], off
	v_lshl_add_u32 v1, v0, 2, 0
	s_mov_b32 s0, exec_lo
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v2, v2, v3
	ds_store_b32 v1, v2
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 0x100, v0
	s_cbranch_execz .LBB0_2
; %bb.1:
	ds_load_2addr_stride64_b32 v[2:3], v1 offset1:4
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v2, v2, v3
	ds_store_b32 v1, v2
.LBB0_2:
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 0x80, v0
	s_cbranch_execz .LBB0_4
; %bb.3:
	ds_load_b32 v2, v1 offset:512
	ds_load_b32 v3, v1
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v2, v3, v2
	ds_store_b32 v1, v2
.LBB0_4:
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 64, v0
	s_cbranch_execz .LBB0_6
; %bb.5:
	ds_load_b32 v2, v1 offset:256
	ds_load_b32 v3, v1
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v2, v3, v2
	ds_store_b32 v1, v2
.LBB0_6:
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v0
	s_cbranch_execz .LBB0_8
; %bb.7:
	ds_load_b32 v8, v1 offset:128
	ds_load_2addr_b32 v[2:3], v1 offset1:1
	ds_load_2addr_b32 v[4:5], v1 offset0:8 offset1:16
	ds_load_2addr_b32 v[6:7], v1 offset0:2 offset1:4
	s_waitcnt lgkmcnt(1)
	v_add3_u32 v2, v2, v8, v5
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v2, v4, v2, v7
	v_add3_u32 v2, v6, v2, v3
	ds_store_b32 v1, v2
.LBB0_8:
	s_or_b32 exec_lo, exec_lo, s0
	s_mov_b32 s5, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB0_10
; %bb.9:
	v_mov_b32_e32 v0, 0
	s_lshl_b64 s[0:1], s[4:5], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s0, s2, s0
	s_addc_u32 s1, s3, s1
	ds_load_b32 v1, v0
	s_waitcnt lgkmcnt(0)
	global_store_b32 v0, v1, s[0:1]
.LBB0_10:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z13cuda_asum_intILj512EEvPiS0_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 9
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z13cuda_asum_intILj512EEvPiS0_,"axG",@progbits,_Z13cuda_asum_intILj512EEvPiS0_,comdat
.Lfunc_end0:
	.size	_Z13cuda_asum_intILj512EEvPiS0_, .Lfunc_end0-_Z13cuda_asum_intILj512EEvPiS0_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 536
; NumSgprs: 18
; NumVgprs: 9
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 9
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.section	.text._Z13cuda_asum_intILj256EEvPiS0_,"axG",@progbits,_Z13cuda_asum_intILj256EEvPiS0_,comdat
	.protected	_Z13cuda_asum_intILj256EEvPiS0_ ; -- Begin function _Z13cuda_asum_intILj256EEvPiS0_
	.globl	_Z13cuda_asum_intILj256EEvPiS0_
	.p2align	8
	.type	_Z13cuda_asum_intILj256EEvPiS0_,@function
_Z13cuda_asum_intILj256EEvPiS0_:        ; @_Z13cuda_asum_intILj256EEvPiS0_
; %bb.0:
	s_clause 0x1
	s_load_b32 s5, s[0:1], 0x1c
	s_load_b128 s[0:3], s[0:1], 0x0
	s_mov_b32 s4, s15
	s_waitcnt lgkmcnt(0)
	s_and_b32 s5, s5, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s6, s15, s5
	v_lshl_add_u32 v1, s6, 1, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[1:2]
	v_add_nc_u32_e32 v1, s5, v1
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v3, vcc_lo, s0, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	s_clause 0x1
	global_load_b32 v3, v[3:4], off
	global_load_b32 v2, v[1:2], off
	v_lshl_add_u32 v1, v0, 2, 0
	s_mov_b32 s0, exec_lo
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v2, v2, v3
	ds_store_b32 v1, v2
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 0x80, v0
	s_cbranch_execz .LBB1_2
; %bb.1:
	ds_load_2addr_stride64_b32 v[2:3], v1 offset1:2
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v2, v2, v3
	ds_store_b32 v1, v2
.LBB1_2:
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 64, v0
	s_cbranch_execz .LBB1_4
; %bb.3:
	ds_load_b32 v2, v1 offset:256
	ds_load_b32 v3, v1
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v2, v3, v2
	ds_store_b32 v1, v2
.LBB1_4:
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v0
	s_cbranch_execz .LBB1_6
; %bb.5:
	ds_load_b32 v8, v1 offset:128
	ds_load_2addr_b32 v[2:3], v1 offset1:1
	ds_load_2addr_b32 v[4:5], v1 offset0:8 offset1:16
	ds_load_2addr_b32 v[6:7], v1 offset0:2 offset1:4
	s_waitcnt lgkmcnt(1)
	v_add3_u32 v2, v2, v8, v5
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v2, v4, v2, v7
	v_add3_u32 v2, v6, v2, v3
	ds_store_b32 v1, v2
.LBB1_6:
	s_or_b32 exec_lo, exec_lo, s0
	s_mov_b32 s5, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB1_8
; %bb.7:
	v_mov_b32_e32 v0, 0
	s_lshl_b64 s[0:1], s[4:5], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s0, s2, s0
	s_addc_u32 s1, s3, s1
	ds_load_b32 v1, v0
	s_waitcnt lgkmcnt(0)
	global_store_b32 v0, v1, s[0:1]
.LBB1_8:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z13cuda_asum_intILj256EEvPiS0_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 9
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z13cuda_asum_intILj256EEvPiS0_,"axG",@progbits,_Z13cuda_asum_intILj256EEvPiS0_,comdat
.Lfunc_end1:
	.size	_Z13cuda_asum_intILj256EEvPiS0_, .Lfunc_end1-_Z13cuda_asum_intILj256EEvPiS0_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 464
; NumSgprs: 18
; NumVgprs: 9
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 9
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.section	.text._Z13cuda_asum_intILj128EEvPiS0_,"axG",@progbits,_Z13cuda_asum_intILj128EEvPiS0_,comdat
	.protected	_Z13cuda_asum_intILj128EEvPiS0_ ; -- Begin function _Z13cuda_asum_intILj128EEvPiS0_
	.globl	_Z13cuda_asum_intILj128EEvPiS0_
	.p2align	8
	.type	_Z13cuda_asum_intILj128EEvPiS0_,@function
_Z13cuda_asum_intILj128EEvPiS0_:        ; @_Z13cuda_asum_intILj128EEvPiS0_
; %bb.0:
	s_clause 0x1
	s_load_b32 s5, s[0:1], 0x1c
	s_load_b128 s[0:3], s[0:1], 0x0
	s_mov_b32 s4, s15
	s_waitcnt lgkmcnt(0)
	s_and_b32 s5, s5, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s6, s15, s5
	v_lshl_add_u32 v1, s6, 1, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[1:2]
	v_add_nc_u32_e32 v1, s5, v1
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v3, vcc_lo, s0, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	s_clause 0x1
	global_load_b32 v3, v[3:4], off
	global_load_b32 v2, v[1:2], off
	v_lshl_add_u32 v1, v0, 2, 0
	s_mov_b32 s0, exec_lo
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v2, v2, v3
	ds_store_b32 v1, v2
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 64, v0
	s_cbranch_execz .LBB2_2
; %bb.1:
	ds_load_2addr_stride64_b32 v[2:3], v1 offset1:1
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v2, v2, v3
	ds_store_b32 v1, v2
.LBB2_2:
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v0
	s_cbranch_execz .LBB2_4
; %bb.3:
	ds_load_b32 v8, v1 offset:128
	ds_load_2addr_b32 v[2:3], v1 offset1:1
	ds_load_2addr_b32 v[4:5], v1 offset0:8 offset1:16
	ds_load_2addr_b32 v[6:7], v1 offset0:2 offset1:4
	s_waitcnt lgkmcnt(1)
	v_add3_u32 v2, v2, v8, v5
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v2, v4, v2, v7
	v_add3_u32 v2, v6, v2, v3
	ds_store_b32 v1, v2
.LBB2_4:
	s_or_b32 exec_lo, exec_lo, s0
	s_mov_b32 s5, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB2_6
; %bb.5:
	v_mov_b32_e32 v0, 0
	s_lshl_b64 s[0:1], s[4:5], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s0, s2, s0
	s_addc_u32 s1, s3, s1
	ds_load_b32 v1, v0
	s_waitcnt lgkmcnt(0)
	global_store_b32 v0, v1, s[0:1]
.LBB2_6:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z13cuda_asum_intILj128EEvPiS0_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 9
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z13cuda_asum_intILj128EEvPiS0_,"axG",@progbits,_Z13cuda_asum_intILj128EEvPiS0_,comdat
.Lfunc_end2:
	.size	_Z13cuda_asum_intILj128EEvPiS0_, .Lfunc_end2-_Z13cuda_asum_intILj128EEvPiS0_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 392
; NumSgprs: 18
; NumVgprs: 9
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 9
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.section	.text._Z13cuda_asum_intILj64EEvPiS0_,"axG",@progbits,_Z13cuda_asum_intILj64EEvPiS0_,comdat
	.protected	_Z13cuda_asum_intILj64EEvPiS0_ ; -- Begin function _Z13cuda_asum_intILj64EEvPiS0_
	.globl	_Z13cuda_asum_intILj64EEvPiS0_
	.p2align	8
	.type	_Z13cuda_asum_intILj64EEvPiS0_,@function
_Z13cuda_asum_intILj64EEvPiS0_:         ; @_Z13cuda_asum_intILj64EEvPiS0_
; %bb.0:
	s_clause 0x1
	s_load_b32 s5, s[0:1], 0x1c
	s_load_b128 s[0:3], s[0:1], 0x0
	s_mov_b32 s4, s15
	s_waitcnt lgkmcnt(0)
	s_and_b32 s5, s5, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s6, s15, s5
	v_lshl_add_u32 v1, s6, 1, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[1:2]
	v_add_nc_u32_e32 v1, s5, v1
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v3, vcc_lo, s0, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	s_clause 0x1
	global_load_b32 v3, v[3:4], off
	global_load_b32 v2, v[1:2], off
	v_lshl_add_u32 v1, v0, 2, 0
	s_mov_b32 s0, exec_lo
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v2, v2, v3
	ds_store_b32 v1, v2
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v0
	s_cbranch_execz .LBB3_2
; %bb.1:
	ds_load_b32 v8, v1 offset:128
	ds_load_2addr_b32 v[2:3], v1 offset1:1
	ds_load_2addr_b32 v[4:5], v1 offset0:8 offset1:16
	ds_load_2addr_b32 v[6:7], v1 offset0:2 offset1:4
	s_waitcnt lgkmcnt(1)
	v_add3_u32 v2, v2, v8, v5
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v2, v4, v2, v7
	v_add3_u32 v2, v6, v2, v3
	ds_store_b32 v1, v2
.LBB3_2:
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB3_4
; %bb.3:
	v_mov_b32_e32 v0, 0
	s_mov_b32 s5, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[0:1], s[4:5], 2
	s_add_u32 s0, s2, s0
	ds_load_b32 v1, v0
	s_addc_u32 s1, s3, s1
	s_waitcnt lgkmcnt(0)
	global_store_b32 v0, v1, s[0:1]
.LBB3_4:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z13cuda_asum_intILj64EEvPiS0_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 9
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z13cuda_asum_intILj64EEvPiS0_,"axG",@progbits,_Z13cuda_asum_intILj64EEvPiS0_,comdat
.Lfunc_end3:
	.size	_Z13cuda_asum_intILj64EEvPiS0_, .Lfunc_end3-_Z13cuda_asum_intILj64EEvPiS0_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 336
; NumSgprs: 18
; NumVgprs: 9
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 9
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.section	.text._Z13cuda_asum_intILj32EEvPiS0_,"axG",@progbits,_Z13cuda_asum_intILj32EEvPiS0_,comdat
	.protected	_Z13cuda_asum_intILj32EEvPiS0_ ; -- Begin function _Z13cuda_asum_intILj32EEvPiS0_
	.globl	_Z13cuda_asum_intILj32EEvPiS0_
	.p2align	8
	.type	_Z13cuda_asum_intILj32EEvPiS0_,@function
_Z13cuda_asum_intILj32EEvPiS0_:         ; @_Z13cuda_asum_intILj32EEvPiS0_
; %bb.0:
	s_clause 0x1
	s_load_b32 s5, s[0:1], 0x1c
	s_load_b128 s[0:3], s[0:1], 0x0
	s_mov_b32 s4, s15
	s_waitcnt lgkmcnt(0)
	s_and_b32 s5, s5, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s6, s15, s5
	v_lshl_add_u32 v1, s6, 1, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[1:2]
	v_add_nc_u32_e32 v1, s5, v1
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v3, vcc_lo, s0, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	s_clause 0x1
	global_load_b32 v3, v[3:4], off
	global_load_b32 v2, v[1:2], off
	v_lshl_add_u32 v1, v0, 2, 0
	s_mov_b32 s0, exec_lo
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v2, v2, v3
	ds_store_b32 v1, v2
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v0
	s_cbranch_execz .LBB4_2
; %bb.1:
	ds_load_2addr_b32 v[2:3], v1 offset0:8 offset1:16
	ds_load_2addr_b32 v[4:5], v1 offset1:1
	ds_load_2addr_b32 v[6:7], v1 offset0:2 offset1:4
	s_waitcnt lgkmcnt(1)
	v_add_nc_u32_e32 v3, v4, v3
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v2, v2, v3, v7
	v_add3_u32 v2, v6, v2, v5
	ds_store_b32 v1, v2
.LBB4_2:
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB4_4
; %bb.3:
	v_mov_b32_e32 v0, 0
	s_mov_b32 s5, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[0:1], s[4:5], 2
	s_add_u32 s0, s2, s0
	ds_load_b32 v1, v0
	s_addc_u32 s1, s3, s1
	s_waitcnt lgkmcnt(0)
	global_store_b32 v0, v1, s[0:1]
.LBB4_4:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z13cuda_asum_intILj32EEvPiS0_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 8
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z13cuda_asum_intILj32EEvPiS0_,"axG",@progbits,_Z13cuda_asum_intILj32EEvPiS0_,comdat
.Lfunc_end4:
	.size	_Z13cuda_asum_intILj32EEvPiS0_, .Lfunc_end4-_Z13cuda_asum_intILj32EEvPiS0_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 324
; NumSgprs: 18
; NumVgprs: 8
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 8
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.section	.text._Z13cuda_asum_intILj16EEvPiS0_,"axG",@progbits,_Z13cuda_asum_intILj16EEvPiS0_,comdat
	.protected	_Z13cuda_asum_intILj16EEvPiS0_ ; -- Begin function _Z13cuda_asum_intILj16EEvPiS0_
	.globl	_Z13cuda_asum_intILj16EEvPiS0_
	.p2align	8
	.type	_Z13cuda_asum_intILj16EEvPiS0_,@function
_Z13cuda_asum_intILj16EEvPiS0_:         ; @_Z13cuda_asum_intILj16EEvPiS0_
; %bb.0:
	s_clause 0x1
	s_load_b32 s5, s[0:1], 0x1c
	s_load_b128 s[0:3], s[0:1], 0x0
	s_mov_b32 s4, s15
	s_waitcnt lgkmcnt(0)
	s_and_b32 s5, s5, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s6, s15, s5
	v_lshl_add_u32 v1, s6, 1, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[1:2]
	v_add_nc_u32_e32 v1, s5, v1
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v3, vcc_lo, s0, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	s_clause 0x1
	global_load_b32 v3, v[3:4], off
	global_load_b32 v2, v[1:2], off
	v_lshl_add_u32 v1, v0, 2, 0
	s_mov_b32 s0, exec_lo
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v2, v2, v3
	ds_store_b32 v1, v2
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v0
	s_cbranch_execz .LBB5_2
; %bb.1:
	ds_load_2addr_b32 v[2:3], v1 offset0:2 offset1:4
	ds_load_b32 v6, v1 offset:32
	ds_load_2addr_b32 v[4:5], v1 offset1:1
	s_waitcnt lgkmcnt(0)
	v_add3_u32 v3, v4, v6, v3
	s_delay_alu instid0(VALU_DEP_1)
	v_add3_u32 v2, v2, v3, v5
	ds_store_b32 v1, v2
.LBB5_2:
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB5_4
; %bb.3:
	v_mov_b32_e32 v0, 0
	s_mov_b32 s5, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[0:1], s[4:5], 2
	s_add_u32 s0, s2, s0
	ds_load_b32 v1, v0
	s_addc_u32 s1, s3, s1
	s_waitcnt lgkmcnt(0)
	global_store_b32 v0, v1, s[0:1]
.LBB5_4:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z13cuda_asum_intILj16EEvPiS0_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 7
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z13cuda_asum_intILj16EEvPiS0_,"axG",@progbits,_Z13cuda_asum_intILj16EEvPiS0_,comdat
.Lfunc_end5:
	.size	_Z13cuda_asum_intILj16EEvPiS0_, .Lfunc_end5-_Z13cuda_asum_intILj16EEvPiS0_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 316
; NumSgprs: 18
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.section	.text._Z13cuda_asum_intILj8EEvPiS0_,"axG",@progbits,_Z13cuda_asum_intILj8EEvPiS0_,comdat
	.protected	_Z13cuda_asum_intILj8EEvPiS0_ ; -- Begin function _Z13cuda_asum_intILj8EEvPiS0_
	.globl	_Z13cuda_asum_intILj8EEvPiS0_
	.p2align	8
	.type	_Z13cuda_asum_intILj8EEvPiS0_,@function
_Z13cuda_asum_intILj8EEvPiS0_:          ; @_Z13cuda_asum_intILj8EEvPiS0_
; %bb.0:
	s_clause 0x1
	s_load_b32 s5, s[0:1], 0x1c
	s_load_b128 s[0:3], s[0:1], 0x0
	s_mov_b32 s4, s15
	s_waitcnt lgkmcnt(0)
	s_and_b32 s5, s5, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s6, s15, s5
	v_lshl_add_u32 v1, s6, 1, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[1:2]
	v_add_nc_u32_e32 v1, s5, v1
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v3, vcc_lo, s0, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	s_clause 0x1
	global_load_b32 v3, v[3:4], off
	global_load_b32 v2, v[1:2], off
	v_lshl_add_u32 v1, v0, 2, 0
	s_mov_b32 s0, exec_lo
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v2, v2, v3
	ds_store_b32 v1, v2
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v0
	s_cbranch_execz .LBB6_2
; %bb.1:
	ds_load_2addr_b32 v[2:3], v1 offset0:2 offset1:4
	ds_load_2addr_b32 v[4:5], v1 offset1:1
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v3, v4, v3
	s_delay_alu instid0(VALU_DEP_1)
	v_add3_u32 v2, v2, v3, v5
	ds_store_b32 v1, v2
.LBB6_2:
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB6_4
; %bb.3:
	v_mov_b32_e32 v0, 0
	s_mov_b32 s5, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[0:1], s[4:5], 2
	s_add_u32 s0, s2, s0
	ds_load_b32 v1, v0
	s_addc_u32 s1, s3, s1
	s_waitcnt lgkmcnt(0)
	global_store_b32 v0, v1, s[0:1]
.LBB6_4:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z13cuda_asum_intILj8EEvPiS0_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 6
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z13cuda_asum_intILj8EEvPiS0_,"axG",@progbits,_Z13cuda_asum_intILj8EEvPiS0_,comdat
.Lfunc_end6:
	.size	_Z13cuda_asum_intILj8EEvPiS0_, .Lfunc_end6-_Z13cuda_asum_intILj8EEvPiS0_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 304
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.section	.text._Z13cuda_asum_intILj4EEvPiS0_,"axG",@progbits,_Z13cuda_asum_intILj4EEvPiS0_,comdat
	.protected	_Z13cuda_asum_intILj4EEvPiS0_ ; -- Begin function _Z13cuda_asum_intILj4EEvPiS0_
	.globl	_Z13cuda_asum_intILj4EEvPiS0_
	.p2align	8
	.type	_Z13cuda_asum_intILj4EEvPiS0_,@function
_Z13cuda_asum_intILj4EEvPiS0_:          ; @_Z13cuda_asum_intILj4EEvPiS0_
; %bb.0:
	s_clause 0x1
	s_load_b32 s5, s[0:1], 0x1c
	s_load_b128 s[0:3], s[0:1], 0x0
	s_mov_b32 s4, s15
	s_waitcnt lgkmcnt(0)
	s_and_b32 s5, s5, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s6, s15, s5
	v_lshl_add_u32 v1, s6, 1, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[1:2]
	v_add_nc_u32_e32 v1, s5, v1
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v3, vcc_lo, s0, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	s_clause 0x1
	global_load_b32 v3, v[3:4], off
	global_load_b32 v2, v[1:2], off
	v_lshl_add_u32 v1, v0, 2, 0
	s_mov_b32 s0, exec_lo
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v2, v2, v3
	ds_store_b32 v1, v2
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v0
	s_cbranch_execz .LBB7_2
; %bb.1:
	ds_load_b32 v4, v1 offset:8
	ds_load_2addr_b32 v[2:3], v1 offset1:1
	s_waitcnt lgkmcnt(0)
	v_add3_u32 v2, v2, v4, v3
	ds_store_b32 v1, v2
.LBB7_2:
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB7_4
; %bb.3:
	v_mov_b32_e32 v0, 0
	s_mov_b32 s5, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[0:1], s[4:5], 2
	s_add_u32 s0, s2, s0
	ds_load_b32 v1, v0
	s_addc_u32 s1, s3, s1
	s_waitcnt lgkmcnt(0)
	global_store_b32 v0, v1, s[0:1]
.LBB7_4:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z13cuda_asum_intILj4EEvPiS0_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 5
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z13cuda_asum_intILj4EEvPiS0_,"axG",@progbits,_Z13cuda_asum_intILj4EEvPiS0_,comdat
.Lfunc_end7:
	.size	_Z13cuda_asum_intILj4EEvPiS0_, .Lfunc_end7-_Z13cuda_asum_intILj4EEvPiS0_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 296
; NumSgprs: 18
; NumVgprs: 5
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 5
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.section	.text._Z13cuda_asum_intILj2EEvPiS0_,"axG",@progbits,_Z13cuda_asum_intILj2EEvPiS0_,comdat
	.protected	_Z13cuda_asum_intILj2EEvPiS0_ ; -- Begin function _Z13cuda_asum_intILj2EEvPiS0_
	.globl	_Z13cuda_asum_intILj2EEvPiS0_
	.p2align	8
	.type	_Z13cuda_asum_intILj2EEvPiS0_,@function
_Z13cuda_asum_intILj2EEvPiS0_:          ; @_Z13cuda_asum_intILj2EEvPiS0_
; %bb.0:
	s_clause 0x1
	s_load_b32 s5, s[0:1], 0x1c
	s_load_b128 s[0:3], s[0:1], 0x0
	s_mov_b32 s4, s15
	s_waitcnt lgkmcnt(0)
	s_and_b32 s5, s5, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s6, s15, s5
	v_lshl_add_u32 v1, s6, 1, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[1:2]
	v_add_nc_u32_e32 v1, s5, v1
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v3, vcc_lo, s0, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	s_clause 0x1
	global_load_b32 v3, v[3:4], off
	global_load_b32 v2, v[1:2], off
	v_lshl_add_u32 v1, v0, 2, 0
	s_mov_b32 s0, exec_lo
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v2, v2, v3
	ds_store_b32 v1, v2
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v0
	s_cbranch_execz .LBB8_2
; %bb.1:
	ds_load_2addr_b32 v[2:3], v1 offset1:1
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v2, v2, v3
	ds_store_b32 v1, v2
.LBB8_2:
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB8_4
; %bb.3:
	v_mov_b32_e32 v0, 0
	s_mov_b32 s5, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[0:1], s[4:5], 2
	s_add_u32 s0, s2, s0
	ds_load_b32 v1, v0
	s_addc_u32 s1, s3, s1
	s_waitcnt lgkmcnt(0)
	global_store_b32 v0, v1, s[0:1]
.LBB8_4:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z13cuda_asum_intILj2EEvPiS0_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 5
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z13cuda_asum_intILj2EEvPiS0_,"axG",@progbits,_Z13cuda_asum_intILj2EEvPiS0_,comdat
.Lfunc_end8:
	.size	_Z13cuda_asum_intILj2EEvPiS0_, .Lfunc_end8-_Z13cuda_asum_intILj2EEvPiS0_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 284
; NumSgprs: 18
; NumVgprs: 5
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 5
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.section	.text._Z13cuda_asum_intILj1EEvPiS0_,"axG",@progbits,_Z13cuda_asum_intILj1EEvPiS0_,comdat
	.protected	_Z13cuda_asum_intILj1EEvPiS0_ ; -- Begin function _Z13cuda_asum_intILj1EEvPiS0_
	.globl	_Z13cuda_asum_intILj1EEvPiS0_
	.p2align	8
	.type	_Z13cuda_asum_intILj1EEvPiS0_,@function
_Z13cuda_asum_intILj1EEvPiS0_:          ; @_Z13cuda_asum_intILj1EEvPiS0_
; %bb.0:
	s_clause 0x1
	s_load_b32 s5, s[0:1], 0x1c
	s_load_b128 s[0:3], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s5, s5, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s6, s15, s5
	v_lshl_add_u32 v1, s6, 1, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[1:2]
	v_add_nc_u32_e32 v1, s5, v1
	s_mov_b32 s5, 0
	v_lshlrev_b64 v[5:6], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v3, vcc_lo, s0, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v5, vcc_lo, s0, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, s1, v6, vcc_lo
	s_clause 0x1
	global_load_b32 v1, v[3:4], off
	global_load_b32 v3, v[5:6], off
	v_lshl_add_u32 v4, v0, 2, 0
	s_mov_b32 s0, exec_lo
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v1, v3, v1
	ds_store_b32 v4, v1
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB9_2
; %bb.1:
	ds_load_b32 v0, v2
	s_mov_b32 s4, s15
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[0:1], s[4:5], 2
	s_add_u32 s0, s2, s0
	s_addc_u32 s1, s3, s1
	s_waitcnt lgkmcnt(0)
	global_store_b32 v2, v0, s[0:1]
.LBB9_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z13cuda_asum_intILj1EEvPiS0_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 7
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z13cuda_asum_intILj1EEvPiS0_,"axG",@progbits,_Z13cuda_asum_intILj1EEvPiS0_,comdat
.Lfunc_end9:
	.size	_Z13cuda_asum_intILj1EEvPiS0_, .Lfunc_end9-_Z13cuda_asum_intILj1EEvPiS0_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 236
; NumSgprs: 18
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.section	.text._Z13cuda_asum_fltILj1024EEvPfS0_,"axG",@progbits,_Z13cuda_asum_fltILj1024EEvPfS0_,comdat
	.protected	_Z13cuda_asum_fltILj1024EEvPfS0_ ; -- Begin function _Z13cuda_asum_fltILj1024EEvPfS0_
	.globl	_Z13cuda_asum_fltILj1024EEvPfS0_
	.p2align	8
	.type	_Z13cuda_asum_fltILj1024EEvPfS0_,@function
_Z13cuda_asum_fltILj1024EEvPfS0_:       ; @_Z13cuda_asum_fltILj1024EEvPfS0_
; %bb.0:
	s_clause 0x1
	s_load_b32 s5, s[0:1], 0x1c
	s_load_b128 s[0:3], s[0:1], 0x0
	s_mov_b32 s4, s15
	s_waitcnt lgkmcnt(0)
	s_and_b32 s5, s5, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s6, s15, s5
	v_lshl_add_u32 v1, s6, 1, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[1:2]
	v_add_nc_u32_e32 v1, s5, v1
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v3, vcc_lo, s0, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	s_clause 0x1
	global_load_b32 v3, v[3:4], off
	global_load_b32 v2, v[1:2], off
	v_lshl_add_u32 v1, v0, 2, 0
	s_mov_b32 s0, exec_lo
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v2, v3, v2
	ds_store_b32 v1, v2
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 0x200, v0
	s_cbranch_execz .LBB10_2
; %bb.1:
	ds_load_2addr_stride64_b32 v[2:3], v1 offset1:8
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v2, v3, v2
	ds_store_b32 v1, v2
.LBB10_2:
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 0x100, v0
	s_cbranch_execz .LBB10_4
; %bb.3:
	ds_load_b32 v2, v1 offset:1024
	ds_load_b32 v3, v1
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v2, v2, v3
	ds_store_b32 v1, v2
.LBB10_4:
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 0x80, v0
	s_cbranch_execz .LBB10_6
; %bb.5:
	ds_load_b32 v2, v1 offset:512
	ds_load_b32 v3, v1
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v2, v2, v3
	ds_store_b32 v1, v2
.LBB10_6:
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 64, v0
	s_cbranch_execz .LBB10_8
; %bb.7:
	ds_load_b32 v2, v1 offset:256
	ds_load_b32 v3, v1
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v2, v2, v3
	ds_store_b32 v1, v2
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_2addr_b32 v[2:3], v1 offset1:32
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v2, v3, v2
	ds_store_b32 v1, v2
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_2addr_b32 v[2:3], v1 offset1:16
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v2, v3, v2
	ds_store_b32 v1, v2
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_2addr_b32 v[2:3], v1 offset1:8
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v2, v3, v2
	ds_store_b32 v1, v2
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_2addr_b32 v[2:3], v1 offset1:4
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v2, v3, v2
	ds_store_b32 v1, v2
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_2addr_b32 v[2:3], v1 offset1:2
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v2, v3, v2
	ds_store_b32 v1, v2
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_2addr_b32 v[2:3], v1 offset1:1
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v2, v3, v2
	ds_store_b32 v1, v2
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
.LBB10_8:
	s_or_b32 exec_lo, exec_lo, s0
	s_mov_b32 s5, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB10_10
; %bb.9:
	v_mov_b32_e32 v0, 0
	s_lshl_b64 s[0:1], s[4:5], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s0, s2, s0
	s_addc_u32 s1, s3, s1
	ds_load_b32 v1, v0
	s_waitcnt lgkmcnt(0)
	global_store_b32 v0, v1, s[0:1]
.LBB10_10:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z13cuda_asum_fltILj1024EEvPfS0_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 5
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z13cuda_asum_fltILj1024EEvPfS0_,"axG",@progbits,_Z13cuda_asum_fltILj1024EEvPfS0_,comdat
.Lfunc_end10:
	.size	_Z13cuda_asum_fltILj1024EEvPfS0_, .Lfunc_end10-_Z13cuda_asum_fltILj1024EEvPfS0_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 752
; NumSgprs: 18
; NumVgprs: 5
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 5
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.section	.text._Z13cuda_asum_fltILj512EEvPfS0_,"axG",@progbits,_Z13cuda_asum_fltILj512EEvPfS0_,comdat
	.protected	_Z13cuda_asum_fltILj512EEvPfS0_ ; -- Begin function _Z13cuda_asum_fltILj512EEvPfS0_
	.globl	_Z13cuda_asum_fltILj512EEvPfS0_
	.p2align	8
	.type	_Z13cuda_asum_fltILj512EEvPfS0_,@function
_Z13cuda_asum_fltILj512EEvPfS0_:        ; @_Z13cuda_asum_fltILj512EEvPfS0_
; %bb.0:
	s_clause 0x1
	s_load_b32 s5, s[0:1], 0x1c
	s_load_b128 s[0:3], s[0:1], 0x0
	s_mov_b32 s4, s15
	s_waitcnt lgkmcnt(0)
	s_and_b32 s5, s5, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s6, s15, s5
	v_lshl_add_u32 v1, s6, 1, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[1:2]
	v_add_nc_u32_e32 v1, s5, v1
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v3, vcc_lo, s0, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	s_clause 0x1
	global_load_b32 v3, v[3:4], off
	global_load_b32 v2, v[1:2], off
	v_lshl_add_u32 v1, v0, 2, 0
	s_mov_b32 s0, exec_lo
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v2, v3, v2
	ds_store_b32 v1, v2
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 0x100, v0
	s_cbranch_execz .LBB11_2
; %bb.1:
	ds_load_2addr_stride64_b32 v[2:3], v1 offset1:4
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v2, v3, v2
	ds_store_b32 v1, v2
.LBB11_2:
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 0x80, v0
	s_cbranch_execz .LBB11_4
; %bb.3:
	ds_load_b32 v2, v1 offset:512
	ds_load_b32 v3, v1
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v2, v2, v3
	ds_store_b32 v1, v2
.LBB11_4:
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 64, v0
	s_cbranch_execz .LBB11_6
; %bb.5:
	ds_load_b32 v2, v1 offset:256
	ds_load_b32 v3, v1
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v2, v2, v3
	ds_store_b32 v1, v2
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_2addr_b32 v[2:3], v1 offset1:32
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v2, v3, v2
	ds_store_b32 v1, v2
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_2addr_b32 v[2:3], v1 offset1:16
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v2, v3, v2
	ds_store_b32 v1, v2
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_2addr_b32 v[2:3], v1 offset1:8
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v2, v3, v2
	ds_store_b32 v1, v2
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_2addr_b32 v[2:3], v1 offset1:4
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v2, v3, v2
	ds_store_b32 v1, v2
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_2addr_b32 v[2:3], v1 offset1:2
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v2, v3, v2
	ds_store_b32 v1, v2
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_2addr_b32 v[2:3], v1 offset1:1
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v2, v3, v2
	ds_store_b32 v1, v2
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
.LBB11_6:
	s_or_b32 exec_lo, exec_lo, s0
	s_mov_b32 s5, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB11_8
; %bb.7:
	v_mov_b32_e32 v0, 0
	s_lshl_b64 s[0:1], s[4:5], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s0, s2, s0
	s_addc_u32 s1, s3, s1
	ds_load_b32 v1, v0
	s_waitcnt lgkmcnt(0)
	global_store_b32 v0, v1, s[0:1]
.LBB11_8:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z13cuda_asum_fltILj512EEvPfS0_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 5
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z13cuda_asum_fltILj512EEvPfS0_,"axG",@progbits,_Z13cuda_asum_fltILj512EEvPfS0_,comdat
.Lfunc_end11:
	.size	_Z13cuda_asum_fltILj512EEvPfS0_, .Lfunc_end11-_Z13cuda_asum_fltILj512EEvPfS0_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 680
; NumSgprs: 18
; NumVgprs: 5
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 5
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.section	.text._Z13cuda_asum_fltILj256EEvPfS0_,"axG",@progbits,_Z13cuda_asum_fltILj256EEvPfS0_,comdat
	.protected	_Z13cuda_asum_fltILj256EEvPfS0_ ; -- Begin function _Z13cuda_asum_fltILj256EEvPfS0_
	.globl	_Z13cuda_asum_fltILj256EEvPfS0_
	.p2align	8
	.type	_Z13cuda_asum_fltILj256EEvPfS0_,@function
_Z13cuda_asum_fltILj256EEvPfS0_:        ; @_Z13cuda_asum_fltILj256EEvPfS0_
; %bb.0:
	s_clause 0x1
	s_load_b32 s5, s[0:1], 0x1c
	s_load_b128 s[0:3], s[0:1], 0x0
	s_mov_b32 s4, s15
	s_waitcnt lgkmcnt(0)
	s_and_b32 s5, s5, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s6, s15, s5
	v_lshl_add_u32 v1, s6, 1, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[1:2]
	v_add_nc_u32_e32 v1, s5, v1
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v3, vcc_lo, s0, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	s_clause 0x1
	global_load_b32 v3, v[3:4], off
	global_load_b32 v2, v[1:2], off
	v_lshl_add_u32 v1, v0, 2, 0
	s_mov_b32 s0, exec_lo
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v2, v3, v2
	ds_store_b32 v1, v2
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 0x80, v0
	s_cbranch_execz .LBB12_2
; %bb.1:
	ds_load_2addr_stride64_b32 v[2:3], v1 offset1:2
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v2, v3, v2
	ds_store_b32 v1, v2
.LBB12_2:
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 64, v0
	s_cbranch_execz .LBB12_4
; %bb.3:
	ds_load_b32 v2, v1 offset:256
	ds_load_b32 v3, v1
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v2, v2, v3
	ds_store_b32 v1, v2
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_2addr_b32 v[2:3], v1 offset1:32
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v2, v3, v2
	ds_store_b32 v1, v2
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_2addr_b32 v[2:3], v1 offset1:16
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v2, v3, v2
	ds_store_b32 v1, v2
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_2addr_b32 v[2:3], v1 offset1:8
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v2, v3, v2
	ds_store_b32 v1, v2
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_2addr_b32 v[2:3], v1 offset1:4
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v2, v3, v2
	ds_store_b32 v1, v2
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_2addr_b32 v[2:3], v1 offset1:2
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v2, v3, v2
	ds_store_b32 v1, v2
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_2addr_b32 v[2:3], v1 offset1:1
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v2, v3, v2
	ds_store_b32 v1, v2
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
.LBB12_4:
	s_or_b32 exec_lo, exec_lo, s0
	s_mov_b32 s5, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB12_6
; %bb.5:
	v_mov_b32_e32 v0, 0
	s_lshl_b64 s[0:1], s[4:5], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s0, s2, s0
	s_addc_u32 s1, s3, s1
	ds_load_b32 v1, v0
	s_waitcnt lgkmcnt(0)
	global_store_b32 v0, v1, s[0:1]
.LBB12_6:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z13cuda_asum_fltILj256EEvPfS0_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 5
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z13cuda_asum_fltILj256EEvPfS0_,"axG",@progbits,_Z13cuda_asum_fltILj256EEvPfS0_,comdat
.Lfunc_end12:
	.size	_Z13cuda_asum_fltILj256EEvPfS0_, .Lfunc_end12-_Z13cuda_asum_fltILj256EEvPfS0_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 608
; NumSgprs: 18
; NumVgprs: 5
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 5
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.section	.text._Z13cuda_asum_fltILj128EEvPfS0_,"axG",@progbits,_Z13cuda_asum_fltILj128EEvPfS0_,comdat
	.protected	_Z13cuda_asum_fltILj128EEvPfS0_ ; -- Begin function _Z13cuda_asum_fltILj128EEvPfS0_
	.globl	_Z13cuda_asum_fltILj128EEvPfS0_
	.p2align	8
	.type	_Z13cuda_asum_fltILj128EEvPfS0_,@function
_Z13cuda_asum_fltILj128EEvPfS0_:        ; @_Z13cuda_asum_fltILj128EEvPfS0_
; %bb.0:
	s_clause 0x1
	s_load_b32 s5, s[0:1], 0x1c
	s_load_b128 s[0:3], s[0:1], 0x0
	s_mov_b32 s4, s15
	s_waitcnt lgkmcnt(0)
	s_and_b32 s5, s5, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s6, s15, s5
	v_lshl_add_u32 v1, s6, 1, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[1:2]
	v_add_nc_u32_e32 v1, s5, v1
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v3, vcc_lo, s0, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	s_clause 0x1
	global_load_b32 v3, v[3:4], off
	global_load_b32 v2, v[1:2], off
	v_lshl_add_u32 v1, v0, 2, 0
	s_mov_b32 s0, exec_lo
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v2, v3, v2
	ds_store_b32 v1, v2
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 64, v0
	s_cbranch_execz .LBB13_2
; %bb.1:
	ds_load_2addr_stride64_b32 v[2:3], v1 offset1:1
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v2, v3, v2
	ds_store_b32 v1, v2
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_2addr_b32 v[2:3], v1 offset1:32
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v2, v3, v2
	ds_store_b32 v1, v2
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_2addr_b32 v[2:3], v1 offset1:16
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v2, v3, v2
	ds_store_b32 v1, v2
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_2addr_b32 v[2:3], v1 offset1:8
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v2, v3, v2
	ds_store_b32 v1, v2
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_2addr_b32 v[2:3], v1 offset1:4
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v2, v3, v2
	ds_store_b32 v1, v2
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_2addr_b32 v[2:3], v1 offset1:2
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v2, v3, v2
	ds_store_b32 v1, v2
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_2addr_b32 v[2:3], v1 offset1:1
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v2, v3, v2
	ds_store_b32 v1, v2
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
.LBB13_2:
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB13_4
; %bb.3:
	v_mov_b32_e32 v0, 0
	s_mov_b32 s5, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[0:1], s[4:5], 2
	s_add_u32 s0, s2, s0
	ds_load_b32 v1, v0
	s_addc_u32 s1, s3, s1
	s_waitcnt lgkmcnt(0)
	global_store_b32 v0, v1, s[0:1]
.LBB13_4:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z13cuda_asum_fltILj128EEvPfS0_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 5
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z13cuda_asum_fltILj128EEvPfS0_,"axG",@progbits,_Z13cuda_asum_fltILj128EEvPfS0_,comdat
.Lfunc_end13:
	.size	_Z13cuda_asum_fltILj128EEvPfS0_, .Lfunc_end13-_Z13cuda_asum_fltILj128EEvPfS0_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 540
; NumSgprs: 18
; NumVgprs: 5
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 5
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.section	.text._Z13cuda_asum_fltILj64EEvPfS0_,"axG",@progbits,_Z13cuda_asum_fltILj64EEvPfS0_,comdat
	.protected	_Z13cuda_asum_fltILj64EEvPfS0_ ; -- Begin function _Z13cuda_asum_fltILj64EEvPfS0_
	.globl	_Z13cuda_asum_fltILj64EEvPfS0_
	.p2align	8
	.type	_Z13cuda_asum_fltILj64EEvPfS0_,@function
_Z13cuda_asum_fltILj64EEvPfS0_:         ; @_Z13cuda_asum_fltILj64EEvPfS0_
; %bb.0:
	s_clause 0x1
	s_load_b32 s5, s[0:1], 0x1c
	s_load_b128 s[0:3], s[0:1], 0x0
	s_mov_b32 s4, s15
	s_waitcnt lgkmcnt(0)
	s_and_b32 s5, s5, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s6, s15, s5
	v_lshl_add_u32 v1, s6, 1, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[1:2]
	v_add_nc_u32_e32 v1, s5, v1
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v3, vcc_lo, s0, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	s_clause 0x1
	global_load_b32 v3, v[3:4], off
	global_load_b32 v2, v[1:2], off
	v_lshl_add_u32 v1, v0, 2, 0
	s_mov_b32 s0, exec_lo
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v2, v3, v2
	ds_store_b32 v1, v2
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 64, v0
	s_cbranch_execz .LBB14_2
; %bb.1:
	s_barrier
	buffer_gl0_inv
	ds_load_2addr_b32 v[2:3], v1 offset1:32
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v2, v3, v2
	ds_store_b32 v1, v2
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_2addr_b32 v[2:3], v1 offset1:16
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v2, v3, v2
	ds_store_b32 v1, v2
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_2addr_b32 v[2:3], v1 offset1:8
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v2, v3, v2
	ds_store_b32 v1, v2
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_2addr_b32 v[2:3], v1 offset1:4
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v2, v3, v2
	ds_store_b32 v1, v2
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_2addr_b32 v[2:3], v1 offset1:2
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v2, v3, v2
	ds_store_b32 v1, v2
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_2addr_b32 v[2:3], v1 offset1:1
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v2, v3, v2
	ds_store_b32 v1, v2
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
.LBB14_2:
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB14_4
; %bb.3:
	v_mov_b32_e32 v0, 0
	s_mov_b32 s5, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[0:1], s[4:5], 2
	s_add_u32 s0, s2, s0
	ds_load_b32 v1, v0
	s_addc_u32 s1, s3, s1
	s_waitcnt lgkmcnt(0)
	global_store_b32 v0, v1, s[0:1]
.LBB14_4:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z13cuda_asum_fltILj64EEvPfS0_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 5
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z13cuda_asum_fltILj64EEvPfS0_,"axG",@progbits,_Z13cuda_asum_fltILj64EEvPfS0_,comdat
.Lfunc_end14:
	.size	_Z13cuda_asum_fltILj64EEvPfS0_, .Lfunc_end14-_Z13cuda_asum_fltILj64EEvPfS0_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 512
; NumSgprs: 18
; NumVgprs: 5
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 5
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.section	.text._Z13cuda_asum_fltILj32EEvPfS0_,"axG",@progbits,_Z13cuda_asum_fltILj32EEvPfS0_,comdat
	.protected	_Z13cuda_asum_fltILj32EEvPfS0_ ; -- Begin function _Z13cuda_asum_fltILj32EEvPfS0_
	.globl	_Z13cuda_asum_fltILj32EEvPfS0_
	.p2align	8
	.type	_Z13cuda_asum_fltILj32EEvPfS0_,@function
_Z13cuda_asum_fltILj32EEvPfS0_:         ; @_Z13cuda_asum_fltILj32EEvPfS0_
; %bb.0:
	s_clause 0x1
	s_load_b32 s5, s[0:1], 0x1c
	s_load_b128 s[0:3], s[0:1], 0x0
	s_mov_b32 s4, s15
	s_waitcnt lgkmcnt(0)
	s_and_b32 s5, s5, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s6, s15, s5
	v_lshl_add_u32 v1, s6, 1, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[1:2]
	v_add_nc_u32_e32 v1, s5, v1
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v3, vcc_lo, s0, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	s_clause 0x1
	global_load_b32 v3, v[3:4], off
	global_load_b32 v2, v[1:2], off
	v_lshl_add_u32 v1, v0, 2, 0
	s_mov_b32 s0, exec_lo
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v2, v3, v2
	ds_store_b32 v1, v2
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 64, v0
	s_cbranch_execz .LBB15_2
; %bb.1:
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	ds_load_2addr_b32 v[2:3], v1 offset1:16
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v2, v3, v2
	ds_store_b32 v1, v2
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_2addr_b32 v[2:3], v1 offset1:8
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v2, v3, v2
	ds_store_b32 v1, v2
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_2addr_b32 v[2:3], v1 offset1:4
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v2, v3, v2
	ds_store_b32 v1, v2
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_2addr_b32 v[2:3], v1 offset1:2
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v2, v3, v2
	ds_store_b32 v1, v2
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_2addr_b32 v[2:3], v1 offset1:1
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v2, v3, v2
	ds_store_b32 v1, v2
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
.LBB15_2:
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB15_4
; %bb.3:
	v_mov_b32_e32 v0, 0
	s_mov_b32 s5, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[0:1], s[4:5], 2
	s_add_u32 s0, s2, s0
	ds_load_b32 v1, v0
	s_addc_u32 s1, s3, s1
	s_waitcnt lgkmcnt(0)
	global_store_b32 v0, v1, s[0:1]
.LBB15_4:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z13cuda_asum_fltILj32EEvPfS0_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 5
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z13cuda_asum_fltILj32EEvPfS0_,"axG",@progbits,_Z13cuda_asum_fltILj32EEvPfS0_,comdat
.Lfunc_end15:
	.size	_Z13cuda_asum_fltILj32EEvPfS0_, .Lfunc_end15-_Z13cuda_asum_fltILj32EEvPfS0_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 484
; NumSgprs: 18
; NumVgprs: 5
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 5
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.section	.text._Z13cuda_asum_fltILj16EEvPfS0_,"axG",@progbits,_Z13cuda_asum_fltILj16EEvPfS0_,comdat
	.protected	_Z13cuda_asum_fltILj16EEvPfS0_ ; -- Begin function _Z13cuda_asum_fltILj16EEvPfS0_
	.globl	_Z13cuda_asum_fltILj16EEvPfS0_
	.p2align	8
	.type	_Z13cuda_asum_fltILj16EEvPfS0_,@function
_Z13cuda_asum_fltILj16EEvPfS0_:         ; @_Z13cuda_asum_fltILj16EEvPfS0_
; %bb.0:
	s_clause 0x1
	s_load_b32 s5, s[0:1], 0x1c
	s_load_b128 s[0:3], s[0:1], 0x0
	s_mov_b32 s4, s15
	s_waitcnt lgkmcnt(0)
	s_and_b32 s5, s5, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s6, s15, s5
	v_lshl_add_u32 v1, s6, 1, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[1:2]
	v_add_nc_u32_e32 v1, s5, v1
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v3, vcc_lo, s0, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	s_clause 0x1
	global_load_b32 v3, v[3:4], off
	global_load_b32 v2, v[1:2], off
	v_lshl_add_u32 v1, v0, 2, 0
	s_mov_b32 s0, exec_lo
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v2, v3, v2
	ds_store_b32 v1, v2
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 64, v0
	s_cbranch_execz .LBB16_2
; %bb.1:
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	ds_load_2addr_b32 v[2:3], v1 offset1:8
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v2, v3, v2
	ds_store_b32 v1, v2
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_2addr_b32 v[2:3], v1 offset1:4
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v2, v3, v2
	ds_store_b32 v1, v2
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_2addr_b32 v[2:3], v1 offset1:2
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v2, v3, v2
	ds_store_b32 v1, v2
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_2addr_b32 v[2:3], v1 offset1:1
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v2, v3, v2
	ds_store_b32 v1, v2
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
.LBB16_2:
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB16_4
; %bb.3:
	v_mov_b32_e32 v0, 0
	s_mov_b32 s5, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[0:1], s[4:5], 2
	s_add_u32 s0, s2, s0
	ds_load_b32 v1, v0
	s_addc_u32 s1, s3, s1
	s_waitcnt lgkmcnt(0)
	global_store_b32 v0, v1, s[0:1]
.LBB16_4:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z13cuda_asum_fltILj16EEvPfS0_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 5
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z13cuda_asum_fltILj16EEvPfS0_,"axG",@progbits,_Z13cuda_asum_fltILj16EEvPfS0_,comdat
.Lfunc_end16:
	.size	_Z13cuda_asum_fltILj16EEvPfS0_, .Lfunc_end16-_Z13cuda_asum_fltILj16EEvPfS0_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 456
; NumSgprs: 18
; NumVgprs: 5
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 5
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.section	.text._Z13cuda_asum_fltILj8EEvPfS0_,"axG",@progbits,_Z13cuda_asum_fltILj8EEvPfS0_,comdat
	.protected	_Z13cuda_asum_fltILj8EEvPfS0_ ; -- Begin function _Z13cuda_asum_fltILj8EEvPfS0_
	.globl	_Z13cuda_asum_fltILj8EEvPfS0_
	.p2align	8
	.type	_Z13cuda_asum_fltILj8EEvPfS0_,@function
_Z13cuda_asum_fltILj8EEvPfS0_:          ; @_Z13cuda_asum_fltILj8EEvPfS0_
; %bb.0:
	s_clause 0x1
	s_load_b32 s5, s[0:1], 0x1c
	s_load_b128 s[0:3], s[0:1], 0x0
	s_mov_b32 s4, s15
	s_waitcnt lgkmcnt(0)
	s_and_b32 s5, s5, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s6, s15, s5
	v_lshl_add_u32 v1, s6, 1, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[1:2]
	v_add_nc_u32_e32 v1, s5, v1
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v3, vcc_lo, s0, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	s_clause 0x1
	global_load_b32 v3, v[3:4], off
	global_load_b32 v2, v[1:2], off
	v_lshl_add_u32 v1, v0, 2, 0
	s_mov_b32 s0, exec_lo
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v2, v3, v2
	ds_store_b32 v1, v2
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 64, v0
	s_cbranch_execz .LBB17_2
; %bb.1:
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	ds_load_2addr_b32 v[2:3], v1 offset1:4
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v2, v3, v2
	ds_store_b32 v1, v2
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_2addr_b32 v[2:3], v1 offset1:2
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v2, v3, v2
	ds_store_b32 v1, v2
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_2addr_b32 v[2:3], v1 offset1:1
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v2, v3, v2
	ds_store_b32 v1, v2
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
.LBB17_2:
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB17_4
; %bb.3:
	v_mov_b32_e32 v0, 0
	s_mov_b32 s5, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[0:1], s[4:5], 2
	s_add_u32 s0, s2, s0
	ds_load_b32 v1, v0
	s_addc_u32 s1, s3, s1
	s_waitcnt lgkmcnt(0)
	global_store_b32 v0, v1, s[0:1]
.LBB17_4:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z13cuda_asum_fltILj8EEvPfS0_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 5
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z13cuda_asum_fltILj8EEvPfS0_,"axG",@progbits,_Z13cuda_asum_fltILj8EEvPfS0_,comdat
.Lfunc_end17:
	.size	_Z13cuda_asum_fltILj8EEvPfS0_, .Lfunc_end17-_Z13cuda_asum_fltILj8EEvPfS0_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 428
; NumSgprs: 18
; NumVgprs: 5
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 5
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.section	.text._Z13cuda_asum_fltILj4EEvPfS0_,"axG",@progbits,_Z13cuda_asum_fltILj4EEvPfS0_,comdat
	.protected	_Z13cuda_asum_fltILj4EEvPfS0_ ; -- Begin function _Z13cuda_asum_fltILj4EEvPfS0_
	.globl	_Z13cuda_asum_fltILj4EEvPfS0_
	.p2align	8
	.type	_Z13cuda_asum_fltILj4EEvPfS0_,@function
_Z13cuda_asum_fltILj4EEvPfS0_:          ; @_Z13cuda_asum_fltILj4EEvPfS0_
; %bb.0:
	s_clause 0x1
	s_load_b32 s5, s[0:1], 0x1c
	s_load_b128 s[0:3], s[0:1], 0x0
	s_mov_b32 s4, s15
	s_waitcnt lgkmcnt(0)
	s_and_b32 s5, s5, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s6, s15, s5
	v_lshl_add_u32 v1, s6, 1, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[1:2]
	v_add_nc_u32_e32 v1, s5, v1
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v3, vcc_lo, s0, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	s_clause 0x1
	global_load_b32 v3, v[3:4], off
	global_load_b32 v2, v[1:2], off
	v_lshl_add_u32 v1, v0, 2, 0
	s_mov_b32 s0, exec_lo
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v2, v3, v2
	ds_store_b32 v1, v2
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 64, v0
	s_cbranch_execz .LBB18_2
; %bb.1:
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	ds_load_2addr_b32 v[2:3], v1 offset1:2
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v2, v3, v2
	ds_store_b32 v1, v2
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_2addr_b32 v[2:3], v1 offset1:1
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v2, v3, v2
	ds_store_b32 v1, v2
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
.LBB18_2:
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB18_4
; %bb.3:
	v_mov_b32_e32 v0, 0
	s_mov_b32 s5, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[0:1], s[4:5], 2
	s_add_u32 s0, s2, s0
	ds_load_b32 v1, v0
	s_addc_u32 s1, s3, s1
	s_waitcnt lgkmcnt(0)
	global_store_b32 v0, v1, s[0:1]
.LBB18_4:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z13cuda_asum_fltILj4EEvPfS0_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 5
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z13cuda_asum_fltILj4EEvPfS0_,"axG",@progbits,_Z13cuda_asum_fltILj4EEvPfS0_,comdat
.Lfunc_end18:
	.size	_Z13cuda_asum_fltILj4EEvPfS0_, .Lfunc_end18-_Z13cuda_asum_fltILj4EEvPfS0_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 400
; NumSgprs: 18
; NumVgprs: 5
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 5
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.section	.text._Z13cuda_asum_fltILj2EEvPfS0_,"axG",@progbits,_Z13cuda_asum_fltILj2EEvPfS0_,comdat
	.protected	_Z13cuda_asum_fltILj2EEvPfS0_ ; -- Begin function _Z13cuda_asum_fltILj2EEvPfS0_
	.globl	_Z13cuda_asum_fltILj2EEvPfS0_
	.p2align	8
	.type	_Z13cuda_asum_fltILj2EEvPfS0_,@function
_Z13cuda_asum_fltILj2EEvPfS0_:          ; @_Z13cuda_asum_fltILj2EEvPfS0_
; %bb.0:
	s_clause 0x1
	s_load_b32 s5, s[0:1], 0x1c
	s_load_b128 s[0:3], s[0:1], 0x0
	s_mov_b32 s4, s15
	s_waitcnt lgkmcnt(0)
	s_and_b32 s5, s5, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s6, s15, s5
	v_lshl_add_u32 v1, s6, 1, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[1:2]
	v_add_nc_u32_e32 v1, s5, v1
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v3, vcc_lo, s0, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	s_clause 0x1
	global_load_b32 v3, v[3:4], off
	global_load_b32 v2, v[1:2], off
	v_lshl_add_u32 v1, v0, 2, 0
	s_mov_b32 s0, exec_lo
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v2, v3, v2
	ds_store_b32 v1, v2
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 64, v0
	s_cbranch_execz .LBB19_2
; %bb.1:
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	ds_load_2addr_b32 v[2:3], v1 offset1:1
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v2, v3, v2
	ds_store_b32 v1, v2
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
.LBB19_2:
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB19_4
; %bb.3:
	v_mov_b32_e32 v0, 0
	s_mov_b32 s5, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[0:1], s[4:5], 2
	s_add_u32 s0, s2, s0
	ds_load_b32 v1, v0
	s_addc_u32 s1, s3, s1
	s_waitcnt lgkmcnt(0)
	global_store_b32 v0, v1, s[0:1]
.LBB19_4:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z13cuda_asum_fltILj2EEvPfS0_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 5
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z13cuda_asum_fltILj2EEvPfS0_,"axG",@progbits,_Z13cuda_asum_fltILj2EEvPfS0_,comdat
.Lfunc_end19:
	.size	_Z13cuda_asum_fltILj2EEvPfS0_, .Lfunc_end19-_Z13cuda_asum_fltILj2EEvPfS0_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 372
; NumSgprs: 18
; NumVgprs: 5
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 5
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.section	.text._Z13cuda_asum_fltILj1EEvPfS0_,"axG",@progbits,_Z13cuda_asum_fltILj1EEvPfS0_,comdat
	.protected	_Z13cuda_asum_fltILj1EEvPfS0_ ; -- Begin function _Z13cuda_asum_fltILj1EEvPfS0_
	.globl	_Z13cuda_asum_fltILj1EEvPfS0_
	.p2align	8
	.type	_Z13cuda_asum_fltILj1EEvPfS0_,@function
_Z13cuda_asum_fltILj1EEvPfS0_:          ; @_Z13cuda_asum_fltILj1EEvPfS0_
; %bb.0:
	s_clause 0x1
	s_load_b32 s5, s[0:1], 0x1c
	s_load_b128 s[0:3], s[0:1], 0x0
	s_mov_b32 s4, s15
	s_waitcnt lgkmcnt(0)
	s_and_b32 s5, s5, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s6, s15, s5
	v_lshl_add_u32 v1, s6, 1, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[1:2]
	v_add_nc_u32_e32 v1, s5, v1
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v3, vcc_lo, s0, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	s_clause 0x1
	global_load_b32 v3, v[3:4], off
	global_load_b32 v1, v[1:2], off
	v_lshl_add_u32 v2, v0, 2, 0
	s_mov_b32 s0, exec_lo
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v1, v3, v1
	ds_store_b32 v2, v1
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 64, v0
	s_cbranch_execz .LBB20_2
; %bb.1:
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
.LBB20_2:
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB20_4
; %bb.3:
	v_mov_b32_e32 v0, 0
	s_mov_b32 s5, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[0:1], s[4:5], 2
	s_add_u32 s0, s2, s0
	ds_load_b32 v1, v0
	s_addc_u32 s1, s3, s1
	s_waitcnt lgkmcnt(0)
	global_store_b32 v0, v1, s[0:1]
.LBB20_4:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z13cuda_asum_fltILj1EEvPfS0_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 5
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z13cuda_asum_fltILj1EEvPfS0_,"axG",@progbits,_Z13cuda_asum_fltILj1EEvPfS0_,comdat
.Lfunc_end20:
	.size	_Z13cuda_asum_fltILj1EEvPfS0_, .Lfunc_end20-_Z13cuda_asum_fltILj1EEvPfS0_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 344
; NumSgprs: 18
; NumVgprs: 5
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 5
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.section	.text._Z14cuda_asum_doubILj512EEvPdS0_,"axG",@progbits,_Z14cuda_asum_doubILj512EEvPdS0_,comdat
	.protected	_Z14cuda_asum_doubILj512EEvPdS0_ ; -- Begin function _Z14cuda_asum_doubILj512EEvPdS0_
	.globl	_Z14cuda_asum_doubILj512EEvPdS0_
	.p2align	8
	.type	_Z14cuda_asum_doubILj512EEvPdS0_,@function
_Z14cuda_asum_doubILj512EEvPdS0_:       ; @_Z14cuda_asum_doubILj512EEvPdS0_
; %bb.0:
	s_clause 0x1
	s_load_b32 s5, s[0:1], 0x1c
	s_load_b128 s[0:3], s[0:1], 0x0
	s_mov_b32 s4, s15
	s_waitcnt lgkmcnt(0)
	s_and_b32 s5, s5, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s6, s15, s5
	v_lshl_add_u32 v1, s6, 1, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 3, v[1:2]
	v_add_nc_u32_e32 v1, s5, v1
	v_lshlrev_b64 v[1:2], 3, v[1:2]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v3, vcc_lo, s0, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	s_clause 0x1
	global_load_b64 v[3:4], v[3:4], off
	global_load_b64 v[1:2], v[1:2], off
	s_mov_b32 s0, exec_lo
	s_waitcnt vmcnt(0)
	v_add_f64 v[2:3], v[3:4], v[1:2]
	v_lshl_add_u32 v1, v0, 3, 0
	ds_store_b64 v1, v[2:3]
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 0x100, v0
	s_cbranch_execz .LBB21_2
; %bb.1:
	ds_load_2addr_stride64_b64 v[2:5], v1 offset1:4
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[2:3], v[4:5], v[2:3]
	ds_store_b64 v1, v[2:3]
.LBB21_2:
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 0x80, v0
	s_cbranch_execz .LBB21_4
; %bb.3:
	ds_load_b64 v[2:3], v1 offset:1024
	ds_load_b64 v[4:5], v1
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[2:3], v[2:3], v[4:5]
	ds_store_b64 v1, v[2:3]
.LBB21_4:
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 64, v0
	s_cbranch_execz .LBB21_6
; %bb.5:
	ds_load_b64 v[2:3], v1 offset:512
	ds_load_b64 v[4:5], v1
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[2:3], v[2:3], v[4:5]
	ds_store_b64 v1, v[2:3]
.LBB21_6:
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v0
	s_cbranch_execz .LBB21_8
; %bb.7:
	ds_load_b64 v[6:7], v1 offset:256
	ds_load_2addr_b64 v[2:5], v1 offset1:1
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[2:3], v[6:7], v[2:3]
	ds_load_2addr_b64 v[6:9], v1 offset0:8 offset1:16
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[2:3], v[2:3], v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_add_f64 v[2:3], v[2:3], v[6:7]
	ds_load_2addr_b64 v[6:9], v1 offset0:2 offset1:4
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[2:3], v[2:3], v[8:9]
	v_add_f64 v[2:3], v[2:3], v[6:7]
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[2:3], v[2:3], v[4:5]
	ds_store_b64 v1, v[2:3]
.LBB21_8:
	s_or_b32 exec_lo, exec_lo, s0
	s_mov_b32 s5, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB21_10
; %bb.9:
	v_mov_b32_e32 v2, 0
	s_lshl_b64 s[0:1], s[4:5], 3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s0, s2, s0
	s_addc_u32 s1, s3, s1
	ds_load_b64 v[0:1], v2
	s_waitcnt lgkmcnt(0)
	global_store_b64 v2, v[0:1], s[0:1]
.LBB21_10:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z14cuda_asum_doubILj512EEvPdS0_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 10
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z14cuda_asum_doubILj512EEvPdS0_,"axG",@progbits,_Z14cuda_asum_doubILj512EEvPdS0_,comdat
.Lfunc_end21:
	.size	_Z14cuda_asum_doubILj512EEvPdS0_, .Lfunc_end21-_Z14cuda_asum_doubILj512EEvPdS0_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 584
; NumSgprs: 18
; NumVgprs: 10
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 10
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.section	.text._Z14cuda_asum_doubILj256EEvPdS0_,"axG",@progbits,_Z14cuda_asum_doubILj256EEvPdS0_,comdat
	.protected	_Z14cuda_asum_doubILj256EEvPdS0_ ; -- Begin function _Z14cuda_asum_doubILj256EEvPdS0_
	.globl	_Z14cuda_asum_doubILj256EEvPdS0_
	.p2align	8
	.type	_Z14cuda_asum_doubILj256EEvPdS0_,@function
_Z14cuda_asum_doubILj256EEvPdS0_:       ; @_Z14cuda_asum_doubILj256EEvPdS0_
; %bb.0:
	s_clause 0x1
	s_load_b32 s5, s[0:1], 0x1c
	s_load_b128 s[0:3], s[0:1], 0x0
	s_mov_b32 s4, s15
	s_waitcnt lgkmcnt(0)
	s_and_b32 s5, s5, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s6, s15, s5
	v_lshl_add_u32 v1, s6, 1, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 3, v[1:2]
	v_add_nc_u32_e32 v1, s5, v1
	v_lshlrev_b64 v[1:2], 3, v[1:2]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v3, vcc_lo, s0, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	s_clause 0x1
	global_load_b64 v[3:4], v[3:4], off
	global_load_b64 v[1:2], v[1:2], off
	s_mov_b32 s0, exec_lo
	s_waitcnt vmcnt(0)
	v_add_f64 v[2:3], v[3:4], v[1:2]
	v_lshl_add_u32 v1, v0, 3, 0
	ds_store_b64 v1, v[2:3]
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 0x80, v0
	s_cbranch_execz .LBB22_2
; %bb.1:
	ds_load_2addr_stride64_b64 v[2:5], v1 offset1:2
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[2:3], v[4:5], v[2:3]
	ds_store_b64 v1, v[2:3]
.LBB22_2:
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 64, v0
	s_cbranch_execz .LBB22_4
; %bb.3:
	ds_load_b64 v[2:3], v1 offset:512
	ds_load_b64 v[4:5], v1
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[2:3], v[2:3], v[4:5]
	ds_store_b64 v1, v[2:3]
.LBB22_4:
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v0
	s_cbranch_execz .LBB22_6
; %bb.5:
	ds_load_b64 v[6:7], v1 offset:256
	ds_load_2addr_b64 v[2:5], v1 offset1:1
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[2:3], v[6:7], v[2:3]
	ds_load_2addr_b64 v[6:9], v1 offset0:8 offset1:16
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[2:3], v[2:3], v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_add_f64 v[2:3], v[2:3], v[6:7]
	ds_load_2addr_b64 v[6:9], v1 offset0:2 offset1:4
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[2:3], v[2:3], v[8:9]
	v_add_f64 v[2:3], v[2:3], v[6:7]
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[2:3], v[2:3], v[4:5]
	ds_store_b64 v1, v[2:3]
.LBB22_6:
	s_or_b32 exec_lo, exec_lo, s0
	s_mov_b32 s5, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB22_8
; %bb.7:
	v_mov_b32_e32 v2, 0
	s_lshl_b64 s[0:1], s[4:5], 3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s0, s2, s0
	s_addc_u32 s1, s3, s1
	ds_load_b64 v[0:1], v2
	s_waitcnt lgkmcnt(0)
	global_store_b64 v2, v[0:1], s[0:1]
.LBB22_8:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z14cuda_asum_doubILj256EEvPdS0_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 10
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z14cuda_asum_doubILj256EEvPdS0_,"axG",@progbits,_Z14cuda_asum_doubILj256EEvPdS0_,comdat
.Lfunc_end22:
	.size	_Z14cuda_asum_doubILj256EEvPdS0_, .Lfunc_end22-_Z14cuda_asum_doubILj256EEvPdS0_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 508
; NumSgprs: 18
; NumVgprs: 10
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 10
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.section	.text._Z14cuda_asum_doubILj128EEvPdS0_,"axG",@progbits,_Z14cuda_asum_doubILj128EEvPdS0_,comdat
	.protected	_Z14cuda_asum_doubILj128EEvPdS0_ ; -- Begin function _Z14cuda_asum_doubILj128EEvPdS0_
	.globl	_Z14cuda_asum_doubILj128EEvPdS0_
	.p2align	8
	.type	_Z14cuda_asum_doubILj128EEvPdS0_,@function
_Z14cuda_asum_doubILj128EEvPdS0_:       ; @_Z14cuda_asum_doubILj128EEvPdS0_
; %bb.0:
	s_clause 0x1
	s_load_b32 s5, s[0:1], 0x1c
	s_load_b128 s[0:3], s[0:1], 0x0
	s_mov_b32 s4, s15
	s_waitcnt lgkmcnt(0)
	s_and_b32 s5, s5, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s6, s15, s5
	v_lshl_add_u32 v1, s6, 1, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 3, v[1:2]
	v_add_nc_u32_e32 v1, s5, v1
	v_lshlrev_b64 v[1:2], 3, v[1:2]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v3, vcc_lo, s0, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	s_clause 0x1
	global_load_b64 v[3:4], v[3:4], off
	global_load_b64 v[1:2], v[1:2], off
	s_mov_b32 s0, exec_lo
	s_waitcnt vmcnt(0)
	v_add_f64 v[2:3], v[3:4], v[1:2]
	v_lshl_add_u32 v1, v0, 3, 0
	ds_store_b64 v1, v[2:3]
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 64, v0
	s_cbranch_execz .LBB23_2
; %bb.1:
	ds_load_2addr_stride64_b64 v[2:5], v1 offset1:1
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[2:3], v[4:5], v[2:3]
	ds_store_b64 v1, v[2:3]
.LBB23_2:
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v0
	s_cbranch_execz .LBB23_4
; %bb.3:
	ds_load_b64 v[6:7], v1 offset:256
	ds_load_2addr_b64 v[2:5], v1 offset1:1
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[2:3], v[6:7], v[2:3]
	ds_load_2addr_b64 v[6:9], v1 offset0:8 offset1:16
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[2:3], v[2:3], v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_add_f64 v[2:3], v[2:3], v[6:7]
	ds_load_2addr_b64 v[6:9], v1 offset0:2 offset1:4
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[2:3], v[2:3], v[8:9]
	v_add_f64 v[2:3], v[2:3], v[6:7]
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[2:3], v[2:3], v[4:5]
	ds_store_b64 v1, v[2:3]
.LBB23_4:
	s_or_b32 exec_lo, exec_lo, s0
	s_mov_b32 s5, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB23_6
; %bb.5:
	v_mov_b32_e32 v2, 0
	s_lshl_b64 s[0:1], s[4:5], 3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s0, s2, s0
	s_addc_u32 s1, s3, s1
	ds_load_b64 v[0:1], v2
	s_waitcnt lgkmcnt(0)
	global_store_b64 v2, v[0:1], s[0:1]
.LBB23_6:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z14cuda_asum_doubILj128EEvPdS0_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 10
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z14cuda_asum_doubILj128EEvPdS0_,"axG",@progbits,_Z14cuda_asum_doubILj128EEvPdS0_,comdat
.Lfunc_end23:
	.size	_Z14cuda_asum_doubILj128EEvPdS0_, .Lfunc_end23-_Z14cuda_asum_doubILj128EEvPdS0_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 432
; NumSgprs: 18
; NumVgprs: 10
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 10
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.section	.text._Z14cuda_asum_doubILj64EEvPdS0_,"axG",@progbits,_Z14cuda_asum_doubILj64EEvPdS0_,comdat
	.protected	_Z14cuda_asum_doubILj64EEvPdS0_ ; -- Begin function _Z14cuda_asum_doubILj64EEvPdS0_
	.globl	_Z14cuda_asum_doubILj64EEvPdS0_
	.p2align	8
	.type	_Z14cuda_asum_doubILj64EEvPdS0_,@function
_Z14cuda_asum_doubILj64EEvPdS0_:        ; @_Z14cuda_asum_doubILj64EEvPdS0_
; %bb.0:
	s_clause 0x1
	s_load_b32 s5, s[0:1], 0x1c
	s_load_b128 s[0:3], s[0:1], 0x0
	s_mov_b32 s4, s15
	s_waitcnt lgkmcnt(0)
	s_and_b32 s5, s5, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s6, s15, s5
	v_lshl_add_u32 v1, s6, 1, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 3, v[1:2]
	v_add_nc_u32_e32 v1, s5, v1
	v_lshlrev_b64 v[1:2], 3, v[1:2]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v3, vcc_lo, s0, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	s_clause 0x1
	global_load_b64 v[3:4], v[3:4], off
	global_load_b64 v[1:2], v[1:2], off
	s_mov_b32 s0, exec_lo
	s_waitcnt vmcnt(0)
	v_add_f64 v[2:3], v[3:4], v[1:2]
	v_lshl_add_u32 v1, v0, 3, 0
	ds_store_b64 v1, v[2:3]
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v0
	s_cbranch_execz .LBB24_2
; %bb.1:
	ds_load_b64 v[6:7], v1 offset:256
	ds_load_2addr_b64 v[2:5], v1 offset1:1
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[2:3], v[6:7], v[2:3]
	ds_load_2addr_b64 v[6:9], v1 offset0:8 offset1:16
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[2:3], v[2:3], v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_add_f64 v[2:3], v[2:3], v[6:7]
	ds_load_2addr_b64 v[6:9], v1 offset0:2 offset1:4
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[2:3], v[2:3], v[8:9]
	v_add_f64 v[2:3], v[2:3], v[6:7]
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[2:3], v[2:3], v[4:5]
	ds_store_b64 v1, v[2:3]
.LBB24_2:
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB24_4
; %bb.3:
	v_mov_b32_e32 v2, 0
	s_mov_b32 s5, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[0:1], s[4:5], 3
	s_add_u32 s0, s2, s0
	ds_load_b64 v[0:1], v2
	s_addc_u32 s1, s3, s1
	s_waitcnt lgkmcnt(0)
	global_store_b64 v2, v[0:1], s[0:1]
.LBB24_4:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z14cuda_asum_doubILj64EEvPdS0_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 10
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z14cuda_asum_doubILj64EEvPdS0_,"axG",@progbits,_Z14cuda_asum_doubILj64EEvPdS0_,comdat
.Lfunc_end24:
	.size	_Z14cuda_asum_doubILj64EEvPdS0_, .Lfunc_end24-_Z14cuda_asum_doubILj64EEvPdS0_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 372
; NumSgprs: 18
; NumVgprs: 10
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 10
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.section	.text._Z14cuda_asum_doubILj32EEvPdS0_,"axG",@progbits,_Z14cuda_asum_doubILj32EEvPdS0_,comdat
	.protected	_Z14cuda_asum_doubILj32EEvPdS0_ ; -- Begin function _Z14cuda_asum_doubILj32EEvPdS0_
	.globl	_Z14cuda_asum_doubILj32EEvPdS0_
	.p2align	8
	.type	_Z14cuda_asum_doubILj32EEvPdS0_,@function
_Z14cuda_asum_doubILj32EEvPdS0_:        ; @_Z14cuda_asum_doubILj32EEvPdS0_
; %bb.0:
	s_clause 0x1
	s_load_b32 s5, s[0:1], 0x1c
	s_load_b128 s[0:3], s[0:1], 0x0
	s_mov_b32 s4, s15
	s_waitcnt lgkmcnt(0)
	s_and_b32 s5, s5, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s6, s15, s5
	v_lshl_add_u32 v1, s6, 1, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 3, v[1:2]
	v_add_nc_u32_e32 v1, s5, v1
	v_lshlrev_b64 v[1:2], 3, v[1:2]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v3, vcc_lo, s0, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	s_clause 0x1
	global_load_b64 v[3:4], v[3:4], off
	global_load_b64 v[1:2], v[1:2], off
	s_mov_b32 s0, exec_lo
	s_waitcnt vmcnt(0)
	v_add_f64 v[2:3], v[3:4], v[1:2]
	v_lshl_add_u32 v1, v0, 3, 0
	ds_store_b64 v1, v[2:3]
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v0
	s_cbranch_execz .LBB25_2
; %bb.1:
	ds_load_2addr_b64 v[2:5], v1 offset0:8 offset1:16
	ds_load_2addr_b64 v[6:9], v1 offset1:1
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[4:5], v[4:5], v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_add_f64 v[6:7], v[4:5], v[2:3]
	ds_load_2addr_b64 v[2:5], v1 offset0:2 offset1:4
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[4:5], v[6:7], v[4:5]
	v_add_f64 v[2:3], v[4:5], v[2:3]
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[2:3], v[2:3], v[8:9]
	ds_store_b64 v1, v[2:3]
.LBB25_2:
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB25_4
; %bb.3:
	v_mov_b32_e32 v2, 0
	s_mov_b32 s5, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[0:1], s[4:5], 3
	s_add_u32 s0, s2, s0
	ds_load_b64 v[0:1], v2
	s_addc_u32 s1, s3, s1
	s_waitcnt lgkmcnt(0)
	global_store_b64 v2, v[0:1], s[0:1]
.LBB25_4:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z14cuda_asum_doubILj32EEvPdS0_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 10
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z14cuda_asum_doubILj32EEvPdS0_,"axG",@progbits,_Z14cuda_asum_doubILj32EEvPdS0_,comdat
.Lfunc_end25:
	.size	_Z14cuda_asum_doubILj32EEvPdS0_, .Lfunc_end25-_Z14cuda_asum_doubILj32EEvPdS0_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 352
; NumSgprs: 18
; NumVgprs: 10
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 10
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.section	.text._Z14cuda_asum_doubILj16EEvPdS0_,"axG",@progbits,_Z14cuda_asum_doubILj16EEvPdS0_,comdat
	.protected	_Z14cuda_asum_doubILj16EEvPdS0_ ; -- Begin function _Z14cuda_asum_doubILj16EEvPdS0_
	.globl	_Z14cuda_asum_doubILj16EEvPdS0_
	.p2align	8
	.type	_Z14cuda_asum_doubILj16EEvPdS0_,@function
_Z14cuda_asum_doubILj16EEvPdS0_:        ; @_Z14cuda_asum_doubILj16EEvPdS0_
; %bb.0:
	s_clause 0x1
	s_load_b32 s5, s[0:1], 0x1c
	s_load_b128 s[0:3], s[0:1], 0x0
	s_mov_b32 s4, s15
	s_waitcnt lgkmcnt(0)
	s_and_b32 s5, s5, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s6, s15, s5
	v_lshl_add_u32 v1, s6, 1, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 3, v[1:2]
	v_add_nc_u32_e32 v1, s5, v1
	v_lshlrev_b64 v[1:2], 3, v[1:2]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v3, vcc_lo, s0, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	s_clause 0x1
	global_load_b64 v[3:4], v[3:4], off
	global_load_b64 v[1:2], v[1:2], off
	s_mov_b32 s0, exec_lo
	s_waitcnt vmcnt(0)
	v_add_f64 v[2:3], v[3:4], v[1:2]
	v_lshl_add_u32 v1, v0, 3, 0
	ds_store_b64 v1, v[2:3]
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v0
	s_cbranch_execz .LBB26_2
; %bb.1:
	ds_load_b64 v[6:7], v1 offset:64
	ds_load_2addr_b64 v[2:5], v1 offset1:1
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[2:3], v[6:7], v[2:3]
	ds_load_2addr_b64 v[6:9], v1 offset0:2 offset1:4
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[2:3], v[2:3], v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[2:3], v[2:3], v[6:7]
	v_add_f64 v[2:3], v[2:3], v[4:5]
	ds_store_b64 v1, v[2:3]
.LBB26_2:
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB26_4
; %bb.3:
	v_mov_b32_e32 v2, 0
	s_mov_b32 s5, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[0:1], s[4:5], 3
	s_add_u32 s0, s2, s0
	ds_load_b64 v[0:1], v2
	s_addc_u32 s1, s3, s1
	s_waitcnt lgkmcnt(0)
	global_store_b64 v2, v[0:1], s[0:1]
.LBB26_4:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z14cuda_asum_doubILj16EEvPdS0_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 10
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z14cuda_asum_doubILj16EEvPdS0_,"axG",@progbits,_Z14cuda_asum_doubILj16EEvPdS0_,comdat
.Lfunc_end26:
	.size	_Z14cuda_asum_doubILj16EEvPdS0_, .Lfunc_end26-_Z14cuda_asum_doubILj16EEvPdS0_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 340
; NumSgprs: 18
; NumVgprs: 10
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 10
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.section	.text._Z14cuda_asum_doubILj8EEvPdS0_,"axG",@progbits,_Z14cuda_asum_doubILj8EEvPdS0_,comdat
	.protected	_Z14cuda_asum_doubILj8EEvPdS0_ ; -- Begin function _Z14cuda_asum_doubILj8EEvPdS0_
	.globl	_Z14cuda_asum_doubILj8EEvPdS0_
	.p2align	8
	.type	_Z14cuda_asum_doubILj8EEvPdS0_,@function
_Z14cuda_asum_doubILj8EEvPdS0_:         ; @_Z14cuda_asum_doubILj8EEvPdS0_
; %bb.0:
	s_clause 0x1
	s_load_b32 s5, s[0:1], 0x1c
	s_load_b128 s[0:3], s[0:1], 0x0
	s_mov_b32 s4, s15
	s_waitcnt lgkmcnt(0)
	s_and_b32 s5, s5, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s6, s15, s5
	v_lshl_add_u32 v1, s6, 1, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 3, v[1:2]
	v_add_nc_u32_e32 v1, s5, v1
	v_lshlrev_b64 v[1:2], 3, v[1:2]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v3, vcc_lo, s0, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	s_clause 0x1
	global_load_b64 v[3:4], v[3:4], off
	global_load_b64 v[1:2], v[1:2], off
	s_mov_b32 s0, exec_lo
	s_waitcnt vmcnt(0)
	v_add_f64 v[2:3], v[3:4], v[1:2]
	v_lshl_add_u32 v1, v0, 3, 0
	ds_store_b64 v1, v[2:3]
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v0
	s_cbranch_execz .LBB27_2
; %bb.1:
	ds_load_2addr_b64 v[2:5], v1 offset0:2 offset1:4
	ds_load_2addr_b64 v[6:9], v1 offset1:1
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[4:5], v[4:5], v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[2:3], v[4:5], v[2:3]
	v_add_f64 v[2:3], v[2:3], v[8:9]
	ds_store_b64 v1, v[2:3]
.LBB27_2:
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB27_4
; %bb.3:
	v_mov_b32_e32 v2, 0
	s_mov_b32 s5, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[0:1], s[4:5], 3
	s_add_u32 s0, s2, s0
	ds_load_b64 v[0:1], v2
	s_addc_u32 s1, s3, s1
	s_waitcnt lgkmcnt(0)
	global_store_b64 v2, v[0:1], s[0:1]
.LBB27_4:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z14cuda_asum_doubILj8EEvPdS0_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 10
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z14cuda_asum_doubILj8EEvPdS0_,"axG",@progbits,_Z14cuda_asum_doubILj8EEvPdS0_,comdat
.Lfunc_end27:
	.size	_Z14cuda_asum_doubILj8EEvPdS0_, .Lfunc_end27-_Z14cuda_asum_doubILj8EEvPdS0_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 320
; NumSgprs: 18
; NumVgprs: 10
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 10
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.section	.text._Z14cuda_asum_doubILj4EEvPdS0_,"axG",@progbits,_Z14cuda_asum_doubILj4EEvPdS0_,comdat
	.protected	_Z14cuda_asum_doubILj4EEvPdS0_ ; -- Begin function _Z14cuda_asum_doubILj4EEvPdS0_
	.globl	_Z14cuda_asum_doubILj4EEvPdS0_
	.p2align	8
	.type	_Z14cuda_asum_doubILj4EEvPdS0_,@function
_Z14cuda_asum_doubILj4EEvPdS0_:         ; @_Z14cuda_asum_doubILj4EEvPdS0_
; %bb.0:
	s_clause 0x1
	s_load_b32 s5, s[0:1], 0x1c
	s_load_b128 s[0:3], s[0:1], 0x0
	s_mov_b32 s4, s15
	s_waitcnt lgkmcnt(0)
	s_and_b32 s5, s5, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s6, s15, s5
	v_lshl_add_u32 v1, s6, 1, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 3, v[1:2]
	v_add_nc_u32_e32 v1, s5, v1
	v_lshlrev_b64 v[1:2], 3, v[1:2]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v3, vcc_lo, s0, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	s_clause 0x1
	global_load_b64 v[3:4], v[3:4], off
	global_load_b64 v[1:2], v[1:2], off
	s_mov_b32 s0, exec_lo
	s_waitcnt vmcnt(0)
	v_add_f64 v[2:3], v[3:4], v[1:2]
	v_lshl_add_u32 v1, v0, 3, 0
	ds_store_b64 v1, v[2:3]
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v0
	s_cbranch_execz .LBB28_2
; %bb.1:
	ds_load_b64 v[6:7], v1 offset:16
	ds_load_2addr_b64 v[2:5], v1 offset1:1
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[2:3], v[6:7], v[2:3]
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[2:3], v[2:3], v[4:5]
	ds_store_b64 v1, v[2:3]
.LBB28_2:
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB28_4
; %bb.3:
	v_mov_b32_e32 v2, 0
	s_mov_b32 s5, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[0:1], s[4:5], 3
	s_add_u32 s0, s2, s0
	ds_load_b64 v[0:1], v2
	s_addc_u32 s1, s3, s1
	s_waitcnt lgkmcnt(0)
	global_store_b64 v2, v[0:1], s[0:1]
.LBB28_4:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z14cuda_asum_doubILj4EEvPdS0_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 8
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z14cuda_asum_doubILj4EEvPdS0_,"axG",@progbits,_Z14cuda_asum_doubILj4EEvPdS0_,comdat
.Lfunc_end28:
	.size	_Z14cuda_asum_doubILj4EEvPdS0_, .Lfunc_end28-_Z14cuda_asum_doubILj4EEvPdS0_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 312
; NumSgprs: 18
; NumVgprs: 8
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 8
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.section	.text._Z14cuda_asum_doubILj2EEvPdS0_,"axG",@progbits,_Z14cuda_asum_doubILj2EEvPdS0_,comdat
	.protected	_Z14cuda_asum_doubILj2EEvPdS0_ ; -- Begin function _Z14cuda_asum_doubILj2EEvPdS0_
	.globl	_Z14cuda_asum_doubILj2EEvPdS0_
	.p2align	8
	.type	_Z14cuda_asum_doubILj2EEvPdS0_,@function
_Z14cuda_asum_doubILj2EEvPdS0_:         ; @_Z14cuda_asum_doubILj2EEvPdS0_
; %bb.0:
	s_clause 0x1
	s_load_b32 s5, s[0:1], 0x1c
	s_load_b128 s[0:3], s[0:1], 0x0
	s_mov_b32 s4, s15
	s_waitcnt lgkmcnt(0)
	s_and_b32 s5, s5, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s6, s15, s5
	v_lshl_add_u32 v1, s6, 1, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 3, v[1:2]
	v_add_nc_u32_e32 v1, s5, v1
	v_lshlrev_b64 v[1:2], 3, v[1:2]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v3, vcc_lo, s0, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	s_clause 0x1
	global_load_b64 v[3:4], v[3:4], off
	global_load_b64 v[1:2], v[1:2], off
	s_mov_b32 s0, exec_lo
	s_waitcnt vmcnt(0)
	v_add_f64 v[2:3], v[3:4], v[1:2]
	v_lshl_add_u32 v1, v0, 3, 0
	ds_store_b64 v1, v[2:3]
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v0
	s_cbranch_execz .LBB29_2
; %bb.1:
	ds_load_2addr_b64 v[2:5], v1 offset1:1
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[2:3], v[4:5], v[2:3]
	ds_store_b64 v1, v[2:3]
.LBB29_2:
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB29_4
; %bb.3:
	v_mov_b32_e32 v2, 0
	s_mov_b32 s5, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[0:1], s[4:5], 3
	s_add_u32 s0, s2, s0
	ds_load_b64 v[0:1], v2
	s_addc_u32 s1, s3, s1
	s_waitcnt lgkmcnt(0)
	global_store_b64 v2, v[0:1], s[0:1]
.LBB29_4:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z14cuda_asum_doubILj2EEvPdS0_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 6
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z14cuda_asum_doubILj2EEvPdS0_,"axG",@progbits,_Z14cuda_asum_doubILj2EEvPdS0_,comdat
.Lfunc_end29:
	.size	_Z14cuda_asum_doubILj2EEvPdS0_, .Lfunc_end29-_Z14cuda_asum_doubILj2EEvPdS0_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 292
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.section	.text._Z14cuda_asum_doubILj1EEvPdS0_,"axG",@progbits,_Z14cuda_asum_doubILj1EEvPdS0_,comdat
	.protected	_Z14cuda_asum_doubILj1EEvPdS0_ ; -- Begin function _Z14cuda_asum_doubILj1EEvPdS0_
	.globl	_Z14cuda_asum_doubILj1EEvPdS0_
	.p2align	8
	.type	_Z14cuda_asum_doubILj1EEvPdS0_,@function
_Z14cuda_asum_doubILj1EEvPdS0_:         ; @_Z14cuda_asum_doubILj1EEvPdS0_
; %bb.0:
	s_clause 0x1
	s_load_b32 s5, s[0:1], 0x1c
	s_load_b128 s[0:3], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s5, s5, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s6, s15, s5
	v_lshl_add_u32 v1, s6, 1, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 3, v[1:2]
	v_add_nc_u32_e32 v1, s5, v1
	s_mov_b32 s5, 0
	v_lshlrev_b64 v[5:6], 3, v[1:2]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v3, vcc_lo, s0, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
	v_lshl_add_u32 v1, v0, 3, 0
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_u32 v5, vcc_lo, s0, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, s1, v6, vcc_lo
	s_clause 0x1
	global_load_b64 v[3:4], v[3:4], off
	global_load_b64 v[5:6], v[5:6], off
	s_mov_b32 s0, exec_lo
	s_waitcnt vmcnt(0)
	v_add_f64 v[3:4], v[3:4], v[5:6]
	ds_store_b64 v1, v[3:4]
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB30_2
; %bb.1:
	ds_load_b64 v[0:1], v2
	s_mov_b32 s4, s15
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[0:1], s[4:5], 3
	s_add_u32 s0, s2, s0
	s_addc_u32 s1, s3, s1
	s_waitcnt lgkmcnt(0)
	global_store_b64 v2, v[0:1], s[0:1]
.LBB30_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z14cuda_asum_doubILj1EEvPdS0_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 7
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z14cuda_asum_doubILj1EEvPdS0_,"axG",@progbits,_Z14cuda_asum_doubILj1EEvPdS0_,comdat
.Lfunc_end30:
	.size	_Z14cuda_asum_doubILj1EEvPdS0_, .Lfunc_end30-_Z14cuda_asum_doubILj1EEvPdS0_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 240
; NumSgprs: 18
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         20
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         28
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         30
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         32
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         34
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         36
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         38
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         56
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         80
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         136
        .size:           4
        .value_kind:     hidden_dynamic_lds_size
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 272
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z13cuda_asum_intILj512EEvPiS0_
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z13cuda_asum_intILj512EEvPiS0_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     9
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         20
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         28
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         30
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         32
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         34
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         36
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         38
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         56
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         80
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         136
        .size:           4
        .value_kind:     hidden_dynamic_lds_size
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 272
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z13cuda_asum_intILj256EEvPiS0_
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z13cuda_asum_intILj256EEvPiS0_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     9
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         20
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         28
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         30
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         32
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         34
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         36
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         38
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         56
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         80
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         136
        .size:           4
        .value_kind:     hidden_dynamic_lds_size
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 272
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z13cuda_asum_intILj128EEvPiS0_
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z13cuda_asum_intILj128EEvPiS0_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     9
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         20
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         28
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         30
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         32
        .size:           2
        .value_kind:     hidden_group_size_z
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        .size:           2
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        .size:           2
        .value_kind:     hidden_remainder_z
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        .value_kind:     hidden_global_offset_x
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        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         80
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         136
        .size:           4
        .value_kind:     hidden_dynamic_lds_size
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 272
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z13cuda_asum_intILj64EEvPiS0_
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z13cuda_asum_intILj64EEvPiS0_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     9
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
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        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
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        .value_kind:     hidden_block_count_z
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        .size:           8
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        .size:           8
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    .group_segment_fixed_size: 0
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    .kernarg_segment_size: 272
    .language:       OpenCL C
    .language_version:
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      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z13cuda_asum_intILj32EEvPiS0_
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z13cuda_asum_intILj32EEvPiS0_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     8
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
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        .offset:         0
        .size:           8
        .value_kind:     global_buffer
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        .size:           4
        .value_kind:     hidden_block_count_z
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        .value_kind:     hidden_group_size_x
      - .offset:         30
        .size:           2
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        .size:           2
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