//Note:
//Cara running program ./nama_file mode besar_matrix besar_grid besar_block
//Ukuran matrix: besar_matrix x besar matrix
//Grid: besar_grid x besar_grid (block per grid)                        | Max: Mengacu pada NVIDIA Compute Capability dari setiap seri GPU
//Block: besar_block x besar_block (thread per block)                   | Max: Mengacu pada NVIDIA Compute Capability dari setiap seri GPU
// Mode:
// 0: Matrix multiplication pada 1 GPU tanpa melihat hasil sekuensial
// 1: Matrix multiplication pada 1 GPU dengan hasil sekuensial
// 2: Matrix multiplication pada multiple GPU tanpa melihat hasil sekuensial
// 3: Matrix multiplication pada multiple GPU dengan hasil sekuensial
// mode 2 ketas belum selesai dikerjakan

#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <assert.h>

//Operasi perkalian matrix pada gpu
__global__ void matrixmul_kernel(int *gpu_matrixA, int *gpu_matrixB, int *gpu_result, int matrix_size, int grid, int block){
    int l, m, n, R, displacement;
    if(matrix_size > (grid * block)) displacement = matrix_size/(grid * block);
    else displacement = 1;
    int row_index = blockIdx.y * blockDim.y + threadIdx.y;
    int col_index = blockIdx.x * blockDim.x + threadIdx.x;

    if(row_index < matrix_size && col_index < matrix_size){
        for(m = 0; m < displacement; m++){
            for(n = 0; n < displacement; n++){
                R = 0;
                for(l = 0; l < matrix_size; l++){
                    int A = gpu_matrixA[(row_index * displacement + m) * matrix_size + l];
                    int B = gpu_matrixB[l * matrix_size + (col_index * displacement + n)];
                    R += A * B;
                }
                gpu_result[(row_index * displacement + m) * matrix_size + (col_index * displacement + n)] = R;
            }
        }
    }
}

int main(int argc, char** argv){
    srand(time(NULL));
    double runtime;
    struct timespec begin, end;

	// Inisialisasi parameter dari user input
	int mode = atoi(argv[1]);
    int matrix_size = atoi(argv[2]);
    int igrid = atoi(argv[3]);
    int iblock = atoi(argv[4]);

    //Debug print variabel user input
    //printf("Mode: %d\n", mode);
    //printf("Size %d x %d\n", matrix_size, matrix_size);
    //printf("Grid: %d\n", igrid);
    //printf("Block:%d\n", iblock);

    // Inisailiasai pada Host
    int matrixBytes = (matrix_size * matrix_size) * sizeof(int);
    int *matrixA = (int *)malloc(matrixBytes);
    int *matrixB = (int *)malloc(matrixBytes);
    int *result = (int *)malloc(matrixBytes);
    int i, j, k;

//Inisialisasi martrix
    for(i = 0; i < matrix_size * matrix_size; i++){
        matrixA[i] = rand() % 99 + 1;
        matrixB[i] = rand() % 99 + 1;
    }

  	//Operasi dengan 1 GPU
    //if(mode < 2){
        clock_gettime(CLOCK_REALTIME, &begin);
        //Inisialisasi pada GPU
        int *gpu_matrixA, *gpu_matrixB, *gpu_result;
        cudaMalloc((void **) &gpu_matrixA, matrixBytes);
        cudaMalloc((void **) &gpu_matrixB, matrixBytes);
        cudaMalloc((void **) &gpu_result, matrixBytes);
        cudaMemcpy(gpu_matrixA, matrixA, matrixBytes, cudaMemcpyHostToDevice);
        cudaMemcpy(gpu_matrixB, matrixB, matrixBytes, cudaMemcpyHostToDevice);

        //Mulai operasi pada device
        dim3 grid(igrid, igrid);
        dim3 block(iblock, iblock);
        matrixmul_kernel<<<grid, block>>>(gpu_matrixA, gpu_matrixB, gpu_result, matrix_size, igrid, iblock);

		//Return hasil perkalian
        cudaMemcpy(result, gpu_result, matrixBytes, cudaMemcpyDeviceToHost);
        clock_gettime(CLOCK_REALTIME, &end);
        runtime = (end.tv_sec - begin.tv_sec) + (end.tv_nsec - begin.tv_nsec) / 1000000000.0;
        printf("Running Time: %f\n\n", runtime);
    /*}else{
        //Operasi pada multiple GPU
        //Check Device
        clock_gettime(CLOCK_REALTIME, &begin);
        int device_count;
        cudaGetDeviceCount(&device_count);
        printf("Device: %d\n", device_count);



        clock_gettime(CLOCK_REALTIME, &end);
        runtime = (end.tv_sec - begin.tv_sec) + (end.tv_nsec - begin.tv_nsec) / 1000000000.0;
        printf("Running Time: %f\n\n", runtime);
    }*/

	//Operasi sekuensial
    if(mode == 1 || mode == 3){
        int right_answer = 0;
        int *seqresult = (int *)malloc(matrixBytes);
        for (i = 0; i < matrix_size; i++){
            for (j = 0; j < matrix_size; j++){
                seqresult[i * matrix_size + j] = 0;
                for (k = 0; k < matrix_size; k++)
                    seqresult[i * matrix_size + j] += matrixA[i * matrix_size + k] * matrixB[k * matrix_size + j];
                if(seqresult[i * matrix_size + j] == result[i * matrix_size + j]) right_answer += 1;
                //printf("%d - %d S: %d, CUDA: %d\n", i * matrix_size, j, seqresult[i * matrix_size + j], result[i * matrix_size + j]);
            }
        }
        if(right_answer == (matrix_size * matrix_size)) printf("The answer is matched.\n");
        free(seqresult);
    }

    //Membebaskan Device
    cudaFree(gpu_matrixB);
    cudaFree(gpu_matrixB);
    cudaFree(gpu_result);

    //Membebaskan Host
    free(matrixA);
    free(matrixB);
    free(result);
}


	.file	"tmpxft_0035a521_00000000-6_mm.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2030:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z43__device_stub__Z16matrixmul_kernelPiS_S_iiiPiS_S_iii
	.type	_Z43__device_stub__Z16matrixmul_kernelPiS_S_iiiPiS_S_iii, @function
_Z43__device_stub__Z16matrixmul_kernelPiS_S_iiiPiS_S_iii:
.LFB2052:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	56(%rsp), %rdx
	movl	%ecx, 20(%rsp)
	leaq	64(%rsp), %rcx
	movl	%r8d, 16(%rsp)
	movl	%r9d, 12(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	64(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z16matrixmul_kernelPiS_S_iii(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 208
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L2:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2052:
	.size	_Z43__device_stub__Z16matrixmul_kernelPiS_S_iiiPiS_S_iii, .-_Z43__device_stub__Z16matrixmul_kernelPiS_S_iiiPiS_S_iii
	.globl	_Z16matrixmul_kernelPiS_S_iii
	.type	_Z16matrixmul_kernelPiS_S_iii, @function
_Z16matrixmul_kernelPiS_S_iii:
.LFB2053:
	.cfi_startproc
	endbr64
	jmp	_Z43__device_stub__Z16matrixmul_kernelPiS_S_iiiPiS_S_iii
	.cfi_endproc
.LFE2053:
	.size	_Z16matrixmul_kernelPiS_S_iii, .-_Z16matrixmul_kernelPiS_S_iii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC1:
	.string	"Running Time: %f\n\n"
.LC2:
	.string	"The answer is matched.\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	xorl	%edi, %edi
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movq	%rsi, %rbx
	subq	$136, %rsp
	.cfi_def_cfa_offset 192
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	call	time@PLT
	movl	%eax, %edi
	call	srand@PLT
	movq	8(%rbx), %rdi
	call	atoi@PLT
	movq	16(%rbx), %rdi
	movl	%eax, %r12d
	call	atoi@PLT
	movq	24(%rbx), %rdi
	movl	%eax, %ebp
	call	atoi@PLT
	movq	32(%rbx), %rdi
	movl	%eax, %r13d
	call	atoi@PLT
	movl	%eax, %r14d
	movl	%ebp, %eax
	imull	%ebp, %eax
	leal	0(,%rax,4), %ebx
	movl	%eax, 20(%rsp)
	movslq	%ebx, %rax
	xorl	%ebx, %ebx
	movq	%rax, %rdi
	movq	%rax, (%rsp)
	call	malloc@PLT
	movq	(%rsp), %rdi
	movq	%rax, 8(%rsp)
	call	malloc@PLT
	movq	(%rsp), %rdi
	movq	%rax, %r15
	call	malloc@PLT
	movq	%rax, 24(%rsp)
.L9:
	cmpl	%ebx, 20(%rsp)
	jle	.L23
	call	rand@PLT
	movl	$99, %ecx
	cltd
	idivl	%ecx
	movq	8(%rsp), %rax
	incl	%edx
	movl	%edx, (%rax,%rbx,4)
	call	rand@PLT
	movl	$99, %ecx
	cltd
	idivl	%ecx
	incl	%edx
	movl	%edx, (%r15,%rbx,4)
	incq	%rbx
	jmp	.L9
.L23:
	xorl	%edi, %edi
	leaq	88(%rsp), %rsi
	call	clock_gettime@PLT
	movq	(%rsp), %rsi
	leaq	40(%rsp), %rdi
	call	cudaMalloc@PLT
	movq	(%rsp), %rsi
	leaq	48(%rsp), %rdi
	call	cudaMalloc@PLT
	movq	(%rsp), %rsi
	leaq	56(%rsp), %rdi
	call	cudaMalloc@PLT
	movq	(%rsp), %rdx
	movq	8(%rsp), %rsi
	movl	$1, %ecx
	movq	40(%rsp), %rdi
	call	cudaMemcpy@PLT
	movq	(%rsp), %rdx
	movq	48(%rsp), %rdi
	movq	%r15, %rsi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	movl	%r13d, 64(%rsp)
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	%r13d, 68(%rsp)
	movq	64(%rsp), %rdi
	movl	$1, %ecx
	movl	$1, %esi
	movl	%r14d, 76(%rsp)
	movl	%r14d, 80(%rsp)
	movq	76(%rsp), %rdx
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L11
	movq	56(%rsp), %rdx
	movq	48(%rsp), %rsi
	movl	%r14d, %r9d
	movl	%r13d, %r8d
	movq	40(%rsp), %rdi
	movl	%ebp, %ecx
	call	_Z43__device_stub__Z16matrixmul_kernelPiS_S_iiiPiS_S_iii
.L11:
	movq	(%rsp), %rdx
	movq	56(%rsp), %rsi
	movl	$2, %ecx
	andl	$-3, %r12d
	movq	24(%rsp), %rdi
	call	cudaMemcpy@PLT
	xorl	%edi, %edi
	leaq	104(%rsp), %rsi
	call	clock_gettime@PLT
	movq	112(%rsp), %rax
	subq	96(%rsp), %rax
	leaq	.LC1(%rip), %rsi
	cvtsi2sdq	%rax, %xmm0
	movq	104(%rsp), %rax
	subq	88(%rsp), %rax
	divsd	.LC0(%rip), %xmm0
	cvtsi2sdq	%rax, %xmm1
	movl	$2, %edi
	movb	$1, %al
	addsd	%xmm1, %xmm0
	call	__printf_chk@PLT
	decl	%r12d
	jne	.L12
	movq	(%rsp), %rdi
	call	malloc@PLT
	movslq	%ebp, %rdx
	xorl	%r9d, %r9d
	xorl	%r10d, %r10d
	movq	%rax, %r13
	salq	$2, %rdx
	xorl	%eax, %eax
.L13:
	cmpl	%ebp, %r10d
	jge	.L24
	movq	8(%rsp), %rbx
	movq	%rax, %rsi
	xorl	%ecx, %ecx
	leaq	(%rbx,%rax), %r12
.L16:
	leaq	(%r15,%rcx,4), %r11
	xorl	%r8d, %r8d
	xorl	%edi, %edi
.L14:
	movl	(%r12,%r8,4), %ebx
	imull	(%r11), %ebx
	incq	%r8
	addq	%rdx, %r11
	addl	%ebx, %edi
	cmpl	%r8d, %ebp
	jg	.L14
	movq	24(%rsp), %rbx
	movl	%edi, 0(%r13,%rsi)
	cmpl	(%rbx,%rsi), %edi
	jne	.L15
	incl	%r9d
.L15:
	incq	%rcx
	addq	$4, %rsi
	cmpl	%ecx, %ebp
	jg	.L16
	incl	%r10d
	addq	%rdx, %rax
	jmp	.L13
.L24:
	cmpl	%r9d, 20(%rsp)
	jne	.L17
	leaq	.LC2(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
.L17:
	movq	%r13, %rdi
	call	free@PLT
.L12:
	movq	48(%rsp), %rdi
	call	cudaFree@PLT
	movq	48(%rsp), %rdi
	call	cudaFree@PLT
	movq	56(%rsp), %rdi
	call	cudaFree@PLT
	movq	8(%rsp), %rdi
	call	free@PLT
	movq	%r15, %rdi
	call	free@PLT
	movq	24(%rsp), %rdi
	call	free@PLT
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L18
	call	__stack_chk_fail@PLT
.L18:
	addq	$136, %rsp
	.cfi_def_cfa_offset 56
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2027:
	.size	main, .-main
	.section	.rodata.str1.1
.LC3:
	.string	"_Z16matrixmul_kernelPiS_S_iii"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC3(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z16matrixmul_kernelPiS_S_iii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2055:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst8,"aM",@progbits,8
	.align 8
.LC0:
	.long	0
	.long	1104006501
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

//Note:
//Cara running program ./nama_file mode besar_matrix besar_grid besar_block
//Ukuran matrix: besar_matrix x besar matrix
//Grid: besar_grid x besar_grid (block per grid)                        | Max: Mengacu pada NVIDIA Compute Capability dari setiap seri GPU
//Block: besar_block x besar_block (thread per block)                   | Max: Mengacu pada NVIDIA Compute Capability dari setiap seri GPU
// Mode:
// 0: Matrix multiplication pada 1 GPU tanpa melihat hasil sekuensial
// 1: Matrix multiplication pada 1 GPU dengan hasil sekuensial
// 2: Matrix multiplication pada multiple GPU tanpa melihat hasil sekuensial
// 3: Matrix multiplication pada multiple GPU dengan hasil sekuensial
// mode 2 ketas belum selesai dikerjakan


#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <assert.h>

//Operasi perkalian matrix pada gpu
__global__ void matrixmul_kernel(int *gpu_matrixA, int *gpu_matrixB, int *gpu_result, int matrix_size, int grid, int block){
    int l, m, n, R, displacement;
    if(matrix_size > (grid * block)) displacement = matrix_size/(grid * block);
    else displacement = 1;
    int row_index = blockIdx.y * blockDim.y + threadIdx.y;
    int col_index = blockIdx.x * blockDim.x + threadIdx.x;

    if(row_index < matrix_size && col_index < matrix_size){
        for(m = 0; m < displacement; m++){
            for(n = 0; n < displacement; n++){
                R = 0;
                for(l = 0; l < matrix_size; l++){
                    int A = gpu_matrixA[(row_index * displacement + m) * matrix_size + l];
                    int B = gpu_matrixB[l * matrix_size + (col_index * displacement + n)];
                    R += A * B;
                }
                gpu_result[(row_index * displacement + m) * matrix_size + (col_index * displacement + n)] = R;
            }
        }
    }
}

int main(int argc, char** argv){
    srand(time(NULL));
    double runtime;
    struct timespec begin, end;

	// Inisialisasi parameter dari user input
	int mode = atoi(argv[1]);
    int matrix_size = atoi(argv[2]);
    int igrid = atoi(argv[3]);
    int iblock = atoi(argv[4]);

    //Debug print variabel user input
    //printf("Mode: %d\n", mode);
    //printf("Size %d x %d\n", matrix_size, matrix_size);
    //printf("Grid: %d\n", igrid);
    //printf("Block:%d\n", iblock);

    // Inisailiasai pada Host
    int matrixBytes = (matrix_size * matrix_size) * sizeof(int);
    int *matrixA = (int *)malloc(matrixBytes);
    int *matrixB = (int *)malloc(matrixBytes);
    int *result = (int *)malloc(matrixBytes);
    int i, j, k;

//Inisialisasi martrix
    for(i = 0; i < matrix_size * matrix_size; i++){
        matrixA[i] = rand() % 99 + 1;
        matrixB[i] = rand() % 99 + 1;
    }

  	//Operasi dengan 1 GPU
    //if(mode < 2){
        clock_gettime(CLOCK_REALTIME, &begin);
        //Inisialisasi pada GPU
        int *gpu_matrixA, *gpu_matrixB, *gpu_result;
        hipMalloc((void **) &gpu_matrixA, matrixBytes);
        hipMalloc((void **) &gpu_matrixB, matrixBytes);
        hipMalloc((void **) &gpu_result, matrixBytes);
        hipMemcpy(gpu_matrixA, matrixA, matrixBytes, hipMemcpyHostToDevice);
        hipMemcpy(gpu_matrixB, matrixB, matrixBytes, hipMemcpyHostToDevice);

        //Mulai operasi pada device
        dim3 grid(igrid, igrid);
        dim3 block(iblock, iblock);
        matrixmul_kernel<<<grid, block>>>(gpu_matrixA, gpu_matrixB, gpu_result, matrix_size, igrid, iblock);

		//Return hasil perkalian
        hipMemcpy(result, gpu_result, matrixBytes, hipMemcpyDeviceToHost);
        clock_gettime(CLOCK_REALTIME, &end);
        runtime = (end.tv_sec - begin.tv_sec) + (end.tv_nsec - begin.tv_nsec) / 1000000000.0;
        printf("Running Time: %f\n\n", runtime);
    /*}else{
        //Operasi pada multiple GPU
        //Check Device
        clock_gettime(CLOCK_REALTIME, &begin);
        int device_count;
        cudaGetDeviceCount(&device_count);
        printf("Device: %d\n", device_count);



        clock_gettime(CLOCK_REALTIME, &end);
        runtime = (end.tv_sec - begin.tv_sec) + (end.tv_nsec - begin.tv_nsec) / 1000000000.0;
        printf("Running Time: %f\n\n", runtime);
    }*/

	//Operasi sekuensial
    if(mode == 1 || mode == 3){
        int right_answer = 0;
        int *seqresult = (int *)malloc(matrixBytes);
        for (i = 0; i < matrix_size; i++){
            for (j = 0; j < matrix_size; j++){
                seqresult[i * matrix_size + j] = 0;
                for (k = 0; k < matrix_size; k++)
                    seqresult[i * matrix_size + j] += matrixA[i * matrix_size + k] * matrixB[k * matrix_size + j];
                if(seqresult[i * matrix_size + j] == result[i * matrix_size + j]) right_answer += 1;
                //printf("%d - %d S: %d, CUDA: %d\n", i * matrix_size, j, seqresult[i * matrix_size + j], result[i * matrix_size + j]);
            }
        }
        if(right_answer == (matrix_size * matrix_size)) printf("The answer is matched.\n");
        free(seqresult);
    }

    //Membebaskan Device
    hipFree(gpu_matrixB);
    hipFree(gpu_matrixB);
    hipFree(gpu_result);

    //Membebaskan Host
    free(matrixA);
    free(matrixB);
    free(result);
}


	.text
	.file	"mm.hip"
	.globl	_Z31__device_stub__matrixmul_kernelPiS_S_iii # -- Begin function _Z31__device_stub__matrixmul_kernelPiS_S_iii
	.type	_Z31__device_stub__matrixmul_kernelPiS_S_iii,@function
_Z31__device_stub__matrixmul_kernelPiS_S_iii: # @_Z31__device_stub__matrixmul_kernelPiS_S_iii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	20(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	16(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	12(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z16matrixmul_kernelPiS_S_iii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z31__device_stub__matrixmul_kernelPiS_S_iii, .Lfunc_end0-_Z31__device_stub__matrixmul_kernelPiS_S_iii
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0                          # -- Begin function main
.LCPI1_0:
	.quad	0x41cdcd6500000000              # double 1.0E+9
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$104, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%rsi, %rbx
	xorl	%edi, %edi
	callq	time
	movl	%eax, %edi
	callq	srand
	movq	8(%rbx), %rdi
	callq	atoi
	movl	%eax, 52(%rsp)                  # 4-byte Spill
	movq	16(%rbx), %rdi
	callq	atoi
	movl	%eax, %ebp
	movq	24(%rbx), %rdi
	callq	atoi
	movl	%eax, 48(%rsp)                  # 4-byte Spill
	movq	32(%rbx), %rdi
	callq	atoi
	movl	%eax, 44(%rsp)                  # 4-byte Spill
	movl	%ebp, %eax
	imull	%eax, %eax
	movq	%rax, 56(%rsp)                  # 8-byte Spill
	leal	(,%rax,4), %eax
	movslq	%eax, %r13
	movq	%r13, %rdi
	callq	malloc
	movq	%rax, %rbx
	movq	%r13, %rdi
	callq	malloc
	movq	%rax, %r14
	movq	%r13, %rdi
	callq	malloc
	movq	%rax, 16(%rsp)                  # 8-byte Spill
	movl	%ebp, 12(%rsp)                  # 4-byte Spill
	testl	%ebp, %ebp
	je	.LBB1_3
# %bb.1:                                # %.lr.ph.preheader
	movq	56(%rsp), %r12                  # 8-byte Reload
	cmpl	$1, %r12d
                                        # kill: def $r12d killed $r12d killed $r12 def $r12
	adcl	$0, %r12d
	xorl	%r15d, %r15d
.LBB1_2:                                # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	callq	rand
	cltq
	imulq	$-1518422781, %rax, %rcx        # imm = 0xA57EB503
	shrq	$32, %rcx
	addl	%eax, %ecx
	movl	%ecx, %edx
	shrl	$31, %edx
	sarl	$6, %ecx
	addl	%edx, %ecx
	imull	$99, %ecx, %ecx
	negl	%ecx
	addl	%ecx, %eax
	incl	%eax
	movl	%eax, (%rbx,%r15,4)
	callq	rand
	cltq
	imulq	$-1518422781, %rax, %rcx        # imm = 0xA57EB503
	shrq	$32, %rcx
	addl	%eax, %ecx
	movl	%ecx, %edx
	shrl	$31, %edx
	sarl	$6, %ecx
	addl	%edx, %ecx
	imull	$99, %ecx, %ecx
	negl	%ecx
	addl	%ecx, %eax
	incl	%eax
	movl	%eax, (%r14,%r15,4)
	incq	%r15
	cmpq	%r15, %r12
	jne	.LBB1_2
.LBB1_3:                                # %._crit_edge
	leaq	72(%rsp), %rsi
	xorl	%edi, %edi
	callq	clock_gettime
	leaq	64(%rsp), %r12
	movq	%r12, %rdi
	movq	%r13, %rsi
	callq	hipMalloc
	leaq	32(%rsp), %r15
	movq	%r15, %rdi
	movq	%r13, %rsi
	callq	hipMalloc
	leaq	24(%rsp), %rdi
	movq	%r13, %rsi
	callq	hipMalloc
	movq	(%r12), %rdi
	movq	%rbx, %rsi
	movq	%r13, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%r15), %rdi
	movq	%r14, %rsi
	movq	%r13, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	movl	48(%rsp), %ebp                  # 4-byte Reload
	movl	%ebp, %eax
	movq	%rax, %rdi
	shlq	$32, %rdi
	orq	%rax, %rdi
	movl	44(%rsp), %r15d                 # 4-byte Reload
	movl	%r15d, %eax
	movq	%rax, %rdx
	shlq	$32, %rdx
	orq	%rax, %rdx
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_5
# %bb.4:
	movq	64(%rsp), %rdi
	movq	32(%rsp), %rsi
	movq	24(%rsp), %rdx
	movl	12(%rsp), %ecx                  # 4-byte Reload
	movl	%ebp, %r8d
	movl	%r15d, %r9d
	callq	_Z31__device_stub__matrixmul_kernelPiS_S_iii
.LBB1_5:
	movq	24(%rsp), %rsi
	movq	16(%rsp), %rdi                  # 8-byte Reload
	movq	%r13, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	xorl	%r13d, %r13d
	leaq	88(%rsp), %r12
	xorl	%edi, %edi
	movq	%r12, %rsi
	callq	clock_gettime
	movq	(%r12), %rax
	movq	8(%r12), %rcx
	subq	72(%rsp), %rax
	cvtsi2sd	%rax, %xmm1
	subq	80(%rsp), %rcx
	cvtsi2sd	%rcx, %xmm0
	divsd	.LCPI1_0(%rip), %xmm0
	addsd	%xmm1, %xmm0
	movl	$.L.str, %edi
	movb	$1, %al
	callq	printf
	movl	52(%rsp), %eax                  # 4-byte Reload
	andl	$-3, %eax
	cmpl	$1, %eax
	jne	.LBB1_15
# %bb.6:
	cmpl	$0, 12(%rsp)                    # 4-byte Folded Reload
	jle	.LBB1_13
# %bb.7:                                # %.preheader.lr.ph
	movl	12(%rsp), %eax                  # 4-byte Reload
	leaq	(,%rax,4), %rcx
	xorl	%edx, %edx
	xorl	%esi, %esi
	xorl	%r13d, %r13d
.LBB1_8:                                # %.lr.ph100
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB1_9 Depth 2
                                        #       Child Loop BB1_10 Depth 3
	movl	%edx, %edi
	leaq	(%rbx,%rdi,4), %rdi
	movq	%rsi, %r8
	imulq	%rax, %r8
	movq	16(%rsp), %r9                   # 8-byte Reload
	leaq	(%r9,%r8,4), %r8
	movq	%r14, %r9
	xorl	%r10d, %r10d
.LBB1_9:                                # %.lr.ph96
                                        #   Parent Loop BB1_8 Depth=1
                                        # =>  This Loop Header: Depth=2
                                        #       Child Loop BB1_10 Depth 3
	xorl	%r11d, %r11d
	movq	%r9, %r12
	xorl	%r15d, %r15d
.LBB1_10:                               #   Parent Loop BB1_8 Depth=1
                                        #     Parent Loop BB1_9 Depth=2
                                        # =>    This Inner Loop Header: Depth=3
	movl	(%r12), %ebp
	imull	(%rdi,%r11,4), %ebp
	addl	%ebp, %r15d
	incq	%r11
	addq	%rcx, %r12
	cmpq	%r11, %rax
	jne	.LBB1_10
# %bb.11:                               # %._crit_edge97
                                        #   in Loop: Header=BB1_9 Depth=2
	xorl	%r11d, %r11d
	cmpl	(%r8,%r10,4), %r15d
	sete	%r11b
	addl	%r11d, %r13d
	incq	%r10
	addq	$4, %r9
	cmpq	%rax, %r10
	jne	.LBB1_9
# %bb.12:                               # %._crit_edge101
                                        #   in Loop: Header=BB1_8 Depth=1
	incq	%rsi
	addl	12(%rsp), %edx                  # 4-byte Folded Reload
	cmpq	%rax, %rsi
	jne	.LBB1_8
.LBB1_13:                               # %._crit_edge104
	cmpl	56(%rsp), %r13d                 # 4-byte Folded Reload
	jne	.LBB1_15
# %bb.14:
	movl	$.Lstr, %edi
	callq	puts@PLT
.LBB1_15:
	movq	32(%rsp), %rdi
	callq	hipFree
	movq	32(%rsp), %rdi
	callq	hipFree
	movq	24(%rsp), %rdi
	callq	hipFree
	movq	%rbx, %rdi
	callq	free
	movq	%r14, %rdi
	callq	free
	movq	16(%rsp), %rdi                  # 8-byte Reload
	callq	free
	xorl	%eax, %eax
	addq	$104, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	main, .Lfunc_end1-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z16matrixmul_kernelPiS_S_iii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z16matrixmul_kernelPiS_S_iii,@object # @_Z16matrixmul_kernelPiS_S_iii
	.section	.rodata,"a",@progbits
	.globl	_Z16matrixmul_kernelPiS_S_iii
	.p2align	3, 0x0
_Z16matrixmul_kernelPiS_S_iii:
	.quad	_Z31__device_stub__matrixmul_kernelPiS_S_iii
	.size	_Z16matrixmul_kernelPiS_S_iii, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"Running Time: %f\n\n"
	.size	.L.str, 19

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z16matrixmul_kernelPiS_S_iii"
	.size	.L__unnamed_1, 30

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.type	.Lstr,@object                   # @str
	.section	.rodata.str1.1,"aMS",@progbits,1
.Lstr:
	.asciz	"The answer is matched."
	.size	.Lstr, 23

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z31__device_stub__matrixmul_kernelPiS_S_iii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z16matrixmul_kernelPiS_S_iii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z16matrixmul_kernelPiS_S_iii ; -- Begin function _Z16matrixmul_kernelPiS_S_iii
	.globl	_Z16matrixmul_kernelPiS_S_iii
	.p2align	8
	.type	_Z16matrixmul_kernelPiS_S_iii,@function
_Z16matrixmul_kernelPiS_S_iii:          ; @_Z16matrixmul_kernelPiS_S_iii
; %bb.0:
	s_load_b128 s[4:7], s[0:1], 0x18
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s2, s6, s5
	s_mov_b32 s6, 1
	s_cmp_ge_i32 s2, s4
	s_cbranch_scc1 .LBB0_2
; %bb.1:
	s_ashr_i32 s3, s2, 31
	s_ashr_i32 s7, s4, 31
	s_add_i32 s2, s2, s3
	s_add_i32 s8, s4, s7
	s_xor_b32 s2, s2, s3
	s_xor_b32 s8, s8, s7
	v_cvt_f32_u32_e32 v1, s2
	s_sub_i32 s6, 0, s2
	s_xor_b32 s3, s7, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v1, v1
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v1, 0x4f7ffffe, v1
	v_cvt_u32_f32_e32 v1, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s5, v1
	s_mul_i32 s6, s6, s5
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_hi_u32 s6, s5, s6
	s_add_i32 s5, s5, s6
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_hi_u32 s5, s8, s5
	s_mul_i32 s6, s5, s2
	s_add_i32 s7, s5, 1
	s_sub_i32 s6, s8, s6
	s_delay_alu instid0(SALU_CYCLE_1)
	s_sub_i32 s8, s6, s2
	s_cmp_ge_u32 s6, s2
	s_cselect_b32 s5, s7, s5
	s_cselect_b32 s6, s8, s6
	s_add_i32 s7, s5, 1
	s_cmp_ge_u32 s6, s2
	s_cselect_b32 s2, s7, s5
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b32 s2, s2, s3
	s_sub_i32 s6, s2, s3
.LBB0_2:
	s_load_b32 s2, s[0:1], 0x34
	v_bfe_u32 v3, v0, 10, 10
	v_and_b32_e32 v0, 0x3ff, v0
	s_mov_b32 s7, 0
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s2, 16
	s_and_b32 s2, s2, 0xffff
	v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
	s_cmp_gt_i32 s6, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[2:3], null, s14, s2, v[0:1]
	s_cselect_b32 s2, -1, 0
	v_max_i32_e32 v0, v1, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_gt_i32_e32 vcc_lo, s4, v0
	s_and_b32 s2, vcc_lo, s2
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_11
; %bb.3:                                ; %.preheader54.lr.ph
	s_clause 0x1
	s_load_b128 s[8:11], s[0:1], 0x0
	s_load_b64 s[0:1], s[0:1], 0x10
	s_mul_i32 s2, s6, s4
	v_mul_lo_u32 v11, v1, s6
	v_mul_lo_u32 v0, v2, s6
	v_mul_lo_u32 v1, s2, v1
	s_cmp_gt_i32 s4, 0
	s_cselect_b32 s12, -1, 0
	s_ashr_i32 s5, s4, 31
	s_delay_alu instid0(SALU_CYCLE_1)
	s_lshl_b64 s[2:3], s[4:5], 2
.LBB0_4:                                ; %.preheader54
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_5 Depth 2
                                        ;       Child Loop BB0_7 Depth 3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v2, 31, v1
	v_add_nc_u32_e32 v6, s7, v11
	s_mov_b32 s5, 0
	v_lshlrev_b64 v[4:5], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[2:3], null, v6, s4, v[0:1]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v3, vcc_lo, s8, v4
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v4, vcc_lo, s9, v5, vcc_lo
	v_mov_b32_e32 v5, v0
.LBB0_5:                                ; %.preheader
                                        ;   Parent Loop BB0_4 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB0_7 Depth 3
	s_and_not1_b32 vcc_lo, exec_lo, s12
	s_cbranch_vccnz .LBB0_8
; %bb.6:                                ; %.lr.ph
                                        ;   in Loop: Header=BB0_5 Depth=2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_ashrrev_i32_e32 v6, 31, v5
	v_mov_b32_e32 v10, v4
	s_mov_b32 s13, s4
	v_mov_b32_e32 v9, v3
	v_lshlrev_b64 v[7:8], 2, v[5:6]
	v_mov_b32_e32 v6, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v7, vcc_lo, s10, v7
	v_add_co_ci_u32_e32 v8, vcc_lo, s11, v8, vcc_lo
.LBB0_7:                                ;   Parent Loop BB0_4 Depth=1
                                        ;     Parent Loop BB0_5 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	global_load_b32 v14, v[9:10], off
	global_load_b32 v15, v[7:8], off
	s_add_i32 s13, s13, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u32 s13, 0
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[12:13], null, v15, v14, v[6:7]
	v_add_co_u32 v7, vcc_lo, v7, s2
	v_add_co_ci_u32_e32 v8, vcc_lo, s3, v8, vcc_lo
	v_add_co_u32 v9, vcc_lo, v9, 4
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v10, vcc_lo
	v_mov_b32_e32 v6, v12
	s_cbranch_scc1 .LBB0_7
	s_branch .LBB0_9
.LBB0_8:                                ;   in Loop: Header=BB0_5 Depth=2
	v_mov_b32_e32 v6, 0
.LBB0_9:                                ; %._crit_edge
                                        ;   in Loop: Header=BB0_5 Depth=2
	v_add_nc_u32_e32 v7, s5, v2
	v_add_nc_u32_e32 v5, 1, v5
	s_add_i32 s5, s5, 1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	s_cmp_lg_u32 s5, s6
	v_ashrrev_i32_e32 v8, 31, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[7:8], 2, v[7:8]
	v_add_co_u32 v7, vcc_lo, s0, v7
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v8, vcc_lo, s1, v8, vcc_lo
	global_store_b32 v[7:8], v6, off
	s_cbranch_scc1 .LBB0_5
; %bb.10:                               ; %._crit_edge59
                                        ;   in Loop: Header=BB0_4 Depth=1
	v_add_nc_u32_e32 v1, s4, v1
	s_add_i32 s7, s7, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u32 s7, s6
	s_cbranch_scc1 .LBB0_4
.LBB0_11:                               ; %.loopexit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z16matrixmul_kernelPiS_S_iii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 16
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z16matrixmul_kernelPiS_S_iii, .Lfunc_end0-_Z16matrixmul_kernelPiS_S_iii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 632
; NumSgprs: 18
; NumVgprs: 16
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 16
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         44
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         52
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         54
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         56
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         58
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         60
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         62
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         104
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 296
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z16matrixmul_kernelPiS_S_iii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z16matrixmul_kernelPiS_S_iii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     16
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
