inline __device__ float4 make_float4(float s)
{
    return make_float4(s, s, s, s);
}

inline __device__ float4 operator+(float4 a, float4 b)
{
    return make_float4(a.x + b.x, a.y + b.y, a.z + b.z,  a.w + b.w);
}

inline __host__ __device__ float4 operator-(float4 a, float4 b)
{
    return make_float4(a.x - b.x, a.y - b.y, a.z - b.z,  a.w - b.w);
}

inline __device__ void operator+=(float4 &a, float4 b)
{
    a.x += b.x;
    a.y += b.y;
    a.z += b.z;
    a.w += b.w;
}

inline __device__ float4 operator*(float4 a, float4 b)
{
    return make_float4(a.x * b.x, a.y * b.y, a.z * b.z,  a.w * b.w);
}

inline __device__ float4 operator*(float4 a, float b)
{
    return make_float4(a.x * b, a.y * b, a.z * b,  a.w * b);
}

inline __device__ float4 operator*(float b, float4 a)
{
    return make_float4(b * a.x, b * a.y, b * a.z, b * a.w);
}

__global__ void nbody_kernel_reference(float dt1,
	float4* pos_old, 
	float4* pos_new,
	float4* oldVel,
	float4* newVel,
	float damping, 
	float softeningSqr)
{
	const float4 dt = make_float4(dt1, dt1, dt1, 0.0f);//(float4){.x=dt1,.y=dt1,.z=dt1,.w=0.0f};
	int gti = blockIdx.x*blockDim.x + threadIdx.x;
	int ti = threadIdx.x;
	int n = blockDim.x*gridDim.x;
	int nt = blockDim.x;
	int nb = n/nt;
	__shared__ float4 pblock[1024]; // FIXME
	float4 p = pos_old[gti];
	float4 v = oldVel[gti];
	float4 a = make_float4(0.0f);//{.x=0.0f,.y=0.0f,.z=0.0f,.w=0.0f};
	
	for(int jb=0; jb < nb; jb++) { /* Foreach block ... */
		pblock[ti] = pos_old[jb*nt+ti]; /* Cache ONE particle position */
		__syncthreads(); /* Wait for others in the work-group */
		for(int j=0; j<nt; j++) { /* For ALL cached particle positions ... */
			float4 p2 = pblock[j]; /* Read a cached particle position */
			float4 d = p2 - p;
			float invr = rsqrtf(d.x*d.x + d.y*d.y + d.z*d.z + softeningSqr);
			float f = p2.w*invr*invr*invr;
			a += f*d; /* Accumulate acceleration */
		}
		__syncthreads(); /* Wait for others in work-group */
	}
	p += dt*v + damping*dt*dt*a;
	v += dt*a;

	pos_new[gti] = p;
	newVel[gti] = v;
}


	.file	"tmpxft_002668f6_00000000-6_NbodyReference.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2017:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2017:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z60__device_stub__Z22nbody_kernel_referencefP6float4S0_S0_S0_fffP6float4S0_S0_S0_ff
	.type	_Z60__device_stub__Z22nbody_kernel_referencefP6float4S0_S0_S0_fffP6float4S0_S0_S0_ff, @function
_Z60__device_stub__Z22nbody_kernel_referencefP6float4S0_S0_S0_fffP6float4S0_S0_S0_ff:
.LFB2039:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 32(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 24(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 16(%rsp)
	leaq	48(%rsp), %rdx
	movq	%rcx, 8(%rsp)
	leaq	56(%rsp), %rcx
	movss	%xmm0, 44(%rsp)
	movss	%xmm1, 40(%rsp)
	movss	%xmm2, 4(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	44(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 112(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	56(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z22nbody_kernel_referencefP6float4S0_S0_S0_ff(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 208
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L2:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2039:
	.size	_Z60__device_stub__Z22nbody_kernel_referencefP6float4S0_S0_S0_fffP6float4S0_S0_S0_ff, .-_Z60__device_stub__Z22nbody_kernel_referencefP6float4S0_S0_S0_fffP6float4S0_S0_S0_ff
	.globl	_Z22nbody_kernel_referencefP6float4S0_S0_S0_ff
	.type	_Z22nbody_kernel_referencefP6float4S0_S0_S0_ff, @function
_Z22nbody_kernel_referencefP6float4S0_S0_S0_ff:
.LFB2040:
	.cfi_startproc
	endbr64
	jmp	_Z60__device_stub__Z22nbody_kernel_referencefP6float4S0_S0_S0_fffP6float4S0_S0_S0_ff
	.cfi_endproc
.LFE2040:
	.size	_Z22nbody_kernel_referencefP6float4S0_S0_S0_ff, .-_Z22nbody_kernel_referencefP6float4S0_S0_S0_ff
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z22nbody_kernel_referencefP6float4S0_S0_S0_ff"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2042:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z22nbody_kernel_referencefP6float4S0_S0_S0_ff(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2042:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
inline __device__ float4 make_float4(float s)
{
    return make_float4(s, s, s, s);
}

inline __device__ float4 operator+(float4 a, float4 b)
{
    return make_float4(a.x + b.x, a.y + b.y, a.z + b.z,  a.w + b.w);
}

inline __host__ __device__ float4 operator-(float4 a, float4 b)
{
    return make_float4(a.x - b.x, a.y - b.y, a.z - b.z,  a.w - b.w);
}

inline __device__ void operator+=(float4 &a, float4 b)
{
    a.x += b.x;
    a.y += b.y;
    a.z += b.z;
    a.w += b.w;
}

inline __device__ float4 operator*(float4 a, float4 b)
{
    return make_float4(a.x * b.x, a.y * b.y, a.z * b.z,  a.w * b.w);
}

inline __device__ float4 operator*(float4 a, float b)
{
    return make_float4(a.x * b, a.y * b, a.z * b,  a.w * b);
}

inline __device__ float4 operator*(float b, float4 a)
{
    return make_float4(b * a.x, b * a.y, b * a.z, b * a.w);
}

__global__ void nbody_kernel_reference(float dt1,
	float4* pos_old, 
	float4* pos_new,
	float4* oldVel,
	float4* newVel,
	float damping, 
	float softeningSqr)
{
	const float4 dt = make_float4(dt1, dt1, dt1, 0.0f);//(float4){.x=dt1,.y=dt1,.z=dt1,.w=0.0f};
	int gti = blockIdx.x*blockDim.x + threadIdx.x;
	int ti = threadIdx.x;
	int n = blockDim.x*gridDim.x;
	int nt = blockDim.x;
	int nb = n/nt;
	__shared__ float4 pblock[1024]; // FIXME
	float4 p = pos_old[gti];
	float4 v = oldVel[gti];
	float4 a = make_float4(0.0f);//{.x=0.0f,.y=0.0f,.z=0.0f,.w=0.0f};
	
	for(int jb=0; jb < nb; jb++) { /* Foreach block ... */
		pblock[ti] = pos_old[jb*nt+ti]; /* Cache ONE particle position */
		__syncthreads(); /* Wait for others in the work-group */
		for(int j=0; j<nt; j++) { /* For ALL cached particle positions ... */
			float4 p2 = pblock[j]; /* Read a cached particle position */
			float4 d = p2 - p;
			float invr = rsqrtf(d.x*d.x + d.y*d.y + d.z*d.z + softeningSqr);
			float f = p2.w*invr*invr*invr;
			a += f*d; /* Accumulate acceleration */
		}
		__syncthreads(); /* Wait for others in work-group */
	}
	p += dt*v + damping*dt*dt*a;
	v += dt*a;

	pos_new[gti] = p;
	newVel[gti] = v;
}


	.text
	.file	"NbodyReference.hip"
	.globl	_Z37__device_stub__nbody_kernel_referencefP15HIP_vector_typeIfLj4EES1_S1_S1_ff # -- Begin function _Z37__device_stub__nbody_kernel_referencefP15HIP_vector_typeIfLj4EES1_S1_S1_ff
	.type	_Z37__device_stub__nbody_kernel_referencefP15HIP_vector_typeIfLj4EES1_S1_S1_ff,@function
_Z37__device_stub__nbody_kernel_referencefP15HIP_vector_typeIfLj4EES1_S1_S1_ff: # @_Z37__device_stub__nbody_kernel_referencefP15HIP_vector_typeIfLj4EES1_S1_S1_ff
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	12(%rsp), %rax
	movss	%xmm0, (%rax)
	leaq	56(%rsp), %r8
	movq	%rdi, (%r8)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	8(%rsp), %rcx
	movss	%xmm1, (%rcx)
	leaq	4(%rsp), %r9
	movss	%xmm2, (%r9)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%r8, 8(%rbx)
	movq	%rdi, 16(%rbx)
	movq	%rsi, 24(%rbx)
	movq	%rdx, 32(%rbx)
	movq	%rcx, 40(%rbx)
	movq	%r9, 48(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z22nbody_kernel_referencefP15HIP_vector_typeIfLj4EES1_S1_S1_ff, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z37__device_stub__nbody_kernel_referencefP15HIP_vector_typeIfLj4EES1_S1_S1_ff, .Lfunc_end0-_Z37__device_stub__nbody_kernel_referencefP15HIP_vector_typeIfLj4EES1_S1_S1_ff
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z22nbody_kernel_referencefP15HIP_vector_typeIfLj4EES1_S1_S1_ff, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z22nbody_kernel_referencefP15HIP_vector_typeIfLj4EES1_S1_S1_ff,@object # @_Z22nbody_kernel_referencefP15HIP_vector_typeIfLj4EES1_S1_S1_ff
	.section	.rodata,"a",@progbits
	.globl	_Z22nbody_kernel_referencefP15HIP_vector_typeIfLj4EES1_S1_S1_ff
	.p2align	3, 0x0
_Z22nbody_kernel_referencefP15HIP_vector_typeIfLj4EES1_S1_S1_ff:
	.quad	_Z37__device_stub__nbody_kernel_referencefP15HIP_vector_typeIfLj4EES1_S1_S1_ff
	.size	_Z22nbody_kernel_referencefP15HIP_vector_typeIfLj4EES1_S1_S1_ff, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z22nbody_kernel_referencefP15HIP_vector_typeIfLj4EES1_S1_S1_ff"
	.size	.L__unnamed_1, 64

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z37__device_stub__nbody_kernel_referencefP15HIP_vector_typeIfLj4EES1_S1_S1_ff
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z22nbody_kernel_referencefP15HIP_vector_typeIfLj4EES1_S1_S1_ff
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z22nbody_kernel_referencefP15HIP_vector_typeIfLj4EES1_S1_S1_ff ; -- Begin function _Z22nbody_kernel_referencefP15HIP_vector_typeIfLj4EES1_S1_S1_ff
	.globl	_Z22nbody_kernel_referencefP15HIP_vector_typeIfLj4EES1_S1_S1_ff
	.p2align	8
	.type	_Z22nbody_kernel_referencefP15HIP_vector_typeIfLj4EES1_S1_S1_ff,@function
_Z22nbody_kernel_referencefP15HIP_vector_typeIfLj4EES1_S1_S1_ff: ; @_Z22nbody_kernel_referencefP15HIP_vector_typeIfLj4EES1_S1_S1_ff
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x3c
	s_load_b256 s[4:11], s[0:1], 0x8
	s_waitcnt lgkmcnt(0)
	s_and_b32 s12, s2, 0xffff
	s_load_b32 s2, s[0:1], 0x30
	v_mad_u64_u32 v[1:2], null, s15, s12, v[0:1]
	v_cvt_f32_u32_e32 v5, s12
	s_sub_i32 s13, 0, s12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rcp_iflag_f32_e32 v5, v5
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_lshlrev_b64 v[9:10], 4, v[1:2]
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v5, 0x4f7ffffe, v5
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s2, s2, s12
	v_add_co_u32 v1, vcc_lo, s4, v9
	v_add_co_ci_u32_e32 v2, vcc_lo, s5, v10, vcc_lo
	v_cvt_u32_f32_e32 v5, v5
	s_ashr_i32 s14, s2, 31
	global_load_b128 v[1:4], v[1:2], off
	s_add_i32 s2, s2, s14
	v_readfirstlane_b32 s3, v5
	s_xor_b32 s15, s2, s14
	v_add_co_u32 v5, vcc_lo, s8, v9
	v_add_co_ci_u32_e32 v6, vcc_lo, s9, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_mul_i32 s13, s13, s3
	s_mov_b32 s8, 0
	s_mul_hi_u32 s13, s3, s13
	s_add_i32 s3, s3, s13
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_mul_hi_u32 s13, s15, s3
	s_load_b64 s[2:3], s[0:1], 0x28
	s_mul_i32 s16, s13, s12
	s_sub_i32 s15, s15, s16
	s_add_i32 s16, s13, 1
	s_sub_i32 s17, s15, s12
	s_cmp_ge_u32 s15, s12
	s_cselect_b32 s13, s16, s13
	s_cselect_b32 s15, s17, s15
	s_add_i32 s16, s13, 1
	s_cmp_ge_u32 s15, s12
	s_cselect_b32 s13, s16, s13
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b32 s13, s13, s14
	s_sub_i32 s13, s13, s14
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_gt_i32 s13, 0
	s_cbranch_scc1 .LBB0_2
; %bb.1:                                ; %.._crit_edge_crit_edge
	s_mov_b32 s9, 0
	s_branch .LBB0_3
.LBB0_2:
	s_mov_b32 s8, -1
                                        ; implicit-def: $sgpr9
.LBB0_3:                                ; %Flow247
	global_load_b128 v[5:8], v[5:6], off
	s_and_not1_b32 vcc_lo, exec_lo, s8
	s_cbranch_vccnz .LBB0_8
; %bb.4:                                ; %.lr.ph
	v_dual_mov_b32 v12, 0 :: v_dual_lshlrev_b32 v15, 4, v0
	v_dual_mov_b32 v16, 0 :: v_dual_mov_b32 v13, 0
	v_dual_mov_b32 v11, 0 :: v_dual_mov_b32 v14, 0
	s_max_u32 s8, s12, 1
	s_mov_b32 s9, 0
.LBB0_5:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_6 Depth 2
	s_waitcnt vmcnt(1)
	v_mad_u64_u32 v[17:18], null, s9, s12, v[0:1]
	v_mov_b32_e32 v18, v16
	s_mov_b32 s14, 0
	s_mov_b32 s15, s8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[17:18], 4, v[17:18]
	v_add_co_u32 v17, vcc_lo, s4, v17
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v18, vcc_lo, s5, v18, vcc_lo
	global_load_b128 v[17:20], v[17:18], off
	s_waitcnt vmcnt(0)
	ds_store_b128 v15, v[17:20]
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
.LBB0_6:                                ;   Parent Loop BB0_5 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_mov_b32_e32 v17, s14
	s_add_i32 s15, s15, -1
	s_add_i32 s14, s14, 16
	s_cmp_eq_u32 s15, 0
	ds_load_b128 v[17:20], v17
	s_waitcnt lgkmcnt(0)
	v_dual_sub_f32 v18, v18, v2 :: v_dual_sub_f32 v17, v17, v1
	v_sub_f32_e32 v19, v19, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v21, v18, v18
	v_fmac_f32_e32 v21, v17, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v21, v19, v19
	v_add_f32_e32 v21, s3, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v22, 0x4b800000, v21
	v_cmp_gt_f32_e32 vcc_lo, 0x800000, v21
	v_cndmask_b32_e32 v21, v21, v22, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rsq_f32_e32 v21, v21
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v22, 0x45800000, v21
	v_cndmask_b32_e32 v21, v21, v22, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v22, v20, v21
	v_sub_f32_e32 v20, v20, v4
	v_mul_f32_e32 v22, v21, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v21, v21, v22
	v_fmac_f32_e32 v13, v18, v21
	v_fmac_f32_e32 v12, v17, v21
	v_fmac_f32_e32 v11, v19, v21
	v_fmac_f32_e32 v14, v20, v21
	s_cbranch_scc0 .LBB0_6
; %bb.7:                                ;   in Loop: Header=BB0_5 Depth=1
	s_add_i32 s9, s9, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s9, s13
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc0 .LBB0_5
	s_branch .LBB0_9
.LBB0_8:
	v_dual_mov_b32 v14, s9 :: v_dual_mov_b32 v11, s9
	v_dual_mov_b32 v13, s9 :: v_dual_mov_b32 v12, s9
.LBB0_9:                                ; %Flow248
	s_load_b32 s0, s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	v_mul_f32_e64 v0, s2, 0
	v_add_co_u32 v15, vcc_lo, s6, v9
	v_add_co_ci_u32_e32 v16, vcc_lo, s7, v10, vcc_lo
	v_add_co_u32 v9, vcc_lo, s10, v9
	v_add_co_ci_u32_e32 v10, vcc_lo, s11, v10, vcc_lo
	v_mul_f32_e64 v17, s0, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v0, 0, v0 :: v_dual_mul_f32 v17, s0, v17
	v_dual_mul_f32 v0, v0, v14 :: v_dual_mul_f32 v19, v17, v13
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v0, 0, v8
	v_mul_f32_e32 v18, v17, v12
	v_dual_mul_f32 v17, v17, v11 :: v_dual_fmac_f32 v8, 0, v14
	v_fmac_f32_e32 v19, s0, v6
	v_fma_f32 v6, s0, v13, v6
	v_dual_fmac_f32 v18, s0, v5 :: v_dual_fmac_f32 v17, s0, v7
	v_add_f32_e32 v4, v4, v0
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f32_e32 v2, v2, v19
	v_fma_f32 v5, s0, v12, v5
	v_add_f32_e32 v1, v1, v18
	v_add_f32_e32 v3, v3, v17
	v_fma_f32 v7, s0, v11, v7
	global_store_b128 v[15:16], v[1:4], off
	global_store_b128 v[9:10], v[5:8], off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z22nbody_kernel_referencefP15HIP_vector_typeIfLj4EES1_S1_S1_ff
		.amdhsa_group_segment_fixed_size 16384
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 304
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 23
		.amdhsa_next_free_sgpr 18
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z22nbody_kernel_referencefP15HIP_vector_typeIfLj4EES1_S1_S1_ff, .Lfunc_end0-_Z22nbody_kernel_referencefP15HIP_vector_typeIfLj4EES1_S1_S1_ff
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 784
; NumSgprs: 20
; NumVgprs: 23
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 16384 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 20
; NumVGPRsForWavesPerEU: 23
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .offset:         40
        .size:           4
        .value_kind:     by_value
      - .offset:         44
        .size:           4
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         52
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         60
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         62
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         64
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         66
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         68
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         70
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         112
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 16384
    .kernarg_segment_align: 8
    .kernarg_segment_size: 304
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z22nbody_kernel_referencefP15HIP_vector_typeIfLj4EES1_S1_S1_ff
    .private_segment_fixed_size: 0
    .sgpr_count:     20
    .sgpr_spill_count: 0
    .symbol:         _Z22nbody_kernel_referencefP15HIP_vector_typeIfLj4EES1_S1_S1_ff.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     23
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
