#include "includes.h"
/* Non-local Means -- Cuda implementation
*
* Graikos Alexandros - 8128
*/

// Padded the mirrored pixels around our image
#define image(i,j) image[((i) + vertical_radius)*(n+2*horizontal_radius) + ((j)+horizontal_radius)]

// Weight function between pixel (i,j) <-> (k,l)
#define weights(i,j,k,l) weights[((i)*n + (j))*m*n + ((k)*n + (l))]

// Gaussian filter matrix
#define gaussian_matrix(i,j) gaussian_matrix[(i)*patchSize[1] + (j)]

// Shared memory patch matrix
#define shared_memory_patch(patch,i,j) patch[((i)+horizontal_radius)*(blockDim.y+2*horizontal_radius) + ((j)+vertical_radius)]

// Filter output
#define filtered_image(i,j) filtered_image[(i)*n + j]


// Start of shared memory
extern __shared__  float gaussian_matrix[];

/* int version of pow */
__device__ float compare_patches (int m, int n, float *patch1, float *patch2, int local_x, int local_y, int target_x, int target_y, float patch_sigma, int *patchSize , float filter_sigma) {

int vertical_radius = (patchSize[0] - 1) / 2;
int horizontal_radius = (patchSize[1] - 1) / 2;

int k, l;
float euclidian_distance = 0;

for (k=-vertical_radius; k<=vertical_radius; k++) {
for (l=-horizontal_radius; l<=horizontal_radius; l++) {

// Filter value assigned to patch (x,y)
float gaussian_filter = gaussian_matrix(k+vertical_radius,l+horizontal_radius);

// Compute euclidian distance (squared) between local_pixel
// and target_pixel
euclidian_distance += gaussian_filter*gaussian_filter*
powf( shared_memory_patch(patch1, local_x+k, local_y+l) -
shared_memory_patch(patch2, target_x+k, target_y+l), 2);
}

}

return expf( -euclidian_distance / (filter_sigma));
}
__device__ float compare_patches (int m, int n, float *patch1, float *patch2, int pixel_1_x, int pixel_1_y, int pixel_2_x, int pixel_2_y, float patch_sigma, int *patchSize , float filter_sigma);


/* Loads image patch(x,y) into shared memory matrix (patch) */
__device__ void load_patch(float *patch, const float *image, int m, int n,int patch_x, int patch_y, int *patchSize) {

int i = patch_x * blockDim.x + threadIdx.x;
int j = patch_y * blockDim.y + threadIdx.y;

int vertical_radius = (patchSize[0] - 1) / 2;
int horizontal_radius = (patchSize[1] -1 ) / 2;

// Copy thread assigned pixel to shared memory
shared_memory_patch(patch, threadIdx.x, threadIdx.y) = image(i,j);

// Copy the mirrored (padded) pixels into shared memory

// Left border
if (threadIdx.x < vertical_radius) {
shared_memory_patch(patch, -threadIdx.x-1, threadIdx.y) = image(i-2*threadIdx.x-1,j);

// Upper left diagonal
if (threadIdx.y < horizontal_radius) {
shared_memory_patch(patch, -threadIdx.x-1, -threadIdx.y-1) = image(i-2*threadIdx.x-1, j-2*threadIdx.y-1);
}
}

// Upper border
if (threadIdx.y < horizontal_radius) {
shared_memory_patch(patch, threadIdx.x, -threadIdx.y-1) = image(i,j-2*threadIdx.y-1);
}

// Bottom border
if (threadIdx.x >= blockDim.x - vertical_radius) {
shared_memory_patch(patch, 2*blockDim.x - (threadIdx.x+1), threadIdx.y) = image(i+1+2*(blockDim.x-threadIdx.x-1), j);

// Botoom left diagonal
if (threadIdx.y < horizontal_radius) {
shared_memory_patch(patch, 2*blockDim.x-(threadIdx.x+1), -threadIdx.y-1) =
image(i+1+2*(blockDim.x-threadIdx.x-1),j-2*threadIdx.y-1);
}
}

// Right border
if (threadIdx.y >= blockDim.y - horizontal_radius) {
shared_memory_patch(patch, threadIdx.x, 2*blockDim.y - (threadIdx.y+1)) = image(i,j+1+2*(blockDim.y-threadIdx.y-1));

// Upper right diagonal
if (threadIdx.x < vertical_radius) {
shared_memory_patch(patch, -threadIdx.x-1, 2*blockDim.y-(threadIdx.y+1)) =
image(i-2*threadIdx.x-1, j+1+2*(blockDim.y-threadIdx.y-1));
}
}

// Bottom right diagonal
if (threadIdx.x >= (blockDim.x - vertical_radius) && threadIdx.y >= (blockDim.y - horizontal_radius)) {
shared_memory_patch(patch, 2*blockDim.x-(threadIdx.x+1),2*blockDim.y-(threadIdx.y+1)) =
image(i+1+2*(blockDim.x-threadIdx.x-1), j+1+2*(blockDim.y-threadIdx.y-1));
}

__syncthreads();

}
__device__ int int_pow(int a, int b) {
int i, prod = 1;
for (i=0; i<b; i++) {
prod *= a;
}
return prod;
}
__global__ void nlm_kernel (float const *image, float *filtered_image,int m, int n, float patch_sigma, int *patchSize, float filter_sigma) {

int vertical_radius = (patchSize[0] - 1) / 2;
int horizontal_radius = (patchSize[1] - 1) / 2;

// Compute gaussian filter
if (threadIdx.x < patchSize[0] && threadIdx.y < patchSize[1]) {
gaussian_matrix(threadIdx.x, threadIdx.y) = exp(-(int_pow(threadIdx.x-horizontal_radius,2) +
int_pow(threadIdx.y-vertical_radius,2)) / (2*(patch_sigma*patch_sigma)));
}
__syncthreads();

// Pixel coordinates assigned to thread
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;

// Addresses of shared memory matrices
float *target_patch = gaussian_matrix + patchSize[0]*patchSize[1];
float *local_patch = target_patch + (blockDim.x+2*vertical_radius)*(blockDim.y+2*horizontal_radius);

// Load local image patch assigned to block to shared memory
load_patch(local_patch, image, m, n, blockIdx.x, blockIdx.y, patchSize);

int k, l;
int patch_x, patch_y;

// Z value for current pixel
float Z = 0.f;
float filtered_pixel = 0.f;

// Load each target_patch from the image to shared memory and calculate
// weight between pixels in local patch and target patch
for (patch_x=0; patch_x<gridDim.x; patch_x++) {
for (patch_y=0; patch_y<gridDim.y; patch_y++) {
// Load image patch (x,y)
// !Do not load already present local_patch!
if (patch_x != blockIdx.x || patch_y != blockIdx.y) {
load_patch(target_patch, image, m, n, patch_x, patch_y, patchSize);
} else {
target_patch = local_patch;
}

// Calculate weights
for (k=0; k<blockDim.x; k++) {
for (l=0; l<blockDim.y; l++) {
float weight;

// Weight between ours pixel and target pixel's patch
// Consider case where local_patch equals target_patch
weight = compare_patches(m, n, local_patch, target_patch, threadIdx.x, threadIdx.y,
k, l, patch_sigma, patchSize, filter_sigma);

Z += weight;
// Add weight*pixel_value
filtered_pixel += weight*shared_memory_patch(target_patch,k,l);
}
}

// If we used local_patch for comparison reset target patch pointer
if (patch_x == blockIdx.x && patch_y == blockIdx.y) {
target_patch = gaussian_matrix + patchSize[0]*patchSize[1];
}

// Sync threads to load next patch
__syncthreads();
}
}

// Divide by Z to normalize weights
filtered_image(i,j) = filtered_pixel / Z;

return;
}
	.file	"tmpxft_00319905_00000000-6_nlm_kernel.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2013:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2013:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z15compare_patchesiiPfS_iiiifPif
	.type	_Z15compare_patchesiiPfS_iiiifPif, @function
_Z15compare_patchesiiPfS_iiiifPif:
.LFB2008:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2008:
	.size	_Z15compare_patchesiiPfS_iiiifPif, .-_Z15compare_patchesiiPfS_iiiifPif
	.globl	_Z10load_patchPfPKfiiiiPi
	.type	_Z10load_patchPfPKfiiiiPi, @function
_Z10load_patchPfPKfiiiiPi:
.LFB2009:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2009:
	.size	_Z10load_patchPfPKfiiiiPi, .-_Z10load_patchPfPKfiiiiPi
	.globl	_Z7int_powii
	.type	_Z7int_powii, @function
_Z7int_powii:
.LFB2010:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2010:
	.size	_Z7int_powii, .-_Z7int_powii
	.globl	_Z39__device_stub__Z10nlm_kernelPKfPfiifPifPKfPfiifPif
	.type	_Z39__device_stub__Z10nlm_kernelPKfPfiifPifPKfPfiifPif, @function
_Z39__device_stub__Z10nlm_kernelPKfPfiifPifPKfPfiifPif:
.LFB2035:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movl	%edx, 28(%rsp)
	leaq	48(%rsp), %rdx
	movl	%ecx, 24(%rsp)
	leaq	56(%rsp), %rcx
	movq	%r8, 8(%rsp)
	movss	%xmm0, 20(%rsp)
	movss	%xmm1, 16(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 112(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	28(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L8
	pushq	56(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z10nlm_kernelPKfPfiifPif(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 208
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L8:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L10
	call	__stack_chk_fail@PLT
.L10:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2035:
	.size	_Z39__device_stub__Z10nlm_kernelPKfPfiifPifPKfPfiifPif, .-_Z39__device_stub__Z10nlm_kernelPKfPfiifPifPKfPfiifPif
	.globl	_Z10nlm_kernelPKfPfiifPif
	.type	_Z10nlm_kernelPKfPfiifPif, @function
_Z10nlm_kernelPKfPfiifPif:
.LFB2036:
	.cfi_startproc
	endbr64
	jmp	_Z39__device_stub__Z10nlm_kernelPKfPfiifPifPKfPfiifPif
	.cfi_endproc
.LFE2036:
	.size	_Z10nlm_kernelPKfPfiifPif, .-_Z10nlm_kernelPKfPfiifPif
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z10nlm_kernelPKfPfiifPif"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2038:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z10nlm_kernelPKfPfiifPif(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2038:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include "includes.h"
/* Non-local Means -- Cuda implementation
*
* Graikos Alexandros - 8128
*/

// Padded the mirrored pixels around our image
#define image(i,j) image[((i) + vertical_radius)*(n+2*horizontal_radius) + ((j)+horizontal_radius)]

// Weight function between pixel (i,j) <-> (k,l)
#define weights(i,j,k,l) weights[((i)*n + (j))*m*n + ((k)*n + (l))]

// Gaussian filter matrix
#define gaussian_matrix(i,j) gaussian_matrix[(i)*patchSize[1] + (j)]

// Shared memory patch matrix
#define shared_memory_patch(patch,i,j) patch[((i)+horizontal_radius)*(blockDim.y+2*horizontal_radius) + ((j)+vertical_radius)]

// Filter output
#define filtered_image(i,j) filtered_image[(i)*n + j]


// Start of shared memory
extern __shared__  float gaussian_matrix[];

/* int version of pow */
__device__ float compare_patches (int m, int n, float *patch1, float *patch2, int local_x, int local_y, int target_x, int target_y, float patch_sigma, int *patchSize , float filter_sigma) {

int vertical_radius = (patchSize[0] - 1) / 2;
int horizontal_radius = (patchSize[1] - 1) / 2;

int k, l;
float euclidian_distance = 0;

for (k=-vertical_radius; k<=vertical_radius; k++) {
for (l=-horizontal_radius; l<=horizontal_radius; l++) {

// Filter value assigned to patch (x,y)
float gaussian_filter = gaussian_matrix(k+vertical_radius,l+horizontal_radius);

// Compute euclidian distance (squared) between local_pixel
// and target_pixel
euclidian_distance += gaussian_filter*gaussian_filter*
powf( shared_memory_patch(patch1, local_x+k, local_y+l) -
shared_memory_patch(patch2, target_x+k, target_y+l), 2);
}

}

return expf( -euclidian_distance / (filter_sigma));
}
__device__ float compare_patches (int m, int n, float *patch1, float *patch2, int pixel_1_x, int pixel_1_y, int pixel_2_x, int pixel_2_y, float patch_sigma, int *patchSize , float filter_sigma);


/* Loads image patch(x,y) into shared memory matrix (patch) */
__device__ void load_patch(float *patch, const float *image, int m, int n,int patch_x, int patch_y, int *patchSize) {

int i = patch_x * blockDim.x + threadIdx.x;
int j = patch_y * blockDim.y + threadIdx.y;

int vertical_radius = (patchSize[0] - 1) / 2;
int horizontal_radius = (patchSize[1] -1 ) / 2;

// Copy thread assigned pixel to shared memory
shared_memory_patch(patch, threadIdx.x, threadIdx.y) = image(i,j);

// Copy the mirrored (padded) pixels into shared memory

// Left border
if (threadIdx.x < vertical_radius) {
shared_memory_patch(patch, -threadIdx.x-1, threadIdx.y) = image(i-2*threadIdx.x-1,j);

// Upper left diagonal
if (threadIdx.y < horizontal_radius) {
shared_memory_patch(patch, -threadIdx.x-1, -threadIdx.y-1) = image(i-2*threadIdx.x-1, j-2*threadIdx.y-1);
}
}

// Upper border
if (threadIdx.y < horizontal_radius) {
shared_memory_patch(patch, threadIdx.x, -threadIdx.y-1) = image(i,j-2*threadIdx.y-1);
}

// Bottom border
if (threadIdx.x >= blockDim.x - vertical_radius) {
shared_memory_patch(patch, 2*blockDim.x - (threadIdx.x+1), threadIdx.y) = image(i+1+2*(blockDim.x-threadIdx.x-1), j);

// Botoom left diagonal
if (threadIdx.y < horizontal_radius) {
shared_memory_patch(patch, 2*blockDim.x-(threadIdx.x+1), -threadIdx.y-1) =
image(i+1+2*(blockDim.x-threadIdx.x-1),j-2*threadIdx.y-1);
}
}

// Right border
if (threadIdx.y >= blockDim.y - horizontal_radius) {
shared_memory_patch(patch, threadIdx.x, 2*blockDim.y - (threadIdx.y+1)) = image(i,j+1+2*(blockDim.y-threadIdx.y-1));

// Upper right diagonal
if (threadIdx.x < vertical_radius) {
shared_memory_patch(patch, -threadIdx.x-1, 2*blockDim.y-(threadIdx.y+1)) =
image(i-2*threadIdx.x-1, j+1+2*(blockDim.y-threadIdx.y-1));
}
}

// Bottom right diagonal
if (threadIdx.x >= (blockDim.x - vertical_radius) && threadIdx.y >= (blockDim.y - horizontal_radius)) {
shared_memory_patch(patch, 2*blockDim.x-(threadIdx.x+1),2*blockDim.y-(threadIdx.y+1)) =
image(i+1+2*(blockDim.x-threadIdx.x-1), j+1+2*(blockDim.y-threadIdx.y-1));
}

__syncthreads();

}
__device__ int int_pow(int a, int b) {
int i, prod = 1;
for (i=0; i<b; i++) {
prod *= a;
}
return prod;
}
__global__ void nlm_kernel (float const *image, float *filtered_image,int m, int n, float patch_sigma, int *patchSize, float filter_sigma) {

int vertical_radius = (patchSize[0] - 1) / 2;
int horizontal_radius = (patchSize[1] - 1) / 2;

// Compute gaussian filter
if (threadIdx.x < patchSize[0] && threadIdx.y < patchSize[1]) {
gaussian_matrix(threadIdx.x, threadIdx.y) = exp(-(int_pow(threadIdx.x-horizontal_radius,2) +
int_pow(threadIdx.y-vertical_radius,2)) / (2*(patch_sigma*patch_sigma)));
}
__syncthreads();

// Pixel coordinates assigned to thread
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;

// Addresses of shared memory matrices
float *target_patch = gaussian_matrix + patchSize[0]*patchSize[1];
float *local_patch = target_patch + (blockDim.x+2*vertical_radius)*(blockDim.y+2*horizontal_radius);

// Load local image patch assigned to block to shared memory
load_patch(local_patch, image, m, n, blockIdx.x, blockIdx.y, patchSize);

int k, l;
int patch_x, patch_y;

// Z value for current pixel
float Z = 0.f;
float filtered_pixel = 0.f;

// Load each target_patch from the image to shared memory and calculate
// weight between pixels in local patch and target patch
for (patch_x=0; patch_x<gridDim.x; patch_x++) {
for (patch_y=0; patch_y<gridDim.y; patch_y++) {
// Load image patch (x,y)
// !Do not load already present local_patch!
if (patch_x != blockIdx.x || patch_y != blockIdx.y) {
load_patch(target_patch, image, m, n, patch_x, patch_y, patchSize);
} else {
target_patch = local_patch;
}

// Calculate weights
for (k=0; k<blockDim.x; k++) {
for (l=0; l<blockDim.y; l++) {
float weight;

// Weight between ours pixel and target pixel's patch
// Consider case where local_patch equals target_patch
weight = compare_patches(m, n, local_patch, target_patch, threadIdx.x, threadIdx.y,
k, l, patch_sigma, patchSize, filter_sigma);

Z += weight;
// Add weight*pixel_value
filtered_pixel += weight*shared_memory_patch(target_patch,k,l);
}
}

// If we used local_patch for comparison reset target patch pointer
if (patch_x == blockIdx.x && patch_y == blockIdx.y) {
target_patch = gaussian_matrix + patchSize[0]*patchSize[1];
}

// Sync threads to load next patch
__syncthreads();
}
}

// Divide by Z to normalize weights
filtered_image(i,j) = filtered_pixel / Z;

return;
}
	.text
	.file	"nlm_kernel.hip"
	.globl	_Z25__device_stub__nlm_kernelPKfPfiifPif # -- Begin function _Z25__device_stub__nlm_kernelPKfPfiifPif
	.type	_Z25__device_stub__nlm_kernelPKfPfiifPif,@function
_Z25__device_stub__nlm_kernelPKfPfiifPif: # @_Z25__device_stub__nlm_kernelPKfPfiifPif
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	20(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	16(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	12(%rsp), %rcx
	movss	%xmm0, (%rcx)
	leaq	40(%rsp), %r9
	movq	%r8, (%r9)
	leaq	8(%rsp), %r8
	movss	%xmm1, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r9, 40(%rbx)
	movq	%r8, 48(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z10nlm_kernelPKfPfiifPif, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z25__device_stub__nlm_kernelPKfPfiifPif, .Lfunc_end0-_Z25__device_stub__nlm_kernelPKfPfiifPif
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z10nlm_kernelPKfPfiifPif, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z10nlm_kernelPKfPfiifPif,@object # @_Z10nlm_kernelPKfPfiifPif
	.section	.rodata,"a",@progbits
	.globl	_Z10nlm_kernelPKfPfiifPif
	.p2align	3, 0x0
_Z10nlm_kernelPKfPfiifPif:
	.quad	_Z25__device_stub__nlm_kernelPKfPfiifPif
	.size	_Z10nlm_kernelPKfPfiifPif, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z10nlm_kernelPKfPfiifPif"
	.size	.L__unnamed_1, 26

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z25__device_stub__nlm_kernelPKfPfiifPif
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z10nlm_kernelPKfPfiifPif
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.p2align	2                               ; -- Begin function _Z10load_patchPfPKfiiiiPi
	.type	_Z10load_patchPfPKfiiiiPi,@function
_Z10load_patchPfPKfiiiiPi:              ; @_Z10load_patchPfPKfiiiiPi
; %bb.0:
	s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	flat_load_b64 v[7:8], v[7:8]
	s_load_b64 s[0:1], s[8:9], 0x0
	v_and_b32_e32 v10, 0x3ff, v31
	s_waitcnt lgkmcnt(0)
	s_cmp_lt_u32 s12, s0
	s_cselect_b32 s0, 12, 18
	s_cmp_lt_u32 s13, s1
	v_mov_b32_e32 v9, s0
	s_cselect_b32 s0, 14, 20
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v8, -1, v8
	global_load_u16 v16, v9, s[8:9]
	v_mov_b32_e32 v9, s0
	v_add_nc_u32_e32 v7, -1, v7
	global_load_u16 v17, v9, s[8:9]
	v_lshrrev_b32_e32 v9, 31, v8
	v_lshrrev_b32_e32 v11, 31, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v12, v8, v9
	v_add_nc_u32_e32 v7, v7, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v14, -2, v12
	v_ashrrev_i32_e32 v18, 1, v7
	v_ashrrev_i32_e32 v19, 1, v12
	s_delay_alu instid0(VALU_DEP_3)
	v_add_nc_u32_e32 v7, v14, v4
	s_waitcnt vmcnt(1)
	v_mad_u64_u32 v[8:9], null, v16, v5, v[10:11]
	v_bfe_u32 v9, v31, 10, 10
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v20, v14, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mad_u64_u32 v[4:5], null, v17, v6, v[9:10]
	v_add_nc_u32_e32 v21, v18, v8
	v_add_nc_u32_e32 v24, v18, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mul_lo_u32 v22, v7, v21
	v_add_nc_u32_e32 v5, v19, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v11, v22, v5
	v_ashrrev_i32_e32 v12, 31, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[12:13], 2, v[11:12]
	v_add_co_u32 v12, vcc_lo, v2, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v13, vcc_lo, v3, v13, vcc_lo
	flat_load_b32 v6, v[12:13]
	v_dual_mov_b32 v13, 0 :: v_dual_add_nc_u32 v12, v19, v10
	v_mul_lo_u32 v23, v20, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v12, v23, v24
	v_lshlrev_b64 v[14:15], 2, v[12:13]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v14, vcc_lo, v0, v14
	v_add_co_ci_u32_e32 v15, vcc_lo, v1, v15, vcc_lo
	v_cmp_lt_u32_e32 vcc_lo, v10, v18
	s_waitcnt vmcnt(0) lgkmcnt(0)
	flat_store_b32 v[14:15], v6
	s_and_saveexec_b32 s1, vcc_lo
	s_cbranch_execz .LBB0_3
; %bb.1:
	v_lshlrev_b32_e32 v6, 1, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xad_u32 v6, v6, -1, v21
	v_mad_u64_u32 v[14:15], null, v7, v6, v[5:6]
	v_mov_b32_e32 v15, v13
	v_xad_u32 v6, v10, -1, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_lo_u32 v6, v20, v6
	v_lshlrev_b64 v[25:26], 2, v[14:15]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v25, s0, v2, v25
	v_add_co_ci_u32_e64 v26, s0, v3, v26, s0
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v12, v6, v24
	flat_load_b32 v15, v[25:26]
	v_lshlrev_b64 v[12:13], 2, v[12:13]
	v_add_co_u32 v12, s0, v0, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v13, s0, v1, v13, s0
	v_cmp_lt_u32_e64 s0, v9, v19
	s_waitcnt vmcnt(0) lgkmcnt(0)
	flat_store_b32 v[12:13], v15
	s_and_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB0_3
; %bb.2:
	v_dual_mov_b32 v13, 0 :: v_dual_lshlrev_b32 v12, 1, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xad_u32 v12, v12, -1, v14
	v_lshlrev_b64 v[14:15], 2, v[12:13]
	v_not_b32_e32 v12, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add3_u32 v12, v18, v12, v6
	v_add_co_u32 v14, s0, v2, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v15, s0, v3, v15, s0
	v_lshlrev_b64 v[12:13], 2, v[12:13]
	flat_load_b32 v14, v[14:15]
	v_add_co_u32 v12, s0, v0, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v13, s0, v1, v13, s0
	s_waitcnt vmcnt(0) lgkmcnt(0)
	flat_store_b32 v[12:13], v14
.LBB0_3:
	s_or_b32 exec_lo, exec_lo, s1
	v_cmp_lt_u32_e64 s1, v9, v19
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s2, s1
	s_cbranch_execz .LBB0_5
; %bb.4:
	v_lshlrev_b32_e32 v6, 1, v9
	v_mov_b32_e32 v12, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xad_u32 v11, v6, -1, v11
	v_lshlrev_b64 v[13:14], 2, v[11:12]
	v_not_b32_e32 v11, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add3_u32 v11, v18, v11, v23
	v_add_co_u32 v13, s0, v2, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v14, s0, v3, v14, s0
	v_lshlrev_b64 v[11:12], 2, v[11:12]
	flat_load_b32 v6, v[13:14]
	v_add_co_u32 v11, s0, v0, v11
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v12, s0, v1, v12, s0
	s_waitcnt vmcnt(0) lgkmcnt(0)
	flat_store_b32 v[11:12], v6
.LBB0_5:
	s_or_b32 exec_lo, exec_lo, s2
	v_sub_nc_u32_e32 v6, v16, v18
	v_xad_u32 v12, v10, -1, v16
	s_mov_b32 s3, exec_lo
	s_delay_alu instid0(VALU_DEP_2)
	v_cmp_lt_u32_e64 s0, v10, v6
	v_cmpx_ge_u32_e64 v10, v6
	s_cbranch_execz .LBB0_8
; %bb.6:
	v_lshlrev_b32_e32 v6, 1, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v6, v8, v6, v18
	v_mul_lo_u32 v11, v7, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add3_u32 v5, v11, v7, v5
	v_add3_u32 v11, v12, v16, v19
	v_mul_lo_u32 v11, v20, v11
	v_mov_b32_e32 v6, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[13:14], 2, v[5:6]
	v_add_co_u32 v13, s2, v2, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e64 v14, s2, v3, v14, s2
	flat_load_b32 v15, v[13:14]
	v_dual_mov_b32 v14, v6 :: v_dual_add_nc_u32 v13, v11, v24
	v_lshlrev_b64 v[13:14], 2, v[13:14]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v13, s2, v0, v13
	v_add_co_ci_u32_e64 v14, s2, v1, v14, s2
	s_waitcnt vmcnt(0) lgkmcnt(0)
	flat_store_b32 v[13:14], v15
	s_and_b32 exec_lo, exec_lo, s1
	s_cbranch_execz .LBB0_8
; %bb.7:
	v_lshlrev_b32_e32 v13, 1, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xad_u32 v5, v13, -1, v5
	v_lshlrev_b64 v[13:14], 2, v[5:6]
	v_not_b32_e32 v5, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add3_u32 v5, v18, v5, v11
	v_add_co_u32 v13, s1, v2, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v14, s1, v3, v14, s1
	v_lshlrev_b64 v[5:6], 2, v[5:6]
	flat_load_b32 v13, v[13:14]
	v_add_co_u32 v5, s1, v0, v5
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v6, s1, v1, v6, s1
	s_waitcnt vmcnt(0) lgkmcnt(0)
	flat_store_b32 v[5:6], v13
.LBB0_8:
	s_or_b32 exec_lo, exec_lo, s3
	v_sub_nc_u32_e32 v5, v17, v19
	v_xad_u32 v13, v9, -1, v17
	s_mov_b32 s3, exec_lo
	s_delay_alu instid0(VALU_DEP_2)
	v_cmp_lt_u32_e64 s1, v9, v5
	v_cmpx_ge_u32_e64 v9, v5
	s_cbranch_execz .LBB0_11
; %bb.9:
	v_lshl_add_u32 v5, v13, 1, v4
	v_add3_u32 v11, v13, v17, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v9, v5, v19, 1
	v_dual_mov_b32 v6, 0 :: v_dual_add_nc_u32 v5, v22, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_lshlrev_b64 v[14:15], 2, v[5:6]
	v_add_nc_u32_e32 v5, v23, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v14, s2, v2, v14
	v_add_co_ci_u32_e64 v15, s2, v3, v15, s2
	flat_load_b32 v22, v[14:15]
	v_lshlrev_b64 v[14:15], 2, v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v14, s2, v0, v14
	v_add_co_ci_u32_e64 v15, s2, v1, v15, s2
	s_waitcnt vmcnt(0) lgkmcnt(0)
	flat_store_b32 v[14:15], v22
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_11
; %bb.10:
	v_lshlrev_b32_e32 v5, 1, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xad_u32 v5, v5, -1, v21
	v_mad_u64_u32 v[14:15], null, v7, v5, v[9:10]
	v_mov_b32_e32 v15, v6
	v_xad_u32 v5, v10, -1, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_mad_u64_u32 v[9:10], null, v20, v5, v[11:12]
	v_mov_b32_e32 v10, v6
	v_lshlrev_b64 v[14:15], 2, v[14:15]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[5:6], 2, v[9:10]
	v_add_co_u32 v14, vcc_lo, v2, v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v15, vcc_lo, v3, v15, vcc_lo
	v_add_co_u32 v5, vcc_lo, v0, v5
	flat_load_b32 v14, v[14:15]
	v_add_co_ci_u32_e32 v6, vcc_lo, v1, v6, vcc_lo
	s_waitcnt vmcnt(0) lgkmcnt(0)
	flat_store_b32 v[5:6], v14
.LBB0_11:
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s0, s0, s1
	s_xor_b32 s1, s0, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s0, s1
	s_cbranch_execz .LBB0_13
; %bb.12:
	v_lshlrev_b32_e32 v5, 1, v12
	v_lshlrev_b32_e32 v9, 1, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add3_u32 v8, v8, v5, v18
	v_add3_u32 v4, v4, v9, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[5:6], null, v7, v8, v[7:8]
	v_mov_b32_e32 v6, 0
	v_add3_u32 v5, v4, v5, 1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 2, v[5:6]
	v_add_co_u32 v2, vcc_lo, v2, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, v3, v5, vcc_lo
	flat_load_b32 v4, v[2:3]
	v_add3_u32 v2, v12, v16, v19
	v_add_nc_u32_e32 v3, v13, v17
	v_mul_lo_u32 v2, v20, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v5, v3, v18, v2
	v_lshlrev_b64 v[2:3], 2, v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, v2
	v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo
	s_waitcnt vmcnt(0) lgkmcnt(0)
	flat_store_b32 v[0:1], v4
.LBB0_13:
	s_or_b32 exec_lo, exec_lo, s0
	s_waitcnt lgkmcnt(0)
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_setpc_b64 s[30:31]
.Lfunc_end0:
	.size	_Z10load_patchPfPKfiiiiPi, .Lfunc_end0-_Z10load_patchPfPKfiiiiPi
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Function info:
; codeLenInByte = 1516
; NumSgprs: 34
; NumVgprs: 32
; ScratchSize: 0
; MemoryBound: 0
	.text
	.protected	_Z10nlm_kernelPKfPfiifPif ; -- Begin function _Z10nlm_kernelPKfPfiifPif
	.globl	_Z10nlm_kernelPKfPfiifPif
	.p2align	8
	.type	_Z10nlm_kernelPKfPfiifPif,@function
_Z10nlm_kernelPKfPfiifPif:              ; @_Z10nlm_kernelPKfPfiifPif
; %bb.0:
	s_load_b64 s[10:11], s[0:1], 0x20
	s_mov_b64 s[4:5], s[0:1]
	v_mov_b32_e32 v31, v0
	s_mov_b32 s13, s15
	s_mov_b32 s12, s14
	s_mov_b32 s32, 0
	s_waitcnt lgkmcnt(0)
	s_load_b64 s[0:1], s[10:11], 0x0
	s_load_b64 s[6:7], s[4:5], 0x14
	v_and_b32_e32 v28, 0x3ff, v31
	v_bfe_u32 v27, v31, 10, 10
	s_waitcnt lgkmcnt(0)
	s_add_i32 s2, s0, -1
	s_add_i32 s3, s1, -1
	v_cmp_gt_u32_e32 vcc_lo, s0, v28
	v_cmp_gt_u32_e64 s0, s1, v27
	s_lshr_b32 s8, s2, 31
	s_lshr_b32 s9, s3, 31
	s_add_i32 s2, s2, s8
	s_add_i32 s3, s3, s9
	s_ashr_i32 s22, s2, 1
	s_ashr_i32 s23, s3, 1
	s_and_b32 s2, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s0, s2
	s_cbranch_execz .LBB1_2
; %bb.1:
	v_subrev_nc_u32_e32 v0, s23, v28
	v_subrev_nc_u32_e32 v3, s22, v27
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v0, v0, v0
	v_mad_u64_u32 v[1:2], null, v3, v3, v[0:1]
	v_mul_f32_e64 v0, s7, s7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v0, v0, v0
	v_sub_nc_u32_e32 v1, 0, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f32_i32_e32 v1, v1
	v_div_scale_f32 v2, null, v0, v0, v1
	v_div_scale_f32 v5, vcc_lo, v1, v0, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v3, v2
	s_waitcnt_depctr 0xfff
	v_fma_f32 v4, -v2, v3, 1.0
	v_fmac_f32_e32 v3, v4, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v4, v5, v3
	v_fma_f32 v6, -v2, v4, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v4, v6, v3
	v_fma_f32 v2, -v2, v4, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v2, v2, v3, v4
	v_div_fixup_f32 v2, v2, v0, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v0, 0x3fb8aa3b, v2
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v2
	v_fma_f32 v1, 0x3fb8aa3b, v2, -v0
	v_rndne_f32_e32 v3, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmamk_f32 v1, v2, 0x32a5705f, v1 :: v_dual_sub_f32 v0, v0, v3
	v_add_f32_e32 v0, v0, v1
	v_cvt_i32_f32_e32 v1, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_exp_f32_e32 v0, v0
	s_waitcnt_depctr 0xfff
	v_ldexp_f32 v3, v0, v1
	v_mad_u64_u32 v[0:1], null, s1, v28, v[27:28]
	v_cndmask_b32_e32 v1, 0, v3, vcc_lo
	v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshl_add_u32 v0, v0, 2, 0
	v_cndmask_b32_e32 v1, 0x7f800000, v1, vcc_lo
	ds_store_b32 v0, v1
.LBB1_2:                                ; %._crit_edge128
	s_or_b32 exec_lo, exec_lo, s0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_load_b32 s2, s[4:5], 0x3c
	s_load_b64 s[0:1], s[10:11], 0x0
	s_clause 0x1
	s_load_b128 s[16:19], s[4:5], 0x0
	s_load_b64 s[14:15], s[4:5], 0x30
	s_lshl_b32 s3, s22, 1
	s_lshl_b32 s25, s23, 1
	s_mov_b64 s[20:21], src_shared_base
	v_dual_mov_b32 v4, s6 :: v_dual_mov_b32 v5, s12
	v_dual_mov_b32 v6, s13 :: v_dual_mov_b32 v7, s10
	v_mov_b32_e32 v8, s11
	s_mov_b32 s27, 0
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s7, s2, 16
	s_and_b32 s24, s2, 0xffff
	s_mul_i32 s0, s1, s0
	s_add_i32 s3, s3, s24
	s_add_i32 s25, s25, s7
	s_lshl_b32 s34, s0, 2
	s_mul_i32 s0, s25, s3
	s_add_i32 s39, s34, 0
	s_lshl_b32 s35, s0, 2
	v_dual_mov_b32 v2, s16 :: v_dual_mov_b32 v3, s17
	s_add_i32 s26, s39, s35
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_cmp_lg_u32 s26, -1
	s_cselect_b32 s2, s26, 0
	s_cselect_b32 s3, s21, 0
	v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
	s_add_u32 s8, s4, 48
	s_addc_u32 s9, s5, 0
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, _Z10load_patchPfPKfiiiiPi@rel32@lo+4
	s_addc_u32 s1, s1, _Z10load_patchPfPKfiiiiPi@rel32@hi+12
	s_delay_alu instid0(SALU_CYCLE_1)
	s_swappc_b64 s[30:31], s[0:1]
	s_cmp_eq_u32 s14, 0
	s_cbranch_scc1 .LBB1_28
; %bb.3:                                ; %.preheader90.lr.ph
	s_load_b32 s20, s[4:5], 0x28
	s_cmp_lg_u32 s15, 0
	v_dual_mov_b32 v29, 0 :: v_dual_lshlrev_b32 v0, 2, v27
	s_cselect_b32 s28, -1, 0
	s_cmp_lg_u32 s24, 0
	v_dual_mov_b32 v33, 0 :: v_dual_mov_b32 v30, 0
	s_cselect_b32 s29, -1, 0
	s_cmp_lg_u32 s7, 0
	s_cselect_b32 s33, -1, 0
	s_add_i32 s34, s34, s35
	s_mov_b32 s35, 0x3e76c4e1
	v_add3_u32 v32, 0, s34, v0
	s_lshl_b32 s34, s7, 2
.LBB1_4:                                ; %.preheader90
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB1_6 Depth 2
                                        ;       Child Loop BB1_10 Depth 3
                                        ;         Child Loop BB1_12 Depth 4
                                        ;           Child Loop BB1_14 Depth 5
                                        ;             Child Loop BB1_15 Depth 6
	s_and_not1_b32 vcc_lo, exec_lo, s28
	s_cbranch_vccnz .LBB1_24
; %bb.5:                                ; %.lr.ph107
                                        ;   in Loop: Header=BB1_4 Depth=1
	s_cmp_eq_u32 s27, s12
	s_mov_b32 s36, 0
	s_cselect_b32 s37, -1, 0
.LBB1_6:                                ;   Parent Loop BB1_4 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB1_10 Depth 3
                                        ;         Child Loop BB1_12 Depth 4
                                        ;           Child Loop BB1_14 Depth 5
                                        ;             Child Loop BB1_15 Depth 6
	s_cmp_eq_u32 s36, s13
	s_mov_b32 s2, s26
	s_cselect_b32 s0, -1, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s38, s37, s0
	s_and_b32 vcc_lo, exec_lo, s38
	s_cbranch_vccnz .LBB1_8
; %bb.7:                                ;   in Loop: Header=BB1_6 Depth=2
	s_cmp_lg_u32 s39, -1
	v_dual_mov_b32 v2, s16 :: v_dual_mov_b32 v3, s17
	s_cselect_b32 s2, s39, 0
	s_cselect_b32 s3, s21, 0
	s_delay_alu instid0(SALU_CYCLE_1)
	v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
	v_dual_mov_b32 v4, s6 :: v_dual_mov_b32 v5, s27
	v_dual_mov_b32 v6, s36 :: v_dual_mov_b32 v7, s10
	v_mov_b32_e32 v8, s11
	s_add_u32 s8, s4, 48
	s_addc_u32 s9, s5, 0
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, _Z10load_patchPfPKfiiiiPi@rel32@lo+4
	s_addc_u32 s1, s1, _Z10load_patchPfPKfiiiiPi@rel32@hi+12
	s_delay_alu instid0(SALU_CYCLE_1)
	s_swappc_b64 s[30:31], s[0:1]
	s_mov_b32 s2, s39
.LBB1_8:                                ;   in Loop: Header=BB1_6 Depth=2
	s_and_not1_b32 vcc_lo, exec_lo, s29
	s_cbranch_vccnz .LBB1_20
; %bb.9:                                ; %.preheader.preheader
                                        ;   in Loop: Header=BB1_6 Depth=2
	s_mov_b32 s3, 0
.LBB1_10:                               ; %.preheader
                                        ;   Parent Loop BB1_4 Depth=1
                                        ;     Parent Loop BB1_6 Depth=2
                                        ; =>    This Loop Header: Depth=3
                                        ;         Child Loop BB1_12 Depth 4
                                        ;           Child Loop BB1_14 Depth 5
                                        ;             Child Loop BB1_15 Depth 6
	s_and_not1_b32 vcc_lo, exec_lo, s33
	s_cbranch_vccnz .LBB1_19
; %bb.11:                               ; %.lr.ph
                                        ;   in Loop: Header=BB1_10 Depth=3
	global_load_b64 v[0:1], v33, s[10:11]
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s1, v1
	v_readfirstlane_b32 s0, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_add_i32 s9, s1, -1
	s_add_i32 s8, s0, -1
	s_lshr_b32 s31, s9, 31
	s_lshr_b32 s30, s8, 31
	s_add_i32 s39, s9, s31
	s_add_i32 s8, s8, s30
	s_ashr_i32 s42, s39, 1
	s_ashr_i32 s41, s8, 1
	v_add_nc_u32_e32 v0, s42, v28
	s_sub_i32 s8, 0, s41
	s_cmp_gt_i32 s0, -1
	s_mov_b32 s30, 0
	s_cselect_b32 s9, -1, 0
	s_cmp_gt_i32 s1, -1
	v_subrev_nc_u32_e32 v0, s41, v0
	s_cselect_b32 s31, -1, 0
	s_and_b32 s0, s39, -2
	s_lshl_b32 s43, s41, 2
	s_add_i32 s0, s0, s7
	s_add_i32 s46, s42, s3
	v_mul_lo_u32 v0, v0, s0
	s_lshl_b32 s44, s42, 2
	s_sub_i32 s46, s46, s41
	s_abs_i32 s39, s41
	s_mul_i32 s46, s46, s0
	s_abs_i32 s47, s42
	s_add_i32 s41, s41, s46
	s_add_i32 s40, s3, s23
	v_lshl_add_u32 v0, v0, 2, s43
	s_lshl_b32 s45, s42, 3
	s_add_i32 s0, s42, s47
	s_sub_i32 s42, s41, s42
	s_mul_i32 s43, s40, s25
	v_subrev_nc_u32_e32 v0, s44, v0
	s_lshl_b32 s42, s42, 2
	s_add_i32 s40, s34, s45
	s_add_i32 s41, s43, s22
	s_add_i32 s42, s2, s42
	v_add_nc_u32_e32 v0, v32, v0
	s_add_i32 s43, s0, 1
	s_lshl_b32 s44, s1, 2
.LBB1_12:                               ;   Parent Loop BB1_4 Depth=1
                                        ;     Parent Loop BB1_6 Depth=2
                                        ;       Parent Loop BB1_10 Depth=3
                                        ; =>      This Loop Header: Depth=4
                                        ;           Child Loop BB1_14 Depth 5
                                        ;             Child Loop BB1_15 Depth 6
	v_mov_b32_e32 v1, 0
	s_and_not1_b32 vcc_lo, exec_lo, s9
	s_cbranch_vccnz .LBB1_18
; %bb.13:                               ; %.lr.ph48.i
                                        ;   in Loop: Header=BB1_12 Depth=4
	v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v2, v0
	s_mov_b32 s45, 0
	s_mov_b32 s46, s42
	s_mov_b32 s47, s8
.LBB1_14:                               ;   Parent Loop BB1_4 Depth=1
                                        ;     Parent Loop BB1_6 Depth=2
                                        ;       Parent Loop BB1_10 Depth=3
                                        ;         Parent Loop BB1_12 Depth=4
                                        ; =>        This Loop Header: Depth=5
                                        ;             Child Loop BB1_15 Depth 6
	s_delay_alu instid0(VALU_DEP_1)
	v_mov_b32_e32 v3, v2
	s_mov_b32 s48, s45
	s_and_not1_b32 vcc_lo, exec_lo, s31
	s_mov_b32 s49, s43
	s_mov_b32 s50, s46
	s_cbranch_vccnz .LBB1_16
.LBB1_15:                               ;   Parent Loop BB1_4 Depth=1
                                        ;     Parent Loop BB1_6 Depth=2
                                        ;       Parent Loop BB1_10 Depth=3
                                        ;         Parent Loop BB1_12 Depth=4
                                        ;           Parent Loop BB1_14 Depth=5
                                        ; =>          This Inner Loop Header: Depth=6
	v_mov_b32_e32 v4, s50
	s_add_i32 s49, s49, -1
	s_add_i32 s50, s50, 4
	ds_load_b32 v5, v3
	ds_load_b32 v4, v4
	s_waitcnt lgkmcnt(0)
	v_dual_sub_f32 v4, v5, v4 :: v_dual_add_nc_u32 v3, 4, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_frexp_mant_f32_e64 v5, |v4|
	v_frexp_exp_i32_f32_e32 v6, v4
	v_cmp_gt_f32_e32 vcc_lo, 0x3f2aaaab, v5
	v_cndmask_b32_e64 v7, 0, 1, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_subrev_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
	v_ldexp_f32 v5, v5, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_f32_i32_e32 v6, v6
	v_add_f32_e32 v7, 1.0, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v11, 0x3f317218, v6
	v_cmp_eq_f32_e32 vcc_lo, 1.0, v4
	v_rcp_f32_e32 v9, v7
	v_add_f32_e32 v10, -1.0, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
	v_dual_add_f32 v8, -1.0, v5 :: v_dual_sub_f32 v5, v5, v10
	v_fma_f32 v10, 0x3f317218, v6, -v11
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v12, v8, v9
	v_fmac_f32_e32 v10, 0xb102e308, v6
	v_mul_f32_e32 v6, v7, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v7, v12, v7, -v6
	v_fmac_f32_e32 v7, v12, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v5, v6, v7
	v_dual_sub_f32 v13, v8, v5 :: v_dual_sub_f32 v6, v5, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v8, v8, v13
	v_dual_sub_f32 v6, v6, v7 :: v_dual_sub_f32 v5, v8, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v5, v6, v5
	v_add_f32_e32 v5, v13, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v5, v9, v5
	v_add_f32_e32 v6, v12, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v7, v6, v12
	v_dual_mul_f32 v8, v6, v6 :: v_dual_sub_f32 v5, v5, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fma_f32 v7, v6, v6, -v8
	v_ldexp_f32 v9, v6, 1
	v_add_f32_e32 v12, v5, v5
	v_ldexp_f32 v13, v5, 1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v7, v6, v12
	v_add_f32_e32 v12, v8, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmaak_f32 v14, s35, v12, 0x3e91f4c4
	v_sub_f32_e32 v8, v12, v8
	v_dual_fmaak_f32 v14, v12, v14, 0x3ecccdef :: v_dual_mul_f32 v15, v6, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v7, v7, v8 :: v_dual_mul_f32 v16, v12, v14
	v_fma_f32 v8, v12, v6, -v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v8, v12, v5
	v_fma_f32 v5, v12, v14, -v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v8, v7, v6
	v_fmac_f32_e32 v5, v7, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v7, v16, v5
	v_sub_f32_e32 v14, v7, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v5, v5, v14
	v_dual_add_f32 v5, 0x31739010, v5 :: v_dual_add_f32 v6, v15, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v12, v6, v15
	v_dual_add_f32 v15, 0x3f2aaaaa, v7 :: v_dual_sub_f32 v8, v8, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v12, 0xbf2aaaaa, v15
	v_sub_f32_e32 v7, v7, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v5, v5, v7
	v_add_f32_e32 v7, v15, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v12, v15, v7
	v_dual_mul_f32 v14, v6, v7 :: v_dual_add_f32 v5, v5, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v12, v6, v7, -v14
	v_fmac_f32_e32 v12, v6, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v12, v8, v7
	v_add_f32_e32 v5, v14, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f32_e32 v6, v9, v5
	v_sub_f32_e32 v7, v5, v14
	v_dual_sub_f32 v7, v12, v7 :: v_dual_sub_f32 v8, v6, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v7, v13, v7
	v_dual_sub_f32 v5, v5, v8 :: v_dual_add_f32 v8, v11, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v5, v7, v5
	v_sub_f32_e32 v7, v8, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v9, v6, v5
	v_dual_sub_f32 v7, v10, v7 :: v_dual_add_f32 v10, v8, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v6, v9, v6 :: v_dual_sub_f32 v11, v10, v8
	v_dual_sub_f32 v5, v5, v6 :: v_dual_sub_f32 v6, v10, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v9, v9, v11 :: v_dual_sub_f32 v6, v8, v6
	v_dual_add_f32 v11, v7, v5 :: v_dual_add_f32 v6, v9, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v8, v11, v7
	v_dual_add_f32 v6, v11, v6 :: v_dual_sub_f32 v5, v5, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v9, v11, v8 :: v_dual_add_f32 v8, v10, v6
	v_sub_f32_e32 v7, v7, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v9, v8, v10
	v_dual_add_f32 v5, v5, v7 :: v_dual_sub_f32 v6, v6, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f32_e32 v5, v5, v6
	v_cndmask_b32_e64 v6, 2.0, 1.0, vcc_lo
	v_add_f32_e32 v7, v8, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v8, v7, v8 :: v_dual_mul_f32 v9, v6, v7
	v_sub_f32_e32 v5, v5, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v7, v6, v7, -v9
	v_cmp_class_f32_e64 vcc_lo, v9, 0x204
	v_fmac_f32_e32 v7, v6, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v5, v9, v7
	v_cndmask_b32_e32 v8, v5, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_f32_e32 vcc_lo, 0x42b17218, v8
	v_cndmask_b32_e64 v10, 0, 0x37000000, vcc_lo
	v_sub_f32_e32 v11, v8, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v12, 0x3fb8aa3b, v11
	v_fma_f32 v13, 0x3fb8aa3b, v11, -v12
	v_rndne_f32_e32 v14, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_fmac_f32 v13, 0x32a5705f, v11 :: v_dual_sub_f32 v12, v12, v14
	v_sub_f32_e32 v5, v5, v9
	v_cvt_i32_f32_e32 v9, v14
	v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v8|
	v_trunc_f32_e32 v8, v6
	v_add_f32_e32 v12, v12, v13
	v_sub_f32_e32 v5, v7, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_exp_f32_e32 v12, v12
	v_cndmask_b32_e32 v5, 0, v5, vcc_lo
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_add_f32_e32 v5, v10, v5
	s_waitcnt_depctr 0xfff
	v_ldexp_f32 v7, v12, v9
	v_mul_f32_e32 v9, 0.5, v6
	v_cndmask_b32_e32 v7, 0, v7, vcc_lo
	v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_trunc_f32_e32 v12, v9
	v_cndmask_b32_e32 v7, 0x7f800000, v7, vcc_lo
	v_cmp_eq_f32_e32 vcc_lo, v8, v6
	s_delay_alu instid0(VALU_DEP_3)
	v_cmp_neq_f32_e64 s0, v12, v9
	v_mov_b32_e32 v6, s48
	s_add_i32 s48, s48, 4
	v_fma_f32 v5, v7, v5, v7
	v_cmp_eq_f32_e64 s1, 0x7f800000, v7
	s_and_b32 s0, vcc_lo, s0
	ds_load_b32 v6, v6
	v_cndmask_b32_e64 v8, 1.0, v4, s0
	v_cndmask_b32_e64 v5, v5, v7, s1
	v_cmp_eq_f32_e64 s1, 0, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_bfi_b32 v5, 0x7fffffff, v5, v8
	v_cndmask_b32_e64 v7, 0x7f800000, 0, s1
	v_cndmask_b32_e64 v8, 0, v4, s0
	v_cmp_class_f32_e64 s0, v4, 0x204
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cndmask_b32_e32 v9, 0x7fc00000, v5, vcc_lo
	v_cmp_gt_f32_e32 vcc_lo, 0, v4
	v_bfi_b32 v7, 0x7fffffff, v7, v8
	s_delay_alu instid0(VALU_DEP_3)
	v_cndmask_b32_e32 v5, v5, v9, vcc_lo
	s_or_b32 vcc_lo, s1, s0
	s_waitcnt lgkmcnt(0)
	v_mul_f32_e32 v6, v6, v6
	s_cmp_lg_u32 s49, 0
	v_cndmask_b32_e32 v5, v5, v7, vcc_lo
	v_cmp_o_f32_e32 vcc_lo, v4, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v4, 0x7fc00000, v5, vcc_lo
	v_fmac_f32_e32 v1, v6, v4
	s_cbranch_scc1 .LBB1_15
.LBB1_16:                               ; %._crit_edge.i
                                        ;   in Loop: Header=BB1_14 Depth=5
	v_add_nc_u32_e32 v2, s40, v2
	s_add_i32 s0, s47, 1
	s_add_i32 s46, s46, s40
	s_add_i32 s45, s45, s44
	s_cmp_lg_u32 s47, s39
	s_cbranch_scc0 .LBB1_18
; %bb.17:                               ;   in Loop: Header=BB1_14 Depth=5
	s_mov_b32 s47, s0
	s_branch .LBB1_14
.LBB1_18:                               ; %_Z15compare_patchesiiPfS_iiiifPif.exit
                                        ;   in Loop: Header=BB1_12 Depth=4
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_div_scale_f32 v2, null, s20, s20, -v1
	v_div_scale_f32 v5, vcc_lo, -v1, s20, -v1
	s_add_i32 s0, s41, s30
	v_rcp_f32_e32 v3, v2
	s_lshl_b32 s0, s0, 2
	s_add_i32 s30, s30, 1
	s_add_i32 s0, s2, s0
	s_add_i32 s42, s42, 4
	s_cmp_lg_u32 s30, s7
	s_waitcnt_depctr 0xfff
	v_fma_f32 v4, -v2, v3, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v3, v4, v3
	v_mul_f32_e32 v4, v5, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v6, -v2, v4, v5
	v_fmac_f32_e32 v4, v6, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v2, -v2, v4, v5
	v_div_fmas_f32 v2, v2, v3, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f32 v1, v2, s20, -v1
	v_mul_f32_e32 v2, 0x3fb8aa3b, v1
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f32 v3, 0x3fb8aa3b, v1, -v2
	v_rndne_f32_e32 v4, v2
	v_dual_fmac_f32 v3, 0x32a5705f, v1 :: v_dual_sub_f32 v2, v2, v4
	v_cvt_i32_f32_e32 v4, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v2, v2, v3 :: v_dual_mov_b32 v3, s0
	v_exp_f32_e32 v2, v2
	ds_load_b32 v3, v3
	v_ldexp_f32 v2, v2, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v2, 0, v2, vcc_lo
	v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v1
	v_cndmask_b32_e32 v1, 0x7f800000, v2, vcc_lo
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v29, v3, v1
	v_add_f32_e32 v30, v30, v1
	s_cbranch_scc1 .LBB1_12
.LBB1_19:                               ; %._crit_edge
                                        ;   in Loop: Header=BB1_10 Depth=3
	s_add_i32 s3, s3, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u32 s3, s24
	s_cbranch_scc1 .LBB1_10
.LBB1_20:                               ; %._crit_edge100
                                        ;   in Loop: Header=BB1_6 Depth=2
	s_and_not1_b32 vcc_lo, exec_lo, s38
	s_cbranch_vccnz .LBB1_22
; %bb.21:                               ;   in Loop: Header=BB1_6 Depth=2
	global_load_b64 v[0:1], v33, s[10:11]
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s0, v0
	v_readfirstlane_b32 s1, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s1, s1, s0
	s_lshl_b32 s0, s1, 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_i32 s2, s0, 0
.LBB1_22:                               ;   in Loop: Header=BB1_6 Depth=2
	s_add_i32 s36, s36, 1
	s_waitcnt lgkmcnt(0)
	s_waitcnt_vscnt null, 0x0
	s_cmp_lg_u32 s36, s15
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc0 .LBB1_25
; %bb.23:                               ;   in Loop: Header=BB1_6 Depth=2
	s_mov_b32 s39, s2
	s_branch .LBB1_6
.LBB1_24:                               ;   in Loop: Header=BB1_4 Depth=1
	s_mov_b32 s2, s39
.LBB1_25:                               ; %._crit_edge108
                                        ;   in Loop: Header=BB1_4 Depth=1
	s_add_i32 s27, s27, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u32 s27, s14
	s_cbranch_scc0 .LBB1_27
; %bb.26:                               ;   in Loop: Header=BB1_4 Depth=1
	s_mov_b32 s39, s2
	s_branch .LBB1_4
.LBB1_27:                               ; %._crit_edge116.loopexit
	v_div_scale_f32 v0, null, v30, v30, v29
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v1, v0
	s_waitcnt_depctr 0xfff
	v_fma_f32 v2, -v0, v1, 1.0
	v_fmac_f32_e32 v1, v2, v1
	v_div_scale_f32 v2, vcc_lo, v29, v30, v29
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v3, v2, v1
	v_fma_f32 v4, -v0, v3, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v3, v4, v1
	v_fma_f32 v0, -v0, v3, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v0, v0, v1, v3
	v_div_fixup_f32 v0, v0, v30, v29
	s_branch .LBB1_29
.LBB1_28:
	v_mov_b32_e32 v0, 0x7fc00000
.LBB1_29:                               ; %._crit_edge116
	v_mad_u64_u32 v[1:2], null, s12, s24, v[28:29]
	s_mul_i32 s13, s13, s7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v1, v1, s6
	v_add3_u32 v1, s13, v27, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v2, 31, v1
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s18, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s19, v2, vcc_lo
	global_store_b32 v[1:2], v0, off
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z10nlm_kernelPKfPfiifPif
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 304
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 34
		.amdhsa_next_free_sgpr 51
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z10nlm_kernelPKfPfiifPif, .Lfunc_end1-_Z10nlm_kernelPKfPfiifPif
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 2816
; NumSgprs: 53
; NumVgprs: 34
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 6
; VGPRBlocks: 4
; NumSGPRsForWavesPerEU: 53
; NumVGPRsForWavesPerEU: 34
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym gaussian_matrix
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
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        .value_kind:     by_value
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        .value_kind:     by_value
      - .address_space:  global
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        .size:           8
        .value_kind:     global_buffer
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        .size:           4
        .value_kind:     by_value
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        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         52
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_z
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        .size:           2
        .value_kind:     hidden_group_size_x
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        .value_kind:     hidden_group_size_y
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        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         66
        .size:           2
        .value_kind:     hidden_remainder_x
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        .size:           2
        .value_kind:     hidden_remainder_y
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        .size:           2
        .value_kind:     hidden_remainder_z
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        .value_kind:     hidden_global_offset_x
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        .value_kind:     hidden_global_offset_y
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        .value_kind:     hidden_global_offset_z
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        .value_kind:     hidden_grid_dims
      - .offset:         168
        .size:           4
        .value_kind:     hidden_dynamic_lds_size
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 304
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z10nlm_kernelPKfPfiifPif
    .private_segment_fixed_size: 0
    .sgpr_count:     53
    .sgpr_spill_count: 0
    .symbol:         _Z10nlm_kernelPKfPfiifPif.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     34
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
