#include <algorithm>
#include <chrono>
#include <cstddef>
#include <iostream>
#include <cuda_runtime.h>

#define THREADS_PER_DIM 32

namespace
{

__global__ void multiply_dp_gpu_kernel( double * A, double * B, double * C, size_t N )
{
    double dot = 0.0;
    const size_t row = blockIdx.y * blockDim.y + threadIdx.y;
    const size_t col = blockIdx.x * blockDim.x + threadIdx.x;

    if( row < N && col < N )
    {
        for( size_t idx = 0; idx < N; ++idx )
            dot += A[row + idx * N] * B[idx + col * N];

        C[row + col * N] = dot;
    }
}

__global__ void multiply_dp_gpu_shared_kernel( double * A, double * B, double * C, size_t N, size_t dp_length )
{
    const size_t block_row = blockIdx.y;
    const size_t block_col = blockIdx.x;

    const size_t row = blockIdx.y * blockDim.y + threadIdx.y;
    const size_t col = blockIdx.x * blockDim.x + threadIdx.x;

    if( row < N && col < N )
    {
        double dot = 0.0;
        const size_t number_subblocks = ceil( static_cast<double>(N) / static_cast<double>(blockDim.x) );

        __shared__ double Asub[THREADS_PER_DIM * THREADS_PER_DIM];
        __shared__ double Bsub[THREADS_PER_DIM * THREADS_PER_DIM];

        for( size_t subblock = 0; subblock < number_subblocks; ++subblock )
        {
            size_t Arow = block_row * blockDim.y + threadIdx.y;
            size_t Acol = subblock * blockDim.x + threadIdx.x;
            size_t Brow = subblock * blockDim.y + threadIdx.y;
            size_t Bcol = block_col * blockDim.x + threadIdx.x;

            Asub[threadIdx.x * THREADS_PER_DIM + threadIdx.y] = A[Arow + Acol * N];
            Bsub[threadIdx.x * THREADS_PER_DIM + threadIdx.y] = B[Brow + Bcol * N];

            __syncthreads();

            for( size_t idx = 0; idx < dp_length; ++idx )
                dot += Asub[idx * THREADS_PER_DIM + threadIdx.y] * Bsub[threadIdx.x * THREADS_PER_DIM + idx];

            __syncthreads();
        }

        C[row + col * N] = dot;
    }
}

}

void multiply_dp_gpu( double * A, double * B, double * C, size_t N, double & duration )
{
    const size_t threads_per_dim = THREADS_PER_DIM;
    const size_t min_blocks_per_dim = 1;
    const size_t blocks_per_dim = std::max( N / threads_per_dim, min_blocks_per_dim );

    dim3 block_size( threads_per_dim, threads_per_dim );
    dim3 grid_size( blocks_per_dim, blocks_per_dim );

    cudaGetLastError();

    const auto start = std::chrono::steady_clock::now();
    multiply_dp_gpu_kernel<<< grid_size, block_size >>>( A, B, C, N );
    cudaDeviceSynchronize();
    const auto end = std::chrono::steady_clock::now();
    duration = std::chrono::duration<double>( end - start ).count();

    std::cout << "N = " << N << ": Last CUDA error: " << cudaGetLastError() << std::endl;
}

void multiply_dp_gpu_shared( double * A, double * B, double * C, size_t N, double & duration )
{
    const size_t threads_per_dim = THREADS_PER_DIM;
    const size_t min_blocks_per_dim = 1;
    const size_t blocks_per_dim = std::max( N / threads_per_dim, min_blocks_per_dim );
    const size_t dp_length = std::min( N, threads_per_dim );

    dim3 block_size( threads_per_dim, threads_per_dim );
    dim3 grid_size( blocks_per_dim, blocks_per_dim );

    cudaGetLastError();

    const auto start = std::chrono::steady_clock::now();
    multiply_dp_gpu_shared_kernel<<< grid_size, block_size >>>( A, B, C, N, dp_length );
    cudaDeviceSynchronize();
    const auto end = std::chrono::steady_clock::now();
    duration = std::chrono::duration<double>( end - start ).count();

    std::cout << "N = " << N << ": Last CUDA error: " << cudaGetLastError() << std::endl;
}

	.file	"tmpxft_00262189_00000000-6_GpuDotProduct.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3997:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3997:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z102__device_stub__ZN49_GLOBAL__N__1f87c0d4_16_GpuDotProduct_cu_84434b2b22multiply_dp_gpu_kernelEPdS0_S0_mPdS_S_m
	.hidden	_Z102__device_stub__ZN49_GLOBAL__N__1f87c0d4_16_GpuDotProduct_cu_84434b2b22multiply_dp_gpu_kernelEPdS0_S0_mPdS_S_m
	.type	_Z102__device_stub__ZN49_GLOBAL__N__1f87c0d4_16_GpuDotProduct_cu_84434b2b22multiply_dp_gpu_kernelEPdS0_S0_mPdS_S_m, @function
_Z102__device_stub__ZN49_GLOBAL__N__1f87c0d4_16_GpuDotProduct_cu_84434b2b22multiply_dp_gpu_kernelEPdS0_S0_mPdS_S_m:
.LFB4019:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movq	%rcx, (%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_ZN49_GLOBAL__N__1f87c0d4_16_GpuDotProduct_cu_84434b2b22multiply_dp_gpu_kernelEPdS0_S0_m(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L2:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4019:
	.size	_Z102__device_stub__ZN49_GLOBAL__N__1f87c0d4_16_GpuDotProduct_cu_84434b2b22multiply_dp_gpu_kernelEPdS0_S0_mPdS_S_m, .-_Z102__device_stub__ZN49_GLOBAL__N__1f87c0d4_16_GpuDotProduct_cu_84434b2b22multiply_dp_gpu_kernelEPdS0_S0_mPdS_S_m
	.globl	_ZN49_GLOBAL__N__1f87c0d4_16_GpuDotProduct_cu_84434b2b22multiply_dp_gpu_kernelEPdS0_S0_m
	.hidden	_ZN49_GLOBAL__N__1f87c0d4_16_GpuDotProduct_cu_84434b2b22multiply_dp_gpu_kernelEPdS0_S0_m
	.type	_ZN49_GLOBAL__N__1f87c0d4_16_GpuDotProduct_cu_84434b2b22multiply_dp_gpu_kernelEPdS0_S0_m, @function
_ZN49_GLOBAL__N__1f87c0d4_16_GpuDotProduct_cu_84434b2b22multiply_dp_gpu_kernelEPdS0_S0_m:
.LFB4020:
	.cfi_startproc
	endbr64
	jmp	_Z102__device_stub__ZN49_GLOBAL__N__1f87c0d4_16_GpuDotProduct_cu_84434b2b22multiply_dp_gpu_kernelEPdS0_S0_mPdS_S_m
	.cfi_endproc
.LFE4020:
	.size	_ZN49_GLOBAL__N__1f87c0d4_16_GpuDotProduct_cu_84434b2b22multiply_dp_gpu_kernelEPdS0_S0_m, .-_ZN49_GLOBAL__N__1f87c0d4_16_GpuDotProduct_cu_84434b2b22multiply_dp_gpu_kernelEPdS0_S0_m
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC1:
	.string	"N = "
.LC2:
	.string	": Last CUDA error: "
	.text
	.globl	_Z15multiply_dp_gpuPdS_S_mRd
	.type	_Z15multiply_dp_gpuPdS_S_mRd, @function
_Z15multiply_dp_gpuPdS_S_mRd:
.LFB3988:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movl	$1, %eax
	movq	%rdx, %r15
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	movq	%rsi, %r14
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movq	%rdi, %r13
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movq	%r8, %rbp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movq	%rcx, %rbx
	subq	$40, %rsp
	.cfi_def_cfa_offset 96
	cmpq	$31, %rcx
	jbe	.L9
	movq	%rcx, %rax
	shrq	$5, %rax
.L9:
	movabsq	$137438953504, %rdx
	movl	$1, 16(%rsp)
	movq	%rdx, 8(%rsp)
	movl	%eax, 20(%rsp)
	movl	%eax, 24(%rsp)
	movl	$1, 28(%rsp)
	call	cudaGetLastError@PLT
	call	_ZNSt6chrono3_V212steady_clock3nowEv@PLT
	movl	16(%rsp), %ecx
	movl	28(%rsp), %esi
	xorl	%r9d, %r9d
	movq	8(%rsp), %rdx
	movq	20(%rsp), %rdi
	xorl	%r8d, %r8d
	movq	%rax, %r12
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L10
	movq	%rbx, %rcx
	movq	%r15, %rdx
	movq	%r14, %rsi
	movq	%r13, %rdi
	call	_Z102__device_stub__ZN49_GLOBAL__N__1f87c0d4_16_GpuDotProduct_cu_84434b2b22multiply_dp_gpu_kernelEPdS0_S0_mPdS_S_m
.L10:
	call	cudaDeviceSynchronize@PLT
	call	_ZNSt6chrono3_V212steady_clock3nowEv@PLT
	leaq	.LC1(%rip), %rsi
	leaq	_ZSt4cout(%rip), %rdi
	subq	%r12, %rax
	cvtsi2sdq	%rax, %xmm0
	divsd	.LC0(%rip), %xmm0
	movsd	%xmm0, 0(%rbp)
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%rbx, %rsi
	movq	%rax, %rdi
	call	_ZNSo9_M_insertImEERSoT_@PLT
	leaq	.LC2(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%rax, %rbx
	call	cudaGetLastError@PLT
	movq	%rbx, %rdi
	movl	%eax, %esi
	call	_ZNSolsEi@PLT
	addq	$40, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	movq	%rax, %rdi
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
	.cfi_endproc
.LFE3988:
	.size	_Z15multiply_dp_gpuPdS_S_mRd, .-_Z15multiply_dp_gpuPdS_S_mRd
	.globl	_Z110__device_stub__ZN49_GLOBAL__N__1f87c0d4_16_GpuDotProduct_cu_84434b2b29multiply_dp_gpu_shared_kernelEPdS0_S0_mmPdS_S_mm
	.hidden	_Z110__device_stub__ZN49_GLOBAL__N__1f87c0d4_16_GpuDotProduct_cu_84434b2b29multiply_dp_gpu_shared_kernelEPdS0_S0_mmPdS_S_mm
	.type	_Z110__device_stub__ZN49_GLOBAL__N__1f87c0d4_16_GpuDotProduct_cu_84434b2b29multiply_dp_gpu_shared_kernelEPdS0_S0_mmPdS_S_mm, @function
_Z110__device_stub__ZN49_GLOBAL__N__1f87c0d4_16_GpuDotProduct_cu_84434b2b29multiply_dp_gpu_shared_kernelEPdS0_S0_mmPdS_S_mm:
.LFB4021:
	.cfi_startproc
	endbr64
	subq	$168, %rsp
	.cfi_def_cfa_offset 176
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	48(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	56(%rsp), %rcx
	movq	%r8, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 152(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 112(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 144(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L14
	pushq	56(%rsp)
	.cfi_def_cfa_offset 184
	leaq	_ZN49_GLOBAL__N__1f87c0d4_16_GpuDotProduct_cu_84434b2b29multiply_dp_gpu_shared_kernelEPdS0_S0_mm(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 192
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 184
	popq	%rdx
	.cfi_def_cfa_offset 176
.L14:
	movq	152(%rsp), %rax
	subq	%fs:40, %rax
	je	.L16
	call	__stack_chk_fail@PLT
.L16:
	addq	$168, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4021:
	.size	_Z110__device_stub__ZN49_GLOBAL__N__1f87c0d4_16_GpuDotProduct_cu_84434b2b29multiply_dp_gpu_shared_kernelEPdS0_S0_mmPdS_S_mm, .-_Z110__device_stub__ZN49_GLOBAL__N__1f87c0d4_16_GpuDotProduct_cu_84434b2b29multiply_dp_gpu_shared_kernelEPdS0_S0_mmPdS_S_mm
	.globl	_ZN49_GLOBAL__N__1f87c0d4_16_GpuDotProduct_cu_84434b2b29multiply_dp_gpu_shared_kernelEPdS0_S0_mm
	.hidden	_ZN49_GLOBAL__N__1f87c0d4_16_GpuDotProduct_cu_84434b2b29multiply_dp_gpu_shared_kernelEPdS0_S0_mm
	.type	_ZN49_GLOBAL__N__1f87c0d4_16_GpuDotProduct_cu_84434b2b29multiply_dp_gpu_shared_kernelEPdS0_S0_mm, @function
_ZN49_GLOBAL__N__1f87c0d4_16_GpuDotProduct_cu_84434b2b29multiply_dp_gpu_shared_kernelEPdS0_S0_mm:
.LFB4022:
	.cfi_startproc
	endbr64
	jmp	_Z110__device_stub__ZN49_GLOBAL__N__1f87c0d4_16_GpuDotProduct_cu_84434b2b29multiply_dp_gpu_shared_kernelEPdS0_S0_mmPdS_S_mm
	.cfi_endproc
.LFE4022:
	.size	_ZN49_GLOBAL__N__1f87c0d4_16_GpuDotProduct_cu_84434b2b29multiply_dp_gpu_shared_kernelEPdS0_S0_mm, .-_ZN49_GLOBAL__N__1f87c0d4_16_GpuDotProduct_cu_84434b2b29multiply_dp_gpu_shared_kernelEPdS0_S0_mm
	.globl	_Z22multiply_dp_gpu_sharedPdS_S_mRd
	.type	_Z22multiply_dp_gpu_sharedPdS_S_mRd, @function
_Z22multiply_dp_gpu_sharedPdS_S_mRd:
.LFB3993:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movl	$1, %eax
	movq	%rdx, %r15
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	movq	%rsi, %r14
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movq	%rdi, %r13
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movq	%r8, %rbp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movq	%rcx, %rbx
	subq	$40, %rsp
	.cfi_def_cfa_offset 96
	cmpq	$31, %rcx
	jbe	.L20
	movq	%rcx, %rax
	shrq	$5, %rax
.L20:
	movabsq	$137438953504, %rdx
	movl	$1, 16(%rsp)
	movq	%rdx, 8(%rsp)
	movl	%eax, 20(%rsp)
	movl	%eax, 24(%rsp)
	movl	$1, 28(%rsp)
	call	cudaGetLastError@PLT
	call	_ZNSt6chrono3_V212steady_clock3nowEv@PLT
	movl	16(%rsp), %ecx
	movl	28(%rsp), %esi
	xorl	%r9d, %r9d
	movq	8(%rsp), %rdx
	movq	20(%rsp), %rdi
	xorl	%r8d, %r8d
	movq	%rax, %r12
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L21
	movl	$32, %r8d
	movq	%rbx, %rcx
	movq	%r15, %rdx
	movq	%r14, %rsi
	cmpq	%r8, %rbx
	movq	%r13, %rdi
	cmovbe	%rbx, %r8
	call	_Z110__device_stub__ZN49_GLOBAL__N__1f87c0d4_16_GpuDotProduct_cu_84434b2b29multiply_dp_gpu_shared_kernelEPdS0_S0_mmPdS_S_mm
.L21:
	call	cudaDeviceSynchronize@PLT
	call	_ZNSt6chrono3_V212steady_clock3nowEv@PLT
	leaq	.LC1(%rip), %rsi
	leaq	_ZSt4cout(%rip), %rdi
	subq	%r12, %rax
	cvtsi2sdq	%rax, %xmm0
	divsd	.LC0(%rip), %xmm0
	movsd	%xmm0, 0(%rbp)
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%rbx, %rsi
	movq	%rax, %rdi
	call	_ZNSo9_M_insertImEERSoT_@PLT
	leaq	.LC2(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%rax, %rbx
	call	cudaGetLastError@PLT
	movq	%rbx, %rdi
	movl	%eax, %esi
	call	_ZNSolsEi@PLT
	addq	$40, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	movq	%rax, %rdi
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
	.cfi_endproc
.LFE3993:
	.size	_Z22multiply_dp_gpu_sharedPdS_S_mRd, .-_Z22multiply_dp_gpu_sharedPdS_S_mRd
	.section	.rodata.str1.1
.LC3:
	.string	"_ZN49_GLOBAL__N__1f87c0d4_16_GpuDotProduct_cu_84434b2b29multiply_dp_gpu_shared_kernelEPdS0_S0_mm"
.LC4:
	.string	"_ZN49_GLOBAL__N__1f87c0d4_16_GpuDotProduct_cu_84434b2b22multiply_dp_gpu_kernelEPdS0_S0_m"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4024:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC3(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_ZN49_GLOBAL__N__1f87c0d4_16_GpuDotProduct_cu_84434b2b29multiply_dp_gpu_shared_kernelEPdS0_S0_mm(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC4(%rip), %rdx
	orl	$-1, %r8d
	leaq	_ZN49_GLOBAL__N__1f87c0d4_16_GpuDotProduct_cu_84434b2b22multiply_dp_gpu_kernelEPdS0_S0_m(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE4024:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst8,"aM",@progbits,8
	.align 8
.LC0:
	.long	0
	.long	1104006501
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <algorithm>
#include <chrono>
#include <cstddef>
#include <iostream>
#include <hip/hip_runtime.h>

#define THREADS_PER_DIM 32

namespace
{

__global__ void multiply_dp_gpu_kernel( double * A, double * B, double * C, size_t N )
{
    double dot = 0.0;
    const size_t row = blockIdx.y * blockDim.y + threadIdx.y;
    const size_t col = blockIdx.x * blockDim.x + threadIdx.x;

    if( row < N && col < N )
    {
        for( size_t idx = 0; idx < N; ++idx )
            dot += A[row + idx * N] * B[idx + col * N];

        C[row + col * N] = dot;
    }
}

__global__ void multiply_dp_gpu_shared_kernel( double * A, double * B, double * C, size_t N, size_t dp_length )
{
    const size_t block_row = blockIdx.y;
    const size_t block_col = blockIdx.x;

    const size_t row = blockIdx.y * blockDim.y + threadIdx.y;
    const size_t col = blockIdx.x * blockDim.x + threadIdx.x;

    if( row < N && col < N )
    {
        double dot = 0.0;
        const size_t number_subblocks = ceil( static_cast<double>(N) / static_cast<double>(blockDim.x) );

        __shared__ double Asub[THREADS_PER_DIM * THREADS_PER_DIM];
        __shared__ double Bsub[THREADS_PER_DIM * THREADS_PER_DIM];

        for( size_t subblock = 0; subblock < number_subblocks; ++subblock )
        {
            size_t Arow = block_row * blockDim.y + threadIdx.y;
            size_t Acol = subblock * blockDim.x + threadIdx.x;
            size_t Brow = subblock * blockDim.y + threadIdx.y;
            size_t Bcol = block_col * blockDim.x + threadIdx.x;

            Asub[threadIdx.x * THREADS_PER_DIM + threadIdx.y] = A[Arow + Acol * N];
            Bsub[threadIdx.x * THREADS_PER_DIM + threadIdx.y] = B[Brow + Bcol * N];

            __syncthreads();

            for( size_t idx = 0; idx < dp_length; ++idx )
                dot += Asub[idx * THREADS_PER_DIM + threadIdx.y] * Bsub[threadIdx.x * THREADS_PER_DIM + idx];

            __syncthreads();
        }

        C[row + col * N] = dot;
    }
}

}

void multiply_dp_gpu( double * A, double * B, double * C, size_t N, double & duration )
{
    const size_t threads_per_dim = THREADS_PER_DIM;
    const size_t min_blocks_per_dim = 1;
    const size_t blocks_per_dim = std::max( N / threads_per_dim, min_blocks_per_dim );

    dim3 block_size( threads_per_dim, threads_per_dim );
    dim3 grid_size( blocks_per_dim, blocks_per_dim );

    hipGetLastError();

    const auto start = std::chrono::steady_clock::now();
    multiply_dp_gpu_kernel<<< grid_size, block_size >>>( A, B, C, N );
    hipDeviceSynchronize();
    const auto end = std::chrono::steady_clock::now();
    duration = std::chrono::duration<double>( end - start ).count();

    std::cout << "N = " << N << ": Last CUDA error: " << hipGetLastError() << std::endl;
}

void multiply_dp_gpu_shared( double * A, double * B, double * C, size_t N, double & duration )
{
    const size_t threads_per_dim = THREADS_PER_DIM;
    const size_t min_blocks_per_dim = 1;
    const size_t blocks_per_dim = std::max( N / threads_per_dim, min_blocks_per_dim );
    const size_t dp_length = std::min( N, threads_per_dim );

    dim3 block_size( threads_per_dim, threads_per_dim );
    dim3 grid_size( blocks_per_dim, blocks_per_dim );

    hipGetLastError();

    const auto start = std::chrono::steady_clock::now();
    multiply_dp_gpu_shared_kernel<<< grid_size, block_size >>>( A, B, C, N, dp_length );
    hipDeviceSynchronize();
    const auto end = std::chrono::steady_clock::now();
    duration = std::chrono::duration<double>( end - start ).count();

    std::cout << "N = " << N << ": Last CUDA error: " << hipGetLastError() << std::endl;
}

	.text
	.file	"GpuDotProduct.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0                          # -- Begin function _Z15multiply_dp_gpuPdS_S_mRd
.LCPI0_0:
	.quad	0x41cdcd6500000000              # double 1.0E+9
	.text
	.globl	_Z15multiply_dp_gpuPdS_S_mRd
	.type	_Z15multiply_dp_gpuPdS_S_mRd,@function
_Z15multiply_dp_gpuPdS_S_mRd:           # @_Z15multiply_dp_gpuPdS_S_mRd
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	pushq	%rax
	.cfi_def_cfa_offset 64
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%r8, %r14
	movq	%rcx, %rbx
	movq	%rdx, (%rsp)                    # 8-byte Spill
	movq	%rsi, %r12
	movq	%rdi, %r13
	movq	%rcx, %rax
	shrq	$5, %rax
	movl	%eax, %ecx
	shlq	$32, %rax
	orq	%rcx, %rax
	cmpq	$32, %rbx
	movabsq	$4294967297, %r15               # imm = 0x100000001
	cmovaeq	%rax, %r15
	callq	hipGetLastError
	callq	_ZNSt6chrono3_V212steady_clock3nowEv
	movq	%rax, %rbp
	movabsq	$137438953504, %rdx             # imm = 0x2000000020
	movq	%r15, %rdi
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB0_2
# %bb.1:
	movq	%r13, %rdi
	movq	%r12, %rsi
	movq	(%rsp), %rdx                    # 8-byte Reload
	movq	%rbx, %rcx
	callq	_ZN12_GLOBAL__N_137__device_stub__multiply_dp_gpu_kernelEPdS0_S0_m
.LBB0_2:
	callq	hipDeviceSynchronize
	callq	_ZNSt6chrono3_V212steady_clock3nowEv
	subq	%rbp, %rax
	cvtsi2sd	%rax, %xmm0
	divsd	.LCPI0_0(%rip), %xmm0
	movsd	%xmm0, (%r14)
	movl	$_ZSt4cout, %edi
	movl	$.L.str, %esi
	movl	$4, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	$_ZSt4cout, %edi
	movq	%rbx, %rsi
	callq	_ZNSo9_M_insertImEERSoT_
	movq	%rax, %rbx
	movl	$.L.str.1, %esi
	movl	$19, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	callq	hipGetLastError
	movq	%rbx, %rdi
	movl	%eax, %esi
	callq	_ZNSolsEi
	movq	%rax, %rbx
	movq	(%rax), %rax
	movq	-24(%rax), %rdi
	addq	%rbx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%rbx, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_ZNSo5flushEv                   # TAILCALL
.Lfunc_end0:
	.size	_Z15multiply_dp_gpuPdS_S_mRd, .Lfunc_end0-_Z15multiply_dp_gpuPdS_S_mRd
	.cfi_endproc
                                        # -- End function
	.type	_ZN12_GLOBAL__N_137__device_stub__multiply_dp_gpu_kernelEPdS0_S0_m,@function # -- Begin function _ZN12_GLOBAL__N_137__device_stub__multiply_dp_gpu_kernelEPdS0_S0_m
_ZN12_GLOBAL__N_137__device_stub__multiply_dp_gpu_kernelEPdS0_S0_m: # @_ZN12_GLOBAL__N_137__device_stub__multiply_dp_gpu_kernelEPdS0_S0_m
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	16(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_ZN12_GLOBAL__N_122multiply_dp_gpu_kernelEPdS0_S0_m, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_ZN12_GLOBAL__N_137__device_stub__multiply_dp_gpu_kernelEPdS0_S0_m, .Lfunc_end1-_ZN12_GLOBAL__N_137__device_stub__multiply_dp_gpu_kernelEPdS0_S0_m
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0                          # -- Begin function _Z22multiply_dp_gpu_sharedPdS_S_mRd
.LCPI2_0:
	.quad	0x41cdcd6500000000              # double 1.0E+9
	.text
	.globl	_Z22multiply_dp_gpu_sharedPdS_S_mRd
	.type	_Z22multiply_dp_gpu_sharedPdS_S_mRd,@function
_Z22multiply_dp_gpu_sharedPdS_S_mRd:    # @_Z22multiply_dp_gpu_sharedPdS_S_mRd
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	pushq	%rax
	.cfi_def_cfa_offset 64
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%r8, %r14
	movq	%rcx, %rbx
	movq	%rdx, (%rsp)                    # 8-byte Spill
	movq	%rsi, %r12
	movq	%rdi, %r13
	movq	%rcx, %rax
	shrq	$5, %rax
	movl	%eax, %ecx
	shlq	$32, %rax
	orq	%rcx, %rax
	cmpq	$32, %rbx
	movabsq	$4294967297, %r15               # imm = 0x100000001
	cmovaeq	%rax, %r15
	callq	hipGetLastError
	callq	_ZNSt6chrono3_V212steady_clock3nowEv
	movq	%rax, %rbp
	movabsq	$137438953504, %rdx             # imm = 0x2000000020
	movq	%r15, %rdi
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_2
# %bb.1:
	cmpq	$32, %rbx
	movl	$32, %r8d
	cmovbq	%rbx, %r8
	movq	%r13, %rdi
	movq	%r12, %rsi
	movq	(%rsp), %rdx                    # 8-byte Reload
	movq	%rbx, %rcx
	callq	_ZN12_GLOBAL__N_144__device_stub__multiply_dp_gpu_shared_kernelEPdS0_S0_mm
.LBB2_2:
	callq	hipDeviceSynchronize
	callq	_ZNSt6chrono3_V212steady_clock3nowEv
	subq	%rbp, %rax
	cvtsi2sd	%rax, %xmm0
	divsd	.LCPI2_0(%rip), %xmm0
	movsd	%xmm0, (%r14)
	movl	$_ZSt4cout, %edi
	movl	$.L.str, %esi
	movl	$4, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	$_ZSt4cout, %edi
	movq	%rbx, %rsi
	callq	_ZNSo9_M_insertImEERSoT_
	movq	%rax, %rbx
	movl	$.L.str.1, %esi
	movl	$19, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	callq	hipGetLastError
	movq	%rbx, %rdi
	movl	%eax, %esi
	callq	_ZNSolsEi
	movq	%rax, %rbx
	movq	(%rax), %rax
	movq	-24(%rax), %rdi
	addq	%rbx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%rbx, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_ZNSo5flushEv                   # TAILCALL
.Lfunc_end2:
	.size	_Z22multiply_dp_gpu_sharedPdS_S_mRd, .Lfunc_end2-_Z22multiply_dp_gpu_sharedPdS_S_mRd
	.cfi_endproc
                                        # -- End function
	.type	_ZN12_GLOBAL__N_144__device_stub__multiply_dp_gpu_shared_kernelEPdS0_S0_mm,@function # -- Begin function _ZN12_GLOBAL__N_144__device_stub__multiply_dp_gpu_shared_kernelEPdS0_S0_mm
_ZN12_GLOBAL__N_144__device_stub__multiply_dp_gpu_shared_kernelEPdS0_S0_mm: # @_ZN12_GLOBAL__N_144__device_stub__multiply_dp_gpu_shared_kernelEPdS0_S0_mm
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_ZN12_GLOBAL__N_129multiply_dp_gpu_shared_kernelEPdS0_S0_mm, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	_ZN12_GLOBAL__N_144__device_stub__multiply_dp_gpu_shared_kernelEPdS0_S0_mm, .Lfunc_end3-_ZN12_GLOBAL__N_144__device_stub__multiply_dp_gpu_shared_kernelEPdS0_S0_mm
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB4_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB4_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_ZN12_GLOBAL__N_122multiply_dp_gpu_kernelEPdS0_S0_m, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_ZN12_GLOBAL__N_129multiply_dp_gpu_shared_kernelEPdS0_S0_mm, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end4:
	.size	__hip_module_ctor, .Lfunc_end4-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB5_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB5_2:
	retq
.Lfunc_end5:
	.size	__hip_module_dtor, .Lfunc_end5-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_ZN12_GLOBAL__N_122multiply_dp_gpu_kernelEPdS0_S0_m,@object # @_ZN12_GLOBAL__N_122multiply_dp_gpu_kernelEPdS0_S0_m
	.section	.rodata,"a",@progbits
	.p2align	3, 0x0
_ZN12_GLOBAL__N_122multiply_dp_gpu_kernelEPdS0_S0_m:
	.quad	_ZN12_GLOBAL__N_137__device_stub__multiply_dp_gpu_kernelEPdS0_S0_m
	.size	_ZN12_GLOBAL__N_122multiply_dp_gpu_kernelEPdS0_S0_m, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"N = "
	.size	.L.str, 5

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	": Last CUDA error: "
	.size	.L.str.1, 20

	.type	_ZN12_GLOBAL__N_129multiply_dp_gpu_shared_kernelEPdS0_S0_mm,@object # @_ZN12_GLOBAL__N_129multiply_dp_gpu_shared_kernelEPdS0_S0_mm
	.section	.rodata,"a",@progbits
	.p2align	3, 0x0
_ZN12_GLOBAL__N_129multiply_dp_gpu_shared_kernelEPdS0_S0_mm:
	.quad	_ZN12_GLOBAL__N_144__device_stub__multiply_dp_gpu_shared_kernelEPdS0_S0_mm
	.size	_ZN12_GLOBAL__N_129multiply_dp_gpu_shared_kernelEPdS0_S0_mm, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_ZN12_GLOBAL__N_122multiply_dp_gpu_kernelEPdS0_S0_m"
	.size	.L__unnamed_1, 52

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_ZN12_GLOBAL__N_129multiply_dp_gpu_shared_kernelEPdS0_S0_mm"
	.size	.L__unnamed_2, 60

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _ZN12_GLOBAL__N_137__device_stub__multiply_dp_gpu_kernelEPdS0_S0_m
	.addrsig_sym _ZN12_GLOBAL__N_144__device_stub__multiply_dp_gpu_shared_kernelEPdS0_S0_mm
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _ZN12_GLOBAL__N_122multiply_dp_gpu_kernelEPdS0_S0_m
	.addrsig_sym _ZSt4cout
	.addrsig_sym _ZN12_GLOBAL__N_129multiply_dp_gpu_shared_kernelEPdS0_S0_mm
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.section	.text._ZN12_GLOBAL__N_122multiply_dp_gpu_kernelEPdS0_S0_m,"axG",@progbits,_ZN12_GLOBAL__N_122multiply_dp_gpu_kernelEPdS0_S0_m,comdat
	.globl	_ZN12_GLOBAL__N_122multiply_dp_gpu_kernelEPdS0_S0_m ; -- Begin function _ZN12_GLOBAL__N_122multiply_dp_gpu_kernelEPdS0_S0_m
	.p2align	8
	.type	_ZN12_GLOBAL__N_122multiply_dp_gpu_kernelEPdS0_S0_m,@function
_ZN12_GLOBAL__N_122multiply_dp_gpu_kernelEPdS0_S0_m: ; @_ZN12_GLOBAL__N_122multiply_dp_gpu_kernelEPdS0_S0_m
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x2c
	s_load_b256 s[4:11], s[0:1], 0x0
	v_bfe_u32 v2, v0, 10, 10
	v_and_b32_e32 v4, 0x3ff, v0
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s0, s2, 16
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[0:1], null, s15, s0, v[2:3]
	v_mov_b32_e32 v1, 0
	s_and_b32 s0, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[2:3], null, s14, s0, v[4:5]
	v_mov_b32_e32 v3, v1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_u64_e32 vcc_lo, s[10:11], v[0:1]
	v_cmp_gt_u64_e64 s0, s[10:11], v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, vcc_lo, s0
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_4
; %bb.1:                                ; %.preheader
	v_mad_u64_u32 v[4:5], null, v2, s10, 0
	v_lshlrev_b64 v[0:1], 3, v[0:1]
	s_lshl_b64 s[0:1], s[10:11], 3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v3, v5
	v_mad_u64_u32 v[5:6], null, v2, s11, v[3:4]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v6, vcc_lo, s4, v0
	v_add_co_ci_u32_e32 v7, vcc_lo, s5, v1, vcc_lo
	v_mov_b32_e32 v2, 0
	v_mov_b32_e32 v3, 0
	v_lshlrev_b64 v[4:5], 3, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v8, vcc_lo, s6, v4
	v_add_co_ci_u32_e32 v9, vcc_lo, s7, v5, vcc_lo
.LBB0_2:                                ; =>This Inner Loop Header: Depth=1
	global_load_b64 v[10:11], v[6:7], off
	global_load_b64 v[12:13], v[8:9], off
	v_add_co_u32 v6, vcc_lo, v6, s0
	v_add_co_ci_u32_e32 v7, vcc_lo, s1, v7, vcc_lo
	v_add_co_u32 v8, vcc_lo, v8, 8
	s_add_u32 s10, s10, -1
	v_add_co_ci_u32_e32 v9, vcc_lo, 0, v9, vcc_lo
	s_addc_u32 s11, s11, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u64 s[10:11], 0
	s_waitcnt vmcnt(0)
	v_fma_f64 v[2:3], v[10:11], v[12:13], v[2:3]
	s_cbranch_scc0 .LBB0_2
; %bb.3:
	v_add_co_u32 v4, vcc_lo, s8, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s9, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v4, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, v5, v1, vcc_lo
	global_store_b64 v[0:1], v[2:3], off
.LBB0_4:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _ZN12_GLOBAL__N_122multiply_dp_gpu_kernelEPdS0_S0_m
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 14
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._ZN12_GLOBAL__N_122multiply_dp_gpu_kernelEPdS0_S0_m,"axG",@progbits,_ZN12_GLOBAL__N_122multiply_dp_gpu_kernelEPdS0_S0_m,comdat
.Lfunc_end0:
	.size	_ZN12_GLOBAL__N_122multiply_dp_gpu_kernelEPdS0_S0_m, .Lfunc_end0-_ZN12_GLOBAL__N_122multiply_dp_gpu_kernelEPdS0_S0_m
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 320
; NumSgprs: 18
; NumVgprs: 14
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 14
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.section	.text._ZN12_GLOBAL__N_129multiply_dp_gpu_shared_kernelEPdS0_S0_mm,"axG",@progbits,_ZN12_GLOBAL__N_129multiply_dp_gpu_shared_kernelEPdS0_S0_mm,comdat
	.globl	_ZN12_GLOBAL__N_129multiply_dp_gpu_shared_kernelEPdS0_S0_mm ; -- Begin function _ZN12_GLOBAL__N_129multiply_dp_gpu_shared_kernelEPdS0_S0_mm
	.p2align	8
	.type	_ZN12_GLOBAL__N_129multiply_dp_gpu_shared_kernelEPdS0_S0_mm,@function
_ZN12_GLOBAL__N_129multiply_dp_gpu_shared_kernelEPdS0_S0_mm: ; @_ZN12_GLOBAL__N_129multiply_dp_gpu_shared_kernelEPdS0_S0_mm
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x34
	s_load_b256 s[4:11], s[0:1], 0x0
	v_bfe_u32 v8, v0, 10, 10
	v_and_b32_e32 v4, 0x3ff, v0
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s13, s2, 16
	s_and_b32 s12, s2, 0xffff
	v_mad_u64_u32 v[0:1], null, s15, s13, v[8:9]
	v_mov_b32_e32 v1, 0
	v_mad_u64_u32 v[2:3], null, s14, s12, v[4:5]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mov_b32_e32 v3, v1
	v_cmp_gt_u64_e32 vcc_lo, s[10:11], v[0:1]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_gt_u64_e64 s2, s[10:11], v[2:3]
	s_and_b32 s2, vcc_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB1_8
; %bb.1:
	v_cvt_f64_u32_e32 v[5:6], s11
	v_cvt_f64_u32_e32 v[9:10], s10
	v_cvt_f64_u32_e32 v[11:12], s12
	s_load_b64 s[0:1], s[0:1], 0x20
	s_mov_b64 s[2:3], 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ldexp_f64 v[5:6], v[5:6], 32
	v_add_f64 v[5:6], v[5:6], v[9:10]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f64 v[9:10], null, v[11:12], v[11:12], v[5:6]
	v_div_scale_f64 v[17:18], vcc_lo, v[5:6], v[11:12], v[5:6]
	v_rcp_f64_e32 v[13:14], v[9:10]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[15:16], -v[9:10], v[13:14], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[13:14], v[13:14], v[15:16], v[13:14]
	v_fma_f64 v[15:16], -v[9:10], v[13:14], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[13:14], v[13:14], v[15:16], v[13:14]
	v_mul_f64 v[15:16], v[17:18], v[13:14]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[9:10], -v[9:10], v[15:16], v[17:18]
	v_div_fmas_f64 v[9:10], v[9:10], v[13:14], v[15:16]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f64 v[5:6], v[9:10], v[11:12], v[5:6]
	v_ceil_f64_e32 v[5:6], v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ldexp_f64 v[9:10], v[5:6], 0xffffffe0
	v_floor_f64_e32 v[9:10], v[9:10]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f64 v[5:6], 0xc1f00000, v[9:10], v[5:6]
	v_cvt_u32_f64_e32 v7, v[9:10]
	v_cvt_u32_f64_e32 v6, v[5:6]
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[6:7]
	s_cbranch_vccnz .LBB1_6
; %bb.2:                                ; %.lr.ph49
	v_mov_b32_e32 v5, 0
	v_lshlrev_b32_e32 v3, 3, v8
	s_and_b32 s13, s13, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	s_mul_hi_u32 s17, s13, s15
	v_mad_u64_u32 v[9:10], null, s12, s14, v[4:5]
	s_mul_i32 s16, s13, s15
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[14:15], s[16:17], 3
	s_add_u32 s4, s4, s14
	s_addc_u32 s5, s5, s15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v14, v10, s10
	v_mul_lo_u32 v15, v9, s11
	v_mad_u64_u32 v[12:13], null, v9, s10, 0
	v_lshlrev_b32_e32 v9, 5, v4
	v_lshl_add_u32 v10, v4, 8, 0x2000
	s_waitcnt lgkmcnt(0)
	s_cmp_lg_u64 s[0:1], 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_lshl_u32 v11, v9, v8, 3
	v_add3_u32 v13, v13, v15, v14
	v_add_co_u32 v15, s6, s6, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v16, null, s7, 0, s6
	v_lshlrev_b64 v[8:9], 3, v[12:13]
	v_add_nc_u32_e32 v14, 0x2000, v11
	s_cselect_b32 s6, -1, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v15, vcc_lo, v15, v8
	v_add_co_ci_u32_e32 v16, vcc_lo, v16, v9, vcc_lo
	v_mov_b32_e32 v8, 0
	v_add_co_u32 v12, s4, s4, v3
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v13, null, s5, 0, s4
	v_mov_b32_e32 v9, 0
.LBB1_3:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB1_4 Depth 2
	v_mad_u64_u32 v[17:18], null, s2, s12, v[4:5]
	s_mul_i32 s5, s3, s13
	s_mul_hi_u32 s7, s2, s13
	s_mul_i32 s4, s2, s13
	s_add_i32 s5, s7, s5
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_lshl_b64 s[4:5], s[4:5], 3
	v_mad_u64_u32 v[19:20], null, s3, s12, v[18:19]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_lo_u32 v18, v17, s11
	v_mad_u64_u32 v[20:21], null, v17, s10, 0
	v_mul_lo_u32 v17, v19, s10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v21, v21, v18, v17
	v_lshlrev_b64 v[17:18], 3, v[20:21]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v17, vcc_lo, v12, v17
	v_add_co_ci_u32_e32 v18, vcc_lo, v13, v18, vcc_lo
	v_add_co_u32 v19, vcc_lo, v15, s4
	v_add_co_ci_u32_e32 v20, vcc_lo, s5, v16, vcc_lo
	s_mov_b64 s[4:5], s[0:1]
	global_load_b64 v[21:22], v[17:18], off
	global_load_b64 v[19:20], v[19:20], off
	v_dual_mov_b32 v17, v3 :: v_dual_mov_b32 v18, v10
	s_and_not1_b32 vcc_lo, exec_lo, s6
	s_waitcnt vmcnt(1)
	ds_store_b64 v11, v[21:22]
	s_waitcnt vmcnt(0)
	ds_store_b64 v14, v[19:20]
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_vccnz .LBB1_5
.LBB1_4:                                ; %.lr.ph
                                        ;   Parent Loop BB1_3 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	ds_load_b64 v[19:20], v17
	ds_load_b64 v[21:22], v18
	s_add_u32 s4, s4, -1
	v_add_nc_u32_e32 v18, 8, v18
	v_add_nc_u32_e32 v17, 0x100, v17
	s_addc_u32 s5, s5, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u64 s[4:5], 0
	s_waitcnt lgkmcnt(0)
	v_fma_f64 v[8:9], v[19:20], v[21:22], v[8:9]
	s_cbranch_scc0 .LBB1_4
.LBB1_5:                                ; %._crit_edge
                                        ;   in Loop: Header=BB1_3 Depth=1
	s_add_u32 s2, s2, 1
	s_addc_u32 s3, s3, 0
	s_delay_alu instid0(SALU_CYCLE_1)
	v_cmp_eq_u64_e32 vcc_lo, s[2:3], v[6:7]
	s_barrier
	buffer_gl0_inv
	s_cbranch_vccz .LBB1_3
	s_branch .LBB1_7
.LBB1_6:
	v_mov_b32_e32 v8, 0
	v_mov_b32_e32 v9, 0
.LBB1_7:                                ; %Flow79
	v_mad_u64_u32 v[3:4], null, v2, s10, 0
	v_lshlrev_b64 v[0:1], 3, v[0:1]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[5:6], null, v2, s11, v[4:5]
	v_mov_b32_e32 v4, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 3, v[3:4]
	v_add_co_u32 v2, vcc_lo, s8, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
	v_add_co_u32 v0, vcc_lo, v2, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, v3, v1, vcc_lo
	global_store_b64 v[0:1], v[8:9], off
.LBB1_8:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _ZN12_GLOBAL__N_129multiply_dp_gpu_shared_kernelEPdS0_S0_mm
		.amdhsa_group_segment_fixed_size 16384
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 23
		.amdhsa_next_free_sgpr 18
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._ZN12_GLOBAL__N_129multiply_dp_gpu_shared_kernelEPdS0_S0_mm,"axG",@progbits,_ZN12_GLOBAL__N_129multiply_dp_gpu_shared_kernelEPdS0_S0_mm,comdat
.Lfunc_end1:
	.size	_ZN12_GLOBAL__N_129multiply_dp_gpu_shared_kernelEPdS0_S0_mm, .Lfunc_end1-_ZN12_GLOBAL__N_129multiply_dp_gpu_shared_kernelEPdS0_S0_mm
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 924
; NumSgprs: 20
; NumVgprs: 23
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 16384 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 20
; NumVGPRsForWavesPerEU: 23
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           8
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _ZN12_GLOBAL__N_122multiply_dp_gpu_kernelEPdS0_S0_m
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _ZN12_GLOBAL__N_122multiply_dp_gpu_kernelEPdS0_S0_m.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     14
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           8
        .value_kind:     by_value
      - .offset:         32
        .size:           8
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         44
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         52
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         54
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         56
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         58
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         60
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         62
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         104
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 16384
    .kernarg_segment_align: 8
    .kernarg_segment_size: 296
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _ZN12_GLOBAL__N_129multiply_dp_gpu_shared_kernelEPdS0_S0_mm
    .private_segment_fixed_size: 0
    .sgpr_count:     20
    .sgpr_spill_count: 0
    .symbol:         _ZN12_GLOBAL__N_129multiply_dp_gpu_shared_kernelEPdS0_S0_mm.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     23
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
