       #include <stdio.h>
    #include <cuda.h>
    #include <time.h>
    #include <math.h>
    //#include <unistd.h>
    #define EXPO 5 //so [0,1] will be break into 2^6 intervals 64*64
    #define PI 3.14159265

    __global__ void CalculateTheD(int step,float* deviceB, float* deviceC, float* deviceD, float* deviceX, float* devicenewB, float* devicenewC)
    {
       int blocksize=16;
       int gridsize=gridDim.x; //this will always be 1
       // int gridsize2=gridDim.x;
       // printf("gridsize: %d %d\n", gridsize,gridsize2);
       // __device__ bool myGlobalFlag=true;
       
        int bx=blockIdx.x;
        int by=blockIdx.y;
        int tx=threadIdx.x;
        int ty=threadIdx.y;
        
        int blocktotal=blocksize*blocksize;
        int temp1=by*gridsize+bx;
        if(tx==1&&ty==1)
        {
        	printf("temp1: %d \n",temp1);
        }
        int temp2=ty*blocksize+tx;

       int ind=temp1*blocktotal+temp2;

      int m=(int)pow(2.0,EXPO*1.0)-1;
      /*int column=threadIdx.x;
      int row=threadIdx.y;*/
      int row=ind/m;
      int column=ind%m;

      int iloopstep=(int)pow(2.0,(EXPO-step)*1.0)-1;
      int h=(int)pow(2.0,(step-1)*1.0);
      int multiplier=(int)pow(2.0,step*1.0);
      int countHelper1=(int)pow(2.0,EXPO+1.0); 
      int countHelper2=(int)pow(2.0,EXPO-step+2);

      float* oldB;
      float* oldC;
 

      float* newB;
      float* newC;
      //float* newD;
    
      

     //this is to exchange which hold the previous value which hold the current value
      if(step%2==0)
      {
      	oldB=devicenewB;
      	oldC=devicenewC;
      	/*oldD=devicenewD;*/

      	newB=deviceB;
      	newC=deviceC;
     /* 	newD=deviceD;*/
      }
      else
      {
      	oldB=deviceB;
      	oldC=deviceC;
      /*	oldD=deviceD;*/
        
        newB=devicenewB;
        newC=devicenewC;
  /*      newD=devicenewD;*/
      }

/*    
     if(row==0&&column==0)
      {
           if(step==1)
      {
        printf("bb-0 \n");
        for(int i=0;i<m;i++)
        {
          for(int j=0;j<m;j++)
          {
            printf("%lf ",oldB[i*m+j]);
          }
          printf("\n");
        }
      }

       if(step==2)
      {
         printf("bb-1 \n");
        for(int i=0;i<m;i++)
        {
          for(int j=0;j<m;j++)
          {
            printf("%lf ",oldB[i*m+j]);
          }
          printf("\n");
        }
      }
      }*/
    

      //use the device value as old value and store the updated one in to the new value
      if(row<m && column<m) //so only the first 63 threads do work and the other one is hanging there
      {
		    float sumBB=0.0;
		    for(int k=0;k<m;k++)
		    {
		      sumBB=sumBB+oldB[row*m+k]*oldB[k*m+column];
		    }
		    float sumCC=0.0;
		    for(int k=0;k<m;k++)
		    {
		      sumCC=sumCC+oldC[row*m+k]*oldC[k*m+column];
		    }

		    //based on formula (5.4.2.15) on book
		    newB[row*m+column]=2*sumCC-sumBB;
		    newC[row*m+column]=sumCC;

		    //now calculate the new d and it needs to loop through i in each block
		    //look at the third formula on 5.4.2.15 on book
		    ///D[ith BLOCK][j thSTep ]=D[(2^(k+1)-2^(k-j+1)+i-j-1)*m+...]
		    if(column==0)
		    {
		    	//for calculate d we just need 63 tthreads but B and C we need 63*63 threads
		    	//so in step :step, each thread will work on the row th value in each block in that step,sicne there are 63 threads.
		    	for(int i=1;i<=iloopstep;i++)
		    {

		    	float sumCD1=0.0;
		    	for(int k=0;k<m;k++)
		    	{

		    		sumCD1=sumCD1+oldC[row*m+k]*deviceD[(countHelper1-countHelper2+i*2-1-step)*m+k];
		    	}

		    	float sumCD2=0.0;
		    	for(int k=0;k<m;k++)
		    	{
		    		sumCD2=sumCD2+oldC[row*m+k]*deviceD[(countHelper1-countHelper2+i*2+1-step)*m+k];
		    	}

		    	float sumBD=0.0;
		    	for(int k=0;k<m;k++)
		    	{
		           sumBD=sumBD+oldB[row*m+k]*deviceD[(countHelper1-countHelper2+i*2-step)*m+k];
		    	}

		    	deviceD[(int)((countHelper1-countHelper2/2+i-step-1)*m)+row]=sumCD1+sumCD2-sumBD;

           if(i==2&&step==1)
           {
            printf("row %d, index %d, %lf",row,(int)((countHelper1-countHelper2/2+i-step-1)*m)+row,deviceD[(int)((countHelper1-countHelper2/2+i-step-1)*m)+row]);

           }
          //printf("step %d,row: %d, index:%d dd1: %lf \n",step,row,(int)(countHelper1-countHelper2/2+i-step-1)*m+row,deviceD[(countHelper1-countHelper2/2+i-step-1)*m+row]);
		    	//printf("in cuda index %d value %lf: \n",(countHelper1-countHelper2/2+i-step-1)*m+row,deviceD[(countHelper1-countHelper2/2+i-step-1)*m+row]);
		    	//printf("gpu:%lf:",newD[(i*multiplier-1)*m+row]);
		    }

		    }
		    
        }
       //sync the thread before go to the next step.
        __syncthreads();

   /*     if(row==0&&column==0)s
        {
            for(int i=0;i<9;i++)
            {
              printf("%lf ",oldD[i]);	
            }
          printf("\n");	
        }*/

    }
//***************************begin of unblock version of cyclic reduction*********************************************************************************//
     __global__ void CalculatePArrayKernel(int step,int blockRow, int blockColumn,float* deviceA, float* deviceB, float* deviceC, float* deviceD)
    {
      int bx=blockIdx.x;
      int by=blockIdx.y;
      int tx=threadIdx.x;
      int ty=threadIdx.y;

      int helper11=pow(2.0,(EXPO+1)*1.0);
      int helper22=pow(2.0,(EXPO-step+1)*1.0);
      int helper44=pow(2.0,(EXPO-step+2)*1.0);
      int helper33=pow(2.0,EXPO*1.0)-1;
        //printf("step is running: %d \n",step);

     // if(helper3<pow(2.0,(EXPO-step)*1.0)-1)
        //--step 1 is special case.
     /*  if((tx!=(blockColumn-1))&&(ty!=(blockRow-1)))-----this is very important branch divergence happen here, need
     //to figure out how exactly cuda works!!
        /*****calcualte A******************/
        int helper1=helper11;
        int helper2=helper22;
        int helper4=helper44;
        int flag=0;//special for step1.
        if(step==1)
        {
            helper1=0;
            helper2=0;
            helper4=0;
            flag=1;
        }

        int helper3=ty*blockColumn+tx+1;
        if(helper3<=(pow(2.0,1.0*(EXPO-step))-1.0))
        {
        float ahelperfora1=deviceA[-step+helper1-helper4+2*(helper3)];
        float ahelperfora2=deviceA[-step+helper1-helper4+2*(helper3)-1];
        float bhelperfora1=deviceB[-step+helper1-helper4+2*(helper3)-1];
        deviceA[-1-step+helper1-helper2+helper3+flag*(1+helper33)]=-1*(ahelperfora1)*ahelperfora2/bhelperfora1;

        //*****calculate C******************/
        float chelperforc1=deviceC[-step+helper1-helper4+2*(helper3)];
        float chelperforc2=deviceC[-step+helper1-helper4+2*(helper3)+1];
        float bhelperforc1=deviceB[-step+helper1-helper4+2*(helper3)+1];
        deviceC[-1-step+helper1-helper2+helper3+flag*(1+helper33)]=-1*chelperforc1*chelperforc2/bhelperforc1;

        //calculate B***********************************************//
        float bhelperforb1=deviceB[-step+helper1-helper4+2*(helper3)];
        float bhelperforb2=deviceB[-step+helper1-helper4+2*(helper3)-1];
        float bhelperforb3=deviceB[-step+helper1-helper4+2*(helper3)+1];
        float ahelperforb1=deviceA[-step+helper1-helper4+2*(helper3)];
        float ahelperforb2=deviceA[-step+helper1-helper4+2*(helper3)+1];
        float chelperforb1=deviceC[-step+helper1-helper4+2*(helper3)-1];
        float chelperforb2=deviceC[-step+helper1-helper4+2*(helper3)];
        deviceB[-1-step+helper1-helper2+helper3+flag*(1+helper33)]=bhelperforb1-ahelperforb1/bhelperforb2*chelperforb1-chelperforb2/bhelperforb3*ahelperforb2;

        //calculate D***************************************************//
        float dhelperford1=deviceD[-step+helper1-helper4+2*(helper3)];
        float dhelperford2=deviceD[-step+helper1-helper4+2*(helper3)-1];
        float dhelperford3=deviceD[-step+helper1-helper4+2*(helper3)+1];
        float ahelperford1=deviceA[-step+helper1-helper4+2*(helper3)];
        float bhelperford1=deviceB[-step+helper1-helper4+2*(helper3)-1];
        float bhelperford2=deviceB[-step+helper1-helper4+2*(helper3)+1];
        float chelperford1=deviceC[-step+helper1-helper4+2*(helper3)];
        deviceD[-1-step+helper1-helper2+helper3+flag*(1+helper33)]=dhelperford1-ahelperford1/bhelperford1*dhelperford2-chelperford1/bhelperford2*dhelperford3;
    /*    for(int i=0;i<6;i++)
        {
        	//printf("cudab %lf \n",deviceB[i]);
        	printf("cudab %lf \n",deviceB[i]);
        }

        for(int i=0;i<6;i++)
        {
        	//printf("cudab %lf \n",deviceB[i]);
        	printf("cudad %lf \n",deviceD[i]);
        }*/
    }

        __syncthreads();
    }
    

        __global__ void BackwardKernel(int k,int blockRow, int blockColumn,float* deviceA, float* deviceB, float* deviceC, float* deviceD,float* deviceFinalX,float initialValue)
     {
      int bx1=blockIdx.x;
      int by1=blockIdx.y;
      int tx1=threadIdx.x;
      int ty1=threadIdx.y;
      //printf("inside of kernle %f \n",deviceFinalX[4]);

      int backhelper1=ty1*blockColumn+tx1+1;
      int backhelper2=2*backhelper1-1;//(int((2*backhelper1-1)*pow(2.0,1.0*(k-1))))/(int)(pow(2.0,(k-1)*1.0));
      int backhelper3=(int)pow(2.0,(EXPO+1)*1.0);
      int backhelper4=(int)pow(2.0,(EXPO-k+2)*1.0);


      int h=(int)(pow(2.0,1.0*(k-1)));

      float backhelperd=deviceD[-k+backhelper3-backhelper4+backhelper2];
      float backhelpera=deviceA[-k+backhelper3-backhelper4+backhelper2];
      float backhelperb=deviceB[-k+backhelper3-backhelper4+backhelper2];
      float backhelperc=deviceC[-k+backhelper3-backhelper4+backhelper2];

      int xindex1=backhelper2*pow(2.0,1.0*(k-1))-h;
      int xindex2=backhelper2*pow(2.0,1.0*(k-1))+h;

      //so thread i will be in charge of (2i-1)*2^(k-1) calculation
      //printf("%d ",int((2*backhelper1-1)*pow(2.0,1.0*(k-1))));
      deviceFinalX[(int)(backhelper2*pow(2.0,1.0*(k-1)))]=(backhelperd-backhelpera*deviceFinalX[xindex1]-backhelperc*deviceFinalX[xindex2])*1.0/backhelperb;

      __syncthreads();
     }
      
//***************************end of not block version of cyclic reduction*********************************************************************************//
    
    int main()
    {


      //matrix size will be 63*63 as our setup
      int m=pow(2,EXPO)-1;
      int loopH=pow(2,EXPO-1);
      int conHelp=4*loopH;
         

      //syntax will follow the  routine in the book
      float *B;
      float *C;
      float *D;
      float *X; //X to store the solution
      float *newB;
      float *newC;
 
      int b=1;
      int a=0;
      int maxBlockSize=16;


      //B and C share the same chuck length 
      int chunkLength=m*m;
      float delta=(b-a)*1.0/(m+1.0);
      float deltaSquare=delta*delta;
      int chunkSize=chunkLength*sizeof(float); 
      //need to store all the version of D, it will be 2^k-k-1 block and each block has m value
      int dLength=(pow(2,EXPO+1)-EXPO-2)*m;
      int dSize=dLength*sizeof(float);
     
     


      B=(float*)malloc(chunkSize);
      C=(float*)malloc(chunkSize);
      D=(float*)malloc(dSize);
      //this is to store the final answer
      X=(float*)malloc(chunkSize);
      newB=(float*)malloc(chunkSize);
      newC=(float*)malloc(chunkSize);
      //newD=(float*)malloc(dSize);

          
      //initilize B

      for(int i=0;i<m;i++)
      {
      	for(int j=0;j<m;j++)
      	{
      		B[i*m+j]=0.0;
      		C[i*m+j]=0.0;
      	}
      }
      

      for(int i=0;i<m;i++)
      {
      	B[i*m+i]=-4.0;
      	if(i!=0)
      	{
         B[i*m+i-1]=1.0;
      	}
      	if(i!=m-1)
      	{
      	 B[i*m+i+1]=1.0;;
      	}
      }
  

      //initilize C
      for(int i=0;i<m;i++)
      {
      	C[i*m+i]=1.0;
      } 
    
    //the first 2^k-1 will be the step 0 initial value
      for(int i=0;i<m;i++)
      {
       for(int j=0;j<m;j++)
       {
       /*	float x=(j+1)*delta;
       	float y=(i+1)*delta;*/
       	D[i*m+j]=deltaSquare;  //f(x,y) will be 1 here.
       	printf("dd block: %d %lf ",i,D[i*m+j]);
       }
        printf("\n");
      }
      //other value initilized to be 0 at the beginnig
      for(int i=m*m;i<dLength;i++)
      {
      	D[i]=0.0;
      }
     /* for(int i=0;i<dLength;i++)
      {
      	printf("dd %lf",D[i]);
      }*/

      //initilize x
      for(int i=0;i<m;i++)
      {
      	for(int j=0;j<m;j++)
      	{
      		X[i*m+j]=0.0; 
      	}
      }
      //printf("let test this2:\n");



     //begin timing here:
        clock_t begin,end;
        begin=clock();
      float *deviceB,*deviceC,*deviceD,*deviceX,*devicenewB,*devicenewC;
      cudaMalloc((void**)&deviceB,chunkSize);
      cudaMalloc((void**)&deviceC,chunkSize);
      cudaMalloc((void**)&deviceD,dSize);
      cudaMalloc((void**)&deviceX,chunkSize);
      cudaMalloc((void**)&devicenewB,chunkSize);
      cudaMalloc((void**)&devicenewC,chunkSize);
      //cudaMalloc((void**)&devicenewD,chunkSize);

      cudaMemcpy(deviceB,B,chunkSize,cudaMemcpyHostToDevice);  //store previous value
      cudaMemcpy(deviceC,C,chunkSize,cudaMemcpyHostToDevice);
      cudaMemcpy(deviceD,D,dSize,cudaMemcpyHostToDevice);
      cudaMemcpy(deviceX,X,chunkSize,cudaMemcpyHostToDevice);
      cudaMemcpy(devicenewB,newB,chunkSize,cudaMemcpyHostToDevice);  //store current stored value
      cudaMemcpy(devicenewC,newC,chunkSize,cudaMemcpyHostToDevice);
     // cudaMemcpy(devicenewD,newD,chunkSize,cudaMemcpyHostToDevice);
        
        //int gridSize=((m+1)/maxBlockSize)*((m+1)/maxBlockSize); //gridSize for this problem will be 16
         	//dim3 dimGrid(1,gridSize)
      	dim3 dimGrid(1,32);  //since the maximum process we are going to use will be 63*63

        int blockRow=maxBlockSize;//pow(2,EXPO/2); //here will be 8 and 8
        int blockColumn=maxBlockSize;//pow(2,EXPO/2); //here will be 8 and 8
        dim3 dimBlock(blockColumn,blockRow);

      for(int step=1;step<EXPO;step++)
      {
      	//so the logic here will be if step is odd, then it use B,C,D as the old value and new value into newB, newC,newD.
      	//if step is even, then use newB,newC,newD as the old value and put the update value into B,C,D.
      
        //here is to calculate the d(2^(k-1))(K-1) in the book
        CalculateTheD<<<dimGrid,dimBlock>>>(step,deviceB,deviceC,deviceD,deviceX,devicenewB,devicenewC);
      }
      cudaDeviceSynchronize();
      //the last step here will be 5 so it will write its new value into newB, newC, newD. 
      cudaMemcpy(D,deviceD,dSize,cudaMemcpyDeviceToHost);
    /*  for (int i=0;i<m;i++)
      {
      	if(i%8==0)
      	{
      		printf("\n");
      	}
      	printf("%lf ",newD[3+i]);
      }*/
      //release some of the memory
      for(int i=0;i<dLength;i++)
      {
        if(i%m==0)
        {
          printf("\n");
        }
        printf("dha:%lf ",D[i]);
      }
      cudaFree(deviceB);
      cudaFree(deviceC);
      //cudaFree(deviceD);
      cudaFree(devicenewB);
      cudaFree(devicenewC);
      //cudaFree(devicenewD);
      
      free(B);
      free(C);
      //free(D);
      free(newB);
      free(newC);
      //free(newD);

      /*cudaMemcpy(deviceB,B,chunkSize,cudaMemcpyHostToDevice);
      cudaMemcpy(deviceC,C,chunkSize,cudaMemcpyHostToDevice);*/

      //z will D in the not block version of cyclic reduction, ZA, ZB, ZC will corresponding to A, B and C
      float *Z,*ZA,*ZB,*ZC,*FinalX;
      int finalLengthX=(int)pow(2,EXPO)+1;
      int chunkLengthZ=(pow(2,EXPO)-1)*2+1;
      int zSize=chunkLengthZ*sizeof(float);
      
      Z=(float*)malloc(zSize);
      ZA=(float*)malloc(zSize);
      ZB=(float*)malloc(zSize);
      ZC=(float*)malloc(zSize);
      FinalX=(float*)malloc(finalLengthX*sizeof(float));  //the first and last one should be know by the boundary condition

      float *deviceZ,*deviceZA,*deviceZB, *deviceZC,*deviceFinalX;
	    cudaMalloc((void**)&deviceZ,zSize);
	    cudaMalloc((void**)&deviceZA,zSize);
	    cudaMalloc((void**)&deviceZB,zSize);
	    cudaMalloc((void**)&deviceZC,zSize);
	    cudaMalloc((void**)&deviceFinalX,finalLengthX*sizeof(float));


      //set up the matrix step 
      for(int j=1;j<=loopH;j++)
      {
      	//for each j, za,zb,zc all going to be different
      	ZA[0]=0;

      	for(int i=1;i<m;i++)
      	{
      		ZA[i]=1.0;
      	}
      	//else will be 0,since it has been seperate to half and half
        for(int i=m;i<chunkLengthZ;i++)
        {
          ZA[i]=0;
        }

        for(int i=0;i<m;i++)
        {
          ZB[i]=-4.0+2*cos((2.0*j-1.0)/(m+1.0)*PI);
          //printf("zb:%f \n",ZB[i]);
        }
        for(int i=m;i<chunkLengthZ;i++)
        {
          ZB[i]=0;
        }

        ZC[m-1]=0;
        for(int i=0;i<m-1;i++)
        {
            ZC[i]=1.0;
        }
        for(int i=m;i<chunkLengthZ;i++)
        {
          ZC[i]=0;
        }

        //if it is the first step z will be from d, otherwise, z will be from the previous solution of x
        if(j==1)
        {
        	for(int i=0;i<m;i++)
        	{
        		/*Z[i]=newD[(loopH-1)*m+i]*(-1.0);
        		printf("this original one being called? %lf \n",Z[i]);*/
        		Z[i]=D[((int)pow(2.0,EXPO+1.0)-3-EXPO)*m+i]*(-1.0);
				//printf("z value: %lf \n",Z[i]);
        	}
        	 for(int i=m;i<chunkLengthZ;i++)
		        {
		          Z[i]=0;
		        }
        }
        else
        {
        	for(int i=0;i<m;i++)
        	{
             //to do this will be x
        		Z[i]=FinalX[i+1];
        		//printf("does this ever called? %lf \n",Z[i]);
        	}
        	 for(int i=m;i<chunkLengthZ;i++)
		        {
		          Z[i]=0;
		        }
        }

        //now need to call the cyclic function to find the solution of x

        cudaMemcpy(deviceZ,Z,zSize,cudaMemcpyHostToDevice);
        cudaMemcpy(deviceZA,ZA,zSize,cudaMemcpyHostToDevice);
        cudaMemcpy(deviceZB,ZB,zSize,cudaMemcpyHostToDevice);
        cudaMemcpy(deviceZC,ZC,zSize,cudaMemcpyHostToDevice);

        for(int j=1;j<EXPO;j++)
        {
        //the lock size should change, the first step it will need 2^(n-j)-1, so first step will be 3 if n=3
        dim3 dimGrid(1,1);
        int blockRow=pow(2,(EXPO-j)/2);
        //printf("blockrow is :%d \n",blockRow);
        int blockColumn=pow(2,EXPO-j-(EXPO-j)/2);
        //printf("blockColumn is :%d \n",blockColumn);
        dim3 dimBlock(blockColumn,blockRow);
          //in each step the processor being used should decrease should be 2^(n-j)-1 in jth step
        CalculatePArrayKernel<<<dimGrid,dimBlock>>>(j,blockRow,blockColumn,deviceZA,deviceZB,deviceZC,deviceZ);
         cudaDeviceSynchronize(); //cpu will wait until cuda finish the job, this is such important function!

        }

          //backward
        //copy the device vector to host
        //cudaMemcpy(ZA,deviceZA,chunkSize,cudaMemcpyDeviceToHost);
       // sleep(20);
       
        cudaMemcpy(ZB,deviceZB,zSize,cudaMemcpyDeviceToHost);
        /*for(int i=0;i<2*m;i++)
        {
        	printf("zbresult:%lf \n",ZB[i]);
        }*/
        //cudaMemcpy(C,deviceC,chunkSize,cudaMemcpyDeviceToHost);
        cudaMemcpy(Z,deviceZ,zSize,cudaMemcpyDeviceToHost);
        int lastIndex=(int)pow(2,EXPO+1)-EXPO-3;
        float initialValue=Z[lastIndex]/ZB[lastIndex];
        //printf("initial value: %lf \n",initialValue);
        FinalX[0]=0;
        FinalX[(int)pow(2,EXPO-1)]=initialValue;
        //printf("the value in the middle is: %f and this suppose to close to 0.5 when n goes big! \n",FinalX[(int)pow(2,EXPO-1)]);

        cudaMemcpy(deviceFinalX,FinalX,finalLengthX*sizeof(float),cudaMemcpyHostToDevice);
        for(int k=EXPO-1;k>=1;k--)
        {
          //so the most one will use 2^(n-k) variable will be covered!
        dim3 dimGrid(1,1);
        int blockRow=pow(2,(EXPO-k)/2);
        int blockColumn=pow(2,EXPO-k-(EXPO-k)/2);
        dim3  dimBlock(blockColumn,blockRow);
        
        BackwardKernel<<<dimGrid,dimBlock>>>(k,blockRow,blockColumn,deviceZA,deviceZB,deviceZC,deviceZ,deviceFinalX,initialValue);
        cudaDeviceSynchronize();
        }
         

        cudaMemcpy(FinalX,deviceFinalX,finalLengthX*sizeof(float),cudaMemcpyDeviceToHost);
      }

      printf("\n final result for x(2^(k-1) block which should have %d values in it:\n",m);
       for (int i=1;i<finalLengthX-1;i++)
      {
       //this will we stored in X the 2^(k-1) the block.
        X[(loopH-1)*m+i-1]=FinalX[i];
      	printf("index: %d, %lf ",(loopH-1)*m+i-1,FinalX[i]);
      }
      printf("\n \n");
    
    //now need to do the block wise backsubstitution based on the formula of 5.4.2.17
     for(int step=EXPO-1;step>=1;step--)
     {
      //based on formula 5.4.2.30
     	//ok this is loop trhough the matrix in 5.4.2.17
     	int help1=pow(2,EXPO-step);
     	int localloopH=pow(2,step-1);
     	int thetaHelper=pow(2,step);
     	//inside of each step, you have this much of sybmatrix to solve
     	for(int backStep=1;backStep<=help1;backStep++)
     	{
     		//factorize B(step-1)
     		//first and last one need to be treat specially, C[j-1] will be just identity matrix here

     	
     	   	//************************************************************//
     	   	                 //this is to loop through the factorization
						     for(int j=1;j<=localloopH;j++)
						      {
						      	//for each j, za,zb,zc all going to be different
						      	ZA[0]=0;

						      	for(int i=1;i<m;i++)
						      	{
						      		ZA[i]=1.0;
						      	}
						      	//else will be 0,since it has been seperate to half and half
						        for(int i=m;i<chunkLengthZ;i++)
						        {
						          ZA[i]=0;
						        }

						        for(int i=0;i<m;i++)
						        {
						          ZB[i]=-4.0+2*cos((2.0*j-1.0)/(thetaHelper)*PI);
						          printf("zb:%f step: %d\n",ZB[i],step);
						        }
						        for(int i=m;i<chunkLengthZ;i++)
						        {
						          ZB[i]=0;
						        }

						        ZC[m-1]=0;
						        for(int i=0;i<m-1;i++)
						        {
						            ZC[i]=1.0;
						        }
						        for(int i=m;i<chunkLengthZ;i++)
						        {
						          ZC[i]=0;
						        }
						        //if it is the first step z will be from d, otherwise, z will be from the previous solution of x
						        if(j==1)
						        {
						        	//the first backsetp and last backstep will be special
						        	if(backStep==1)
						        	{
                                      //teh first d will be d(t-s)(j-1)-c(j-1)x(t)
								        		for(int i=0;i<m;i++)
								        	{
								        		//Z[i]=D[(loopH-1)*m+i]*(-1.0);
								        		//printf("this original one being called? %lf \n",Z[i]);
								        		Z[i]=(D[(conHelp-4*help1-step+1)*m+i]-X[(thetaHelper-1)*m+i])*(-1.0);

								        	}
								        	 for(int i=m;i<chunkLengthZ;i++)
										        {
										          Z[i]=0;
										        }
						        	}
						        	else if(backStep==help1)
						        	{
					        				for(int i=0;i<m;i++)
							        	{
							        		//Z[i]=D[(loopH-1)*m+i]*(-1.0);
							        		//printf("this original one being called? %lf \n",Z[i]);
							        		Z[i]=(D[(conHelp-2*help1-1-step)*m+i]-X[(conHelp/2-thetaHelper-1)*m+i])*(-1.0);

							        	}
							        	 for(int i=m;i<chunkLengthZ;i++)
									        {
									          Z[i]=0;
									        }

						        	}
						        	else //this is at the middle bakcstep
						        	{
						        			for(int i=0;i<m;i++)
							        	{
							        		//Z[i]=D[(loopH-1)*m+i]*(-1.0);
							        		//printf("this original one being called? %lf \n",Z[i]);
							        		Z[i]=(D[(2*backStep-1-step+conHelp-4*help1)*m+i]-X[(backStep*thetaHelper-1)*m+i]-X[((backStep-1)*thetaHelper-1)*m+i])*(-1.0);
							        	}
							        	 for(int i=m;i<chunkLengthZ;i++)
									        {
									          Z[i]=0;
									        }

						        	}
						        }
						        else
						        {
						        	for(int i=0;i<m;i++)
						        	{
						             //to do this will be x
						        		Z[i]=FinalX[i+1];
						        		//printf("does this ever called? %lf \n",Z[i]);
						        	}
						        	 for(int i=m;i<chunkLengthZ;i++)
								        {
								          Z[i]=0;
								        }
						        }

						        //now need to call the cyclic function to find the solution of x

						        cudaMemcpy(deviceZ,Z,zSize,cudaMemcpyHostToDevice);
						        cudaMemcpy(deviceZA,ZA,zSize,cudaMemcpyHostToDevice);
						        cudaMemcpy(deviceZB,ZB,zSize,cudaMemcpyHostToDevice);
						        cudaMemcpy(deviceZC,ZC,zSize,cudaMemcpyHostToDevice);

						        for(int j=1;j<EXPO;j++)
						        {
						        //the lock size should change, the first step it will need 2^(n-j)-1, so first step will be 3 if n=3
						        dim3 dimGrid(1,1);
						        int blockRow=pow(2,(EXPO-j)/2);
						        //printf("blockrow is :%d \n",blockRow);
						        int blockColumn=pow(2,EXPO-j-(EXPO-j)/2);
						        //printf("blockColumn is :%d \n",blockColumn);
						        dim3 dimBlock(blockColumn,blockRow);
						          //in each step the processor being used should decrease should be 2^(n-j)-1 in jth step
						        CalculatePArrayKernel<<<dimGrid,dimBlock>>>(j,blockRow,blockColumn,deviceZA,deviceZB,deviceZC,deviceZ);
						        cudaDeviceSynchronize(); //cpu will wait until cuda finish the job, this is such important function!

						        }

						          //backward
						        //copy the device vector to host
						        //cudaMemcpy(ZA,deviceZA,chunkSize,cudaMemcpyDeviceToHost);
						       // sleep(20);
						        
						        cudaMemcpy(ZB,deviceZB,zSize,cudaMemcpyDeviceToHost);
						     /*   for(int i=0;i<2*m;i++)
						        {
						        	printf("zbresult:%lf \n",ZB[i]);
						        }*/
						        //cudaMemcpy(C,deviceC,chunkSize,cudaMemcpyDeviceToHost);
						        cudaMemcpy(Z,deviceZ,zSize,cudaMemcpyDeviceToHost);
						        int lastIndex=(int)pow(2,EXPO+1)-EXPO-3;
						        float initialValue=Z[lastIndex]/ZB[lastIndex];
						        //printf("initial value: %lf \n",initialValue);
						        FinalX[0]=0;
						        FinalX[(int)pow(2,EXPO-1)]=initialValue;
						        //printf("the value in the middle is: %f and this suppose to close to 0.5 when n goes big! \n",FinalX[(int)pow(2,EXPO-1)]);

						        cudaMemcpy(deviceFinalX,FinalX,finalLengthX*sizeof(float),cudaMemcpyHostToDevice);
						        for(int k=EXPO-1;k>=1;k--)
						        {
						          //so the most one will use 2^(n-k) variable will be covered!
						        dim3 dimGrid(1,1);
						        int blockRow=pow(2,(EXPO-k)/2);
						        int blockColumn=pow(2,EXPO-k-(EXPO-k)/2);
						        dim3  dimBlock(blockColumn,blockRow);
						        
						        BackwardKernel<<<dimGrid,dimBlock>>>(k,blockRow,blockColumn,deviceZA,deviceZB,deviceZC,deviceZ,deviceFinalX,initialValue);
						          cudaDeviceSynchronize();
						           
						        }

                               cudaMemcpy(FinalX,deviceFinalX,finalLengthX*sizeof(float),cudaMemcpyDeviceToHost);

						      }
                              printf("\n");
						      for(int i=1;i<finalLengthX-1;i++)
						       {
						       	X[((2*backStep-1)*localloopH-1)*m+i-1]=FinalX[i];
                                //printf("%lf \n",FinalX[i]);
                                if(backStep==1)
                                {
                                	printf("test [%d],%lf \n",((2*backStep-1)*localloopH-1)*m+i-1,FinalX[i]);
                                }
						       }


     	   	//************************************************************//
     	}

     }

     printf("\n");
       for (int i=0;i<m*m;i++)
      {
       //this will we stored in X the 2^(k-1) the block.
      	if(m%31==0)
      	{
      		printf("\n");
      	}
        printf("[%d]:%lf ",i,X[i]);
      }
         double time_spent;
        end=clock();
       time_spent=(double)(end-begin)/CLOCKS_PER_SEC;
     
     printf("\n time spent to calcuate x with partition [0,1] into %d intervals:%lf seconds \n",m+1,time_spent);  
  }






	.file	"tmpxft_00352d9f_00000000-6_new.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2031:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.section	.text._ZSt3powIiiEN9__gnu_cxx11__promote_2IDTplcvNS1_IT_XsrSt12__is_integerIS2_E7__valueEE6__typeELi0EcvNS1_IT0_XsrS3_IS7_E7__valueEE6__typeELi0EEXsrS3_ISB_E7__valueEE6__typeES2_S7_,"axG",@progbits,_ZSt3powIiiEN9__gnu_cxx11__promote_2IDTplcvNS1_IT_XsrSt12__is_integerIS2_E7__valueEE6__typeELi0EcvNS1_IT0_XsrS3_IS7_E7__valueEE6__typeELi0EEXsrS3_ISB_E7__valueEE6__typeES2_S7_,comdat
	.weak	_ZSt3powIiiEN9__gnu_cxx11__promote_2IDTplcvNS1_IT_XsrSt12__is_integerIS2_E7__valueEE6__typeELi0EcvNS1_IT0_XsrS3_IS7_E7__valueEE6__typeELi0EEXsrS3_ISB_E7__valueEE6__typeES2_S7_
	.type	_ZSt3powIiiEN9__gnu_cxx11__promote_2IDTplcvNS1_IT_XsrSt12__is_integerIS2_E7__valueEE6__typeELi0EcvNS1_IT0_XsrS3_IS7_E7__valueEE6__typeELi0EEXsrS3_ISB_E7__valueEE6__typeES2_S7_, @function
_ZSt3powIiiEN9__gnu_cxx11__promote_2IDTplcvNS1_IT_XsrSt12__is_integerIS2_E7__valueEE6__typeELi0EcvNS1_IT0_XsrS3_IS7_E7__valueEE6__typeELi0EEXsrS3_ISB_E7__valueEE6__typeES2_S7_:
.LFB2028:
	.cfi_startproc
	endbr64
	cvtsi2sdl	%edi, %xmm0
	cvtsi2sdl	%esi, %xmm1
	jmp	pow@PLT
	.cfi_endproc
.LFE2028:
	.size	_ZSt3powIiiEN9__gnu_cxx11__promote_2IDTplcvNS1_IT_XsrSt12__is_integerIS2_E7__valueEE6__typeELi0EcvNS1_IT0_XsrS3_IS7_E7__valueEE6__typeELi0EEXsrS3_ISB_E7__valueEE6__typeES2_S7_, .-_ZSt3powIiiEN9__gnu_cxx11__promote_2IDTplcvNS1_IT_XsrSt12__is_integerIS2_E7__valueEE6__typeELi0EcvNS1_IT0_XsrS3_IS7_E7__valueEE6__typeELi0EEXsrS3_ISB_E7__valueEE6__typeES2_S7_
	.text
	.globl	_Z44__device_stub__Z13CalculateTheDiPfS_S_S_S_S_iPfS_S_S_S_S_
	.type	_Z44__device_stub__Z13CalculateTheDiPfS_S_S_S_S_iPfS_S_S_S_S_, @function
_Z44__device_stub__Z13CalculateTheDiPfS_S_S_S_S_iPfS_S_S_S_S_:
.LFB2053:
	.cfi_startproc
	endbr64
	subq	$200, %rsp
	.cfi_def_cfa_offset 208
	movq	208(%rsp), %rax
	movl	%edi, 60(%rsp)
	leaq	80(%rsp), %rdi
	movq	%rsi, 48(%rsp)
	leaq	92(%rsp), %rsi
	movq	%rdx, 40(%rsp)
	leaq	64(%rsp), %rdx
	movq	%rcx, 32(%rsp)
	leaq	72(%rsp), %rcx
	movq	%r8, 24(%rsp)
	movq	%r9, 16(%rsp)
	movq	%rax, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 184(%rsp)
	xorl	%eax, %eax
	leaq	60(%rsp), %rax
	movl	$1, 88(%rsp)
	movq	%rax, 128(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 176(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 80(%rsp)
	movq	%rax, 92(%rsp)
	movl	$1, 100(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L3
	pushq	72(%rsp)
	.cfi_def_cfa_offset 216
	leaq	_Z13CalculateTheDiPfS_S_S_S_S_(%rip), %rdi
	pushq	72(%rsp)
	.cfi_def_cfa_offset 224
	movq	108(%rsp), %rcx
	movl	116(%rsp), %r8d
	movq	96(%rsp), %rsi
	movl	104(%rsp), %edx
	leaq	144(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 216
	popq	%rdx
	.cfi_def_cfa_offset 208
.L3:
	movq	184(%rsp), %rax
	subq	%fs:40, %rax
	je	.L5
	call	__stack_chk_fail@PLT
.L5:
	addq	$200, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2053:
	.size	_Z44__device_stub__Z13CalculateTheDiPfS_S_S_S_S_iPfS_S_S_S_S_, .-_Z44__device_stub__Z13CalculateTheDiPfS_S_S_S_S_iPfS_S_S_S_S_
	.globl	_Z13CalculateTheDiPfS_S_S_S_S_
	.type	_Z13CalculateTheDiPfS_S_S_S_S_, @function
_Z13CalculateTheDiPfS_S_S_S_S_:
.LFB2054:
	.cfi_startproc
	endbr64
	jmp	_Z44__device_stub__Z13CalculateTheDiPfS_S_S_S_S_iPfS_S_S_S_S_
	.cfi_endproc
.LFE2054:
	.size	_Z13CalculateTheDiPfS_S_S_S_S_, .-_Z13CalculateTheDiPfS_S_S_S_S_
	.globl	_Z50__device_stub__Z21CalculatePArrayKerneliiiPfS_S_S_iiiPfS_S_S_
	.type	_Z50__device_stub__Z21CalculatePArrayKerneliiiPfS_S_S_iiiPfS_S_S_, @function
_Z50__device_stub__Z21CalculatePArrayKerneliiiPfS_S_S_iiiPfS_S_S_:
.LFB2055:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	192(%rsp), %rax
	movl	%edi, 44(%rsp)
	leaq	64(%rsp), %rdi
	movl	%esi, 40(%rsp)
	leaq	76(%rsp), %rsi
	movl	%edx, 36(%rsp)
	leaq	48(%rsp), %rdx
	movq	%rcx, 24(%rsp)
	leaq	56(%rsp), %rcx
	movq	%r8, 16(%rsp)
	movq	%r9, 8(%rsp)
	movq	%rax, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	44(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 112(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	36(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 152(%rsp)
	movq	%rsp, %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L9
	pushq	56(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z21CalculatePArrayKerneliiiPfS_S_S_(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 208
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L9:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L11
	call	__stack_chk_fail@PLT
.L11:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2055:
	.size	_Z50__device_stub__Z21CalculatePArrayKerneliiiPfS_S_S_iiiPfS_S_S_, .-_Z50__device_stub__Z21CalculatePArrayKerneliiiPfS_S_S_iiiPfS_S_S_
	.globl	_Z21CalculatePArrayKerneliiiPfS_S_S_
	.type	_Z21CalculatePArrayKerneliiiPfS_S_S_, @function
_Z21CalculatePArrayKerneliiiPfS_S_S_:
.LFB2056:
	.cfi_startproc
	endbr64
	jmp	_Z50__device_stub__Z21CalculatePArrayKerneliiiPfS_S_S_iiiPfS_S_S_
	.cfi_endproc
.LFE2056:
	.size	_Z21CalculatePArrayKerneliiiPfS_S_S_, .-_Z21CalculatePArrayKerneliiiPfS_S_S_
	.globl	_Z46__device_stub__Z14BackwardKerneliiiPfS_S_S_S_fiiiPfS_S_S_S_f
	.type	_Z46__device_stub__Z14BackwardKerneliiiPfS_S_S_S_fiiiPfS_S_S_S_f, @function
_Z46__device_stub__Z14BackwardKerneliiiPfS_S_S_S_fiiiPfS_S_S_S_f:
.LFB2057:
	.cfi_startproc
	endbr64
	subq	$216, %rsp
	.cfi_def_cfa_offset 224
	movq	224(%rsp), %rax
	movl	%edi, 60(%rsp)
	leaq	80(%rsp), %rdi
	movl	%esi, 56(%rsp)
	leaq	92(%rsp), %rsi
	movq	%rax, 16(%rsp)
	movq	232(%rsp), %rax
	movl	%edx, 52(%rsp)
	leaq	64(%rsp), %rdx
	movq	%rcx, 40(%rsp)
	leaq	72(%rsp), %rcx
	movq	%r8, 32(%rsp)
	movq	%r9, 24(%rsp)
	movq	%rax, 8(%rsp)
	movss	%xmm0, 48(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 200(%rsp)
	xorl	%eax, %eax
	leaq	60(%rsp), %rax
	movl	$1, 88(%rsp)
	movq	%rax, 128(%rsp)
	leaq	56(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	52(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 192(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 80(%rsp)
	movq	%rax, 92(%rsp)
	movl	$1, 100(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L14
	pushq	72(%rsp)
	.cfi_def_cfa_offset 232
	leaq	_Z14BackwardKerneliiiPfS_S_S_S_f(%rip), %rdi
	pushq	72(%rsp)
	.cfi_def_cfa_offset 240
	movq	108(%rsp), %rcx
	movl	116(%rsp), %r8d
	movq	96(%rsp), %rsi
	movl	104(%rsp), %edx
	leaq	144(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 232
	popq	%rdx
	.cfi_def_cfa_offset 224
.L14:
	movq	200(%rsp), %rax
	subq	%fs:40, %rax
	je	.L16
	call	__stack_chk_fail@PLT
.L16:
	addq	$216, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2057:
	.size	_Z46__device_stub__Z14BackwardKerneliiiPfS_S_S_S_fiiiPfS_S_S_S_f, .-_Z46__device_stub__Z14BackwardKerneliiiPfS_S_S_S_fiiiPfS_S_S_S_f
	.globl	_Z14BackwardKerneliiiPfS_S_S_S_f
	.type	_Z14BackwardKerneliiiPfS_S_S_S_f, @function
_Z14BackwardKerneliiiPfS_S_S_S_f:
.LFB2058:
	.cfi_startproc
	endbr64
	jmp	_Z46__device_stub__Z14BackwardKerneliiiPfS_S_S_S_fiiiPfS_S_S_S_f
	.cfi_endproc
.LFE2058:
	.size	_Z14BackwardKerneliiiPfS_S_S_S_f, .-_Z14BackwardKerneliiiPfS_S_S_S_f
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC4:
	.string	"dd block: %d %lf "
.LC5:
	.string	"\n"
.LC6:
	.string	"dha:%lf "
.LC13:
	.string	"\n final result for x(2^(k-1) block which should have %d values in it:\n"
.LC14:
	.string	"index: %d, %lf "
.LC15:
	.string	"\n \n"
.LC16:
	.string	"zb:%f step: %d\n"
.LC17:
	.string	"test [%d],%lf \n"
.LC18:
	.string	"[%d]:%lf "
.LC20:
	.string	"\n time spent to calcuate x with partition [0,1] into %d intervals:%lf seconds \n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movl	$3844, %edi
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$360, %rsp
	.cfi_def_cfa_offset 416
	movq	%fs:40, %rax
	movq	%rax, 344(%rsp)
	xorl	%eax, %eax
	call	malloc@PLT
	movl	$3844, %edi
	movq	%rax, %rbp
	call	malloc@PLT
	movl	$7068, %edi
	movq	%rax, %rbx
	call	malloc@PLT
	movl	$3844, %edi
	movq	%rax, 8(%rsp)
	call	malloc@PLT
	movl	$3844, %edi
	movq	%rax, 16(%rsp)
	call	malloc@PLT
	movl	$3844, %edi
	movq	%rax, 24(%rsp)
	call	malloc@PLT
	movl	$961, %ecx
	movq	%rbp, %rdi
	xorl	%edx, %edx
	movq	%rax, 32(%rsp)
	xorl	%eax, %eax
	movss	.LC0(%rip), %xmm1
	rep stosl
	movss	.LC1(%rip), %xmm0
	movl	$961, %ecx
	movq	%rbx, %rdi
	rep stosl
	movq	%rbp, %rax
.L21:
	movss	%xmm1, (%rax)
	testl	%edx, %edx
	jne	.L20
.L22:
	movss	%xmm0, 4(%rax)
	incl	%edx
	subq	$-128, %rax
	jmp	.L21
.L20:
	movss	%xmm0, -4(%rax)
	cmpl	$30, %edx
	jne	.L22
	movq	%rbx, %rax
	leaq	3968(%rbx), %rdx
.L23:
	movss	%xmm0, (%rax)
	subq	$-128, %rax
	cmpq	%rdx, %rax
	jne	.L23
	xorl	%r12d, %r12d
.L24:
	imulq	$124, %r12, %r14
	movq	8(%rsp), %rax
	movl	%r12d, %r15d
	xorl	%r13d, %r13d
	addq	%rax, %r14
.L25:
	movl	$0x3a800000, (%r14,%r13,4)
	movl	%r15d, %edx
	movb	$1, %al
	incq	%r13
	movsd	.LC3(%rip), %xmm0
	leaq	.LC4(%rip), %rsi
	movl	$2, %edi
	call	__printf_chk@PLT
	cmpq	$31, %r13
	jne	.L25
	leaq	.LC5(%rip), %r14
	movl	$2, %edi
	xorl	%eax, %eax
	incq	%r12
	movq	%r14, %rsi
	call	__printf_chk@PLT
	cmpq	$31, %r12
	jne	.L24
	movq	8(%rsp), %rax
	movl	$806, %ecx
	movl	$1, %r12d
	leaq	3844(%rax), %rdx
	xorl	%eax, %eax
	movq	%rdx, %rdi
	rep stosl
	movq	16(%rsp), %rdi
	movl	$961, %ecx
	rep stosl
	call	clock@PLT
	leaq	208(%rsp), %rdi
	movl	$3844, %esi
	movq	%rax, 160(%rsp)
	call	cudaMalloc@PLT
	leaq	216(%rsp), %rdi
	movl	$3844, %esi
	call	cudaMalloc@PLT
	leaq	224(%rsp), %rdi
	movl	$7068, %esi
	call	cudaMalloc@PLT
	leaq	232(%rsp), %rdi
	movl	$3844, %esi
	call	cudaMalloc@PLT
	leaq	240(%rsp), %rdi
	movl	$3844, %esi
	call	cudaMalloc@PLT
	leaq	248(%rsp), %rdi
	movl	$3844, %esi
	call	cudaMalloc@PLT
	movq	208(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbp, %rsi
	movl	$3844, %edx
	call	cudaMemcpy@PLT
	movq	216(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbx, %rsi
	movl	$3844, %edx
	call	cudaMemcpy@PLT
	movq	8(%rsp), %rsi
	movl	$1, %ecx
	movq	224(%rsp), %rdi
	movl	$7068, %edx
	call	cudaMemcpy@PLT
	movq	16(%rsp), %rsi
	movl	$1, %ecx
	movq	232(%rsp), %rdi
	movl	$3844, %edx
	call	cudaMemcpy@PLT
	movq	24(%rsp), %rsi
	movl	$1, %ecx
	movq	240(%rsp), %rdi
	movl	$3844, %edx
	call	cudaMemcpy@PLT
	movq	32(%rsp), %rsi
	movl	$1, %ecx
	movq	248(%rsp), %rdi
	movl	$3844, %edx
	call	cudaMemcpy@PLT
	movabsq	$137438953473, %rax
	movl	$1, 304(%rsp)
	movq	%rax, 296(%rsp)
	movabsq	$68719476752, %rax
	movq	%rax, 308(%rsp)
	movl	$1, 316(%rsp)
.L28:
	movl	316(%rsp), %ecx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	308(%rsp), %rdx
	movq	296(%rsp), %rdi
	movl	304(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L27
	pushq	%r15
	.cfi_def_cfa_offset 424
	movl	%r12d, %edi
	pushq	256(%rsp)
	.cfi_def_cfa_offset 432
	movq	256(%rsp), %r9
	movq	248(%rsp), %r8
	movq	240(%rsp), %rcx
	movq	232(%rsp), %rdx
	movq	224(%rsp), %rsi
	call	_Z44__device_stub__Z13CalculateTheDiPfS_S_S_S_S_iPfS_S_S_S_S_
	popq	%rax
	.cfi_def_cfa_offset 424
	popq	%rdx
	.cfi_def_cfa_offset 416
.L27:
	incl	%r12d
	cmpl	$5, %r12d
	jne	.L28
	call	cudaDeviceSynchronize@PLT
	movq	224(%rsp), %rsi
	movq	8(%rsp), %rdi
	xorl	%r15d, %r15d
	movl	$2, %ecx
	movl	$7068, %edx
	leaq	.LC6(%rip), %r12
	call	cudaMemcpy@PLT
.L30:
	imull	$-1108378657, %r15d, %eax
	cmpl	$138547332, %eax
	ja	.L29
	movq	%r14, %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
.L29:
	movq	8(%rsp), %rax
	movq	%r12, %rsi
	movl	$2, %edi
	cvtss2sd	(%rax,%r15,4), %xmm0
	movb	$1, %al
	incq	%r15
	call	__printf_chk@PLT
	cmpq	$1767, %r15
	jne	.L30
	movq	208(%rsp), %rdi
	call	cudaFree@PLT
	movq	216(%rsp), %rdi
	call	cudaFree@PLT
	movq	240(%rsp), %rdi
	call	cudaFree@PLT
	movq	248(%rsp), %rdi
	call	cudaFree@PLT
	movq	%rbp, %rdi
	movl	$1, %ebp
	call	free@PLT
	movq	%rbx, %rdi
	call	free@PLT
	movq	24(%rsp), %rdi
	call	free@PLT
	movq	32(%rsp), %rdi
	call	free@PLT
	movl	$252, %edi
	call	malloc@PLT
	movl	$252, %edi
	movq	%rax, %rbx
	call	malloc@PLT
	movl	$252, %edi
	movq	%rax, 32(%rsp)
	call	malloc@PLT
	movl	$252, %edi
	movq	%rax, 24(%rsp)
	call	malloc@PLT
	movl	$132, %edi
	movq	%rax, 40(%rsp)
	call	malloc@PLT
	leaq	256(%rsp), %rdi
	movl	$252, %esi
	movq	%rax, %r15
	call	cudaMalloc@PLT
	leaq	264(%rsp), %rdi
	movl	$252, %esi
	call	cudaMalloc@PLT
	leaq	272(%rsp), %rdi
	movl	$252, %esi
	call	cudaMalloc@PLT
	leaq	280(%rsp), %rdi
	movl	$252, %esi
	call	cudaMalloc@PLT
	leaq	288(%rsp), %rdi
	movl	$132, %esi
	call	cudaMalloc@PLT
.L41:
	movq	32(%rsp), %rax
	movl	$0x00000000, (%rax)
	movl	$1, %eax
.L31:
	movq	32(%rsp), %rcx
	movl	$0x3f800000, (%rcx,%rax,4)
	incq	%rax
	cmpq	$31, %rax
	jne	.L31
	cvtsi2sdl	%ebp, %xmm0
	movq	%rcx, %rax
	movl	$32, %ecx
	addq	$124, %rax
	movq	%rax, 104(%rsp)
	movq	%rax, %rdi
	xorl	%eax, %eax
	rep stosl
	addsd	%xmm0, %xmm0
	subsd	.LC8(%rip), %xmm0
	mulsd	.LC9(%rip), %xmm0
	mulsd	.LC10(%rip), %xmm0
	call	cos@PLT
	xorl	%eax, %eax
	addsd	%xmm0, %xmm0
	subsd	.LC11(%rip), %xmm0
	cvtsd2ss	%xmm0, %xmm0
.L32:
	movq	24(%rsp), %rdx
	movss	%xmm0, (%rdx,%rax,4)
	incq	%rax
	cmpq	$31, %rax
	jne	.L32
	movq	%rdx, %rax
	movl	$32, %ecx
	addq	$124, %rax
	movq	%rax, %rdi
	movq	%rax, 96(%rsp)
	xorl	%eax, %eax
	rep stosl
	movq	40(%rsp), %rax
	movl	$0x00000000, 120(%rax)
	xorl	%eax, %eax
.L33:
	movq	40(%rsp), %rcx
	movl	$0x3f800000, (%rcx,%rax,4)
	incq	%rax
	cmpq	$30, %rax
	jne	.L33
	movq	%rcx, %rax
	movl	$32, %ecx
	addq	$124, %rax
	movq	%rax, %rdi
	movq	%rax, 88(%rsp)
	xorl	%eax, %eax
	rep stosl
	cmpl	$1, %ebp
	jne	.L34
	xorl	%eax, %eax
.L35:
	movq	8(%rsp), %rdx
	cvtss2sd	6944(%rdx,%rax), %xmm0
	xorps	.LC12(%rip), %xmm0
	cvtsd2ss	%xmm0, %xmm0
	movss	%xmm0, (%rbx,%rax)
	addq	$4, %rax
	cmpq	$124, %rax
	jne	.L35
.L91:
	leaq	124(%rbx), %rdx
	xorl	%eax, %eax
	movl	$32, %ecx
	movq	%rbx, %rsi
	movq	%rdx, %rdi
	movl	$252, %edx
	movl	$4, %r12d
	rep stosl
	movl	$1, %ecx
	movq	256(%rsp), %rdi
	call	cudaMemcpy@PLT
	movq	32(%rsp), %rsi
	movl	$1, %ecx
	movq	264(%rsp), %rdi
	movl	$252, %edx
	call	cudaMemcpy@PLT
	movq	24(%rsp), %rsi
	movl	$1, %ecx
	movq	272(%rsp), %rdi
	movl	$252, %edx
	call	cudaMemcpy@PLT
	movq	40(%rsp), %rsi
	movl	$1, %ecx
	movq	280(%rsp), %rdi
	movl	$252, %edx
	call	cudaMemcpy@PLT
	jmp	.L36
.L34:
	leaq	4(%r15), %rsi
	movl	$31, %ecx
	movq	%rbx, %rdi
	rep movsl
	jmp	.L91
.L36:
	movl	%r12d, %r14d
	movl	$2, %edi
	movabsq	$4294967297, %rax
	movl	$1, 328(%rsp)
	sarl	%r14d
	movq	%rax, 320(%rsp)
	movl	%r14d, %esi
	call	_ZSt3powIiiEN9__gnu_cxx11__promote_2IDTplcvNS1_IT_XsrSt12__is_integerIS2_E7__valueEE6__typeELi0EcvNS1_IT0_XsrS3_IS7_E7__valueEE6__typeELi0EEXsrS3_ISB_E7__valueEE6__typeES2_S7_
	movl	%r12d, %esi
	movl	$2, %edi
	subl	%r14d, %esi
	cvttsd2sil	%xmm0, %r13d
	call	_ZSt3powIiiEN9__gnu_cxx11__promote_2IDTplcvNS1_IT_XsrSt12__is_integerIS2_E7__valueEE6__typeELi0EcvNS1_IT0_XsrS3_IS7_E7__valueEE6__typeELi0EEXsrS3_ISB_E7__valueEE6__typeES2_S7_
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$1, %ecx
	cvttsd2sil	%xmm0, %r14d
	movq	320(%rsp), %rdi
	movl	328(%rsp), %esi
	movl	$1, 340(%rsp)
	movl	%r13d, 336(%rsp)
	movl	%r14d, 332(%rsp)
	movq	332(%rsp), %rdx
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L38
	pushq	%r10
	.cfi_def_cfa_offset 424
	movl	$5, %edi
	movl	%r13d, %esi
	movl	%r14d, %edx
	pushq	264(%rsp)
	.cfi_def_cfa_offset 432
	movq	296(%rsp), %r9
	subl	%r12d, %edi
	movq	288(%rsp), %r8
	movq	280(%rsp), %rcx
	call	_Z50__device_stub__Z21CalculatePArrayKerneliiiPfS_S_S_iiiPfS_S_S_
	popq	%r11
	.cfi_def_cfa_offset 424
	popq	%r13
	.cfi_def_cfa_offset 416
.L38:
	call	cudaDeviceSynchronize@PLT
	decl	%r12d
	jne	.L36
	movq	24(%rsp), %rdi
	movl	$2, %ecx
	movl	$252, %edx
	movq	272(%rsp), %rsi
	movl	$4, %r12d
	call	cudaMemcpy@PLT
	movq	256(%rsp), %rsi
	movl	$2, %ecx
	movq	%rbx, %rdi
	movl	$252, %edx
	call	cudaMemcpy@PLT
	movq	24(%rsp), %rax
	movq	%r15, %rsi
	movl	$0x00000000, (%r15)
	movq	288(%rsp), %rdi
	movl	$1, %ecx
	movl	$132, %edx
	movss	224(%rbx), %xmm0
	divss	224(%rax), %xmm0
	movss	%xmm0, 64(%r15)
	movss	%xmm0, 56(%rsp)
	call	cudaMemcpy@PLT
.L40:
	movl	$5, %r13d
	movl	$2, %edi
	movabsq	$4294967297, %rax
	movl	$1, 328(%rsp)
	subl	%r12d, %r13d
	movq	%rax, 320(%rsp)
	movl	%r13d, %eax
	sarl	%eax
	movl	%eax, %esi
	movl	%eax, 52(%rsp)
	call	_ZSt3powIiiEN9__gnu_cxx11__promote_2IDTplcvNS1_IT_XsrSt12__is_integerIS2_E7__valueEE6__typeELi0EcvNS1_IT0_XsrS3_IS7_E7__valueEE6__typeELi0EEXsrS3_ISB_E7__valueEE6__typeES2_S7_
	movl	52(%rsp), %eax
	movl	%r13d, %esi
	movl	$2, %edi
	cvttsd2sil	%xmm0, %r14d
	subl	%eax, %esi
	call	_ZSt3powIiiEN9__gnu_cxx11__promote_2IDTplcvNS1_IT_XsrSt12__is_integerIS2_E7__valueEE6__typeELi0EcvNS1_IT0_XsrS3_IS7_E7__valueEE6__typeELi0EEXsrS3_ISB_E7__valueEE6__typeES2_S7_
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$1, %ecx
	cvttsd2sil	%xmm0, %r13d
	movq	320(%rsp), %rdi
	movl	328(%rsp), %esi
	movl	$1, 340(%rsp)
	movl	%r14d, 336(%rsp)
	movl	%r13d, 332(%rsp)
	movq	332(%rsp), %rdx
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L39
	pushq	288(%rsp)
	.cfi_def_cfa_offset 424
	movl	%r13d, %edx
	movl	%r14d, %esi
	movl	%r12d, %edi
	pushq	264(%rsp)
	.cfi_def_cfa_offset 432
	movss	72(%rsp), %xmm0
	movq	296(%rsp), %r9
	movq	288(%rsp), %r8
	movq	280(%rsp), %rcx
	call	_Z46__device_stub__Z14BackwardKerneliiiPfS_S_S_S_fiiiPfS_S_S_S_f
	popq	%r8
	.cfi_def_cfa_offset 424
	popq	%r9
	.cfi_def_cfa_offset 416
.L39:
	call	cudaDeviceSynchronize@PLT
	decl	%r12d
	jne	.L40
	movl	$2, %ecx
	movl	$132, %edx
	movq	%r15, %rdi
	incl	%ebp
	movq	288(%rsp), %rsi
	call	cudaMemcpy@PLT
	cmpl	$17, %ebp
	jne	.L41
	movl	$31, %edx
	leaq	.LC13(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movl	$1, %r12d
	leaq	.LC14(%rip), %rbp
.L42:
	movss	(%r15,%r12,4), %xmm0
	movq	16(%rsp), %rax
	movq	%rbp, %rsi
	movl	$2, %edi
	leal	464(%r12), %edx
	movss	%xmm0, 1856(%rax,%r12,4)
	movb	$1, %al
	incq	%r12
	cvtss2sd	%xmm0, %xmm0
	call	__printf_chk@PLT
	cmpq	$32, %r12
	jne	.L42
	leaq	.LC15(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movl	$4, 60(%rsp)
.L62:
	movl	60(%rsp), %eax
	movl	$5, %esi
	movl	$2, %edi
	subl	%eax, %esi
	movl	%eax, 64(%rsp)
	call	_ZSt3powIiiEN9__gnu_cxx11__promote_2IDTplcvNS1_IT_XsrSt12__is_integerIS2_E7__valueEE6__typeELi0EcvNS1_IT0_XsrS3_IS7_E7__valueEE6__typeELi0EEXsrS3_ISB_E7__valueEE6__typeES2_S7_
	decl	60(%rsp)
	movl	60(%rsp), %esi
	movl	$2, %edi
	cvttsd2sil	%xmm0, %r14d
	call	_ZSt3powIiiEN9__gnu_cxx11__promote_2IDTplcvNS1_IT_XsrSt12__is_integerIS2_E7__valueEE6__typeELi0EcvNS1_IT0_XsrS3_IS7_E7__valueEE6__typeELi0EEXsrS3_ISB_E7__valueEE6__typeES2_S7_
	movl	64(%rsp), %esi
	movl	$2, %edi
	cvttsd2sil	%xmm0, %eax
	movl	%eax, 56(%rsp)
	call	_ZSt3powIiiEN9__gnu_cxx11__promote_2IDTplcvNS1_IT_XsrSt12__is_integerIS2_E7__valueEE6__typeELi0EcvNS1_IT0_XsrS3_IS7_E7__valueEE6__typeELi0EEXsrS3_ISB_E7__valueEE6__typeES2_S7_
	movq	16(%rsp), %rcx
	leal	0(,%r14,4), %edx
	movl	$1, 52(%rsp)
	cvttsd2sil	%xmm0, %eax
	movl	%eax, 80(%rsp)
	imull	$62, 56(%rsp), %eax
	movl	%eax, 196(%rsp)
	movl	56(%rsp), %eax
	addl	%eax, %eax
	cltq
	imulq	$124, %rax, %rax
	movq	%rax, 168(%rsp)
	movslq	56(%rsp), %rax
	imulq	$124, %rax, %rax
	addq	%rcx, %rax
	movl	64(%rsp), %ecx
	movq	%rax, 72(%rsp)
	imull	$31, 56(%rsp), %eax
	movl	%eax, 192(%rsp)
	movl	64(%rsp), %eax
	addl	%edx, %eax
	imull	$-31, %eax, %eax
	addl	$2015, %eax
	movl	%eax, 120(%rsp)
	imull	$31, 80(%rsp), %eax
	movl	%eax, 116(%rsp)
	movl	$63, %eax
	subl	%ecx, %eax
	leal	(%r14,%r14), %ecx
	subl	%ecx, %eax
	movq	8(%rsp), %rcx
	imull	$31, %eax, %eax
	cltq
	leaq	(%rcx,%rax,4), %rax
	movl	80(%rsp), %ecx
	movq	%rax, 136(%rsp)
	movl	$31, %eax
	subl	%ecx, %eax
	movq	16(%rsp), %rcx
	imull	$31, %eax, %eax
	cltq
	leaq	(%rcx,%rax,4), %rax
	movl	64(%rsp), %ecx
	movq	%rax, 144(%rsp)
	movl	$64, %eax
	subl	%ecx, %eax
	subl	%edx, %eax
	movq	8(%rsp), %rdx
	incl	%eax
	imull	$31, %eax, %eax
	cltq
	leaq	(%rdx,%rax,4), %rax
	movq	16(%rsp), %rdx
	movq	%rax, 128(%rsp)
	movl	116(%rsp), %eax
	subl	$31, %eax
	cltq
	leaq	(%rdx,%rax,4), %rax
	movq	%rax, 184(%rsp)
	movq	$-31, %rax
.L43:
	cmpl	%r14d, 52(%rsp)
	jg	.L60
	movl	116(%rsp), %ecx
	movl	$1, 68(%rsp)
	leal	(%rax,%rcx), %edx
	movq	8(%rsp), %rcx
	movl	%edx, 124(%rsp)
	movslq	120(%rsp), %rdx
	leaq	(%rcx,%rdx,4), %rdx
	movq	16(%rsp), %rcx
	movq	%rdx, 176(%rsp)
	movslq	124(%rsp), %rdx
	leaq	(%rcx,%rax,4), %rax
	leaq	(%rcx,%rdx,4), %rdx
	movq	%rax, 200(%rsp)
	movq	%rdx, 152(%rsp)
.L61:
	movl	56(%rsp), %edx
	cmpl	%edx, 68(%rsp)
	jg	.L94
	movq	32(%rsp), %rax
	movss	.LC1(%rip), %xmm0
	movl	$0x00000000, (%rax)
	movl	$1, %eax
.L44:
	movq	32(%rsp), %rdx
	movss	%xmm0, (%rdx,%rax,4)
	incq	%rax
	cmpq	$31, %rax
	jne	.L44
	cvtsi2sdl	68(%rsp), %xmm0
	movq	104(%rsp), %rdi
	xorl	%eax, %eax
	xorl	%r13d, %r13d
	cvtsi2sdl	80(%rsp), %xmm1
	movl	$32, %ecx
	leaq	.LC16(%rip), %rbp
	rep stosl
	addsd	%xmm0, %xmm0
	subsd	.LC8(%rip), %xmm0
	divsd	%xmm1, %xmm0
	mulsd	.LC10(%rip), %xmm0
	call	cos@PLT
	addsd	%xmm0, %xmm0
	subsd	.LC11(%rip), %xmm0
	cvtsd2ss	%xmm0, %xmm1
	cvtss2sd	%xmm1, %xmm3
	movq	%xmm3, %r12
.L45:
	movq	24(%rsp), %rax
	movl	64(%rsp), %edx
	movq	%r12, %xmm0
	movq	%rbp, %rsi
	movl	$2, %edi
	movss	%xmm1, 84(%rsp)
	movss	%xmm1, (%rax,%r13,4)
	movb	$1, %al
	incq	%r13
	call	__printf_chk@PLT
	cmpq	$31, %r13
	movss	84(%rsp), %xmm1
	jne	.L45
	movq	96(%rsp), %rdi
	xorl	%eax, %eax
	movl	$32, %ecx
	movss	.LC1(%rip), %xmm0
	rep stosl
	movq	40(%rsp), %rax
	movl	$0x00000000, 120(%rax)
	xorl	%eax, %eax
.L46:
	movq	40(%rsp), %rdx
	movss	%xmm0, (%rdx,%rax,4)
	incq	%rax
	cmpq	$30, %rax
	jne	.L46
	movq	88(%rsp), %rdi
	xorl	%eax, %eax
	movl	$32, %ecx
	cmpl	$1, 68(%rsp)
	rep stosl
	jne	.L47
	xorl	%eax, %eax
	cmpl	$1, 52(%rsp)
	jne	.L48
.L49:
	movq	128(%rsp), %rdx
	movq	184(%rsp), %rcx
	movss	(%rdx,%rax), %xmm0
	subss	(%rcx,%rax), %xmm0
	cvtss2sd	%xmm0, %xmm0
	xorps	.LC12(%rip), %xmm0
	cvtsd2ss	%xmm0, %xmm0
	movss	%xmm0, (%rbx,%rax)
	addq	$4, %rax
	cmpq	$124, %rax
	jne	.L49
.L92:
	leaq	124(%rbx), %rdx
	movl	$32, %ecx
	xorl	%eax, %eax
.L93:
	movq	%rdx, %rdi
	movq	%rbx, %rsi
	movl	$252, %edx
	movl	$4, %ebp
	rep stosl
	movl	$1, %ecx
	movq	256(%rsp), %rdi
	call	cudaMemcpy@PLT
	movq	32(%rsp), %rsi
	movl	$1, %ecx
	movq	264(%rsp), %rdi
	movl	$252, %edx
	call	cudaMemcpy@PLT
	movq	24(%rsp), %rsi
	movl	$1, %ecx
	movq	272(%rsp), %rdi
	movl	$252, %edx
	call	cudaMemcpy@PLT
	movq	40(%rsp), %rsi
	movl	$1, %ecx
	movq	280(%rsp), %rdi
	movl	$252, %edx
	call	cudaMemcpy@PLT
	jmp	.L50
.L48:
	cmpl	%r14d, 52(%rsp)
	jne	.L51
.L52:
	movq	136(%rsp), %rcx
	movq	144(%rsp), %rdx
	movss	(%rcx,%rax), %xmm0
	subss	(%rdx,%rax), %xmm0
	cvtss2sd	%xmm0, %xmm0
	xorps	.LC12(%rip), %xmm0
	cvtsd2ss	%xmm0, %xmm0
	movss	%xmm0, (%rbx,%rax)
	addq	$4, %rax
	cmpq	$124, %rax
	jne	.L52
	jmp	.L92
.L51:
	movq	176(%rsp), %rcx
	movq	152(%rsp), %rdx
	movss	(%rcx,%rax), %xmm0
	movq	200(%rsp), %rcx
	subss	(%rdx,%rax), %xmm0
	subss	(%rcx,%rax), %xmm0
	cvtss2sd	%xmm0, %xmm0
	xorps	.LC12(%rip), %xmm0
	cvtsd2ss	%xmm0, %xmm0
	movss	%xmm0, (%rbx,%rax)
	addq	$4, %rax
	cmpq	$124, %rax
	jne	.L51
	jmp	.L92
.L47:
	leaq	4(%r15), %rsi
	movl	$31, %ecx
	leaq	124(%rbx), %rdx
	movq	%rbx, %rdi
	rep movsl
	movl	$32, %ecx
	jmp	.L93
.L50:
	movl	%ebp, %r13d
	movl	$2, %edi
	movabsq	$4294967297, %rax
	movl	$1, 328(%rsp)
	sarl	%r13d
	movq	%rax, 320(%rsp)
	movl	%r13d, %esi
	call	_ZSt3powIiiEN9__gnu_cxx11__promote_2IDTplcvNS1_IT_XsrSt12__is_integerIS2_E7__valueEE6__typeELi0EcvNS1_IT0_XsrS3_IS7_E7__valueEE6__typeELi0EEXsrS3_ISB_E7__valueEE6__typeES2_S7_
	movl	%ebp, %esi
	movl	$2, %edi
	subl	%r13d, %esi
	cvttsd2sil	%xmm0, %r12d
	call	_ZSt3powIiiEN9__gnu_cxx11__promote_2IDTplcvNS1_IT_XsrSt12__is_integerIS2_E7__valueEE6__typeELi0EcvNS1_IT0_XsrS3_IS7_E7__valueEE6__typeELi0EEXsrS3_ISB_E7__valueEE6__typeES2_S7_
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$1, %ecx
	cvttsd2sil	%xmm0, %r13d
	movq	320(%rsp), %rdi
	movl	328(%rsp), %esi
	movl	$1, 340(%rsp)
	movl	%r12d, 336(%rsp)
	movl	%r13d, 332(%rsp)
	movq	332(%rsp), %rdx
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L54
	pushq	%rcx
	.cfi_def_cfa_offset 424
	movl	$5, %edi
	movl	%r12d, %esi
	movl	%r13d, %edx
	pushq	264(%rsp)
	.cfi_def_cfa_offset 432
	movq	296(%rsp), %r9
	subl	%ebp, %edi
	movq	288(%rsp), %r8
	movq	280(%rsp), %rcx
	call	_Z50__device_stub__Z21CalculatePArrayKerneliiiPfS_S_S_iiiPfS_S_S_
	popq	%rsi
	.cfi_def_cfa_offset 424
	popq	%rdi
	.cfi_def_cfa_offset 416
.L54:
	call	cudaDeviceSynchronize@PLT
	decl	%ebp
	jne	.L50
	movq	24(%rsp), %rdi
	movl	$2, %ecx
	movl	$252, %edx
	movq	272(%rsp), %rsi
	movl	$4, %r12d
	call	cudaMemcpy@PLT
	movq	256(%rsp), %rsi
	movl	$2, %ecx
	movq	%rbx, %rdi
	movl	$252, %edx
	call	cudaMemcpy@PLT
	movq	24(%rsp), %rax
	movq	%r15, %rsi
	movl	$0x00000000, (%r15)
	movq	288(%rsp), %rdi
	movl	$1, %ecx
	movl	$132, %edx
	movss	224(%rbx), %xmm0
	divss	224(%rax), %xmm0
	movss	%xmm0, 64(%r15)
	movss	%xmm0, 112(%rsp)
	call	cudaMemcpy@PLT
.L56:
	movl	$5, %ebp
	movl	$2, %edi
	movabsq	$4294967297, %rax
	movl	$1, 328(%rsp)
	subl	%r12d, %ebp
	movq	%rax, 320(%rsp)
	movl	%ebp, %eax
	sarl	%eax
	movl	%eax, %esi
	movl	%eax, 84(%rsp)
	call	_ZSt3powIiiEN9__gnu_cxx11__promote_2IDTplcvNS1_IT_XsrSt12__is_integerIS2_E7__valueEE6__typeELi0EcvNS1_IT0_XsrS3_IS7_E7__valueEE6__typeELi0EEXsrS3_ISB_E7__valueEE6__typeES2_S7_
	movl	84(%rsp), %eax
	movl	%ebp, %esi
	movl	$2, %edi
	cvttsd2sil	%xmm0, %r13d
	subl	%eax, %esi
	call	_ZSt3powIiiEN9__gnu_cxx11__promote_2IDTplcvNS1_IT_XsrSt12__is_integerIS2_E7__valueEE6__typeELi0EcvNS1_IT0_XsrS3_IS7_E7__valueEE6__typeELi0EEXsrS3_ISB_E7__valueEE6__typeES2_S7_
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$1, %ecx
	cvttsd2sil	%xmm0, %ebp
	movq	320(%rsp), %rdi
	movl	328(%rsp), %esi
	movl	$1, 340(%rsp)
	movl	%r13d, 336(%rsp)
	movl	%ebp, 332(%rsp)
	movq	332(%rsp), %rdx
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L55
	pushq	288(%rsp)
	.cfi_def_cfa_offset 424
	movl	%ebp, %edx
	movl	%r13d, %esi
	movl	%r12d, %edi
	pushq	264(%rsp)
	.cfi_def_cfa_offset 432
	movss	128(%rsp), %xmm0
	movq	296(%rsp), %r9
	movq	288(%rsp), %r8
	movq	280(%rsp), %rcx
	call	_Z46__device_stub__Z14BackwardKerneliiiPfS_S_S_S_fiiiPfS_S_S_S_f
	popq	%rax
	.cfi_def_cfa_offset 424
	popq	%rdx
	.cfi_def_cfa_offset 416
.L55:
	call	cudaDeviceSynchronize@PLT
	decl	%r12d
	jne	.L56
	movq	288(%rsp), %rsi
	movl	$2, %ecx
	movl	$132, %edx
	movq	%r15, %rdi
	call	cudaMemcpy@PLT
	incl	68(%rsp)
	jmp	.L61
.L94:
	leaq	.LC5(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	movl	$1, %r12d
	call	__printf_chk@PLT
	leaq	.LC17(%rip), %rbp
.L59:
	movss	(%r15,%r12,4), %xmm0
	movq	72(%rsp), %rax
	cmpl	$1, 52(%rsp)
	movss	%xmm0, -128(%rax,%r12,4)
	jne	.L58
	movl	192(%rsp), %eax
	movq	%rbp, %rsi
	movl	$2, %edi
	cvtss2sd	%xmm0, %xmm0
	leal	-32(%rax,%r12), %edx
	movb	$1, %al
	call	__printf_chk@PLT
.L58:
	incq	%r12
	cmpq	$32, %r12
	jne	.L59
	movq	168(%rsp), %rcx
	movl	196(%rsp), %edx
	incl	52(%rsp)
	movslq	124(%rsp), %rax
	addq	%rcx, 72(%rsp)
	addl	%edx, 192(%rsp)
	addl	$62, 120(%rsp)
	jmp	.L43
.L60:
	cmpl	$0, 60(%rsp)
	jne	.L62
	leaq	.LC5(%rip), %rbp
	movl	$2, %edi
	xorl	%eax, %eax
	xorl	%ebx, %ebx
	movq	%rbp, %rsi
	leaq	.LC18(%rip), %r12
	call	__printf_chk@PLT
.L63:
	movq	%rbp, %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movq	16(%rsp), %rax
	movl	%ebx, %edx
	movq	%r12, %rsi
	movl	$2, %edi
	cvtss2sd	(%rax,%rbx,4), %xmm0
	movb	$1, %al
	incq	%rbx
	call	__printf_chk@PLT
	cmpq	$961, %rbx
	jne	.L63
	call	clock@PLT
	movl	$32, %edx
	movl	$2, %edi
	movq	160(%rsp), %rbx
	leaq	.LC20(%rip), %rsi
	subq	%rbx, %rax
	cvtsi2sdq	%rax, %xmm0
	movb	$1, %al
	divsd	.LC19(%rip), %xmm0
	call	__printf_chk@PLT
	movq	344(%rsp), %rax
	subq	%fs:40, %rax
	je	.L64
	call	__stack_chk_fail@PLT
.L64:
	addq	$360, %rsp
	.cfi_def_cfa_offset 56
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2027:
	.size	main, .-main
	.section	.rodata.str1.1
.LC21:
	.string	"_Z14BackwardKerneliiiPfS_S_S_S_f"
.LC22:
	.string	"_Z21CalculatePArrayKerneliiiPfS_S_S_"
.LC23:
	.string	"_Z13CalculateTheDiPfS_S_S_S_S_"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2060:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC21(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z14BackwardKerneliiiPfS_S_S_S_f(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC22(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z21CalculatePArrayKerneliiiPfS_S_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC23(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z13CalculateTheDiPfS_S_S_S_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2060:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst4,"aM",@progbits,4
	.align 4
.LC0:
	.long	-1065353216
	.align 4
.LC1:
	.long	1065353216
	.section	.rodata.cst8,"aM",@progbits,8
	.align 8
.LC3:
	.long	0
	.long	1062207488
	.align 8
.LC8:
	.long	0
	.long	1072693248
	.align 8
.LC9:
	.long	0
	.long	1067450368
	.align 8
.LC10:
	.long	1405670641
	.long	1074340347
	.align 8
.LC11:
	.long	0
	.long	1074790400
	.section	.rodata.cst16,"aM",@progbits,16
	.align 16
.LC12:
	.long	0
	.long	-2147483648
	.long	0
	.long	0
	.section	.rodata.cst8
	.align 8
.LC19:
	.long	0
	.long	1093567616
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

       #include <stdio.h>
    #include <hip/hip_runtime.h>
    #include <time.h>
    #include <math.h>
    //#include <unistd.h>
    #define EXPO 5 //so [0,1] will be break into 2^6 intervals 64*64
    #define PI 3.14159265

    __global__ void CalculateTheD(int step,float* deviceB, float* deviceC, float* deviceD, float* deviceX, float* devicenewB, float* devicenewC)
    {
       int blocksize=16;
       int gridsize=gridDim.x; //this will always be 1
       // int gridsize2=gridDim.x;
       // printf("gridsize: %d %d\n", gridsize,gridsize2);
       // __device__ bool myGlobalFlag=true;
       
        int bx=blockIdx.x;
        int by=blockIdx.y;
        int tx=threadIdx.x;
        int ty=threadIdx.y;
        
        int blocktotal=blocksize*blocksize;
        int temp1=by*gridsize+bx;
        if(tx==1&&ty==1)
        {
        	printf("temp1: %d \n",temp1);
        }
        int temp2=ty*blocksize+tx;

       int ind=temp1*blocktotal+temp2;

      int m=(int)pow(2.0,EXPO*1.0)-1;
      /*int column=threadIdx.x;
      int row=threadIdx.y;*/
      int row=ind/m;
      int column=ind%m;

      int iloopstep=(int)pow(2.0,(EXPO-step)*1.0)-1;
      int h=(int)pow(2.0,(step-1)*1.0);
      int multiplier=(int)pow(2.0,step*1.0);
      int countHelper1=(int)pow(2.0,EXPO+1.0); 
      int countHelper2=(int)pow(2.0,EXPO-step+2);

      float* oldB;
      float* oldC;
 

      float* newB;
      float* newC;
      //float* newD;
    
      

     //this is to exchange which hold the previous value which hold the current value
      if(step%2==0)
      {
      	oldB=devicenewB;
      	oldC=devicenewC;
      	/*oldD=devicenewD;*/

      	newB=deviceB;
      	newC=deviceC;
     /* 	newD=deviceD;*/
      }
      else
      {
      	oldB=deviceB;
      	oldC=deviceC;
      /*	oldD=deviceD;*/
        
        newB=devicenewB;
        newC=devicenewC;
  /*      newD=devicenewD;*/
      }

/*    
     if(row==0&&column==0)
      {
           if(step==1)
      {
        printf("bb-0 \n");
        for(int i=0;i<m;i++)
        {
          for(int j=0;j<m;j++)
          {
            printf("%lf ",oldB[i*m+j]);
          }
          printf("\n");
        }
      }

       if(step==2)
      {
         printf("bb-1 \n");
        for(int i=0;i<m;i++)
        {
          for(int j=0;j<m;j++)
          {
            printf("%lf ",oldB[i*m+j]);
          }
          printf("\n");
        }
      }
      }*/
    

      //use the device value as old value and store the updated one in to the new value
      if(row<m && column<m) //so only the first 63 threads do work and the other one is hanging there
      {
		    float sumBB=0.0;
		    for(int k=0;k<m;k++)
		    {
		      sumBB=sumBB+oldB[row*m+k]*oldB[k*m+column];
		    }
		    float sumCC=0.0;
		    for(int k=0;k<m;k++)
		    {
		      sumCC=sumCC+oldC[row*m+k]*oldC[k*m+column];
		    }

		    //based on formula (5.4.2.15) on book
		    newB[row*m+column]=2*sumCC-sumBB;
		    newC[row*m+column]=sumCC;

		    //now calculate the new d and it needs to loop through i in each block
		    //look at the third formula on 5.4.2.15 on book
		    ///D[ith BLOCK][j thSTep ]=D[(2^(k+1)-2^(k-j+1)+i-j-1)*m+...]
		    if(column==0)
		    {
		    	//for calculate d we just need 63 tthreads but B and C we need 63*63 threads
		    	//so in step :step, each thread will work on the row th value in each block in that step,sicne there are 63 threads.
		    	for(int i=1;i<=iloopstep;i++)
		    {

		    	float sumCD1=0.0;
		    	for(int k=0;k<m;k++)
		    	{

		    		sumCD1=sumCD1+oldC[row*m+k]*deviceD[(countHelper1-countHelper2+i*2-1-step)*m+k];
		    	}

		    	float sumCD2=0.0;
		    	for(int k=0;k<m;k++)
		    	{
		    		sumCD2=sumCD2+oldC[row*m+k]*deviceD[(countHelper1-countHelper2+i*2+1-step)*m+k];
		    	}

		    	float sumBD=0.0;
		    	for(int k=0;k<m;k++)
		    	{
		           sumBD=sumBD+oldB[row*m+k]*deviceD[(countHelper1-countHelper2+i*2-step)*m+k];
		    	}

		    	deviceD[(int)((countHelper1-countHelper2/2+i-step-1)*m)+row]=sumCD1+sumCD2-sumBD;

           if(i==2&&step==1)
           {
            printf("row %d, index %d, %lf",row,(int)((countHelper1-countHelper2/2+i-step-1)*m)+row,deviceD[(int)((countHelper1-countHelper2/2+i-step-1)*m)+row]);

           }
          //printf("step %d,row: %d, index:%d dd1: %lf \n",step,row,(int)(countHelper1-countHelper2/2+i-step-1)*m+row,deviceD[(countHelper1-countHelper2/2+i-step-1)*m+row]);
		    	//printf("in cuda index %d value %lf: \n",(countHelper1-countHelper2/2+i-step-1)*m+row,deviceD[(countHelper1-countHelper2/2+i-step-1)*m+row]);
		    	//printf("gpu:%lf:",newD[(i*multiplier-1)*m+row]);
		    }

		    }
		    
        }
       //sync the thread before go to the next step.
        __syncthreads();

   /*     if(row==0&&column==0)s
        {
            for(int i=0;i<9;i++)
            {
              printf("%lf ",oldD[i]);	
            }
          printf("\n");	
        }*/

    }
//***************************begin of unblock version of cyclic reduction*********************************************************************************//
     __global__ void CalculatePArrayKernel(int step,int blockRow, int blockColumn,float* deviceA, float* deviceB, float* deviceC, float* deviceD)
    {
      int bx=blockIdx.x;
      int by=blockIdx.y;
      int tx=threadIdx.x;
      int ty=threadIdx.y;

      int helper11=pow(2.0,(EXPO+1)*1.0);
      int helper22=pow(2.0,(EXPO-step+1)*1.0);
      int helper44=pow(2.0,(EXPO-step+2)*1.0);
      int helper33=pow(2.0,EXPO*1.0)-1;
        //printf("step is running: %d \n",step);

     // if(helper3<pow(2.0,(EXPO-step)*1.0)-1)
        //--step 1 is special case.
     /*  if((tx!=(blockColumn-1))&&(ty!=(blockRow-1)))-----this is very important branch divergence happen here, need
     //to figure out how exactly cuda works!!
        /*****calcualte A******************/
        int helper1=helper11;
        int helper2=helper22;
        int helper4=helper44;
        int flag=0;//special for step1.
        if(step==1)
        {
            helper1=0;
            helper2=0;
            helper4=0;
            flag=1;
        }

        int helper3=ty*blockColumn+tx+1;
        if(helper3<=(pow(2.0,1.0*(EXPO-step))-1.0))
        {
        float ahelperfora1=deviceA[-step+helper1-helper4+2*(helper3)];
        float ahelperfora2=deviceA[-step+helper1-helper4+2*(helper3)-1];
        float bhelperfora1=deviceB[-step+helper1-helper4+2*(helper3)-1];
        deviceA[-1-step+helper1-helper2+helper3+flag*(1+helper33)]=-1*(ahelperfora1)*ahelperfora2/bhelperfora1;

        //*****calculate C******************/
        float chelperforc1=deviceC[-step+helper1-helper4+2*(helper3)];
        float chelperforc2=deviceC[-step+helper1-helper4+2*(helper3)+1];
        float bhelperforc1=deviceB[-step+helper1-helper4+2*(helper3)+1];
        deviceC[-1-step+helper1-helper2+helper3+flag*(1+helper33)]=-1*chelperforc1*chelperforc2/bhelperforc1;

        //calculate B***********************************************//
        float bhelperforb1=deviceB[-step+helper1-helper4+2*(helper3)];
        float bhelperforb2=deviceB[-step+helper1-helper4+2*(helper3)-1];
        float bhelperforb3=deviceB[-step+helper1-helper4+2*(helper3)+1];
        float ahelperforb1=deviceA[-step+helper1-helper4+2*(helper3)];
        float ahelperforb2=deviceA[-step+helper1-helper4+2*(helper3)+1];
        float chelperforb1=deviceC[-step+helper1-helper4+2*(helper3)-1];
        float chelperforb2=deviceC[-step+helper1-helper4+2*(helper3)];
        deviceB[-1-step+helper1-helper2+helper3+flag*(1+helper33)]=bhelperforb1-ahelperforb1/bhelperforb2*chelperforb1-chelperforb2/bhelperforb3*ahelperforb2;

        //calculate D***************************************************//
        float dhelperford1=deviceD[-step+helper1-helper4+2*(helper3)];
        float dhelperford2=deviceD[-step+helper1-helper4+2*(helper3)-1];
        float dhelperford3=deviceD[-step+helper1-helper4+2*(helper3)+1];
        float ahelperford1=deviceA[-step+helper1-helper4+2*(helper3)];
        float bhelperford1=deviceB[-step+helper1-helper4+2*(helper3)-1];
        float bhelperford2=deviceB[-step+helper1-helper4+2*(helper3)+1];
        float chelperford1=deviceC[-step+helper1-helper4+2*(helper3)];
        deviceD[-1-step+helper1-helper2+helper3+flag*(1+helper33)]=dhelperford1-ahelperford1/bhelperford1*dhelperford2-chelperford1/bhelperford2*dhelperford3;
    /*    for(int i=0;i<6;i++)
        {
        	//printf("cudab %lf \n",deviceB[i]);
        	printf("cudab %lf \n",deviceB[i]);
        }

        for(int i=0;i<6;i++)
        {
        	//printf("cudab %lf \n",deviceB[i]);
        	printf("cudad %lf \n",deviceD[i]);
        }*/
    }

        __syncthreads();
    }
    

        __global__ void BackwardKernel(int k,int blockRow, int blockColumn,float* deviceA, float* deviceB, float* deviceC, float* deviceD,float* deviceFinalX,float initialValue)
     {
      int bx1=blockIdx.x;
      int by1=blockIdx.y;
      int tx1=threadIdx.x;
      int ty1=threadIdx.y;
      //printf("inside of kernle %f \n",deviceFinalX[4]);

      int backhelper1=ty1*blockColumn+tx1+1;
      int backhelper2=2*backhelper1-1;//(int((2*backhelper1-1)*pow(2.0,1.0*(k-1))))/(int)(pow(2.0,(k-1)*1.0));
      int backhelper3=(int)pow(2.0,(EXPO+1)*1.0);
      int backhelper4=(int)pow(2.0,(EXPO-k+2)*1.0);


      int h=(int)(pow(2.0,1.0*(k-1)));

      float backhelperd=deviceD[-k+backhelper3-backhelper4+backhelper2];
      float backhelpera=deviceA[-k+backhelper3-backhelper4+backhelper2];
      float backhelperb=deviceB[-k+backhelper3-backhelper4+backhelper2];
      float backhelperc=deviceC[-k+backhelper3-backhelper4+backhelper2];

      int xindex1=backhelper2*pow(2.0,1.0*(k-1))-h;
      int xindex2=backhelper2*pow(2.0,1.0*(k-1))+h;

      //so thread i will be in charge of (2i-1)*2^(k-1) calculation
      //printf("%d ",int((2*backhelper1-1)*pow(2.0,1.0*(k-1))));
      deviceFinalX[(int)(backhelper2*pow(2.0,1.0*(k-1)))]=(backhelperd-backhelpera*deviceFinalX[xindex1]-backhelperc*deviceFinalX[xindex2])*1.0/backhelperb;

      __syncthreads();
     }
      
//***************************end of not block version of cyclic reduction*********************************************************************************//
    
    int main()
    {


      //matrix size will be 63*63 as our setup
      int m=pow(2,EXPO)-1;
      int loopH=pow(2,EXPO-1);
      int conHelp=4*loopH;
         

      //syntax will follow the  routine in the book
      float *B;
      float *C;
      float *D;
      float *X; //X to store the solution
      float *newB;
      float *newC;
 
      int b=1;
      int a=0;
      int maxBlockSize=16;


      //B and C share the same chuck length 
      int chunkLength=m*m;
      float delta=(b-a)*1.0/(m+1.0);
      float deltaSquare=delta*delta;
      int chunkSize=chunkLength*sizeof(float); 
      //need to store all the version of D, it will be 2^k-k-1 block and each block has m value
      int dLength=(pow(2,EXPO+1)-EXPO-2)*m;
      int dSize=dLength*sizeof(float);
     
     


      B=(float*)malloc(chunkSize);
      C=(float*)malloc(chunkSize);
      D=(float*)malloc(dSize);
      //this is to store the final answer
      X=(float*)malloc(chunkSize);
      newB=(float*)malloc(chunkSize);
      newC=(float*)malloc(chunkSize);
      //newD=(float*)malloc(dSize);

          
      //initilize B

      for(int i=0;i<m;i++)
      {
      	for(int j=0;j<m;j++)
      	{
      		B[i*m+j]=0.0;
      		C[i*m+j]=0.0;
      	}
      }
      

      for(int i=0;i<m;i++)
      {
      	B[i*m+i]=-4.0;
      	if(i!=0)
      	{
         B[i*m+i-1]=1.0;
      	}
      	if(i!=m-1)
      	{
      	 B[i*m+i+1]=1.0;;
      	}
      }
  

      //initilize C
      for(int i=0;i<m;i++)
      {
      	C[i*m+i]=1.0;
      } 
    
    //the first 2^k-1 will be the step 0 initial value
      for(int i=0;i<m;i++)
      {
       for(int j=0;j<m;j++)
       {
       /*	float x=(j+1)*delta;
       	float y=(i+1)*delta;*/
       	D[i*m+j]=deltaSquare;  //f(x,y) will be 1 here.
       	printf("dd block: %d %lf ",i,D[i*m+j]);
       }
        printf("\n");
      }
      //other value initilized to be 0 at the beginnig
      for(int i=m*m;i<dLength;i++)
      {
      	D[i]=0.0;
      }
     /* for(int i=0;i<dLength;i++)
      {
      	printf("dd %lf",D[i]);
      }*/

      //initilize x
      for(int i=0;i<m;i++)
      {
      	for(int j=0;j<m;j++)
      	{
      		X[i*m+j]=0.0; 
      	}
      }
      //printf("let test this2:\n");



     //begin timing here:
        clock_t begin,end;
        begin=clock();
      float *deviceB,*deviceC,*deviceD,*deviceX,*devicenewB,*devicenewC;
      hipMalloc((void**)&deviceB,chunkSize);
      hipMalloc((void**)&deviceC,chunkSize);
      hipMalloc((void**)&deviceD,dSize);
      hipMalloc((void**)&deviceX,chunkSize);
      hipMalloc((void**)&devicenewB,chunkSize);
      hipMalloc((void**)&devicenewC,chunkSize);
      //cudaMalloc((void**)&devicenewD,chunkSize);

      hipMemcpy(deviceB,B,chunkSize,hipMemcpyHostToDevice);  //store previous value
      hipMemcpy(deviceC,C,chunkSize,hipMemcpyHostToDevice);
      hipMemcpy(deviceD,D,dSize,hipMemcpyHostToDevice);
      hipMemcpy(deviceX,X,chunkSize,hipMemcpyHostToDevice);
      hipMemcpy(devicenewB,newB,chunkSize,hipMemcpyHostToDevice);  //store current stored value
      hipMemcpy(devicenewC,newC,chunkSize,hipMemcpyHostToDevice);
     // cudaMemcpy(devicenewD,newD,chunkSize,cudaMemcpyHostToDevice);
        
        //int gridSize=((m+1)/maxBlockSize)*((m+1)/maxBlockSize); //gridSize for this problem will be 16
         	//dim3 dimGrid(1,gridSize)
      	dim3 dimGrid(1,32);  //since the maximum process we are going to use will be 63*63

        int blockRow=maxBlockSize;//pow(2,EXPO/2); //here will be 8 and 8
        int blockColumn=maxBlockSize;//pow(2,EXPO/2); //here will be 8 and 8
        dim3 dimBlock(blockColumn,blockRow);

      for(int step=1;step<EXPO;step++)
      {
      	//so the logic here will be if step is odd, then it use B,C,D as the old value and new value into newB, newC,newD.
      	//if step is even, then use newB,newC,newD as the old value and put the update value into B,C,D.
      
        //here is to calculate the d(2^(k-1))(K-1) in the book
        CalculateTheD<<<dimGrid,dimBlock>>>(step,deviceB,deviceC,deviceD,deviceX,devicenewB,devicenewC);
      }
      hipDeviceSynchronize();
      //the last step here will be 5 so it will write its new value into newB, newC, newD. 
      hipMemcpy(D,deviceD,dSize,hipMemcpyDeviceToHost);
    /*  for (int i=0;i<m;i++)
      {
      	if(i%8==0)
      	{
      		printf("\n");
      	}
      	printf("%lf ",newD[3+i]);
      }*/
      //release some of the memory
      for(int i=0;i<dLength;i++)
      {
        if(i%m==0)
        {
          printf("\n");
        }
        printf("dha:%lf ",D[i]);
      }
      hipFree(deviceB);
      hipFree(deviceC);
      //cudaFree(deviceD);
      hipFree(devicenewB);
      hipFree(devicenewC);
      //cudaFree(devicenewD);
      
      free(B);
      free(C);
      //free(D);
      free(newB);
      free(newC);
      //free(newD);

      /*cudaMemcpy(deviceB,B,chunkSize,cudaMemcpyHostToDevice);
      cudaMemcpy(deviceC,C,chunkSize,cudaMemcpyHostToDevice);*/

      //z will D in the not block version of cyclic reduction, ZA, ZB, ZC will corresponding to A, B and C
      float *Z,*ZA,*ZB,*ZC,*FinalX;
      int finalLengthX=(int)pow(2,EXPO)+1;
      int chunkLengthZ=(pow(2,EXPO)-1)*2+1;
      int zSize=chunkLengthZ*sizeof(float);
      
      Z=(float*)malloc(zSize);
      ZA=(float*)malloc(zSize);
      ZB=(float*)malloc(zSize);
      ZC=(float*)malloc(zSize);
      FinalX=(float*)malloc(finalLengthX*sizeof(float));  //the first and last one should be know by the boundary condition

      float *deviceZ,*deviceZA,*deviceZB, *deviceZC,*deviceFinalX;
	    hipMalloc((void**)&deviceZ,zSize);
	    hipMalloc((void**)&deviceZA,zSize);
	    hipMalloc((void**)&deviceZB,zSize);
	    hipMalloc((void**)&deviceZC,zSize);
	    hipMalloc((void**)&deviceFinalX,finalLengthX*sizeof(float));


      //set up the matrix step 
      for(int j=1;j<=loopH;j++)
      {
      	//for each j, za,zb,zc all going to be different
      	ZA[0]=0;

      	for(int i=1;i<m;i++)
      	{
      		ZA[i]=1.0;
      	}
      	//else will be 0,since it has been seperate to half and half
        for(int i=m;i<chunkLengthZ;i++)
        {
          ZA[i]=0;
        }

        for(int i=0;i<m;i++)
        {
          ZB[i]=-4.0+2*cos((2.0*j-1.0)/(m+1.0)*PI);
          //printf("zb:%f \n",ZB[i]);
        }
        for(int i=m;i<chunkLengthZ;i++)
        {
          ZB[i]=0;
        }

        ZC[m-1]=0;
        for(int i=0;i<m-1;i++)
        {
            ZC[i]=1.0;
        }
        for(int i=m;i<chunkLengthZ;i++)
        {
          ZC[i]=0;
        }

        //if it is the first step z will be from d, otherwise, z will be from the previous solution of x
        if(j==1)
        {
        	for(int i=0;i<m;i++)
        	{
        		/*Z[i]=newD[(loopH-1)*m+i]*(-1.0);
        		printf("this original one being called? %lf \n",Z[i]);*/
        		Z[i]=D[((int)pow(2.0,EXPO+1.0)-3-EXPO)*m+i]*(-1.0);
				//printf("z value: %lf \n",Z[i]);
        	}
        	 for(int i=m;i<chunkLengthZ;i++)
		        {
		          Z[i]=0;
		        }
        }
        else
        {
        	for(int i=0;i<m;i++)
        	{
             //to do this will be x
        		Z[i]=FinalX[i+1];
        		//printf("does this ever called? %lf \n",Z[i]);
        	}
        	 for(int i=m;i<chunkLengthZ;i++)
		        {
		          Z[i]=0;
		        }
        }

        //now need to call the cyclic function to find the solution of x

        hipMemcpy(deviceZ,Z,zSize,hipMemcpyHostToDevice);
        hipMemcpy(deviceZA,ZA,zSize,hipMemcpyHostToDevice);
        hipMemcpy(deviceZB,ZB,zSize,hipMemcpyHostToDevice);
        hipMemcpy(deviceZC,ZC,zSize,hipMemcpyHostToDevice);

        for(int j=1;j<EXPO;j++)
        {
        //the lock size should change, the first step it will need 2^(n-j)-1, so first step will be 3 if n=3
        dim3 dimGrid(1,1);
        int blockRow=pow(2,(EXPO-j)/2);
        //printf("blockrow is :%d \n",blockRow);
        int blockColumn=pow(2,EXPO-j-(EXPO-j)/2);
        //printf("blockColumn is :%d \n",blockColumn);
        dim3 dimBlock(blockColumn,blockRow);
          //in each step the processor being used should decrease should be 2^(n-j)-1 in jth step
        CalculatePArrayKernel<<<dimGrid,dimBlock>>>(j,blockRow,blockColumn,deviceZA,deviceZB,deviceZC,deviceZ);
         hipDeviceSynchronize(); //cpu will wait until cuda finish the job, this is such important function!

        }

          //backward
        //copy the device vector to host
        //cudaMemcpy(ZA,deviceZA,chunkSize,cudaMemcpyDeviceToHost);
       // sleep(20);
       
        hipMemcpy(ZB,deviceZB,zSize,hipMemcpyDeviceToHost);
        /*for(int i=0;i<2*m;i++)
        {
        	printf("zbresult:%lf \n",ZB[i]);
        }*/
        //cudaMemcpy(C,deviceC,chunkSize,cudaMemcpyDeviceToHost);
        hipMemcpy(Z,deviceZ,zSize,hipMemcpyDeviceToHost);
        int lastIndex=(int)pow(2,EXPO+1)-EXPO-3;
        float initialValue=Z[lastIndex]/ZB[lastIndex];
        //printf("initial value: %lf \n",initialValue);
        FinalX[0]=0;
        FinalX[(int)pow(2,EXPO-1)]=initialValue;
        //printf("the value in the middle is: %f and this suppose to close to 0.5 when n goes big! \n",FinalX[(int)pow(2,EXPO-1)]);

        hipMemcpy(deviceFinalX,FinalX,finalLengthX*sizeof(float),hipMemcpyHostToDevice);
        for(int k=EXPO-1;k>=1;k--)
        {
          //so the most one will use 2^(n-k) variable will be covered!
        dim3 dimGrid(1,1);
        int blockRow=pow(2,(EXPO-k)/2);
        int blockColumn=pow(2,EXPO-k-(EXPO-k)/2);
        dim3  dimBlock(blockColumn,blockRow);
        
        BackwardKernel<<<dimGrid,dimBlock>>>(k,blockRow,blockColumn,deviceZA,deviceZB,deviceZC,deviceZ,deviceFinalX,initialValue);
        hipDeviceSynchronize();
        }
         

        hipMemcpy(FinalX,deviceFinalX,finalLengthX*sizeof(float),hipMemcpyDeviceToHost);
      }

      printf("\n final result for x(2^(k-1) block which should have %d values in it:\n",m);
       for (int i=1;i<finalLengthX-1;i++)
      {
       //this will we stored in X the 2^(k-1) the block.
        X[(loopH-1)*m+i-1]=FinalX[i];
      	printf("index: %d, %lf ",(loopH-1)*m+i-1,FinalX[i]);
      }
      printf("\n \n");
    
    //now need to do the block wise backsubstitution based on the formula of 5.4.2.17
     for(int step=EXPO-1;step>=1;step--)
     {
      //based on formula 5.4.2.30
     	//ok this is loop trhough the matrix in 5.4.2.17
     	int help1=pow(2,EXPO-step);
     	int localloopH=pow(2,step-1);
     	int thetaHelper=pow(2,step);
     	//inside of each step, you have this much of sybmatrix to solve
     	for(int backStep=1;backStep<=help1;backStep++)
     	{
     		//factorize B(step-1)
     		//first and last one need to be treat specially, C[j-1] will be just identity matrix here

     	
     	   	//************************************************************//
     	   	                 //this is to loop through the factorization
						     for(int j=1;j<=localloopH;j++)
						      {
						      	//for each j, za,zb,zc all going to be different
						      	ZA[0]=0;

						      	for(int i=1;i<m;i++)
						      	{
						      		ZA[i]=1.0;
						      	}
						      	//else will be 0,since it has been seperate to half and half
						        for(int i=m;i<chunkLengthZ;i++)
						        {
						          ZA[i]=0;
						        }

						        for(int i=0;i<m;i++)
						        {
						          ZB[i]=-4.0+2*cos((2.0*j-1.0)/(thetaHelper)*PI);
						          printf("zb:%f step: %d\n",ZB[i],step);
						        }
						        for(int i=m;i<chunkLengthZ;i++)
						        {
						          ZB[i]=0;
						        }

						        ZC[m-1]=0;
						        for(int i=0;i<m-1;i++)
						        {
						            ZC[i]=1.0;
						        }
						        for(int i=m;i<chunkLengthZ;i++)
						        {
						          ZC[i]=0;
						        }
						        //if it is the first step z will be from d, otherwise, z will be from the previous solution of x
						        if(j==1)
						        {
						        	//the first backsetp and last backstep will be special
						        	if(backStep==1)
						        	{
                                      //teh first d will be d(t-s)(j-1)-c(j-1)x(t)
								        		for(int i=0;i<m;i++)
								        	{
								        		//Z[i]=D[(loopH-1)*m+i]*(-1.0);
								        		//printf("this original one being called? %lf \n",Z[i]);
								        		Z[i]=(D[(conHelp-4*help1-step+1)*m+i]-X[(thetaHelper-1)*m+i])*(-1.0);

								        	}
								        	 for(int i=m;i<chunkLengthZ;i++)
										        {
										          Z[i]=0;
										        }
						        	}
						        	else if(backStep==help1)
						        	{
					        				for(int i=0;i<m;i++)
							        	{
							        		//Z[i]=D[(loopH-1)*m+i]*(-1.0);
							        		//printf("this original one being called? %lf \n",Z[i]);
							        		Z[i]=(D[(conHelp-2*help1-1-step)*m+i]-X[(conHelp/2-thetaHelper-1)*m+i])*(-1.0);

							        	}
							        	 for(int i=m;i<chunkLengthZ;i++)
									        {
									          Z[i]=0;
									        }

						        	}
						        	else //this is at the middle bakcstep
						        	{
						        			for(int i=0;i<m;i++)
							        	{
							        		//Z[i]=D[(loopH-1)*m+i]*(-1.0);
							        		//printf("this original one being called? %lf \n",Z[i]);
							        		Z[i]=(D[(2*backStep-1-step+conHelp-4*help1)*m+i]-X[(backStep*thetaHelper-1)*m+i]-X[((backStep-1)*thetaHelper-1)*m+i])*(-1.0);
							        	}
							        	 for(int i=m;i<chunkLengthZ;i++)
									        {
									          Z[i]=0;
									        }

						        	}
						        }
						        else
						        {
						        	for(int i=0;i<m;i++)
						        	{
						             //to do this will be x
						        		Z[i]=FinalX[i+1];
						        		//printf("does this ever called? %lf \n",Z[i]);
						        	}
						        	 for(int i=m;i<chunkLengthZ;i++)
								        {
								          Z[i]=0;
								        }
						        }

						        //now need to call the cyclic function to find the solution of x

						        hipMemcpy(deviceZ,Z,zSize,hipMemcpyHostToDevice);
						        hipMemcpy(deviceZA,ZA,zSize,hipMemcpyHostToDevice);
						        hipMemcpy(deviceZB,ZB,zSize,hipMemcpyHostToDevice);
						        hipMemcpy(deviceZC,ZC,zSize,hipMemcpyHostToDevice);

						        for(int j=1;j<EXPO;j++)
						        {
						        //the lock size should change, the first step it will need 2^(n-j)-1, so first step will be 3 if n=3
						        dim3 dimGrid(1,1);
						        int blockRow=pow(2,(EXPO-j)/2);
						        //printf("blockrow is :%d \n",blockRow);
						        int blockColumn=pow(2,EXPO-j-(EXPO-j)/2);
						        //printf("blockColumn is :%d \n",blockColumn);
						        dim3 dimBlock(blockColumn,blockRow);
						          //in each step the processor being used should decrease should be 2^(n-j)-1 in jth step
						        CalculatePArrayKernel<<<dimGrid,dimBlock>>>(j,blockRow,blockColumn,deviceZA,deviceZB,deviceZC,deviceZ);
						        hipDeviceSynchronize(); //cpu will wait until cuda finish the job, this is such important function!

						        }

						          //backward
						        //copy the device vector to host
						        //cudaMemcpy(ZA,deviceZA,chunkSize,cudaMemcpyDeviceToHost);
						       // sleep(20);
						        
						        hipMemcpy(ZB,deviceZB,zSize,hipMemcpyDeviceToHost);
						     /*   for(int i=0;i<2*m;i++)
						        {
						        	printf("zbresult:%lf \n",ZB[i]);
						        }*/
						        //cudaMemcpy(C,deviceC,chunkSize,cudaMemcpyDeviceToHost);
						        hipMemcpy(Z,deviceZ,zSize,hipMemcpyDeviceToHost);
						        int lastIndex=(int)pow(2,EXPO+1)-EXPO-3;
						        float initialValue=Z[lastIndex]/ZB[lastIndex];
						        //printf("initial value: %lf \n",initialValue);
						        FinalX[0]=0;
						        FinalX[(int)pow(2,EXPO-1)]=initialValue;
						        //printf("the value in the middle is: %f and this suppose to close to 0.5 when n goes big! \n",FinalX[(int)pow(2,EXPO-1)]);

						        hipMemcpy(deviceFinalX,FinalX,finalLengthX*sizeof(float),hipMemcpyHostToDevice);
						        for(int k=EXPO-1;k>=1;k--)
						        {
						          //so the most one will use 2^(n-k) variable will be covered!
						        dim3 dimGrid(1,1);
						        int blockRow=pow(2,(EXPO-k)/2);
						        int blockColumn=pow(2,EXPO-k-(EXPO-k)/2);
						        dim3  dimBlock(blockColumn,blockRow);
						        
						        BackwardKernel<<<dimGrid,dimBlock>>>(k,blockRow,blockColumn,deviceZA,deviceZB,deviceZC,deviceZ,deviceFinalX,initialValue);
						          hipDeviceSynchronize();
						           
						        }

                               hipMemcpy(FinalX,deviceFinalX,finalLengthX*sizeof(float),hipMemcpyDeviceToHost);

						      }
                              printf("\n");
						      for(int i=1;i<finalLengthX-1;i++)
						       {
						       	X[((2*backStep-1)*localloopH-1)*m+i-1]=FinalX[i];
                                //printf("%lf \n",FinalX[i]);
                                if(backStep==1)
                                {
                                	printf("test [%d],%lf \n",((2*backStep-1)*localloopH-1)*m+i-1,FinalX[i]);
                                }
						       }


     	   	//************************************************************//
     	}

     }

     printf("\n");
       for (int i=0;i<m*m;i++)
      {
       //this will we stored in X the 2^(k-1) the block.
      	if(m%31==0)
      	{
      		printf("\n");
      	}
        printf("[%d]:%lf ",i,X[i]);
      }
         double time_spent;
        end=clock();
       time_spent=(double)(end-begin)/CLOCKS_PER_SEC;
     
     printf("\n time spent to calcuate x with partition [0,1] into %d intervals:%lf seconds \n",m+1,time_spent);  
  }






	.text
	.file	"new.hip"
	.globl	_Z28__device_stub__CalculateTheDiPfS_S_S_S_S_ # -- Begin function _Z28__device_stub__CalculateTheDiPfS_S_S_S_S_
	.type	_Z28__device_stub__CalculateTheDiPfS_S_S_S_S_,@function
_Z28__device_stub__CalculateTheDiPfS_S_S_S_S_: # @_Z28__device_stub__CalculateTheDiPfS_S_S_S_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	4(%rsp), %rax
	movl	%edi, (%rax)
	leaq	56(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	48(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	40(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	32(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	24(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z13CalculateTheDiPfS_S_S_S_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z28__device_stub__CalculateTheDiPfS_S_S_S_S_, .Lfunc_end0-_Z28__device_stub__CalculateTheDiPfS_S_S_S_S_
	.cfi_endproc
                                        # -- End function
	.globl	_Z36__device_stub__CalculatePArrayKerneliiiPfS_S_S_ # -- Begin function _Z36__device_stub__CalculatePArrayKerneliiiPfS_S_S_
	.type	_Z36__device_stub__CalculatePArrayKerneliiiPfS_S_S_,@function
_Z36__device_stub__CalculatePArrayKerneliiiPfS_S_S_: # @_Z36__device_stub__CalculatePArrayKerneliiiPfS_S_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	20(%rsp), %rax
	movl	%edi, (%rax)
	leaq	16(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	56(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	48(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	40(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z21CalculatePArrayKerneliiiPfS_S_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z36__device_stub__CalculatePArrayKerneliiiPfS_S_S_, .Lfunc_end1-_Z36__device_stub__CalculatePArrayKerneliiiPfS_S_S_
	.cfi_endproc
                                        # -- End function
	.globl	_Z29__device_stub__BackwardKerneliiiPfS_S_S_S_f # -- Begin function _Z29__device_stub__BackwardKerneliiiPfS_S_S_S_f
	.type	_Z29__device_stub__BackwardKerneliiiPfS_S_S_S_f,@function
_Z29__device_stub__BackwardKerneliiiPfS_S_S_S_f: # @_Z29__device_stub__BackwardKerneliiiPfS_S_S_S_f
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$176, %rsp
	.cfi_def_cfa_offset 224
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	20(%rsp), %rax
	movl	%edi, (%rax)
	leaq	16(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	56(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	48(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	40(%rsp), %r8
	movq	%r9, (%r8)
	leaq	8(%rsp), %r9
	movss	%xmm0, (%r9)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	224(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	232(%rsp), %rax
	movq	%rax, 56(%rbx)
	movq	%r9, 64(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z14BackwardKerneliiiPfS_S_S_S_f, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$192, %rsp
	.cfi_adjust_cfa_offset -192
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z29__device_stub__BackwardKerneliiiPfS_S_S_S_f, .Lfunc_end2-_Z29__device_stub__BackwardKerneliiiPfS_S_S_S_f
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0                          # -- Begin function main
.LCPI3_0:
	.quad	0x3f50000000000000              # double 9.765625E-4
.LCPI3_1:
	.quad	0x3ff0000000000000              # double 1
.LCPI3_2:
	.quad	0xbff0000000000000              # double -1
.LCPI3_3:
	.quad	0x3fa0000000000000              # double 0.03125
.LCPI3_4:
	.quad	0x400921fb53c8d4f1              # double 3.1415926500000002
.LCPI3_5:
	.quad	0xc010000000000000              # double -4
.LCPI3_7:
	.quad	0x412e848000000000              # double 1.0E+6
	.section	.rodata.cst16,"aM",@progbits,16
	.p2align	4, 0x0
.LCPI3_6:
	.long	0x80000000                      # float -0
	.long	0x80000000                      # float -0
	.long	0x80000000                      # float -0
	.long	0x80000000                      # float -0
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:                                # %.preheader651.preheader
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$376, %rsp                      # imm = 0x178
	.cfi_def_cfa_offset 432
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	$1, %edi
	movl	$3844, %esi                     # imm = 0xF04
	callq	calloc@PLT
	movq	%rax, %rbx
	movl	$1, %edi
	movl	$3844, %esi                     # imm = 0xF04
	callq	calloc@PLT
	movq	%rax, %r14
	movl	$7068, %edi                     # imm = 0x1B9C
	callq	malloc
	movq	%rax, 48(%rsp)                  # 8-byte Spill
	movl	$3844, %edi                     # imm = 0xF04
	callq	malloc
	movq	%rax, 56(%rsp)                  # 8-byte Spill
	movl	$3844, %edi                     # imm = 0xF04
	callq	malloc
	movq	%rax, %r15
	movl	$3844, %edi                     # imm = 0xF04
	callq	malloc
	movq	%rax, 16(%rsp)                  # 8-byte Spill
	xorl	%eax, %eax
.LBB3_1:                                # %.preheader651
                                        # =>This Inner Loop Header: Depth=1
	movl	$-1065353216, (%rbx,%rax)       # imm = 0xC0800000
	testq	%rax, %rax
	je	.LBB3_79
# %bb.2:                                #   in Loop: Header=BB3_1 Depth=1
	movl	$1065353216, -4(%rbx,%rax)      # imm = 0x3F800000
	cmpq	$3840, %rax                     # imm = 0xF00
	je	.LBB3_3
.LBB3_79:                               #   in Loop: Header=BB3_1 Depth=1
	movl	$1065353216, 4(%rbx,%rax)       # imm = 0x3F800000
	subq	$-128, %rax
	jmp	.LBB3_1
.LBB3_3:                                # %.preheader650.preheader
	xorl	%eax, %eax
.LBB3_4:                                # %.preheader650
                                        # =>This Inner Loop Header: Depth=1
	movl	$1065353216, (%r14,%rax)        # imm = 0x3F800000
	subq	$-128, %rax
	cmpq	$3968, %rax                     # imm = 0xF80
	jne	.LBB3_4
# %bb.5:                                # %.preheader648.preheader
	movq	%r15, 24(%rsp)                  # 8-byte Spill
	xorl	%r15d, %r15d
	movq	48(%rsp), %r12                  # 8-byte Reload
.LBB3_6:                                # %.preheader648
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB3_7 Depth 2
	xorl	%r13d, %r13d
.LBB3_7:                                #   Parent Loop BB3_6 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movl	$981467136, (%r12,%r13,4)       # imm = 0x3A800000
	movl	$.L.str, %edi
	movl	%r15d, %esi
	movsd	.LCPI3_0(%rip), %xmm0           # xmm0 = mem[0],zero
	movb	$1, %al
	callq	printf
	incq	%r13
	cmpq	$31, %r13
	jne	.LBB3_7
# %bb.8:                                #   in Loop: Header=BB3_6 Depth=1
	movl	$10, %edi
	callq	putchar@PLT
	incq	%r15
	addq	$124, %r12
	cmpq	$31, %r15
	jne	.LBB3_6
# %bb.9:                                # %.preheader647.preheader
	movq	48(%rsp), %r12                  # 8-byte Reload
	leaq	3844(%r12), %rdi
	movl	$3224, %edx                     # imm = 0xC98
	xorl	%esi, %esi
	callq	memset@PLT
	movl	$3844, %edx                     # imm = 0xF04
	movq	56(%rsp), %r13                  # 8-byte Reload
	movq	%r13, %rdi
	xorl	%esi, %esi
	callq	memset@PLT
	callq	clock
	movq	%rax, 264(%rsp)                 # 8-byte Spill
	leaq	256(%rsp), %rbp
	movl	$3844, %esi                     # imm = 0xF04
	movq	%rbp, %rdi
	callq	hipMalloc
	leaq	248(%rsp), %r15
	movl	$3844, %esi                     # imm = 0xF04
	movq	%r15, %rdi
	callq	hipMalloc
	leaq	152(%rsp), %rdi
	movl	$7068, %esi                     # imm = 0x1B9C
	callq	hipMalloc
	leaq	240(%rsp), %rdi
	movl	$3844, %esi                     # imm = 0xF04
	callq	hipMalloc
	leaq	144(%rsp), %rdi
	movl	$3844, %esi                     # imm = 0xF04
	callq	hipMalloc
	leaq	136(%rsp), %rdi
	movl	$3844, %esi                     # imm = 0xF04
	callq	hipMalloc
	movq	(%rbp), %rdi
	movl	$1, %ebp
	movl	$3844, %edx                     # imm = 0xF04
	movq	%rbx, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%r15), %rdi
	movl	$3844, %edx                     # imm = 0xF04
	movq	%r14, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	152(%rsp), %rax
	movq	(%rax), %rdi
	movl	$7068, %edx                     # imm = 0x1B9C
	movq	%r12, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	240(%rsp), %rax
	movq	(%rax), %rdi
	movl	$3844, %edx                     # imm = 0xF04
	movq	%r13, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	144(%rsp), %rax
	movq	(%rax), %rdi
	movl	$3844, %edx                     # imm = 0xF04
	movq	24(%rsp), %r13                  # 8-byte Reload
	movq	%r13, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	136(%rsp), %rax
	movq	(%rax), %rdi
	movl	$3844, %edx                     # imm = 0xF04
	movq	16(%rsp), %rsi                  # 8-byte Reload
	movl	$1, %ecx
	callq	hipMemcpy
	movabsq	$137438953473, %r15             # imm = 0x2000000001
	movabsq	$68719476752, %r12              # imm = 0x1000000010
.LBB3_10:                               # =>This Inner Loop Header: Depth=1
	movq	%r15, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB3_12
# %bb.11:                               #   in Loop: Header=BB3_10 Depth=1
	movq	256(%rsp), %rsi
	movq	248(%rsp), %rdx
	movq	152(%rsp), %rcx
	movq	240(%rsp), %r8
	movq	144(%rsp), %r9
	movq	136(%rsp), %rax
	movq	%rax, (%rsp)
	movl	%ebp, %edi
	callq	_Z28__device_stub__CalculateTheDiPfS_S_S_S_S_
.LBB3_12:                               #   in Loop: Header=BB3_10 Depth=1
	incl	%ebp
	cmpl	$5, %ebp
	jne	.LBB3_10
# %bb.13:
	callq	hipDeviceSynchronize
	movq	152(%rsp), %rsi
	movl	$7068, %edx                     # imm = 0x1B9C
	movq	48(%rsp), %rdi                  # 8-byte Reload
	movl	$2, %ecx
	callq	hipMemcpy
	movq	$-7068, %r15                    # imm = 0xE464
	xorl	%ebp, %ebp
	xorl	%r12d, %r12d
.LBB3_14:                               # =>This Inner Loop Header: Depth=1
	movl	%ebp, %eax
	imulq	$138547333, %rax, %rax          # imm = 0x8421085
	shrq	$32, %rax
	movl	%ebp, %ecx
	subl	%eax, %ecx
	shrl	%ecx
	addl	%eax, %ecx
	shrl	$4, %ecx
	movl	%ecx, %eax
	shll	$5, %eax
	subl	%ecx, %eax
	addl	%r12d, %eax
	jne	.LBB3_16
# %bb.15:                               #   in Loop: Header=BB3_14 Depth=1
	movl	$10, %edi
	callq	putchar@PLT
.LBB3_16:                               #   in Loop: Header=BB3_14 Depth=1
	movq	48(%rsp), %rax                  # 8-byte Reload
	xorps	%xmm0, %xmm0
	cvtss2sd	7068(%rax,%r15), %xmm0
	movl	$.L.str.2, %edi
	movb	$1, %al
	callq	printf
	decl	%r12d
	incl	%ebp
	addq	$4, %r15
	jne	.LBB3_14
# %bb.17:
	movq	256(%rsp), %rdi
	callq	hipFree
	movq	248(%rsp), %rdi
	callq	hipFree
	movq	144(%rsp), %rdi
	callq	hipFree
	movq	136(%rsp), %rdi
	callq	hipFree
	movq	%rbx, %rdi
	callq	free
	movq	%r14, %rdi
	callq	free
	movq	%r13, %rdi
	callq	free
	movq	16(%rsp), %rdi                  # 8-byte Reload
	callq	free
	movl	$252, %edi
	callq	malloc
	movq	%rax, %r14
	movl	$252, %edi
	callq	malloc
	movq	%rax, %r12
	movl	$252, %edi
	callq	malloc
	movq	%rax, %r15
	movl	$252, %edi
	callq	malloc
	movq	%rax, %rbp
	movl	$132, %edi
	callq	malloc
	movq	%rax, %r13
	leaq	40(%rsp), %rdi
	movl	$252, %esi
	callq	hipMalloc
	leaq	80(%rsp), %rdi
	movl	$252, %esi
	callq	hipMalloc
	leaq	32(%rsp), %rdi
	movl	$252, %esi
	callq	hipMalloc
	leaq	72(%rsp), %rdi
	movl	$252, %esi
	callq	hipMalloc
	leaq	64(%rsp), %rdi
	movl	$132, %esi
	callq	hipMalloc
	movq	%r12, %rax
	addq	$124, %rax
	movq	%rax, 224(%rsp)                 # 8-byte Spill
	movq	%r15, %rax
	addq	$124, %rax
	movq	%rax, 216(%rsp)                 # 8-byte Spill
	movq	%rbp, %rax
	addq	$124, %rax
	movq	%rax, 208(%rsp)                 # 8-byte Spill
	movq	%r13, %rax
	addq	$4, %rax
	movq	%rax, 192(%rsp)                 # 8-byte Spill
	movq	%r14, %rax
	addq	$124, %rax
	movq	%rax, 200(%rsp)                 # 8-byte Spill
	movl	$1, 24(%rsp)                    # 4-byte Folded Spill
	movsd	.LCPI3_1(%rip), %xmm0           # xmm0 = mem[0],zero
	xorps	%xmm1, %xmm1
	movq	%r14, 128(%rsp)                 # 8-byte Spill
	movq	%r12, 232(%rsp)                 # 8-byte Spill
	movq	%rbp, 120(%rsp)                 # 8-byte Spill
	movq	%r13, 112(%rsp)                 # 8-byte Spill
.LBB3_18:                               # =>This Loop Header: Depth=1
                                        #     Child Loop BB3_19 Depth 2
                                        #     Child Loop BB3_21 Depth 2
                                        #     Child Loop BB3_23 Depth 2
                                        #     Child Loop BB3_26 Depth 2
                                        #     Child Loop BB3_28 Depth 2
                                        #     Child Loop BB3_32 Depth 2
	movl	$0, (%r12)
	movl	$1, %eax
.LBB3_19:                               #   Parent Loop BB3_18 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movl	$1065353216, (%r12,%rax,4)      # imm = 0x3F800000
	incq	%rax
	cmpq	$31, %rax
	jne	.LBB3_19
# %bb.20:                               # %.preheader644.preheader
                                        #   in Loop: Header=BB3_18 Depth=1
	movq	224(%rsp), %rax                 # 8-byte Reload
	movups	%xmm1, 112(%rax)
	movups	%xmm1, 96(%rax)
	movups	%xmm1, 80(%rax)
	movups	%xmm1, 64(%rax)
	movups	%xmm1, 48(%rax)
	movups	%xmm1, 32(%rax)
	movups	%xmm1, 16(%rax)
	movups	%xmm1, (%rax)
	movsd	%xmm0, 88(%rsp)                 # 8-byte Spill
	addsd	%xmm0, %xmm0
	addsd	.LCPI3_2(%rip), %xmm0
	mulsd	.LCPI3_3(%rip), %xmm0
	mulsd	.LCPI3_4(%rip), %xmm0
	movsd	%xmm0, 16(%rsp)                 # 8-byte Spill
	xorl	%ebx, %ebx
.LBB3_21:                               #   Parent Loop BB3_18 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movsd	16(%rsp), %xmm0                 # 8-byte Reload
                                        # xmm0 = mem[0],zero
	callq	cos
	addsd	%xmm0, %xmm0
	addsd	.LCPI3_5(%rip), %xmm0
	cvtsd2ss	%xmm0, %xmm0
	movss	%xmm0, (%r15,%rbx,4)
	incq	%rbx
	cmpq	$31, %rbx
	jne	.LBB3_21
# %bb.22:                               # %.preheader642.preheader
                                        #   in Loop: Header=BB3_18 Depth=1
	movq	216(%rsp), %rax                 # 8-byte Reload
	xorps	%xmm2, %xmm2
	movups	%xmm2, 112(%rax)
	movups	%xmm2, 96(%rax)
	movups	%xmm2, 80(%rax)
	movups	%xmm2, 64(%rax)
	movups	%xmm2, 48(%rax)
	movups	%xmm2, 32(%rax)
	movups	%xmm2, 16(%rax)
	movups	%xmm2, (%rax)
	movl	$0, 120(%rbp)
	xorl	%eax, %eax
.LBB3_23:                               #   Parent Loop BB3_18 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movl	$1065353216, (%rbp,%rax,4)      # imm = 0x3F800000
	incq	%rax
	cmpq	$30, %rax
	jne	.LBB3_23
# %bb.24:                               # %.preheader641.preheader
                                        #   in Loop: Header=BB3_18 Depth=1
	movq	208(%rsp), %rax                 # 8-byte Reload
	movups	%xmm2, 112(%rax)
	movups	%xmm2, 96(%rax)
	movups	%xmm2, 80(%rax)
	movups	%xmm2, 64(%rax)
	movups	%xmm2, 48(%rax)
	movups	%xmm2, 32(%rax)
	movups	%xmm2, 16(%rax)
	movups	%xmm2, (%rax)
	cmpl	$1, 24(%rsp)                    # 4-byte Folded Reload
	movq	48(%rsp), %rcx                  # 8-byte Reload
	movaps	.LCPI3_6(%rip), %xmm1           # xmm1 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0]
	jne	.LBB3_80
# %bb.25:                               # %.preheader637.preheader
                                        #   in Loop: Header=BB3_18 Depth=1
	xorl	%eax, %eax
.LBB3_26:                               # %.preheader637
                                        #   Parent Loop BB3_18 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movss	6944(%rcx,%rax,4), %xmm0        # xmm0 = mem[0],zero,zero,zero
	xorps	%xmm1, %xmm0
	movss	%xmm0, (%r14,%rax,4)
	incq	%rax
	cmpq	$31, %rax
	jne	.LBB3_26
	jmp	.LBB3_27
.LBB3_80:                               # %.preheader640.preheader
                                        #   in Loop: Header=BB3_18 Depth=1
	movl	$31, %ecx
	movq	%r14, %rdi
	movq	192(%rsp), %rsi                 # 8-byte Reload
	rep;movsl (%rsi), %es:(%rdi)
.LBB3_27:                               # %.loopexit636
                                        #   in Loop: Header=BB3_18 Depth=1
	movq	200(%rsp), %rax                 # 8-byte Reload
	movups	%xmm2, 112(%rax)
	movups	%xmm2, 96(%rax)
	movups	%xmm2, 80(%rax)
	movups	%xmm2, 64(%rax)
	movups	%xmm2, 48(%rax)
	movups	%xmm2, 32(%rax)
	movups	%xmm2, 16(%rax)
	movups	%xmm2, (%rax)
	movq	40(%rsp), %rdi
	movl	$1, %ebx
	movl	$252, %edx
	movq	%r14, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	80(%rsp), %rdi
	movl	$252, %edx
	movq	%r12, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	32(%rsp), %rdi
	movl	$252, %edx
	movq	%r15, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	72(%rsp), %rdi
	movl	$252, %edx
	movq	%rbp, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movl	$4, %r14d
.LBB3_28:                               #   Parent Loop BB3_18 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movl	%r14d, %ebp
	shrl	%ebp
	movsd	.LCPI3_1(%rip), %xmm0           # xmm0 = mem[0],zero
	movl	%ebp, %edi
	callq	ldexp@PLT
	cvttsd2si	%xmm0, %r12d
	movl	%r14d, %edi
	subl	%ebp, %edi
	movsd	.LCPI3_1(%rip), %xmm0           # xmm0 = mem[0],zero
	callq	ldexp@PLT
	cvttsd2si	%xmm0, %r13d
	movq	%r12, %rdx
	shlq	$32, %rdx
	orq	%r13, %rdx
	movabsq	$4294967297, %rdi               # imm = 0x100000001
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB3_30
# %bb.29:                               #   in Loop: Header=BB3_28 Depth=2
	movq	80(%rsp), %rcx
	movq	32(%rsp), %r8
	movq	72(%rsp), %r9
	movq	40(%rsp), %rax
	movq	%rax, (%rsp)
	movl	%ebx, %edi
	movl	%r12d, %esi
	movl	%r13d, %edx
	callq	_Z36__device_stub__CalculatePArrayKerneliiiPfS_S_S_
.LBB3_30:                               #   in Loop: Header=BB3_28 Depth=2
	callq	hipDeviceSynchronize
	incl	%ebx
	decl	%r14d
	cmpl	$5, %ebx
	jne	.LBB3_28
# %bb.31:                               #   in Loop: Header=BB3_18 Depth=1
	movq	32(%rsp), %rsi
	movl	$252, %edx
	movq	%r15, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movq	40(%rsp), %rsi
	movl	$252, %edx
	movq	128(%rsp), %r14                 # 8-byte Reload
	movq	%r14, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movss	224(%r14), %xmm0                # xmm0 = mem[0],zero,zero,zero
	divss	224(%r15), %xmm0
	movq	112(%rsp), %rsi                 # 8-byte Reload
	movl	$0, (%rsi)
	movss	%xmm0, 16(%rsp)                 # 4-byte Spill
	movss	%xmm0, 64(%rsi)
	movq	64(%rsp), %rdi
	movl	$1, %ebx
	movl	$132, %edx
	movl	$1, %ecx
	callq	hipMemcpy
	movl	$5, %ebp
.LBB3_32:                               #   Parent Loop BB3_18 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	decl	%ebp
	movl	%ebp, %r12d
	movl	%ebx, %ebp
	shrl	%ebp
	movsd	.LCPI3_1(%rip), %xmm0           # xmm0 = mem[0],zero
	movl	%ebp, %edi
	callq	ldexp@PLT
	cvttsd2si	%xmm0, %r13d
	movl	%ebx, %edi
	subl	%ebp, %edi
	movl	%r12d, %ebp
	movsd	.LCPI3_1(%rip), %xmm0           # xmm0 = mem[0],zero
	callq	ldexp@PLT
	cvttsd2si	%xmm0, %r12d
	movq	%r13, %rdx
	shlq	$32, %rdx
	orq	%r12, %rdx
	movabsq	$4294967297, %rdi               # imm = 0x100000001
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB3_34
# %bb.33:                               #   in Loop: Header=BB3_32 Depth=2
	movq	80(%rsp), %rcx
	movq	32(%rsp), %r8
	movq	72(%rsp), %r9
	movq	40(%rsp), %rax
	movq	64(%rsp), %rdx
	movq	%rdx, 8(%rsp)
	movq	%rax, (%rsp)
	movl	%ebp, %edi
	movl	%r13d, %esi
	movl	%r12d, %edx
	movss	16(%rsp), %xmm0                 # 4-byte Reload
                                        # xmm0 = mem[0],zero,zero,zero
	callq	_Z29__device_stub__BackwardKerneliiiPfS_S_S_S_f
.LBB3_34:                               #   in Loop: Header=BB3_32 Depth=2
	callq	hipDeviceSynchronize
	incl	%ebx
	cmpl	$1, %ebp
	ja	.LBB3_32
# %bb.35:                               #   in Loop: Header=BB3_18 Depth=1
	movq	64(%rsp), %rsi
	movl	$132, %edx
	movq	112(%rsp), %r13                 # 8-byte Reload
	movq	%r13, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movsd	88(%rsp), %xmm0                 # 8-byte Reload
                                        # xmm0 = mem[0],zero
	addsd	.LCPI3_1(%rip), %xmm0
	movl	24(%rsp), %eax                  # 4-byte Reload
	incl	%eax
	movl	%eax, 24(%rsp)                  # 4-byte Spill
	cmpl	$17, %eax
	movq	232(%rsp), %r12                 # 8-byte Reload
	movq	120(%rsp), %rbp                 # 8-byte Reload
	xorps	%xmm1, %xmm1
	jne	.LBB3_18
# %bb.36:
	movl	$.L.str.3, %edi
	movl	$31, %esi
	xorl	%eax, %eax
	callq	printf
	movl	$465, %ebx                      # imm = 0x1D1
	movq	56(%rsp), %r14                  # 8-byte Reload
.LBB3_37:                               # =>This Inner Loop Header: Depth=1
	movss	-1856(%r13,%rbx,4), %xmm0       # xmm0 = mem[0],zero,zero,zero
	movss	%xmm0, (%r14,%rbx,4)
	cvtss2sd	%xmm0, %xmm0
	movl	$.L.str.4, %edi
	movl	%ebx, %esi
	movb	$1, %al
	callq	printf
	incq	%rbx
	cmpq	$496, %rbx                      # imm = 0x1F0
	jne	.LBB3_37
# %bb.38:
	movl	$.Lstr, %edi
	callq	puts@PLT
	movl	$4, %eax
	movl	$1891, 104(%rsp)                # 4-byte Folded Spill
                                        # imm = 0x763
	movl	$1829, 100(%rsp)                # 4-byte Folded Spill
                                        # imm = 0x725
.LBB3_39:                               # =>This Loop Header: Depth=1
                                        #     Child Loop BB3_45 Depth 2
                                        #       Child Loop BB3_53 Depth 3
                                        #         Child Loop BB3_54 Depth 4
                                        #         Child Loop BB3_56 Depth 4
                                        #         Child Loop BB3_58 Depth 4
                                        #         Child Loop BB3_66 Depth 4
                                        #         Child Loop BB3_68 Depth 4
                                        #         Child Loop BB3_63 Depth 4
                                        #         Child Loop BB3_70 Depth 4
                                        #         Child Loop BB3_74 Depth 4
                                        #       Child Loop BB3_48 Depth 3
	movl	%eax, %ebx
	movl	$5, %edi
	subl	%eax, %edi
	movsd	.LCPI3_1(%rip), %xmm0           # xmm0 = mem[0],zero
	callq	ldexp@PLT
	cvttsd2si	%xmm0, %r14d
	leal	-1(%rbx), %edi
	movsd	.LCPI3_1(%rip), %xmm0           # xmm0 = mem[0],zero
	movl	%edi, 164(%rsp)                 # 4-byte Spill
	callq	ldexp@PLT
	movsd	%xmm0, 16(%rsp)                 # 8-byte Spill
	movsd	.LCPI3_1(%rip), %xmm0           # xmm0 = mem[0],zero
	movl	%ebx, %edi
	callq	ldexp@PLT
	testl	%r14d, %r14d
	movq	56(%rsp), %rdx                  # 8-byte Reload
	jle	.LBB3_40
# %bb.44:                               # %.preheader633.lr.ph
                                        #   in Loop: Header=BB3_39 Depth=1
	cvttsd2si	16(%rsp), %esi          # 8-byte Folded Reload
	cvttsd2si	%xmm0, %eax
	cvttpd2dq	%xmm0, %xmm0
	cvtdq2pd	%xmm0, %xmm0
	movapd	%xmm0, 352(%rsp)                # 16-byte Spill
	movl	%eax, %edi
	shll	$5, %edi
	subl	%eax, %edi
	movl	$31, %ecx
	subl	%eax, %ecx
	movl	%ecx, %eax
	shll	$5, %eax
	subl	%ecx, %eax
	movq	%rdi, 280(%rsp)                 # 8-byte Spill
	leal	-31(%rdi), %ecx
	movl	%esi, %edi
	shll	$5, %edi
	movl	%esi, 108(%rsp)                 # 4-byte Spill
	subl	%esi, %edi
	movl	%edi, 168(%rsp)                 # 4-byte Spill
	movl	%ecx, %esi
	cltq
	movslq	%ecx, %rcx
	movl	%r14d, %edi
	movq	%rdi, 288(%rsp)                 # 8-byte Spill
	leal	1(%r14), %edi
	movq	%rdi, 272(%rsp)                 # 8-byte Spill
	leaq	(%rdx,%rax,4), %rax
	movq	%rax, 312(%rsp)                 # 8-byte Spill
	leaq	(%rdx,%rcx,4), %rax
	movq	%rax, 320(%rsp)                 # 8-byte Spill
	imull	$124, %r14d, %eax
	movl	104(%rsp), %edi                 # 4-byte Reload
	subl	%eax, %edi
	movl	%r14d, %eax
	shll	$6, %eax
	addl	%r14d, %r14d
	subl	%eax, %r14d
	addl	100(%rsp), %r14d                # 4-byte Folded Reload
	movslq	%r14d, %rax
	movq	48(%rsp), %rcx                  # 8-byte Reload
	leaq	(%rcx,%rax,4), %rax
	movq	%rax, 304(%rsp)                 # 8-byte Spill
	movslq	%edi, %rax
	leaq	(%rcx,%rax,4), %rax
	movq	%rax, 296(%rsp)                 # 8-byte Spill
	movl	$1, %r8d
	movl	$-31, %ecx
.LBB3_45:                               # %.preheader633
                                        #   Parent Loop BB3_39 Depth=1
                                        # =>  This Loop Header: Depth=2
                                        #       Child Loop BB3_53 Depth 3
                                        #         Child Loop BB3_54 Depth 4
                                        #         Child Loop BB3_56 Depth 4
                                        #         Child Loop BB3_58 Depth 4
                                        #         Child Loop BB3_66 Depth 4
                                        #         Child Loop BB3_68 Depth 4
                                        #         Child Loop BB3_63 Depth 4
                                        #         Child Loop BB3_70 Depth 4
                                        #         Child Loop BB3_74 Depth 4
                                        #       Child Loop BB3_48 Depth 3
	cmpl	$0, 108(%rsp)                   # 4-byte Folded Reload
	movq	%r8, 88(%rsp)                   # 8-byte Spill
	movl	%esi, 180(%rsp)                 # 4-byte Spill
	movl	%edi, 176(%rsp)                 # 4-byte Spill
	movl	%ecx, 172(%rsp)                 # 4-byte Spill
	jle	.LBB3_46
# %bb.52:                               # %.lr.ph
                                        #   in Loop: Header=BB3_45 Depth=2
	movslq	%ecx, %rax
	leaq	(%rdx,%rax,4), %r13
	movslq	%esi, %rax
	leaq	(%rdx,%rax,4), %rax
	movq	%rax, 336(%rsp)                 # 8-byte Spill
	movslq	%edi, %rax
	movq	48(%rsp), %rcx                  # 8-byte Reload
	leaq	(%rcx,%rax,4), %rax
	movq	%rax, 328(%rsp)                 # 8-byte Spill
	leaq	(%r8,%r8), %rax
	movq	%rax, 184(%rsp)                 # 8-byte Spill
	movl	$1, %ecx
	movq	%r13, 344(%rsp)                 # 8-byte Spill
.LBB3_53:                               #   Parent Loop BB3_39 Depth=1
                                        #     Parent Loop BB3_45 Depth=2
                                        # =>    This Loop Header: Depth=3
                                        #         Child Loop BB3_54 Depth 4
                                        #         Child Loop BB3_56 Depth 4
                                        #         Child Loop BB3_58 Depth 4
                                        #         Child Loop BB3_66 Depth 4
                                        #         Child Loop BB3_68 Depth 4
                                        #         Child Loop BB3_63 Depth 4
                                        #         Child Loop BB3_70 Depth 4
                                        #         Child Loop BB3_74 Depth 4
	movl	$0, (%r12)
	movl	$1, %eax
.LBB3_54:                               #   Parent Loop BB3_39 Depth=1
                                        #     Parent Loop BB3_45 Depth=2
                                        #       Parent Loop BB3_53 Depth=3
                                        # =>      This Inner Loop Header: Depth=4
	movl	$1065353216, (%r12,%rax,4)      # imm = 0x3F800000
	incq	%rax
	cmpq	$31, %rax
	jne	.LBB3_54
# %bb.55:                               # %.preheader632.preheader
                                        #   in Loop: Header=BB3_53 Depth=3
	movq	224(%rsp), %rax                 # 8-byte Reload
	xorpd	%xmm0, %xmm0
	movupd	%xmm0, 112(%rax)
	movupd	%xmm0, 96(%rax)
	movupd	%xmm0, 80(%rax)
	movupd	%xmm0, 64(%rax)
	movupd	%xmm0, 48(%rax)
	movupd	%xmm0, 32(%rax)
	movupd	%xmm0, 16(%rax)
	movupd	%xmm0, (%rax)
	movq	%rcx, 24(%rsp)                  # 8-byte Spill
	xorps	%xmm0, %xmm0
	cvtsi2sd	%ecx, %xmm0
	addsd	%xmm0, %xmm0
	addsd	.LCPI3_2(%rip), %xmm0
	divsd	352(%rsp), %xmm0                # 16-byte Folded Reload
	mulsd	.LCPI3_4(%rip), %xmm0
	movsd	%xmm0, 16(%rsp)                 # 8-byte Spill
	xorl	%r14d, %r14d
.LBB3_56:                               #   Parent Loop BB3_39 Depth=1
                                        #     Parent Loop BB3_45 Depth=2
                                        #       Parent Loop BB3_53 Depth=3
                                        # =>      This Inner Loop Header: Depth=4
	movsd	16(%rsp), %xmm0                 # 8-byte Reload
                                        # xmm0 = mem[0],zero
	callq	cos
	addsd	%xmm0, %xmm0
	addsd	.LCPI3_5(%rip), %xmm0
	cvtsd2ss	%xmm0, %xmm0
	movss	%xmm0, (%r15,%r14,4)
	cvtss2sd	%xmm0, %xmm0
	movl	$.L.str.6, %edi
	movl	%ebx, %esi
	movb	$1, %al
	callq	printf
	incq	%r14
	cmpq	$31, %r14
	jne	.LBB3_56
# %bb.57:                               # %.preheader630.preheader
                                        #   in Loop: Header=BB3_53 Depth=3
	movq	216(%rsp), %rax                 # 8-byte Reload
	xorps	%xmm0, %xmm0
	movups	%xmm0, 112(%rax)
	movups	%xmm0, 96(%rax)
	movups	%xmm0, 80(%rax)
	movups	%xmm0, 64(%rax)
	movups	%xmm0, 48(%rax)
	movups	%xmm0, 32(%rax)
	movups	%xmm0, 16(%rax)
	movups	%xmm0, (%rax)
	movl	$0, 120(%rbp)
	xorl	%eax, %eax
.LBB3_58:                               #   Parent Loop BB3_39 Depth=1
                                        #     Parent Loop BB3_45 Depth=2
                                        #       Parent Loop BB3_53 Depth=3
                                        # =>      This Inner Loop Header: Depth=4
	movl	$1065353216, (%rbp,%rax,4)      # imm = 0x3F800000
	incq	%rax
	cmpq	$30, %rax
	jne	.LBB3_58
# %bb.59:                               # %.preheader629.preheader
                                        #   in Loop: Header=BB3_53 Depth=3
	movq	208(%rsp), %rax                 # 8-byte Reload
	xorps	%xmm0, %xmm0
	movups	%xmm0, 112(%rax)
	movups	%xmm0, 96(%rax)
	movups	%xmm0, 80(%rax)
	movups	%xmm0, 64(%rax)
	movups	%xmm0, 48(%rax)
	movups	%xmm0, 32(%rax)
	movups	%xmm0, 16(%rax)
	movups	%xmm0, (%rax)
	cmpl	$1, 24(%rsp)                    # 4-byte Folded Reload
	movq	128(%rsp), %r8                  # 8-byte Reload
	movaps	.LCPI3_6(%rip), %xmm1           # xmm1 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0]
	movq	320(%rsp), %rdx                 # 8-byte Reload
	movq	336(%rsp), %r9                  # 8-byte Reload
	movq	328(%rsp), %r10                 # 8-byte Reload
	jne	.LBB3_60
# %bb.61:                               #   in Loop: Header=BB3_53 Depth=3
	movq	88(%rsp), %rax                  # 8-byte Reload
	cmpq	$1, %rax
	movq	312(%rsp), %rcx                 # 8-byte Reload
	movq	304(%rsp), %rsi                 # 8-byte Reload
	movq	296(%rsp), %rdi                 # 8-byte Reload
	jne	.LBB3_64
# %bb.62:                               # %.preheader619.preheader
                                        #   in Loop: Header=BB3_53 Depth=3
	xorl	%eax, %eax
.LBB3_63:                               # %.preheader619
                                        #   Parent Loop BB3_39 Depth=1
                                        #     Parent Loop BB3_45 Depth=2
                                        #       Parent Loop BB3_53 Depth=3
                                        # =>      This Inner Loop Header: Depth=4
	movss	(%rdi,%rax,4), %xmm0            # xmm0 = mem[0],zero,zero,zero
	subss	(%rdx,%rax,4), %xmm0
	xorps	%xmm1, %xmm0
	movss	%xmm0, (%r8,%rax,4)
	incq	%rax
	cmpq	$31, %rax
	jne	.LBB3_63
	jmp	.LBB3_69
.LBB3_60:                               # %.preheader628.preheader
                                        #   in Loop: Header=BB3_53 Depth=3
	movl	$31, %ecx
	movq	%r8, %rdi
	movq	192(%rsp), %rsi                 # 8-byte Reload
	rep;movsl (%rsi), %es:(%rdi)
.LBB3_69:                               # %.loopexit
                                        #   in Loop: Header=BB3_53 Depth=3
	movq	200(%rsp), %rax                 # 8-byte Reload
	xorps	%xmm0, %xmm0
	movups	%xmm0, 112(%rax)
	movups	%xmm0, 96(%rax)
	movups	%xmm0, 80(%rax)
	movups	%xmm0, 64(%rax)
	movups	%xmm0, 48(%rax)
	movups	%xmm0, 32(%rax)
	movups	%xmm0, 16(%rax)
	movups	%xmm0, (%rax)
	movq	40(%rsp), %rdi
	movl	$1, %r13d
	movl	$252, %edx
	movq	%r8, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	80(%rsp), %rdi
	movl	$252, %edx
	movq	%r12, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	32(%rsp), %rdi
	movl	$252, %edx
	movq	%r15, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	72(%rsp), %rdi
	movl	$252, %edx
	movq	%rbp, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movl	$4, %r14d
.LBB3_70:                               #   Parent Loop BB3_39 Depth=1
                                        #     Parent Loop BB3_45 Depth=2
                                        #       Parent Loop BB3_53 Depth=3
                                        # =>      This Inner Loop Header: Depth=4
	movl	%r14d, %ebp
	shrl	%ebp
	movsd	.LCPI3_1(%rip), %xmm0           # xmm0 = mem[0],zero
	movl	%ebp, %edi
	callq	ldexp@PLT
	cvttsd2si	%xmm0, %r12d
	movl	%r14d, %edi
	subl	%ebp, %edi
	movsd	.LCPI3_1(%rip), %xmm0           # xmm0 = mem[0],zero
	callq	ldexp@PLT
	cvttsd2si	%xmm0, %ebp
	movq	%r12, %rdx
	shlq	$32, %rdx
	orq	%rbp, %rdx
	movabsq	$4294967297, %rdi               # imm = 0x100000001
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB3_72
# %bb.71:                               #   in Loop: Header=BB3_70 Depth=4
	movq	80(%rsp), %rcx
	movq	32(%rsp), %r8
	movq	72(%rsp), %r9
	movq	40(%rsp), %rax
	movq	%rax, (%rsp)
	movl	%r13d, %edi
	movl	%r12d, %esi
	movl	%ebp, %edx
	callq	_Z36__device_stub__CalculatePArrayKerneliiiPfS_S_S_
.LBB3_72:                               #   in Loop: Header=BB3_70 Depth=4
	callq	hipDeviceSynchronize
	incl	%r13d
	decl	%r14d
	cmpl	$5, %r13d
	jne	.LBB3_70
# %bb.73:                               #   in Loop: Header=BB3_53 Depth=3
	movq	32(%rsp), %rsi
	movl	$252, %edx
	movq	%r15, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movq	40(%rsp), %rsi
	movl	$252, %edx
	movq	128(%rsp), %r14                 # 8-byte Reload
	movq	%r14, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movss	224(%r14), %xmm0                # xmm0 = mem[0],zero,zero,zero
	divss	224(%r15), %xmm0
	movq	112(%rsp), %rsi                 # 8-byte Reload
	movl	$0, (%rsi)
	movss	%xmm0, 16(%rsp)                 # 4-byte Spill
	movss	%xmm0, 64(%rsi)
	movq	64(%rsp), %rdi
	movl	$1, %r14d
	movl	$132, %edx
	movl	$1, %ecx
	callq	hipMemcpy
	movl	$5, %r13d
.LBB3_74:                               #   Parent Loop BB3_39 Depth=1
                                        #     Parent Loop BB3_45 Depth=2
                                        #       Parent Loop BB3_53 Depth=3
                                        # =>      This Inner Loop Header: Depth=4
	decl	%r13d
	movl	%r14d, %ebp
	shrl	%ebp
	movsd	.LCPI3_1(%rip), %xmm0           # xmm0 = mem[0],zero
	movl	%ebp, %edi
	callq	ldexp@PLT
	cvttsd2si	%xmm0, %r12d
	movl	%r14d, %edi
	subl	%ebp, %edi
	movsd	.LCPI3_1(%rip), %xmm0           # xmm0 = mem[0],zero
	callq	ldexp@PLT
	cvttsd2si	%xmm0, %ebp
	movq	%r12, %rdx
	shlq	$32, %rdx
	orq	%rbp, %rdx
	movabsq	$4294967297, %rdi               # imm = 0x100000001
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB3_76
# %bb.75:                               #   in Loop: Header=BB3_74 Depth=4
	movq	80(%rsp), %rcx
	movq	32(%rsp), %r8
	movq	72(%rsp), %r9
	movq	40(%rsp), %rax
	movq	64(%rsp), %rdx
	movq	%rdx, 8(%rsp)
	movq	%rax, (%rsp)
	movl	%r13d, %edi
	movl	%r12d, %esi
	movl	%ebp, %edx
	movss	16(%rsp), %xmm0                 # 4-byte Reload
                                        # xmm0 = mem[0],zero,zero,zero
	callq	_Z29__device_stub__BackwardKerneliiiPfS_S_S_S_f
.LBB3_76:                               #   in Loop: Header=BB3_74 Depth=4
	callq	hipDeviceSynchronize
	incl	%r14d
	cmpl	$1, %r13d
	ja	.LBB3_74
# %bb.77:                               #   in Loop: Header=BB3_53 Depth=3
	movq	64(%rsp), %rsi
	movl	$132, %edx
	movq	112(%rsp), %r14                 # 8-byte Reload
	movq	%r14, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movq	24(%rsp), %rcx                  # 8-byte Reload
	leal	1(%rcx), %eax
	cmpl	108(%rsp), %ecx                 # 4-byte Folded Reload
	movl	%eax, %ecx
	movq	232(%rsp), %r12                 # 8-byte Reload
	movq	120(%rsp), %rbp                 # 8-byte Reload
	movq	344(%rsp), %r13                 # 8-byte Reload
	jne	.LBB3_53
	jmp	.LBB3_78
.LBB3_64:                               #   in Loop: Header=BB3_53 Depth=3
	cmpq	288(%rsp), %rax                 # 8-byte Folded Reload
	jne	.LBB3_65
# %bb.67:                               # %.preheader622.preheader
                                        #   in Loop: Header=BB3_53 Depth=3
	xorl	%eax, %eax
.LBB3_68:                               # %.preheader622
                                        #   Parent Loop BB3_39 Depth=1
                                        #     Parent Loop BB3_45 Depth=2
                                        #       Parent Loop BB3_53 Depth=3
                                        # =>      This Inner Loop Header: Depth=4
	movss	(%rsi,%rax,4), %xmm0            # xmm0 = mem[0],zero,zero,zero
	subss	(%rcx,%rax,4), %xmm0
	xorps	%xmm1, %xmm0
	movss	%xmm0, (%r8,%rax,4)
	incq	%rax
	cmpq	$31, %rax
	jne	.LBB3_68
	jmp	.LBB3_69
.LBB3_65:                               # %.preheader625.preheader
                                        #   in Loop: Header=BB3_53 Depth=3
	xorl	%eax, %eax
.LBB3_66:                               # %.preheader625
                                        #   Parent Loop BB3_39 Depth=1
                                        #     Parent Loop BB3_45 Depth=2
                                        #       Parent Loop BB3_53 Depth=3
                                        # =>      This Inner Loop Header: Depth=4
	movss	(%r10,%rax,4), %xmm0            # xmm0 = mem[0],zero,zero,zero
	subss	(%r9,%rax,4), %xmm0
	subss	(%r13,%rax,4), %xmm0
	xorps	%xmm1, %xmm0
	movss	%xmm0, (%r8,%rax,4)
	incq	%rax
	cmpq	$31, %rax
	jne	.LBB3_66
	jmp	.LBB3_69
.LBB3_78:                               #   in Loop: Header=BB3_45 Depth=2
	movq	%r14, %r13
	jmp	.LBB3_47
.LBB3_46:                               # %.preheader633.._crit_edge_crit_edge
                                        #   in Loop: Header=BB3_45 Depth=2
	leaq	(%r8,%r8), %rax
	movq	%rax, 184(%rsp)                 # 8-byte Spill
.LBB3_47:                               # %._crit_edge
                                        #   in Loop: Header=BB3_45 Depth=2
	movl	$10, %edi
	callq	putchar@PLT
	movq	184(%rsp), %rcx                 # 8-byte Reload
	decl	%ecx
	imull	168(%rsp), %ecx                 # 4-byte Folded Reload
	addl	$-31, %ecx
	xorl	%r14d, %r14d
	movq	56(%rsp), %rdx                  # 8-byte Reload
	movq	88(%rsp), %r8                   # 8-byte Reload
.LBB3_48:                               #   Parent Loop BB3_39 Depth=1
                                        #     Parent Loop BB3_45 Depth=2
                                        # =>    This Inner Loop Header: Depth=3
	leaq	(%rcx,%r14), %rsi
	movss	4(%r13,%r14,4), %xmm0           # xmm0 = mem[0],zero,zero,zero
	movslq	%esi, %rax
	movss	%xmm0, (%rdx,%rax,4)
	cmpq	$1, %r8
	jne	.LBB3_50
# %bb.49:                               #   in Loop: Header=BB3_48 Depth=3
	cvtss2sd	%xmm0, %xmm0
	movl	$.L.str.7, %edi
                                        # kill: def $esi killed $esi killed $rsi
	movb	$1, %al
	movq	%rbx, %rbp
	movq	%r15, %rbx
	movq	%r13, %r15
	movq	%rcx, %r13
	callq	printf
	movq	%r13, %rcx
	movq	%r15, %r13
	movq	%rbx, %r15
	movq	%rbp, %rbx
	movq	120(%rsp), %rbp                 # 8-byte Reload
	movq	88(%rsp), %r8                   # 8-byte Reload
	movq	56(%rsp), %rdx                  # 8-byte Reload
.LBB3_50:                               #   in Loop: Header=BB3_48 Depth=3
	incq	%r14
	cmpq	$31, %r14
	jne	.LBB3_48
# %bb.51:                               #   in Loop: Header=BB3_45 Depth=2
	incq	%r8
	movq	280(%rsp), %rax                 # 8-byte Reload
	movl	172(%rsp), %ecx                 # 4-byte Reload
	addl	%eax, %ecx
	movl	180(%rsp), %esi                 # 4-byte Reload
	addl	%eax, %esi
	movl	176(%rsp), %edi                 # 4-byte Reload
	addl	$62, %edi
	cmpq	272(%rsp), %r8                  # 8-byte Folded Reload
	jne	.LBB3_45
.LBB3_40:                               # %.loopexit634
                                        #   in Loop: Header=BB3_39 Depth=1
	addl	$31, 104(%rsp)                  # 4-byte Folded Spill
	addl	$31, 100(%rsp)                  # 4-byte Folded Spill
	cmpl	$1, %ebx
	movl	164(%rsp), %eax                 # 4-byte Reload
	ja	.LBB3_39
# %bb.41:
	movl	$10, %edi
	callq	putchar@PLT
	xorl	%ebx, %ebx
	movq	56(%rsp), %r14                  # 8-byte Reload
.LBB3_42:                               # =>This Inner Loop Header: Depth=1
	movl	$10, %edi
	callq	putchar@PLT
	xorps	%xmm0, %xmm0
	cvtss2sd	(%r14,%rbx,4), %xmm0
	movl	$.L.str.8, %edi
	movl	%ebx, %esi
	movb	$1, %al
	callq	printf
	incq	%rbx
	cmpq	$961, %rbx                      # imm = 0x3C1
	jne	.LBB3_42
# %bb.43:
	callq	clock
	subq	264(%rsp), %rax                 # 8-byte Folded Reload
	xorps	%xmm0, %xmm0
	cvtsi2sd	%rax, %xmm0
	divsd	.LCPI3_7(%rip), %xmm0
	movl	$.L.str.9, %edi
	movl	$32, %esi
	movb	$1, %al
	callq	printf
	xorl	%eax, %eax
	addq	$376, %rsp                      # imm = 0x178
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	main, .Lfunc_end3-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB4_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB4_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z13CalculateTheDiPfS_S_S_S_S_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z21CalculatePArrayKerneliiiPfS_S_S_, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z14BackwardKerneliiiPfS_S_S_S_f, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end4:
	.size	__hip_module_ctor, .Lfunc_end4-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB5_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB5_2:
	retq
.Lfunc_end5:
	.size	__hip_module_dtor, .Lfunc_end5-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z13CalculateTheDiPfS_S_S_S_S_,@object # @_Z13CalculateTheDiPfS_S_S_S_S_
	.section	.rodata,"a",@progbits
	.globl	_Z13CalculateTheDiPfS_S_S_S_S_
	.p2align	3, 0x0
_Z13CalculateTheDiPfS_S_S_S_S_:
	.quad	_Z28__device_stub__CalculateTheDiPfS_S_S_S_S_
	.size	_Z13CalculateTheDiPfS_S_S_S_S_, 8

	.type	_Z21CalculatePArrayKerneliiiPfS_S_S_,@object # @_Z21CalculatePArrayKerneliiiPfS_S_S_
	.globl	_Z21CalculatePArrayKerneliiiPfS_S_S_
	.p2align	3, 0x0
_Z21CalculatePArrayKerneliiiPfS_S_S_:
	.quad	_Z36__device_stub__CalculatePArrayKerneliiiPfS_S_S_
	.size	_Z21CalculatePArrayKerneliiiPfS_S_S_, 8

	.type	_Z14BackwardKerneliiiPfS_S_S_S_f,@object # @_Z14BackwardKerneliiiPfS_S_S_S_f
	.globl	_Z14BackwardKerneliiiPfS_S_S_S_f
	.p2align	3, 0x0
_Z14BackwardKerneliiiPfS_S_S_S_f:
	.quad	_Z29__device_stub__BackwardKerneliiiPfS_S_S_S_f
	.size	_Z14BackwardKerneliiiPfS_S_S_S_f, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"dd block: %d %lf "
	.size	.L.str, 18

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"dha:%lf "
	.size	.L.str.2, 9

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"\n final result for x(2^(k-1) block which should have %d values in it:\n"
	.size	.L.str.3, 71

	.type	.L.str.4,@object                # @.str.4
.L.str.4:
	.asciz	"index: %d, %lf "
	.size	.L.str.4, 16

	.type	.L.str.6,@object                # @.str.6
.L.str.6:
	.asciz	"zb:%f step: %d\n"
	.size	.L.str.6, 16

	.type	.L.str.7,@object                # @.str.7
.L.str.7:
	.asciz	"test [%d],%lf \n"
	.size	.L.str.7, 16

	.type	.L.str.8,@object                # @.str.8
.L.str.8:
	.asciz	"[%d]:%lf "
	.size	.L.str.8, 10

	.type	.L.str.9,@object                # @.str.9
.L.str.9:
	.asciz	"\n time spent to calcuate x with partition [0,1] into %d intervals:%lf seconds \n"
	.size	.L.str.9, 80

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z13CalculateTheDiPfS_S_S_S_S_"
	.size	.L__unnamed_1, 31

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z21CalculatePArrayKerneliiiPfS_S_S_"
	.size	.L__unnamed_2, 37

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z14BackwardKerneliiiPfS_S_S_S_f"
	.size	.L__unnamed_3, 33

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.type	.Lstr,@object                   # @str
	.section	.rodata.str1.1,"aMS",@progbits,1
.Lstr:
	.asciz	"\n "
	.size	.Lstr, 3

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z28__device_stub__CalculateTheDiPfS_S_S_S_S_
	.addrsig_sym _Z36__device_stub__CalculatePArrayKerneliiiPfS_S_S_
	.addrsig_sym _Z29__device_stub__BackwardKerneliiiPfS_S_S_S_f
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z13CalculateTheDiPfS_S_S_S_S_
	.addrsig_sym _Z21CalculatePArrayKerneliiiPfS_S_S_
	.addrsig_sym _Z14BackwardKerneliiiPfS_S_S_S_f
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.p2align	2                               ; -- Begin function __ockl_printf_append_string_n
	.type	__ockl_printf_append_string_n,@function
__ockl_printf_append_string_n:          ; @__ockl_printf_append_string_n
; %bb.0:
	s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	v_dual_mov_b32 v7, v3 :: v_dual_mov_b32 v6, v2
	v_mov_b32_e32 v8, v0
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_2)
	v_cmpx_ne_u64_e32 0, v[6:7]
	s_xor_b32 s10, exec_lo, s0
	s_cbranch_execz .LBB0_87
; %bb.1:
	s_load_b64 s[2:3], s[8:9], 0x50
	v_dual_mov_b32 v29, 0 :: v_dual_and_b32 v32, 2, v8
	v_dual_mov_b32 v11, 1 :: v_dual_and_b32 v0, -3, v8
	v_mbcnt_lo_u32_b32 v33, -1, 0
	v_mov_b32_e32 v10, 2
	s_mov_b32 s12, 0
	s_mov_b32 s11, 0
.LBB0_2:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_5 Depth 2
                                        ;     Child Loop BB0_13 Depth 2
                                        ;     Child Loop BB0_21 Depth 2
                                        ;     Child Loop BB0_29 Depth 2
                                        ;     Child Loop BB0_37 Depth 2
                                        ;     Child Loop BB0_45 Depth 2
                                        ;     Child Loop BB0_53 Depth 2
                                        ;     Child Loop BB0_61 Depth 2
                                        ;     Child Loop BB0_69 Depth 2
                                        ;     Child Loop BB0_75 Depth 2
                                        ;     Child Loop BB0_84 Depth 2
	v_cmp_gt_u64_e32 vcc_lo, 56, v[4:5]
                                        ; implicit-def: $vgpr2_vgpr3
                                        ; implicit-def: $sgpr4
	s_mov_b32 s0, exec_lo
	v_dual_cndmask_b32 v31, 0, v5 :: v_dual_cndmask_b32 v30, 56, v4
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e32 8, v30
	s_xor_b32 s1, exec_lo, s0
	s_cbranch_execz .LBB0_8
; %bb.3:                                ;   in Loop: Header=BB0_2 Depth=1
	s_waitcnt vmcnt(0)
	v_mov_b32_e32 v2, 0
	v_mov_b32_e32 v3, 0
	s_mov_b32 s6, exec_lo
	v_cmpx_ne_u32_e32 0, v30
	s_cbranch_execz .LBB0_7
; %bb.4:                                ; %.preheader31.preheader
                                        ;   in Loop: Header=BB0_2 Depth=1
	v_lshlrev_b64 v[8:9], 3, v[30:31]
	v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v13, v7
	v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v12, v6
	s_mov_b64 s[4:5], 0
	s_mov_b32 s7, 0
.LBB0_5:                                ; %.preheader31
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	flat_load_u8 v9, v[12:13]
	v_mov_b32_e32 v15, s12
	v_add_co_u32 v12, vcc_lo, v12, 1
	v_add_co_ci_u32_e32 v13, vcc_lo, 0, v13, vcc_lo
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_and_b32_e32 v14, 0xffff, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[14:15], s4, v[14:15]
	s_add_u32 s4, s4, 8
	s_addc_u32 s5, s5, 0
	v_cmp_eq_u32_e64 s0, s4, v8
	v_or_b32_e32 v3, v15, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_or_b32_e32 v2, v14, v2
	s_or_b32 s7, s0, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s7
	s_cbranch_execnz .LBB0_5
; %bb.6:                                ; %Flow172
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s7
.LBB0_7:                                ; %Flow174
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s6
	s_mov_b32 s4, 0
.LBB0_8:                                ; %Flow176
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_saveexec_b32 s0, s1
	v_dual_mov_b32 v14, s4 :: v_dual_mov_b32 v9, v7
	v_mov_b32_e32 v8, v6
	s_xor_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB0_10
; %bb.9:                                ;   in Loop: Header=BB0_2 Depth=1
	s_waitcnt vmcnt(0)
	s_clause 0x5
	flat_load_u8 v2, v[6:7]
	flat_load_u8 v3, v[6:7] offset:1
	flat_load_u8 v8, v[6:7] offset:2
	flat_load_u8 v9, v[6:7] offset:3
	flat_load_u8 v12, v[6:7] offset:5
	flat_load_u8 v13, v[6:7] offset:4
	s_waitcnt vmcnt(5) lgkmcnt(0)
	v_dual_mov_b32 v15, v29 :: v_dual_and_b32 v2, 0xffff, v2
	s_clause 0x1
	flat_load_u8 v14, v[6:7] offset:7
	flat_load_d16_hi_u8 v15, v[6:7] offset:6
	s_waitcnt vmcnt(6)
	v_lshlrev_b32_e32 v3, 8, v3
	s_waitcnt vmcnt(5)
	v_lshlrev_b32_e32 v8, 16, v8
	s_waitcnt vmcnt(4)
	v_lshlrev_b32_e32 v9, 24, v9
	v_or_b32_e32 v2, v3, v2
	s_waitcnt vmcnt(3)
	v_lshlrev_b32_e32 v3, 8, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_or3_b32 v2, v2, v8, v9
	s_waitcnt vmcnt(2)
	v_or3_b32 v3, 0, v13, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or3_b32 v2, v2, 0, 0
	v_or3_b32 v2, v2, 0, 0
	s_waitcnt vmcnt(1) lgkmcnt(1)
	v_lshlrev_b32_e32 v8, 24, v14
	v_add_nc_u32_e32 v14, -8, v30
	s_waitcnt vmcnt(0) lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2)
	v_or3_b32 v3, v3, v15, v8
	v_add_co_u32 v8, vcc_lo, v6, 8
	v_add_co_ci_u32_e32 v9, vcc_lo, 0, v7, vcc_lo
.LBB0_10:                               ; %.loopexit32
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $vgpr12_vgpr13
                                        ; implicit-def: $sgpr1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 8, v14
	s_xor_b32 s6, exec_lo, s0
	s_cbranch_execz .LBB0_16
; %bb.11:                               ;   in Loop: Header=BB0_2 Depth=1
	v_mov_b32_e32 v12, 0
	v_mov_b32_e32 v13, 0
	s_mov_b32 s7, exec_lo
	v_cmpx_ne_u32_e32 0, v14
	s_cbranch_execz .LBB0_15
; %bb.12:                               ; %.preheader29.preheader
                                        ;   in Loop: Header=BB0_2 Depth=1
	v_mov_b32_e32 v12, 0
	v_mov_b32_e32 v13, 0
	s_mov_b64 s[0:1], 0
	s_mov_b32 s13, 0
	s_mov_b64 s[4:5], 0
.LBB0_13:                               ; %.preheader29
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	v_add_co_u32 v15, vcc_lo, v8, s4
	v_add_co_ci_u32_e32 v16, vcc_lo, s5, v9, vcc_lo
	s_add_u32 s4, s4, 1
	s_addc_u32 s5, s5, 0
	v_cmp_eq_u32_e32 vcc_lo, s4, v14
	flat_load_u8 v15, v[15:16]
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_dual_mov_b32 v16, s12 :: v_dual_and_b32 v15, 0xffff, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[15:16], s0, v[15:16]
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	s_or_b32 s13, vcc_lo, s13
	v_or_b32_e32 v13, v16, v13
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v12, v15, v12
	s_and_not1_b32 exec_lo, exec_lo, s13
	s_cbranch_execnz .LBB0_13
; %bb.14:                               ; %Flow167
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s13
.LBB0_15:                               ; %Flow169
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s7
	s_mov_b32 s1, 0
                                        ; implicit-def: $vgpr14
.LBB0_16:                               ; %Flow171
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_saveexec_b32 s0, s6
	v_mov_b32_e32 v16, s1
	s_xor_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB0_18
; %bb.17:                               ;   in Loop: Header=BB0_2 Depth=1
	s_clause 0x5
	flat_load_u8 v12, v[8:9]
	flat_load_u8 v13, v[8:9] offset:1
	flat_load_u8 v15, v[8:9] offset:2
	flat_load_u8 v16, v[8:9] offset:3
	flat_load_u8 v17, v[8:9] offset:5
	flat_load_u8 v18, v[8:9] offset:4
	s_waitcnt vmcnt(5) lgkmcnt(0)
	v_dual_mov_b32 v19, v29 :: v_dual_and_b32 v12, 0xffff, v12
	s_clause 0x1
	flat_load_u8 v20, v[8:9] offset:7
	flat_load_d16_hi_u8 v19, v[8:9] offset:6
	s_waitcnt vmcnt(6)
	v_lshlrev_b32_e32 v13, 8, v13
	s_waitcnt vmcnt(5)
	v_lshlrev_b32_e32 v15, 16, v15
	s_waitcnt vmcnt(4)
	v_lshlrev_b32_e32 v16, 24, v16
	v_add_co_u32 v8, vcc_lo, v8, 8
	v_or_b32_e32 v12, v13, v12
	s_waitcnt vmcnt(3)
	v_lshlrev_b32_e32 v13, 8, v17
	v_add_co_ci_u32_e32 v9, vcc_lo, 0, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_or3_b32 v12, v12, v15, v16
	s_waitcnt vmcnt(2)
	v_or3_b32 v13, 0, v18, v13
	v_add_nc_u32_e32 v16, -8, v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or3_b32 v12, v12, 0, 0
	v_or3_b32 v12, v12, 0, 0
	s_waitcnt vmcnt(1) lgkmcnt(1)
	v_lshlrev_b32_e32 v15, 24, v20
	s_waitcnt vmcnt(0) lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_or3_b32 v13, v13, v19, v15
.LBB0_18:                               ; %.loopexit30
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $sgpr1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 8, v16
	s_xor_b32 s6, exec_lo, s0
	s_cbranch_execz .LBB0_24
; %bb.19:                               ;   in Loop: Header=BB0_2 Depth=1
	v_mov_b32_e32 v14, 0
	v_mov_b32_e32 v15, 0
	s_mov_b32 s7, exec_lo
	v_cmpx_ne_u32_e32 0, v16
	s_cbranch_execz .LBB0_23
; %bb.20:                               ; %.preheader27.preheader
                                        ;   in Loop: Header=BB0_2 Depth=1
	v_mov_b32_e32 v14, 0
	v_mov_b32_e32 v15, 0
	s_mov_b64 s[0:1], 0
	s_mov_b32 s13, 0
	s_mov_b64 s[4:5], 0
.LBB0_21:                               ; %.preheader27
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	v_add_co_u32 v17, vcc_lo, v8, s4
	v_add_co_ci_u32_e32 v18, vcc_lo, s5, v9, vcc_lo
	s_add_u32 s4, s4, 1
	s_addc_u32 s5, s5, 0
	v_cmp_eq_u32_e32 vcc_lo, s4, v16
	flat_load_u8 v17, v[17:18]
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_dual_mov_b32 v18, s12 :: v_dual_and_b32 v17, 0xffff, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[17:18], s0, v[17:18]
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	s_or_b32 s13, vcc_lo, s13
	v_or_b32_e32 v15, v18, v15
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v14, v17, v14
	s_and_not1_b32 exec_lo, exec_lo, s13
	s_cbranch_execnz .LBB0_21
; %bb.22:                               ; %Flow162
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s13
.LBB0_23:                               ; %Flow164
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s7
	s_mov_b32 s1, 0
                                        ; implicit-def: $vgpr16
.LBB0_24:                               ; %Flow166
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_saveexec_b32 s0, s6
	v_mov_b32_e32 v18, s1
	s_xor_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB0_26
; %bb.25:                               ;   in Loop: Header=BB0_2 Depth=1
	s_clause 0x5
	flat_load_u8 v14, v[8:9]
	flat_load_u8 v15, v[8:9] offset:1
	flat_load_u8 v17, v[8:9] offset:2
	flat_load_u8 v18, v[8:9] offset:3
	flat_load_u8 v19, v[8:9] offset:5
	flat_load_u8 v20, v[8:9] offset:4
	s_waitcnt vmcnt(5) lgkmcnt(0)
	v_dual_mov_b32 v21, v29 :: v_dual_and_b32 v14, 0xffff, v14
	s_clause 0x1
	flat_load_u8 v22, v[8:9] offset:7
	flat_load_d16_hi_u8 v21, v[8:9] offset:6
	s_waitcnt vmcnt(6)
	v_lshlrev_b32_e32 v15, 8, v15
	s_waitcnt vmcnt(5)
	v_lshlrev_b32_e32 v17, 16, v17
	s_waitcnt vmcnt(4)
	v_lshlrev_b32_e32 v18, 24, v18
	v_add_co_u32 v8, vcc_lo, v8, 8
	v_or_b32_e32 v14, v15, v14
	s_waitcnt vmcnt(3)
	v_lshlrev_b32_e32 v15, 8, v19
	v_add_co_ci_u32_e32 v9, vcc_lo, 0, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_or3_b32 v14, v14, v17, v18
	s_waitcnt vmcnt(2)
	v_or3_b32 v15, 0, v20, v15
	v_add_nc_u32_e32 v18, -8, v16
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or3_b32 v14, v14, 0, 0
	v_or3_b32 v14, v14, 0, 0
	s_waitcnt vmcnt(1) lgkmcnt(1)
	v_lshlrev_b32_e32 v17, 24, v22
	s_waitcnt vmcnt(0) lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_or3_b32 v15, v15, v21, v17
.LBB0_26:                               ; %.loopexit28
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $vgpr16_vgpr17
                                        ; implicit-def: $sgpr1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 8, v18
	s_xor_b32 s6, exec_lo, s0
	s_cbranch_execz .LBB0_32
; %bb.27:                               ;   in Loop: Header=BB0_2 Depth=1
	v_mov_b32_e32 v16, 0
	v_mov_b32_e32 v17, 0
	s_mov_b32 s7, exec_lo
	v_cmpx_ne_u32_e32 0, v18
	s_cbranch_execz .LBB0_31
; %bb.28:                               ; %.preheader25.preheader
                                        ;   in Loop: Header=BB0_2 Depth=1
	v_mov_b32_e32 v16, 0
	v_mov_b32_e32 v17, 0
	s_mov_b64 s[0:1], 0
	s_mov_b32 s13, 0
	s_mov_b64 s[4:5], 0
.LBB0_29:                               ; %.preheader25
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	v_add_co_u32 v19, vcc_lo, v8, s4
	v_add_co_ci_u32_e32 v20, vcc_lo, s5, v9, vcc_lo
	s_add_u32 s4, s4, 1
	s_addc_u32 s5, s5, 0
	v_cmp_eq_u32_e32 vcc_lo, s4, v18
	flat_load_u8 v19, v[19:20]
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_dual_mov_b32 v20, s12 :: v_dual_and_b32 v19, 0xffff, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[19:20], s0, v[19:20]
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	s_or_b32 s13, vcc_lo, s13
	v_or_b32_e32 v17, v20, v17
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v16, v19, v16
	s_and_not1_b32 exec_lo, exec_lo, s13
	s_cbranch_execnz .LBB0_29
; %bb.30:                               ; %Flow157
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s13
.LBB0_31:                               ; %Flow159
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s7
	s_mov_b32 s1, 0
                                        ; implicit-def: $vgpr18
.LBB0_32:                               ; %Flow161
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_saveexec_b32 s0, s6
	v_mov_b32_e32 v20, s1
	s_xor_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB0_34
; %bb.33:                               ;   in Loop: Header=BB0_2 Depth=1
	s_clause 0x5
	flat_load_u8 v16, v[8:9]
	flat_load_u8 v17, v[8:9] offset:1
	flat_load_u8 v19, v[8:9] offset:2
	flat_load_u8 v20, v[8:9] offset:3
	flat_load_u8 v21, v[8:9] offset:5
	flat_load_u8 v22, v[8:9] offset:4
	s_waitcnt vmcnt(5) lgkmcnt(0)
	v_dual_mov_b32 v23, v29 :: v_dual_and_b32 v16, 0xffff, v16
	s_clause 0x1
	flat_load_u8 v24, v[8:9] offset:7
	flat_load_d16_hi_u8 v23, v[8:9] offset:6
	s_waitcnt vmcnt(6)
	v_lshlrev_b32_e32 v17, 8, v17
	s_waitcnt vmcnt(5)
	v_lshlrev_b32_e32 v19, 16, v19
	s_waitcnt vmcnt(4)
	v_lshlrev_b32_e32 v20, 24, v20
	v_add_co_u32 v8, vcc_lo, v8, 8
	v_or_b32_e32 v16, v17, v16
	s_waitcnt vmcnt(3)
	v_lshlrev_b32_e32 v17, 8, v21
	v_add_co_ci_u32_e32 v9, vcc_lo, 0, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_or3_b32 v16, v16, v19, v20
	s_waitcnt vmcnt(2)
	v_or3_b32 v17, 0, v22, v17
	v_add_nc_u32_e32 v20, -8, v18
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or3_b32 v16, v16, 0, 0
	v_or3_b32 v16, v16, 0, 0
	s_waitcnt vmcnt(1) lgkmcnt(1)
	v_lshlrev_b32_e32 v19, 24, v24
	s_waitcnt vmcnt(0) lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_or3_b32 v17, v17, v23, v19
.LBB0_34:                               ; %.loopexit26
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $sgpr1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 8, v20
	s_xor_b32 s6, exec_lo, s0
	s_cbranch_execz .LBB0_40
; %bb.35:                               ;   in Loop: Header=BB0_2 Depth=1
	v_mov_b32_e32 v18, 0
	v_mov_b32_e32 v19, 0
	s_mov_b32 s7, exec_lo
	v_cmpx_ne_u32_e32 0, v20
	s_cbranch_execz .LBB0_39
; %bb.36:                               ; %.preheader23.preheader
                                        ;   in Loop: Header=BB0_2 Depth=1
	v_mov_b32_e32 v18, 0
	v_mov_b32_e32 v19, 0
	s_mov_b64 s[0:1], 0
	s_mov_b32 s13, 0
	s_mov_b64 s[4:5], 0
.LBB0_37:                               ; %.preheader23
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	v_add_co_u32 v21, vcc_lo, v8, s4
	v_add_co_ci_u32_e32 v22, vcc_lo, s5, v9, vcc_lo
	s_add_u32 s4, s4, 1
	s_addc_u32 s5, s5, 0
	v_cmp_eq_u32_e32 vcc_lo, s4, v20
	flat_load_u8 v21, v[21:22]
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_dual_mov_b32 v22, s12 :: v_dual_and_b32 v21, 0xffff, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[21:22], s0, v[21:22]
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	s_or_b32 s13, vcc_lo, s13
	v_or_b32_e32 v19, v22, v19
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v18, v21, v18
	s_and_not1_b32 exec_lo, exec_lo, s13
	s_cbranch_execnz .LBB0_37
; %bb.38:                               ; %Flow152
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s13
.LBB0_39:                               ; %Flow154
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s7
	s_mov_b32 s1, 0
                                        ; implicit-def: $vgpr20
.LBB0_40:                               ; %Flow156
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_saveexec_b32 s0, s6
	v_mov_b32_e32 v22, s1
	s_xor_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB0_42
; %bb.41:                               ;   in Loop: Header=BB0_2 Depth=1
	s_clause 0x5
	flat_load_u8 v18, v[8:9]
	flat_load_u8 v19, v[8:9] offset:1
	flat_load_u8 v21, v[8:9] offset:2
	flat_load_u8 v22, v[8:9] offset:3
	flat_load_u8 v23, v[8:9] offset:5
	flat_load_u8 v24, v[8:9] offset:4
	s_waitcnt vmcnt(5) lgkmcnt(0)
	v_dual_mov_b32 v25, v29 :: v_dual_and_b32 v18, 0xffff, v18
	s_clause 0x1
	flat_load_u8 v26, v[8:9] offset:7
	flat_load_d16_hi_u8 v25, v[8:9] offset:6
	s_waitcnt vmcnt(6)
	v_lshlrev_b32_e32 v19, 8, v19
	s_waitcnt vmcnt(5)
	v_lshlrev_b32_e32 v21, 16, v21
	s_waitcnt vmcnt(4)
	v_lshlrev_b32_e32 v22, 24, v22
	v_add_co_u32 v8, vcc_lo, v8, 8
	v_or_b32_e32 v18, v19, v18
	s_waitcnt vmcnt(3)
	v_lshlrev_b32_e32 v19, 8, v23
	v_add_co_ci_u32_e32 v9, vcc_lo, 0, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_or3_b32 v18, v18, v21, v22
	s_waitcnt vmcnt(2)
	v_or3_b32 v19, 0, v24, v19
	v_add_nc_u32_e32 v22, -8, v20
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or3_b32 v18, v18, 0, 0
	v_or3_b32 v18, v18, 0, 0
	s_waitcnt vmcnt(1) lgkmcnt(1)
	v_lshlrev_b32_e32 v21, 24, v26
	s_waitcnt vmcnt(0) lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_or3_b32 v19, v19, v25, v21
.LBB0_42:                               ; %.loopexit24
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $vgpr20_vgpr21
                                        ; implicit-def: $sgpr1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 8, v22
	s_xor_b32 s6, exec_lo, s0
	s_cbranch_execz .LBB0_48
; %bb.43:                               ;   in Loop: Header=BB0_2 Depth=1
	v_mov_b32_e32 v20, 0
	v_mov_b32_e32 v21, 0
	s_mov_b32 s7, exec_lo
	v_cmpx_ne_u32_e32 0, v22
	s_cbranch_execz .LBB0_47
; %bb.44:                               ; %.preheader21.preheader
                                        ;   in Loop: Header=BB0_2 Depth=1
	v_mov_b32_e32 v20, 0
	v_mov_b32_e32 v21, 0
	s_mov_b64 s[0:1], 0
	s_mov_b32 s13, 0
	s_mov_b64 s[4:5], 0
.LBB0_45:                               ; %.preheader21
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	v_add_co_u32 v23, vcc_lo, v8, s4
	v_add_co_ci_u32_e32 v24, vcc_lo, s5, v9, vcc_lo
	s_add_u32 s4, s4, 1
	s_addc_u32 s5, s5, 0
	v_cmp_eq_u32_e32 vcc_lo, s4, v22
	flat_load_u8 v23, v[23:24]
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_dual_mov_b32 v24, s12 :: v_dual_and_b32 v23, 0xffff, v23
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[23:24], s0, v[23:24]
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	s_or_b32 s13, vcc_lo, s13
	v_or_b32_e32 v21, v24, v21
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v20, v23, v20
	s_and_not1_b32 exec_lo, exec_lo, s13
	s_cbranch_execnz .LBB0_45
; %bb.46:                               ; %Flow147
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s13
.LBB0_47:                               ; %Flow149
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s7
	s_mov_b32 s1, 0
                                        ; implicit-def: $vgpr22
.LBB0_48:                               ; %Flow151
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_saveexec_b32 s0, s6
	v_mov_b32_e32 v24, s1
	s_xor_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB0_50
; %bb.49:                               ;   in Loop: Header=BB0_2 Depth=1
	s_clause 0x5
	flat_load_u8 v20, v[8:9]
	flat_load_u8 v21, v[8:9] offset:1
	flat_load_u8 v23, v[8:9] offset:2
	flat_load_u8 v24, v[8:9] offset:3
	flat_load_u8 v25, v[8:9] offset:5
	flat_load_u8 v26, v[8:9] offset:4
	s_waitcnt vmcnt(5) lgkmcnt(0)
	v_dual_mov_b32 v27, v29 :: v_dual_and_b32 v20, 0xffff, v20
	s_clause 0x1
	flat_load_u8 v28, v[8:9] offset:7
	flat_load_d16_hi_u8 v27, v[8:9] offset:6
	s_waitcnt vmcnt(6)
	v_lshlrev_b32_e32 v21, 8, v21
	s_waitcnt vmcnt(5)
	v_lshlrev_b32_e32 v23, 16, v23
	s_waitcnt vmcnt(4)
	v_lshlrev_b32_e32 v24, 24, v24
	v_add_co_u32 v8, vcc_lo, v8, 8
	v_or_b32_e32 v20, v21, v20
	s_waitcnt vmcnt(3)
	v_lshlrev_b32_e32 v21, 8, v25
	v_add_co_ci_u32_e32 v9, vcc_lo, 0, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_or3_b32 v20, v20, v23, v24
	s_waitcnt vmcnt(2)
	v_or3_b32 v21, 0, v26, v21
	v_add_nc_u32_e32 v24, -8, v22
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or3_b32 v20, v20, 0, 0
	v_or3_b32 v20, v20, 0, 0
	s_waitcnt vmcnt(1) lgkmcnt(1)
	v_lshlrev_b32_e32 v23, 24, v28
	s_waitcnt vmcnt(0) lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_or3_b32 v21, v21, v27, v23
.LBB0_50:                               ; %.loopexit22
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 8, v24
	s_xor_b32 s4, exec_lo, s0
	s_cbranch_execz .LBB0_56
; %bb.51:                               ;   in Loop: Header=BB0_2 Depth=1
	v_mov_b32_e32 v22, 0
	v_mov_b32_e32 v23, 0
	s_mov_b32 s5, exec_lo
	v_cmpx_ne_u32_e32 0, v24
	s_cbranch_execz .LBB0_55
; %bb.52:                               ; %.preheader.preheader
                                        ;   in Loop: Header=BB0_2 Depth=1
	v_mov_b32_e32 v22, 0
	v_mov_b32_e32 v23, 0
	s_mov_b64 s[0:1], 0
	s_mov_b32 s6, 0
.LBB0_53:                               ; %.preheader
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	flat_load_u8 v25, v[8:9]
	v_mov_b32_e32 v26, s12
	v_add_nc_u32_e32 v24, -1, v24
	v_add_co_u32 v8, vcc_lo, v8, 1
	v_add_co_ci_u32_e32 v9, vcc_lo, 0, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_cmp_eq_u32_e32 vcc_lo, 0, v24
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_and_b32_e32 v25, 0xffff, v25
	v_lshlrev_b64 v[25:26], s0, v[25:26]
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	s_or_b32 s6, vcc_lo, s6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or_b32_e32 v23, v26, v23
	v_or_b32_e32 v22, v25, v22
	s_and_not1_b32 exec_lo, exec_lo, s6
	s_cbranch_execnz .LBB0_53
; %bb.54:                               ; %Flow142
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s6
.LBB0_55:                               ; %Flow144
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s5
                                        ; implicit-def: $vgpr8_vgpr9
.LBB0_56:                               ; %Flow146
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_and_not1_saveexec_b32 s0, s4
	s_cbranch_execz .LBB0_58
; %bb.57:                               ;   in Loop: Header=BB0_2 Depth=1
	s_clause 0x5
	flat_load_u8 v22, v[8:9]
	flat_load_u8 v23, v[8:9] offset:1
	flat_load_u8 v24, v[8:9] offset:2
	flat_load_u8 v25, v[8:9] offset:3
	flat_load_u8 v26, v[8:9] offset:5
	flat_load_u8 v27, v[8:9] offset:4
	v_mov_b32_e32 v28, v29
	s_clause 0x1
	flat_load_u8 v34, v[8:9] offset:7
	flat_load_d16_hi_u8 v28, v[8:9] offset:6
	s_waitcnt vmcnt(7) lgkmcnt(0)
	v_and_b32_e32 v8, 0xffff, v22
	s_waitcnt vmcnt(6)
	v_lshlrev_b32_e32 v9, 8, v23
	s_waitcnt vmcnt(5)
	v_lshlrev_b32_e32 v22, 16, v24
	s_waitcnt vmcnt(3)
	v_lshlrev_b32_e32 v23, 8, v26
	v_or_b32_e32 v8, v9, v8
	v_lshlrev_b32_e32 v9, 24, v25
	s_delay_alu instid0(VALU_DEP_1)
	v_or3_b32 v8, v8, v22, v9
	s_waitcnt vmcnt(2)
	v_or3_b32 v9, 0, v27, v23
	s_waitcnt vmcnt(1)
	v_lshlrev_b32_e32 v22, 24, v34
	v_or3_b32 v8, v8, 0, 0
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or3_b32 v23, v9, v28, v22
	v_or3_b32 v22, v8, 0, 0
.LBB0_58:                               ; %.loopexit
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	v_mov_b32_e32 v28, v33
	v_mov_b32_e32 v8, 0
	v_mov_b32_e32 v9, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s0, v28
	v_cmp_eq_u32_e64 s0, s0, v28
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_64
; %bb.59:                               ;   in Loop: Header=BB0_2 Depth=1
	s_waitcnt lgkmcnt(0)
	global_load_b64 v[26:27], v29, s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[8:9], v29, s[2:3] offset:40
	global_load_b64 v[24:25], v29, s[2:3]
	s_mov_b32 s4, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v9, v9, v27
	v_and_b32_e32 v8, v8, v26
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v9, v9, 24
	v_mul_hi_u32 v34, v8, 24
	v_mul_lo_u32 v8, v8, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v9, v34, v9
	s_waitcnt vmcnt(0)
	v_add_co_u32 v8, vcc_lo, v24, v8
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v9, vcc_lo, v25, v9, vcc_lo
	global_load_b64 v[24:25], v[8:9], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[8:9], v29, v[24:27], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[8:9], v[26:27]
	s_cbranch_execz .LBB0_63
; %bb.60:                               ; %.preheader3.i.i19.preheader
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_mov_b32 s5, 0
.LBB0_61:                               ; %.preheader3.i.i19
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[24:25], v29, s[2:3] offset:40
	global_load_b64 v[34:35], v29, s[2:3]
	v_dual_mov_b32 v27, v9 :: v_dual_mov_b32 v26, v8
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v24, v24, v26
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[8:9], null, v24, 24, v[34:35]
	v_and_b32_e32 v34, v25, v27
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[24:25], null, v34, 24, v[9:10]
	v_mov_b32_e32 v9, v24
	global_load_b64 v[24:25], v[8:9], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[8:9], v29, v[24:27], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[26:27]
	s_or_b32 s5, vcc_lo, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s5
	s_cbranch_execnz .LBB0_61
; %bb.62:                               ; %Flow139
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s5
.LBB0_63:                               ; %Flow141
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s4
.LBB0_64:                               ; %.loopexit4.i.i14
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_waitcnt lgkmcnt(0)
	s_clause 0x1
	global_load_b64 v[34:35], v29, s[2:3] offset:40
	global_load_b128 v[24:27], v29, s[2:3]
	v_readfirstlane_b32 s4, v8
	v_readfirstlane_b32 s5, v9
	s_mov_b32 s15, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s6, v34
	v_readfirstlane_b32 s7, v35
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[6:7], s[4:5], s[6:7]
	s_mul_i32 s1, s7, 24
	s_mul_hi_u32 s13, s6, 24
	s_mul_i32 s14, s6, 24
	s_and_saveexec_b32 s16, s0
	s_cbranch_execz .LBB0_66
; %bb.65:                               ;   in Loop: Header=BB0_2 Depth=1
	s_add_i32 s17, s13, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v34, vcc_lo, v24, s14
	v_add_co_ci_u32_e32 v35, vcc_lo, s17, v25, vcc_lo
	v_dual_mov_b32 v8, s15 :: v_dual_mov_b32 v9, v29
	global_store_b128 v[34:35], v[8:11], off offset:8
.LBB0_66:                               ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s16
	v_cmp_lt_u64_e32 vcc_lo, 56, v[4:5]
	v_or_b32_e32 v8, 0, v1
	v_or_b32_e32 v9, v0, v32
	v_lshl_add_u32 v34, v30, 2, 28
	s_lshl_b64 s[6:7], s[6:7], 12
	s_delay_alu instid0(VALU_DEP_2)
	v_dual_cndmask_b32 v1, v8, v1 :: v_dual_cndmask_b32 v0, v9, v0
	v_lshlrev_b64 v[8:9], 6, v[28:29]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v26, vcc_lo, v26, s6
	v_and_b32_e32 v34, 0x1e0, v34
	v_add_co_ci_u32_e32 v27, vcc_lo, s7, v27, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v8, vcc_lo, v26, v8
	v_and_or_b32 v0, 0xffffff1f, v0, v34
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v9, vcc_lo, v27, v9, vcc_lo
	s_clause 0x3
	global_store_b128 v[8:9], v[0:3], off
	global_store_b128 v[8:9], v[12:15], off offset:16
	global_store_b128 v[8:9], v[16:19], off offset:32
	global_store_b128 v[8:9], v[20:23], off offset:48
	s_and_saveexec_b32 s6, s0
	s_cbranch_execz .LBB0_74
; %bb.67:                               ;   in Loop: Header=BB0_2 Depth=1
	s_clause 0x1
	global_load_b64 v[16:17], v29, s[2:3] offset:32 glc
	global_load_b64 v[0:1], v29, s[2:3] offset:40
	v_dual_mov_b32 v14, s4 :: v_dual_mov_b32 v15, s5
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s16, v0
	v_readfirstlane_b32 s17, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[16:17], s[16:17], s[4:5]
	s_mul_i32 s7, s17, 24
	s_mul_hi_u32 s15, s16, 24
	s_mul_i32 s16, s16, 24
	s_add_i32 s15, s15, s7
	v_add_co_u32 v12, vcc_lo, v24, s16
	v_add_co_ci_u32_e32 v13, vcc_lo, s15, v25, vcc_lo
	s_mov_b32 s7, exec_lo
	global_store_b64 v[12:13], v[16:17], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v29, v[14:17], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[2:3], v[16:17]
	s_cbranch_execz .LBB0_70
; %bb.68:                               ; %.preheader1.i.i17.preheader
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_mov_b32 s15, 0
.LBB0_69:                               ; %.preheader1.i.i17
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s5
	s_sleep 1
	global_store_b64 v[12:13], v[2:3], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[0:1], v29, v[0:3], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
	v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
	s_or_b32 s15, vcc_lo, s15
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s15
	s_cbranch_execnz .LBB0_69
.LBB0_70:                               ; %Flow137
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s7
	global_load_b64 v[0:1], v29, s[2:3] offset:16
	s_mov_b32 s15, exec_lo
	s_mov_b32 s7, exec_lo
	v_mbcnt_lo_u32_b32 v2, s15, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB0_72
; %bb.71:                               ;   in Loop: Header=BB0_2 Depth=1
	s_bcnt1_i32_b32 s15, s15
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v28, s15
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[0:1], v[28:29], off offset:8
.LBB0_72:                               ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s7
	s_waitcnt vmcnt(0)
	global_load_b64 v[2:3], v[0:1], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
	s_cbranch_vccnz .LBB0_74
; %bb.73:                               ;   in Loop: Header=BB0_2 Depth=1
	global_load_b32 v28, v[0:1], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s7, v28
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[2:3], v[28:29], off
	s_and_b32 m0, s7, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_74:                               ; %Flow138
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s6
	s_add_i32 s13, s13, s1
	v_add_co_u32 v0, vcc_lo, v24, s14
	v_add_co_ci_u32_e32 v1, vcc_lo, s13, v25, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, 20
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
.LBB0_75:                               ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_mov_b32_e32 v2, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_77
; %bb.76:                               ;   in Loop: Header=BB0_75 Depth=2
	global_load_b32 v2, v[0:1], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v2, 1, v2
.LBB0_77:                               ;   in Loop: Header=BB0_75 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v2
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB0_79
; %bb.78:                               ;   in Loop: Header=BB0_75 Depth=2
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB0_80
.LBB0_79:                               ;   in Loop: Header=BB0_75 Depth=2
	s_mov_b32 s1, -1
.LBB0_80:                               ; %Flow132
                                        ;   in Loop: Header=BB0_75 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB0_75
; %bb.81:                               ;   in Loop: Header=BB0_2 Depth=1
	global_load_b128 v[0:3], v[8:9], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_85
; %bb.82:                               ;   in Loop: Header=BB0_2 Depth=1
	s_clause 0x2
	global_load_b64 v[2:3], v29, s[2:3] offset:40
	global_load_b64 v[8:9], v29, s[2:3] offset:24 glc
	global_load_b64 v[14:15], v29, s[2:3]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v16, vcc_lo, v2, 1
	v_add_co_ci_u32_e32 v17, vcc_lo, 0, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v12, vcc_lo, v16, s4
	v_add_co_ci_u32_e32 v13, vcc_lo, s5, v17, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[12:13]
	v_dual_cndmask_b32 v13, v13, v17 :: v_dual_cndmask_b32 v12, v12, v16
	v_and_b32_e32 v3, v13, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v2, v12, v2
	v_mul_hi_u32 v16, v2, 24
	v_mul_lo_u32 v2, v2, 24
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_u32 v2, vcc_lo, v14, v2
	v_mov_b32_e32 v14, v8
	v_mul_lo_u32 v3, v3, 24
	v_add_nc_u32_e32 v3, v16, v3
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e32 v3, vcc_lo, v15, v3, vcc_lo
	v_mov_b32_e32 v15, v9
	global_store_b64 v[2:3], v[8:9], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[14:15], v29, v[12:15], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[14:15], v[8:9]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_85
; %bb.83:                               ; %.preheader.i.i16.preheader
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_mov_b32 s0, 0
.LBB0_84:                               ; %.preheader.i.i16
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	global_store_b64 v[2:3], v[14:15], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[8:9], v29, v[12:15], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[14:15]
	v_dual_mov_b32 v15, v9 :: v_dual_mov_b32 v14, v8
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB0_84
.LBB0_85:                               ; %__ockl_hostcall_preview.exit20
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	v_sub_co_u32 v4, vcc_lo, v4, v30
	v_sub_co_ci_u32_e32 v5, vcc_lo, v5, v31, vcc_lo
	v_add_co_u32 v6, s0, v6, v30
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v7, s0, v7, v31, s0
	v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
	s_or_b32 s11, vcc_lo, s11
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s11
	s_cbranch_execnz .LBB0_2
; %bb.86:                               ; %Flow177
	s_or_b32 exec_lo, exec_lo, s11
                                        ; implicit-def: $vgpr8
.LBB0_87:                               ; %Flow193
	s_and_not1_saveexec_b32 s1, s10
	s_cbranch_execz .LBB0_116
; %bb.88:
	s_load_b64 s[2:3], s[8:9], 0x50
	s_waitcnt vmcnt(0)
	v_mbcnt_lo_u32_b32 v2, -1, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_readfirstlane_b32 s0, v2
	v_mov_b32_e32 v9, 0
	v_mov_b32_e32 v10, 0
	v_cmp_eq_u32_e64 s0, s0, v2
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s4, s0
	s_cbranch_execz .LBB0_94
; %bb.89:
	v_mov_b32_e32 v0, 0
	s_mov_b32 s5, exec_lo
	s_waitcnt lgkmcnt(0)
	global_load_b64 v[5:6], v0, s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[3:4], v0, s[2:3] offset:40
	global_load_b64 v[9:10], v0, s[2:3]
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v3, v3, v5
	v_and_b32_e32 v4, v4, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v7, v3, 24
	v_mul_lo_u32 v4, v4, 24
	v_mul_lo_u32 v3, v3, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v4, v7, v4
	s_waitcnt vmcnt(0)
	v_add_co_u32 v3, vcc_lo, v9, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, v10, v4, vcc_lo
	global_load_b64 v[3:4], v[3:4], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[9:10], v0, v[3:6], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[9:10], v[5:6]
	s_cbranch_execz .LBB0_93
; %bb.90:                               ; %.preheader3.i.i.preheader
	s_mov_b32 s6, 0
.LBB0_91:                               ; %.preheader3.i.i
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[3:4], v0, s[2:3] offset:40
	global_load_b64 v[11:12], v0, s[2:3]
	v_dual_mov_b32 v5, v9 :: v_dual_mov_b32 v6, v10
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v3, v3, v5
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[9:10], null, v3, 24, v[11:12]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v3, v10 :: v_dual_and_b32 v4, v4, v6
	v_mad_u64_u32 v[10:11], null, v4, 24, v[3:4]
	global_load_b64 v[3:4], v[9:10], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[9:10], v0, v[3:6], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[9:10], v[5:6]
	s_or_b32 s6, vcc_lo, s6
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s6
	s_cbranch_execnz .LBB0_91
; %bb.92:                               ; %Flow189
	s_or_b32 exec_lo, exec_lo, s6
.LBB0_93:                               ; %Flow191
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s5
.LBB0_94:                               ; %.loopexit4.i.i
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s4
	v_mov_b32_e32 v3, 0
	v_readfirstlane_b32 s4, v9
	v_readfirstlane_b32 s5, v10
	s_mov_b32 s11, exec_lo
	s_waitcnt lgkmcnt(0)
	s_clause 0x1
	global_load_b64 v[11:12], v3, s[2:3] offset:40
	global_load_b128 v[4:7], v3, s[2:3]
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s6, v11
	v_readfirstlane_b32 s7, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[6:7], s[4:5], s[6:7]
	s_mul_i32 s8, s7, 24
	s_mul_hi_u32 s9, s6, 24
	s_mul_i32 s10, s6, 24
	s_and_saveexec_b32 s12, s0
	s_cbranch_execz .LBB0_96
; %bb.95:
	s_add_i32 s13, s9, s8
	s_waitcnt vmcnt(0)
	v_add_co_u32 v13, vcc_lo, v4, s10
	v_add_co_ci_u32_e32 v14, vcc_lo, s13, v5, vcc_lo
	v_dual_mov_b32 v9, s11 :: v_dual_mov_b32 v10, v3
	v_dual_mov_b32 v11, 2 :: v_dual_mov_b32 v12, 1
	global_store_b128 v[13:14], v[9:12], off offset:8
.LBB0_96:
	s_or_b32 exec_lo, exec_lo, s12
	s_lshl_b64 s[6:7], s[6:7], 12
	v_lshlrev_b64 v[9:10], 6, v[2:3]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v2, vcc_lo, v6, s6
	v_add_co_ci_u32_e32 v7, vcc_lo, s7, v7, vcc_lo
	s_mov_b32 s12, 0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v6, vcc_lo, v2, v9
	s_mov_b32 s13, s12
	s_mov_b32 s14, s12
	s_mov_b32 s15, s12
	v_and_or_b32 v0, 0xffffff1f, v8, 32
	v_add_co_ci_u32_e32 v7, vcc_lo, v7, v10, vcc_lo
	v_mov_b32_e32 v2, v3
	v_dual_mov_b32 v8, s12 :: v_dual_mov_b32 v11, s15
	v_dual_mov_b32 v9, s13 :: v_dual_mov_b32 v10, s14
	s_clause 0x3
	global_store_b128 v[6:7], v[0:3], off
	global_store_b128 v[6:7], v[8:11], off offset:16
	global_store_b128 v[6:7], v[8:11], off offset:32
	global_store_b128 v[6:7], v[8:11], off offset:48
	s_and_saveexec_b32 s6, s0
	s_cbranch_execz .LBB0_104
; %bb.97:
	v_mov_b32_e32 v10, 0
	s_mov_b32 s7, exec_lo
	s_clause 0x1
	global_load_b64 v[13:14], v10, s[2:3] offset:32 glc
	global_load_b64 v[0:1], v10, s[2:3] offset:40
	v_dual_mov_b32 v11, s4 :: v_dual_mov_b32 v12, s5
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v1, s5, v1
	v_and_b32_e32 v0, s4, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v1, v1, 24
	v_mul_hi_u32 v2, v0, 24
	v_mul_lo_u32 v0, v0, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v1, v2, v1
	v_add_co_u32 v8, vcc_lo, v4, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v9, vcc_lo, v5, v1, vcc_lo
	global_store_b64 v[8:9], v[13:14], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v10, v[11:14], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[2:3], v[13:14]
	s_cbranch_execz .LBB0_100
; %bb.98:                               ; %.preheader1.i.i.preheader
	s_mov_b32 s11, 0
.LBB0_99:                               ; %.preheader1.i.i
                                        ; =>This Inner Loop Header: Depth=1
	v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s5
	s_sleep 1
	global_store_b64 v[8:9], v[2:3], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[0:1], v10, v[0:3], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
	v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
	s_or_b32 s11, vcc_lo, s11
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s11
	s_cbranch_execnz .LBB0_99
.LBB0_100:                              ; %Flow187
	s_or_b32 exec_lo, exec_lo, s7
	v_mov_b32_e32 v3, 0
	s_mov_b32 s11, exec_lo
	s_mov_b32 s7, exec_lo
	v_mbcnt_lo_u32_b32 v2, s11, 0
	global_load_b64 v[0:1], v3, s[2:3] offset:16
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB0_102
; %bb.101:
	s_bcnt1_i32_b32 s11, s11
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v2, s11
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[0:1], v[2:3], off offset:8
.LBB0_102:
	s_or_b32 exec_lo, exec_lo, s7
	s_waitcnt vmcnt(0)
	global_load_b64 v[2:3], v[0:1], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
	s_cbranch_vccnz .LBB0_104
; %bb.103:
	global_load_b32 v0, v[0:1], off offset:24
	v_mov_b32_e32 v1, 0
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s7, v0
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[2:3], v[0:1], off
	s_and_b32 m0, s7, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_104:                              ; %Flow188
	s_or_b32 exec_lo, exec_lo, s6
	s_add_i32 s9, s9, s8
	v_add_co_u32 v0, vcc_lo, v4, s10
	v_add_co_ci_u32_e32 v1, vcc_lo, s9, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, 20
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
.LBB0_105:                              ; =>This Inner Loop Header: Depth=1
	v_mov_b32_e32 v2, 1
	s_and_saveexec_b32 s6, s0
	s_cbranch_execz .LBB0_107
; %bb.106:                              ;   in Loop: Header=BB0_105 Depth=1
	global_load_b32 v2, v[0:1], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v2, 1, v2
.LBB0_107:                              ;   in Loop: Header=BB0_105 Depth=1
	s_or_b32 exec_lo, exec_lo, s6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s6, v2
	s_cmp_eq_u32 s6, 0
	s_cbranch_scc1 .LBB0_109
; %bb.108:                              ;   in Loop: Header=BB0_105 Depth=1
	s_mov_b32 s6, 0
	s_sleep 1
	s_branch .LBB0_110
.LBB0_109:                              ;   in Loop: Header=BB0_105 Depth=1
	s_mov_b32 s6, -1
.LBB0_110:                              ; %Flow182
                                        ;   in Loop: Header=BB0_105 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s6
	s_cbranch_vccnz .LBB0_105
; %bb.111:
	global_load_b128 v[0:3], v[6:7], off
	s_and_saveexec_b32 s6, s0
	s_cbranch_execz .LBB0_115
; %bb.112:
	v_mov_b32_e32 v8, 0
	s_clause 0x2
	global_load_b64 v[4:5], v8, s[2:3] offset:40
	global_load_b64 v[9:10], v8, s[2:3] offset:24 glc
	global_load_b64 v[6:7], v8, s[2:3]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v11, vcc_lo, v4, 1
	v_add_co_ci_u32_e32 v12, vcc_lo, 0, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, v11, s4
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v12, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
	v_dual_cndmask_b32 v3, v3, v12 :: v_dual_cndmask_b32 v2, v2, v11
	v_and_b32_e32 v5, v3, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v4, v2, v4
	v_mul_lo_u32 v5, v5, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v11, v4, 24
	v_mul_lo_u32 v4, v4, 24
	v_add_nc_u32_e32 v5, v11, v5
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v6, vcc_lo, v6, v4
	v_mov_b32_e32 v4, v9
	v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
	v_mov_b32_e32 v5, v10
	global_store_b64 v[6:7], v[9:10], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[4:5], v8, v[2:5], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[4:5], v[9:10]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_115
; %bb.113:                              ; %.preheader.i.i.preheader
	s_mov_b32 s0, 0
.LBB0_114:                              ; %.preheader.i.i
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	global_store_b64 v[6:7], v[4:5], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[9:10], v8, v[2:5], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[9:10], v[4:5]
	v_dual_mov_b32 v4, v9 :: v_dual_mov_b32 v5, v10
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB0_114
.LBB0_115:                              ; %__ockl_hostcall_preview.exit
	s_or_b32 exec_lo, exec_lo, s6
.LBB0_116:                              ; %Flow194
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_waitcnt vmcnt(0) lgkmcnt(0)
	s_setpc_b64 s[30:31]
.Lfunc_end0:
	.size	__ockl_printf_append_string_n, .Lfunc_end0-__ockl_printf_append_string_n
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Function info:
; codeLenInByte = 5688
; NumSgprs: 34
; NumVgprs: 36
; ScratchSize: 0
; MemoryBound: 0
	.text
	.protected	_Z13CalculateTheDiPfS_S_S_S_S_ ; -- Begin function _Z13CalculateTheDiPfS_S_S_S_S_
	.globl	_Z13CalculateTheDiPfS_S_S_S_S_
	.p2align	8
	.type	_Z13CalculateTheDiPfS_S_S_S_S_,@function
_Z13CalculateTheDiPfS_S_S_S_S_:         ; @_Z13CalculateTheDiPfS_S_S_S_S_
; %bb.0:
	s_mov_b64 s[18:19], s[0:1]
	s_load_b32 s1, s[0:1], 0x38
	v_and_b32_e32 v40, 0x3ff, v0
	v_bfe_u32 v41, v0, 10, 10
	s_add_u32 s24, s18, 56
	s_addc_u32 s25, s19, 0
	s_mov_b32 s32, 0
	v_cmp_eq_u32_e32 vcc_lo, 1, v40
	v_cmp_eq_u32_e64 s0, 1, v41
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, vcc_lo, s0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s22, s1, s15
	s_add_i32 s22, s22, s14
	s_and_saveexec_b32 s23, s0
	s_cbranch_execz .LBB1_54
; %bb.1:
	s_load_b64 s[20:21], s[24:25], 0x50
	v_mbcnt_lo_u32_b32 v38, -1, 0
	v_mov_b32_e32 v6, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v7, 0 :: v_dual_mov_b32 v4, v38
	;;#ASMSTART
	;;#ASMEND
	v_readfirstlane_b32 s0, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_eq_u32_e64 s0, s0, v4
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_7
; %bb.2:
	v_mov_b32_e32 v0, 0
	s_mov_b32 s2, exec_lo
	s_waitcnt lgkmcnt(0)
	global_load_b64 v[8:9], v0, s[20:21] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[1:2], v0, s[20:21] offset:40
	global_load_b64 v[5:6], v0, s[20:21]
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v1, v1, v8
	v_and_b32_e32 v2, v2, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v3, v1, 24
	v_mul_lo_u32 v2, v2, 24
	v_mul_lo_u32 v1, v1, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v2, v3, v2
	s_waitcnt vmcnt(0)
	v_add_co_u32 v1, vcc_lo, v5, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, v6, v2, vcc_lo
	global_load_b64 v[6:7], v[1:2], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[20:21] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[6:7], v[8:9]
	s_cbranch_execz .LBB1_6
; %bb.3:                                ; %.preheader3.i.i.i.preheader
	s_mov_b32 s3, 0
.LBB1_4:                                ; %.preheader3.i.i.i
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[1:2], v0, s[20:21] offset:40
	global_load_b64 v[10:11], v0, s[20:21]
	v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v1, v1, v8
	v_and_b32_e32 v7, v2, v9
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[5:6], null, v1, 24, v[10:11]
	v_mov_b32_e32 v1, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[2:3], null, v7, 24, v[1:2]
	v_mov_b32_e32 v6, v2
	global_load_b64 v[6:7], v[5:6], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[20:21] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[8:9]
	s_or_b32 s3, vcc_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s3
	s_cbranch_execnz .LBB1_4
; %bb.5:                                ; %Flow556
	s_or_b32 exec_lo, exec_lo, s3
.LBB1_6:                                ; %Flow558
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s2
.LBB1_7:                                ; %.loopexit4.i.i.i
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	v_mov_b32_e32 v5, 0
	v_readfirstlane_b32 s2, v6
	v_readfirstlane_b32 s3, v7
	s_mov_b32 s8, exec_lo
	s_waitcnt lgkmcnt(0)
	s_clause 0x1
	global_load_b64 v[8:9], v5, s[20:21] offset:40
	global_load_b128 v[0:3], v5, s[20:21]
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s4, v8
	v_readfirstlane_b32 s5, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[4:5], s[2:3], s[4:5]
	s_mul_i32 s1, s5, 24
	s_mul_hi_u32 s6, s4, 24
	s_mul_i32 s7, s4, 24
	s_and_saveexec_b32 s9, s0
	s_cbranch_execz .LBB1_9
; %bb.8:
	v_dual_mov_b32 v6, s8 :: v_dual_mov_b32 v7, v5
	s_add_i32 s8, s6, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v10, vcc_lo, v0, s7
	v_add_co_ci_u32_e32 v11, vcc_lo, s8, v1, vcc_lo
	v_dual_mov_b32 v8, 2 :: v_dual_mov_b32 v9, 1
	global_store_b128 v[10:11], v[6:9], off offset:8
.LBB1_9:
	s_or_b32 exec_lo, exec_lo, s9
	s_lshl_b64 s[4:5], s[4:5], 12
	v_lshlrev_b64 v[6:7], 6, v[4:5]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v2, vcc_lo, v2, s4
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
	s_mov_b32 s8, 0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v8, vcc_lo, v2, v6
	s_mov_b32 s11, s8
	s_mov_b32 s9, s8
	s_mov_b32 s10, s8
	v_add_co_ci_u32_e32 v9, vcc_lo, v3, v7, vcc_lo
	v_dual_mov_b32 v4, 33 :: v_dual_mov_b32 v7, v5
	v_dual_mov_b32 v6, v5 :: v_dual_mov_b32 v13, s11
	v_dual_mov_b32 v12, s10 :: v_dual_mov_b32 v11, s9
	v_mov_b32_e32 v10, s8
	s_clause 0x3
	global_store_b128 v[8:9], v[4:7], off
	global_store_b128 v[8:9], v[10:13], off offset:16
	global_store_b128 v[8:9], v[10:13], off offset:32
	global_store_b128 v[8:9], v[10:13], off offset:48
	s_and_saveexec_b32 s4, s0
	s_cbranch_execz .LBB1_16
; %bb.10:
	v_mov_b32_e32 v10, 0
	s_mov_b32 s5, exec_lo
	s_clause 0x1
	global_load_b64 v[13:14], v10, s[20:21] offset:32 glc
	global_load_b64 v[2:3], v10, s[20:21] offset:40
	v_dual_mov_b32 v11, s2 :: v_dual_mov_b32 v12, s3
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v3, s3, v3
	v_and_b32_e32 v2, s2, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v3, v3, 24
	v_mul_hi_u32 v4, v2, 24
	v_mul_lo_u32 v2, v2, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v3, v4, v3
	v_add_co_u32 v6, vcc_lo, v0, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v7, vcc_lo, v1, v3, vcc_lo
	global_store_b64 v[6:7], v[13:14], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[4:5], v10, v[11:14], s[20:21] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[4:5], v[13:14]
	s_cbranch_execz .LBB1_12
.LBB1_11:                               ; %.preheader1.i.i.i
                                        ; =>This Inner Loop Header: Depth=1
	v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
	s_sleep 1
	global_store_b64 v[6:7], v[4:5], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v10, v[2:5], s[20:21] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
	v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
	s_or_b32 s8, vcc_lo, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s8
	s_cbranch_execnz .LBB1_11
.LBB1_12:                               ; %Flow554
	s_or_b32 exec_lo, exec_lo, s5
	v_mov_b32_e32 v5, 0
	s_mov_b32 s8, exec_lo
	s_mov_b32 s5, exec_lo
	v_mbcnt_lo_u32_b32 v4, s8, 0
	global_load_b64 v[2:3], v5, s[20:21] offset:16
	v_cmpx_eq_u32_e32 0, v4
	s_cbranch_execz .LBB1_14
; %bb.13:
	s_bcnt1_i32_b32 s8, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v4, s8
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[2:3], v[4:5], off offset:8
.LBB1_14:
	s_or_b32 exec_lo, exec_lo, s5
	s_waitcnt vmcnt(0)
	global_load_b64 v[4:5], v[2:3], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
	s_cbranch_vccnz .LBB1_16
; %bb.15:
	global_load_b32 v2, v[2:3], off offset:24
	v_mov_b32_e32 v3, 0
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s5, v2
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[4:5], v[2:3], off
	s_and_b32 m0, s5, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB1_16:                               ; %Flow555
	s_or_b32 exec_lo, exec_lo, s4
	s_add_i32 s6, s6, s1
	v_add_co_u32 v0, vcc_lo, v0, s7
	v_add_co_ci_u32_e32 v1, vcc_lo, s6, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, 20
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
.LBB1_17:                               ; =>This Inner Loop Header: Depth=1
	v_mov_b32_e32 v2, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_19
; %bb.18:                               ;   in Loop: Header=BB1_17 Depth=1
	global_load_b32 v2, v[0:1], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v2, 1, v2
.LBB1_19:                               ;   in Loop: Header=BB1_17 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v2
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB1_21
; %bb.20:                               ;   in Loop: Header=BB1_17 Depth=1
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB1_22
.LBB1_21:                               ;   in Loop: Header=BB1_17 Depth=1
	s_mov_b32 s1, -1
.LBB1_22:                               ; %Flow549
                                        ;   in Loop: Header=BB1_17 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB1_17
; %bb.23:
	global_load_b64 v[0:1], v[8:9], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_27
; %bb.24:
	v_mov_b32_e32 v8, 0
	s_clause 0x2
	global_load_b64 v[4:5], v8, s[20:21] offset:40
	global_load_b64 v[9:10], v8, s[20:21] offset:24 glc
	global_load_b64 v[6:7], v8, s[20:21]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v11, vcc_lo, v4, 1
	v_add_co_ci_u32_e32 v12, vcc_lo, 0, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, v11, s2
	v_add_co_ci_u32_e32 v3, vcc_lo, s3, v12, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
	v_dual_cndmask_b32 v3, v3, v12 :: v_dual_cndmask_b32 v2, v2, v11
	v_and_b32_e32 v5, v3, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v4, v2, v4
	v_mul_lo_u32 v5, v5, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v11, v4, 24
	v_mul_lo_u32 v4, v4, 24
	v_add_nc_u32_e32 v5, v11, v5
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v6, vcc_lo, v6, v4
	v_mov_b32_e32 v4, v9
	v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
	v_mov_b32_e32 v5, v10
	global_store_b64 v[6:7], v[9:10], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[4:5], v8, v[2:5], s[20:21] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[4:5], v[9:10]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB1_27
; %bb.25:                               ; %.preheader.i.i.i.preheader
	s_mov_b32 s0, 0
.LBB1_26:                               ; %.preheader.i.i.i
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	global_store_b64 v[6:7], v[4:5], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[9:10], v8, v[2:5], s[20:21] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[9:10], v[4:5]
	v_dual_mov_b32 v4, v9 :: v_dual_mov_b32 v5, v10
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB1_26
.LBB1_27:                               ; %__ockl_printf_begin.exit
	s_or_b32 exec_lo, exec_lo, s1
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, .str@rel32@lo+4
	s_addc_u32 s1, s1, .str@rel32@hi+12
	s_delay_alu instid0(SALU_CYCLE_1)
	v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
	s_cmp_lg_u64 s[0:1], 0
	v_mov_b32_e32 v5, 0
	s_cselect_b32 s4, 12, 0
	s_add_u32 s8, s18, 56
	v_mov_b32_e32 v4, s4
	s_addc_u32 s9, s19, 0
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, __ockl_printf_append_string_n@rel32@lo+4
	s_addc_u32 s3, s3, __ockl_printf_append_string_n@rel32@hi+12
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_3)
	s_swappc_b64 s[30:31], s[2:3]
	;;#ASMSTART
	;;#ASMEND
	v_readfirstlane_b32 s0, v38
	v_mov_b32_e32 v5, 0
	v_dual_mov_b32 v37, v1 :: v_dual_mov_b32 v6, 0
	v_cmp_eq_u32_e64 s0, s0, v38
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_33
; %bb.28:
	v_mov_b32_e32 v1, 0
	s_mov_b32 s2, exec_lo
	global_load_b64 v[7:8], v1, s[20:21] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[2:3], v1, s[20:21] offset:40
	global_load_b64 v[4:5], v1, s[20:21]
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v2, v2, v7
	v_and_b32_e32 v3, v3, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v6, v2, 24
	v_mul_lo_u32 v3, v3, 24
	v_mul_lo_u32 v2, v2, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v3, v6, v3
	s_waitcnt vmcnt(0)
	v_add_co_u32 v2, vcc_lo, v4, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, v5, v3, vcc_lo
	global_load_b64 v[5:6], v[2:3], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[5:6], v1, v[5:8], s[20:21] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[5:6], v[7:8]
	s_cbranch_execz .LBB1_32
; %bb.29:                               ; %.preheader3.i.i.i179.preheader
	s_mov_b32 s3, 0
.LBB1_30:                               ; %.preheader3.i.i.i179
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[2:3], v1, s[20:21] offset:40
	global_load_b64 v[9:10], v1, s[20:21]
	v_dual_mov_b32 v8, v6 :: v_dual_mov_b32 v7, v5
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v2, v2, v7
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[4:5], null, v2, 24, v[9:10]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v2, v5 :: v_dual_and_b32 v3, v3, v8
	v_mad_u64_u32 v[5:6], null, v3, 24, v[2:3]
	global_load_b64 v[5:6], v[4:5], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[5:6], v1, v[5:8], s[20:21] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[5:6], v[7:8]
	s_or_b32 s3, vcc_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s3
	s_cbranch_execnz .LBB1_30
; %bb.31:                               ; %Flow542
	s_or_b32 exec_lo, exec_lo, s3
.LBB1_32:                               ; %Flow544
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s2
.LBB1_33:                               ; %.loopexit4.i.i.i174
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	v_mov_b32_e32 v39, 0
	v_readfirstlane_b32 s2, v5
	v_readfirstlane_b32 s3, v6
	s_mov_b32 s8, exec_lo
	s_clause 0x1
	global_load_b64 v[7:8], v39, s[20:21] offset:40
	global_load_b128 v[1:4], v39, s[20:21]
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s4, v7
	v_readfirstlane_b32 s5, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[4:5], s[2:3], s[4:5]
	s_mul_i32 s1, s5, 24
	s_mul_hi_u32 s6, s4, 24
	s_mul_i32 s7, s4, 24
	s_and_saveexec_b32 s9, s0
	s_cbranch_execz .LBB1_35
; %bb.34:
	v_dual_mov_b32 v5, s8 :: v_dual_mov_b32 v6, v39
	s_add_i32 s8, s6, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v9, vcc_lo, v1, s7
	v_add_co_ci_u32_e32 v10, vcc_lo, s8, v2, vcc_lo
	v_dual_mov_b32 v7, 2 :: v_dual_mov_b32 v8, 1
	global_store_b128 v[9:10], v[5:8], off offset:8
.LBB1_35:
	s_or_b32 exec_lo, exec_lo, s9
	s_lshl_b64 s[4:5], s[4:5], 12
	v_lshlrev_b64 v[5:6], 6, v[38:39]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v3, vcc_lo, v3, s4
	v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
	s_mov_b32 s8, 0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v7, vcc_lo, v3, v5
	s_mov_b32 s9, s8
	s_mov_b32 s10, s8
	s_mov_b32 s11, s8
	v_and_or_b32 v36, 0xffffff1d, v0, 34
	v_add_co_ci_u32_e32 v8, vcc_lo, v4, v6, vcc_lo
	v_dual_mov_b32 v38, s22 :: v_dual_mov_b32 v3, s8
	v_dual_mov_b32 v4, s9 :: v_dual_mov_b32 v5, s10
	v_mov_b32_e32 v6, s11
	s_clause 0x3
	global_store_b128 v[7:8], v[36:39], off
	global_store_b128 v[7:8], v[3:6], off offset:16
	global_store_b128 v[7:8], v[3:6], off offset:32
	global_store_b128 v[7:8], v[3:6], off offset:48
	s_and_saveexec_b32 s4, s0
	s_cbranch_execz .LBB1_43
; %bb.36:
	v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v9, s2
	v_mov_b32_e32 v10, s3
	s_clause 0x1
	global_load_b64 v[11:12], v0, s[20:21] offset:32 glc
	global_load_b64 v[3:4], v0, s[20:21] offset:40
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s8, v3
	v_readfirstlane_b32 s9, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[8:9], s[8:9], s[2:3]
	s_mul_i32 s5, s9, 24
	s_mul_hi_u32 s9, s8, 24
	s_mul_i32 s8, s8, 24
	s_add_i32 s9, s9, s5
	v_add_co_u32 v7, vcc_lo, v1, s8
	v_add_co_ci_u32_e32 v8, vcc_lo, s9, v2, vcc_lo
	s_mov_b32 s5, exec_lo
	global_store_b64 v[7:8], v[11:12], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[5:6], v0, v[9:12], s[20:21] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[5:6], v[11:12]
	s_cbranch_execz .LBB1_39
; %bb.37:                               ; %.preheader1.i.i.i177.preheader
	s_mov_b32 s8, 0
.LBB1_38:                               ; %.preheader1.i.i.i177
                                        ; =>This Inner Loop Header: Depth=1
	v_dual_mov_b32 v3, s2 :: v_dual_mov_b32 v4, s3
	s_sleep 1
	global_store_b64 v[7:8], v[5:6], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[3:4], v0, v[3:6], s[20:21] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[3:4], v[5:6]
	v_dual_mov_b32 v6, v4 :: v_dual_mov_b32 v5, v3
	s_or_b32 s8, vcc_lo, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s8
	s_cbranch_execnz .LBB1_38
.LBB1_39:                               ; %Flow540
	s_or_b32 exec_lo, exec_lo, s5
	v_mov_b32_e32 v6, 0
	s_mov_b32 s8, exec_lo
	s_mov_b32 s5, exec_lo
	v_mbcnt_lo_u32_b32 v0, s8, 0
	global_load_b64 v[3:4], v6, s[20:21] offset:16
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB1_41
; %bb.40:
	s_bcnt1_i32_b32 s8, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v5, s8
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[3:4], v[5:6], off offset:8
.LBB1_41:
	s_or_b32 exec_lo, exec_lo, s5
	s_waitcnt vmcnt(0)
	global_load_b64 v[5:6], v[3:4], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[5:6]
	s_cbranch_vccnz .LBB1_43
; %bb.42:
	global_load_b32 v3, v[3:4], off offset:24
	v_mov_b32_e32 v4, 0
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s5, v3
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[5:6], v[3:4], off
	s_and_b32 m0, s5, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB1_43:                               ; %Flow541
	s_or_b32 exec_lo, exec_lo, s4
	s_add_i32 s6, s6, s1
	v_add_co_u32 v0, vcc_lo, v1, s7
	v_add_co_ci_u32_e32 v1, vcc_lo, s6, v2, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, 20
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
.LBB1_44:                               ; =>This Inner Loop Header: Depth=1
	v_mov_b32_e32 v2, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_46
; %bb.45:                               ;   in Loop: Header=BB1_44 Depth=1
	global_load_b32 v2, v[0:1], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v2, 1, v2
.LBB1_46:                               ;   in Loop: Header=BB1_44 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v2
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB1_48
; %bb.47:                               ;   in Loop: Header=BB1_44 Depth=1
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB1_49
.LBB1_48:                               ;   in Loop: Header=BB1_44 Depth=1
	s_mov_b32 s1, -1
.LBB1_49:                               ; %Flow535
                                        ;   in Loop: Header=BB1_44 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB1_44
; %bb.50:
	s_and_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB1_54
; %bb.51:
	v_mov_b32_e32 v6, 0
	s_clause 0x2
	global_load_b64 v[2:3], v6, s[20:21] offset:40
	global_load_b64 v[7:8], v6, s[20:21] offset:24 glc
	global_load_b64 v[4:5], v6, s[20:21]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v9, vcc_lo, v2, 1
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v9, s2
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
	v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
	v_and_b32_e32 v3, v1, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v2, v0, v2
	v_mul_lo_u32 v3, v3, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v9, v2, 24
	v_mul_lo_u32 v2, v2, 24
	v_add_nc_u32_e32 v3, v9, v3
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v4, vcc_lo, v4, v2
	v_mov_b32_e32 v2, v7
	v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
	v_mov_b32_e32 v3, v8
	global_store_b64 v[4:5], v[7:8], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[20:21] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB1_54
; %bb.52:                               ; %.preheader.i.i.i176.preheader
	s_mov_b32 s0, 0
.LBB1_53:                               ; %.preheader.i.i.i176
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	global_store_b64 v[4:5], v[2:3], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[20:21] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
	v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB1_53
.LBB1_54:                               ; %Flow559
	s_or_b32 exec_lo, exec_lo, s23
	v_lshlrev_b32_e32 v0, 4, v41
	s_lshl_b32 s0, s22, 8
	s_mov_b32 s33, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v0, v0, v40, s0
	v_cmpx_gt_i32_e32 0x3c1, v0
	s_cbranch_execz .LBB1_178
; %bb.55:                               ; %.preheader217
	v_mul_hi_i32 v1, 0x84210843, v0
	s_clause 0x3
	s_load_b32 s75, s[18:19], 0x0
	s_load_b128 s[4:7], s[18:19], 0x8
	s_load_b128 s[8:11], s[18:19], 0x28
	s_load_b64 s[26:27], s[18:19], 0x18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v6, 0 :: v_dual_add_nc_u32 v1, v1, v0
	v_lshrrev_b32_e32 v2, 31, v1
	v_ashrrev_i32_e32 v1, 4, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v38, v1, v2
	s_waitcnt lgkmcnt(0)
	s_bitcmp0_b32 s75, 0
	s_cselect_b32 s74, -1, 0
	v_mul_lo_u32 v3, v38, 31
	s_and_b32 s0, s74, exec_lo
	s_cselect_b32 s3, s8, s4
	s_cselect_b32 s2, s9, s5
	s_mov_b64 s[0:1], 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v4, 31, v3
	v_sub_nc_u32_e32 v5, v0, v3
	v_lshlrev_b64 v[1:2], 2, v[3:4]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v3, v5
	v_add_co_u32 v51, vcc_lo, s3, v1
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v52, vcc_lo, s2, v2, vcc_lo
.LBB1_56:                               ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_ashrrev_i32_e32 v4, 31, v3
	v_add_co_u32 v7, vcc_lo, v51, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v8, vcc_lo, s1, v52, vcc_lo
	v_lshlrev_b64 v[9:10], 2, v[3:4]
	v_add_nc_u32_e32 v3, 31, v3
	s_add_u32 s0, s0, 4
	s_addc_u32 s1, s1, 0
	s_cmpk_lg_i32 s0, 0x7c
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v9, vcc_lo, s3, v9
	v_add_co_ci_u32_e32 v10, vcc_lo, s2, v10, vcc_lo
	s_clause 0x1
	global_load_b32 v4, v[7:8], off
	global_load_b32 v7, v[9:10], off
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v6, v4, v7
	s_cbranch_scc1 .LBB1_56
; %bb.57:                               ; %.preheader216.preheader
	s_and_b32 s0, s74, exec_lo
	s_cselect_b32 s3, s10, s6
	s_cselect_b32 s2, s11, s7
	v_add_co_u32 v53, vcc_lo, s3, v1
	v_add_co_ci_u32_e32 v54, vcc_lo, s2, v2, vcc_lo
	v_mov_b32_e32 v3, 0
	v_mov_b32_e32 v1, v5
	s_mov_b64 s[0:1], 0
.LBB1_58:                               ; %.preheader216
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_ashrrev_i32_e32 v2, 31, v1
	v_add_co_u32 v7, vcc_lo, v53, s0
	v_add_co_ci_u32_e32 v8, vcc_lo, s1, v54, vcc_lo
	v_lshlrev_b64 v[9:10], 2, v[1:2]
	v_add_nc_u32_e32 v1, 31, v1
	s_add_u32 s0, s0, 4
	s_addc_u32 s1, s1, 0
	s_cmpk_eq_i32 s0, 0x7c
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v9, vcc_lo, s3, v9
	v_add_co_ci_u32_e32 v10, vcc_lo, s2, v10, vcc_lo
	s_clause 0x1
	global_load_b32 v2, v[7:8], off
	global_load_b32 v4, v[9:10], off
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v3, v2, v4
	s_cbranch_scc0 .LBB1_58
; %bb.59:
	s_sub_i32 s0, 5, s75
	s_cmp_eq_u32 s75, 5
	s_mov_b32 s20, 0
	s_cselect_b32 s21, 0x3ff00000, 2.0
	s_mov_b32 s2, 0x55555555
	v_frexp_mant_f64_e32 v[1:2], s[20:21]
	s_mov_b32 s3, 0x3fe55555
	s_mov_b32 s12, 0x968915a9
	s_mov_b32 s14, 0x4222de17
	s_mov_b32 s13, 0x3fba6564
	s_mov_b32 s15, 0x3fbdee67
	s_mov_b32 s16, 0x3abe935a
	s_mov_b32 s17, 0x3fbe25e4
	s_mov_b32 s22, 0x47e6c9c2
	s_mov_b32 s23, 0x3fc110ef
	s_mov_b32 s28, 0xcfa74449
	s_mov_b32 s29, 0x3fc3b13b
	s_mov_b32 s30, 0x71bf3c30
	s_mov_b32 s31, 0x3fc745d1
	s_mov_b32 s34, 0x1c7792ce
	s_mov_b32 s35, 0x3fcc71c7
	s_mov_b32 s36, 0x924920da
	s_mov_b32 s37, 0x3fd24924
	s_mov_b32 s38, 0x9999999c
	s_mov_b32 s39, 0x3fd99999
	s_mov_b32 s41, 0xbfe55555
	s_mov_b32 s40, s2
	s_mov_b32 s42, 0xd5df274d
	s_mov_b32 s43, 0x3c8543b0
	s_mov_b32 s44, 0xfefa39ef
	s_mov_b32 s45, 0x3fe62e42
	s_mov_b32 s48, 0x3b39803f
	s_mov_b32 s49, 0x3c7abc9e
	s_mov_b32 s46, 0x652b82fe
	s_mov_b32 s47, 0x3ff71547
	s_mov_b32 s51, 0xbfe62e42
	s_mov_b32 s50, s44
	s_mov_b32 s53, 0xbc7abc9e
	s_mov_b32 s52, s48
	s_mov_b32 s54, 0xfca7ab0c
	s_mov_b32 s56, 0x6a5dcb37
	s_mov_b32 s55, 0x3e928af3
	s_mov_b32 s57, 0x3e5ade15
	v_cmp_gt_f64_e32 vcc_lo, s[2:3], v[1:2]
	s_mov_b32 s58, 0x623fde64
	s_mov_b32 s59, 0x3ec71dee
	s_mov_b32 s60, 0x7c89e6b0
	s_mov_b32 s61, 0x3efa0199
	s_mov_b32 s62, 0x14761f6e
	s_mov_b32 s63, 0x3f2a01a0
	s_mov_b32 s64, 0x1852b7b0
	s_mov_b32 s65, 0x3f56c16c
	s_mov_b32 s66, 0x11122322
	s_mov_b32 s67, 0x3f811111
	s_mov_b32 s68, 0x555502a1
	s_mov_b32 s69, 0x3fa55555
	s_mov_b32 s70, 0x55555511
	s_mov_b32 s71, 0x3fc55555
	s_mov_b32 s72, 11
	s_mov_b32 s73, 0x3fe00000
	v_cndmask_b32_e64 v4, 0, 1, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_ldexp_f64 v[1:2], v[1:2], v4
	v_frexp_exp_i32_f64_e32 v4, s[20:21]
	v_add_f64 v[7:8], v[1:2], 1.0
	v_add_f64 v[13:14], v[1:2], -1.0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_subrev_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
	v_rcp_f64_e32 v[9:10], v[7:8]
	v_add_f64 v[15:16], v[7:8], -1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_f64 v[1:2], v[1:2], -v[15:16]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[11:12], -v[7:8], v[9:10], 1.0
	v_fma_f64 v[9:10], v[11:12], v[9:10], v[9:10]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[11:12], -v[7:8], v[9:10], 1.0
	v_fma_f64 v[9:10], v[11:12], v[9:10], v[9:10]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[11:12], v[13:14], v[9:10]
	v_mul_f64 v[17:18], v[7:8], v[11:12]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[7:8], v[11:12], v[7:8], -v[17:18]
	v_fma_f64 v[1:2], v[11:12], v[1:2], v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[7:8], v[17:18], v[1:2]
	v_add_f64 v[15:16], v[13:14], -v[7:8]
	v_add_f64 v[17:18], v[7:8], -v[17:18]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[13:14], v[13:14], -v[15:16]
	v_add_f64 v[1:2], v[17:18], -v[1:2]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[7:8], v[13:14], -v[7:8]
	v_add_f64 v[1:2], v[1:2], v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[1:2], v[15:16], v[1:2]
	v_mul_f64 v[1:2], v[9:10], v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[7:8], v[11:12], v[1:2]
	v_add_f64 v[9:10], v[7:8], -v[11:12]
	v_mul_f64 v[11:12], v[7:8], v[7:8]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[1:2], v[1:2], -v[9:10]
	v_fma_f64 v[9:10], v[7:8], v[7:8], -v[11:12]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[13:14], v[1:2], v[1:2]
	v_fma_f64 v[9:10], v[7:8], v[13:14], v[9:10]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[13:14], v[11:12], v[9:10]
	v_fma_f64 v[15:16], v[13:14], s[14:15], s[12:13]
	v_add_f64 v[11:12], v[13:14], -v[11:12]
	v_mul_f64 v[21:22], v[7:8], v[13:14]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[15:16], v[13:14], v[15:16], s[16:17]
	v_add_f64 v[9:10], v[9:10], -v[11:12]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[15:16], v[13:14], v[15:16], s[22:23]
	v_fma_f64 v[15:16], v[13:14], v[15:16], s[28:29]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[15:16], v[13:14], v[15:16], s[30:31]
	v_fma_f64 v[15:16], v[13:14], v[15:16], s[34:35]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[15:16], v[13:14], v[15:16], s[36:37]
	v_fma_f64 v[15:16], v[13:14], v[15:16], s[38:39]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[17:18], v[13:14], v[15:16]
	v_fma_f64 v[11:12], v[13:14], v[15:16], -v[17:18]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[11:12], v[9:10], v[15:16], v[11:12]
	v_add_f64 v[15:16], v[17:18], v[11:12]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[19:20], v[15:16], s[2:3]
	v_add_f64 v[17:18], v[15:16], -v[17:18]
	v_add_f64 v[23:24], v[19:20], s[40:41]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[11:12], v[11:12], -v[17:18]
	v_fma_f64 v[17:18], v[13:14], v[7:8], -v[21:22]
	v_add_f64 v[15:16], v[15:16], -v[23:24]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[11:12], v[11:12], s[42:43]
	v_fma_f64 v[13:14], v[13:14], v[1:2], v[17:18]
	v_ldexp_f64 v[1:2], v[1:2], 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[11:12], v[11:12], v[15:16]
	v_fma_f64 v[9:10], v[9:10], v[7:8], v[13:14]
	v_ldexp_f64 v[7:8], v[7:8], 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[13:14], v[19:20], v[11:12]
	v_add_f64 v[15:16], v[21:22], v[9:10]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[17:18], v[19:20], -v[13:14]
	v_mul_f64 v[19:20], v[15:16], v[13:14]
	v_add_f64 v[21:22], v[15:16], -v[21:22]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[11:12], v[11:12], v[17:18]
	v_fma_f64 v[17:18], v[15:16], v[13:14], -v[19:20]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[9:10], v[9:10], -v[21:22]
	v_fma_f64 v[11:12], v[15:16], v[11:12], v[17:18]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f64 v[9:10], v[9:10], v[13:14], v[11:12]
	v_cvt_f64_i32_e32 v[13:14], v4
	v_add_f64 v[11:12], v[19:20], v[9:10]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f64 v[15:16], v[7:8], v[11:12]
	v_add_f64 v[17:18], v[11:12], -v[19:20]
	v_mul_f64 v[19:20], v[13:14], s[44:45]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[7:8], v[15:16], -v[7:8]
	v_add_f64 v[9:10], v[9:10], -v[17:18]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[17:18], v[13:14], s[44:45], -v[19:20]
	v_add_f64 v[7:8], v[11:12], -v[7:8]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[1:2], v[1:2], v[9:10]
	v_fma_f64 v[9:10], v[13:14], s[48:49], v[17:18]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[1:2], v[1:2], v[7:8]
	v_add_f64 v[7:8], v[19:20], v[9:10]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[11:12], v[15:16], v[1:2]
	v_add_f64 v[19:20], v[7:8], -v[19:20]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[13:14], v[7:8], v[11:12]
	v_add_f64 v[15:16], v[11:12], -v[15:16]
	v_add_f64 v[9:10], v[9:10], -v[19:20]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[17:18], v[13:14], -v[7:8]
	v_add_f64 v[1:2], v[1:2], -v[15:16]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[21:22], v[13:14], -v[17:18]
	v_add_f64 v[11:12], v[11:12], -v[17:18]
	v_add_f64 v[15:16], v[9:10], v[1:2]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[7:8], v[7:8], -v[21:22]
	v_add_f64 v[7:8], v[11:12], v[7:8]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[11:12], v[15:16], -v[9:10]
	v_add_f64 v[7:8], v[15:16], v[7:8]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[15:16], v[15:16], -v[11:12]
	v_add_f64 v[1:2], v[1:2], -v[11:12]
	v_add_f64 v[17:18], v[13:14], v[7:8]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[9:10], v[9:10], -v[15:16]
	v_add_f64 v[11:12], v[17:18], -v[13:14]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[1:2], v[1:2], v[9:10]
	v_cvt_f64_i32_e32 v[9:10], s0
	v_add_f64 v[7:8], v[7:8], -v[11:12]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[1:2], v[1:2], v[7:8]
	v_add_f64 v[7:8], v[17:18], v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[11:12], v[7:8], -v[17:18]
	v_mul_f64 v[13:14], v[7:8], v[9:10]
	v_add_f64 v[1:2], v[1:2], -v[11:12]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f64 v[7:8], v[9:10], v[7:8], -v[13:14]
	v_cmp_class_f64_e64 vcc_lo, v[13:14], 0x204
	v_fma_f64 v[1:2], v[9:10], v[1:2], v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[7:8], v[13:14], v[1:2]
	v_dual_cndmask_b32 v10, v8, v14 :: v_dual_cndmask_b32 v9, v7, v13
	v_add_f64 v[7:8], v[7:8], -v[13:14]
	s_delay_alu instid0(VALU_DEP_2)
	v_mul_f64 v[11:12], v[9:10], s[46:47]
	v_cmp_nlt_f64_e64 s0, 0x40900000, v[9:10]
	v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[9:10]|
	v_cmp_ngt_f64_e64 s1, 0xc090cc00, v[9:10]
	v_add_f64 v[1:2], v[1:2], -v[7:8]
	v_rndne_f64_e32 v[11:12], v[11:12]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_cndmask_b32 v2, 0, v2 :: v_dual_cndmask_b32 v1, 0, v1
	s_and_b32 vcc_lo, s1, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f64 v[15:16], v[11:12], s[50:51], v[9:10]
	v_cvt_i32_f64_e32 v4, v[11:12]
	v_fma_f64 v[15:16], v[11:12], s[52:53], v[15:16]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[17:18], v[15:16], s[56:57], s[54:55]
	v_fma_f64 v[17:18], v[15:16], v[17:18], s[58:59]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[17:18], v[15:16], v[17:18], s[60:61]
	v_fma_f64 v[17:18], v[15:16], v[17:18], s[62:63]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[17:18], v[15:16], v[17:18], s[64:65]
	v_fma_f64 v[17:18], v[15:16], v[17:18], s[66:67]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[17:18], v[15:16], v[17:18], s[68:69]
	v_fma_f64 v[17:18], v[15:16], v[17:18], s[70:71]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[17:18], v[15:16], v[17:18], s[72:73]
	v_fma_f64 v[17:18], v[15:16], v[17:18], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[11:12], v[15:16], v[17:18], 1.0
	v_ldexp_f64 v[11:12], v[11:12], v4
	s_delay_alu instid0(VALU_DEP_1)
	v_cndmask_b32_e64 v4, 0x7ff00000, v12, s0
	s_and_b32 s0, s74, exec_lo
	s_cselect_b32 s0, s5, s9
	s_cselect_b32 s5, s6, s10
	s_mov_b32 s74, 1
	v_cndmask_b32_e64 v8, 0, v4, s1
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v7, 0, v11, vcc_lo
	s_cselect_b32 s1, s4, s8
	s_cselect_b32 s4, s7, s11
	v_fma_f64 v[1:2], v[7:8], v[1:2], v[7:8]
	v_cmp_class_f64_e64 vcc_lo, v[7:8], 0x204
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_cndmask_b32 v2, v2, v8 :: v_dual_cndmask_b32 v1, v1, v7
	v_cvt_i32_f64_e64 v55, |v[1:2]|
	v_ashrrev_i32_e32 v1, 31, v0
	v_fma_f32 v2, v3, 2.0, -v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	v_add_co_u32 v6, vcc_lo, s1, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v7, vcc_lo, s0, v1, vcc_lo
	v_add_co_u32 v0, vcc_lo, s5, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s4, v1, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 0, v5
	global_store_b32 v[6:7], v2, off
	global_store_b32 v[0:1], v3, off
	v_readfirstlane_b32 s0, v55
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_cmp_gt_i32 s0, 1
	s_cselect_b32 s0, -1, 0
	s_and_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB1_178
; %bb.60:                               ; %.preheader214.lr.ph
	s_sub_i32 s0, 7, s75
	s_cmp_eq_u32 s75, 7
	v_mov_b32_e32 v42, 0
	s_cselect_b32 s21, 0x3ff00000, 2.0
	v_mbcnt_lo_u32_b32 v56, -1, 0
	v_frexp_mant_f64_e32 v[0:1], s[20:21]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_mov_b32 v46, 1 :: v_dual_mov_b32 v39, v42
	v_dual_mov_b32 v40, 33 :: v_dual_mov_b32 v45, 2
	v_cmp_gt_f64_e32 vcc_lo, s[2:3], v[0:1]
	v_cndmask_b32_e64 v2, 0, 1, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ldexp_f64 v[0:1], v[0:1], v2
	v_add_f64 v[2:3], v[0:1], 1.0
	v_add_f64 v[8:9], v[0:1], -1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[4:5], v[2:3]
	v_add_f64 v[10:11], v[2:3], -1.0
	v_add_f64 v[0:1], v[0:1], -v[10:11]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[4:5], v[6:7], v[4:5], v[4:5]
	v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[4:5], v[6:7], v[4:5], v[4:5]
	v_mul_f64 v[6:7], v[8:9], v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[12:13], v[2:3], v[6:7]
	v_fma_f64 v[2:3], v[6:7], v[2:3], -v[12:13]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[0:1], v[6:7], v[0:1], v[2:3]
	v_add_f64 v[2:3], v[12:13], v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[10:11], v[8:9], -v[2:3]
	v_add_f64 v[12:13], v[2:3], -v[12:13]
	v_add_f64 v[8:9], v[8:9], -v[10:11]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[0:1], v[12:13], -v[0:1]
	v_add_f64 v[2:3], v[8:9], -v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[0:1], v[0:1], v[2:3]
	v_add_f64 v[0:1], v[10:11], v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[0:1], v[4:5], v[0:1]
	v_add_f64 v[2:3], v[6:7], v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[4:5], v[2:3], -v[6:7]
	v_mul_f64 v[6:7], v[2:3], v[2:3]
	v_add_f64 v[0:1], v[0:1], -v[4:5]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[4:5], v[2:3], v[2:3], -v[6:7]
	v_add_f64 v[8:9], v[0:1], v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[4:5], v[2:3], v[8:9], v[4:5]
	v_add_f64 v[8:9], v[6:7], v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_fma_f64 v[10:11], v[8:9], s[14:15], s[12:13]
	v_add_f64 v[6:7], v[8:9], -v[6:7]
	v_mul_f64 v[16:17], v[2:3], v[8:9]
	v_fma_f64 v[10:11], v[8:9], v[10:11], s[16:17]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[4:5], v[4:5], -v[6:7]
	v_fma_f64 v[10:11], v[8:9], v[10:11], s[22:23]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[10:11], v[8:9], v[10:11], s[28:29]
	v_fma_f64 v[10:11], v[8:9], v[10:11], s[30:31]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[10:11], v[8:9], v[10:11], s[34:35]
	v_fma_f64 v[10:11], v[8:9], v[10:11], s[36:37]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[10:11], v[8:9], v[10:11], s[38:39]
	v_mul_f64 v[12:13], v[8:9], v[10:11]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[6:7], v[8:9], v[10:11], -v[12:13]
	v_fma_f64 v[6:7], v[4:5], v[10:11], v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[10:11], v[12:13], v[6:7]
	v_add_f64 v[14:15], v[10:11], s[2:3]
	v_add_f64 v[12:13], v[10:11], -v[12:13]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[18:19], v[14:15], s[40:41]
	v_add_f64 v[6:7], v[6:7], -v[12:13]
	v_fma_f64 v[12:13], v[8:9], v[2:3], -v[16:17]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[10:11], v[10:11], -v[18:19]
	v_add_f64 v[6:7], v[6:7], s[42:43]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fma_f64 v[8:9], v[8:9], v[0:1], v[12:13]
	v_ldexp_f64 v[0:1], v[0:1], 1
	v_add_f64 v[6:7], v[6:7], v[10:11]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fma_f64 v[4:5], v[4:5], v[2:3], v[8:9]
	v_ldexp_f64 v[2:3], v[2:3], 1
	v_add_f64 v[8:9], v[14:15], v[6:7]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[10:11], v[16:17], v[4:5]
	v_add_f64 v[12:13], v[14:15], -v[8:9]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_f64 v[14:15], v[10:11], v[8:9]
	v_add_f64 v[16:17], v[10:11], -v[16:17]
	v_add_f64 v[6:7], v[6:7], v[12:13]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[12:13], v[10:11], v[8:9], -v[14:15]
	v_add_f64 v[4:5], v[4:5], -v[16:17]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[6:7], v[10:11], v[6:7], v[12:13]
	v_fma_f64 v[4:5], v[4:5], v[8:9], v[6:7]
	v_frexp_exp_i32_f64_e32 v8, s[20:21]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[6:7], v[14:15], v[4:5]
	v_subrev_co_ci_u32_e32 v8, vcc_lo, 0, v8, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cvt_f64_i32_e32 v[8:9], v8
	v_add_f64 v[10:11], v[2:3], v[6:7]
	v_add_f64 v[12:13], v[6:7], -v[14:15]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f64 v[14:15], v[8:9], s[44:45]
	v_add_f64 v[2:3], v[10:11], -v[2:3]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[4:5], v[4:5], -v[12:13]
	v_fma_f64 v[12:13], v[8:9], s[44:45], -v[14:15]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[2:3], v[6:7], -v[2:3]
	v_add_f64 v[0:1], v[0:1], v[4:5]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[4:5], v[8:9], s[48:49], v[12:13]
	v_add_f64 v[0:1], v[0:1], v[2:3]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[2:3], v[14:15], v[4:5]
	v_add_f64 v[6:7], v[10:11], v[0:1]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[14:15], v[2:3], -v[14:15]
	v_add_f64 v[8:9], v[2:3], v[6:7]
	v_add_f64 v[10:11], v[6:7], -v[10:11]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[4:5], v[4:5], -v[14:15]
	v_add_f64 v[12:13], v[8:9], -v[2:3]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[0:1], v[0:1], -v[10:11]
	v_add_f64 v[16:17], v[8:9], -v[12:13]
	v_add_f64 v[6:7], v[6:7], -v[12:13]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[10:11], v[4:5], v[0:1]
	v_add_f64 v[2:3], v[2:3], -v[16:17]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[2:3], v[6:7], v[2:3]
	v_add_f64 v[6:7], v[10:11], -v[4:5]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[2:3], v[10:11], v[2:3]
	v_add_f64 v[10:11], v[10:11], -v[6:7]
	v_add_f64 v[0:1], v[0:1], -v[6:7]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[12:13], v[8:9], v[2:3]
	v_add_f64 v[4:5], v[4:5], -v[10:11]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[6:7], v[12:13], -v[8:9]
	v_add_f64 v[0:1], v[0:1], v[4:5]
	v_cvt_f64_i32_e32 v[4:5], s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[2:3], v[2:3], -v[6:7]
	v_add_f64 v[0:1], v[0:1], v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[2:3], v[12:13], v[0:1]
	v_add_f64 v[6:7], v[2:3], -v[12:13]
	v_mul_f64 v[8:9], v[2:3], v[4:5]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[0:1], v[0:1], -v[6:7]
	v_fma_f64 v[2:3], v[4:5], v[2:3], -v[8:9]
	v_cmp_class_f64_e64 vcc_lo, v[8:9], 0x204
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[0:1], v[4:5], v[0:1], v[2:3]
	v_add_f64 v[2:3], v[8:9], v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v5, v3, v9 :: v_dual_cndmask_b32 v4, v2, v8
	v_add_f64 v[2:3], v[2:3], -v[8:9]
	v_mul_f64 v[6:7], v[4:5], s[46:47]
	v_cmp_nlt_f64_e64 s0, 0x40900000, v[4:5]
	v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[4:5]|
	v_cmp_ngt_f64_e64 s1, 0xc090cc00, v[4:5]
	v_add_f64 v[0:1], v[0:1], -v[2:3]
	v_rndne_f64_e32 v[6:7], v[6:7]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_cndmask_b32 v1, 0, v1 :: v_dual_cndmask_b32 v0, 0, v0
	s_and_b32 vcc_lo, s1, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f64 v[10:11], v[6:7], s[50:51], v[4:5]
	v_cvt_i32_f64_e32 v14, v[6:7]
	v_fma_f64 v[10:11], v[6:7], s[52:53], v[10:11]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[12:13], v[10:11], s[56:57], s[54:55]
	v_fma_f64 v[12:13], v[10:11], v[12:13], s[58:59]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[12:13], v[10:11], v[12:13], s[60:61]
	v_fma_f64 v[12:13], v[10:11], v[12:13], s[62:63]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[12:13], v[10:11], v[12:13], s[64:65]
	v_fma_f64 v[12:13], v[10:11], v[12:13], s[66:67]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[12:13], v[10:11], v[12:13], s[68:69]
	v_fma_f64 v[12:13], v[10:11], v[12:13], s[70:71]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[12:13], v[10:11], v[12:13], s[72:73]
	v_fma_f64 v[12:13], v[10:11], v[12:13], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[6:7], v[10:11], v[12:13], 1.0
	v_ldexp_f64 v[6:7], v[6:7], v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v2, 0x7ff00000, v7, s0
	v_cndmask_b32_e64 v3, 0, v2, s1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v2, 0, v6, vcc_lo
	v_fma_f64 v[0:1], v[2:3], v[0:1], v[2:3]
	v_cmp_class_f64_e64 vcc_lo, v[2:3], 0x204
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_cndmask_b32 v1, v1, v3 :: v_dual_cndmask_b32 v0, v0, v2
	v_cvt_i32_f64_e64 v0, |v[0:1]|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s0, v0
	s_lshr_b32 s1, s0, 31
	s_add_i32 s2, s0, s75
	s_add_i32 s1, s0, s1
	s_mul_i32 s2, s2, 31
	s_ashr_i32 s1, s1, 1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s1, s1, s75
	s_sub_i32 s40, 63, s1
	s_cmp_eq_u32 s75, 1
	s_cselect_b32 s41, -1, 0
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, .str.1@rel32@lo+4
	s_addc_u32 s1, s1, .str.1@rel32@hi+12
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u64 s[0:1], 0
	s_cselect_b32 s42, 22, 0
	s_sub_i32 s28, 0x7df, s2
	s_sub_i32 s34, 0x81d, s2
	s_sub_i32 s36, 0x7fe, s2
.LBB1_61:                               ; %.preheader214
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB1_62 Depth 2
                                        ;     Child Loop BB1_64 Depth 2
                                        ;     Child Loop BB1_66 Depth 2
                                        ;     Child Loop BB1_71 Depth 2
                                        ;     Child Loop BB1_79 Depth 2
                                        ;     Child Loop BB1_85 Depth 2
                                        ;     Child Loop BB1_94 Depth 2
                                        ;     Child Loop BB1_98 Depth 2
                                        ;     Child Loop BB1_106 Depth 2
                                        ;     Child Loop BB1_112 Depth 2
                                        ;     Child Loop BB1_121 Depth 2
                                        ;     Child Loop BB1_125 Depth 2
                                        ;     Child Loop BB1_133 Depth 2
                                        ;     Child Loop BB1_139 Depth 2
                                        ;     Child Loop BB1_148 Depth 2
                                        ;     Child Loop BB1_152 Depth 2
                                        ;     Child Loop BB1_160 Depth 2
                                        ;     Child Loop BB1_166 Depth 2
                                        ;     Child Loop BB1_175 Depth 2
	s_ashr_i32 s29, s28, 31
	v_mov_b32_e32 v0, 0
	s_lshl_b64 s[0:1], s[28:29], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s2, s26, s0
	s_addc_u32 s3, s27, s1
	s_mov_b64 s[0:1], 0
.LBB1_62:                               ;   Parent Loop BB1_61 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	v_add_co_u32 v1, vcc_lo, v53, s0
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v54, vcc_lo
	s_add_u32 s4, s2, s0
	s_addc_u32 s5, s3, s1
	global_load_b32 v3, v42, s[4:5]
	global_load_b32 v1, v[1:2], off
	s_add_u32 s0, s0, 4
	s_addc_u32 s1, s1, 0
	s_cmpk_eq_i32 s0, 0x7c
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v0, v1, v3
	s_cbranch_scc0 .LBB1_62
; %bb.63:                               ; %.preheader213
                                        ;   in Loop: Header=BB1_61 Depth=1
	s_ashr_i32 s35, s34, 31
	v_mov_b32_e32 v1, 0
	s_lshl_b64 s[0:1], s[34:35], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s2, s26, s0
	s_addc_u32 s3, s27, s1
	s_mov_b64 s[0:1], 0
.LBB1_64:                               ;   Parent Loop BB1_61 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	v_add_co_u32 v2, vcc_lo, v53, s0
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v54, vcc_lo
	s_add_u32 s4, s2, s0
	s_addc_u32 s5, s3, s1
	global_load_b32 v4, v42, s[4:5]
	global_load_b32 v2, v[2:3], off
	s_add_u32 s0, s0, 4
	s_addc_u32 s1, s1, 0
	s_cmpk_eq_i32 s0, 0x7c
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v1, v2, v4
	s_cbranch_scc0 .LBB1_64
; %bb.65:                               ; %.preheader212
                                        ;   in Loop: Header=BB1_61 Depth=1
	s_ashr_i32 s37, s36, 31
	v_mov_b32_e32 v2, 0
	s_lshl_b64 s[0:1], s[36:37], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s2, s26, s0
	s_addc_u32 s3, s27, s1
	s_mov_b64 s[0:1], 0
.LBB1_66:                               ;   Parent Loop BB1_61 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	v_add_co_u32 v3, vcc_lo, v51, s0
	v_add_co_ci_u32_e32 v4, vcc_lo, s1, v52, vcc_lo
	s_add_u32 s4, s2, s0
	s_addc_u32 s5, s3, s1
	global_load_b32 v5, v42, s[4:5]
	global_load_b32 v3, v[3:4], off
	s_add_u32 s0, s0, 4
	s_addc_u32 s1, s1, 0
	s_cmpk_eq_i32 s0, 0x7c
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v2, v3, v5
	s_cbranch_scc0 .LBB1_66
; %bb.67:                               ;   in Loop: Header=BB1_61 Depth=1
	s_add_i32 s0, s40, s74
	v_add_f32_e32 v3, v0, v1
	v_mad_u64_u32 v[49:50], null, s0, 31, v[38:39]
	s_cmp_eq_u32 s74, 2
	s_cselect_b32 s0, -1, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v57, v3, v2
	s_and_b32 s0, s41, s0
	v_ashrrev_i32_e32 v50, 31, v49
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[49:50]
	v_add_co_u32 v0, vcc_lo, s26, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s27, v1, vcc_lo
	s_and_b32 vcc_lo, exec_lo, s0
	global_store_b32 v[0:1], v57, off
	s_cbranch_vccz .LBB1_177
; %bb.68:                               ;   in Loop: Header=BB1_61 Depth=1
	s_load_b64 s[38:39], s[24:25], 0x50
	v_dual_mov_b32 v41, v56 :: v_dual_mov_b32 v4, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s0, v41
	v_mov_b32_e32 v5, 0
	v_cmp_eq_u32_e64 s0, s0, v41
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_74
; %bb.69:                               ;   in Loop: Header=BB1_61 Depth=1
	s_waitcnt lgkmcnt(0)
	global_load_b64 v[2:3], v42, s[38:39] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[0:1], v42, s[38:39] offset:40
	global_load_b64 v[4:5], v42, s[38:39]
	s_mov_b32 s2, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v1, v1, v3
	v_and_b32_e32 v0, v0, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v1, v1, 24
	v_mul_hi_u32 v6, v0, 24
	v_mul_lo_u32 v0, v0, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v1, v6, v1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v0, vcc_lo, v4, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, v5, v1, vcc_lo
	global_load_b64 v[0:1], v[0:1], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[4:5], v42, v[0:3], s[38:39] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[4:5], v[2:3]
	s_cbranch_execz .LBB1_73
; %bb.70:                               ; %.preheader3.i.i.i185.preheader
                                        ;   in Loop: Header=BB1_61 Depth=1
	s_mov_b32 s3, 0
.LBB1_71:                               ; %.preheader3.i.i.i185
                                        ;   Parent Loop BB1_61 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[0:1], v42, s[38:39] offset:40
	global_load_b64 v[6:7], v42, s[38:39]
	v_dual_mov_b32 v2, v4 :: v_dual_mov_b32 v3, v5
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v0, v0, v2
	v_and_b32_e32 v1, v1, v3
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[4:5], null, v0, 24, v[6:7]
	v_mov_b32_e32 v0, v5
	s_delay_alu instid0(VALU_DEP_1)
	v_mad_u64_u32 v[5:6], null, v1, 24, v[0:1]
	global_load_b64 v[0:1], v[4:5], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[4:5], v42, v[0:3], s[38:39] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[2:3]
	s_or_b32 s3, vcc_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s3
	s_cbranch_execnz .LBB1_71
; %bb.72:                               ; %Flow523
                                        ;   in Loop: Header=BB1_61 Depth=1
	s_or_b32 exec_lo, exec_lo, s3
.LBB1_73:                               ; %Flow525
                                        ;   in Loop: Header=BB1_61 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s2
.LBB1_74:                               ; %.loopexit4.i.i.i180
                                        ;   in Loop: Header=BB1_61 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_waitcnt lgkmcnt(0)
	s_clause 0x1
	global_load_b64 v[6:7], v42, s[38:39] offset:40
	global_load_b128 v[0:3], v42, s[38:39]
	v_readfirstlane_b32 s2, v4
	v_readfirstlane_b32 s3, v5
	s_mov_b32 s8, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s4, v6
	v_readfirstlane_b32 s5, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[4:5], s[2:3], s[4:5]
	s_mul_i32 s1, s5, 24
	s_mul_hi_u32 s6, s4, 24
	s_mul_i32 s7, s4, 24
	s_and_saveexec_b32 s9, s0
	s_cbranch_execz .LBB1_76
; %bb.75:                               ;   in Loop: Header=BB1_61 Depth=1
	v_dual_mov_b32 v43, s8 :: v_dual_mov_b32 v44, v42
	s_add_i32 s8, s6, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v4, vcc_lo, v0, s7
	v_add_co_ci_u32_e32 v5, vcc_lo, s8, v1, vcc_lo
	global_store_b128 v[4:5], v[43:46], off offset:8
.LBB1_76:                               ;   in Loop: Header=BB1_61 Depth=1
	s_or_b32 exec_lo, exec_lo, s9
	s_lshl_b64 s[4:5], s[4:5], 12
	v_lshlrev_b64 v[4:5], 6, v[41:42]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v2, vcc_lo, v2, s4
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
	s_mov_b32 s21, s20
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v6, vcc_lo, v2, v4
	s_mov_b32 s22, s20
	s_mov_b32 s23, s20
	v_add_co_ci_u32_e32 v7, vcc_lo, v3, v5, vcc_lo
	v_dual_mov_b32 v41, v42 :: v_dual_mov_b32 v2, s20
	v_dual_mov_b32 v43, v42 :: v_dual_mov_b32 v4, s22
	v_mov_b32_e32 v3, s21
	v_mov_b32_e32 v5, s23
	s_clause 0x3
	global_store_b128 v[6:7], v[40:43], off
	global_store_b128 v[6:7], v[2:5], off offset:16
	global_store_b128 v[6:7], v[2:5], off offset:32
	global_store_b128 v[6:7], v[2:5], off offset:48
	s_and_saveexec_b32 s4, s0
	s_cbranch_execz .LBB1_84
; %bb.77:                               ;   in Loop: Header=BB1_61 Depth=1
	s_clause 0x1
	global_load_b64 v[12:13], v42, s[38:39] offset:32 glc
	global_load_b64 v[2:3], v42, s[38:39] offset:40
	s_mov_b32 s5, exec_lo
	v_dual_mov_b32 v10, s2 :: v_dual_mov_b32 v11, s3
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v3, s3, v3
	v_and_b32_e32 v2, s2, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v3, v3, 24
	v_mul_hi_u32 v4, v2, 24
	v_mul_lo_u32 v2, v2, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v3, v4, v3
	v_add_co_u32 v8, vcc_lo, v0, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v9, vcc_lo, v1, v3, vcc_lo
	global_store_b64 v[8:9], v[12:13], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[4:5], v42, v[10:13], s[38:39] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[4:5], v[12:13]
	s_cbranch_execz .LBB1_80
; %bb.78:                               ; %.preheader1.i.i.i183.preheader
                                        ;   in Loop: Header=BB1_61 Depth=1
	s_mov_b32 s8, 0
.LBB1_79:                               ; %.preheader1.i.i.i183
                                        ;   Parent Loop BB1_61 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
	s_sleep 1
	global_store_b64 v[8:9], v[4:5], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v42, v[2:5], s[38:39] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
	v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
	s_or_b32 s8, vcc_lo, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s8
	s_cbranch_execnz .LBB1_79
.LBB1_80:                               ; %Flow521
                                        ;   in Loop: Header=BB1_61 Depth=1
	s_or_b32 exec_lo, exec_lo, s5
	global_load_b64 v[2:3], v42, s[38:39] offset:16
	s_mov_b32 s8, exec_lo
	s_mov_b32 s5, exec_lo
	v_mbcnt_lo_u32_b32 v4, s8, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v4
	s_cbranch_execz .LBB1_82
; %bb.81:                               ;   in Loop: Header=BB1_61 Depth=1
	s_bcnt1_i32_b32 s8, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v41, s8
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[2:3], v[41:42], off offset:8
.LBB1_82:                               ;   in Loop: Header=BB1_61 Depth=1
	s_or_b32 exec_lo, exec_lo, s5
	s_waitcnt vmcnt(0)
	global_load_b64 v[4:5], v[2:3], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
	s_cbranch_vccnz .LBB1_84
; %bb.83:                               ;   in Loop: Header=BB1_61 Depth=1
	global_load_b32 v41, v[2:3], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s5, v41
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[4:5], v[41:42], off
	s_and_b32 m0, s5, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB1_84:                               ; %Flow522
                                        ;   in Loop: Header=BB1_61 Depth=1
	s_or_b32 exec_lo, exec_lo, s4
	s_add_i32 s6, s6, s1
	v_add_co_u32 v0, vcc_lo, v0, s7
	v_add_co_ci_u32_e32 v1, vcc_lo, s6, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, 20
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
.LBB1_85:                               ;   Parent Loop BB1_61 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_mov_b32_e32 v2, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_87
; %bb.86:                               ;   in Loop: Header=BB1_85 Depth=2
	global_load_b32 v2, v[0:1], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v2, 1, v2
.LBB1_87:                               ;   in Loop: Header=BB1_85 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v2
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB1_89
; %bb.88:                               ;   in Loop: Header=BB1_85 Depth=2
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB1_90
.LBB1_89:                               ;   in Loop: Header=BB1_85 Depth=2
	s_mov_b32 s1, -1
.LBB1_90:                               ; %Flow516
                                        ;   in Loop: Header=BB1_85 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB1_85
; %bb.91:                               ;   in Loop: Header=BB1_61 Depth=1
	global_load_b64 v[0:1], v[6:7], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_95
; %bb.92:                               ;   in Loop: Header=BB1_61 Depth=1
	s_clause 0x2
	global_load_b64 v[4:5], v42, s[38:39] offset:40
	global_load_b64 v[8:9], v42, s[38:39] offset:24 glc
	global_load_b64 v[6:7], v42, s[38:39]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v10, vcc_lo, v4, 1
	v_add_co_ci_u32_e32 v11, vcc_lo, 0, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, v10, s2
	v_add_co_ci_u32_e32 v3, vcc_lo, s3, v11, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
	v_dual_cndmask_b32 v3, v3, v11 :: v_dual_cndmask_b32 v2, v2, v10
	v_and_b32_e32 v5, v3, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v4, v2, v4
	v_mul_hi_u32 v10, v4, 24
	v_mul_lo_u32 v4, v4, 24
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_u32 v6, vcc_lo, v6, v4
	v_mov_b32_e32 v4, v8
	v_mul_lo_u32 v5, v5, 24
	v_add_nc_u32_e32 v5, v10, v5
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
	v_mov_b32_e32 v5, v9
	global_store_b64 v[6:7], v[8:9], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[4:5], v42, v[2:5], s[38:39] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[4:5], v[8:9]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB1_95
; %bb.93:                               ; %.preheader.i.i.i182.preheader
                                        ;   in Loop: Header=BB1_61 Depth=1
	s_mov_b32 s0, 0
.LBB1_94:                               ; %.preheader.i.i.i182
                                        ;   Parent Loop BB1_61 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	global_store_b64 v[6:7], v[4:5], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[8:9], v42, v[2:5], s[38:39] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[4:5]
	v_dual_mov_b32 v4, v8 :: v_dual_mov_b32 v5, v9
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB1_94
.LBB1_95:                               ; %__ockl_printf_begin.exit186
                                        ;   in Loop: Header=BB1_61 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_add_u32 s8, s18, 56
	s_addc_u32 s9, s19, 0
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, .str.1@rel32@lo+4
	s_addc_u32 s1, s1, .str.1@rel32@hi+12
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
	v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
	v_dual_mov_b32 v4, s42 :: v_dual_mov_b32 v5, 0
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, __ockl_printf_append_string_n@rel32@lo+4
	s_addc_u32 s3, s3, __ockl_printf_append_string_n@rel32@hi+12
	s_swappc_b64 s[30:31], s[2:3]
	v_mov_b32_e32 v41, v56
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_readfirstlane_b32 s0, v41
	v_mov_b32_e32 v5, 0
	v_dual_mov_b32 v37, v1 :: v_dual_mov_b32 v6, 0
	v_cmp_eq_u32_e64 s0, s0, v41
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_101
; %bb.96:                               ;   in Loop: Header=BB1_61 Depth=1
	global_load_b64 v[3:4], v42, s[38:39] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[1:2], v42, s[38:39] offset:40
	global_load_b64 v[5:6], v42, s[38:39]
	s_mov_b32 s2, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v2, v2, v4
	v_and_b32_e32 v1, v1, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v2, v2, 24
	v_mul_hi_u32 v7, v1, 24
	v_mul_lo_u32 v1, v1, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v2, v7, v2
	s_waitcnt vmcnt(0)
	v_add_co_u32 v1, vcc_lo, v5, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, v6, v2, vcc_lo
	global_load_b64 v[1:2], v[1:2], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[5:6], v42, v[1:4], s[38:39] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[5:6], v[3:4]
	s_cbranch_execz .LBB1_100
; %bb.97:                               ; %.preheader3.i.i.i192.preheader
                                        ;   in Loop: Header=BB1_61 Depth=1
	s_mov_b32 s3, 0
.LBB1_98:                               ; %.preheader3.i.i.i192
                                        ;   Parent Loop BB1_61 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[1:2], v42, s[38:39] offset:40
	global_load_b64 v[7:8], v42, s[38:39]
	v_dual_mov_b32 v3, v5 :: v_dual_mov_b32 v4, v6
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v1, v1, v3
	v_and_b32_e32 v2, v2, v4
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[5:6], null, v1, 24, v[7:8]
	v_mov_b32_e32 v1, v6
	s_delay_alu instid0(VALU_DEP_1)
	v_mad_u64_u32 v[6:7], null, v2, 24, v[1:2]
	global_load_b64 v[1:2], v[5:6], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[5:6], v42, v[1:4], s[38:39] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[5:6], v[3:4]
	s_or_b32 s3, vcc_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s3
	s_cbranch_execnz .LBB1_98
; %bb.99:                               ; %Flow509
                                        ;   in Loop: Header=BB1_61 Depth=1
	s_or_b32 exec_lo, exec_lo, s3
.LBB1_100:                              ; %Flow511
                                        ;   in Loop: Header=BB1_61 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s2
.LBB1_101:                              ; %.loopexit4.i.i.i187
                                        ;   in Loop: Header=BB1_61 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_clause 0x1
	global_load_b64 v[7:8], v42, s[38:39] offset:40
	global_load_b128 v[1:4], v42, s[38:39]
	v_readfirstlane_b32 s2, v5
	v_readfirstlane_b32 s3, v6
	s_mov_b32 s8, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s4, v7
	v_readfirstlane_b32 s5, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[4:5], s[2:3], s[4:5]
	s_mul_i32 s1, s5, 24
	s_mul_hi_u32 s6, s4, 24
	s_mul_i32 s7, s4, 24
	s_and_saveexec_b32 s9, s0
	s_cbranch_execz .LBB1_103
; %bb.102:                              ;   in Loop: Header=BB1_61 Depth=1
	v_dual_mov_b32 v43, s8 :: v_dual_mov_b32 v44, v42
	s_add_i32 s8, s6, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v5, vcc_lo, v1, s7
	v_add_co_ci_u32_e32 v6, vcc_lo, s8, v2, vcc_lo
	global_store_b128 v[5:6], v[43:46], off offset:8
.LBB1_103:                              ;   in Loop: Header=BB1_61 Depth=1
	s_or_b32 exec_lo, exec_lo, s9
	s_lshl_b64 s[4:5], s[4:5], 12
	s_mov_b32 s21, s20
	s_waitcnt vmcnt(0)
	v_add_co_u32 v5, vcc_lo, v3, s4
	v_add_co_ci_u32_e32 v6, vcc_lo, s5, v4, vcc_lo
	v_lshlrev_b64 v[3:4], 6, v[41:42]
	s_mov_b32 s22, s20
	s_mov_b32 s23, s20
	v_and_or_b32 v36, 0xffffff1f, v0, 32
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v7, vcc_lo, v5, v3
	v_add_co_ci_u32_e32 v8, vcc_lo, v6, v4, vcc_lo
	v_dual_mov_b32 v3, s20 :: v_dual_mov_b32 v4, s21
	v_dual_mov_b32 v5, s22 :: v_dual_mov_b32 v6, s23
	s_clause 0x3
	global_store_b128 v[7:8], v[36:39], off
	global_store_b128 v[7:8], v[3:6], off offset:16
	global_store_b128 v[7:8], v[3:6], off offset:32
	global_store_b128 v[7:8], v[3:6], off offset:48
	s_and_saveexec_b32 s4, s0
	s_cbranch_execz .LBB1_111
; %bb.104:                              ;   in Loop: Header=BB1_61 Depth=1
	s_clause 0x1
	global_load_b64 v[13:14], v42, s[38:39] offset:32 glc
	global_load_b64 v[3:4], v42, s[38:39] offset:40
	v_dual_mov_b32 v11, s2 :: v_dual_mov_b32 v12, s3
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s8, v3
	v_readfirstlane_b32 s9, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[8:9], s[8:9], s[2:3]
	s_mul_i32 s5, s9, 24
	s_mul_hi_u32 s9, s8, 24
	s_mul_i32 s8, s8, 24
	s_add_i32 s9, s9, s5
	v_add_co_u32 v9, vcc_lo, v1, s8
	v_add_co_ci_u32_e32 v10, vcc_lo, s9, v2, vcc_lo
	s_mov_b32 s5, exec_lo
	global_store_b64 v[9:10], v[13:14], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[5:6], v42, v[11:14], s[38:39] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[5:6], v[13:14]
	s_cbranch_execz .LBB1_107
; %bb.105:                              ; %.preheader1.i.i.i190.preheader
                                        ;   in Loop: Header=BB1_61 Depth=1
	s_mov_b32 s8, 0
.LBB1_106:                              ; %.preheader1.i.i.i190
                                        ;   Parent Loop BB1_61 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_dual_mov_b32 v3, s2 :: v_dual_mov_b32 v4, s3
	s_sleep 1
	global_store_b64 v[9:10], v[5:6], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[3:4], v42, v[3:6], s[38:39] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[3:4], v[5:6]
	v_dual_mov_b32 v6, v4 :: v_dual_mov_b32 v5, v3
	s_or_b32 s8, vcc_lo, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s8
	s_cbranch_execnz .LBB1_106
.LBB1_107:                              ; %Flow507
                                        ;   in Loop: Header=BB1_61 Depth=1
	s_or_b32 exec_lo, exec_lo, s5
	global_load_b64 v[3:4], v42, s[38:39] offset:16
	s_mov_b32 s8, exec_lo
	s_mov_b32 s5, exec_lo
	v_mbcnt_lo_u32_b32 v0, s8, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB1_109
; %bb.108:                              ;   in Loop: Header=BB1_61 Depth=1
	s_bcnt1_i32_b32 s8, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v41, s8
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[3:4], v[41:42], off offset:8
.LBB1_109:                              ;   in Loop: Header=BB1_61 Depth=1
	s_or_b32 exec_lo, exec_lo, s5
	s_waitcnt vmcnt(0)
	global_load_b64 v[5:6], v[3:4], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[5:6]
	s_cbranch_vccnz .LBB1_111
; %bb.110:                              ;   in Loop: Header=BB1_61 Depth=1
	global_load_b32 v41, v[3:4], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s5, v41
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[5:6], v[41:42], off
	s_and_b32 m0, s5, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB1_111:                              ; %Flow508
                                        ;   in Loop: Header=BB1_61 Depth=1
	s_or_b32 exec_lo, exec_lo, s4
	s_add_i32 s6, s6, s1
	v_add_co_u32 v0, vcc_lo, v1, s7
	v_add_co_ci_u32_e32 v1, vcc_lo, s6, v2, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, 20
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
.LBB1_112:                              ;   Parent Loop BB1_61 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_mov_b32_e32 v2, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_114
; %bb.113:                              ;   in Loop: Header=BB1_112 Depth=2
	global_load_b32 v2, v[0:1], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v2, 1, v2
.LBB1_114:                              ;   in Loop: Header=BB1_112 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v2
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB1_116
; %bb.115:                              ;   in Loop: Header=BB1_112 Depth=2
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB1_117
.LBB1_116:                              ;   in Loop: Header=BB1_112 Depth=2
	s_mov_b32 s1, -1
.LBB1_117:                              ; %Flow502
                                        ;   in Loop: Header=BB1_112 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB1_112
; %bb.118:                              ;   in Loop: Header=BB1_61 Depth=1
	global_load_b64 v[47:48], v[7:8], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_122
; %bb.119:                              ;   in Loop: Header=BB1_61 Depth=1
	s_clause 0x2
	global_load_b64 v[2:3], v42, s[38:39] offset:40
	global_load_b64 v[6:7], v42, s[38:39] offset:24 glc
	global_load_b64 v[4:5], v42, s[38:39]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v8, vcc_lo, v2, 1
	v_add_co_ci_u32_e32 v9, vcc_lo, 0, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v8, s2
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
	v_dual_cndmask_b32 v1, v1, v9 :: v_dual_cndmask_b32 v0, v0, v8
	v_and_b32_e32 v3, v1, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v2, v0, v2
	v_mul_hi_u32 v8, v2, 24
	v_mul_lo_u32 v2, v2, 24
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_u32 v4, vcc_lo, v4, v2
	v_mov_b32_e32 v2, v6
	v_mul_lo_u32 v3, v3, 24
	v_add_nc_u32_e32 v3, v8, v3
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
	v_mov_b32_e32 v3, v7
	global_store_b64 v[4:5], v[6:7], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v42, v[0:3], s[38:39] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[6:7]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB1_122
; %bb.120:                              ; %.preheader.i.i.i189.preheader
                                        ;   in Loop: Header=BB1_61 Depth=1
	s_mov_b32 s0, 0
.LBB1_121:                              ; %.preheader.i.i.i189
                                        ;   Parent Loop BB1_61 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	global_store_b64 v[4:5], v[2:3], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[6:7], v42, v[0:3], s[38:39] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[2:3]
	v_dual_mov_b32 v2, v6 :: v_dual_mov_b32 v3, v7
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB1_121
.LBB1_122:                              ; %__ockl_printf_append_args.exit193
                                        ;   in Loop: Header=BB1_61 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	v_dual_mov_b32 v41, v56 :: v_dual_mov_b32 v4, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s0, v41
	v_mov_b32_e32 v5, 0
	v_cmp_eq_u32_e64 s0, s0, v41
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_128
; %bb.123:                              ;   in Loop: Header=BB1_61 Depth=1
	global_load_b64 v[2:3], v42, s[38:39] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[0:1], v42, s[38:39] offset:40
	global_load_b64 v[4:5], v42, s[38:39]
	s_mov_b32 s2, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v1, v1, v3
	v_and_b32_e32 v0, v0, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v1, v1, 24
	v_mul_hi_u32 v6, v0, 24
	v_mul_lo_u32 v0, v0, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v1, v6, v1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v0, vcc_lo, v4, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, v5, v1, vcc_lo
	global_load_b64 v[0:1], v[0:1], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[4:5], v42, v[0:3], s[38:39] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[4:5], v[2:3]
	s_cbranch_execz .LBB1_127
; %bb.124:                              ; %.preheader3.i.i.i199.preheader
                                        ;   in Loop: Header=BB1_61 Depth=1
	s_mov_b32 s3, 0
.LBB1_125:                              ; %.preheader3.i.i.i199
                                        ;   Parent Loop BB1_61 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[0:1], v42, s[38:39] offset:40
	global_load_b64 v[6:7], v42, s[38:39]
	v_dual_mov_b32 v2, v4 :: v_dual_mov_b32 v3, v5
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v0, v0, v2
	v_and_b32_e32 v1, v1, v3
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[4:5], null, v0, 24, v[6:7]
	v_mov_b32_e32 v0, v5
	s_delay_alu instid0(VALU_DEP_1)
	v_mad_u64_u32 v[5:6], null, v1, 24, v[0:1]
	global_load_b64 v[0:1], v[4:5], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[4:5], v42, v[0:3], s[38:39] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[2:3]
	s_or_b32 s3, vcc_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s3
	s_cbranch_execnz .LBB1_125
; %bb.126:                              ; %Flow495
                                        ;   in Loop: Header=BB1_61 Depth=1
	s_or_b32 exec_lo, exec_lo, s3
.LBB1_127:                              ; %Flow497
                                        ;   in Loop: Header=BB1_61 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s2
.LBB1_128:                              ; %.loopexit4.i.i.i194
                                        ;   in Loop: Header=BB1_61 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_clause 0x1
	global_load_b64 v[6:7], v42, s[38:39] offset:40
	global_load_b128 v[0:3], v42, s[38:39]
	v_readfirstlane_b32 s2, v4
	v_readfirstlane_b32 s3, v5
	s_mov_b32 s8, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s4, v6
	v_readfirstlane_b32 s5, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[4:5], s[2:3], s[4:5]
	s_mul_i32 s1, s5, 24
	s_mul_hi_u32 s6, s4, 24
	s_mul_i32 s7, s4, 24
	s_and_saveexec_b32 s9, s0
	s_cbranch_execz .LBB1_130
; %bb.129:                              ;   in Loop: Header=BB1_61 Depth=1
	v_dual_mov_b32 v43, s8 :: v_dual_mov_b32 v44, v42
	s_add_i32 s8, s6, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v4, vcc_lo, v0, s7
	v_add_co_ci_u32_e32 v5, vcc_lo, s8, v1, vcc_lo
	global_store_b128 v[4:5], v[43:46], off offset:8
.LBB1_130:                              ;   in Loop: Header=BB1_61 Depth=1
	s_or_b32 exec_lo, exec_lo, s9
	s_lshl_b64 s[4:5], s[4:5], 12
	v_lshlrev_b64 v[4:5], 6, v[41:42]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v2, vcc_lo, v2, s4
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
	s_mov_b32 s21, s20
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v6, vcc_lo, v2, v4
	s_mov_b32 s22, s20
	s_mov_b32 s23, s20
	v_and_or_b32 v47, 0xffffff1f, v47, 32
	v_add_co_ci_u32_e32 v7, vcc_lo, v3, v5, vcc_lo
	v_mov_b32_e32 v50, v42
	v_dual_mov_b32 v2, s20 :: v_dual_mov_b32 v5, s23
	v_dual_mov_b32 v3, s21 :: v_dual_mov_b32 v4, s22
	s_clause 0x3
	global_store_b128 v[6:7], v[47:50], off
	global_store_b128 v[6:7], v[2:5], off offset:16
	global_store_b128 v[6:7], v[2:5], off offset:32
	global_store_b128 v[6:7], v[2:5], off offset:48
	s_and_saveexec_b32 s4, s0
	s_cbranch_execz .LBB1_138
; %bb.131:                              ;   in Loop: Header=BB1_61 Depth=1
	s_clause 0x1
	global_load_b64 v[12:13], v42, s[38:39] offset:32 glc
	global_load_b64 v[2:3], v42, s[38:39] offset:40
	v_dual_mov_b32 v10, s2 :: v_dual_mov_b32 v11, s3
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s8, v2
	v_readfirstlane_b32 s9, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[8:9], s[8:9], s[2:3]
	s_mul_i32 s5, s9, 24
	s_mul_hi_u32 s9, s8, 24
	s_mul_i32 s8, s8, 24
	s_add_i32 s9, s9, s5
	v_add_co_u32 v8, vcc_lo, v0, s8
	v_add_co_ci_u32_e32 v9, vcc_lo, s9, v1, vcc_lo
	s_mov_b32 s5, exec_lo
	global_store_b64 v[8:9], v[12:13], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[4:5], v42, v[10:13], s[38:39] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[4:5], v[12:13]
	s_cbranch_execz .LBB1_134
; %bb.132:                              ; %.preheader1.i.i.i197.preheader
                                        ;   in Loop: Header=BB1_61 Depth=1
	s_mov_b32 s8, 0
.LBB1_133:                              ; %.preheader1.i.i.i197
                                        ;   Parent Loop BB1_61 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
	s_sleep 1
	global_store_b64 v[8:9], v[4:5], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v42, v[2:5], s[38:39] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
	v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
	s_or_b32 s8, vcc_lo, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s8
	s_cbranch_execnz .LBB1_133
.LBB1_134:                              ; %Flow493
                                        ;   in Loop: Header=BB1_61 Depth=1
	s_or_b32 exec_lo, exec_lo, s5
	global_load_b64 v[2:3], v42, s[38:39] offset:16
	s_mov_b32 s8, exec_lo
	s_mov_b32 s5, exec_lo
	v_mbcnt_lo_u32_b32 v4, s8, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v4
	s_cbranch_execz .LBB1_136
; %bb.135:                              ;   in Loop: Header=BB1_61 Depth=1
	s_bcnt1_i32_b32 s8, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v41, s8
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[2:3], v[41:42], off offset:8
.LBB1_136:                              ;   in Loop: Header=BB1_61 Depth=1
	s_or_b32 exec_lo, exec_lo, s5
	s_waitcnt vmcnt(0)
	global_load_b64 v[4:5], v[2:3], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
	s_cbranch_vccnz .LBB1_138
; %bb.137:                              ;   in Loop: Header=BB1_61 Depth=1
	global_load_b32 v41, v[2:3], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s5, v41
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[4:5], v[41:42], off
	s_and_b32 m0, s5, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB1_138:                              ; %Flow494
                                        ;   in Loop: Header=BB1_61 Depth=1
	s_or_b32 exec_lo, exec_lo, s4
	s_add_i32 s6, s6, s1
	v_add_co_u32 v0, vcc_lo, v0, s7
	v_add_co_ci_u32_e32 v1, vcc_lo, s6, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, 20
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
.LBB1_139:                              ;   Parent Loop BB1_61 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_mov_b32_e32 v2, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_141
; %bb.140:                              ;   in Loop: Header=BB1_139 Depth=2
	global_load_b32 v2, v[0:1], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v2, 1, v2
.LBB1_141:                              ;   in Loop: Header=BB1_139 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v2
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB1_143
; %bb.142:                              ;   in Loop: Header=BB1_139 Depth=2
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB1_144
.LBB1_143:                              ;   in Loop: Header=BB1_139 Depth=2
	s_mov_b32 s1, -1
.LBB1_144:                              ; %Flow488
                                        ;   in Loop: Header=BB1_139 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB1_139
; %bb.145:                              ;   in Loop: Header=BB1_61 Depth=1
	global_load_b64 v[0:1], v[6:7], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_149
; %bb.146:                              ;   in Loop: Header=BB1_61 Depth=1
	s_clause 0x2
	global_load_b64 v[4:5], v42, s[38:39] offset:40
	global_load_b64 v[8:9], v42, s[38:39] offset:24 glc
	global_load_b64 v[6:7], v42, s[38:39]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v10, vcc_lo, v4, 1
	v_add_co_ci_u32_e32 v11, vcc_lo, 0, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, v10, s2
	v_add_co_ci_u32_e32 v3, vcc_lo, s3, v11, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
	v_dual_cndmask_b32 v3, v3, v11 :: v_dual_cndmask_b32 v2, v2, v10
	v_and_b32_e32 v5, v3, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v4, v2, v4
	v_mul_hi_u32 v10, v4, 24
	v_mul_lo_u32 v4, v4, 24
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_u32 v6, vcc_lo, v6, v4
	v_mov_b32_e32 v4, v8
	v_mul_lo_u32 v5, v5, 24
	v_add_nc_u32_e32 v5, v10, v5
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
	v_mov_b32_e32 v5, v9
	global_store_b64 v[6:7], v[8:9], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[4:5], v42, v[2:5], s[38:39] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[4:5], v[8:9]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB1_149
; %bb.147:                              ; %.preheader.i.i.i196.preheader
                                        ;   in Loop: Header=BB1_61 Depth=1
	s_mov_b32 s0, 0
.LBB1_148:                              ; %.preheader.i.i.i196
                                        ;   Parent Loop BB1_61 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	global_store_b64 v[6:7], v[4:5], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[8:9], v42, v[2:5], s[38:39] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[4:5]
	v_dual_mov_b32 v4, v8 :: v_dual_mov_b32 v5, v9
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB1_148
.LBB1_149:                              ; %__ockl_printf_append_args.exit200
                                        ;   in Loop: Header=BB1_61 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	v_dual_mov_b32 v41, v56 :: v_dual_mov_b32 v2, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s0, v41
	v_mov_b32_e32 v3, 0
	v_cmp_eq_u32_e64 s0, s0, v41
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_155
; %bb.150:                              ;   in Loop: Header=BB1_61 Depth=1
	global_load_b64 v[4:5], v42, s[38:39] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[2:3], v42, s[38:39] offset:40
	global_load_b64 v[6:7], v42, s[38:39]
	s_mov_b32 s2, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v3, v3, v5
	v_and_b32_e32 v2, v2, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v3, v3, 24
	v_mul_hi_u32 v8, v2, 24
	v_mul_lo_u32 v2, v2, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v3, v8, v3
	s_waitcnt vmcnt(0)
	v_add_co_u32 v2, vcc_lo, v6, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, v7, v3, vcc_lo
	global_load_b64 v[2:3], v[2:3], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[2:3], v42, v[2:5], s[38:39] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[2:3], v[4:5]
	s_cbranch_execz .LBB1_154
; %bb.151:                              ; %.preheader3.i.i.i206.preheader
                                        ;   in Loop: Header=BB1_61 Depth=1
	s_mov_b32 s3, 0
.LBB1_152:                              ; %.preheader3.i.i.i206
                                        ;   Parent Loop BB1_61 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[6:7], v42, s[38:39] offset:40
	global_load_b64 v[8:9], v42, s[38:39]
	v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v6, v6, v4
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[2:3], null, v6, 24, v[8:9]
	v_and_b32_e32 v8, v7, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[6:7], null, v8, 24, v[3:4]
	v_mov_b32_e32 v3, v6
	global_load_b64 v[2:3], v[2:3], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[2:3], v42, v[2:5], s[38:39] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
	s_or_b32 s3, vcc_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s3
	s_cbranch_execnz .LBB1_152
; %bb.153:                              ; %Flow481
                                        ;   in Loop: Header=BB1_61 Depth=1
	s_or_b32 exec_lo, exec_lo, s3
.LBB1_154:                              ; %Flow483
                                        ;   in Loop: Header=BB1_61 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s2
.LBB1_155:                              ; %.loopexit4.i.i.i201
                                        ;   in Loop: Header=BB1_61 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_clause 0x1
	global_load_b64 v[8:9], v42, s[38:39] offset:40
	global_load_b128 v[4:7], v42, s[38:39]
	v_readfirstlane_b32 s2, v2
	v_readfirstlane_b32 s3, v3
	s_mov_b32 s8, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s4, v8
	v_readfirstlane_b32 s5, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[4:5], s[2:3], s[4:5]
	s_mul_i32 s1, s5, 24
	s_mul_hi_u32 s6, s4, 24
	s_mul_i32 s7, s4, 24
	s_and_saveexec_b32 s9, s0
	s_cbranch_execz .LBB1_157
; %bb.156:                              ;   in Loop: Header=BB1_61 Depth=1
	v_dual_mov_b32 v43, s8 :: v_dual_mov_b32 v44, v42
	s_add_i32 s8, s6, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v2, vcc_lo, v4, s7
	v_add_co_ci_u32_e32 v3, vcc_lo, s8, v5, vcc_lo
	global_store_b128 v[2:3], v[43:46], off offset:8
.LBB1_157:                              ;   in Loop: Header=BB1_61 Depth=1
	s_or_b32 exec_lo, exec_lo, s9
	v_cvt_f64_f32_e32 v[2:3], v57
	s_lshl_b64 s[4:5], s[4:5], 12
	v_lshlrev_b64 v[8:9], 6, v[41:42]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v6, vcc_lo, v6, s4
	v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
	s_mov_b32 s21, s20
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v10, vcc_lo, v6, v8
	s_mov_b32 s22, s20
	s_mov_b32 s23, s20
	v_and_or_b32 v0, 0xffffff1d, v0, 34
	v_add_co_ci_u32_e32 v11, vcc_lo, v7, v9, vcc_lo
	v_dual_mov_b32 v6, s20 :: v_dual_mov_b32 v7, s21
	v_dual_mov_b32 v8, s22 :: v_dual_mov_b32 v9, s23
	s_clause 0x3
	global_store_b128 v[10:11], v[0:3], off
	global_store_b128 v[10:11], v[6:9], off offset:16
	global_store_b128 v[10:11], v[6:9], off offset:32
	global_store_b128 v[10:11], v[6:9], off offset:48
	s_and_saveexec_b32 s4, s0
	s_cbranch_execz .LBB1_165
; %bb.158:                              ;   in Loop: Header=BB1_61 Depth=1
	s_clause 0x1
	global_load_b64 v[10:11], v42, s[38:39] offset:32 glc
	global_load_b64 v[0:1], v42, s[38:39] offset:40
	v_dual_mov_b32 v8, s2 :: v_dual_mov_b32 v9, s3
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s8, v0
	v_readfirstlane_b32 s9, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[8:9], s[8:9], s[2:3]
	s_mul_i32 s5, s9, 24
	s_mul_hi_u32 s9, s8, 24
	s_mul_i32 s8, s8, 24
	s_add_i32 s9, s9, s5
	v_add_co_u32 v6, vcc_lo, v4, s8
	v_add_co_ci_u32_e32 v7, vcc_lo, s9, v5, vcc_lo
	s_mov_b32 s5, exec_lo
	global_store_b64 v[6:7], v[10:11], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v42, v[8:11], s[38:39] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[2:3], v[10:11]
	s_cbranch_execz .LBB1_161
; %bb.159:                              ; %.preheader1.i.i.i204.preheader
                                        ;   in Loop: Header=BB1_61 Depth=1
	s_mov_b32 s8, 0
.LBB1_160:                              ; %.preheader1.i.i.i204
                                        ;   Parent Loop BB1_61 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
	s_sleep 1
	global_store_b64 v[6:7], v[2:3], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[0:1], v42, v[0:3], s[38:39] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
	v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
	s_or_b32 s8, vcc_lo, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s8
	s_cbranch_execnz .LBB1_160
.LBB1_161:                              ; %Flow479
                                        ;   in Loop: Header=BB1_61 Depth=1
	s_or_b32 exec_lo, exec_lo, s5
	global_load_b64 v[0:1], v42, s[38:39] offset:16
	s_mov_b32 s8, exec_lo
	s_mov_b32 s5, exec_lo
	v_mbcnt_lo_u32_b32 v2, s8, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB1_163
; %bb.162:                              ;   in Loop: Header=BB1_61 Depth=1
	s_bcnt1_i32_b32 s8, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v41, s8
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[0:1], v[41:42], off offset:8
.LBB1_163:                              ;   in Loop: Header=BB1_61 Depth=1
	s_or_b32 exec_lo, exec_lo, s5
	s_waitcnt vmcnt(0)
	global_load_b64 v[2:3], v[0:1], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
	s_cbranch_vccnz .LBB1_165
; %bb.164:                              ;   in Loop: Header=BB1_61 Depth=1
	global_load_b32 v41, v[0:1], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s5, v41
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[2:3], v[41:42], off
	s_and_b32 m0, s5, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB1_165:                              ; %Flow480
                                        ;   in Loop: Header=BB1_61 Depth=1
	s_or_b32 exec_lo, exec_lo, s4
	s_add_i32 s6, s6, s1
	v_add_co_u32 v0, vcc_lo, v4, s7
	v_add_co_ci_u32_e32 v1, vcc_lo, s6, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, 20
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
.LBB1_166:                              ;   Parent Loop BB1_61 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_mov_b32_e32 v2, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_168
; %bb.167:                              ;   in Loop: Header=BB1_166 Depth=2
	global_load_b32 v2, v[0:1], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v2, 1, v2
.LBB1_168:                              ;   in Loop: Header=BB1_166 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v2
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB1_170
; %bb.169:                              ;   in Loop: Header=BB1_166 Depth=2
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB1_171
.LBB1_170:                              ;   in Loop: Header=BB1_166 Depth=2
	s_mov_b32 s1, -1
.LBB1_171:                              ; %Flow474
                                        ;   in Loop: Header=BB1_166 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB1_166
; %bb.172:                              ;   in Loop: Header=BB1_61 Depth=1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_176
; %bb.173:                              ;   in Loop: Header=BB1_61 Depth=1
	s_clause 0x2
	global_load_b64 v[2:3], v42, s[38:39] offset:40
	global_load_b64 v[6:7], v42, s[38:39] offset:24 glc
	global_load_b64 v[4:5], v42, s[38:39]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v8, vcc_lo, v2, 1
	v_add_co_ci_u32_e32 v9, vcc_lo, 0, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v8, s2
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
	v_dual_cndmask_b32 v1, v1, v9 :: v_dual_cndmask_b32 v0, v0, v8
	v_and_b32_e32 v3, v1, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v2, v0, v2
	v_mul_hi_u32 v8, v2, 24
	v_mul_lo_u32 v2, v2, 24
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_u32 v4, vcc_lo, v4, v2
	v_mov_b32_e32 v2, v6
	v_mul_lo_u32 v3, v3, 24
	v_add_nc_u32_e32 v3, v8, v3
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
	v_mov_b32_e32 v3, v7
	global_store_b64 v[4:5], v[6:7], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v42, v[0:3], s[38:39] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[6:7]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB1_176
; %bb.174:                              ; %.preheader.i.i.i203.preheader
                                        ;   in Loop: Header=BB1_61 Depth=1
	s_mov_b32 s0, 0
.LBB1_175:                              ; %.preheader.i.i.i203
                                        ;   Parent Loop BB1_61 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	global_store_b64 v[4:5], v[2:3], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[6:7], v42, v[0:3], s[38:39] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[2:3]
	v_dual_mov_b32 v2, v6 :: v_dual_mov_b32 v3, v7
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB1_175
.LBB1_176:                              ; %Flow472
                                        ;   in Loop: Header=BB1_61 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
.LBB1_177:                              ; %__ockl_printf_append_args.exit207
                                        ;   in Loop: Header=BB1_61 Depth=1
	s_add_i32 s74, s74, 1
	s_add_i32 s28, s28, 62
	v_cmp_ne_u32_e32 vcc_lo, s74, v55
	s_add_i32 s34, s34, 62
	s_add_i32 s36, s36, 62
	s_cbranch_vccnz .LBB1_61
.LBB1_178:                              ; %Flow529
	s_or_b32 exec_lo, exec_lo, s33
	s_waitcnt lgkmcnt(0)
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z13CalculateTheDiPfS_S_S_S_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 312
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 58
		.amdhsa_next_free_sgpr 76
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z13CalculateTheDiPfS_S_S_S_S_, .Lfunc_end1-_Z13CalculateTheDiPfS_S_S_S_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 12668
; NumSgprs: 78
; NumVgprs: 58
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 9
; VGPRBlocks: 7
; NumSGPRsForWavesPerEU: 78
; NumVGPRsForWavesPerEU: 58
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z21CalculatePArrayKerneliiiPfS_S_S_ ; -- Begin function _Z21CalculatePArrayKerneliiiPfS_S_S_
	.globl	_Z21CalculatePArrayKerneliiiPfS_S_S_
	.p2align	8
	.type	_Z21CalculatePArrayKerneliiiPfS_S_S_,@function
_Z21CalculatePArrayKerneliiiPfS_S_S_:   ; @_Z21CalculatePArrayKerneliiiPfS_S_S_
; %bb.0:
	s_load_b32 s33, s[0:1], 0x0
	s_mov_b32 s8, 0
	s_mov_b32 s10, 0x55555555
	s_mov_b32 s11, 0x3fe55555
	s_mov_b32 s12, 0x968915a9
	s_mov_b32 s14, 0x4222de17
	s_mov_b32 s13, 0x3fba6564
	s_mov_b32 s15, 0x3fbdee67
	s_mov_b32 s16, 0x3abe935a
	s_mov_b32 s17, 0x3fbe25e4
	s_mov_b32 s18, 0x47e6c9c2
	s_mov_b32 s19, 0x3fc110ef
	s_mov_b32 s20, 0xcfa74449
	s_mov_b32 s21, 0x3fc3b13b
	s_mov_b32 s22, 0x71bf3c30
	s_mov_b32 s23, 0x3fc745d1
	s_mov_b32 s24, 0x1c7792ce
	s_mov_b32 s25, 0x3fcc71c7
	s_mov_b32 s26, 0x924920da
	s_mov_b32 s27, 0x3fd24924
	s_waitcnt lgkmcnt(0)
	s_sub_i32 s3, 6, s33
	s_cmp_eq_u32 s33, 6
	s_mov_b32 s28, 0x9999999c
	s_cselect_b32 s9, 0x3ff00000, 2.0
	s_sub_i32 s4, 7, s33
	s_cmp_eq_u32 s33, 7
	v_frexp_mant_f64_e32 v[1:2], s[8:9]
	v_frexp_exp_i32_f64_e32 v41, s[8:9]
	s_cselect_b32 s9, 0x3ff00000, 2.0
	s_mov_b32 s29, 0x3fd99999
	v_frexp_mant_f64_e32 v[3:4], s[8:9]
	s_mov_b32 s31, 0xbfe55555
	s_mov_b32 s30, s10
	s_mov_b32 s34, 0xd5df274d
	s_mov_b32 s35, 0x3c8543b0
	s_mov_b32 s36, 0xfefa39ef
	s_mov_b32 s37, 0x3fe62e42
	s_mov_b32 s38, 0x3b39803f
	s_mov_b32 s39, 0x3c7abc9e
	s_mov_b32 s62, 0x652b82fe
	s_mov_b32 s40, 0xfca7ab0c
	s_mov_b32 s44, 0x6a5dcb37
	s_mov_b32 s46, 0x623fde64
	s_mov_b32 s48, 0x7c89e6b0
	s_mov_b32 s50, 0x14761f6e
	s_mov_b32 s52, 0x1852b7b0
	s_mov_b32 s54, 0x11122322
	s_mov_b32 s56, 0x555502a1
	s_mov_b32 s58, 0x55555511
	s_mov_b32 s60, 11
	s_mov_b32 s63, 0x3ff71547
	s_mov_b32 s43, 0xbfe62e42
	s_mov_b32 s41, 0x3e928af3
	s_mov_b32 s45, 0x3e5ade15
	s_mov_b32 s47, 0x3ec71dee
	s_mov_b32 s49, 0x3efa0199
	s_mov_b32 s51, 0x3f2a01a0
	s_mov_b32 s53, 0x3f56c16c
	s_mov_b32 s55, 0x3f811111
	s_mov_b32 s57, 0x3fa55555
	s_mov_b32 s59, 0x3fc55555
	s_mov_b32 s61, 0x3fe00000
	s_mov_b32 s42, s36
	s_mov_b32 s65, 0xbc7abc9e
	v_cmp_gt_f64_e32 vcc_lo, s[10:11], v[1:2]
	s_cmp_lg_u32 s33, 1
	s_mov_b32 s64, s38
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cmp_gt_f64_e64 s2, s[10:11], v[3:4]
	v_cndmask_b32_e64 v5, 0, 1, vcc_lo
	v_cndmask_b32_e64 v6, 0, 1, s2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ldexp_f64 v[1:2], v[1:2], v5
	v_ldexp_f64 v[3:4], v[3:4], v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[5:6], v[1:2], 1.0
	v_add_f64 v[17:18], v[1:2], -1.0
	v_add_f64 v[7:8], v[3:4], 1.0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_rcp_f64_e32 v[9:10], v[5:6]
	v_add_f64 v[21:22], v[5:6], -1.0
	v_rcp_f64_e32 v[11:12], v[7:8]
	v_add_f64 v[25:26], v[7:8], -1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_add_f64 v[1:2], v[1:2], -v[21:22]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[13:14], -v[5:6], v[9:10], 1.0
	v_fma_f64 v[15:16], -v[7:8], v[11:12], 1.0
	v_fma_f64 v[9:10], v[13:14], v[9:10], v[9:10]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[11:12], v[15:16], v[11:12], v[11:12]
	v_fma_f64 v[13:14], -v[5:6], v[9:10], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[15:16], -v[7:8], v[11:12], 1.0
	v_fma_f64 v[9:10], v[13:14], v[9:10], v[9:10]
	v_add_f64 v[13:14], v[3:4], -1.0
	v_add_f64 v[3:4], v[3:4], -v[25:26]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[11:12], v[15:16], v[11:12], v[11:12]
	v_mul_f64 v[15:16], v[17:18], v[9:10]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[19:20], v[13:14], v[11:12]
	v_mul_f64 v[23:24], v[5:6], v[15:16]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[27:28], v[7:8], v[19:20]
	v_fma_f64 v[5:6], v[15:16], v[5:6], -v[23:24]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[7:8], v[19:20], v[7:8], -v[27:28]
	v_fma_f64 v[1:2], v[15:16], v[1:2], v[5:6]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[3:4], v[19:20], v[3:4], v[7:8]
	v_add_f64 v[5:6], v[23:24], v[1:2]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[7:8], v[27:28], v[3:4]
	v_add_f64 v[21:22], v[17:18], -v[5:6]
	v_add_f64 v[23:24], v[5:6], -v[23:24]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f64 v[25:26], v[13:14], -v[7:8]
	v_add_f64 v[27:28], v[7:8], -v[27:28]
	v_add_f64 v[17:18], v[17:18], -v[21:22]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[1:2], v[23:24], -v[1:2]
	v_add_f64 v[13:14], v[13:14], -v[25:26]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[3:4], v[27:28], -v[3:4]
	v_add_f64 v[5:6], v[17:18], -v[5:6]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[7:8], v[13:14], -v[7:8]
	v_add_f64 v[1:2], v[1:2], v[5:6]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[3:4], v[3:4], v[7:8]
	v_add_f64 v[1:2], v[21:22], v[1:2]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[3:4], v[25:26], v[3:4]
	v_mul_f64 v[1:2], v[9:10], v[1:2]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[3:4], v[11:12], v[3:4]
	v_add_f64 v[5:6], v[15:16], v[1:2]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[7:8], v[19:20], v[3:4]
	v_add_f64 v[9:10], v[5:6], -v[15:16]
	v_mul_f64 v[13:14], v[5:6], v[5:6]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[11:12], v[7:8], -v[19:20]
	v_add_f64 v[1:2], v[1:2], -v[9:10]
	v_mul_f64 v[9:10], v[7:8], v[7:8]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f64 v[3:4], v[3:4], -v[11:12]
	v_fma_f64 v[11:12], v[5:6], v[5:6], -v[13:14]
	v_add_f64 v[15:16], v[1:2], v[1:2]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[17:18], v[7:8], v[7:8], -v[9:10]
	v_add_f64 v[19:20], v[3:4], v[3:4]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[11:12], v[5:6], v[15:16], v[11:12]
	v_fma_f64 v[15:16], v[7:8], v[19:20], v[17:18]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[17:18], v[13:14], v[11:12]
	v_add_f64 v[19:20], v[9:10], v[15:16]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_fma_f64 v[21:22], v[17:18], s[14:15], s[12:13]
	v_add_f64 v[13:14], v[17:18], -v[13:14]
	v_mul_f64 v[31:32], v[5:6], v[17:18]
	v_fma_f64 v[23:24], v[19:20], s[14:15], s[12:13]
	v_add_f64 v[9:10], v[19:20], -v[9:10]
	v_mul_f64 v[35:36], v[7:8], v[19:20]
	v_fma_f64 v[21:22], v[17:18], v[21:22], s[16:17]
	v_add_f64 v[11:12], v[11:12], -v[13:14]
	v_fma_f64 v[23:24], v[19:20], v[23:24], s[16:17]
	v_add_f64 v[9:10], v[15:16], -v[9:10]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[21:22], v[17:18], v[21:22], s[18:19]
	v_fma_f64 v[23:24], v[19:20], v[23:24], s[18:19]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[21:22], v[17:18], v[21:22], s[20:21]
	v_fma_f64 v[23:24], v[19:20], v[23:24], s[20:21]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[21:22], v[17:18], v[21:22], s[22:23]
	v_fma_f64 v[23:24], v[19:20], v[23:24], s[22:23]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[21:22], v[17:18], v[21:22], s[24:25]
	v_fma_f64 v[23:24], v[19:20], v[23:24], s[24:25]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[21:22], v[17:18], v[21:22], s[26:27]
	v_fma_f64 v[23:24], v[19:20], v[23:24], s[26:27]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[21:22], v[17:18], v[21:22], s[28:29]
	v_fma_f64 v[23:24], v[19:20], v[23:24], s[28:29]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[25:26], v[17:18], v[21:22]
	v_mul_f64 v[27:28], v[19:20], v[23:24]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[13:14], v[17:18], v[21:22], -v[25:26]
	v_fma_f64 v[15:16], v[19:20], v[23:24], -v[27:28]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[13:14], v[11:12], v[21:22], v[13:14]
	v_fma_f64 v[15:16], v[9:10], v[23:24], v[15:16]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[21:22], v[25:26], v[13:14]
	v_add_f64 v[23:24], v[27:28], v[15:16]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[29:30], v[21:22], s[10:11]
	v_add_f64 v[25:26], v[21:22], -v[25:26]
	v_add_f64 v[33:34], v[23:24], s[10:11]
	v_add_f64 v[27:28], v[23:24], -v[27:28]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[37:38], v[29:30], s[30:31]
	v_add_f64 v[13:14], v[13:14], -v[25:26]
	v_fma_f64 v[25:26], v[17:18], v[5:6], -v[31:32]
	v_add_f64 v[39:40], v[33:34], s[30:31]
	v_add_f64 v[15:16], v[15:16], -v[27:28]
	v_fma_f64 v[27:28], v[19:20], v[7:8], -v[35:36]
	v_add_f64 v[21:22], v[21:22], -v[37:38]
	v_add_f64 v[13:14], v[13:14], s[34:35]
	v_fma_f64 v[17:18], v[17:18], v[1:2], v[25:26]
	v_ldexp_f64 v[1:2], v[1:2], 1
	v_add_f64 v[23:24], v[23:24], -v[39:40]
	v_add_f64 v[15:16], v[15:16], s[34:35]
	v_fma_f64 v[19:20], v[19:20], v[3:4], v[27:28]
	v_ldexp_f64 v[3:4], v[3:4], 1
	v_add_f64 v[13:14], v[13:14], v[21:22]
	v_fma_f64 v[11:12], v[11:12], v[5:6], v[17:18]
	v_ldexp_f64 v[5:6], v[5:6], 1
	v_add_f64 v[15:16], v[15:16], v[23:24]
	v_fma_f64 v[9:10], v[9:10], v[7:8], v[19:20]
	v_ldexp_f64 v[7:8], v[7:8], 1
	v_add_f64 v[17:18], v[29:30], v[13:14]
	v_add_f64 v[19:20], v[31:32], v[11:12]
	v_add_f64 v[21:22], v[33:34], v[15:16]
	v_add_f64 v[23:24], v[35:36], v[9:10]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[25:26], v[29:30], -v[17:18]
	v_mul_f64 v[27:28], v[19:20], v[17:18]
	v_add_f64 v[31:32], v[19:20], -v[31:32]
	v_add_f64 v[29:30], v[33:34], -v[21:22]
	v_mul_f64 v[33:34], v[23:24], v[21:22]
	v_add_f64 v[35:36], v[23:24], -v[35:36]
	v_add_f64 v[13:14], v[13:14], v[25:26]
	v_fma_f64 v[25:26], v[19:20], v[17:18], -v[27:28]
	v_add_f64 v[11:12], v[11:12], -v[31:32]
	v_add_f64 v[15:16], v[15:16], v[29:30]
	v_fma_f64 v[29:30], v[23:24], v[21:22], -v[33:34]
	v_add_f64 v[9:10], v[9:10], -v[35:36]
	v_fma_f64 v[13:14], v[19:20], v[13:14], v[25:26]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[15:16], v[23:24], v[15:16], v[29:30]
	v_fma_f64 v[11:12], v[11:12], v[17:18], v[13:14]
	v_frexp_exp_i32_f64_e32 v17, s[8:9]
	v_subrev_co_ci_u32_e32 v18, vcc_lo, 0, v41, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[9:10], v[9:10], v[21:22], v[15:16]
	v_add_f64 v[13:14], v[27:28], v[11:12]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_subrev_co_ci_u32_e64 v19, vcc_lo, 0, v17, s2
	v_cvt_f64_i32_e32 v[17:18], v18
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[15:16], v[33:34], v[9:10]
	v_cvt_f64_i32_e32 v[19:20], v19
	v_add_f64 v[21:22], v[5:6], v[13:14]
	v_add_f64 v[23:24], v[13:14], -v[27:28]
	v_mul_f64 v[29:30], v[17:18], s[36:37]
	v_add_f64 v[25:26], v[7:8], v[15:16]
	v_add_f64 v[27:28], v[15:16], -v[33:34]
	v_mul_f64 v[31:32], v[19:20], s[36:37]
	v_add_f64 v[5:6], v[21:22], -v[5:6]
	v_add_f64 v[11:12], v[11:12], -v[23:24]
	v_fma_f64 v[23:24], v[17:18], s[36:37], -v[29:30]
	v_add_f64 v[7:8], v[25:26], -v[7:8]
	v_add_f64 v[9:10], v[9:10], -v[27:28]
	v_add_f64 v[5:6], v[13:14], -v[5:6]
	v_add_f64 v[1:2], v[1:2], v[11:12]
	v_fma_f64 v[11:12], v[19:20], s[36:37], -v[31:32]
	v_add_f64 v[7:8], v[15:16], -v[7:8]
	v_add_f64 v[3:4], v[3:4], v[9:10]
	v_fma_f64 v[9:10], v[17:18], s[38:39], v[23:24]
	v_add_f64 v[1:2], v[1:2], v[5:6]
	v_fma_f64 v[5:6], v[19:20], s[38:39], v[11:12]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[3:4], v[3:4], v[7:8]
	v_add_f64 v[7:8], v[29:30], v[9:10]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[11:12], v[21:22], v[1:2]
	v_add_f64 v[13:14], v[31:32], v[5:6]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[15:16], v[25:26], v[3:4]
	v_add_f64 v[29:30], v[7:8], -v[29:30]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[17:18], v[7:8], v[11:12]
	v_add_f64 v[31:32], v[13:14], -v[31:32]
	v_add_f64 v[21:22], v[11:12], -v[21:22]
	v_add_f64 v[19:20], v[13:14], v[15:16]
	v_add_f64 v[25:26], v[15:16], -v[25:26]
	v_add_f64 v[9:10], v[9:10], -v[29:30]
	v_add_f64 v[23:24], v[17:18], -v[7:8]
	v_add_f64 v[5:6], v[5:6], -v[31:32]
	v_add_f64 v[1:2], v[1:2], -v[21:22]
	v_add_f64 v[27:28], v[19:20], -v[13:14]
	v_add_f64 v[3:4], v[3:4], -v[25:26]
	v_add_f64 v[33:34], v[17:18], -v[23:24]
	v_add_f64 v[11:12], v[11:12], -v[23:24]
	v_add_f64 v[21:22], v[9:10], v[1:2]
	v_add_f64 v[35:36], v[19:20], -v[27:28]
	v_add_f64 v[15:16], v[15:16], -v[27:28]
	v_add_f64 v[7:8], v[7:8], -v[33:34]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[13:14], v[13:14], -v[35:36]
	v_add_f64 v[7:8], v[11:12], v[7:8]
	v_add_f64 v[11:12], v[5:6], v[3:4]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f64 v[13:14], v[15:16], v[13:14]
	v_add_f64 v[15:16], v[21:22], -v[9:10]
	v_add_f64 v[7:8], v[21:22], v[7:8]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[23:24], v[11:12], -v[5:6]
	v_add_f64 v[13:14], v[11:12], v[13:14]
	s_delay_alu instid0(VALU_DEP_4)
	v_add_f64 v[21:22], v[21:22], -v[15:16]
	v_add_f64 v[1:2], v[1:2], -v[15:16]
	v_add_f64 v[25:26], v[17:18], v[7:8]
	v_add_f64 v[11:12], v[11:12], -v[23:24]
	v_add_f64 v[3:4], v[3:4], -v[23:24]
	v_add_f64 v[27:28], v[19:20], v[13:14]
	v_add_f64 v[9:10], v[9:10], -v[21:22]
	v_add_f64 v[15:16], v[25:26], -v[17:18]
	v_add_f64 v[5:6], v[5:6], -v[11:12]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[11:12], v[27:28], -v[19:20]
	v_add_f64 v[1:2], v[1:2], v[9:10]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[7:8], v[7:8], -v[15:16]
	v_add_f64 v[3:4], v[3:4], v[5:6]
	v_cvt_f64_i32_e32 v[15:16], s4
	v_add_f64 v[5:6], v[13:14], -v[11:12]
	v_cvt_f64_i32_e32 v[11:12], s3
	v_add_f64 v[9:10], v[1:2], v[7:8]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[3:4], v[3:4], v[5:6]
	v_add_f64 v[5:6], v[25:26], v[9:10]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[13:14], v[27:28], v[3:4]
	v_add_f64 v[17:18], v[5:6], -v[25:26]
	v_mul_f64 v[1:2], v[5:6], v[11:12]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f64 v[19:20], v[13:14], -v[27:28]
	v_mul_f64 v[7:8], v[13:14], v[15:16]
	v_add_f64 v[9:10], v[9:10], -v[17:18]
	s_delay_alu instid0(VALU_DEP_4)
	v_fma_f64 v[5:6], v[11:12], v[5:6], -v[1:2]
	v_cmp_class_f64_e64 vcc_lo, v[1:2], 0x204
	v_add_f64 v[17:18], v[3:4], -v[19:20]
	v_fma_f64 v[13:14], v[15:16], v[13:14], -v[7:8]
	v_cmp_class_f64_e64 s2, v[7:8], 0x204
	v_fma_f64 v[3:4], v[11:12], v[9:10], v[5:6]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[5:6], v[15:16], v[17:18], v[13:14]
	v_add_f64 v[9:10], v[1:2], v[3:4]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[11:12], v[7:8], v[5:6]
	v_dual_cndmask_b32 v14, v10, v2 :: v_dual_cndmask_b32 v13, v9, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v16, v12, v8, s2
	v_cndmask_b32_e64 v15, v11, v7, s2
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_cmp_neq_f64_e64 s5, 0x7ff00000, |v[13:14]|
	v_cmp_nlt_f64_e64 s2, 0x40900000, v[13:14]
	v_cmp_ngt_f64_e32 vcc_lo, 0xc090cc00, v[13:14]
	v_cmp_neq_f64_e64 s6, 0x7ff00000, |v[15:16]|
	v_cmp_nlt_f64_e64 s4, 0x40900000, v[15:16]
	v_cmp_ngt_f64_e64 s3, 0xc090cc00, v[15:16]
	s_cbranch_scc1 .LBB2_2
; %bb.1:
	v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, 0
	s_mov_b32 s66, 0
	s_mov_b32 s67, 32
	s_branch .LBB2_3
.LBB2_2:
	v_mul_f64 v[17:18], v[13:14], s[62:63]
	v_mul_f64 v[19:20], v[15:16], s[62:63]
	v_add_f64 v[1:2], v[9:10], -v[1:2]
	v_add_f64 v[7:8], v[11:12], -v[7:8]
	s_mov_b32 s66, 64
	s_mov_b32 s67, 0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_rndne_f64_e32 v[17:18], v[17:18]
	v_rndne_f64_e32 v[19:20], v[19:20]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[1:2], v[3:4], -v[1:2]
	v_add_f64 v[3:4], v[5:6], -v[7:8]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[13:14], v[17:18], s[42:43], v[13:14]
	v_fma_f64 v[15:16], v[19:20], s[42:43], v[15:16]
	s_delay_alu instid0(VALU_DEP_4)
	v_cndmask_b32_e64 v2, 0, v2, s5
	v_cndmask_b32_e64 v1, 0, v1, s5
	v_cndmask_b32_e64 v4, 0, v4, s6
	v_cndmask_b32_e64 v3, 0, v3, s6
	v_fma_f64 v[13:14], v[17:18], s[64:65], v[13:14]
	v_fma_f64 v[15:16], v[19:20], s[64:65], v[15:16]
	v_cvt_i32_f64_e32 v17, v[17:18]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[21:22], v[13:14], s[44:45], s[40:41]
	v_fma_f64 v[23:24], v[15:16], s[44:45], s[40:41]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[21:22], v[13:14], v[21:22], s[46:47]
	v_fma_f64 v[23:24], v[15:16], v[23:24], s[46:47]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[21:22], v[13:14], v[21:22], s[48:49]
	v_fma_f64 v[23:24], v[15:16], v[23:24], s[48:49]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[21:22], v[13:14], v[21:22], s[50:51]
	v_fma_f64 v[23:24], v[15:16], v[23:24], s[50:51]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[21:22], v[13:14], v[21:22], s[52:53]
	v_fma_f64 v[23:24], v[15:16], v[23:24], s[52:53]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[21:22], v[13:14], v[21:22], s[54:55]
	v_fma_f64 v[23:24], v[15:16], v[23:24], s[54:55]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[21:22], v[13:14], v[21:22], s[56:57]
	v_fma_f64 v[23:24], v[15:16], v[23:24], s[56:57]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[21:22], v[13:14], v[21:22], s[58:59]
	v_fma_f64 v[23:24], v[15:16], v[23:24], s[58:59]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[21:22], v[13:14], v[21:22], s[60:61]
	v_fma_f64 v[23:24], v[15:16], v[23:24], s[60:61]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[21:22], v[13:14], v[21:22], 1.0
	v_fma_f64 v[23:24], v[15:16], v[23:24], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fma_f64 v[9:10], v[13:14], v[21:22], 1.0
	v_cvt_i32_f64_e32 v13, v[19:20]
	v_fma_f64 v[11:12], v[15:16], v[23:24], 1.0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ldexp_f64 v[5:6], v[9:10], v17
	v_ldexp_f64 v[7:8], v[11:12], v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v6, 0x7ff00000, v6, s2
	s_and_b32 s2, vcc_lo, s2
	v_cndmask_b32_e64 v8, 0x7ff00000, v8, s4
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v5, 0, v5, s2
	v_cndmask_b32_e32 v6, 0, v6, vcc_lo
	s_and_b32 vcc_lo, s3, s4
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v8, 0, v8, s3
	v_cndmask_b32_e32 v7, 0, v7, vcc_lo
	v_fma_f64 v[1:2], v[5:6], v[1:2], v[5:6]
	v_cmp_class_f64_e64 vcc_lo, v[5:6], 0x204
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_fma_f64 v[3:4], v[7:8], v[3:4], v[7:8]
	v_cmp_class_f64_e64 s2, v[7:8], 0x204
	v_dual_cndmask_b32 v2, v2, v6 :: v_dual_cndmask_b32 v1, v1, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v4, v4, v8, s2
	v_cndmask_b32_e64 v3, v3, v7, s2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_i32_f64_e64 v1, |v[1:2]|
	v_cvt_i32_f64_e64 v2, |v[3:4]|
.LBB2_3:
	s_sub_i32 s2, 5, s33
	s_cmp_eq_u32 s33, 5
	s_cselect_b32 s9, 0x3ff00000, 2.0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_frexp_mant_f64_e32 v[3:4], s[8:9]
	v_cmp_gt_f64_e32 vcc_lo, s[10:11], v[3:4]
	v_cndmask_b32_e64 v5, 0, 1, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ldexp_f64 v[3:4], v[3:4], v5
	v_add_f64 v[5:6], v[3:4], 1.0
	v_add_f64 v[11:12], v[3:4], -1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[7:8], v[5:6]
	v_add_f64 v[13:14], v[5:6], -1.0
	v_add_f64 v[3:4], v[3:4], -v[13:14]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[9:10], -v[5:6], v[7:8], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[7:8], v[9:10], v[7:8], v[7:8]
	v_fma_f64 v[9:10], -v[5:6], v[7:8], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[7:8], v[9:10], v[7:8], v[7:8]
	v_mul_f64 v[9:10], v[11:12], v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[15:16], v[5:6], v[9:10]
	v_fma_f64 v[5:6], v[9:10], v[5:6], -v[15:16]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[3:4], v[9:10], v[3:4], v[5:6]
	v_add_f64 v[5:6], v[15:16], v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[13:14], v[11:12], -v[5:6]
	v_add_f64 v[15:16], v[5:6], -v[15:16]
	v_add_f64 v[11:12], v[11:12], -v[13:14]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[3:4], v[15:16], -v[3:4]
	v_add_f64 v[5:6], v[11:12], -v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[3:4], v[3:4], v[5:6]
	v_add_f64 v[3:4], v[13:14], v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[3:4], v[7:8], v[3:4]
	v_add_f64 v[5:6], v[9:10], v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[7:8], v[5:6], -v[9:10]
	v_mul_f64 v[9:10], v[5:6], v[5:6]
	v_add_f64 v[3:4], v[3:4], -v[7:8]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[7:8], v[5:6], v[5:6], -v[9:10]
	v_add_f64 v[11:12], v[3:4], v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[7:8], v[5:6], v[11:12], v[7:8]
	v_add_f64 v[11:12], v[9:10], v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_fma_f64 v[13:14], v[11:12], s[14:15], s[12:13]
	v_add_f64 v[9:10], v[11:12], -v[9:10]
	v_mul_f64 v[19:20], v[5:6], v[11:12]
	v_fma_f64 v[13:14], v[11:12], v[13:14], s[16:17]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[7:8], v[7:8], -v[9:10]
	v_fma_f64 v[13:14], v[11:12], v[13:14], s[18:19]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[13:14], v[11:12], v[13:14], s[20:21]
	v_fma_f64 v[13:14], v[11:12], v[13:14], s[22:23]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[13:14], v[11:12], v[13:14], s[24:25]
	v_fma_f64 v[13:14], v[11:12], v[13:14], s[26:27]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[13:14], v[11:12], v[13:14], s[28:29]
	v_mul_f64 v[15:16], v[11:12], v[13:14]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[9:10], v[11:12], v[13:14], -v[15:16]
	v_fma_f64 v[9:10], v[7:8], v[13:14], v[9:10]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[13:14], v[15:16], v[9:10]
	v_add_f64 v[17:18], v[13:14], s[10:11]
	v_add_f64 v[15:16], v[13:14], -v[15:16]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[21:22], v[17:18], s[30:31]
	v_add_f64 v[9:10], v[9:10], -v[15:16]
	v_fma_f64 v[15:16], v[11:12], v[5:6], -v[19:20]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[13:14], v[13:14], -v[21:22]
	v_add_f64 v[9:10], v[9:10], s[34:35]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fma_f64 v[11:12], v[11:12], v[3:4], v[15:16]
	v_ldexp_f64 v[3:4], v[3:4], 1
	v_add_f64 v[9:10], v[9:10], v[13:14]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fma_f64 v[7:8], v[7:8], v[5:6], v[11:12]
	v_ldexp_f64 v[5:6], v[5:6], 1
	v_add_f64 v[11:12], v[17:18], v[9:10]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[13:14], v[19:20], v[7:8]
	v_add_f64 v[15:16], v[17:18], -v[11:12]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_f64 v[17:18], v[13:14], v[11:12]
	v_add_f64 v[19:20], v[13:14], -v[19:20]
	v_add_f64 v[9:10], v[9:10], v[15:16]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[15:16], v[13:14], v[11:12], -v[17:18]
	v_add_f64 v[7:8], v[7:8], -v[19:20]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[9:10], v[13:14], v[9:10], v[15:16]
	v_fma_f64 v[7:8], v[7:8], v[11:12], v[9:10]
	v_frexp_exp_i32_f64_e32 v11, s[8:9]
	s_mov_b32 s8, exec_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[9:10], v[17:18], v[7:8]
	v_subrev_co_ci_u32_e32 v11, vcc_lo, 0, v11, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cvt_f64_i32_e32 v[11:12], v11
	v_add_f64 v[13:14], v[5:6], v[9:10]
	v_add_f64 v[15:16], v[9:10], -v[17:18]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f64 v[17:18], v[11:12], s[36:37]
	v_add_f64 v[5:6], v[13:14], -v[5:6]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[7:8], v[7:8], -v[15:16]
	v_fma_f64 v[15:16], v[11:12], s[36:37], -v[17:18]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[5:6], v[9:10], -v[5:6]
	v_add_f64 v[3:4], v[3:4], v[7:8]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[7:8], v[11:12], s[38:39], v[15:16]
	v_add_f64 v[3:4], v[3:4], v[5:6]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[5:6], v[17:18], v[7:8]
	v_add_f64 v[9:10], v[13:14], v[3:4]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[17:18], v[5:6], -v[17:18]
	v_add_f64 v[11:12], v[5:6], v[9:10]
	v_add_f64 v[13:14], v[9:10], -v[13:14]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[7:8], v[7:8], -v[17:18]
	v_add_f64 v[15:16], v[11:12], -v[5:6]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[3:4], v[3:4], -v[13:14]
	v_add_f64 v[19:20], v[11:12], -v[15:16]
	v_add_f64 v[9:10], v[9:10], -v[15:16]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[13:14], v[7:8], v[3:4]
	v_add_f64 v[5:6], v[5:6], -v[19:20]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[5:6], v[9:10], v[5:6]
	v_add_f64 v[9:10], v[13:14], -v[7:8]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[5:6], v[13:14], v[5:6]
	v_add_f64 v[13:14], v[13:14], -v[9:10]
	v_add_f64 v[3:4], v[3:4], -v[9:10]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[15:16], v[11:12], v[5:6]
	v_add_f64 v[7:8], v[7:8], -v[13:14]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[9:10], v[15:16], -v[11:12]
	v_add_f64 v[3:4], v[3:4], v[7:8]
	v_cvt_f64_i32_e32 v[7:8], s2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[5:6], v[5:6], -v[9:10]
	v_add_f64 v[3:4], v[3:4], v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[5:6], v[15:16], v[3:4]
	v_add_f64 v[9:10], v[5:6], -v[15:16]
	v_mul_f64 v[11:12], v[5:6], v[7:8]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[3:4], v[3:4], -v[9:10]
	v_fma_f64 v[5:6], v[7:8], v[5:6], -v[11:12]
	v_cmp_class_f64_e64 vcc_lo, v[11:12], 0x204
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[3:4], v[7:8], v[3:4], v[5:6]
	v_add_f64 v[5:6], v[11:12], v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v8, v6, v12 :: v_dual_cndmask_b32 v7, v5, v11
	v_add_f64 v[5:6], v[5:6], -v[11:12]
	v_mul_f64 v[9:10], v[7:8], s[62:63]
	v_cmp_nlt_f64_e64 s2, 0x40900000, v[7:8]
	v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[7:8]|
	v_cmp_ngt_f64_e64 s3, 0xc090cc00, v[7:8]
	v_add_f64 v[3:4], v[3:4], -v[5:6]
	v_rndne_f64_e32 v[9:10], v[9:10]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_cndmask_b32 v4, 0, v4 :: v_dual_cndmask_b32 v3, 0, v3
	s_and_b32 vcc_lo, s3, s2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_fma_f64 v[13:14], v[9:10], s[42:43], v[7:8]
	v_cvt_i32_f64_e32 v17, v[9:10]
	v_bfe_u32 v7, v0, 10, 10
	v_and_b32_e32 v0, 0x3ff, v0
	v_fma_f64 v[13:14], v[9:10], s[64:65], v[13:14]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[15:16], v[13:14], s[44:45], s[40:41]
	v_fma_f64 v[15:16], v[13:14], v[15:16], s[46:47]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[15:16], v[13:14], v[15:16], s[48:49]
	v_fma_f64 v[15:16], v[13:14], v[15:16], s[50:51]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[15:16], v[13:14], v[15:16], s[52:53]
	v_fma_f64 v[15:16], v[13:14], v[15:16], s[54:55]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[15:16], v[13:14], v[15:16], s[56:57]
	v_fma_f64 v[15:16], v[13:14], v[15:16], s[58:59]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[15:16], v[13:14], v[15:16], s[60:61]
	v_fma_f64 v[15:16], v[13:14], v[15:16], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[9:10], v[13:14], v[15:16], 1.0
	v_ldexp_f64 v[9:10], v[9:10], v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v5, 0x7ff00000, v10, s2
	s_load_b32 s2, s[0:1], 0x8
	v_cndmask_b32_e64 v6, 0, v5, s3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v5, 0, v9, vcc_lo
	v_fma_f64 v[3:4], v[5:6], v[3:4], v[5:6]
	v_cmp_class_f64_e64 vcc_lo, v[5:6], 0x204
	s_waitcnt lgkmcnt(0)
	v_mul_lo_u32 v7, v7, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add3_u32 v0, v0, v7, 1
	v_dual_cndmask_b32 v4, v4, v6 :: v_dual_cndmask_b32 v3, v3, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_f64_i32_e32 v[5:6], v0
	v_add_f64 v[3:4], |v[3:4]|, -1.0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_ge_f64_e32 v[3:4], v[5:6]
	s_cbranch_execz .LBB2_5
; %bb.4:
	v_lshlrev_b32_e32 v3, 1, v0
	v_add_nc_u32_e32 v2, s33, v2
	s_load_b256 s[0:7], s[0:1], 0x10
	s_not_b32 s9, s33
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add3_u32 v0, s67, s9, v0
	v_sub_nc_u32_e32 v2, v3, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v0, v0, v1
	v_add_nc_u32_e32 v2, s66, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v0, s66, v0
	v_ashrrev_i32_e32 v3, 31, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[2:3]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v5, vcc_lo, s0, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v6, vcc_lo, s1, v4, vcc_lo
	v_add_co_u32 v7, vcc_lo, s2, v3
	v_add_co_ci_u32_e32 v8, vcc_lo, s3, v4, vcc_lo
	global_load_b64 v[9:10], v[5:6], off offset:-4
	global_load_b32 v2, v[7:8], off offset:-4
	s_waitcnt vmcnt(1)
	v_mul_f32_e64 v11, v9, -v10
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f32 v9, null, v2, v2, v11
	v_div_scale_f32 v13, vcc_lo, v11, v2, v11
	v_rcp_f32_e32 v12, v9
	s_waitcnt_depctr 0xfff
	v_fma_f32 v10, -v9, v12, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v12, v10, v12
	v_mul_f32_e32 v14, v13, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v1, -v9, v14, v13
	v_fmac_f32_e32 v14, v1, v12
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v13, -v9, v14, v13
	v_lshlrev_b64 v[9:10], 2, v[0:1]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fmas_f32 v12, v13, v12, v14
	v_add_co_u32 v0, vcc_lo, s0, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v10, vcc_lo
	v_div_fixup_f32 v2, v12, v2, v11
	v_add_co_u32 v11, vcc_lo, s4, v3
	v_add_co_ci_u32_e32 v12, vcc_lo, s5, v4, vcc_lo
	global_store_b32 v[0:1], v2, off
	global_load_b64 v[0:1], v[11:12], off
	global_load_b32 v2, v[7:8], off offset:4
	s_waitcnt vmcnt(1)
	v_mul_f32_e64 v13, v1, -v0
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f32 v0, null, v2, v2, v13
	v_div_scale_f32 v15, vcc_lo, v13, v2, v13
	v_rcp_f32_e32 v1, v0
	s_waitcnt_depctr 0xfff
	v_fma_f32 v14, -v0, v1, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v1, v14, v1
	v_mul_f32_e32 v14, v15, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v16, -v0, v14, v15
	v_fmac_f32_e32 v14, v16, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v0, -v0, v14, v15
	v_div_fmas_f32 v14, v0, v1, v14
	v_add_co_u32 v0, vcc_lo, s4, v9
	v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_3)
	v_div_fixup_f32 v2, v14, v2, v13
	global_store_b32 v[0:1], v2, off
	global_load_b96 v[0:2], v[7:8], off offset:-4
	global_load_b64 v[13:14], v[5:6], off
	global_load_b64 v[15:16], v[11:12], off offset:-4
	s_waitcnt vmcnt(1)
	v_div_scale_f32 v17, null, v0, v0, v13
	s_waitcnt vmcnt(0)
	v_div_scale_f32 v18, null, v2, v2, v16
	v_div_scale_f32 v23, vcc_lo, v13, v0, v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rcp_f32_e32 v19, v17
	v_rcp_f32_e32 v20, v18
	s_waitcnt_depctr 0xfff
	v_fma_f32 v21, -v17, v19, 1.0
	v_fma_f32 v22, -v18, v20, 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v19, v21, v19
	v_div_scale_f32 v21, s0, v16, v2, v16
	v_fmac_f32_e32 v20, v22, v20
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v22, v23, v19
	v_mul_f32_e32 v24, v21, v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v25, -v17, v22, v23
	v_fma_f32 v26, -v18, v24, v21
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v22, v25, v19
	v_fmac_f32_e32 v24, v26, v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v17, -v17, v22, v23
	v_fma_f32 v18, -v18, v24, v21
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_fmas_f32 v17, v17, v19, v22
	s_mov_b32 vcc_lo, s0
	v_div_fmas_f32 v18, v18, v20, v24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fixup_f32 v0, v17, v0, v13
	v_div_fixup_f32 v2, v18, v2, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_fma_f32 v13, -v0, v15, v1
	v_add_co_u32 v0, vcc_lo, s2, v9
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v10, vcc_lo
	v_fma_f32 v2, -v14, v2, v13
	global_store_b32 v[0:1], v2, off
	global_load_b32 v5, v[5:6], off
	s_clause 0x1
	global_load_b32 v6, v[7:8], off offset:-4
	global_load_b32 v7, v[7:8], off offset:4
	global_load_b32 v8, v[11:12], off
	v_add_co_u32 v0, vcc_lo, s6, v3
	v_add_co_ci_u32_e32 v1, vcc_lo, s7, v4, vcc_lo
	global_load_b96 v[0:2], v[0:1], off offset:-4
	s_waitcnt vmcnt(3)
	v_div_scale_f32 v3, null, v6, v6, v5
	s_waitcnt vmcnt(1)
	v_div_scale_f32 v4, null, v7, v7, v8
	v_div_scale_f32 v15, vcc_lo, v5, v6, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rcp_f32_e32 v11, v3
	v_rcp_f32_e32 v12, v4
	s_waitcnt_depctr 0xfff
	v_fma_f32 v13, -v3, v11, 1.0
	v_fma_f32 v14, -v4, v12, 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v11, v13, v11
	v_div_scale_f32 v13, s0, v8, v7, v8
	v_fmac_f32_e32 v12, v14, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v14, v15, v11
	v_mul_f32_e32 v16, v13, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v17, -v3, v14, v15
	v_fma_f32 v18, -v4, v16, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v14, v17, v11
	v_fmac_f32_e32 v16, v18, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v3, -v3, v14, v15
	v_fma_f32 v4, -v4, v16, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_fmas_f32 v3, v3, v11, v14
	s_mov_b32 vcc_lo, s0
	v_div_fmas_f32 v4, v4, v12, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fixup_f32 v3, v3, v6, v5
	v_div_fixup_f32 v4, v4, v7, v8
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v0, -v0, v3, v1
	v_fma_f32 v2, -v2, v4, v0
	v_add_co_u32 v0, vcc_lo, s6, v9
	v_add_co_ci_u32_e32 v1, vcc_lo, s7, v10, vcc_lo
	global_store_b32 v[0:1], v2, off
.LBB2_5:
	s_or_b32 exec_lo, exec_lo, s8
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z21CalculatePArrayKerneliiiPfS_S_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 48
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 42
		.amdhsa_next_free_sgpr 68
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_Z21CalculatePArrayKerneliiiPfS_S_S_, .Lfunc_end2-_Z21CalculatePArrayKerneliiiPfS_S_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 5720
; NumSgprs: 70
; NumVgprs: 42
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 8
; VGPRBlocks: 5
; NumSGPRsForWavesPerEU: 70
; NumVGPRsForWavesPerEU: 42
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z14BackwardKerneliiiPfS_S_S_S_f ; -- Begin function _Z14BackwardKerneliiiPfS_S_S_S_f
	.globl	_Z14BackwardKerneliiiPfS_S_S_S_f
	.p2align	8
	.type	_Z14BackwardKerneliiiPfS_S_S_S_f,@function
_Z14BackwardKerneliiiPfS_S_S_S_f:       ; @_Z14BackwardKerneliiiPfS_S_S_S_f
; %bb.0:
	s_clause 0x1
	s_load_b32 s33, s[0:1], 0x0
	s_load_b32 s62, s[0:1], 0x8
	s_mov_b32 s4, 0
	s_mov_b32 s6, 0x55555555
	s_mov_b32 s7, 0x3fe55555
	s_mov_b32 s8, 0x968915a9
	s_mov_b32 s10, 0x4222de17
	s_mov_b32 s9, 0x3fba6564
	s_mov_b32 s11, 0x3fbdee67
	s_mov_b32 s12, 0x3abe935a
	s_mov_b32 s13, 0x3fbe25e4
	s_mov_b32 s14, 0x47e6c9c2
	s_mov_b32 s15, 0x3fc110ef
	s_mov_b32 s16, 0xcfa74449
	s_mov_b32 s17, 0x3fc3b13b
	s_mov_b32 s18, 0x71bf3c30
	s_mov_b32 s19, 0x3fc745d1
	s_mov_b32 s20, 0x1c7792ce
	s_mov_b32 s21, 0x3fcc71c7
	s_mov_b32 s22, 0x924920da
	s_waitcnt lgkmcnt(0)
	s_sub_i32 s2, 7, s33
	s_cmp_eq_u32 s33, 7
	s_mov_b32 s23, 0x3fd24924
	s_cselect_b32 s5, 0x3ff00000, 2.0
	s_mov_b32 s24, 0x9999999c
	v_frexp_mant_f64_e32 v[1:2], s[4:5]
	s_mov_b32 s25, 0x3fd99999
	s_mov_b32 s27, 0xbfe55555
	s_mov_b32 s26, s6
	s_mov_b32 s28, 0xd5df274d
	s_mov_b32 s29, 0x3c8543b0
	s_mov_b32 s30, 0xfefa39ef
	s_mov_b32 s31, 0x3fe62e42
	s_mov_b32 s36, 0x3b39803f
	s_mov_b32 s37, 0x3c7abc9e
	s_mov_b32 s34, 0x652b82fe
	s_mov_b32 s35, 0x3ff71547
	s_mov_b32 s39, 0xbfe62e42
	s_mov_b32 s38, s30
	s_mov_b32 s41, 0xbc7abc9e
	s_mov_b32 s40, s36
	s_mov_b32 s42, 0xfca7ab0c
	s_mov_b32 s44, 0x6a5dcb37
	s_mov_b32 s43, 0x3e928af3
	s_mov_b32 s45, 0x3e5ade15
	s_mov_b32 s46, 0x623fde64
	s_mov_b32 s47, 0x3ec71dee
	s_mov_b32 s48, 0x7c89e6b0
	s_mov_b32 s49, 0x3efa0199
	s_mov_b32 s50, 0x14761f6e
	s_mov_b32 s51, 0x3f2a01a0
	s_mov_b32 s52, 0x1852b7b0
	s_mov_b32 s53, 0x3f56c16c
	s_mov_b32 s54, 0x11122322
	s_mov_b32 s55, 0x3f811111
	s_mov_b32 s56, 0x555502a1
	s_mov_b32 s57, 0x3fa55555
	s_mov_b32 s58, 0x55555511
	s_mov_b32 s59, 0x3fc55555
	s_mov_b32 s60, 11
	s_mov_b32 s61, 0x3fe00000
	s_add_i32 s3, s33, -1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_gt_f64_e32 vcc_lo, s[6:7], v[1:2]
	v_cndmask_b32_e64 v3, 0, 1, vcc_lo
	v_ldexp_f64 v[1:2], v[1:2], v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[3:4], v[1:2], 1.0
	v_add_f64 v[9:10], v[1:2], -1.0
	v_rcp_f64_e32 v[5:6], v[3:4]
	v_add_f64 v[11:12], v[3:4], -1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_f64 v[1:2], v[1:2], -v[11:12]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[7:8], -v[3:4], v[5:6], 1.0
	v_fma_f64 v[5:6], v[7:8], v[5:6], v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[7:8], -v[3:4], v[5:6], 1.0
	v_fma_f64 v[5:6], v[7:8], v[5:6], v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[7:8], v[9:10], v[5:6]
	v_mul_f64 v[13:14], v[3:4], v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[3:4], v[7:8], v[3:4], -v[13:14]
	v_fma_f64 v[1:2], v[7:8], v[1:2], v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[3:4], v[13:14], v[1:2]
	v_add_f64 v[11:12], v[9:10], -v[3:4]
	v_add_f64 v[13:14], v[3:4], -v[13:14]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[9:10], v[9:10], -v[11:12]
	v_add_f64 v[1:2], v[13:14], -v[1:2]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[3:4], v[9:10], -v[3:4]
	v_add_f64 v[1:2], v[1:2], v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[1:2], v[11:12], v[1:2]
	v_mul_f64 v[1:2], v[5:6], v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[3:4], v[7:8], v[1:2]
	v_add_f64 v[5:6], v[3:4], -v[7:8]
	v_mul_f64 v[7:8], v[3:4], v[3:4]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[1:2], v[1:2], -v[5:6]
	v_fma_f64 v[5:6], v[3:4], v[3:4], -v[7:8]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[9:10], v[1:2], v[1:2]
	v_fma_f64 v[5:6], v[3:4], v[9:10], v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[9:10], v[7:8], v[5:6]
	v_fma_f64 v[11:12], v[9:10], s[10:11], s[8:9]
	v_add_f64 v[7:8], v[9:10], -v[7:8]
	v_mul_f64 v[17:18], v[3:4], v[9:10]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[11:12], v[9:10], v[11:12], s[12:13]
	v_add_f64 v[5:6], v[5:6], -v[7:8]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[11:12], v[9:10], v[11:12], s[14:15]
	v_fma_f64 v[11:12], v[9:10], v[11:12], s[16:17]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[11:12], v[9:10], v[11:12], s[18:19]
	v_fma_f64 v[11:12], v[9:10], v[11:12], s[20:21]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[11:12], v[9:10], v[11:12], s[22:23]
	v_fma_f64 v[11:12], v[9:10], v[11:12], s[24:25]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[13:14], v[9:10], v[11:12]
	v_fma_f64 v[7:8], v[9:10], v[11:12], -v[13:14]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[7:8], v[5:6], v[11:12], v[7:8]
	v_add_f64 v[11:12], v[13:14], v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[15:16], v[11:12], s[6:7]
	v_add_f64 v[13:14], v[11:12], -v[13:14]
	v_add_f64 v[19:20], v[15:16], s[26:27]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[7:8], v[7:8], -v[13:14]
	v_fma_f64 v[13:14], v[9:10], v[3:4], -v[17:18]
	v_add_f64 v[11:12], v[11:12], -v[19:20]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[7:8], v[7:8], s[28:29]
	v_fma_f64 v[9:10], v[9:10], v[1:2], v[13:14]
	v_ldexp_f64 v[1:2], v[1:2], 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[7:8], v[7:8], v[11:12]
	v_fma_f64 v[5:6], v[5:6], v[3:4], v[9:10]
	v_ldexp_f64 v[3:4], v[3:4], 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[9:10], v[15:16], v[7:8]
	v_add_f64 v[11:12], v[17:18], v[5:6]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[13:14], v[15:16], -v[9:10]
	v_mul_f64 v[15:16], v[11:12], v[9:10]
	v_add_f64 v[17:18], v[11:12], -v[17:18]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[7:8], v[7:8], v[13:14]
	v_fma_f64 v[13:14], v[11:12], v[9:10], -v[15:16]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[5:6], v[5:6], -v[17:18]
	v_fma_f64 v[7:8], v[11:12], v[7:8], v[13:14]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f64 v[5:6], v[5:6], v[9:10], v[7:8]
	v_frexp_exp_i32_f64_e32 v9, s[4:5]
	v_add_f64 v[7:8], v[15:16], v[5:6]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_subrev_co_ci_u32_e32 v9, vcc_lo, 0, v9, vcc_lo
	v_cvt_f64_i32_e32 v[9:10], v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[11:12], v[3:4], v[7:8]
	v_add_f64 v[13:14], v[7:8], -v[15:16]
	v_mul_f64 v[15:16], v[9:10], s[30:31]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[3:4], v[11:12], -v[3:4]
	v_add_f64 v[5:6], v[5:6], -v[13:14]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[13:14], v[9:10], s[30:31], -v[15:16]
	v_add_f64 v[3:4], v[7:8], -v[3:4]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[1:2], v[1:2], v[5:6]
	v_fma_f64 v[5:6], v[9:10], s[36:37], v[13:14]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[1:2], v[1:2], v[3:4]
	v_add_f64 v[3:4], v[15:16], v[5:6]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[7:8], v[11:12], v[1:2]
	v_add_f64 v[15:16], v[3:4], -v[15:16]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[9:10], v[3:4], v[7:8]
	v_add_f64 v[11:12], v[7:8], -v[11:12]
	v_add_f64 v[5:6], v[5:6], -v[15:16]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[13:14], v[9:10], -v[3:4]
	v_add_f64 v[1:2], v[1:2], -v[11:12]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[17:18], v[9:10], -v[13:14]
	v_add_f64 v[7:8], v[7:8], -v[13:14]
	v_add_f64 v[11:12], v[5:6], v[1:2]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[3:4], v[3:4], -v[17:18]
	v_add_f64 v[3:4], v[7:8], v[3:4]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[7:8], v[11:12], -v[5:6]
	v_add_f64 v[3:4], v[11:12], v[3:4]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[11:12], v[11:12], -v[7:8]
	v_add_f64 v[1:2], v[1:2], -v[7:8]
	v_add_f64 v[13:14], v[9:10], v[3:4]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[5:6], v[5:6], -v[11:12]
	v_add_f64 v[7:8], v[13:14], -v[9:10]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[1:2], v[1:2], v[5:6]
	v_cvt_f64_i32_e32 v[5:6], s2
	v_add_f64 v[3:4], v[3:4], -v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[1:2], v[1:2], v[3:4]
	v_add_f64 v[3:4], v[13:14], v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[7:8], v[3:4], -v[13:14]
	v_mul_f64 v[9:10], v[3:4], v[5:6]
	v_add_f64 v[1:2], v[1:2], -v[7:8]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f64 v[3:4], v[5:6], v[3:4], -v[9:10]
	v_cmp_class_f64_e64 vcc_lo, v[9:10], 0x204
	v_fma_f64 v[1:2], v[5:6], v[1:2], v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[3:4], v[9:10], v[1:2]
	v_dual_cndmask_b32 v6, v4, v10 :: v_dual_cndmask_b32 v5, v3, v9
	v_add_f64 v[3:4], v[3:4], -v[9:10]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_mul_f64 v[7:8], v[5:6], s[34:35]
	v_cmp_nlt_f64_e32 vcc_lo, 0x40900000, v[5:6]
	v_cmp_ngt_f64_e64 s2, 0xc090cc00, v[5:6]
	v_add_f64 v[1:2], v[1:2], -v[3:4]
	v_bfe_u32 v3, v0, 10, 10
	v_rndne_f64_e32 v[7:8], v[7:8]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v3, v3, s62
	v_fma_f64 v[11:12], v[7:8], s[38:39], v[5:6]
	v_cvt_i32_f64_e32 v15, v[7:8]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[11:12], v[7:8], s[40:41], v[11:12]
	v_fma_f64 v[13:14], v[11:12], s[44:45], s[42:43]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[13:14], v[11:12], v[13:14], s[46:47]
	v_fma_f64 v[13:14], v[11:12], v[13:14], s[48:49]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[13:14], v[11:12], v[13:14], s[50:51]
	v_fma_f64 v[13:14], v[11:12], v[13:14], s[52:53]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[13:14], v[11:12], v[13:14], s[54:55]
	v_fma_f64 v[13:14], v[11:12], v[13:14], s[56:57]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[13:14], v[11:12], v[13:14], s[58:59]
	v_fma_f64 v[13:14], v[11:12], v[13:14], s[60:61]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[13:14], v[11:12], v[13:14], 1.0
	v_fma_f64 v[7:8], v[11:12], v[13:14], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ldexp_f64 v[7:8], v[7:8], v15
	v_cndmask_b32_e32 v8, 0x7ff00000, v8, vcc_lo
	s_and_b32 vcc_lo, s2, vcc_lo
	s_cmp_eq_u32 s3, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v7, 0, v7 :: v_dual_and_b32 v0, 0x3ff, v0
	s_cselect_b32 s5, 0x3ff00000, 2.0
	v_cndmask_b32_e64 v8, 0, v8, s2
	v_frexp_mant_f64_e32 v[11:12], s[4:5]
	v_cmp_class_f64_e64 vcc_lo, v[7:8], 0x204
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_gt_f64_e64 s2, s[6:7], v[11:12]
	v_cndmask_b32_e64 v13, 0, 1, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ldexp_f64 v[11:12], v[11:12], v13
	v_add_f64 v[13:14], v[11:12], 1.0
	v_add_f64 v[19:20], v[11:12], -1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[15:16], v[13:14]
	v_add_f64 v[21:22], v[13:14], -1.0
	v_add_f64 v[11:12], v[11:12], -v[21:22]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[17:18], -v[13:14], v[15:16], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[15:16], v[17:18], v[15:16], v[15:16]
	v_fma_f64 v[17:18], -v[13:14], v[15:16], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[15:16], v[17:18], v[15:16], v[15:16]
	v_mul_f64 v[17:18], v[19:20], v[15:16]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[23:24], v[13:14], v[17:18]
	v_fma_f64 v[13:14], v[17:18], v[13:14], -v[23:24]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[11:12], v[17:18], v[11:12], v[13:14]
	v_add_f64 v[13:14], v[23:24], v[11:12]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[21:22], v[19:20], -v[13:14]
	v_add_f64 v[23:24], v[13:14], -v[23:24]
	v_add_f64 v[19:20], v[19:20], -v[21:22]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[11:12], v[23:24], -v[11:12]
	v_add_f64 v[13:14], v[19:20], -v[13:14]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[11:12], v[11:12], v[13:14]
	v_add_f64 v[11:12], v[21:22], v[11:12]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[11:12], v[15:16], v[11:12]
	v_add_f64 v[13:14], v[17:18], v[11:12]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[15:16], v[13:14], -v[17:18]
	v_mul_f64 v[17:18], v[13:14], v[13:14]
	v_add_f64 v[11:12], v[11:12], -v[15:16]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[15:16], v[13:14], v[13:14], -v[17:18]
	v_add_f64 v[19:20], v[11:12], v[11:12]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[15:16], v[13:14], v[19:20], v[15:16]
	v_add_f64 v[19:20], v[17:18], v[15:16]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_fma_f64 v[21:22], v[19:20], s[10:11], s[8:9]
	v_add_f64 v[17:18], v[19:20], -v[17:18]
	v_mul_f64 v[27:28], v[13:14], v[19:20]
	v_fma_f64 v[21:22], v[19:20], v[21:22], s[12:13]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[15:16], v[15:16], -v[17:18]
	v_fma_f64 v[21:22], v[19:20], v[21:22], s[14:15]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[21:22], v[19:20], v[21:22], s[16:17]
	v_fma_f64 v[21:22], v[19:20], v[21:22], s[18:19]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[21:22], v[19:20], v[21:22], s[20:21]
	v_fma_f64 v[21:22], v[19:20], v[21:22], s[22:23]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[21:22], v[19:20], v[21:22], s[24:25]
	v_mul_f64 v[23:24], v[19:20], v[21:22]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[17:18], v[19:20], v[21:22], -v[23:24]
	v_fma_f64 v[17:18], v[15:16], v[21:22], v[17:18]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[21:22], v[23:24], v[17:18]
	v_add_f64 v[25:26], v[21:22], s[6:7]
	v_add_f64 v[23:24], v[21:22], -v[23:24]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[29:30], v[25:26], s[26:27]
	v_add_f64 v[17:18], v[17:18], -v[23:24]
	v_fma_f64 v[23:24], v[19:20], v[13:14], -v[27:28]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[21:22], v[21:22], -v[29:30]
	v_add_f64 v[17:18], v[17:18], s[28:29]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fma_f64 v[19:20], v[19:20], v[11:12], v[23:24]
	v_ldexp_f64 v[11:12], v[11:12], 1
	v_add_f64 v[17:18], v[17:18], v[21:22]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fma_f64 v[15:16], v[15:16], v[13:14], v[19:20]
	v_ldexp_f64 v[13:14], v[13:14], 1
	v_add_f64 v[19:20], v[25:26], v[17:18]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[21:22], v[27:28], v[15:16]
	v_add_f64 v[23:24], v[25:26], -v[19:20]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_f64 v[25:26], v[21:22], v[19:20]
	v_add_f64 v[27:28], v[21:22], -v[27:28]
	v_add_f64 v[17:18], v[17:18], v[23:24]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[23:24], v[21:22], v[19:20], -v[25:26]
	v_add_f64 v[15:16], v[15:16], -v[27:28]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[17:18], v[21:22], v[17:18], v[23:24]
	v_fma_f64 v[15:16], v[15:16], v[19:20], v[17:18]
	v_frexp_exp_i32_f64_e32 v19, s[4:5]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[17:18], v[25:26], v[15:16]
	v_subrev_co_ci_u32_e64 v19, s2, 0, v19, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cvt_f64_i32_e32 v[19:20], v19
	v_add_f64 v[21:22], v[13:14], v[17:18]
	v_add_f64 v[23:24], v[17:18], -v[25:26]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f64 v[25:26], v[19:20], s[30:31]
	v_add_f64 v[13:14], v[21:22], -v[13:14]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[15:16], v[15:16], -v[23:24]
	v_fma_f64 v[23:24], v[19:20], s[30:31], -v[25:26]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[13:14], v[17:18], -v[13:14]
	v_add_f64 v[11:12], v[11:12], v[15:16]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[15:16], v[19:20], s[36:37], v[23:24]
	v_add_f64 v[11:12], v[11:12], v[13:14]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[13:14], v[25:26], v[15:16]
	v_add_f64 v[17:18], v[21:22], v[11:12]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[25:26], v[13:14], -v[25:26]
	v_add_f64 v[19:20], v[13:14], v[17:18]
	v_add_f64 v[21:22], v[17:18], -v[21:22]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[15:16], v[15:16], -v[25:26]
	v_add_f64 v[23:24], v[19:20], -v[13:14]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[11:12], v[11:12], -v[21:22]
	v_add_f64 v[27:28], v[19:20], -v[23:24]
	v_add_f64 v[17:18], v[17:18], -v[23:24]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[21:22], v[15:16], v[11:12]
	v_add_f64 v[13:14], v[13:14], -v[27:28]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[13:14], v[17:18], v[13:14]
	v_add_f64 v[17:18], v[21:22], -v[15:16]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[13:14], v[21:22], v[13:14]
	v_add_f64 v[21:22], v[21:22], -v[17:18]
	v_add_f64 v[11:12], v[11:12], -v[17:18]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[23:24], v[19:20], v[13:14]
	v_add_f64 v[15:16], v[15:16], -v[21:22]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[17:18], v[23:24], -v[19:20]
	v_add_f64 v[11:12], v[11:12], v[15:16]
	v_cvt_f64_i32_e32 v[15:16], s3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[13:14], v[13:14], -v[17:18]
	v_add_f64 v[11:12], v[11:12], v[13:14]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[13:14], v[23:24], v[11:12]
	v_add_f64 v[17:18], v[13:14], -v[23:24]
	v_mul_f64 v[19:20], v[13:14], v[15:16]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[11:12], v[11:12], -v[17:18]
	v_fma_f64 v[13:14], v[15:16], v[13:14], -v[19:20]
	v_cmp_class_f64_e64 s2, v[19:20], 0x204
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[11:12], v[15:16], v[11:12], v[13:14]
	v_add_f64 v[13:14], v[19:20], v[11:12]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v16, v14, v20, s2
	v_cndmask_b32_e64 v15, v13, v19, s2
	v_add_f64 v[13:14], v[13:14], -v[19:20]
	s_delay_alu instid0(VALU_DEP_2)
	v_mul_f64 v[17:18], v[15:16], s[34:35]
	v_cmp_nlt_f64_e64 s3, 0x40900000, v[15:16]
	v_cmp_neq_f64_e64 s2, 0x7ff00000, |v[15:16]|
	v_cmp_ngt_f64_e64 s4, 0xc090cc00, v[15:16]
	v_add_f64 v[11:12], v[11:12], -v[13:14]
	v_rndne_f64_e32 v[17:18], v[17:18]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v12, 0, v12, s2
	v_cndmask_b32_e64 v11, 0, v11, s2
	s_and_b32 s2, s4, s3
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f64 v[21:22], v[17:18], s[38:39], v[15:16]
	v_cvt_i32_f64_e32 v25, v[17:18]
	v_fma_f64 v[21:22], v[17:18], s[40:41], v[21:22]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[23:24], v[21:22], s[44:45], s[42:43]
	v_fma_f64 v[23:24], v[21:22], v[23:24], s[46:47]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[23:24], v[21:22], v[23:24], s[48:49]
	v_fma_f64 v[23:24], v[21:22], v[23:24], s[50:51]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[23:24], v[21:22], v[23:24], s[52:53]
	v_fma_f64 v[23:24], v[21:22], v[23:24], s[54:55]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[23:24], v[21:22], v[23:24], s[56:57]
	v_fma_f64 v[23:24], v[21:22], v[23:24], s[58:59]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[23:24], v[21:22], v[23:24], s[60:61]
	v_fma_f64 v[23:24], v[21:22], v[23:24], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[17:18], v[21:22], v[23:24], 1.0
	v_ldexp_f64 v[17:18], v[17:18], v25
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v13, 0x7ff00000, v18, s3
	v_cndmask_b32_e64 v14, 0, v13, s4
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v13, 0, v17, s2
	s_clause 0x1
	s_load_b256 s[4:11], s[0:1], 0x10
	s_load_b64 s[0:1], s[0:1], 0x30
	v_fma_f64 v[11:12], v[13:14], v[11:12], v[13:14]
	v_cmp_class_f64_e64 s2, v[13:14], 0x204
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v10, v12, v14, s2
	v_cndmask_b32_e64 v9, v11, v13, s2
	v_cmp_neq_f64_e64 s2, 0x7ff00000, |v[5:6]|
	v_add_lshl_u32 v13, v3, v0, 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_i32_f64_e64 v5, |v[9:10]|
	v_or_b32_e32 v0, 1, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_cvt_f64_i32_e32 v[3:4], v0
	v_cndmask_b32_e64 v2, 0, v2, s2
	v_cndmask_b32_e64 v1, 0, v1, s2
	v_cvt_f64_i32_e32 v[5:6], v5
	v_fma_f64 v[0:1], v[7:8], v[1:2], v[7:8]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fma_f64 v[11:12], |v[9:10]|, v[3:4], -v[5:6]
	v_fma_f64 v[5:6], |v[9:10]|, v[3:4], v[5:6]
	v_dual_cndmask_b32 v1, v1, v8 :: v_dual_cndmask_b32 v0, v0, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cvt_i32_f64_e64 v1, |v[0:1]|
	v_cvt_i32_f64_e32 v0, v[11:12]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cvt_i32_f64_e32 v5, v[5:6]
	v_add_nc_u32_e32 v1, s33, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v1, v13, v1
	v_add_nc_u32_e32 v1, 0x41, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v2, 31, v1
	v_lshlrev_b64 v[7:8], 2, v[1:2]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v11, vcc_lo, s10, v7
	v_add_co_ci_u32_e32 v12, vcc_lo, s11, v8, vcc_lo
	v_ashrrev_i32_e32 v1, 31, v0
	v_add_co_u32 v13, vcc_lo, s4, v7
	v_ashrrev_i32_e32 v6, 31, v5
	v_add_co_ci_u32_e32 v14, vcc_lo, s5, v8, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	v_add_co_u32 v15, vcc_lo, s8, v7
	v_add_co_ci_u32_e32 v16, vcc_lo, s9, v8, vcc_lo
	v_lshlrev_b64 v[5:6], 2, v[5:6]
	v_add_co_u32 v0, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	global_load_b32 v2, v[11:12], off
	global_load_b32 v11, v[13:14], off
	v_add_co_u32 v5, vcc_lo, s0, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, s1, v6, vcc_lo
	global_load_b32 v12, v[0:1], off
	v_add_co_u32 v0, vcc_lo, s6, v7
	v_add_co_ci_u32_e32 v1, vcc_lo, s7, v8, vcc_lo
	global_load_b32 v7, v[15:16], off
	global_load_b32 v5, v[5:6], off
	global_load_b32 v6, v[0:1], off
	v_mul_f64 v[0:1], |v[9:10]|, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_cvt_i32_f64_e32 v0, v[0:1]
	s_waitcnt vmcnt(3)
	v_fma_f32 v2, -v11, v12, v2
	s_waitcnt vmcnt(1)
	v_fma_f32 v2, -v7, v5, v2
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f32 v3, null, v6, v6, v2
	v_div_scale_f32 v5, vcc_lo, v2, v6, v2
	v_rcp_f32_e32 v4, v3
	s_waitcnt_depctr 0xfff
	v_fma_f32 v1, -v3, v4, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v4, v1, v4
	v_mul_f32_e32 v7, v5, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v1, -v3, v7, v5
	v_fmac_f32_e32 v7, v1, v4
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v3, -v3, v7, v5
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fmas_f32 v3, v3, v4, v7
	v_add_co_u32 v0, vcc_lo, s0, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	v_div_fixup_f32 v2, v3, v6, v2
	global_store_b32 v[0:1], v2, off
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z14BackwardKerneliiiPfS_S_S_S_f
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 60
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 31
		.amdhsa_next_free_sgpr 63
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end3:
	.size	_Z14BackwardKerneliiiPfS_S_S_S_f, .Lfunc_end3-_Z14BackwardKerneliiiPfS_S_S_S_f
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 3836
; NumSgprs: 65
; NumVgprs: 31
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 8
; VGPRBlocks: 3
; NumSGPRsForWavesPerEU: 65
; NumVGPRsForWavesPerEU: 31
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	.str,@object                    ; @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.str:
	.asciz	"temp1: %d \n"
	.size	.str, 12

	.type	.str.1,@object                  ; @.str.1
.str.1:
	.asciz	"row %d, index %d, %lf"
	.size	.str.1, 22

	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         48
        .size:           8
        .value_kind:     global_buffer
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         60
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         64
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         68
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         70
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         72
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         74
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         76
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         78
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         112
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         120
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         136
        .size:           8
        .value_kind:     hidden_hostcall_buffer
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 312
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z13CalculateTheDiPfS_S_S_S_S_
    .private_segment_fixed_size: 0
    .sgpr_count:     78
    .sgpr_spill_count: 0
    .symbol:         _Z13CalculateTheDiPfS_S_S_S_S_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     58
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     by_value
      - .offset:         4
        .size:           4
        .value_kind:     by_value
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 48
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z21CalculatePArrayKerneliiiPfS_S_S_
    .private_segment_fixed_size: 0
    .sgpr_count:     70
    .sgpr_spill_count: 0
    .symbol:         _Z21CalculatePArrayKerneliiiPfS_S_S_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     42
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     by_value
      - .offset:         4
        .size:           4
        .value_kind:     by_value
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         48
        .size:           8
        .value_kind:     global_buffer
      - .offset:         56
        .size:           4
        .value_kind:     by_value
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 60
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z14BackwardKerneliiiPfS_S_S_S_f
    .private_segment_fixed_size: 0
    .sgpr_count:     65
    .sgpr_spill_count: 0
    .symbol:         _Z14BackwardKerneliiiPfS_S_S_S_f.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     31
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
