#include <iostream>

constexpr int LEN_INITAL = 8;
constexpr int STEPS = 6;

constexpr int LEN_W = 1 + 2 * STEPS;
constexpr int LEN_Z = LEN_W;
constexpr int LEN_Y = LEN_INITAL + 2 * STEPS;
constexpr int LEN_X = LEN_INITAL + 2 * STEPS;
constexpr int LEN_TOTAL = LEN_W * LEN_Z * LEN_Y * LEN_X;

constexpr int SIZE_W = LEN_Z * LEN_Y * LEN_X;
constexpr int SIZE_Z = LEN_Y * LEN_X;
constexpr int SIZE_Y = LEN_X;

constexpr int NUM_THREADS = 512;
constexpr int NUM_BLOCKS = LEN_TOTAL / NUM_THREADS;

inline int coord_to_idx(const int w, const int z, const int y, const int x) {
  return
    w * SIZE_W +
    z * SIZE_Z +
    y * SIZE_Y +
    x;
}

inline void print_slice(const int* grid, const int w, const int z) {
  for (int row = 0; row < LEN_Y; ++row) {
    for (int col = 0; col < LEN_X; ++col) {
      std::cout << grid[coord_to_idx(w, z, row, col)] << " ";
    }
    std::cout << "\n";
  }
}

__device__
int coord_to_idx_dev(const int w, const int z, const int y, const int x) {
  return w * SIZE_W + z * SIZE_Z + y * SIZE_Y + x;
}

__global__
void step(const int* grid, int* grid_next) {
  // Find out where we are.
  const int idx = blockIdx.x * blockDim.x + threadIdx.x;
  if (idx < LEN_TOTAL) {
    int left = idx;
    int w = idx / SIZE_W;
    left = idx - w * SIZE_W;
    int z = left / SIZE_Z;
    left = left - z * SIZE_Z;
    int y = left / SIZE_Y;
    int x = left - y * SIZE_Y;

    // TODO: for loop here?
    const int active = grid[idx];
    // Count active neighbors.
    int active_neighbors = 0;
    int min_nw = max(0, w - 1);
    int max_nw = min(LEN_W, w + 2);
    int min_nz = max(0, z - 1);
    int max_nz = min(LEN_Z, z + 2);
    int min_ny = max(0, y - 1);
    int max_ny = min(LEN_Y, y + 2);
    int min_nx = max(0, x - 1);
    int max_nx = min(LEN_X, x + 2);
    for (int nw = min_nw; nw < max_nw; ++nw) {
      for (int nz = min_nz; nz < max_nz; ++nz) {
        for (int ny = min_ny; ny < max_ny; ++ny) {
          for (int nx = min_nx; nx < max_nx; ++nx) {
            active_neighbors += grid[coord_to_idx_dev(nw, nz, ny, nx)];
          }
        }
      }
    }
    active_neighbors -= active;
    // Rules
    int active_next = active;
    if (active == 1 && (active_neighbors < 2 || active_neighbors > 3)) {
      active_next = 0;
    }
    else if (active == 0 && active_neighbors == 3) {
      active_next = 1;
    }
    //active_next = idx;
    grid_next[idx] = active_next;
  }
}

int main() {

  // Initialize grid.
  int* grid;
  cudaMallocManaged(&grid, LEN_TOTAL * sizeof(int));
  cudaMemset(grid, 0, LEN_TOTAL);
  int initial_grid[LEN_INITAL][LEN_INITAL] = {
    {1, 1, 0, 0, 1, 0, 1, 0},
    {1, 1, 1, 0, 1, 0, 1, 1},
    {0, 0, 1, 1, 1, 0, 0, 1},
    {0, 1, 0, 0, 0, 0, 1, 1},
    {0, 1, 0, 0, 1, 1, 1, 1},
    {1, 1, 1, 1, 1, 0, 0, 0},
    {1, 1, 1, 1, 1, 1, 1, 0},
    {1, 0, 1, 1, 0, 1, 0, 1}
  };
  for (int row = 0; row < LEN_INITAL; ++row) {
    for (int col = 0; col < LEN_INITAL; ++col) {
      grid[coord_to_idx(STEPS, STEPS, STEPS + row, STEPS + col)] = initial_grid[row][col];
    }
  }
  //print_slice(grid, STEPS, STEPS);
  int* grid_next;
  cudaMallocManaged(&grid_next, LEN_TOTAL * sizeof(int));
  for (int i = 0; i < STEPS; ++i) {
    //std::cout << "Step " << i << "\n";
    step<<<NUM_BLOCKS, NUM_THREADS>>>(grid, grid_next);
    cudaDeviceSynchronize();
    std::swap(grid, grid_next);
    //print_slice(grid, STEPS, STEPS);
  }
  // Count actives.
  int count = 0;
  for (int i = 0; i < LEN_TOTAL; ++i) {
    count += grid[i];
  }
  std::cout << "Active: " << count << "\n";
  cudaFree(grid);
  cudaFree(grid_next);
  return 0;
}

	.file	"tmpxft_0037624a_00000000-6_17.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3642:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3642:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z16coord_to_idx_deviiii
	.type	_Z16coord_to_idx_deviiii, @function
_Z16coord_to_idx_deviiii:
.LFB3637:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE3637:
	.size	_Z16coord_to_idx_deviiii, .-_Z16coord_to_idx_deviiii
	.globl	_Z26__device_stub__Z4stepPKiPiPKiPi
	.type	_Z26__device_stub__Z4stepPKiPiPKiPi, @function
_Z26__device_stub__Z4stepPKiPiPKiPi:
.LFB3664:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 8(%rsp)
	leaq	32(%rsp), %rcx
	leaq	24(%rsp), %rdx
	movq	%rsi, (%rsp)
	leaq	40(%rsp), %rdi
	leaq	52(%rsp), %rsi
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 48(%rsp)
	movq	%rax, 88(%rsp)
	movq	%rsp, %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L4
	pushq	32(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z4stepPKiPi(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 144
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	104(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L4:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L6
	call	__stack_chk_fail@PLT
.L6:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3664:
	.size	_Z26__device_stub__Z4stepPKiPiPKiPi, .-_Z26__device_stub__Z4stepPKiPiPKiPi
	.globl	_Z4stepPKiPi
	.type	_Z4stepPKiPi, @function
_Z4stepPKiPi:
.LFB3665:
	.cfi_startproc
	endbr64
	jmp	_Z26__device_stub__Z4stepPKiPiPKiPi
	.cfi_endproc
.LFE3665:
	.size	_Z4stepPKiPi, .-_Z4stepPKiPi
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC1:
	.string	"Active: "
.LC2:
	.string	"\n"
	.section	.rodata
	.align 32
.LC0:
	.long	1
	.long	1
	.long	0
	.long	0
	.long	1
	.long	0
	.long	1
	.long	0
	.long	1
	.long	1
	.long	1
	.long	0
	.long	1
	.long	0
	.long	1
	.long	1
	.long	0
	.long	0
	.long	1
	.long	1
	.long	1
	.long	0
	.long	0
	.long	1
	.long	0
	.long	1
	.long	0
	.long	0
	.long	0
	.long	0
	.long	1
	.long	1
	.long	0
	.long	1
	.long	0
	.long	0
	.long	1
	.long	1
	.long	1
	.long	1
	.long	1
	.long	1
	.long	1
	.long	1
	.long	1
	.long	0
	.long	0
	.long	0
	.long	1
	.long	1
	.long	1
	.long	1
	.long	1
	.long	1
	.long	1
	.long	0
	.long	1
	.long	0
	.long	1
	.long	1
	.long	0
	.long	1
	.long	0
	.long	1
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB3638:
	.cfi_startproc
	endbr64
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	movl	$1, %edx
	movl	$270400, %esi
	pushq	%rbx
	.cfi_def_cfa_offset 24
	.cfi_offset 3, -24
	subq	$312, %rsp
	.cfi_def_cfa_offset 336
	movq	%fs:40, %rax
	movq	%rax, 296(%rsp)
	xorl	%eax, %eax
	movq	%rsp, %rdi
	call	cudaMallocManaged@PLT
	movq	(%rsp), %rdi
	movl	$67600, %edx
	xorl	%esi, %esi
	call	cudaMemset@PLT
	movq	(%rsp), %rax
	leaq	40(%rsp), %rdi
	leaq	.LC0(%rip), %rsi
	movl	$64, %ecx
	leaq	40(%rsp), %rdx
	rep movsl
	addq	$134904, %rax
	leaq	296(%rsp), %rcx
.L11:
	movups	(%rdx), %xmm0
	addq	$32, %rdx
	addq	$80, %rax
	movups	%xmm0, -80(%rax)
	movups	-16(%rdx), %xmm1
	movups	%xmm1, -64(%rax)
	cmpq	%rcx, %rdx
	jne	.L11
	leaq	8(%rsp), %rdi
	movl	$1, %edx
	movl	$270400, %esi
	movl	$8388609, %ebp
	call	cudaMallocManaged@PLT
	movl	$6, %ebx
	salq	$9, %rbp
.L13:
	movl	$1073741857, %edi
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	%rbp, %rdx
	salq	$2, %rdi
	movl	$1, %ecx
	movl	$1, %esi
	movq	%rbp, 28(%rsp)
	movl	$1, 36(%rsp)
	movq	%rdi, 16(%rsp)
	movl	$1, 24(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L12
	movq	8(%rsp), %rsi
	movq	(%rsp), %rdi
	call	_Z26__device_stub__Z4stepPKiPiPKiPi
.L12:
	call	cudaDeviceSynchronize@PLT
	movq	(%rsp), %rax
	movq	8(%rsp), %rdx
	movq	%rax, 8(%rsp)
	movq	%rdx, (%rsp)
	decl	%ebx
	jne	.L13
	xorl	%eax, %eax
	xorl	%ebx, %ebx
.L14:
	addl	(%rdx,%rax,4), %ebx
	incq	%rax
	cmpq	$67600, %rax
	jne	.L14
	leaq	.LC1(%rip), %rsi
	leaq	_ZSt4cout(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	%ebx, %esi
	movq	%rax, %rdi
	call	_ZNSolsEi@PLT
	leaq	.LC2(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	(%rsp), %rdi
	call	cudaFree@PLT
	movq	8(%rsp), %rdi
	call	cudaFree@PLT
	movq	296(%rsp), %rax
	subq	%fs:40, %rax
	je	.L15
	call	__stack_chk_fail@PLT
.L15:
	addq	$312, %rsp
	.cfi_def_cfa_offset 24
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3638:
	.size	main, .-main
	.section	.rodata.str1.1
.LC3:
	.string	"_Z4stepPKiPi"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3667:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC3(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z4stepPKiPi(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3667:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include <iostream>

constexpr int LEN_INITAL = 8;
constexpr int STEPS = 6;

constexpr int LEN_W = 1 + 2 * STEPS;
constexpr int LEN_Z = LEN_W;
constexpr int LEN_Y = LEN_INITAL + 2 * STEPS;
constexpr int LEN_X = LEN_INITAL + 2 * STEPS;
constexpr int LEN_TOTAL = LEN_W * LEN_Z * LEN_Y * LEN_X;

constexpr int SIZE_W = LEN_Z * LEN_Y * LEN_X;
constexpr int SIZE_Z = LEN_Y * LEN_X;
constexpr int SIZE_Y = LEN_X;

constexpr int NUM_THREADS = 512;
constexpr int NUM_BLOCKS = LEN_TOTAL / NUM_THREADS;

inline int coord_to_idx(const int w, const int z, const int y, const int x) {
  return
    w * SIZE_W +
    z * SIZE_Z +
    y * SIZE_Y +
    x;
}

inline void print_slice(const int* grid, const int w, const int z) {
  for (int row = 0; row < LEN_Y; ++row) {
    for (int col = 0; col < LEN_X; ++col) {
      std::cout << grid[coord_to_idx(w, z, row, col)] << " ";
    }
    std::cout << "\n";
  }
}

__device__
int coord_to_idx_dev(const int w, const int z, const int y, const int x) {
  return w * SIZE_W + z * SIZE_Z + y * SIZE_Y + x;
}

__global__
void step(const int* grid, int* grid_next) {
  // Find out where we are.
  const int idx = blockIdx.x * blockDim.x + threadIdx.x;
  if (idx < LEN_TOTAL) {
    int left = idx;
    int w = idx / SIZE_W;
    left = idx - w * SIZE_W;
    int z = left / SIZE_Z;
    left = left - z * SIZE_Z;
    int y = left / SIZE_Y;
    int x = left - y * SIZE_Y;

    // TODO: for loop here?
    const int active = grid[idx];
    // Count active neighbors.
    int active_neighbors = 0;
    int min_nw = max(0, w - 1);
    int max_nw = min(LEN_W, w + 2);
    int min_nz = max(0, z - 1);
    int max_nz = min(LEN_Z, z + 2);
    int min_ny = max(0, y - 1);
    int max_ny = min(LEN_Y, y + 2);
    int min_nx = max(0, x - 1);
    int max_nx = min(LEN_X, x + 2);
    for (int nw = min_nw; nw < max_nw; ++nw) {
      for (int nz = min_nz; nz < max_nz; ++nz) {
        for (int ny = min_ny; ny < max_ny; ++ny) {
          for (int nx = min_nx; nx < max_nx; ++nx) {
            active_neighbors += grid[coord_to_idx_dev(nw, nz, ny, nx)];
          }
        }
      }
    }
    active_neighbors -= active;
    // Rules
    int active_next = active;
    if (active == 1 && (active_neighbors < 2 || active_neighbors > 3)) {
      active_next = 0;
    }
    else if (active == 0 && active_neighbors == 3) {
      active_next = 1;
    }
    //active_next = idx;
    grid_next[idx] = active_next;
  }
}

int main() {

  // Initialize grid.
  int* grid;
  hipMallocManaged(&grid, LEN_TOTAL * sizeof(int));
  hipMemset(grid, 0, LEN_TOTAL);
  int initial_grid[LEN_INITAL][LEN_INITAL] = {
    {1, 1, 0, 0, 1, 0, 1, 0},
    {1, 1, 1, 0, 1, 0, 1, 1},
    {0, 0, 1, 1, 1, 0, 0, 1},
    {0, 1, 0, 0, 0, 0, 1, 1},
    {0, 1, 0, 0, 1, 1, 1, 1},
    {1, 1, 1, 1, 1, 0, 0, 0},
    {1, 1, 1, 1, 1, 1, 1, 0},
    {1, 0, 1, 1, 0, 1, 0, 1}
  };
  for (int row = 0; row < LEN_INITAL; ++row) {
    for (int col = 0; col < LEN_INITAL; ++col) {
      grid[coord_to_idx(STEPS, STEPS, STEPS + row, STEPS + col)] = initial_grid[row][col];
    }
  }
  //print_slice(grid, STEPS, STEPS);
  int* grid_next;
  hipMallocManaged(&grid_next, LEN_TOTAL * sizeof(int));
  for (int i = 0; i < STEPS; ++i) {
    //std::cout << "Step " << i << "\n";
    step<<<NUM_BLOCKS, NUM_THREADS>>>(grid, grid_next);
    hipDeviceSynchronize();
    std::swap(grid, grid_next);
    //print_slice(grid, STEPS, STEPS);
  }
  // Count actives.
  int count = 0;
  for (int i = 0; i < LEN_TOTAL; ++i) {
    count += grid[i];
  }
  std::cout << "Active: " << count << "\n";
  hipFree(grid);
  hipFree(grid_next);
  return 0;
}

	.text
	.file	"17.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z19__device_stub__stepPKiPi    # -- Begin function _Z19__device_stub__stepPKiPi
	.type	_Z19__device_stub__stepPKiPi,@function
_Z19__device_stub__stepPKiPi:           # @_Z19__device_stub__stepPKiPi
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	16(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z4stepPKiPi, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z19__device_stub__stepPKiPi, .Lfunc_end0-_Z19__device_stub__stepPKiPi
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	subq	$16, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	.cfi_offset %rbp, -16
	leaq	8(%rsp), %rbx
	movl	$270400, %esi                   # imm = 0x42040
	movq	%rbx, %rdi
	movl	$1, %edx
	callq	hipMallocManaged
	movq	(%rbx), %rdi
	xorl	%r14d, %r14d
	movl	$67600, %edx                    # imm = 0x10810
	xorl	%esi, %esi
	callq	hipMemset
	movl	$134904, %eax                   # imm = 0x20EF8
	addq	(%rbx), %rax
	movl	$.L__const.main.initial_grid, %ecx
.LBB1_1:                                # %.preheader25
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB1_2 Depth 2
	xorl	%edx, %edx
.LBB1_2:                                #   Parent Loop BB1_1 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movl	(%rcx,%rdx,4), %esi
	movl	%esi, (%rax,%rdx,4)
	incq	%rdx
	cmpq	$8, %rdx
	jne	.LBB1_2
# %bb.3:                                #   in Loop: Header=BB1_1 Depth=1
	incq	%r14
	addq	$80, %rax
	addq	$32, %rcx
	cmpq	$8, %r14
	jne	.LBB1_1
# %bb.4:
	movabsq	$4294967428, %rbx               # imm = 0x100000084
	movq	%rsp, %rdi
	movl	$270400, %esi                   # imm = 0x42040
	movl	$1, %edx
	callq	hipMallocManaged
	movl	$6, %ebp
	leaq	380(%rbx), %r14
.LBB1_5:                                # =>This Inner Loop Header: Depth=1
	movq	%rbx, %rdi
	movl	$1, %esi
	movq	%r14, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_7
# %bb.6:                                #   in Loop: Header=BB1_5 Depth=1
	movq	8(%rsp), %rdi
	movq	(%rsp), %rsi
	callq	_Z19__device_stub__stepPKiPi
.LBB1_7:                                #   in Loop: Header=BB1_5 Depth=1
	callq	hipDeviceSynchronize
	movq	8(%rsp), %rcx
	movq	(%rsp), %rax
	movq	%rax, 8(%rsp)
	movq	%rcx, (%rsp)
	decl	%ebp
	jne	.LBB1_5
# %bb.8:                                # %.preheader.preheader
	xorl	%ecx, %ecx
	xorl	%ebx, %ebx
.LBB1_9:                                # %.preheader
                                        # =>This Inner Loop Header: Depth=1
	addl	(%rax,%rcx,4), %ebx
	incq	%rcx
	cmpq	$67600, %rcx                    # imm = 0x10810
	jne	.LBB1_9
# %bb.10:
	movl	$_ZSt4cout, %edi
	movl	$.L.str, %esi
	movl	$8, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	$_ZSt4cout, %edi
	movl	%ebx, %esi
	callq	_ZNSolsEi
	movl	$.L.str.1, %esi
	movl	$1, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	8(%rsp), %rdi
	callq	hipFree
	movq	(%rsp), %rdi
	callq	hipFree
	xorl	%eax, %eax
	addq	$16, %rsp
	.cfi_def_cfa_offset 32
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	main, .Lfunc_end1-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z4stepPKiPi, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z4stepPKiPi,@object            # @_Z4stepPKiPi
	.section	.rodata,"a",@progbits
	.globl	_Z4stepPKiPi
	.p2align	3, 0x0
_Z4stepPKiPi:
	.quad	_Z19__device_stub__stepPKiPi
	.size	_Z4stepPKiPi, 8

	.type	.L__const.main.initial_grid,@object # @__const.main.initial_grid
	.p2align	4, 0x0
.L__const.main.initial_grid:
	.long	1                               # 0x1
	.long	1                               # 0x1
	.long	0                               # 0x0
	.long	0                               # 0x0
	.long	1                               # 0x1
	.long	0                               # 0x0
	.long	1                               # 0x1
	.long	0                               # 0x0
	.long	1                               # 0x1
	.long	1                               # 0x1
	.long	1                               # 0x1
	.long	0                               # 0x0
	.long	1                               # 0x1
	.long	0                               # 0x0
	.long	1                               # 0x1
	.long	1                               # 0x1
	.long	0                               # 0x0
	.long	0                               # 0x0
	.long	1                               # 0x1
	.long	1                               # 0x1
	.long	1                               # 0x1
	.long	0                               # 0x0
	.long	0                               # 0x0
	.long	1                               # 0x1
	.long	0                               # 0x0
	.long	1                               # 0x1
	.long	0                               # 0x0
	.long	0                               # 0x0
	.long	0                               # 0x0
	.long	0                               # 0x0
	.long	1                               # 0x1
	.long	1                               # 0x1
	.long	0                               # 0x0
	.long	1                               # 0x1
	.long	0                               # 0x0
	.long	0                               # 0x0
	.long	1                               # 0x1
	.long	1                               # 0x1
	.long	1                               # 0x1
	.long	1                               # 0x1
	.long	1                               # 0x1
	.long	1                               # 0x1
	.long	1                               # 0x1
	.long	1                               # 0x1
	.long	1                               # 0x1
	.long	0                               # 0x0
	.long	0                               # 0x0
	.long	0                               # 0x0
	.long	1                               # 0x1
	.long	1                               # 0x1
	.long	1                               # 0x1
	.long	1                               # 0x1
	.long	1                               # 0x1
	.long	1                               # 0x1
	.long	1                               # 0x1
	.long	0                               # 0x0
	.long	1                               # 0x1
	.long	0                               # 0x0
	.long	1                               # 0x1
	.long	1                               # 0x1
	.long	0                               # 0x0
	.long	1                               # 0x1
	.long	0                               # 0x0
	.long	1                               # 0x1
	.size	.L__const.main.initial_grid, 256

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"Active: "
	.size	.L.str, 9

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"\n"
	.size	.L.str.1, 2

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z4stepPKiPi"
	.size	.L__unnamed_1, 13

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z19__device_stub__stepPKiPi
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z4stepPKiPi
	.addrsig_sym _ZSt4cout
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z4stepPKiPi            ; -- Begin function _Z4stepPKiPi
	.globl	_Z4stepPKiPi
	.p2align	8
	.type	_Z4stepPKiPi,@function
_Z4stepPKiPi:                           ; @_Z4stepPKiPi
; %bb.0:
	s_load_b32 s2, s[0:1], 0x1c
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[2:3], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_i32_e32 0x10810, v2
	s_cbranch_execz .LBB0_18
; %bb.1:
	s_load_b128 s[4:7], s[0:1], 0x0
	v_ashrrev_i32_e32 v3, 31, v2
	s_mov_b32 s8, exec_lo
	v_mov_b32_e32 v9, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[2:3]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v3, vcc_lo, s4, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v4, vcc_lo, s5, v1, vcc_lo
	global_load_b32 v5, v[3:4], off
	v_mul_hi_i32 v3, 0x64d319ff, v2
	v_lshrrev_b32_e32 v4, 31, v3
	v_ashrrev_i32_e32 v3, 11, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v4, v3, v4
	v_min_i32_e32 v6, 11, v4
	v_max_i32_e32 v3, 1, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v6, 2, v6
	v_cmpx_le_i32_e64 v3, v6
	s_cbranch_execz .LBB0_17
; %bb.2:                                ; %.preheader68.lr.ph
	v_mad_i32_i24 v2, 0xffffebb0, v4, v2
	s_mov_b32 s9, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_i32 v4, 0x51eb851f, v2
	v_lshrrev_b32_e32 v7, 31, v4
	v_ashrrev_i32_e32 v4, 7, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v4, v4, v7
	v_mad_i32_i24 v2, 0xfffffe70, v4, v2
	v_max_i32_e32 v12, 1, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_i32 v7, 0x66666667, v2
	v_lshrrev_b32_e32 v8, 31, v7
	v_ashrrev_i32_e32 v7, 3, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v11, v7, v8
	v_add_nc_u32_e32 v7, -1, v3
	v_add_nc_u32_e32 v8, -1, v12
	v_mad_u64_u32 v[9:10], null, 0xffffffec, v11, v[2:3]
	v_mul_u32_u24_e32 v2, 0x1450, v3
	v_min_i32_e32 v3, 11, v4
	v_mul_lo_u32 v4, 0x190, v12
	v_max_i32_e32 v14, 1, v11
	v_min_i32_e32 v13, 18, v11
	s_delay_alu instid0(VALU_DEP_4)
	v_add_nc_u32_e32 v10, 2, v3
	v_min_i32_e32 v3, 18, v9
	v_max_i32_e32 v9, 1, v9
	v_mul_lo_u32 v15, v14, 20
	v_add_nc_u32_e32 v11, 2, v13
	v_cmp_le_i32_e32 vcc_lo, v12, v10
	v_add_nc_u32_e32 v12, 2, v3
	v_add3_u32 v2, v9, v2, v4
	v_add_nc_u32_e32 v13, -1, v14
	v_cmp_le_i32_e64 s0, v14, v11
	v_add_nc_u32_e32 v14, -1, v9
	v_cmp_le_i32_e64 s1, v9, v12
	v_mov_b32_e32 v9, 0
	v_add3_u32 v15, v2, v15, 0xffffea0b
.LBB0_3:                                ; %.preheader68
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_5 Depth 2
                                        ;       Child Loop BB0_7 Depth 3
                                        ;         Child Loop BB0_9 Depth 4
	s_and_saveexec_b32 s10, vcc_lo
	s_cbranch_execz .LBB0_15
; %bb.4:                                ; %.preheader67.lr.ph
                                        ;   in Loop: Header=BB0_3 Depth=1
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_mov_b32 v16, v15 :: v_dual_mov_b32 v17, v8
	s_mov_b32 s11, 0
.LBB0_5:                                ; %.preheader67
                                        ;   Parent Loop BB0_3 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB0_7 Depth 3
                                        ;         Child Loop BB0_9 Depth 4
	s_and_saveexec_b32 s12, s0
	s_cbranch_execz .LBB0_13
; %bb.6:                                ; %.preheader.lr.ph
                                        ;   in Loop: Header=BB0_5 Depth=2
	s_delay_alu instid0(VALU_DEP_1)
	v_mov_b32_e32 v2, v16
	v_mov_b32_e32 v18, v13
	s_mov_b32 s13, 0
.LBB0_7:                                ; %.preheader
                                        ;   Parent Loop BB0_3 Depth=1
                                        ;     Parent Loop BB0_5 Depth=2
                                        ; =>    This Loop Header: Depth=3
                                        ;         Child Loop BB0_9 Depth 4
	s_and_saveexec_b32 s14, s1
	s_cbranch_execz .LBB0_11
; %bb.8:                                ; %.lr.ph
                                        ;   in Loop: Header=BB0_7 Depth=3
	v_ashrrev_i32_e32 v3, 31, v2
	v_mov_b32_e32 v19, v14
	s_mov_b32 s15, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[2:3]
	v_add_co_u32 v3, s2, s4, v3
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v4, s2, s5, v4, s2
.LBB0_9:                                ;   Parent Loop BB0_3 Depth=1
                                        ;     Parent Loop BB0_5 Depth=2
                                        ;       Parent Loop BB0_7 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	global_load_b32 v20, v[3:4], off
	v_add_nc_u32_e32 v19, 1, v19
	v_add_co_u32 v3, s2, v3, 4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v4, s2, 0, v4, s2
	v_cmp_ge_i32_e64 s3, v19, v12
	s_delay_alu instid0(VALU_DEP_1)
	s_or_b32 s15, s3, s15
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v9, v20, v9
	s_and_not1_b32 exec_lo, exec_lo, s15
	s_cbranch_execnz .LBB0_9
; %bb.10:                               ; %Flow
                                        ;   in Loop: Header=BB0_7 Depth=3
	s_or_b32 exec_lo, exec_lo, s15
.LBB0_11:                               ; %Flow97
                                        ;   in Loop: Header=BB0_7 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	s_or_b32 exec_lo, exec_lo, s14
	v_add_nc_u32_e32 v18, 1, v18
	v_add_nc_u32_e32 v2, 20, v2
	v_cmp_ge_i32_e64 s2, v18, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s13, s2, s13
	s_and_not1_b32 exec_lo, exec_lo, s13
	s_cbranch_execnz .LBB0_7
; %bb.12:                               ; %Flow98
                                        ;   in Loop: Header=BB0_5 Depth=2
	s_or_b32 exec_lo, exec_lo, s13
.LBB0_13:                               ; %Flow99
                                        ;   in Loop: Header=BB0_5 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	s_or_b32 exec_lo, exec_lo, s12
	v_add_nc_u32_e32 v17, 1, v17
	v_add_nc_u32_e32 v16, 0x190, v16
	v_cmp_ge_i32_e64 s2, v17, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s11, s2, s11
	s_and_not1_b32 exec_lo, exec_lo, s11
	s_cbranch_execnz .LBB0_5
; %bb.14:                               ; %Flow100
                                        ;   in Loop: Header=BB0_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s11
.LBB0_15:                               ; %Flow101
                                        ;   in Loop: Header=BB0_3 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	s_or_b32 exec_lo, exec_lo, s10
	v_add_nc_u32_e32 v7, 1, v7
	v_add_nc_u32_e32 v15, 0x1450, v15
	v_cmp_ge_i32_e64 s2, v7, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s9, s2, s9
	s_and_not1_b32 exec_lo, exec_lo, s9
	s_cbranch_execnz .LBB0_3
; %bb.16:                               ; %Flow102
	s_or_b32 exec_lo, exec_lo, s9
.LBB0_17:                               ; %Flow103
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_3)
	s_or_b32 exec_lo, exec_lo, s8
	s_waitcnt vmcnt(0)
	v_sub_nc_u32_e32 v2, v9, v5
	v_cmp_eq_u32_e32 vcc_lo, 0, v5
	v_cmp_eq_u32_e64 s1, 1, v5
	v_add_nc_u32_e32 v3, -4, v2
	v_cmp_eq_u32_e64 s0, 3, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_u32_e64 s2, -2, v3
	s_and_b32 s0, vcc_lo, s0
	v_add_co_u32 v0, vcc_lo, s6, v0
	v_cndmask_b32_e64 v2, v5, 1, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	s_and_b32 s0, s1, s2
	v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
	v_cndmask_b32_e64 v2, v2, 0, s0
	global_store_b32 v[0:1], v2, off
.LBB0_18:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z4stepPKiPi
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 21
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z4stepPKiPi, .Lfunc_end0-_Z4stepPKiPi
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 816
; NumSgprs: 18
; NumVgprs: 21
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 21
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         20
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         28
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         30
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         32
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         34
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         36
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         38
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         56
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         80
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 272
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z4stepPKiPi
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z4stepPKiPi.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     21
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
