
// BlockDim = 16x16
//GridDim = w/16*h/16
extern "C" __global__ void RGB2NV12( unsigned char *in_rgb, unsigned char *nv12,
        int rgb_width, int rgb_height, int rgb_pitch, int nv12_pitch )
{
    unsigned char *rgb1,*rgb2,*rgb3,*rgb4, r,g,b,u,v;
    unsigned char *pYDst, *pUVDst;
    int x,y,uv_y;
    x = blockIdx.x*blockDim.x+threadIdx.x;
    y = blockIdx.y*blockDim.y+threadIdx.y;//Y 
    uv_y = y + (rgb_height<<1);// UV 

    if ((x < rgb_width) && (y < rgb_height))
    {
        rgb1 = in_rgb + (y << 1) * rgb_pitch + (x << 1) * 3;
        rgb2 = in_rgb + (y << 1) * rgb_pitch + ((x << 1) + 1) * 3;
        rgb3 = rgb1 + rgb_pitch;
        rgb4 = rgb2 + rgb_pitch;

        pYDst = nv12 + (y << 1)*nv12_pitch;
        u = -0.09991f * rgb1[0] - 0.33609f * rgb1[1] + 0.436f * rgb1[2] + 128;
        v = 0.614f * rgb1[0] - 0.55861f * rgb1[1] - 0.05639f * rgb1[2] + 128;
        pYDst[x << 1] = (rgb1[0]+ rgb1[1] + rgb1[2])/3.492f + 104.339f - 0.446f*u - 0.224f*v;//Y 

        u = -0.09991f * rgb2[0] - 0.33609f * rgb2[1] + 0.436f * rgb2[2] + 128;
        v = 0.614f*rgb2[0]  - 0.55861f*rgb2[1]  - 0.05639f*rgb2[2]  + 128;
        pYDst[(x << 1) + 1] = (rgb2[0] + rgb2[1] +rgb2[2])/3.492f + 104.339f - 0.446f*u - 0.224f*v;//Y

        pYDst = nv12 + ((y << 1) + 1)*nv12_pitch;
        u = -0.09991f * rgb3[0]- 0.33609f * rgb3[1] + 0.436f * rgb3[2] + 128;
        v = 0.614f * rgb3[0]  - 0.55861f * rgb3[1] - 0.05639f * rgb3[2] + 128;
        pYDst[x << 1] = (rgb3[0]+ rgb3[1] + rgb3[2])/3.492f + 104.339f - 0.446f*u - 0.224f*v;//Y

        u = -0.09991f * rgb4[0] - 0.33609f * rgb4[1] + 0.436f * rgb4[2] + 128;
        v = 0.614f * rgb4[0] - 0.55861f * rgb4[1] - 0.05639f * rgb4[2] + 128;
        pYDst[(x << 1) + 1] = (rgb4[0]+ rgb4[1] + rgb4[2])/3.492f + 104.339f - 0.446f*u - 0.224f*v;//Y

        r = (rgb1[0] + rgb2[0] + rgb3[0] + rgb4[0])/4;
        g = (rgb1[1] + rgb2[1] + rgb3[1] + rgb4[1])/4;
        b = (rgb1[2] + rgb2[2] + rgb3[2] + rgb4[2])/4;
        pUVDst = nv12 + uv_y*nv12_pitch;
        pUVDst[x << 1] =  -0.09991f*r - 0.33609f*g + 0.436f*b + 128;//U
        pUVDst[(x << 1) + 1] = 0.614f*r - 0.55861f*g - 0.05639f*b + 128;//V

    }
}


	.file	"tmpxft_0033c1e3_00000000-6_rgb2nv12.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2010:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2010:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z33__device_stub__Z8RGB2NV12PhS_iiiiPhS_iiii
	.type	_Z33__device_stub__Z8RGB2NV12PhS_iiiiPhS_iiii, @function
_Z33__device_stub__Z8RGB2NV12PhS_iiiiPhS_iiii:
.LFB2032:
	.cfi_startproc
	endbr64
	subq	$168, %rsp
	.cfi_def_cfa_offset 176
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	48(%rsp), %rcx
	movl	%r8d, 4(%rsp)
	movl	%r9d, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 152(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 136(%rsp)
	movq	%rsp, %rax
	movq	%rax, 144(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	48(%rsp)
	.cfi_def_cfa_offset 184
	leaq	RGB2NV12(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 192
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 184
	popq	%rdx
	.cfi_def_cfa_offset 176
.L2:
	movq	152(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$168, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2032:
	.size	_Z33__device_stub__Z8RGB2NV12PhS_iiiiPhS_iiii, .-_Z33__device_stub__Z8RGB2NV12PhS_iiiiPhS_iiii
	.globl	RGB2NV12
	.type	RGB2NV12, @function
RGB2NV12:
.LFB2033:
	.cfi_startproc
	endbr64
	jmp	_Z33__device_stub__Z8RGB2NV12PhS_iiiiPhS_iiii
	.cfi_endproc
.LFE2033:
	.size	RGB2NV12, .-RGB2NV12
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"RGB2NV12"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2035:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	RGB2NV12(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2035:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>

// BlockDim = 16x16
//GridDim = w/16*h/16
extern "C" __global__ void RGB2NV12( unsigned char *in_rgb, unsigned char *nv12,
        int rgb_width, int rgb_height, int rgb_pitch, int nv12_pitch )
{
    unsigned char *rgb1,*rgb2,*rgb3,*rgb4, r,g,b,u,v;
    unsigned char *pYDst, *pUVDst;
    int x,y,uv_y;
    x = blockIdx.x*blockDim.x+threadIdx.x;
    y = blockIdx.y*blockDim.y+threadIdx.y;//Y 
    uv_y = y + (rgb_height<<1);// UV 

    if ((x < rgb_width) && (y < rgb_height))
    {
        rgb1 = in_rgb + (y << 1) * rgb_pitch + (x << 1) * 3;
        rgb2 = in_rgb + (y << 1) * rgb_pitch + ((x << 1) + 1) * 3;
        rgb3 = rgb1 + rgb_pitch;
        rgb4 = rgb2 + rgb_pitch;

        pYDst = nv12 + (y << 1)*nv12_pitch;
        u = -0.09991f * rgb1[0] - 0.33609f * rgb1[1] + 0.436f * rgb1[2] + 128;
        v = 0.614f * rgb1[0] - 0.55861f * rgb1[1] - 0.05639f * rgb1[2] + 128;
        pYDst[x << 1] = (rgb1[0]+ rgb1[1] + rgb1[2])/3.492f + 104.339f - 0.446f*u - 0.224f*v;//Y 

        u = -0.09991f * rgb2[0] - 0.33609f * rgb2[1] + 0.436f * rgb2[2] + 128;
        v = 0.614f*rgb2[0]  - 0.55861f*rgb2[1]  - 0.05639f*rgb2[2]  + 128;
        pYDst[(x << 1) + 1] = (rgb2[0] + rgb2[1] +rgb2[2])/3.492f + 104.339f - 0.446f*u - 0.224f*v;//Y

        pYDst = nv12 + ((y << 1) + 1)*nv12_pitch;
        u = -0.09991f * rgb3[0]- 0.33609f * rgb3[1] + 0.436f * rgb3[2] + 128;
        v = 0.614f * rgb3[0]  - 0.55861f * rgb3[1] - 0.05639f * rgb3[2] + 128;
        pYDst[x << 1] = (rgb3[0]+ rgb3[1] + rgb3[2])/3.492f + 104.339f - 0.446f*u - 0.224f*v;//Y

        u = -0.09991f * rgb4[0] - 0.33609f * rgb4[1] + 0.436f * rgb4[2] + 128;
        v = 0.614f * rgb4[0] - 0.55861f * rgb4[1] - 0.05639f * rgb4[2] + 128;
        pYDst[(x << 1) + 1] = (rgb4[0]+ rgb4[1] + rgb4[2])/3.492f + 104.339f - 0.446f*u - 0.224f*v;//Y

        r = (rgb1[0] + rgb2[0] + rgb3[0] + rgb4[0])/4;
        g = (rgb1[1] + rgb2[1] + rgb3[1] + rgb4[1])/4;
        b = (rgb1[2] + rgb2[2] + rgb3[2] + rgb4[2])/4;
        pUVDst = nv12 + uv_y*nv12_pitch;
        pUVDst[x << 1] =  -0.09991f*r - 0.33609f*g + 0.436f*b + 128;//U
        pUVDst[(x << 1) + 1] = 0.614f*r - 0.55861f*g - 0.05639f*b + 128;//V

    }
}


	.text
	.file	"rgb2nv12.hip"
	.globl	__device_stub__RGB2NV12         # -- Begin function __device_stub__RGB2NV12
	.type	__device_stub__RGB2NV12,@function
__device_stub__RGB2NV12:                # @__device_stub__RGB2NV12
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	4(%rsp), %rcx
	movl	%r8d, (%rcx)
	movq	%rsp, %r8
	movl	%r9d, (%r8)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$RGB2NV12, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	__device_stub__RGB2NV12, .Lfunc_end0-__device_stub__RGB2NV12
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$RGB2NV12, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	RGB2NV12,@object                # @RGB2NV12
	.section	.rodata,"a",@progbits
	.globl	RGB2NV12
	.p2align	3, 0x0
RGB2NV12:
	.quad	__device_stub__RGB2NV12
	.size	RGB2NV12, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"RGB2NV12"
	.size	.L__unnamed_1, 9

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __device_stub__RGB2NV12
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym RGB2NV12
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	RGB2NV12                ; -- Begin function RGB2NV12
	.globl	RGB2NV12
	.p2align	8
	.type	RGB2NV12,@function
RGB2NV12:                               ; @RGB2NV12
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x2c
	s_load_b128 s[4:7], s[0:1], 0x10
	v_and_b32_e32 v1, 0x3ff, v0
	v_bfe_u32 v4, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s2, 16
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[2:3], null, s14, s2, v[1:2]
	v_mad_u64_u32 v[0:1], null, s15, s3, v[4:5]
	v_cmp_gt_i32_e32 vcc_lo, s4, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_gt_i32_e64 s2, s5, v0
	s_and_b32 s2, vcc_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_2
; %bb.1:
	s_load_b128 s[0:3], s[0:1], 0x0
	v_lshlrev_b32_e32 v1, 1, v0
	v_mul_lo_u32 v4, v2, 6
	v_lshl_add_u32 v0, s5, 1, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v3, v1, s6
	v_mul_lo_u32 v0, v0, s7
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_ashrrev_i32_e32 v6, 31, v4
	v_ashrrev_i32_e32 v5, 31, v3
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v7, vcc_lo, s0, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v8, vcc_lo, s1, v5, vcc_lo
	s_ashr_i32 s0, s6, 31
	v_add_co_u32 v3, vcc_lo, v7, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, v8, v6, vcc_lo
	s_clause 0x1
	global_load_u16 v5, v[3:4], off
	global_load_i8 v6, v[3:4], off offset:2
	s_waitcnt vmcnt(1)
	v_lshrrev_b32_e32 v9, 8, v5
	v_and_b32_e32 v10, 0xff, v5
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v11, 0xff, v6
	v_cvt_f32_ubyte0_e32 v6, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v9, v9, v10, v11
	v_cvt_f32_i32_e32 v9, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f32 v10, null, 0x405f7cee, 0x405f7cee, v9
	v_div_scale_f32 v13, vcc_lo, v9, 0x405f7cee, v9
	v_rcp_f32_e32 v11, v10
	s_waitcnt_depctr 0xfff
	v_fma_f32 v12, -v10, v11, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v11, v12, v11
	v_cvt_f32_ubyte1_e32 v12, v5
	v_cvt_f32_ubyte0_e32 v5, v5
	v_mul_f32_e32 v14, v13, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f32 v16, -v10, v14, v13
	v_mul_f32_e32 v15, 0x3eac13fd, v12
	v_mul_f32_e32 v12, 0x3f0f0111, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v14, v16, v11
	v_fma_f32 v15, 0xbdcc9d9d, v5, -v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v5, 0x3f1d2f1b, v5, -v12
	v_fmac_f32_e32 v15, 0x3edf3b64, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v5, 0xbd66f933, v6
	v_lshlrev_b32_e32 v12, 1, v2
	v_fma_f32 v2, -v10, v14, v13
	v_add_f32_e32 v6, 0x43000000, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_div_fmas_f32 v2, v2, v11, v14
	v_mul_lo_u32 v11, v1, s7
	v_add_f32_e32 v1, 0x43000000, v5
	v_cvt_i32_f32_e32 v5, v6
	v_or_b32_e32 v10, 1, v12
	v_div_fixup_f32 v2, v2, 0x405f7cee, v9
	v_ashrrev_i32_e32 v13, 31, v12
	v_cvt_i32_f32_e32 v1, v1
	v_cvt_f32_ubyte0_e32 v5, v5
	v_lshl_add_u32 v6, v10, 1, v10
	v_add_f32_e32 v9, 0x42d0ad91, v2
	v_ashrrev_i32_e32 v2, 31, v11
	v_cvt_f32_ubyte0_e32 v1, v1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_ashrrev_i32_e32 v10, 31, v6
	v_fmac_f32_e32 v9, 0xbee45a1d, v5
	v_add_co_u32 v5, vcc_lo, s2, v11
	v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v9, 0xbe656042, v1
	v_add_co_u32 v1, vcc_lo, v5, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_co_ci_u32_e32 v2, vcc_lo, v2, v13, vcc_lo
	v_add_co_u32 v5, vcc_lo, v7, v6
	v_cvt_i32_f32_e32 v9, v9
	v_add_co_ci_u32_e32 v6, vcc_lo, v8, v10, vcc_lo
	global_store_b8 v[1:2], v9, off
	s_clause 0x1
	global_load_u16 v7, v[5:6], off
	global_load_i8 v8, v[5:6], off offset:2
	s_waitcnt vmcnt(1)
	v_lshrrev_b32_e32 v9, 8, v7
	v_and_b32_e32 v10, 0xff, v7
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v14, 0xff, v8
	v_cvt_f32_ubyte0_e32 v8, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v9, v9, v10, v14
	v_cvt_f32_i32_e32 v9, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f32 v10, null, 0x405f7cee, 0x405f7cee, v9
	v_div_scale_f32 v16, vcc_lo, v9, 0x405f7cee, v9
	v_rcp_f32_e32 v14, v10
	s_waitcnt_depctr 0xfff
	v_fma_f32 v15, -v10, v14, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v14, v15, v14
	v_cvt_f32_ubyte1_e32 v15, v7
	v_cvt_f32_ubyte0_e32 v7, v7
	v_dual_mul_f32 v17, v16, v14 :: v_dual_mul_f32 v18, 0x3eac13fd, v15
	v_mul_f32_e32 v15, 0x3f0f0111, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v19, -v10, v17, v16
	v_fma_f32 v18, 0xbdcc9d9d, v7, -v18
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v7, 0x3f1d2f1b, v7, -v15
	v_dual_fmac_f32 v17, v19, v14 :: v_dual_fmac_f32 v18, 0x3edf3b64, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v7, 0xbd66f933, v8
	v_fma_f32 v10, -v10, v17, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_add_f32 v8, 0x43000000, v18 :: v_dual_add_f32 v7, 0x43000000, v7
	v_div_fmas_f32 v10, v10, v14, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cvt_i32_f32_e32 v8, v8
	v_cvt_i32_f32_e32 v7, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_div_fixup_f32 v9, v10, 0x405f7cee, v9
	v_cvt_f32_ubyte0_e32 v8, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cvt_f32_ubyte0_e32 v7, v7
	v_add_f32_e32 v9, 0x42d0ad91, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v9, 0xbee45a1d, v8
	v_fmac_f32_e32 v9, 0xbe656042, v7
	v_add_co_u32 v7, vcc_lo, v3, s6
	v_add_co_ci_u32_e32 v8, vcc_lo, s0, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_3)
	v_cvt_i32_f32_e32 v9, v9
	global_store_b8 v[1:2], v9, off offset:1
	s_clause 0x1
	global_load_u16 v1, v[7:8], off
	global_load_i8 v2, v[7:8], off offset:2
	s_waitcnt vmcnt(1)
	v_lshrrev_b32_e32 v9, 8, v1
	v_and_b32_e32 v10, 0xff, v1
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v14, 0xff, v2
	v_cvt_f32_ubyte0_e32 v2, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v9, v9, v10, v14
	v_cvt_f32_i32_e32 v9, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f32 v10, null, 0x405f7cee, 0x405f7cee, v9
	v_div_scale_f32 v16, vcc_lo, v9, 0x405f7cee, v9
	v_rcp_f32_e32 v14, v10
	s_waitcnt_depctr 0xfff
	v_fma_f32 v15, -v10, v14, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v14, v15, v14
	v_cvt_f32_ubyte1_e32 v15, v1
	v_cvt_f32_ubyte0_e32 v1, v1
	v_dual_mul_f32 v17, v16, v14 :: v_dual_mul_f32 v18, 0x3eac13fd, v15
	v_mul_f32_e32 v15, 0x3f0f0111, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v19, -v10, v17, v16
	v_fma_f32 v18, 0xbdcc9d9d, v1, -v18
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v1, 0x3f1d2f1b, v1, -v15
	v_fmac_f32_e32 v17, v19, v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v18, 0x3edf3b64, v2
	v_fmac_f32_e32 v1, 0xbd66f933, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v10, -v10, v17, v16
	v_dual_add_f32 v2, 0x43000000, v18 :: v_dual_add_f32 v1, 0x43000000, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fmas_f32 v10, v10, v14, v17
	v_cvt_i32_f32_e32 v2, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cvt_i32_f32_e32 v1, v1
	v_div_fixup_f32 v9, v10, 0x405f7cee, v9
	v_add_nc_u32_e32 v10, s7, v11
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cvt_f32_ubyte0_e32 v2, v2
	v_cvt_f32_ubyte0_e32 v1, v1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f32_e32 v9, 0x42d0ad91, v9
	v_ashrrev_i32_e32 v11, 31, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v9, 0xbee45a1d, v2
	v_add_co_u32 v2, vcc_lo, s2, v10
	v_add_co_ci_u32_e32 v10, vcc_lo, s3, v11, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v9, 0xbe656042, v1
	v_add_co_u32 v1, vcc_lo, v2, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v2, vcc_lo, v10, v13, vcc_lo
	v_cvt_i32_f32_e32 v11, v9
	v_add_co_u32 v9, vcc_lo, v5, s6
	v_add_co_ci_u32_e32 v10, vcc_lo, s0, v6, vcc_lo
	global_store_b8 v[1:2], v11, off
	s_clause 0x1
	global_load_u16 v11, v[9:10], off
	global_load_i8 v14, v[9:10], off offset:2
	s_waitcnt vmcnt(1)
	v_lshrrev_b32_e32 v15, 8, v11
	v_and_b32_e32 v16, 0xff, v11
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v17, 0xff, v14
	v_cvt_f32_ubyte0_e32 v14, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v15, v15, v16, v17
	v_cvt_f32_i32_e32 v15, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f32 v16, null, 0x405f7cee, 0x405f7cee, v15
	v_div_scale_f32 v19, vcc_lo, v15, 0x405f7cee, v15
	v_rcp_f32_e32 v17, v16
	s_waitcnt_depctr 0xfff
	v_fma_f32 v18, -v16, v17, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v17, v18, v17
	v_cvt_f32_ubyte1_e32 v18, v11
	v_cvt_f32_ubyte0_e32 v11, v11
	v_dual_mul_f32 v20, v19, v17 :: v_dual_mul_f32 v21, 0x3eac13fd, v18
	v_mul_f32_e32 v18, 0x3f0f0111, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v22, -v16, v20, v19
	v_fma_f32 v21, 0xbdcc9d9d, v11, -v21
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v11, 0x3f1d2f1b, v11, -v18
	v_dual_fmac_f32 v20, v22, v17 :: v_dual_fmac_f32 v21, 0x3edf3b64, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v11, 0xbd66f933, v14
	v_fma_f32 v16, -v16, v20, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_add_f32 v14, 0x43000000, v21 :: v_dual_add_f32 v11, 0x43000000, v11
	v_div_fmas_f32 v16, v16, v17, v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cvt_i32_f32_e32 v14, v14
	v_cvt_i32_f32_e32 v11, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_div_fixup_f32 v15, v16, 0x405f7cee, v15
	v_cvt_f32_ubyte0_e32 v14, v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cvt_f32_ubyte0_e32 v11, v11
	v_add_f32_e32 v15, 0x42d0ad91, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v15, 0xbee45a1d, v14
	v_fmac_f32_e32 v15, 0xbe656042, v11
	s_delay_alu instid0(VALU_DEP_1)
	v_cvt_i32_f32_e32 v11, v15
	global_store_b8 v[1:2], v11, off offset:1
	s_clause 0x7
	global_load_u16 v1, v[3:4], off
	global_load_u16 v2, v[5:6], off
	global_load_u16 v11, v[7:8], off
	global_load_u16 v14, v[9:10], off
	global_load_u8 v9, v[9:10], off offset:2
	global_load_u8 v7, v[7:8], off offset:2
	global_load_u8 v5, v[5:6], off offset:2
	global_load_u8 v3, v[3:4], off offset:2
	s_waitcnt vmcnt(7)
	v_lshrrev_b32_e32 v4, 8, v1
	s_waitcnt vmcnt(6)
	v_lshrrev_b32_e32 v6, 8, v2
	v_and_b32_e32 v1, 0xff, v1
	v_and_b32_e32 v2, 0xff, v2
	s_waitcnt vmcnt(5)
	v_lshrrev_b32_e32 v8, 8, v11
	s_waitcnt vmcnt(4)
	v_lshrrev_b32_e32 v10, 8, v14
	v_add_nc_u32_e32 v4, v6, v4
	v_and_b32_e32 v6, 0xff, v11
	v_and_b32_e32 v11, 0xff, v14
	v_add_nc_u32_e32 v1, v2, v1
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v3, v5, v3
	v_add3_u32 v2, v4, v8, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add3_u32 v1, v1, v6, v11
	v_add3_u32 v3, v3, v7, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshrrev_b32_e32 v2, 2, v2
	v_lshrrev_b32_e32 v1, 2, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshrrev_b32_e32 v3, 2, v3
	v_cvt_f32_i32_e32 v2, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cvt_f32_i32_e32 v1, v1
	v_cvt_f32_i32_e32 v3, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v4, 0x3f0f0111, v2
	v_mul_f32_e32 v2, 0x3eac13fd, v2
	v_fma_f32 v4, 0x3f1d2f1b, v1, -v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v1, 0xbdcc9d9d, v1, -v2
	v_fmac_f32_e32 v4, 0xbd66f933, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v1, 0x3edf3b64, v3
	v_ashrrev_i32_e32 v3, 31, v0
	v_add_co_u32 v0, vcc_lo, s2, v0
	v_dual_add_f32 v2, 0x43000000, v4 :: v_dual_add_f32 v1, 0x43000000, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
	v_add_co_u32 v0, vcc_lo, v0, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cvt_i32_f32_e32 v2, v2
	v_cvt_i32_f32_e32 v4, v1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v1, vcc_lo, v3, v13, vcc_lo
	v_lshlrev_b16 v2, 8, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_or_b32_e32 v2, v4, v2
	global_store_b16 v[0:1], v2, off
.LBB0_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel RGB2NV12
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 23
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	RGB2NV12, .Lfunc_end0-RGB2NV12
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 2028
; NumSgprs: 18
; NumVgprs: 23
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 23
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           RGB2NV12
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         RGB2NV12.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     23
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
