/* compile with /usr/local/cuda-10.0/bin/nvcc -arch=compute_XX -o foo.out foo.cu
*  run with ./foo.out N mode
*  N is the size of matrix, mode is different way to multiply matrix
*  1 represents naive gpu, 2 means tiled gpu, 3 means transposed tiled gpu 
*/

#include <stdio.h>
#include <stdlib.h>

#define MAX_MAT_VALUE 10
#define BLOCK_SIZE 16

void cpu_matrixMul(float *A, float *B, float *C, int N) {
    int i, j, k;
    for (i = 0; i < N; i++) {
        for (j = 0; j < N; j++) {
            float partial = 0.0;
            for (k = 0; k < N; k++) {
                partial += A[i * N + k] * B[k * N + j];
            }
            C[i * N + j] = partial;
        }
    }
}

__global__ void naive_matrxiMul(float *dev_A, float *dev_B, float *dev_C, int N) {
    float partial = 0.0;
    int row = blockIdx.y * blockDim.y + threadIdx.y;
    int col = blockIdx.x * blockDim.x + threadIdx.x;

    int k;
    if (row < N && col < N) {
        for (k = 0; k < N; k++) {
            partial += dev_A[row * N + k] * dev_B[k * N + col];
        }
        dev_C[row * N + col] = partial;
    }
}

__global__ void tiled_matrxiMul(float *dev_A, float *dev_B, float *dev_C, int N) {
    __shared__ float A_tile[BLOCK_SIZE][BLOCK_SIZE];
    __shared__ float B_tile[BLOCK_SIZE][BLOCK_SIZE];

    float partial = 0.0;
    int row = blockIdx.y * blockDim.y + threadIdx.y;
    int col = blockIdx.x * blockDim.x + threadIdx.x;

    int tx = threadIdx.x, ty = threadIdx.y;

    int m;
    for (m = 0; m < N / blockDim.x; ++m) {
        A_tile[ty][tx] = dev_A[row * N + m * blockDim.x + tx];
        B_tile[ty][tx] = dev_B[N * (m * blockDim.y + ty) + col];
        __syncthreads();
        int k;
        for (k = 0; k < blockDim.x; ++k) {
            partial += A_tile[ty][k] * B_tile[k][tx];
        }
        __syncthreads();
    }
    if (row < N && col < N) {
        dev_C[row * N + col] = partial;
    }
}

__global__ void transposed_tiled_matrxiMul(float *dev_A, float *dev_B, float *dev_C, int N) {
    __shared__ float A_tile[BLOCK_SIZE][BLOCK_SIZE];
    __shared__ float B_tile[BLOCK_SIZE][BLOCK_SIZE];

    float partial = 0.0;
    int row = blockIdx.y * blockDim.y + threadIdx.y;
    int col = blockIdx.x * blockDim.x + threadIdx.x;

    int tx = threadIdx.x, ty = threadIdx.y;

    int m;
    for (m = 0; m < N / blockDim.x; ++m) {
        A_tile[ty][tx] = dev_A[row * N + m * blockDim.x + tx];
        B_tile[tx][ty] = dev_B[N * (m * blockDim.y + ty) + col];
        __syncthreads();
        int k;
        for (k = 0; k < blockDim.x; ++k) {
            partial += A_tile[ty][k] * B_tile[tx][k];
        }
        __syncthreads();
    }
    if (row < N && col < N) {
        dev_C[row * N + col] = partial;
    }
}

void print_matrix(float *A, int N) {
    int i, j;
    for (i = 0; i < N; i++) {
        for (j = 0; j < N; j++) {
            printf("%.3f ", A[i * N + j]);
        }
        printf("\n");
    }
}

int main(int argc, char *argv[]) {
    if (argc != 3) {
        puts("Please specify the size of matrix and mode (1, 2, 3, 4)");
        return 0;
    }

    int N;
    int mode;
    N = atoi(argv[1]);
    mode = atoi(argv[2]);

    float *A, *B, *C, *CC, *dev_A, *dev_B, *dev_C;

    // allocate memory in host
    cudaMallocHost((void **) &A, N * N * sizeof(float));
    cudaMallocHost((void **) &B, N * N * sizeof(float));
    cudaMallocHost((void **) &C, N * N * sizeof(float));
    cudaMallocHost((void **) &CC, N * N * sizeof(float));

    int i, j;
    // initialize matrix A and B
    srand48(1);
    for (i = 0; i < N; i++) {
        for (j = 0; j < N; j++) {
            A[i * N + j] = drand48() * MAX_MAT_VALUE;
            B[i * N + j] = drand48() * MAX_MAT_VALUE;
        }
    }

    float gpu_time, cpu_time;
    cudaEvent_t start, stop;
    cudaEventCreate(&start);
    cudaEventCreate(&stop);

    cudaEventRecord(start, 0);

    // allocate memory on the device
    cudaMalloc((void**) &dev_A, N * N * sizeof(float));
    cudaMalloc((void**) &dev_B, N * N * sizeof(float));
    cudaMalloc((void**) &dev_C, N * N * sizeof(float));

    cudaMemcpy(dev_A, A, N * N * sizeof(float), cudaMemcpyHostToDevice);
    cudaMemcpy(dev_B, B, N * N * sizeof(float), cudaMemcpyHostToDevice);

    dim3 Block(BLOCK_SIZE, BLOCK_SIZE);
    dim3 Grid(N / Block.x, N / Block.y);

    if (mode == 1) {
        naive_matrxiMul<<< Grid, Block>>>(dev_A, dev_B, dev_C, N);
    } else if (mode == 2) {
        tiled_matrxiMul<<< Grid, Block>>>(dev_A, dev_B, dev_C, N);
    } else if (mode == 3) {
        transposed_tiled_matrxiMul<<< Grid, Block>>>(dev_A, dev_B, dev_C, N);
    } else {
        return 0;
    }
    
    cudaMemcpy(C, dev_C, N * N * sizeof(float), cudaMemcpyDeviceToHost);
    cudaDeviceSynchronize();
    cudaEventRecord(stop, 0);
    cudaEventSynchronize(stop);

    cudaEventElapsedTime(&gpu_time, start, stop);
    printf("total time used on gpu matrix multiply: %f ms.\n", gpu_time);

    // start cpu matrix multiply
    cudaEventRecord(start, 0);
    cpu_matrixMul(A, B, CC, N);

    cudaEventRecord(stop, 0);
    cudaEventSynchronize(stop);
    cudaEventElapsedTime(&cpu_time, start, stop);
    printf("total time used on cpu matrix multiply: %f ms.\n", cpu_time);

    // validate result
    int all_right = 1;
    for (i = 0; i < N; ++i) {
        for (j = 0; j < N; ++j) {
            if (abs(CC[i * N + j] - C[i * N + j]) > 2) {
                printf("%3.f != %3.f\n", C[i * N + j], CC[i * N + j]);
                all_right = 0;
                break;
            }
        }
    }

    if (all_right) {
        printf("all results are right, speed up by gpu = %f.2\n", cpu_time / gpu_time);
    } else {
        printf("wrong results\n");
    }

    cudaFree(dev_A);
    cudaFree(dev_B);
    cudaFree(dev_C);
    cudaFreeHost(A);
    cudaFreeHost(B);
    cudaFreeHost(C);
    cudaFreeHost(CC);

    return 0;
}
	.file	"tmpxft_003b10c7_00000000-6_jf773_hw4_1_to_3.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2032:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2032:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z13cpu_matrixMulPfS_S_i
	.type	_Z13cpu_matrixMulPfS_S_i, @function
_Z13cpu_matrixMulPfS_S_i:
.LFB2027:
	.cfi_startproc
	endbr64
	movq	%rdi, %r10
	xorl	%r9d, %r9d
	movslq	%ecx, %rdi
	movq	%rsi, %r11
	salq	$2, %rdi
	xorl	%esi, %esi
	cmpl	%ecx, %r9d
	jl	.L11
	ret
.L11:
	pushq	%r12
	.cfi_def_cfa_offset 16
	.cfi_offset 12, -16
	pushq	%rbp
	.cfi_def_cfa_offset 24
	.cfi_offset 6, -24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset 3, -32
.L7:
	xorl	%eax, %eax
	leaq	(%r10,%rsi), %rbp
	leaq	(%rdx,%rsi), %r12
.L6:
	leaq	(%r11,%rax,4), %rbx
	xorl	%r8d, %r8d
	xorps	%xmm0, %xmm0
.L4:
	movss	0(%rbp,%r8,4), %xmm1
	mulss	(%rbx), %xmm1
	incq	%r8
	addq	%rdi, %rbx
	addss	%xmm1, %xmm0
	cmpl	%r8d, %ecx
	jg	.L4
	movss	%xmm0, (%r12,%rax,4)
	incq	%rax
	cmpl	%eax, %ecx
	jg	.L6
	incl	%r9d
	addq	%rdi, %rsi
	cmpl	%ecx, %r9d
	jl	.L7
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2027:
	.size	_Z13cpu_matrixMulPfS_S_i, .-_Z13cpu_matrixMulPfS_S_i
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC1:
	.string	"%.3f "
.LC2:
	.string	"\n"
	.text
	.globl	_Z12print_matrixPfi
	.type	_Z12print_matrixPfi, @function
_Z12print_matrixPfi:
.LFB2028:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	leaq	.LC1(%rip), %r14
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movslq	%esi, %r13
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	xorl	%r12d, %r12d
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movq	%r13, %rbp
	salq	$2, %r13
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movq	%rdi, %rbx
	pushq	%rdx
	.cfi_def_cfa_offset 64
.L14:
	cmpl	%ebp, %r12d
	jge	.L19
	leaq	(%rbx,%r13), %r15
.L15:
	cvtss2sd	(%rbx), %xmm0
	movq	%r14, %rsi
	movl	$2, %edi
	movb	$1, %al
	call	__printf_chk@PLT
	addq	$4, %rbx
	cmpq	%r15, %rbx
	jne	.L15
	leaq	.LC2(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	incl	%r12d
	call	__printf_chk@PLT
	jmp	.L14
.L19:
	popq	%rax
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2028:
	.size	_Z12print_matrixPfi, .-_Z12print_matrixPfi
	.globl	_Z40__device_stub__Z15naive_matrxiMulPfS_S_iPfS_S_i
	.type	_Z40__device_stub__Z15naive_matrxiMulPfS_S_iPfS_S_i, @function
_Z40__device_stub__Z15naive_matrxiMulPfS_S_iPfS_S_i:
.LFB2054:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 4(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L20
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z15naive_matrxiMulPfS_S_i(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L20:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L22
	call	__stack_chk_fail@PLT
.L22:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2054:
	.size	_Z40__device_stub__Z15naive_matrxiMulPfS_S_iPfS_S_i, .-_Z40__device_stub__Z15naive_matrxiMulPfS_S_iPfS_S_i
	.globl	_Z15naive_matrxiMulPfS_S_i
	.type	_Z15naive_matrxiMulPfS_S_i, @function
_Z15naive_matrxiMulPfS_S_i:
.LFB2055:
	.cfi_startproc
	endbr64
	jmp	_Z40__device_stub__Z15naive_matrxiMulPfS_S_iPfS_S_i
	.cfi_endproc
.LFE2055:
	.size	_Z15naive_matrxiMulPfS_S_i, .-_Z15naive_matrxiMulPfS_S_i
	.globl	_Z40__device_stub__Z15tiled_matrxiMulPfS_S_iPfS_S_i
	.type	_Z40__device_stub__Z15tiled_matrxiMulPfS_S_iPfS_S_i, @function
_Z40__device_stub__Z15tiled_matrxiMulPfS_S_iPfS_S_i:
.LFB2056:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 4(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L25
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z15tiled_matrxiMulPfS_S_i(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L25:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L27
	call	__stack_chk_fail@PLT
.L27:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2056:
	.size	_Z40__device_stub__Z15tiled_matrxiMulPfS_S_iPfS_S_i, .-_Z40__device_stub__Z15tiled_matrxiMulPfS_S_iPfS_S_i
	.globl	_Z15tiled_matrxiMulPfS_S_i
	.type	_Z15tiled_matrxiMulPfS_S_i, @function
_Z15tiled_matrxiMulPfS_S_i:
.LFB2057:
	.cfi_startproc
	endbr64
	jmp	_Z40__device_stub__Z15tiled_matrxiMulPfS_S_iPfS_S_i
	.cfi_endproc
.LFE2057:
	.size	_Z15tiled_matrxiMulPfS_S_i, .-_Z15tiled_matrxiMulPfS_S_i
	.globl	_Z51__device_stub__Z26transposed_tiled_matrxiMulPfS_S_iPfS_S_i
	.type	_Z51__device_stub__Z26transposed_tiled_matrxiMulPfS_S_iPfS_S_i, @function
_Z51__device_stub__Z26transposed_tiled_matrxiMulPfS_S_iPfS_S_i:
.LFB2058:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 4(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L30
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z26transposed_tiled_matrxiMulPfS_S_i(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L30:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L32
	call	__stack_chk_fail@PLT
.L32:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2058:
	.size	_Z51__device_stub__Z26transposed_tiled_matrxiMulPfS_S_iPfS_S_i, .-_Z51__device_stub__Z26transposed_tiled_matrxiMulPfS_S_iPfS_S_i
	.globl	_Z26transposed_tiled_matrxiMulPfS_S_i
	.type	_Z26transposed_tiled_matrxiMulPfS_S_i, @function
_Z26transposed_tiled_matrxiMulPfS_S_i:
.LFB2059:
	.cfi_startproc
	endbr64
	jmp	_Z51__device_stub__Z26transposed_tiled_matrxiMulPfS_S_iPfS_S_i
	.cfi_endproc
.LFE2059:
	.size	_Z26transposed_tiled_matrxiMulPfS_S_i, .-_Z26transposed_tiled_matrxiMulPfS_S_i
	.section	.rodata.str1.1
.LC3:
	.string	"Please specify the size of matrix and mode (1, 2, 3, 4)"
.LC5:
	.string	"total time used on gpu matrix multiply: %f ms.\n"
.LC6:
	.string	"total time used on cpu matrix multiply: %f ms.\n"
.LC9:
	.string	"%3.f != %3.f\n"
.LC10:
	.string	"all results are right, speed up by gpu = %f.2\n"
.LC11:
	.string	"wrong results\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2029:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$136, %rsp
	.cfi_def_cfa_offset 192
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	cmpl	$3, %edi
	je	.L36
	leaq	.LC3(%rip), %rdi
	call	puts@PLT
	jmp	.L37
.L36:
	movq	8(%rsi), %rdi
	movq	%rsi, %rbx
	xorl	%r12d, %r12d
	xorl	%r15d, %r15d
	call	atoi@PLT
	movq	16(%rbx), %rdi
	movslq	%eax, %r14
	call	atoi@PLT
	movl	%r14d, %ebx
	leaq	24(%rsp), %rdi
	movq	%r14, %rbp
	imull	%r14d, %ebx
	movl	%eax, %r13d
	salq	$2, %r14
	movslq	%ebx, %rbx
	leaq	0(,%rbx,4), %rax
	movq	%rax, %rsi
	movq	%rax, 8(%rsp)
	call	cudaMallocHost@PLT
	movq	8(%rsp), %rsi
	leaq	32(%rsp), %rdi
	call	cudaMallocHost@PLT
	movq	8(%rsp), %rsi
	leaq	40(%rsp), %rdi
	call	cudaMallocHost@PLT
	movq	8(%rsp), %rsi
	leaq	48(%rsp), %rdi
	call	cudaMallocHost@PLT
	movl	$1, %edi
	call	srand48@PLT
.L38:
	cmpl	%ebp, %r15d
	jge	.L60
	leaq	(%r12,%r14), %rbx
.L39:
	call	drand48@PLT
	mulsd	.LC4(%rip), %xmm0
	movq	24(%rsp), %rdx
	cvtsd2ss	%xmm0, %xmm0
	movss	%xmm0, (%rdx,%r12)
	call	drand48@PLT
	mulsd	.LC4(%rip), %xmm0
	movq	32(%rsp), %rdx
	cvtsd2ss	%xmm0, %xmm0
	movss	%xmm0, (%rdx,%r12)
	addq	$4, %r12
	cmpq	%rbx, %r12
	jne	.L39
	incl	%r15d
	jmp	.L38
.L60:
	leaq	80(%rsp), %rdi
	call	cudaEventCreate@PLT
	leaq	88(%rsp), %rdi
	call	cudaEventCreate@PLT
	movq	80(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movq	8(%rsp), %rsi
	leaq	56(%rsp), %rdi
	call	cudaMalloc@PLT
	movq	8(%rsp), %rsi
	leaq	64(%rsp), %rdi
	call	cudaMalloc@PLT
	movq	8(%rsp), %rsi
	leaq	72(%rsp), %rdi
	call	cudaMalloc@PLT
	movq	8(%rsp), %rdx
	movq	24(%rsp), %rsi
	movl	$1, %ecx
	movq	56(%rsp), %rdi
	call	cudaMemcpy@PLT
	movq	8(%rsp), %rdx
	movq	32(%rsp), %rsi
	movl	$1, %ecx
	movq	64(%rsp), %rdi
	call	cudaMemcpy@PLT
	movl	%ebp, %eax
	movl	$1, 104(%rsp)
	shrl	$4, %eax
	movl	$1, 116(%rsp)
	movl	%eax, 108(%rsp)
	movl	%eax, 112(%rsp)
	cmpl	$1, %r13d
	jne	.L41
	movq	108(%rsp), %rdi
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$1, %ecx
	movabsq	$68719476752, %rdx
	movl	$1, %esi
	movq	%rdx, 96(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L43
	movq	72(%rsp), %rdx
	movq	64(%rsp), %rsi
	movl	%ebp, %ecx
	movq	56(%rsp), %rdi
	call	_Z40__device_stub__Z15naive_matrxiMulPfS_S_iPfS_S_i
	jmp	.L43
.L41:
	cmpl	$2, %r13d
	jne	.L44
	movq	108(%rsp), %rdi
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$1, %ecx
	movabsq	$68719476752, %rdx
	movl	$1, %esi
	movq	%rdx, 96(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L43
	movq	72(%rsp), %rdx
	movq	64(%rsp), %rsi
	movl	%ebp, %ecx
	movq	56(%rsp), %rdi
	call	_Z40__device_stub__Z15tiled_matrxiMulPfS_S_iPfS_S_i
	jmp	.L43
.L44:
	cmpl	$3, %r13d
	jne	.L37
	movq	108(%rsp), %rdi
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$1, %ecx
	movabsq	$68719476752, %rdx
	movl	$1, %esi
	movq	%rdx, 96(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L43
	movq	72(%rsp), %rdx
	movq	64(%rsp), %rsi
	movl	%ebp, %ecx
	movq	56(%rsp), %rdi
	call	_Z51__device_stub__Z26transposed_tiled_matrxiMulPfS_S_iPfS_S_i
.L43:
	movq	8(%rsp), %rdx
	movq	72(%rsp), %rsi
	xorl	%r12d, %r12d
	xorl	%ebx, %ebx
	movq	40(%rsp), %rdi
	movl	$2, %ecx
	call	cudaMemcpy@PLT
	call	cudaDeviceSynchronize@PLT
	movq	88(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movq	88(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movq	88(%rsp), %rdx
	movq	80(%rsp), %rsi
	leaq	16(%rsp), %rdi
	call	cudaEventElapsedTime@PLT
	leaq	.LC5(%rip), %rsi
	movl	$2, %edi
	movb	$1, %al
	cvtss2sd	16(%rsp), %xmm0
	call	__printf_chk@PLT
	movq	80(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movq	48(%rsp), %rdx
	movq	32(%rsp), %rsi
	movl	%ebp, %ecx
	movq	24(%rsp), %rdi
	call	_Z13cpu_matrixMulPfS_S_i
	movq	88(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movq	88(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movq	88(%rsp), %rdx
	movq	80(%rsp), %rsi
	leaq	20(%rsp), %rdi
	call	cudaEventElapsedTime@PLT
	leaq	.LC6(%rip), %rsi
	movl	$2, %edi
	movb	$1, %al
	cvtss2sd	20(%rsp), %xmm0
	call	__printf_chk@PLT
	movl	$1, %ecx
.L46:
	cmpl	%ebp, %ebx
	jge	.L61
	movq	48(%rsp), %rsi
	movq	40(%rsp), %rdi
	movq	%r12, %rax
	xorl	%edx, %edx
.L50:
	movss	(%rsi,%rax), %xmm1
	movss	(%rdi,%rax), %xmm0
	movaps	%xmm1, %xmm2
	subss	%xmm0, %xmm2
	andps	.LC7(%rip), %xmm2
	comiss	.LC8(%rip), %xmm2
	jbe	.L58
	movl	$2, %edi
	movb	$2, %al
	cvtss2sd	%xmm0, %xmm0
	cvtss2sd	%xmm1, %xmm1
	leaq	.LC9(%rip), %rsi
	call	__printf_chk@PLT
	xorl	%ecx, %ecx
	jmp	.L49
.L58:
	incl	%edx
	addq	$4, %rax
	cmpl	%edx, %ebp
	jne	.L50
.L49:
	incl	%ebx
	addq	%r14, %r12
	jmp	.L46
.L61:
	testl	%ecx, %ecx
	je	.L52
	leaq	.LC10(%rip), %rsi
	movl	$2, %edi
	movb	$1, %al
	movss	20(%rsp), %xmm0
	divss	16(%rsp), %xmm0
	cvtss2sd	%xmm0, %xmm0
	call	__printf_chk@PLT
	jmp	.L53
.L52:
	leaq	.LC11(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
.L53:
	movq	56(%rsp), %rdi
	call	cudaFree@PLT
	movq	64(%rsp), %rdi
	call	cudaFree@PLT
	movq	72(%rsp), %rdi
	call	cudaFree@PLT
	movq	24(%rsp), %rdi
	call	cudaFreeHost@PLT
	movq	32(%rsp), %rdi
	call	cudaFreeHost@PLT
	movq	40(%rsp), %rdi
	call	cudaFreeHost@PLT
	movq	48(%rsp), %rdi
	call	cudaFreeHost@PLT
.L37:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L54
	call	__stack_chk_fail@PLT
.L54:
	addq	$136, %rsp
	.cfi_def_cfa_offset 56
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2029:
	.size	main, .-main
	.section	.rodata.str1.1
.LC12:
	.string	"_Z26transposed_tiled_matrxiMulPfS_S_i"
.LC13:
	.string	"_Z15tiled_matrxiMulPfS_S_i"
.LC14:
	.string	"_Z15naive_matrxiMulPfS_S_i"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2061:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC12(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z26transposed_tiled_matrxiMulPfS_S_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC13(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z15tiled_matrxiMulPfS_S_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC14(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z15naive_matrxiMulPfS_S_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2061:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst8,"aM",@progbits,8
	.align 8
.LC4:
	.long	0
	.long	1076101120
	.section	.rodata.cst16,"aM",@progbits,16
	.align 16
.LC7:
	.long	2147483647
	.long	0
	.long	0
	.long	0
	.section	.rodata.cst4,"aM",@progbits,4
	.align 4
.LC8:
	.long	1073741824
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

/* compile with /usr/local/cuda-10.0/bin/nvcc -arch=compute_XX -o foo.out foo.cu
*  run with ./foo.out N mode
*  N is the size of matrix, mode is different way to multiply matrix
*  1 represents naive gpu, 2 means tiled gpu, 3 means transposed tiled gpu 
*/


#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>

#define MAX_MAT_VALUE 10
#define BLOCK_SIZE 16

void cpu_matrixMul(float *A, float *B, float *C, int N) {
    int i, j, k;
    for (i = 0; i < N; i++) {
        for (j = 0; j < N; j++) {
            float partial = 0.0;
            for (k = 0; k < N; k++) {
                partial += A[i * N + k] * B[k * N + j];
            }
            C[i * N + j] = partial;
        }
    }
}

__global__ void naive_matrxiMul(float *dev_A, float *dev_B, float *dev_C, int N) {
    float partial = 0.0;
    int row = blockIdx.y * blockDim.y + threadIdx.y;
    int col = blockIdx.x * blockDim.x + threadIdx.x;

    int k;
    if (row < N && col < N) {
        for (k = 0; k < N; k++) {
            partial += dev_A[row * N + k] * dev_B[k * N + col];
        }
        dev_C[row * N + col] = partial;
    }
}

__global__ void tiled_matrxiMul(float *dev_A, float *dev_B, float *dev_C, int N) {
    __shared__ float A_tile[BLOCK_SIZE][BLOCK_SIZE];
    __shared__ float B_tile[BLOCK_SIZE][BLOCK_SIZE];

    float partial = 0.0;
    int row = blockIdx.y * blockDim.y + threadIdx.y;
    int col = blockIdx.x * blockDim.x + threadIdx.x;

    int tx = threadIdx.x, ty = threadIdx.y;

    int m;
    for (m = 0; m < N / blockDim.x; ++m) {
        A_tile[ty][tx] = dev_A[row * N + m * blockDim.x + tx];
        B_tile[ty][tx] = dev_B[N * (m * blockDim.y + ty) + col];
        __syncthreads();
        int k;
        for (k = 0; k < blockDim.x; ++k) {
            partial += A_tile[ty][k] * B_tile[k][tx];
        }
        __syncthreads();
    }
    if (row < N && col < N) {
        dev_C[row * N + col] = partial;
    }
}

__global__ void transposed_tiled_matrxiMul(float *dev_A, float *dev_B, float *dev_C, int N) {
    __shared__ float A_tile[BLOCK_SIZE][BLOCK_SIZE];
    __shared__ float B_tile[BLOCK_SIZE][BLOCK_SIZE];

    float partial = 0.0;
    int row = blockIdx.y * blockDim.y + threadIdx.y;
    int col = blockIdx.x * blockDim.x + threadIdx.x;

    int tx = threadIdx.x, ty = threadIdx.y;

    int m;
    for (m = 0; m < N / blockDim.x; ++m) {
        A_tile[ty][tx] = dev_A[row * N + m * blockDim.x + tx];
        B_tile[tx][ty] = dev_B[N * (m * blockDim.y + ty) + col];
        __syncthreads();
        int k;
        for (k = 0; k < blockDim.x; ++k) {
            partial += A_tile[ty][k] * B_tile[tx][k];
        }
        __syncthreads();
    }
    if (row < N && col < N) {
        dev_C[row * N + col] = partial;
    }
}

void print_matrix(float *A, int N) {
    int i, j;
    for (i = 0; i < N; i++) {
        for (j = 0; j < N; j++) {
            printf("%.3f ", A[i * N + j]);
        }
        printf("\n");
    }
}

int main(int argc, char *argv[]) {
    if (argc != 3) {
        puts("Please specify the size of matrix and mode (1, 2, 3, 4)");
        return 0;
    }

    int N;
    int mode;
    N = atoi(argv[1]);
    mode = atoi(argv[2]);

    float *A, *B, *C, *CC, *dev_A, *dev_B, *dev_C;

    // allocate memory in host
    hipHostMalloc((void **) &A, N * N * sizeof(float), hipHostMallocDefault);
    hipHostMalloc((void **) &B, N * N * sizeof(float), hipHostMallocDefault);
    hipHostMalloc((void **) &C, N * N * sizeof(float), hipHostMallocDefault);
    hipHostMalloc((void **) &CC, N * N * sizeof(float), hipHostMallocDefault);

    int i, j;
    // initialize matrix A and B
    srand48(1);
    for (i = 0; i < N; i++) {
        for (j = 0; j < N; j++) {
            A[i * N + j] = drand48() * MAX_MAT_VALUE;
            B[i * N + j] = drand48() * MAX_MAT_VALUE;
        }
    }

    float gpu_time, cpu_time;
    hipEvent_t start, stop;
    hipEventCreate(&start);
    hipEventCreate(&stop);

    hipEventRecord(start, 0);

    // allocate memory on the device
    hipMalloc((void**) &dev_A, N * N * sizeof(float));
    hipMalloc((void**) &dev_B, N * N * sizeof(float));
    hipMalloc((void**) &dev_C, N * N * sizeof(float));

    hipMemcpy(dev_A, A, N * N * sizeof(float), hipMemcpyHostToDevice);
    hipMemcpy(dev_B, B, N * N * sizeof(float), hipMemcpyHostToDevice);

    dim3 Block(BLOCK_SIZE, BLOCK_SIZE);
    dim3 Grid(N / Block.x, N / Block.y);

    if (mode == 1) {
        naive_matrxiMul<<< Grid, Block>>>(dev_A, dev_B, dev_C, N);
    } else if (mode == 2) {
        tiled_matrxiMul<<< Grid, Block>>>(dev_A, dev_B, dev_C, N);
    } else if (mode == 3) {
        transposed_tiled_matrxiMul<<< Grid, Block>>>(dev_A, dev_B, dev_C, N);
    } else {
        return 0;
    }
    
    hipMemcpy(C, dev_C, N * N * sizeof(float), hipMemcpyDeviceToHost);
    hipDeviceSynchronize();
    hipEventRecord(stop, 0);
    hipEventSynchronize(stop);

    hipEventElapsedTime(&gpu_time, start, stop);
    printf("total time used on gpu matrix multiply: %f ms.\n", gpu_time);

    // start cpu matrix multiply
    hipEventRecord(start, 0);
    cpu_matrixMul(A, B, CC, N);

    hipEventRecord(stop, 0);
    hipEventSynchronize(stop);
    hipEventElapsedTime(&cpu_time, start, stop);
    printf("total time used on cpu matrix multiply: %f ms.\n", cpu_time);

    // validate result
    int all_right = 1;
    for (i = 0; i < N; ++i) {
        for (j = 0; j < N; ++j) {
            if (abs(CC[i * N + j] - C[i * N + j]) > 2) {
                printf("%3.f != %3.f\n", C[i * N + j], CC[i * N + j]);
                all_right = 0;
                break;
            }
        }
    }

    if (all_right) {
        printf("all results are right, speed up by gpu = %f.2\n", cpu_time / gpu_time);
    } else {
        printf("wrong results\n");
    }

    hipFree(dev_A);
    hipFree(dev_B);
    hipFree(dev_C);
    hipHostFree(A);
    hipHostFree(B);
    hipHostFree(C);
    hipHostFree(CC);

    return 0;
}
	.text
	.file	"jf773_hw4_1_to_3.hip"
	.globl	_Z13cpu_matrixMulPfS_S_i        # -- Begin function _Z13cpu_matrixMulPfS_S_i
	.type	_Z13cpu_matrixMulPfS_S_i,@function
_Z13cpu_matrixMulPfS_S_i:               # @_Z13cpu_matrixMulPfS_S_i
	.cfi_startproc
# %bb.0:
	testl	%ecx, %ecx
	jle	.LBB0_8
# %bb.1:                                # %.preheader26.lr.ph
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movl	%ecx, %eax
	leaq	(,%rax,4), %r8
	xorl	%r9d, %r9d
	xorl	%r10d, %r10d
.LBB0_2:                                # %.preheader.lr.ph
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB0_3 Depth 2
                                        #       Child Loop BB0_4 Depth 3
	movl	%r9d, %r11d
	leaq	(%rdi,%r11,4), %r11
	movq	%r10, %rbx
	imulq	%rax, %rbx
	leaq	(%rdx,%rbx,4), %rbx
	movq	%rsi, %r14
	xorl	%r15d, %r15d
.LBB0_3:                                # %.preheader
                                        #   Parent Loop BB0_2 Depth=1
                                        # =>  This Loop Header: Depth=2
                                        #       Child Loop BB0_4 Depth 3
	xorps	%xmm0, %xmm0
	movq	%r14, %r12
	xorl	%r13d, %r13d
.LBB0_4:                                #   Parent Loop BB0_2 Depth=1
                                        #     Parent Loop BB0_3 Depth=2
                                        # =>    This Inner Loop Header: Depth=3
	movss	(%r11,%r13,4), %xmm1            # xmm1 = mem[0],zero,zero,zero
	mulss	(%r12), %xmm1
	addss	%xmm1, %xmm0
	incq	%r13
	addq	%r8, %r12
	cmpq	%r13, %rax
	jne	.LBB0_4
# %bb.5:                                # %._crit_edge
                                        #   in Loop: Header=BB0_3 Depth=2
	movss	%xmm0, (%rbx,%r15,4)
	incq	%r15
	addq	$4, %r14
	cmpq	%rax, %r15
	jne	.LBB0_3
# %bb.6:                                # %._crit_edge30
                                        #   in Loop: Header=BB0_2 Depth=1
	incq	%r10
	addl	%ecx, %r9d
	cmpq	%rax, %r10
	jne	.LBB0_2
# %bb.7:
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	.cfi_restore %rbx
	.cfi_restore %r12
	.cfi_restore %r13
	.cfi_restore %r14
	.cfi_restore %r15
.LBB0_8:                                # %._crit_edge32
	retq
.Lfunc_end0:
	.size	_Z13cpu_matrixMulPfS_S_i, .Lfunc_end0-_Z13cpu_matrixMulPfS_S_i
	.cfi_endproc
                                        # -- End function
	.globl	_Z30__device_stub__naive_matrxiMulPfS_S_i # -- Begin function _Z30__device_stub__naive_matrxiMulPfS_S_i
	.type	_Z30__device_stub__naive_matrxiMulPfS_S_i,@function
_Z30__device_stub__naive_matrxiMulPfS_S_i: # @_Z30__device_stub__naive_matrxiMulPfS_S_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	4(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z15naive_matrxiMulPfS_S_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z30__device_stub__naive_matrxiMulPfS_S_i, .Lfunc_end1-_Z30__device_stub__naive_matrxiMulPfS_S_i
	.cfi_endproc
                                        # -- End function
	.globl	_Z30__device_stub__tiled_matrxiMulPfS_S_i # -- Begin function _Z30__device_stub__tiled_matrxiMulPfS_S_i
	.type	_Z30__device_stub__tiled_matrxiMulPfS_S_i,@function
_Z30__device_stub__tiled_matrxiMulPfS_S_i: # @_Z30__device_stub__tiled_matrxiMulPfS_S_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	4(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z15tiled_matrxiMulPfS_S_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z30__device_stub__tiled_matrxiMulPfS_S_i, .Lfunc_end2-_Z30__device_stub__tiled_matrxiMulPfS_S_i
	.cfi_endproc
                                        # -- End function
	.globl	_Z41__device_stub__transposed_tiled_matrxiMulPfS_S_i # -- Begin function _Z41__device_stub__transposed_tiled_matrxiMulPfS_S_i
	.type	_Z41__device_stub__transposed_tiled_matrxiMulPfS_S_i,@function
_Z41__device_stub__transposed_tiled_matrxiMulPfS_S_i: # @_Z41__device_stub__transposed_tiled_matrxiMulPfS_S_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	4(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z26transposed_tiled_matrxiMulPfS_S_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	_Z41__device_stub__transposed_tiled_matrxiMulPfS_S_i, .Lfunc_end3-_Z41__device_stub__transposed_tiled_matrxiMulPfS_S_i
	.cfi_endproc
                                        # -- End function
	.globl	_Z12print_matrixPfi             # -- Begin function _Z12print_matrixPfi
	.type	_Z12print_matrixPfi,@function
_Z12print_matrixPfi:                    # @_Z12print_matrixPfi
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	pushq	%rax
	.cfi_def_cfa_offset 64
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%rdi, (%rsp)                    # 8-byte Spill
	testl	%esi, %esi
	jle	.LBB4_5
# %bb.1:                                # %.preheader.lr.ph
	movl	%esi, %ebx
	movl	%esi, %r15d
	xorl	%r12d, %r12d
	xorl	%r13d, %r13d
.LBB4_2:                                # %.lr.ph
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB4_3 Depth 2
	movl	%r12d, %eax
	movq	(%rsp), %rcx                    # 8-byte Reload
	leaq	(%rcx,%rax,4), %rbp
	xorl	%r14d, %r14d
.LBB4_3:                                #   Parent Loop BB4_2 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	xorps	%xmm0, %xmm0
	cvtss2sd	(%rbp,%r14,4), %xmm0
	movl	$.L.str, %edi
	movb	$1, %al
	callq	printf
	incq	%r14
	cmpq	%r14, %r15
	jne	.LBB4_3
# %bb.4:                                # %._crit_edge
                                        #   in Loop: Header=BB4_2 Depth=1
	movl	$10, %edi
	callq	putchar@PLT
	incq	%r13
	addl	%ebx, %r12d
	cmpq	%r15, %r13
	jne	.LBB4_2
.LBB4_5:                                # %._crit_edge13
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end4:
	.size	_Z12print_matrixPfi, .Lfunc_end4-_Z12print_matrixPfi
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0                          # -- Begin function main
.LCPI5_0:
	.quad	0x4024000000000000              # double 10
	.section	.rodata.cst16,"aM",@progbits,16
	.p2align	4, 0x0
.LCPI5_1:
	.long	0x7fffffff                      # float NaN
	.long	0x7fffffff                      # float NaN
	.long	0x7fffffff                      # float NaN
	.long	0x7fffffff                      # float NaN
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0
.LCPI5_2:
	.long	0x40000000                      # float 2
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$104, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	cmpl	$3, %edi
	jne	.LBB5_1
# %bb.2:
	movq	%rsi, %r14
	movq	8(%rsi), %rdi
	callq	atoi
	movl	%eax, %ebx
	movq	16(%r14), %rdi
	callq	atoi
	movl	%eax, 88(%rsp)                  # 4-byte Spill
	movl	%ebx, %r15d
	imull	%r15d, %r15d
	shlq	$2, %r15
	leaq	64(%rsp), %rdi
	xorl	%r14d, %r14d
	movq	%r15, %rsi
	xorl	%edx, %edx
	callq	hipHostMalloc
	leaq	56(%rsp), %rdi
	movq	%r15, %rsi
	xorl	%edx, %edx
	callq	hipHostMalloc
	leaq	80(%rsp), %rdi
	movq	%r15, %rsi
	xorl	%edx, %edx
	callq	hipHostMalloc
	leaq	72(%rsp), %rdi
	movq	%r15, 96(%rsp)                  # 8-byte Spill
	movq	%r15, %rsi
	xorl	%edx, %edx
	callq	hipHostMalloc
	movl	$1, %edi
	callq	srand48
	movl	%ebx, %ebp
	testl	%ebx, %ebx
	jle	.LBB5_7
# %bb.3:                                # %.preheader107.lr.ph
	xorl	%r12d, %r12d
.LBB5_4:                                # %.lr.ph
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB5_5 Depth 2
	movl	%r14d, %r14d
	movq	%rbp, %r13
	movq	%r14, %r15
.LBB5_5:                                #   Parent Loop BB5_4 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	callq	drand48
	mulsd	.LCPI5_0(%rip), %xmm0
	cvtsd2ss	%xmm0, %xmm0
	movq	64(%rsp), %rax
	movss	%xmm0, (%rax,%r15,4)
	callq	drand48
	movsd	.LCPI5_0(%rip), %xmm1           # xmm1 = mem[0],zero
	mulsd	%xmm1, %xmm0
	cvtsd2ss	%xmm0, %xmm0
	movq	56(%rsp), %rax
	movss	%xmm0, (%rax,%r15,4)
	incq	%r15
	decq	%r13
	jne	.LBB5_5
# %bb.6:                                # %._crit_edge
                                        #   in Loop: Header=BB5_4 Depth=1
	incq	%r12
	addl	%ebx, %r14d
	cmpq	%rbp, %r12
	jne	.LBB5_4
.LBB5_7:                                # %._crit_edge112
	leaq	32(%rsp), %r15
	movq	%r15, %rdi
	callq	hipEventCreate
	leaq	8(%rsp), %rdi
	callq	hipEventCreate
	movq	(%r15), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	leaq	48(%rsp), %r15
	movq	%r15, %rdi
	movq	96(%rsp), %r14                  # 8-byte Reload
	movq	%r14, %rsi
	callq	hipMalloc
	leaq	40(%rsp), %r12
	movq	%r12, %rdi
	movq	%r14, %rsi
	callq	hipMalloc
	leaq	16(%rsp), %rdi
	movq	%r14, %rsi
	callq	hipMalloc
	movq	(%r15), %rdi
	movq	64(%rsp), %rsi
	movq	%r14, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%r12), %rdi
	movq	56(%rsp), %rsi
	movq	%r14, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	movl	%ebx, %eax
	shrl	$4, %eax
	movq	%rax, %rdi
	shlq	$32, %rdi
	orq	%rax, %rdi
	movl	88(%rsp), %eax                  # 4-byte Reload
	cmpl	$3, %eax
	je	.LBB5_14
# %bb.8:                                # %._crit_edge112
	cmpl	$2, %eax
	je	.LBB5_12
# %bb.9:                                # %._crit_edge112
	cmpl	$1, %eax
	jne	.LBB5_36
# %bb.10:
	movabsq	$68719476752, %rdx              # imm = 0x1000000010
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB5_16
# %bb.11:
	movq	48(%rsp), %rdi
	movq	40(%rsp), %rsi
	movq	16(%rsp), %rdx
	movl	%ebx, %ecx
	callq	_Z30__device_stub__naive_matrxiMulPfS_S_i
	jmp	.LBB5_16
.LBB5_1:
	movl	$.L.str.2, %edi
	callq	puts
	jmp	.LBB5_36
.LBB5_12:
	movabsq	$68719476752, %rdx              # imm = 0x1000000010
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB5_16
# %bb.13:
	movq	48(%rsp), %rdi
	movq	40(%rsp), %rsi
	movq	16(%rsp), %rdx
	movl	%ebx, %ecx
	callq	_Z30__device_stub__tiled_matrxiMulPfS_S_i
	jmp	.LBB5_16
.LBB5_14:
	movabsq	$68719476752, %rdx              # imm = 0x1000000010
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB5_16
# %bb.15:
	movq	48(%rsp), %rdi
	movq	40(%rsp), %rsi
	movq	16(%rsp), %rdx
	movl	%ebx, %ecx
	callq	_Z41__device_stub__transposed_tiled_matrxiMulPfS_S_i
.LBB5_16:
	movq	80(%rsp), %rdi
	movq	16(%rsp), %rsi
	movq	%r14, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	callq	hipDeviceSynchronize
	movq	8(%rsp), %rdi
	xorl	%r15d, %r15d
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	8(%rsp), %rdi
	callq	hipEventSynchronize
	movq	32(%rsp), %rsi
	movq	8(%rsp), %rdx
	leaq	92(%rsp), %r14
	movq	%r14, %rdi
	callq	hipEventElapsedTime
	cvtss2sd	(%r14), %xmm0
	movl	$.L.str.3, %edi
	movb	$1, %al
	callq	printf
	movq	32(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	testl	%ebx, %ebx
	jle	.LBB5_33
# %bb.17:                               # %.preheader26.lr.ph.i
	movq	64(%rsp), %rax
	movq	56(%rsp), %rcx
	movq	72(%rsp), %rdx
	leaq	(,%rbp,4), %rsi
	xorl	%edi, %edi
.LBB5_18:                               # %.preheader.lr.ph.i
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB5_19 Depth 2
                                        #       Child Loop BB5_20 Depth 3
	movl	%r15d, %r8d
	leaq	(%rax,%r8,4), %r8
	movq	%rdi, %r9
	imulq	%rbp, %r9
	leaq	(%rdx,%r9,4), %r9
	movq	%rcx, %r10
	xorl	%r11d, %r11d
.LBB5_19:                               # %.preheader.i
                                        #   Parent Loop BB5_18 Depth=1
                                        # =>  This Loop Header: Depth=2
                                        #       Child Loop BB5_20 Depth 3
	xorps	%xmm0, %xmm0
	movq	%r10, %r14
	xorl	%r12d, %r12d
.LBB5_20:                               #   Parent Loop BB5_18 Depth=1
                                        #     Parent Loop BB5_19 Depth=2
                                        # =>    This Inner Loop Header: Depth=3
	movss	(%r8,%r12), %xmm1               # xmm1 = mem[0],zero,zero,zero
	mulss	(%r14), %xmm1
	addss	%xmm1, %xmm0
	addq	$4, %r12
	addq	%rsi, %r14
	cmpq	%r12, %rsi
	jne	.LBB5_20
# %bb.21:                               # %._crit_edge.i
                                        #   in Loop: Header=BB5_19 Depth=2
	movss	%xmm0, (%r9,%r11,4)
	incq	%r11
	addq	$4, %r10
	cmpq	%rbp, %r11
	jne	.LBB5_19
# %bb.22:                               # %._crit_edge30.i
                                        #   in Loop: Header=BB5_18 Depth=1
	incq	%rdi
	addl	%ebx, %r15d
	cmpq	%rbp, %rdi
	jne	.LBB5_18
# %bb.23:                               # %_Z13cpu_matrixMulPfS_S_i.exit
	movq	8(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	8(%rsp), %rdi
	callq	hipEventSynchronize
	movq	32(%rsp), %rsi
	movq	8(%rsp), %rdx
	leaq	28(%rsp), %r14
	movq	%r14, %rdi
	callq	hipEventElapsedTime
	xorps	%xmm0, %xmm0
	cvtss2sd	(%r14), %xmm0
	movl	$.L.str.4, %edi
	movb	$1, %al
	callq	printf
	testl	%ebx, %ebx
	jle	.LBB5_34
# %bb.24:                               # %.preheader.lr.ph
	leaq	(,%rbp,4), %rbx
	xorl	%r14d, %r14d
	movaps	.LCPI5_1(%rip), %xmm3           # xmm3 = [NaN,NaN,NaN,NaN]
	movss	.LCPI5_2(%rip), %xmm4           # xmm4 = mem[0],zero,zero,zero
	xorl	%eax, %eax
.LBB5_25:                               # %.lr.ph114.outer
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB5_26 Depth 2
                                        #       Child Loop BB5_28 Depth 3
	movq	%rbx, %rcx
	imulq	%r14, %rcx
	movq	72(%rsp), %rdx
	addq	%rcx, %rdx
	addq	80(%rsp), %rcx
.LBB5_26:                               # %.lr.ph114
                                        #   Parent Loop BB5_25 Depth=1
                                        # =>  This Loop Header: Depth=2
                                        #       Child Loop BB5_28 Depth 3
	xorl	%esi, %esi
.LBB5_28:                               #   Parent Loop BB5_25 Depth=1
                                        #     Parent Loop BB5_26 Depth=2
                                        # =>    This Inner Loop Header: Depth=3
	movss	(%rdx,%rsi,4), %xmm1            # xmm1 = mem[0],zero,zero,zero
	movss	(%rcx,%rsi,4), %xmm0            # xmm0 = mem[0],zero,zero,zero
	movaps	%xmm1, %xmm2
	subss	%xmm0, %xmm2
	andps	%xmm3, %xmm2
	ucomiss	%xmm4, %xmm2
	ja	.LBB5_29
# %bb.27:                               #   in Loop: Header=BB5_28 Depth=3
	incq	%rsi
	cmpq	%rsi, %rbp
	jne	.LBB5_28
# %bb.30:                               # %.loopexit
                                        #   in Loop: Header=BB5_26 Depth=2
	incq	%r14
	addq	%rbx, %rdx
	addq	%rbx, %rcx
	cmpq	%rbp, %r14
	jne	.LBB5_26
	jmp	.LBB5_31
.LBB5_29:                               # %.loopexit.thread
                                        #   in Loop: Header=BB5_25 Depth=1
	cvtss2sd	%xmm0, %xmm0
	cvtss2sd	%xmm1, %xmm1
	movl	$.L.str.5, %edi
	movb	$2, %al
	callq	printf
	movss	.LCPI5_2(%rip), %xmm4           # xmm4 = mem[0],zero,zero,zero
	movaps	.LCPI5_1(%rip), %xmm3           # xmm3 = [NaN,NaN,NaN,NaN]
	incq	%r14
	movb	$1, %al
	cmpq	%rbp, %r14
	jne	.LBB5_25
	jmp	.LBB5_32
.LBB5_33:                               # %._crit_edge118.thread.critedge
	movq	8(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	8(%rsp), %rdi
	callq	hipEventSynchronize
	movq	32(%rsp), %rsi
	movq	8(%rsp), %rdx
	leaq	28(%rsp), %rbx
	movq	%rbx, %rdi
	callq	hipEventElapsedTime
	xorps	%xmm0, %xmm0
	cvtss2sd	(%rbx), %xmm0
	movl	$.L.str.4, %edi
	movb	$1, %al
	callq	printf
	jmp	.LBB5_34
.LBB5_31:                               # %._crit_edge118
	testb	$1, %al
	je	.LBB5_34
.LBB5_32:                               # %._crit_edge118.thread144
	movl	$.Lstr, %edi
	callq	puts
	jmp	.LBB5_35
.LBB5_34:                               # %._crit_edge118.thread
	movss	28(%rsp), %xmm0                 # xmm0 = mem[0],zero,zero,zero
	divss	92(%rsp), %xmm0
	cvtss2sd	%xmm0, %xmm0
	movl	$.L.str.6, %edi
	movb	$1, %al
	callq	printf
.LBB5_35:
	movq	48(%rsp), %rdi
	callq	hipFree
	movq	40(%rsp), %rdi
	callq	hipFree
	movq	16(%rsp), %rdi
	callq	hipFree
	movq	64(%rsp), %rdi
	callq	hipHostFree
	movq	56(%rsp), %rdi
	callq	hipHostFree
	movq	80(%rsp), %rdi
	callq	hipHostFree
	movq	72(%rsp), %rdi
	callq	hipHostFree
.LBB5_36:
	xorl	%eax, %eax
	addq	$104, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end5:
	.size	main, .Lfunc_end5-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB6_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB6_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z15naive_matrxiMulPfS_S_i, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z15tiled_matrxiMulPfS_S_i, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z26transposed_tiled_matrxiMulPfS_S_i, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end6:
	.size	__hip_module_ctor, .Lfunc_end6-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB7_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB7_2:
	retq
.Lfunc_end7:
	.size	__hip_module_dtor, .Lfunc_end7-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z15naive_matrxiMulPfS_S_i,@object # @_Z15naive_matrxiMulPfS_S_i
	.section	.rodata,"a",@progbits
	.globl	_Z15naive_matrxiMulPfS_S_i
	.p2align	3, 0x0
_Z15naive_matrxiMulPfS_S_i:
	.quad	_Z30__device_stub__naive_matrxiMulPfS_S_i
	.size	_Z15naive_matrxiMulPfS_S_i, 8

	.type	_Z15tiled_matrxiMulPfS_S_i,@object # @_Z15tiled_matrxiMulPfS_S_i
	.globl	_Z15tiled_matrxiMulPfS_S_i
	.p2align	3, 0x0
_Z15tiled_matrxiMulPfS_S_i:
	.quad	_Z30__device_stub__tiled_matrxiMulPfS_S_i
	.size	_Z15tiled_matrxiMulPfS_S_i, 8

	.type	_Z26transposed_tiled_matrxiMulPfS_S_i,@object # @_Z26transposed_tiled_matrxiMulPfS_S_i
	.globl	_Z26transposed_tiled_matrxiMulPfS_S_i
	.p2align	3, 0x0
_Z26transposed_tiled_matrxiMulPfS_S_i:
	.quad	_Z41__device_stub__transposed_tiled_matrxiMulPfS_S_i
	.size	_Z26transposed_tiled_matrxiMulPfS_S_i, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"%.3f "
	.size	.L.str, 6

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"Please specify the size of matrix and mode (1, 2, 3, 4)"
	.size	.L.str.2, 56

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"total time used on gpu matrix multiply: %f ms.\n"
	.size	.L.str.3, 48

	.type	.L.str.4,@object                # @.str.4
.L.str.4:
	.asciz	"total time used on cpu matrix multiply: %f ms.\n"
	.size	.L.str.4, 48

	.type	.L.str.5,@object                # @.str.5
.L.str.5:
	.asciz	"%3.f != %3.f\n"
	.size	.L.str.5, 14

	.type	.L.str.6,@object                # @.str.6
.L.str.6:
	.asciz	"all results are right, speed up by gpu = %f.2\n"
	.size	.L.str.6, 47

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z15naive_matrxiMulPfS_S_i"
	.size	.L__unnamed_1, 27

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z15tiled_matrxiMulPfS_S_i"
	.size	.L__unnamed_2, 27

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z26transposed_tiled_matrxiMulPfS_S_i"
	.size	.L__unnamed_3, 38

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.type	.Lstr,@object                   # @str
	.section	.rodata.str1.1,"aMS",@progbits,1
.Lstr:
	.asciz	"wrong results"
	.size	.Lstr, 14

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z30__device_stub__naive_matrxiMulPfS_S_i
	.addrsig_sym _Z30__device_stub__tiled_matrxiMulPfS_S_i
	.addrsig_sym _Z41__device_stub__transposed_tiled_matrxiMulPfS_S_i
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z15naive_matrxiMulPfS_S_i
	.addrsig_sym _Z15tiled_matrxiMulPfS_S_i
	.addrsig_sym _Z26transposed_tiled_matrxiMulPfS_S_i
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z15naive_matrxiMulPfS_S_i ; -- Begin function _Z15naive_matrxiMulPfS_S_i
	.globl	_Z15naive_matrxiMulPfS_S_i
	.p2align	8
	.type	_Z15naive_matrxiMulPfS_S_i,@function
_Z15naive_matrxiMulPfS_S_i:             ; @_Z15naive_matrxiMulPfS_S_i
; %bb.0:
	s_clause 0x1
	s_load_b32 s3, s[0:1], 0x2c
	s_load_b32 s2, s[0:1], 0x18
	v_bfe_u32 v1, v0, 10, 10
	v_and_b32_e32 v4, 0x3ff, v0
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s4, s3, 16
	s_and_b32 s3, s3, 0xffff
	v_mad_u64_u32 v[2:3], null, s15, s4, v[1:2]
	v_mad_u64_u32 v[0:1], null, s14, s3, v[4:5]
	s_mov_b32 s3, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_max_i32_e32 v1, v2, v0
	v_cmpx_gt_i32_e64 s2, v1
	s_cbranch_execz .LBB0_6
; %bb.1:                                ; %.preheader
	s_clause 0x1
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b64 s[0:1], s[0:1], 0x10
	v_mul_lo_u32 v1, v2, s2
	s_cmp_lt_i32 s2, 1
	s_cbranch_scc1 .LBB0_4
; %bb.2:                                ; %.lr.ph.preheader
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_ashrrev_i32_e32 v2, 31, v1
	v_mov_b32_e32 v6, 0
	v_mov_b32_e32 v4, v0
	s_mov_b32 s3, s2
	v_lshlrev_b64 v[2:3], 2, v[1:2]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s4, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
.LBB0_3:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	v_ashrrev_i32_e32 v5, 31, v4
	s_add_i32 s3, s3, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_cmp_lg_u32 s3, 0
	v_lshlrev_b64 v[7:8], 2, v[4:5]
	v_add_nc_u32_e32 v4, s2, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v7, vcc_lo, s6, v7
	v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
	global_load_b32 v5, v[2:3], off
	global_load_b32 v7, v[7:8], off
	v_add_co_u32 v2, vcc_lo, v2, 4
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v6, v5, v7
	s_cbranch_scc1 .LBB0_3
	s_branch .LBB0_5
.LBB0_4:
	v_mov_b32_e32 v6, 0
.LBB0_5:                                ; %._crit_edge
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v0, v1, v0
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v0, vcc_lo, s0, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	global_store_b32 v[0:1], v6, off
.LBB0_6:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z15naive_matrxiMulPfS_S_i
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 9
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z15naive_matrxiMulPfS_S_i, .Lfunc_end0-_Z15naive_matrxiMulPfS_S_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 332
; NumSgprs: 18
; NumVgprs: 9
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 9
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z15tiled_matrxiMulPfS_S_i ; -- Begin function _Z15tiled_matrxiMulPfS_S_i
	.globl	_Z15tiled_matrxiMulPfS_S_i
	.p2align	8
	.type	_Z15tiled_matrxiMulPfS_S_i,@function
_Z15tiled_matrxiMulPfS_S_i:             ; @_Z15tiled_matrxiMulPfS_S_i
; %bb.0:
	s_clause 0x3
	s_load_b32 s8, s[0:1], 0x2c
	s_load_b32 s2, s[0:1], 0x18
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b64 s[0:1], s[0:1], 0x10
	v_bfe_u32 v3, v0, 10, 10
	v_and_b32_e32 v6, 0x3ff, v0
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s8, 16
	s_and_b32 s8, s8, 0xffff
	v_mad_u64_u32 v[0:1], null, s15, s3, v[3:4]
	v_mad_u64_u32 v[1:2], null, s14, s8, v[6:7]
	v_mov_b32_e32 v2, 0
	s_cmp_gt_u32 s8, s2
	s_cbranch_scc1 .LBB1_5
; %bb.1:                                ; %.lr.ph
	v_cvt_f32_u32_e32 v2, s8
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[4:5], null, v0, s2, v[6:7]
	s_sub_i32 s10, 0, s8
	v_lshlrev_b32_e32 v8, 2, v6
	v_rcp_iflag_f32_e32 v2, v2
	v_dual_mov_b32 v6, 0 :: v_dual_lshlrev_b32 v5, 6, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v7, v5, v8
	v_add_nc_u32_e32 v8, 0x400, v8
	s_waitcnt_depctr 0xfff
	v_dual_mul_f32 v2, 0x4f7ffffe, v2 :: v_dual_add_nc_u32 v9, v8, v5
	v_cvt_u32_f32_e32 v2, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s9, v2
	v_mov_b32_e32 v2, 0
	s_mul_i32 s10, s10, s9
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_hi_u32 s10, s9, s10
	s_add_i32 s9, s9, s10
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_hi_u32 s9, s2, s9
	s_mul_i32 s10, s9, s8
	s_add_i32 s11, s9, 1
	s_sub_i32 s10, s2, s10
	s_delay_alu instid0(SALU_CYCLE_1)
	s_sub_i32 s12, s10, s8
	s_cmp_ge_u32 s10, s8
	s_cselect_b32 s11, s11, s9
	s_cselect_b32 s9, s12, s10
	s_add_i32 s10, s11, 1
	s_cmp_ge_u32 s9, s8
	s_mov_b32 s9, 0
	s_cselect_b32 s10, s10, s11
	s_max_u32 s11, s8, 1
.LBB1_2:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB1_3 Depth 2
	v_mad_u64_u32 v[10:11], null, s9, s3, v[3:4]
	v_mad_u64_u32 v[11:12], null, s9, s8, v[4:5]
	v_mov_b32_e32 v12, v6
	s_mov_b32 s12, s11
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[13:14], null, v10, s2, v[1:2]
	v_mov_b32_e32 v14, v6
	v_lshlrev_b64 v[10:11], 2, v[11:12]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[12:13], 2, v[13:14]
	v_add_co_u32 v10, vcc_lo, s4, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v11, vcc_lo, s5, v11, vcc_lo
	v_add_co_u32 v12, vcc_lo, s6, v12
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v13, vcc_lo, s7, v13, vcc_lo
	global_load_b32 v14, v[10:11], off
	global_load_b32 v12, v[12:13], off
	v_dual_mov_b32 v11, v5 :: v_dual_mov_b32 v10, v8
	s_waitcnt vmcnt(1)
	ds_store_b32 v7, v14
	s_waitcnt vmcnt(0)
	ds_store_b32 v9, v12
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
.LBB1_3:                                ;   Parent Loop BB1_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	ds_load_b32 v12, v11
	ds_load_b32 v13, v10
	v_add_nc_u32_e32 v11, 4, v11
	v_add_nc_u32_e32 v10, 64, v10
	s_add_i32 s12, s12, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u32 s12, 0
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v2, v12, v13
	s_cbranch_scc1 .LBB1_3
; %bb.4:                                ;   in Loop: Header=BB1_2 Depth=1
	s_add_i32 s9, s9, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lt_u32 s9, s10
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB1_2
.LBB1_5:                                ; %._crit_edge
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_max_i32_e32 v3, v0, v1
	s_mov_b32 s3, exec_lo
	v_cmpx_gt_i32_e64 s2, v3
	s_cbranch_execz .LBB1_7
; %bb.6:
	v_mad_u64_u32 v[3:4], null, v0, s2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v4, 31, v3
	v_lshlrev_b64 v[0:1], 2, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	global_store_b32 v[0:1], v2, off
.LBB1_7:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z15tiled_matrxiMulPfS_S_i
		.amdhsa_group_segment_fixed_size 2048
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 15
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z15tiled_matrxiMulPfS_S_i, .Lfunc_end1-_Z15tiled_matrxiMulPfS_S_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 572
; NumSgprs: 18
; NumVgprs: 15
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 2048 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 15
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z26transposed_tiled_matrxiMulPfS_S_i ; -- Begin function _Z26transposed_tiled_matrxiMulPfS_S_i
	.globl	_Z26transposed_tiled_matrxiMulPfS_S_i
	.p2align	8
	.type	_Z26transposed_tiled_matrxiMulPfS_S_i,@function
_Z26transposed_tiled_matrxiMulPfS_S_i:  ; @_Z26transposed_tiled_matrxiMulPfS_S_i
; %bb.0:
	s_clause 0x3
	s_load_b32 s8, s[0:1], 0x2c
	s_load_b32 s2, s[0:1], 0x18
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b64 s[0:1], s[0:1], 0x10
	v_bfe_u32 v3, v0, 10, 10
	v_and_b32_e32 v6, 0x3ff, v0
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s8, 16
	s_and_b32 s8, s8, 0xffff
	v_mad_u64_u32 v[0:1], null, s15, s3, v[3:4]
	v_mad_u64_u32 v[1:2], null, s14, s8, v[6:7]
	v_mov_b32_e32 v2, 0
	s_cmp_gt_u32 s8, s2
	s_cbranch_scc1 .LBB2_5
; %bb.1:                                ; %.lr.ph
	v_cvt_f32_u32_e32 v2, s8
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[4:5], null, v0, s2, v[6:7]
	s_sub_i32 s10, 0, s8
	v_lshl_add_u32 v7, v6, 6, 0x400
	v_rcp_iflag_f32_e32 v2, v2
	v_dual_mov_b32 v8, 0 :: v_dual_lshlrev_b32 v5, 6, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshl_add_u32 v9, v3, 2, v7
	v_lshl_add_u32 v6, v6, 2, v5
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v2, 0x4f7ffffe, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v2, v2
	v_readfirstlane_b32 s9, v2
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s10, s10, s9
	s_mul_hi_u32 s10, s9, s10
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s9, s9, s10
	s_mul_hi_u32 s9, s2, s9
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_mul_i32 s10, s9, s8
	s_add_i32 s11, s9, 1
	s_sub_i32 s10, s2, s10
	s_sub_i32 s12, s10, s8
	s_cmp_ge_u32 s10, s8
	s_cselect_b32 s11, s11, s9
	s_cselect_b32 s9, s12, s10
	s_add_i32 s10, s11, 1
	s_cmp_ge_u32 s9, s8
	s_mov_b32 s9, 0
	s_cselect_b32 s10, s10, s11
	s_max_u32 s11, s8, 1
.LBB2_2:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB2_3 Depth 2
	v_mad_u64_u32 v[10:11], null, s9, s3, v[3:4]
	v_mad_u64_u32 v[11:12], null, s9, s8, v[4:5]
	v_mov_b32_e32 v12, v8
	s_mov_b32 s12, s11
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[13:14], null, v10, s2, v[1:2]
	v_mov_b32_e32 v14, v8
	v_lshlrev_b64 v[10:11], 2, v[11:12]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[12:13], 2, v[13:14]
	v_add_co_u32 v10, vcc_lo, s4, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v11, vcc_lo, s5, v11, vcc_lo
	v_add_co_u32 v12, vcc_lo, s6, v12
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v13, vcc_lo, s7, v13, vcc_lo
	global_load_b32 v14, v[10:11], off
	global_load_b32 v12, v[12:13], off
	v_dual_mov_b32 v11, v5 :: v_dual_mov_b32 v10, v7
	s_waitcnt vmcnt(1)
	ds_store_b32 v6, v14
	s_waitcnt vmcnt(0)
	ds_store_b32 v9, v12
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
.LBB2_3:                                ;   Parent Loop BB2_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	ds_load_b32 v12, v11
	ds_load_b32 v13, v10
	v_add_nc_u32_e32 v11, 4, v11
	v_add_nc_u32_e32 v10, 4, v10
	s_add_i32 s12, s12, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u32 s12, 0
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v2, v12, v13
	s_cbranch_scc1 .LBB2_3
; %bb.4:                                ;   in Loop: Header=BB2_2 Depth=1
	s_add_i32 s9, s9, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lt_u32 s9, s10
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB2_2
.LBB2_5:                                ; %._crit_edge
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_max_i32_e32 v3, v0, v1
	s_mov_b32 s3, exec_lo
	v_cmpx_gt_i32_e64 s2, v3
	s_cbranch_execz .LBB2_7
; %bb.6:
	v_mad_u64_u32 v[3:4], null, v0, s2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v4, 31, v3
	v_lshlrev_b64 v[0:1], 2, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	global_store_b32 v[0:1], v2, off
.LBB2_7:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z26transposed_tiled_matrxiMulPfS_S_i
		.amdhsa_group_segment_fixed_size 2048
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 15
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_Z26transposed_tiled_matrxiMulPfS_S_i, .Lfunc_end2-_Z26transposed_tiled_matrxiMulPfS_S_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 580
; NumSgprs: 18
; NumVgprs: 15
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 2048 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 15
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
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amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
