/*******************************************************************************
 * serveral useful gpu functions will be defined in this file to facilitate
 * the extension scheme 
 ******************************************************************************/

typedef struct
{
	double sR;
	double sL;
} double_eno_derivative;

__device__ inline
double max2(double x, double y)
{
	return (x<y) ? y : x;
}

__device__ inline
double min2(double x, double y)
{
	return (x<y) ? x : y;
}

__device__ inline
double min_mod(double x, double y)
{
	return (x*y<0) ? 0.0 : (fabs(x)<fabs(y) ? x : y);
}

__device__ inline
double min_abs(double x, double y)
{
	return (fabs(x)<fabs(y)) ? x : y;
}

__device__ inline
double sign(double x)
{
	return (x>0) ? 1.0 : -1.0;
}


// convert subindex to linear index
// periodic boundary conditions are assumed
__device__ inline
int sub2ind(int row_idx, int col_idx, int pge_idx, int rows, int cols, int pges)
{	
	int row_idxn = min2(rows-1, max2(0, row_idx));
	int col_idxn = min2(cols-1, max2(0, col_idx));
	int pge_idxn = min2(pges-1, max2(0, pge_idx));

	int ind = pge_idxn * rows * cols + col_idxn * rows + row_idxn;

	return ind;
}

__device__ inline
double weno_onesided_derivative(double v1, double v2, double v3, double v4, double v5)
{
	// different choices of ENO derivatives
	double phi1 = 1./3. * v1 	- 7./6. * v2 	+ 11./6. * v3;
	double phi2 = -1./6. * v2 	+ 5./6. * v3 	+ 1./3. * v4;
	double phi3 = 1./3. * v3	+ 5./6. * v4	- 1./6. * v5;

	// smoothness parameter
	double S1 = 13./12. * pow((v1 - 2*v2 + v3),2) + 1./4. * pow((v1 - 4*v2 + 3*v3),2);
	double S2 = 13./12. * pow((v2 - 2*v3 + v4),2) + 1./4. * pow((v2 - v4),2);
	double S3 = 13./12. * pow((v3 - 2*v4 + v5),2) + 1./4. * pow((3*v3 - 4*v4 + v5),2);

	double epsilon = 1e-6;
	double alpha1 = 0.1 / pow( (S1 + epsilon), 2);
	double alpha2 = 0.6 / pow( (S2 + epsilon), 2);
	double alpha3 = 0.3 / pow( (S3 + epsilon), 2);

	// weights for each stencil
	double sum = alpha1 + alpha2 + alpha3;
	double omega1 = alpha1 / sum;
	double omega2 = alpha2 / sum;
	double omega3 = alpha3 / sum;

	return (omega1*phi1 + omega2*phi2 + omega3*phi3);

}

// given a stencil across the boundary: p1<-l3-p2<-l2-p3<-l1-p4-r1->p5-r2->p6-r3->p7
// create a new stencil (x3m,h3m),(x2m,h2m),(x1m,h1m),(x0,h0),(x1,h1),(x2,h2),(x3,h3) including boundary nodes
__device__ inline
void select_stencil(double & h3m, double & h2m, double & h1m, double & h0, double & h1, double & h2, double & h3, double & x3m, double & x2m, double & x1m, double & x0, double & x1, double & x2, double & x3, double p1, double p2, double p3, double p4, double p5, double p6, double p7, double r1, double r2, double r3, double l1, double l2, double l3, double ds, double h_fore, double h_back)
{
		h0 = p4; x0 = 0.0;

		if(r1<ds){
			x1 = r1;
			x2 = ds;
			x3 = 2*ds;
			h1 = h_fore;
			h2 = p5;
			h3 = p6;
		}else{
			x1 = ds;
			x2 = 2*ds;
			x3 = 3*ds;
			h1 = p5;
			h2 = p6;
			h3 = p7;
		}

		if(l1<ds){
			x1m = -l1;
			x2m = - ds;
			x3m = - 2*ds;
			h1m = h_back;
			h2m = p3;
			h3m = p2;
		}else{
			x1m = -ds;
			x2m = - 2*ds;
			x3m = - 3*ds;
			h1m = p3;
			h2m = p2;
			h3m = p1;
		}
}

// for stencil (x3m,h3m),(x2m,h2m),(x1m,h1m),(x0,h0),(x1,h1),(x2,h2),(x3,h3) including boundary nodes
// calculate cubic eno derivatives at (x0,h0)
// note that this is a nonuniform stencil
__device__ inline
void ENO_cubic_derivative(double & d_fore, double & d_back, double h3m, double h2m, double h1m, double h0, double h1, double h2, double h3, double x3m, double x2m, double x1m, double x0, double x1, double x2, double x3)
{

	// divided differences
	double d1_2_5   = (h3  - h2)  / (x3  - x2) ;
	double d1_1_5   = (h2  - h1)  / (x2  - x1) ;
	double d1_0_5   = (h1  - h0)  / (x1  - x0) ;
	double d1_m0_5  = (h0  - h1m) / (x0  - x1m);
	double d1_m1_5  = (h1m - h2m) / (x1m - x2m);
	double d1_m2_5  = (h2m - h3m) / (x2m - x3m);

	double d2_2  = (d1_2_5  - d1_1_5)  / (x3  - x1) ;
	double d2_1  = (d1_1_5  - d1_0_5)  / (x2  - x0) ;
	double d2_0  = (d1_0_5  - d1_m0_5) / (x1  - x1m);
	double d2_m1 = (d1_m0_5 - d1_m1_5) / (x0  - x2m);
	double d2_m2 = (d1_m1_5 - d1_m2_5) / (x1m - x3m);

	double d3_1_5  = (d2_2  - d2_1)  / (x3 - x0) ;
	double d3_0_5  = (d2_1  - d2_0)  / (x2 - x1m);
	double d3_m0_5 = (d2_0  - d2_m1) / (x1 - x2m);
	double d3_m1_5 = (d2_m1 - d2_m2) / (x0 - x3m);

	double a1 = (x0 - x1m) * (x0 - x2m) * min_abs(d3_m0_5, d3_m1_5);
	double a2 = (x0 - x1m) * (x0 - x1)  * min_abs(d3_m0_5, d3_0_5);
	double a = (fabs(d2_m1) < fabs(d2_0)) ? a1 : a2;

	double b1 = (x0 - x1m) * (x0 - x1) * min_abs(d3_m0_5, d3_0_5);
	double b2 = (x0 - x1)  * (x0 - x2) * min_abs(d3_0_5,  d3_1_5);
	double b = (fabs(d2_0) < fabs(d2_1)) ? b1 : b2;

	d_back = d1_m0_5 + min_mod(d2_m1,d2_0) * (x0 - x1m) + a;
	d_fore = d1_0_5  + min_mod(d2_0, d2_1) * (x0 - x1)  + b;
}

// calculate weno derivative at p4: p1<-l3-p2<-l2-p3<-l1-p4-r1->p5-r2->p6-r3->p7
// where px are level set function values at node x
// lx, rx are distance to the left/right node 
__device__ inline
void weno_derivative_boundary(double & d_fore, double & d_back, double p1, double p2, double p3, double p4, double p5, double p6, double p7, double r1, double r2, double r3, double l1, double l2, double l3, double ds, double v_fore, double v_back)
{
	// the condistion below is better than p3*p4<0 || p4*p5<0 
	bool cross_interface = r1<ds || l1<ds;

	if(!cross_interface){
		double v1 = (p2 - p1) / ds;
		double v2 = (p3 - p2) / ds;
		double v3 = (p4 - p3) / ds;
		double v4 = (p5 - p4) / ds;
		double v5 = (p6 - p5) / ds;
		double v6 = (p7 - p6) / ds;
		d_back = weno_onesided_derivative(v1,v2,v3,v4,v5);
		d_fore = weno_onesided_derivative(v6,v5,v4,v3,v2);
	}// if not a node IMMEDIATELY adjacent to the boundary, calculate weno derivatives as usual
	else{
		double h3m,h2m,h1m,h0,h1,h2,h3;
		double x3m,x2m,x1m,x0,x1,x2,x3;
		select_stencil(h3m,h2m,h1m,h0,h1,h2,h3,x3m,x2m,x1m,x0,x1,x2,x3,p1,p2,p3,p4,p5,p6,p7,r1,r2,r3,l1,l2,l3,ds,v_fore,v_back);
		ENO_cubic_derivative(d_fore,d_back,h3m,h2m,h1m,h0,h1,h2,h3,x3m,x2m,x1m,x0,x1,x2,x3);
	}// for nodes IMMEDIATELY adjacent to the boundary, use cubic ENO interpolant
}

__device__ inline
double upwind_normal_point(double p1, double p2, double p3, double p4, double p5, double p6, double p7, double r1, double r2, double r3, double l1, double l2, double l3, double ds)
{
	double d_back, d_fore;
	weno_derivative_boundary(d_fore,d_back,p1,p2,p3,p4,p5,p6,p7,r1,r2,r3,l1,l2,l3,ds,0.0,0.0);

	return (fabs(p5)<fabs(p3)) ? d_fore : d_back;
}

// calculate the upwind normal
__global__
void upwind_normal(double * nx, double * ny, double * nz, double const * lsf, double const * xpr, double const * xpl, double const * ypf, double const * ypb, double const * zpu, double const * zpd, int rows, int cols, int pges, double dx, double dy, double dz, int num_ele)
{
	int row_idx = blockIdx.x * blockDim.x + threadIdx.x;
	int col_idx = blockIdx.y * blockDim.y + threadIdx.y;
	int pge_idx = blockIdx.z * blockDim.z + threadIdx.z;

	if(row_idx >= rows || col_idx >= cols || pge_idx >= pges){
		return;
	}

	int ind = sub2ind(row_idx, col_idx, pge_idx, rows, cols, pges);

	double p1,p2,p3,p4,p5,p6,p7;
	double r1,r2,r3,l1,l2,l3;

	p4 = lsf[ind];

	int rght1 	= sub2ind(row_idx, col_idx+1, pge_idx, rows, cols, pges);
	int rght2 	= sub2ind(row_idx, col_idx+2, pge_idx, rows, cols, pges);
	int rght3 	= sub2ind(row_idx, col_idx+3, pge_idx, rows, cols, pges);
	int left1 	= sub2ind(row_idx, col_idx-1, pge_idx, rows, cols, pges);
	int left2 	= sub2ind(row_idx, col_idx-2, pge_idx, rows, cols, pges);
	int left3 	= sub2ind(row_idx, col_idx-3, pge_idx, rows, cols, pges);

	p1 = lsf[left3];
	p2 = lsf[left2];
	p3 = lsf[left1];
	p5 = lsf[rght1];
	p6 = lsf[rght2];
	p7 = lsf[rght3];

	r1 = xpr[ind];
	r2 = xpr[rght1];
	r3 = xpr[rght2];

	l1 = xpl[ind];
	l2 = xpl[left1];
	l3 = xpl[left2];

	nx[ind] = upwind_normal_point(p1,p2,p3,p4,p5,p6,p7,r1,r2,r3,l1,l2,l3,dx);

	int frnt1 	= sub2ind(row_idx+1, col_idx, pge_idx, rows, cols, pges);	
	int frnt2 	= sub2ind(row_idx+2, col_idx, pge_idx, rows, cols, pges);	
	int frnt3 	= sub2ind(row_idx+3, col_idx, pge_idx, rows, cols, pges);	
	int back1 	= sub2ind(row_idx-1, col_idx, pge_idx, rows, cols, pges);
	int back2 	= sub2ind(row_idx-2, col_idx, pge_idx, rows, cols, pges);
	int back3 	= sub2ind(row_idx-3, col_idx, pge_idx, rows, cols, pges);

	p1 = lsf[back3];
	p2 = lsf[back2];
	p3 = lsf[back1];
	p5 = lsf[frnt1];
	p6 = lsf[frnt2];
	p7 = lsf[frnt3];

	r1 = ypf[ind];
	r2 = ypf[frnt1];
	r3 = ypf[frnt2];

	l1 = ypb[ind];
	l2 = ypb[back1];
	l3 = ypb[back2];

	ny[ind] = upwind_normal_point(p1,p2,p3,p4,p5,p6,p7,r1,r2,r3,l1,l2,l3,dy);

	int upup1	= sub2ind(row_idx, col_idx, pge_idx+1, rows, cols, pges);	
	int upup2	= sub2ind(row_idx, col_idx, pge_idx+2, rows, cols, pges);	
	int upup3	= sub2ind(row_idx, col_idx, pge_idx+3, rows, cols, pges);	
	int down1 	= sub2ind(row_idx, col_idx, pge_idx-1, rows, cols, pges);
	int down2 	= sub2ind(row_idx, col_idx, pge_idx-2, rows, cols, pges);
	int down3 	= sub2ind(row_idx, col_idx, pge_idx-3, rows, cols, pges);

	p1 = lsf[down3];
	p2 = lsf[down2];
	p3 = lsf[down1];
	p5 = lsf[upup1];
	p6 = lsf[upup2];
	p7 = lsf[upup3];

	r1 = zpu[ind];
	r2 = zpu[upup1];
	r3 = zpu[upup2];

	l1 = zpd[ind];
	l2 = zpd[down1];
	l3 = zpd[down2];

	nz[ind] = upwind_normal_point(p1,p2,p3,p4,p5,p6,p7,r1,r2,r3,l1,l2,l3,dz);
	
}

__device__ inline
void cubic_interp_coefficient(double & c0, double & c1, double & c2, double & c3, double v0, double v1, double v2, double v3, double s)
{
	c0 = v0;
 	c1 = (     3.0 * (v1-v0) - 3.0/2.0 * (v2-v0) + 1.0/3.0 * (v3-v0) ) / s;
 	c2 = (-5.0/2.0 * (v1-v0) +     2.0 * (v2-v0) - 1.0/2.0 * (v3-v0) ) / pow(s,2);
 	c3 = ( 1.0/2.0 * (v1-v0) - 1.0/2.0 * (v2-v0) + 1.0/6.0 * (v3-v0) ) / pow(s,3);
}

// modify forward/backward(c_f/b) values at v0:[v4,v1,v0,v2,v3]
// if dis_b/f!=ds, then there is boundary nearby, a cubic interpolant is then constructed
// C(x) = c0 + c1*x + c2*x^2 + c3*c^3 through (0,v1),(ds,v0),(2*ds,v2),(3*ds,v2) assuming boundary is between v0,v2
// and used to calculate c_b/f at boundary crossing nodes
__device__ inline
void cubic_interp(double & c_forward, double & c_backward, double dis_f, double dis_b, double ds, double v4, double v1, double v0, double v2, double v3)
{
	c_forward = 0;
	c_backward = 0;

	double c0,c1,c2,c3; // coefficient for cubic interpolant
	// if there is a boundary in the forward direction
	if(dis_f!=ds){
		cubic_interp_coefficient(c0,c1,c2,c3,v1,v0,v2,v3,ds);
		double xc = ds + dis_f; // coordinate of the boundary point
		c_forward = c0 + c1 * xc + c2 * pow(xc,2) + c3 * pow(xc,3);
	}
	// if there is a boundary in the backward direction
	if(dis_b!=ds){
		cubic_interp_coefficient(c0,c1,c2,c3,v4,v1,v0,v2,ds);
		double xc = 2*ds - dis_b; 
		c_backward = c0 + c1 * xc + c2 * pow(xc,2) + c3 * pow(xc,3);
	}
}


// interpolate values at boundary points
__global__
void boundary_interpolate(double * cpr, double * cpl, double * cpf, double * cpb, double * cpu, double * cpd, double const * xpr, double const * xpl, double const * ypf, double const * ypb, double const * zpu, double const * zpd, double const * lsf, int rows, int cols, int pges, double dx, double dy, double dz, int num_ele)
{
	int row_idx = blockIdx.x * blockDim.x + threadIdx.x;
	int col_idx = blockIdx.y * blockDim.y + threadIdx.y;
	int pge_idx = blockIdx.z * blockDim.z + threadIdx.z;

	if(row_idx >= rows || col_idx >= cols || pge_idx >= pges){
		return;
	}

	int ind = sub2ind(row_idx, col_idx, pge_idx, rows, cols, pges);

	int right 	= sub2ind(row_idx, col_idx+1, pge_idx, rows, cols, pges);
	int right2 	= sub2ind(row_idx, col_idx+2, pge_idx, rows, cols, pges);
	int left 	= sub2ind(row_idx, col_idx-1, pge_idx, rows, cols, pges);
	int left2 	= sub2ind(row_idx, col_idx-2, pge_idx, rows, cols, pges);

	cubic_interp(cpr[ind],cpl[ind],xpr[ind],xpl[ind],dx,lsf[left2],lsf[left],lsf[ind],lsf[right],lsf[right2]);

	int front 	= sub2ind(row_idx+1, col_idx, pge_idx, rows, cols, pges);	
	int front2 	= sub2ind(row_idx+2, col_idx, pge_idx, rows, cols, pges);
	int back 	= sub2ind(row_idx-1, col_idx, pge_idx, rows, cols, pges);
	int back2 	= sub2ind(row_idx-2, col_idx, pge_idx, rows, cols, pges);

	cubic_interp(cpf[ind],cpb[ind],ypf[ind],ypb[ind],dy,lsf[back2],lsf[back],lsf[ind],lsf[front],lsf[front2]);

	int up 		= sub2ind(row_idx, col_idx, pge_idx+1, rows, cols, pges);	
	int up2 	= sub2ind(row_idx, col_idx, pge_idx+2, rows, cols, pges);	
	int down 	= sub2ind(row_idx, col_idx, pge_idx-1, rows, cols, pges);
	int down2 	= sub2ind(row_idx, col_idx, pge_idx-2, rows, cols, pges);

	cubic_interp(cpu[ind],cpd[ind],zpu[ind],zpd[ind],dz,lsf[down2],lsf[down],lsf[ind],lsf[up],lsf[up2]);

}


// calculate extend step
// now lsf represents a scalar field (not the level set function)
__global__
void extend_step(double * step, double const * deltat, double const * lsf, double const * vx, double const * vy, double const * vz, double const * xpr, double const * xpl, double const * ypf, double const * ypb, double const * zpu, double const * zpd, double const * cpr, double const * cpl, double const * cpf, double const * cpb, double const * cpu, double const * cpd, int rows, int cols, int pges, double dx, double dy, double dz, int num_ele)
{
	int row_idx = blockIdx.x * blockDim.x + threadIdx.x;
	int col_idx = blockIdx.y * blockDim.y + threadIdx.y;
	int pge_idx = blockIdx.z * blockDim.z + threadIdx.z;

	if(row_idx >= rows || col_idx >= cols || pge_idx >= pges){
		return;
	}

	int ind = sub2ind(row_idx, col_idx, pge_idx, rows, cols, pges);

	double p1,p2,p3,p4,p5,p6,p7;
	double r1,r2,r3,l1,l2,l3;
	double v_fore, v_back;

	p4 = lsf[ind];

	int rght1 	= sub2ind(row_idx, col_idx+1, pge_idx, rows, cols, pges);
	int rght2 	= sub2ind(row_idx, col_idx+2, pge_idx, rows, cols, pges);
	int rght3 	= sub2ind(row_idx, col_idx+3, pge_idx, rows, cols, pges);
	int left1 	= sub2ind(row_idx, col_idx-1, pge_idx, rows, cols, pges);
	int left2 	= sub2ind(row_idx, col_idx-2, pge_idx, rows, cols, pges);
	int left3 	= sub2ind(row_idx, col_idx-3, pge_idx, rows, cols, pges);

	p1 = lsf[left3];
	p2 = lsf[left2];
	p3 = lsf[left1];
	p5 = lsf[rght1];
	p6 = lsf[rght2];
	p7 = lsf[rght3];

	r1 = xpr[ind];
	r2 = xpr[rght1];
	r3 = xpr[rght2];

	l1 = xpl[ind];
	l2 = xpl[left1];
	l3 = xpl[left2];

	v_fore = cpr[ind];
	v_back = cpl[ind];

	double xR, xL;
	weno_derivative_boundary(xR,xL,p1,p2,p3,p4,p5,p6,p7,r1,r2,r3,l1,l2,l3,dx,v_fore,v_back);

	int frnt1 	= sub2ind(row_idx+1, col_idx, pge_idx, rows, cols, pges);	
	int frnt2 	= sub2ind(row_idx+2, col_idx, pge_idx, rows, cols, pges);	
	int frnt3 	= sub2ind(row_idx+3, col_idx, pge_idx, rows, cols, pges);	
	int back1 	= sub2ind(row_idx-1, col_idx, pge_idx, rows, cols, pges);
	int back2 	= sub2ind(row_idx-2, col_idx, pge_idx, rows, cols, pges);
	int back3 	= sub2ind(row_idx-3, col_idx, pge_idx, rows, cols, pges);

	p1 = lsf[back3];
	p2 = lsf[back2];
	p3 = lsf[back1];
	p5 = lsf[frnt1];
	p6 = lsf[frnt2];
	p7 = lsf[frnt3];

	r1 = ypf[ind];
	r2 = ypf[frnt1];
	r3 = ypf[frnt2];

	l1 = ypb[ind];
	l2 = ypb[back1];
	l3 = ypb[back2];

	v_fore = cpf[ind];
	v_back = cpb[ind];

	double yF, yB;
	weno_derivative_boundary(yF,yB,p1,p2,p3,p4,p5,p6,p7,r1,r2,r3,l1,l2,l3,dy,v_fore,v_back);

	int upup1	= sub2ind(row_idx, col_idx, pge_idx+1, rows, cols, pges);	
	int upup2	= sub2ind(row_idx, col_idx, pge_idx+2, rows, cols, pges);	
	int upup3	= sub2ind(row_idx, col_idx, pge_idx+3, rows, cols, pges);	
	int down1 	= sub2ind(row_idx, col_idx, pge_idx-1, rows, cols, pges);
	int down2 	= sub2ind(row_idx, col_idx, pge_idx-2, rows, cols, pges);
	int down3 	= sub2ind(row_idx, col_idx, pge_idx-3, rows, cols, pges);

	p1 = lsf[down3];
	p2 = lsf[down2];
	p3 = lsf[down1];
	p5 = lsf[upup1];
	p6 = lsf[upup2];
	p7 = lsf[upup3];

	r1 = zpu[ind];
	r2 = zpu[upup1];
	r3 = zpu[upup2];

	l1 = zpd[ind];
	l2 = zpd[down1];
	l3 = zpd[down2];

	v_fore = cpu[ind];
	v_back = cpd[ind];

	double zU, zD;
	weno_derivative_boundary(zU,zD,p1,p2,p3,p4,p5,p6,p7,r1,r2,r3,l1,l2,l3,dz,v_fore,v_back);
	
	step[ind] = (min2(0,vx[ind]) * xR + max2(0,vx[ind]) * xL + 
				 min2(0,vy[ind]) * yF + max2(0,vy[ind]) * yB + 
				 min2(0,vz[ind]) * zU + max2(0,vz[ind]) * zD ) * deltat[ind];

}









	.file	"tmpxft_00236321_00000000-6_wenork3_extend.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2023:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2023:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z65__device_stub__Z13upwind_normalPdS_S_PKdS1_S1_S1_S1_S1_S1_iiidddiPdS_S_PKdS1_S1_S1_S1_S1_S1_iiidddi
	.type	_Z65__device_stub__Z13upwind_normalPdS_S_PKdS1_S1_S1_S1_S1_S1_iiidddiPdS_S_PKdS1_S1_S1_S1_S1_S1_iiidddi, @function
_Z65__device_stub__Z13upwind_normalPdS_S_PKdS1_S1_S1_S1_S1_S1_iiidddiPdS_S_PKdS1_S1_S1_S1_S1_S1_iiidddi:
.LFB2045:
	.cfi_startproc
	endbr64
	subq	$328, %rsp
	.cfi_def_cfa_offset 336
	movq	336(%rsp), %rax
	movq	%rdi, 104(%rsp)
	leaq	128(%rsp), %rdi
	movq	%rsi, 96(%rsp)
	leaq	140(%rsp), %rsi
	movq	%rax, 56(%rsp)
	movq	344(%rsp), %rax
	movq	%rdx, 88(%rsp)
	leaq	112(%rsp), %rdx
	movq	%rax, 48(%rsp)
	movq	352(%rsp), %rax
	movq	%rcx, 80(%rsp)
	leaq	120(%rsp), %rcx
	movq	%rax, 40(%rsp)
	movq	360(%rsp), %rax
	movq	%r8, 72(%rsp)
	movq	%r9, 64(%rsp)
	movq	%rax, 32(%rsp)
	movsd	%xmm0, 24(%rsp)
	movsd	%xmm1, 16(%rsp)
	movsd	%xmm2, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 312(%rsp)
	xorl	%eax, %eax
	leaq	104(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	96(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	88(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	80(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	72(%rsp), %rax
	movq	%rax, 208(%rsp)
	leaq	64(%rsp), %rax
	movq	%rax, 216(%rsp)
	leaq	56(%rsp), %rax
	movq	%rax, 224(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 232(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 240(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 248(%rsp)
	leaq	368(%rsp), %rax
	movq	%rax, 256(%rsp)
	leaq	376(%rsp), %rax
	movq	%rax, 264(%rsp)
	leaq	384(%rsp), %rax
	movq	%rax, 272(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 280(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 288(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 296(%rsp)
	leaq	392(%rsp), %rax
	movq	%rax, 304(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 128(%rsp)
	movl	$1, 136(%rsp)
	movq	%rax, 140(%rsp)
	movl	$1, 148(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	120(%rsp)
	.cfi_def_cfa_offset 344
	leaq	_Z13upwind_normalPdS_S_PKdS1_S1_S1_S1_S1_S1_iiidddi(%rip), %rdi
	pushq	120(%rsp)
	.cfi_def_cfa_offset 352
	movq	156(%rsp), %rcx
	movl	164(%rsp), %r8d
	movq	144(%rsp), %rsi
	movl	152(%rsp), %edx
	leaq	192(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 344
	popq	%rdx
	.cfi_def_cfa_offset 336
.L2:
	movq	312(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$328, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2045:
	.size	_Z65__device_stub__Z13upwind_normalPdS_S_PKdS1_S1_S1_S1_S1_S1_iiidddiPdS_S_PKdS1_S1_S1_S1_S1_S1_iiidddi, .-_Z65__device_stub__Z13upwind_normalPdS_S_PKdS1_S1_S1_S1_S1_S1_iiidddiPdS_S_PKdS1_S1_S1_S1_S1_S1_iiidddi
	.globl	_Z13upwind_normalPdS_S_PKdS1_S1_S1_S1_S1_S1_iiidddi
	.type	_Z13upwind_normalPdS_S_PKdS1_S1_S1_S1_S1_S1_iiidddi, @function
_Z13upwind_normalPdS_S_PKdS1_S1_S1_S1_S1_S1_iiidddi:
.LFB2046:
	.cfi_startproc
	endbr64
	jmp	_Z65__device_stub__Z13upwind_normalPdS_S_PKdS1_S1_S1_S1_S1_S1_iiidddiPdS_S_PKdS1_S1_S1_S1_S1_S1_iiidddi
	.cfi_endproc
.LFE2046:
	.size	_Z13upwind_normalPdS_S_PKdS1_S1_S1_S1_S1_S1_iiidddi, .-_Z13upwind_normalPdS_S_PKdS1_S1_S1_S1_S1_S1_iiidddi
	.globl	_Z78__device_stub__Z20boundary_interpolatePdS_S_S_S_S_PKdS1_S1_S1_S1_S1_S1_iiidddiPdS_S_S_S_S_PKdS1_S1_S1_S1_S1_S1_iiidddi
	.type	_Z78__device_stub__Z20boundary_interpolatePdS_S_S_S_S_PKdS1_S1_S1_S1_S1_S1_iiidddiPdS_S_S_S_S_PKdS1_S1_S1_S1_S1_S1_iiidddi, @function
_Z78__device_stub__Z20boundary_interpolatePdS_S_S_S_S_PKdS1_S1_S1_S1_S1_S1_iiidddiPdS_S_S_S_S_PKdS1_S1_S1_S1_S1_S1_iiidddi:
.LFB2047:
	.cfi_startproc
	endbr64
	subq	$376, %rsp
	.cfi_def_cfa_offset 384
	movq	384(%rsp), %rax
	movq	%rdi, 120(%rsp)
	leaq	152(%rsp), %rdi
	movq	%rsi, 112(%rsp)
	leaq	164(%rsp), %rsi
	movq	%rax, 72(%rsp)
	movq	392(%rsp), %rax
	movq	%rdx, 104(%rsp)
	leaq	136(%rsp), %rdx
	movq	%rax, 64(%rsp)
	movq	400(%rsp), %rax
	movq	%rcx, 96(%rsp)
	leaq	144(%rsp), %rcx
	movq	%rax, 56(%rsp)
	movq	408(%rsp), %rax
	movq	%r8, 88(%rsp)
	movq	%rax, 48(%rsp)
	movq	416(%rsp), %rax
	movq	%r9, 80(%rsp)
	movq	%rax, 40(%rsp)
	movq	424(%rsp), %rax
	movsd	%xmm0, 16(%rsp)
	movq	%rax, 32(%rsp)
	movq	432(%rsp), %rax
	movsd	%xmm1, 8(%rsp)
	movq	%rax, 24(%rsp)
	movsd	%xmm2, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 360(%rsp)
	xorl	%eax, %eax
	leaq	120(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	112(%rsp), %rax
	movq	%rax, 208(%rsp)
	leaq	104(%rsp), %rax
	movq	%rax, 216(%rsp)
	leaq	96(%rsp), %rax
	movq	%rax, 224(%rsp)
	leaq	88(%rsp), %rax
	movq	%rax, 232(%rsp)
	leaq	80(%rsp), %rax
	movq	%rax, 240(%rsp)
	leaq	72(%rsp), %rax
	movq	%rax, 248(%rsp)
	leaq	64(%rsp), %rax
	movq	%rax, 256(%rsp)
	leaq	56(%rsp), %rax
	movq	%rax, 264(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 272(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 280(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 288(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 296(%rsp)
	leaq	440(%rsp), %rax
	movq	%rax, 304(%rsp)
	leaq	448(%rsp), %rax
	movq	%rax, 312(%rsp)
	leaq	456(%rsp), %rax
	movq	%rax, 320(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 328(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 336(%rsp)
	movq	%rsp, %rax
	movq	%rax, 344(%rsp)
	leaq	464(%rsp), %rax
	movq	%rax, 352(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 152(%rsp)
	movl	$1, 160(%rsp)
	movq	%rax, 164(%rsp)
	movl	$1, 172(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L8
	pushq	144(%rsp)
	.cfi_def_cfa_offset 392
	leaq	_Z20boundary_interpolatePdS_S_S_S_S_PKdS1_S1_S1_S1_S1_S1_iiidddi(%rip), %rdi
	pushq	144(%rsp)
	.cfi_def_cfa_offset 400
	movq	180(%rsp), %rcx
	movl	188(%rsp), %r8d
	movq	168(%rsp), %rsi
	movl	176(%rsp), %edx
	leaq	216(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 392
	popq	%rdx
	.cfi_def_cfa_offset 384
.L8:
	movq	360(%rsp), %rax
	subq	%fs:40, %rax
	je	.L10
	call	__stack_chk_fail@PLT
.L10:
	addq	$376, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2047:
	.size	_Z78__device_stub__Z20boundary_interpolatePdS_S_S_S_S_PKdS1_S1_S1_S1_S1_S1_iiidddiPdS_S_S_S_S_PKdS1_S1_S1_S1_S1_S1_iiidddi, .-_Z78__device_stub__Z20boundary_interpolatePdS_S_S_S_S_PKdS1_S1_S1_S1_S1_S1_iiidddiPdS_S_S_S_S_PKdS1_S1_S1_S1_S1_S1_iiidddi
	.globl	_Z20boundary_interpolatePdS_S_S_S_S_PKdS1_S1_S1_S1_S1_S1_iiidddi
	.type	_Z20boundary_interpolatePdS_S_S_S_S_PKdS1_S1_S1_S1_S1_S1_iiidddi, @function
_Z20boundary_interpolatePdS_S_S_S_S_PKdS1_S1_S1_S1_S1_S1_iiidddi:
.LFB2048:
	.cfi_startproc
	endbr64
	jmp	_Z78__device_stub__Z20boundary_interpolatePdS_S_S_S_S_PKdS1_S1_S1_S1_S1_S1_iiidddiPdS_S_S_S_S_PKdS1_S1_S1_S1_S1_S1_iiidddi
	.cfi_endproc
.LFE2048:
	.size	_Z20boundary_interpolatePdS_S_S_S_S_PKdS1_S1_S1_S1_S1_S1_iiidddi, .-_Z20boundary_interpolatePdS_S_S_S_S_PKdS1_S1_S1_S1_S1_S1_iiidddi
	.globl	_Z89__device_stub__Z11extend_stepPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddiPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi
	.type	_Z89__device_stub__Z11extend_stepPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddiPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi, @function
_Z89__device_stub__Z11extend_stepPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddiPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi:
.LFB2049:
	.cfi_startproc
	endbr64
	subq	$456, %rsp
	.cfi_def_cfa_offset 464
	movq	464(%rsp), %rax
	movq	%rdi, 168(%rsp)
	leaq	192(%rsp), %rdi
	movq	%rsi, 160(%rsp)
	leaq	204(%rsp), %rsi
	movq	%rax, 120(%rsp)
	movq	472(%rsp), %rax
	movq	%rdx, 152(%rsp)
	leaq	176(%rsp), %rdx
	movq	%rax, 112(%rsp)
	movq	480(%rsp), %rax
	movq	%rcx, 144(%rsp)
	leaq	184(%rsp), %rcx
	movq	%rax, 104(%rsp)
	movq	488(%rsp), %rax
	movq	%r8, 136(%rsp)
	movq	%rax, 96(%rsp)
	movq	496(%rsp), %rax
	movq	%r9, 128(%rsp)
	movq	%rax, 88(%rsp)
	movq	504(%rsp), %rax
	movsd	%xmm0, 24(%rsp)
	movq	%rax, 80(%rsp)
	movq	512(%rsp), %rax
	movsd	%xmm1, 16(%rsp)
	movq	%rax, 72(%rsp)
	movq	520(%rsp), %rax
	movsd	%xmm2, 8(%rsp)
	movq	%rax, 64(%rsp)
	movq	528(%rsp), %rax
	movq	%rax, 56(%rsp)
	movq	536(%rsp), %rax
	movq	%rax, 48(%rsp)
	movq	544(%rsp), %rax
	movq	%rax, 40(%rsp)
	movq	552(%rsp), %rax
	movq	%rax, 32(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 440(%rsp)
	xorl	%eax, %eax
	leaq	168(%rsp), %rax
	movl	$1, 200(%rsp)
	movq	%rax, 240(%rsp)
	leaq	160(%rsp), %rax
	movq	%rax, 248(%rsp)
	leaq	152(%rsp), %rax
	movq	%rax, 256(%rsp)
	leaq	144(%rsp), %rax
	movq	%rax, 264(%rsp)
	leaq	136(%rsp), %rax
	movq	%rax, 272(%rsp)
	leaq	128(%rsp), %rax
	movq	%rax, 280(%rsp)
	leaq	120(%rsp), %rax
	movq	%rax, 288(%rsp)
	leaq	112(%rsp), %rax
	movq	%rax, 296(%rsp)
	leaq	104(%rsp), %rax
	movq	%rax, 304(%rsp)
	leaq	96(%rsp), %rax
	movq	%rax, 312(%rsp)
	leaq	88(%rsp), %rax
	movq	%rax, 320(%rsp)
	leaq	80(%rsp), %rax
	movq	%rax, 328(%rsp)
	leaq	72(%rsp), %rax
	movq	%rax, 336(%rsp)
	leaq	64(%rsp), %rax
	movq	%rax, 344(%rsp)
	leaq	56(%rsp), %rax
	movq	%rax, 352(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 360(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 368(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 376(%rsp)
	leaq	560(%rsp), %rax
	movq	%rax, 384(%rsp)
	leaq	568(%rsp), %rax
	movq	%rax, 392(%rsp)
	leaq	576(%rsp), %rax
	movq	%rax, 400(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 408(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 416(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 424(%rsp)
	leaq	584(%rsp), %rax
	movq	%rax, 432(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 192(%rsp)
	movq	%rax, 204(%rsp)
	movl	$1, 212(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L13
	pushq	184(%rsp)
	.cfi_def_cfa_offset 472
	leaq	_Z11extend_stepPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi(%rip), %rdi
	pushq	184(%rsp)
	.cfi_def_cfa_offset 480
	movq	220(%rsp), %rcx
	movl	228(%rsp), %r8d
	movq	208(%rsp), %rsi
	movl	216(%rsp), %edx
	leaq	256(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 472
	popq	%rdx
	.cfi_def_cfa_offset 464
.L13:
	movq	440(%rsp), %rax
	subq	%fs:40, %rax
	je	.L15
	call	__stack_chk_fail@PLT
.L15:
	addq	$456, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2049:
	.size	_Z89__device_stub__Z11extend_stepPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddiPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi, .-_Z89__device_stub__Z11extend_stepPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddiPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi
	.globl	_Z11extend_stepPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi
	.type	_Z11extend_stepPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi, @function
_Z11extend_stepPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi:
.LFB2050:
	.cfi_startproc
	endbr64
	jmp	_Z89__device_stub__Z11extend_stepPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddiPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi
	.cfi_endproc
.LFE2050:
	.size	_Z11extend_stepPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi, .-_Z11extend_stepPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z11extend_stepPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi"
.LC1:
	.string	"_Z20boundary_interpolatePdS_S_S_S_S_PKdS1_S1_S1_S1_S1_S1_iiidddi"
.LC2:
	.string	"_Z13upwind_normalPdS_S_PKdS1_S1_S1_S1_S1_S1_iiidddi"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2052:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z11extend_stepPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC1(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z20boundary_interpolatePdS_S_S_S_S_PKdS1_S1_S1_S1_S1_S1_iiidddi(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC2(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z13upwind_normalPdS_S_PKdS1_S1_S1_S1_S1_S1_iiidddi(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2052:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
/*******************************************************************************
 * serveral useful gpu functions will be defined in this file to facilitate
 * the extension scheme 
 ******************************************************************************/

typedef struct
{
	double sR;
	double sL;
} double_eno_derivative;

__device__ inline
double max2(double x, double y)
{
	return (x<y) ? y : x;
}

__device__ inline
double min2(double x, double y)
{
	return (x<y) ? x : y;
}

__device__ inline
double min_mod(double x, double y)
{
	return (x*y<0) ? 0.0 : (fabs(x)<fabs(y) ? x : y);
}

__device__ inline
double min_abs(double x, double y)
{
	return (fabs(x)<fabs(y)) ? x : y;
}

__device__ inline
double sign(double x)
{
	return (x>0) ? 1.0 : -1.0;
}


// convert subindex to linear index
// periodic boundary conditions are assumed
__device__ inline
int sub2ind(int row_idx, int col_idx, int pge_idx, int rows, int cols, int pges)
{	
	int row_idxn = min2(rows-1, max2(0, row_idx));
	int col_idxn = min2(cols-1, max2(0, col_idx));
	int pge_idxn = min2(pges-1, max2(0, pge_idx));

	int ind = pge_idxn * rows * cols + col_idxn * rows + row_idxn;

	return ind;
}

__device__ inline
double weno_onesided_derivative(double v1, double v2, double v3, double v4, double v5)
{
	// different choices of ENO derivatives
	double phi1 = 1./3. * v1 	- 7./6. * v2 	+ 11./6. * v3;
	double phi2 = -1./6. * v2 	+ 5./6. * v3 	+ 1./3. * v4;
	double phi3 = 1./3. * v3	+ 5./6. * v4	- 1./6. * v5;

	// smoothness parameter
	double S1 = 13./12. * pow((v1 - 2*v2 + v3),2) + 1./4. * pow((v1 - 4*v2 + 3*v3),2);
	double S2 = 13./12. * pow((v2 - 2*v3 + v4),2) + 1./4. * pow((v2 - v4),2);
	double S3 = 13./12. * pow((v3 - 2*v4 + v5),2) + 1./4. * pow((3*v3 - 4*v4 + v5),2);

	double epsilon = 1e-6;
	double alpha1 = 0.1 / pow( (S1 + epsilon), 2);
	double alpha2 = 0.6 / pow( (S2 + epsilon), 2);
	double alpha3 = 0.3 / pow( (S3 + epsilon), 2);

	// weights for each stencil
	double sum = alpha1 + alpha2 + alpha3;
	double omega1 = alpha1 / sum;
	double omega2 = alpha2 / sum;
	double omega3 = alpha3 / sum;

	return (omega1*phi1 + omega2*phi2 + omega3*phi3);

}

// given a stencil across the boundary: p1<-l3-p2<-l2-p3<-l1-p4-r1->p5-r2->p6-r3->p7
// create a new stencil (x3m,h3m),(x2m,h2m),(x1m,h1m),(x0,h0),(x1,h1),(x2,h2),(x3,h3) including boundary nodes
__device__ inline
void select_stencil(double & h3m, double & h2m, double & h1m, double & h0, double & h1, double & h2, double & h3, double & x3m, double & x2m, double & x1m, double & x0, double & x1, double & x2, double & x3, double p1, double p2, double p3, double p4, double p5, double p6, double p7, double r1, double r2, double r3, double l1, double l2, double l3, double ds, double h_fore, double h_back)
{
		h0 = p4; x0 = 0.0;

		if(r1<ds){
			x1 = r1;
			x2 = ds;
			x3 = 2*ds;
			h1 = h_fore;
			h2 = p5;
			h3 = p6;
		}else{
			x1 = ds;
			x2 = 2*ds;
			x3 = 3*ds;
			h1 = p5;
			h2 = p6;
			h3 = p7;
		}

		if(l1<ds){
			x1m = -l1;
			x2m = - ds;
			x3m = - 2*ds;
			h1m = h_back;
			h2m = p3;
			h3m = p2;
		}else{
			x1m = -ds;
			x2m = - 2*ds;
			x3m = - 3*ds;
			h1m = p3;
			h2m = p2;
			h3m = p1;
		}
}

// for stencil (x3m,h3m),(x2m,h2m),(x1m,h1m),(x0,h0),(x1,h1),(x2,h2),(x3,h3) including boundary nodes
// calculate cubic eno derivatives at (x0,h0)
// note that this is a nonuniform stencil
__device__ inline
void ENO_cubic_derivative(double & d_fore, double & d_back, double h3m, double h2m, double h1m, double h0, double h1, double h2, double h3, double x3m, double x2m, double x1m, double x0, double x1, double x2, double x3)
{

	// divided differences
	double d1_2_5   = (h3  - h2)  / (x3  - x2) ;
	double d1_1_5   = (h2  - h1)  / (x2  - x1) ;
	double d1_0_5   = (h1  - h0)  / (x1  - x0) ;
	double d1_m0_5  = (h0  - h1m) / (x0  - x1m);
	double d1_m1_5  = (h1m - h2m) / (x1m - x2m);
	double d1_m2_5  = (h2m - h3m) / (x2m - x3m);

	double d2_2  = (d1_2_5  - d1_1_5)  / (x3  - x1) ;
	double d2_1  = (d1_1_5  - d1_0_5)  / (x2  - x0) ;
	double d2_0  = (d1_0_5  - d1_m0_5) / (x1  - x1m);
	double d2_m1 = (d1_m0_5 - d1_m1_5) / (x0  - x2m);
	double d2_m2 = (d1_m1_5 - d1_m2_5) / (x1m - x3m);

	double d3_1_5  = (d2_2  - d2_1)  / (x3 - x0) ;
	double d3_0_5  = (d2_1  - d2_0)  / (x2 - x1m);
	double d3_m0_5 = (d2_0  - d2_m1) / (x1 - x2m);
	double d3_m1_5 = (d2_m1 - d2_m2) / (x0 - x3m);

	double a1 = (x0 - x1m) * (x0 - x2m) * min_abs(d3_m0_5, d3_m1_5);
	double a2 = (x0 - x1m) * (x0 - x1)  * min_abs(d3_m0_5, d3_0_5);
	double a = (fabs(d2_m1) < fabs(d2_0)) ? a1 : a2;

	double b1 = (x0 - x1m) * (x0 - x1) * min_abs(d3_m0_5, d3_0_5);
	double b2 = (x0 - x1)  * (x0 - x2) * min_abs(d3_0_5,  d3_1_5);
	double b = (fabs(d2_0) < fabs(d2_1)) ? b1 : b2;

	d_back = d1_m0_5 + min_mod(d2_m1,d2_0) * (x0 - x1m) + a;
	d_fore = d1_0_5  + min_mod(d2_0, d2_1) * (x0 - x1)  + b;
}

// calculate weno derivative at p4: p1<-l3-p2<-l2-p3<-l1-p4-r1->p5-r2->p6-r3->p7
// where px are level set function values at node x
// lx, rx are distance to the left/right node 
__device__ inline
void weno_derivative_boundary(double & d_fore, double & d_back, double p1, double p2, double p3, double p4, double p5, double p6, double p7, double r1, double r2, double r3, double l1, double l2, double l3, double ds, double v_fore, double v_back)
{
	// the condistion below is better than p3*p4<0 || p4*p5<0 
	bool cross_interface = r1<ds || l1<ds;

	if(!cross_interface){
		double v1 = (p2 - p1) / ds;
		double v2 = (p3 - p2) / ds;
		double v3 = (p4 - p3) / ds;
		double v4 = (p5 - p4) / ds;
		double v5 = (p6 - p5) / ds;
		double v6 = (p7 - p6) / ds;
		d_back = weno_onesided_derivative(v1,v2,v3,v4,v5);
		d_fore = weno_onesided_derivative(v6,v5,v4,v3,v2);
	}// if not a node IMMEDIATELY adjacent to the boundary, calculate weno derivatives as usual
	else{
		double h3m,h2m,h1m,h0,h1,h2,h3;
		double x3m,x2m,x1m,x0,x1,x2,x3;
		select_stencil(h3m,h2m,h1m,h0,h1,h2,h3,x3m,x2m,x1m,x0,x1,x2,x3,p1,p2,p3,p4,p5,p6,p7,r1,r2,r3,l1,l2,l3,ds,v_fore,v_back);
		ENO_cubic_derivative(d_fore,d_back,h3m,h2m,h1m,h0,h1,h2,h3,x3m,x2m,x1m,x0,x1,x2,x3);
	}// for nodes IMMEDIATELY adjacent to the boundary, use cubic ENO interpolant
}

__device__ inline
double upwind_normal_point(double p1, double p2, double p3, double p4, double p5, double p6, double p7, double r1, double r2, double r3, double l1, double l2, double l3, double ds)
{
	double d_back, d_fore;
	weno_derivative_boundary(d_fore,d_back,p1,p2,p3,p4,p5,p6,p7,r1,r2,r3,l1,l2,l3,ds,0.0,0.0);

	return (fabs(p5)<fabs(p3)) ? d_fore : d_back;
}

// calculate the upwind normal
__global__
void upwind_normal(double * nx, double * ny, double * nz, double const * lsf, double const * xpr, double const * xpl, double const * ypf, double const * ypb, double const * zpu, double const * zpd, int rows, int cols, int pges, double dx, double dy, double dz, int num_ele)
{
	int row_idx = blockIdx.x * blockDim.x + threadIdx.x;
	int col_idx = blockIdx.y * blockDim.y + threadIdx.y;
	int pge_idx = blockIdx.z * blockDim.z + threadIdx.z;

	if(row_idx >= rows || col_idx >= cols || pge_idx >= pges){
		return;
	}

	int ind = sub2ind(row_idx, col_idx, pge_idx, rows, cols, pges);

	double p1,p2,p3,p4,p5,p6,p7;
	double r1,r2,r3,l1,l2,l3;

	p4 = lsf[ind];

	int rght1 	= sub2ind(row_idx, col_idx+1, pge_idx, rows, cols, pges);
	int rght2 	= sub2ind(row_idx, col_idx+2, pge_idx, rows, cols, pges);
	int rght3 	= sub2ind(row_idx, col_idx+3, pge_idx, rows, cols, pges);
	int left1 	= sub2ind(row_idx, col_idx-1, pge_idx, rows, cols, pges);
	int left2 	= sub2ind(row_idx, col_idx-2, pge_idx, rows, cols, pges);
	int left3 	= sub2ind(row_idx, col_idx-3, pge_idx, rows, cols, pges);

	p1 = lsf[left3];
	p2 = lsf[left2];
	p3 = lsf[left1];
	p5 = lsf[rght1];
	p6 = lsf[rght2];
	p7 = lsf[rght3];

	r1 = xpr[ind];
	r2 = xpr[rght1];
	r3 = xpr[rght2];

	l1 = xpl[ind];
	l2 = xpl[left1];
	l3 = xpl[left2];

	nx[ind] = upwind_normal_point(p1,p2,p3,p4,p5,p6,p7,r1,r2,r3,l1,l2,l3,dx);

	int frnt1 	= sub2ind(row_idx+1, col_idx, pge_idx, rows, cols, pges);	
	int frnt2 	= sub2ind(row_idx+2, col_idx, pge_idx, rows, cols, pges);	
	int frnt3 	= sub2ind(row_idx+3, col_idx, pge_idx, rows, cols, pges);	
	int back1 	= sub2ind(row_idx-1, col_idx, pge_idx, rows, cols, pges);
	int back2 	= sub2ind(row_idx-2, col_idx, pge_idx, rows, cols, pges);
	int back3 	= sub2ind(row_idx-3, col_idx, pge_idx, rows, cols, pges);

	p1 = lsf[back3];
	p2 = lsf[back2];
	p3 = lsf[back1];
	p5 = lsf[frnt1];
	p6 = lsf[frnt2];
	p7 = lsf[frnt3];

	r1 = ypf[ind];
	r2 = ypf[frnt1];
	r3 = ypf[frnt2];

	l1 = ypb[ind];
	l2 = ypb[back1];
	l3 = ypb[back2];

	ny[ind] = upwind_normal_point(p1,p2,p3,p4,p5,p6,p7,r1,r2,r3,l1,l2,l3,dy);

	int upup1	= sub2ind(row_idx, col_idx, pge_idx+1, rows, cols, pges);	
	int upup2	= sub2ind(row_idx, col_idx, pge_idx+2, rows, cols, pges);	
	int upup3	= sub2ind(row_idx, col_idx, pge_idx+3, rows, cols, pges);	
	int down1 	= sub2ind(row_idx, col_idx, pge_idx-1, rows, cols, pges);
	int down2 	= sub2ind(row_idx, col_idx, pge_idx-2, rows, cols, pges);
	int down3 	= sub2ind(row_idx, col_idx, pge_idx-3, rows, cols, pges);

	p1 = lsf[down3];
	p2 = lsf[down2];
	p3 = lsf[down1];
	p5 = lsf[upup1];
	p6 = lsf[upup2];
	p7 = lsf[upup3];

	r1 = zpu[ind];
	r2 = zpu[upup1];
	r3 = zpu[upup2];

	l1 = zpd[ind];
	l2 = zpd[down1];
	l3 = zpd[down2];

	nz[ind] = upwind_normal_point(p1,p2,p3,p4,p5,p6,p7,r1,r2,r3,l1,l2,l3,dz);
	
}

__device__ inline
void cubic_interp_coefficient(double & c0, double & c1, double & c2, double & c3, double v0, double v1, double v2, double v3, double s)
{
	c0 = v0;
 	c1 = (     3.0 * (v1-v0) - 3.0/2.0 * (v2-v0) + 1.0/3.0 * (v3-v0) ) / s;
 	c2 = (-5.0/2.0 * (v1-v0) +     2.0 * (v2-v0) - 1.0/2.0 * (v3-v0) ) / pow(s,2);
 	c3 = ( 1.0/2.0 * (v1-v0) - 1.0/2.0 * (v2-v0) + 1.0/6.0 * (v3-v0) ) / pow(s,3);
}

// modify forward/backward(c_f/b) values at v0:[v4,v1,v0,v2,v3]
// if dis_b/f!=ds, then there is boundary nearby, a cubic interpolant is then constructed
// C(x) = c0 + c1*x + c2*x^2 + c3*c^3 through (0,v1),(ds,v0),(2*ds,v2),(3*ds,v2) assuming boundary is between v0,v2
// and used to calculate c_b/f at boundary crossing nodes
__device__ inline
void cubic_interp(double & c_forward, double & c_backward, double dis_f, double dis_b, double ds, double v4, double v1, double v0, double v2, double v3)
{
	c_forward = 0;
	c_backward = 0;

	double c0,c1,c2,c3; // coefficient for cubic interpolant
	// if there is a boundary in the forward direction
	if(dis_f!=ds){
		cubic_interp_coefficient(c0,c1,c2,c3,v1,v0,v2,v3,ds);
		double xc = ds + dis_f; // coordinate of the boundary point
		c_forward = c0 + c1 * xc + c2 * pow(xc,2) + c3 * pow(xc,3);
	}
	// if there is a boundary in the backward direction
	if(dis_b!=ds){
		cubic_interp_coefficient(c0,c1,c2,c3,v4,v1,v0,v2,ds);
		double xc = 2*ds - dis_b; 
		c_backward = c0 + c1 * xc + c2 * pow(xc,2) + c3 * pow(xc,3);
	}
}


// interpolate values at boundary points
__global__
void boundary_interpolate(double * cpr, double * cpl, double * cpf, double * cpb, double * cpu, double * cpd, double const * xpr, double const * xpl, double const * ypf, double const * ypb, double const * zpu, double const * zpd, double const * lsf, int rows, int cols, int pges, double dx, double dy, double dz, int num_ele)
{
	int row_idx = blockIdx.x * blockDim.x + threadIdx.x;
	int col_idx = blockIdx.y * blockDim.y + threadIdx.y;
	int pge_idx = blockIdx.z * blockDim.z + threadIdx.z;

	if(row_idx >= rows || col_idx >= cols || pge_idx >= pges){
		return;
	}

	int ind = sub2ind(row_idx, col_idx, pge_idx, rows, cols, pges);

	int right 	= sub2ind(row_idx, col_idx+1, pge_idx, rows, cols, pges);
	int right2 	= sub2ind(row_idx, col_idx+2, pge_idx, rows, cols, pges);
	int left 	= sub2ind(row_idx, col_idx-1, pge_idx, rows, cols, pges);
	int left2 	= sub2ind(row_idx, col_idx-2, pge_idx, rows, cols, pges);

	cubic_interp(cpr[ind],cpl[ind],xpr[ind],xpl[ind],dx,lsf[left2],lsf[left],lsf[ind],lsf[right],lsf[right2]);

	int front 	= sub2ind(row_idx+1, col_idx, pge_idx, rows, cols, pges);	
	int front2 	= sub2ind(row_idx+2, col_idx, pge_idx, rows, cols, pges);
	int back 	= sub2ind(row_idx-1, col_idx, pge_idx, rows, cols, pges);
	int back2 	= sub2ind(row_idx-2, col_idx, pge_idx, rows, cols, pges);

	cubic_interp(cpf[ind],cpb[ind],ypf[ind],ypb[ind],dy,lsf[back2],lsf[back],lsf[ind],lsf[front],lsf[front2]);

	int up 		= sub2ind(row_idx, col_idx, pge_idx+1, rows, cols, pges);	
	int up2 	= sub2ind(row_idx, col_idx, pge_idx+2, rows, cols, pges);	
	int down 	= sub2ind(row_idx, col_idx, pge_idx-1, rows, cols, pges);
	int down2 	= sub2ind(row_idx, col_idx, pge_idx-2, rows, cols, pges);

	cubic_interp(cpu[ind],cpd[ind],zpu[ind],zpd[ind],dz,lsf[down2],lsf[down],lsf[ind],lsf[up],lsf[up2]);

}


// calculate extend step
// now lsf represents a scalar field (not the level set function)
__global__
void extend_step(double * step, double const * deltat, double const * lsf, double const * vx, double const * vy, double const * vz, double const * xpr, double const * xpl, double const * ypf, double const * ypb, double const * zpu, double const * zpd, double const * cpr, double const * cpl, double const * cpf, double const * cpb, double const * cpu, double const * cpd, int rows, int cols, int pges, double dx, double dy, double dz, int num_ele)
{
	int row_idx = blockIdx.x * blockDim.x + threadIdx.x;
	int col_idx = blockIdx.y * blockDim.y + threadIdx.y;
	int pge_idx = blockIdx.z * blockDim.z + threadIdx.z;

	if(row_idx >= rows || col_idx >= cols || pge_idx >= pges){
		return;
	}

	int ind = sub2ind(row_idx, col_idx, pge_idx, rows, cols, pges);

	double p1,p2,p3,p4,p5,p6,p7;
	double r1,r2,r3,l1,l2,l3;
	double v_fore, v_back;

	p4 = lsf[ind];

	int rght1 	= sub2ind(row_idx, col_idx+1, pge_idx, rows, cols, pges);
	int rght2 	= sub2ind(row_idx, col_idx+2, pge_idx, rows, cols, pges);
	int rght3 	= sub2ind(row_idx, col_idx+3, pge_idx, rows, cols, pges);
	int left1 	= sub2ind(row_idx, col_idx-1, pge_idx, rows, cols, pges);
	int left2 	= sub2ind(row_idx, col_idx-2, pge_idx, rows, cols, pges);
	int left3 	= sub2ind(row_idx, col_idx-3, pge_idx, rows, cols, pges);

	p1 = lsf[left3];
	p2 = lsf[left2];
	p3 = lsf[left1];
	p5 = lsf[rght1];
	p6 = lsf[rght2];
	p7 = lsf[rght3];

	r1 = xpr[ind];
	r2 = xpr[rght1];
	r3 = xpr[rght2];

	l1 = xpl[ind];
	l2 = xpl[left1];
	l3 = xpl[left2];

	v_fore = cpr[ind];
	v_back = cpl[ind];

	double xR, xL;
	weno_derivative_boundary(xR,xL,p1,p2,p3,p4,p5,p6,p7,r1,r2,r3,l1,l2,l3,dx,v_fore,v_back);

	int frnt1 	= sub2ind(row_idx+1, col_idx, pge_idx, rows, cols, pges);	
	int frnt2 	= sub2ind(row_idx+2, col_idx, pge_idx, rows, cols, pges);	
	int frnt3 	= sub2ind(row_idx+3, col_idx, pge_idx, rows, cols, pges);	
	int back1 	= sub2ind(row_idx-1, col_idx, pge_idx, rows, cols, pges);
	int back2 	= sub2ind(row_idx-2, col_idx, pge_idx, rows, cols, pges);
	int back3 	= sub2ind(row_idx-3, col_idx, pge_idx, rows, cols, pges);

	p1 = lsf[back3];
	p2 = lsf[back2];
	p3 = lsf[back1];
	p5 = lsf[frnt1];
	p6 = lsf[frnt2];
	p7 = lsf[frnt3];

	r1 = ypf[ind];
	r2 = ypf[frnt1];
	r3 = ypf[frnt2];

	l1 = ypb[ind];
	l2 = ypb[back1];
	l3 = ypb[back2];

	v_fore = cpf[ind];
	v_back = cpb[ind];

	double yF, yB;
	weno_derivative_boundary(yF,yB,p1,p2,p3,p4,p5,p6,p7,r1,r2,r3,l1,l2,l3,dy,v_fore,v_back);

	int upup1	= sub2ind(row_idx, col_idx, pge_idx+1, rows, cols, pges);	
	int upup2	= sub2ind(row_idx, col_idx, pge_idx+2, rows, cols, pges);	
	int upup3	= sub2ind(row_idx, col_idx, pge_idx+3, rows, cols, pges);	
	int down1 	= sub2ind(row_idx, col_idx, pge_idx-1, rows, cols, pges);
	int down2 	= sub2ind(row_idx, col_idx, pge_idx-2, rows, cols, pges);
	int down3 	= sub2ind(row_idx, col_idx, pge_idx-3, rows, cols, pges);

	p1 = lsf[down3];
	p2 = lsf[down2];
	p3 = lsf[down1];
	p5 = lsf[upup1];
	p6 = lsf[upup2];
	p7 = lsf[upup3];

	r1 = zpu[ind];
	r2 = zpu[upup1];
	r3 = zpu[upup2];

	l1 = zpd[ind];
	l2 = zpd[down1];
	l3 = zpd[down2];

	v_fore = cpu[ind];
	v_back = cpd[ind];

	double zU, zD;
	weno_derivative_boundary(zU,zD,p1,p2,p3,p4,p5,p6,p7,r1,r2,r3,l1,l2,l3,dz,v_fore,v_back);
	
	step[ind] = (min2(0,vx[ind]) * xR + max2(0,vx[ind]) * xL + 
				 min2(0,vy[ind]) * yF + max2(0,vy[ind]) * yB + 
				 min2(0,vz[ind]) * zU + max2(0,vz[ind]) * zD ) * deltat[ind];

}









	.text
	.file	"wenork3_extend.hip"
	.globl	_Z28__device_stub__upwind_normalPdS_S_PKdS1_S1_S1_S1_S1_S1_iiidddi # -- Begin function _Z28__device_stub__upwind_normalPdS_S_PKdS1_S1_S1_S1_S1_S1_iiidddi
	.type	_Z28__device_stub__upwind_normalPdS_S_PKdS1_S1_S1_S1_S1_S1_iiidddi,@function
_Z28__device_stub__upwind_normalPdS_S_PKdS1_S1_S1_S1_S1_S1_iiidddi: # @_Z28__device_stub__upwind_normalPdS_S_PKdS1_S1_S1_S1_S1_S1_iiidddi
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$272, %rsp                      # imm = 0x110
	.cfi_def_cfa_offset 320
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	88(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	80(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	72(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	64(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	56(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	48(%rsp), %r8
	movq	%r9, (%r8)
	leaq	40(%rsp), %r9
	movsd	%xmm0, (%r9)
	leaq	32(%rsp), %r10
	movsd	%xmm1, (%r10)
	leaq	24(%rsp), %r11
	movsd	%xmm2, (%r11)
	leaq	128(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	320(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	328(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	336(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	344(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	352(%rsp), %rax
	movq	%rax, 80(%rbx)
	leaq	360(%rsp), %rax
	movq	%rax, 88(%rbx)
	leaq	368(%rsp), %rax
	movq	%rax, 96(%rbx)
	movq	%r9, 104(%rbx)
	movq	%r10, 112(%rbx)
	movq	%r11, 120(%rbx)
	leaq	376(%rsp), %rax
	movq	%rax, 128(%rbx)
	leaq	112(%rsp), %r14
	leaq	96(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z13upwind_normalPdS_S_PKdS1_S1_S1_S1_S1_S1_iiidddi, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$288, %rsp                      # imm = 0x120
	.cfi_adjust_cfa_offset -288
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z28__device_stub__upwind_normalPdS_S_PKdS1_S1_S1_S1_S1_S1_iiidddi, .Lfunc_end0-_Z28__device_stub__upwind_normalPdS_S_PKdS1_S1_S1_S1_S1_S1_iiidddi
	.cfi_endproc
                                        # -- End function
	.globl	_Z35__device_stub__boundary_interpolatePdS_S_S_S_S_PKdS1_S1_S1_S1_S1_S1_iiidddi # -- Begin function _Z35__device_stub__boundary_interpolatePdS_S_S_S_S_PKdS1_S1_S1_S1_S1_S1_iiidddi
	.type	_Z35__device_stub__boundary_interpolatePdS_S_S_S_S_PKdS1_S1_S1_S1_S1_S1_iiidddi,@function
_Z35__device_stub__boundary_interpolatePdS_S_S_S_S_PKdS1_S1_S1_S1_S1_S1_iiidddi: # @_Z35__device_stub__boundary_interpolatePdS_S_S_S_S_PKdS1_S1_S1_S1_S1_S1_iiidddi
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$288, %rsp                      # imm = 0x120
	.cfi_def_cfa_offset 336
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	88(%rsp), %r10
	movq	%rdi, (%r10)
	leaq	80(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	72(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	64(%rsp), %r11
	movq	%rcx, (%r11)
	leaq	56(%rsp), %r14
	movq	%r8, (%r14)
	leaq	48(%rsp), %r8
	movq	%r9, (%r8)
	leaq	40(%rsp), %rax
	movsd	%xmm0, (%rax)
	leaq	32(%rsp), %rcx
	movsd	%xmm1, (%rcx)
	leaq	24(%rsp), %rdx
	movsd	%xmm2, (%rdx)
	leaq	128(%rsp), %rbx
	movq	%r10, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%r11, 24(%rbx)
	movq	%r14, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	336(%rsp), %rsi
	movq	%rsi, 48(%rbx)
	leaq	344(%rsp), %rsi
	movq	%rsi, 56(%rbx)
	leaq	352(%rsp), %rsi
	movq	%rsi, 64(%rbx)
	leaq	360(%rsp), %rsi
	movq	%rsi, 72(%rbx)
	leaq	368(%rsp), %rsi
	movq	%rsi, 80(%rbx)
	leaq	376(%rsp), %rsi
	movq	%rsi, 88(%rbx)
	leaq	384(%rsp), %rsi
	movq	%rsi, 96(%rbx)
	leaq	392(%rsp), %rsi
	movq	%rsi, 104(%rbx)
	leaq	400(%rsp), %rsi
	movq	%rsi, 112(%rbx)
	leaq	408(%rsp), %rsi
	movq	%rsi, 120(%rbx)
	movq	%rax, 128(%rbx)
	movq	%rcx, 136(%rbx)
	movq	%rdx, 144(%rbx)
	leaq	416(%rsp), %rax
	movq	%rax, 152(%rbx)
	leaq	112(%rsp), %r14
	leaq	96(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z20boundary_interpolatePdS_S_S_S_S_PKdS1_S1_S1_S1_S1_S1_iiidddi, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$304, %rsp                      # imm = 0x130
	.cfi_adjust_cfa_offset -304
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z35__device_stub__boundary_interpolatePdS_S_S_S_S_PKdS1_S1_S1_S1_S1_S1_iiidddi, .Lfunc_end1-_Z35__device_stub__boundary_interpolatePdS_S_S_S_S_PKdS1_S1_S1_S1_S1_S1_iiidddi
	.cfi_endproc
                                        # -- End function
	.globl	_Z26__device_stub__extend_stepPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi # -- Begin function _Z26__device_stub__extend_stepPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi
	.type	_Z26__device_stub__extend_stepPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi,@function
_Z26__device_stub__extend_stepPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi: # @_Z26__device_stub__extend_stepPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$336, %rsp                      # imm = 0x150
	.cfi_def_cfa_offset 384
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	88(%rsp), %r10
	movq	%rdi, (%r10)
	leaq	80(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	72(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	64(%rsp), %r11
	movq	%rcx, (%r11)
	leaq	56(%rsp), %r14
	movq	%r8, (%r14)
	leaq	48(%rsp), %r8
	movq	%r9, (%r8)
	leaq	40(%rsp), %rax
	movsd	%xmm0, (%rax)
	leaq	32(%rsp), %rcx
	movsd	%xmm1, (%rcx)
	leaq	24(%rsp), %rdx
	movsd	%xmm2, (%rdx)
	leaq	128(%rsp), %rbx
	movq	%r10, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%r11, 24(%rbx)
	movq	%r14, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	384(%rsp), %rsi
	movq	%rsi, 48(%rbx)
	leaq	392(%rsp), %rsi
	movq	%rsi, 56(%rbx)
	leaq	400(%rsp), %rsi
	movq	%rsi, 64(%rbx)
	leaq	408(%rsp), %rsi
	movq	%rsi, 72(%rbx)
	leaq	416(%rsp), %rsi
	movq	%rsi, 80(%rbx)
	leaq	424(%rsp), %rsi
	movq	%rsi, 88(%rbx)
	leaq	432(%rsp), %rsi
	movq	%rsi, 96(%rbx)
	leaq	440(%rsp), %rsi
	movq	%rsi, 104(%rbx)
	leaq	448(%rsp), %rsi
	movq	%rsi, 112(%rbx)
	leaq	456(%rsp), %rsi
	movq	%rsi, 120(%rbx)
	leaq	464(%rsp), %rsi
	movq	%rsi, 128(%rbx)
	leaq	472(%rsp), %rsi
	movq	%rsi, 136(%rbx)
	leaq	480(%rsp), %rsi
	movq	%rsi, 144(%rbx)
	leaq	488(%rsp), %rsi
	movq	%rsi, 152(%rbx)
	leaq	496(%rsp), %rsi
	movq	%rsi, 160(%rbx)
	movq	%rax, 168(%rbx)
	movq	%rcx, 176(%rbx)
	movq	%rdx, 184(%rbx)
	leaq	504(%rsp), %rax
	movq	%rax, 192(%rbx)
	leaq	112(%rsp), %r14
	leaq	96(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z11extend_stepPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$352, %rsp                      # imm = 0x160
	.cfi_adjust_cfa_offset -352
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z26__device_stub__extend_stepPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi, .Lfunc_end2-_Z26__device_stub__extend_stepPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB3_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB3_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z13upwind_normalPdS_S_PKdS1_S1_S1_S1_S1_S1_iiidddi, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z20boundary_interpolatePdS_S_S_S_S_PKdS1_S1_S1_S1_S1_S1_iiidddi, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z11extend_stepPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end3:
	.size	__hip_module_ctor, .Lfunc_end3-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB4_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB4_2:
	retq
.Lfunc_end4:
	.size	__hip_module_dtor, .Lfunc_end4-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z13upwind_normalPdS_S_PKdS1_S1_S1_S1_S1_S1_iiidddi,@object # @_Z13upwind_normalPdS_S_PKdS1_S1_S1_S1_S1_S1_iiidddi
	.section	.rodata,"a",@progbits
	.globl	_Z13upwind_normalPdS_S_PKdS1_S1_S1_S1_S1_S1_iiidddi
	.p2align	3, 0x0
_Z13upwind_normalPdS_S_PKdS1_S1_S1_S1_S1_S1_iiidddi:
	.quad	_Z28__device_stub__upwind_normalPdS_S_PKdS1_S1_S1_S1_S1_S1_iiidddi
	.size	_Z13upwind_normalPdS_S_PKdS1_S1_S1_S1_S1_S1_iiidddi, 8

	.type	_Z20boundary_interpolatePdS_S_S_S_S_PKdS1_S1_S1_S1_S1_S1_iiidddi,@object # @_Z20boundary_interpolatePdS_S_S_S_S_PKdS1_S1_S1_S1_S1_S1_iiidddi
	.globl	_Z20boundary_interpolatePdS_S_S_S_S_PKdS1_S1_S1_S1_S1_S1_iiidddi
	.p2align	3, 0x0
_Z20boundary_interpolatePdS_S_S_S_S_PKdS1_S1_S1_S1_S1_S1_iiidddi:
	.quad	_Z35__device_stub__boundary_interpolatePdS_S_S_S_S_PKdS1_S1_S1_S1_S1_S1_iiidddi
	.size	_Z20boundary_interpolatePdS_S_S_S_S_PKdS1_S1_S1_S1_S1_S1_iiidddi, 8

	.type	_Z11extend_stepPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi,@object # @_Z11extend_stepPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi
	.globl	_Z11extend_stepPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi
	.p2align	3, 0x0
_Z11extend_stepPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi:
	.quad	_Z26__device_stub__extend_stepPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi
	.size	_Z11extend_stepPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z13upwind_normalPdS_S_PKdS1_S1_S1_S1_S1_S1_iiidddi"
	.size	.L__unnamed_1, 52

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z20boundary_interpolatePdS_S_S_S_S_PKdS1_S1_S1_S1_S1_S1_iiidddi"
	.size	.L__unnamed_2, 65

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z11extend_stepPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi"
	.size	.L__unnamed_3, 76

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z28__device_stub__upwind_normalPdS_S_PKdS1_S1_S1_S1_S1_S1_iiidddi
	.addrsig_sym _Z35__device_stub__boundary_interpolatePdS_S_S_S_S_PKdS1_S1_S1_S1_S1_S1_iiidddi
	.addrsig_sym _Z26__device_stub__extend_stepPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z13upwind_normalPdS_S_PKdS1_S1_S1_S1_S1_S1_iiidddi
	.addrsig_sym _Z20boundary_interpolatePdS_S_S_S_S_PKdS1_S1_S1_S1_S1_S1_iiidddi
	.addrsig_sym _Z11extend_stepPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.p2align	2                               ; -- Begin function _Z24weno_onesided_derivativeddddd
	.type	_Z24weno_onesided_derivativeddddd,@function
_Z24weno_onesided_derivativeddddd:      ; @_Z24weno_onesided_derivativeddddd
; %bb.0:
	s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	s_or_saveexec_b32 s0, -1
	scratch_store_b32 off, v40, s32         ; 4-byte Folded Spill
	s_mov_b32 exec_lo, s0
	v_writelane_b32 v40, s34, 0
	v_writelane_b32 v40, s35, 1
	v_writelane_b32 v40, s36, 2
	v_writelane_b32 v40, s37, 3
	v_writelane_b32 v40, s38, 4
	v_writelane_b32 v40, s39, 5
	v_writelane_b32 v40, s40, 6
	v_writelane_b32 v40, s41, 7
	v_writelane_b32 v40, s42, 8
	v_writelane_b32 v40, s43, 9
	v_writelane_b32 v40, s44, 10
	v_writelane_b32 v40, s45, 11
	v_writelane_b32 v40, s46, 12
	v_writelane_b32 v40, s47, 13
	v_writelane_b32 v40, s48, 14
	v_writelane_b32 v40, s49, 15
	v_writelane_b32 v40, s50, 16
	v_writelane_b32 v40, s51, 17
	v_writelane_b32 v40, s52, 18
	v_writelane_b32 v40, s53, 19
	v_writelane_b32 v40, s54, 20
	v_writelane_b32 v40, s55, 21
	v_writelane_b32 v40, s56, 22
	v_writelane_b32 v40, s57, 23
	v_writelane_b32 v40, s58, 24
	v_writelane_b32 v40, s59, 25
	v_writelane_b32 v40, s60, 26
	v_writelane_b32 v40, s61, 27
	v_writelane_b32 v40, s30, 28
	v_writelane_b32 v40, s31, 29
	s_mov_b32 s1, 0xbff2aaaa
	s_mov_b32 s0, 0xaaaaaaab
	s_mov_b32 s29, 0x3fd55555
	v_mul_f64 v[10:11], v[2:3], s[0:1]
	s_mov_b32 s28, 0x55555555
	s_mov_b32 s3, 0x3ffd5555
	s_mov_b32 s2, s28
	v_fma_f64 v[16:17], v[2:3], -2.0, v[0:1]
	s_mov_b32 s1, 0x3feaaaaa
	s_mov_b32 s54, 0x968915a9
	s_mov_b32 s56, 0x4222de17
	s_mov_b32 s55, 0x3fba6564
	s_mov_b32 s57, 0x3fbdee67
	s_mov_b32 s52, 0x3abe935a
	s_mov_b32 s38, 0xfefa39ef
	s_mov_b32 s53, 0x3fbe25e4
	s_mov_b32 s39, 0x3fe62e42
	s_mov_b32 s50, 0x47e6c9c2
	s_mov_b32 s51, 0x3fc110ef
	s_mov_b32 s48, 0xcfa74449
	s_mov_b32 s40, 0x3b39803f
	s_mov_b32 s49, 0x3fc3b13b
	s_mov_b32 s41, 0x3c7abc9e
	s_mov_b32 s46, 0x71bf3c30
	s_mov_b32 s47, 0x3fc745d1
	s_mov_b32 s44, 0x1c7792ce
	s_mov_b32 s45, 0x3fcc71c7
	s_mov_b32 s42, 0x924920da
	s_mov_b32 s43, 0x3fd24924
	s_mov_b32 s36, 0x9999999c
	s_mov_b32 s37, 0x3fd99999
	s_mov_b32 s35, 0xbfe55555
	s_mov_b32 s34, s28
	s_mov_b32 s30, 0xd5df274d
	s_mov_b32 s31, 0x3c8543b0
	s_mov_b32 s26, 0x652b82fe
	s_mov_b32 s27, 0x3ff71547
	s_mov_b32 s19, 0xbfe62e42
	s_mov_b32 s18, s38
	s_mov_b32 s21, 0xbc7abc9e
	s_mov_b32 s20, s40
	v_fma_f64 v[10:11], v[0:1], s[28:29], v[10:11]
	s_mov_b32 s22, 0xfca7ab0c
	s_mov_b32 s24, 0x6a5dcb37
	s_mov_b32 s23, 0x3e928af3
	v_add_f64 v[16:17], v[16:17], v[4:5]
	s_mov_b32 s25, 0x3e5ade15
	s_mov_b32 s16, 0x623fde64
	s_mov_b32 s17, 0x3ec71dee
	s_mov_b32 s14, 0x7c89e6b0
	s_mov_b32 s15, 0x3efa0199
	s_mov_b32 s12, 0x14761f6e
	s_mov_b32 s13, 0x3f2a01a0
	s_mov_b32 s10, 0x1852b7b0
	s_mov_b32 s11, 0x3f56c16c
	s_mov_b32 s8, 0x11122322
	s_mov_b32 s9, 0x3f811111
	s_mov_b32 s6, 0x555502a1
	s_mov_b32 s7, 0x3fa55555
	s_mov_b32 s4, 0x55555511
	s_mov_b32 s5, 0x3fc55555
	v_fma_f64 v[0:1], v[2:3], -4.0, v[0:1]
	s_mov_b32 s59, 0x3ff15555
	s_mov_b32 s58, s28
	s_mov_b32 s61, 0x3fe33333
	s_mov_b32 s60, 0x33333333
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[10:11], v[4:5], s[2:3], v[10:11]
	s_mov_b32 s3, 0xbfc55555
	v_mul_f64 v[12:13], v[2:3], s[2:3]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_frexp_mant_f64_e64 v[18:19], |v[16:17]|
	v_fma_f64 v[0:1], 0x40080000, v[4:5], v[0:1]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[12:13], v[4:5], s[0:1], v[12:13]
	v_fma_f64 v[14:15], v[6:7], s[28:29], v[12:13]
	v_mul_f64 v[12:13], v[6:7], s[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[12:13], v[4:5], s[28:29], v[12:13]
	s_mov_b32 s29, 0x3fe55555
	v_cmp_gt_f64_e32 vcc_lo, s[28:29], v[18:19]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_fma_f64 v[12:13], v[8:9], s[2:3], v[12:13]
	s_mov_b32 s2, 11
	s_mov_b32 s3, 0x3fe00000
	v_cndmask_b32_e64 v20, 0, 1, vcc_lo
	v_ldexp_f64 v[18:19], v[18:19], v20
	v_frexp_exp_i32_f64_e32 v20, v[16:17]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[22:23], v[18:19], 1.0
	v_subrev_co_ci_u32_e32 v32, vcc_lo, 0, v20, vcc_lo
	v_add_f64 v[20:21], v[18:19], -1.0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[24:25], v[22:23], -1.0
	v_add_f64 v[18:19], v[18:19], -v[24:25]
	v_rcp_f64_e32 v[24:25], v[22:23]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[26:27], -v[22:23], v[24:25], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[24:25], v[26:27], v[24:25], v[24:25]
	v_fma_f64 v[26:27], -v[22:23], v[24:25], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[24:25], v[26:27], v[24:25], v[24:25]
	v_mul_f64 v[26:27], v[20:21], v[24:25]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[28:29], v[22:23], v[26:27]
	v_fma_f64 v[22:23], v[26:27], v[22:23], -v[28:29]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[18:19], v[26:27], v[18:19], v[22:23]
	v_add_f64 v[22:23], v[28:29], v[18:19]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[30:31], v[20:21], -v[22:23]
	v_add_f64 v[28:29], v[22:23], -v[28:29]
	v_add_f64 v[20:21], v[20:21], -v[30:31]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[18:19], v[28:29], -v[18:19]
	v_cvt_f64_i32_e32 v[28:29], v32
	v_add_f64 v[20:21], v[20:21], -v[22:23]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[18:19], v[18:19], v[20:21]
	v_add_f64 v[18:19], v[30:31], v[18:19]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[30:31], v[28:29], s[38:39]
	v_mul_f64 v[18:19], v[24:25], v[18:19]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[32:33], v[28:29], s[38:39], -v[30:31]
	v_add_f64 v[20:21], v[26:27], v[18:19]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[28:29], v[28:29], s[40:41], v[32:33]
	v_add_f64 v[22:23], v[20:21], -v[26:27]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[32:33], v[30:31], v[28:29]
	v_add_f64 v[18:19], v[18:19], -v[22:23]
	v_mul_f64 v[22:23], v[20:21], v[20:21]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[30:31], v[32:33], -v[30:31]
	v_add_f64 v[26:27], v[18:19], v[18:19]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_fma_f64 v[24:25], v[20:21], v[20:21], -v[22:23]
	v_ldexp_f64 v[34:35], v[18:19], 1
	v_add_f64 v[28:29], v[28:29], -v[30:31]
	v_ldexp_f64 v[30:31], v[20:21], 1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[24:25], v[20:21], v[26:27], v[24:25]
	v_add_f64 v[26:27], v[22:23], v[24:25]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[22:23], v[26:27], -v[22:23]
	v_mul_f64 v[36:37], v[20:21], v[26:27]
	v_add_f64 v[22:23], v[24:25], -v[22:23]
	v_fma_f64 v[24:25], v[26:27], s[56:57], s[54:55]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[38:39], v[26:27], v[20:21], -v[36:37]
	v_fma_f64 v[24:25], v[26:27], v[24:25], s[52:53]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[18:19], v[26:27], v[18:19], v[38:39]
	v_fma_f64 v[24:25], v[26:27], v[24:25], s[50:51]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[18:19], v[22:23], v[20:21], v[18:19]
	v_fma_f64 v[24:25], v[26:27], v[24:25], s[48:49]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[20:21], v[36:37], v[18:19]
	v_fma_f64 v[24:25], v[26:27], v[24:25], s[46:47]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[36:37], v[20:21], -v[36:37]
	v_fma_f64 v[24:25], v[26:27], v[24:25], s[44:45]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[18:19], v[18:19], -v[36:37]
	v_fma_f64 v[24:25], v[26:27], v[24:25], s[42:43]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[24:25], v[26:27], v[24:25], s[36:37]
	v_mul_f64 v[36:37], v[26:27], v[24:25]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[26:27], v[26:27], v[24:25], -v[36:37]
	v_fma_f64 v[22:23], v[22:23], v[24:25], v[26:27]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[24:25], v[36:37], v[22:23]
	v_add_f64 v[26:27], v[24:25], -v[36:37]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[22:23], v[22:23], -v[26:27]
	v_add_f64 v[26:27], v[24:25], s[28:29]
	v_add_f64 v[22:23], v[22:23], s[30:31]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[36:37], v[26:27], s[34:35]
	v_add_f64 v[24:25], v[24:25], -v[36:37]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[22:23], v[22:23], v[24:25]
	v_add_f64 v[24:25], v[26:27], v[22:23]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[26:27], v[26:27], -v[24:25]
	v_add_f64 v[22:23], v[22:23], v[26:27]
	v_mul_f64 v[26:27], v[20:21], v[24:25]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[36:37], v[20:21], v[24:25], -v[26:27]
	v_fma_f64 v[20:21], v[20:21], v[22:23], v[36:37]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[18:19], v[18:19], v[24:25], v[20:21]
	v_add_f64 v[20:21], v[26:27], v[18:19]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[22:23], v[20:21], -v[26:27]
	v_add_f64 v[18:19], v[18:19], -v[22:23]
	v_add_f64 v[22:23], v[30:31], v[20:21]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[18:19], v[34:35], v[18:19]
	v_add_f64 v[24:25], v[22:23], -v[30:31]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[20:21], v[20:21], -v[24:25]
	v_add_f64 v[18:19], v[18:19], v[20:21]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[20:21], v[22:23], v[18:19]
	v_add_f64 v[22:23], v[20:21], -v[22:23]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f64 v[18:19], v[18:19], -v[22:23]
	v_add_f64 v[22:23], v[32:33], v[20:21]
	v_add_f64 v[24:25], v[22:23], -v[32:33]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_add_f64 v[26:27], v[22:23], -v[24:25]
	v_add_f64 v[20:21], v[20:21], -v[24:25]
	v_add_f64 v[24:25], v[28:29], v[18:19]
	v_add_f64 v[26:27], v[32:33], -v[26:27]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[20:21], v[20:21], v[26:27]
	v_add_f64 v[26:27], v[24:25], -v[28:29]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[20:21], v[24:25], v[20:21]
	v_add_f64 v[30:31], v[24:25], -v[26:27]
	v_add_f64 v[18:19], v[18:19], -v[26:27]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[24:25], v[22:23], v[20:21]
	v_add_f64 v[28:29], v[28:29], -v[30:31]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[22:23], v[24:25], -v[22:23]
	v_add_f64 v[18:19], v[18:19], v[28:29]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[20:21], v[20:21], -v[22:23]
	v_add_f64 v[18:19], v[18:19], v[20:21]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[20:21], v[24:25], v[18:19]
	v_add_f64 v[22:23], v[20:21], -v[24:25]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f64 v[18:19], v[18:19], -v[22:23]
	v_add_f64 v[22:23], v[20:21], v[20:21]
	v_fma_f64 v[20:21], v[20:21], 2.0, -v[22:23]
	v_cmp_class_f64_e64 vcc_lo, v[22:23], 0x204
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[18:19], v[18:19], 2.0, v[20:21]
	v_add_f64 v[20:21], v[22:23], v[18:19]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f64 v[24:25], v[20:21], -v[22:23]
	v_dual_cndmask_b32 v21, v21, v23 :: v_dual_cndmask_b32 v20, v20, v22
	v_mul_f64 v[22:23], v[20:21], s[26:27]
	v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[20:21]|
	v_cmp_ngt_f64_e64 s0, 0xc090cc00, v[20:21]
	v_add_f64 v[18:19], v[18:19], -v[24:25]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rndne_f64_e32 v[22:23], v[22:23]
	v_dual_cndmask_b32 v19, 0, v19 :: v_dual_cndmask_b32 v18, 0, v18
	v_cmp_nlt_f64_e32 vcc_lo, 0x40900000, v[20:21]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[24:25], v[22:23], s[18:19], v[20:21]
	v_fma_f64 v[24:25], v[22:23], s[20:21], v[24:25]
	v_cvt_i32_f64_e32 v22, v[22:23]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[26:27], v[24:25], s[24:25], s[22:23]
	v_fma_f64 v[26:27], v[24:25], v[26:27], s[16:17]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[26:27], v[24:25], v[26:27], s[14:15]
	v_fma_f64 v[26:27], v[24:25], v[26:27], s[12:13]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[26:27], v[24:25], v[26:27], s[10:11]
	v_fma_f64 v[26:27], v[24:25], v[26:27], s[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[26:27], v[24:25], v[26:27], s[6:7]
	v_fma_f64 v[26:27], v[24:25], v[26:27], s[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[26:27], v[24:25], v[26:27], s[2:3]
	v_fma_f64 v[26:27], v[24:25], v[26:27], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[24:25], v[24:25], v[26:27], 1.0
	v_ldexp_f64 v[22:23], v[24:25], v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v23, 0x7ff00000, v23, vcc_lo
	s_and_b32 vcc_lo, s0, vcc_lo
	v_cndmask_b32_e64 v21, 0, v23, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v20, 0, v22, vcc_lo
	v_cmp_neq_f64_e64 s0, 0, v[16:17]
	v_fma_f64 v[18:19], v[20:21], v[18:19], v[20:21]
	v_cmp_class_f64_e64 vcc_lo, v[20:21], 0x204
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_dual_cndmask_b32 v19, v19, v21 :: v_dual_cndmask_b32 v18, v18, v20
	v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[16:17]|
	v_frexp_mant_f64_e64 v[20:21], |v[0:1]|
	v_mul_f64 v[16:17], 0x40080000, v[4:5]
	v_mul_f64 v[18:19], |v[18:19]|, s[58:59]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v19, 0x7ff00000, v19, vcc_lo
	s_and_b32 vcc_lo, s0, vcc_lo
	v_cndmask_b32_e32 v18, 0, v18, vcc_lo
	v_cmp_gt_f64_e32 vcc_lo, s[28:29], v[20:21]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v19, 0, v19, s0
	v_cndmask_b32_e64 v22, 0, 1, vcc_lo
	v_ldexp_f64 v[20:21], v[20:21], v22
	v_frexp_exp_i32_f64_e32 v22, v[0:1]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[24:25], v[20:21], 1.0
	v_subrev_co_ci_u32_e32 v34, vcc_lo, 0, v22, vcc_lo
	v_add_f64 v[22:23], v[20:21], -1.0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[26:27], v[24:25], -1.0
	v_add_f64 v[20:21], v[20:21], -v[26:27]
	v_rcp_f64_e32 v[26:27], v[24:25]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[28:29], -v[24:25], v[26:27], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[26:27], v[28:29], v[26:27], v[26:27]
	v_fma_f64 v[28:29], -v[24:25], v[26:27], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[26:27], v[28:29], v[26:27], v[26:27]
	v_mul_f64 v[28:29], v[22:23], v[26:27]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[30:31], v[24:25], v[28:29]
	v_fma_f64 v[24:25], v[28:29], v[24:25], -v[30:31]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[20:21], v[28:29], v[20:21], v[24:25]
	v_add_f64 v[24:25], v[30:31], v[20:21]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[32:33], v[22:23], -v[24:25]
	v_add_f64 v[30:31], v[24:25], -v[30:31]
	v_add_f64 v[22:23], v[22:23], -v[32:33]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[20:21], v[30:31], -v[20:21]
	v_cvt_f64_i32_e32 v[30:31], v34
	v_add_f64 v[22:23], v[22:23], -v[24:25]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[20:21], v[20:21], v[22:23]
	v_add_f64 v[20:21], v[32:33], v[20:21]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[32:33], v[30:31], s[38:39]
	v_mul_f64 v[20:21], v[26:27], v[20:21]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[34:35], v[30:31], s[38:39], -v[32:33]
	v_add_f64 v[22:23], v[28:29], v[20:21]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[30:31], v[30:31], s[40:41], v[34:35]
	v_add_f64 v[24:25], v[22:23], -v[28:29]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[34:35], v[32:33], v[30:31]
	v_add_f64 v[20:21], v[20:21], -v[24:25]
	v_mul_f64 v[24:25], v[22:23], v[22:23]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[32:33], v[34:35], -v[32:33]
	v_add_f64 v[28:29], v[20:21], v[20:21]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_fma_f64 v[26:27], v[22:23], v[22:23], -v[24:25]
	v_ldexp_f64 v[36:37], v[20:21], 1
	v_add_f64 v[30:31], v[30:31], -v[32:33]
	v_ldexp_f64 v[32:33], v[22:23], 1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[26:27], v[22:23], v[28:29], v[26:27]
	v_add_f64 v[28:29], v[24:25], v[26:27]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[24:25], v[28:29], -v[24:25]
	v_mul_f64 v[38:39], v[22:23], v[28:29]
	v_add_f64 v[24:25], v[26:27], -v[24:25]
	v_fma_f64 v[26:27], v[28:29], s[56:57], s[54:55]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[48:49], v[28:29], v[22:23], -v[38:39]
	v_fma_f64 v[26:27], v[28:29], v[26:27], s[52:53]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[20:21], v[28:29], v[20:21], v[48:49]
	v_fma_f64 v[26:27], v[28:29], v[26:27], s[50:51]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[20:21], v[24:25], v[22:23], v[20:21]
	v_fma_f64 v[26:27], v[28:29], v[26:27], s[48:49]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[22:23], v[38:39], v[20:21]
	v_fma_f64 v[26:27], v[28:29], v[26:27], s[46:47]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[38:39], v[22:23], -v[38:39]
	v_fma_f64 v[26:27], v[28:29], v[26:27], s[44:45]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[20:21], v[20:21], -v[38:39]
	v_fma_f64 v[26:27], v[28:29], v[26:27], s[42:43]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[26:27], v[28:29], v[26:27], s[36:37]
	v_mul_f64 v[38:39], v[28:29], v[26:27]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[28:29], v[28:29], v[26:27], -v[38:39]
	v_fma_f64 v[24:25], v[24:25], v[26:27], v[28:29]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[26:27], v[38:39], v[24:25]
	v_add_f64 v[28:29], v[26:27], -v[38:39]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[24:25], v[24:25], -v[28:29]
	v_add_f64 v[28:29], v[26:27], s[28:29]
	v_add_f64 v[24:25], v[24:25], s[30:31]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[38:39], v[28:29], s[34:35]
	v_add_f64 v[26:27], v[26:27], -v[38:39]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[24:25], v[24:25], v[26:27]
	v_add_f64 v[26:27], v[28:29], v[24:25]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[28:29], v[28:29], -v[26:27]
	v_add_f64 v[24:25], v[24:25], v[28:29]
	v_mul_f64 v[28:29], v[22:23], v[26:27]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[38:39], v[22:23], v[26:27], -v[28:29]
	v_fma_f64 v[22:23], v[22:23], v[24:25], v[38:39]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[20:21], v[20:21], v[26:27], v[22:23]
	v_add_f64 v[22:23], v[28:29], v[20:21]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[24:25], v[22:23], -v[28:29]
	v_add_f64 v[20:21], v[20:21], -v[24:25]
	v_add_f64 v[24:25], v[32:33], v[22:23]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[20:21], v[36:37], v[20:21]
	v_add_f64 v[26:27], v[24:25], -v[32:33]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[22:23], v[22:23], -v[26:27]
	v_add_f64 v[20:21], v[20:21], v[22:23]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[22:23], v[24:25], v[20:21]
	v_add_f64 v[24:25], v[22:23], -v[24:25]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f64 v[20:21], v[20:21], -v[24:25]
	v_add_f64 v[24:25], v[34:35], v[22:23]
	v_add_f64 v[26:27], v[24:25], -v[34:35]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_add_f64 v[28:29], v[24:25], -v[26:27]
	v_add_f64 v[22:23], v[22:23], -v[26:27]
	v_add_f64 v[26:27], v[30:31], v[20:21]
	v_add_f64 v[28:29], v[34:35], -v[28:29]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[22:23], v[22:23], v[28:29]
	v_add_f64 v[28:29], v[26:27], -v[30:31]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[22:23], v[26:27], v[22:23]
	v_add_f64 v[32:33], v[26:27], -v[28:29]
	v_add_f64 v[20:21], v[20:21], -v[28:29]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[26:27], v[24:25], v[22:23]
	v_add_f64 v[30:31], v[30:31], -v[32:33]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[24:25], v[26:27], -v[24:25]
	v_add_f64 v[20:21], v[20:21], v[30:31]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[22:23], v[22:23], -v[24:25]
	v_add_f64 v[20:21], v[20:21], v[22:23]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[22:23], v[26:27], v[20:21]
	v_add_f64 v[24:25], v[22:23], -v[26:27]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f64 v[20:21], v[20:21], -v[24:25]
	v_add_f64 v[24:25], v[22:23], v[22:23]
	v_fma_f64 v[22:23], v[22:23], 2.0, -v[24:25]
	v_cmp_class_f64_e64 vcc_lo, v[24:25], 0x204
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[20:21], v[20:21], 2.0, v[22:23]
	v_add_f64 v[22:23], v[24:25], v[20:21]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f64 v[26:27], v[22:23], -v[24:25]
	v_dual_cndmask_b32 v23, v23, v25 :: v_dual_cndmask_b32 v22, v22, v24
	v_mul_f64 v[24:25], v[22:23], s[26:27]
	v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[22:23]|
	v_cmp_ngt_f64_e64 s0, 0xc090cc00, v[22:23]
	v_add_f64 v[20:21], v[20:21], -v[26:27]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rndne_f64_e32 v[24:25], v[24:25]
	v_dual_cndmask_b32 v21, 0, v21 :: v_dual_cndmask_b32 v20, 0, v20
	v_cmp_nlt_f64_e32 vcc_lo, 0x40900000, v[22:23]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[26:27], v[24:25], s[18:19], v[22:23]
	v_fma_f64 v[26:27], v[24:25], s[20:21], v[26:27]
	v_cvt_i32_f64_e32 v24, v[24:25]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[28:29], v[26:27], s[24:25], s[22:23]
	v_fma_f64 v[28:29], v[26:27], v[28:29], s[16:17]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[28:29], v[26:27], v[28:29], s[14:15]
	v_fma_f64 v[28:29], v[26:27], v[28:29], s[12:13]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[28:29], v[26:27], v[28:29], s[10:11]
	v_fma_f64 v[28:29], v[26:27], v[28:29], s[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[28:29], v[26:27], v[28:29], s[6:7]
	v_fma_f64 v[28:29], v[26:27], v[28:29], s[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[28:29], v[26:27], v[28:29], s[2:3]
	v_fma_f64 v[28:29], v[26:27], v[28:29], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[26:27], v[26:27], v[28:29], 1.0
	v_ldexp_f64 v[24:25], v[26:27], v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v25, 0x7ff00000, v25, vcc_lo
	s_and_b32 vcc_lo, s0, vcc_lo
	v_cndmask_b32_e32 v22, 0, v24, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v23, 0, v25, s0
	v_cmp_neq_f64_e64 s0, 0, v[0:1]
	v_fma_f64 v[20:21], v[22:23], v[20:21], v[22:23]
	v_cmp_class_f64_e64 vcc_lo, v[22:23], 0x204
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v21, v21, v23 :: v_dual_cndmask_b32 v20, v20, v22
	v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[0:1]|
	v_ldexp_f64 v[20:21], |v[20:21]|, -2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v21, 0x7ff00000, v21, vcc_lo
	s_and_b32 vcc_lo, s0, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v0, 0, v20, vcc_lo
	v_cndmask_b32_e64 v1, 0, v21, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_add_f64 v[0:1], v[18:19], v[0:1]
	v_fma_f64 v[18:19], v[4:5], -2.0, v[2:3]
	v_add_f64 v[2:3], v[2:3], -v[6:7]
	v_fma_f64 v[4:5], v[6:7], -2.0, v[4:5]
	v_add_f64 v[18:19], v[18:19], v[6:7]
	v_fma_f64 v[6:7], v[6:7], -4.0, v[16:17]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[4:5], v[4:5], v[8:9]
	v_frexp_mant_f64_e64 v[20:21], |v[18:19]|
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[6:7], v[6:7], v[8:9]
	v_cmp_gt_f64_e32 vcc_lo, s[28:29], v[20:21]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_frexp_mant_f64_e64 v[8:9], |v[6:7]|
	v_cndmask_b32_e64 v22, 0, 1, vcc_lo
	v_ldexp_f64 v[20:21], v[20:21], v22
	v_frexp_exp_i32_f64_e32 v22, v[18:19]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[24:25], v[20:21], 1.0
	v_subrev_co_ci_u32_e32 v34, vcc_lo, 0, v22, vcc_lo
	v_add_f64 v[22:23], v[20:21], -1.0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[26:27], v[24:25], -1.0
	v_add_f64 v[20:21], v[20:21], -v[26:27]
	v_rcp_f64_e32 v[26:27], v[24:25]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[28:29], -v[24:25], v[26:27], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[26:27], v[28:29], v[26:27], v[26:27]
	v_fma_f64 v[28:29], -v[24:25], v[26:27], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[26:27], v[28:29], v[26:27], v[26:27]
	v_mul_f64 v[28:29], v[22:23], v[26:27]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[30:31], v[24:25], v[28:29]
	v_fma_f64 v[24:25], v[28:29], v[24:25], -v[30:31]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[20:21], v[28:29], v[20:21], v[24:25]
	v_add_f64 v[24:25], v[30:31], v[20:21]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[32:33], v[22:23], -v[24:25]
	v_add_f64 v[30:31], v[24:25], -v[30:31]
	v_add_f64 v[22:23], v[22:23], -v[32:33]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[20:21], v[30:31], -v[20:21]
	v_cvt_f64_i32_e32 v[30:31], v34
	v_add_f64 v[22:23], v[22:23], -v[24:25]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[20:21], v[20:21], v[22:23]
	v_add_f64 v[20:21], v[32:33], v[20:21]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[32:33], v[30:31], s[38:39]
	v_mul_f64 v[20:21], v[26:27], v[20:21]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[34:35], v[30:31], s[38:39], -v[32:33]
	v_add_f64 v[22:23], v[28:29], v[20:21]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[30:31], v[30:31], s[40:41], v[34:35]
	v_add_f64 v[24:25], v[22:23], -v[28:29]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[34:35], v[32:33], v[30:31]
	v_add_f64 v[20:21], v[20:21], -v[24:25]
	v_mul_f64 v[24:25], v[22:23], v[22:23]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[32:33], v[34:35], -v[32:33]
	v_add_f64 v[28:29], v[20:21], v[20:21]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_fma_f64 v[26:27], v[22:23], v[22:23], -v[24:25]
	v_ldexp_f64 v[36:37], v[20:21], 1
	v_add_f64 v[30:31], v[30:31], -v[32:33]
	v_ldexp_f64 v[32:33], v[22:23], 1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[26:27], v[22:23], v[28:29], v[26:27]
	v_add_f64 v[28:29], v[24:25], v[26:27]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[24:25], v[28:29], -v[24:25]
	v_mul_f64 v[38:39], v[22:23], v[28:29]
	v_add_f64 v[24:25], v[26:27], -v[24:25]
	v_fma_f64 v[26:27], v[28:29], s[56:57], s[54:55]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[48:49], v[28:29], v[22:23], -v[38:39]
	v_fma_f64 v[26:27], v[28:29], v[26:27], s[52:53]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[20:21], v[28:29], v[20:21], v[48:49]
	v_fma_f64 v[26:27], v[28:29], v[26:27], s[50:51]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[20:21], v[24:25], v[22:23], v[20:21]
	v_fma_f64 v[26:27], v[28:29], v[26:27], s[48:49]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[22:23], v[38:39], v[20:21]
	v_fma_f64 v[26:27], v[28:29], v[26:27], s[46:47]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[38:39], v[22:23], -v[38:39]
	v_fma_f64 v[26:27], v[28:29], v[26:27], s[44:45]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[20:21], v[20:21], -v[38:39]
	v_fma_f64 v[26:27], v[28:29], v[26:27], s[42:43]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[26:27], v[28:29], v[26:27], s[36:37]
	v_mul_f64 v[38:39], v[28:29], v[26:27]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[28:29], v[28:29], v[26:27], -v[38:39]
	v_fma_f64 v[24:25], v[24:25], v[26:27], v[28:29]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[26:27], v[38:39], v[24:25]
	v_add_f64 v[28:29], v[26:27], -v[38:39]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[24:25], v[24:25], -v[28:29]
	v_add_f64 v[28:29], v[26:27], s[28:29]
	v_add_f64 v[24:25], v[24:25], s[30:31]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[38:39], v[28:29], s[34:35]
	v_add_f64 v[26:27], v[26:27], -v[38:39]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[24:25], v[24:25], v[26:27]
	v_add_f64 v[26:27], v[28:29], v[24:25]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[28:29], v[28:29], -v[26:27]
	v_add_f64 v[24:25], v[24:25], v[28:29]
	v_mul_f64 v[28:29], v[22:23], v[26:27]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[38:39], v[22:23], v[26:27], -v[28:29]
	v_fma_f64 v[22:23], v[22:23], v[24:25], v[38:39]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[20:21], v[20:21], v[26:27], v[22:23]
	v_add_f64 v[22:23], v[28:29], v[20:21]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[24:25], v[22:23], -v[28:29]
	v_add_f64 v[20:21], v[20:21], -v[24:25]
	v_add_f64 v[24:25], v[32:33], v[22:23]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[20:21], v[36:37], v[20:21]
	v_add_f64 v[26:27], v[24:25], -v[32:33]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[22:23], v[22:23], -v[26:27]
	v_add_f64 v[20:21], v[20:21], v[22:23]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[22:23], v[24:25], v[20:21]
	v_add_f64 v[24:25], v[22:23], -v[24:25]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f64 v[20:21], v[20:21], -v[24:25]
	v_add_f64 v[24:25], v[34:35], v[22:23]
	v_add_f64 v[26:27], v[24:25], -v[34:35]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_add_f64 v[28:29], v[24:25], -v[26:27]
	v_add_f64 v[22:23], v[22:23], -v[26:27]
	v_add_f64 v[26:27], v[30:31], v[20:21]
	v_add_f64 v[28:29], v[34:35], -v[28:29]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[22:23], v[22:23], v[28:29]
	v_add_f64 v[28:29], v[26:27], -v[30:31]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[22:23], v[26:27], v[22:23]
	v_add_f64 v[32:33], v[26:27], -v[28:29]
	v_add_f64 v[20:21], v[20:21], -v[28:29]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[26:27], v[24:25], v[22:23]
	v_add_f64 v[30:31], v[30:31], -v[32:33]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[24:25], v[26:27], -v[24:25]
	v_add_f64 v[20:21], v[20:21], v[30:31]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[22:23], v[22:23], -v[24:25]
	v_add_f64 v[20:21], v[20:21], v[22:23]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[22:23], v[26:27], v[20:21]
	v_add_f64 v[24:25], v[22:23], -v[26:27]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f64 v[20:21], v[20:21], -v[24:25]
	v_add_f64 v[24:25], v[22:23], v[22:23]
	v_fma_f64 v[22:23], v[22:23], 2.0, -v[24:25]
	v_cmp_class_f64_e64 vcc_lo, v[24:25], 0x204
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[20:21], v[20:21], 2.0, v[22:23]
	v_add_f64 v[22:23], v[24:25], v[20:21]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f64 v[26:27], v[22:23], -v[24:25]
	v_dual_cndmask_b32 v23, v23, v25 :: v_dual_cndmask_b32 v22, v22, v24
	v_mul_f64 v[24:25], v[22:23], s[26:27]
	v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[22:23]|
	v_cmp_ngt_f64_e64 s0, 0xc090cc00, v[22:23]
	v_add_f64 v[20:21], v[20:21], -v[26:27]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rndne_f64_e32 v[24:25], v[24:25]
	v_dual_cndmask_b32 v21, 0, v21 :: v_dual_cndmask_b32 v20, 0, v20
	v_cmp_nlt_f64_e32 vcc_lo, 0x40900000, v[22:23]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[26:27], v[24:25], s[18:19], v[22:23]
	v_fma_f64 v[26:27], v[24:25], s[20:21], v[26:27]
	v_cvt_i32_f64_e32 v24, v[24:25]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[28:29], v[26:27], s[24:25], s[22:23]
	v_fma_f64 v[28:29], v[26:27], v[28:29], s[16:17]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[28:29], v[26:27], v[28:29], s[14:15]
	v_fma_f64 v[28:29], v[26:27], v[28:29], s[12:13]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[28:29], v[26:27], v[28:29], s[10:11]
	v_fma_f64 v[28:29], v[26:27], v[28:29], s[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[28:29], v[26:27], v[28:29], s[6:7]
	v_fma_f64 v[28:29], v[26:27], v[28:29], s[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[28:29], v[26:27], v[28:29], s[2:3]
	v_fma_f64 v[28:29], v[26:27], v[28:29], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[26:27], v[26:27], v[28:29], 1.0
	v_ldexp_f64 v[24:25], v[26:27], v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v25, 0x7ff00000, v25, vcc_lo
	s_and_b32 vcc_lo, s0, vcc_lo
	v_cndmask_b32_e32 v22, 0, v24, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v23, 0, v25, s0
	v_cmp_neq_f64_e64 s0, 0, v[18:19]
	v_fma_f64 v[20:21], v[22:23], v[20:21], v[22:23]
	v_cmp_class_f64_e64 vcc_lo, v[22:23], 0x204
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v21, v21, v23 :: v_dual_cndmask_b32 v20, v20, v22
	v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[18:19]|
	v_mul_f64 v[20:21], |v[20:21]|, s[58:59]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v21, 0x7ff00000, v21, vcc_lo
	s_and_b32 vcc_lo, s0, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v18, 0, v20, vcc_lo
	v_cndmask_b32_e64 v19, 0, v21, s0
	v_frexp_mant_f64_e64 v[20:21], |v[2:3]|
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_gt_f64_e32 vcc_lo, s[28:29], v[20:21]
	v_cndmask_b32_e64 v22, 0, 1, vcc_lo
	v_ldexp_f64 v[20:21], v[20:21], v22
	v_frexp_exp_i32_f64_e32 v22, v[2:3]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[24:25], v[20:21], 1.0
	v_subrev_co_ci_u32_e32 v34, vcc_lo, 0, v22, vcc_lo
	v_add_f64 v[22:23], v[20:21], -1.0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[26:27], v[24:25], -1.0
	v_add_f64 v[20:21], v[20:21], -v[26:27]
	v_rcp_f64_e32 v[26:27], v[24:25]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[28:29], -v[24:25], v[26:27], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[26:27], v[28:29], v[26:27], v[26:27]
	v_fma_f64 v[28:29], -v[24:25], v[26:27], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[26:27], v[28:29], v[26:27], v[26:27]
	v_mul_f64 v[28:29], v[22:23], v[26:27]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[30:31], v[24:25], v[28:29]
	v_fma_f64 v[24:25], v[28:29], v[24:25], -v[30:31]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[20:21], v[28:29], v[20:21], v[24:25]
	v_add_f64 v[24:25], v[30:31], v[20:21]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[32:33], v[22:23], -v[24:25]
	v_add_f64 v[30:31], v[24:25], -v[30:31]
	v_add_f64 v[22:23], v[22:23], -v[32:33]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[20:21], v[30:31], -v[20:21]
	v_cvt_f64_i32_e32 v[30:31], v34
	v_add_f64 v[22:23], v[22:23], -v[24:25]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[20:21], v[20:21], v[22:23]
	v_add_f64 v[20:21], v[32:33], v[20:21]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[32:33], v[30:31], s[38:39]
	v_mul_f64 v[20:21], v[26:27], v[20:21]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[34:35], v[30:31], s[38:39], -v[32:33]
	v_add_f64 v[22:23], v[28:29], v[20:21]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[30:31], v[30:31], s[40:41], v[34:35]
	v_add_f64 v[24:25], v[22:23], -v[28:29]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[34:35], v[32:33], v[30:31]
	v_add_f64 v[20:21], v[20:21], -v[24:25]
	v_mul_f64 v[24:25], v[22:23], v[22:23]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[32:33], v[34:35], -v[32:33]
	v_add_f64 v[28:29], v[20:21], v[20:21]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_fma_f64 v[26:27], v[22:23], v[22:23], -v[24:25]
	v_ldexp_f64 v[36:37], v[20:21], 1
	v_add_f64 v[30:31], v[30:31], -v[32:33]
	v_ldexp_f64 v[32:33], v[22:23], 1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[26:27], v[22:23], v[28:29], v[26:27]
	v_add_f64 v[28:29], v[24:25], v[26:27]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[24:25], v[28:29], -v[24:25]
	v_mul_f64 v[38:39], v[22:23], v[28:29]
	v_add_f64 v[24:25], v[26:27], -v[24:25]
	v_fma_f64 v[26:27], v[28:29], s[56:57], s[54:55]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[48:49], v[28:29], v[22:23], -v[38:39]
	v_fma_f64 v[26:27], v[28:29], v[26:27], s[52:53]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[20:21], v[28:29], v[20:21], v[48:49]
	v_fma_f64 v[26:27], v[28:29], v[26:27], s[50:51]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[20:21], v[24:25], v[22:23], v[20:21]
	v_fma_f64 v[26:27], v[28:29], v[26:27], s[48:49]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[22:23], v[38:39], v[20:21]
	v_fma_f64 v[26:27], v[28:29], v[26:27], s[46:47]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[38:39], v[22:23], -v[38:39]
	v_fma_f64 v[26:27], v[28:29], v[26:27], s[44:45]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[20:21], v[20:21], -v[38:39]
	v_fma_f64 v[26:27], v[28:29], v[26:27], s[42:43]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[26:27], v[28:29], v[26:27], s[36:37]
	v_mul_f64 v[38:39], v[28:29], v[26:27]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[28:29], v[28:29], v[26:27], -v[38:39]
	v_fma_f64 v[24:25], v[24:25], v[26:27], v[28:29]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[26:27], v[38:39], v[24:25]
	v_add_f64 v[28:29], v[26:27], -v[38:39]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[24:25], v[24:25], -v[28:29]
	v_add_f64 v[28:29], v[26:27], s[28:29]
	v_add_f64 v[24:25], v[24:25], s[30:31]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[38:39], v[28:29], s[34:35]
	v_add_f64 v[26:27], v[26:27], -v[38:39]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[24:25], v[24:25], v[26:27]
	v_add_f64 v[26:27], v[28:29], v[24:25]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[28:29], v[28:29], -v[26:27]
	v_add_f64 v[24:25], v[24:25], v[28:29]
	v_mul_f64 v[28:29], v[22:23], v[26:27]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[38:39], v[22:23], v[26:27], -v[28:29]
	v_fma_f64 v[22:23], v[22:23], v[24:25], v[38:39]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[20:21], v[20:21], v[26:27], v[22:23]
	v_add_f64 v[22:23], v[28:29], v[20:21]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[24:25], v[22:23], -v[28:29]
	v_add_f64 v[20:21], v[20:21], -v[24:25]
	v_add_f64 v[24:25], v[32:33], v[22:23]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[20:21], v[36:37], v[20:21]
	v_add_f64 v[26:27], v[24:25], -v[32:33]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[22:23], v[22:23], -v[26:27]
	v_add_f64 v[20:21], v[20:21], v[22:23]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[22:23], v[24:25], v[20:21]
	v_add_f64 v[24:25], v[22:23], -v[24:25]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f64 v[20:21], v[20:21], -v[24:25]
	v_add_f64 v[24:25], v[34:35], v[22:23]
	v_add_f64 v[26:27], v[24:25], -v[34:35]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_add_f64 v[28:29], v[24:25], -v[26:27]
	v_add_f64 v[22:23], v[22:23], -v[26:27]
	v_add_f64 v[26:27], v[30:31], v[20:21]
	v_add_f64 v[28:29], v[34:35], -v[28:29]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[22:23], v[22:23], v[28:29]
	v_add_f64 v[28:29], v[26:27], -v[30:31]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[22:23], v[26:27], v[22:23]
	v_add_f64 v[32:33], v[26:27], -v[28:29]
	v_add_f64 v[20:21], v[20:21], -v[28:29]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[26:27], v[24:25], v[22:23]
	v_add_f64 v[30:31], v[30:31], -v[32:33]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[24:25], v[26:27], -v[24:25]
	v_add_f64 v[20:21], v[20:21], v[30:31]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[22:23], v[22:23], -v[24:25]
	v_add_f64 v[20:21], v[20:21], v[22:23]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[22:23], v[26:27], v[20:21]
	v_add_f64 v[24:25], v[22:23], -v[26:27]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f64 v[20:21], v[20:21], -v[24:25]
	v_add_f64 v[24:25], v[22:23], v[22:23]
	v_fma_f64 v[22:23], v[22:23], 2.0, -v[24:25]
	v_cmp_class_f64_e64 vcc_lo, v[24:25], 0x204
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[20:21], v[20:21], 2.0, v[22:23]
	v_add_f64 v[22:23], v[24:25], v[20:21]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f64 v[26:27], v[22:23], -v[24:25]
	v_dual_cndmask_b32 v23, v23, v25 :: v_dual_cndmask_b32 v22, v22, v24
	v_mul_f64 v[24:25], v[22:23], s[26:27]
	v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[22:23]|
	v_cmp_ngt_f64_e64 s0, 0xc090cc00, v[22:23]
	v_add_f64 v[20:21], v[20:21], -v[26:27]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rndne_f64_e32 v[24:25], v[24:25]
	v_dual_cndmask_b32 v21, 0, v21 :: v_dual_cndmask_b32 v20, 0, v20
	v_cmp_nlt_f64_e32 vcc_lo, 0x40900000, v[22:23]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[26:27], v[24:25], s[18:19], v[22:23]
	v_fma_f64 v[26:27], v[24:25], s[20:21], v[26:27]
	v_cvt_i32_f64_e32 v24, v[24:25]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[28:29], v[26:27], s[24:25], s[22:23]
	v_fma_f64 v[28:29], v[26:27], v[28:29], s[16:17]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[28:29], v[26:27], v[28:29], s[14:15]
	v_fma_f64 v[28:29], v[26:27], v[28:29], s[12:13]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[28:29], v[26:27], v[28:29], s[10:11]
	v_fma_f64 v[28:29], v[26:27], v[28:29], s[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[28:29], v[26:27], v[28:29], s[6:7]
	v_fma_f64 v[28:29], v[26:27], v[28:29], s[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[28:29], v[26:27], v[28:29], s[2:3]
	v_fma_f64 v[28:29], v[26:27], v[28:29], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[26:27], v[26:27], v[28:29], 1.0
	v_ldexp_f64 v[24:25], v[26:27], v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v25, 0x7ff00000, v25, vcc_lo
	s_and_b32 vcc_lo, s0, vcc_lo
	v_cndmask_b32_e32 v22, 0, v24, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v23, 0, v25, s0
	v_cmp_neq_f64_e64 s0, 0, v[2:3]
	v_fma_f64 v[20:21], v[22:23], v[20:21], v[22:23]
	v_cmp_class_f64_e64 vcc_lo, v[22:23], 0x204
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v21, v21, v23 :: v_dual_cndmask_b32 v20, v20, v22
	v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[2:3]|
	v_ldexp_f64 v[20:21], |v[20:21]|, -2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v21, 0x7ff00000, v21, vcc_lo
	s_and_b32 vcc_lo, s0, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v2, 0, v20, vcc_lo
	v_cndmask_b32_e64 v3, 0, v21, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f64 v[2:3], v[2:3], v[18:19]
	v_frexp_mant_f64_e64 v[18:19], |v[4:5]|
	v_cmp_gt_f64_e32 vcc_lo, s[28:29], v[18:19]
	v_cndmask_b32_e64 v20, 0, 1, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_ldexp_f64 v[18:19], v[18:19], v20
	v_frexp_exp_i32_f64_e32 v20, v[4:5]
	v_add_f64 v[22:23], v[18:19], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_subrev_co_ci_u32_e32 v32, vcc_lo, 0, v20, vcc_lo
	v_add_f64 v[20:21], v[18:19], -1.0
	v_add_f64 v[24:25], v[22:23], -1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_add_f64 v[18:19], v[18:19], -v[24:25]
	v_rcp_f64_e32 v[24:25], v[22:23]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[26:27], -v[22:23], v[24:25], 1.0
	v_fma_f64 v[24:25], v[26:27], v[24:25], v[24:25]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[26:27], -v[22:23], v[24:25], 1.0
	v_fma_f64 v[24:25], v[26:27], v[24:25], v[24:25]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[26:27], v[20:21], v[24:25]
	v_mul_f64 v[28:29], v[22:23], v[26:27]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[22:23], v[26:27], v[22:23], -v[28:29]
	v_fma_f64 v[18:19], v[26:27], v[18:19], v[22:23]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[22:23], v[28:29], v[18:19]
	v_add_f64 v[30:31], v[20:21], -v[22:23]
	v_add_f64 v[28:29], v[22:23], -v[28:29]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[20:21], v[20:21], -v[30:31]
	v_add_f64 v[18:19], v[28:29], -v[18:19]
	v_cvt_f64_i32_e32 v[28:29], v32
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[20:21], v[20:21], -v[22:23]
	v_add_f64 v[18:19], v[18:19], v[20:21]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[18:19], v[30:31], v[18:19]
	v_mul_f64 v[30:31], v[28:29], s[38:39]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[18:19], v[24:25], v[18:19]
	v_fma_f64 v[32:33], v[28:29], s[38:39], -v[30:31]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[20:21], v[26:27], v[18:19]
	v_fma_f64 v[28:29], v[28:29], s[40:41], v[32:33]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[22:23], v[20:21], -v[26:27]
	v_add_f64 v[32:33], v[30:31], v[28:29]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[18:19], v[18:19], -v[22:23]
	v_mul_f64 v[22:23], v[20:21], v[20:21]
	v_add_f64 v[30:31], v[32:33], -v[30:31]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[26:27], v[18:19], v[18:19]
	v_fma_f64 v[24:25], v[20:21], v[20:21], -v[22:23]
	v_ldexp_f64 v[34:35], v[18:19], 1
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f64 v[28:29], v[28:29], -v[30:31]
	v_ldexp_f64 v[30:31], v[20:21], 1
	v_fma_f64 v[24:25], v[20:21], v[26:27], v[24:25]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[26:27], v[22:23], v[24:25]
	v_add_f64 v[22:23], v[26:27], -v[22:23]
	v_mul_f64 v[36:37], v[20:21], v[26:27]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[22:23], v[24:25], -v[22:23]
	v_fma_f64 v[24:25], v[26:27], s[56:57], s[54:55]
	v_fma_f64 v[38:39], v[26:27], v[20:21], -v[36:37]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[24:25], v[26:27], v[24:25], s[52:53]
	v_fma_f64 v[18:19], v[26:27], v[18:19], v[38:39]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[24:25], v[26:27], v[24:25], s[50:51]
	v_fma_f64 v[18:19], v[22:23], v[20:21], v[18:19]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[24:25], v[26:27], v[24:25], s[48:49]
	v_add_f64 v[20:21], v[36:37], v[18:19]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[24:25], v[26:27], v[24:25], s[46:47]
	v_add_f64 v[36:37], v[20:21], -v[36:37]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[24:25], v[26:27], v[24:25], s[44:45]
	v_add_f64 v[18:19], v[18:19], -v[36:37]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[24:25], v[26:27], v[24:25], s[42:43]
	v_fma_f64 v[24:25], v[26:27], v[24:25], s[36:37]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[36:37], v[26:27], v[24:25]
	v_fma_f64 v[26:27], v[26:27], v[24:25], -v[36:37]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[22:23], v[22:23], v[24:25], v[26:27]
	v_add_f64 v[24:25], v[36:37], v[22:23]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[26:27], v[24:25], -v[36:37]
	v_add_f64 v[22:23], v[22:23], -v[26:27]
	v_add_f64 v[26:27], v[24:25], s[28:29]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[22:23], v[22:23], s[30:31]
	v_add_f64 v[36:37], v[26:27], s[34:35]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[24:25], v[24:25], -v[36:37]
	v_add_f64 v[22:23], v[22:23], v[24:25]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[24:25], v[26:27], v[22:23]
	v_add_f64 v[26:27], v[26:27], -v[24:25]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f64 v[22:23], v[22:23], v[26:27]
	v_mul_f64 v[26:27], v[20:21], v[24:25]
	v_fma_f64 v[36:37], v[20:21], v[24:25], -v[26:27]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[20:21], v[20:21], v[22:23], v[36:37]
	v_fma_f64 v[18:19], v[18:19], v[24:25], v[20:21]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[20:21], v[26:27], v[18:19]
	v_add_f64 v[22:23], v[20:21], -v[26:27]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[18:19], v[18:19], -v[22:23]
	v_add_f64 v[22:23], v[30:31], v[20:21]
	v_add_f64 v[18:19], v[34:35], v[18:19]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[24:25], v[22:23], -v[30:31]
	v_add_f64 v[20:21], v[20:21], -v[24:25]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[18:19], v[18:19], v[20:21]
	v_add_f64 v[20:21], v[22:23], v[18:19]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[22:23], v[20:21], -v[22:23]
	v_add_f64 v[18:19], v[18:19], -v[22:23]
	v_add_f64 v[22:23], v[32:33], v[20:21]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[24:25], v[22:23], -v[32:33]
	v_add_f64 v[26:27], v[22:23], -v[24:25]
	v_add_f64 v[20:21], v[20:21], -v[24:25]
	v_add_f64 v[24:25], v[28:29], v[18:19]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[26:27], v[32:33], -v[26:27]
	v_add_f64 v[20:21], v[20:21], v[26:27]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[26:27], v[24:25], -v[28:29]
	v_add_f64 v[20:21], v[24:25], v[20:21]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[30:31], v[24:25], -v[26:27]
	v_add_f64 v[18:19], v[18:19], -v[26:27]
	v_add_f64 v[24:25], v[22:23], v[20:21]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[28:29], v[28:29], -v[30:31]
	v_add_f64 v[22:23], v[24:25], -v[22:23]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[18:19], v[18:19], v[28:29]
	v_add_f64 v[20:21], v[20:21], -v[22:23]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[18:19], v[18:19], v[20:21]
	v_add_f64 v[20:21], v[24:25], v[18:19]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[22:23], v[20:21], -v[24:25]
	v_add_f64 v[18:19], v[18:19], -v[22:23]
	v_add_f64 v[22:23], v[20:21], v[20:21]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f64 v[20:21], v[20:21], 2.0, -v[22:23]
	v_cmp_class_f64_e64 vcc_lo, v[22:23], 0x204
	v_fma_f64 v[18:19], v[18:19], 2.0, v[20:21]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[20:21], v[22:23], v[18:19]
	v_add_f64 v[24:25], v[20:21], -v[22:23]
	v_dual_cndmask_b32 v21, v21, v23 :: v_dual_cndmask_b32 v20, v20, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_mul_f64 v[22:23], v[20:21], s[26:27]
	v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[20:21]|
	v_cmp_ngt_f64_e64 s0, 0xc090cc00, v[20:21]
	v_add_f64 v[18:19], v[18:19], -v[24:25]
	v_rndne_f64_e32 v[22:23], v[22:23]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v19, 0, v19 :: v_dual_cndmask_b32 v18, 0, v18
	v_cmp_nlt_f64_e32 vcc_lo, 0x40900000, v[20:21]
	v_fma_f64 v[24:25], v[22:23], s[18:19], v[20:21]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f64 v[24:25], v[22:23], s[20:21], v[24:25]
	v_cvt_i32_f64_e32 v22, v[22:23]
	v_fma_f64 v[26:27], v[24:25], s[24:25], s[22:23]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[26:27], v[24:25], v[26:27], s[16:17]
	v_fma_f64 v[26:27], v[24:25], v[26:27], s[14:15]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[26:27], v[24:25], v[26:27], s[12:13]
	v_fma_f64 v[26:27], v[24:25], v[26:27], s[10:11]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[26:27], v[24:25], v[26:27], s[8:9]
	v_fma_f64 v[26:27], v[24:25], v[26:27], s[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[26:27], v[24:25], v[26:27], s[4:5]
	v_fma_f64 v[26:27], v[24:25], v[26:27], s[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[26:27], v[24:25], v[26:27], 1.0
	v_fma_f64 v[24:25], v[24:25], v[26:27], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ldexp_f64 v[22:23], v[24:25], v22
	v_cndmask_b32_e32 v23, 0x7ff00000, v23, vcc_lo
	s_and_b32 vcc_lo, s0, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v20, 0, v22, vcc_lo
	v_cndmask_b32_e64 v21, 0, v23, s0
	v_cmp_neq_f64_e64 s0, 0, v[4:5]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f64 v[18:19], v[20:21], v[18:19], v[20:21]
	v_cmp_class_f64_e64 vcc_lo, v[20:21], 0x204
	v_dual_cndmask_b32 v19, v19, v21 :: v_dual_cndmask_b32 v18, v18, v20
	v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[4:5]|
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_mul_f64 v[18:19], |v[18:19]|, s[58:59]
	s_mov_b32 s58, 0xa0b5ed8d
	s_mov_b32 s59, 0x3eb0c6f7
	v_add_f64 v[0:1], v[0:1], s[58:59]
	v_add_f64 v[2:3], v[2:3], s[58:59]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cndmask_b32_e32 v19, 0x7ff00000, v19, vcc_lo
	s_and_b32 vcc_lo, s0, vcc_lo
	v_cndmask_b32_e32 v4, 0, v18, vcc_lo
	v_cmp_gt_f64_e32 vcc_lo, s[28:29], v[8:9]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v5, 0, v19, s0
	v_cndmask_b32_e64 v16, 0, 1, vcc_lo
	v_ldexp_f64 v[16:17], v[8:9], v16
	v_frexp_exp_i32_f64_e32 v8, v[6:7]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[20:21], v[16:17], 1.0
	v_add_f64 v[18:19], v[16:17], -1.0
	v_subrev_co_ci_u32_e32 v8, vcc_lo, 0, v8, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cvt_f64_i32_e32 v[8:9], v8
	v_add_f64 v[22:23], v[20:21], -1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_add_f64 v[16:17], v[16:17], -v[22:23]
	v_rcp_f64_e32 v[22:23], v[20:21]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[24:25], -v[20:21], v[22:23], 1.0
	v_fma_f64 v[22:23], v[24:25], v[22:23], v[22:23]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[24:25], -v[20:21], v[22:23], 1.0
	v_fma_f64 v[22:23], v[24:25], v[22:23], v[22:23]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[24:25], v[18:19], v[22:23]
	v_mul_f64 v[26:27], v[20:21], v[24:25]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[20:21], v[24:25], v[20:21], -v[26:27]
	v_fma_f64 v[16:17], v[24:25], v[16:17], v[20:21]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[20:21], v[26:27], v[16:17]
	v_add_f64 v[28:29], v[18:19], -v[20:21]
	v_add_f64 v[26:27], v[20:21], -v[26:27]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[18:19], v[18:19], -v[28:29]
	v_add_f64 v[16:17], v[26:27], -v[16:17]
	v_mul_f64 v[26:27], v[8:9], s[38:39]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[18:19], v[18:19], -v[20:21]
	v_add_f64 v[16:17], v[16:17], v[18:19]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[16:17], v[28:29], v[16:17]
	v_fma_f64 v[28:29], v[8:9], s[38:39], -v[26:27]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[16:17], v[22:23], v[16:17]
	v_fma_f64 v[8:9], v[8:9], s[40:41], v[28:29]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[18:19], v[24:25], v[16:17]
	v_add_f64 v[28:29], v[26:27], v[8:9]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[20:21], v[18:19], -v[24:25]
	v_add_f64 v[26:27], v[28:29], -v[26:27]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[16:17], v[16:17], -v[20:21]
	v_mul_f64 v[20:21], v[18:19], v[18:19]
	v_add_f64 v[8:9], v[8:9], -v[26:27]
	v_ldexp_f64 v[26:27], v[18:19], 1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[24:25], v[16:17], v[16:17]
	v_fma_f64 v[22:23], v[18:19], v[18:19], -v[20:21]
	v_ldexp_f64 v[30:31], v[16:17], 1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[22:23], v[18:19], v[24:25], v[22:23]
	v_add_f64 v[24:25], v[20:21], v[22:23]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[20:21], v[24:25], -v[20:21]
	v_mul_f64 v[32:33], v[18:19], v[24:25]
	v_add_f64 v[20:21], v[22:23], -v[20:21]
	v_fma_f64 v[22:23], v[24:25], s[56:57], s[54:55]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[34:35], v[24:25], v[18:19], -v[32:33]
	v_fma_f64 v[22:23], v[24:25], v[22:23], s[52:53]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[16:17], v[24:25], v[16:17], v[34:35]
	v_fma_f64 v[22:23], v[24:25], v[22:23], s[50:51]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[16:17], v[20:21], v[18:19], v[16:17]
	v_fma_f64 v[22:23], v[24:25], v[22:23], s[48:49]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[18:19], v[32:33], v[16:17]
	v_fma_f64 v[22:23], v[24:25], v[22:23], s[46:47]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[32:33], v[18:19], -v[32:33]
	v_fma_f64 v[22:23], v[24:25], v[22:23], s[44:45]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[16:17], v[16:17], -v[32:33]
	v_fma_f64 v[22:23], v[24:25], v[22:23], s[42:43]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[22:23], v[24:25], v[22:23], s[36:37]
	v_mul_f64 v[32:33], v[24:25], v[22:23]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[24:25], v[24:25], v[22:23], -v[32:33]
	v_fma_f64 v[20:21], v[20:21], v[22:23], v[24:25]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[22:23], v[32:33], v[20:21]
	v_add_f64 v[24:25], v[22:23], -v[32:33]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[20:21], v[20:21], -v[24:25]
	v_add_f64 v[24:25], v[22:23], s[28:29]
	v_add_f64 v[20:21], v[20:21], s[30:31]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[32:33], v[24:25], s[34:35]
	v_add_f64 v[22:23], v[22:23], -v[32:33]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[20:21], v[20:21], v[22:23]
	v_add_f64 v[22:23], v[24:25], v[20:21]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[24:25], v[24:25], -v[22:23]
	v_add_f64 v[20:21], v[20:21], v[24:25]
	v_mul_f64 v[24:25], v[18:19], v[22:23]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[32:33], v[18:19], v[22:23], -v[24:25]
	v_fma_f64 v[18:19], v[18:19], v[20:21], v[32:33]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[16:17], v[16:17], v[22:23], v[18:19]
	v_add_f64 v[18:19], v[24:25], v[16:17]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[20:21], v[18:19], -v[24:25]
	v_add_f64 v[16:17], v[16:17], -v[20:21]
	v_add_f64 v[20:21], v[26:27], v[18:19]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[16:17], v[30:31], v[16:17]
	v_add_f64 v[22:23], v[20:21], -v[26:27]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[18:19], v[18:19], -v[22:23]
	v_add_f64 v[16:17], v[16:17], v[18:19]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[18:19], v[20:21], v[16:17]
	v_add_f64 v[20:21], v[18:19], -v[20:21]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f64 v[16:17], v[16:17], -v[20:21]
	v_add_f64 v[20:21], v[28:29], v[18:19]
	v_add_f64 v[22:23], v[20:21], -v[28:29]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_add_f64 v[24:25], v[20:21], -v[22:23]
	v_add_f64 v[18:19], v[18:19], -v[22:23]
	v_add_f64 v[22:23], v[8:9], v[16:17]
	v_add_f64 v[24:25], v[28:29], -v[24:25]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[18:19], v[18:19], v[24:25]
	v_add_f64 v[24:25], v[22:23], -v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[26:27], v[22:23], -v[24:25]
	v_add_f64 v[16:17], v[16:17], -v[24:25]
	v_add_f64 v[8:9], v[8:9], -v[26:27]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f64 v[8:9], v[16:17], v[8:9]
	v_add_f64 v[16:17], v[22:23], v[18:19]
	v_add_f64 v[18:19], v[20:21], v[16:17]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[20:21], v[18:19], -v[20:21]
	v_add_f64 v[16:17], v[16:17], -v[20:21]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[8:9], v[8:9], v[16:17]
	v_add_f64 v[16:17], v[18:19], v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[18:19], v[16:17], -v[18:19]
	v_add_f64 v[8:9], v[8:9], -v[18:19]
	v_add_f64 v[18:19], v[16:17], v[16:17]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f64 v[16:17], v[16:17], 2.0, -v[18:19]
	v_cmp_class_f64_e64 vcc_lo, v[18:19], 0x204
	v_fma_f64 v[8:9], v[8:9], 2.0, v[16:17]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[16:17], v[18:19], v[8:9]
	v_add_f64 v[20:21], v[16:17], -v[18:19]
	v_dual_cndmask_b32 v17, v17, v19 :: v_dual_cndmask_b32 v16, v16, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_mul_f64 v[18:19], v[16:17], s[26:27]
	v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[16:17]|
	v_cmp_ngt_f64_e64 s0, 0xc090cc00, v[16:17]
	v_add_f64 v[8:9], v[8:9], -v[20:21]
	v_rndne_f64_e32 v[18:19], v[18:19]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v9, 0, v9 :: v_dual_cndmask_b32 v8, 0, v8
	v_cmp_nlt_f64_e32 vcc_lo, 0x40900000, v[16:17]
	v_fma_f64 v[20:21], v[18:19], s[18:19], v[16:17]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f64 v[20:21], v[18:19], s[20:21], v[20:21]
	v_cvt_i32_f64_e32 v18, v[18:19]
	v_fma_f64 v[22:23], v[20:21], s[24:25], s[22:23]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[22:23], v[20:21], v[22:23], s[16:17]
	v_fma_f64 v[22:23], v[20:21], v[22:23], s[14:15]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[22:23], v[20:21], v[22:23], s[12:13]
	v_fma_f64 v[22:23], v[20:21], v[22:23], s[10:11]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[22:23], v[20:21], v[22:23], s[8:9]
	v_fma_f64 v[22:23], v[20:21], v[22:23], s[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[22:23], v[20:21], v[22:23], s[4:5]
	v_fma_f64 v[22:23], v[20:21], v[22:23], s[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[22:23], v[20:21], v[22:23], 1.0
	v_fma_f64 v[20:21], v[20:21], v[22:23], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ldexp_f64 v[18:19], v[20:21], v18
	v_cndmask_b32_e32 v19, 0x7ff00000, v19, vcc_lo
	s_and_b32 vcc_lo, s0, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v16, 0, v18, vcc_lo
	v_cndmask_b32_e64 v17, 0, v19, s0
	v_cmp_neq_f64_e64 s0, 0, v[6:7]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f64 v[8:9], v[16:17], v[8:9], v[16:17]
	v_cmp_class_f64_e64 vcc_lo, v[16:17], 0x204
	v_dual_cndmask_b32 v9, v9, v17 :: v_dual_cndmask_b32 v8, v8, v16
	v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[6:7]|
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ldexp_f64 v[8:9], |v[8:9]|, -2
	v_cndmask_b32_e32 v9, 0x7ff00000, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	s_and_b32 vcc_lo, s0, vcc_lo
	v_cndmask_b32_e32 v6, 0, v8, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v7, 0, v9, s0
	v_add_f64 v[4:5], v[4:5], v[6:7]
	v_frexp_mant_f64_e32 v[6:7], v[0:1]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[4:5], v[4:5], s[58:59]
	v_cmp_gt_f64_e32 vcc_lo, s[28:29], v[6:7]
	v_readlane_b32 s59, v40, 25
	v_readlane_b32 s58, v40, 24
	v_cndmask_b32_e64 v8, 0, 1, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_ldexp_f64 v[6:7], v[6:7], v8
	v_frexp_exp_i32_f64_e32 v8, v[0:1]
	v_add_f64 v[16:17], v[6:7], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_subrev_co_ci_u32_e32 v26, vcc_lo, 0, v8, vcc_lo
	v_add_f64 v[8:9], v[6:7], -1.0
	v_add_f64 v[18:19], v[16:17], -1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_add_f64 v[6:7], v[6:7], -v[18:19]
	v_rcp_f64_e32 v[18:19], v[16:17]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[20:21], -v[16:17], v[18:19], 1.0
	v_fma_f64 v[18:19], v[20:21], v[18:19], v[18:19]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[20:21], -v[16:17], v[18:19], 1.0
	v_fma_f64 v[18:19], v[20:21], v[18:19], v[18:19]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[20:21], v[8:9], v[18:19]
	v_mul_f64 v[22:23], v[16:17], v[20:21]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[16:17], v[20:21], v[16:17], -v[22:23]
	v_fma_f64 v[6:7], v[20:21], v[6:7], v[16:17]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[16:17], v[22:23], v[6:7]
	v_add_f64 v[24:25], v[8:9], -v[16:17]
	v_add_f64 v[22:23], v[16:17], -v[22:23]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[8:9], v[8:9], -v[24:25]
	v_add_f64 v[6:7], v[22:23], -v[6:7]
	v_cvt_f64_i32_e32 v[22:23], v26
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[8:9], v[8:9], -v[16:17]
	v_add_f64 v[6:7], v[6:7], v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[6:7], v[24:25], v[6:7]
	v_mul_f64 v[24:25], v[22:23], s[38:39]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[6:7], v[18:19], v[6:7]
	v_fma_f64 v[26:27], v[22:23], s[38:39], -v[24:25]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[8:9], v[20:21], v[6:7]
	v_fma_f64 v[22:23], v[22:23], s[40:41], v[26:27]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[16:17], v[8:9], -v[20:21]
	v_add_f64 v[26:27], v[24:25], v[22:23]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[6:7], v[6:7], -v[16:17]
	v_mul_f64 v[16:17], v[8:9], v[8:9]
	v_add_f64 v[24:25], v[26:27], -v[24:25]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[20:21], v[6:7], v[6:7]
	v_fma_f64 v[18:19], v[8:9], v[8:9], -v[16:17]
	v_ldexp_f64 v[28:29], v[6:7], 1
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f64 v[22:23], v[22:23], -v[24:25]
	v_ldexp_f64 v[24:25], v[8:9], 1
	v_fma_f64 v[18:19], v[8:9], v[20:21], v[18:19]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[20:21], v[16:17], v[18:19]
	v_add_f64 v[16:17], v[20:21], -v[16:17]
	v_mul_f64 v[30:31], v[8:9], v[20:21]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[16:17], v[18:19], -v[16:17]
	v_fma_f64 v[18:19], v[20:21], s[56:57], s[54:55]
	v_fma_f64 v[32:33], v[20:21], v[8:9], -v[30:31]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[18:19], v[20:21], v[18:19], s[52:53]
	v_fma_f64 v[6:7], v[20:21], v[6:7], v[32:33]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[18:19], v[20:21], v[18:19], s[50:51]
	v_fma_f64 v[6:7], v[16:17], v[8:9], v[6:7]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[18:19], v[20:21], v[18:19], s[48:49]
	v_add_f64 v[8:9], v[30:31], v[6:7]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[18:19], v[20:21], v[18:19], s[46:47]
	v_add_f64 v[30:31], v[8:9], -v[30:31]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[18:19], v[20:21], v[18:19], s[44:45]
	v_add_f64 v[6:7], v[6:7], -v[30:31]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[18:19], v[20:21], v[18:19], s[42:43]
	v_fma_f64 v[18:19], v[20:21], v[18:19], s[36:37]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[30:31], v[20:21], v[18:19]
	v_fma_f64 v[20:21], v[20:21], v[18:19], -v[30:31]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[16:17], v[16:17], v[18:19], v[20:21]
	v_add_f64 v[18:19], v[30:31], v[16:17]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[20:21], v[18:19], -v[30:31]
	v_add_f64 v[16:17], v[16:17], -v[20:21]
	v_add_f64 v[20:21], v[18:19], s[28:29]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[16:17], v[16:17], s[30:31]
	v_add_f64 v[30:31], v[20:21], s[34:35]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[18:19], v[18:19], -v[30:31]
	v_add_f64 v[16:17], v[16:17], v[18:19]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[18:19], v[20:21], v[16:17]
	v_add_f64 v[20:21], v[20:21], -v[18:19]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f64 v[16:17], v[16:17], v[20:21]
	v_mul_f64 v[20:21], v[8:9], v[18:19]
	v_fma_f64 v[30:31], v[8:9], v[18:19], -v[20:21]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[8:9], v[8:9], v[16:17], v[30:31]
	v_fma_f64 v[6:7], v[6:7], v[18:19], v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[8:9], v[20:21], v[6:7]
	v_add_f64 v[16:17], v[8:9], -v[20:21]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[6:7], v[6:7], -v[16:17]
	v_add_f64 v[16:17], v[24:25], v[8:9]
	v_add_f64 v[6:7], v[28:29], v[6:7]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[18:19], v[16:17], -v[24:25]
	v_add_f64 v[8:9], v[8:9], -v[18:19]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[6:7], v[6:7], v[8:9]
	v_add_f64 v[8:9], v[16:17], v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[16:17], v[8:9], -v[16:17]
	v_add_f64 v[6:7], v[6:7], -v[16:17]
	v_add_f64 v[16:17], v[26:27], v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[18:19], v[16:17], -v[26:27]
	v_add_f64 v[20:21], v[16:17], -v[18:19]
	v_add_f64 v[8:9], v[8:9], -v[18:19]
	v_add_f64 v[18:19], v[22:23], v[6:7]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[20:21], v[26:27], -v[20:21]
	v_add_f64 v[8:9], v[8:9], v[20:21]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[20:21], v[18:19], -v[22:23]
	v_add_f64 v[8:9], v[18:19], v[8:9]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[24:25], v[18:19], -v[20:21]
	v_add_f64 v[6:7], v[6:7], -v[20:21]
	v_add_f64 v[18:19], v[16:17], v[8:9]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[22:23], v[22:23], -v[24:25]
	v_add_f64 v[16:17], v[18:19], -v[16:17]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[6:7], v[6:7], v[22:23]
	v_add_f64 v[8:9], v[8:9], -v[16:17]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[6:7], v[6:7], v[8:9]
	v_add_f64 v[8:9], v[18:19], v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[16:17], v[8:9], -v[18:19]
	v_add_f64 v[6:7], v[6:7], -v[16:17]
	v_add_f64 v[16:17], v[8:9], v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f64 v[8:9], v[8:9], 2.0, -v[16:17]
	v_cmp_class_f64_e64 vcc_lo, v[16:17], 0x204
	v_fma_f64 v[6:7], v[6:7], 2.0, v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[8:9], v[16:17], v[6:7]
	v_add_f64 v[18:19], v[8:9], -v[16:17]
	v_dual_cndmask_b32 v9, v9, v17 :: v_dual_cndmask_b32 v8, v8, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_mul_f64 v[16:17], v[8:9], s[26:27]
	v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[8:9]|
	v_cmp_ngt_f64_e64 s0, 0xc090cc00, v[8:9]
	v_add_f64 v[6:7], v[6:7], -v[18:19]
	v_rndne_f64_e32 v[16:17], v[16:17]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v7, 0, v7 :: v_dual_cndmask_b32 v6, 0, v6
	v_cmp_nlt_f64_e32 vcc_lo, 0x40900000, v[8:9]
	v_fma_f64 v[18:19], v[16:17], s[18:19], v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f64 v[18:19], v[16:17], s[20:21], v[18:19]
	v_cvt_i32_f64_e32 v16, v[16:17]
	v_fma_f64 v[20:21], v[18:19], s[24:25], s[22:23]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[20:21], v[18:19], v[20:21], s[16:17]
	v_fma_f64 v[20:21], v[18:19], v[20:21], s[14:15]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[20:21], v[18:19], v[20:21], s[12:13]
	v_fma_f64 v[20:21], v[18:19], v[20:21], s[10:11]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[20:21], v[18:19], v[20:21], s[8:9]
	v_fma_f64 v[20:21], v[18:19], v[20:21], s[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[20:21], v[18:19], v[20:21], s[4:5]
	v_fma_f64 v[20:21], v[18:19], v[20:21], s[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[20:21], v[18:19], v[20:21], 1.0
	v_fma_f64 v[18:19], v[18:19], v[20:21], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ldexp_f64 v[16:17], v[18:19], v16
	v_cndmask_b32_e32 v17, 0x7ff00000, v17, vcc_lo
	s_and_b32 vcc_lo, s0, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v8, 0, v16, vcc_lo
	v_cndmask_b32_e64 v9, 0, v17, s0
	s_mov_b32 s0, 0x9999999a
	s_mov_b32 s1, 0x3fb99999
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f64 v[6:7], v[8:9], v[6:7], v[8:9]
	v_cmp_class_f64_e64 vcc_lo, v[8:9], 0x204
	v_dual_cndmask_b32 v7, v7, v9 :: v_dual_cndmask_b32 v6, v6, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v8, v6 :: v_dual_and_b32 v9, 0x7fffffff, v7
	v_div_scale_f64 v[16:17], null, v[8:9], v[8:9], s[0:1]
	v_div_scale_f64 v[8:9], vcc_lo, s[0:1], v[8:9], s[0:1]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[18:19], v[16:17]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[20:21], -v[16:17], v[18:19], 1.0
	v_fma_f64 v[18:19], v[18:19], v[20:21], v[18:19]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[20:21], -v[16:17], v[18:19], 1.0
	v_fma_f64 v[18:19], v[18:19], v[20:21], v[18:19]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[20:21], v[8:9], v[18:19]
	v_fma_f64 v[8:9], -v[16:17], v[20:21], v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_fmas_f64 v[8:9], v[8:9], v[18:19], v[20:21]
	v_cmp_neq_f64_e32 vcc_lo, 0x7ff00000, v[0:1]
	v_div_fixup_f64 v[6:7], v[8:9], |v[6:7]|, s[0:1]
	v_cmp_neq_f64_e64 s0, 0, v[0:1]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v7, 0, v7, vcc_lo
	s_and_b32 vcc_lo, s0, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v0, 0, v6, vcc_lo
	v_cndmask_b32_e64 v1, 0x7ff00000, v7, s0
	v_frexp_mant_f64_e32 v[6:7], v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_gt_f64_e32 vcc_lo, s[28:29], v[6:7]
	v_cndmask_b32_e64 v8, 0, 1, vcc_lo
	v_ldexp_f64 v[6:7], v[6:7], v8
	v_frexp_exp_i32_f64_e32 v8, v[2:3]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[16:17], v[6:7], 1.0
	v_subrev_co_ci_u32_e32 v26, vcc_lo, 0, v8, vcc_lo
	v_add_f64 v[8:9], v[6:7], -1.0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[18:19], v[16:17], -1.0
	v_add_f64 v[6:7], v[6:7], -v[18:19]
	v_rcp_f64_e32 v[18:19], v[16:17]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[20:21], -v[16:17], v[18:19], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[18:19], v[20:21], v[18:19], v[18:19]
	v_fma_f64 v[20:21], -v[16:17], v[18:19], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[18:19], v[20:21], v[18:19], v[18:19]
	v_mul_f64 v[20:21], v[8:9], v[18:19]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[22:23], v[16:17], v[20:21]
	v_fma_f64 v[16:17], v[20:21], v[16:17], -v[22:23]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[6:7], v[20:21], v[6:7], v[16:17]
	v_add_f64 v[16:17], v[22:23], v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[24:25], v[8:9], -v[16:17]
	v_add_f64 v[22:23], v[16:17], -v[22:23]
	v_add_f64 v[8:9], v[8:9], -v[24:25]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[6:7], v[22:23], -v[6:7]
	v_cvt_f64_i32_e32 v[22:23], v26
	v_add_f64 v[8:9], v[8:9], -v[16:17]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[6:7], v[6:7], v[8:9]
	v_add_f64 v[6:7], v[24:25], v[6:7]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[24:25], v[22:23], s[38:39]
	v_mul_f64 v[6:7], v[18:19], v[6:7]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[26:27], v[22:23], s[38:39], -v[24:25]
	v_add_f64 v[8:9], v[20:21], v[6:7]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[22:23], v[22:23], s[40:41], v[26:27]
	v_add_f64 v[16:17], v[8:9], -v[20:21]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[26:27], v[24:25], v[22:23]
	v_add_f64 v[6:7], v[6:7], -v[16:17]
	v_mul_f64 v[16:17], v[8:9], v[8:9]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[24:25], v[26:27], -v[24:25]
	v_add_f64 v[20:21], v[6:7], v[6:7]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_fma_f64 v[18:19], v[8:9], v[8:9], -v[16:17]
	v_ldexp_f64 v[28:29], v[6:7], 1
	v_add_f64 v[22:23], v[22:23], -v[24:25]
	v_ldexp_f64 v[24:25], v[8:9], 1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[18:19], v[8:9], v[20:21], v[18:19]
	v_add_f64 v[20:21], v[16:17], v[18:19]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[16:17], v[20:21], -v[16:17]
	v_mul_f64 v[30:31], v[8:9], v[20:21]
	v_add_f64 v[16:17], v[18:19], -v[16:17]
	v_fma_f64 v[18:19], v[20:21], s[56:57], s[54:55]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[32:33], v[20:21], v[8:9], -v[30:31]
	v_fma_f64 v[18:19], v[20:21], v[18:19], s[52:53]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[6:7], v[20:21], v[6:7], v[32:33]
	v_fma_f64 v[18:19], v[20:21], v[18:19], s[50:51]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[6:7], v[16:17], v[8:9], v[6:7]
	v_fma_f64 v[18:19], v[20:21], v[18:19], s[48:49]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[8:9], v[30:31], v[6:7]
	v_fma_f64 v[18:19], v[20:21], v[18:19], s[46:47]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[30:31], v[8:9], -v[30:31]
	v_fma_f64 v[18:19], v[20:21], v[18:19], s[44:45]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[6:7], v[6:7], -v[30:31]
	v_fma_f64 v[18:19], v[20:21], v[18:19], s[42:43]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[18:19], v[20:21], v[18:19], s[36:37]
	v_mul_f64 v[30:31], v[20:21], v[18:19]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[20:21], v[20:21], v[18:19], -v[30:31]
	v_fma_f64 v[16:17], v[16:17], v[18:19], v[20:21]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[18:19], v[30:31], v[16:17]
	v_add_f64 v[20:21], v[18:19], -v[30:31]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[16:17], v[16:17], -v[20:21]
	v_add_f64 v[20:21], v[18:19], s[28:29]
	v_add_f64 v[16:17], v[16:17], s[30:31]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[30:31], v[20:21], s[34:35]
	v_add_f64 v[18:19], v[18:19], -v[30:31]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[16:17], v[16:17], v[18:19]
	v_add_f64 v[18:19], v[20:21], v[16:17]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[20:21], v[20:21], -v[18:19]
	v_add_f64 v[16:17], v[16:17], v[20:21]
	v_mul_f64 v[20:21], v[8:9], v[18:19]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[30:31], v[8:9], v[18:19], -v[20:21]
	v_fma_f64 v[8:9], v[8:9], v[16:17], v[30:31]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[6:7], v[6:7], v[18:19], v[8:9]
	v_add_f64 v[8:9], v[20:21], v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[16:17], v[8:9], -v[20:21]
	v_add_f64 v[6:7], v[6:7], -v[16:17]
	v_add_f64 v[16:17], v[24:25], v[8:9]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[6:7], v[28:29], v[6:7]
	v_add_f64 v[18:19], v[16:17], -v[24:25]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[8:9], v[8:9], -v[18:19]
	v_add_f64 v[6:7], v[6:7], v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[8:9], v[16:17], v[6:7]
	v_add_f64 v[16:17], v[8:9], -v[16:17]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f64 v[6:7], v[6:7], -v[16:17]
	v_add_f64 v[16:17], v[26:27], v[8:9]
	v_add_f64 v[18:19], v[16:17], -v[26:27]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_add_f64 v[20:21], v[16:17], -v[18:19]
	v_add_f64 v[8:9], v[8:9], -v[18:19]
	v_add_f64 v[18:19], v[22:23], v[6:7]
	v_add_f64 v[20:21], v[26:27], -v[20:21]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[8:9], v[8:9], v[20:21]
	v_add_f64 v[20:21], v[18:19], -v[22:23]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[8:9], v[18:19], v[8:9]
	v_add_f64 v[24:25], v[18:19], -v[20:21]
	v_add_f64 v[6:7], v[6:7], -v[20:21]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[18:19], v[16:17], v[8:9]
	v_add_f64 v[22:23], v[22:23], -v[24:25]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[16:17], v[18:19], -v[16:17]
	v_add_f64 v[6:7], v[6:7], v[22:23]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[8:9], v[8:9], -v[16:17]
	v_add_f64 v[6:7], v[6:7], v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[8:9], v[18:19], v[6:7]
	v_add_f64 v[16:17], v[8:9], -v[18:19]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f64 v[6:7], v[6:7], -v[16:17]
	v_add_f64 v[16:17], v[8:9], v[8:9]
	v_fma_f64 v[8:9], v[8:9], 2.0, -v[16:17]
	v_cmp_class_f64_e64 vcc_lo, v[16:17], 0x204
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[6:7], v[6:7], 2.0, v[8:9]
	v_add_f64 v[8:9], v[16:17], v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f64 v[18:19], v[8:9], -v[16:17]
	v_dual_cndmask_b32 v9, v9, v17 :: v_dual_cndmask_b32 v8, v8, v16
	v_mul_f64 v[16:17], v[8:9], s[26:27]
	v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[8:9]|
	v_cmp_ngt_f64_e64 s0, 0xc090cc00, v[8:9]
	v_add_f64 v[6:7], v[6:7], -v[18:19]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rndne_f64_e32 v[16:17], v[16:17]
	v_dual_cndmask_b32 v7, 0, v7 :: v_dual_cndmask_b32 v6, 0, v6
	v_cmp_nlt_f64_e32 vcc_lo, 0x40900000, v[8:9]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[18:19], v[16:17], s[18:19], v[8:9]
	v_fma_f64 v[18:19], v[16:17], s[20:21], v[18:19]
	v_cvt_i32_f64_e32 v16, v[16:17]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[20:21], v[18:19], s[24:25], s[22:23]
	v_fma_f64 v[20:21], v[18:19], v[20:21], s[16:17]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[20:21], v[18:19], v[20:21], s[14:15]
	v_fma_f64 v[20:21], v[18:19], v[20:21], s[12:13]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[20:21], v[18:19], v[20:21], s[10:11]
	v_fma_f64 v[20:21], v[18:19], v[20:21], s[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[20:21], v[18:19], v[20:21], s[6:7]
	v_fma_f64 v[20:21], v[18:19], v[20:21], s[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[20:21], v[18:19], v[20:21], s[2:3]
	v_fma_f64 v[20:21], v[18:19], v[20:21], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[18:19], v[18:19], v[20:21], 1.0
	v_ldexp_f64 v[16:17], v[18:19], v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v17, 0x7ff00000, v17, vcc_lo
	s_and_b32 vcc_lo, s0, vcc_lo
	v_cndmask_b32_e32 v8, 0, v16, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v9, 0, v17, s0
	v_cmp_neq_f64_e64 s0, 0, v[2:3]
	v_fma_f64 v[6:7], v[8:9], v[6:7], v[8:9]
	v_cmp_class_f64_e64 vcc_lo, v[8:9], 0x204
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_cndmask_b32 v7, v7, v9 :: v_dual_cndmask_b32 v6, v6, v8
	v_dual_mov_b32 v8, v6 :: v_dual_and_b32 v9, 0x7fffffff, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f64 v[16:17], null, v[8:9], v[8:9], s[60:61]
	v_div_scale_f64 v[8:9], vcc_lo, s[60:61], v[8:9], s[60:61]
	v_rcp_f64_e32 v[18:19], v[16:17]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[20:21], -v[16:17], v[18:19], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[18:19], v[18:19], v[20:21], v[18:19]
	v_fma_f64 v[20:21], -v[16:17], v[18:19], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[18:19], v[18:19], v[20:21], v[18:19]
	v_mul_f64 v[20:21], v[8:9], v[18:19]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[8:9], -v[16:17], v[20:21], v[8:9]
	v_div_fmas_f64 v[8:9], v[8:9], v[18:19], v[20:21]
	v_cmp_neq_f64_e32 vcc_lo, 0x7ff00000, v[2:3]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_div_fixup_f64 v[6:7], v[8:9], |v[6:7]|, s[60:61]
	s_mov_b32 s61, 0x3fd33333
	v_cndmask_b32_e32 v7, 0, v7, vcc_lo
	s_and_b32 vcc_lo, s0, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v2, 0, v6, vcc_lo
	v_cndmask_b32_e64 v3, 0x7ff00000, v7, s0
	v_frexp_mant_f64_e32 v[6:7], v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_gt_f64_e32 vcc_lo, s[28:29], v[6:7]
	v_cndmask_b32_e64 v8, 0, 1, vcc_lo
	v_ldexp_f64 v[6:7], v[6:7], v8
	v_frexp_exp_i32_f64_e32 v8, v[4:5]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[16:17], v[6:7], 1.0
	v_subrev_co_ci_u32_e32 v26, vcc_lo, 0, v8, vcc_lo
	v_add_f64 v[8:9], v[6:7], -1.0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[18:19], v[16:17], -1.0
	v_add_f64 v[6:7], v[6:7], -v[18:19]
	v_rcp_f64_e32 v[18:19], v[16:17]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[20:21], -v[16:17], v[18:19], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[18:19], v[20:21], v[18:19], v[18:19]
	v_fma_f64 v[20:21], -v[16:17], v[18:19], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[18:19], v[20:21], v[18:19], v[18:19]
	v_mul_f64 v[20:21], v[8:9], v[18:19]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[22:23], v[16:17], v[20:21]
	v_fma_f64 v[16:17], v[20:21], v[16:17], -v[22:23]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[6:7], v[20:21], v[6:7], v[16:17]
	v_add_f64 v[16:17], v[22:23], v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[24:25], v[8:9], -v[16:17]
	v_add_f64 v[22:23], v[16:17], -v[22:23]
	v_add_f64 v[8:9], v[8:9], -v[24:25]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[6:7], v[22:23], -v[6:7]
	v_cvt_f64_i32_e32 v[22:23], v26
	v_add_f64 v[8:9], v[8:9], -v[16:17]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[6:7], v[6:7], v[8:9]
	v_add_f64 v[6:7], v[24:25], v[6:7]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[24:25], v[22:23], s[38:39]
	v_mul_f64 v[6:7], v[18:19], v[6:7]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_fma_f64 v[26:27], v[22:23], s[38:39], -v[24:25]
	v_readlane_b32 s39, v40, 5
	v_readlane_b32 s38, v40, 4
	v_add_f64 v[8:9], v[20:21], v[6:7]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_fma_f64 v[22:23], v[22:23], s[40:41], v[26:27]
	v_readlane_b32 s41, v40, 7
	v_readlane_b32 s40, v40, 6
	v_add_f64 v[16:17], v[8:9], -v[20:21]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[26:27], v[24:25], v[22:23]
	v_add_f64 v[6:7], v[6:7], -v[16:17]
	v_mul_f64 v[16:17], v[8:9], v[8:9]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[24:25], v[26:27], -v[24:25]
	v_add_f64 v[20:21], v[6:7], v[6:7]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_fma_f64 v[18:19], v[8:9], v[8:9], -v[16:17]
	v_ldexp_f64 v[28:29], v[6:7], 1
	v_add_f64 v[22:23], v[22:23], -v[24:25]
	v_ldexp_f64 v[24:25], v[8:9], 1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[18:19], v[8:9], v[20:21], v[18:19]
	v_add_f64 v[20:21], v[16:17], v[18:19]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[16:17], v[20:21], -v[16:17]
	v_mul_f64 v[30:31], v[8:9], v[20:21]
	v_add_f64 v[16:17], v[18:19], -v[16:17]
	v_fma_f64 v[18:19], v[20:21], s[56:57], s[54:55]
	s_delay_alu instid0(VALU_DEP_3)
	v_fma_f64 v[32:33], v[20:21], v[8:9], -v[30:31]
	v_readlane_b32 s57, v40, 23
	v_readlane_b32 s56, v40, 22
	v_readlane_b32 s55, v40, 21
	v_readlane_b32 s54, v40, 20
	v_fma_f64 v[18:19], v[20:21], v[18:19], s[52:53]
	v_fma_f64 v[6:7], v[20:21], v[6:7], v[32:33]
	v_readlane_b32 s53, v40, 19
	v_readlane_b32 s52, v40, 18
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[18:19], v[20:21], v[18:19], s[50:51]
	v_fma_f64 v[6:7], v[16:17], v[8:9], v[6:7]
	v_readlane_b32 s51, v40, 17
	v_readlane_b32 s50, v40, 16
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[18:19], v[20:21], v[18:19], s[48:49]
	v_add_f64 v[8:9], v[30:31], v[6:7]
	v_readlane_b32 s49, v40, 15
	v_readlane_b32 s48, v40, 14
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[18:19], v[20:21], v[18:19], s[46:47]
	v_add_f64 v[30:31], v[8:9], -v[30:31]
	v_readlane_b32 s47, v40, 13
	v_readlane_b32 s46, v40, 12
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[18:19], v[20:21], v[18:19], s[44:45]
	v_add_f64 v[6:7], v[6:7], -v[30:31]
	v_readlane_b32 s45, v40, 11
	v_readlane_b32 s44, v40, 10
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_fma_f64 v[18:19], v[20:21], v[18:19], s[42:43]
	v_readlane_b32 s43, v40, 9
	v_readlane_b32 s42, v40, 8
	v_fma_f64 v[18:19], v[20:21], v[18:19], s[36:37]
	v_readlane_b32 s37, v40, 3
	v_readlane_b32 s36, v40, 2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[30:31], v[20:21], v[18:19]
	v_fma_f64 v[20:21], v[20:21], v[18:19], -v[30:31]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[16:17], v[16:17], v[18:19], v[20:21]
	v_add_f64 v[18:19], v[30:31], v[16:17]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[20:21], v[18:19], -v[30:31]
	v_add_f64 v[16:17], v[16:17], -v[20:21]
	v_add_f64 v[20:21], v[18:19], s[28:29]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[16:17], v[16:17], s[30:31]
	v_add_f64 v[30:31], v[20:21], s[34:35]
	v_readlane_b32 s30, v40, 28
	v_readlane_b32 s31, v40, 29
	v_readlane_b32 s35, v40, 1
	v_readlane_b32 s34, v40, 0
	v_add_f64 v[18:19], v[18:19], -v[30:31]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[16:17], v[16:17], v[18:19]
	v_add_f64 v[18:19], v[20:21], v[16:17]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[20:21], v[20:21], -v[18:19]
	v_add_f64 v[16:17], v[16:17], v[20:21]
	v_mul_f64 v[20:21], v[8:9], v[18:19]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[30:31], v[8:9], v[18:19], -v[20:21]
	v_fma_f64 v[8:9], v[8:9], v[16:17], v[30:31]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[6:7], v[6:7], v[18:19], v[8:9]
	v_add_f64 v[8:9], v[20:21], v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[16:17], v[8:9], -v[20:21]
	v_add_f64 v[6:7], v[6:7], -v[16:17]
	v_add_f64 v[16:17], v[24:25], v[8:9]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[6:7], v[28:29], v[6:7]
	v_add_f64 v[18:19], v[16:17], -v[24:25]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[8:9], v[8:9], -v[18:19]
	v_add_f64 v[6:7], v[6:7], v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[8:9], v[16:17], v[6:7]
	v_add_f64 v[16:17], v[8:9], -v[16:17]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f64 v[6:7], v[6:7], -v[16:17]
	v_add_f64 v[16:17], v[26:27], v[8:9]
	v_add_f64 v[18:19], v[16:17], -v[26:27]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_add_f64 v[20:21], v[16:17], -v[18:19]
	v_add_f64 v[8:9], v[8:9], -v[18:19]
	v_add_f64 v[18:19], v[22:23], v[6:7]
	v_add_f64 v[20:21], v[26:27], -v[20:21]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[8:9], v[8:9], v[20:21]
	v_add_f64 v[20:21], v[18:19], -v[22:23]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[8:9], v[18:19], v[8:9]
	v_add_f64 v[24:25], v[18:19], -v[20:21]
	v_add_f64 v[6:7], v[6:7], -v[20:21]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[18:19], v[16:17], v[8:9]
	v_add_f64 v[22:23], v[22:23], -v[24:25]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[16:17], v[18:19], -v[16:17]
	v_add_f64 v[6:7], v[6:7], v[22:23]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[8:9], v[8:9], -v[16:17]
	v_add_f64 v[6:7], v[6:7], v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[8:9], v[18:19], v[6:7]
	v_add_f64 v[16:17], v[8:9], -v[18:19]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f64 v[6:7], v[6:7], -v[16:17]
	v_add_f64 v[16:17], v[8:9], v[8:9]
	v_fma_f64 v[8:9], v[8:9], 2.0, -v[16:17]
	v_cmp_class_f64_e64 vcc_lo, v[16:17], 0x204
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[6:7], v[6:7], 2.0, v[8:9]
	v_add_f64 v[8:9], v[16:17], v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f64 v[18:19], v[8:9], -v[16:17]
	v_dual_cndmask_b32 v9, v9, v17 :: v_dual_cndmask_b32 v8, v8, v16
	v_mul_f64 v[16:17], v[8:9], s[26:27]
	v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[8:9]|
	v_cmp_ngt_f64_e64 s0, 0xc090cc00, v[8:9]
	v_add_f64 v[6:7], v[6:7], -v[18:19]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rndne_f64_e32 v[16:17], v[16:17]
	v_dual_cndmask_b32 v7, 0, v7 :: v_dual_cndmask_b32 v6, 0, v6
	v_cmp_nlt_f64_e32 vcc_lo, 0x40900000, v[8:9]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[18:19], v[16:17], s[18:19], v[8:9]
	v_fma_f64 v[18:19], v[16:17], s[20:21], v[18:19]
	v_cvt_i32_f64_e32 v16, v[16:17]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[20:21], v[18:19], s[24:25], s[22:23]
	v_fma_f64 v[20:21], v[18:19], v[20:21], s[16:17]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[20:21], v[18:19], v[20:21], s[14:15]
	v_fma_f64 v[20:21], v[18:19], v[20:21], s[12:13]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[20:21], v[18:19], v[20:21], s[10:11]
	v_fma_f64 v[20:21], v[18:19], v[20:21], s[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[20:21], v[18:19], v[20:21], s[6:7]
	v_fma_f64 v[20:21], v[18:19], v[20:21], s[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[20:21], v[18:19], v[20:21], s[2:3]
	v_fma_f64 v[20:21], v[18:19], v[20:21], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[18:19], v[18:19], v[20:21], 1.0
	v_ldexp_f64 v[16:17], v[18:19], v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v17, 0x7ff00000, v17, vcc_lo
	s_and_b32 vcc_lo, s0, vcc_lo
	v_cndmask_b32_e32 v8, 0, v16, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v9, 0, v17, s0
	v_cmp_neq_f64_e64 s0, 0, v[4:5]
	v_fma_f64 v[6:7], v[8:9], v[6:7], v[8:9]
	v_cmp_class_f64_e64 vcc_lo, v[8:9], 0x204
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_cndmask_b32 v7, v7, v9 :: v_dual_cndmask_b32 v6, v6, v8
	v_dual_mov_b32 v8, v6 :: v_dual_and_b32 v9, 0x7fffffff, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f64 v[16:17], null, v[8:9], v[8:9], s[60:61]
	v_div_scale_f64 v[8:9], vcc_lo, s[60:61], v[8:9], s[60:61]
	v_rcp_f64_e32 v[18:19], v[16:17]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[20:21], -v[16:17], v[18:19], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[18:19], v[18:19], v[20:21], v[18:19]
	v_fma_f64 v[20:21], -v[16:17], v[18:19], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[18:19], v[18:19], v[20:21], v[18:19]
	v_mul_f64 v[20:21], v[8:9], v[18:19]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[8:9], -v[16:17], v[20:21], v[8:9]
	v_div_fmas_f64 v[8:9], v[8:9], v[18:19], v[20:21]
	v_cmp_neq_f64_e32 vcc_lo, 0x7ff00000, v[4:5]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_div_fixup_f64 v[6:7], v[8:9], |v[6:7]|, s[60:61]
	v_readlane_b32 s61, v40, 27
	v_readlane_b32 s60, v40, 26
	v_cndmask_b32_e32 v7, 0, v7, vcc_lo
	s_and_b32 vcc_lo, s0, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v4, 0, v6, vcc_lo
	v_cndmask_b32_e64 v5, 0x7ff00000, v7, s0
	v_add_f64 v[6:7], v[0:1], v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[6:7], v[6:7], v[4:5]
	v_div_scale_f64 v[8:9], null, v[6:7], v[6:7], v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[16:17], v[8:9]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[18:19], -v[8:9], v[16:17], 1.0
	v_fma_f64 v[16:17], v[16:17], v[18:19], v[16:17]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[18:19], -v[8:9], v[16:17], 1.0
	v_fma_f64 v[16:17], v[16:17], v[18:19], v[16:17]
	v_div_scale_f64 v[18:19], vcc_lo, v[0:1], v[6:7], v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[20:21], v[18:19], v[16:17]
	v_fma_f64 v[8:9], -v[8:9], v[20:21], v[18:19]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f64 v[8:9], v[8:9], v[16:17], v[20:21]
	v_div_fixup_f64 v[0:1], v[8:9], v[6:7], v[0:1]
	v_div_scale_f64 v[8:9], null, v[6:7], v[6:7], v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[16:17], v[8:9]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[18:19], -v[8:9], v[16:17], 1.0
	v_fma_f64 v[16:17], v[16:17], v[18:19], v[16:17]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[18:19], -v[8:9], v[16:17], 1.0
	v_fma_f64 v[16:17], v[16:17], v[18:19], v[16:17]
	v_div_scale_f64 v[18:19], vcc_lo, v[2:3], v[6:7], v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[20:21], v[18:19], v[16:17]
	v_fma_f64 v[8:9], -v[8:9], v[20:21], v[18:19]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f64 v[8:9], v[8:9], v[16:17], v[20:21]
	v_div_fixup_f64 v[2:3], v[8:9], v[6:7], v[2:3]
	v_div_scale_f64 v[8:9], null, v[6:7], v[6:7], v[4:5]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[2:3], v[14:15], v[2:3]
	v_rcp_f64_e32 v[16:17], v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_fma_f64 v[0:1], v[10:11], v[0:1], v[2:3]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[18:19], -v[8:9], v[16:17], 1.0
	v_fma_f64 v[16:17], v[16:17], v[18:19], v[16:17]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[18:19], -v[8:9], v[16:17], 1.0
	v_fma_f64 v[16:17], v[16:17], v[18:19], v[16:17]
	v_div_scale_f64 v[18:19], vcc_lo, v[4:5], v[6:7], v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[20:21], v[18:19], v[16:17]
	v_fma_f64 v[8:9], -v[8:9], v[20:21], v[18:19]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f64 v[8:9], v[8:9], v[16:17], v[20:21]
	v_div_fixup_f64 v[4:5], v[8:9], v[6:7], v[4:5]
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[0:1], v[12:13], v[4:5], v[0:1]
	s_or_saveexec_b32 s0, -1
	scratch_load_b32 v40, off, s32          ; 4-byte Folded Reload
	s_mov_b32 exec_lo, s0
	s_waitcnt vmcnt(0)
	s_setpc_b64 s[30:31]
.Lfunc_end0:
	.size	_Z24weno_onesided_derivativeddddd, .Lfunc_end0-_Z24weno_onesided_derivativeddddd
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Function info:
; codeLenInByte = 15076
; NumSgprs: 64
; NumVgprs: 50
; ScratchSize: 8
; MemoryBound: 0
	.text
	.protected	_Z13upwind_normalPdS_S_PKdS1_S1_S1_S1_S1_S1_iiidddi ; -- Begin function _Z13upwind_normalPdS_S_PKdS1_S1_S1_S1_S1_S1_iiidddi
	.globl	_Z13upwind_normalPdS_S_PKdS1_S1_S1_S1_S1_S1_iiidddi
	.p2align	8
	.type	_Z13upwind_normalPdS_S_PKdS1_S1_S1_S1_S1_S1_iiidddi,@function
_Z13upwind_normalPdS_S_PKdS1_S1_S1_S1_S1_S1_iiidddi: ; @_Z13upwind_normalPdS_S_PKdS1_S1_S1_S1_S1_S1_iiidddi
; %bb.0:
	s_mov_b64 s[62:63], s[0:1]
	s_load_b64 s[0:1], s[0:1], 0x8c
	s_load_b128 s[84:87], s[62:63], 0x50
	v_and_b32_e32 v1, 0x3ff, v0
	v_bfe_u32 v2, v0, 10, 10
	v_bfe_u32 v3, v0, 20, 10
	s_mov_b32 s32, 0
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s2, s0, 16
	s_and_b32 s0, s0, 0xffff
	s_and_b32 s1, s1, 0xffff
	v_mad_u64_u32 v[65:66], null, s13, s0, v[1:2]
	v_mad_u64_u32 v[0:1], null, s14, s2, v[2:3]
	v_mad_u64_u32 v[60:61], null, s15, s1, v[3:4]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_gt_i32_e32 vcc_lo, s84, v65
	v_cmp_gt_i32_e64 s0, s85, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_i32_e64 s1, s86, v60
	s_and_b32 s0, vcc_lo, s0
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, s0, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_32
; %bb.1:
	v_cvt_f64_i32_e32 v[1:2], v60
	s_add_i32 s0, s86, -1
	v_cvt_f64_i32_e32 v[3:4], v0
	v_add_nc_u32_e32 v7, 2, v0
	v_add_nc_u32_e32 v9, 3, v0
	v_add_nc_u32_e32 v11, -1, v0
	v_add_nc_u32_e32 v13, -2, v0
	v_cvt_f64_i32_e32 v[63:64], s0
	v_add_nc_u32_e32 v5, 1, v0
	v_add_nc_u32_e32 v0, -3, v0
	v_cvt_f64_i32_e32 v[7:8], v7
	v_cvt_f64_i32_e32 v[9:10], v9
	v_cvt_f64_i32_e32 v[11:12], v11
	v_cvt_f64_i32_e32 v[13:14], v13
	v_cvt_f64_i32_e32 v[15:16], v0
	v_cvt_f64_i32_e32 v[17:18], v65
	s_add_i32 s1, s85, -1
	s_add_i32 s0, s84, -1
	v_cvt_f64_i32_e32 v[19:20], s1
	v_cvt_f64_i32_e32 v[66:67], s0
	s_clause 0x1
	s_load_b512 s[68:83], s[62:63], 0x0
	; meta instruction
	s_load_b64 s[66:67], s[62:63], 0x70
	v_max_f64 v[0:1], v[1:2], 0
	v_max_f64 v[2:3], v[3:4], 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_f64_e32 vcc_lo, v[0:1], v[63:64]
	v_cmp_gt_f64_e64 s0, v[2:3], v[19:20]
	v_cndmask_b32_e32 v0, v0, v63, vcc_lo
	v_cvt_f64_i32_e32 v[5:6], v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v3, v3, v20, s0
	v_cndmask_b32_e64 v2, v2, v19, s0
	v_cvt_i32_f64_e32 v61, v[2:3]
	s_delay_alu instid0(VALU_DEP_4)
	v_max_f64 v[4:5], v[5:6], 0
	v_max_f64 v[6:7], v[7:8], 0
	v_max_f64 v[8:9], v[9:10], 0
	v_max_f64 v[10:11], v[11:12], 0
	v_max_f64 v[12:13], v[13:14], 0
	v_max_f64 v[14:15], v[15:16], 0
	v_max_f64 v[16:17], v[17:18], 0
	v_cmp_gt_f64_e64 s1, v[4:5], v[19:20]
	v_cmp_gt_f64_e64 s2, v[6:7], v[19:20]
	v_cmp_gt_f64_e64 s3, v[8:9], v[19:20]
	v_cmp_gt_f64_e64 s4, v[10:11], v[19:20]
	v_cmp_gt_f64_e64 s5, v[12:13], v[19:20]
	v_cmp_gt_f64_e64 s6, v[14:15], v[19:20]
	v_cmp_gt_f64_e64 s7, v[16:17], v[66:67]
	v_cndmask_b32_e64 v5, v5, v20, s1
	v_cndmask_b32_e64 v4, v4, v19, s1
	v_cndmask_b32_e64 v7, v7, v20, s2
	v_cndmask_b32_e64 v11, v11, v20, s4
	v_cndmask_b32_e64 v6, v6, v19, s2
	v_cndmask_b32_e64 v10, v10, v19, s4
	v_cvt_i32_f64_e32 v2, v[4:5]
	v_cndmask_b32_e32 v1, v1, v64, vcc_lo
	v_cndmask_b32_e64 v17, v17, v67, s7
	v_cndmask_b32_e64 v16, v16, v66, s7
	v_cndmask_b32_e64 v9, v9, v20, s3
	v_cndmask_b32_e64 v8, v8, v19, s3
	v_cvt_i32_f64_e32 v18, v[0:1]
	v_cndmask_b32_e64 v1, v13, v20, s5
	v_cndmask_b32_e64 v13, v15, v20, s6
	v_cndmask_b32_e64 v0, v12, v19, s5
	v_cndmask_b32_e64 v12, v14, v19, s6
	v_cvt_i32_f64_e32 v62, v[16:17]
	v_cvt_i32_f64_e32 v3, v[6:7]
	v_cvt_i32_f64_e32 v5, v[10:11]
	v_cvt_i32_f64_e32 v0, v[0:1]
	v_cvt_i32_f64_e32 v1, v[12:13]
	v_cvt_i32_f64_e32 v4, v[8:9]
	v_mul_lo_u32 v6, v18, s85
	s_delay_alu instid0(VALU_DEP_1)
	v_add_nc_u32_e32 v2, v6, v2
	v_add_nc_u32_e32 v7, v6, v61
	v_add_nc_u32_e32 v10, v6, v0
	v_add_nc_u32_e32 v8, v6, v1
	v_add_nc_u32_e32 v3, v6, v3
	v_mad_u64_u32 v[0:1], null, v2, s84, v[62:63]
	v_mul_lo_u32 v47, v7, s84
	v_add_nc_u32_e32 v7, v6, v5
	v_add_nc_u32_e32 v14, v6, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mad_u64_u32 v[4:5], null, v7, s84, v[62:63]
	v_add_nc_u32_e32 v1, v47, v62
	v_mad_u64_u32 v[6:7], null, v8, s84, v[62:63]
	v_mad_u64_u32 v[8:9], null, v10, s84, v[62:63]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_ashrrev_i32_e32 v2, 31, v1
	v_mad_u64_u32 v[10:11], null, v3, s84, v[62:63]
	v_mad_u64_u32 v[12:13], null, v14, s84, v[62:63]
	v_lshlrev_b64 v[56:57], 3, v[1:2]
	v_ashrrev_i32_e32 v7, 31, v6
	v_ashrrev_i32_e32 v9, 31, v8
	v_ashrrev_i32_e32 v1, 31, v0
	v_ashrrev_i32_e32 v11, 31, v10
	v_ashrrev_i32_e32 v5, 31, v4
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v2, vcc_lo, s76, v56
	v_add_co_ci_u32_e32 v3, vcc_lo, s77, v57, vcc_lo
	v_add_co_u32 v14, vcc_lo, s78, v56
	v_add_co_ci_u32_e32 v15, vcc_lo, s79, v57, vcc_lo
	global_load_b64 v[2:3], v[2:3], off
	global_load_b64 v[18:19], v[14:15], off
	v_lshlrev_b64 v[6:7], 3, v[6:7]
	v_lshlrev_b64 v[8:9], 3, v[8:9]
	v_lshlrev_b64 v[0:1], 3, v[0:1]
	v_ashrrev_i32_e32 v13, 31, v12
	v_lshlrev_b64 v[10:11], 3, v[10:11]
	v_lshlrev_b64 v[4:5], 3, v[4:5]
	v_add_co_u32 v14, vcc_lo, s74, v6
	v_add_co_ci_u32_e32 v15, vcc_lo, s75, v7, vcc_lo
	v_add_co_u32 v16, vcc_lo, s74, v8
	v_add_co_ci_u32_e32 v17, vcc_lo, s75, v9, vcc_lo
	v_lshlrev_b64 v[12:13], 3, v[12:13]
	v_add_co_u32 v0, vcc_lo, s74, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s75, v1, vcc_lo
	v_add_co_u32 v6, vcc_lo, s74, v10
	v_add_co_ci_u32_e32 v7, vcc_lo, s75, v11, vcc_lo
	v_add_co_u32 v8, vcc_lo, s74, v12
	v_add_co_ci_u32_e32 v9, vcc_lo, s75, v13, vcc_lo
	v_add_co_u32 v10, vcc_lo, s74, v56
	v_add_co_ci_u32_e32 v11, vcc_lo, s75, v57, vcc_lo
	v_add_co_u32 v4, vcc_lo, s74, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s75, v5, vcc_lo
	s_clause 0x6
	global_load_b64 v[68:69], v[0:1], off
	global_load_b64 v[6:7], v[6:7], off
	global_load_b64 v[8:9], v[8:9], off
	global_load_b64 v[58:59], v[10:11], off
	global_load_b64 v[14:15], v[14:15], off
	global_load_b64 v[16:17], v[16:17], off
	global_load_b64 v[70:71], v[4:5], off
	s_load_b128 s[76:79], s[62:63], 0x60
                                        ; implicit-def: $vgpr0_vgpr1
	s_waitcnt vmcnt(8) lgkmcnt(0)
	v_cmp_ngt_f64_e64 s64, s[76:77], v[2:3]
	s_waitcnt vmcnt(7)
	v_cmp_ngt_f64_e64 s33, s[76:77], v[18:19]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, s64, s33
	s_and_saveexec_b32 s1, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s65, exec_lo, s1
	s_cbranch_execz .LBB1_3
; %bb.2:
	s_waitcnt vmcnt(1)
	v_add_f64 v[0:1], v[16:17], -v[14:15]
	s_waitcnt vmcnt(0)
	v_add_f64 v[2:3], v[70:71], -v[16:17]
	v_add_f64 v[4:5], v[58:59], -v[70:71]
	v_add_f64 v[10:11], v[68:69], -v[58:59]
	v_add_f64 v[12:13], v[6:7], -v[68:69]
	v_add_f64 v[6:7], v[8:9], -v[6:7]
	s_getpc_b64 s[86:87]
	s_add_u32 s86, s86, _Z24weno_onesided_derivativeddddd@rel32@lo+4
	s_addc_u32 s87, s87, _Z24weno_onesided_derivativeddddd@rel32@hi+12
	v_div_scale_f64 v[8:9], null, s[76:77], s[76:77], v[0:1]
	v_div_scale_f64 v[14:15], null, s[76:77], s[76:77], v[2:3]
	v_div_scale_f64 v[16:17], null, s[76:77], s[76:77], v[4:5]
	v_div_scale_f64 v[18:19], null, s[76:77], s[76:77], v[10:11]
	v_div_scale_f64 v[20:21], null, s[76:77], s[76:77], v[12:13]
	v_div_scale_f64 v[22:23], null, s[76:77], s[76:77], v[6:7]
	v_div_scale_f64 v[50:51], vcc_lo, v[0:1], s[76:77], v[0:1]
	v_rcp_f64_e32 v[24:25], v[8:9]
	v_rcp_f64_e32 v[26:27], v[14:15]
	v_rcp_f64_e32 v[28:29], v[16:17]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_rcp_f64_e32 v[30:31], v[18:19]
	v_rcp_f64_e32 v[32:33], v[20:21]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(TRANS32_DEP_3)
	v_rcp_f64_e32 v[34:35], v[22:23]
	v_fma_f64 v[36:37], -v[8:9], v[24:25], 1.0
	v_fma_f64 v[38:39], -v[14:15], v[26:27], 1.0
	v_fma_f64 v[40:41], -v[16:17], v[28:29], 1.0
	v_fma_f64 v[42:43], -v[18:19], v[30:31], 1.0
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[44:45], -v[20:21], v[32:33], 1.0
	v_fma_f64 v[48:49], -v[22:23], v[34:35], 1.0
	v_fma_f64 v[24:25], v[24:25], v[36:37], v[24:25]
	v_fma_f64 v[26:27], v[26:27], v[38:39], v[26:27]
	v_fma_f64 v[28:29], v[28:29], v[40:41], v[28:29]
	v_fma_f64 v[30:31], v[30:31], v[42:43], v[30:31]
	v_fma_f64 v[32:33], v[32:33], v[44:45], v[32:33]
	v_fma_f64 v[34:35], v[34:35], v[48:49], v[34:35]
	v_fma_f64 v[36:37], -v[8:9], v[24:25], 1.0
	v_fma_f64 v[38:39], -v[14:15], v[26:27], 1.0
	v_fma_f64 v[40:41], -v[16:17], v[28:29], 1.0
	v_fma_f64 v[42:43], -v[18:19], v[30:31], 1.0
	v_fma_f64 v[44:45], -v[20:21], v[32:33], 1.0
	v_fma_f64 v[48:49], -v[22:23], v[34:35], 1.0
	v_fma_f64 v[24:25], v[24:25], v[36:37], v[24:25]
	v_div_scale_f64 v[36:37], s0, v[2:3], s[76:77], v[2:3]
	v_fma_f64 v[26:27], v[26:27], v[38:39], v[26:27]
	v_div_scale_f64 v[38:39], s1, v[4:5], s[76:77], v[4:5]
	v_fma_f64 v[28:29], v[28:29], v[40:41], v[28:29]
	v_div_scale_f64 v[40:41], s2, v[10:11], s[76:77], v[10:11]
	v_fma_f64 v[30:31], v[30:31], v[42:43], v[30:31]
	v_div_scale_f64 v[42:43], s3, v[12:13], s[76:77], v[12:13]
	v_fma_f64 v[32:33], v[32:33], v[44:45], v[32:33]
	v_fma_f64 v[34:35], v[34:35], v[48:49], v[34:35]
	v_div_scale_f64 v[44:45], s4, v[6:7], s[76:77], v[6:7]
	v_mul_f64 v[48:49], v[50:51], v[24:25]
	v_mul_f64 v[52:53], v[36:37], v[26:27]
	v_mul_f64 v[54:55], v[38:39], v[28:29]
	v_mul_f64 v[72:73], v[40:41], v[30:31]
	v_mul_f64 v[74:75], v[42:43], v[32:33]
	v_mul_f64 v[76:77], v[44:45], v[34:35]
	v_fma_f64 v[8:9], -v[8:9], v[48:49], v[50:51]
	v_fma_f64 v[14:15], -v[14:15], v[52:53], v[36:37]
	v_fma_f64 v[16:17], -v[16:17], v[54:55], v[38:39]
	v_fma_f64 v[18:19], -v[18:19], v[72:73], v[40:41]
	v_fma_f64 v[20:21], -v[20:21], v[74:75], v[42:43]
	v_fma_f64 v[22:23], -v[22:23], v[76:77], v[44:45]
	v_div_fmas_f64 v[8:9], v[8:9], v[24:25], v[48:49]
	s_mov_b32 vcc_lo, s0
	v_div_fmas_f64 v[14:15], v[14:15], v[26:27], v[52:53]
	s_mov_b32 vcc_lo, s1
	v_div_fmas_f64 v[16:17], v[16:17], v[28:29], v[54:55]
	s_mov_b32 vcc_lo, s2
	v_div_fmas_f64 v[18:19], v[18:19], v[30:31], v[72:73]
	s_mov_b32 vcc_lo, s3
	v_div_fmas_f64 v[20:21], v[20:21], v[32:33], v[74:75]
	s_mov_b32 vcc_lo, s4
	v_div_fmas_f64 v[22:23], v[22:23], v[34:35], v[76:77]
	v_div_fixup_f64 v[0:1], v[8:9], s[76:77], v[0:1]
	v_div_fixup_f64 v[43:44], v[14:15], s[76:77], v[2:3]
	v_div_fixup_f64 v[45:46], v[16:17], s[76:77], v[4:5]
	v_div_fixup_f64 v[50:51], v[18:19], s[76:77], v[10:11]
	v_div_fixup_f64 v[52:53], v[20:21], s[76:77], v[12:13]
	v_div_fixup_f64 v[54:55], v[22:23], s[76:77], v[6:7]
	v_dual_mov_b32 v2, v43 :: v_dual_mov_b32 v3, v44
	v_dual_mov_b32 v4, v45 :: v_dual_mov_b32 v5, v46
	v_dual_mov_b32 v6, v50 :: v_dual_mov_b32 v7, v51
	v_dual_mov_b32 v8, v52 :: v_dual_mov_b32 v9, v53
	s_swappc_b64 s[30:31], s[86:87]
	v_dual_mov_b32 v41, v0 :: v_dual_mov_b32 v42, v1
	v_dual_mov_b32 v0, v54 :: v_dual_mov_b32 v1, v55
	v_dual_mov_b32 v2, v52 :: v_dual_mov_b32 v3, v53
	v_dual_mov_b32 v4, v50 :: v_dual_mov_b32 v5, v51
	v_dual_mov_b32 v6, v45 :: v_dual_mov_b32 v7, v46
	v_dual_mov_b32 v8, v43 :: v_dual_mov_b32 v9, v44
	s_swappc_b64 s[30:31], s[86:87]
                                        ; implicit-def: $vgpr16_vgpr17
                                        ; implicit-def: $vgpr14_vgpr15
                                        ; implicit-def: $vgpr18_vgpr19
                                        ; implicit-def: $vgpr2_vgpr3
                                        ; implicit-def: $vgpr6_vgpr7
                                        ; implicit-def: $vgpr8_vgpr9
.LBB1_3:                                ; %Flow393
	s_and_not1_saveexec_b32 s5, s65
	s_cbranch_execz .LBB1_11
; %bb.4:
	v_add_f64 v[4:5], s[76:77], s[76:77]
	v_mov_b32_e32 v20, 0
	s_waitcnt vmcnt(6)
	v_dual_mov_b32 v21, 0 :: v_dual_mov_b32 v22, v68
	v_dual_mov_b32 v0, s76 :: v_dual_mov_b32 v1, s77
	v_mov_b32_e32 v23, v69
	s_and_saveexec_b32 s0, s64
	s_cbranch_execz .LBB1_6
; %bb.5:
	v_mul_f64 v[10:11], 0x40080000, s[76:77]
	v_dual_mov_b32 v2, s76 :: v_dual_mov_b32 v3, s77
	v_dual_mov_b32 v0, v4 :: v_dual_mov_b32 v1, v5
	v_dual_mov_b32 v20, v68 :: v_dual_mov_b32 v21, v69
	s_waitcnt vmcnt(5)
	v_dual_mov_b32 v23, v7 :: v_dual_mov_b32 v22, v6
	s_waitcnt vmcnt(4)
	v_dual_mov_b32 v6, v8 :: v_dual_mov_b32 v7, v9
	v_dual_mov_b32 v4, v10 :: v_dual_mov_b32 v5, v11
.LBB1_6:
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $vgpr8_vgpr9
                                        ; implicit-def: $sgpr0_sgpr1
                                        ; implicit-def: $sgpr2_sgpr3
	s_and_saveexec_b32 s4, s33
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s4, exec_lo, s4
	s_cbranch_execz .LBB1_8
; %bb.7:
	s_mov_b32 s2, 0
	s_waitcnt vmcnt(4)
	v_mul_f64 v[8:9], s[76:77], -2.0
	s_mov_b32 s3, 0xc0080000
	s_xor_b32 s1, s77, 0x80000000
	s_mov_b32 s0, s76
                                        ; implicit-def: $vgpr18_vgpr19
.LBB1_8:                                ; %Flow390
	s_or_saveexec_b32 s4, s4
	v_dual_mov_b32 v11, s3 :: v_dual_mov_b32 v10, s2
	v_dual_mov_b32 v13, s1 :: v_dual_mov_b32 v12, s0
	s_waitcnt vmcnt(0)
	v_dual_mov_b32 v26, v70 :: v_dual_mov_b32 v27, v71
	v_dual_mov_b32 v25, v17 :: v_dual_mov_b32 v24, v16
	s_xor_b32 exec_lo, exec_lo, s4
; %bb.9:
	v_xor_b32_e32 v19, 0x80000000, v19
	s_xor_b32 s1, s77, 0x80000000
	s_mov_b32 s0, s76
	v_mov_b32_e32 v26, 0
	v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v9, s1
	v_dual_mov_b32 v27, 0 :: v_dual_mov_b32 v12, v18
	v_dual_mov_b32 v11, -2.0 :: v_dual_mov_b32 v8, s0
	v_dual_mov_b32 v13, v19 :: v_dual_mov_b32 v24, v70
	v_dual_mov_b32 v25, v71 :: v_dual_mov_b32 v14, v16
	v_mov_b32_e32 v15, v17
; %bb.10:                               ; %_Z14select_stencilRdS_S_S_S_S_S_S_S_S_S_S_S_S_dddddddddddddddd.exit.i.i
	s_or_b32 exec_lo, exec_lo, s4
	v_add_f64 v[16:17], v[6:7], -v[22:23]
	v_add_f64 v[18:19], v[4:5], -v[0:1]
	v_add_f64 v[22:23], v[22:23], -v[20:21]
	v_add_f64 v[28:29], v[0:1], -v[2:3]
	v_add_f64 v[20:21], v[20:21], -v[58:59]
	v_add_f64 v[30:31], v[58:59], -v[26:27]
	v_add_f64 v[6:7], -v[12:13], 0
	v_add_f64 v[26:27], v[26:27], -v[24:25]
	v_add_f64 v[32:33], v[12:13], -v[8:9]
	v_add_f64 v[14:15], v[24:25], -v[14:15]
	v_fma_f64 v[24:25], -v[10:11], s[76:77], v[8:9]
	v_div_scale_f64 v[34:35], null, v[18:19], v[18:19], v[16:17]
	v_div_scale_f64 v[36:37], null, v[28:29], v[28:29], v[22:23]
	v_div_scale_f64 v[38:39], null, v[2:3], v[2:3], v[20:21]
	v_div_scale_f64 v[40:41], null, v[6:7], v[6:7], v[30:31]
	v_div_scale_f64 v[42:43], null, v[32:33], v[32:33], v[26:27]
	v_div_scale_f64 v[44:45], null, v[24:25], v[24:25], v[14:15]
	v_div_scale_f64 v[88:89], vcc_lo, v[16:17], v[18:19], v[16:17]
	v_rcp_f64_e32 v[48:49], v[34:35]
	v_rcp_f64_e32 v[50:51], v[36:37]
	v_rcp_f64_e32 v[52:53], v[38:39]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_rcp_f64_e32 v[54:55], v[40:41]
	v_rcp_f64_e32 v[72:73], v[42:43]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(TRANS32_DEP_3)
	v_rcp_f64_e32 v[74:75], v[44:45]
	v_fma_f64 v[76:77], -v[34:35], v[48:49], 1.0
	v_fma_f64 v[78:79], -v[36:37], v[50:51], 1.0
	v_fma_f64 v[80:81], -v[38:39], v[52:53], 1.0
	v_fma_f64 v[82:83], -v[40:41], v[54:55], 1.0
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[84:85], -v[42:43], v[72:73], 1.0
	v_fma_f64 v[86:87], -v[44:45], v[74:75], 1.0
	v_fma_f64 v[48:49], v[48:49], v[76:77], v[48:49]
	v_fma_f64 v[50:51], v[50:51], v[78:79], v[50:51]
	v_fma_f64 v[52:53], v[52:53], v[80:81], v[52:53]
	v_fma_f64 v[54:55], v[54:55], v[82:83], v[54:55]
	v_fma_f64 v[72:73], v[72:73], v[84:85], v[72:73]
	v_fma_f64 v[74:75], v[74:75], v[86:87], v[74:75]
	v_fma_f64 v[76:77], -v[34:35], v[48:49], 1.0
	v_fma_f64 v[78:79], -v[36:37], v[50:51], 1.0
	v_fma_f64 v[80:81], -v[38:39], v[52:53], 1.0
	v_fma_f64 v[82:83], -v[40:41], v[54:55], 1.0
	v_fma_f64 v[84:85], -v[42:43], v[72:73], 1.0
	v_fma_f64 v[86:87], -v[44:45], v[74:75], 1.0
	v_fma_f64 v[48:49], v[48:49], v[76:77], v[48:49]
	v_div_scale_f64 v[76:77], s0, v[22:23], v[28:29], v[22:23]
	v_fma_f64 v[50:51], v[50:51], v[78:79], v[50:51]
	v_div_scale_f64 v[78:79], s1, v[20:21], v[2:3], v[20:21]
	v_fma_f64 v[52:53], v[52:53], v[80:81], v[52:53]
	v_div_scale_f64 v[80:81], s2, v[30:31], v[6:7], v[30:31]
	v_fma_f64 v[54:55], v[54:55], v[82:83], v[54:55]
	v_div_scale_f64 v[82:83], s3, v[26:27], v[32:33], v[26:27]
	v_fma_f64 v[72:73], v[72:73], v[84:85], v[72:73]
	v_div_scale_f64 v[84:85], s4, v[14:15], v[24:25], v[14:15]
	v_fma_f64 v[74:75], v[74:75], v[86:87], v[74:75]
	v_mul_f64 v[86:87], v[88:89], v[48:49]
	v_mul_f64 v[90:91], v[76:77], v[50:51]
	v_mul_f64 v[92:93], v[78:79], v[52:53]
	v_mul_f64 v[94:95], v[80:81], v[54:55]
	v_mul_f64 v[96:97], v[82:83], v[72:73]
	v_mul_f64 v[98:99], v[84:85], v[74:75]
	v_fma_f64 v[34:35], -v[34:35], v[86:87], v[88:89]
	v_fma_f64 v[36:37], -v[36:37], v[90:91], v[76:77]
	v_fma_f64 v[38:39], -v[38:39], v[92:93], v[78:79]
	v_fma_f64 v[40:41], -v[40:41], v[94:95], v[80:81]
	v_fma_f64 v[42:43], -v[42:43], v[96:97], v[82:83]
	v_fma_f64 v[44:45], -v[44:45], v[98:99], v[84:85]
	v_div_fmas_f64 v[34:35], v[34:35], v[48:49], v[86:87]
	s_mov_b32 vcc_lo, s0
	v_div_fmas_f64 v[36:37], v[36:37], v[50:51], v[90:91]
	s_mov_b32 vcc_lo, s1
	v_div_fmas_f64 v[38:39], v[38:39], v[52:53], v[92:93]
	s_mov_b32 vcc_lo, s2
	v_div_fmas_f64 v[40:41], v[40:41], v[54:55], v[94:95]
	s_mov_b32 vcc_lo, s3
	v_div_fmas_f64 v[42:43], v[42:43], v[72:73], v[96:97]
	s_mov_b32 vcc_lo, s4
	v_div_fmas_f64 v[44:45], v[44:45], v[74:75], v[98:99]
	v_div_fixup_f64 v[16:17], v[34:35], v[18:19], v[16:17]
	v_div_fixup_f64 v[18:19], v[36:37], v[28:29], v[22:23]
	v_add_f64 v[28:29], v[2:3], -v[12:13]
	v_fma_f64 v[36:37], -v[10:11], s[76:77], v[12:13]
	v_div_fixup_f64 v[20:21], v[38:39], v[2:3], v[20:21]
	v_add_f64 v[12:13], v[0:1], -v[12:13]
	v_fma_f64 v[10:11], -v[10:11], s[76:77], 0
	v_div_fixup_f64 v[22:23], v[40:41], v[6:7], v[30:31]
	v_div_fixup_f64 v[26:27], v[42:43], v[32:33], v[26:27]
	v_add_f64 v[32:33], -v[8:9], 0
	v_add_f64 v[8:9], v[2:3], -v[8:9]
	v_div_fixup_f64 v[14:15], v[44:45], v[24:25], v[14:15]
	v_add_f64 v[24:25], v[4:5], -v[2:3]
	v_add_f64 v[2:3], -v[2:3], 0
	v_add_f64 v[16:17], v[16:17], -v[18:19]
	v_add_f64 v[18:19], v[18:19], -v[20:21]
	v_add_f64 v[30:31], v[20:21], -v[22:23]
	v_add_f64 v[34:35], v[22:23], -v[26:27]
	v_add_f64 v[14:15], v[26:27], -v[14:15]
	v_div_scale_f64 v[26:27], null, v[24:25], v[24:25], v[16:17]
	v_div_scale_f64 v[84:85], vcc_lo, v[16:17], v[24:25], v[16:17]
	v_div_scale_f64 v[38:39], null, v[0:1], v[0:1], v[18:19]
	v_div_scale_f64 v[40:41], null, v[28:29], v[28:29], v[30:31]
	v_div_scale_f64 v[42:43], null, v[32:33], v[32:33], v[34:35]
	v_div_scale_f64 v[44:45], null, v[36:37], v[36:37], v[14:15]
	v_rcp_f64_e32 v[48:49], v[26:27]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_rcp_f64_e32 v[50:51], v[38:39]
	v_rcp_f64_e32 v[52:53], v[40:41]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[54:55], v[42:43]
	v_rcp_f64_e32 v[72:73], v[44:45]
	v_fma_f64 v[74:75], -v[26:27], v[48:49], 1.0
	v_fma_f64 v[76:77], -v[38:39], v[50:51], 1.0
	s_delay_alu instid0(TRANS32_DEP_3)
	v_fma_f64 v[78:79], -v[40:41], v[52:53], 1.0
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[80:81], -v[42:43], v[54:55], 1.0
	v_fma_f64 v[82:83], -v[44:45], v[72:73], 1.0
	v_fma_f64 v[48:49], v[48:49], v[74:75], v[48:49]
	v_fma_f64 v[50:51], v[50:51], v[76:77], v[50:51]
	v_fma_f64 v[52:53], v[52:53], v[78:79], v[52:53]
	v_fma_f64 v[54:55], v[54:55], v[80:81], v[54:55]
	v_fma_f64 v[72:73], v[72:73], v[82:83], v[72:73]
	v_fma_f64 v[74:75], -v[26:27], v[48:49], 1.0
	v_fma_f64 v[76:77], -v[38:39], v[50:51], 1.0
	v_fma_f64 v[78:79], -v[40:41], v[52:53], 1.0
	v_fma_f64 v[80:81], -v[42:43], v[54:55], 1.0
	v_fma_f64 v[82:83], -v[44:45], v[72:73], 1.0
	v_fma_f64 v[48:49], v[48:49], v[74:75], v[48:49]
	v_div_scale_f64 v[74:75], s0, v[18:19], v[0:1], v[18:19]
	v_fma_f64 v[50:51], v[50:51], v[76:77], v[50:51]
	v_div_scale_f64 v[76:77], s1, v[30:31], v[28:29], v[30:31]
	v_fma_f64 v[52:53], v[52:53], v[78:79], v[52:53]
	v_div_scale_f64 v[78:79], s2, v[34:35], v[32:33], v[34:35]
	v_fma_f64 v[54:55], v[54:55], v[80:81], v[54:55]
	v_div_scale_f64 v[80:81], s3, v[14:15], v[36:37], v[14:15]
	v_fma_f64 v[72:73], v[72:73], v[82:83], v[72:73]
	v_mul_f64 v[82:83], v[84:85], v[48:49]
	v_mul_f64 v[86:87], v[74:75], v[50:51]
	v_mul_f64 v[88:89], v[76:77], v[52:53]
	v_mul_f64 v[90:91], v[78:79], v[54:55]
	v_mul_f64 v[92:93], v[80:81], v[72:73]
	v_fma_f64 v[26:27], -v[26:27], v[82:83], v[84:85]
	v_fma_f64 v[38:39], -v[38:39], v[86:87], v[74:75]
	v_fma_f64 v[40:41], -v[40:41], v[88:89], v[76:77]
	v_fma_f64 v[42:43], -v[42:43], v[90:91], v[78:79]
	v_fma_f64 v[44:45], -v[44:45], v[92:93], v[80:81]
	v_div_fmas_f64 v[26:27], v[26:27], v[48:49], v[82:83]
	s_mov_b32 vcc_lo, s0
	v_div_fmas_f64 v[38:39], v[38:39], v[50:51], v[86:87]
	s_mov_b32 vcc_lo, s1
	v_div_fmas_f64 v[40:41], v[40:41], v[52:53], v[88:89]
	s_mov_b32 vcc_lo, s2
	v_div_fmas_f64 v[42:43], v[42:43], v[54:55], v[90:91]
	s_mov_b32 vcc_lo, s3
	v_div_fmas_f64 v[44:45], v[44:45], v[72:73], v[92:93]
	v_div_fixup_f64 v[16:17], v[26:27], v[24:25], v[16:17]
	v_div_fixup_f64 v[18:19], v[38:39], v[0:1], v[18:19]
	v_add_f64 v[0:1], -v[0:1], 0
	v_div_fixup_f64 v[24:25], v[40:41], v[28:29], v[30:31]
	v_div_fixup_f64 v[26:27], v[42:43], v[32:33], v[34:35]
	v_div_fixup_f64 v[14:15], v[44:45], v[36:37], v[14:15]
	v_add_f64 v[16:17], v[16:17], -v[18:19]
	v_mul_f64 v[0:1], v[2:3], v[0:1]
	v_add_f64 v[28:29], v[18:19], -v[24:25]
	v_add_f64 v[30:31], v[24:25], -v[26:27]
	v_add_f64 v[14:15], v[26:27], -v[14:15]
	v_div_scale_f64 v[34:35], null, v[4:5], v[4:5], v[16:17]
	v_div_scale_f64 v[76:77], vcc_lo, v[16:17], v[4:5], v[16:17]
	v_div_scale_f64 v[36:37], null, v[12:13], v[12:13], v[28:29]
	v_div_scale_f64 v[38:39], null, v[8:9], v[8:9], v[30:31]
	v_div_scale_f64 v[40:41], null, v[10:11], v[10:11], v[14:15]
	v_rcp_f64_e32 v[42:43], v[34:35]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rcp_f64_e32 v[44:45], v[36:37]
	v_rcp_f64_e32 v[48:49], v[38:39]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(TRANS32_DEP_3)
	v_rcp_f64_e32 v[50:51], v[40:41]
	v_fma_f64 v[52:53], -v[34:35], v[42:43], 1.0
	v_fma_f64 v[54:55], -v[36:37], v[44:45], 1.0
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[72:73], -v[38:39], v[48:49], 1.0
	v_fma_f64 v[74:75], -v[40:41], v[50:51], 1.0
	v_fma_f64 v[42:43], v[42:43], v[52:53], v[42:43]
	v_fma_f64 v[44:45], v[44:45], v[54:55], v[44:45]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[48:49], v[48:49], v[72:73], v[48:49]
	v_fma_f64 v[50:51], v[50:51], v[74:75], v[50:51]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[52:53], -v[34:35], v[42:43], 1.0
	v_fma_f64 v[54:55], -v[36:37], v[44:45], 1.0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[72:73], -v[38:39], v[48:49], 1.0
	v_fma_f64 v[74:75], -v[40:41], v[50:51], 1.0
	s_delay_alu instid0(VALU_DEP_4)
	v_fma_f64 v[42:43], v[42:43], v[52:53], v[42:43]
	v_div_scale_f64 v[52:53], s0, v[28:29], v[12:13], v[28:29]
	v_fma_f64 v[44:45], v[44:45], v[54:55], v[44:45]
	v_div_scale_f64 v[54:55], s1, v[30:31], v[8:9], v[30:31]
	v_fma_f64 v[48:49], v[48:49], v[72:73], v[48:49]
	v_div_scale_f64 v[72:73], s2, v[14:15], v[10:11], v[14:15]
	v_fma_f64 v[50:51], v[50:51], v[74:75], v[50:51]
	v_mul_f64 v[74:75], v[76:77], v[42:43]
	v_mul_f64 v[78:79], v[52:53], v[44:45]
	v_mul_f64 v[80:81], v[54:55], v[48:49]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mul_f64 v[82:83], v[72:73], v[50:51]
	v_fma_f64 v[34:35], -v[34:35], v[74:75], v[76:77]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[36:37], -v[36:37], v[78:79], v[52:53]
	v_fma_f64 v[38:39], -v[38:39], v[80:81], v[54:55]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[40:41], -v[40:41], v[82:83], v[72:73]
	v_div_fmas_f64 v[34:35], v[34:35], v[42:43], v[74:75]
	s_mov_b32 vcc_lo, s0
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_div_fmas_f64 v[36:37], v[36:37], v[44:45], v[78:79]
	s_mov_b32 vcc_lo, s1
	v_div_fmas_f64 v[38:39], v[38:39], v[48:49], v[80:81]
	s_mov_b32 vcc_lo, s2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_div_fmas_f64 v[40:41], v[40:41], v[50:51], v[82:83]
	v_div_fixup_f64 v[4:5], v[34:35], v[4:5], v[16:17]
	v_mul_f64 v[16:17], v[6:7], v[32:33]
	v_div_fixup_f64 v[12:13], v[36:37], v[12:13], v[28:29]
	v_div_fixup_f64 v[8:9], v[38:39], v[8:9], v[30:31]
	v_div_fixup_f64 v[10:11], v[40:41], v[10:11], v[14:15]
	v_mul_f64 v[14:15], v[2:3], v[6:7]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cmp_lt_f64_e64 vcc_lo, |v[12:13]|, |v[4:5]|
	v_cmp_lt_f64_e64 s0, |v[8:9]|, |v[12:13]|
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_cmp_lt_f64_e64 s1, |v[8:9]|, |v[10:11]|
	v_dual_cndmask_b32 v5, v5, v13 :: v_dual_cndmask_b32 v4, v4, v12
	v_cmp_lt_f64_e64 vcc_lo, |v[24:25]|, |v[18:19]|
	v_cndmask_b32_e64 v13, v13, v9, s0
	v_cndmask_b32_e64 v12, v12, v8, s0
	v_cmp_lt_f64_e64 s0, |v[26:27]|, |v[24:25]|
	v_cndmask_b32_e64 v9, v11, v9, s1
	v_cndmask_b32_e64 v8, v10, v8, s1
	v_mul_f64 v[0:1], v[0:1], v[4:5]
	v_mul_f64 v[4:5], v[14:15], v[12:13]
	v_mul_f64 v[10:11], v[24:25], v[26:27]
	v_mul_f64 v[12:13], v[18:19], v[24:25]
	v_mul_f64 v[8:9], v[16:17], v[8:9]
	v_dual_cndmask_b32 v14, v19, v25 :: v_dual_cndmask_b32 v15, v18, v24
	v_dual_cndmask_b32 v1, v1, v5 :: v_dual_cndmask_b32 v0, v0, v4
	v_cmp_ngt_f64_e64 s1, 0, v[10:11]
	v_cmp_ngt_f64_e64 s2, 0, v[12:13]
	v_cndmask_b32_e64 v9, v5, v9, s0
	v_cndmask_b32_e64 v5, v25, v27, s0
	v_cndmask_b32_e64 v10, v24, v26, s0
	v_cndmask_b32_e64 v8, v4, v8, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v13, 0, v5, s1
	v_cndmask_b32_e64 v11, 0, v14, s2
	v_cndmask_b32_e64 v12, 0, v10, s1
	v_cndmask_b32_e64 v10, 0, v15, s2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[5:6], v[6:7], v[12:13], v[22:23]
	v_fma_f64 v[2:3], v[2:3], v[10:11], v[20:21]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[41:42], v[5:6], v[8:9]
	v_add_f64 v[0:1], v[2:3], v[0:1]
.LBB1_11:                               ; %Flow394
	s_or_b32 exec_lo, exec_lo, s5
	s_waitcnt vmcnt(5)
	v_add_nc_u32_e32 v6, -3, v65
	s_waitcnt vmcnt(4)
	v_add_nc_u32_e32 v8, -2, v65
	v_add_nc_u32_e32 v10, -1, v65
	v_add_nc_u32_e32 v2, 1, v65
	v_add_nc_u32_e32 v4, 2, v65
	v_cvt_f64_i32_e32 v[6:7], v6
	v_cvt_f64_i32_e32 v[8:9], v8
	v_cvt_f64_i32_e32 v[10:11], v10
	v_cvt_f64_i32_e32 v[2:3], v2
	v_add_nc_u32_e32 v12, 3, v65
	v_cvt_f64_i32_e32 v[4:5], v4
	s_waitcnt vmcnt(0)
	v_cmp_lt_f64_e64 s5, |v[68:69]|, |v[70:71]|
	s_delay_alu instid0(VALU_DEP_3)
	v_cvt_f64_i32_e32 v[12:13], v12
	v_max_f64 v[6:7], v[6:7], 0
	v_max_f64 v[8:9], v[8:9], 0
	v_max_f64 v[10:11], v[10:11], 0
	v_max_f64 v[2:3], v[2:3], 0
	v_max_f64 v[4:5], v[4:5], 0
	v_cndmask_b32_e64 v1, v42, v1, s5
	v_cndmask_b32_e64 v0, v41, v0, s5
                                        ; implicit-def: $vgpr41_vgpr42
	v_max_f64 v[12:13], v[12:13], 0
	v_cmp_gt_f64_e64 s1, v[6:7], v[66:67]
	v_cmp_gt_f64_e64 s2, v[8:9], v[66:67]
	v_cmp_gt_f64_e64 s3, v[10:11], v[66:67]
	v_cmp_gt_f64_e32 vcc_lo, v[2:3], v[66:67]
	v_cmp_gt_f64_e64 s0, v[4:5], v[66:67]
	v_cmp_gt_f64_e64 s4, v[12:13], v[66:67]
	v_cndmask_b32_e64 v7, v7, v67, s1
	v_cndmask_b32_e64 v6, v6, v66, s1
	v_cndmask_b32_e64 v9, v9, v67, s2
	v_cndmask_b32_e32 v3, v3, v67, vcc_lo
	v_cndmask_b32_e64 v8, v8, v66, s2
	v_cndmask_b32_e64 v11, v11, v67, s3
	v_cvt_i32_f64_e32 v15, v[6:7]
	v_cndmask_b32_e64 v10, v10, v66, s3
	v_cndmask_b32_e32 v2, v2, v66, vcc_lo
	v_cvt_i32_f64_e32 v8, v[8:9]
	v_cndmask_b32_e64 v5, v5, v67, s0
	v_cndmask_b32_e64 v4, v4, v66, s0
	v_cvt_i32_f64_e32 v9, v[10:11]
	v_cvt_i32_f64_e32 v14, v[2:3]
	v_cndmask_b32_e64 v13, v13, v67, s4
	v_cndmask_b32_e64 v12, v12, v66, s4
	v_cvt_i32_f64_e32 v10, v[4:5]
	v_add_co_u32 v2, vcc_lo, s68, v56
	v_add_co_ci_u32_e32 v3, vcc_lo, s69, v57, vcc_lo
	s_delay_alu instid0(VALU_DEP_4)
	v_cvt_i32_f64_e32 v11, v[12:13]
	v_add_co_u32 v4, vcc_lo, s80, v56
	v_add_co_ci_u32_e32 v5, vcc_lo, s81, v57, vcc_lo
	v_add_co_u32 v6, vcc_lo, s82, v56
	v_add_co_ci_u32_e32 v7, vcc_lo, s83, v57, vcc_lo
	global_store_b64 v[2:3], v[0:1], off
	global_load_b64 v[2:3], v[4:5], off
	global_load_b64 v[18:19], v[6:7], off
	v_add_nc_u32_e32 v4, v47, v15
	v_add_nc_u32_e32 v6, v47, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_ashrrev_i32_e32 v5, 31, v4
	v_add_nc_u32_e32 v8, v47, v9
	v_add_nc_u32_e32 v0, v47, v14
	v_ashrrev_i32_e32 v7, 31, v6
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_lshlrev_b64 v[4:5], 3, v[4:5]
	v_ashrrev_i32_e32 v9, 31, v8
	v_add_nc_u32_e32 v10, v47, v10
	s_delay_alu instid0(VALU_DEP_4)
	v_lshlrev_b64 v[6:7], 3, v[6:7]
	v_ashrrev_i32_e32 v1, 31, v0
	v_add_nc_u32_e32 v12, v47, v11
	v_lshlrev_b64 v[8:9], 3, v[8:9]
	v_add_co_u32 v4, vcc_lo, s74, v4
	v_ashrrev_i32_e32 v11, 31, v10
	v_add_co_ci_u32_e32 v5, vcc_lo, s75, v5, vcc_lo
	v_lshlrev_b64 v[0:1], 3, v[0:1]
	v_add_co_u32 v6, vcc_lo, s74, v6
	v_ashrrev_i32_e32 v13, 31, v12
	v_add_co_ci_u32_e32 v7, vcc_lo, s75, v7, vcc_lo
	v_lshlrev_b64 v[10:11], 3, v[10:11]
	v_add_co_u32 v8, vcc_lo, s74, v8
	v_add_co_ci_u32_e32 v9, vcc_lo, s75, v9, vcc_lo
	v_lshlrev_b64 v[12:13], 3, v[12:13]
	v_add_co_u32 v0, vcc_lo, s74, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s75, v1, vcc_lo
	v_add_co_u32 v10, vcc_lo, s74, v10
	v_add_co_ci_u32_e32 v11, vcc_lo, s75, v11, vcc_lo
	v_add_co_u32 v12, vcc_lo, s74, v12
	v_add_co_ci_u32_e32 v13, vcc_lo, s75, v13, vcc_lo
	s_clause 0x5
	global_load_b64 v[14:15], v[4:5], off
	global_load_b64 v[16:17], v[6:7], off
	global_load_b64 v[65:66], v[8:9], off
	global_load_b64 v[67:68], v[0:1], off
	global_load_b64 v[6:7], v[10:11], off
	global_load_b64 v[8:9], v[12:13], off
                                        ; implicit-def: $vgpr0_vgpr1
	s_waitcnt vmcnt(7)
	v_cmp_ngt_f64_e64 s64, s[78:79], v[2:3]
	s_waitcnt vmcnt(6)
	v_cmp_ngt_f64_e64 s33, s[78:79], v[18:19]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, s64, s33
	s_and_saveexec_b32 s1, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s65, exec_lo, s1
	s_cbranch_execz .LBB1_13
; %bb.12:
	s_waitcnt vmcnt(4)
	v_add_f64 v[0:1], v[16:17], -v[14:15]
	s_waitcnt vmcnt(3)
	v_add_f64 v[2:3], v[65:66], -v[16:17]
	v_add_f64 v[4:5], v[58:59], -v[65:66]
	s_waitcnt vmcnt(2)
	v_add_f64 v[10:11], v[67:68], -v[58:59]
	s_waitcnt vmcnt(1)
	v_add_f64 v[12:13], v[6:7], -v[67:68]
	s_waitcnt vmcnt(0)
	v_add_f64 v[6:7], v[8:9], -v[6:7]
	s_getpc_b64 s[68:69]
	s_add_u32 s68, s68, _Z24weno_onesided_derivativeddddd@rel32@lo+4
	s_addc_u32 s69, s69, _Z24weno_onesided_derivativeddddd@rel32@hi+12
	v_div_scale_f64 v[8:9], null, s[78:79], s[78:79], v[0:1]
	v_div_scale_f64 v[14:15], null, s[78:79], s[78:79], v[2:3]
	v_div_scale_f64 v[16:17], null, s[78:79], s[78:79], v[4:5]
	v_div_scale_f64 v[18:19], null, s[78:79], s[78:79], v[10:11]
	v_div_scale_f64 v[20:21], null, s[78:79], s[78:79], v[12:13]
	v_div_scale_f64 v[22:23], null, s[78:79], s[78:79], v[6:7]
	v_div_scale_f64 v[48:49], vcc_lo, v[0:1], s[78:79], v[0:1]
	v_rcp_f64_e32 v[24:25], v[8:9]
	v_rcp_f64_e32 v[26:27], v[14:15]
	v_rcp_f64_e32 v[28:29], v[16:17]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_rcp_f64_e32 v[30:31], v[18:19]
	v_rcp_f64_e32 v[32:33], v[20:21]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(TRANS32_DEP_3)
	v_rcp_f64_e32 v[34:35], v[22:23]
	v_fma_f64 v[36:37], -v[8:9], v[24:25], 1.0
	v_fma_f64 v[38:39], -v[14:15], v[26:27], 1.0
	v_fma_f64 v[40:41], -v[16:17], v[28:29], 1.0
	v_fma_f64 v[42:43], -v[18:19], v[30:31], 1.0
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[44:45], -v[20:21], v[32:33], 1.0
	v_fma_f64 v[46:47], -v[22:23], v[34:35], 1.0
	v_fma_f64 v[24:25], v[24:25], v[36:37], v[24:25]
	v_fma_f64 v[26:27], v[26:27], v[38:39], v[26:27]
	v_fma_f64 v[28:29], v[28:29], v[40:41], v[28:29]
	v_fma_f64 v[30:31], v[30:31], v[42:43], v[30:31]
	v_fma_f64 v[32:33], v[32:33], v[44:45], v[32:33]
	v_fma_f64 v[34:35], v[34:35], v[46:47], v[34:35]
	v_fma_f64 v[36:37], -v[8:9], v[24:25], 1.0
	v_fma_f64 v[38:39], -v[14:15], v[26:27], 1.0
	v_fma_f64 v[40:41], -v[16:17], v[28:29], 1.0
	v_fma_f64 v[42:43], -v[18:19], v[30:31], 1.0
	v_fma_f64 v[44:45], -v[20:21], v[32:33], 1.0
	v_fma_f64 v[46:47], -v[22:23], v[34:35], 1.0
	v_fma_f64 v[24:25], v[24:25], v[36:37], v[24:25]
	v_div_scale_f64 v[36:37], s0, v[2:3], s[78:79], v[2:3]
	v_fma_f64 v[26:27], v[26:27], v[38:39], v[26:27]
	v_div_scale_f64 v[38:39], s1, v[4:5], s[78:79], v[4:5]
	v_fma_f64 v[28:29], v[28:29], v[40:41], v[28:29]
	v_div_scale_f64 v[40:41], s2, v[10:11], s[78:79], v[10:11]
	v_fma_f64 v[30:31], v[30:31], v[42:43], v[30:31]
	v_div_scale_f64 v[42:43], s3, v[12:13], s[78:79], v[12:13]
	v_fma_f64 v[32:33], v[32:33], v[44:45], v[32:33]
	v_fma_f64 v[34:35], v[34:35], v[46:47], v[34:35]
	v_div_scale_f64 v[44:45], s4, v[6:7], s[78:79], v[6:7]
	v_mul_f64 v[46:47], v[48:49], v[24:25]
	v_mul_f64 v[50:51], v[36:37], v[26:27]
	v_mul_f64 v[52:53], v[38:39], v[28:29]
	v_mul_f64 v[54:55], v[40:41], v[30:31]
	v_mul_f64 v[69:70], v[42:43], v[32:33]
	v_mul_f64 v[71:72], v[44:45], v[34:35]
	v_fma_f64 v[8:9], -v[8:9], v[46:47], v[48:49]
	v_fma_f64 v[14:15], -v[14:15], v[50:51], v[36:37]
	v_fma_f64 v[16:17], -v[16:17], v[52:53], v[38:39]
	v_fma_f64 v[18:19], -v[18:19], v[54:55], v[40:41]
	v_fma_f64 v[20:21], -v[20:21], v[69:70], v[42:43]
	v_fma_f64 v[22:23], -v[22:23], v[71:72], v[44:45]
	v_div_fmas_f64 v[8:9], v[8:9], v[24:25], v[46:47]
	s_mov_b32 vcc_lo, s0
	v_div_fmas_f64 v[14:15], v[14:15], v[26:27], v[50:51]
	s_mov_b32 vcc_lo, s1
	v_div_fmas_f64 v[16:17], v[16:17], v[28:29], v[52:53]
	s_mov_b32 vcc_lo, s2
	v_div_fmas_f64 v[18:19], v[18:19], v[30:31], v[54:55]
	s_mov_b32 vcc_lo, s3
	v_div_fmas_f64 v[20:21], v[20:21], v[32:33], v[69:70]
	s_mov_b32 vcc_lo, s4
	v_div_fmas_f64 v[22:23], v[22:23], v[34:35], v[71:72]
	v_div_fixup_f64 v[0:1], v[8:9], s[78:79], v[0:1]
	v_div_fixup_f64 v[43:44], v[14:15], s[78:79], v[2:3]
	v_div_fixup_f64 v[45:46], v[16:17], s[78:79], v[4:5]
	v_div_fixup_f64 v[50:51], v[18:19], s[78:79], v[10:11]
	v_div_fixup_f64 v[52:53], v[20:21], s[78:79], v[12:13]
	v_div_fixup_f64 v[54:55], v[22:23], s[78:79], v[6:7]
	v_dual_mov_b32 v2, v43 :: v_dual_mov_b32 v3, v44
	v_dual_mov_b32 v4, v45 :: v_dual_mov_b32 v5, v46
	v_dual_mov_b32 v6, v50 :: v_dual_mov_b32 v7, v51
	v_dual_mov_b32 v8, v52 :: v_dual_mov_b32 v9, v53
	s_swappc_b64 s[30:31], s[68:69]
	v_dual_mov_b32 v41, v0 :: v_dual_mov_b32 v42, v1
	v_dual_mov_b32 v0, v54 :: v_dual_mov_b32 v1, v55
	v_dual_mov_b32 v2, v52 :: v_dual_mov_b32 v3, v53
	v_dual_mov_b32 v4, v50 :: v_dual_mov_b32 v5, v51
	v_dual_mov_b32 v6, v45 :: v_dual_mov_b32 v7, v46
	v_dual_mov_b32 v8, v43 :: v_dual_mov_b32 v9, v44
	s_swappc_b64 s[30:31], s[68:69]
                                        ; implicit-def: $vgpr16_vgpr17
                                        ; implicit-def: $vgpr14_vgpr15
                                        ; implicit-def: $vgpr18_vgpr19
                                        ; implicit-def: $vgpr2_vgpr3
                                        ; implicit-def: $vgpr6_vgpr7
                                        ; implicit-def: $vgpr8_vgpr9
.LBB1_13:                               ; %Flow387
	s_and_not1_saveexec_b32 s5, s65
	s_cbranch_execz .LBB1_21
; %bb.14:
	v_add_f64 v[4:5], s[78:79], s[78:79]
	v_mov_b32_e32 v20, 0
	s_waitcnt vmcnt(2)
	v_dual_mov_b32 v21, 0 :: v_dual_mov_b32 v22, v67
	v_dual_mov_b32 v0, s78 :: v_dual_mov_b32 v1, s79
	v_mov_b32_e32 v23, v68
	s_and_saveexec_b32 s0, s64
	s_cbranch_execz .LBB1_16
; %bb.15:
	v_mul_f64 v[10:11], 0x40080000, s[78:79]
	v_dual_mov_b32 v2, s78 :: v_dual_mov_b32 v3, s79
	v_dual_mov_b32 v0, v4 :: v_dual_mov_b32 v1, v5
	v_dual_mov_b32 v20, v67 :: v_dual_mov_b32 v21, v68
	s_waitcnt vmcnt(1)
	v_dual_mov_b32 v23, v7 :: v_dual_mov_b32 v22, v6
	s_waitcnt vmcnt(0)
	v_dual_mov_b32 v6, v8 :: v_dual_mov_b32 v7, v9
	v_dual_mov_b32 v4, v10 :: v_dual_mov_b32 v5, v11
.LBB1_16:
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $vgpr8_vgpr9
                                        ; implicit-def: $sgpr0_sgpr1
                                        ; implicit-def: $sgpr2_sgpr3
	s_and_saveexec_b32 s4, s33
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s4, exec_lo, s4
	s_cbranch_execz .LBB1_18
; %bb.17:
	s_mov_b32 s2, 0
	s_waitcnt vmcnt(0)
	v_mul_f64 v[8:9], s[78:79], -2.0
	s_mov_b32 s3, 0xc0080000
	s_xor_b32 s1, s79, 0x80000000
	s_mov_b32 s0, s78
                                        ; implicit-def: $vgpr18_vgpr19
.LBB1_18:                               ; %Flow384
	s_or_saveexec_b32 s4, s4
	v_dual_mov_b32 v11, s3 :: v_dual_mov_b32 v10, s2
	v_dual_mov_b32 v13, s1 :: v_dual_mov_b32 v12, s0
	v_dual_mov_b32 v26, v65 :: v_dual_mov_b32 v27, v66
	v_dual_mov_b32 v25, v17 :: v_dual_mov_b32 v24, v16
	s_xor_b32 exec_lo, exec_lo, s4
	s_cbranch_execz .LBB1_20
; %bb.19:
	v_xor_b32_e32 v19, 0x80000000, v19
	s_xor_b32 s1, s79, 0x80000000
	s_mov_b32 s0, s78
	v_mov_b32_e32 v26, 0
	s_waitcnt vmcnt(0)
	v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v9, s1
	v_dual_mov_b32 v27, 0 :: v_dual_mov_b32 v12, v18
	v_dual_mov_b32 v11, -2.0 :: v_dual_mov_b32 v8, s0
	v_dual_mov_b32 v13, v19 :: v_dual_mov_b32 v24, v65
	v_dual_mov_b32 v25, v66 :: v_dual_mov_b32 v14, v16
	v_mov_b32_e32 v15, v17
.LBB1_20:                               ; %_Z14select_stencilRdS_S_S_S_S_S_S_S_S_S_S_S_S_dddddddddddddddd.exit.i.i293
	s_or_b32 exec_lo, exec_lo, s4
	s_waitcnt vmcnt(1)
	v_add_f64 v[16:17], v[6:7], -v[22:23]
	v_add_f64 v[18:19], v[4:5], -v[0:1]
	v_add_f64 v[22:23], v[22:23], -v[20:21]
	v_add_f64 v[28:29], v[0:1], -v[2:3]
	v_add_f64 v[20:21], v[20:21], -v[58:59]
	v_add_f64 v[30:31], v[58:59], -v[26:27]
	v_add_f64 v[6:7], -v[12:13], 0
	v_add_f64 v[26:27], v[26:27], -v[24:25]
	s_waitcnt vmcnt(0)
	v_add_f64 v[32:33], v[12:13], -v[8:9]
	v_add_f64 v[14:15], v[24:25], -v[14:15]
	v_fma_f64 v[24:25], -v[10:11], s[78:79], v[8:9]
	v_div_scale_f64 v[34:35], null, v[18:19], v[18:19], v[16:17]
	v_div_scale_f64 v[36:37], null, v[28:29], v[28:29], v[22:23]
	v_div_scale_f64 v[38:39], null, v[2:3], v[2:3], v[20:21]
	v_div_scale_f64 v[40:41], null, v[6:7], v[6:7], v[30:31]
	v_div_scale_f64 v[42:43], null, v[32:33], v[32:33], v[26:27]
	v_div_scale_f64 v[44:45], null, v[24:25], v[24:25], v[14:15]
	v_div_scale_f64 v[83:84], vcc_lo, v[16:17], v[18:19], v[16:17]
	v_rcp_f64_e32 v[46:47], v[34:35]
	v_rcp_f64_e32 v[48:49], v[36:37]
	v_rcp_f64_e32 v[50:51], v[38:39]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_rcp_f64_e32 v[52:53], v[40:41]
	v_rcp_f64_e32 v[54:55], v[42:43]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(TRANS32_DEP_3)
	v_rcp_f64_e32 v[69:70], v[44:45]
	v_fma_f64 v[71:72], -v[34:35], v[46:47], 1.0
	v_fma_f64 v[73:74], -v[36:37], v[48:49], 1.0
	v_fma_f64 v[75:76], -v[38:39], v[50:51], 1.0
	v_fma_f64 v[77:78], -v[40:41], v[52:53], 1.0
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[79:80], -v[42:43], v[54:55], 1.0
	v_fma_f64 v[81:82], -v[44:45], v[69:70], 1.0
	v_fma_f64 v[46:47], v[46:47], v[71:72], v[46:47]
	v_fma_f64 v[48:49], v[48:49], v[73:74], v[48:49]
	v_fma_f64 v[50:51], v[50:51], v[75:76], v[50:51]
	v_fma_f64 v[52:53], v[52:53], v[77:78], v[52:53]
	v_fma_f64 v[54:55], v[54:55], v[79:80], v[54:55]
	v_fma_f64 v[69:70], v[69:70], v[81:82], v[69:70]
	v_fma_f64 v[71:72], -v[34:35], v[46:47], 1.0
	v_fma_f64 v[73:74], -v[36:37], v[48:49], 1.0
	v_fma_f64 v[75:76], -v[38:39], v[50:51], 1.0
	v_fma_f64 v[77:78], -v[40:41], v[52:53], 1.0
	v_fma_f64 v[79:80], -v[42:43], v[54:55], 1.0
	v_fma_f64 v[81:82], -v[44:45], v[69:70], 1.0
	v_fma_f64 v[46:47], v[46:47], v[71:72], v[46:47]
	v_div_scale_f64 v[71:72], s0, v[22:23], v[28:29], v[22:23]
	v_fma_f64 v[48:49], v[48:49], v[73:74], v[48:49]
	v_div_scale_f64 v[73:74], s1, v[20:21], v[2:3], v[20:21]
	v_fma_f64 v[50:51], v[50:51], v[75:76], v[50:51]
	v_div_scale_f64 v[75:76], s2, v[30:31], v[6:7], v[30:31]
	v_fma_f64 v[52:53], v[52:53], v[77:78], v[52:53]
	v_div_scale_f64 v[77:78], s3, v[26:27], v[32:33], v[26:27]
	v_fma_f64 v[54:55], v[54:55], v[79:80], v[54:55]
	v_div_scale_f64 v[79:80], s4, v[14:15], v[24:25], v[14:15]
	v_fma_f64 v[69:70], v[69:70], v[81:82], v[69:70]
	v_mul_f64 v[81:82], v[83:84], v[46:47]
	v_mul_f64 v[85:86], v[71:72], v[48:49]
	v_mul_f64 v[87:88], v[73:74], v[50:51]
	v_mul_f64 v[89:90], v[75:76], v[52:53]
	v_mul_f64 v[91:92], v[77:78], v[54:55]
	v_mul_f64 v[93:94], v[79:80], v[69:70]
	v_fma_f64 v[34:35], -v[34:35], v[81:82], v[83:84]
	v_fma_f64 v[36:37], -v[36:37], v[85:86], v[71:72]
	v_fma_f64 v[38:39], -v[38:39], v[87:88], v[73:74]
	v_fma_f64 v[40:41], -v[40:41], v[89:90], v[75:76]
	v_fma_f64 v[42:43], -v[42:43], v[91:92], v[77:78]
	v_fma_f64 v[44:45], -v[44:45], v[93:94], v[79:80]
	v_div_fmas_f64 v[34:35], v[34:35], v[46:47], v[81:82]
	s_mov_b32 vcc_lo, s0
	v_div_fmas_f64 v[36:37], v[36:37], v[48:49], v[85:86]
	s_mov_b32 vcc_lo, s1
	v_div_fmas_f64 v[38:39], v[38:39], v[50:51], v[87:88]
	s_mov_b32 vcc_lo, s2
	v_div_fmas_f64 v[40:41], v[40:41], v[52:53], v[89:90]
	s_mov_b32 vcc_lo, s3
	v_div_fmas_f64 v[42:43], v[42:43], v[54:55], v[91:92]
	s_mov_b32 vcc_lo, s4
	v_div_fmas_f64 v[44:45], v[44:45], v[69:70], v[93:94]
	v_div_fixup_f64 v[16:17], v[34:35], v[18:19], v[16:17]
	v_div_fixup_f64 v[18:19], v[36:37], v[28:29], v[22:23]
	v_add_f64 v[28:29], v[2:3], -v[12:13]
	v_fma_f64 v[36:37], -v[10:11], s[78:79], v[12:13]
	v_div_fixup_f64 v[20:21], v[38:39], v[2:3], v[20:21]
	v_add_f64 v[12:13], v[0:1], -v[12:13]
	v_fma_f64 v[10:11], -v[10:11], s[78:79], 0
	v_div_fixup_f64 v[22:23], v[40:41], v[6:7], v[30:31]
	v_div_fixup_f64 v[26:27], v[42:43], v[32:33], v[26:27]
	v_add_f64 v[32:33], -v[8:9], 0
	v_add_f64 v[8:9], v[2:3], -v[8:9]
	v_div_fixup_f64 v[14:15], v[44:45], v[24:25], v[14:15]
	v_add_f64 v[24:25], v[4:5], -v[2:3]
	v_add_f64 v[2:3], -v[2:3], 0
	v_add_f64 v[16:17], v[16:17], -v[18:19]
	v_add_f64 v[18:19], v[18:19], -v[20:21]
	v_add_f64 v[30:31], v[20:21], -v[22:23]
	v_add_f64 v[34:35], v[22:23], -v[26:27]
	v_add_f64 v[14:15], v[26:27], -v[14:15]
	v_div_scale_f64 v[26:27], null, v[24:25], v[24:25], v[16:17]
	v_div_scale_f64 v[79:80], vcc_lo, v[16:17], v[24:25], v[16:17]
	v_div_scale_f64 v[38:39], null, v[0:1], v[0:1], v[18:19]
	v_div_scale_f64 v[40:41], null, v[28:29], v[28:29], v[30:31]
	v_div_scale_f64 v[42:43], null, v[32:33], v[32:33], v[34:35]
	v_div_scale_f64 v[44:45], null, v[36:37], v[36:37], v[14:15]
	v_rcp_f64_e32 v[46:47], v[26:27]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_rcp_f64_e32 v[48:49], v[38:39]
	v_rcp_f64_e32 v[50:51], v[40:41]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[52:53], v[42:43]
	v_rcp_f64_e32 v[54:55], v[44:45]
	v_fma_f64 v[69:70], -v[26:27], v[46:47], 1.0
	v_fma_f64 v[71:72], -v[38:39], v[48:49], 1.0
	s_delay_alu instid0(TRANS32_DEP_3)
	v_fma_f64 v[73:74], -v[40:41], v[50:51], 1.0
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[75:76], -v[42:43], v[52:53], 1.0
	v_fma_f64 v[77:78], -v[44:45], v[54:55], 1.0
	v_fma_f64 v[46:47], v[46:47], v[69:70], v[46:47]
	v_fma_f64 v[48:49], v[48:49], v[71:72], v[48:49]
	v_fma_f64 v[50:51], v[50:51], v[73:74], v[50:51]
	v_fma_f64 v[52:53], v[52:53], v[75:76], v[52:53]
	v_fma_f64 v[54:55], v[54:55], v[77:78], v[54:55]
	v_fma_f64 v[69:70], -v[26:27], v[46:47], 1.0
	v_fma_f64 v[71:72], -v[38:39], v[48:49], 1.0
	v_fma_f64 v[73:74], -v[40:41], v[50:51], 1.0
	v_fma_f64 v[75:76], -v[42:43], v[52:53], 1.0
	v_fma_f64 v[77:78], -v[44:45], v[54:55], 1.0
	v_fma_f64 v[46:47], v[46:47], v[69:70], v[46:47]
	v_div_scale_f64 v[69:70], s0, v[18:19], v[0:1], v[18:19]
	v_fma_f64 v[48:49], v[48:49], v[71:72], v[48:49]
	v_div_scale_f64 v[71:72], s1, v[30:31], v[28:29], v[30:31]
	v_fma_f64 v[50:51], v[50:51], v[73:74], v[50:51]
	v_div_scale_f64 v[73:74], s2, v[34:35], v[32:33], v[34:35]
	v_fma_f64 v[52:53], v[52:53], v[75:76], v[52:53]
	v_div_scale_f64 v[75:76], s3, v[14:15], v[36:37], v[14:15]
	v_fma_f64 v[54:55], v[54:55], v[77:78], v[54:55]
	v_mul_f64 v[77:78], v[79:80], v[46:47]
	v_mul_f64 v[81:82], v[69:70], v[48:49]
	v_mul_f64 v[83:84], v[71:72], v[50:51]
	v_mul_f64 v[85:86], v[73:74], v[52:53]
	v_mul_f64 v[87:88], v[75:76], v[54:55]
	v_fma_f64 v[26:27], -v[26:27], v[77:78], v[79:80]
	v_fma_f64 v[38:39], -v[38:39], v[81:82], v[69:70]
	v_fma_f64 v[40:41], -v[40:41], v[83:84], v[71:72]
	v_fma_f64 v[42:43], -v[42:43], v[85:86], v[73:74]
	v_fma_f64 v[44:45], -v[44:45], v[87:88], v[75:76]
	v_div_fmas_f64 v[26:27], v[26:27], v[46:47], v[77:78]
	s_mov_b32 vcc_lo, s0
	v_div_fmas_f64 v[38:39], v[38:39], v[48:49], v[81:82]
	s_mov_b32 vcc_lo, s1
	v_div_fmas_f64 v[40:41], v[40:41], v[50:51], v[83:84]
	s_mov_b32 vcc_lo, s2
	v_div_fmas_f64 v[42:43], v[42:43], v[52:53], v[85:86]
	s_mov_b32 vcc_lo, s3
	v_div_fmas_f64 v[44:45], v[44:45], v[54:55], v[87:88]
	v_div_fixup_f64 v[16:17], v[26:27], v[24:25], v[16:17]
	v_div_fixup_f64 v[18:19], v[38:39], v[0:1], v[18:19]
	v_add_f64 v[0:1], -v[0:1], 0
	v_div_fixup_f64 v[24:25], v[40:41], v[28:29], v[30:31]
	v_div_fixup_f64 v[26:27], v[42:43], v[32:33], v[34:35]
	v_div_fixup_f64 v[14:15], v[44:45], v[36:37], v[14:15]
	v_add_f64 v[16:17], v[16:17], -v[18:19]
	v_mul_f64 v[0:1], v[2:3], v[0:1]
	v_add_f64 v[28:29], v[18:19], -v[24:25]
	v_add_f64 v[30:31], v[24:25], -v[26:27]
	v_add_f64 v[14:15], v[26:27], -v[14:15]
	v_div_scale_f64 v[34:35], null, v[4:5], v[4:5], v[16:17]
	v_div_scale_f64 v[71:72], vcc_lo, v[16:17], v[4:5], v[16:17]
	v_div_scale_f64 v[36:37], null, v[12:13], v[12:13], v[28:29]
	v_div_scale_f64 v[38:39], null, v[8:9], v[8:9], v[30:31]
	v_div_scale_f64 v[40:41], null, v[10:11], v[10:11], v[14:15]
	v_rcp_f64_e32 v[42:43], v[34:35]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rcp_f64_e32 v[44:45], v[36:37]
	v_rcp_f64_e32 v[46:47], v[38:39]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(TRANS32_DEP_3)
	v_rcp_f64_e32 v[48:49], v[40:41]
	v_fma_f64 v[50:51], -v[34:35], v[42:43], 1.0
	v_fma_f64 v[52:53], -v[36:37], v[44:45], 1.0
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[54:55], -v[38:39], v[46:47], 1.0
	v_fma_f64 v[69:70], -v[40:41], v[48:49], 1.0
	v_fma_f64 v[42:43], v[42:43], v[50:51], v[42:43]
	v_fma_f64 v[44:45], v[44:45], v[52:53], v[44:45]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[46:47], v[46:47], v[54:55], v[46:47]
	v_fma_f64 v[48:49], v[48:49], v[69:70], v[48:49]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[50:51], -v[34:35], v[42:43], 1.0
	v_fma_f64 v[52:53], -v[36:37], v[44:45], 1.0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[54:55], -v[38:39], v[46:47], 1.0
	v_fma_f64 v[69:70], -v[40:41], v[48:49], 1.0
	s_delay_alu instid0(VALU_DEP_4)
	v_fma_f64 v[42:43], v[42:43], v[50:51], v[42:43]
	v_div_scale_f64 v[50:51], s0, v[28:29], v[12:13], v[28:29]
	v_fma_f64 v[44:45], v[44:45], v[52:53], v[44:45]
	v_div_scale_f64 v[52:53], s1, v[30:31], v[8:9], v[30:31]
	v_fma_f64 v[46:47], v[46:47], v[54:55], v[46:47]
	v_div_scale_f64 v[54:55], s2, v[14:15], v[10:11], v[14:15]
	v_fma_f64 v[48:49], v[48:49], v[69:70], v[48:49]
	v_mul_f64 v[69:70], v[71:72], v[42:43]
	v_mul_f64 v[73:74], v[50:51], v[44:45]
	v_mul_f64 v[75:76], v[52:53], v[46:47]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mul_f64 v[77:78], v[54:55], v[48:49]
	v_fma_f64 v[34:35], -v[34:35], v[69:70], v[71:72]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[36:37], -v[36:37], v[73:74], v[50:51]
	v_fma_f64 v[38:39], -v[38:39], v[75:76], v[52:53]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[40:41], -v[40:41], v[77:78], v[54:55]
	v_div_fmas_f64 v[34:35], v[34:35], v[42:43], v[69:70]
	s_mov_b32 vcc_lo, s0
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_div_fmas_f64 v[36:37], v[36:37], v[44:45], v[73:74]
	s_mov_b32 vcc_lo, s1
	v_div_fmas_f64 v[38:39], v[38:39], v[46:47], v[75:76]
	s_mov_b32 vcc_lo, s2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_div_fmas_f64 v[40:41], v[40:41], v[48:49], v[77:78]
	v_div_fixup_f64 v[4:5], v[34:35], v[4:5], v[16:17]
	v_mul_f64 v[16:17], v[6:7], v[32:33]
	v_div_fixup_f64 v[12:13], v[36:37], v[12:13], v[28:29]
	v_div_fixup_f64 v[8:9], v[38:39], v[8:9], v[30:31]
	v_div_fixup_f64 v[10:11], v[40:41], v[10:11], v[14:15]
	v_mul_f64 v[14:15], v[2:3], v[6:7]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cmp_lt_f64_e64 vcc_lo, |v[12:13]|, |v[4:5]|
	v_cmp_lt_f64_e64 s0, |v[8:9]|, |v[12:13]|
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_cmp_lt_f64_e64 s1, |v[8:9]|, |v[10:11]|
	v_dual_cndmask_b32 v5, v5, v13 :: v_dual_cndmask_b32 v4, v4, v12
	v_cmp_lt_f64_e64 vcc_lo, |v[24:25]|, |v[18:19]|
	v_cndmask_b32_e64 v13, v13, v9, s0
	v_cndmask_b32_e64 v12, v12, v8, s0
	v_cmp_lt_f64_e64 s0, |v[26:27]|, |v[24:25]|
	v_cndmask_b32_e64 v9, v11, v9, s1
	v_cndmask_b32_e64 v8, v10, v8, s1
	v_mul_f64 v[0:1], v[0:1], v[4:5]
	v_mul_f64 v[4:5], v[14:15], v[12:13]
	v_mul_f64 v[10:11], v[24:25], v[26:27]
	v_mul_f64 v[12:13], v[18:19], v[24:25]
	v_mul_f64 v[8:9], v[16:17], v[8:9]
	v_dual_cndmask_b32 v14, v19, v25 :: v_dual_cndmask_b32 v15, v18, v24
	v_dual_cndmask_b32 v1, v1, v5 :: v_dual_cndmask_b32 v0, v0, v4
	v_cmp_ngt_f64_e64 s1, 0, v[10:11]
	v_cmp_ngt_f64_e64 s2, 0, v[12:13]
	v_cndmask_b32_e64 v9, v5, v9, s0
	v_cndmask_b32_e64 v5, v25, v27, s0
	v_cndmask_b32_e64 v10, v24, v26, s0
	v_cndmask_b32_e64 v8, v4, v8, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v13, 0, v5, s1
	v_cndmask_b32_e64 v11, 0, v14, s2
	v_cndmask_b32_e64 v12, 0, v10, s1
	v_cndmask_b32_e64 v10, 0, v15, s2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[5:6], v[6:7], v[12:13], v[22:23]
	v_fma_f64 v[2:3], v[2:3], v[10:11], v[20:21]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[41:42], v[5:6], v[8:9]
	v_add_f64 v[0:1], v[2:3], v[0:1]
.LBB1_21:                               ; %Flow388
	s_or_b32 exec_lo, exec_lo, s5
	v_add_nc_u32_e32 v2, 1, v60
	v_add_nc_u32_e32 v4, 2, v60
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v8, -1, v60
	v_add_nc_u32_e32 v6, 3, v60
	v_add_nc_u32_e32 v10, -3, v60
	v_cvt_f64_i32_e32 v[2:3], v2
	v_add_nc_u32_e32 v12, -2, v60
	v_cvt_f64_i32_e32 v[4:5], v4
	v_cvt_f64_i32_e32 v[8:9], v8
	v_cvt_f64_i32_e32 v[6:7], v6
	v_cvt_f64_i32_e32 v[10:11], v10
	v_cvt_f64_i32_e32 v[12:13], v12
	v_cmp_lt_f64_e64 s5, |v[67:68]|, |v[65:66]|
	v_max_f64 v[2:3], v[2:3], 0
	v_max_f64 v[4:5], v[4:5], 0
	v_max_f64 v[8:9], v[8:9], 0
	v_max_f64 v[6:7], v[6:7], 0
	v_max_f64 v[10:11], v[10:11], 0
	v_max_f64 v[12:13], v[12:13], 0
	v_cndmask_b32_e64 v1, v42, v1, s5
	v_cndmask_b32_e64 v0, v41, v0, s5
                                        ; implicit-def: $vgpr41_vgpr42
	v_cmp_gt_f64_e32 vcc_lo, v[2:3], v[63:64]
	v_cmp_gt_f64_e64 s0, v[4:5], v[63:64]
	v_cmp_gt_f64_e64 s2, v[8:9], v[63:64]
	v_cmp_gt_f64_e64 s1, v[6:7], v[63:64]
	v_cmp_gt_f64_e64 s3, v[10:11], v[63:64]
	v_cmp_gt_f64_e64 s4, v[12:13], v[63:64]
	v_dual_cndmask_b32 v3, v3, v64 :: v_dual_cndmask_b32 v2, v2, v63
	v_cndmask_b32_e64 v5, v5, v64, s0
	v_cndmask_b32_e64 v9, v9, v64, s2
	v_cndmask_b32_e64 v4, v4, v63, s0
	v_cndmask_b32_e64 v8, v8, v63, s2
	v_cndmask_b32_e64 v7, v7, v64, s1
	v_cndmask_b32_e64 v11, v11, v64, s3
	v_cndmask_b32_e64 v6, v6, v63, s1
	v_cndmask_b32_e64 v10, v10, v63, s3
	v_cndmask_b32_e64 v13, v13, v64, s4
	v_cvt_i32_f64_e32 v14, v[2:3]
	v_cndmask_b32_e64 v12, v12, v63, s4
	v_cvt_i32_f64_e32 v15, v[4:5]
	v_cvt_i32_f64_e32 v17, v[8:9]
	v_cvt_i32_f64_e32 v16, v[6:7]
	v_cvt_i32_f64_e32 v11, v[10:11]
	v_cvt_i32_f64_e32 v12, v[12:13]
	s_load_b128 s[0:3], s[62:63], 0x40
	v_add_co_u32 v2, vcc_lo, s70, v56
	v_add_co_ci_u32_e32 v3, vcc_lo, s71, v57, vcc_lo
	global_store_b64 v[2:3], v[0:1], off
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v4, vcc_lo, s0, v56
	v_add_co_ci_u32_e32 v5, vcc_lo, s1, v57, vcc_lo
	v_add_co_u32 v6, vcc_lo, s2, v56
	v_add_co_ci_u32_e32 v7, vcc_lo, s3, v57, vcc_lo
	v_mad_u64_u32 v[0:1], null, v14, s85, v[61:62]
	v_mad_u64_u32 v[1:2], null, v15, s85, v[61:62]
	v_mad_u64_u32 v[8:9], null, v17, s85, v[61:62]
	v_mad_u64_u32 v[2:3], null, v16, s85, v[61:62]
	v_mad_u64_u32 v[9:10], null, v11, s85, v[61:62]
	v_mad_u64_u32 v[10:11], null, v12, s85, v[61:62]
	v_mad_u64_u32 v[11:12], null, v0, s84, v[62:63]
	v_mad_u64_u32 v[20:21], null, v1, s84, v[62:63]
	s_delay_alu instid0(VALU_DEP_4)
	v_mad_u64_u32 v[15:16], null, v9, s84, v[62:63]
	v_mad_u64_u32 v[0:1], null, v2, s84, v[62:63]
	global_load_b64 v[2:3], v[4:5], off
	global_load_b64 v[18:19], v[6:7], off
	v_mad_u64_u32 v[13:14], null, v8, s84, v[62:63]
	v_mad_u64_u32 v[8:9], null, v10, s84, v[62:63]
	v_ashrrev_i32_e32 v16, 31, v15
	v_ashrrev_i32_e32 v12, 31, v11
	v_ashrrev_i32_e32 v21, 31, v20
	v_ashrrev_i32_e32 v1, 31, v0
	v_ashrrev_i32_e32 v14, 31, v13
	v_lshlrev_b64 v[4:5], 3, v[15:16]
	v_ashrrev_i32_e32 v9, 31, v8
	v_lshlrev_b64 v[10:11], 3, v[11:12]
	v_lshlrev_b64 v[0:1], 3, v[0:1]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_lshlrev_b64 v[6:7], 3, v[8:9]
	v_lshlrev_b64 v[8:9], 3, v[13:14]
	v_add_co_u32 v4, vcc_lo, s74, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s75, v5, vcc_lo
	v_add_co_u32 v6, vcc_lo, s74, v6
	v_add_co_ci_u32_e32 v7, vcc_lo, s75, v7, vcc_lo
	v_lshlrev_b64 v[12:13], 3, v[20:21]
	v_add_co_u32 v8, vcc_lo, s74, v8
	v_add_co_ci_u32_e32 v9, vcc_lo, s75, v9, vcc_lo
	v_add_co_u32 v10, vcc_lo, s74, v10
	v_add_co_ci_u32_e32 v11, vcc_lo, s75, v11, vcc_lo
	v_add_co_u32 v12, vcc_lo, s74, v12
	v_add_co_ci_u32_e32 v13, vcc_lo, s75, v13, vcc_lo
	v_add_co_u32 v0, vcc_lo, s74, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s75, v1, vcc_lo
	s_clause 0x5
	global_load_b64 v[14:15], v[4:5], off
	global_load_b64 v[16:17], v[6:7], off
	global_load_b64 v[60:61], v[8:9], off
	global_load_b64 v[62:63], v[10:11], off
	global_load_b64 v[6:7], v[12:13], off
	global_load_b64 v[8:9], v[0:1], off
                                        ; implicit-def: $vgpr0_vgpr1
	s_waitcnt vmcnt(7)
	v_cmp_ngt_f64_e64 s62, s[66:67], v[2:3]
	s_waitcnt vmcnt(6)
	v_cmp_ngt_f64_e64 s33, s[66:67], v[18:19]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, s62, s33
	s_and_saveexec_b32 s1, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s63, exec_lo, s1
	s_cbranch_execz .LBB1_23
; %bb.22:
	s_waitcnt vmcnt(4)
	v_add_f64 v[0:1], v[16:17], -v[14:15]
	s_waitcnt vmcnt(3)
	v_add_f64 v[2:3], v[60:61], -v[16:17]
	v_add_f64 v[4:5], v[58:59], -v[60:61]
	s_waitcnt vmcnt(2)
	v_add_f64 v[10:11], v[62:63], -v[58:59]
	s_waitcnt vmcnt(1)
	v_add_f64 v[12:13], v[6:7], -v[62:63]
	s_waitcnt vmcnt(0)
	v_add_f64 v[6:7], v[8:9], -v[6:7]
	s_getpc_b64 s[64:65]
	s_add_u32 s64, s64, _Z24weno_onesided_derivativeddddd@rel32@lo+4
	s_addc_u32 s65, s65, _Z24weno_onesided_derivativeddddd@rel32@hi+12
	v_div_scale_f64 v[8:9], null, s[66:67], s[66:67], v[0:1]
	v_div_scale_f64 v[14:15], null, s[66:67], s[66:67], v[2:3]
	v_div_scale_f64 v[16:17], null, s[66:67], s[66:67], v[4:5]
	v_div_scale_f64 v[18:19], null, s[66:67], s[66:67], v[10:11]
	v_div_scale_f64 v[20:21], null, s[66:67], s[66:67], v[12:13]
	v_div_scale_f64 v[22:23], null, s[66:67], s[66:67], v[6:7]
	v_div_scale_f64 v[48:49], vcc_lo, v[0:1], s[66:67], v[0:1]
	v_rcp_f64_e32 v[24:25], v[8:9]
	v_rcp_f64_e32 v[26:27], v[14:15]
	v_rcp_f64_e32 v[28:29], v[16:17]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_rcp_f64_e32 v[30:31], v[18:19]
	v_rcp_f64_e32 v[32:33], v[20:21]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(TRANS32_DEP_3)
	v_rcp_f64_e32 v[34:35], v[22:23]
	v_fma_f64 v[36:37], -v[8:9], v[24:25], 1.0
	v_fma_f64 v[38:39], -v[14:15], v[26:27], 1.0
	v_fma_f64 v[40:41], -v[16:17], v[28:29], 1.0
	v_fma_f64 v[42:43], -v[18:19], v[30:31], 1.0
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[44:45], -v[20:21], v[32:33], 1.0
	v_fma_f64 v[46:47], -v[22:23], v[34:35], 1.0
	v_fma_f64 v[24:25], v[24:25], v[36:37], v[24:25]
	v_fma_f64 v[26:27], v[26:27], v[38:39], v[26:27]
	v_fma_f64 v[28:29], v[28:29], v[40:41], v[28:29]
	v_fma_f64 v[30:31], v[30:31], v[42:43], v[30:31]
	v_fma_f64 v[32:33], v[32:33], v[44:45], v[32:33]
	v_fma_f64 v[34:35], v[34:35], v[46:47], v[34:35]
	v_fma_f64 v[36:37], -v[8:9], v[24:25], 1.0
	v_fma_f64 v[38:39], -v[14:15], v[26:27], 1.0
	v_fma_f64 v[40:41], -v[16:17], v[28:29], 1.0
	v_fma_f64 v[42:43], -v[18:19], v[30:31], 1.0
	v_fma_f64 v[44:45], -v[20:21], v[32:33], 1.0
	v_fma_f64 v[46:47], -v[22:23], v[34:35], 1.0
	v_fma_f64 v[24:25], v[24:25], v[36:37], v[24:25]
	v_div_scale_f64 v[36:37], s0, v[2:3], s[66:67], v[2:3]
	v_fma_f64 v[26:27], v[26:27], v[38:39], v[26:27]
	v_div_scale_f64 v[38:39], s1, v[4:5], s[66:67], v[4:5]
	v_fma_f64 v[28:29], v[28:29], v[40:41], v[28:29]
	v_div_scale_f64 v[40:41], s2, v[10:11], s[66:67], v[10:11]
	v_fma_f64 v[30:31], v[30:31], v[42:43], v[30:31]
	v_div_scale_f64 v[42:43], s3, v[12:13], s[66:67], v[12:13]
	v_fma_f64 v[32:33], v[32:33], v[44:45], v[32:33]
	v_fma_f64 v[34:35], v[34:35], v[46:47], v[34:35]
	v_div_scale_f64 v[44:45], s4, v[6:7], s[66:67], v[6:7]
	v_mul_f64 v[46:47], v[48:49], v[24:25]
	v_mul_f64 v[50:51], v[36:37], v[26:27]
	v_mul_f64 v[52:53], v[38:39], v[28:29]
	v_mul_f64 v[54:55], v[40:41], v[30:31]
	v_mul_f64 v[58:59], v[42:43], v[32:33]
	v_mul_f64 v[64:65], v[44:45], v[34:35]
	v_fma_f64 v[8:9], -v[8:9], v[46:47], v[48:49]
	v_fma_f64 v[14:15], -v[14:15], v[50:51], v[36:37]
	v_fma_f64 v[16:17], -v[16:17], v[52:53], v[38:39]
	v_fma_f64 v[18:19], -v[18:19], v[54:55], v[40:41]
	v_fma_f64 v[20:21], -v[20:21], v[58:59], v[42:43]
	v_fma_f64 v[22:23], -v[22:23], v[64:65], v[44:45]
	v_div_fmas_f64 v[8:9], v[8:9], v[24:25], v[46:47]
	s_mov_b32 vcc_lo, s0
	v_div_fmas_f64 v[14:15], v[14:15], v[26:27], v[50:51]
	s_mov_b32 vcc_lo, s1
	v_div_fmas_f64 v[16:17], v[16:17], v[28:29], v[52:53]
	s_mov_b32 vcc_lo, s2
	v_div_fmas_f64 v[18:19], v[18:19], v[30:31], v[54:55]
	s_mov_b32 vcc_lo, s3
	v_div_fmas_f64 v[20:21], v[20:21], v[32:33], v[58:59]
	s_mov_b32 vcc_lo, s4
	v_div_fmas_f64 v[22:23], v[22:23], v[34:35], v[64:65]
	v_div_fixup_f64 v[0:1], v[8:9], s[66:67], v[0:1]
	v_div_fixup_f64 v[43:44], v[14:15], s[66:67], v[2:3]
	v_div_fixup_f64 v[45:46], v[16:17], s[66:67], v[4:5]
	v_div_fixup_f64 v[50:51], v[18:19], s[66:67], v[10:11]
	v_div_fixup_f64 v[52:53], v[20:21], s[66:67], v[12:13]
	v_div_fixup_f64 v[54:55], v[22:23], s[66:67], v[6:7]
	v_dual_mov_b32 v2, v43 :: v_dual_mov_b32 v3, v44
	v_dual_mov_b32 v4, v45 :: v_dual_mov_b32 v5, v46
	v_dual_mov_b32 v6, v50 :: v_dual_mov_b32 v7, v51
	v_dual_mov_b32 v8, v52 :: v_dual_mov_b32 v9, v53
	s_swappc_b64 s[30:31], s[64:65]
	v_dual_mov_b32 v41, v0 :: v_dual_mov_b32 v42, v1
	v_dual_mov_b32 v0, v54 :: v_dual_mov_b32 v1, v55
	v_dual_mov_b32 v2, v52 :: v_dual_mov_b32 v3, v53
	v_dual_mov_b32 v4, v50 :: v_dual_mov_b32 v5, v51
	v_dual_mov_b32 v6, v45 :: v_dual_mov_b32 v7, v46
	v_dual_mov_b32 v8, v43 :: v_dual_mov_b32 v9, v44
	s_swappc_b64 s[30:31], s[64:65]
                                        ; implicit-def: $vgpr16_vgpr17
                                        ; implicit-def: $vgpr58_vgpr59
                                        ; implicit-def: $vgpr14_vgpr15
                                        ; implicit-def: $vgpr18_vgpr19
                                        ; implicit-def: $vgpr2_vgpr3
                                        ; implicit-def: $vgpr6_vgpr7
                                        ; implicit-def: $vgpr8_vgpr9
.LBB1_23:                               ; %Flow381
	s_and_not1_saveexec_b32 s5, s63
	s_cbranch_execz .LBB1_31
; %bb.24:
	v_add_f64 v[4:5], s[66:67], s[66:67]
	v_mov_b32_e32 v20, 0
	s_waitcnt vmcnt(2)
	v_dual_mov_b32 v21, 0 :: v_dual_mov_b32 v22, v62
	v_dual_mov_b32 v0, s66 :: v_dual_mov_b32 v1, s67
	v_mov_b32_e32 v23, v63
	s_and_saveexec_b32 s0, s62
	s_cbranch_execz .LBB1_26
; %bb.25:
	v_mul_f64 v[10:11], 0x40080000, s[66:67]
	v_dual_mov_b32 v2, s66 :: v_dual_mov_b32 v3, s67
	v_dual_mov_b32 v0, v4 :: v_dual_mov_b32 v1, v5
	v_dual_mov_b32 v20, v62 :: v_dual_mov_b32 v21, v63
	s_waitcnt vmcnt(1)
	v_dual_mov_b32 v23, v7 :: v_dual_mov_b32 v22, v6
	s_waitcnt vmcnt(0)
	v_dual_mov_b32 v6, v8 :: v_dual_mov_b32 v7, v9
	v_dual_mov_b32 v4, v10 :: v_dual_mov_b32 v5, v11
.LBB1_26:
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $vgpr8_vgpr9
                                        ; implicit-def: $sgpr0_sgpr1
                                        ; implicit-def: $sgpr2_sgpr3
	s_and_saveexec_b32 s4, s33
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s4, exec_lo, s4
	s_cbranch_execz .LBB1_28
; %bb.27:
	s_mov_b32 s2, 0
	s_waitcnt vmcnt(0)
	v_mul_f64 v[8:9], s[66:67], -2.0
	s_mov_b32 s3, 0xc0080000
	s_xor_b32 s1, s67, 0x80000000
	s_mov_b32 s0, s66
                                        ; implicit-def: $vgpr18_vgpr19
.LBB1_28:                               ; %Flow
	s_or_saveexec_b32 s4, s4
	v_dual_mov_b32 v11, s3 :: v_dual_mov_b32 v10, s2
	v_dual_mov_b32 v13, s1 :: v_dual_mov_b32 v12, s0
	v_dual_mov_b32 v26, v60 :: v_dual_mov_b32 v27, v61
	v_dual_mov_b32 v25, v17 :: v_dual_mov_b32 v24, v16
	s_xor_b32 exec_lo, exec_lo, s4
	s_cbranch_execz .LBB1_30
; %bb.29:
	v_xor_b32_e32 v19, 0x80000000, v19
	s_xor_b32 s1, s67, 0x80000000
	s_mov_b32 s0, s66
	v_mov_b32_e32 v26, 0
	s_waitcnt vmcnt(0)
	v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v9, s1
	v_dual_mov_b32 v27, 0 :: v_dual_mov_b32 v12, v18
	v_dual_mov_b32 v11, -2.0 :: v_dual_mov_b32 v8, s0
	v_dual_mov_b32 v13, v19 :: v_dual_mov_b32 v24, v60
	v_dual_mov_b32 v25, v61 :: v_dual_mov_b32 v14, v16
	v_mov_b32_e32 v15, v17
.LBB1_30:                               ; %_Z14select_stencilRdS_S_S_S_S_S_S_S_S_S_S_S_S_dddddddddddddddd.exit.i.i321
	s_or_b32 exec_lo, exec_lo, s4
	s_waitcnt vmcnt(1)
	v_add_f64 v[16:17], v[6:7], -v[22:23]
	v_add_f64 v[18:19], v[4:5], -v[0:1]
	v_add_f64 v[22:23], v[22:23], -v[20:21]
	v_add_f64 v[28:29], v[0:1], -v[2:3]
	v_add_f64 v[20:21], v[20:21], -v[58:59]
	v_add_f64 v[30:31], v[58:59], -v[26:27]
	v_add_f64 v[6:7], -v[12:13], 0
	v_add_f64 v[26:27], v[26:27], -v[24:25]
	s_waitcnt vmcnt(0)
	v_add_f64 v[32:33], v[12:13], -v[8:9]
	v_add_f64 v[14:15], v[24:25], -v[14:15]
	v_fma_f64 v[24:25], -v[10:11], s[66:67], v[8:9]
	v_div_scale_f64 v[34:35], null, v[18:19], v[18:19], v[16:17]
	v_div_scale_f64 v[36:37], null, v[28:29], v[28:29], v[22:23]
	v_div_scale_f64 v[38:39], null, v[2:3], v[2:3], v[20:21]
	v_div_scale_f64 v[40:41], null, v[6:7], v[6:7], v[30:31]
	v_div_scale_f64 v[42:43], null, v[32:33], v[32:33], v[26:27]
	v_div_scale_f64 v[44:45], null, v[24:25], v[24:25], v[14:15]
	v_div_scale_f64 v[76:77], vcc_lo, v[16:17], v[18:19], v[16:17]
	v_rcp_f64_e32 v[46:47], v[34:35]
	v_rcp_f64_e32 v[48:49], v[36:37]
	v_rcp_f64_e32 v[50:51], v[38:39]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_rcp_f64_e32 v[52:53], v[40:41]
	v_rcp_f64_e32 v[54:55], v[42:43]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(TRANS32_DEP_3)
	v_rcp_f64_e32 v[58:59], v[44:45]
	v_fma_f64 v[64:65], -v[34:35], v[46:47], 1.0
	v_fma_f64 v[66:67], -v[36:37], v[48:49], 1.0
	v_fma_f64 v[68:69], -v[38:39], v[50:51], 1.0
	v_fma_f64 v[70:71], -v[40:41], v[52:53], 1.0
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[72:73], -v[42:43], v[54:55], 1.0
	v_fma_f64 v[74:75], -v[44:45], v[58:59], 1.0
	v_fma_f64 v[46:47], v[46:47], v[64:65], v[46:47]
	v_fma_f64 v[48:49], v[48:49], v[66:67], v[48:49]
	v_fma_f64 v[50:51], v[50:51], v[68:69], v[50:51]
	v_fma_f64 v[52:53], v[52:53], v[70:71], v[52:53]
	v_fma_f64 v[54:55], v[54:55], v[72:73], v[54:55]
	v_fma_f64 v[58:59], v[58:59], v[74:75], v[58:59]
	v_fma_f64 v[64:65], -v[34:35], v[46:47], 1.0
	v_fma_f64 v[66:67], -v[36:37], v[48:49], 1.0
	v_fma_f64 v[68:69], -v[38:39], v[50:51], 1.0
	v_fma_f64 v[70:71], -v[40:41], v[52:53], 1.0
	v_fma_f64 v[72:73], -v[42:43], v[54:55], 1.0
	v_fma_f64 v[74:75], -v[44:45], v[58:59], 1.0
	v_fma_f64 v[46:47], v[46:47], v[64:65], v[46:47]
	v_div_scale_f64 v[64:65], s0, v[22:23], v[28:29], v[22:23]
	v_fma_f64 v[48:49], v[48:49], v[66:67], v[48:49]
	v_div_scale_f64 v[66:67], s1, v[20:21], v[2:3], v[20:21]
	v_fma_f64 v[50:51], v[50:51], v[68:69], v[50:51]
	v_div_scale_f64 v[68:69], s2, v[30:31], v[6:7], v[30:31]
	v_fma_f64 v[52:53], v[52:53], v[70:71], v[52:53]
	v_div_scale_f64 v[70:71], s3, v[26:27], v[32:33], v[26:27]
	v_fma_f64 v[54:55], v[54:55], v[72:73], v[54:55]
	v_div_scale_f64 v[72:73], s4, v[14:15], v[24:25], v[14:15]
	v_fma_f64 v[58:59], v[58:59], v[74:75], v[58:59]
	v_mul_f64 v[74:75], v[76:77], v[46:47]
	v_mul_f64 v[78:79], v[64:65], v[48:49]
	v_mul_f64 v[80:81], v[66:67], v[50:51]
	v_mul_f64 v[82:83], v[68:69], v[52:53]
	v_mul_f64 v[84:85], v[70:71], v[54:55]
	v_mul_f64 v[86:87], v[72:73], v[58:59]
	v_fma_f64 v[34:35], -v[34:35], v[74:75], v[76:77]
	v_fma_f64 v[36:37], -v[36:37], v[78:79], v[64:65]
	v_fma_f64 v[38:39], -v[38:39], v[80:81], v[66:67]
	v_fma_f64 v[40:41], -v[40:41], v[82:83], v[68:69]
	v_fma_f64 v[42:43], -v[42:43], v[84:85], v[70:71]
	v_fma_f64 v[44:45], -v[44:45], v[86:87], v[72:73]
	v_div_fmas_f64 v[34:35], v[34:35], v[46:47], v[74:75]
	s_mov_b32 vcc_lo, s0
	v_div_fmas_f64 v[36:37], v[36:37], v[48:49], v[78:79]
	s_mov_b32 vcc_lo, s1
	v_div_fmas_f64 v[38:39], v[38:39], v[50:51], v[80:81]
	s_mov_b32 vcc_lo, s2
	v_div_fmas_f64 v[40:41], v[40:41], v[52:53], v[82:83]
	s_mov_b32 vcc_lo, s3
	v_div_fmas_f64 v[42:43], v[42:43], v[54:55], v[84:85]
	s_mov_b32 vcc_lo, s4
	v_div_fmas_f64 v[44:45], v[44:45], v[58:59], v[86:87]
	v_div_fixup_f64 v[16:17], v[34:35], v[18:19], v[16:17]
	v_div_fixup_f64 v[18:19], v[36:37], v[28:29], v[22:23]
	v_add_f64 v[28:29], v[2:3], -v[12:13]
	v_fma_f64 v[36:37], -v[10:11], s[66:67], v[12:13]
	v_div_fixup_f64 v[20:21], v[38:39], v[2:3], v[20:21]
	v_add_f64 v[12:13], v[0:1], -v[12:13]
	v_fma_f64 v[10:11], -v[10:11], s[66:67], 0
	v_div_fixup_f64 v[22:23], v[40:41], v[6:7], v[30:31]
	v_div_fixup_f64 v[26:27], v[42:43], v[32:33], v[26:27]
	v_add_f64 v[32:33], -v[8:9], 0
	v_add_f64 v[8:9], v[2:3], -v[8:9]
	v_div_fixup_f64 v[14:15], v[44:45], v[24:25], v[14:15]
	v_add_f64 v[24:25], v[4:5], -v[2:3]
	v_add_f64 v[2:3], -v[2:3], 0
	v_add_f64 v[16:17], v[16:17], -v[18:19]
	v_add_f64 v[18:19], v[18:19], -v[20:21]
	v_add_f64 v[30:31], v[20:21], -v[22:23]
	v_add_f64 v[34:35], v[22:23], -v[26:27]
	v_add_f64 v[14:15], v[26:27], -v[14:15]
	v_div_scale_f64 v[26:27], null, v[24:25], v[24:25], v[16:17]
	v_div_scale_f64 v[72:73], vcc_lo, v[16:17], v[24:25], v[16:17]
	v_div_scale_f64 v[38:39], null, v[0:1], v[0:1], v[18:19]
	v_div_scale_f64 v[40:41], null, v[28:29], v[28:29], v[30:31]
	v_div_scale_f64 v[42:43], null, v[32:33], v[32:33], v[34:35]
	v_div_scale_f64 v[44:45], null, v[36:37], v[36:37], v[14:15]
	v_rcp_f64_e32 v[46:47], v[26:27]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_rcp_f64_e32 v[48:49], v[38:39]
	v_rcp_f64_e32 v[50:51], v[40:41]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[52:53], v[42:43]
	v_rcp_f64_e32 v[54:55], v[44:45]
	v_fma_f64 v[58:59], -v[26:27], v[46:47], 1.0
	v_fma_f64 v[64:65], -v[38:39], v[48:49], 1.0
	s_delay_alu instid0(TRANS32_DEP_3)
	v_fma_f64 v[66:67], -v[40:41], v[50:51], 1.0
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[68:69], -v[42:43], v[52:53], 1.0
	v_fma_f64 v[70:71], -v[44:45], v[54:55], 1.0
	v_fma_f64 v[46:47], v[46:47], v[58:59], v[46:47]
	v_fma_f64 v[48:49], v[48:49], v[64:65], v[48:49]
	v_fma_f64 v[50:51], v[50:51], v[66:67], v[50:51]
	v_fma_f64 v[52:53], v[52:53], v[68:69], v[52:53]
	v_fma_f64 v[54:55], v[54:55], v[70:71], v[54:55]
	v_fma_f64 v[58:59], -v[26:27], v[46:47], 1.0
	v_fma_f64 v[64:65], -v[38:39], v[48:49], 1.0
	v_fma_f64 v[66:67], -v[40:41], v[50:51], 1.0
	v_fma_f64 v[68:69], -v[42:43], v[52:53], 1.0
	v_fma_f64 v[70:71], -v[44:45], v[54:55], 1.0
	v_fma_f64 v[46:47], v[46:47], v[58:59], v[46:47]
	v_div_scale_f64 v[58:59], s0, v[18:19], v[0:1], v[18:19]
	v_fma_f64 v[48:49], v[48:49], v[64:65], v[48:49]
	v_div_scale_f64 v[64:65], s1, v[30:31], v[28:29], v[30:31]
	v_fma_f64 v[50:51], v[50:51], v[66:67], v[50:51]
	v_div_scale_f64 v[66:67], s2, v[34:35], v[32:33], v[34:35]
	v_fma_f64 v[52:53], v[52:53], v[68:69], v[52:53]
	v_div_scale_f64 v[68:69], s3, v[14:15], v[36:37], v[14:15]
	v_fma_f64 v[54:55], v[54:55], v[70:71], v[54:55]
	v_mul_f64 v[70:71], v[72:73], v[46:47]
	v_mul_f64 v[74:75], v[58:59], v[48:49]
	v_mul_f64 v[76:77], v[64:65], v[50:51]
	v_mul_f64 v[78:79], v[66:67], v[52:53]
	v_mul_f64 v[80:81], v[68:69], v[54:55]
	v_fma_f64 v[26:27], -v[26:27], v[70:71], v[72:73]
	v_fma_f64 v[38:39], -v[38:39], v[74:75], v[58:59]
	v_fma_f64 v[40:41], -v[40:41], v[76:77], v[64:65]
	v_fma_f64 v[42:43], -v[42:43], v[78:79], v[66:67]
	v_fma_f64 v[44:45], -v[44:45], v[80:81], v[68:69]
	v_div_fmas_f64 v[26:27], v[26:27], v[46:47], v[70:71]
	s_mov_b32 vcc_lo, s0
	v_div_fmas_f64 v[38:39], v[38:39], v[48:49], v[74:75]
	s_mov_b32 vcc_lo, s1
	v_div_fmas_f64 v[40:41], v[40:41], v[50:51], v[76:77]
	s_mov_b32 vcc_lo, s2
	v_div_fmas_f64 v[42:43], v[42:43], v[52:53], v[78:79]
	s_mov_b32 vcc_lo, s3
	v_div_fmas_f64 v[44:45], v[44:45], v[54:55], v[80:81]
	v_div_fixup_f64 v[16:17], v[26:27], v[24:25], v[16:17]
	v_div_fixup_f64 v[18:19], v[38:39], v[0:1], v[18:19]
	v_add_f64 v[0:1], -v[0:1], 0
	v_div_fixup_f64 v[24:25], v[40:41], v[28:29], v[30:31]
	v_div_fixup_f64 v[26:27], v[42:43], v[32:33], v[34:35]
	v_div_fixup_f64 v[14:15], v[44:45], v[36:37], v[14:15]
	v_add_f64 v[16:17], v[16:17], -v[18:19]
	v_mul_f64 v[0:1], v[2:3], v[0:1]
	v_add_f64 v[28:29], v[18:19], -v[24:25]
	v_add_f64 v[30:31], v[24:25], -v[26:27]
	v_add_f64 v[14:15], v[26:27], -v[14:15]
	v_div_scale_f64 v[34:35], null, v[4:5], v[4:5], v[16:17]
	v_div_scale_f64 v[64:65], vcc_lo, v[16:17], v[4:5], v[16:17]
	v_div_scale_f64 v[36:37], null, v[12:13], v[12:13], v[28:29]
	v_div_scale_f64 v[38:39], null, v[8:9], v[8:9], v[30:31]
	v_div_scale_f64 v[40:41], null, v[10:11], v[10:11], v[14:15]
	v_rcp_f64_e32 v[42:43], v[34:35]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rcp_f64_e32 v[44:45], v[36:37]
	v_rcp_f64_e32 v[46:47], v[38:39]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(TRANS32_DEP_3)
	v_rcp_f64_e32 v[48:49], v[40:41]
	v_fma_f64 v[50:51], -v[34:35], v[42:43], 1.0
	v_fma_f64 v[52:53], -v[36:37], v[44:45], 1.0
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[54:55], -v[38:39], v[46:47], 1.0
	v_fma_f64 v[58:59], -v[40:41], v[48:49], 1.0
	v_fma_f64 v[42:43], v[42:43], v[50:51], v[42:43]
	v_fma_f64 v[44:45], v[44:45], v[52:53], v[44:45]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[46:47], v[46:47], v[54:55], v[46:47]
	v_fma_f64 v[48:49], v[48:49], v[58:59], v[48:49]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[50:51], -v[34:35], v[42:43], 1.0
	v_fma_f64 v[52:53], -v[36:37], v[44:45], 1.0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[54:55], -v[38:39], v[46:47], 1.0
	v_fma_f64 v[58:59], -v[40:41], v[48:49], 1.0
	s_delay_alu instid0(VALU_DEP_4)
	v_fma_f64 v[42:43], v[42:43], v[50:51], v[42:43]
	v_div_scale_f64 v[50:51], s0, v[28:29], v[12:13], v[28:29]
	v_fma_f64 v[44:45], v[44:45], v[52:53], v[44:45]
	v_div_scale_f64 v[52:53], s1, v[30:31], v[8:9], v[30:31]
	v_fma_f64 v[46:47], v[46:47], v[54:55], v[46:47]
	v_div_scale_f64 v[54:55], s2, v[14:15], v[10:11], v[14:15]
	v_fma_f64 v[48:49], v[48:49], v[58:59], v[48:49]
	v_mul_f64 v[58:59], v[64:65], v[42:43]
	v_mul_f64 v[66:67], v[50:51], v[44:45]
	v_mul_f64 v[68:69], v[52:53], v[46:47]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mul_f64 v[70:71], v[54:55], v[48:49]
	v_fma_f64 v[34:35], -v[34:35], v[58:59], v[64:65]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[36:37], -v[36:37], v[66:67], v[50:51]
	v_fma_f64 v[38:39], -v[38:39], v[68:69], v[52:53]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[40:41], -v[40:41], v[70:71], v[54:55]
	v_div_fmas_f64 v[34:35], v[34:35], v[42:43], v[58:59]
	s_mov_b32 vcc_lo, s0
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_div_fmas_f64 v[36:37], v[36:37], v[44:45], v[66:67]
	s_mov_b32 vcc_lo, s1
	v_div_fmas_f64 v[38:39], v[38:39], v[46:47], v[68:69]
	s_mov_b32 vcc_lo, s2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_div_fmas_f64 v[40:41], v[40:41], v[48:49], v[70:71]
	v_div_fixup_f64 v[4:5], v[34:35], v[4:5], v[16:17]
	v_mul_f64 v[16:17], v[6:7], v[32:33]
	v_div_fixup_f64 v[12:13], v[36:37], v[12:13], v[28:29]
	v_div_fixup_f64 v[8:9], v[38:39], v[8:9], v[30:31]
	v_div_fixup_f64 v[10:11], v[40:41], v[10:11], v[14:15]
	v_mul_f64 v[14:15], v[2:3], v[6:7]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cmp_lt_f64_e64 vcc_lo, |v[12:13]|, |v[4:5]|
	v_cmp_lt_f64_e64 s0, |v[8:9]|, |v[12:13]|
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_cmp_lt_f64_e64 s1, |v[8:9]|, |v[10:11]|
	v_dual_cndmask_b32 v5, v5, v13 :: v_dual_cndmask_b32 v4, v4, v12
	v_cmp_lt_f64_e64 vcc_lo, |v[24:25]|, |v[18:19]|
	v_cndmask_b32_e64 v13, v13, v9, s0
	v_cndmask_b32_e64 v12, v12, v8, s0
	v_cmp_lt_f64_e64 s0, |v[26:27]|, |v[24:25]|
	v_cndmask_b32_e64 v9, v11, v9, s1
	v_cndmask_b32_e64 v8, v10, v8, s1
	v_mul_f64 v[0:1], v[0:1], v[4:5]
	v_mul_f64 v[4:5], v[14:15], v[12:13]
	v_mul_f64 v[10:11], v[24:25], v[26:27]
	v_mul_f64 v[12:13], v[18:19], v[24:25]
	v_mul_f64 v[8:9], v[16:17], v[8:9]
	v_dual_cndmask_b32 v14, v19, v25 :: v_dual_cndmask_b32 v15, v18, v24
	v_dual_cndmask_b32 v1, v1, v5 :: v_dual_cndmask_b32 v0, v0, v4
	v_cmp_ngt_f64_e64 s1, 0, v[10:11]
	v_cmp_ngt_f64_e64 s2, 0, v[12:13]
	v_cndmask_b32_e64 v9, v5, v9, s0
	v_cndmask_b32_e64 v5, v25, v27, s0
	v_cndmask_b32_e64 v10, v24, v26, s0
	v_cndmask_b32_e64 v8, v4, v8, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v13, 0, v5, s1
	v_cndmask_b32_e64 v11, 0, v14, s2
	v_cndmask_b32_e64 v12, 0, v10, s1
	v_cndmask_b32_e64 v10, 0, v15, s2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[5:6], v[6:7], v[12:13], v[22:23]
	v_fma_f64 v[2:3], v[2:3], v[10:11], v[20:21]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[41:42], v[5:6], v[8:9]
	v_add_f64 v[0:1], v[2:3], v[0:1]
.LBB1_31:                               ; %Flow382
	s_or_b32 exec_lo, exec_lo, s5
	s_waitcnt vmcnt(2)
	v_cmp_lt_f64_e64 vcc_lo, |v[62:63]|, |v[60:61]|
	s_delay_alu instid0(VALU_DEP_2)
	v_dual_cndmask_b32 v1, v42, v1 :: v_dual_cndmask_b32 v0, v41, v0
	v_add_co_u32 v2, vcc_lo, s72, v56
	v_add_co_ci_u32_e32 v3, vcc_lo, s73, v57, vcc_lo
	global_store_b64 v[2:3], v[0:1], off
.LBB1_32:
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z13upwind_normalPdS_S_PKdS1_S1_S1_S1_S1_S1_iiidddi
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 8
		.amdhsa_kernarg_size 384
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 1
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 100
		.amdhsa_next_free_sgpr 88
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z13upwind_normalPdS_S_PKdS1_S1_S1_S1_S1_S1_iiidddi, .Lfunc_end1-_Z13upwind_normalPdS_S_PKdS1_S1_S1_S1_S1_S1_iiidddi
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 11156
; NumSgprs: 90
; NumVgprs: 100
; ScratchSize: 8
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 11
; VGPRBlocks: 12
; NumSGPRsForWavesPerEU: 90
; NumVGPRsForWavesPerEU: 100
; Occupancy: 12
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 1
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.text
	.p2align	2                               ; -- Begin function _Z12cubic_interpRdS_dddddddd
	.type	_Z12cubic_interpRdS_dddddddd,@function
_Z12cubic_interpRdS_dddddddd:           ; @_Z12cubic_interpRdS_dddddddd
; %bb.0:
	s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	v_frexp_mant_f64_e64 v[20:21], |v[8:9]|
	v_frexp_exp_i32_f64_e32 v32, v[8:9]
	v_cmp_class_f64_e64 s24, v[8:9], 0x204
	s_mov_b32 s0, 0
	s_mov_b32 s25, exec_lo
	s_mov_b32 s1, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	v_dual_mov_b32 v23, s1 :: v_dual_mov_b32 v22, s0
	flat_store_b64 v[0:1], v[22:23]
	flat_store_b64 v[2:3], v[22:23]
	v_cmpx_neq_f64_e32 v[4:5], v[8:9]
	s_cbranch_execz .LBB2_2
; %bb.1:
	v_add_f64 v[26:27], v[16:17], -v[12:13]
	v_add_f64 v[24:25], v[14:15], -v[12:13]
	v_add_f64 v[22:23], v[18:19], -v[12:13]
	s_mov_b32 s5, 0x3fd55555
	s_mov_b32 s4, 0x55555555
	v_add_f64 v[4:5], v[4:5], v[8:9]
	s_mov_b32 s2, 0x968915a9
	s_mov_b32 s6, 0x4222de17
	s_mov_b32 s3, 0x3fba6564
	s_mov_b32 s7, 0x3fbdee67
	s_mov_b32 s8, 0x3abe935a
	s_mov_b32 s9, 0x3fbe25e4
	s_mov_b32 s10, 0x47e6c9c2
	s_mov_b32 s11, 0x3fc110ef
	s_mov_b32 s12, 0xcfa74449
	s_mov_b32 s13, 0x3fc3b13b
	s_mov_b32 s14, 0x71bf3c30
	s_mov_b32 s15, 0x3fc745d1
	s_mov_b32 s16, 0x1c7792ce
	s_mov_b32 s17, 0x3fcc71c7
	s_mov_b32 s18, 0x924920da
	s_mov_b32 s19, 0x3fd24924
	s_mov_b32 s20, 0x9999999c
	s_mov_b32 s21, 0x3fd99999
	s_mov_b32 s26, 0x14761f6e
	s_mov_b32 s27, 0x3f2a01a0
	s_mov_b32 s22, 0x1852b7b0
	s_mov_b32 s23, 0x3f56c16c
	s_mov_b32 s28, 11
	s_mov_b32 s29, 0x3fe00000
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[28:29], 0xbff80000, v[26:27]
	v_frexp_mant_f64_e64 v[52:53], |v[4:5]|
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[18:19], 0x40080000, v[24:25], v[28:29]
	v_fma_f64 v[18:19], v[22:23], s[4:5], v[18:19]
	s_mov_b32 s5, 0x3fe55555
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cmp_gt_f64_e32 vcc_lo, s[4:5], v[20:21]
	v_cmp_gt_f64_e64 s0, s[4:5], v[52:53]
	v_cndmask_b32_e64 v28, 0, 1, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v39, 0, 1, s0
	v_ldexp_f64 v[33:34], v[20:21], v28
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[35:36], v[33:34], 1.0
	v_add_f64 v[37:38], v[33:34], -1.0
	v_rcp_f64_e32 v[28:29], v[35:36]
	v_add_f64 v[48:49], v[35:36], -1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_3)
	v_add_f64 v[33:34], v[33:34], -v[48:49]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[30:31], -v[35:36], v[28:29], 1.0
	v_ldexp_f64 v[48:49], v[52:53], v39
	v_subrev_co_ci_u32_e32 v39, vcc_lo, 0, v32, vcc_lo
	v_fma_f64 v[28:29], v[30:31], v[28:29], v[28:29]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[30:31], -v[35:36], v[28:29], 1.0
	v_fma_f64 v[30:31], v[30:31], v[28:29], v[28:29]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[28:29], v[37:38], v[30:31]
	v_mul_f64 v[50:51], v[35:36], v[28:29]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[35:36], v[28:29], v[35:36], -v[50:51]
	v_fma_f64 v[33:34], v[28:29], v[33:34], v[35:36]
	v_add_f64 v[35:36], v[48:49], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[52:53], v[50:51], v[33:34]
	v_rcp_f64_e32 v[54:55], v[35:36]
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[64:65], v[37:38], -v[52:53]
	v_add_f64 v[50:51], v[52:53], -v[50:51]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[66:67], -v[35:36], v[54:55], 1.0
	v_add_f64 v[37:38], v[37:38], -v[64:65]
	v_add_f64 v[33:34], v[50:51], -v[33:34]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[54:55], v[66:67], v[54:55], v[54:55]
	v_add_f64 v[37:38], v[37:38], -v[52:53]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[50:51], -v[35:36], v[54:55], 1.0
	v_add_f64 v[33:34], v[33:34], v[37:38]
	v_add_f64 v[37:38], v[48:49], -1.0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[50:51], v[50:51], v[54:55], v[54:55]
	v_add_f64 v[33:34], v[64:65], v[33:34]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[52:53], v[37:38], v[50:51]
	v_mul_f64 v[30:31], v[30:31], v[33:34]
	v_add_f64 v[33:34], v[35:36], -1.0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f64 v[54:55], v[35:36], v[52:53]
	v_add_f64 v[64:65], v[28:29], v[30:31]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[33:34], v[48:49], -v[33:34]
	v_fma_f64 v[35:36], v[52:53], v[35:36], -v[54:55]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[28:29], v[64:65], -v[28:29]
	v_fma_f64 v[33:34], v[52:53], v[33:34], v[35:36]
	v_mul_f64 v[35:36], v[64:65], v[64:65]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[28:29], v[30:31], -v[28:29]
	v_add_f64 v[30:31], v[54:55], v[33:34]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[48:49], v[64:65], v[64:65], -v[35:36]
	v_add_f64 v[66:67], v[28:29], v[28:29]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[68:69], v[37:38], -v[30:31]
	v_add_f64 v[54:55], v[30:31], -v[54:55]
	v_fma_f64 v[48:49], v[64:65], v[66:67], v[48:49]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[37:38], v[37:38], -v[68:69]
	v_add_f64 v[33:34], v[54:55], -v[33:34]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[66:67], v[35:36], v[48:49]
	v_add_f64 v[30:31], v[37:38], -v[30:31]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_fma_f64 v[37:38], v[66:67], s[6:7], s[2:3]
	v_add_f64 v[35:36], v[66:67], -v[35:36]
	v_mul_f64 v[82:83], v[64:65], v[66:67]
	v_add_f64 v[30:31], v[33:34], v[30:31]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[33:34], v[66:67], v[37:38], s[8:9]
	v_add_f64 v[35:36], v[48:49], -v[35:36]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[30:31], v[68:69], v[30:31]
	v_fma_f64 v[33:34], v[66:67], v[33:34], s[10:11]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[30:31], v[50:51], v[30:31]
	v_fma_f64 v[33:34], v[66:67], v[33:34], s[12:13]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[37:38], v[52:53], v[30:31]
	v_fma_f64 v[33:34], v[66:67], v[33:34], s[14:15]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[50:51], v[37:38], -v[52:53]
	v_mul_f64 v[52:53], v[37:38], v[37:38]
	v_fma_f64 v[33:34], v[66:67], v[33:34], s[16:17]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[30:31], v[30:31], -v[50:51]
	v_fma_f64 v[50:51], v[37:38], v[37:38], -v[52:53]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[33:34], v[66:67], v[33:34], s[18:19]
	v_add_f64 v[54:55], v[30:31], v[30:31]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[33:34], v[66:67], v[33:34], s[20:21]
	v_fma_f64 v[50:51], v[37:38], v[54:55], v[50:51]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[54:55], v[66:67], v[33:34]
	v_add_f64 v[68:69], v[52:53], v[50:51]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[48:49], v[66:67], v[33:34], -v[54:55]
	v_fma_f64 v[70:71], v[68:69], s[6:7], s[2:3]
	s_mov_b32 s3, 0xbfe55555
	s_mov_b32 s2, s4
	s_mov_b32 s6, 0xd5df274d
	s_mov_b32 s7, 0x3c8543b0
	v_add_f64 v[52:53], v[68:69], -v[52:53]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[33:34], v[35:36], v[33:34], v[48:49]
	v_fma_f64 v[48:49], v[68:69], v[70:71], s[8:9]
	s_mov_b32 s8, 0x652b82fe
	s_mov_b32 s9, 0x3ff71547
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[50:51], v[50:51], -v[52:53]
	v_add_f64 v[70:71], v[54:55], v[33:34]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_fma_f64 v[48:49], v[68:69], v[48:49], s[10:11]
	s_mov_b32 s10, 0xfefa39ef
	s_mov_b32 s11, 0x3fe62e42
	v_add_f64 v[80:81], v[70:71], s[4:5]
	v_add_f64 v[54:55], v[70:71], -v[54:55]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_fma_f64 v[48:49], v[68:69], v[48:49], s[12:13]
	s_mov_b32 s12, 0xfca7ab0c
	s_mov_b32 s13, 0x3e928af3
	v_add_f64 v[84:85], v[80:81], s[2:3]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f64 v[33:34], v[33:34], -v[54:55]
	v_fma_f64 v[54:55], v[66:67], v[64:65], -v[82:83]
	v_fma_f64 v[48:49], v[68:69], v[48:49], s[14:15]
	s_mov_b32 s14, 0x3b39803f
	s_mov_b32 s15, 0x3c7abc9e
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[70:71], v[70:71], -v[84:85]
	v_add_f64 v[33:34], v[33:34], s[6:7]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[54:55], v[66:67], v[28:29], v[54:55]
	v_fma_f64 v[48:49], v[68:69], v[48:49], s[16:17]
	v_ldexp_f64 v[28:29], v[28:29], 1
	s_mov_b32 s16, 0x6a5dcb37
	s_mov_b32 s17, 0x3e5ade15
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[33:34], v[33:34], v[70:71]
	v_fma_f64 v[35:36], v[35:36], v[64:65], v[54:55]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_fma_f64 v[48:49], v[68:69], v[48:49], s[18:19]
	s_mov_b32 s18, 0x11122322
	s_mov_b32 s19, 0x3f811111
	v_add_f64 v[54:55], v[80:81], v[33:34]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[66:67], v[82:83], v[35:36]
	v_fma_f64 v[48:49], v[68:69], v[48:49], s[20:21]
	s_mov_b32 s20, 0x555502a1
	s_mov_b32 s21, 0x3fa55555
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[70:71], v[80:81], -v[54:55]
	v_mul_f64 v[80:81], v[66:67], v[54:55]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_mul_f64 v[84:85], v[68:69], v[48:49]
	v_add_f64 v[82:83], v[66:67], -v[82:83]
	v_add_f64 v[33:34], v[33:34], v[70:71]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[70:71], v[66:67], v[54:55], -v[80:81]
	v_fma_f64 v[52:53], v[68:69], v[48:49], -v[84:85]
	s_delay_alu instid0(VALU_DEP_4)
	v_add_f64 v[35:36], v[35:36], -v[82:83]
	v_cvt_f64_i32_e32 v[82:83], v39
	v_frexp_exp_i32_f64_e32 v39, v[4:5]
	v_fma_f64 v[33:34], v[66:67], v[33:34], v[70:71]
	v_fma_f64 v[48:49], v[50:51], v[48:49], v[52:53]
	v_ldexp_f64 v[52:53], v[64:65], 1
	v_mul_f64 v[64:65], v[37:38], v[68:69]
	v_subrev_co_ci_u32_e64 v39, vcc_lo, 0, v39, s0
	v_fma_f64 v[33:34], v[35:36], v[54:55], v[33:34]
	v_add_f64 v[35:36], v[84:85], v[48:49]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[86:87], v[68:69], v[37:38], -v[64:65]
	v_add_f64 v[54:55], v[80:81], v[33:34]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f64 v[66:67], v[35:36], s[4:5]
	v_add_f64 v[70:71], v[35:36], -v[84:85]
	v_fma_f64 v[68:69], v[68:69], v[30:31], v[86:87]
	v_ldexp_f64 v[30:31], v[30:31], 1
	v_add_f64 v[84:85], v[52:53], v[54:55]
	v_add_f64 v[80:81], v[54:55], -v[80:81]
	v_add_f64 v[96:97], v[66:67], s[2:3]
	v_add_f64 v[48:49], v[48:49], -v[70:71]
	v_mul_f64 v[70:71], v[82:83], s[10:11]
	s_mov_b32 s2, 0x623fde64
	s_mov_b32 s3, 0x3ec71dee
	v_add_f64 v[52:53], v[84:85], -v[52:53]
	v_add_f64 v[33:34], v[33:34], -v[80:81]
	v_add_f64 v[35:36], v[35:36], -v[96:97]
	v_add_f64 v[48:49], v[48:49], s[6:7]
	v_fma_f64 v[80:81], v[82:83], s[10:11], -v[70:71]
	s_mov_b32 s6, 0x7c89e6b0
	s_mov_b32 s7, 0x3efa0199
	v_add_f64 v[52:53], v[54:55], -v[52:53]
	v_add_f64 v[28:29], v[28:29], v[33:34]
	v_fma_f64 v[33:34], v[50:51], v[37:38], v[68:69]
	v_add_f64 v[35:36], v[48:49], v[35:36]
	v_fma_f64 v[48:49], v[82:83], s[14:15], v[80:81]
	v_ldexp_f64 v[37:38], v[37:38], 1
	v_add_f64 v[28:29], v[28:29], v[52:53]
	v_add_f64 v[52:53], v[64:65], v[33:34]
	v_add_f64 v[50:51], v[66:67], v[35:36]
	v_add_f64 v[54:55], v[70:71], v[48:49]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[68:69], v[84:85], v[28:29]
	v_add_f64 v[64:65], v[52:53], -v[64:65]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f64 v[66:67], v[66:67], -v[50:51]
	v_mul_f64 v[80:81], v[52:53], v[50:51]
	v_add_f64 v[82:83], v[54:55], v[68:69]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[33:34], v[33:34], -v[64:65]
	v_add_f64 v[35:36], v[35:36], v[66:67]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_fma_f64 v[66:67], v[52:53], v[50:51], -v[80:81]
	v_add_f64 v[64:65], v[68:69], -v[84:85]
	v_add_f64 v[86:87], v[82:83], -v[54:55]
	v_fma_f64 v[35:36], v[52:53], v[35:36], v[66:67]
	v_add_f64 v[52:53], v[54:55], -v[70:71]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[28:29], v[28:29], -v[64:65]
	v_add_f64 v[66:67], v[82:83], -v[86:87]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[33:34], v[33:34], v[50:51], v[35:36]
	v_add_f64 v[35:36], v[48:49], -v[52:53]
	v_add_f64 v[48:49], v[68:69], -v[86:87]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[50:51], v[54:55], -v[66:67]
	v_add_f64 v[52:53], v[80:81], v[33:34]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[54:55], v[35:36], v[28:29]
	v_add_f64 v[48:49], v[48:49], v[50:51]
	v_cvt_f64_i32_e32 v[50:51], v39
	s_delay_alu instid0(VALU_DEP_4)
	v_add_f64 v[64:65], v[37:38], v[52:53]
	v_add_f64 v[66:67], v[52:53], -v[80:81]
	v_add_f64 v[68:69], v[54:55], -v[35:36]
	v_add_f64 v[48:49], v[54:55], v[48:49]
	v_mul_f64 v[70:71], v[50:51], s[10:11]
	v_add_f64 v[37:38], v[64:65], -v[37:38]
	v_add_f64 v[33:34], v[33:34], -v[66:67]
	v_add_f64 v[54:55], v[54:55], -v[68:69]
	v_add_f64 v[28:29], v[28:29], -v[68:69]
	v_add_f64 v[66:67], v[82:83], v[48:49]
	v_fma_f64 v[80:81], v[50:51], s[10:11], -v[70:71]
	s_mov_b32 s11, 0xbfe62e42
	v_add_f64 v[37:38], v[52:53], -v[37:38]
	v_add_f64 v[30:31], v[30:31], v[33:34]
	v_add_f64 v[33:34], v[35:36], -v[54:55]
	v_add_f64 v[35:36], v[66:67], -v[82:83]
	v_fma_f64 v[50:51], v[50:51], s[14:15], v[80:81]
	s_mov_b32 s15, 0xbc7abc9e
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[30:31], v[30:31], v[37:38]
	v_add_f64 v[28:29], v[28:29], v[33:34]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[33:34], v[48:49], -v[35:36]
	v_add_f64 v[35:36], v[70:71], v[50:51]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[37:38], v[64:65], v[30:31]
	v_add_f64 v[28:29], v[28:29], v[33:34]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[68:69], v[35:36], -v[70:71]
	v_add_f64 v[33:34], v[35:36], v[37:38]
	v_add_f64 v[64:65], v[37:38], -v[64:65]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[48:49], v[66:67], v[28:29]
	v_add_f64 v[50:51], v[50:51], -v[68:69]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[52:53], v[33:34], -v[35:36]
	v_add_f64 v[30:31], v[30:31], -v[64:65]
	s_delay_alu instid0(VALU_DEP_4)
	v_add_f64 v[54:55], v[48:49], -v[66:67]
	v_add_f64 v[66:67], v[48:49], v[48:49]
	v_mul_f64 v[80:81], 0x40080000, v[48:49]
	v_add_f64 v[70:71], v[33:34], -v[52:53]
	v_add_f64 v[37:38], v[37:38], -v[52:53]
	v_add_f64 v[28:29], v[28:29], -v[54:55]
	v_fma_f64 v[54:55], v[48:49], 2.0, -v[66:67]
	v_fma_f64 v[48:49], 0x40080000, v[48:49], -v[80:81]
	v_cmp_class_f64_e64 vcc_lo, v[66:67], 0x204
	v_add_f64 v[35:36], v[35:36], -v[70:71]
	v_cmp_class_f64_e64 s0, v[80:81], 0x204
	v_fma_f64 v[52:53], v[28:29], 2.0, v[54:55]
	v_fma_f64 v[28:29], 0x40080000, v[28:29], v[48:49]
	v_add_f64 v[54:55], v[50:51], v[30:31]
	v_add_f64 v[35:36], v[37:38], v[35:36]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[37:38], v[66:67], v[52:53]
	v_add_f64 v[64:65], v[80:81], v[28:29]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[48:49], v[54:55], -v[50:51]
	v_add_f64 v[35:36], v[54:55], v[35:36]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_cndmask_b32 v69, v38, v67 :: v_dual_cndmask_b32 v68, v37, v66
	v_cndmask_b32_e64 v85, v65, v81, s0
	v_cndmask_b32_e64 v84, v64, v80, s0
	v_add_f64 v[54:55], v[54:55], -v[48:49]
	v_add_f64 v[82:83], v[33:34], v[35:36]
	v_mul_f64 v[70:71], v[68:69], s[8:9]
	v_add_f64 v[30:31], v[30:31], -v[48:49]
	v_mul_f64 v[86:87], v[84:85], s[8:9]
	v_add_f64 v[37:38], v[37:38], -v[66:67]
	v_cmp_ngt_f64_e64 s1, 0xc090cc00, v[68:69]
	v_add_f64 v[64:65], v[64:65], -v[80:81]
	v_add_f64 v[48:49], v[50:51], -v[54:55]
	v_add_f64 v[33:34], v[82:83], -v[33:34]
	v_rndne_f64_e32 v[70:71], v[70:71]
	v_rndne_f64_e32 v[50:51], v[86:87]
	v_add_f64 v[37:38], v[52:53], -v[37:38]
	v_add_f64 v[28:29], v[28:29], -v[64:65]
	v_add_f64 v[30:31], v[30:31], v[48:49]
	v_add_f64 v[33:34], v[35:36], -v[33:34]
	v_fma_f64 v[54:55], v[70:71], s[10:11], v[68:69]
	v_cvt_i32_f64_e32 v39, v[70:71]
	v_fma_f64 v[35:36], v[50:51], s[10:11], v[84:85]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[30:31], v[30:31], v[33:34]
	v_fma_f64 v[48:49], v[70:71], s[14:15], v[54:55]
	v_cvt_i32_f64_e32 v70, v[50:51]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_fma_f64 v[33:34], v[50:51], s[14:15], v[35:36]
	v_mul_f64 v[50:51], 0xc0040000, v[24:25]
	v_add_f64 v[54:55], v[82:83], v[30:31]
	v_fma_f64 v[35:36], v[48:49], s[16:17], s[12:13]
	v_fma_f64 v[86:87], v[33:34], s[16:17], s[12:13]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[82:83], v[54:55], -v[82:83]
	v_fma_f64 v[35:36], v[48:49], v[35:36], s[2:3]
	v_add_f64 v[96:97], v[54:55], v[54:55]
	s_delay_alu instid0(VALU_DEP_4)
	v_fma_f64 v[86:87], v[33:34], v[86:87], s[2:3]
	v_mul_f64 v[98:99], 0x40080000, v[54:55]
	v_add_f64 v[30:31], v[30:31], -v[82:83]
	v_fma_f64 v[35:36], v[48:49], v[35:36], s[6:7]
	v_fma_f64 v[82:83], v[54:55], 2.0, -v[96:97]
	v_fma_f64 v[86:87], v[33:34], v[86:87], s[6:7]
	v_fma_f64 v[54:55], 0x40080000, v[54:55], -v[98:99]
	v_cmp_class_f64_e64 vcc_lo, v[96:97], 0x204
	v_cmp_class_f64_e64 s0, v[98:99], 0x204
	v_fma_f64 v[35:36], v[48:49], v[35:36], s[26:27]
	v_fma_f64 v[82:83], v[30:31], 2.0, v[82:83]
	v_fma_f64 v[86:87], v[33:34], v[86:87], s[26:27]
	v_fma_f64 v[30:31], 0x40080000, v[30:31], v[54:55]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[35:36], v[48:49], v[35:36], s[22:23]
	v_add_f64 v[54:55], v[96:97], v[82:83]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[86:87], v[33:34], v[86:87], s[22:23]
	v_add_f64 v[100:101], v[98:99], v[30:31]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[35:36], v[48:49], v[35:36], s[18:19]
	v_dual_cndmask_b32 v103, v55, v97 :: v_dual_cndmask_b32 v102, v54, v96
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[86:87], v[33:34], v[86:87], s[18:19]
	v_cndmask_b32_e64 v115, v101, v99, s0
	v_cndmask_b32_e64 v114, v100, v98, s0
	v_cmp_nlt_f64_e64 s0, 0x40900000, v[68:69]
	v_mul_f64 v[112:113], v[102:103], s[8:9]
	v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[68:69]|
	v_add_f64 v[54:55], v[54:55], -v[96:97]
	v_mul_f64 v[116:117], v[114:115], s[8:9]
	s_mov_b32 s8, 0x55555511
	s_mov_b32 s9, 0x3fc55555
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s5, s9
	v_fma_f64 v[35:36], v[48:49], v[35:36], s[20:21]
	v_fma_f64 v[86:87], v[33:34], v[86:87], s[20:21]
	v_rndne_f64_e32 v[112:113], v[112:113]
	v_dual_cndmask_b32 v38, 0, v38 :: v_dual_cndmask_b32 v37, 0, v37
	v_rndne_f64_e32 v[116:117], v[116:117]
	v_cmp_nlt_f64_e32 vcc_lo, 0x40900000, v[84:85]
	v_add_f64 v[54:55], v[82:83], -v[54:55]
	v_fma_f64 v[35:36], v[48:49], v[35:36], s[8:9]
	v_fma_f64 v[86:87], v[33:34], v[86:87], s[8:9]
	v_fma_f64 v[118:119], v[112:113], s[10:11], v[102:103]
	v_fma_f64 v[128:129], v[116:117], s[10:11], v[114:115]
	v_cvt_i32_f64_e32 v96, v[116:117]
	v_fma_f64 v[35:36], v[48:49], v[35:36], s[28:29]
	v_fma_f64 v[86:87], v[33:34], v[86:87], s[28:29]
	v_fma_f64 v[118:119], v[112:113], s[14:15], v[118:119]
	v_fma_f64 v[128:129], v[116:117], s[14:15], v[128:129]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[35:36], v[48:49], v[35:36], 1.0
	v_fma_f64 v[86:87], v[33:34], v[86:87], 1.0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[66:67], v[128:129], s[16:17], s[12:13]
	v_fma_f64 v[35:36], v[48:49], v[35:36], 1.0
	v_fma_f64 v[48:49], v[118:119], s[16:17], s[12:13]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[33:34], v[33:34], v[86:87], 1.0
	v_fma_f64 v[52:53], v[128:129], v[66:67], s[2:3]
	v_mul_f64 v[66:67], v[26:27], -0.5
	v_fma_f64 v[26:27], v[26:27], 2.0, v[50:51]
	v_ldexp_f64 v[35:36], v[35:36], v39
	v_fma_f64 v[48:49], v[118:119], v[48:49], s[2:3]
	v_cmp_ngt_f64_e64 s3, 0xc090cc00, v[84:85]
	v_ldexp_f64 v[33:34], v[33:34], v70
	v_cmp_neq_f64_e64 s2, 0x7ff00000, |v[84:85]|
	v_fma_f64 v[50:51], v[128:129], v[52:53], s[6:7]
	v_fma_f64 v[24:25], v[24:25], 0.5, v[66:67]
	v_fma_f64 v[26:27], v[22:23], -0.5, v[26:27]
	v_div_scale_f64 v[52:53], null, v[8:9], v[8:9], v[18:19]
	v_cndmask_b32_e64 v36, 0x7ff00000, v36, s0
	s_and_b32 s0, s1, s0
	v_fma_f64 v[48:49], v[118:119], v[48:49], s[6:7]
	v_cndmask_b32_e64 v35, 0, v35, s0
	v_cndmask_b32_e32 v34, 0x7ff00000, v34, vcc_lo
	v_cndmask_b32_e64 v36, 0, v36, s1
	v_cmp_eq_f64_e64 s1, 0, v[8:9]
	s_and_b32 vcc_lo, s3, vcc_lo
	v_cndmask_b32_e64 v29, 0, v29, s2
	v_cndmask_b32_e64 v28, 0, v28, s2
	v_fma_f64 v[37:38], v[35:36], v[37:38], v[35:36]
	v_cmp_class_f64_e64 s0, v[35:36], 0x204
	v_cndmask_b32_e64 v34, 0, v34, s3
	v_fma_f64 v[22:23], v[22:23], s[4:5], v[24:25]
	v_fma_f64 v[50:51], v[128:129], v[50:51], s[26:27]
	v_cmp_neq_f64_e64 s2, 0x7ff00000, |v[102:103]|
	v_cmp_nlt_f64_e64 s3, 0x40900000, v[102:103]
	v_cmp_ngt_f64_e64 s4, 0xc090cc00, v[102:103]
	v_cmp_ngt_f64_e64 s5, 0xc090cc00, v[114:115]
	v_cmp_class_f64_e64 s6, v[4:5], 0x204
	v_fma_f64 v[48:49], v[118:119], v[48:49], s[26:27]
	v_cndmask_b32_e64 v39, 0x7ff00000, 0, s1
	v_cndmask_b32_e64 v36, v38, v36, s0
	v_cndmask_b32_e32 v33, 0, v33, vcc_lo
	v_cndmask_b32_e64 v35, v37, v35, s0
	s_or_b32 s0, s1, s24
	v_rcp_f64_e32 v[37:38], v[52:53]
	v_and_b32_e32 v36, 0x7fffffff, v36
	v_fma_f64 v[28:29], v[33:34], v[28:29], v[33:34]
	v_cmp_class_f64_e64 vcc_lo, v[33:34], 0x204
	v_cndmask_b32_e64 v35, v35, 0, s0
	v_fma_f64 v[50:51], v[128:129], v[50:51], s[22:23]
	v_cndmask_b32_e64 v36, v36, v39, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(TRANS32_DEP_1)
	v_div_scale_f64 v[24:25], null, v[35:36], v[35:36], v[26:27]
	v_fma_f64 v[48:49], v[118:119], v[48:49], s[22:23]
	v_fma_f64 v[66:67], -v[52:53], v[37:38], 1.0
	v_dual_cndmask_b32 v28, v28, v33 :: v_dual_cndmask_b32 v29, v29, v34
	v_bfi_b32 v33, 0x7fffffff, v39, v9
	v_fma_f64 v[50:51], v[128:129], v[50:51], s[18:19]
	v_div_scale_f64 v[80:81], vcc_lo, v[18:19], v[8:9], v[18:19]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_bfi_b32 v29, 0x7fffffff, v29, v9
	v_cndmask_b32_e64 v28, v28, 0, s0
	v_rcp_f64_e32 v[64:65], v[24:25]
	v_cvt_i32_f64_e32 v39, v[112:113]
	v_cndmask_b32_e64 v29, v29, v33, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(TRANS32_DEP_1)
	v_div_scale_f64 v[33:34], null, v[28:29], v[28:29], v[22:23]
	v_div_scale_f64 v[86:87], s1, v[22:23], v[28:29], v[22:23]
	v_fma_f64 v[48:49], v[118:119], v[48:49], s[18:19]
	v_fma_f64 v[37:38], v[37:38], v[66:67], v[37:38]
	v_fma_f64 v[50:51], v[128:129], v[50:51], s[20:21]
	v_fma_f64 v[70:71], -v[24:25], v[64:65], 1.0
	v_rcp_f64_e32 v[68:69], v[33:34]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[48:49], v[118:119], v[48:49], s[20:21]
	v_fma_f64 v[50:51], v[128:129], v[50:51], s[8:9]
	s_delay_alu instid0(VALU_DEP_3)
	v_fma_f64 v[64:65], v[64:65], v[70:71], v[64:65]
	v_fma_f64 v[70:71], -v[52:53], v[37:38], 1.0
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[66:67], -v[33:34], v[68:69], 1.0
	v_fma_f64 v[48:49], v[118:119], v[48:49], s[8:9]
	v_fma_f64 v[50:51], v[128:129], v[50:51], s[28:29]
	v_fma_f64 v[37:38], v[37:38], v[70:71], v[37:38]
	v_div_scale_f64 v[70:71], s0, v[26:27], v[35:36], v[26:27]
	v_fma_f64 v[66:67], v[68:69], v[66:67], v[68:69]
	v_fma_f64 v[68:69], -v[24:25], v[64:65], 1.0
	v_fma_f64 v[48:49], v[118:119], v[48:49], s[28:29]
	v_fma_f64 v[50:51], v[128:129], v[50:51], 1.0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[84:85], -v[33:34], v[66:67], 1.0
	v_fma_f64 v[64:65], v[64:65], v[68:69], v[64:65]
	v_mul_f64 v[68:69], v[80:81], v[37:38]
	v_fma_f64 v[48:49], v[118:119], v[48:49], 1.0
	v_fma_f64 v[50:51], v[128:129], v[50:51], 1.0
	v_fma_f64 v[66:67], v[66:67], v[84:85], v[66:67]
	v_mul_f64 v[84:85], v[70:71], v[64:65]
	v_fma_f64 v[52:53], -v[52:53], v[68:69], v[80:81]
	v_fma_f64 v[48:49], v[118:119], v[48:49], 1.0
	v_ldexp_f64 v[50:51], v[50:51], v96
	v_mul_f64 v[80:81], v[86:87], v[66:67]
	v_fma_f64 v[24:25], -v[24:25], v[84:85], v[70:71]
	v_div_fmas_f64 v[37:38], v[52:53], v[37:38], v[68:69]
	v_add_f64 v[52:53], v[100:101], -v[98:99]
	v_ldexp_f64 v[48:49], v[48:49], v39
	s_mov_b32 vcc_lo, s0
	v_cmp_neq_f64_e64 s0, 0x7ff00000, |v[114:115]|
	v_fma_f64 v[33:34], -v[33:34], v[80:81], v[86:87]
	v_div_fmas_f64 v[24:25], v[24:25], v[64:65], v[84:85]
	v_div_fixup_f64 v[18:19], v[37:38], v[8:9], v[18:19]
	v_cndmask_b32_e64 v38, 0, v55, s2
	v_cndmask_b32_e64 v39, 0x7ff00000, v49, s3
	v_cndmask_b32_e64 v37, 0, v54, s2
	v_cmp_nlt_f64_e64 s2, 0x40900000, v[114:115]
	s_and_b32 vcc_lo, s4, s3
	v_add_f64 v[30:31], v[30:31], -v[52:53]
	v_cndmask_b32_e64 v49, 0, v39, s4
	v_cndmask_b32_e32 v48, 0, v48, vcc_lo
	v_cmp_eq_f64_e64 s4, 0, v[4:5]
	s_mov_b32 vcc_lo, s1
	s_delay_alu instid0(VALU_DEP_2)
	v_fma_f64 v[37:38], v[48:49], v[37:38], v[48:49]
	v_cmp_class_f64_e64 s3, v[48:49], 0x204
	v_div_fmas_f64 v[33:34], v[33:34], v[66:67], v[80:81]
	v_div_fixup_f64 v[24:25], v[24:25], v[35:36], v[26:27]
	v_fma_f64 v[18:19], v[4:5], v[18:19], v[12:13]
	v_cndmask_b32_e64 v51, 0x7ff00000, v51, s2
	s_and_b32 vcc_lo, s5, s2
	v_cndmask_b32_e64 v27, 0, v31, s0
	v_cndmask_b32_e64 v26, 0, v30, s0
	v_cndmask_b32_e32 v30, 0, v50, vcc_lo
	v_cndmask_b32_e64 v31, 0, v51, s5
	s_or_b32 s0, s4, s6
	v_cndmask_b32_e64 v4, v38, v49, s3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
	v_fma_f64 v[26:27], v[30:31], v[26:27], v[30:31]
	v_cmp_class_f64_e64 vcc_lo, v[30:31], 0x204
	v_cndmask_b32_e64 v38, 0x7ff00000, 0, s4
	v_cndmask_b32_e64 v35, v37, v48, s3
	v_and_b32_e32 v4, 0x7fffffff, v4
	v_cndmask_b32_e64 v35, v35, 0, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v36, v4, v38, s0
	v_div_fixup_f64 v[22:23], v[33:34], v[28:29], v[22:23]
	v_fma_f64 v[18:19], v[24:25], v[35:36], v[18:19]
	v_cndmask_b32_e32 v24, v27, v31, vcc_lo
	v_cndmask_b32_e32 v4, v26, v30, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_bfi_b32 v24, 0x7fffffff, v24, v5
	v_bfi_b32 v5, 0x7fffffff, v38, v5
	v_cndmask_b32_e64 v4, v4, 0, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v5, v24, v5, s0
	v_fma_f64 v[4:5], v[22:23], v[4:5], v[18:19]
	flat_store_b64 v[0:1], v[4:5]
.LBB2_2:
	s_or_b32 exec_lo, exec_lo, s25
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s25, exec_lo
	v_cmpx_neq_f64_e32 v[6:7], v[8:9]
	s_cbranch_execz .LBB2_4
; %bb.3:
	v_add_f64 v[14:15], v[14:15], -v[10:11]
	v_add_f64 v[12:13], v[12:13], -v[10:11]
	v_add_f64 v[4:5], v[16:17], -v[10:11]
	s_mov_b32 s5, 0x3fd55555
	s_mov_b32 s4, 0x55555555
	v_fma_f64 v[6:7], v[8:9], 2.0, -v[6:7]
	s_mov_b32 s2, 0x968915a9
	s_mov_b32 s6, 0x4222de17
	s_mov_b32 s3, 0x3fba6564
	s_mov_b32 s7, 0x3fbdee67
	s_mov_b32 s8, 0x3abe935a
	s_mov_b32 s9, 0x3fbe25e4
	s_mov_b32 s10, 0x47e6c9c2
	s_mov_b32 s11, 0x3fc110ef
	s_mov_b32 s12, 0xcfa74449
	s_mov_b32 s13, 0x3fc3b13b
	s_mov_b32 s14, 0x71bf3c30
	s_mov_b32 s15, 0x3fc745d1
	s_mov_b32 s16, 0x1c7792ce
	s_mov_b32 s17, 0x3fcc71c7
	s_mov_b32 s18, 0x924920da
	s_mov_b32 s19, 0x3fd24924
	s_mov_b32 s20, 0x9999999c
	s_mov_b32 s21, 0x3fd99999
	s_mov_b32 s26, 0x14761f6e
	s_mov_b32 s27, 0x3f2a01a0
	s_mov_b32 s22, 0x1852b7b0
	s_mov_b32 s23, 0x3f56c16c
	s_mov_b32 s28, 11
	s_mov_b32 s29, 0x3fe00000
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[0:1], 0xbff80000, v[14:15]
	v_frexp_mant_f64_e64 v[30:31], |v[6:7]|
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[0:1], 0x40080000, v[12:13], v[0:1]
	v_fma_f64 v[0:1], v[4:5], s[4:5], v[0:1]
	s_mov_b32 s5, 0x3fe55555
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cmp_gt_f64_e32 vcc_lo, s[4:5], v[20:21]
	v_cmp_gt_f64_e64 s0, s[4:5], v[30:31]
	v_cndmask_b32_e64 v16, 0, 1, vcc_lo
	v_subrev_co_ci_u32_e32 v32, vcc_lo, 0, v32, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ldexp_f64 v[20:21], v[20:21], v16
	v_add_f64 v[22:23], v[20:21], 1.0
	v_add_f64 v[24:25], v[20:21], -1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[16:17], v[22:23]
	v_add_f64 v[26:27], v[22:23], -1.0
	v_add_f64 v[20:21], v[20:21], -v[26:27]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[18:19], -v[22:23], v[16:17], 1.0
	v_cndmask_b32_e64 v26, 0, 1, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_ldexp_f64 v[26:27], v[30:31], v26
	v_fma_f64 v[16:17], v[18:19], v[16:17], v[16:17]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[18:19], -v[22:23], v[16:17], 1.0
	v_fma_f64 v[18:19], v[18:19], v[16:17], v[16:17]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[16:17], v[24:25], v[18:19]
	v_mul_f64 v[28:29], v[22:23], v[16:17]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[22:23], v[16:17], v[22:23], -v[28:29]
	v_fma_f64 v[20:21], v[16:17], v[20:21], v[22:23]
	v_add_f64 v[22:23], v[26:27], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[30:31], v[28:29], v[20:21]
	v_rcp_f64_e32 v[33:34], v[22:23]
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[35:36], v[24:25], -v[30:31]
	v_add_f64 v[28:29], v[30:31], -v[28:29]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[37:38], -v[22:23], v[33:34], 1.0
	v_add_f64 v[24:25], v[24:25], -v[35:36]
	v_add_f64 v[20:21], v[28:29], -v[20:21]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[33:34], v[37:38], v[33:34], v[33:34]
	v_add_f64 v[24:25], v[24:25], -v[30:31]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[28:29], -v[22:23], v[33:34], 1.0
	v_add_f64 v[20:21], v[20:21], v[24:25]
	v_add_f64 v[24:25], v[26:27], -1.0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[28:29], v[28:29], v[33:34], v[33:34]
	v_add_f64 v[20:21], v[35:36], v[20:21]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[30:31], v[24:25], v[28:29]
	v_mul_f64 v[18:19], v[18:19], v[20:21]
	v_add_f64 v[20:21], v[22:23], -1.0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f64 v[33:34], v[22:23], v[30:31]
	v_add_f64 v[35:36], v[16:17], v[18:19]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[20:21], v[26:27], -v[20:21]
	v_fma_f64 v[22:23], v[30:31], v[22:23], -v[33:34]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[16:17], v[35:36], -v[16:17]
	v_fma_f64 v[20:21], v[30:31], v[20:21], v[22:23]
	v_mul_f64 v[22:23], v[35:36], v[35:36]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[16:17], v[18:19], -v[16:17]
	v_add_f64 v[18:19], v[33:34], v[20:21]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[26:27], v[35:36], v[35:36], -v[22:23]
	v_add_f64 v[37:38], v[16:17], v[16:17]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[48:49], v[24:25], -v[18:19]
	v_add_f64 v[33:34], v[18:19], -v[33:34]
	v_fma_f64 v[26:27], v[35:36], v[37:38], v[26:27]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[24:25], v[24:25], -v[48:49]
	v_add_f64 v[20:21], v[33:34], -v[20:21]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[37:38], v[22:23], v[26:27]
	v_add_f64 v[18:19], v[24:25], -v[18:19]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_fma_f64 v[24:25], v[37:38], s[6:7], s[2:3]
	v_add_f64 v[22:23], v[37:38], -v[22:23]
	v_mul_f64 v[54:55], v[35:36], v[37:38]
	v_add_f64 v[18:19], v[20:21], v[18:19]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[20:21], v[37:38], v[24:25], s[8:9]
	v_add_f64 v[22:23], v[26:27], -v[22:23]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[18:19], v[48:49], v[18:19]
	v_fma_f64 v[20:21], v[37:38], v[20:21], s[10:11]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[18:19], v[28:29], v[18:19]
	v_fma_f64 v[20:21], v[37:38], v[20:21], s[12:13]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[24:25], v[30:31], v[18:19]
	v_fma_f64 v[20:21], v[37:38], v[20:21], s[14:15]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[28:29], v[24:25], -v[30:31]
	v_mul_f64 v[30:31], v[24:25], v[24:25]
	v_fma_f64 v[20:21], v[37:38], v[20:21], s[16:17]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[18:19], v[18:19], -v[28:29]
	v_fma_f64 v[28:29], v[24:25], v[24:25], -v[30:31]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[20:21], v[37:38], v[20:21], s[18:19]
	v_add_f64 v[33:34], v[18:19], v[18:19]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[20:21], v[37:38], v[20:21], s[20:21]
	v_fma_f64 v[28:29], v[24:25], v[33:34], v[28:29]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[33:34], v[37:38], v[20:21]
	v_add_f64 v[48:49], v[30:31], v[28:29]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[26:27], v[37:38], v[20:21], -v[33:34]
	v_fma_f64 v[50:51], v[48:49], s[6:7], s[2:3]
	s_mov_b32 s3, 0xbfe55555
	s_mov_b32 s2, s4
	s_mov_b32 s6, 0xd5df274d
	s_mov_b32 s7, 0x3c8543b0
	v_add_f64 v[30:31], v[48:49], -v[30:31]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[20:21], v[22:23], v[20:21], v[26:27]
	v_fma_f64 v[26:27], v[48:49], v[50:51], s[8:9]
	s_mov_b32 s8, 0x652b82fe
	s_mov_b32 s9, 0x3ff71547
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[28:29], v[28:29], -v[30:31]
	v_add_f64 v[50:51], v[33:34], v[20:21]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_fma_f64 v[26:27], v[48:49], v[26:27], s[10:11]
	s_mov_b32 s10, 0xfefa39ef
	s_mov_b32 s11, 0x3fe62e42
	v_add_f64 v[52:53], v[50:51], s[4:5]
	v_add_f64 v[33:34], v[50:51], -v[33:34]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_fma_f64 v[26:27], v[48:49], v[26:27], s[12:13]
	s_mov_b32 s12, 0xfca7ab0c
	s_mov_b32 s13, 0x3e928af3
	v_add_f64 v[64:65], v[52:53], s[2:3]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f64 v[20:21], v[20:21], -v[33:34]
	v_fma_f64 v[33:34], v[37:38], v[35:36], -v[54:55]
	v_fma_f64 v[26:27], v[48:49], v[26:27], s[14:15]
	s_mov_b32 s14, 0x3b39803f
	s_mov_b32 s15, 0x3c7abc9e
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[50:51], v[50:51], -v[64:65]
	v_add_f64 v[20:21], v[20:21], s[6:7]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[33:34], v[37:38], v[16:17], v[33:34]
	v_fma_f64 v[26:27], v[48:49], v[26:27], s[16:17]
	v_ldexp_f64 v[16:17], v[16:17], 1
	s_mov_b32 s16, 0x6a5dcb37
	s_mov_b32 s17, 0x3e5ade15
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[20:21], v[20:21], v[50:51]
	v_fma_f64 v[22:23], v[22:23], v[35:36], v[33:34]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_fma_f64 v[26:27], v[48:49], v[26:27], s[18:19]
	s_mov_b32 s18, 0x11122322
	s_mov_b32 s19, 0x3f811111
	v_add_f64 v[33:34], v[52:53], v[20:21]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[37:38], v[54:55], v[22:23]
	v_fma_f64 v[26:27], v[48:49], v[26:27], s[20:21]
	s_mov_b32 s20, 0x555502a1
	s_mov_b32 s21, 0x3fa55555
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[50:51], v[52:53], -v[33:34]
	v_mul_f64 v[52:53], v[37:38], v[33:34]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_mul_f64 v[64:65], v[48:49], v[26:27]
	v_add_f64 v[54:55], v[37:38], -v[54:55]
	v_add_f64 v[20:21], v[20:21], v[50:51]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[50:51], v[37:38], v[33:34], -v[52:53]
	v_fma_f64 v[30:31], v[48:49], v[26:27], -v[64:65]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f64 v[22:23], v[22:23], -v[54:55]
	v_cvt_f64_i32_e32 v[54:55], v32
	v_fma_f64 v[20:21], v[37:38], v[20:21], v[50:51]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_fma_f64 v[26:27], v[28:29], v[26:27], v[30:31]
	v_ldexp_f64 v[30:31], v[35:36], 1
	v_mul_f64 v[35:36], v[24:25], v[48:49]
	v_fma_f64 v[20:21], v[22:23], v[33:34], v[20:21]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[22:23], v[64:65], v[26:27]
	v_fma_f64 v[66:67], v[48:49], v[24:25], -v[35:36]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[33:34], v[52:53], v[20:21]
	v_add_f64 v[37:38], v[22:23], s[4:5]
	v_add_f64 v[50:51], v[22:23], -v[64:65]
	s_delay_alu instid0(VALU_DEP_4)
	v_fma_f64 v[48:49], v[48:49], v[18:19], v[66:67]
	v_ldexp_f64 v[18:19], v[18:19], 1
	v_add_f64 v[64:65], v[30:31], v[33:34]
	v_add_f64 v[52:53], v[33:34], -v[52:53]
	v_add_f64 v[68:69], v[37:38], s[2:3]
	v_add_f64 v[26:27], v[26:27], -v[50:51]
	v_mul_f64 v[50:51], v[54:55], s[10:11]
	s_mov_b32 s2, 0x623fde64
	s_mov_b32 s3, 0x3ec71dee
	v_add_f64 v[30:31], v[64:65], -v[30:31]
	v_add_f64 v[20:21], v[20:21], -v[52:53]
	v_add_f64 v[22:23], v[22:23], -v[68:69]
	v_add_f64 v[26:27], v[26:27], s[6:7]
	v_fma_f64 v[52:53], v[54:55], s[10:11], -v[50:51]
	s_mov_b32 s6, 0x7c89e6b0
	s_mov_b32 s7, 0x3efa0199
	v_add_f64 v[30:31], v[33:34], -v[30:31]
	v_add_f64 v[16:17], v[16:17], v[20:21]
	v_fma_f64 v[20:21], v[28:29], v[24:25], v[48:49]
	v_add_f64 v[22:23], v[26:27], v[22:23]
	v_fma_f64 v[26:27], v[54:55], s[14:15], v[52:53]
	v_ldexp_f64 v[24:25], v[24:25], 1
	v_add_f64 v[16:17], v[16:17], v[30:31]
	v_add_f64 v[30:31], v[35:36], v[20:21]
	v_add_f64 v[28:29], v[37:38], v[22:23]
	v_add_f64 v[32:33], v[50:51], v[26:27]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[48:49], v[64:65], v[16:17]
	v_add_f64 v[34:35], v[30:31], -v[35:36]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f64 v[37:38], v[37:38], -v[28:29]
	v_mul_f64 v[52:53], v[30:31], v[28:29]
	v_add_f64 v[54:55], v[32:33], v[48:49]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[20:21], v[20:21], -v[34:35]
	v_add_f64 v[22:23], v[22:23], v[37:38]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_fma_f64 v[36:37], v[30:31], v[28:29], -v[52:53]
	v_add_f64 v[34:35], v[48:49], -v[64:65]
	v_add_f64 v[38:39], v[54:55], -v[32:33]
	v_fma_f64 v[22:23], v[30:31], v[22:23], v[36:37]
	v_add_f64 v[30:31], v[32:33], -v[50:51]
	s_delay_alu instid0(VALU_DEP_4)
	v_add_f64 v[16:17], v[16:17], -v[34:35]
	v_frexp_exp_i32_f64_e32 v34, v[6:7]
	v_add_f64 v[36:37], v[54:55], -v[38:39]
	v_fma_f64 v[20:21], v[20:21], v[28:29], v[22:23]
	v_add_f64 v[22:23], v[26:27], -v[30:31]
	v_add_f64 v[26:27], v[48:49], -v[38:39]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[28:29], v[32:33], -v[36:37]
	v_add_f64 v[30:31], v[52:53], v[20:21]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[32:33], v[22:23], v[16:17]
	v_add_f64 v[26:27], v[26:27], v[28:29]
	v_subrev_co_ci_u32_e64 v28, vcc_lo, 0, v34, s0
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_add_f64 v[34:35], v[24:25], v[30:31]
	v_add_f64 v[36:37], v[30:31], -v[52:53]
	v_add_f64 v[38:39], v[32:33], -v[22:23]
	v_cvt_f64_i32_e32 v[28:29], v28
	v_add_f64 v[26:27], v[32:33], v[26:27]
	v_add_f64 v[24:25], v[34:35], -v[24:25]
	v_add_f64 v[20:21], v[20:21], -v[36:37]
	v_add_f64 v[32:33], v[32:33], -v[38:39]
	v_mul_f64 v[48:49], v[28:29], s[10:11]
	v_add_f64 v[16:17], v[16:17], -v[38:39]
	v_add_f64 v[36:37], v[54:55], v[26:27]
	v_add_f64 v[24:25], v[30:31], -v[24:25]
	v_add_f64 v[18:19], v[18:19], v[20:21]
	v_add_f64 v[20:21], v[22:23], -v[32:33]
	v_fma_f64 v[50:51], v[28:29], s[10:11], -v[48:49]
	s_mov_b32 s11, 0xbfe62e42
	v_add_f64 v[22:23], v[36:37], -v[54:55]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[18:19], v[18:19], v[24:25]
	v_add_f64 v[16:17], v[16:17], v[20:21]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_fma_f64 v[28:29], v[28:29], s[14:15], v[50:51]
	s_mov_b32 s15, 0xbc7abc9e
	v_add_f64 v[20:21], v[26:27], -v[22:23]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[24:25], v[34:35], v[18:19]
	v_add_f64 v[22:23], v[48:49], v[28:29]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[16:17], v[16:17], v[20:21]
	v_add_f64 v[34:35], v[24:25], -v[34:35]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f64 v[20:21], v[22:23], v[24:25]
	v_add_f64 v[38:39], v[22:23], -v[48:49]
	v_add_f64 v[26:27], v[36:37], v[16:17]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[18:19], v[18:19], -v[34:35]
	v_add_f64 v[30:31], v[20:21], -v[22:23]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[28:29], v[28:29], -v[38:39]
	v_add_f64 v[32:33], v[26:27], -v[36:37]
	v_add_f64 v[36:37], v[26:27], v[26:27]
	v_mul_f64 v[50:51], 0x40080000, v[26:27]
	v_add_f64 v[48:49], v[20:21], -v[30:31]
	v_add_f64 v[24:25], v[24:25], -v[30:31]
	v_add_f64 v[16:17], v[16:17], -v[32:33]
	v_fma_f64 v[32:33], v[26:27], 2.0, -v[36:37]
	v_fma_f64 v[26:27], 0x40080000, v[26:27], -v[50:51]
	v_cmp_class_f64_e64 vcc_lo, v[36:37], 0x204
	v_cmp_class_f64_e64 s0, v[50:51], 0x204
	v_add_f64 v[22:23], v[22:23], -v[48:49]
	v_fma_f64 v[30:31], v[16:17], 2.0, v[32:33]
	v_fma_f64 v[16:17], 0x40080000, v[16:17], v[26:27]
	v_add_f64 v[32:33], v[28:29], v[18:19]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[22:23], v[24:25], v[22:23]
	v_add_f64 v[24:25], v[36:37], v[30:31]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[34:35], v[50:51], v[16:17]
	v_add_f64 v[26:27], v[32:33], -v[28:29]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[22:23], v[32:33], v[22:23]
	v_dual_cndmask_b32 v39, v25, v37 :: v_dual_cndmask_b32 v38, v24, v36
	s_delay_alu instid0(VALU_DEP_4)
	v_cndmask_b32_e64 v55, v35, v51, s0
	v_cndmask_b32_e64 v54, v34, v50, s0
	v_add_f64 v[32:33], v[32:33], -v[26:27]
	v_add_f64 v[52:53], v[20:21], v[22:23]
	v_mul_f64 v[48:49], v[38:39], s[8:9]
	v_add_f64 v[18:19], v[18:19], -v[26:27]
	v_mul_f64 v[64:65], v[54:55], s[8:9]
	v_add_f64 v[24:25], v[24:25], -v[36:37]
	v_cmp_ngt_f64_e64 s1, 0xc090cc00, v[38:39]
	v_add_f64 v[34:35], v[34:35], -v[50:51]
	v_add_f64 v[26:27], v[28:29], -v[32:33]
	v_add_f64 v[20:21], v[52:53], -v[20:21]
	v_rndne_f64_e32 v[48:49], v[48:49]
	v_rndne_f64_e32 v[28:29], v[64:65]
	v_add_f64 v[24:25], v[30:31], -v[24:25]
	v_add_f64 v[16:17], v[16:17], -v[34:35]
	v_add_f64 v[18:19], v[18:19], v[26:27]
	v_add_f64 v[20:21], v[22:23], -v[20:21]
	v_fma_f64 v[32:33], v[48:49], s[10:11], v[38:39]
	v_fma_f64 v[22:23], v[28:29], s[10:11], v[54:55]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[18:19], v[18:19], v[20:21]
	v_fma_f64 v[26:27], v[48:49], s[14:15], v[32:33]
	v_cvt_i32_f64_e32 v48, v[48:49]
	s_delay_alu instid0(VALU_DEP_4)
	v_fma_f64 v[20:21], v[28:29], s[14:15], v[22:23]
	v_cvt_i32_f64_e32 v49, v[28:29]
	v_mul_f64 v[28:29], 0xc0040000, v[12:13]
	v_add_f64 v[32:33], v[52:53], v[18:19]
	v_fma_f64 v[22:23], v[26:27], s[16:17], s[12:13]
	v_fma_f64 v[64:65], v[20:21], s[16:17], s[12:13]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[52:53], v[32:33], -v[52:53]
	v_fma_f64 v[22:23], v[26:27], v[22:23], s[2:3]
	v_add_f64 v[66:67], v[32:33], v[32:33]
	s_delay_alu instid0(VALU_DEP_4)
	v_fma_f64 v[64:65], v[20:21], v[64:65], s[2:3]
	v_mul_f64 v[68:69], 0x40080000, v[32:33]
	v_add_f64 v[18:19], v[18:19], -v[52:53]
	v_fma_f64 v[22:23], v[26:27], v[22:23], s[6:7]
	v_fma_f64 v[52:53], v[32:33], 2.0, -v[66:67]
	v_fma_f64 v[64:65], v[20:21], v[64:65], s[6:7]
	v_fma_f64 v[32:33], 0x40080000, v[32:33], -v[68:69]
	v_cmp_class_f64_e64 vcc_lo, v[66:67], 0x204
	v_cmp_class_f64_e64 s0, v[68:69], 0x204
	v_fma_f64 v[22:23], v[26:27], v[22:23], s[26:27]
	v_fma_f64 v[52:53], v[18:19], 2.0, v[52:53]
	v_fma_f64 v[64:65], v[20:21], v[64:65], s[26:27]
	v_fma_f64 v[18:19], 0x40080000, v[18:19], v[32:33]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[22:23], v[26:27], v[22:23], s[22:23]
	v_add_f64 v[32:33], v[66:67], v[52:53]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[64:65], v[20:21], v[64:65], s[22:23]
	v_add_f64 v[70:71], v[68:69], v[18:19]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[22:23], v[26:27], v[22:23], s[18:19]
	v_dual_cndmask_b32 v81, v33, v67 :: v_dual_cndmask_b32 v80, v32, v66
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[64:65], v[20:21], v[64:65], s[18:19]
	v_cndmask_b32_e64 v85, v71, v69, s0
	v_cndmask_b32_e64 v84, v70, v68, s0
	v_cmp_nlt_f64_e64 s0, 0x40900000, v[38:39]
	v_mul_f64 v[82:83], v[80:81], s[8:9]
	v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[38:39]|
	v_add_f64 v[32:33], v[32:33], -v[66:67]
	v_mul_f64 v[86:87], v[84:85], s[8:9]
	s_mov_b32 s8, 0x55555511
	s_mov_b32 s9, 0x3fc55555
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s5, s9
	v_fma_f64 v[22:23], v[26:27], v[22:23], s[20:21]
	v_fma_f64 v[64:65], v[20:21], v[64:65], s[20:21]
	v_rndne_f64_e32 v[82:83], v[82:83]
	v_dual_cndmask_b32 v25, 0, v25 :: v_dual_cndmask_b32 v24, 0, v24
	v_rndne_f64_e32 v[86:87], v[86:87]
	v_cmp_nlt_f64_e32 vcc_lo, 0x40900000, v[54:55]
	v_add_f64 v[32:33], v[52:53], -v[32:33]
	v_fma_f64 v[22:23], v[26:27], v[22:23], s[8:9]
	v_fma_f64 v[64:65], v[20:21], v[64:65], s[8:9]
	v_fma_f64 v[96:97], v[82:83], s[10:11], v[80:81]
	v_fma_f64 v[98:99], v[86:87], s[10:11], v[84:85]
	v_cvt_i32_f64_e32 v66, v[86:87]
	v_fma_f64 v[22:23], v[26:27], v[22:23], s[28:29]
	v_fma_f64 v[64:65], v[20:21], v[64:65], s[28:29]
	v_fma_f64 v[96:97], v[82:83], s[14:15], v[96:97]
	v_cvt_i32_f64_e32 v82, v[82:83]
	v_fma_f64 v[98:99], v[86:87], s[14:15], v[98:99]
	v_fma_f64 v[22:23], v[26:27], v[22:23], 1.0
	v_fma_f64 v[64:65], v[20:21], v[64:65], 1.0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[36:37], v[98:99], s[16:17], s[12:13]
	v_fma_f64 v[22:23], v[26:27], v[22:23], 1.0
	v_fma_f64 v[26:27], v[96:97], s[16:17], s[12:13]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[20:21], v[20:21], v[64:65], 1.0
	v_fma_f64 v[30:31], v[98:99], v[36:37], s[2:3]
	v_mul_f64 v[36:37], v[14:15], -0.5
	v_fma_f64 v[14:15], v[14:15], 2.0, v[28:29]
	v_ldexp_f64 v[22:23], v[22:23], v48
	v_fma_f64 v[26:27], v[96:97], v[26:27], s[2:3]
	v_cmp_ngt_f64_e64 s3, 0xc090cc00, v[54:55]
	v_ldexp_f64 v[20:21], v[20:21], v49
	v_cmp_neq_f64_e64 s2, 0x7ff00000, |v[54:55]|
	v_fma_f64 v[28:29], v[98:99], v[30:31], s[6:7]
	v_fma_f64 v[12:13], v[12:13], 0.5, v[36:37]
	v_fma_f64 v[14:15], v[4:5], -0.5, v[14:15]
	v_div_scale_f64 v[30:31], null, v[8:9], v[8:9], v[0:1]
	v_cndmask_b32_e64 v23, 0x7ff00000, v23, s0
	s_and_b32 s0, s1, s0
	v_fma_f64 v[26:27], v[96:97], v[26:27], s[6:7]
	v_cndmask_b32_e64 v22, 0, v22, s0
	v_cndmask_b32_e32 v21, 0x7ff00000, v21, vcc_lo
	v_cndmask_b32_e64 v23, 0, v23, s1
	v_cmp_eq_f64_e64 s1, 0, v[8:9]
	s_and_b32 vcc_lo, s3, vcc_lo
	v_cndmask_b32_e64 v17, 0, v17, s2
	v_cndmask_b32_e64 v16, 0, v16, s2
	v_fma_f64 v[24:25], v[22:23], v[24:25], v[22:23]
	v_cmp_class_f64_e64 s0, v[22:23], 0x204
	v_cndmask_b32_e64 v21, 0, v21, s3
	v_fma_f64 v[4:5], v[4:5], s[4:5], v[12:13]
	v_fma_f64 v[28:29], v[98:99], v[28:29], s[26:27]
	v_cmp_neq_f64_e64 s2, 0x7ff00000, |v[80:81]|
	v_cmp_nlt_f64_e64 s3, 0x40900000, v[80:81]
	v_cmp_ngt_f64_e64 s4, 0xc090cc00, v[80:81]
	v_cmp_ngt_f64_e64 s5, 0xc090cc00, v[84:85]
	v_cmp_class_f64_e64 s6, v[6:7], 0x204
	v_fma_f64 v[26:27], v[96:97], v[26:27], s[26:27]
	v_cndmask_b32_e64 v34, 0x7ff00000, 0, s1
	v_cndmask_b32_e64 v23, v25, v23, s0
	v_cndmask_b32_e32 v20, 0, v20, vcc_lo
	v_cndmask_b32_e64 v22, v24, v22, s0
	s_or_b32 s0, s1, s24
	v_rcp_f64_e32 v[24:25], v[30:31]
	v_and_b32_e32 v23, 0x7fffffff, v23
	v_fma_f64 v[16:17], v[20:21], v[16:17], v[20:21]
	v_cmp_class_f64_e64 vcc_lo, v[20:21], 0x204
	v_cndmask_b32_e64 v22, v22, 0, s0
	v_fma_f64 v[28:29], v[98:99], v[28:29], s[22:23]
	v_cndmask_b32_e64 v23, v23, v34, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(TRANS32_DEP_1)
	v_div_scale_f64 v[12:13], null, v[22:23], v[22:23], v[14:15]
	v_fma_f64 v[26:27], v[96:97], v[26:27], s[22:23]
	v_fma_f64 v[36:37], -v[30:31], v[24:25], 1.0
	v_dual_cndmask_b32 v16, v16, v20 :: v_dual_cndmask_b32 v17, v17, v21
	v_bfi_b32 v20, 0x7fffffff, v34, v9
	v_fma_f64 v[28:29], v[98:99], v[28:29], s[18:19]
	v_div_scale_f64 v[50:51], vcc_lo, v[0:1], v[8:9], v[0:1]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_bfi_b32 v17, 0x7fffffff, v17, v9
	v_cndmask_b32_e64 v16, v16, 0, s0
	v_rcp_f64_e32 v[34:35], v[12:13]
	v_cndmask_b32_e64 v17, v17, v20, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(TRANS32_DEP_1)
	v_div_scale_f64 v[20:21], null, v[16:17], v[16:17], v[4:5]
	v_div_scale_f64 v[64:65], s1, v[4:5], v[16:17], v[4:5]
	v_fma_f64 v[26:27], v[96:97], v[26:27], s[18:19]
	v_fma_f64 v[24:25], v[24:25], v[36:37], v[24:25]
	v_fma_f64 v[28:29], v[98:99], v[28:29], s[20:21]
	v_fma_f64 v[48:49], -v[12:13], v[34:35], 1.0
	v_rcp_f64_e32 v[38:39], v[20:21]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[26:27], v[96:97], v[26:27], s[20:21]
	v_fma_f64 v[28:29], v[98:99], v[28:29], s[8:9]
	s_delay_alu instid0(VALU_DEP_3)
	v_fma_f64 v[34:35], v[34:35], v[48:49], v[34:35]
	v_fma_f64 v[48:49], -v[30:31], v[24:25], 1.0
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[36:37], -v[20:21], v[38:39], 1.0
	v_fma_f64 v[26:27], v[96:97], v[26:27], s[8:9]
	v_fma_f64 v[28:29], v[98:99], v[28:29], s[28:29]
	v_fma_f64 v[24:25], v[24:25], v[48:49], v[24:25]
	v_div_scale_f64 v[48:49], s0, v[14:15], v[22:23], v[14:15]
	v_fma_f64 v[36:37], v[38:39], v[36:37], v[38:39]
	v_fma_f64 v[38:39], -v[12:13], v[34:35], 1.0
	v_fma_f64 v[26:27], v[96:97], v[26:27], s[28:29]
	v_fma_f64 v[28:29], v[98:99], v[28:29], 1.0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[54:55], -v[20:21], v[36:37], 1.0
	v_fma_f64 v[34:35], v[34:35], v[38:39], v[34:35]
	v_mul_f64 v[38:39], v[50:51], v[24:25]
	v_fma_f64 v[26:27], v[96:97], v[26:27], 1.0
	v_fma_f64 v[28:29], v[98:99], v[28:29], 1.0
	v_fma_f64 v[36:37], v[36:37], v[54:55], v[36:37]
	v_mul_f64 v[54:55], v[48:49], v[34:35]
	v_fma_f64 v[30:31], -v[30:31], v[38:39], v[50:51]
	v_fma_f64 v[26:27], v[96:97], v[26:27], 1.0
	v_ldexp_f64 v[28:29], v[28:29], v66
	v_mul_f64 v[50:51], v[64:65], v[36:37]
	v_fma_f64 v[12:13], -v[12:13], v[54:55], v[48:49]
	v_div_fmas_f64 v[24:25], v[30:31], v[24:25], v[38:39]
	v_add_f64 v[30:31], v[70:71], -v[68:69]
	v_ldexp_f64 v[26:27], v[26:27], v82
	s_mov_b32 vcc_lo, s0
	v_cmp_neq_f64_e64 s0, 0x7ff00000, |v[84:85]|
	v_fma_f64 v[20:21], -v[20:21], v[50:51], v[64:65]
	v_div_fmas_f64 v[12:13], v[12:13], v[34:35], v[54:55]
	v_div_fixup_f64 v[0:1], v[24:25], v[8:9], v[0:1]
	v_add_f64 v[8:9], v[18:19], -v[30:31]
	v_cndmask_b32_e64 v27, 0x7ff00000, v27, s3
	v_cndmask_b32_e64 v19, 0, v33, s2
	v_cndmask_b32_e64 v18, 0, v32, s2
	v_cmp_nlt_f64_e64 s2, 0x40900000, v[84:85]
	s_and_b32 vcc_lo, s4, s3
	v_cndmask_b32_e64 v25, 0, v27, s4
	v_cndmask_b32_e32 v24, 0, v26, vcc_lo
	v_cmp_eq_f64_e64 s4, 0, v[6:7]
	s_mov_b32 vcc_lo, s1
	s_delay_alu instid0(VALU_DEP_2)
	v_fma_f64 v[18:19], v[24:25], v[18:19], v[24:25]
	v_cmp_class_f64_e64 s3, v[24:25], 0x204
	v_div_fmas_f64 v[20:21], v[20:21], v[36:37], v[50:51]
	v_div_fixup_f64 v[12:13], v[12:13], v[22:23], v[14:15]
	v_fma_f64 v[0:1], v[6:7], v[0:1], v[10:11]
	v_cndmask_b32_e64 v9, 0, v9, s0
	v_cndmask_b32_e64 v8, 0, v8, s0
	v_cndmask_b32_e64 v29, 0x7ff00000, v29, s2
	s_and_b32 vcc_lo, s5, s2
	v_cndmask_b32_e32 v10, 0, v28, vcc_lo
	s_or_b32 s0, s4, s6
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v11, 0, v29, s5
	v_cndmask_b32_e64 v6, v19, v25, s3
	v_fma_f64 v[8:9], v[10:11], v[8:9], v[10:11]
	v_cmp_class_f64_e64 vcc_lo, v[10:11], 0x204
	v_cndmask_b32_e64 v19, 0x7ff00000, 0, s4
	v_cndmask_b32_e64 v14, v18, v24, s3
	v_and_b32_e32 v6, 0x7fffffff, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v14, v14, 0, s0
	v_cndmask_b32_e64 v15, v6, v19, s0
	v_div_fixup_f64 v[4:5], v[20:21], v[16:17], v[4:5]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_fma_f64 v[0:1], v[12:13], v[14:15], v[0:1]
	v_cndmask_b32_e32 v6, v8, v10, vcc_lo
	v_cndmask_b32_e32 v8, v9, v11, vcc_lo
	v_cndmask_b32_e64 v6, v6, 0, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_bfi_b32 v8, 0x7fffffff, v8, v7
	v_bfi_b32 v7, 0x7fffffff, v19, v7
	v_cndmask_b32_e64 v7, v8, v7, s0
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[0:1], v[4:5], v[6:7], v[0:1]
	flat_store_b64 v[2:3], v[0:1]
.LBB2_4:
	s_or_b32 exec_lo, exec_lo, s25
	s_waitcnt lgkmcnt(0)
	s_setpc_b64 s[30:31]
.Lfunc_end2:
	.size	_Z12cubic_interpRdS_dddddddd, .Lfunc_end2-_Z12cubic_interpRdS_dddddddd
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Function info:
; codeLenInByte = 8892
; NumSgprs: 34
; NumVgprs: 130
; ScratchSize: 0
; MemoryBound: 0
	.text
	.protected	_Z20boundary_interpolatePdS_S_S_S_S_PKdS1_S1_S1_S1_S1_S1_iiidddi ; -- Begin function _Z20boundary_interpolatePdS_S_S_S_S_PKdS1_S1_S1_S1_S1_S1_iiidddi
	.globl	_Z20boundary_interpolatePdS_S_S_S_S_PKdS1_S1_S1_S1_S1_S1_iiidddi
	.p2align	8
	.type	_Z20boundary_interpolatePdS_S_S_S_S_PKdS1_S1_S1_S1_S1_S1_iiidddi,@function
_Z20boundary_interpolatePdS_S_S_S_S_PKdS1_S1_S1_S1_S1_S1_iiidddi: ; @_Z20boundary_interpolatePdS_S_S_S_S_PKdS1_S1_S1_S1_S1_S1_iiidddi
; %bb.0:
	s_clause 0x1
	s_load_b64 s[2:3], s[0:1], 0xa4
	s_load_b128 s[56:59], s[0:1], 0x68
	v_and_b32_e32 v1, 0x3ff, v0
	v_bfe_u32 v2, v0, 10, 10
	v_bfe_u32 v3, v0, 20, 10
	s_mov_b32 s32, 0
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s4, s2, 16
	s_and_b32 s2, s2, 0xffff
	s_and_b32 s3, s3, 0xffff
	v_mad_u64_u32 v[58:59], null, s13, s2, v[1:2]
	v_mad_u64_u32 v[0:1], null, s14, s4, v[2:3]
	v_mad_u64_u32 v[40:41], null, s15, s3, v[3:4]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_gt_i32_e32 vcc_lo, s56, v58
	v_cmp_gt_i32_e64 s2, s57, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_i32_e64 s3, s58, v40
	s_and_b32 s2, vcc_lo, s2
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, s2, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB3_2
; %bb.1:
	v_cvt_f64_i32_e32 v[1:2], v40
	s_add_i32 s2, s58, -1
	v_add_nc_u32_e32 v11, -1, v0
	v_add_nc_u32_e32 v13, -2, v0
	v_cvt_f64_i32_e32 v[5:6], v0
	v_cvt_f64_i32_e32 v[41:42], s2
	v_add_nc_u32_e32 v7, 1, v0
	s_clause 0x1
	s_load_b512 s[36:51], s[0:1], 0x0
	s_load_b128 s[60:63], s[0:1], 0x78
	v_add_nc_u32_e32 v9, 2, v0
	v_cvt_f64_i32_e32 v[3:4], v58
	v_cvt_f64_i32_e32 v[11:12], v11
	v_cvt_f64_i32_e32 v[13:14], v13
	s_add_i32 s3, s57, -1
	v_cvt_f64_i32_e32 v[9:10], v9
	v_cvt_f64_i32_e32 v[15:16], s3
	s_add_i32 s2, s56, -1
	s_load_b64 s[34:35], s[0:1], 0x60
	v_cvt_f64_i32_e32 v[59:60], s2
	s_getpc_b64 s[58:59]
	s_add_u32 s58, s58, _Z12cubic_interpRdS_dddddddd@rel32@lo+4
	s_addc_u32 s59, s59, _Z12cubic_interpRdS_dddddddd@rel32@hi+12
	v_max_f64 v[0:1], v[1:2], 0
	v_max_f64 v[2:3], v[3:4], 0
	v_max_f64 v[4:5], v[5:6], 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_gt_f64_e32 vcc_lo, v[0:1], v[41:42]
	v_cmp_gt_f64_e64 s2, v[2:3], v[59:60]
	s_delay_alu instid0(VALU_DEP_3)
	v_cmp_gt_f64_e64 s3, v[4:5], v[15:16]
	v_cndmask_b32_e32 v0, v0, v41, vcc_lo
	v_cvt_f64_i32_e32 v[7:8], v7
	v_cndmask_b32_e32 v1, v1, v42, vcc_lo
	v_cndmask_b32_e64 v3, v3, v60, s2
	v_cndmask_b32_e64 v5, v5, v16, s3
	v_cndmask_b32_e64 v4, v4, v15, s3
	v_cndmask_b32_e64 v2, v2, v59, s2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_i32_f64_e32 v45, v[4:5]
	v_cvt_i32_f64_e32 v46, v[2:3]
	v_max_f64 v[6:7], v[7:8], 0
	v_max_f64 v[8:9], v[9:10], 0
	v_max_f64 v[10:11], v[11:12], 0
	v_max_f64 v[12:13], v[13:14], 0
	v_cvt_i32_f64_e32 v14, v[0:1]
	v_cmp_gt_f64_e64 s4, v[6:7], v[15:16]
	v_cmp_gt_f64_e64 s5, v[8:9], v[15:16]
	v_cmp_gt_f64_e64 s6, v[10:11], v[15:16]
	v_cmp_gt_f64_e64 s7, v[12:13], v[15:16]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v7, v7, v16, s4
	v_cndmask_b32_e64 v6, v6, v15, s4
	v_cndmask_b32_e64 v11, v11, v16, s6
	s_delay_alu instid0(VALU_DEP_4)
	v_cndmask_b32_e64 v1, v13, v16, s7
	v_cndmask_b32_e64 v0, v12, v15, s7
	v_cndmask_b32_e64 v10, v10, v15, s6
	v_cndmask_b32_e64 v9, v9, v16, s5
	v_cndmask_b32_e64 v8, v8, v15, s5
	v_cvt_i32_f64_e32 v4, v[6:7]
	v_cvt_i32_f64_e32 v0, v[0:1]
	v_cvt_i32_f64_e32 v6, v[10:11]
	v_mul_lo_u32 v1, v14, s57
	v_cvt_i32_f64_e32 v5, v[8:9]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v2, v1, v45
	v_mul_lo_u32 v47, v2, s56
	v_add_nc_u32_e32 v3, v1, v4
	v_add_nc_u32_e32 v4, v1, v0
	v_add_nc_u32_e32 v6, v1, v6
	v_add_nc_u32_e32 v8, v1, v5
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mad_u64_u32 v[0:1], null, v3, s56, v[46:47]
	v_mad_u64_u32 v[2:3], null, v4, s56, v[46:47]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mad_u64_u32 v[4:5], null, v6, s56, v[46:47]
	v_mad_u64_u32 v[6:7], null, v8, s56, v[46:47]
	v_add_nc_u32_e32 v8, v47, v46
	v_ashrrev_i32_e32 v1, 31, v0
	v_ashrrev_i32_e32 v3, 31, v2
	v_ashrrev_i32_e32 v5, 31, v4
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_ashrrev_i32_e32 v9, 31, v8
	v_ashrrev_i32_e32 v7, 31, v6
	v_lshlrev_b64 v[2:3], 3, v[2:3]
	v_lshlrev_b64 v[0:1], 3, v[0:1]
	v_lshlrev_b64 v[4:5], 3, v[4:5]
	v_lshlrev_b64 v[43:44], 3, v[8:9]
	v_lshlrev_b64 v[6:7], 3, v[6:7]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v2, vcc_lo, s34, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s35, v3, vcc_lo
	v_add_co_u32 v4, vcc_lo, s34, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s35, v5, vcc_lo
	v_add_co_u32 v6, vcc_lo, s34, v6
	v_add_co_ci_u32_e32 v7, vcc_lo, s35, v7, vcc_lo
	v_add_co_u32 v8, vcc_lo, s48, v43
	v_add_co_ci_u32_e32 v9, vcc_lo, s49, v44, vcc_lo
	v_add_co_u32 v14, vcc_lo, s50, v43
	v_add_co_ci_u32_e32 v15, vcc_lo, s51, v44, vcc_lo
	v_add_co_u32 v56, vcc_lo, s34, v43
	v_add_co_ci_u32_e32 v57, vcc_lo, s35, v44, vcc_lo
	v_add_co_u32 v0, vcc_lo, s34, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s35, v1, vcc_lo
	s_clause 0x2
	global_load_b64 v[10:11], v[2:3], off
	global_load_b64 v[12:13], v[4:5], off
	global_load_b64 v[18:19], v[6:7], off
	global_load_b64 v[4:5], v[8:9], off
	v_mov_b32_e32 v9, s61
	global_load_b64 v[6:7], v[14:15], off
	s_clause 0x1
	global_load_b64 v[14:15], v[56:57], off
	global_load_b64 v[16:17], v[0:1], off
	s_clause 0x1
	s_load_b256 s[48:55], s[0:1], 0x40
	s_load_b64 s[64:65], s[0:1], 0x88
	v_add_co_u32 v0, vcc_lo, s36, v43
	v_add_co_ci_u32_e32 v1, vcc_lo, s37, v44, vcc_lo
	v_add_co_u32 v2, vcc_lo, s38, v43
	v_add_co_ci_u32_e32 v3, vcc_lo, s39, v44, vcc_lo
	v_mov_b32_e32 v8, s60
	s_swappc_b64 s[30:31], s[58:59]
	v_add_nc_u32_e32 v0, -2, v58
	v_add_nc_u32_e32 v2, -1, v58
	v_add_nc_u32_e32 v4, 1, v58
	v_add_nc_u32_e32 v6, 2, v58
	global_load_b64 v[14:15], v[56:57], off
	v_cvt_f64_i32_e32 v[0:1], v0
	v_cvt_f64_i32_e32 v[2:3], v2
	v_cvt_f64_i32_e32 v[4:5], v4
	v_cvt_f64_i32_e32 v[6:7], v6
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_max_f64 v[0:1], v[0:1], 0
	v_max_f64 v[2:3], v[2:3], 0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_max_f64 v[4:5], v[4:5], 0
	v_max_f64 v[6:7], v[6:7], 0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cmp_gt_f64_e32 vcc_lo, v[0:1], v[59:60]
	v_cmp_gt_f64_e64 s0, v[2:3], v[59:60]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cmp_gt_f64_e64 s1, v[4:5], v[59:60]
	v_cmp_gt_f64_e64 s2, v[6:7], v[59:60]
	v_dual_cndmask_b32 v1, v1, v60 :: v_dual_cndmask_b32 v0, v0, v59
	s_delay_alu instid0(VALU_DEP_4)
	v_cndmask_b32_e64 v3, v3, v60, s0
	v_cndmask_b32_e64 v2, v2, v59, s0
	v_cndmask_b32_e64 v5, v5, v60, s1
	v_cndmask_b32_e64 v4, v4, v59, s1
	v_cvt_i32_f64_e32 v8, v[0:1]
	v_cndmask_b32_e64 v7, v7, v60, s2
	v_cvt_i32_f64_e32 v9, v[2:3]
	v_cndmask_b32_e64 v6, v6, v59, s2
	v_cvt_i32_f64_e32 v4, v[4:5]
	v_add_co_u32 v0, vcc_lo, s48, v43
	v_add_co_ci_u32_e32 v1, vcc_lo, s49, v44, vcc_lo
	s_delay_alu instid0(VALU_DEP_4)
	v_cvt_i32_f64_e32 v5, v[6:7]
	v_add_co_u32 v2, vcc_lo, s50, v43
	v_add_co_ci_u32_e32 v3, vcc_lo, s51, v44, vcc_lo
	v_add_nc_u32_e32 v6, v47, v8
	v_add_nc_u32_e32 v8, v47, v9
	v_add_nc_u32_e32 v10, v47, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_ashrrev_i32_e32 v7, 31, v6
	v_ashrrev_i32_e32 v9, 31, v8
	v_add_nc_u32_e32 v12, v47, v5
	global_load_b64 v[4:5], v[0:1], off
	v_lshlrev_b64 v[0:1], 3, v[6:7]
	v_ashrrev_i32_e32 v11, 31, v10
	global_load_b64 v[6:7], v[2:3], off
	v_lshlrev_b64 v[2:3], 3, v[8:9]
	v_ashrrev_i32_e32 v13, 31, v12
	v_lshlrev_b64 v[8:9], 3, v[10:11]
	v_add_co_u32 v0, vcc_lo, s34, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s35, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_4)
	v_lshlrev_b64 v[12:13], 3, v[12:13]
	v_add_co_u32 v2, vcc_lo, s34, v2
	global_load_b64 v[10:11], v[0:1], off
	v_add_co_ci_u32_e32 v3, vcc_lo, s35, v3, vcc_lo
	v_add_co_u32 v8, vcc_lo, s34, v8
	v_add_co_ci_u32_e32 v9, vcc_lo, s35, v9, vcc_lo
	v_add_co_u32 v0, vcc_lo, s34, v12
	v_add_co_ci_u32_e32 v1, vcc_lo, s35, v13, vcc_lo
	s_clause 0x2
	global_load_b64 v[12:13], v[2:3], off
	global_load_b64 v[16:17], v[8:9], off
	global_load_b64 v[18:19], v[0:1], off
	v_add_co_u32 v0, vcc_lo, s40, v43
	v_add_co_ci_u32_e32 v1, vcc_lo, s41, v44, vcc_lo
	v_add_co_u32 v2, vcc_lo, s42, v43
	v_add_co_ci_u32_e32 v3, vcc_lo, s43, v44, vcc_lo
	v_dual_mov_b32 v8, s62 :: v_dual_mov_b32 v9, s63
	s_swappc_b64 s[30:31], s[58:59]
	v_add_nc_u32_e32 v0, 1, v40
	v_add_nc_u32_e32 v2, 2, v40
	v_add_nc_u32_e32 v4, -2, v40
	v_add_nc_u32_e32 v6, -1, v40
	global_load_b64 v[14:15], v[56:57], off
	v_cvt_f64_i32_e32 v[0:1], v0
	v_cvt_f64_i32_e32 v[2:3], v2
	v_cvt_f64_i32_e32 v[4:5], v4
	v_cvt_f64_i32_e32 v[6:7], v6
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_max_f64 v[0:1], v[0:1], 0
	v_max_f64 v[2:3], v[2:3], 0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_max_f64 v[4:5], v[4:5], 0
	v_max_f64 v[6:7], v[6:7], 0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cmp_gt_f64_e32 vcc_lo, v[0:1], v[41:42]
	v_cmp_gt_f64_e64 s0, v[2:3], v[41:42]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cmp_gt_f64_e64 s1, v[4:5], v[41:42]
	v_cmp_gt_f64_e64 s2, v[6:7], v[41:42]
	v_dual_cndmask_b32 v1, v1, v42 :: v_dual_cndmask_b32 v0, v0, v41
	s_delay_alu instid0(VALU_DEP_4)
	v_cndmask_b32_e64 v3, v3, v42, s0
	v_cndmask_b32_e64 v2, v2, v41, s0
	v_cndmask_b32_e64 v5, v5, v42, s1
	v_cndmask_b32_e64 v4, v4, v41, s1
	v_cndmask_b32_e64 v7, v7, v42, s2
	v_cvt_i32_f64_e32 v8, v[0:1]
	v_cndmask_b32_e64 v6, v6, v41, s2
	v_cvt_i32_f64_e32 v9, v[2:3]
	v_cvt_i32_f64_e32 v10, v[4:5]
	v_add_co_u32 v0, vcc_lo, s52, v43
	s_delay_alu instid0(VALU_DEP_4)
	v_cvt_i32_f64_e32 v7, v[6:7]
	v_add_co_ci_u32_e32 v1, vcc_lo, s53, v44, vcc_lo
	v_mad_u64_u32 v[2:3], null, v8, s57, v[45:46]
	v_mad_u64_u32 v[3:4], null, v9, s57, v[45:46]
	v_mad_u64_u32 v[4:5], null, v10, s57, v[45:46]
	v_mad_u64_u32 v[5:6], null, v7, s57, v[45:46]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mad_u64_u32 v[8:9], null, v2, s56, v[46:47]
	v_mad_u64_u32 v[10:11], null, v3, s56, v[46:47]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mad_u64_u32 v[2:3], null, v4, s56, v[46:47]
	v_mad_u64_u32 v[12:13], null, v5, s56, v[46:47]
	global_load_b64 v[4:5], v[0:1], off
	v_ashrrev_i32_e32 v9, 31, v8
	v_add_co_u32 v6, vcc_lo, s54, v43
	v_ashrrev_i32_e32 v3, 31, v2
	v_ashrrev_i32_e32 v11, 31, v10
	v_ashrrev_i32_e32 v13, 31, v12
	v_add_co_ci_u32_e32 v7, vcc_lo, s55, v44, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_lshlrev_b64 v[0:1], 3, v[2:3]
	v_lshlrev_b64 v[8:9], 3, v[8:9]
	v_lshlrev_b64 v[2:3], 3, v[12:13]
	v_lshlrev_b64 v[12:13], 3, v[10:11]
	global_load_b64 v[6:7], v[6:7], off
	v_add_co_u32 v0, vcc_lo, s34, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s35, v1, vcc_lo
	v_add_co_u32 v2, vcc_lo, s34, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s35, v3, vcc_lo
	v_add_co_u32 v8, vcc_lo, s34, v8
	v_add_co_ci_u32_e32 v9, vcc_lo, s35, v9, vcc_lo
	global_load_b64 v[10:11], v[0:1], off
	v_add_co_u32 v0, vcc_lo, s34, v12
	v_add_co_ci_u32_e32 v1, vcc_lo, s35, v13, vcc_lo
	s_clause 0x2
	global_load_b64 v[12:13], v[2:3], off
	global_load_b64 v[16:17], v[8:9], off
	global_load_b64 v[18:19], v[0:1], off
	v_mov_b32_e32 v9, s65
	v_add_co_u32 v0, vcc_lo, s44, v43
	v_add_co_ci_u32_e32 v1, vcc_lo, s45, v44, vcc_lo
	v_add_co_u32 v2, vcc_lo, s46, v43
	v_add_co_ci_u32_e32 v3, vcc_lo, s47, v44, vcc_lo
	v_mov_b32_e32 v8, s64
	s_swappc_b64 s[30:31], s[58:59]
.LBB3_2:
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z20boundary_interpolatePdS_S_S_S_S_PKdS1_S1_S1_S1_S1_S1_iiidddi
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 408
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 130
		.amdhsa_next_free_sgpr 66
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end3:
	.size	_Z20boundary_interpolatePdS_S_S_S_S_PKdS1_S1_S1_S1_S1_S1_iiidddi, .Lfunc_end3-_Z20boundary_interpolatePdS_S_S_S_S_PKdS1_S1_S1_S1_S1_S1_iiidddi
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1792
; NumSgprs: 68
; NumVgprs: 130
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 8
; VGPRBlocks: 16
; NumSGPRsForWavesPerEU: 68
; NumVGPRsForWavesPerEU: 130
; Occupancy: 10
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.text
	.protected	_Z11extend_stepPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi ; -- Begin function _Z11extend_stepPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi
	.globl	_Z11extend_stepPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi
	.p2align	8
	.type	_Z11extend_stepPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi,@function
_Z11extend_stepPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi: ; @_Z11extend_stepPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi
; %bb.0:
	s_mov_b64 s[62:63], s[0:1]
	s_load_b64 s[0:1], s[0:1], 0xcc
	s_load_b128 s[96:99], s[62:63], 0x90
	v_and_b32_e32 v1, 0x3ff, v0
	v_bfe_u32 v2, v0, 10, 10
	v_bfe_u32 v3, v0, 20, 10
	s_mov_b32 s32, 0
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s2, s0, 16
	s_and_b32 s0, s0, 0xffff
	s_and_b32 s1, s1, 0xffff
	v_mad_u64_u32 v[56:57], null, s13, s0, v[1:2]
	v_mad_u64_u32 v[0:1], null, s14, s2, v[2:3]
	v_mad_u64_u32 v[62:63], null, s15, s1, v[3:4]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_gt_i32_e32 vcc_lo, s96, v56
	v_cmp_gt_i32_e64 s0, s97, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_i32_e64 s1, s98, v62
	s_and_b32 s0, vcc_lo, s0
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, s0, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB4_32
; %bb.1:
	v_cvt_f64_i32_e32 v[1:2], v62
	s_add_i32 s0, s98, -1
	v_cvt_f64_i32_e32 v[3:4], v0
	v_add_nc_u32_e32 v7, 2, v0
	v_add_nc_u32_e32 v9, 3, v0
	v_add_nc_u32_e32 v11, -1, v0
	v_add_nc_u32_e32 v13, -2, v0
	v_cvt_f64_i32_e32 v[67:68], s0
	v_add_nc_u32_e32 v5, 1, v0
	v_add_nc_u32_e32 v0, -3, v0
	v_cvt_f64_i32_e32 v[7:8], v7
	v_cvt_f64_i32_e32 v[9:10], v9
	v_cvt_f64_i32_e32 v[11:12], v11
	v_cvt_f64_i32_e32 v[13:14], v13
	v_cvt_f64_i32_e32 v[15:16], v0
	v_cvt_f64_i32_e32 v[17:18], v56
	s_add_i32 s1, s97, -1
	s_add_i32 s0, s96, -1
	v_cvt_f64_i32_e32 v[19:20], s1
	v_cvt_f64_i32_e32 v[57:58], s0
	s_clause 0x2
	s_load_b512 s[68:83], s[62:63], 0x0
	s_load_b128 s[100:103], s[62:63], 0xa0
	s_load_b64 s[66:67], s[62:63], 0xb0
                                        ; implicit-def: $vgpr43_vgpr44
                                        ; implicit-def: $vgpr41_vgpr42
	v_max_f64 v[0:1], v[1:2], 0
	v_max_f64 v[2:3], v[3:4], 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_f64_e32 vcc_lo, v[0:1], v[67:68]
	v_cmp_gt_f64_e64 s0, v[2:3], v[19:20]
	v_cndmask_b32_e32 v0, v0, v67, vcc_lo
	v_cvt_f64_i32_e32 v[5:6], v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v3, v3, v20, s0
	v_cndmask_b32_e64 v2, v2, v19, s0
	v_cvt_i32_f64_e32 v63, v[2:3]
	s_delay_alu instid0(VALU_DEP_4)
	v_max_f64 v[4:5], v[5:6], 0
	v_max_f64 v[6:7], v[7:8], 0
	v_max_f64 v[8:9], v[9:10], 0
	v_max_f64 v[10:11], v[11:12], 0
	v_max_f64 v[12:13], v[13:14], 0
	v_max_f64 v[14:15], v[15:16], 0
	v_max_f64 v[16:17], v[17:18], 0
	v_cmp_gt_f64_e64 s1, v[4:5], v[19:20]
	v_cmp_gt_f64_e64 s2, v[6:7], v[19:20]
	v_cmp_gt_f64_e64 s3, v[8:9], v[19:20]
	v_cmp_gt_f64_e64 s4, v[10:11], v[19:20]
	v_cmp_gt_f64_e64 s5, v[12:13], v[19:20]
	v_cmp_gt_f64_e64 s6, v[14:15], v[19:20]
	v_cmp_gt_f64_e64 s7, v[16:17], v[57:58]
	v_cndmask_b32_e64 v5, v5, v20, s1
	v_cndmask_b32_e64 v4, v4, v19, s1
	v_cndmask_b32_e64 v7, v7, v20, s2
	v_cndmask_b32_e64 v11, v11, v20, s4
	v_cndmask_b32_e64 v10, v10, v19, s4
	v_cndmask_b32_e64 v9, v9, v20, s3
	v_cvt_i32_f64_e32 v2, v[4:5]
	v_cndmask_b32_e32 v1, v1, v68, vcc_lo
	v_cndmask_b32_e64 v17, v17, v58, s7
	v_cndmask_b32_e64 v16, v16, v57, s7
	v_cndmask_b32_e64 v6, v6, v19, s2
	v_cndmask_b32_e64 v8, v8, v19, s3
	v_cvt_i32_f64_e32 v18, v[0:1]
	v_cndmask_b32_e64 v1, v13, v20, s5
	v_cndmask_b32_e64 v13, v15, v20, s6
	v_cndmask_b32_e64 v0, v12, v19, s5
	v_cndmask_b32_e64 v12, v14, v19, s6
	v_cvt_i32_f64_e32 v5, v[10:11]
	v_cvt_i32_f64_e32 v66, v[16:17]
	v_cvt_i32_f64_e32 v3, v[6:7]
	v_cvt_i32_f64_e32 v0, v[0:1]
	v_cvt_i32_f64_e32 v1, v[12:13]
	v_cvt_i32_f64_e32 v4, v[8:9]
	v_mul_lo_u32 v6, v18, s97
	s_delay_alu instid0(VALU_DEP_1)
	v_add_nc_u32_e32 v8, v6, v2
	v_add_nc_u32_e32 v7, v6, v63
	v_add_nc_u32_e32 v10, v6, v0
	v_add_nc_u32_e32 v1, v6, v1
	v_add_nc_u32_e32 v12, v6, v3
	v_add_nc_u32_e32 v14, v6, v4
	v_mul_lo_u32 v47, v7, s96
	v_add_nc_u32_e32 v7, v6, v5
	v_mad_u64_u32 v[2:3], null, v8, s96, v[66:67]
	v_mad_u64_u32 v[8:9], null, v10, s96, v[66:67]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[4:5], null, v7, s96, v[66:67]
	v_add_nc_u32_e32 v0, v47, v66
	v_mad_u64_u32 v[6:7], null, v1, s96, v[66:67]
	v_mad_u64_u32 v[10:11], null, v12, s96, v[66:67]
	v_ashrrev_i32_e32 v1, 31, v0
	v_mad_u64_u32 v[12:13], null, v14, s96, v[66:67]
	v_ashrrev_i32_e32 v9, 31, v8
	v_ashrrev_i32_e32 v7, 31, v6
	s_delay_alu instid0(VALU_DEP_4)
	v_lshlrev_b64 v[64:65], 3, v[0:1]
	v_ashrrev_i32_e32 v3, 31, v2
	v_ashrrev_i32_e32 v11, 31, v10
	v_lshlrev_b64 v[8:9], 3, v[8:9]
	v_lshlrev_b64 v[6:7], 3, v[6:7]
	v_ashrrev_i32_e32 v13, 31, v12
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v0, vcc_lo, s80, v64
	v_add_co_ci_u32_e32 v1, vcc_lo, s81, v65, vcc_lo
	v_add_co_u32 v14, vcc_lo, s82, v64
	v_add_co_ci_u32_e32 v15, vcc_lo, s83, v65, vcc_lo
	global_load_b64 v[0:1], v[0:1], off
	global_load_b64 v[22:23], v[14:15], off
	v_lshlrev_b64 v[2:3], 3, v[2:3]
	v_add_co_u32 v16, vcc_lo, s72, v6
	v_add_co_ci_u32_e32 v17, vcc_lo, s73, v7, vcc_lo
	v_lshlrev_b64 v[10:11], 3, v[10:11]
	v_add_co_u32 v18, vcc_lo, s72, v8
	v_add_co_ci_u32_e32 v19, vcc_lo, s73, v9, vcc_lo
	v_lshlrev_b64 v[12:13], 3, v[12:13]
	v_add_co_u32 v2, vcc_lo, s72, v2
	v_ashrrev_i32_e32 v5, 31, v4
	v_add_co_ci_u32_e32 v3, vcc_lo, s73, v3, vcc_lo
	v_add_co_u32 v8, vcc_lo, s72, v10
	v_add_co_ci_u32_e32 v9, vcc_lo, s73, v11, vcc_lo
	s_delay_alu instid0(VALU_DEP_4)
	v_lshlrev_b64 v[4:5], 3, v[4:5]
	v_add_co_u32 v10, vcc_lo, s72, v12
	v_add_co_ci_u32_e32 v11, vcc_lo, s73, v13, vcc_lo
	v_add_co_u32 v12, vcc_lo, s72, v64
	v_add_co_ci_u32_e32 v13, vcc_lo, s73, v65, vcc_lo
	v_add_co_u32 v4, vcc_lo, s72, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s73, v5, vcc_lo
	s_clause 0x6
	global_load_b64 v[6:7], v[2:3], off
	global_load_b64 v[14:15], v[8:9], off
	global_load_b64 v[8:9], v[10:11], off
	global_load_b64 v[60:61], v[12:13], off
	global_load_b64 v[16:17], v[16:17], off
	global_load_b64 v[20:21], v[18:19], off
	global_load_b64 v[18:19], v[4:5], off
	s_waitcnt vmcnt(8)
	v_cmp_ngt_f64_e64 s64, s[100:101], v[0:1]
	s_waitcnt vmcnt(7)
	v_cmp_ngt_f64_e64 s33, s[100:101], v[22:23]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, s64, s33
	s_and_saveexec_b32 s1, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s65, exec_lo, s1
	s_cbranch_execz .LBB4_3
; %bb.2:
	s_waitcnt vmcnt(1)
	v_add_f64 v[0:1], v[20:21], -v[16:17]
	s_waitcnt vmcnt(0)
	v_add_f64 v[2:3], v[18:19], -v[20:21]
	v_add_f64 v[4:5], v[60:61], -v[18:19]
	v_add_f64 v[10:11], v[6:7], -v[60:61]
	v_add_f64 v[6:7], v[14:15], -v[6:7]
	v_add_f64 v[8:9], v[8:9], -v[14:15]
	s_getpc_b64 s[80:81]
	s_add_u32 s80, s80, _Z24weno_onesided_derivativeddddd@rel32@lo+4
	s_addc_u32 s81, s81, _Z24weno_onesided_derivativeddddd@rel32@hi+12
	v_div_scale_f64 v[12:13], null, s[100:101], s[100:101], v[0:1]
	v_div_scale_f64 v[14:15], null, s[100:101], s[100:101], v[2:3]
	v_div_scale_f64 v[16:17], null, s[100:101], s[100:101], v[4:5]
	v_div_scale_f64 v[18:19], null, s[100:101], s[100:101], v[10:11]
	v_div_scale_f64 v[20:21], null, s[100:101], s[100:101], v[6:7]
	v_div_scale_f64 v[22:23], null, s[100:101], s[100:101], v[8:9]
	v_div_scale_f64 v[50:51], vcc_lo, v[0:1], s[100:101], v[0:1]
	v_rcp_f64_e32 v[24:25], v[12:13]
	v_rcp_f64_e32 v[26:27], v[14:15]
	v_rcp_f64_e32 v[28:29], v[16:17]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_rcp_f64_e32 v[30:31], v[18:19]
	v_rcp_f64_e32 v[32:33], v[20:21]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(TRANS32_DEP_3)
	v_rcp_f64_e32 v[34:35], v[22:23]
	v_fma_f64 v[36:37], -v[12:13], v[24:25], 1.0
	v_fma_f64 v[38:39], -v[14:15], v[26:27], 1.0
	v_fma_f64 v[40:41], -v[16:17], v[28:29], 1.0
	v_fma_f64 v[42:43], -v[18:19], v[30:31], 1.0
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[44:45], -v[20:21], v[32:33], 1.0
	v_fma_f64 v[48:49], -v[22:23], v[34:35], 1.0
	v_fma_f64 v[24:25], v[24:25], v[36:37], v[24:25]
	v_fma_f64 v[26:27], v[26:27], v[38:39], v[26:27]
	v_fma_f64 v[28:29], v[28:29], v[40:41], v[28:29]
	v_fma_f64 v[30:31], v[30:31], v[42:43], v[30:31]
	v_fma_f64 v[32:33], v[32:33], v[44:45], v[32:33]
	v_fma_f64 v[34:35], v[34:35], v[48:49], v[34:35]
	v_fma_f64 v[36:37], -v[12:13], v[24:25], 1.0
	v_fma_f64 v[38:39], -v[14:15], v[26:27], 1.0
	v_fma_f64 v[40:41], -v[16:17], v[28:29], 1.0
	v_fma_f64 v[42:43], -v[18:19], v[30:31], 1.0
	v_fma_f64 v[44:45], -v[20:21], v[32:33], 1.0
	v_fma_f64 v[48:49], -v[22:23], v[34:35], 1.0
	v_fma_f64 v[24:25], v[24:25], v[36:37], v[24:25]
	v_div_scale_f64 v[36:37], s0, v[2:3], s[100:101], v[2:3]
	v_fma_f64 v[26:27], v[26:27], v[38:39], v[26:27]
	v_div_scale_f64 v[38:39], s1, v[4:5], s[100:101], v[4:5]
	v_fma_f64 v[28:29], v[28:29], v[40:41], v[28:29]
	v_div_scale_f64 v[40:41], s2, v[10:11], s[100:101], v[10:11]
	v_fma_f64 v[30:31], v[30:31], v[42:43], v[30:31]
	v_div_scale_f64 v[42:43], s3, v[6:7], s[100:101], v[6:7]
	v_fma_f64 v[32:33], v[32:33], v[44:45], v[32:33]
	v_fma_f64 v[34:35], v[34:35], v[48:49], v[34:35]
	v_div_scale_f64 v[44:45], s4, v[8:9], s[100:101], v[8:9]
	v_mul_f64 v[48:49], v[50:51], v[24:25]
	v_mul_f64 v[52:53], v[36:37], v[26:27]
	v_mul_f64 v[54:55], v[38:39], v[28:29]
	v_mul_f64 v[69:70], v[40:41], v[30:31]
	v_mul_f64 v[71:72], v[42:43], v[32:33]
	v_mul_f64 v[73:74], v[44:45], v[34:35]
	v_fma_f64 v[12:13], -v[12:13], v[48:49], v[50:51]
	v_fma_f64 v[14:15], -v[14:15], v[52:53], v[36:37]
	v_fma_f64 v[16:17], -v[16:17], v[54:55], v[38:39]
	v_fma_f64 v[18:19], -v[18:19], v[69:70], v[40:41]
	v_fma_f64 v[20:21], -v[20:21], v[71:72], v[42:43]
	v_fma_f64 v[22:23], -v[22:23], v[73:74], v[44:45]
	v_div_fmas_f64 v[12:13], v[12:13], v[24:25], v[48:49]
	s_mov_b32 vcc_lo, s0
	v_div_fmas_f64 v[14:15], v[14:15], v[26:27], v[52:53]
	s_mov_b32 vcc_lo, s1
	v_div_fmas_f64 v[16:17], v[16:17], v[28:29], v[54:55]
	s_mov_b32 vcc_lo, s2
	v_div_fmas_f64 v[18:19], v[18:19], v[30:31], v[69:70]
	s_mov_b32 vcc_lo, s3
	v_div_fmas_f64 v[20:21], v[20:21], v[32:33], v[71:72]
	s_mov_b32 vcc_lo, s4
	v_div_fmas_f64 v[22:23], v[22:23], v[34:35], v[73:74]
	v_div_fixup_f64 v[0:1], v[12:13], s[100:101], v[0:1]
	v_div_fixup_f64 v[43:44], v[14:15], s[100:101], v[2:3]
	v_div_fixup_f64 v[45:46], v[16:17], s[100:101], v[4:5]
	v_div_fixup_f64 v[50:51], v[18:19], s[100:101], v[10:11]
	v_div_fixup_f64 v[52:53], v[20:21], s[100:101], v[6:7]
	v_div_fixup_f64 v[54:55], v[22:23], s[100:101], v[8:9]
	v_dual_mov_b32 v2, v43 :: v_dual_mov_b32 v3, v44
	v_dual_mov_b32 v4, v45 :: v_dual_mov_b32 v5, v46
	v_dual_mov_b32 v6, v50 :: v_dual_mov_b32 v7, v51
	v_dual_mov_b32 v8, v52 :: v_dual_mov_b32 v9, v53
	s_swappc_b64 s[30:31], s[80:81]
	v_dual_mov_b32 v41, v0 :: v_dual_mov_b32 v42, v1
	v_dual_mov_b32 v0, v54 :: v_dual_mov_b32 v1, v55
	v_dual_mov_b32 v2, v52 :: v_dual_mov_b32 v3, v53
	v_dual_mov_b32 v4, v50 :: v_dual_mov_b32 v5, v51
	v_dual_mov_b32 v6, v45 :: v_dual_mov_b32 v7, v46
	v_dual_mov_b32 v8, v43 :: v_dual_mov_b32 v9, v44
	s_swappc_b64 s[30:31], s[80:81]
	v_dual_mov_b32 v43, v0 :: v_dual_mov_b32 v44, v1
                                        ; implicit-def: $vgpr18_vgpr19
                                        ; implicit-def: $vgpr20_vgpr21
                                        ; implicit-def: $vgpr16_vgpr17
                                        ; implicit-def: $vgpr22_vgpr23
                                        ; implicit-def: $vgpr0_vgpr1
                                        ; implicit-def: $vgpr6_vgpr7
                                        ; implicit-def: $vgpr14_vgpr15
                                        ; implicit-def: $vgpr8_vgpr9
.LBB4_3:                                ; %Flow458
	s_or_saveexec_b32 s5, s65
	s_load_b512 s[80:95], s[62:63], 0x40
	s_xor_b32 exec_lo, exec_lo, s5
	s_cbranch_execz .LBB4_11
; %bb.4:
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v2, vcc_lo, s90, v64
	v_add_co_ci_u32_e32 v3, vcc_lo, s91, v65, vcc_lo
	v_add_co_u32 v4, vcc_lo, s88, v64
	v_add_co_ci_u32_e32 v5, vcc_lo, s89, v65, vcc_lo
	global_load_b64 v[26:27], v[2:3], off
	global_load_b64 v[24:25], v[4:5], off
	v_add_f64 v[4:5], s[100:101], s[100:101]
	v_dual_mov_b32 v2, s100 :: v_dual_mov_b32 v3, s101
	s_and_saveexec_b32 s0, s64
	s_cbranch_execz .LBB4_6
; %bb.5:
	v_mul_f64 v[10:11], 0x40080000, s[100:101]
	v_dual_mov_b32 v0, s100 :: v_dual_mov_b32 v1, s101
	s_delay_alu instid0(VALU_DEP_4)
	v_dual_mov_b32 v2, v4 :: v_dual_mov_b32 v3, v5
	s_waitcnt vmcnt(0)
	v_dual_mov_b32 v25, v7 :: v_dual_mov_b32 v24, v6
	v_dual_mov_b32 v6, v14 :: v_dual_mov_b32 v7, v15
	v_dual_mov_b32 v15, v9 :: v_dual_mov_b32 v14, v8
	v_dual_mov_b32 v4, v10 :: v_dual_mov_b32 v5, v11
.LBB4_6:
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $vgpr8_vgpr9
                                        ; implicit-def: $sgpr0_sgpr1
                                        ; implicit-def: $sgpr2_sgpr3
	s_and_saveexec_b32 s4, s33
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s4, exec_lo, s4
	s_cbranch_execz .LBB4_8
; %bb.7:
	s_mov_b32 s2, 0
	s_waitcnt vmcnt(6)
	v_mul_f64 v[8:9], s[100:101], -2.0
	s_mov_b32 s3, 0xc0080000
	s_xor_b32 s1, s101, 0x80000000
	s_mov_b32 s0, s100
                                        ; implicit-def: $vgpr22_vgpr23
                                        ; implicit-def: $vgpr26_vgpr27
.LBB4_8:                                ; %Flow455
	s_or_saveexec_b32 s4, s4
	v_dual_mov_b32 v11, s3 :: v_dual_mov_b32 v10, s2
	v_dual_mov_b32 v13, s1 :: v_dual_mov_b32 v12, s0
	s_waitcnt vmcnt(2)
	v_dual_mov_b32 v31, v19 :: v_dual_mov_b32 v30, v18
	v_dual_mov_b32 v29, v21 :: v_dual_mov_b32 v28, v20
	s_xor_b32 exec_lo, exec_lo, s4
	s_cbranch_execz .LBB4_10
; %bb.9:
	v_xor_b32_e32 v23, 0x80000000, v23
	s_xor_b32 s1, s101, 0x80000000
	s_mov_b32 s0, s100
	v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v9, s1
	v_dual_mov_b32 v11, -2.0 :: v_dual_mov_b32 v8, s0
	v_dual_mov_b32 v12, v22 :: v_dual_mov_b32 v13, v23
	s_waitcnt vmcnt(1)
	v_dual_mov_b32 v31, v27 :: v_dual_mov_b32 v30, v26
	v_dual_mov_b32 v29, v19 :: v_dual_mov_b32 v28, v18
	v_dual_mov_b32 v16, v20 :: v_dual_mov_b32 v17, v21
.LBB4_10:                               ; %_Z14select_stencilRdS_S_S_S_S_S_S_S_S_S_S_S_S_dddddddddddddddd.exit.i
	s_or_b32 exec_lo, exec_lo, s4
	v_add_f64 v[14:15], v[14:15], -v[6:7]
	v_add_f64 v[18:19], v[4:5], -v[2:3]
	s_waitcnt vmcnt(0)
	v_add_f64 v[20:21], v[6:7], -v[24:25]
	v_add_f64 v[22:23], v[2:3], -v[0:1]
	v_add_f64 v[24:25], v[24:25], -v[60:61]
	v_add_f64 v[26:27], v[60:61], -v[30:31]
	v_add_f64 v[6:7], -v[12:13], 0
	v_add_f64 v[30:31], v[30:31], -v[28:29]
	v_add_f64 v[32:33], v[12:13], -v[8:9]
	v_add_f64 v[16:17], v[28:29], -v[16:17]
	v_fma_f64 v[28:29], -v[10:11], s[100:101], v[8:9]
	v_div_scale_f64 v[34:35], null, v[18:19], v[18:19], v[14:15]
	v_div_scale_f64 v[36:37], null, v[22:23], v[22:23], v[20:21]
	v_div_scale_f64 v[38:39], null, v[0:1], v[0:1], v[24:25]
	v_div_scale_f64 v[40:41], null, v[6:7], v[6:7], v[26:27]
	v_div_scale_f64 v[42:43], null, v[32:33], v[32:33], v[30:31]
	v_div_scale_f64 v[44:45], null, v[28:29], v[28:29], v[16:17]
	v_div_scale_f64 v[85:86], vcc_lo, v[14:15], v[18:19], v[14:15]
	v_rcp_f64_e32 v[48:49], v[34:35]
	v_rcp_f64_e32 v[50:51], v[36:37]
	v_rcp_f64_e32 v[52:53], v[38:39]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_rcp_f64_e32 v[54:55], v[40:41]
	v_rcp_f64_e32 v[69:70], v[42:43]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(TRANS32_DEP_3)
	v_rcp_f64_e32 v[71:72], v[44:45]
	v_fma_f64 v[73:74], -v[34:35], v[48:49], 1.0
	v_fma_f64 v[75:76], -v[36:37], v[50:51], 1.0
	v_fma_f64 v[77:78], -v[38:39], v[52:53], 1.0
	v_fma_f64 v[79:80], -v[40:41], v[54:55], 1.0
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[81:82], -v[42:43], v[69:70], 1.0
	v_fma_f64 v[83:84], -v[44:45], v[71:72], 1.0
	v_fma_f64 v[48:49], v[48:49], v[73:74], v[48:49]
	v_fma_f64 v[50:51], v[50:51], v[75:76], v[50:51]
	v_fma_f64 v[52:53], v[52:53], v[77:78], v[52:53]
	v_fma_f64 v[54:55], v[54:55], v[79:80], v[54:55]
	v_fma_f64 v[69:70], v[69:70], v[81:82], v[69:70]
	v_fma_f64 v[71:72], v[71:72], v[83:84], v[71:72]
	v_fma_f64 v[73:74], -v[34:35], v[48:49], 1.0
	v_fma_f64 v[75:76], -v[36:37], v[50:51], 1.0
	v_fma_f64 v[77:78], -v[38:39], v[52:53], 1.0
	v_fma_f64 v[79:80], -v[40:41], v[54:55], 1.0
	v_fma_f64 v[81:82], -v[42:43], v[69:70], 1.0
	v_fma_f64 v[83:84], -v[44:45], v[71:72], 1.0
	v_fma_f64 v[48:49], v[48:49], v[73:74], v[48:49]
	v_div_scale_f64 v[73:74], s0, v[20:21], v[22:23], v[20:21]
	v_fma_f64 v[50:51], v[50:51], v[75:76], v[50:51]
	v_div_scale_f64 v[75:76], s1, v[24:25], v[0:1], v[24:25]
	v_fma_f64 v[52:53], v[52:53], v[77:78], v[52:53]
	v_div_scale_f64 v[77:78], s2, v[26:27], v[6:7], v[26:27]
	v_fma_f64 v[54:55], v[54:55], v[79:80], v[54:55]
	v_div_scale_f64 v[79:80], s3, v[30:31], v[32:33], v[30:31]
	v_fma_f64 v[69:70], v[69:70], v[81:82], v[69:70]
	v_div_scale_f64 v[81:82], s4, v[16:17], v[28:29], v[16:17]
	v_fma_f64 v[71:72], v[71:72], v[83:84], v[71:72]
	v_mul_f64 v[83:84], v[85:86], v[48:49]
	v_mul_f64 v[87:88], v[73:74], v[50:51]
	v_mul_f64 v[89:90], v[75:76], v[52:53]
	v_mul_f64 v[91:92], v[77:78], v[54:55]
	v_mul_f64 v[93:94], v[79:80], v[69:70]
	v_mul_f64 v[95:96], v[81:82], v[71:72]
	v_fma_f64 v[34:35], -v[34:35], v[83:84], v[85:86]
	v_fma_f64 v[36:37], -v[36:37], v[87:88], v[73:74]
	v_fma_f64 v[38:39], -v[38:39], v[89:90], v[75:76]
	v_fma_f64 v[40:41], -v[40:41], v[91:92], v[77:78]
	v_fma_f64 v[42:43], -v[42:43], v[93:94], v[79:80]
	v_fma_f64 v[44:45], -v[44:45], v[95:96], v[81:82]
	v_div_fmas_f64 v[34:35], v[34:35], v[48:49], v[83:84]
	s_mov_b32 vcc_lo, s0
	v_div_fmas_f64 v[36:37], v[36:37], v[50:51], v[87:88]
	s_mov_b32 vcc_lo, s1
	v_div_fmas_f64 v[38:39], v[38:39], v[52:53], v[89:90]
	s_mov_b32 vcc_lo, s2
	v_div_fmas_f64 v[40:41], v[40:41], v[54:55], v[91:92]
	s_mov_b32 vcc_lo, s3
	v_div_fmas_f64 v[42:43], v[42:43], v[69:70], v[93:94]
	s_mov_b32 vcc_lo, s4
	v_div_fmas_f64 v[44:45], v[44:45], v[71:72], v[95:96]
	v_div_fixup_f64 v[14:15], v[34:35], v[18:19], v[14:15]
	v_div_fixup_f64 v[18:19], v[36:37], v[22:23], v[20:21]
	v_fma_f64 v[36:37], -v[10:11], s[100:101], v[12:13]
	v_fma_f64 v[10:11], -v[10:11], s[100:101], 0
	v_div_fixup_f64 v[20:21], v[38:39], v[0:1], v[24:25]
	v_div_fixup_f64 v[22:23], v[40:41], v[6:7], v[26:27]
	v_add_f64 v[26:27], v[4:5], -v[0:1]
	v_div_fixup_f64 v[24:25], v[42:43], v[32:33], v[30:31]
	v_add_f64 v[32:33], -v[8:9], 0
	v_add_f64 v[8:9], v[0:1], -v[8:9]
	v_div_fixup_f64 v[16:17], v[44:45], v[28:29], v[16:17]
	v_add_f64 v[28:29], v[0:1], -v[12:13]
	v_add_f64 v[12:13], v[2:3], -v[12:13]
	v_add_f64 v[0:1], -v[0:1], 0
	v_add_f64 v[14:15], v[14:15], -v[18:19]
	v_add_f64 v[18:19], v[18:19], -v[20:21]
	v_add_f64 v[30:31], v[20:21], -v[22:23]
	v_add_f64 v[34:35], v[22:23], -v[24:25]
	v_add_f64 v[16:17], v[24:25], -v[16:17]
	v_div_scale_f64 v[24:25], null, v[26:27], v[26:27], v[14:15]
	v_div_scale_f64 v[81:82], vcc_lo, v[14:15], v[26:27], v[14:15]
	v_div_scale_f64 v[38:39], null, v[2:3], v[2:3], v[18:19]
	v_div_scale_f64 v[40:41], null, v[28:29], v[28:29], v[30:31]
	v_div_scale_f64 v[42:43], null, v[32:33], v[32:33], v[34:35]
	v_div_scale_f64 v[44:45], null, v[36:37], v[36:37], v[16:17]
	v_rcp_f64_e32 v[48:49], v[24:25]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_rcp_f64_e32 v[50:51], v[38:39]
	v_rcp_f64_e32 v[52:53], v[40:41]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[54:55], v[42:43]
	v_rcp_f64_e32 v[69:70], v[44:45]
	v_fma_f64 v[71:72], -v[24:25], v[48:49], 1.0
	v_fma_f64 v[73:74], -v[38:39], v[50:51], 1.0
	s_delay_alu instid0(TRANS32_DEP_3)
	v_fma_f64 v[75:76], -v[40:41], v[52:53], 1.0
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[77:78], -v[42:43], v[54:55], 1.0
	v_fma_f64 v[79:80], -v[44:45], v[69:70], 1.0
	v_fma_f64 v[48:49], v[48:49], v[71:72], v[48:49]
	v_fma_f64 v[50:51], v[50:51], v[73:74], v[50:51]
	v_fma_f64 v[52:53], v[52:53], v[75:76], v[52:53]
	v_fma_f64 v[54:55], v[54:55], v[77:78], v[54:55]
	v_fma_f64 v[69:70], v[69:70], v[79:80], v[69:70]
	v_fma_f64 v[71:72], -v[24:25], v[48:49], 1.0
	v_fma_f64 v[73:74], -v[38:39], v[50:51], 1.0
	v_fma_f64 v[75:76], -v[40:41], v[52:53], 1.0
	v_fma_f64 v[77:78], -v[42:43], v[54:55], 1.0
	v_fma_f64 v[79:80], -v[44:45], v[69:70], 1.0
	v_fma_f64 v[48:49], v[48:49], v[71:72], v[48:49]
	v_div_scale_f64 v[71:72], s0, v[18:19], v[2:3], v[18:19]
	v_fma_f64 v[50:51], v[50:51], v[73:74], v[50:51]
	v_div_scale_f64 v[73:74], s1, v[30:31], v[28:29], v[30:31]
	v_fma_f64 v[52:53], v[52:53], v[75:76], v[52:53]
	v_div_scale_f64 v[75:76], s2, v[34:35], v[32:33], v[34:35]
	v_fma_f64 v[54:55], v[54:55], v[77:78], v[54:55]
	v_div_scale_f64 v[77:78], s3, v[16:17], v[36:37], v[16:17]
	v_fma_f64 v[69:70], v[69:70], v[79:80], v[69:70]
	v_mul_f64 v[79:80], v[81:82], v[48:49]
	v_mul_f64 v[83:84], v[71:72], v[50:51]
	v_mul_f64 v[85:86], v[73:74], v[52:53]
	v_mul_f64 v[87:88], v[75:76], v[54:55]
	v_mul_f64 v[89:90], v[77:78], v[69:70]
	v_fma_f64 v[24:25], -v[24:25], v[79:80], v[81:82]
	v_fma_f64 v[38:39], -v[38:39], v[83:84], v[71:72]
	v_fma_f64 v[40:41], -v[40:41], v[85:86], v[73:74]
	v_fma_f64 v[42:43], -v[42:43], v[87:88], v[75:76]
	v_fma_f64 v[44:45], -v[44:45], v[89:90], v[77:78]
	v_div_fmas_f64 v[24:25], v[24:25], v[48:49], v[79:80]
	s_mov_b32 vcc_lo, s0
	v_div_fmas_f64 v[38:39], v[38:39], v[50:51], v[83:84]
	s_mov_b32 vcc_lo, s1
	v_div_fmas_f64 v[40:41], v[40:41], v[52:53], v[85:86]
	s_mov_b32 vcc_lo, s2
	v_div_fmas_f64 v[42:43], v[42:43], v[54:55], v[87:88]
	s_mov_b32 vcc_lo, s3
	v_div_fmas_f64 v[44:45], v[44:45], v[69:70], v[89:90]
	v_div_fixup_f64 v[14:15], v[24:25], v[26:27], v[14:15]
	v_div_fixup_f64 v[18:19], v[38:39], v[2:3], v[18:19]
	v_add_f64 v[2:3], -v[2:3], 0
	v_div_fixup_f64 v[24:25], v[40:41], v[28:29], v[30:31]
	v_div_fixup_f64 v[26:27], v[42:43], v[32:33], v[34:35]
	v_div_fixup_f64 v[16:17], v[44:45], v[36:37], v[16:17]
	v_add_f64 v[14:15], v[14:15], -v[18:19]
	v_mul_f64 v[2:3], v[0:1], v[2:3]
	v_add_f64 v[28:29], v[18:19], -v[24:25]
	v_add_f64 v[30:31], v[24:25], -v[26:27]
	v_add_f64 v[16:17], v[26:27], -v[16:17]
	v_div_scale_f64 v[34:35], null, v[4:5], v[4:5], v[14:15]
	v_div_scale_f64 v[73:74], vcc_lo, v[14:15], v[4:5], v[14:15]
	v_div_scale_f64 v[36:37], null, v[12:13], v[12:13], v[28:29]
	v_div_scale_f64 v[38:39], null, v[8:9], v[8:9], v[30:31]
	v_div_scale_f64 v[40:41], null, v[10:11], v[10:11], v[16:17]
	v_rcp_f64_e32 v[42:43], v[34:35]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rcp_f64_e32 v[44:45], v[36:37]
	v_rcp_f64_e32 v[48:49], v[38:39]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(TRANS32_DEP_3)
	v_rcp_f64_e32 v[50:51], v[40:41]
	v_fma_f64 v[52:53], -v[34:35], v[42:43], 1.0
	v_fma_f64 v[54:55], -v[36:37], v[44:45], 1.0
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[69:70], -v[38:39], v[48:49], 1.0
	v_fma_f64 v[71:72], -v[40:41], v[50:51], 1.0
	v_fma_f64 v[42:43], v[42:43], v[52:53], v[42:43]
	v_fma_f64 v[44:45], v[44:45], v[54:55], v[44:45]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[48:49], v[48:49], v[69:70], v[48:49]
	v_fma_f64 v[50:51], v[50:51], v[71:72], v[50:51]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[52:53], -v[34:35], v[42:43], 1.0
	v_fma_f64 v[54:55], -v[36:37], v[44:45], 1.0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[69:70], -v[38:39], v[48:49], 1.0
	v_fma_f64 v[71:72], -v[40:41], v[50:51], 1.0
	s_delay_alu instid0(VALU_DEP_4)
	v_fma_f64 v[42:43], v[42:43], v[52:53], v[42:43]
	v_div_scale_f64 v[52:53], s0, v[28:29], v[12:13], v[28:29]
	v_fma_f64 v[44:45], v[44:45], v[54:55], v[44:45]
	v_div_scale_f64 v[54:55], s1, v[30:31], v[8:9], v[30:31]
	v_fma_f64 v[48:49], v[48:49], v[69:70], v[48:49]
	v_div_scale_f64 v[69:70], s2, v[16:17], v[10:11], v[16:17]
	v_fma_f64 v[50:51], v[50:51], v[71:72], v[50:51]
	v_mul_f64 v[71:72], v[73:74], v[42:43]
	v_mul_f64 v[75:76], v[52:53], v[44:45]
	v_mul_f64 v[77:78], v[54:55], v[48:49]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mul_f64 v[79:80], v[69:70], v[50:51]
	v_fma_f64 v[34:35], -v[34:35], v[71:72], v[73:74]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[36:37], -v[36:37], v[75:76], v[52:53]
	v_fma_f64 v[38:39], -v[38:39], v[77:78], v[54:55]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[40:41], -v[40:41], v[79:80], v[69:70]
	v_div_fmas_f64 v[34:35], v[34:35], v[42:43], v[71:72]
	s_mov_b32 vcc_lo, s0
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_div_fmas_f64 v[36:37], v[36:37], v[44:45], v[75:76]
	s_mov_b32 vcc_lo, s1
	v_div_fmas_f64 v[38:39], v[38:39], v[48:49], v[77:78]
	s_mov_b32 vcc_lo, s2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_div_fmas_f64 v[40:41], v[40:41], v[50:51], v[79:80]
	v_div_fixup_f64 v[4:5], v[34:35], v[4:5], v[14:15]
	v_mul_f64 v[14:15], v[0:1], v[6:7]
	v_div_fixup_f64 v[12:13], v[36:37], v[12:13], v[28:29]
	v_div_fixup_f64 v[8:9], v[38:39], v[8:9], v[30:31]
	v_div_fixup_f64 v[10:11], v[40:41], v[10:11], v[16:17]
	v_mul_f64 v[16:17], v[6:7], v[32:33]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cmp_lt_f64_e64 vcc_lo, |v[12:13]|, |v[4:5]|
	v_cmp_lt_f64_e64 s0, |v[8:9]|, |v[12:13]|
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_cmp_lt_f64_e64 s1, |v[8:9]|, |v[10:11]|
	v_dual_cndmask_b32 v5, v5, v13 :: v_dual_cndmask_b32 v4, v4, v12
	v_cmp_lt_f64_e64 vcc_lo, |v[24:25]|, |v[18:19]|
	v_cndmask_b32_e64 v13, v13, v9, s0
	v_cndmask_b32_e64 v12, v12, v8, s0
	v_cmp_lt_f64_e64 s0, |v[26:27]|, |v[24:25]|
	v_cndmask_b32_e64 v9, v11, v9, s1
	v_cndmask_b32_e64 v8, v10, v8, s1
	v_mul_f64 v[2:3], v[2:3], v[4:5]
	v_mul_f64 v[4:5], v[14:15], v[12:13]
	v_mul_f64 v[10:11], v[24:25], v[26:27]
	v_mul_f64 v[12:13], v[18:19], v[24:25]
	v_mul_f64 v[8:9], v[16:17], v[8:9]
	v_dual_cndmask_b32 v14, v19, v25 :: v_dual_cndmask_b32 v15, v18, v24
	v_dual_cndmask_b32 v3, v3, v5 :: v_dual_cndmask_b32 v2, v2, v4
	v_cmp_ngt_f64_e64 s1, 0, v[10:11]
	v_cmp_ngt_f64_e64 s2, 0, v[12:13]
	v_cndmask_b32_e64 v9, v5, v9, s0
	v_cndmask_b32_e64 v5, v25, v27, s0
	v_cndmask_b32_e64 v10, v24, v26, s0
	v_cndmask_b32_e64 v8, v4, v8, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v13, 0, v5, s1
	v_cndmask_b32_e64 v11, 0, v14, s2
	v_cndmask_b32_e64 v12, 0, v10, s1
	v_cndmask_b32_e64 v10, 0, v15, s2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[5:6], v[6:7], v[12:13], v[22:23]
	v_fma_f64 v[0:1], v[0:1], v[10:11], v[20:21]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[41:42], v[5:6], v[8:9]
	v_add_f64 v[43:44], v[0:1], v[2:3]
.LBB4_11:                               ; %Flow459
	s_or_b32 exec_lo, exec_lo, s5
	v_add_nc_u32_e32 v4, -3, v56
	s_waitcnt vmcnt(6)
	v_add_nc_u32_e32 v6, -2, v56
	s_waitcnt vmcnt(4)
	v_add_nc_u32_e32 v8, -1, v56
	v_add_nc_u32_e32 v0, 1, v56
	v_add_nc_u32_e32 v2, 2, v56
	v_cvt_f64_i32_e32 v[4:5], v4
	v_cvt_f64_i32_e32 v[6:7], v6
	v_cvt_f64_i32_e32 v[8:9], v8
	v_cvt_f64_i32_e32 v[0:1], v0
	v_add_nc_u32_e32 v10, 3, v56
	v_cvt_f64_i32_e32 v[2:3], v2
                                        ; implicit-def: $vgpr50_vgpr51
                                        ; implicit-def: $vgpr45_vgpr46
	s_delay_alu instid0(VALU_DEP_2)
	v_cvt_f64_i32_e32 v[10:11], v10
	v_max_f64 v[4:5], v[4:5], 0
	v_max_f64 v[6:7], v[6:7], 0
	v_max_f64 v[8:9], v[8:9], 0
	v_max_f64 v[0:1], v[0:1], 0
	v_max_f64 v[2:3], v[2:3], 0
	v_max_f64 v[10:11], v[10:11], 0
	v_cmp_gt_f64_e64 s1, v[4:5], v[57:58]
	v_cmp_gt_f64_e64 s2, v[6:7], v[57:58]
	v_cmp_gt_f64_e64 s3, v[8:9], v[57:58]
	v_cmp_gt_f64_e32 vcc_lo, v[0:1], v[57:58]
	v_cmp_gt_f64_e64 s0, v[2:3], v[57:58]
	v_cmp_gt_f64_e64 s4, v[10:11], v[57:58]
	v_cndmask_b32_e64 v5, v5, v58, s1
	v_cndmask_b32_e64 v4, v4, v57, s1
	v_cndmask_b32_e64 v7, v7, v58, s2
	v_cndmask_b32_e32 v1, v1, v58, vcc_lo
	v_cndmask_b32_e64 v6, v6, v57, s2
	v_cndmask_b32_e64 v9, v9, v58, s3
	v_cvt_i32_f64_e32 v4, v[4:5]
	v_cndmask_b32_e64 v8, v8, v57, s3
	v_cndmask_b32_e32 v0, v0, v57, vcc_lo
	v_cvt_i32_f64_e32 v5, v[6:7]
	v_cndmask_b32_e64 v3, v3, v58, s0
	v_cndmask_b32_e64 v2, v2, v57, s0
	v_cvt_i32_f64_e32 v7, v[8:9]
	v_cvt_i32_f64_e32 v12, v[0:1]
	v_cndmask_b32_e64 v11, v11, v58, s4
	v_cndmask_b32_e64 v10, v10, v57, s4
	v_cvt_i32_f64_e32 v9, v[2:3]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v0, vcc_lo, s80, v64
	v_add_co_ci_u32_e32 v1, vcc_lo, s81, v65, vcc_lo
	v_cvt_i32_f64_e32 v11, v[10:11]
	v_add_co_u32 v2, vcc_lo, s82, v64
	v_add_co_ci_u32_e32 v3, vcc_lo, s83, v65, vcc_lo
	global_load_b64 v[0:1], v[0:1], off
	global_load_b64 v[22:23], v[2:3], off
	v_add_nc_u32_e32 v4, v47, v4
	v_add_nc_u32_e32 v6, v47, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_ashrrev_i32_e32 v5, 31, v4
	v_add_nc_u32_e32 v8, v47, v7
	v_add_nc_u32_e32 v2, v47, v12
	v_ashrrev_i32_e32 v7, 31, v6
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_lshlrev_b64 v[4:5], 3, v[4:5]
	v_add_nc_u32_e32 v10, v47, v9
	v_ashrrev_i32_e32 v9, 31, v8
	v_lshlrev_b64 v[6:7], 3, v[6:7]
	v_ashrrev_i32_e32 v3, 31, v2
	v_add_nc_u32_e32 v12, v47, v11
	v_add_co_u32 v4, vcc_lo, s72, v4
	v_lshlrev_b64 v[8:9], 3, v[8:9]
	v_ashrrev_i32_e32 v11, 31, v10
	v_add_co_ci_u32_e32 v5, vcc_lo, s73, v5, vcc_lo
	v_lshlrev_b64 v[2:3], 3, v[2:3]
	v_add_co_u32 v6, vcc_lo, s72, v6
	v_ashrrev_i32_e32 v13, 31, v12
	v_add_co_ci_u32_e32 v7, vcc_lo, s73, v7, vcc_lo
	v_lshlrev_b64 v[10:11], 3, v[10:11]
	v_add_co_u32 v8, vcc_lo, s72, v8
	v_add_co_ci_u32_e32 v9, vcc_lo, s73, v9, vcc_lo
	v_lshlrev_b64 v[12:13], 3, v[12:13]
	v_add_co_u32 v2, vcc_lo, s72, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s73, v3, vcc_lo
	v_add_co_u32 v10, vcc_lo, s72, v10
	v_add_co_ci_u32_e32 v11, vcc_lo, s73, v11, vcc_lo
	v_add_co_u32 v12, vcc_lo, s72, v12
	v_add_co_ci_u32_e32 v13, vcc_lo, s73, v13, vcc_lo
	s_clause 0x5
	global_load_b64 v[16:17], v[4:5], off
	global_load_b64 v[20:21], v[6:7], off
	global_load_b64 v[18:19], v[8:9], off
	global_load_b64 v[6:7], v[2:3], off
	global_load_b64 v[14:15], v[10:11], off
	global_load_b64 v[8:9], v[12:13], off
	s_waitcnt vmcnt(7)
	v_cmp_ngt_f64_e64 s64, s[102:103], v[0:1]
	s_waitcnt vmcnt(6)
	v_cmp_ngt_f64_e64 s33, s[102:103], v[22:23]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, s64, s33
	s_and_saveexec_b32 s1, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s65, exec_lo, s1
	s_cbranch_execz .LBB4_13
; %bb.12:
	s_waitcnt vmcnt(4)
	v_add_f64 v[0:1], v[20:21], -v[16:17]
	s_waitcnt vmcnt(3)
	v_add_f64 v[2:3], v[18:19], -v[20:21]
	v_add_f64 v[4:5], v[60:61], -v[18:19]
	s_waitcnt vmcnt(2)
	v_add_f64 v[10:11], v[6:7], -v[60:61]
	s_waitcnt vmcnt(1)
	v_add_f64 v[6:7], v[14:15], -v[6:7]
	s_waitcnt vmcnt(0)
	v_add_f64 v[8:9], v[8:9], -v[14:15]
	s_getpc_b64 s[80:81]
	s_add_u32 s80, s80, _Z24weno_onesided_derivativeddddd@rel32@lo+4
	s_addc_u32 s81, s81, _Z24weno_onesided_derivativeddddd@rel32@hi+12
	v_div_scale_f64 v[12:13], null, s[102:103], s[102:103], v[0:1]
	v_div_scale_f64 v[14:15], null, s[102:103], s[102:103], v[2:3]
	v_div_scale_f64 v[16:17], null, s[102:103], s[102:103], v[4:5]
	v_div_scale_f64 v[18:19], null, s[102:103], s[102:103], v[10:11]
	v_div_scale_f64 v[20:21], null, s[102:103], s[102:103], v[6:7]
	v_div_scale_f64 v[22:23], null, s[102:103], s[102:103], v[8:9]
	v_div_scale_f64 v[53:54], vcc_lo, v[0:1], s[102:103], v[0:1]
	v_rcp_f64_e32 v[24:25], v[12:13]
	v_rcp_f64_e32 v[26:27], v[14:15]
	v_rcp_f64_e32 v[28:29], v[16:17]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_rcp_f64_e32 v[30:31], v[18:19]
	v_rcp_f64_e32 v[32:33], v[20:21]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(TRANS32_DEP_3)
	v_rcp_f64_e32 v[34:35], v[22:23]
	v_fma_f64 v[36:37], -v[12:13], v[24:25], 1.0
	v_fma_f64 v[38:39], -v[14:15], v[26:27], 1.0
	v_fma_f64 v[45:46], -v[16:17], v[28:29], 1.0
	v_fma_f64 v[47:48], -v[18:19], v[30:31], 1.0
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[49:50], -v[20:21], v[32:33], 1.0
	v_fma_f64 v[51:52], -v[22:23], v[34:35], 1.0
	v_fma_f64 v[24:25], v[24:25], v[36:37], v[24:25]
	v_fma_f64 v[26:27], v[26:27], v[38:39], v[26:27]
	v_fma_f64 v[28:29], v[28:29], v[45:46], v[28:29]
	v_fma_f64 v[30:31], v[30:31], v[47:48], v[30:31]
	v_fma_f64 v[32:33], v[32:33], v[49:50], v[32:33]
	v_fma_f64 v[34:35], v[34:35], v[51:52], v[34:35]
	v_fma_f64 v[36:37], -v[12:13], v[24:25], 1.0
	v_fma_f64 v[38:39], -v[14:15], v[26:27], 1.0
	v_fma_f64 v[45:46], -v[16:17], v[28:29], 1.0
	v_fma_f64 v[47:48], -v[18:19], v[30:31], 1.0
	v_fma_f64 v[49:50], -v[20:21], v[32:33], 1.0
	v_fma_f64 v[51:52], -v[22:23], v[34:35], 1.0
	v_fma_f64 v[24:25], v[24:25], v[36:37], v[24:25]
	v_div_scale_f64 v[36:37], s0, v[2:3], s[102:103], v[2:3]
	v_fma_f64 v[26:27], v[26:27], v[38:39], v[26:27]
	v_div_scale_f64 v[38:39], s1, v[4:5], s[102:103], v[4:5]
	v_fma_f64 v[28:29], v[28:29], v[45:46], v[28:29]
	v_div_scale_f64 v[45:46], s2, v[10:11], s[102:103], v[10:11]
	v_fma_f64 v[30:31], v[30:31], v[47:48], v[30:31]
	v_div_scale_f64 v[47:48], s3, v[6:7], s[102:103], v[6:7]
	v_fma_f64 v[32:33], v[32:33], v[49:50], v[32:33]
	v_fma_f64 v[34:35], v[34:35], v[51:52], v[34:35]
	v_div_scale_f64 v[49:50], s4, v[8:9], s[102:103], v[8:9]
	v_mul_f64 v[51:52], v[53:54], v[24:25]
	v_mul_f64 v[55:56], v[36:37], v[26:27]
	v_mul_f64 v[57:58], v[38:39], v[28:29]
	v_mul_f64 v[69:70], v[45:46], v[30:31]
	v_mul_f64 v[71:72], v[47:48], v[32:33]
	v_mul_f64 v[73:74], v[49:50], v[34:35]
	v_fma_f64 v[12:13], -v[12:13], v[51:52], v[53:54]
	v_fma_f64 v[14:15], -v[14:15], v[55:56], v[36:37]
	v_fma_f64 v[16:17], -v[16:17], v[57:58], v[38:39]
	v_fma_f64 v[18:19], -v[18:19], v[69:70], v[45:46]
	v_fma_f64 v[20:21], -v[20:21], v[71:72], v[47:48]
	v_fma_f64 v[22:23], -v[22:23], v[73:74], v[49:50]
	v_div_fmas_f64 v[12:13], v[12:13], v[24:25], v[51:52]
	s_mov_b32 vcc_lo, s0
	v_div_fmas_f64 v[14:15], v[14:15], v[26:27], v[55:56]
	s_mov_b32 vcc_lo, s1
	v_div_fmas_f64 v[16:17], v[16:17], v[28:29], v[57:58]
	s_mov_b32 vcc_lo, s2
	v_div_fmas_f64 v[18:19], v[18:19], v[30:31], v[69:70]
	s_mov_b32 vcc_lo, s3
	v_div_fmas_f64 v[20:21], v[20:21], v[32:33], v[71:72]
	s_mov_b32 vcc_lo, s4
	v_div_fmas_f64 v[22:23], v[22:23], v[34:35], v[73:74]
	v_div_fixup_f64 v[0:1], v[12:13], s[102:103], v[0:1]
	v_div_fixup_f64 v[50:51], v[14:15], s[102:103], v[2:3]
	v_div_fixup_f64 v[52:53], v[16:17], s[102:103], v[4:5]
	v_div_fixup_f64 v[54:55], v[18:19], s[102:103], v[10:11]
	v_div_fixup_f64 v[56:57], v[20:21], s[102:103], v[6:7]
	v_div_fixup_f64 v[58:59], v[22:23], s[102:103], v[8:9]
	v_dual_mov_b32 v2, v50 :: v_dual_mov_b32 v3, v51
	v_dual_mov_b32 v4, v52 :: v_dual_mov_b32 v5, v53
	v_dual_mov_b32 v6, v54 :: v_dual_mov_b32 v7, v55
	v_dual_mov_b32 v8, v56 :: v_dual_mov_b32 v9, v57
	s_swappc_b64 s[30:31], s[80:81]
	v_dual_mov_b32 v45, v0 :: v_dual_mov_b32 v46, v1
	v_dual_mov_b32 v0, v58 :: v_dual_mov_b32 v1, v59
	v_dual_mov_b32 v2, v56 :: v_dual_mov_b32 v3, v57
	v_dual_mov_b32 v4, v54 :: v_dual_mov_b32 v5, v55
	v_dual_mov_b32 v6, v52 :: v_dual_mov_b32 v7, v53
	v_dual_mov_b32 v8, v50 :: v_dual_mov_b32 v9, v51
	s_swappc_b64 s[30:31], s[80:81]
	v_dual_mov_b32 v50, v0 :: v_dual_mov_b32 v51, v1
                                        ; implicit-def: $vgpr18_vgpr19
                                        ; implicit-def: $vgpr20_vgpr21
                                        ; implicit-def: $vgpr16_vgpr17
                                        ; implicit-def: $vgpr22_vgpr23
                                        ; implicit-def: $vgpr0_vgpr1
                                        ; implicit-def: $vgpr6_vgpr7
                                        ; implicit-def: $vgpr14_vgpr15
                                        ; implicit-def: $vgpr8_vgpr9
.LBB4_13:                               ; %Flow452
	s_and_not1_saveexec_b32 s5, s65
	s_cbranch_execz .LBB4_21
; %bb.14:
	v_add_co_u32 v2, vcc_lo, s94, v64
	v_add_co_ci_u32_e32 v3, vcc_lo, s95, v65, vcc_lo
	v_add_co_u32 v4, vcc_lo, s92, v64
	v_add_co_ci_u32_e32 v5, vcc_lo, s93, v65, vcc_lo
	global_load_b64 v[26:27], v[2:3], off
	global_load_b64 v[24:25], v[4:5], off
	v_add_f64 v[4:5], s[102:103], s[102:103]
	v_dual_mov_b32 v2, s102 :: v_dual_mov_b32 v3, s103
	s_and_saveexec_b32 s0, s64
	s_cbranch_execz .LBB4_16
; %bb.15:
	v_mul_f64 v[10:11], 0x40080000, s[102:103]
	v_dual_mov_b32 v0, s102 :: v_dual_mov_b32 v1, s103
	s_delay_alu instid0(VALU_DEP_4)
	v_dual_mov_b32 v2, v4 :: v_dual_mov_b32 v3, v5
	s_waitcnt vmcnt(0)
	v_dual_mov_b32 v25, v7 :: v_dual_mov_b32 v24, v6
	v_dual_mov_b32 v6, v14 :: v_dual_mov_b32 v7, v15
	v_dual_mov_b32 v15, v9 :: v_dual_mov_b32 v14, v8
	v_dual_mov_b32 v4, v10 :: v_dual_mov_b32 v5, v11
.LBB4_16:
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $vgpr8_vgpr9
                                        ; implicit-def: $sgpr0_sgpr1
                                        ; implicit-def: $sgpr2_sgpr3
	s_and_saveexec_b32 s4, s33
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s4, exec_lo, s4
	s_cbranch_execz .LBB4_18
; %bb.17:
	s_mov_b32 s2, 0
	s_waitcnt vmcnt(2)
	v_mul_f64 v[8:9], s[102:103], -2.0
	s_mov_b32 s3, 0xc0080000
	s_xor_b32 s1, s103, 0x80000000
	s_mov_b32 s0, s102
                                        ; implicit-def: $vgpr22_vgpr23
                                        ; implicit-def: $vgpr26_vgpr27
.LBB4_18:                               ; %Flow449
	s_or_saveexec_b32 s4, s4
	v_dual_mov_b32 v11, s3 :: v_dual_mov_b32 v10, s2
	v_dual_mov_b32 v13, s1 :: v_dual_mov_b32 v12, s0
	s_waitcnt vmcnt(5)
	v_dual_mov_b32 v31, v19 :: v_dual_mov_b32 v30, v18
	v_dual_mov_b32 v29, v21 :: v_dual_mov_b32 v28, v20
	s_xor_b32 exec_lo, exec_lo, s4
	s_cbranch_execz .LBB4_20
; %bb.19:
	v_xor_b32_e32 v23, 0x80000000, v23
	s_xor_b32 s1, s103, 0x80000000
	s_mov_b32 s0, s102
	s_waitcnt vmcnt(2)
	v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v9, s1
	v_dual_mov_b32 v11, -2.0 :: v_dual_mov_b32 v8, s0
	v_dual_mov_b32 v12, v22 :: v_dual_mov_b32 v13, v23
	s_waitcnt vmcnt(1)
	v_dual_mov_b32 v31, v27 :: v_dual_mov_b32 v30, v26
	v_dual_mov_b32 v29, v19 :: v_dual_mov_b32 v28, v18
	v_dual_mov_b32 v16, v20 :: v_dual_mov_b32 v17, v21
.LBB4_20:                               ; %_Z14select_stencilRdS_S_S_S_S_S_S_S_S_S_S_S_S_dddddddddddddddd.exit.i328
	s_or_b32 exec_lo, exec_lo, s4
	s_waitcnt vmcnt(3)
	v_add_f64 v[14:15], v[14:15], -v[6:7]
	v_add_f64 v[18:19], v[4:5], -v[2:3]
	s_waitcnt vmcnt(0)
	v_add_f64 v[20:21], v[6:7], -v[24:25]
	v_add_f64 v[22:23], v[2:3], -v[0:1]
	v_add_f64 v[24:25], v[24:25], -v[60:61]
	v_add_f64 v[26:27], v[60:61], -v[30:31]
	v_add_f64 v[6:7], -v[12:13], 0
	v_add_f64 v[30:31], v[30:31], -v[28:29]
	v_add_f64 v[32:33], v[12:13], -v[8:9]
	v_add_f64 v[16:17], v[28:29], -v[16:17]
	v_fma_f64 v[28:29], -v[10:11], s[102:103], v[8:9]
	v_div_scale_f64 v[34:35], null, v[18:19], v[18:19], v[14:15]
	v_div_scale_f64 v[36:37], null, v[22:23], v[22:23], v[20:21]
	v_div_scale_f64 v[38:39], null, v[0:1], v[0:1], v[24:25]
	v_div_scale_f64 v[45:46], null, v[6:7], v[6:7], v[26:27]
	v_div_scale_f64 v[47:48], null, v[32:33], v[32:33], v[30:31]
	v_div_scale_f64 v[49:50], null, v[28:29], v[28:29], v[16:17]
	v_div_scale_f64 v[85:86], vcc_lo, v[14:15], v[18:19], v[14:15]
	v_rcp_f64_e32 v[51:52], v[34:35]
	v_rcp_f64_e32 v[53:54], v[36:37]
	v_rcp_f64_e32 v[55:56], v[38:39]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_rcp_f64_e32 v[57:58], v[45:46]
	v_rcp_f64_e32 v[69:70], v[47:48]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(TRANS32_DEP_3)
	v_rcp_f64_e32 v[71:72], v[49:50]
	v_fma_f64 v[73:74], -v[34:35], v[51:52], 1.0
	v_fma_f64 v[75:76], -v[36:37], v[53:54], 1.0
	v_fma_f64 v[77:78], -v[38:39], v[55:56], 1.0
	v_fma_f64 v[79:80], -v[45:46], v[57:58], 1.0
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[81:82], -v[47:48], v[69:70], 1.0
	v_fma_f64 v[83:84], -v[49:50], v[71:72], 1.0
	v_fma_f64 v[51:52], v[51:52], v[73:74], v[51:52]
	v_fma_f64 v[53:54], v[53:54], v[75:76], v[53:54]
	v_fma_f64 v[55:56], v[55:56], v[77:78], v[55:56]
	v_fma_f64 v[57:58], v[57:58], v[79:80], v[57:58]
	v_fma_f64 v[69:70], v[69:70], v[81:82], v[69:70]
	v_fma_f64 v[71:72], v[71:72], v[83:84], v[71:72]
	v_fma_f64 v[73:74], -v[34:35], v[51:52], 1.0
	v_fma_f64 v[75:76], -v[36:37], v[53:54], 1.0
	v_fma_f64 v[77:78], -v[38:39], v[55:56], 1.0
	v_fma_f64 v[79:80], -v[45:46], v[57:58], 1.0
	v_fma_f64 v[81:82], -v[47:48], v[69:70], 1.0
	v_fma_f64 v[83:84], -v[49:50], v[71:72], 1.0
	v_fma_f64 v[51:52], v[51:52], v[73:74], v[51:52]
	v_div_scale_f64 v[73:74], s0, v[20:21], v[22:23], v[20:21]
	v_fma_f64 v[53:54], v[53:54], v[75:76], v[53:54]
	v_div_scale_f64 v[75:76], s1, v[24:25], v[0:1], v[24:25]
	v_fma_f64 v[55:56], v[55:56], v[77:78], v[55:56]
	v_div_scale_f64 v[77:78], s2, v[26:27], v[6:7], v[26:27]
	v_fma_f64 v[57:58], v[57:58], v[79:80], v[57:58]
	v_div_scale_f64 v[79:80], s3, v[30:31], v[32:33], v[30:31]
	v_fma_f64 v[69:70], v[69:70], v[81:82], v[69:70]
	v_div_scale_f64 v[81:82], s4, v[16:17], v[28:29], v[16:17]
	v_fma_f64 v[71:72], v[71:72], v[83:84], v[71:72]
	v_mul_f64 v[83:84], v[85:86], v[51:52]
	v_mul_f64 v[87:88], v[73:74], v[53:54]
	v_mul_f64 v[89:90], v[75:76], v[55:56]
	v_mul_f64 v[91:92], v[77:78], v[57:58]
	v_mul_f64 v[93:94], v[79:80], v[69:70]
	v_mul_f64 v[95:96], v[81:82], v[71:72]
	v_fma_f64 v[34:35], -v[34:35], v[83:84], v[85:86]
	v_fma_f64 v[36:37], -v[36:37], v[87:88], v[73:74]
	v_fma_f64 v[38:39], -v[38:39], v[89:90], v[75:76]
	v_fma_f64 v[45:46], -v[45:46], v[91:92], v[77:78]
	v_fma_f64 v[47:48], -v[47:48], v[93:94], v[79:80]
	v_fma_f64 v[49:50], -v[49:50], v[95:96], v[81:82]
	v_div_fmas_f64 v[34:35], v[34:35], v[51:52], v[83:84]
	s_mov_b32 vcc_lo, s0
	v_div_fmas_f64 v[36:37], v[36:37], v[53:54], v[87:88]
	s_mov_b32 vcc_lo, s1
	v_div_fmas_f64 v[38:39], v[38:39], v[55:56], v[89:90]
	s_mov_b32 vcc_lo, s2
	v_div_fmas_f64 v[45:46], v[45:46], v[57:58], v[91:92]
	s_mov_b32 vcc_lo, s3
	v_div_fmas_f64 v[47:48], v[47:48], v[69:70], v[93:94]
	s_mov_b32 vcc_lo, s4
	v_div_fmas_f64 v[49:50], v[49:50], v[71:72], v[95:96]
	v_div_fixup_f64 v[14:15], v[34:35], v[18:19], v[14:15]
	v_div_fixup_f64 v[18:19], v[36:37], v[22:23], v[20:21]
	v_fma_f64 v[36:37], -v[10:11], s[102:103], v[12:13]
	v_fma_f64 v[10:11], -v[10:11], s[102:103], 0
	v_div_fixup_f64 v[20:21], v[38:39], v[0:1], v[24:25]
	v_div_fixup_f64 v[22:23], v[45:46], v[6:7], v[26:27]
	v_add_f64 v[26:27], v[4:5], -v[0:1]
	v_div_fixup_f64 v[24:25], v[47:48], v[32:33], v[30:31]
	v_add_f64 v[32:33], -v[8:9], 0
	v_add_f64 v[8:9], v[0:1], -v[8:9]
	v_div_fixup_f64 v[16:17], v[49:50], v[28:29], v[16:17]
	v_add_f64 v[28:29], v[0:1], -v[12:13]
	v_add_f64 v[12:13], v[2:3], -v[12:13]
	v_add_f64 v[0:1], -v[0:1], 0
	v_add_f64 v[14:15], v[14:15], -v[18:19]
	v_add_f64 v[18:19], v[18:19], -v[20:21]
	v_add_f64 v[30:31], v[20:21], -v[22:23]
	v_add_f64 v[34:35], v[22:23], -v[24:25]
	v_add_f64 v[16:17], v[24:25], -v[16:17]
	v_div_scale_f64 v[24:25], null, v[26:27], v[26:27], v[14:15]
	v_div_scale_f64 v[81:82], vcc_lo, v[14:15], v[26:27], v[14:15]
	v_div_scale_f64 v[38:39], null, v[2:3], v[2:3], v[18:19]
	v_div_scale_f64 v[45:46], null, v[28:29], v[28:29], v[30:31]
	v_div_scale_f64 v[47:48], null, v[32:33], v[32:33], v[34:35]
	v_div_scale_f64 v[49:50], null, v[36:37], v[36:37], v[16:17]
	v_rcp_f64_e32 v[51:52], v[24:25]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_rcp_f64_e32 v[53:54], v[38:39]
	v_rcp_f64_e32 v[55:56], v[45:46]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[57:58], v[47:48]
	v_rcp_f64_e32 v[69:70], v[49:50]
	v_fma_f64 v[71:72], -v[24:25], v[51:52], 1.0
	v_fma_f64 v[73:74], -v[38:39], v[53:54], 1.0
	s_delay_alu instid0(TRANS32_DEP_3)
	v_fma_f64 v[75:76], -v[45:46], v[55:56], 1.0
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[77:78], -v[47:48], v[57:58], 1.0
	v_fma_f64 v[79:80], -v[49:50], v[69:70], 1.0
	v_fma_f64 v[51:52], v[51:52], v[71:72], v[51:52]
	v_fma_f64 v[53:54], v[53:54], v[73:74], v[53:54]
	v_fma_f64 v[55:56], v[55:56], v[75:76], v[55:56]
	v_fma_f64 v[57:58], v[57:58], v[77:78], v[57:58]
	v_fma_f64 v[69:70], v[69:70], v[79:80], v[69:70]
	v_fma_f64 v[71:72], -v[24:25], v[51:52], 1.0
	v_fma_f64 v[73:74], -v[38:39], v[53:54], 1.0
	v_fma_f64 v[75:76], -v[45:46], v[55:56], 1.0
	v_fma_f64 v[77:78], -v[47:48], v[57:58], 1.0
	v_fma_f64 v[79:80], -v[49:50], v[69:70], 1.0
	v_fma_f64 v[51:52], v[51:52], v[71:72], v[51:52]
	v_div_scale_f64 v[71:72], s0, v[18:19], v[2:3], v[18:19]
	v_fma_f64 v[53:54], v[53:54], v[73:74], v[53:54]
	v_div_scale_f64 v[73:74], s1, v[30:31], v[28:29], v[30:31]
	v_fma_f64 v[55:56], v[55:56], v[75:76], v[55:56]
	v_div_scale_f64 v[75:76], s2, v[34:35], v[32:33], v[34:35]
	v_fma_f64 v[57:58], v[57:58], v[77:78], v[57:58]
	v_div_scale_f64 v[77:78], s3, v[16:17], v[36:37], v[16:17]
	v_fma_f64 v[69:70], v[69:70], v[79:80], v[69:70]
	v_mul_f64 v[79:80], v[81:82], v[51:52]
	v_mul_f64 v[83:84], v[71:72], v[53:54]
	v_mul_f64 v[85:86], v[73:74], v[55:56]
	v_mul_f64 v[87:88], v[75:76], v[57:58]
	v_mul_f64 v[89:90], v[77:78], v[69:70]
	v_fma_f64 v[24:25], -v[24:25], v[79:80], v[81:82]
	v_fma_f64 v[38:39], -v[38:39], v[83:84], v[71:72]
	v_fma_f64 v[45:46], -v[45:46], v[85:86], v[73:74]
	v_fma_f64 v[47:48], -v[47:48], v[87:88], v[75:76]
	v_fma_f64 v[49:50], -v[49:50], v[89:90], v[77:78]
	v_div_fmas_f64 v[24:25], v[24:25], v[51:52], v[79:80]
	s_mov_b32 vcc_lo, s0
	v_div_fmas_f64 v[38:39], v[38:39], v[53:54], v[83:84]
	s_mov_b32 vcc_lo, s1
	v_div_fmas_f64 v[45:46], v[45:46], v[55:56], v[85:86]
	s_mov_b32 vcc_lo, s2
	v_div_fmas_f64 v[47:48], v[47:48], v[57:58], v[87:88]
	s_mov_b32 vcc_lo, s3
	v_div_fmas_f64 v[49:50], v[49:50], v[69:70], v[89:90]
	v_div_fixup_f64 v[14:15], v[24:25], v[26:27], v[14:15]
	v_div_fixup_f64 v[18:19], v[38:39], v[2:3], v[18:19]
	v_add_f64 v[2:3], -v[2:3], 0
	v_div_fixup_f64 v[24:25], v[45:46], v[28:29], v[30:31]
	v_div_fixup_f64 v[26:27], v[47:48], v[32:33], v[34:35]
	v_div_fixup_f64 v[16:17], v[49:50], v[36:37], v[16:17]
	v_add_f64 v[14:15], v[14:15], -v[18:19]
	v_mul_f64 v[2:3], v[0:1], v[2:3]
	v_add_f64 v[28:29], v[18:19], -v[24:25]
	v_add_f64 v[30:31], v[24:25], -v[26:27]
	v_add_f64 v[16:17], v[26:27], -v[16:17]
	v_div_scale_f64 v[34:35], null, v[4:5], v[4:5], v[14:15]
	v_div_scale_f64 v[73:74], vcc_lo, v[14:15], v[4:5], v[14:15]
	v_div_scale_f64 v[36:37], null, v[12:13], v[12:13], v[28:29]
	v_div_scale_f64 v[38:39], null, v[8:9], v[8:9], v[30:31]
	v_div_scale_f64 v[45:46], null, v[10:11], v[10:11], v[16:17]
	v_rcp_f64_e32 v[47:48], v[34:35]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rcp_f64_e32 v[49:50], v[36:37]
	v_rcp_f64_e32 v[51:52], v[38:39]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(TRANS32_DEP_3)
	v_rcp_f64_e32 v[53:54], v[45:46]
	v_fma_f64 v[55:56], -v[34:35], v[47:48], 1.0
	v_fma_f64 v[57:58], -v[36:37], v[49:50], 1.0
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[69:70], -v[38:39], v[51:52], 1.0
	v_fma_f64 v[71:72], -v[45:46], v[53:54], 1.0
	v_fma_f64 v[47:48], v[47:48], v[55:56], v[47:48]
	v_fma_f64 v[49:50], v[49:50], v[57:58], v[49:50]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[51:52], v[51:52], v[69:70], v[51:52]
	v_fma_f64 v[53:54], v[53:54], v[71:72], v[53:54]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[55:56], -v[34:35], v[47:48], 1.0
	v_fma_f64 v[57:58], -v[36:37], v[49:50], 1.0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[69:70], -v[38:39], v[51:52], 1.0
	v_fma_f64 v[71:72], -v[45:46], v[53:54], 1.0
	s_delay_alu instid0(VALU_DEP_4)
	v_fma_f64 v[47:48], v[47:48], v[55:56], v[47:48]
	v_div_scale_f64 v[55:56], s0, v[28:29], v[12:13], v[28:29]
	v_fma_f64 v[49:50], v[49:50], v[57:58], v[49:50]
	v_div_scale_f64 v[57:58], s1, v[30:31], v[8:9], v[30:31]
	v_fma_f64 v[51:52], v[51:52], v[69:70], v[51:52]
	v_div_scale_f64 v[69:70], s2, v[16:17], v[10:11], v[16:17]
	v_fma_f64 v[53:54], v[53:54], v[71:72], v[53:54]
	v_mul_f64 v[71:72], v[73:74], v[47:48]
	v_mul_f64 v[75:76], v[55:56], v[49:50]
	v_mul_f64 v[77:78], v[57:58], v[51:52]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mul_f64 v[79:80], v[69:70], v[53:54]
	v_fma_f64 v[34:35], -v[34:35], v[71:72], v[73:74]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[36:37], -v[36:37], v[75:76], v[55:56]
	v_fma_f64 v[38:39], -v[38:39], v[77:78], v[57:58]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[45:46], -v[45:46], v[79:80], v[69:70]
	v_div_fmas_f64 v[34:35], v[34:35], v[47:48], v[71:72]
	s_mov_b32 vcc_lo, s0
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_div_fmas_f64 v[36:37], v[36:37], v[49:50], v[75:76]
	s_mov_b32 vcc_lo, s1
	v_div_fmas_f64 v[38:39], v[38:39], v[51:52], v[77:78]
	s_mov_b32 vcc_lo, s2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_div_fmas_f64 v[45:46], v[45:46], v[53:54], v[79:80]
	v_div_fixup_f64 v[4:5], v[34:35], v[4:5], v[14:15]
	v_mul_f64 v[14:15], v[0:1], v[6:7]
	v_div_fixup_f64 v[12:13], v[36:37], v[12:13], v[28:29]
	v_div_fixup_f64 v[8:9], v[38:39], v[8:9], v[30:31]
	v_div_fixup_f64 v[10:11], v[45:46], v[10:11], v[16:17]
	v_mul_f64 v[16:17], v[6:7], v[32:33]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cmp_lt_f64_e64 vcc_lo, |v[12:13]|, |v[4:5]|
	v_cmp_lt_f64_e64 s0, |v[8:9]|, |v[12:13]|
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_cmp_lt_f64_e64 s1, |v[8:9]|, |v[10:11]|
	v_dual_cndmask_b32 v5, v5, v13 :: v_dual_cndmask_b32 v4, v4, v12
	v_cmp_lt_f64_e64 vcc_lo, |v[24:25]|, |v[18:19]|
	v_cndmask_b32_e64 v13, v13, v9, s0
	v_cndmask_b32_e64 v12, v12, v8, s0
	v_cmp_lt_f64_e64 s0, |v[26:27]|, |v[24:25]|
	v_cndmask_b32_e64 v9, v11, v9, s1
	v_cndmask_b32_e64 v8, v10, v8, s1
	v_mul_f64 v[2:3], v[2:3], v[4:5]
	v_mul_f64 v[4:5], v[14:15], v[12:13]
	v_mul_f64 v[10:11], v[24:25], v[26:27]
	v_mul_f64 v[12:13], v[18:19], v[24:25]
	v_mul_f64 v[8:9], v[16:17], v[8:9]
	v_dual_cndmask_b32 v14, v19, v25 :: v_dual_cndmask_b32 v15, v18, v24
	v_dual_cndmask_b32 v3, v3, v5 :: v_dual_cndmask_b32 v2, v2, v4
	v_cmp_ngt_f64_e64 s1, 0, v[10:11]
	v_cmp_ngt_f64_e64 s2, 0, v[12:13]
	v_cndmask_b32_e64 v9, v5, v9, s0
	v_cndmask_b32_e64 v5, v25, v27, s0
	v_cndmask_b32_e64 v10, v24, v26, s0
	v_cndmask_b32_e64 v8, v4, v8, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v13, 0, v5, s1
	v_cndmask_b32_e64 v11, 0, v14, s2
	v_cndmask_b32_e64 v12, 0, v10, s1
	v_cndmask_b32_e64 v10, 0, v15, s2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[5:6], v[6:7], v[12:13], v[22:23]
	v_fma_f64 v[0:1], v[0:1], v[10:11], v[20:21]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[45:46], v[5:6], v[8:9]
	v_add_f64 v[50:51], v[0:1], v[2:3]
.LBB4_21:                               ; %Flow453
	s_or_b32 exec_lo, exec_lo, s5
	v_add_nc_u32_e32 v2, 2, v62
	v_add_nc_u32_e32 v4, 3, v62
	s_waitcnt vmcnt(2)
	v_add_nc_u32_e32 v6, -1, v62
	v_add_nc_u32_e32 v0, 1, v62
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v8, -3, v62
	v_cvt_f64_i32_e32 v[2:3], v2
	v_cvt_f64_i32_e32 v[4:5], v4
	v_add_nc_u32_e32 v10, -2, v62
	v_cvt_f64_i32_e32 v[6:7], v6
	v_cvt_f64_i32_e32 v[0:1], v0
	v_cvt_f64_i32_e32 v[8:9], v8
                                        ; implicit-def: $vgpr52_vgpr53
	s_delay_alu instid0(VALU_DEP_4)
	v_cvt_f64_i32_e32 v[10:11], v10
	v_max_f64 v[2:3], v[2:3], 0
	v_max_f64 v[4:5], v[4:5], 0
	v_max_f64 v[6:7], v[6:7], 0
	v_max_f64 v[0:1], v[0:1], 0
	v_max_f64 v[8:9], v[8:9], 0
	v_max_f64 v[10:11], v[10:11], 0
	v_cmp_gt_f64_e64 s0, v[2:3], v[67:68]
	v_cmp_gt_f64_e64 s1, v[4:5], v[67:68]
	v_cmp_gt_f64_e64 s2, v[6:7], v[67:68]
	v_cmp_gt_f64_e32 vcc_lo, v[0:1], v[67:68]
	v_cmp_gt_f64_e64 s3, v[8:9], v[67:68]
	v_cmp_gt_f64_e64 s4, v[10:11], v[67:68]
	v_cndmask_b32_e64 v3, v3, v68, s0
	v_cndmask_b32_e64 v2, v2, v67, s0
	v_cndmask_b32_e64 v5, v5, v68, s1
	v_cndmask_b32_e64 v4, v4, v67, s1
	v_cndmask_b32_e32 v1, v1, v68, vcc_lo
	v_cndmask_b32_e64 v7, v7, v68, s2
	v_cndmask_b32_e64 v6, v6, v67, s2
	v_cndmask_b32_e32 v0, v0, v67, vcc_lo
	v_cndmask_b32_e64 v9, v9, v68, s3
	v_cndmask_b32_e64 v8, v8, v67, s3
	v_cvt_i32_f64_e32 v13, v[2:3]
	v_cndmask_b32_e64 v11, v11, v68, s4
	v_cvt_i32_f64_e32 v14, v[4:5]
	v_cndmask_b32_e64 v10, v10, v67, s4
	v_cvt_i32_f64_e32 v15, v[6:7]
	v_cvt_i32_f64_e32 v12, v[0:1]
	v_cvt_i32_f64_e32 v16, v[8:9]
	v_add_co_u32 v0, vcc_lo, s84, v64
	v_cvt_i32_f64_e32 v17, v[10:11]
	v_add_co_ci_u32_e32 v1, vcc_lo, s85, v65, vcc_lo
	v_add_co_u32 v4, vcc_lo, s86, v64
	v_add_co_ci_u32_e32 v5, vcc_lo, s87, v65, vcc_lo
	v_mad_u64_u32 v[6:7], null, v13, s97, v[63:64]
	v_mad_u64_u32 v[7:8], null, v14, s97, v[63:64]
	v_mad_u64_u32 v[8:9], null, v15, s97, v[63:64]
	v_mad_u64_u32 v[2:3], null, v12, s97, v[63:64]
	v_mad_u64_u32 v[9:10], null, v16, s97, v[63:64]
	v_mad_u64_u32 v[10:11], null, v17, s97, v[63:64]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mad_u64_u32 v[13:14], null, v8, s96, v[66:67]
	v_mad_u64_u32 v[11:12], null, v2, s96, v[66:67]
	s_delay_alu instid0(VALU_DEP_4)
	v_mad_u64_u32 v[15:16], null, v9, s96, v[66:67]
	global_load_b64 v[2:3], v[0:1], off
	global_load_b64 v[22:23], v[4:5], off
	v_mad_u64_u32 v[8:9], null, v10, s96, v[66:67]
	v_mad_u64_u32 v[17:18], null, v6, s96, v[66:67]
	v_ashrrev_i32_e32 v14, 31, v13
	v_ashrrev_i32_e32 v16, 31, v15
	v_mad_u64_u32 v[19:20], null, v7, s96, v[66:67]
	v_ashrrev_i32_e32 v9, 31, v8
	v_ashrrev_i32_e32 v12, 31, v11
	s_delay_alu instid0(VALU_DEP_4)
	v_lshlrev_b64 v[0:1], 3, v[15:16]
	v_lshlrev_b64 v[6:7], 3, v[13:14]
	v_ashrrev_i32_e32 v18, 31, v17
	v_lshlrev_b64 v[4:5], 3, v[8:9]
	v_lshlrev_b64 v[8:9], 3, v[11:12]
	v_ashrrev_i32_e32 v20, 31, v19
	v_add_co_u32 v0, vcc_lo, s72, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s73, v1, vcc_lo
	v_add_co_u32 v4, vcc_lo, s72, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s73, v5, vcc_lo
	v_lshlrev_b64 v[10:11], 3, v[17:18]
	v_add_co_u32 v6, vcc_lo, s72, v6
	v_add_co_ci_u32_e32 v7, vcc_lo, s73, v7, vcc_lo
	v_lshlrev_b64 v[12:13], 3, v[19:20]
	v_add_co_u32 v8, vcc_lo, s72, v8
	v_add_co_ci_u32_e32 v9, vcc_lo, s73, v9, vcc_lo
	v_add_co_u32 v10, vcc_lo, s72, v10
	v_add_co_ci_u32_e32 v11, vcc_lo, s73, v11, vcc_lo
	v_add_co_u32 v12, vcc_lo, s72, v12
	v_add_co_ci_u32_e32 v13, vcc_lo, s73, v13, vcc_lo
	s_clause 0x5
	global_load_b64 v[16:17], v[0:1], off
	global_load_b64 v[20:21], v[4:5], off
	global_load_b64 v[18:19], v[6:7], off
	global_load_b64 v[6:7], v[8:9], off
	global_load_b64 v[14:15], v[10:11], off
	global_load_b64 v[8:9], v[12:13], off
                                        ; implicit-def: $vgpr0_vgpr1
	s_waitcnt vmcnt(7)
	v_cmp_ngt_f64_e64 s64, s[66:67], v[2:3]
	s_waitcnt vmcnt(6)
	v_cmp_ngt_f64_e64 s33, s[66:67], v[22:23]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, s64, s33
	s_and_saveexec_b32 s1, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s65, exec_lo, s1
	s_cbranch_execz .LBB4_23
; %bb.22:
	s_waitcnt vmcnt(4)
	v_add_f64 v[0:1], v[20:21], -v[16:17]
	s_waitcnt vmcnt(3)
	v_add_f64 v[2:3], v[18:19], -v[20:21]
	v_add_f64 v[4:5], v[60:61], -v[18:19]
	s_waitcnt vmcnt(2)
	v_add_f64 v[10:11], v[6:7], -v[60:61]
	s_waitcnt vmcnt(1)
	v_add_f64 v[6:7], v[14:15], -v[6:7]
	s_waitcnt vmcnt(0)
	v_add_f64 v[8:9], v[8:9], -v[14:15]
	s_getpc_b64 s[72:73]
	s_add_u32 s72, s72, _Z24weno_onesided_derivativeddddd@rel32@lo+4
	s_addc_u32 s73, s73, _Z24weno_onesided_derivativeddddd@rel32@hi+12
	v_div_scale_f64 v[12:13], null, s[66:67], s[66:67], v[0:1]
	v_div_scale_f64 v[14:15], null, s[66:67], s[66:67], v[2:3]
	v_div_scale_f64 v[16:17], null, s[66:67], s[66:67], v[4:5]
	v_div_scale_f64 v[18:19], null, s[66:67], s[66:67], v[10:11]
	v_div_scale_f64 v[20:21], null, s[66:67], s[66:67], v[6:7]
	v_div_scale_f64 v[22:23], null, s[66:67], s[66:67], v[8:9]
	v_div_scale_f64 v[58:59], vcc_lo, v[0:1], s[66:67], v[0:1]
	v_rcp_f64_e32 v[24:25], v[12:13]
	v_rcp_f64_e32 v[26:27], v[14:15]
	v_rcp_f64_e32 v[28:29], v[16:17]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_rcp_f64_e32 v[30:31], v[18:19]
	v_rcp_f64_e32 v[32:33], v[20:21]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(TRANS32_DEP_3)
	v_rcp_f64_e32 v[34:35], v[22:23]
	v_fma_f64 v[36:37], -v[12:13], v[24:25], 1.0
	v_fma_f64 v[38:39], -v[14:15], v[26:27], 1.0
	v_fma_f64 v[47:48], -v[16:17], v[28:29], 1.0
	v_fma_f64 v[52:53], -v[18:19], v[30:31], 1.0
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[54:55], -v[20:21], v[32:33], 1.0
	v_fma_f64 v[56:57], -v[22:23], v[34:35], 1.0
	v_fma_f64 v[24:25], v[24:25], v[36:37], v[24:25]
	v_fma_f64 v[26:27], v[26:27], v[38:39], v[26:27]
	v_fma_f64 v[28:29], v[28:29], v[47:48], v[28:29]
	v_fma_f64 v[30:31], v[30:31], v[52:53], v[30:31]
	v_fma_f64 v[32:33], v[32:33], v[54:55], v[32:33]
	v_fma_f64 v[34:35], v[34:35], v[56:57], v[34:35]
	v_fma_f64 v[36:37], -v[12:13], v[24:25], 1.0
	v_fma_f64 v[38:39], -v[14:15], v[26:27], 1.0
	v_fma_f64 v[47:48], -v[16:17], v[28:29], 1.0
	v_fma_f64 v[52:53], -v[18:19], v[30:31], 1.0
	v_fma_f64 v[54:55], -v[20:21], v[32:33], 1.0
	v_fma_f64 v[56:57], -v[22:23], v[34:35], 1.0
	v_fma_f64 v[24:25], v[24:25], v[36:37], v[24:25]
	v_div_scale_f64 v[36:37], s0, v[2:3], s[66:67], v[2:3]
	v_fma_f64 v[26:27], v[26:27], v[38:39], v[26:27]
	v_div_scale_f64 v[38:39], s1, v[4:5], s[66:67], v[4:5]
	v_fma_f64 v[28:29], v[28:29], v[47:48], v[28:29]
	v_div_scale_f64 v[47:48], s2, v[10:11], s[66:67], v[10:11]
	v_fma_f64 v[30:31], v[30:31], v[52:53], v[30:31]
	v_div_scale_f64 v[52:53], s3, v[6:7], s[66:67], v[6:7]
	v_fma_f64 v[32:33], v[32:33], v[54:55], v[32:33]
	v_fma_f64 v[34:35], v[34:35], v[56:57], v[34:35]
	v_div_scale_f64 v[54:55], s4, v[8:9], s[66:67], v[8:9]
	v_mul_f64 v[56:57], v[58:59], v[24:25]
	v_mul_f64 v[60:61], v[36:37], v[26:27]
	v_mul_f64 v[62:63], v[38:39], v[28:29]
	v_mul_f64 v[66:67], v[47:48], v[30:31]
	v_mul_f64 v[68:69], v[52:53], v[32:33]
	v_mul_f64 v[70:71], v[54:55], v[34:35]
	v_fma_f64 v[12:13], -v[12:13], v[56:57], v[58:59]
	v_fma_f64 v[14:15], -v[14:15], v[60:61], v[36:37]
	v_fma_f64 v[16:17], -v[16:17], v[62:63], v[38:39]
	v_fma_f64 v[18:19], -v[18:19], v[66:67], v[47:48]
	v_fma_f64 v[20:21], -v[20:21], v[68:69], v[52:53]
	v_fma_f64 v[22:23], -v[22:23], v[70:71], v[54:55]
	v_div_fmas_f64 v[12:13], v[12:13], v[24:25], v[56:57]
	s_mov_b32 vcc_lo, s0
	v_div_fmas_f64 v[14:15], v[14:15], v[26:27], v[60:61]
	s_mov_b32 vcc_lo, s1
	v_div_fmas_f64 v[16:17], v[16:17], v[28:29], v[62:63]
	s_mov_b32 vcc_lo, s2
	v_div_fmas_f64 v[18:19], v[18:19], v[30:31], v[66:67]
	s_mov_b32 vcc_lo, s3
	v_div_fmas_f64 v[20:21], v[20:21], v[32:33], v[68:69]
	s_mov_b32 vcc_lo, s4
	v_div_fmas_f64 v[22:23], v[22:23], v[34:35], v[70:71]
	v_div_fixup_f64 v[0:1], v[12:13], s[66:67], v[0:1]
	v_div_fixup_f64 v[54:55], v[14:15], s[66:67], v[2:3]
	v_div_fixup_f64 v[56:57], v[16:17], s[66:67], v[4:5]
	v_div_fixup_f64 v[58:59], v[18:19], s[66:67], v[10:11]
	v_div_fixup_f64 v[60:61], v[20:21], s[66:67], v[6:7]
	v_div_fixup_f64 v[62:63], v[22:23], s[66:67], v[8:9]
	v_dual_mov_b32 v2, v54 :: v_dual_mov_b32 v3, v55
	v_dual_mov_b32 v4, v56 :: v_dual_mov_b32 v5, v57
	v_dual_mov_b32 v6, v58 :: v_dual_mov_b32 v7, v59
	v_dual_mov_b32 v8, v60 :: v_dual_mov_b32 v9, v61
	s_swappc_b64 s[30:31], s[72:73]
	v_dual_mov_b32 v52, v0 :: v_dual_mov_b32 v53, v1
	v_dual_mov_b32 v0, v62 :: v_dual_mov_b32 v1, v63
	v_dual_mov_b32 v2, v60 :: v_dual_mov_b32 v3, v61
	v_dual_mov_b32 v4, v58 :: v_dual_mov_b32 v5, v59
	v_dual_mov_b32 v6, v56 :: v_dual_mov_b32 v7, v57
	v_dual_mov_b32 v8, v54 :: v_dual_mov_b32 v9, v55
	s_swappc_b64 s[30:31], s[72:73]
                                        ; implicit-def: $vgpr60_vgpr61
                                        ; implicit-def: $vgpr16_vgpr17
                                        ; implicit-def: $vgpr20_vgpr21
                                        ; implicit-def: $vgpr18_vgpr19
                                        ; implicit-def: $vgpr6_vgpr7
                                        ; implicit-def: $vgpr14_vgpr15
                                        ; implicit-def: $vgpr8_vgpr9
                                        ; implicit-def: $vgpr2_vgpr3
                                        ; implicit-def: $vgpr22_vgpr23
.LBB4_23:                               ; %Flow446
	s_and_not1_saveexec_b32 s5, s65
	s_cbranch_execz .LBB4_31
; %bb.24:
	s_load_b128 s[0:3], s[62:63], 0x80
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v0, vcc_lo, s2, v64
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v65, vcc_lo
	v_add_co_u32 v4, vcc_lo, s0, v64
	v_add_co_ci_u32_e32 v5, vcc_lo, s1, v65, vcc_lo
	global_load_b64 v[26:27], v[0:1], off
	global_load_b64 v[24:25], v[4:5], off
	v_add_f64 v[4:5], s[66:67], s[66:67]
	v_dual_mov_b32 v0, s66 :: v_dual_mov_b32 v1, s67
	s_and_saveexec_b32 s0, s64
	s_cbranch_execz .LBB4_26
; %bb.25:
	v_mul_f64 v[10:11], 0x40080000, s[66:67]
	v_dual_mov_b32 v2, s66 :: v_dual_mov_b32 v3, s67
	s_delay_alu instid0(VALU_DEP_4)
	v_dual_mov_b32 v0, v4 :: v_dual_mov_b32 v1, v5
	s_waitcnt vmcnt(0)
	v_dual_mov_b32 v25, v7 :: v_dual_mov_b32 v24, v6
	v_dual_mov_b32 v6, v14 :: v_dual_mov_b32 v7, v15
	v_dual_mov_b32 v15, v9 :: v_dual_mov_b32 v14, v8
	v_dual_mov_b32 v4, v10 :: v_dual_mov_b32 v5, v11
.LBB4_26:
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $vgpr8_vgpr9
                                        ; implicit-def: $sgpr0_sgpr1
                                        ; implicit-def: $sgpr2_sgpr3
	s_and_saveexec_b32 s4, s33
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s4, exec_lo, s4
	s_cbranch_execz .LBB4_28
; %bb.27:
	s_mov_b32 s2, 0
	s_waitcnt vmcnt(2)
	v_mul_f64 v[8:9], s[66:67], -2.0
	s_mov_b32 s3, 0xc0080000
	s_xor_b32 s1, s67, 0x80000000
	s_mov_b32 s0, s66
                                        ; implicit-def: $vgpr22_vgpr23
                                        ; implicit-def: $vgpr26_vgpr27
.LBB4_28:                               ; %Flow
	s_or_saveexec_b32 s4, s4
	v_dual_mov_b32 v11, s3 :: v_dual_mov_b32 v10, s2
	v_dual_mov_b32 v13, s1 :: v_dual_mov_b32 v12, s0
	s_waitcnt vmcnt(5)
	v_dual_mov_b32 v31, v19 :: v_dual_mov_b32 v30, v18
	v_dual_mov_b32 v29, v21 :: v_dual_mov_b32 v28, v20
	s_xor_b32 exec_lo, exec_lo, s4
	s_cbranch_execz .LBB4_30
; %bb.29:
	v_xor_b32_e32 v23, 0x80000000, v23
	s_xor_b32 s1, s67, 0x80000000
	s_mov_b32 s0, s66
	s_waitcnt vmcnt(2)
	v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v9, s1
	v_dual_mov_b32 v11, -2.0 :: v_dual_mov_b32 v8, s0
	v_dual_mov_b32 v12, v22 :: v_dual_mov_b32 v13, v23
	s_waitcnt vmcnt(1)
	v_dual_mov_b32 v31, v27 :: v_dual_mov_b32 v30, v26
	v_dual_mov_b32 v29, v19 :: v_dual_mov_b32 v28, v18
	v_dual_mov_b32 v16, v20 :: v_dual_mov_b32 v17, v21
.LBB4_30:                               ; %_Z14select_stencilRdS_S_S_S_S_S_S_S_S_S_S_S_S_dddddddddddddddd.exit.i355
	s_or_b32 exec_lo, exec_lo, s4
	s_waitcnt vmcnt(3)
	v_add_f64 v[14:15], v[14:15], -v[6:7]
	v_add_f64 v[18:19], v[4:5], -v[0:1]
	s_waitcnt vmcnt(0)
	v_add_f64 v[20:21], v[6:7], -v[24:25]
	v_add_f64 v[22:23], v[0:1], -v[2:3]
	v_add_f64 v[24:25], v[24:25], -v[60:61]
	v_add_f64 v[26:27], v[60:61], -v[30:31]
	v_add_f64 v[6:7], -v[12:13], 0
	v_add_f64 v[30:31], v[30:31], -v[28:29]
	v_add_f64 v[32:33], v[12:13], -v[8:9]
	v_add_f64 v[16:17], v[28:29], -v[16:17]
	v_fma_f64 v[28:29], -v[10:11], s[66:67], v[8:9]
	v_div_scale_f64 v[34:35], null, v[18:19], v[18:19], v[14:15]
	v_div_scale_f64 v[36:37], null, v[22:23], v[22:23], v[20:21]
	v_div_scale_f64 v[38:39], null, v[2:3], v[2:3], v[24:25]
	v_div_scale_f64 v[47:48], null, v[6:7], v[6:7], v[26:27]
	v_div_scale_f64 v[52:53], null, v[32:33], v[32:33], v[30:31]
	v_div_scale_f64 v[54:55], null, v[28:29], v[28:29], v[16:17]
	v_div_scale_f64 v[82:83], vcc_lo, v[14:15], v[18:19], v[14:15]
	v_rcp_f64_e32 v[56:57], v[34:35]
	v_rcp_f64_e32 v[58:59], v[36:37]
	v_rcp_f64_e32 v[60:61], v[38:39]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_rcp_f64_e32 v[62:63], v[47:48]
	v_rcp_f64_e32 v[66:67], v[52:53]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(TRANS32_DEP_3)
	v_rcp_f64_e32 v[68:69], v[54:55]
	v_fma_f64 v[70:71], -v[34:35], v[56:57], 1.0
	v_fma_f64 v[72:73], -v[36:37], v[58:59], 1.0
	v_fma_f64 v[74:75], -v[38:39], v[60:61], 1.0
	v_fma_f64 v[76:77], -v[47:48], v[62:63], 1.0
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[78:79], -v[52:53], v[66:67], 1.0
	v_fma_f64 v[80:81], -v[54:55], v[68:69], 1.0
	v_fma_f64 v[56:57], v[56:57], v[70:71], v[56:57]
	v_fma_f64 v[58:59], v[58:59], v[72:73], v[58:59]
	v_fma_f64 v[60:61], v[60:61], v[74:75], v[60:61]
	v_fma_f64 v[62:63], v[62:63], v[76:77], v[62:63]
	v_fma_f64 v[66:67], v[66:67], v[78:79], v[66:67]
	v_fma_f64 v[68:69], v[68:69], v[80:81], v[68:69]
	v_fma_f64 v[70:71], -v[34:35], v[56:57], 1.0
	v_fma_f64 v[72:73], -v[36:37], v[58:59], 1.0
	v_fma_f64 v[74:75], -v[38:39], v[60:61], 1.0
	v_fma_f64 v[76:77], -v[47:48], v[62:63], 1.0
	v_fma_f64 v[78:79], -v[52:53], v[66:67], 1.0
	v_fma_f64 v[80:81], -v[54:55], v[68:69], 1.0
	v_fma_f64 v[56:57], v[56:57], v[70:71], v[56:57]
	v_div_scale_f64 v[70:71], s0, v[20:21], v[22:23], v[20:21]
	v_fma_f64 v[58:59], v[58:59], v[72:73], v[58:59]
	v_div_scale_f64 v[72:73], s1, v[24:25], v[2:3], v[24:25]
	v_fma_f64 v[60:61], v[60:61], v[74:75], v[60:61]
	v_div_scale_f64 v[74:75], s2, v[26:27], v[6:7], v[26:27]
	v_fma_f64 v[62:63], v[62:63], v[76:77], v[62:63]
	v_div_scale_f64 v[76:77], s3, v[30:31], v[32:33], v[30:31]
	v_fma_f64 v[66:67], v[66:67], v[78:79], v[66:67]
	v_div_scale_f64 v[78:79], s4, v[16:17], v[28:29], v[16:17]
	v_fma_f64 v[68:69], v[68:69], v[80:81], v[68:69]
	v_mul_f64 v[80:81], v[82:83], v[56:57]
	v_mul_f64 v[84:85], v[70:71], v[58:59]
	v_mul_f64 v[86:87], v[72:73], v[60:61]
	v_mul_f64 v[88:89], v[74:75], v[62:63]
	v_mul_f64 v[90:91], v[76:77], v[66:67]
	v_mul_f64 v[92:93], v[78:79], v[68:69]
	v_fma_f64 v[34:35], -v[34:35], v[80:81], v[82:83]
	v_fma_f64 v[36:37], -v[36:37], v[84:85], v[70:71]
	v_fma_f64 v[38:39], -v[38:39], v[86:87], v[72:73]
	v_fma_f64 v[47:48], -v[47:48], v[88:89], v[74:75]
	v_fma_f64 v[52:53], -v[52:53], v[90:91], v[76:77]
	v_fma_f64 v[54:55], -v[54:55], v[92:93], v[78:79]
	v_div_fmas_f64 v[34:35], v[34:35], v[56:57], v[80:81]
	s_mov_b32 vcc_lo, s0
	v_div_fmas_f64 v[36:37], v[36:37], v[58:59], v[84:85]
	s_mov_b32 vcc_lo, s1
	v_div_fmas_f64 v[38:39], v[38:39], v[60:61], v[86:87]
	s_mov_b32 vcc_lo, s2
	v_div_fmas_f64 v[47:48], v[47:48], v[62:63], v[88:89]
	s_mov_b32 vcc_lo, s3
	v_div_fmas_f64 v[52:53], v[52:53], v[66:67], v[90:91]
	s_mov_b32 vcc_lo, s4
	v_div_fmas_f64 v[54:55], v[54:55], v[68:69], v[92:93]
	v_div_fixup_f64 v[14:15], v[34:35], v[18:19], v[14:15]
	v_div_fixup_f64 v[18:19], v[36:37], v[22:23], v[20:21]
	v_fma_f64 v[36:37], -v[10:11], s[66:67], v[12:13]
	v_fma_f64 v[10:11], -v[10:11], s[66:67], 0
	v_div_fixup_f64 v[20:21], v[38:39], v[2:3], v[24:25]
	v_div_fixup_f64 v[22:23], v[47:48], v[6:7], v[26:27]
	v_add_f64 v[26:27], v[4:5], -v[2:3]
	v_div_fixup_f64 v[24:25], v[52:53], v[32:33], v[30:31]
	v_add_f64 v[32:33], -v[8:9], 0
	v_add_f64 v[8:9], v[2:3], -v[8:9]
	v_div_fixup_f64 v[16:17], v[54:55], v[28:29], v[16:17]
	v_add_f64 v[28:29], v[2:3], -v[12:13]
	v_add_f64 v[12:13], v[0:1], -v[12:13]
	v_add_f64 v[2:3], -v[2:3], 0
	v_add_f64 v[14:15], v[14:15], -v[18:19]
	v_add_f64 v[18:19], v[18:19], -v[20:21]
	v_add_f64 v[30:31], v[20:21], -v[22:23]
	v_add_f64 v[34:35], v[22:23], -v[24:25]
	v_add_f64 v[16:17], v[24:25], -v[16:17]
	v_div_scale_f64 v[24:25], null, v[26:27], v[26:27], v[14:15]
	v_div_scale_f64 v[78:79], vcc_lo, v[14:15], v[26:27], v[14:15]
	v_div_scale_f64 v[38:39], null, v[0:1], v[0:1], v[18:19]
	v_div_scale_f64 v[47:48], null, v[28:29], v[28:29], v[30:31]
	v_div_scale_f64 v[52:53], null, v[32:33], v[32:33], v[34:35]
	v_div_scale_f64 v[54:55], null, v[36:37], v[36:37], v[16:17]
	v_rcp_f64_e32 v[56:57], v[24:25]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_rcp_f64_e32 v[58:59], v[38:39]
	v_rcp_f64_e32 v[60:61], v[47:48]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[62:63], v[52:53]
	v_rcp_f64_e32 v[66:67], v[54:55]
	v_fma_f64 v[68:69], -v[24:25], v[56:57], 1.0
	v_fma_f64 v[70:71], -v[38:39], v[58:59], 1.0
	s_delay_alu instid0(TRANS32_DEP_3)
	v_fma_f64 v[72:73], -v[47:48], v[60:61], 1.0
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[74:75], -v[52:53], v[62:63], 1.0
	v_fma_f64 v[76:77], -v[54:55], v[66:67], 1.0
	v_fma_f64 v[56:57], v[56:57], v[68:69], v[56:57]
	v_fma_f64 v[58:59], v[58:59], v[70:71], v[58:59]
	v_fma_f64 v[60:61], v[60:61], v[72:73], v[60:61]
	v_fma_f64 v[62:63], v[62:63], v[74:75], v[62:63]
	v_fma_f64 v[66:67], v[66:67], v[76:77], v[66:67]
	v_fma_f64 v[68:69], -v[24:25], v[56:57], 1.0
	v_fma_f64 v[70:71], -v[38:39], v[58:59], 1.0
	v_fma_f64 v[72:73], -v[47:48], v[60:61], 1.0
	v_fma_f64 v[74:75], -v[52:53], v[62:63], 1.0
	v_fma_f64 v[76:77], -v[54:55], v[66:67], 1.0
	v_fma_f64 v[56:57], v[56:57], v[68:69], v[56:57]
	v_div_scale_f64 v[68:69], s0, v[18:19], v[0:1], v[18:19]
	v_fma_f64 v[58:59], v[58:59], v[70:71], v[58:59]
	v_div_scale_f64 v[70:71], s1, v[30:31], v[28:29], v[30:31]
	v_fma_f64 v[60:61], v[60:61], v[72:73], v[60:61]
	v_div_scale_f64 v[72:73], s2, v[34:35], v[32:33], v[34:35]
	v_fma_f64 v[62:63], v[62:63], v[74:75], v[62:63]
	v_div_scale_f64 v[74:75], s3, v[16:17], v[36:37], v[16:17]
	v_fma_f64 v[66:67], v[66:67], v[76:77], v[66:67]
	v_mul_f64 v[76:77], v[78:79], v[56:57]
	v_mul_f64 v[80:81], v[68:69], v[58:59]
	v_mul_f64 v[82:83], v[70:71], v[60:61]
	v_mul_f64 v[84:85], v[72:73], v[62:63]
	v_mul_f64 v[86:87], v[74:75], v[66:67]
	v_fma_f64 v[24:25], -v[24:25], v[76:77], v[78:79]
	v_fma_f64 v[38:39], -v[38:39], v[80:81], v[68:69]
	v_fma_f64 v[47:48], -v[47:48], v[82:83], v[70:71]
	v_fma_f64 v[52:53], -v[52:53], v[84:85], v[72:73]
	v_fma_f64 v[54:55], -v[54:55], v[86:87], v[74:75]
	v_div_fmas_f64 v[24:25], v[24:25], v[56:57], v[76:77]
	s_mov_b32 vcc_lo, s0
	v_div_fmas_f64 v[38:39], v[38:39], v[58:59], v[80:81]
	s_mov_b32 vcc_lo, s1
	v_div_fmas_f64 v[47:48], v[47:48], v[60:61], v[82:83]
	s_mov_b32 vcc_lo, s2
	v_div_fmas_f64 v[52:53], v[52:53], v[62:63], v[84:85]
	s_mov_b32 vcc_lo, s3
	v_div_fmas_f64 v[54:55], v[54:55], v[66:67], v[86:87]
	v_div_fixup_f64 v[14:15], v[24:25], v[26:27], v[14:15]
	v_div_fixup_f64 v[18:19], v[38:39], v[0:1], v[18:19]
	v_add_f64 v[0:1], -v[0:1], 0
	v_div_fixup_f64 v[24:25], v[47:48], v[28:29], v[30:31]
	v_div_fixup_f64 v[26:27], v[52:53], v[32:33], v[34:35]
	v_div_fixup_f64 v[16:17], v[54:55], v[36:37], v[16:17]
	v_add_f64 v[14:15], v[14:15], -v[18:19]
	v_mul_f64 v[0:1], v[2:3], v[0:1]
	v_add_f64 v[28:29], v[18:19], -v[24:25]
	v_add_f64 v[30:31], v[24:25], -v[26:27]
	v_add_f64 v[16:17], v[26:27], -v[16:17]
	v_div_scale_f64 v[34:35], null, v[4:5], v[4:5], v[14:15]
	v_div_scale_f64 v[70:71], vcc_lo, v[14:15], v[4:5], v[14:15]
	v_div_scale_f64 v[36:37], null, v[12:13], v[12:13], v[28:29]
	v_div_scale_f64 v[38:39], null, v[8:9], v[8:9], v[30:31]
	v_div_scale_f64 v[47:48], null, v[10:11], v[10:11], v[16:17]
	v_rcp_f64_e32 v[52:53], v[34:35]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rcp_f64_e32 v[54:55], v[36:37]
	v_rcp_f64_e32 v[56:57], v[38:39]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(TRANS32_DEP_3)
	v_rcp_f64_e32 v[58:59], v[47:48]
	v_fma_f64 v[60:61], -v[34:35], v[52:53], 1.0
	v_fma_f64 v[62:63], -v[36:37], v[54:55], 1.0
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[66:67], -v[38:39], v[56:57], 1.0
	v_fma_f64 v[68:69], -v[47:48], v[58:59], 1.0
	v_fma_f64 v[52:53], v[52:53], v[60:61], v[52:53]
	v_fma_f64 v[54:55], v[54:55], v[62:63], v[54:55]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[56:57], v[56:57], v[66:67], v[56:57]
	v_fma_f64 v[58:59], v[58:59], v[68:69], v[58:59]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[60:61], -v[34:35], v[52:53], 1.0
	v_fma_f64 v[62:63], -v[36:37], v[54:55], 1.0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[66:67], -v[38:39], v[56:57], 1.0
	v_fma_f64 v[68:69], -v[47:48], v[58:59], 1.0
	s_delay_alu instid0(VALU_DEP_4)
	v_fma_f64 v[52:53], v[52:53], v[60:61], v[52:53]
	v_div_scale_f64 v[60:61], s0, v[28:29], v[12:13], v[28:29]
	v_fma_f64 v[54:55], v[54:55], v[62:63], v[54:55]
	v_div_scale_f64 v[62:63], s1, v[30:31], v[8:9], v[30:31]
	v_fma_f64 v[56:57], v[56:57], v[66:67], v[56:57]
	v_div_scale_f64 v[66:67], s2, v[16:17], v[10:11], v[16:17]
	v_fma_f64 v[58:59], v[58:59], v[68:69], v[58:59]
	v_mul_f64 v[68:69], v[70:71], v[52:53]
	v_mul_f64 v[72:73], v[60:61], v[54:55]
	v_mul_f64 v[74:75], v[62:63], v[56:57]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mul_f64 v[76:77], v[66:67], v[58:59]
	v_fma_f64 v[34:35], -v[34:35], v[68:69], v[70:71]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[36:37], -v[36:37], v[72:73], v[60:61]
	v_fma_f64 v[38:39], -v[38:39], v[74:75], v[62:63]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[47:48], -v[47:48], v[76:77], v[66:67]
	v_div_fmas_f64 v[34:35], v[34:35], v[52:53], v[68:69]
	s_mov_b32 vcc_lo, s0
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_div_fmas_f64 v[36:37], v[36:37], v[54:55], v[72:73]
	s_mov_b32 vcc_lo, s1
	v_div_fmas_f64 v[38:39], v[38:39], v[56:57], v[74:75]
	s_mov_b32 vcc_lo, s2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_div_fmas_f64 v[47:48], v[47:48], v[58:59], v[76:77]
	v_div_fixup_f64 v[4:5], v[34:35], v[4:5], v[14:15]
	v_mul_f64 v[14:15], v[2:3], v[6:7]
	v_div_fixup_f64 v[12:13], v[36:37], v[12:13], v[28:29]
	v_div_fixup_f64 v[8:9], v[38:39], v[8:9], v[30:31]
	v_div_fixup_f64 v[10:11], v[47:48], v[10:11], v[16:17]
	v_mul_f64 v[16:17], v[6:7], v[32:33]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cmp_lt_f64_e64 vcc_lo, |v[12:13]|, |v[4:5]|
	v_cmp_lt_f64_e64 s0, |v[8:9]|, |v[12:13]|
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_cmp_lt_f64_e64 s1, |v[8:9]|, |v[10:11]|
	v_dual_cndmask_b32 v5, v5, v13 :: v_dual_cndmask_b32 v4, v4, v12
	v_cmp_lt_f64_e64 vcc_lo, |v[24:25]|, |v[18:19]|
	v_cndmask_b32_e64 v13, v13, v9, s0
	v_cndmask_b32_e64 v12, v12, v8, s0
	v_cmp_lt_f64_e64 s0, |v[26:27]|, |v[24:25]|
	v_cndmask_b32_e64 v9, v11, v9, s1
	v_cndmask_b32_e64 v8, v10, v8, s1
	v_mul_f64 v[0:1], v[0:1], v[4:5]
	v_mul_f64 v[4:5], v[14:15], v[12:13]
	v_mul_f64 v[10:11], v[24:25], v[26:27]
	v_mul_f64 v[12:13], v[18:19], v[24:25]
	v_mul_f64 v[8:9], v[16:17], v[8:9]
	v_dual_cndmask_b32 v14, v19, v25 :: v_dual_cndmask_b32 v15, v18, v24
	v_dual_cndmask_b32 v1, v1, v5 :: v_dual_cndmask_b32 v0, v0, v4
	v_cmp_ngt_f64_e64 s1, 0, v[10:11]
	v_cmp_ngt_f64_e64 s2, 0, v[12:13]
	v_cndmask_b32_e64 v9, v5, v9, s0
	v_cndmask_b32_e64 v5, v25, v27, s0
	v_cndmask_b32_e64 v10, v24, v26, s0
	v_cndmask_b32_e64 v8, v4, v8, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v13, 0, v5, s1
	v_cndmask_b32_e64 v11, 0, v14, s2
	v_cndmask_b32_e64 v12, 0, v10, s1
	v_cndmask_b32_e64 v10, 0, v15, s2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[5:6], v[6:7], v[12:13], v[22:23]
	v_fma_f64 v[2:3], v[2:3], v[10:11], v[20:21]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[52:53], v[5:6], v[8:9]
	v_add_f64 v[0:1], v[2:3], v[0:1]
.LBB4_31:                               ; %Flow447
	s_or_b32 exec_lo, exec_lo, s5
	v_add_co_u32 v2, vcc_lo, s74, v64
	v_add_co_ci_u32_e32 v3, vcc_lo, s75, v65, vcc_lo
	v_add_co_u32 v4, vcc_lo, s76, v64
	v_add_co_ci_u32_e32 v5, vcc_lo, s77, v65, vcc_lo
	global_load_b64 v[2:3], v[2:3], off
	s_waitcnt vmcnt(3)
	v_add_co_u32 v6, vcc_lo, s78, v64
	global_load_b64 v[4:5], v[4:5], off
	v_add_co_ci_u32_e32 v7, vcc_lo, s79, v65, vcc_lo
	s_waitcnt vmcnt(2)
	v_add_co_u32 v8, vcc_lo, s70, v64
	v_add_co_ci_u32_e32 v9, vcc_lo, s71, v65, vcc_lo
	global_load_b64 v[6:7], v[6:7], off
	global_load_b64 v[8:9], v[8:9], off
	s_waitcnt vmcnt(3)
	v_max_f64 v[10:11], v[2:3], v[2:3]
	v_cmp_nlt_f64_e32 vcc_lo, 0, v[2:3]
	s_waitcnt vmcnt(2)
	v_max_f64 v[12:13], v[4:5], v[4:5]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_max_f64 v[10:11], v[10:11], 0
	v_dual_cndmask_b32 v3, 0, v3 :: v_dual_cndmask_b32 v2, 0, v2
	v_cmp_nlt_f64_e32 vcc_lo, 0, v[4:5]
	v_mul_f64 v[10:11], v[41:42], v[10:11]
	v_dual_cndmask_b32 v5, 0, v5 :: v_dual_cndmask_b32 v4, 0, v4
	s_waitcnt vmcnt(1)
	v_cmp_nlt_f64_e32 vcc_lo, 0, v[6:7]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f64 v[2:3], v[43:44], v[2:3], v[10:11]
	v_max_f64 v[10:11], v[12:13], 0
	v_fma_f64 v[2:3], v[50:51], v[4:5], v[2:3]
	v_max_f64 v[4:5], v[6:7], v[6:7]
	v_dual_cndmask_b32 v7, 0, v7 :: v_dual_cndmask_b32 v6, 0, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[2:3], v[45:46], v[10:11], v[2:3]
	v_fma_f64 v[0:1], v[0:1], v[6:7], v[2:3]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_max_f64 v[2:3], v[4:5], 0
	v_fma_f64 v[0:1], v[52:53], v[2:3], v[0:1]
	v_add_co_u32 v2, vcc_lo, s68, v64
	v_add_co_ci_u32_e32 v3, vcc_lo, s69, v65, vcc_lo
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_3)
	v_mul_f64 v[0:1], v[8:9], v[0:1]
	global_store_b64 v[2:3], v[0:1], off
.LBB4_32:
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z11extend_stepPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 8
		.amdhsa_kernarg_size 448
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 1
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 97
		.amdhsa_next_free_sgpr 104
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end4:
	.size	_Z11extend_stepPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi, .Lfunc_end4-_Z11extend_stepPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 11436
; NumSgprs: 106
; NumVgprs: 97
; ScratchSize: 8
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 13
; VGPRBlocks: 12
; NumSGPRsForWavesPerEU: 106
; NumVGPRsForWavesPerEU: 97
; Occupancy: 12
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 1
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         48
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         56
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         64
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         72
        .size:           8
        .value_kind:     global_buffer
      - .offset:         80
        .size:           4
        .value_kind:     by_value
      - .offset:         84
        .size:           4
        .value_kind:     by_value
      - .offset:         88
        .size:           4
        .value_kind:     by_value
      - .offset:         96
        .size:           8
        .value_kind:     by_value
      - .offset:         104
        .size:           8
        .value_kind:     by_value
      - .offset:         112
        .size:           8
        .value_kind:     by_value
      - .offset:         120
        .size:           4
        .value_kind:     by_value
      - .offset:         128
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         132
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         136
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         140
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         142
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         144
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         146
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         148
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         150
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         168
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         176
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         184
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         192
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 384
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z13upwind_normalPdS_S_PKdS1_S1_S1_S1_S1_S1_iiidddi
    .private_segment_fixed_size: 8
    .sgpr_count:     90
    .sgpr_spill_count: 0
    .symbol:         _Z13upwind_normalPdS_S_PKdS1_S1_S1_S1_S1_S1_iiidddi.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     100
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
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amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
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...

	.end_amdgpu_metadata
