// Copyright 2020 NVIDIA CORPORATION.  All rights reserved.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
//     https://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.

#include <stdio.h>
#include <cassert>

#define THREADBLOCK_SIZE 512
__launch_bounds__(THREADBLOCK_SIZE)
__global__ void gatherKernel(
    const int8_t ** __restrict numericalInputPtrBuffer,
    const int32_t ** __restrict categoricalInputPtrBuffer,
    const size_t * __restrict sampleSizesBuf,
    const size_t * __restrict sampleOffsetsBuf,
    int8_t * __restrict numericalOutputBuf,
    int32_t * __restrict categoricalOutputBuf,
    int sampleCount,
    int numericVolume,
    int categoricalVolume)
{
    int sampleId = blockIdx.x;
    int laneId = threadIdx.x;
    const int8_t * numericalInputBuffer = numericalInputPtrBuffer[sampleId];
    const int32_t * categoricalInputBuffer = categoricalInputPtrBuffer[sampleId];
    int sampleSize = sampleSizesBuf[sampleId];
    int sampleOffset = sampleOffsetsBuf[sampleId];

    int numericalElems = sampleSize * numericVolume;
    int8_t * numericDstBuf = numericalOutputBuf + sampleOffset * numericVolume;
    for(int elemId = laneId; elemId < numericalElems; elemId += THREADBLOCK_SIZE)
    {
        numericDstBuf[elemId] = __ldg(numericalInputBuffer + elemId);
    }

    int categoricalElems = sampleSize * categoricalVolume;
    int32_t * categoricalDstBuf = categoricalOutputBuf + sampleOffset * categoricalVolume;
    for(int elemId = laneId; elemId < categoricalElems; elemId += THREADBLOCK_SIZE)
    {
        categoricalDstBuf[elemId] = __ldg(categoricalInputBuffer + elemId);
    }
}

void runGatherKernel(
    const int8_t ** numericalInputPtrBuffer,
    const int32_t ** categoricalInputPtrBuffer,
    const size_t * sampleSizesBuf,
    const size_t * sampleOffsetsBuf,
    int8_t * numericalOutputBuf,
    int32_t * categoricalOutputBuf,
    int sampleCount,
    int numericVolume,
    int categoricalVolume,
    cudaStream_t stream)
{
    gatherKernel<<<sampleCount,THREADBLOCK_SIZE,0,stream>>>(
        numericalInputPtrBuffer,
        categoricalInputPtrBuffer,
        sampleSizesBuf,
        sampleOffsetsBuf,
        numericalOutputBuf,
        categoricalOutputBuf,
        sampleCount,
        numericVolume,
        categoricalVolume);
    assert(cudaGetLastError() == cudaSuccess);
}

	.file	"tmpxft_00203869_00000000-6_dlrm_kernels.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2030:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z51__device_stub__Z12gatherKernelPPKaPPKiPKmS6_PaPiiiiPPKaPPKiPKmS6_PaPiiii
	.type	_Z51__device_stub__Z12gatherKernelPPKaPPKiPKmS6_PaPiiiiPPKaPPKiPKmS6_PaPiiii, @function
_Z51__device_stub__Z12gatherKernelPPKaPPKiPKmS6_PaPiiiiPPKaPPKiPKmS6_PaPiiii:
.LFB2052:
	.cfi_startproc
	endbr64
	subq	$200, %rsp
	.cfi_def_cfa_offset 208
	movq	%fs:40, %rax
	movq	%rax, 184(%rsp)
	xorl	%eax, %eax
	movq	%rsp, %rax
	movq	%rdi, (%rsp)
	leaq	64(%rsp), %rdi
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	208(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	216(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	224(%rsp), %rax
	movq	%rsi, 8(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 16(%rsp)
	leaq	48(%rsp), %rdx
	movq	%rcx, 24(%rsp)
	leaq	56(%rsp), %rcx
	movq	%rax, 176(%rsp)
	movabsq	$4294967297, %rax
	movq	%r8, 32(%rsp)
	movq	%r9, 40(%rsp)
	movq	%rax, 64(%rsp)
	movl	$1, 72(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	56(%rsp)
	.cfi_def_cfa_offset 216
	leaq	_Z12gatherKernelPPKaPPKiPKmS6_PaPiiii(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 224
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 216
	popq	%rdx
	.cfi_def_cfa_offset 208
.L2:
	movq	184(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$200, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2052:
	.size	_Z51__device_stub__Z12gatherKernelPPKaPPKiPKmS6_PaPiiiiPPKaPPKiPKmS6_PaPiiii, .-_Z51__device_stub__Z12gatherKernelPPKaPPKiPKmS6_PaPiiiiPPKaPPKiPKmS6_PaPiiii
	.globl	_Z12gatherKernelPPKaPPKiPKmS6_PaPiiii
	.type	_Z12gatherKernelPPKaPPKiPKmS6_PaPiiii, @function
_Z12gatherKernelPPKaPPKiPKmS6_PaPiiii:
.LFB2053:
	.cfi_startproc
	endbr64
	jmp	_Z51__device_stub__Z12gatherKernelPPKaPPKiPKmS6_PaPiiiiPPKaPPKiPKmS6_PaPiiii
	.cfi_endproc
.LFE2053:
	.size	_Z12gatherKernelPPKaPPKiPKmS6_PaPiiii, .-_Z12gatherKernelPPKaPPKiPKmS6_PaPiiii
	.globl	_Z15runGatherKernelPPKaPPKiPKmS6_PaPiiiiP11CUstream_st
	.type	_Z15runGatherKernelPPKaPPKiPKmS6_PaPiiiiP11CUstream_st, @function
_Z15runGatherKernelPPKaPPKiPKmS6_PaPiiiiP11CUstream_st:
.LFB2027:
	.cfi_startproc
	endbr64
	movabsq	$4294967297, %rax
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	movq	%r9, %r14
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movq	%r8, %r13
	xorl	%r8d, %r8d
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movq	%rcx, %r12
	movl	$1, %ecx
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$72, %rsp
	.cfi_def_cfa_offset 128
	movl	128(%rsp), %r15d
	movq	%rax, 44(%rsp)
	movq	%rdi, 8(%rsp)
	movq	152(%rsp), %r9
	movq	%rsi, 16(%rsp)
	movl	48(%rsp), %esi
	movq	%rdx, 24(%rsp)
	movl	$8388609, %edx
	movl	136(%rsp), %ebx
	movl	%r15d, 40(%rsp)
	movq	40(%rsp), %rdi
	salq	$9, %rdx
	movl	144(%rsp), %ebp
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L8
	movl	%ebp, 144(%rsp)
	movq	%r14, %r9
	movq	%r13, %r8
	movq	%r12, %rcx
	movl	%ebx, 136(%rsp)
	movq	24(%rsp), %rdx
	movl	%r15d, 128(%rsp)
	movq	16(%rsp), %rsi
	movq	8(%rsp), %rdi
	addq	$72, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	_Z51__device_stub__Z12gatherKernelPPKaPPKiPKmS6_PaPiiiiPPKaPPKiPKmS6_PaPiiii
.L8:
	.cfi_restore_state
	addq	$72, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2027:
	.size	_Z15runGatherKernelPPKaPPKiPKmS6_PaPiiiiP11CUstream_st, .-_Z15runGatherKernelPPKaPPKiPKmS6_PaPiiiiP11CUstream_st
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z12gatherKernelPPKaPPKiPKmS6_PaPiiii"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z12gatherKernelPPKaPPKiPKmS6_PaPiiii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2055:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

// Copyright 2020 NVIDIA CORPORATION.  All rights reserved.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
//     https://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.


#include <hip/hip_runtime.h>
#include <stdio.h>
#include <cassert>

#define THREADBLOCK_SIZE 512
__launch_bounds__(THREADBLOCK_SIZE)
__global__ void gatherKernel(
    const int8_t ** __restrict numericalInputPtrBuffer,
    const int32_t ** __restrict categoricalInputPtrBuffer,
    const size_t * __restrict sampleSizesBuf,
    const size_t * __restrict sampleOffsetsBuf,
    int8_t * __restrict numericalOutputBuf,
    int32_t * __restrict categoricalOutputBuf,
    int sampleCount,
    int numericVolume,
    int categoricalVolume)
{
    int sampleId = blockIdx.x;
    int laneId = threadIdx.x;
    const int8_t * numericalInputBuffer = numericalInputPtrBuffer[sampleId];
    const int32_t * categoricalInputBuffer = categoricalInputPtrBuffer[sampleId];
    int sampleSize = sampleSizesBuf[sampleId];
    int sampleOffset = sampleOffsetsBuf[sampleId];

    int numericalElems = sampleSize * numericVolume;
    int8_t * numericDstBuf = numericalOutputBuf + sampleOffset * numericVolume;
    for(int elemId = laneId; elemId < numericalElems; elemId += THREADBLOCK_SIZE)
    {
        numericDstBuf[elemId] = __ldg(numericalInputBuffer + elemId);
    }

    int categoricalElems = sampleSize * categoricalVolume;
    int32_t * categoricalDstBuf = categoricalOutputBuf + sampleOffset * categoricalVolume;
    for(int elemId = laneId; elemId < categoricalElems; elemId += THREADBLOCK_SIZE)
    {
        categoricalDstBuf[elemId] = __ldg(categoricalInputBuffer + elemId);
    }
}

void runGatherKernel(
    const int8_t ** numericalInputPtrBuffer,
    const int32_t ** categoricalInputPtrBuffer,
    const size_t * sampleSizesBuf,
    const size_t * sampleOffsetsBuf,
    int8_t * numericalOutputBuf,
    int32_t * categoricalOutputBuf,
    int sampleCount,
    int numericVolume,
    int categoricalVolume,
    hipStream_t stream)
{
    gatherKernel<<<sampleCount,THREADBLOCK_SIZE,0,stream>>>(
        numericalInputPtrBuffer,
        categoricalInputPtrBuffer,
        sampleSizesBuf,
        sampleOffsetsBuf,
        numericalOutputBuf,
        categoricalOutputBuf,
        sampleCount,
        numericVolume,
        categoricalVolume);
    assert(hipGetLastError() == hipSuccess);
}

	.text
	.file	"dlrm_kernels.hip"
	.globl	_Z27__device_stub__gatherKernelPPKaPPKiPKmS6_PaPiiii # -- Begin function _Z27__device_stub__gatherKernelPPKaPPKiPKmS6_PaPiiii
	.type	_Z27__device_stub__gatherKernelPPKaPPKiPKmS6_PaPiiii,@function
_Z27__device_stub__gatherKernelPPKaPPKiPKmS6_PaPiiii: # @_Z27__device_stub__gatherKernelPPKaPPKiPKmS6_PaPiiii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$176, %rsp
	.cfi_def_cfa_offset 224
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	224(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	232(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	240(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z12gatherKernelPPKaPPKiPKmS6_PaPiiii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$192, %rsp
	.cfi_adjust_cfa_offset -192
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z27__device_stub__gatherKernelPPKaPPKiPKmS6_PaPiiii, .Lfunc_end0-_Z27__device_stub__gatherKernelPPKaPPKiPKmS6_PaPiiii
	.cfi_endproc
                                        # -- End function
	.globl	_Z15runGatherKernelPPKaPPKiPKmS6_PaPiiiiP12ihipStream_t # -- Begin function _Z15runGatherKernelPPKaPPKiPKmS6_PaPiiiiP12ihipStream_t
	.type	_Z15runGatherKernelPPKaPPKiPKmS6_PaPiiiiP12ihipStream_t,@function
_Z15runGatherKernelPPKaPPKiPKmS6_PaPiiiiP12ihipStream_t: # @_Z15runGatherKernelPPKaPPKiPKmS6_PaPiiiiP12ihipStream_t
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	pushq	%rax
	.cfi_def_cfa_offset 64
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%r9, %rbx
	movq	%r8, %r14
	movq	%rcx, %r15
	movq	%rdx, %r12
	movq	%rsi, %r13
	movq	%rdi, %rbp
	movl	64(%rsp), %edi
	movq	88(%rsp), %r9
	btsq	$32, %rdi
	movabsq	$4294967296, %rdx               # imm = 0x100000000
	orq	$512, %rdx                      # imm = 0x200
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	je	.LBB1_1
# %bb.2:
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	jmp	.LBB1_3
.LBB1_1:
	.cfi_def_cfa_offset 64
	movl	80(%rsp), %eax
	movl	72(%rsp), %r10d
	subq	$8, %rsp
	.cfi_adjust_cfa_offset 8
	movq	%rbp, %rdi
	movq	%r13, %rsi
	movq	%r12, %rdx
	movq	%r15, %rcx
	movq	%r14, %r8
	movq	%rbx, %r9
	pushq	%rax
	.cfi_adjust_cfa_offset 8
	pushq	%r10
	.cfi_adjust_cfa_offset 8
	movl	88(%rsp), %eax
	pushq	%rax
	.cfi_adjust_cfa_offset 8
	callq	_Z27__device_stub__gatherKernelPPKaPPKiPKmS6_PaPiiii
	addq	$40, %rsp
	.cfi_adjust_cfa_offset -40
.LBB1_3:
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z15runGatherKernelPPKaPPKiPKmS6_PaPiiiiP12ihipStream_t, .Lfunc_end1-_Z15runGatherKernelPPKaPPKiPKmS6_PaPiiiiP12ihipStream_t
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z12gatherKernelPPKaPPKiPKmS6_PaPiiii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z12gatherKernelPPKaPPKiPKmS6_PaPiiii,@object # @_Z12gatherKernelPPKaPPKiPKmS6_PaPiiii
	.section	.rodata,"a",@progbits
	.globl	_Z12gatherKernelPPKaPPKiPKmS6_PaPiiii
	.p2align	3, 0x0
_Z12gatherKernelPPKaPPKiPKmS6_PaPiiii:
	.quad	_Z27__device_stub__gatherKernelPPKaPPKiPKmS6_PaPiiii
	.size	_Z12gatherKernelPPKaPPKiPKmS6_PaPiiii, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z12gatherKernelPPKaPPKiPKmS6_PaPiiii"
	.size	.L__unnamed_1, 38

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z27__device_stub__gatherKernelPPKaPPKiPKmS6_PaPiiii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z12gatherKernelPPKaPPKiPKmS6_PaPiiii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z12gatherKernelPPKaPPKiPKmS6_PaPiiii ; -- Begin function _Z12gatherKernelPPKaPPKiPKmS6_PaPiiii
	.globl	_Z12gatherKernelPPKaPPKiPKmS6_PaPiiii
	.p2align	8
	.type	_Z12gatherKernelPPKaPPKiPKmS6_PaPiiii,@function
_Z12gatherKernelPPKaPPKiPKmS6_PaPiiii:  ; @_Z12gatherKernelPPKaPPKiPKmS6_PaPiiii
; %bb.0:
	s_clause 0x1
	s_load_b128 s[4:7], s[0:1], 0x8
	s_load_b64 s[12:13], s[0:1], 0x18
	s_mov_b32 s2, s15
	s_ashr_i32 s3, s15, 31
	s_delay_alu instid0(SALU_CYCLE_1)
	s_lshl_b64 s[8:9], s[2:3], 3
	s_waitcnt lgkmcnt(0)
	s_add_u32 s4, s4, s8
	s_addc_u32 s5, s5, s9
	s_add_u32 s2, s6, s8
	s_addc_u32 s3, s7, s9
	s_add_u32 s12, s12, s8
	s_load_b64 s[6:7], s[0:1], 0x34
	s_load_b32 s11, s[2:3], 0x0
	s_load_b64 s[2:3], s[0:1], 0x28
	s_addc_u32 s13, s13, s9
	s_load_b64 s[4:5], s[4:5], 0x0
	s_load_b32 s10, s[12:13], 0x0
	s_mov_b32 s13, exec_lo
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s12, s11, s6
	s_delay_alu instid0(SALU_CYCLE_1)
	v_cmpx_gt_i32_e64 s12, v0
	s_cbranch_execz .LBB0_3
; %bb.1:                                ; %.lr.ph.preheader
	s_clause 0x1
	s_load_b64 s[14:15], s[0:1], 0x0
	s_load_b64 s[16:17], s[0:1], 0x20
	v_mov_b32_e32 v1, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_mov_b32_e32 v2, v1
	v_mov_b32_e32 v1, v0
	s_waitcnt lgkmcnt(0)
	s_add_u32 s0, s14, s8
	s_addc_u32 s1, s15, s9
	s_mov_b32 s14, 0
	s_load_b64 s[8:9], s[0:1], 0x0
	s_mul_i32 s0, s10, s6
	s_delay_alu instid0(SALU_CYCLE_1)
	s_ashr_i32 s6, s0, 31
	s_add_u32 s1, s16, s0
	s_addc_u32 s6, s17, s6
.LBB0_2:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v3, vcc_lo, s8, v1
	v_add_co_ci_u32_e32 v4, vcc_lo, s9, v2, vcc_lo
	global_load_u8 v5, v[3:4], off
	v_add_co_u32 v3, vcc_lo, s1, v1
	v_add_co_u32 v1, s0, 0x200, v1
	v_add_co_ci_u32_e32 v4, vcc_lo, s6, v2, vcc_lo
	v_add_co_ci_u32_e64 v2, vcc_lo, 0, v2, s0
	s_delay_alu instid0(VALU_DEP_3)
	v_cmp_le_i32_e32 vcc_lo, s12, v1
	s_or_b32 s14, vcc_lo, s14
	s_waitcnt vmcnt(0)
	global_store_b8 v[3:4], v5, off
	s_and_not1_b32 exec_lo, exec_lo, s14
	s_cbranch_execnz .LBB0_2
.LBB0_3:                                ; %Flow60
	s_or_b32 exec_lo, exec_lo, s13
	s_mul_i32 s11, s11, s7
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_i32_e64 s11, v0
	s_cbranch_execz .LBB0_6
; %bb.4:                                ; %.lr.ph45.preheader
	s_mul_i32 s0, s10, s7
	v_lshlrev_b32_e32 v3, 2, v0
	s_ashr_i32 s1, s0, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_lshl_b64 s[0:1], s[0:1], 2
	v_add_co_u32 v1, s4, s4, v3
	s_add_u32 s0, s2, s0
	s_addc_u32 s1, s3, s1
	v_add_co_u32 v3, s0, s0, v3
	v_add_co_ci_u32_e64 v2, null, s5, 0, s4
	v_add_co_ci_u32_e64 v4, null, s1, 0, s0
	s_mov_b32 s1, 0
.LBB0_5:                                ; %.lr.ph45
                                        ; =>This Inner Loop Header: Depth=1
	global_load_b32 v5, v[1:2], off
	v_add_nc_u32_e32 v0, 0x200, v0
	v_add_co_u32 v1, vcc_lo, 0x800, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, 0, v2, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_cmp_le_i32_e32 vcc_lo, s11, v0
	s_or_b32 s1, vcc_lo, s1
	s_waitcnt vmcnt(0)
	global_store_b32 v[3:4], v5, off
	v_add_co_u32 v3, s0, 0x800, v3
	v_add_co_ci_u32_e64 v4, s0, 0, v4, s0
	s_and_not1_b32 exec_lo, exec_lo, s1
	s_cbranch_execnz .LBB0_5
.LBB0_6:                                ; %Flow58
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z12gatherKernelPPKaPPKiPKmS6_PaPiiii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 60
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 6
		.amdhsa_next_free_sgpr 18
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z12gatherKernelPPKaPPKiPKmS6_PaPiiii, .Lfunc_end0-_Z12gatherKernelPPKaPPKiPKmS6_PaPiiii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 484
; NumSgprs: 20
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 20
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .actual_access:  read_only
        .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .actual_access:  read_only
        .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .actual_access:  read_only
        .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .actual_access:  read_only
        .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .actual_access:  write_only
        .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .actual_access:  write_only
        .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .offset:         48
        .size:           4
        .value_kind:     by_value
      - .offset:         52
        .size:           4
        .value_kind:     by_value
      - .offset:         56
        .size:           4
        .value_kind:     by_value
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 60
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 512
    .name:           _Z12gatherKernelPPKaPPKiPKmS6_PaPiiii
    .private_segment_fixed_size: 0
    .sgpr_count:     20
    .sgpr_spill_count: 0
    .symbol:         _Z12gatherKernelPPKaPPKiPKmS6_PaPiiii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     6
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
