#include <stdio.h>
#include <stdlib.h>
#include <cuda.h>

#define BLOCK_SIZE 8
#define M 2560
#define K 2560 
#define N 2560 

#define checkCudaErrors(err)  __checkCudaErrors (err, __FILE__, __LINE__)

inline void __checkCudaErrors(cudaError_t err, const char *file, const int line )
{
	if( CUDA_SUCCESS != err) {
		fprintf(stderr,
				"CUDA Driver API error = %04d from file <%s>, line %i.\n",
				err, file, line );
		exit(-1);
	}   
}

/*
typedef struct {
	int height;
	int width;
	float *elements;
} Matrix;
*/

struct Matrix {
	int height;
	int width;
	float *elements;
};

__global__ void MatMulKernel(const Matrix A, const Matrix B, Matrix C) {
	float cValue = 0.; 
	int row = threadIdx.x + blockIdx.x * blockDim.x;
	int col = threadIdx.y + blockIdx.y * blockDim.y;
	for (int i = 0; i < A.width; ++i) {
		cValue += A.elements[row * A.width + i] * B.elements[i * B.width + col];
	}
	C.elements[row * C.width + col] = cValue;
}

void MatMulGPU(const Matrix A, const Matrix B, Matrix C) {
	Matrix d_A, d_B, d_C;
	d_A.width = A.width; d_A.height = A.height;
	d_B.width = B.width; d_B.height = B.height;
	d_C.width = C.width; d_C.height = C.height;
	size_t size_A = A.width * A.height * sizeof(float);
	size_t size_B = B.width * B.height * sizeof(float);
	size_t size_C = C.width * C.height * sizeof(float);
	checkCudaErrors(cudaMalloc(&d_A.elements, size_A));
	checkCudaErrors(cudaMalloc(&d_B.elements, size_B));
	checkCudaErrors(cudaMalloc(&d_C.elements, size_C));
	checkCudaErrors(cudaMemcpy(d_A.elements, A.elements, size_A, cudaMemcpyHostToDevice));
	checkCudaErrors(cudaMemcpy(d_B.elements, B.elements, size_B, cudaMemcpyHostToDevice));

	dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE);
	dim3 dimGrid(A.height / dimBlock.x, B.width / dimBlock.y);
	MatMulKernel<<<dimGrid, dimBlock>>>(d_A, d_B, d_C);

	checkCudaErrors(cudaMemcpy(C.elements, d_C.elements, size_C, cudaMemcpyDeviceToHost));

	cudaFree(d_A.elements);
	cudaFree(d_B.elements);
	cudaFree(d_C.elements);
	//cudaDeviceSynchronize();
}

void MatMulCPU(const Matrix A, const Matrix B, Matrix C) {
	for (int i = 0; i < C.height; ++i) {
		for (int j = 0; j < C.width; ++j) {
			C.elements[i * C.width + j] = 0.;
			for (int k = 0; k < A.width; ++k) {
				C.elements[i * C.width + j] += A.elements[i * A.width + k] * B.elements[k * B.width + j];
			}
		}
	}
}

int main(void)
{
	// init Matrix A, B
	Matrix h_A, h_B, h_C;
	h_A.height = M; h_A.width = K;
	h_A.elements = (float *) malloc(M * K * sizeof(float));
	for (int i = 0; i < M * K; ++i) h_A.elements[i] = 0.1;

	h_B.height = K; h_B.width = N;
	h_B.elements = (float *) malloc(K * N * sizeof(float));
	for (int i = 0; i < K * N; ++i) h_B.elements[i] = 0.2;

	h_C.height = M; h_C.width = N;
	h_C.elements = (float *) malloc(M * N * sizeof(float));

	MatMulGPU(h_A, h_B, h_C);
	//MatMulCPU(h_A, h_B, h_C);

/*
	for (int i = 0; i < M; ++i) {
		for (int j = 0; j < N; ++j) {
			printf("%f ", h_C.elements[j + i * M]);
		}
		printf("\n");
	}
*/

	free(h_A.elements);
	free(h_B.elements);
	free(h_C.elements);
	return 0;
}

	.file	"tmpxft_0034250f_00000000-6_mm.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2033:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2033:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.section	.rodata._Z17__checkCudaErrors9cudaErrorPKci.str1.1,"aMS",@progbits,1
.LC0:
	.string	"CUDA Driver API error = %04d from file <%s>, line %i.\n"
	.section	.text._Z17__checkCudaErrors9cudaErrorPKci,"axG",@progbits,_Z17__checkCudaErrors9cudaErrorPKci,comdat
	.weak	_Z17__checkCudaErrors9cudaErrorPKci
	.type	_Z17__checkCudaErrors9cudaErrorPKci, @function
_Z17__checkCudaErrors9cudaErrorPKci:
.LFB2027:
	.cfi_startproc
	endbr64
	testl	%edi, %edi
	je	.L2
	pushq	%rax
	.cfi_def_cfa_offset 16
	movl	%edi, %ecx
	movq	stderr(%rip), %rdi
	movq	%rsi, %r8
	movl	%edx, %r9d
	movl	$2, %esi
	xorl	%eax, %eax
	leaq	.LC0(%rip), %rdx
	call	__fprintf_chk@PLT
	orl	$-1, %edi
	call	exit@PLT
.L2:
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2027:
	.size	_Z17__checkCudaErrors9cudaErrorPKci, .-_Z17__checkCudaErrors9cudaErrorPKci
	.text
	.globl	_Z9MatMulCPU6MatrixS_S_
	.type	_Z9MatMulCPU6MatrixS_S_, @function
_Z9MatMulCPU6MatrixS_S_:
.LFB2029:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	sarq	$32, %rdi
	movq	%rdx, %rax
	movq	%r8, %rdx
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	sarq	$32, %rdx
	sarq	$32, %rax
	movq	%rsi, %r10
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movl	%edx, %r15d
	salq	$2, %rax
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	xorl	%r12d, %r12d
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	xorl	%ebx, %ebx
	movq	%rcx, -8(%rsp)
	movl	%edi, -12(%rsp)
	movl	%r8d, -16(%rsp)
	xorl	%r8d, %r8d
.L9:
	cmpl	%r12d, -16(%rsp)
	jle	.L8
	movslq	%ebx, %rcx
	movq	-8(%rsp), %rbp
	xorl	%esi, %esi
	leaq	(%r9,%rcx,4), %r11
	movslq	%r8d, %rcx
	leaq	(%r10,%rcx,4), %r14
.L13:
	cmpl	%r15d, %esi
	jge	.L16
	movq	%rbp, %r13
	xorl	%ecx, %ecx
	xorps	%xmm0, %xmm0
.L11:
	movss	%xmm0, (%r11)
	cmpl	%ecx, -12(%rsp)
	jle	.L17
	movss	(%r14,%rcx,4), %xmm1
	mulss	0(%r13), %xmm1
	incq	%rcx
	addq	%rax, %r13
	addss	%xmm1, %xmm0
	jmp	.L11
.L17:
	incl	%esi
	addq	$4, %rbp
	addq	$4, %r11
	jmp	.L13
.L16:
	incl	%r12d
	addl	%edx, %ebx
	addl	%edi, %r8d
	jmp	.L9
.L8:
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2029:
	.size	_Z9MatMulCPU6MatrixS_S_, .-_Z9MatMulCPU6MatrixS_S_
	.globl	_Z41__device_stub__Z12MatMulKernel6MatrixS_S_RK6MatrixS1_RS_
	.type	_Z41__device_stub__Z12MatMulKernel6MatrixS_S_RK6MatrixS1_RS_, @function
_Z41__device_stub__Z12MatMulKernel6MatrixS_S_RK6MatrixS1_RS_:
.LFB2055:
	.cfi_startproc
	endbr64
	subq	$104, %rsp
	.cfi_def_cfa_offset 112
	movq	%fs:40, %rax
	movq	%rax, 88(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rcx
	movq	%rdi, 64(%rsp)
	movabsq	$4294967297, %rax
	movq	%rsi, 72(%rsp)
	leaq	16(%rsp), %rdi
	leaq	28(%rsp), %rsi
	movq	%rdx, 80(%rsp)
	movq	%rsp, %rdx
	movq	%rax, 16(%rsp)
	movl	$1, 24(%rsp)
	movq	%rax, 28(%rsp)
	movl	$1, 36(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L18
	pushq	8(%rsp)
	.cfi_def_cfa_offset 120
	leaq	_Z12MatMulKernel6MatrixS_S_(%rip), %rdi
	pushq	8(%rsp)
	.cfi_def_cfa_offset 128
	movq	44(%rsp), %rcx
	movl	52(%rsp), %r8d
	movq	32(%rsp), %rsi
	movl	40(%rsp), %edx
	leaq	80(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 120
	popq	%rdx
	.cfi_def_cfa_offset 112
.L18:
	movq	88(%rsp), %rax
	subq	%fs:40, %rax
	je	.L20
	call	__stack_chk_fail@PLT
.L20:
	addq	$104, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2055:
	.size	_Z41__device_stub__Z12MatMulKernel6MatrixS_S_RK6MatrixS1_RS_, .-_Z41__device_stub__Z12MatMulKernel6MatrixS_S_RK6MatrixS1_RS_
	.globl	_Z12MatMulKernel6MatrixS_S_
	.type	_Z12MatMulKernel6MatrixS_S_, @function
_Z12MatMulKernel6MatrixS_S_:
.LFB2056:
	.cfi_startproc
	endbr64
	subq	$56, %rsp
	.cfi_def_cfa_offset 64
	movq	%rdi, 32(%rsp)
	leaq	32(%rsp), %rdi
	movq	%rsi, 40(%rsp)
	leaq	16(%rsp), %rsi
	movq	%rdx, 16(%rsp)
	movq	%rsp, %rdx
	movq	%rcx, 24(%rsp)
	movq	%r8, (%rsp)
	movq	%r9, 8(%rsp)
	call	_Z41__device_stub__Z12MatMulKernel6MatrixS_S_RK6MatrixS1_RS_
	addq	$56, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2056:
	.size	_Z12MatMulKernel6MatrixS_S_, .-_Z12MatMulKernel6MatrixS_S_
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC2:
	.string	"/home/ubuntu/Datasets/stackv2/train-structured/xunzhang/xz_lab/master/cuda/mm.cu"
	.text
	.globl	_Z9MatMulGPU6MatrixS_S_
	.type	_Z9MatMulGPU6MatrixS_S_, @function
_Z9MatMulGPU6MatrixS_S_:
.LFB2028:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movq	%rsi, %r15
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	movq	%rcx, %r14
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movq	%r9, %r13
	movq	%rdx, %r9
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	sarq	$32, %r9
	leaq	.LC2(%rip), %r12
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movq	%rdi, %rbp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	sarq	$32, %rbp
	movq	%rdx, %rbx
	imull	%r9d, %ebx
	subq	$168, %rsp
	.cfi_def_cfa_offset 224
	movq	%fs:40, %rax
	movq	%rax, 152(%rsp)
	xorl	%eax, %eax
	movq	%r8, %rax
	movl	%ebp, 60(%rsp)
	imull	%edi, %ebp
	sarq	$32, %rax
	movl	%r8d, 88(%rsp)
	movslq	%ebx, %rbx
	imull	%eax, %r8d
	movl	%edi, 56(%rsp)
	salq	$2, %rbx
	movslq	%ebp, %rbp
	movl	%eax, 92(%rsp)
	salq	$2, %rbp
	movq	%rdi, 24(%rsp)
	leaq	64(%rsp), %rdi
	movslq	%r8d, %r8
	movq	%rbp, %rsi
	movl	%r9d, 76(%rsp)
	leaq	0(,%r8,4), %rax
	movq	%r9, 16(%rsp)
	movl	%edx, 72(%rsp)
	movq	%rax, 8(%rsp)
	call	cudaMalloc@PLT
	movl	$54, %edx
	movq	%r12, %rsi
	movl	%eax, %edi
	call	_Z17__checkCudaErrors9cudaErrorPKci
	leaq	80(%rsp), %rdi
	movq	%rbx, %rsi
	call	cudaMalloc@PLT
	movl	$55, %edx
	movq	%r12, %rsi
	movl	%eax, %edi
	call	_Z17__checkCudaErrors9cudaErrorPKci
	movq	8(%rsp), %rsi
	leaq	96(%rsp), %rdi
	call	cudaMalloc@PLT
	movl	$56, %edx
	movq	%r12, %rsi
	movl	%eax, %edi
	call	_Z17__checkCudaErrors9cudaErrorPKci
	movq	64(%rsp), %rdi
	movq	%rbp, %rdx
	movq	%r15, %rsi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	movl	$57, %edx
	movq	%r12, %rsi
	movl	%eax, %edi
	call	_Z17__checkCudaErrors9cudaErrorPKci
	movq	80(%rsp), %rdi
	movq	%rbx, %rdx
	movq	%r14, %rsi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	movl	$58, %edx
	movq	%r12, %rsi
	movl	%eax, %edi
	call	_Z17__checkCudaErrors9cudaErrorPKci
	movq	24(%rsp), %r10
	movq	16(%rsp), %r9
	xorl	%r8d, %r8d
	movabsq	$34359738376, %rdx
	movl	$1, %ecx
	movl	$1, %esi
	shrl	$3, %r9d
	shrl	$3, %r10d
	movl	%r9d, 48(%rsp)
	xorl	%r9d, %r9d
	movl	%r10d, 44(%rsp)
	movq	44(%rsp), %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L25
	movups	56(%rsp), %xmm0
	movups	72(%rsp), %xmm1
	leaq	136(%rsp), %rdx
	leaq	120(%rsp), %rsi
	movups	88(%rsp), %xmm2
	leaq	104(%rsp), %rdi
	movups	%xmm0, 104(%rsp)
	movups	%xmm1, 120(%rsp)
	movups	%xmm2, 136(%rsp)
	call	_Z41__device_stub__Z12MatMulKernel6MatrixS_S_RK6MatrixS1_RS_
.L25:
	movq	8(%rsp), %rdx
	movq	96(%rsp), %rsi
	movl	$2, %ecx
	movq	%r13, %rdi
	call	cudaMemcpy@PLT
	movl	$64, %edx
	movq	%r12, %rsi
	movl	%eax, %edi
	call	_Z17__checkCudaErrors9cudaErrorPKci
	movq	64(%rsp), %rdi
	call	cudaFree@PLT
	movq	80(%rsp), %rdi
	call	cudaFree@PLT
	movq	96(%rsp), %rdi
	call	cudaFree@PLT
	movq	152(%rsp), %rax
	subq	%fs:40, %rax
	je	.L26
	call	__stack_chk_fail@PLT
.L26:
	addq	$168, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2028:
	.size	_Z9MatMulGPU6MatrixS_S_, .-_Z9MatMulGPU6MatrixS_S_
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2030:
	.cfi_startproc
	endbr64
	pushq	%r12
	.cfi_def_cfa_offset 16
	.cfi_offset 12, -16
	movl	$26214400, %edi
	pushq	%rbp
	.cfi_def_cfa_offset 24
	.cfi_offset 6, -24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset 3, -32
	call	malloc@PLT
	movss	.LC3(%rip), %xmm0
	movq	%rax, %rbp
	xorl	%eax, %eax
.L29:
	movss	%xmm0, 0(%rbp,%rax,4)
	incq	%rax
	cmpq	$6553600, %rax
	jne	.L29
	movl	$26214400, %edi
	call	malloc@PLT
	movss	.LC4(%rip), %xmm0
	movq	%rax, %rbx
	xorl	%eax, %eax
.L30:
	movss	%xmm0, (%rbx,%rax,4)
	incq	%rax
	cmpq	$6553600, %rax
	jne	.L30
	movl	$26214400, %edi
	call	malloc@PLT
	movq	%rbx, %rcx
	movq	%rbp, %rsi
	movabsq	$10995116280320, %r8
	movq	%rax, %r9
	movq	%r8, %rdi
	movq	%r8, %rdx
	movq	%rax, %r12
	call	_Z9MatMulGPU6MatrixS_S_
	movq	%rbp, %rdi
	call	free@PLT
	movq	%rbx, %rdi
	call	free@PLT
	movq	%r12, %rdi
	call	free@PLT
	popq	%rbx
	.cfi_def_cfa_offset 24
	xorl	%eax, %eax
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2030:
	.size	main, .-main
	.section	.rodata.str1.1
.LC5:
	.string	"_Z12MatMulKernel6MatrixS_S_"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2058:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC5(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z12MatMulKernel6MatrixS_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2058:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst4,"aM",@progbits,4
	.align 4
.LC3:
	.long	1036831949
	.align 4
.LC4:
	.long	1045220557
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>

#define BLOCK_SIZE 8
#define M 2560
#define K 2560 
#define N 2560 

#define checkCudaErrors(err)  __checkCudaErrors (err, __FILE__, __LINE__)

inline void __checkCudaErrors(hipError_t err, const char *file, const int line )
{
	if( hipSuccess != err) {
		fprintf(stderr,
				"CUDA Driver API error = %04d from file <%s>, line %i.\n",
				err, file, line );
		exit(-1);
	}   
}

/*
typedef struct {
	int height;
	int width;
	float *elements;
} Matrix;
*/

struct Matrix {
	int height;
	int width;
	float *elements;
};

__global__ void MatMulKernel(const Matrix A, const Matrix B, Matrix C) {
	float cValue = 0.; 
	int row = threadIdx.x + blockIdx.x * blockDim.x;
	int col = threadIdx.y + blockIdx.y * blockDim.y;
	for (int i = 0; i < A.width; ++i) {
		cValue += A.elements[row * A.width + i] * B.elements[i * B.width + col];
	}
	C.elements[row * C.width + col] = cValue;
}

void MatMulGPU(const Matrix A, const Matrix B, Matrix C) {
	Matrix d_A, d_B, d_C;
	d_A.width = A.width; d_A.height = A.height;
	d_B.width = B.width; d_B.height = B.height;
	d_C.width = C.width; d_C.height = C.height;
	size_t size_A = A.width * A.height * sizeof(float);
	size_t size_B = B.width * B.height * sizeof(float);
	size_t size_C = C.width * C.height * sizeof(float);
	checkCudaErrors(hipMalloc(&d_A.elements, size_A));
	checkCudaErrors(hipMalloc(&d_B.elements, size_B));
	checkCudaErrors(hipMalloc(&d_C.elements, size_C));
	checkCudaErrors(hipMemcpy(d_A.elements, A.elements, size_A, hipMemcpyHostToDevice));
	checkCudaErrors(hipMemcpy(d_B.elements, B.elements, size_B, hipMemcpyHostToDevice));

	dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE);
	dim3 dimGrid(A.height / dimBlock.x, B.width / dimBlock.y);
	MatMulKernel<<<dimGrid, dimBlock>>>(d_A, d_B, d_C);

	checkCudaErrors(hipMemcpy(C.elements, d_C.elements, size_C, hipMemcpyDeviceToHost));

	hipFree(d_A.elements);
	hipFree(d_B.elements);
	hipFree(d_C.elements);
	//cudaDeviceSynchronize();
}

void MatMulCPU(const Matrix A, const Matrix B, Matrix C) {
	for (int i = 0; i < C.height; ++i) {
		for (int j = 0; j < C.width; ++j) {
			C.elements[i * C.width + j] = 0.;
			for (int k = 0; k < A.width; ++k) {
				C.elements[i * C.width + j] += A.elements[i * A.width + k] * B.elements[k * B.width + j];
			}
		}
	}
}

int main(void)
{
	// init Matrix A, B
	Matrix h_A, h_B, h_C;
	h_A.height = M; h_A.width = K;
	h_A.elements = (float *) malloc(M * K * sizeof(float));
	for (int i = 0; i < M * K; ++i) h_A.elements[i] = 0.1;

	h_B.height = K; h_B.width = N;
	h_B.elements = (float *) malloc(K * N * sizeof(float));
	for (int i = 0; i < K * N; ++i) h_B.elements[i] = 0.2;

	h_C.height = M; h_C.width = N;
	h_C.elements = (float *) malloc(M * N * sizeof(float));

	MatMulGPU(h_A, h_B, h_C);
	//MatMulCPU(h_A, h_B, h_C);

/*
	for (int i = 0; i < M; ++i) {
		for (int j = 0; j < N; ++j) {
			printf("%f ", h_C.elements[j + i * M]);
		}
		printf("\n");
	}
*/

	free(h_A.elements);
	free(h_B.elements);
	free(h_C.elements);
	return 0;
}

	.text
	.file	"mm.hip"
	.globl	_Z27__device_stub__MatMulKernel6MatrixS_S_ # -- Begin function _Z27__device_stub__MatMulKernel6MatrixS_S_
	.type	_Z27__device_stub__MatMulKernel6MatrixS_S_,@function
_Z27__device_stub__MatMulKernel6MatrixS_S_: # @_Z27__device_stub__MatMulKernel6MatrixS_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	80(%rsp), %rax
	movq	%rdi, (%rax)
	movq	%rsi, 8(%rax)
	leaq	64(%rsp), %rsi
	movq	%rdx, (%rsi)
	movq	%rcx, 8(%rsi)
	leaq	48(%rsp), %rcx
	movq	%r8, (%rcx)
	movq	%r9, 8(%rcx)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rsi, 8(%rbx)
	movq	%rcx, 16(%rbx)
	leaq	32(%rsp), %r14
	leaq	16(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z12MatMulKernel6MatrixS_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z27__device_stub__MatMulKernel6MatrixS_S_, .Lfunc_end0-_Z27__device_stub__MatMulKernel6MatrixS_S_
	.cfi_endproc
                                        # -- End function
	.globl	_Z9MatMulGPU6MatrixS_S_         # -- Begin function _Z9MatMulGPU6MatrixS_S_
	.type	_Z9MatMulGPU6MatrixS_S_,@function
_Z9MatMulGPU6MatrixS_S_:                # @_Z9MatMulGPU6MatrixS_S_
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$72, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%r9, 48(%rsp)                   # 8-byte Spill
	movq	%r8, %rbp
	movq	%rcx, 56(%rsp)                  # 8-byte Spill
	movq	%rdx, %r14
	movq	%rsi, 64(%rsp)                  # 8-byte Spill
	movq	%rdi, %r15
	movq	%rdi, %rax
	shrq	$32, %rax
	movq	%rdx, %r13
	shrq	$32, %r13
	movq	%r8, %r12
	shrq	$32, %r12
	leaq	40(%rsp), %rdi
	movq	%r15, -8(%rdi)
	movl	%r13d, 20(%rsp)
	movl	%r14d, 16(%rsp)
	movl	%r12d, 4(%rsp)
	movl	%ebp, (%rsp)
	imull	%r15d, %eax
	movslq	%eax, %rbx
	shlq	$2, %rbx
	movq	%rbx, %rsi
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB1_1
# %bb.3:                                # %_Z17__checkCudaErrors10hipError_tPKci.exit
	imull	%r14d, %r13d
	movslq	%r13d, %r13
	shlq	$2, %r13
	leaq	24(%rsp), %rdi
	movq	%r13, %rsi
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB1_4
# %bb.5:                                # %_Z17__checkCudaErrors10hipError_tPKci.exit34
	imull	%ebp, %r12d
	movslq	%r12d, %r12
	shlq	$2, %r12
	leaq	8(%rsp), %rdi
	movq	%r12, %rsi
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB1_6
# %bb.7:                                # %_Z17__checkCudaErrors10hipError_tPKci.exit36
	movq	40(%rsp), %rdi
	movq	64(%rsp), %rsi                  # 8-byte Reload
	movq	%rbx, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	testl	%eax, %eax
	jne	.LBB1_8
# %bb.9:                                # %_Z17__checkCudaErrors10hipError_tPKci.exit38
	movq	24(%rsp), %rdi
	movq	56(%rsp), %rsi                  # 8-byte Reload
	movq	%r13, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	testl	%eax, %eax
	jne	.LBB1_10
# %bb.11:                               # %_Z17__checkCudaErrors10hipError_tPKci.exit40
	shrl	$3, %r15d
	shrq	$3, %r14
	movabsq	$2305843004918726656, %rdi      # imm = 0x1FFFFFFF00000000
	andq	%r14, %rdi
	orq	%r15, %rdi
	movabsq	$34359738376, %rdx              # imm = 0x800000008
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_13
# %bb.12:
	movq	32(%rsp), %rdi
	movq	40(%rsp), %rsi
	movq	16(%rsp), %rdx
	movq	24(%rsp), %rcx
	movq	(%rsp), %r8
	movq	8(%rsp), %r9
	callq	_Z27__device_stub__MatMulKernel6MatrixS_S_
.LBB1_13:
	movq	8(%rsp), %rsi
	movq	48(%rsp), %rdi                  # 8-byte Reload
	movq	%r12, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	testl	%eax, %eax
	jne	.LBB1_14
# %bb.15:                               # %_Z17__checkCudaErrors10hipError_tPKci.exit42
	movq	40(%rsp), %rdi
	callq	hipFree
	movq	24(%rsp), %rdi
	callq	hipFree
	movq	8(%rsp), %rdi
	callq	hipFree
	addq	$72, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB1_1:
	.cfi_def_cfa_offset 128
	movq	stderr(%rip), %rdi
	movl	$.L.str.1, %esi
	movl	$.L.str, %ecx
	movl	%eax, %edx
	movl	$54, %r8d
	jmp	.LBB1_2
.LBB1_4:
	movq	stderr(%rip), %rdi
	movl	$.L.str.1, %esi
	movl	$.L.str, %ecx
	movl	%eax, %edx
	movl	$55, %r8d
	jmp	.LBB1_2
.LBB1_6:
	movq	stderr(%rip), %rdi
	movl	$.L.str.1, %esi
	movl	$.L.str, %ecx
	movl	%eax, %edx
	movl	$56, %r8d
	jmp	.LBB1_2
.LBB1_8:
	movq	stderr(%rip), %rdi
	movl	$.L.str.1, %esi
	movl	$.L.str, %ecx
	movl	%eax, %edx
	movl	$57, %r8d
	jmp	.LBB1_2
.LBB1_10:
	movq	stderr(%rip), %rdi
	movl	$.L.str.1, %esi
	movl	$.L.str, %ecx
	movl	%eax, %edx
	movl	$58, %r8d
	jmp	.LBB1_2
.LBB1_14:
	movq	stderr(%rip), %rdi
	movl	$.L.str.1, %esi
	movl	$.L.str, %ecx
	movl	%eax, %edx
	movl	$64, %r8d
.LBB1_2:
	xorl	%eax, %eax
	callq	fprintf
	movl	$-1, %edi
	callq	exit
.Lfunc_end1:
	.size	_Z9MatMulGPU6MatrixS_S_, .Lfunc_end1-_Z9MatMulGPU6MatrixS_S_
	.cfi_endproc
                                        # -- End function
	.globl	_Z9MatMulCPU6MatrixS_S_         # -- Begin function _Z9MatMulCPU6MatrixS_S_
	.type	_Z9MatMulCPU6MatrixS_S_,@function
_Z9MatMulCPU6MatrixS_S_:                # @_Z9MatMulCPU6MatrixS_S_
	.cfi_startproc
# %bb.0:
	testl	%r8d, %r8d
	jle	.LBB2_10
# %bb.1:                                # %.preheader.lr.ph
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%rdi, %rax
	shrq	$32, %rax
	movq	%r8, %r10
	shrq	$32, %r10
	sarq	$32, %rdx
	movq	%r8, %r11
	sarq	$32, %r11
	sarq	$32, %rdi
	movl	%r8d, %r8d
	shlq	$2, %rdi
	shlq	$2, %rdx
	xorl	%ebx, %ebx
.LBB2_2:                                # %.preheader
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB2_4 Depth 2
                                        #       Child Loop BB2_6 Depth 3
	testl	%r10d, %r10d
	jle	.LBB2_8
# %bb.3:                                # %.lr.ph26
                                        #   in Loop: Header=BB2_2 Depth=1
	movq	%rbx, %r14
	imulq	%r11, %r14
	leaq	(%r9,%r14,4), %r14
	movq	%rcx, %r15
	xorl	%r12d, %r12d
.LBB2_4:                                #   Parent Loop BB2_2 Depth=1
                                        # =>  This Loop Header: Depth=2
                                        #       Child Loop BB2_6 Depth 3
	movl	$0, (%r14,%r12,4)
	testl	%eax, %eax
	jle	.LBB2_7
# %bb.5:                                # %.lr.ph
                                        #   in Loop: Header=BB2_4 Depth=2
	xorps	%xmm0, %xmm0
	movq	%r15, %r13
	xorl	%ebp, %ebp
.LBB2_6:                                #   Parent Loop BB2_2 Depth=1
                                        #     Parent Loop BB2_4 Depth=2
                                        # =>    This Inner Loop Header: Depth=3
	movss	(%rsi,%rbp,4), %xmm1            # xmm1 = mem[0],zero,zero,zero
	mulss	(%r13), %xmm1
	addss	%xmm1, %xmm0
	movss	%xmm0, (%r14,%r12,4)
	incq	%rbp
	addq	%rdx, %r13
	cmpq	%rbp, %rax
	jne	.LBB2_6
.LBB2_7:                                # %._crit_edge
                                        #   in Loop: Header=BB2_4 Depth=2
	incq	%r12
	addq	$4, %r15
	cmpq	%r10, %r12
	jne	.LBB2_4
.LBB2_8:                                # %._crit_edge27
                                        #   in Loop: Header=BB2_2 Depth=1
	incq	%rbx
	addq	%rdi, %rsi
	cmpq	%r8, %rbx
	jne	.LBB2_2
# %bb.9:
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	.cfi_restore %rbx
	.cfi_restore %r12
	.cfi_restore %r13
	.cfi_restore %r14
	.cfi_restore %r15
	.cfi_restore %rbp
.LBB2_10:                               # %._crit_edge29
	retq
.Lfunc_end2:
	.size	_Z9MatMulCPU6MatrixS_S_, .Lfunc_end2-_Z9MatMulCPU6MatrixS_S_
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movl	$26214400, %edi                 # imm = 0x1900000
	callq	malloc
	movq	%rax, %rbx
	xorl	%eax, %eax
.LBB3_1:                                # =>This Inner Loop Header: Depth=1
	movl	$1036831949, (%rbx,%rax,4)      # imm = 0x3DCCCCCD
	incq	%rax
	cmpq	$6553600, %rax                  # imm = 0x640000
	jne	.LBB3_1
# %bb.2:
	movl	$26214400, %edi                 # imm = 0x1900000
	callq	malloc
	movq	%rax, %r14
	xorl	%eax, %eax
.LBB3_3:                                # =>This Inner Loop Header: Depth=1
	movl	$1045220557, (%r14,%rax,4)      # imm = 0x3E4CCCCD
	incq	%rax
	cmpq	$6553600, %rax                  # imm = 0x640000
	jne	.LBB3_3
# %bb.4:
	movl	$26214400, %edi                 # imm = 0x1900000
	callq	malloc
	movq	%rax, %r15
	movabsq	$10995116280320, %rdi           # imm = 0xA0000000A00
	movq	%rbx, %rsi
	movq	%rdi, %rdx
	movq	%r14, %rcx
	movq	%rdi, %r8
	movq	%rax, %r9
	callq	_Z9MatMulGPU6MatrixS_S_
	movq	%rbx, %rdi
	callq	free
	movq	%r14, %rdi
	callq	free
	movq	%r15, %rdi
	callq	free
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	main, .Lfunc_end3-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB4_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB4_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z12MatMulKernel6MatrixS_S_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end4:
	.size	__hip_module_ctor, .Lfunc_end4-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB5_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB5_2:
	retq
.Lfunc_end5:
	.size	__hip_module_dtor, .Lfunc_end5-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z12MatMulKernel6MatrixS_S_,@object # @_Z12MatMulKernel6MatrixS_S_
	.section	.rodata,"a",@progbits
	.globl	_Z12MatMulKernel6MatrixS_S_
	.p2align	3, 0x0
_Z12MatMulKernel6MatrixS_S_:
	.quad	_Z27__device_stub__MatMulKernel6MatrixS_S_
	.size	_Z12MatMulKernel6MatrixS_S_, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"/home/ubuntu/Datasets/stackv2/train-structured-repos-hip-sm89/xunzhang/xz_lab/master/cuda/mm.hip"
	.size	.L.str, 97

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"CUDA Driver API error = %04d from file <%s>, line %i.\n"
	.size	.L.str.1, 55

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z12MatMulKernel6MatrixS_S_"
	.size	.L__unnamed_1, 28

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z27__device_stub__MatMulKernel6MatrixS_S_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z12MatMulKernel6MatrixS_S_
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z12MatMulKernel6MatrixS_S_ ; -- Begin function _Z12MatMulKernel6MatrixS_S_
	.globl	_Z12MatMulKernel6MatrixS_S_
	.p2align	8
	.type	_Z12MatMulKernel6MatrixS_S_,@function
_Z12MatMulKernel6MatrixS_S_:            ; @_Z12MatMulKernel6MatrixS_S_
; %bb.0:
	s_clause 0x2
	s_load_b32 s4, s[0:1], 0x3c
	s_load_b32 s6, s[0:1], 0x4
	s_load_b64 s[2:3], s[0:1], 0x28
	v_and_b32_e32 v2, 0x3ff, v0
	v_bfe_u32 v3, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s5, s4, 16
	s_and_b32 s4, s4, 0xffff
	s_cmp_lt_i32 s6, 1
	v_mad_u64_u32 v[0:1], null, s14, s4, v[2:3]
	v_mad_u64_u32 v[1:2], null, s15, s5, v[3:4]
	s_cbranch_scc1 .LBB0_3
; %bb.1:                                ; %.lr.ph
	s_load_b64 s[8:9], s[0:1], 0x8
	s_delay_alu instid0(VALU_DEP_2)
	v_mul_lo_u32 v2, v0, s6
	s_clause 0x1
	s_load_b32 s7, s[0:1], 0x14
	s_load_b64 s[4:5], s[0:1], 0x18
	v_mov_b32_e32 v6, 0
	v_mov_b32_e32 v4, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s8, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
.LBB0_2:                                ; =>This Inner Loop Header: Depth=1
	v_ashrrev_i32_e32 v5, 31, v4
	s_add_i32 s6, s6, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_cmp_eq_u32 s6, 0
	v_lshlrev_b64 v[7:8], 2, v[4:5]
	v_add_nc_u32_e32 v4, s7, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v7, vcc_lo, s4, v7
	v_add_co_ci_u32_e32 v8, vcc_lo, s5, v8, vcc_lo
	global_load_b32 v5, v[2:3], off
	global_load_b32 v7, v[7:8], off
	v_add_co_u32 v2, vcc_lo, v2, 4
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v6, v5, v7
	s_cbranch_scc0 .LBB0_2
	s_branch .LBB0_4
.LBB0_3:
	v_mov_b32_e32 v6, 0
.LBB0_4:                                ; %Flow28
	s_load_b32 s0, s[0:1], 0x24
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[2:3], null, v0, s0, v[1:2]
	v_ashrrev_i32_e32 v3, 31, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[2:3]
	v_add_co_u32 v0, vcc_lo, s2, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
	global_store_b32 v[0:1], v6, off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z12MatMulKernel6MatrixS_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 304
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 9
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z12MatMulKernel6MatrixS_S_, .Lfunc_end0-_Z12MatMulKernel6MatrixS_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 336
; NumSgprs: 18
; NumVgprs: 9
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 9
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .offset:         0
        .size:           16
        .value_kind:     by_value
      - .offset:         16
        .size:           16
        .value_kind:     by_value
      - .offset:         32
        .size:           16
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         52
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         60
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         62
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         64
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         66
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         68
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         70
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         112
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 304
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z12MatMulKernel6MatrixS_S_
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z12MatMulKernel6MatrixS_S_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     9
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
