
#include <iostream>
#include <ctime>
#include <cuda.h>
#include <cuda_runtime.h>

using namespace std;

#define TILE_WIDTH 100 // for shared kernel

// CPU computation

__host__ void cpuTranspose(float* M, float* R, int dim1, int dim2){

	for (int i = 0; i < dim1; i++){
		for (int j = 0; j < dim2; j++){
			R[j*dim2 + i] = M[i*dim2 + j];
		}
	}
}

// NAIVE APPROACH - global memory access only
__global__ void transpose(float* M, float* R, int dim1, int dim2){

	int column = blockDim.x* blockIdx.x + threadIdx.x;
	int row = blockDim.y * blockIdx.y + threadIdx.y;

	if(column < dim2 && row < dim1){
		R[column*dim2 + row] = M[column + row*dim2];
	}

	// __syncthreads() not needed above as only non-conflicting read/write operations occuring
}

// SHARED MEM APROACH - use shared memory
__global__ void sharedMem_transpose(float* M, float* R, int dim1, int dim2){

	// fill data into shared memory
	__shared__ float M_Shared[TILE_WIDTH][TILE_WIDTH];

	int column = TILE_WIDTH * blockIdx.x + threadIdx.x;
	int row = TILE_WIDTH * blockIdx.y + threadIdx.y;
	
	int index_in = row*dim2 + column;
	int index_out = column*dim2 + row;


	if(row < dim1 && column < dim2 && index_in < dim1*dim2){
		M_Shared[threadIdx.y][threadIdx.x] = M[index_in];
	}
	__syncthreads(); // transfer to global mem after all threads finish computation

	if(row < dim1 && column < dim2 && index_out < dim1*dim2){
		R[index_out] = M_Shared[threadIdx.y][threadIdx.x];
	}
}

int main(void){

	int const dim1 = 3000;
	int const dim2 = 3000;

	float *M_h;
	float *R_h;
	float *M_d;
	float *R_d;

	size_t size = dim1*dim2*sizeof(float);

	cudaMallocHost((float**)&M_h,size); //page locked host mem allocation
	R_h = (float*)malloc(size);
	cudaMalloc((float **)&M_d, size);


	// init matrix
	for (int i = 0; i < dim1*dim2; ++i) {
		M_h[i]=i;
	}

	// asynchronous mem copies can only happen from pinned memory (direct RAM transfer)
	// CPU cannot be held up in mem copies for async copy
	cudaMemcpyAsync(M_d,M_h,size,cudaMemcpyHostToDevice);
	cudaMalloc((float**)&R_d,size);
	cudaMemset(R_d,0,size);


	// init kernel

	// TILE_WIDTH is chosen as per shared memory availaibility in a block
	// TILE_WIDTH doesn't have much use for naive access and we could lump computatiom into fewer blocks.
	int threadNumX = TILE_WIDTH;
	int threadNumY = TILE_WIDTH;
	int blockNumX = dim1 / TILE_WIDTH + (dim1%TILE_WIDTH == 0 ? 0 : 1 );
	int blockNumY = dim2 / TILE_WIDTH + (dim2%TILE_WIDTH == 0 ? 0 : 1 );

	dim3 blockSize(threadNumX,threadNumY);
	dim3 gridSize(blockNumX, blockNumY);

	// CUDA TIMER to Measure the performance
	cudaEvent_t start_naive, start_shared, stop_shared, stop_naive;
	
	float elapsedTime1, elapsedTime2;
	cudaEventCreate(&start_naive);
	cudaEventCreate(&stop_naive);
	cudaEventCreate(&start_shared);
	cudaEventCreate(&stop_shared);

	cudaEventRecord(start_naive, 0);

	transpose<<<gridSize,blockSize>>>(M_d,R_d,dim1,dim2);

	cudaEventRecord(stop_naive, 0);
	cudaEventSynchronize(stop_naive);
	cudaEventElapsedTime(&elapsedTime1, start_naive, stop_naive);

	cudaEventRecord(start_shared,0);

	sharedMem_transpose<<<gridSize,blockSize>>>(M_d,R_d,dim1,dim2);

	cudaEventRecord(stop_shared, 0);
	cudaEventSynchronize(stop_shared);
	cudaEventElapsedTime(&elapsedTime2, start_shared, stop_shared);

	clock_t begin = clock();

    cpuTranspose(M_h, R_h, dim1, dim2); //matrix multiplication on cpu
    
    clock_t end = clock();
    double elapsedTime3 = (double)1000*(end - begin) / CLOCKS_PER_SEC;

	cout <<"Time for the NAIVE kernel: "<<elapsedTime1<<" ms"<<endl;
	cout <<"Time for the SHARED kernel: "<<elapsedTime2<<" ms"<<endl;
	cout <<"Time for the CPU code "<<elapsedTime3<<" ms"<<endl;


	cudaFreeHost(M_h);
	free(R_h);
	cudaFree(R_d);
	cudaFree(M_d);
	return 0;
}

	.file	"tmpxft_00352797_00000000-6_transpose.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3639:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3639:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z12cpuTransposePfS_ii
	.type	_Z12cpuTransposePfS_ii, @function
_Z12cpuTransposePfS_ii:
.LFB3635:
	.cfi_startproc
	endbr64
	movslq	%ecx, %r11
	xorl	%r10d, %r10d
	movq	%rdi, %r8
	xorl	%r9d, %r9d
	salq	$2, %r11
	cmpl	%edx, %r10d
	jl	.L11
	ret
.L11:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
.L9:
	movslq	%r9d, %rax
	movq	%rsi, %rdi
	leaq	(%r8,%rax,4), %rbx
	xorl	%eax, %eax
.L6:
	cmpl	%eax, %ecx
	jle	.L13
	movss	(%rbx,%rax,4), %xmm0
	incq	%rax
	movss	%xmm0, (%rdi)
	addq	%r11, %rdi
	jmp	.L6
.L13:
	incl	%r10d
	addq	$4, %rsi
	addl	%ecx, %r9d
	cmpl	%edx, %r10d
	jl	.L9
	popq	%rbx
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3635:
	.size	_Z12cpuTransposePfS_ii, .-_Z12cpuTransposePfS_ii
	.globl	_Z32__device_stub__Z9transposePfS_iiPfS_ii
	.type	_Z32__device_stub__Z9transposePfS_iiPfS_ii, @function
_Z32__device_stub__Z9transposePfS_iiPfS_ii:
.LFB3661:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L14
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z9transposePfS_ii(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L14:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L16
	call	__stack_chk_fail@PLT
.L16:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3661:
	.size	_Z32__device_stub__Z9transposePfS_iiPfS_ii, .-_Z32__device_stub__Z9transposePfS_iiPfS_ii
	.globl	_Z9transposePfS_ii
	.type	_Z9transposePfS_ii, @function
_Z9transposePfS_ii:
.LFB3662:
	.cfi_startproc
	endbr64
	jmp	_Z32__device_stub__Z9transposePfS_iiPfS_ii
	.cfi_endproc
.LFE3662:
	.size	_Z9transposePfS_ii, .-_Z9transposePfS_ii
	.globl	_Z43__device_stub__Z19sharedMem_transposePfS_iiPfS_ii
	.type	_Z43__device_stub__Z19sharedMem_transposePfS_iiPfS_ii, @function
_Z43__device_stub__Z19sharedMem_transposePfS_iiPfS_ii:
.LFB3663:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L19
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z19sharedMem_transposePfS_ii(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L19:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L21
	call	__stack_chk_fail@PLT
.L21:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3663:
	.size	_Z43__device_stub__Z19sharedMem_transposePfS_iiPfS_ii, .-_Z43__device_stub__Z19sharedMem_transposePfS_iiPfS_ii
	.globl	_Z19sharedMem_transposePfS_ii
	.type	_Z19sharedMem_transposePfS_ii, @function
_Z19sharedMem_transposePfS_ii:
.LFB3664:
	.cfi_startproc
	endbr64
	jmp	_Z43__device_stub__Z19sharedMem_transposePfS_iiPfS_ii
	.cfi_endproc
.LFE3664:
	.size	_Z19sharedMem_transposePfS_ii, .-_Z19sharedMem_transposePfS_ii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC2:
	.string	"Time for the NAIVE kernel: "
.LC3:
	.string	" ms"
.LC4:
	.string	"Time for the SHARED kernel: "
.LC5:
	.string	"Time for the CPU code "
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB3636:
	.cfi_startproc
	endbr64
	pushq	%r14
	.cfi_def_cfa_offset 16
	.cfi_offset 14, -16
	xorl	%edx, %edx
	movl	$36000000, %esi
	pushq	%r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	pushq	%rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	subq	$104, %rsp
	.cfi_def_cfa_offset 144
	movq	%fs:40, %rax
	movq	%rax, 88(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rdi
	call	cudaHostAlloc@PLT
	movl	$36000000, %edi
	call	malloc@PLT
	movl	$36000000, %esi
	leaq	16(%rsp), %rdi
	movq	%rax, %rbx
	call	cudaMalloc@PLT
	movq	8(%rsp), %rsi
	xorl	%eax, %eax
.L25:
	cvtsi2ssl	%eax, %xmm0
	movss	%xmm0, (%rsi,%rax,4)
	incq	%rax
	cmpq	$9000000, %rax
	jne	.L25
	movq	16(%rsp), %rdi
	xorl	%r8d, %r8d
	movl	$1, %ecx
	movl	$36000000, %edx
	call	cudaMemcpyAsync@PLT
	leaq	24(%rsp), %rdi
	movl	$36000000, %esi
	call	cudaMalloc@PLT
	movq	24(%rsp), %rdi
	movl	$36000000, %edx
	xorl	%esi, %esi
	call	cudaMemset@PLT
	leaq	32(%rsp), %rdi
	movabsq	$429496729700, %rax
	movl	$1, 72(%rsp)
	movq	%rax, 64(%rsp)
	movabsq	$128849018910, %rax
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	cudaEventCreate@PLT
	leaq	56(%rsp), %rdi
	call	cudaEventCreate@PLT
	leaq	40(%rsp), %rdi
	call	cudaEventCreate@PLT
	leaq	48(%rsp), %rdi
	call	cudaEventCreate@PLT
	movq	32(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movl	72(%rsp), %ecx
	movl	84(%rsp), %esi
	xorl	%r9d, %r9d
	movq	64(%rsp), %rdx
	movq	76(%rsp), %rdi
	xorl	%r8d, %r8d
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L26
	movq	24(%rsp), %rsi
	movq	16(%rsp), %rdi
	movl	$3000, %ecx
	movl	$3000, %edx
	call	_Z32__device_stub__Z9transposePfS_iiPfS_ii
.L26:
	movq	56(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movq	56(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movq	56(%rsp), %rdx
	movq	32(%rsp), %rsi
	movq	%rsp, %rdi
	call	cudaEventElapsedTime@PLT
	movq	40(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movl	72(%rsp), %ecx
	movl	84(%rsp), %esi
	xorl	%r9d, %r9d
	movq	64(%rsp), %rdx
	movq	76(%rsp), %rdi
	xorl	%r8d, %r8d
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L27
	movq	24(%rsp), %rsi
	movq	16(%rsp), %rdi
	movl	$3000, %ecx
	movl	$3000, %edx
	call	_Z43__device_stub__Z19sharedMem_transposePfS_iiPfS_ii
.L27:
	movq	48(%rsp), %rdi
	xorl	%esi, %esi
	leaq	_ZSt4cout(%rip), %r12
	call	cudaEventRecord@PLT
	movq	48(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movq	48(%rsp), %rdx
	movq	40(%rsp), %rsi
	leaq	4(%rsp), %rdi
	call	cudaEventElapsedTime@PLT
	call	clock@PLT
	movq	8(%rsp), %rdi
	movl	$3000, %ecx
	movq	%rbx, %rsi
	movl	$3000, %edx
	movq	%rax, %rbp
	call	_Z12cpuTransposePfS_ii
	call	clock@PLT
	leaq	.LC2(%rip), %rsi
	movq	%r12, %rdi
	subq	%rbp, %rax
	leaq	.LC3(%rip), %rbp
	cvtsi2sdq	%rax, %xmm0
	mulsd	.LC0(%rip), %xmm0
	divsd	.LC1(%rip), %xmm0
	movq	%xmm0, %r14
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	cvtss2sd	(%rsp), %xmm0
	movq	%rax, %rdi
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	movq	%rbp, %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%rax, %rdi
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
	leaq	.LC4(%rip), %rsi
	movq	%r12, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	cvtss2sd	4(%rsp), %xmm0
	movq	%rax, %rdi
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	movq	%rbp, %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%rax, %rdi
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
	leaq	.LC5(%rip), %rsi
	movq	%r12, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%r14, %xmm0
	movq	%rax, %rdi
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	movq	%rbp, %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%rax, %rdi
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
	movq	8(%rsp), %rdi
	call	cudaFreeHost@PLT
	movq	%rbx, %rdi
	call	free@PLT
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	movq	16(%rsp), %rdi
	call	cudaFree@PLT
	movq	88(%rsp), %rax
	subq	%fs:40, %rax
	je	.L28
	call	__stack_chk_fail@PLT
.L28:
	addq	$104, %rsp
	.cfi_def_cfa_offset 40
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3636:
	.size	main, .-main
	.section	.rodata.str1.1
.LC6:
	.string	"_Z19sharedMem_transposePfS_ii"
.LC7:
	.string	"_Z9transposePfS_ii"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3666:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC6(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z19sharedMem_transposePfS_ii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC7(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z9transposePfS_ii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3666:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst8,"aM",@progbits,8
	.align 8
.LC0:
	.long	0
	.long	1083129856
	.align 8
.LC1:
	.long	0
	.long	1093567616
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <iostream>
#include <ctime>
#include <hip/hip_runtime.h>


using namespace std;

#define TILE_WIDTH 100 // for shared kernel

// CPU computation

__host__ void cpuTranspose(float* M, float* R, int dim1, int dim2){

	for (int i = 0; i < dim1; i++){
		for (int j = 0; j < dim2; j++){
			R[j*dim2 + i] = M[i*dim2 + j];
		}
	}
}

// NAIVE APPROACH - global memory access only
__global__ void transpose(float* M, float* R, int dim1, int dim2){

	int column = blockDim.x* blockIdx.x + threadIdx.x;
	int row = blockDim.y * blockIdx.y + threadIdx.y;

	if(column < dim2 && row < dim1){
		R[column*dim2 + row] = M[column + row*dim2];
	}

	// __syncthreads() not needed above as only non-conflicting read/write operations occuring
}

// SHARED MEM APROACH - use shared memory
__global__ void sharedMem_transpose(float* M, float* R, int dim1, int dim2){

	// fill data into shared memory
	__shared__ float M_Shared[TILE_WIDTH][TILE_WIDTH];

	int column = TILE_WIDTH * blockIdx.x + threadIdx.x;
	int row = TILE_WIDTH * blockIdx.y + threadIdx.y;
	
	int index_in = row*dim2 + column;
	int index_out = column*dim2 + row;


	if(row < dim1 && column < dim2 && index_in < dim1*dim2){
		M_Shared[threadIdx.y][threadIdx.x] = M[index_in];
	}
	__syncthreads(); // transfer to global mem after all threads finish computation

	if(row < dim1 && column < dim2 && index_out < dim1*dim2){
		R[index_out] = M_Shared[threadIdx.y][threadIdx.x];
	}
}

int main(void){

	int const dim1 = 3000;
	int const dim2 = 3000;

	float *M_h;
	float *R_h;
	float *M_d;
	float *R_d;

	size_t size = dim1*dim2*sizeof(float);

	hipHostMalloc((float**)&M_h,size, hipHostMallocDefault); //page locked host mem allocation
	R_h = (float*)malloc(size);
	hipMalloc((float **)&M_d, size);


	// init matrix
	for (int i = 0; i < dim1*dim2; ++i) {
		M_h[i]=i;
	}

	// asynchronous mem copies can only happen from pinned memory (direct RAM transfer)
	// CPU cannot be held up in mem copies for async copy
	hipMemcpyAsync(M_d,M_h,size,hipMemcpyHostToDevice);
	hipMalloc((float**)&R_d,size);
	hipMemset(R_d,0,size);


	// init kernel

	// TILE_WIDTH is chosen as per shared memory availaibility in a block
	// TILE_WIDTH doesn't have much use for naive access and we could lump computatiom into fewer blocks.
	int threadNumX = TILE_WIDTH;
	int threadNumY = TILE_WIDTH;
	int blockNumX = dim1 / TILE_WIDTH + (dim1%TILE_WIDTH == 0 ? 0 : 1 );
	int blockNumY = dim2 / TILE_WIDTH + (dim2%TILE_WIDTH == 0 ? 0 : 1 );

	dim3 blockSize(threadNumX,threadNumY);
	dim3 gridSize(blockNumX, blockNumY);

	// CUDA TIMER to Measure the performance
	hipEvent_t start_naive, start_shared, stop_shared, stop_naive;
	
	float elapsedTime1, elapsedTime2;
	hipEventCreate(&start_naive);
	hipEventCreate(&stop_naive);
	hipEventCreate(&start_shared);
	hipEventCreate(&stop_shared);

	hipEventRecord(start_naive, 0);

	transpose<<<gridSize,blockSize>>>(M_d,R_d,dim1,dim2);

	hipEventRecord(stop_naive, 0);
	hipEventSynchronize(stop_naive);
	hipEventElapsedTime(&elapsedTime1, start_naive, stop_naive);

	hipEventRecord(start_shared,0);

	sharedMem_transpose<<<gridSize,blockSize>>>(M_d,R_d,dim1,dim2);

	hipEventRecord(stop_shared, 0);
	hipEventSynchronize(stop_shared);
	hipEventElapsedTime(&elapsedTime2, start_shared, stop_shared);

	clock_t begin = clock();

    cpuTranspose(M_h, R_h, dim1, dim2); //matrix multiplication on cpu
    
    clock_t end = clock();
    double elapsedTime3 = (double)1000*(end - begin) / CLOCKS_PER_SEC;

	cout <<"Time for the NAIVE kernel: "<<elapsedTime1<<" ms"<<endl;
	cout <<"Time for the SHARED kernel: "<<elapsedTime2<<" ms"<<endl;
	cout <<"Time for the CPU code "<<elapsedTime3<<" ms"<<endl;


	hipHostFree(M_h);
	free(R_h);
	hipFree(R_d);
	hipFree(M_d);
	return 0;
}

	.text
	.file	"transpose.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z12cpuTransposePfS_ii          # -- Begin function _Z12cpuTransposePfS_ii
	.type	_Z12cpuTransposePfS_ii,@function
_Z12cpuTransposePfS_ii:                 # @_Z12cpuTransposePfS_ii
	.cfi_startproc
# %bb.0:
	testl	%edx, %edx
	jle	.LBB0_7
# %bb.1:                                # %.preheader.lr.ph
	pushq	%r14
	.cfi_def_cfa_offset 16
	pushq	%rbx
	.cfi_def_cfa_offset 24
	.cfi_offset %rbx, -24
	.cfi_offset %r14, -16
	movslq	%ecx, %rax
	movl	%edx, %edx
	movl	%eax, %r8d
	shlq	$2, %rax
	xorl	%r9d, %r9d
	xorl	%r10d, %r10d
.LBB0_2:                                # %.preheader
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB0_4 Depth 2
	testl	%ecx, %ecx
	jle	.LBB0_5
# %bb.3:                                # %.lr.ph
                                        #   in Loop: Header=BB0_2 Depth=1
	movl	%r9d, %r11d
	leaq	(%rdi,%r11,4), %r11
	movq	%rsi, %rbx
	xorl	%r14d, %r14d
.LBB0_4:                                #   Parent Loop BB0_2 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movss	(%r11,%r14,4), %xmm0            # xmm0 = mem[0],zero,zero,zero
	movss	%xmm0, (%rbx)
	incq	%r14
	addq	%rax, %rbx
	cmpq	%r14, %r8
	jne	.LBB0_4
.LBB0_5:                                # %._crit_edge
                                        #   in Loop: Header=BB0_2 Depth=1
	incq	%r10
	addl	%ecx, %r9d
	addq	$4, %rsi
	cmpq	%rdx, %r10
	jne	.LBB0_2
# %bb.6:
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	.cfi_restore %rbx
	.cfi_restore %r14
.LBB0_7:                                # %._crit_edge17
	retq
.Lfunc_end0:
	.size	_Z12cpuTransposePfS_ii, .Lfunc_end0-_Z12cpuTransposePfS_ii
	.cfi_endproc
                                        # -- End function
	.globl	_Z24__device_stub__transposePfS_ii # -- Begin function _Z24__device_stub__transposePfS_ii
	.type	_Z24__device_stub__transposePfS_ii,@function
_Z24__device_stub__transposePfS_ii:     # @_Z24__device_stub__transposePfS_ii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z9transposePfS_ii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z24__device_stub__transposePfS_ii, .Lfunc_end1-_Z24__device_stub__transposePfS_ii
	.cfi_endproc
                                        # -- End function
	.globl	_Z34__device_stub__sharedMem_transposePfS_ii # -- Begin function _Z34__device_stub__sharedMem_transposePfS_ii
	.type	_Z34__device_stub__sharedMem_transposePfS_ii,@function
_Z34__device_stub__sharedMem_transposePfS_ii: # @_Z34__device_stub__sharedMem_transposePfS_ii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z19sharedMem_transposePfS_ii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z34__device_stub__sharedMem_transposePfS_ii, .Lfunc_end2-_Z34__device_stub__sharedMem_transposePfS_ii
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0                          # -- Begin function main
.LCPI3_0:
	.quad	0x408f400000000000              # double 1000
.LCPI3_1:
	.quad	0x412e848000000000              # double 1.0E+6
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	subq	$80, %rsp
	.cfi_def_cfa_offset 112
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	64(%rsp), %rbx
	xorl	%r14d, %r14d
	movl	$36000000, %esi                 # imm = 0x2255100
	movq	%rbx, %rdi
	xorl	%edx, %edx
	callq	hipHostMalloc
	movq	%rsp, %rdi
	movl	$36000000, %esi                 # imm = 0x2255100
	callq	hipMalloc
	movq	(%rbx), %rsi
.LBB3_1:                                # =>This Inner Loop Header: Depth=1
	xorps	%xmm0, %xmm0
	cvtsi2ss	%r14d, %xmm0
	movss	%xmm0, (%rsi,%r14,4)
	incq	%r14
	cmpq	$9000000, %r14                  # imm = 0x895440
	jne	.LBB3_1
# %bb.2:
	movabsq	$429496729700, %rbx             # imm = 0x6400000064
	movabsq	$128849018910, %r14             # imm = 0x1E0000001E
	movq	(%rsp), %rdi
	movl	$36000000, %edx                 # imm = 0x2255100
	movl	$1, %ecx
	xorl	%r8d, %r8d
	callq	hipMemcpyAsync
	leaq	24(%rsp), %r15
	movl	$36000000, %esi                 # imm = 0x2255100
	movq	%r15, %rdi
	callq	hipMalloc
	movq	(%r15), %rdi
	movl	$36000000, %edx                 # imm = 0x2255100
	xorl	%esi, %esi
	callq	hipMemset
	leaq	56(%rsp), %r15
	movq	%r15, %rdi
	callq	hipEventCreate
	leaq	8(%rsp), %rdi
	callq	hipEventCreate
	leaq	40(%rsp), %rdi
	callq	hipEventCreate
	leaq	16(%rsp), %rdi
	callq	hipEventCreate
	movq	(%r15), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	%r14, %rdi
	movl	$1, %esi
	movq	%rbx, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB3_4
# %bb.3:
	movq	(%rsp), %rdi
	movq	24(%rsp), %rsi
	movl	$3000, %edx                     # imm = 0xBB8
	movl	$3000, %ecx                     # imm = 0xBB8
	callq	_Z24__device_stub__transposePfS_ii
.LBB3_4:
	movq	8(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	8(%rsp), %rdi
	callq	hipEventSynchronize
	movq	56(%rsp), %rsi
	movq	8(%rsp), %rdx
	leaq	36(%rsp), %rdi
	callq	hipEventElapsedTime
	movq	40(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	%r14, %rdi
	movl	$1, %esi
	movq	%rbx, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB3_6
# %bb.5:
	movq	(%rsp), %rdi
	movq	24(%rsp), %rsi
	movl	$3000, %edx                     # imm = 0xBB8
	movl	$3000, %ecx                     # imm = 0xBB8
	callq	_Z34__device_stub__sharedMem_transposePfS_ii
.LBB3_6:                                # %_Z12cpuTransposePfS_ii.exit
	movq	16(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	16(%rsp), %rdi
	callq	hipEventSynchronize
	movq	40(%rsp), %rsi
	movq	16(%rsp), %rdx
	leaq	76(%rsp), %rbx
	movq	%rbx, %rdi
	callq	hipEventElapsedTime
	callq	clock
	movq	%rax, %r14
	callq	clock
	subq	%r14, %rax
	cvtsi2sd	%rax, %xmm0
	mulsd	.LCPI3_0(%rip), %xmm0
	divsd	.LCPI3_1(%rip), %xmm0
	movsd	%xmm0, 48(%rsp)                 # 8-byte Spill
	movl	$_ZSt4cout, %edi
	movl	$.L.str, %esi
	movl	$27, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	xorps	%xmm0, %xmm0
	cvtss2sd	36(%rsp), %xmm0
	movl	$_ZSt4cout, %edi
	callq	_ZNSo9_M_insertIdEERSoT_
	movq	%rax, %r14
	movl	$.L.str.1, %esi
	movl	$3, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	(%r14), %rax
	movq	-24(%rax), %rdi
	addq	%r14, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%r14, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movl	$_ZSt4cout, %edi
	movl	$.L.str.2, %esi
	movl	$28, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	xorps	%xmm0, %xmm0
	cvtss2sd	(%rbx), %xmm0
	movl	$_ZSt4cout, %edi
	callq	_ZNSo9_M_insertIdEERSoT_
	movq	%rax, %rbx
	movl	$.L.str.1, %esi
	movl	$3, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	(%rbx), %rax
	movq	-24(%rax), %rdi
	addq	%rbx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%rbx, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movl	$_ZSt4cout, %edi
	movl	$.L.str.3, %esi
	movl	$22, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	$_ZSt4cout, %edi
	movsd	48(%rsp), %xmm0                 # 8-byte Reload
                                        # xmm0 = mem[0],zero
	callq	_ZNSo9_M_insertIdEERSoT_
	movq	%rax, %rbx
	movl	$.L.str.1, %esi
	movl	$3, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	(%rbx), %rax
	movq	-24(%rax), %rdi
	addq	%rbx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%rbx, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movq	64(%rsp), %rdi
	callq	hipHostFree
	movq	24(%rsp), %rdi
	callq	hipFree
	movq	(%rsp), %rdi
	callq	hipFree
	xorl	%eax, %eax
	addq	$80, %rsp
	.cfi_def_cfa_offset 32
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	main, .Lfunc_end3-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB4_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB4_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z9transposePfS_ii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z19sharedMem_transposePfS_ii, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end4:
	.size	__hip_module_ctor, .Lfunc_end4-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB5_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB5_2:
	retq
.Lfunc_end5:
	.size	__hip_module_dtor, .Lfunc_end5-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z9transposePfS_ii,@object      # @_Z9transposePfS_ii
	.section	.rodata,"a",@progbits
	.globl	_Z9transposePfS_ii
	.p2align	3, 0x0
_Z9transposePfS_ii:
	.quad	_Z24__device_stub__transposePfS_ii
	.size	_Z9transposePfS_ii, 8

	.type	_Z19sharedMem_transposePfS_ii,@object # @_Z19sharedMem_transposePfS_ii
	.globl	_Z19sharedMem_transposePfS_ii
	.p2align	3, 0x0
_Z19sharedMem_transposePfS_ii:
	.quad	_Z34__device_stub__sharedMem_transposePfS_ii
	.size	_Z19sharedMem_transposePfS_ii, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"Time for the NAIVE kernel: "
	.size	.L.str, 28

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	" ms"
	.size	.L.str.1, 4

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"Time for the SHARED kernel: "
	.size	.L.str.2, 29

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"Time for the CPU code "
	.size	.L.str.3, 23

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z9transposePfS_ii"
	.size	.L__unnamed_1, 19

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z19sharedMem_transposePfS_ii"
	.size	.L__unnamed_2, 30

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z24__device_stub__transposePfS_ii
	.addrsig_sym _Z34__device_stub__sharedMem_transposePfS_ii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z9transposePfS_ii
	.addrsig_sym _Z19sharedMem_transposePfS_ii
	.addrsig_sym _ZSt4cout
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z9transposePfS_ii      ; -- Begin function _Z9transposePfS_ii
	.globl	_Z9transposePfS_ii
	.p2align	8
	.type	_Z9transposePfS_ii,@function
_Z9transposePfS_ii:                     ; @_Z9transposePfS_ii
; %bb.0:
	s_clause 0x1
	s_load_b32 s4, s[0:1], 0x24
	s_load_b64 s[2:3], s[0:1], 0x10
	v_and_b32_e32 v2, 0x3ff, v0
	v_bfe_u32 v3, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s5, s4, 16
	s_and_b32 s4, s4, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[0:1], null, s14, s4, v[2:3]
	v_mad_u64_u32 v[1:2], null, s15, s5, v[3:4]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_i32_e32 vcc_lo, s3, v0
	v_cmp_gt_i32_e64 s2, s2, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, vcc_lo, s2
	s_and_saveexec_b32 s4, s2
	s_cbranch_execz .LBB0_2
; %bb.1:
	s_load_b128 s[4:7], s[0:1], 0x0
	v_mad_u64_u32 v[2:3], null, v1, s3, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s4, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
	global_load_b32 v4, v[2:3], off
	v_mad_u64_u32 v[2:3], null, v0, s3, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[0:1], 2, v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s6, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b32 v[0:1], v4, off
.LBB0_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z9transposePfS_ii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 5
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z9transposePfS_ii, .Lfunc_end0-_Z9transposePfS_ii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 228
; NumSgprs: 18
; NumVgprs: 5
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 5
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z19sharedMem_transposePfS_ii ; -- Begin function _Z19sharedMem_transposePfS_ii
	.globl	_Z19sharedMem_transposePfS_ii
	.p2align	8
	.type	_Z19sharedMem_transposePfS_ii,@function
_Z19sharedMem_transposePfS_ii:          ; @_Z19sharedMem_transposePfS_ii
; %bb.0:
	v_and_b32_e32 v5, 0x3ff, v0
	s_clause 0x1
	s_load_b64 s[2:3], s[0:1], 0x10
	s_load_b128 s[4:7], s[0:1], 0x0
	v_bfe_u32 v0, v0, 10, 10
	v_mad_u64_u32 v[1:2], null, 0x64, s14, v[5:6]
	v_lshlrev_b32_e32 v5, 2, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[2:3], null, 0x64, s15, v[0:1]
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_i32_e64 s0, s3, v1
	v_mad_u64_u32 v[3:4], null, v2, s3, v[1:2]
	v_cmp_gt_i32_e32 vcc_lo, s2, v2
	s_mul_i32 s2, s3, s2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	s_and_b32 s0, vcc_lo, s0
	v_cmp_gt_i32_e64 s1, s2, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s8, s0, s1
	s_and_saveexec_b32 s1, s8
	s_cbranch_execz .LBB1_2
; %bb.1:
	v_ashrrev_i32_e32 v4, 31, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	v_add_co_u32 v3, vcc_lo, s4, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
	global_load_b32 v3, v[3:4], off
	v_mad_u32_u24 v4, 0x190, v0, v5
	s_waitcnt vmcnt(0)
	ds_store_b32 v4, v3
.LBB1_2:
	s_or_b32 exec_lo, exec_lo, s1
	v_mad_u64_u32 v[3:4], null, v1, s3, v[2:3]
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmp_gt_i32_e32 vcc_lo, s2, v3
	s_and_b32 s0, s0, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_4
; %bb.3:
	v_mad_u32_u24 v0, 0x190, v0, v5
	v_ashrrev_i32_e32 v4, 31, v3
	ds_load_b32 v2, v0
	v_lshlrev_b64 v[0:1], 2, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s6, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
	s_waitcnt lgkmcnt(0)
	global_store_b32 v[0:1], v2, off
.LBB1_4:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z19sharedMem_transposePfS_ii
		.amdhsa_group_segment_fixed_size 40000
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 24
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 7
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z19sharedMem_transposePfS_ii, .Lfunc_end1-_Z19sharedMem_transposePfS_ii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 312
; NumSgprs: 18
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 40000 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z9transposePfS_ii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z9transposePfS_ii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     5
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
    .group_segment_fixed_size: 40000
    .kernarg_segment_align: 8
    .kernarg_segment_size: 24
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z19sharedMem_transposePfS_ii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z19sharedMem_transposePfS_ii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     7
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
