#define BLOCK_SIZE 128
#define DATALEN_PER_BLOCK (BLOCK_SIZE * 2)
#include <stdio.h>

/**
    this works, because 
    last warp is like simd ? when is simd or not?
    volatile because each instruct deps on last result, why others not need ?
    **/
__device__ void warpReduce(volatile float *sdata, int tid)
{
    sdata[tid] += sdata[tid + 32];
    sdata[tid] += sdata[tid + 16];
    sdata[tid] += sdata[tid + 8];
    sdata[tid] += sdata[tid + 4];
    sdata[tid] += sdata[tid + 2];
    sdata[tid] += sdata[tid + 1];
}

__global__ void reductionKernel(float *a, float *r)
{
    int blocksz = blockDim.x;
    int tid = threadIdx.x;
    int bid = blockIdx.x;

    int i1 = DATALEN_PER_BLOCK * bid + tid;
    int i2 = i1 + blocksz;

    __shared__ float shared_data[BLOCK_SIZE];

    shared_data[tid] = a[i1] + a[i2];
    //shared_data[tid + blocksz] = a[i2];

    __syncthreads();

    for (int i = blocksz / 2; i > 32; i >>= 1) {
        if (tid < i) {
            shared_data[tid] += shared_data[tid + i];
        }

        __syncthreads();
    }

    if (tid < 32)
        warpReduce(shared_data, tid);

    r[bid] = shared_data[0];
}


float reduction(float *a, size_t len)
{
    int data_len_per_block = DATALEN_PER_BLOCK;
    float *dr = nullptr;
    float *da = nullptr;
    float *r = new float[data_len_per_block * sizeof(float)];
    size_t tlen = len;

    cudaMalloc(&da, sizeof(float) * len);

    for (int k = 0; k < 20; k++) {
        len = tlen;
        cudaMemcpy(da, a, sizeof(float) * len, cudaMemcpyHostToDevice);

        while (len > data_len_per_block) {
            len /= data_len_per_block;

            dim3 threads(BLOCK_SIZE);
            dim3 grids(len);

            reductionKernel<<<grids, threads>>>(da, da);
        }
    }

    cudaMemcpy(r, da, len * sizeof(float), cudaMemcpyDeviceToHost);

    if (len > 0) {
        for (int i = 1; i < len; i++)
            r[0] += r[i];
    }

    int rr = r[0];

    cudaFree(&da);
    cudaFree(&dr);
    free(r);
    return rr;
}


int main(int argc, char *argv[])
{
    int len = 8192;

    if (argc > 1)
        len = atoi(argv[1]);

    printf("len %d\n", len);

    float *a = new float[len];

    for (int i = 0; i < len; i++)
        a[i] = 1.0;

    float r = reduction(a, len);
    printf("%.2f\n", r);
    return 0;
}
	.file	"tmpxft_0021ca68_00000000-6_reduction_unroll_warp.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2032:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2032:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z10warpReducePVfi
	.type	_Z10warpReducePVfi, @function
_Z10warpReducePVfi:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2027:
	.size	_Z10warpReducePVfi, .-_Z10warpReducePVfi
	.globl	_Z37__device_stub__Z15reductionKernelPfS_PfS_
	.type	_Z37__device_stub__Z15reductionKernelPfS_PfS_, @function
_Z37__device_stub__Z15reductionKernelPfS_PfS_:
.LFB2054:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 8(%rsp)
	leaq	32(%rsp), %rcx
	leaq	24(%rsp), %rdx
	movq	%rsi, (%rsp)
	leaq	40(%rsp), %rdi
	leaq	52(%rsp), %rsi
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 48(%rsp)
	movq	%rax, 88(%rsp)
	movq	%rsp, %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L4
	pushq	32(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z15reductionKernelPfS_(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 144
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	104(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L4:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L6
	call	__stack_chk_fail@PLT
.L6:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2054:
	.size	_Z37__device_stub__Z15reductionKernelPfS_PfS_, .-_Z37__device_stub__Z15reductionKernelPfS_PfS_
	.globl	_Z15reductionKernelPfS_
	.type	_Z15reductionKernelPfS_, @function
_Z15reductionKernelPfS_:
.LFB2055:
	.cfi_startproc
	endbr64
	jmp	_Z37__device_stub__Z15reductionKernelPfS_PfS_
	.cfi_endproc
.LFE2055:
	.size	_Z15reductionKernelPfS_, .-_Z15reductionKernelPfS_
	.globl	_Z9reductionPfm
	.type	_Z9reductionPfm, @function
_Z9reductionPfm:
.LFB2028:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movabsq	$4294967424, %r15
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movl	$20, %r12d
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movq	%rsi, %rbp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	leaq	0(,%rbp,4), %r14
	subq	$72, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 8(%rsp)
	movl	$4096, %edi
	movq	%fs:40, %rax
	movq	%rax, 56(%rsp)
	xorl	%eax, %eax
	xorl	%eax, %eax
	movq	%rax, 16(%rsp)
	movq	%rax, 24(%rsp)
	call	_Znam@PLT
	movq	%r14, %rsi
	movq	%rax, %rbx
	leaq	24(%rsp), %rax
	movq	%rax, %rdi
	movq	%rax, (%rsp)
	call	cudaMalloc@PLT
.L14:
	movq	8(%rsp), %rsi
	movq	24(%rsp), %rdi
	movq	%r14, %rdx
	movq	%rbp, %r13
	movl	$1, %ecx
	call	cudaMemcpy@PLT
.L11:
	cmpq	$256, %r13
	jbe	.L23
	shrq	$8, %r13
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	%r15, %rdx
	movabsq	$4294967297, %rax
	movl	%r13d, 44(%rsp)
	movl	$1, %ecx
	movq	%rax, 48(%rsp)
	movq	44(%rsp), %rdi
	movl	52(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L11
	movq	24(%rsp), %rdi
	movq	%rdi, %rsi
	call	_Z37__device_stub__Z15reductionKernelPfS_PfS_
	jmp	.L11
.L23:
	decl	%r12d
	jne	.L14
	movq	24(%rsp), %rsi
	leaq	0(,%r13,4), %rdx
	movl	$2, %ecx
	movq	%rbx, %rdi
	call	cudaMemcpy@PLT
	testq	%r13, %r13
	jne	.L19
.L17:
	cvttss2sil	(%rbx), %ebp
	movq	(%rsp), %rdi
	call	cudaFree@PLT
	leaq	16(%rsp), %rdi
	call	cudaFree@PLT
	movq	%rbx, %rdi
	call	free@PLT
	cvtsi2ssl	%ebp, %xmm0
	movq	56(%rsp), %rax
	subq	%fs:40, %rax
	je	.L18
	call	__stack_chk_fail@PLT
.L19:
	xorl	%eax, %eax
.L15:
	incq	%rax
	movss	(%rbx), %xmm0
	cmpq	%rax, %r13
	je	.L17
	addss	(%rbx,%rax,4), %xmm0
	movss	%xmm0, (%rbx)
	jmp	.L15
.L18:
	addq	$72, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2028:
	.size	_Z9reductionPfm, .-_Z9reductionPfm
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"len %d\n"
.LC2:
	.string	"%.2f\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2029:
	.cfi_startproc
	endbr64
	decl	%edi
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	pushq	%rbx
	.cfi_def_cfa_offset 24
	.cfi_offset 3, -24
	movl	$8192, %ebx
	pushq	%rcx
	.cfi_def_cfa_offset 32
	jle	.L25
	movq	8(%rsi), %rdi
	call	atoi@PLT
	movl	%eax, %ebx
.L25:
	movl	%ebx, %edx
	leaq	.LC0(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movslq	%ebx, %rbp
	movabsq	$2305843009213693950, %rax
	cmpq	%rbp, %rax
	jb	.L26
	leaq	0(,%rbp,4), %rdi
	call	_Znam@PLT
	movss	.LC1(%rip), %xmm0
	movq	%rax, %rdi
	xorl	%eax, %eax
	jmp	.L27
.L26:
	call	__cxa_throw_bad_array_new_length@PLT
.L27:
	cmpl	%eax, %ebx
	jle	.L32
	movss	%xmm0, (%rdi,%rax,4)
	incq	%rax
	jmp	.L27
.L32:
	movq	%rbp, %rsi
	call	_Z9reductionPfm
	leaq	.LC2(%rip), %rsi
	movl	$2, %edi
	movb	$1, %al
	cvtss2sd	%xmm0, %xmm0
	call	__printf_chk@PLT
	popq	%rdx
	.cfi_def_cfa_offset 24
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2029:
	.size	main, .-main
	.section	.rodata.str1.1
.LC3:
	.string	"_Z15reductionKernelPfS_"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2057:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC3(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z15reductionKernelPfS_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2057:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst4,"aM",@progbits,4
	.align 4
.LC1:
	.long	1065353216
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#define BLOCK_SIZE 128
#define DATALEN_PER_BLOCK (BLOCK_SIZE * 2)

#include <hip/hip_runtime.h>
#include <stdio.h>

/**
    this works, because 
    last warp is like simd ? when is simd or not?
    volatile because each instruct deps on last result, why others not need ?
    **/
__device__ void warpReduce(volatile float *sdata, int tid)
{
    sdata[tid] += sdata[tid + 32];
    sdata[tid] += sdata[tid + 16];
    sdata[tid] += sdata[tid + 8];
    sdata[tid] += sdata[tid + 4];
    sdata[tid] += sdata[tid + 2];
    sdata[tid] += sdata[tid + 1];
}

__global__ void reductionKernel(float *a, float *r)
{
    int blocksz = blockDim.x;
    int tid = threadIdx.x;
    int bid = blockIdx.x;

    int i1 = DATALEN_PER_BLOCK * bid + tid;
    int i2 = i1 + blocksz;

    __shared__ float shared_data[BLOCK_SIZE];

    shared_data[tid] = a[i1] + a[i2];
    //shared_data[tid + blocksz] = a[i2];

    __syncthreads();

    for (int i = blocksz / 2; i > 32; i >>= 1) {
        if (tid < i) {
            shared_data[tid] += shared_data[tid + i];
        }

        __syncthreads();
    }

    if (tid < 32)
        warpReduce(shared_data, tid);

    r[bid] = shared_data[0];
}


float reduction(float *a, size_t len)
{
    int data_len_per_block = DATALEN_PER_BLOCK;
    float *dr = nullptr;
    float *da = nullptr;
    float *r = new float[data_len_per_block * sizeof(float)];
    size_t tlen = len;

    hipMalloc(&da, sizeof(float) * len);

    for (int k = 0; k < 20; k++) {
        len = tlen;
        hipMemcpy(da, a, sizeof(float) * len, hipMemcpyHostToDevice);

        while (len > data_len_per_block) {
            len /= data_len_per_block;

            dim3 threads(BLOCK_SIZE);
            dim3 grids(len);

            reductionKernel<<<grids, threads>>>(da, da);
        }
    }

    hipMemcpy(r, da, len * sizeof(float), hipMemcpyDeviceToHost);

    if (len > 0) {
        for (int i = 1; i < len; i++)
            r[0] += r[i];
    }

    int rr = r[0];

    hipFree(&da);
    hipFree(&dr);
    free(r);
    return rr;
}


int main(int argc, char *argv[])
{
    int len = 8192;

    if (argc > 1)
        len = atoi(argv[1]);

    printf("len %d\n", len);

    float *a = new float[len];

    for (int i = 0; i < len; i++)
        a[i] = 1.0;

    float r = reduction(a, len);
    printf("%.2f\n", r);
    return 0;
}
	.text
	.file	"reduction_unroll_warp.hip"
	.globl	_Z30__device_stub__reductionKernelPfS_ # -- Begin function _Z30__device_stub__reductionKernelPfS_
	.type	_Z30__device_stub__reductionKernelPfS_,@function
_Z30__device_stub__reductionKernelPfS_: # @_Z30__device_stub__reductionKernelPfS_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	16(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z15reductionKernelPfS_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z30__device_stub__reductionKernelPfS_, .Lfunc_end0-_Z30__device_stub__reductionKernelPfS_
	.cfi_endproc
                                        # -- End function
	.globl	_Z9reductionPfm                 # -- Begin function _Z9reductionPfm
	.type	_Z9reductionPfm,@function
_Z9reductionPfm:                        # @_Z9reductionPfm
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$56, %rsp
	.cfi_def_cfa_offset 112
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%rsi, %r12
	movq	%rdi, 16(%rsp)                  # 8-byte Spill
	movabsq	$4294967296, %rbp               # imm = 0x100000000
	xorl	%ebx, %ebx
	movq	%rbx, 48(%rsp)
	leaq	8(%rsp), %r13
	movq	%rbx, (%r13)
	movl	$4096, %edi                     # imm = 0x1000
	callq	_Znam
	movq	%rax, 32(%rsp)                  # 8-byte Spill
	leaq	(,%r12,4), %rsi
	movq	%r13, %rdi
	movq	%rsi, 40(%rsp)                  # 8-byte Spill
	callq	hipMalloc
	leaq	128(%rbp), %r13
.LBB1_1:                                # =>This Loop Header: Depth=1
                                        #     Child Loop BB1_3 Depth 2
	movq	8(%rsp), %rdi
	movq	16(%rsp), %rsi                  # 8-byte Reload
	movq	40(%rsp), %rdx                  # 8-byte Reload
	movl	$1, %ecx
	callq	hipMemcpy
	movq	%r12, %r15
	cmpq	$257, %r12                      # imm = 0x101
	jb	.LBB1_6
# %bb.2:                                # %.lr.ph.preheader
                                        #   in Loop: Header=BB1_1 Depth=1
	movq	%r12, %r14
	movq	%r12, %r15
.LBB1_3:                                # %.lr.ph
                                        #   Parent Loop BB1_1 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	shrq	$8, %r15
	movl	%r15d, %edi
	orq	%rbp, %rdi
	movl	$1, %esi
	movq	%r13, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_5
# %bb.4:                                #   in Loop: Header=BB1_3 Depth=2
	movq	8(%rsp), %rdi
	movq	%rdi, %rsi
	callq	_Z30__device_stub__reductionKernelPfS_
.LBB1_5:                                #   in Loop: Header=BB1_3 Depth=2
	cmpq	$65791, %r14                    # imm = 0x100FF
	movq	%r15, %r14
	ja	.LBB1_3
.LBB1_6:                                # %._crit_edge
                                        #   in Loop: Header=BB1_1 Depth=1
	incl	%ebx
	cmpl	$20, %ebx
	jne	.LBB1_1
# %bb.7:
	movq	8(%rsp), %rsi
	leaq	(,%r15,4), %rdx
	movq	32(%rsp), %rbx                  # 8-byte Reload
	movq	%rbx, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movss	(%rbx), %xmm0                   # xmm0 = mem[0],zero,zero,zero
	cmpq	$2, %r15
	jb	.LBB1_11
# %bb.8:                                # %.lr.ph39.preheader
	movl	$1, %eax
.LBB1_9:                                # %.lr.ph39
                                        # =>This Inner Loop Header: Depth=1
	addss	(%rbx,%rax,4), %xmm0
	incq	%rax
	cmpq	%rax, %r15
	jne	.LBB1_9
# %bb.10:                               # %.loopexit.loopexit
	movss	%xmm0, (%rbx)
.LBB1_11:                               # %.loopexit
	movaps	%xmm0, 16(%rsp)                 # 16-byte Spill
	leaq	8(%rsp), %rdi
	callq	hipFree
	leaq	48(%rsp), %rdi
	callq	hipFree
	movq	%rbx, %rdi
	callq	free
	cvttps2dq	16(%rsp), %xmm0         # 16-byte Folded Reload
	cvtdq2ps	%xmm0, %xmm0
	addq	$56, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z9reductionPfm, .Lfunc_end1-_Z9reductionPfm
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%rbx
	.cfi_def_cfa_offset 24
	pushq	%rax
	.cfi_def_cfa_offset 32
	.cfi_offset %rbx, -24
	.cfi_offset %rbp, -16
	movl	$8192, %ebp                     # imm = 0x2000
	cmpl	$2, %edi
	jl	.LBB2_2
# %bb.1:
	movq	8(%rsi), %rdi
	callq	atoi
	movl	%eax, %ebp
.LBB2_2:
	movl	$.L.str, %edi
	movl	%ebp, %esi
	xorl	%eax, %eax
	callq	printf
	movslq	%ebp, %rbx
	testl	%ebx, %ebx
	js	.LBB2_3
# %bb.5:
	leaq	(,%rbx,4), %rdi
	callq	_Znam
	testl	%ebx, %ebx
	je	.LBB2_4
# %bb.6:                                # %.lr.ph.preheader
	movl	%ebp, %ecx
	xorl	%edx, %edx
.LBB2_7:                                # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	movl	$1065353216, (%rax,%rdx,4)      # imm = 0x3F800000
	incq	%rdx
	cmpq	%rdx, %rcx
	jne	.LBB2_7
	jmp	.LBB2_4
.LBB2_3:                                # %.thread
	movq	$-1, %rdi
	callq	_Znam
.LBB2_4:                                # %._crit_edge
	movq	%rax, %rdi
	movq	%rbx, %rsi
	callq	_Z9reductionPfm
	cvtss2sd	%xmm0, %xmm0
	movl	$.L.str.1, %edi
	movb	$1, %al
	callq	printf
	xorl	%eax, %eax
	addq	$8, %rsp
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	main, .Lfunc_end2-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB3_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB3_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z15reductionKernelPfS_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end3:
	.size	__hip_module_ctor, .Lfunc_end3-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB4_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB4_2:
	retq
.Lfunc_end4:
	.size	__hip_module_dtor, .Lfunc_end4-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z15reductionKernelPfS_,@object # @_Z15reductionKernelPfS_
	.section	.rodata,"a",@progbits
	.globl	_Z15reductionKernelPfS_
	.p2align	3, 0x0
_Z15reductionKernelPfS_:
	.quad	_Z30__device_stub__reductionKernelPfS_
	.size	_Z15reductionKernelPfS_, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"len %d\n"
	.size	.L.str, 8

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"%.2f\n"
	.size	.L.str.1, 6

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z15reductionKernelPfS_"
	.size	.L__unnamed_1, 24

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z30__device_stub__reductionKernelPfS_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z15reductionKernelPfS_
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z15reductionKernelPfS_ ; -- Begin function _Z15reductionKernelPfS_
	.globl	_Z15reductionKernelPfS_
	.p2align	8
	.type	_Z15reductionKernelPfS_,@function
_Z15reductionKernelPfS_:                ; @_Z15reductionKernelPfS_
; %bb.0:
	s_clause 0x1
	s_load_b32 s5, s[0:1], 0x1c
	s_load_b128 s[0:3], s[0:1], 0x0
	s_mov_b32 s4, s15
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshl_add_u32 v1, s4, 8, v0
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_waitcnt lgkmcnt(0)
	s_and_b32 s5, s5, 0xffff
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	s_lshl_b32 s0, s5, 2
	s_cmpk_lt_u32 s5, 0x42
	v_add_co_u32 v3, vcc_lo, v1, s0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, 0, v2, vcc_lo
	s_clause 0x1
	global_load_b32 v2, v[1:2], off
	global_load_b32 v3, v[3:4], off
	s_waitcnt vmcnt(0)
	v_dual_add_f32 v2, v2, v3 :: v_dual_lshlrev_b32 v1, 2, v0
	ds_store_b32 v1, v2
	s_waitcnt lgkmcnt(0)
	s_barrier
.LBB0_1:                                ; =>This Inner Loop Header: Depth=1
	buffer_gl0_inv
	s_cbranch_scc1 .LBB0_5
; %bb.2:                                ; %.lr.ph
                                        ;   in Loop: Header=BB0_1 Depth=1
	s_lshr_b32 s0, s5, 1
	s_mov_b32 s1, exec_lo
	v_cmpx_gt_u32_e64 s0, v0
	s_cbranch_execz .LBB0_4
; %bb.3:                                ;   in Loop: Header=BB0_1 Depth=1
	v_lshl_add_u32 v2, s0, 2, v1
	ds_load_b32 v2, v2
	ds_load_b32 v3, v1
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v2, v2, v3
	ds_store_b32 v1, v2
.LBB0_4:                                ;   in Loop: Header=BB0_1 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_waitcnt lgkmcnt(0)
	s_barrier
	s_cmpk_lt_u32 s5, 0x84
	s_mov_b32 s5, s0
	s_branch .LBB0_1
.LBB0_5:                                ; %._crit_edge
	s_mov_b32 s1, exec_lo
	v_cmpx_gt_u32_e32 32, v0
	s_cbranch_execz .LBB0_7
; %bb.6:
	v_add_nc_u32_e32 v0, 0x80, v1
	v_cmp_ne_u32_e64 s0, -1, v1
	s_mov_b64 s[6:7], src_shared_base
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_ne_u32_e32 vcc_lo, -1, v0
	v_cndmask_b32_e64 v3, 0, s7, s0
	v_cndmask_b32_e64 v2, 0, v1, s0
	v_cndmask_b32_e32 v4, 0, v0, vcc_lo
	v_cndmask_b32_e64 v5, 0, s7, vcc_lo
	flat_load_b32 v0, v[4:5] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v5, v[2:3] glc dlc
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v4, 64, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v4
	v_cndmask_b32_e32 v4, 0, v4, vcc_lo
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v0, v0, v5
	v_cndmask_b32_e64 v5, 0, s7, vcc_lo
	flat_store_b32 v[2:3], v0 dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b32 v0, v[4:5] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v5, v[2:3] glc dlc
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v4, 32, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v4
	v_cndmask_b32_e32 v4, 0, v4, vcc_lo
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v0, v0, v5
	v_cndmask_b32_e64 v5, 0, s7, vcc_lo
	flat_store_b32 v[2:3], v0 dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b32 v0, v[4:5] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v5, v[2:3] glc dlc
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v4, 16, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v4
	v_cndmask_b32_e32 v4, 0, v4, vcc_lo
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v0, v0, v5
	v_cndmask_b32_e64 v5, 0, s7, vcc_lo
	flat_store_b32 v[2:3], v0 dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b32 v0, v[4:5] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v5, v[2:3] glc dlc
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v4, 8, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v4
	v_cndmask_b32_e32 v4, 0, v4, vcc_lo
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v0, v0, v5
	v_cndmask_b32_e64 v5, 0, s7, vcc_lo
	flat_store_b32 v[2:3], v0 dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b32 v4, v[4:5] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v5, v[2:3] glc dlc
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v0, 4, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v0
	v_cndmask_b32_e32 v0, 0, v0, vcc_lo
	v_cndmask_b32_e64 v1, 0, s7, vcc_lo
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v4, v4, v5
	flat_store_b32 v[2:3], v4 dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b32 v0, v[0:1] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v1, v[2:3] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f32_e32 v0, v0, v1
	flat_store_b32 v[2:3], v0 dlc
	s_waitcnt_vscnt null, 0x0
.LBB0_7:
	s_or_b32 exec_lo, exec_lo, s1
	v_mov_b32_e32 v0, 0
	s_ashr_i32 s5, s4, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[0:1], s[4:5], 2
	s_add_u32 s0, s2, s0
	ds_load_b32 v1, v0
	s_addc_u32 s1, s3, s1
	s_waitcnt lgkmcnt(0)
	global_store_b32 v0, v1, s[0:1]
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z15reductionKernelPfS_
		.amdhsa_group_segment_fixed_size 512
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 6
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z15reductionKernelPfS_, .Lfunc_end0-_Z15reductionKernelPfS_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 748
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 512 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         20
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         28
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         30
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         32
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         34
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         36
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         38
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         56
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         80
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 512
    .kernarg_segment_align: 8
    .kernarg_segment_size: 272
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z15reductionKernelPfS_
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z15reductionKernelPfS_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     6
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
