// Copyright (c) 2013-2019 Anton Kozhevnikov, Thomas Schulthess
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification, are permitted provided that
// the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the
//    following disclaimer.
// 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions
//    and the following disclaimer in the documentation and/or other materials provided with the distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
// WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
// ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
// OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

/** \file mul_by_veff.cu
 *
 *  \brief CUDA kernels to multiply wave-functions by effective potential.
 */

//#include "gpu/acc_common.hpp"
//#include "gpu/acc_runtime.hpp"
//
//template <typename T>
//__global__ void
//mul_by_veff_real_real_gpu_kernel(int nr__, T const* in__,T const* veff__, T* out__)
//{
//    int i = blockDim.x * blockIdx.x + threadIdx.x;
//    if (i < nr__) {
//        out__[i] = in__[i] * veff__[i];
//    }
//}
//
//template <typename T>
//__global__ void
//mul_by_veff_complex_real_gpu_kernel(int nr__, gpu_complex_type<T> const* in__, T const* veff__,
//        gpu_complex_type<T>* out__)
//{
//    int i = blockDim.x * blockIdx.x + threadIdx.x;
//    if (i < nr__) {
//        out__[i] = mul_accNumbers(veff__[i], in__[i]);
//    }
//}
//
//template <typename T>
//__global__ void
//mul_by_veff_complex_complex_gpu_kernel(int nr__, gpu_complex_type<T> const* in__, T pref__, T const* vx__,
//        T const* vy__, gpu_complex_type<T>* out__)
//{
//    int i = blockDim.x * blockIdx.x + threadIdx.x;
//    if (i < nr__) {
//        out__[i] = mul_accNumbers(in__[i], make_accComplex(vx__[i], pref__ * vy__[i]));
//    }
//}
//
//extern "C" {
//
//void
//mul_by_veff_real_real_gpu_float(int nr__, float const* in__, float const* veff__, float* out__)
//{
//    dim3 grid_t(64);
//    dim3 grid_b(num_blocks(nr__, grid_t.x));
//
//    accLaunchKernel((mul_by_veff_real_real_gpu_kernel<float>), dim3(grid_b), dim3(grid_t), 0, 0,
//            nr__, in__, veff__, out__);
//}
//
//void
//mul_by_veff_real_real_gpu_double(int nr__, double const* in__, double const* veff__, double* out__)
//{
//    dim3 grid_t(64);
//    dim3 grid_b(num_blocks(nr__, grid_t.x));
//
//    accLaunchKernel((mul_by_veff_real_real_gpu_kernel<double>), dim3(grid_b), dim3(grid_t), 0, 0,
//            nr__, in__, veff__, out__);
//}
//
//void
//mul_by_veff_complex_real_gpu_float(int nr__, gpu_complex_type<float> const* in__, float const* veff__,
//        gpu_complex_type<float>* out__)
//{
//    dim3 grid_t(64);
//    dim3 grid_b(num_blocks(nr__, grid_t.x));
//
//    accLaunchKernel((mul_by_veff_complex_real_gpu_kernel<float>), dim3(grid_b), dim3(grid_t), 0, 0,
//            nr__, in__, veff__, out__);
//}
//
//void
//mul_by_veff_complex_real_gpu_double(int nr__, gpu_complex_type<double> const* in__, double const* veff__,
//        gpu_complex_type<double>* out__)
//{
//    dim3 grid_t(64);
//    dim3 grid_b(num_blocks(nr__, grid_t.x));
//
//    accLaunchKernel((mul_by_veff_complex_real_gpu_kernel<double>), dim3(grid_b), dim3(grid_t), 0, 0,
//            nr__, in__, veff__, out__);
//}
//
//void
//mul_by_veff_complex_complex_gpu_float(int nr__, gpu_complex_type<float> const* in__, float pref__,
//    float const* vx__, float const* vy__, gpu_complex_type<float>* out__)
//{
//    dim3 grid_t(64);
//    dim3 grid_b(num_blocks(nr__, grid_t.x));
//
//    accLaunchKernel((mul_by_veff_complex_complex_gpu_kernel<float>), dim3(grid_b), dim3(grid_t), 0, 0,
//            nr__, in__, pref__, vx__, vy__, out__);
//}
//
//void
//mul_by_veff_complex_complex_gpu_double(int nr__, gpu_complex_type<double> const* in__, double pref__,
//    double const* vx__, double const* vy__, gpu_complex_type<double>* out__)
//{
//    dim3 grid_t(64);
//    dim3 grid_b(num_blocks(nr__, grid_t.x));
//
//    accLaunchKernel((mul_by_veff_complex_complex_gpu_kernel<double>), dim3(grid_b), dim3(grid_t), 0, 0,
//            nr__, in__, pref__, vx__, vy__, out__);
//}

//}



	.file	"tmpxft_002a5439_00000000-6_mul_by_veff.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2010:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2010:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2033:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	movq	%rax, %rdi
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2033:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
// Copyright (c) 2013-2019 Anton Kozhevnikov, Thomas Schulthess
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification, are permitted provided that
// the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the
//    following disclaimer.
// 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions
//    and the following disclaimer in the documentation and/or other materials provided with the distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
// WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
// ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
// OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

/** \file mul_by_veff.cu
 *
 *  \brief CUDA kernels to multiply wave-functions by effective potential.
 */

//#include "gpu/acc_common.hpp"
//#include "gpu/acc_runtime.hpp"
//
//template <typename T>
//__global__ void
//mul_by_veff_real_real_gpu_kernel(int nr__, T const* in__,T const* veff__, T* out__)
//{
//    int i = blockDim.x * blockIdx.x + threadIdx.x;
//    if (i < nr__) {
//        out__[i] = in__[i] * veff__[i];
//    }
//}
//
//template <typename T>
//__global__ void
//mul_by_veff_complex_real_gpu_kernel(int nr__, gpu_complex_type<T> const* in__, T const* veff__,
//        gpu_complex_type<T>* out__)
//{
//    int i = blockDim.x * blockIdx.x + threadIdx.x;
//    if (i < nr__) {
//        out__[i] = mul_accNumbers(veff__[i], in__[i]);
//    }
//}
//
//template <typename T>
//__global__ void
//mul_by_veff_complex_complex_gpu_kernel(int nr__, gpu_complex_type<T> const* in__, T pref__, T const* vx__,
//        T const* vy__, gpu_complex_type<T>* out__)
//{
//    int i = blockDim.x * blockIdx.x + threadIdx.x;
//    if (i < nr__) {
//        out__[i] = mul_accNumbers(in__[i], make_accComplex(vx__[i], pref__ * vy__[i]));
//    }
//}
//
//extern "C" {
//
//void
//mul_by_veff_real_real_gpu_float(int nr__, float const* in__, float const* veff__, float* out__)
//{
//    dim3 grid_t(64);
//    dim3 grid_b(num_blocks(nr__, grid_t.x));
//
//    accLaunchKernel((mul_by_veff_real_real_gpu_kernel<float>), dim3(grid_b), dim3(grid_t), 0, 0,
//            nr__, in__, veff__, out__);
//}
//
//void
//mul_by_veff_real_real_gpu_double(int nr__, double const* in__, double const* veff__, double* out__)
//{
//    dim3 grid_t(64);
//    dim3 grid_b(num_blocks(nr__, grid_t.x));
//
//    accLaunchKernel((mul_by_veff_real_real_gpu_kernel<double>), dim3(grid_b), dim3(grid_t), 0, 0,
//            nr__, in__, veff__, out__);
//}
//
//void
//mul_by_veff_complex_real_gpu_float(int nr__, gpu_complex_type<float> const* in__, float const* veff__,
//        gpu_complex_type<float>* out__)
//{
//    dim3 grid_t(64);
//    dim3 grid_b(num_blocks(nr__, grid_t.x));
//
//    accLaunchKernel((mul_by_veff_complex_real_gpu_kernel<float>), dim3(grid_b), dim3(grid_t), 0, 0,
//            nr__, in__, veff__, out__);
//}
//
//void
//mul_by_veff_complex_real_gpu_double(int nr__, gpu_complex_type<double> const* in__, double const* veff__,
//        gpu_complex_type<double>* out__)
//{
//    dim3 grid_t(64);
//    dim3 grid_b(num_blocks(nr__, grid_t.x));
//
//    accLaunchKernel((mul_by_veff_complex_real_gpu_kernel<double>), dim3(grid_b), dim3(grid_t), 0, 0,
//            nr__, in__, veff__, out__);
//}
//
//void
//mul_by_veff_complex_complex_gpu_float(int nr__, gpu_complex_type<float> const* in__, float pref__,
//    float const* vx__, float const* vy__, gpu_complex_type<float>* out__)
//{
//    dim3 grid_t(64);
//    dim3 grid_b(num_blocks(nr__, grid_t.x));
//
//    accLaunchKernel((mul_by_veff_complex_complex_gpu_kernel<float>), dim3(grid_b), dim3(grid_t), 0, 0,
//            nr__, in__, pref__, vx__, vy__, out__);
//}
//
//void
//mul_by_veff_complex_complex_gpu_double(int nr__, gpu_complex_type<double> const* in__, double pref__,
//    double const* vx__, double const* vy__, gpu_complex_type<double>* out__)
//{
//    dim3 grid_t(64);
//    dim3 grid_b(num_blocks(nr__, grid_t.x));
//
//    accLaunchKernel((mul_by_veff_complex_complex_gpu_kernel<double>), dim3(grid_b), dim3(grid_t), 0, 0,
//            nr__, in__, pref__, vx__, vy__, out__);
//}

//}



	.text
	.file	"mul_by_veff.hip"
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_

	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.amdgpu_metadata
---
amdhsa.kernels:  []
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
