#include <stdio.h>
#include <cuda.h>
#include <cuda_runtime.h>
#define dx 0.01
#define dy 0.01
#define rho 8800
#define C 381
#define lambda 384.0
#define tau 0.01
#define BLOCK_SIZE 16

__global__ void __laplas__(float *T,float *T_old, const int n, const int height)
{
        double at = lambda / (rho * C);

        int iA = n * (blockDim.y * blockIdx.y + threadIdx.y) + blockDim.x * blockIdx.x + threadIdx.x;

        if(blockDim.y * blockIdx.y + threadIdx.y>0 && blockDim.x * blockIdx.x + threadIdx.x>0 && blockDim.y * blockIdx.y + threadIdx.y < height && blockDim.x * blockIdx.x + threadIdx.x < n)
                T[iA] = T_old[iA] + (tau / (dx * dx)) * at * (T_old[n * (blockDim.y * blockIdx.y + threadIdx.y-1) + blockDim.x * blockIdx.x + threadIdx.x] - 2 * T_old[iA] + T_old[n * (blockDim.y * blockIdx.y + threadIdx.y+1) + blockDim.x * blockIdx.x + threadIdx.x]) + (tau / (dy * dy)) * at * (T_old[n * (blockDim.y * blockIdx.y + threadIdx.y) + blockDim.x * blockIdx.x + threadIdx.x-1] - 2 * T_old[iA] + T_old[n * (blockDim.y * blockIdx.y + threadIdx.y) + blockDim.x * blockIdx.x + threadIdx.x+1]);
}

extern "C" void gpu(int index, int numDev, int n, int height, float *T, float *T_old)
{
        cudaSetDevice(numDev);
        if (index == 0)
        {
                int count;
                unsigned int flag;
                int device;
                cudaGetDevice(&device);
                cudaGetDeviceCount(&count);
                cudaGetDeviceFlags(&flag);
                printf("set device %d\n", numDev);
                printf("device %d\n", device);
                printf("device flag %d\n", flag);
                printf("device count %d\n", count);
        }
        size_t size = (height+1) * (n+1) * sizeof(float);

        float *dev_T = NULL;
        cudaMalloc((void **)&dev_T, size);
        float *dev_T_old = NULL;
        cudaMalloc((void **)&dev_T_old, size);

        cudaMemcpy( dev_T, T, size, cudaMemcpyHostToDevice );
        cudaMemcpy( dev_T_old, T_old, size, cudaMemcpyHostToDevice );

        dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE, 1);
        dim3 dimGrid(n/BLOCK_SIZE, height/BLOCK_SIZE, 1);

        __laplas__<<<dimGrid, dimBlock>>>(dev_T,dev_T_old, n, height);
        cudaDeviceSynchronize();

        cudaMemcpy(T, dev_T, size, cudaMemcpyDeviceToHost);

        cudaFree(dev_T);
        cudaFree(dev_T_old);
}

	.file	"tmpxft_002d5cb9_00000000-6_kernel.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2030:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z34__device_stub__Z10__laplas__PfS_iiPfS_ii
	.type	_Z34__device_stub__Z10__laplas__PfS_iiPfS_ii, @function
_Z34__device_stub__Z10__laplas__PfS_iiPfS_ii:
.LFB2052:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z10__laplas__PfS_ii(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L2:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2052:
	.size	_Z34__device_stub__Z10__laplas__PfS_iiPfS_ii, .-_Z34__device_stub__Z10__laplas__PfS_iiPfS_ii
	.globl	_Z10__laplas__PfS_ii
	.type	_Z10__laplas__PfS_ii, @function
_Z10__laplas__PfS_ii:
.LFB2053:
	.cfi_startproc
	endbr64
	jmp	_Z34__device_stub__Z10__laplas__PfS_iiPfS_ii
	.cfi_endproc
.LFE2053:
	.size	_Z10__laplas__PfS_ii, .-_Z10__laplas__PfS_ii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"set device %d\n"
.LC1:
	.string	"device %d\n"
.LC2:
	.string	"device flag %d\n"
.LC3:
	.string	"device count %d\n"
	.text
	.globl	gpu
	.type	gpu, @function
gpu:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movl	%edi, %r15d
	movl	%esi, %edi
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	movq	%r9, %r14
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movq	%r8, %r13
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movl	%ecx, %r12d
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movl	%edx, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movl	%esi, %ebx
	subq	$56, %rsp
	.cfi_def_cfa_offset 112
	movq	%fs:40, %rax
	movq	%rax, 40(%rsp)
	xorl	%eax, %eax
	call	cudaSetDevice@PLT
	testl	%r15d, %r15d
	leaq	8(%rsp), %r15
	jne	.L9
	leaq	28(%rsp), %rdi
	call	cudaGetDevice@PLT
	movq	%r15, %rdi
	call	cudaGetDeviceCount@PLT
	leaq	16(%rsp), %rdi
	call	cudaGetDeviceFlags@PLT
	movl	%ebx, %edx
	leaq	.LC0(%rip), %rsi
	xorl	%eax, %eax
	movl	$2, %edi
	call	__printf_chk@PLT
	movl	28(%rsp), %edx
	movl	$2, %edi
	xorl	%eax, %eax
	leaq	.LC1(%rip), %rsi
	call	__printf_chk@PLT
	movl	16(%rsp), %edx
	movl	$2, %edi
	xorl	%eax, %eax
	leaq	.LC2(%rip), %rsi
	call	__printf_chk@PLT
	movl	8(%rsp), %edx
	movl	$2, %edi
	xorl	%eax, %eax
	leaq	.LC3(%rip), %rsi
	call	__printf_chk@PLT
.L9:
	leal	1(%rbp), %eax
	leal	1(%r12), %ebx
	movq	%rsp, %rdi
	imull	%eax, %ebx
	xorl	%eax, %eax
	movq	%rax, (%rsp)
	movslq	%ebx, %rbx
	salq	$2, %rbx
	movq	%rbx, %rsi
	call	cudaMalloc@PLT
	xorl	%edx, %edx
	movq	%rbx, %rsi
	movq	%r15, %rdi
	movq	%rdx, 8(%rsp)
	call	cudaMalloc@PLT
	movq	(%rsp), %rdi
	movq	%rbx, %rdx
	movq	%r13, %rsi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	movq	8(%rsp), %rdi
	movq	%rbx, %rdx
	movq	%r14, %rsi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	movl	%ebp, %eax
	movl	$16, %ecx
	xorl	%r9d, %r9d
	cltd
	xorl	%r8d, %r8d
	movabsq	$68719476752, %rsi
	movl	$1, 24(%rsp)
	idivl	%ecx
	movq	%rsi, 16(%rsp)
	movl	$1, 36(%rsp)
	movl	%eax, 28(%rsp)
	movl	%r12d, %eax
	cltd
	idivl	%ecx
	movq	%rsi, %rdx
	movl	$1, %ecx
	movl	$1, %esi
	movl	%eax, 32(%rsp)
	movq	28(%rsp), %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L10
	movq	8(%rsp), %rsi
	movq	(%rsp), %rdi
	movl	%r12d, %ecx
	movl	%ebp, %edx
	call	_Z34__device_stub__Z10__laplas__PfS_iiPfS_ii
.L10:
	call	cudaDeviceSynchronize@PLT
	movq	(%rsp), %rsi
	movq	%rbx, %rdx
	movq	%r13, %rdi
	movl	$2, %ecx
	call	cudaMemcpy@PLT
	movq	(%rsp), %rdi
	call	cudaFree@PLT
	movq	8(%rsp), %rdi
	call	cudaFree@PLT
	movq	40(%rsp), %rax
	subq	%fs:40, %rax
	je	.L11
	call	__stack_chk_fail@PLT
.L11:
	addq	$56, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2027:
	.size	gpu, .-gpu
	.section	.rodata.str1.1
.LC4:
	.string	"_Z10__laplas__PfS_ii"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC4(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z10__laplas__PfS_ii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2055:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <stdio.h>
#include <hip/hip_runtime.h>

#define dx 0.01
#define dy 0.01
#define rho 8800
#define C 381
#define lambda 384.0
#define tau 0.01
#define BLOCK_SIZE 16

__global__ void __laplas__(float *T,float *T_old, const int n, const int height)
{
        double at = lambda / (rho * C);

        int iA = n * (blockDim.y * blockIdx.y + threadIdx.y) + blockDim.x * blockIdx.x + threadIdx.x;

        if(blockDim.y * blockIdx.y + threadIdx.y>0 && blockDim.x * blockIdx.x + threadIdx.x>0 && blockDim.y * blockIdx.y + threadIdx.y < height && blockDim.x * blockIdx.x + threadIdx.x < n)
                T[iA] = T_old[iA] + (tau / (dx * dx)) * at * (T_old[n * (blockDim.y * blockIdx.y + threadIdx.y-1) + blockDim.x * blockIdx.x + threadIdx.x] - 2 * T_old[iA] + T_old[n * (blockDim.y * blockIdx.y + threadIdx.y+1) + blockDim.x * blockIdx.x + threadIdx.x]) + (tau / (dy * dy)) * at * (T_old[n * (blockDim.y * blockIdx.y + threadIdx.y) + blockDim.x * blockIdx.x + threadIdx.x-1] - 2 * T_old[iA] + T_old[n * (blockDim.y * blockIdx.y + threadIdx.y) + blockDim.x * blockIdx.x + threadIdx.x+1]);
}

extern "C" void gpu(int index, int numDev, int n, int height, float *T, float *T_old)
{
        hipSetDevice(numDev);
        if (index == 0)
        {
                int count;
                unsigned int flag;
                int device;
                hipGetDevice(&device);
                hipGetDeviceCount(&count);
                hipGetDeviceFlags(&flag);
                printf("set device %d\n", numDev);
                printf("device %d\n", device);
                printf("device flag %d\n", flag);
                printf("device count %d\n", count);
        }
        size_t size = (height+1) * (n+1) * sizeof(float);

        float *dev_T = NULL;
        hipMalloc((void **)&dev_T, size);
        float *dev_T_old = NULL;
        hipMalloc((void **)&dev_T_old, size);

        hipMemcpy( dev_T, T, size, hipMemcpyHostToDevice );
        hipMemcpy( dev_T_old, T_old, size, hipMemcpyHostToDevice );

        dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE, 1);
        dim3 dimGrid(n/BLOCK_SIZE, height/BLOCK_SIZE, 1);

        __laplas__<<<dimGrid, dimBlock>>>(dev_T,dev_T_old, n, height);
        hipDeviceSynchronize();

        hipMemcpy(T, dev_T, size, hipMemcpyDeviceToHost);

        hipFree(dev_T);
        hipFree(dev_T_old);
}

	.text
	.file	"kernel.hip"
	.globl	_Z25__device_stub____laplas__PfS_ii # -- Begin function _Z25__device_stub____laplas__PfS_ii
	.type	_Z25__device_stub____laplas__PfS_ii,@function
_Z25__device_stub____laplas__PfS_ii:    # @_Z25__device_stub____laplas__PfS_ii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z10__laplas__PfS_ii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z25__device_stub____laplas__PfS_ii, .Lfunc_end0-_Z25__device_stub____laplas__PfS_ii
	.cfi_endproc
                                        # -- End function
	.globl	gpu                             # -- Begin function gpu
	.type	gpu,@function
gpu:                                    # @gpu
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$40, %rsp
	.cfi_def_cfa_offset 96
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%r9, 16(%rsp)                   # 8-byte Spill
	movq	%r8, 24(%rsp)                   # 8-byte Spill
	movl	%ecx, %r14d
	movl	%edx, %r15d
	movl	%esi, %ebp
	movl	%edi, %r13d
	movl	%esi, %edi
	callq	hipSetDevice
	testl	%r13d, %r13d
	jne	.LBB1_2
# %bb.1:
	leaq	36(%rsp), %r12
	movq	%r12, %rdi
	callq	hipGetDevice
	movq	%rsp, %rbx
	movq	%rbx, %rdi
	callq	hipGetDeviceCount
	leaq	8(%rsp), %r13
	movq	%r13, %rdi
	callq	hipGetDeviceFlags
	movl	$.L.str, %edi
	movl	%ebp, %esi
	xorl	%eax, %eax
	callq	printf
	movl	(%r12), %esi
	movl	$.L.str.1, %edi
	xorl	%eax, %eax
	callq	printf
	movl	(%r13), %esi
	movl	$.L.str.2, %edi
	xorl	%eax, %eax
	callq	printf
	movl	(%rbx), %esi
	movl	$.L.str.3, %edi
	xorl	%eax, %eax
	callq	printf
.LBB1_2:
	leal	1(%r14), %eax
	leal	1(%r15), %ecx
	imull	%eax, %ecx
	movslq	%ecx, %r13
	shlq	$2, %r13
	xorl	%ebx, %ebx
	movq	%rsp, %rbp
	movq	%rbx, (%rbp)
	movq	%rbp, %rdi
	movq	%r13, %rsi
	callq	hipMalloc
	leaq	8(%rsp), %r12
	movq	%rbx, (%r12)
	movq	%r12, %rdi
	movq	%r13, %rsi
	callq	hipMalloc
	movq	(%rbp), %rdi
	movq	24(%rsp), %rbx                  # 8-byte Reload
	movq	%rbx, %rsi
	movq	%r13, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%r12), %rdi
	movq	16(%rsp), %rsi                  # 8-byte Reload
	movq	%r13, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	leal	15(%r15), %eax
	testl	%r15d, %r15d
	cmovnsl	%r15d, %eax
	sarl	$4, %eax
	leal	15(%r14), %edi
	testl	%r14d, %r14d
	cmovnsl	%r14d, %edi
	sarl	$4, %edi
	shlq	$32, %rdi
	orq	%rax, %rdi
	movabsq	$68719476752, %rdx              # imm = 0x1000000010
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_4
# %bb.3:
	movq	(%rsp), %rdi
	movq	8(%rsp), %rsi
	movl	%r15d, %edx
	movl	%r14d, %ecx
	callq	_Z25__device_stub____laplas__PfS_ii
.LBB1_4:
	callq	hipDeviceSynchronize
	movq	(%rsp), %rsi
	movq	%rbx, %rdi
	movq	%r13, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	movq	(%rsp), %rdi
	callq	hipFree
	movq	8(%rsp), %rdi
	callq	hipFree
	addq	$40, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	gpu, .Lfunc_end1-gpu
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z10__laplas__PfS_ii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z10__laplas__PfS_ii,@object    # @_Z10__laplas__PfS_ii
	.section	.rodata,"a",@progbits
	.globl	_Z10__laplas__PfS_ii
	.p2align	3, 0x0
_Z10__laplas__PfS_ii:
	.quad	_Z25__device_stub____laplas__PfS_ii
	.size	_Z10__laplas__PfS_ii, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"set device %d\n"
	.size	.L.str, 15

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"device %d\n"
	.size	.L.str.1, 11

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"device flag %d\n"
	.size	.L.str.2, 16

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"device count %d\n"
	.size	.L.str.3, 17

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z10__laplas__PfS_ii"
	.size	.L__unnamed_1, 21

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z25__device_stub____laplas__PfS_ii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z10__laplas__PfS_ii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z10__laplas__PfS_ii    ; -- Begin function _Z10__laplas__PfS_ii
	.globl	_Z10__laplas__PfS_ii
	.p2align	8
	.type	_Z10__laplas__PfS_ii,@function
_Z10__laplas__PfS_ii:                   ; @_Z10__laplas__PfS_ii
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x24
	s_load_b64 s[6:7], s[0:1], 0x10
	v_bfe_u32 v1, v0, 10, 10
	v_and_b32_e32 v0, 0x3ff, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v2, 0, v1
	v_sub_nc_u32_e32 v3, 0, v0
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s2, 16
	s_and_b32 s2, s2, 0xffff
	s_mul_i32 s15, s15, s3
	s_mul_i32 s14, s14, s2
	v_add_nc_u32_e32 v1, s15, v1
	v_add_nc_u32_e32 v0, s14, v0
	v_cmp_ne_u32_e32 vcc_lo, s15, v2
	v_cmp_ne_u32_e64 s2, s14, v3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cmp_gt_u32_e64 s3, s7, v1
	v_cmp_gt_u32_e64 s4, s6, v0
	s_delay_alu instid0(VALU_DEP_3)
	s_and_b32 s2, vcc_lo, s2
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, s3, s2
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, s2, s4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_2
; %bb.1:
	v_mul_lo_u32 v1, v1, s6
	s_load_b128 s[0:3], s[0:1], 0x0
	v_mov_b32_e32 v4, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v2, s6, v1
	v_add_nc_u32_e32 v1, v0, v1
	v_add_nc_u32_e32 v3, v0, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v2, 31, v1
	v_lshlrev_b64 v[5:6], 2, v[3:4]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[7:8], 2, v[1:2]
	v_lshl_add_u32 v3, s6, 1, v3
	v_lshlrev_b64 v[2:3], 2, v[3:4]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v9, vcc_lo, s2, v7
	v_add_co_ci_u32_e32 v10, vcc_lo, s3, v8, vcc_lo
	v_add_co_u32 v5, vcc_lo, s2, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, s3, v6, vcc_lo
	v_add_co_u32 v2, vcc_lo, s2, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
	s_clause 0x2
	global_load_b32 v9, v[9:10], off
	global_load_b32 v10, v[5:6], off
	global_load_b32 v11, v[2:3], off
	s_waitcnt vmcnt(1)
	v_fmac_f32_e32 v10, -2.0, v9
	v_add_nc_u32_e32 v3, -1, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[5:6], 2, v[3:4]
	v_add_nc_u32_e32 v3, 1, v1
	v_lshlrev_b64 v[0:1], 2, v[3:4]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v2, vcc_lo, s2, v5
	v_add_co_ci_u32_e32 v3, vcc_lo, s3, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v0, vcc_lo, s2, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
	s_clause 0x1
	global_load_b32 v4, v[2:3], off
	global_load_b32 v5, v[0:1], off
	s_waitcnt vmcnt(2)
	v_add_f32_e32 v2, v10, v11
	v_cvt_f64_f32_e32 v[0:1], v9
	s_mov_b32 s2, 0xea317a3b
	s_mov_b32 s3, 0x3f8774ba
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f64_f32_e32 v[2:3], v2
	v_fma_f64 v[0:1], v[2:3], s[2:3], v[0:1]
	s_waitcnt vmcnt(1)
	v_fmac_f32_e32 v4, -2.0, v9
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v4, v4, v5
	v_cvt_f64_f32_e32 v[2:3], v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[0:1], v[2:3], s[2:3], v[0:1]
	v_cvt_f32_f64_e32 v2, v[0:1]
	v_add_co_u32 v0, vcc_lo, s0, v7
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v8, vcc_lo
	global_store_b32 v[0:1], v2, off
.LBB0_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z10__laplas__PfS_ii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 12
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z10__laplas__PfS_ii, .Lfunc_end0-_Z10__laplas__PfS_ii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 504
; NumSgprs: 18
; NumVgprs: 12
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 12
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z10__laplas__PfS_ii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z10__laplas__PfS_ii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     12
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
