/* Andrew Miller <amiller@dappervision.com>
 *
 * Cuda 512*512*512*4bytes test
 * 
 * According to the KinectFusion UIST 2011 paper, it's possible 
 * to do a sweep of 512^3 voxels, 32-bits each, in ~2ms on a GTX470.
 * 
 * This code is a simple benchmark accessing 512^3 voxels. Each
 * voxel has two 16-bit components. In this benchmark kernel, we
 * simply increment these values by a constant K. More than anything
 * it's a test of the memory bandwidth.
 *
 * On my GTX470 card, this kernel takes 10.7ms instead of ~2ms. Is there
 * a faster way to do this?
 *
 * Citation: http://dl.acm.org/citation.cfm?id=2047270
 * Public gdocs pdf link: http://tinyurl.com/6xlznbx
 */

#include <stdio.h>
#include <cuda.h>
#include <sys/time.h>
#include <assert.h>

struct Voxel {
    short int sd;
    short int w;
};

const int N_BYTES = (512*512*512*4);
const int N_LOOPS = 10;
const int K = 7;

__global__ void incr_tsdf(Voxel *vox, Voxel *out)
{
    int idx = blockIdx.x*512 + threadIdx.x;
    for (int z = 0; z < 512; z++) {
	out[idx].sd = vox[idx].sd + K;
	out[idx].w = vox[idx].w += K;
	idx += 512*512;
    }
}

int main(void) {
    Voxel *vox_gpu;
    Voxel *vox_gpuA;
    Voxel *vox_cpu;

    cudaMalloc((void **) &vox_gpu, N_BYTES);
    cudaMalloc((void **) &vox_gpuA, N_BYTES);
    vox_cpu = (Voxel *) calloc(N_BYTES, 1);
    cudaMemcpy(vox_gpu, vox_cpu, N_BYTES, cudaMemcpyHostToDevice);

    dim3 dimBlock(512,1,1);
    dim3 dimGrid(512,1,1);

    cudaEvent_t e_start, e_stop;
    cudaEventCreate(&e_start);
    cudaEventCreate(&e_stop);
    cudaEventRecord(e_start);
    for (int i = 0; i < N_LOOPS; i++) {      
	incr_tsdf<<<dimGrid, dimBlock>>>(vox_gpu, vox_gpuA);
    }
    cudaEventRecord(e_stop);
    cudaEventSynchronize(e_stop);

    float ms;
    cudaEventElapsedTime(&ms, e_start, e_stop);

    // Copy back to the host and check we have what we expect
    cudaMemcpy(vox_cpu, vox_gpu, N_BYTES, cudaMemcpyDeviceToHost);
    for (int i = 0; i < 512; i++) {
    	for (int j = 0; j < 512; j++) {
	    for (int k = 0; k < 512; k++) {
	    	int idx = i*512*512 + j*512 + k;
	    	assert(vox_cpu[idx].sd == (short)N_LOOPS*K);
	    	assert(vox_cpu[idx].w == (short)N_LOOPS*K);
	    }
	}
    }

    printf("%d sweeps of %.1f megavoxels in %.1fms (avg %.1fms)\n", 
        N_LOOPS, N_BYTES/4.0/1000.0/1000.0, ms, ms/N_LOOPS);

    cudaFree(vox_gpu);
    free(vox_cpu);
    return 0;
}

	.file	"tmpxft_002c6d59_00000000-6_cuda_512_512_512_4_bytes.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2030:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z36__device_stub__Z9incr_tsdfP5VoxelS0_P5VoxelS0_
	.type	_Z36__device_stub__Z9incr_tsdfP5VoxelS0_P5VoxelS0_, @function
_Z36__device_stub__Z9incr_tsdfP5VoxelS0_P5VoxelS0_:
.LFB2052:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 8(%rsp)
	leaq	32(%rsp), %rcx
	leaq	24(%rsp), %rdx
	movq	%rsi, (%rsp)
	leaq	40(%rsp), %rdi
	leaq	52(%rsp), %rsi
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 48(%rsp)
	movq	%rax, 88(%rsp)
	movq	%rsp, %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	32(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z9incr_tsdfP5VoxelS0_(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 144
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	104(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L2:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2052:
	.size	_Z36__device_stub__Z9incr_tsdfP5VoxelS0_P5VoxelS0_, .-_Z36__device_stub__Z9incr_tsdfP5VoxelS0_P5VoxelS0_
	.globl	_Z9incr_tsdfP5VoxelS0_
	.type	_Z9incr_tsdfP5VoxelS0_, @function
_Z9incr_tsdfP5VoxelS0_:
.LFB2053:
	.cfi_startproc
	endbr64
	jmp	_Z36__device_stub__Z9incr_tsdfP5VoxelS0_P5VoxelS0_
	.cfi_endproc
.LFE2053:
	.size	_Z9incr_tsdfP5VoxelS0_, .-_Z9incr_tsdfP5VoxelS0_
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC2:
	.string	"%d sweeps of %.1f megavoxels in %.1fms (avg %.1fms)\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	movl	$536870912, %esi
	movl	$10, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 24
	.cfi_offset 3, -24
	subq	$88, %rsp
	.cfi_def_cfa_offset 112
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	xorl	%eax, %eax
	leaq	16(%rsp), %rdi
	call	cudaMalloc@PLT
	leaq	24(%rsp), %rdi
	movl	$536870912, %esi
	call	cudaMalloc@PLT
	movl	$1, %esi
	movl	$536870912, %edi
	call	calloc@PLT
	movq	16(%rsp), %rdi
	movl	$1, %ecx
	movl	$536870912, %edx
	movq	%rax, %rsi
	movq	%rax, %rbx
	call	cudaMemcpy@PLT
	movl	$8388609, %eax
	leaq	32(%rsp), %rdi
	movl	$1, 56(%rsp)
	salq	$9, %rax
	movl	$1, 68(%rsp)
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	call	cudaEventCreate@PLT
	leaq	40(%rsp), %rdi
	call	cudaEventCreate@PLT
	movq	32(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
.L10:
	movl	56(%rsp), %ecx
	movq	48(%rsp), %rdx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	60(%rsp), %rdi
	movl	68(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L9
	movq	24(%rsp), %rsi
	movq	16(%rsp), %rdi
	call	_Z36__device_stub__Z9incr_tsdfP5VoxelS0_P5VoxelS0_
.L9:
	decl	%ebp
	jne	.L10
	movq	40(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movq	40(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movq	40(%rsp), %rdx
	movq	32(%rsp), %rsi
	leaq	12(%rsp), %rdi
	call	cudaEventElapsedTime@PLT
	movq	16(%rsp), %rsi
	movl	$2, %ecx
	movq	%rbx, %rdi
	movl	$536870912, %edx
	call	cudaMemcpy@PLT
	movss	12(%rsp), %xmm1
	movb	$3, %al
	movsd	.LC1(%rip), %xmm0
	movl	$10, %edx
	leaq	.LC2(%rip), %rsi
	movl	$2, %edi
	movaps	%xmm1, %xmm2
	cvtss2sd	%xmm1, %xmm1
	divss	.LC0(%rip), %xmm2
	cvtss2sd	%xmm2, %xmm2
	call	__printf_chk@PLT
	movq	16(%rsp), %rdi
	call	cudaFree@PLT
	movq	%rbx, %rdi
	call	free@PLT
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L11
	call	__stack_chk_fail@PLT
.L11:
	addq	$88, %rsp
	.cfi_def_cfa_offset 24
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2027:
	.size	main, .-main
	.section	.rodata.str1.1
.LC3:
	.string	"_Z9incr_tsdfP5VoxelS0_"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC3(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z9incr_tsdfP5VoxelS0_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2055:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst4,"aM",@progbits,4
	.align 4
.LC0:
	.long	1092616192
	.section	.rodata.cst8,"aM",@progbits,8
	.align 8
.LC1:
	.long	-1598689907
	.long	1080084215
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

/* Andrew Miller <amiller@dappervision.com>
 *
 * Cuda 512*512*512*4bytes test
 * 
 * According to the KinectFusion UIST 2011 paper, it's possible 
 * to do a sweep of 512^3 voxels, 32-bits each, in ~2ms on a GTX470.
 * 
 * This code is a simple benchmark accessing 512^3 voxels. Each
 * voxel has two 16-bit components. In this benchmark kernel, we
 * simply increment these values by a constant K. More than anything
 * it's a test of the memory bandwidth.
 *
 * On my GTX470 card, this kernel takes 10.7ms instead of ~2ms. Is there
 * a faster way to do this?
 *
 * Citation: http://dl.acm.org/citation.cfm?id=2047270
 * Public gdocs pdf link: http://tinyurl.com/6xlznbx
 */

#include <stdio.h>
#include <hip/hip_runtime.h>
#include <sys/time.h>
#include <assert.h>

struct Voxel {
    short int sd;
    short int w;
};

const int N_BYTES = (512*512*512*4);
const int N_LOOPS = 10;
const int K = 7;

__global__ void incr_tsdf(Voxel *vox, Voxel *out)
{
    int idx = blockIdx.x*512 + threadIdx.x;
    for (int z = 0; z < 512; z++) {
	out[idx].sd = vox[idx].sd + K;
	out[idx].w = vox[idx].w += K;
	idx += 512*512;
    }
}

int main(void) {
    Voxel *vox_gpu;
    Voxel *vox_gpuA;
    Voxel *vox_cpu;

    hipMalloc((void **) &vox_gpu, N_BYTES);
    hipMalloc((void **) &vox_gpuA, N_BYTES);
    vox_cpu = (Voxel *) calloc(N_BYTES, 1);
    hipMemcpy(vox_gpu, vox_cpu, N_BYTES, hipMemcpyHostToDevice);

    dim3 dimBlock(512,1,1);
    dim3 dimGrid(512,1,1);

    hipEvent_t e_start, e_stop;
    hipEventCreate(&e_start);
    hipEventCreate(&e_stop);
    hipEventRecord(e_start);
    for (int i = 0; i < N_LOOPS; i++) {      
	incr_tsdf<<<dimGrid, dimBlock>>>(vox_gpu, vox_gpuA);
    }
    hipEventRecord(e_stop);
    hipEventSynchronize(e_stop);

    float ms;
    hipEventElapsedTime(&ms, e_start, e_stop);

    // Copy back to the host and check we have what we expect
    hipMemcpy(vox_cpu, vox_gpu, N_BYTES, hipMemcpyDeviceToHost);
    for (int i = 0; i < 512; i++) {
    	for (int j = 0; j < 512; j++) {
	    for (int k = 0; k < 512; k++) {
	    	int idx = i*512*512 + j*512 + k;
	    	assert(vox_cpu[idx].sd == (short)N_LOOPS*K);
	    	assert(vox_cpu[idx].w == (short)N_LOOPS*K);
	    }
	}
    }

    printf("%d sweeps of %.1f megavoxels in %.1fms (avg %.1fms)\n", 
        N_LOOPS, N_BYTES/4.0/1000.0/1000.0, ms, ms/N_LOOPS);

    hipFree(vox_gpu);
    free(vox_cpu);
    return 0;
}

	.text
	.file	"cuda_512_512_512_4_bytes.hip"
	.globl	_Z24__device_stub__incr_tsdfP5VoxelS0_ # -- Begin function _Z24__device_stub__incr_tsdfP5VoxelS0_
	.type	_Z24__device_stub__incr_tsdfP5VoxelS0_,@function
_Z24__device_stub__incr_tsdfP5VoxelS0_: # @_Z24__device_stub__incr_tsdfP5VoxelS0_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	16(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z9incr_tsdfP5VoxelS0_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z24__device_stub__incr_tsdfP5VoxelS0_, .Lfunc_end0-_Z24__device_stub__incr_tsdfP5VoxelS0_
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0                          # -- Begin function main
.LCPI1_0:
	.long	0x41200000                      # float 10
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0
.LCPI1_1:
	.quad	0x4060c6f7a0b5ed8d              # double 134.21772799999999
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	subq	$40, %rsp
	.cfi_def_cfa_offset 80
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movabsq	$4294967808, %r14               # imm = 0x100000200
	leaq	8(%rsp), %r15
	movl	$536870912, %esi                # imm = 0x20000000
	movq	%r15, %rdi
	callq	hipMalloc
	leaq	24(%rsp), %rdi
	movl	$536870912, %esi                # imm = 0x20000000
	callq	hipMalloc
	movl	$536870912, %edi                # imm = 0x20000000
	movl	$1, %esi
	callq	calloc
	movq	%rax, %rbx
	movq	(%r15), %rdi
	movl	$536870912, %edx                # imm = 0x20000000
	movq	%rax, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	16(%rsp), %r15
	movq	%r15, %rdi
	callq	hipEventCreate
	movq	%rsp, %rdi
	callq	hipEventCreate
	movq	(%r15), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movl	$10, %ebp
.LBB1_1:                                # =>This Inner Loop Header: Depth=1
	movq	%r14, %rdi
	movl	$1, %esi
	movq	%r14, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_3
# %bb.2:                                #   in Loop: Header=BB1_1 Depth=1
	movq	8(%rsp), %rdi
	movq	24(%rsp), %rsi
	callq	_Z24__device_stub__incr_tsdfP5VoxelS0_
.LBB1_3:                                #   in Loop: Header=BB1_1 Depth=1
	decl	%ebp
	jne	.LBB1_1
# %bb.4:
	movq	(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	(%rsp), %rdi
	callq	hipEventSynchronize
	movq	16(%rsp), %rsi
	movq	(%rsp), %rdx
	leaq	36(%rsp), %r14
	movq	%r14, %rdi
	callq	hipEventElapsedTime
	movq	8(%rsp), %rsi
	movl	$536870912, %edx                # imm = 0x20000000
	movq	%rbx, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movss	(%r14), %xmm0                   # xmm0 = mem[0],zero,zero,zero
	cvtss2sd	%xmm0, %xmm1
	divss	.LCPI1_0(%rip), %xmm0
	cvtss2sd	%xmm0, %xmm2
	movsd	.LCPI1_1(%rip), %xmm0           # xmm0 = mem[0],zero
	movl	$.L.str, %edi
	movl	$10, %esi
	movb	$3, %al
	callq	printf
	movq	8(%rsp), %rdi
	callq	hipFree
	movq	%rbx, %rdi
	callq	free
	xorl	%eax, %eax
	addq	$40, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	main, .Lfunc_end1-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z9incr_tsdfP5VoxelS0_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z9incr_tsdfP5VoxelS0_,@object  # @_Z9incr_tsdfP5VoxelS0_
	.section	.rodata,"a",@progbits
	.globl	_Z9incr_tsdfP5VoxelS0_
	.p2align	3, 0x0
_Z9incr_tsdfP5VoxelS0_:
	.quad	_Z24__device_stub__incr_tsdfP5VoxelS0_
	.size	_Z9incr_tsdfP5VoxelS0_, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"%d sweeps of %.1f megavoxels in %.1fms (avg %.1fms)\n"
	.size	.L.str, 53

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z9incr_tsdfP5VoxelS0_"
	.size	.L__unnamed_1, 23

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z24__device_stub__incr_tsdfP5VoxelS0_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z9incr_tsdfP5VoxelS0_
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z9incr_tsdfP5VoxelS0_  ; -- Begin function _Z9incr_tsdfP5VoxelS0_
	.globl	_Z9incr_tsdfP5VoxelS0_
	.p2align	8
	.type	_Z9incr_tsdfP5VoxelS0_,@function
_Z9incr_tsdfP5VoxelS0_:                 ; @_Z9incr_tsdfP5VoxelS0_
; %bb.0:
	s_load_b128 s[0:3], s[0:1], 0x0
	v_lshl_add_u32 v0, s15, 9, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v1, 31, v0
	v_lshlrev_b64 v[2:3], 2, v[0:1]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s0, v2
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v3, vcc_lo
	v_add_co_u32 v2, vcc_lo, s2, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
	s_mov_b64 s[0:1], 0
.LBB0_1:                                ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	v_add_co_u32 v4, vcc_lo, v0, s0
	v_add_co_ci_u32_e32 v5, vcc_lo, s1, v1, vcc_lo
	global_load_b32 v6, v[4:5], off
	s_waitcnt vmcnt(0)
	v_lshrrev_b32_e32 v7, 16, v6
	v_add_nc_u16 v8, v6, 7
	v_add_co_u32 v6, vcc_lo, v2, s0
	s_add_u32 s0, s0, 0x100000
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_add_nc_u16 v9, v7, 7
	v_add_co_ci_u32_e32 v7, vcc_lo, s1, v3, vcc_lo
	s_addc_u32 s1, s1, 0
	s_cmp_eq_u32 s0, 0x20000000
	v_perm_b32 v8, v9, v8, 0x5040100
	global_store_b16 v[4:5], v9, off offset:2
	global_store_b32 v[6:7], v8, off
	s_cbranch_scc0 .LBB0_1
; %bb.2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z9incr_tsdfP5VoxelS0_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 16
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 10
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z9incr_tsdfP5VoxelS0_, .Lfunc_end0-_Z9incr_tsdfP5VoxelS0_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 196
; NumSgprs: 18
; NumVgprs: 10
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 10
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 16
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z9incr_tsdfP5VoxelS0_
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z9incr_tsdfP5VoxelS0_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     10
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
