#include <cstdio>
#define BLOCK_SIZE 256

__global__ void mtrxToVec(int* mtrx,int* vec, int* ans,int n){
	int idx=blockDim.x*blockIdx.x+threadIdx.x;
	while(idx<n){
		int sum=0;
		for(int i=0;i<n;i++)
			sum+=mtrx[n*i+idx]*vec[idx];
		ans[idx]=sum;
		idx+=gridDim.x*blockDim.x;
	}
	return;
}


__global__ void mtrxToVecY(int* mtrx,int* vec, int* ans,int n){
	int idy=blockDim.y*blockIdx.y+threadIdx.y;
	while(idy<n){
		int sum=0;
		for(int i=0;i<n;i++)
			sum+=mtrx[n*i+idy]*vec[idy];
		ans[idy]=sum;
		idy+=gridDim.y*blockDim.y;
	}
	return;
}

__global__ void transposeMtrxToVec(int* mtrx,int* vec, int* ans,int n){
	int idx=blockDim.x*blockIdx.x+threadIdx.x;
	while(idx<n){
		int sum=0;
		for(int i=0;i<n;i++)
			sum+=mtrx[n+idx*i]*vec[idx];
		ans[idx]=sum;
		idx+=gridDim.x*blockDim.x;
	}
	return;
}

__host__ void  cuAssert(cudaError_t error){
	if(error!=cudaSuccess){
		printf("%s\n",cudaGetErrorString(error));
		exit(0);
	}
}

__host__ void print(int* ans,int n){
	for(int i=0;i<n;i++)
		printf("%5d ",ans[i]);
	printf("\n");
	return;
}

__host__ int main(int argc,char* argv[]){
	cudaEvent_t start,stop;
	cuAssert(cudaEventCreate(&start));
	cuAssert(cudaEventCreate(&stop));
	float time;

	const int n=10000;
	size_t size=sizeof(int)*n;
	int* vec=(int*)malloc(size);
	int* ans=(int*)malloc(size);
	int* mtrx=(int*)malloc(size*n);

	for(int i=0;i<n;i++){
		for(int j=0;j<n;j++)
			mtrx[i*n+j]=(i==j)?(1):(0);
		vec[i]=i;
	}

	int* cuVec=NULL;
	int* cuAns=NULL;
	int* cuMtrx=NULL;
	cuAssert(cudaMalloc((void**)&cuVec,size));
	cuAssert(cudaMalloc((void**)&cuAns,size));
	cuAssert(cudaMalloc((void**)&cuMtrx,size*n));

	cuAssert(cudaMemcpy(cuMtrx,mtrx,size*n,cudaMemcpyHostToDevice));
	cuAssert(cudaMemcpy(cuVec,vec,size,cudaMemcpyHostToDevice));

	dim3 grid((n+BLOCK_SIZE-1)/BLOCK_SIZE,1,1);
	dim3 block(BLOCK_SIZE,1,1);

//coalesced block 1D indexes
	cuAssert(cudaEventRecord(start));
	mtrxToVec<<<grid,block>>>(cuMtrx,cuVec,cuAns,n);
	cuAssert(cudaEventRecord(stop));
	cuAssert(cudaEventSynchronize(stop));
	cuAssert(cudaEventElapsedTime(&time,start,stop));
	printf("coalesced time X %f\n",time);
	cuAssert(cudaGetLastError());
	cuAssert(cudaMemcpy(ans,cuAns,size,cudaMemcpyDeviceToHost));
	//print(ans,n);

	dim3 gridY(1,(n+BLOCK_SIZE-1)/BLOCK_SIZE,1);
	dim3 blockY(1,BLOCK_SIZE,1);	
	cuAssert(cudaEventRecord(start));
	mtrxToVecY<<<gridY,blockY>>>(cuMtrx,cuVec,cuAns,n);
	cuAssert(cudaEventRecord(stop));
	cuAssert(cudaEventSynchronize(stop));
	cuAssert(cudaEventElapsedTime(&time,start,stop));
	printf("coalesced time Y %f\n",time);
	cuAssert(cudaGetLastError());
	
//Non coalesced block
	cuAssert(cudaEventRecord(start));
	transposeMtrxToVec<<<grid,block>>>(cuMtrx,cuVec,cuAns,n);
	cuAssert(cudaEventRecord(stop));
	cuAssert(cudaEventSynchronize(stop));
	cuAssert(cudaEventElapsedTime(&time,start,stop));
	printf("non coalesced time %f\n",time);
	cuAssert(cudaGetLastError());

	cuAssert(cudaFree(cuVec));
	cuAssert(cudaFree(cuAns));
	cuAssert(cudaFree(cuMtrx));

	free(vec);
	free(ans);
	free(mtrx);
	return 0;
}

	.file	"tmpxft_002d4233_00000000-6_mtrxTovector.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2032:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2032:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"%s\n"
	.text
	.globl	_Z8cuAssert9cudaError
	.type	_Z8cuAssert9cudaError, @function
_Z8cuAssert9cudaError:
.LFB2027:
	.cfi_startproc
	endbr64
	testl	%edi, %edi
	je	.L2
	pushq	%rax
	.cfi_def_cfa_offset 16
	call	cudaGetErrorString@PLT
	movl	$2, %edi
	leaq	.LC0(%rip), %rsi
	movq	%rax, %rdx
	xorl	%eax, %eax
	call	__printf_chk@PLT
	xorl	%edi, %edi
	call	exit@PLT
.L2:
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2027:
	.size	_Z8cuAssert9cudaError, .-_Z8cuAssert9cudaError
	.section	.rodata.str1.1
.LC1:
	.string	"%5d "
.LC2:
	.string	"\n"
	.text
	.globl	_Z5printPii
	.type	_Z5printPii, @function
_Z5printPii:
.LFB2028:
	.cfi_startproc
	endbr64
	pushq	%r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	leaq	.LC1(%rip), %r13
	pushq	%r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	movq	%rdi, %r12
	pushq	%rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	movl	%esi, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	xorl	%ebx, %ebx
	pushq	%rcx
	.cfi_def_cfa_offset 48
.L9:
	cmpl	%ebx, %ebp
	jle	.L12
	movl	(%r12,%rbx,4), %edx
	movq	%r13, %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	incq	%rbx
	call	__printf_chk@PLT
	jmp	.L9
.L12:
	popq	%rdx
	.cfi_def_cfa_offset 40
	leaq	.LC2(%rip), %rsi
	popq	%rbx
	.cfi_def_cfa_offset 32
	movl	$2, %edi
	popq	%rbp
	.cfi_def_cfa_offset 24
	xorl	%eax, %eax
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	__printf_chk@PLT
	.cfi_endproc
.LFE2028:
	.size	_Z5printPii, .-_Z5printPii
	.globl	_Z33__device_stub__Z9mtrxToVecPiS_S_iPiS_S_i
	.type	_Z33__device_stub__Z9mtrxToVecPiS_S_iPiS_S_i, @function
_Z33__device_stub__Z9mtrxToVecPiS_S_iPiS_S_i:
.LFB2054:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 4(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L13
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z9mtrxToVecPiS_S_i(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L13:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L15
	call	__stack_chk_fail@PLT
.L15:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2054:
	.size	_Z33__device_stub__Z9mtrxToVecPiS_S_iPiS_S_i, .-_Z33__device_stub__Z9mtrxToVecPiS_S_iPiS_S_i
	.globl	_Z9mtrxToVecPiS_S_i
	.type	_Z9mtrxToVecPiS_S_i, @function
_Z9mtrxToVecPiS_S_i:
.LFB2055:
	.cfi_startproc
	endbr64
	jmp	_Z33__device_stub__Z9mtrxToVecPiS_S_iPiS_S_i
	.cfi_endproc
.LFE2055:
	.size	_Z9mtrxToVecPiS_S_i, .-_Z9mtrxToVecPiS_S_i
	.globl	_Z35__device_stub__Z10mtrxToVecYPiS_S_iPiS_S_i
	.type	_Z35__device_stub__Z10mtrxToVecYPiS_S_iPiS_S_i, @function
_Z35__device_stub__Z10mtrxToVecYPiS_S_iPiS_S_i:
.LFB2056:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 4(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L18
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z10mtrxToVecYPiS_S_i(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L18:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L20
	call	__stack_chk_fail@PLT
.L20:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2056:
	.size	_Z35__device_stub__Z10mtrxToVecYPiS_S_iPiS_S_i, .-_Z35__device_stub__Z10mtrxToVecYPiS_S_iPiS_S_i
	.globl	_Z10mtrxToVecYPiS_S_i
	.type	_Z10mtrxToVecYPiS_S_i, @function
_Z10mtrxToVecYPiS_S_i:
.LFB2057:
	.cfi_startproc
	endbr64
	jmp	_Z35__device_stub__Z10mtrxToVecYPiS_S_iPiS_S_i
	.cfi_endproc
.LFE2057:
	.size	_Z10mtrxToVecYPiS_S_i, .-_Z10mtrxToVecYPiS_S_i
	.globl	_Z43__device_stub__Z18transposeMtrxToVecPiS_S_iPiS_S_i
	.type	_Z43__device_stub__Z18transposeMtrxToVecPiS_S_iPiS_S_i, @function
_Z43__device_stub__Z18transposeMtrxToVecPiS_S_iPiS_S_i:
.LFB2058:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 4(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L23
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z18transposeMtrxToVecPiS_S_i(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L23:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L25
	call	__stack_chk_fail@PLT
.L25:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2058:
	.size	_Z43__device_stub__Z18transposeMtrxToVecPiS_S_iPiS_S_i, .-_Z43__device_stub__Z18transposeMtrxToVecPiS_S_iPiS_S_i
	.globl	_Z18transposeMtrxToVecPiS_S_i
	.type	_Z18transposeMtrxToVecPiS_S_i, @function
_Z18transposeMtrxToVecPiS_S_i:
.LFB2059:
	.cfi_startproc
	endbr64
	jmp	_Z43__device_stub__Z18transposeMtrxToVecPiS_S_iPiS_S_i
	.cfi_endproc
.LFE2059:
	.size	_Z18transposeMtrxToVecPiS_S_i, .-_Z18transposeMtrxToVecPiS_S_i
	.section	.rodata.str1.1
.LC3:
	.string	"coalesced time X %f\n"
.LC4:
	.string	"coalesced time Y %f\n"
.LC5:
	.string	"non coalesced time %f\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2029:
	.cfi_startproc
	endbr64
	pushq	%r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	pushq	%r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	pushq	%rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	subq	$120, %rsp
	.cfi_def_cfa_offset 160
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	16(%rsp), %rdi
	call	cudaEventCreate@PLT
	movl	%eax, %edi
	call	_Z8cuAssert9cudaError
	leaq	24(%rsp), %rdi
	call	cudaEventCreate@PLT
	movl	%eax, %edi
	call	_Z8cuAssert9cudaError
	movl	$40000, %edi
	call	malloc@PLT
	movl	$40000, %edi
	movq	%rax, %rbp
	call	malloc@PLT
	movl	$400000000, %edi
	movq	%rax, %r12
	call	malloc@PLT
	movq	%rax, %rbx
	xorl	%eax, %eax
.L29:
	imulq	$40000, %rax, %rcx
	movl	%eax, %esi
	xorl	%edx, %edx
	addq	%rbx, %rcx
.L30:
	xorl	%edi, %edi
	cmpl	%eax, %edx
	sete	%dil
	movl	%edi, (%rcx,%rdx,4)
	incq	%rdx
	cmpq	$10000, %rdx
	jne	.L30
	movl	%esi, 0(%rbp,%rax,4)
	incq	%rax
	cmpq	$10000, %rax
	jne	.L29
	xorl	%eax, %eax
	movl	$40000, %esi
	leaq	32(%rsp), %rdi
	movq	%rax, 32(%rsp)
	movq	%rax, 40(%rsp)
	movq	%rax, 48(%rsp)
	call	cudaMalloc@PLT
	movl	%eax, %edi
	call	_Z8cuAssert9cudaError
	movl	$40000, %esi
	leaq	40(%rsp), %rdi
	call	cudaMalloc@PLT
	movl	%eax, %edi
	call	_Z8cuAssert9cudaError
	movl	$400000000, %esi
	leaq	48(%rsp), %rdi
	call	cudaMalloc@PLT
	movl	%eax, %edi
	call	_Z8cuAssert9cudaError
	movq	48(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbx, %rsi
	movl	$400000000, %edx
	call	cudaMemcpy@PLT
	movl	%eax, %edi
	call	_Z8cuAssert9cudaError
	movq	32(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbp, %rsi
	movl	$40000, %edx
	call	cudaMemcpy@PLT
	movl	%eax, %edi
	call	_Z8cuAssert9cudaError
	movl	$536870917, %eax
	xorl	%esi, %esi
	movq	16(%rsp), %rdi
	salq	$3, %rax
	movl	$1, 64(%rsp)
	movq	%rax, 56(%rsp)
	addq	$216, %rax
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	cudaEventRecord@PLT
	movl	%eax, %edi
	call	_Z8cuAssert9cudaError
	movl	76(%rsp), %ecx
	movl	64(%rsp), %esi
	xorl	%r9d, %r9d
	movq	68(%rsp), %rdx
	movq	56(%rsp), %rdi
	xorl	%r8d, %r8d
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L32
	movq	40(%rsp), %rdx
	movq	32(%rsp), %rsi
	movl	$10000, %ecx
	movq	48(%rsp), %rdi
	call	_Z33__device_stub__Z9mtrxToVecPiS_S_iPiS_S_i
.L32:
	movq	24(%rsp), %rdi
	xorl	%esi, %esi
	leaq	12(%rsp), %r13
	call	cudaEventRecord@PLT
	movl	%eax, %edi
	call	_Z8cuAssert9cudaError
	movq	24(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movl	%eax, %edi
	call	_Z8cuAssert9cudaError
	movq	24(%rsp), %rdx
	movq	16(%rsp), %rsi
	movq	%r13, %rdi
	call	cudaEventElapsedTime@PLT
	movl	%eax, %edi
	call	_Z8cuAssert9cudaError
	leaq	.LC3(%rip), %rsi
	movl	$2, %edi
	movb	$1, %al
	cvtss2sd	12(%rsp), %xmm0
	call	__printf_chk@PLT
	call	cudaGetLastError@PLT
	movl	%eax, %edi
	call	_Z8cuAssert9cudaError
	movq	40(%rsp), %rsi
	movl	$2, %ecx
	movq	%r12, %rdi
	movl	$40000, %edx
	call	cudaMemcpy@PLT
	movl	%eax, %edi
	call	_Z8cuAssert9cudaError
	movq	16(%rsp), %rdi
	xorl	%esi, %esi
	movabsq	$171798691841, %rax
	movq	%rax, 80(%rsp)
	movabsq	$1099511627777, %rax
	movl	$1, 88(%rsp)
	movq	%rax, 92(%rsp)
	movl	$1, 100(%rsp)
	call	cudaEventRecord@PLT
	movl	%eax, %edi
	call	_Z8cuAssert9cudaError
	movl	100(%rsp), %ecx
	movl	88(%rsp), %esi
	xorl	%r9d, %r9d
	movq	92(%rsp), %rdx
	movq	80(%rsp), %rdi
	xorl	%r8d, %r8d
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L33
	movq	40(%rsp), %rdx
	movq	32(%rsp), %rsi
	movl	$10000, %ecx
	movq	48(%rsp), %rdi
	call	_Z35__device_stub__Z10mtrxToVecYPiS_S_iPiS_S_i
.L33:
	movq	24(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movl	%eax, %edi
	call	_Z8cuAssert9cudaError
	movq	24(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movl	%eax, %edi
	call	_Z8cuAssert9cudaError
	movq	24(%rsp), %rdx
	movq	16(%rsp), %rsi
	movq	%r13, %rdi
	call	cudaEventElapsedTime@PLT
	movl	%eax, %edi
	call	_Z8cuAssert9cudaError
	leaq	.LC4(%rip), %rsi
	movl	$2, %edi
	movb	$1, %al
	cvtss2sd	12(%rsp), %xmm0
	call	__printf_chk@PLT
	call	cudaGetLastError@PLT
	movl	%eax, %edi
	call	_Z8cuAssert9cudaError
	movq	16(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movl	%eax, %edi
	call	_Z8cuAssert9cudaError
	movl	76(%rsp), %ecx
	movl	64(%rsp), %esi
	xorl	%r9d, %r9d
	movq	68(%rsp), %rdx
	movq	56(%rsp), %rdi
	xorl	%r8d, %r8d
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L34
	movq	40(%rsp), %rdx
	movq	32(%rsp), %rsi
	movl	$10000, %ecx
	movq	48(%rsp), %rdi
	call	_Z43__device_stub__Z18transposeMtrxToVecPiS_S_iPiS_S_i
.L34:
	movq	24(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movl	%eax, %edi
	call	_Z8cuAssert9cudaError
	movq	24(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movl	%eax, %edi
	call	_Z8cuAssert9cudaError
	movq	24(%rsp), %rdx
	movq	16(%rsp), %rsi
	movq	%r13, %rdi
	call	cudaEventElapsedTime@PLT
	movl	%eax, %edi
	call	_Z8cuAssert9cudaError
	leaq	.LC5(%rip), %rsi
	movl	$2, %edi
	movb	$1, %al
	cvtss2sd	12(%rsp), %xmm0
	call	__printf_chk@PLT
	call	cudaGetLastError@PLT
	movl	%eax, %edi
	call	_Z8cuAssert9cudaError
	movq	32(%rsp), %rdi
	call	cudaFree@PLT
	movl	%eax, %edi
	call	_Z8cuAssert9cudaError
	movq	40(%rsp), %rdi
	call	cudaFree@PLT
	movl	%eax, %edi
	call	_Z8cuAssert9cudaError
	movq	48(%rsp), %rdi
	call	cudaFree@PLT
	movl	%eax, %edi
	call	_Z8cuAssert9cudaError
	movq	%rbp, %rdi
	call	free@PLT
	movq	%r12, %rdi
	call	free@PLT
	movq	%rbx, %rdi
	call	free@PLT
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L35
	call	__stack_chk_fail@PLT
.L35:
	addq	$120, %rsp
	.cfi_def_cfa_offset 40
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2029:
	.size	main, .-main
	.section	.rodata.str1.1
.LC6:
	.string	"_Z18transposeMtrxToVecPiS_S_i"
.LC7:
	.string	"_Z10mtrxToVecYPiS_S_i"
.LC8:
	.string	"_Z9mtrxToVecPiS_S_i"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2061:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC6(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z18transposeMtrxToVecPiS_S_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC7(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z10mtrxToVecYPiS_S_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC8(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z9mtrxToVecPiS_S_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2061:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include <cstdio>
#define BLOCK_SIZE 256

__global__ void mtrxToVec(int* mtrx,int* vec, int* ans,int n){
	int idx=blockDim.x*blockIdx.x+threadIdx.x;
	while(idx<n){
		int sum=0;
		for(int i=0;i<n;i++)
			sum+=mtrx[n*i+idx]*vec[idx];
		ans[idx]=sum;
		idx+=gridDim.x*blockDim.x;
	}
	return;
}


__global__ void mtrxToVecY(int* mtrx,int* vec, int* ans,int n){
	int idy=blockDim.y*blockIdx.y+threadIdx.y;
	while(idy<n){
		int sum=0;
		for(int i=0;i<n;i++)
			sum+=mtrx[n*i+idy]*vec[idy];
		ans[idy]=sum;
		idy+=gridDim.y*blockDim.y;
	}
	return;
}

__global__ void transposeMtrxToVec(int* mtrx,int* vec, int* ans,int n){
	int idx=blockDim.x*blockIdx.x+threadIdx.x;
	while(idx<n){
		int sum=0;
		for(int i=0;i<n;i++)
			sum+=mtrx[n+idx*i]*vec[idx];
		ans[idx]=sum;
		idx+=gridDim.x*blockDim.x;
	}
	return;
}

__host__ void  cuAssert(hipError_t error){
	if(error!=hipSuccess){
		printf("%s\n",hipGetErrorString(error));
		exit(0);
	}
}

__host__ void print(int* ans,int n){
	for(int i=0;i<n;i++)
		printf("%5d ",ans[i]);
	printf("\n");
	return;
}

__host__ int main(int argc,char* argv[]){
	hipEvent_t start,stop;
	cuAssert(hipEventCreate(&start));
	cuAssert(hipEventCreate(&stop));
	float time;

	const int n=10000;
	size_t size=sizeof(int)*n;
	int* vec=(int*)malloc(size);
	int* ans=(int*)malloc(size);
	int* mtrx=(int*)malloc(size*n);

	for(int i=0;i<n;i++){
		for(int j=0;j<n;j++)
			mtrx[i*n+j]=(i==j)?(1):(0);
		vec[i]=i;
	}

	int* cuVec=NULL;
	int* cuAns=NULL;
	int* cuMtrx=NULL;
	cuAssert(hipMalloc((void**)&cuVec,size));
	cuAssert(hipMalloc((void**)&cuAns,size));
	cuAssert(hipMalloc((void**)&cuMtrx,size*n));

	cuAssert(hipMemcpy(cuMtrx,mtrx,size*n,hipMemcpyHostToDevice));
	cuAssert(hipMemcpy(cuVec,vec,size,hipMemcpyHostToDevice));

	dim3 grid((n+BLOCK_SIZE-1)/BLOCK_SIZE,1,1);
	dim3 block(BLOCK_SIZE,1,1);

//coalesced block 1D indexes
	cuAssert(hipEventRecord(start));
	mtrxToVec<<<grid,block>>>(cuMtrx,cuVec,cuAns,n);
	cuAssert(hipEventRecord(stop));
	cuAssert(hipEventSynchronize(stop));
	cuAssert(hipEventElapsedTime(&time,start,stop));
	printf("coalesced time X %f\n",time);
	cuAssert(hipGetLastError());
	cuAssert(hipMemcpy(ans,cuAns,size,hipMemcpyDeviceToHost));
	//print(ans,n);

	dim3 gridY(1,(n+BLOCK_SIZE-1)/BLOCK_SIZE,1);
	dim3 blockY(1,BLOCK_SIZE,1);	
	cuAssert(hipEventRecord(start));
	mtrxToVecY<<<gridY,blockY>>>(cuMtrx,cuVec,cuAns,n);
	cuAssert(hipEventRecord(stop));
	cuAssert(hipEventSynchronize(stop));
	cuAssert(hipEventElapsedTime(&time,start,stop));
	printf("coalesced time Y %f\n",time);
	cuAssert(hipGetLastError());
	
//Non coalesced block
	cuAssert(hipEventRecord(start));
	transposeMtrxToVec<<<grid,block>>>(cuMtrx,cuVec,cuAns,n);
	cuAssert(hipEventRecord(stop));
	cuAssert(hipEventSynchronize(stop));
	cuAssert(hipEventElapsedTime(&time,start,stop));
	printf("non coalesced time %f\n",time);
	cuAssert(hipGetLastError());

	cuAssert(hipFree(cuVec));
	cuAssert(hipFree(cuAns));
	cuAssert(hipFree(cuMtrx));

	free(vec);
	free(ans);
	free(mtrx);
	return 0;
}

	.text
	.file	"mtrxTovector.hip"
	.globl	_Z24__device_stub__mtrxToVecPiS_S_i # -- Begin function _Z24__device_stub__mtrxToVecPiS_S_i
	.type	_Z24__device_stub__mtrxToVecPiS_S_i,@function
_Z24__device_stub__mtrxToVecPiS_S_i:    # @_Z24__device_stub__mtrxToVecPiS_S_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	4(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z9mtrxToVecPiS_S_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z24__device_stub__mtrxToVecPiS_S_i, .Lfunc_end0-_Z24__device_stub__mtrxToVecPiS_S_i
	.cfi_endproc
                                        # -- End function
	.globl	_Z25__device_stub__mtrxToVecYPiS_S_i # -- Begin function _Z25__device_stub__mtrxToVecYPiS_S_i
	.type	_Z25__device_stub__mtrxToVecYPiS_S_i,@function
_Z25__device_stub__mtrxToVecYPiS_S_i:   # @_Z25__device_stub__mtrxToVecYPiS_S_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	4(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z10mtrxToVecYPiS_S_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z25__device_stub__mtrxToVecYPiS_S_i, .Lfunc_end1-_Z25__device_stub__mtrxToVecYPiS_S_i
	.cfi_endproc
                                        # -- End function
	.globl	_Z33__device_stub__transposeMtrxToVecPiS_S_i # -- Begin function _Z33__device_stub__transposeMtrxToVecPiS_S_i
	.type	_Z33__device_stub__transposeMtrxToVecPiS_S_i,@function
_Z33__device_stub__transposeMtrxToVecPiS_S_i: # @_Z33__device_stub__transposeMtrxToVecPiS_S_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	4(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z18transposeMtrxToVecPiS_S_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z33__device_stub__transposeMtrxToVecPiS_S_i, .Lfunc_end2-_Z33__device_stub__transposeMtrxToVecPiS_S_i
	.cfi_endproc
                                        # -- End function
	.globl	_Z8cuAssert10hipError_t         # -- Begin function _Z8cuAssert10hipError_t
	.type	_Z8cuAssert10hipError_t,@function
_Z8cuAssert10hipError_t:                # @_Z8cuAssert10hipError_t
	.cfi_startproc
# %bb.0:
	testl	%edi, %edi
	jne	.LBB3_2
# %bb.1:
	retq
.LBB3_2:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	hipGetErrorString
	movq	%rax, %rdi
	callq	puts@PLT
	xorl	%edi, %edi
	callq	exit
.Lfunc_end3:
	.size	_Z8cuAssert10hipError_t, .Lfunc_end3-_Z8cuAssert10hipError_t
	.cfi_endproc
                                        # -- End function
	.globl	_Z5printPii                     # -- Begin function _Z5printPii
	.type	_Z5printPii,@function
_Z5printPii:                            # @_Z5printPii
	.cfi_startproc
# %bb.0:
	testl	%esi, %esi
	jle	.LBB4_4
# %bb.1:                                # %.lr.ph.preheader
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movq	%rdi, %rbx
	movl	%esi, %r14d
	xorl	%r15d, %r15d
.LBB4_2:                                # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	movl	(%rbx,%r15,4), %esi
	movl	$.L.str.1, %edi
	xorl	%eax, %eax
	callq	printf
	incq	%r15
	cmpq	%r15, %r14
	jne	.LBB4_2
# %bb.3:
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	.cfi_restore %rbx
	.cfi_restore %r14
	.cfi_restore %r15
.LBB4_4:                                # %._crit_edge
	movl	$10, %edi
	jmp	putchar@PLT                     # TAILCALL
.Lfunc_end4:
	.size	_Z5printPii, .Lfunc_end4-_Z5printPii
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$56, %rsp
	.cfi_def_cfa_offset 112
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	leaq	8(%rsp), %rdi
	callq	hipEventCreate
	movl	%eax, %edi
	callq	_Z8cuAssert10hipError_t
	movq	%rsp, %rdi
	callq	hipEventCreate
	movl	%eax, %edi
	callq	_Z8cuAssert10hipError_t
	movl	$40000, %edi                    # imm = 0x9C40
	callq	malloc
	movq	%rax, %rbx
	movl	$40000, %edi                    # imm = 0x9C40
	callq	malloc
	movq	%rax, %r12
	movl	$400000000, %edi                # imm = 0x17D78400
	callq	malloc
	movq	%rax, %rcx
	xorl	%eax, %eax
	movq	%rcx, 48(%rsp)                  # 8-byte Spill
.LBB5_1:                                # %.preheader
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB5_2 Depth 2
	xorl	%edx, %edx
.LBB5_2:                                #   Parent Loop BB5_1 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	xorl	%esi, %esi
	cmpq	%rdx, %rax
	sete	%sil
	movl	%esi, (%rcx,%rdx,4)
	incq	%rdx
	cmpq	$10000, %rdx                    # imm = 0x2710
	jne	.LBB5_2
# %bb.3:                                #   in Loop: Header=BB5_1 Depth=1
	movl	%eax, (%rbx,%rax,4)
	incq	%rax
	addq	$40000, %rcx                    # imm = 0x9C40
	cmpq	$10000, %rax                    # imm = 0x2710
	jne	.LBB5_1
# %bb.4:
	movabsq	$4294967336, %r15               # imm = 0x100000028
	xorl	%eax, %eax
	leaq	40(%rsp), %r13
	movq	%rax, (%r13)
	leaq	16(%rsp), %r14
	movq	%rax, (%r14)
	leaq	32(%rsp), %rbp
	movq	%rax, (%rbp)
	movl	$40000, %esi                    # imm = 0x9C40
	movq	%r13, %rdi
	callq	hipMalloc
	movl	%eax, %edi
	callq	_Z8cuAssert10hipError_t
	movl	$40000, %esi                    # imm = 0x9C40
	movq	%r14, %rdi
	callq	hipMalloc
	movl	%eax, %edi
	callq	_Z8cuAssert10hipError_t
	movl	$400000000, %esi                # imm = 0x17D78400
	movq	%rbp, %rdi
	callq	hipMalloc
	movl	%eax, %edi
	callq	_Z8cuAssert10hipError_t
	movq	(%rbp), %rdi
	movl	$400000000, %edx                # imm = 0x17D78400
	movq	48(%rsp), %rsi                  # 8-byte Reload
	movl	$1, %ecx
	callq	hipMemcpy
	movl	%eax, %edi
	callq	_Z8cuAssert10hipError_t
	movq	(%r13), %rdi
	movl	$40000, %edx                    # imm = 0x9C40
	movq	%rbx, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movl	%eax, %edi
	callq	_Z8cuAssert10hipError_t
	movq	8(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movl	%eax, %edi
	callq	_Z8cuAssert10hipError_t
	leaq	216(%r15), %r13
	movq	%r15, %rdi
	movl	$1, %esi
	movq	%r13, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB5_6
# %bb.5:
	movq	32(%rsp), %rdi
	movq	40(%rsp), %rsi
	movq	16(%rsp), %rdx
	movl	$10000, %ecx                    # imm = 0x2710
	callq	_Z24__device_stub__mtrxToVecPiS_S_i
.LBB5_6:
	movq	(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movl	%eax, %edi
	callq	_Z8cuAssert10hipError_t
	movq	(%rsp), %rdi
	callq	hipEventSynchronize
	movl	%eax, %edi
	callq	_Z8cuAssert10hipError_t
	movq	8(%rsp), %rsi
	movq	(%rsp), %rdx
	leaq	28(%rsp), %r14
	movq	%r14, %rdi
	callq	hipEventElapsedTime
	movl	%eax, %edi
	callq	_Z8cuAssert10hipError_t
	cvtss2sd	(%r14), %xmm0
	movl	$.L.str.3, %edi
	movb	$1, %al
	callq	printf
	callq	hipGetLastError
	movl	%eax, %edi
	callq	_Z8cuAssert10hipError_t
	movq	16(%rsp), %rsi
	movl	$40000, %edx                    # imm = 0x9C40
	movq	%r12, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movl	%eax, %edi
	callq	_Z8cuAssert10hipError_t
	movq	8(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movl	%eax, %edi
	callq	_Z8cuAssert10hipError_t
	movabsq	$171798691841, %rdi             # imm = 0x2800000001
	movabsq	$1099511627777, %rdx            # imm = 0x10000000001
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB5_8
# %bb.7:
	movq	32(%rsp), %rdi
	movq	40(%rsp), %rsi
	movq	16(%rsp), %rdx
	movl	$10000, %ecx                    # imm = 0x2710
	callq	_Z25__device_stub__mtrxToVecYPiS_S_i
.LBB5_8:
	movq	(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movl	%eax, %edi
	callq	_Z8cuAssert10hipError_t
	movq	(%rsp), %rdi
	callq	hipEventSynchronize
	movl	%eax, %edi
	callq	_Z8cuAssert10hipError_t
	movq	8(%rsp), %rsi
	movq	(%rsp), %rdx
	leaq	28(%rsp), %r14
	movq	%r14, %rdi
	callq	hipEventElapsedTime
	movl	%eax, %edi
	callq	_Z8cuAssert10hipError_t
	xorps	%xmm0, %xmm0
	cvtss2sd	(%r14), %xmm0
	movl	$.L.str.4, %edi
	movb	$1, %al
	callq	printf
	callq	hipGetLastError
	movl	%eax, %edi
	callq	_Z8cuAssert10hipError_t
	movq	8(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movl	%eax, %edi
	callq	_Z8cuAssert10hipError_t
	movabsq	$4294967336, %rdi               # imm = 0x100000028
	movl	$1, %esi
	movq	%r13, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB5_10
# %bb.9:
	movq	32(%rsp), %rdi
	movq	40(%rsp), %rsi
	movq	16(%rsp), %rdx
	movl	$10000, %ecx                    # imm = 0x2710
	callq	_Z33__device_stub__transposeMtrxToVecPiS_S_i
.LBB5_10:
	movq	(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movl	%eax, %edi
	callq	_Z8cuAssert10hipError_t
	movq	(%rsp), %rdi
	callq	hipEventSynchronize
	movl	%eax, %edi
	callq	_Z8cuAssert10hipError_t
	movq	8(%rsp), %rsi
	movq	(%rsp), %rdx
	leaq	28(%rsp), %r14
	movq	%r14, %rdi
	callq	hipEventElapsedTime
	movl	%eax, %edi
	callq	_Z8cuAssert10hipError_t
	xorps	%xmm0, %xmm0
	cvtss2sd	(%r14), %xmm0
	movl	$.L.str.5, %edi
	movb	$1, %al
	callq	printf
	callq	hipGetLastError
	movl	%eax, %edi
	callq	_Z8cuAssert10hipError_t
	movq	40(%rsp), %rdi
	callq	hipFree
	movl	%eax, %edi
	callq	_Z8cuAssert10hipError_t
	movq	16(%rsp), %rdi
	callq	hipFree
	movl	%eax, %edi
	callq	_Z8cuAssert10hipError_t
	movq	32(%rsp), %rdi
	callq	hipFree
	movl	%eax, %edi
	callq	_Z8cuAssert10hipError_t
	movq	%rbx, %rdi
	callq	free
	movq	%r12, %rdi
	callq	free
	movq	48(%rsp), %rdi                  # 8-byte Reload
	callq	free
	xorl	%eax, %eax
	addq	$56, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end5:
	.size	main, .Lfunc_end5-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB6_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB6_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z9mtrxToVecPiS_S_i, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z10mtrxToVecYPiS_S_i, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z18transposeMtrxToVecPiS_S_i, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end6:
	.size	__hip_module_ctor, .Lfunc_end6-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB7_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB7_2:
	retq
.Lfunc_end7:
	.size	__hip_module_dtor, .Lfunc_end7-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z9mtrxToVecPiS_S_i,@object     # @_Z9mtrxToVecPiS_S_i
	.section	.rodata,"a",@progbits
	.globl	_Z9mtrxToVecPiS_S_i
	.p2align	3, 0x0
_Z9mtrxToVecPiS_S_i:
	.quad	_Z24__device_stub__mtrxToVecPiS_S_i
	.size	_Z9mtrxToVecPiS_S_i, 8

	.type	_Z10mtrxToVecYPiS_S_i,@object   # @_Z10mtrxToVecYPiS_S_i
	.globl	_Z10mtrxToVecYPiS_S_i
	.p2align	3, 0x0
_Z10mtrxToVecYPiS_S_i:
	.quad	_Z25__device_stub__mtrxToVecYPiS_S_i
	.size	_Z10mtrxToVecYPiS_S_i, 8

	.type	_Z18transposeMtrxToVecPiS_S_i,@object # @_Z18transposeMtrxToVecPiS_S_i
	.globl	_Z18transposeMtrxToVecPiS_S_i
	.p2align	3, 0x0
_Z18transposeMtrxToVecPiS_S_i:
	.quad	_Z33__device_stub__transposeMtrxToVecPiS_S_i
	.size	_Z18transposeMtrxToVecPiS_S_i, 8

	.type	.L.str.1,@object                # @.str.1
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str.1:
	.asciz	"%5d "
	.size	.L.str.1, 5

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"coalesced time X %f\n"
	.size	.L.str.3, 21

	.type	.L.str.4,@object                # @.str.4
.L.str.4:
	.asciz	"coalesced time Y %f\n"
	.size	.L.str.4, 21

	.type	.L.str.5,@object                # @.str.5
.L.str.5:
	.asciz	"non coalesced time %f\n"
	.size	.L.str.5, 23

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z9mtrxToVecPiS_S_i"
	.size	.L__unnamed_1, 20

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z10mtrxToVecYPiS_S_i"
	.size	.L__unnamed_2, 22

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z18transposeMtrxToVecPiS_S_i"
	.size	.L__unnamed_3, 30

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z24__device_stub__mtrxToVecPiS_S_i
	.addrsig_sym _Z25__device_stub__mtrxToVecYPiS_S_i
	.addrsig_sym _Z33__device_stub__transposeMtrxToVecPiS_S_i
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z9mtrxToVecPiS_S_i
	.addrsig_sym _Z10mtrxToVecYPiS_S_i
	.addrsig_sym _Z18transposeMtrxToVecPiS_S_i
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z9mtrxToVecPiS_S_i     ; -- Begin function _Z9mtrxToVecPiS_S_i
	.globl	_Z9mtrxToVecPiS_S_i
	.p2align	8
	.type	_Z9mtrxToVecPiS_S_i,@function
_Z9mtrxToVecPiS_S_i:                    ; @_Z9mtrxToVecPiS_S_i
; %bb.0:
	s_clause 0x1
	s_load_b32 s3, s[0:1], 0x2c
	s_load_b32 s2, s[0:1], 0x18
	s_add_u32 s4, s0, 32
	s_addc_u32 s5, s1, 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s10, s3, 0xffff
	s_mov_b32 s3, exec_lo
	v_mad_u64_u32 v[1:2], null, s15, s10, v[0:1]
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e64 s2, v1
	s_cbranch_execz .LBB0_7
; %bb.1:                                ; %.preheader.lr.ph
	s_load_b32 s13, s[4:5], 0x0
	s_clause 0x1
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b64 s[8:9], s[0:1], 0x10
	s_cmp_gt_i32 s2, 0
	s_mov_b32 s1, 0
	s_cselect_b32 s12, -1, 0
	s_ashr_i32 s3, s2, 31
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s13, s13, s10
	s_lshl_b64 s[10:11], s[2:3], 2
.LBB0_2:                                ; %.preheader
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_4 Depth 2
	v_ashrrev_i32_e32 v2, 31, v1
	s_and_not1_b32 vcc_lo, exec_lo, s12
	s_delay_alu instid0(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[1:2]
	s_cbranch_vccnz .LBB0_5
; %bb.3:                                ; %.lr.ph
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, s6, v2
	v_add_co_ci_u32_e32 v5, vcc_lo, s7, v3, vcc_lo
	v_mov_b32_e32 v0, 0
	s_mov_b32 s0, s2
	global_load_b32 v6, v[4:5], off
	v_add_co_u32 v4, vcc_lo, s4, v2
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
.LBB0_4:                                ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	global_load_b32 v9, v[4:5], off
	v_add_co_u32 v4, vcc_lo, v4, s10
	v_add_co_ci_u32_e32 v5, vcc_lo, s11, v5, vcc_lo
	s_add_i32 s0, s0, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	s_cmp_eq_u32 s0, 0
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[7:8], null, v6, v9, v[0:1]
	v_mov_b32_e32 v0, v7
	s_cbranch_scc0 .LBB0_4
	s_branch .LBB0_6
.LBB0_5:                                ;   in Loop: Header=BB0_2 Depth=1
	v_mov_b32_e32 v0, 0
.LBB0_6:                                ; %Flow38
                                        ;   in Loop: Header=BB0_2 Depth=1
	v_add_nc_u32_e32 v1, s13, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v2, s0, s8, v2
	v_add_co_ci_u32_e64 v3, s0, s9, v3, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_cmp_le_i32_e32 vcc_lo, s2, v1
	global_store_b32 v[2:3], v0, off
	s_or_b32 s1, vcc_lo, s1
	s_and_not1_b32 exec_lo, exec_lo, s1
	s_cbranch_execnz .LBB0_2
.LBB0_7:                                ; %._crit_edge25
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z9mtrxToVecPiS_S_i
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 10
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z9mtrxToVecPiS_S_i, .Lfunc_end0-_Z9mtrxToVecPiS_S_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 316
; NumSgprs: 18
; NumVgprs: 10
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 10
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z10mtrxToVecYPiS_S_i   ; -- Begin function _Z10mtrxToVecYPiS_S_i
	.globl	_Z10mtrxToVecYPiS_S_i
	.p2align	8
	.type	_Z10mtrxToVecYPiS_S_i,@function
_Z10mtrxToVecYPiS_S_i:                  ; @_Z10mtrxToVecYPiS_S_i
; %bb.0:
	s_clause 0x1
	s_load_b32 s3, s[0:1], 0x2c
	s_load_b32 s2, s[0:1], 0x18
	v_bfe_u32 v2, v0, 10, 10
	s_add_u32 s4, s0, 32
	s_addc_u32 s5, s1, 0
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s10, s3, 16
	s_mov_b32 s3, exec_lo
	v_mad_u64_u32 v[0:1], null, s15, s10, v[2:3]
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e64 s2, v0
	s_cbranch_execz .LBB1_7
; %bb.1:                                ; %.preheader.lr.ph
	s_load_b32 s13, s[4:5], 0x4
	s_clause 0x1
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b64 s[8:9], s[0:1], 0x10
	s_cmp_gt_i32 s2, 0
	s_mov_b32 s1, 0
	s_cselect_b32 s12, -1, 0
	s_ashr_i32 s3, s2, 31
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s13, s13, s10
	s_lshl_b64 s[10:11], s[2:3], 2
.LBB1_2:                                ; %.preheader
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB1_4 Depth 2
	v_ashrrev_i32_e32 v1, 31, v0
	s_and_not1_b32 vcc_lo, exec_lo, s12
	s_delay_alu instid0(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[0:1]
	s_cbranch_vccnz .LBB1_5
; %bb.3:                                ; %.lr.ph
                                        ;   in Loop: Header=BB1_2 Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, s6, v1
	v_add_co_ci_u32_e32 v4, vcc_lo, s7, v2, vcc_lo
	s_mov_b32 s0, s2
	global_load_b32 v6, v[3:4], off
	v_add_co_u32 v4, vcc_lo, s4, v1
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v2, vcc_lo
	v_mov_b32_e32 v3, 0
.LBB1_4:                                ;   Parent Loop BB1_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	global_load_b32 v9, v[4:5], off
	s_add_i32 s0, s0, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_3)
	s_cmp_eq_u32 s0, 0
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[7:8], null, v6, v9, v[3:4]
	v_add_co_u32 v4, vcc_lo, v4, s10
	v_add_co_ci_u32_e32 v5, vcc_lo, s11, v5, vcc_lo
	v_mov_b32_e32 v3, v7
	s_cbranch_scc0 .LBB1_4
	s_branch .LBB1_6
.LBB1_5:                                ;   in Loop: Header=BB1_2 Depth=1
	v_mov_b32_e32 v3, 0
.LBB1_6:                                ; %Flow38
                                        ;   in Loop: Header=BB1_2 Depth=1
	v_add_nc_u32_e32 v0, s13, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v1, s0, s8, v1
	v_add_co_ci_u32_e64 v2, s0, s9, v2, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_cmp_le_i32_e32 vcc_lo, s2, v0
	global_store_b32 v[1:2], v3, off
	s_or_b32 s1, vcc_lo, s1
	s_and_not1_b32 exec_lo, exec_lo, s1
	s_cbranch_execnz .LBB1_2
.LBB1_7:                                ; %._crit_edge25
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z10mtrxToVecYPiS_S_i
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 10
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z10mtrxToVecYPiS_S_i, .Lfunc_end1-_Z10mtrxToVecYPiS_S_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 320
; NumSgprs: 18
; NumVgprs: 10
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 10
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z18transposeMtrxToVecPiS_S_i ; -- Begin function _Z18transposeMtrxToVecPiS_S_i
	.globl	_Z18transposeMtrxToVecPiS_S_i
	.p2align	8
	.type	_Z18transposeMtrxToVecPiS_S_i,@function
_Z18transposeMtrxToVecPiS_S_i:          ; @_Z18transposeMtrxToVecPiS_S_i
; %bb.0:
	s_clause 0x1
	s_load_b32 s3, s[0:1], 0x2c
	s_load_b32 s2, s[0:1], 0x18
	s_add_u32 s4, s0, 32
	s_addc_u32 s5, s1, 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s11, s3, 0xffff
	s_mov_b32 s3, exec_lo
	v_mad_u64_u32 v[1:2], null, s15, s11, v[0:1]
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e64 s2, v1
	s_cbranch_execz .LBB2_7
; %bb.1:                                ; %.preheader.lr.ph
	s_load_b32 s14, s[4:5], 0x0
	s_clause 0x1
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b64 s[8:9], s[0:1], 0x10
	s_cmp_gt_i32 s2, 0
	s_mov_b32 s1, 0
	s_cselect_b32 s10, -1, 0
	s_ashr_i32 s3, s2, 31
	s_delay_alu instid0(SALU_CYCLE_1)
	s_lshl_b64 s[12:13], s[2:3], 2
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s3, s14, s11
	s_add_u32 s4, s4, s12
	s_addc_u32 s5, s5, s13
.LBB2_2:                                ; %.preheader
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB2_4 Depth 2
	v_ashrrev_i32_e32 v2, 31, v1
	s_and_not1_b32 vcc_lo, exec_lo, s10
	s_delay_alu instid0(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[1:2]
	s_cbranch_vccnz .LBB2_5
; %bb.3:                                ; %.lr.ph
                                        ;   in Loop: Header=BB2_2 Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, s6, v2
	v_add_co_ci_u32_e32 v5, vcc_lo, s7, v3, vcc_lo
	v_mov_b32_e32 v0, 0
	s_mov_b32 s0, s2
	global_load_b32 v6, v[4:5], off
	v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v5, s5
.LBB2_4:                                ;   Parent Loop BB2_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	global_load_b32 v9, v[4:5], off
	v_add_co_u32 v4, vcc_lo, v4, v2
	v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
	s_add_i32 s0, s0, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	s_cmp_eq_u32 s0, 0
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[7:8], null, v6, v9, v[0:1]
	v_mov_b32_e32 v0, v7
	s_cbranch_scc0 .LBB2_4
	s_branch .LBB2_6
.LBB2_5:                                ;   in Loop: Header=BB2_2 Depth=1
	v_mov_b32_e32 v0, 0
.LBB2_6:                                ; %Flow38
                                        ;   in Loop: Header=BB2_2 Depth=1
	v_add_nc_u32_e32 v1, s3, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v2, s0, s8, v2
	v_add_co_ci_u32_e64 v3, s0, s9, v3, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_cmp_le_i32_e32 vcc_lo, s2, v1
	global_store_b32 v[2:3], v0, off
	s_or_b32 s1, vcc_lo, s1
	s_and_not1_b32 exec_lo, exec_lo, s1
	s_cbranch_execnz .LBB2_2
.LBB2_7:                                ; %._crit_edge25
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z18transposeMtrxToVecPiS_S_i
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 10
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_Z18transposeMtrxToVecPiS_S_i, .Lfunc_end2-_Z18transposeMtrxToVecPiS_S_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 324
; NumSgprs: 18
; NumVgprs: 10
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 10
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z9mtrxToVecPiS_S_i
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z9mtrxToVecPiS_S_i.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     10
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
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    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
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      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z10mtrxToVecYPiS_S_i
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z10mtrxToVecYPiS_S_i.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     10
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
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        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
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        .size:           8
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        .size:           4
        .value_kind:     by_value
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        .size:           4
        .value_kind:     hidden_block_count_x
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        .size:           4
        .value_kind:     hidden_block_count_y
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        .size:           4
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        .value_kind:     hidden_global_offset_z
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        .value_kind:     hidden_grid_dims
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    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
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    .name:           _Z18transposeMtrxToVecPiS_S_i
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    .sgpr_spill_count: 0
    .symbol:         _Z18transposeMtrxToVecPiS_S_i.kd
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    .vgpr_spill_count: 0
    .wavefront_size: 32
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amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
