/**
 *  Implementation of Hillis-Steele parallel prefix scan.
 */

#include <stdio.h>
#include <stdlib.h>
#include <cuda_runtime.h>

template <typename T>
__global__ void exclusiveScanKernel(T *dataOut, const T *dataIn, const size_t dataSize) {
    extern __shared__ T shmData[];

    int thId = threadIdx.x;
    int bufA = 0, bufB = 1;

    // Load everything into shared memory. We need to copy twice to fill the shared memory space
    shmData[bufA * dataSize + thId] = (thId == 0) ? 0 : dataIn[thId - 1];
    shmData[bufB * dataSize + thId] = (thId == 0) ? 0 : dataIn[thId - 1];
    __syncthreads();

    for (int offset = 1; offset < dataSize; offset <<= 1) {
        // Swap which side of the buffer we're writing into
        bufA = 1 - bufA;
        bufB = 1 - bufA;
        // Do scan step
        if (thId >= offset) {
            shmData[bufA * dataSize + thId] = shmData[bufB * dataSize + thId] + 
                                                    shmData[bufB * dataSize + thId - offset];
        } else {
            shmData[bufA * dataSize + thId] = shmData[bufB * dataSize + thId];
        }

        __syncthreads();
    }
    // Write to output array
    dataOut[thId] = shmData[bufA * dataSize + thId];
    printf("Thread %d = %d\n", thId, dataOut[thId]);
}

//template <typename T>
//void launchScanKernel(T *h_dataOut, const T *h_dataIn, const size_t dataSize) {
void launchScanKernel(int *h_dataOut, const int *h_dataIn, const size_t dataSize, float *execTime = nullptr) {
    const size_t dataBytes = dataSize * sizeof(int);

    // Declare GPU memory pointers
    int *d_dataOut, *d_dataIn;

    // Set up GPU timers
    cudaEvent_t start, stop;
    cudaEventCreate(&start);
    cudaEventCreate(&stop);

    // Allocate GPU memory
    cudaMalloc((void **) &d_dataOut, dataBytes);
    cudaMalloc((void **) &d_dataIn, dataBytes);

    cudaMemcpy(d_dataIn, h_dataIn, dataBytes, cudaMemcpyHostToDevice);

    // Execute kernel and record runtime
    const unsigned int blocks = 1;
    const unsigned int threads = (dataSize) / blocks;
    cudaEventRecord(start);
    exclusiveScanKernel<<<blocks, threads, dataBytes>>>(d_dataOut, d_dataIn, dataSize);
    cudaEventRecord(stop);

    // Copy back from GPU to CPU
    cudaMemcpy(h_dataOut, d_dataOut, dataBytes, cudaMemcpyDeviceToHost);

    cudaEventSynchronize(stop);
    float timeInMs = 0;
    cudaEventElapsedTime(&timeInMs, start, stop);
    *execTime = timeInMs;

    // Free memory
    cudaFree(d_dataIn);
    cudaFree(d_dataOut);
}

//template void launchScanKernel<int>(int *h_dataOut, const int *h_dataIn, const size_t dataSize);
	.file	"tmpxft_003264e6_00000000-6_HillisSteeleScan.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2032:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2032:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.type	_ZL50__device_stub__Z19exclusiveScanKernelIiEvPT_PKS0_mPiPKim, @function
_ZL50__device_stub__Z19exclusiveScanKernelIiEvPT_PKS0_mPiPKim:
.LFB2054:
	.cfi_startproc
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z19exclusiveScanKernelIiEvPT_PKS0_m(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L2:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2054:
	.size	_ZL50__device_stub__Z19exclusiveScanKernelIiEvPT_PKS0_mPiPKim, .-_ZL50__device_stub__Z19exclusiveScanKernelIiEvPT_PKS0_mPiPKim
	.section	.text._Z19exclusiveScanKernelIiEvPT_PKS0_m,"axG",@progbits,_Z19exclusiveScanKernelIiEvPT_PKS0_m,comdat
	.weak	_Z19exclusiveScanKernelIiEvPT_PKS0_m
	.type	_Z19exclusiveScanKernelIiEvPT_PKS0_m, @function
_Z19exclusiveScanKernelIiEvPT_PKS0_m:
.LFB2103:
	.cfi_startproc
	endbr64
	jmp	_ZL50__device_stub__Z19exclusiveScanKernelIiEvPT_PKS0_mPiPKim
	.cfi_endproc
.LFE2103:
	.size	_Z19exclusiveScanKernelIiEvPT_PKS0_m, .-_Z19exclusiveScanKernelIiEvPT_PKS0_m
	.text
	.globl	_Z16launchScanKernelPiPKimPf
	.type	_Z16launchScanKernelPiPKimPf, @function
_Z16launchScanKernelPiPKimPf:
.LFB2029:
	.cfi_startproc
	endbr64
	pushq	%r14
	.cfi_def_cfa_offset 16
	.cfi_offset 14, -16
	movq	%rsi, %r14
	pushq	%r13
	.cfi_def_cfa_offset 24
	.cfi_offset 13, -24
	movq	%rdi, %r13
	pushq	%r12
	.cfi_def_cfa_offset 32
	.cfi_offset 12, -32
	movq	%rcx, %r12
	pushq	%rbp
	.cfi_def_cfa_offset 40
	.cfi_offset 6, -40
	movq	%rdx, %rbp
	pushq	%rbx
	.cfi_def_cfa_offset 48
	.cfi_offset 3, -48
	leaq	0(,%rdx,4), %rbx
	subq	$64, %rsp
	.cfi_def_cfa_offset 112
	movq	%fs:40, %rax
	movq	%rax, 56(%rsp)
	xorl	%eax, %eax
	leaq	16(%rsp), %rdi
	call	cudaEventCreate@PLT
	leaq	24(%rsp), %rdi
	call	cudaEventCreate@PLT
	movq	%rsp, %rdi
	movq	%rbx, %rsi
	call	cudaMalloc@PLT
	leaq	8(%rsp), %rdi
	movq	%rbx, %rsi
	call	cudaMalloc@PLT
	movq	8(%rsp), %rdi
	movq	%rbx, %rdx
	movq	%r14, %rsi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	movq	16(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movl	%ebp, 44(%rsp)
	xorl	%r9d, %r9d
	movq	%rbx, %r8
	movabsq	$4294967297, %rdi
	movl	$1, %esi
	movq	%rdi, 48(%rsp)
	movl	52(%rsp), %ecx
	movq	44(%rsp), %rdx
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L9
	movq	8(%rsp), %rsi
	movq	(%rsp), %rdi
	movq	%rbp, %rdx
	call	_ZL50__device_stub__Z19exclusiveScanKernelIiEvPT_PKS0_mPiPKim
.L9:
	movq	24(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movq	(%rsp), %rsi
	movq	%rbx, %rdx
	movq	%r13, %rdi
	movl	$2, %ecx
	call	cudaMemcpy@PLT
	movq	24(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movq	24(%rsp), %rdx
	movq	16(%rsp), %rsi
	leaq	44(%rsp), %rdi
	movl	$0x00000000, 44(%rsp)
	call	cudaEventElapsedTime@PLT
	movss	44(%rsp), %xmm0
	movq	8(%rsp), %rdi
	movss	%xmm0, (%r12)
	call	cudaFree@PLT
	movq	(%rsp), %rdi
	call	cudaFree@PLT
	movq	56(%rsp), %rax
	subq	%fs:40, %rax
	je	.L10
	call	__stack_chk_fail@PLT
.L10:
	addq	$64, %rsp
	.cfi_def_cfa_offset 48
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%rbp
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r13
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2029:
	.size	_Z16launchScanKernelPiPKimPf, .-_Z16launchScanKernelPiPKimPf
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC1:
	.string	"_Z19exclusiveScanKernelIiEvPT_PKS0_m"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2057:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC1(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z19exclusiveScanKernelIiEvPT_PKS0_m(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2057:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

/**
 *  Implementation of Hillis-Steele parallel prefix scan.
 */

#include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>

template <typename T>
__global__ void exclusiveScanKernel(T *dataOut, const T *dataIn, const size_t dataSize) {
    extern __shared__ T shmData[];

    int thId = threadIdx.x;
    int bufA = 0, bufB = 1;

    // Load everything into shared memory. We need to copy twice to fill the shared memory space
    shmData[bufA * dataSize + thId] = (thId == 0) ? 0 : dataIn[thId - 1];
    shmData[bufB * dataSize + thId] = (thId == 0) ? 0 : dataIn[thId - 1];
    __syncthreads();

    for (int offset = 1; offset < dataSize; offset <<= 1) {
        // Swap which side of the buffer we're writing into
        bufA = 1 - bufA;
        bufB = 1 - bufA;
        // Do scan step
        if (thId >= offset) {
            shmData[bufA * dataSize + thId] = shmData[bufB * dataSize + thId] + 
                                                    shmData[bufB * dataSize + thId - offset];
        } else {
            shmData[bufA * dataSize + thId] = shmData[bufB * dataSize + thId];
        }

        __syncthreads();
    }
    // Write to output array
    dataOut[thId] = shmData[bufA * dataSize + thId];
    printf("Thread %d = %d\n", thId, dataOut[thId]);
}

//template <typename T>
//void launchScanKernel(T *h_dataOut, const T *h_dataIn, const size_t dataSize) {
void launchScanKernel(int *h_dataOut, const int *h_dataIn, const size_t dataSize, float *execTime = nullptr) {
    const size_t dataBytes = dataSize * sizeof(int);

    // Declare GPU memory pointers
    int *d_dataOut, *d_dataIn;

    // Set up GPU timers
    hipEvent_t start, stop;
    hipEventCreate(&start);
    hipEventCreate(&stop);

    // Allocate GPU memory
    hipMalloc((void **) &d_dataOut, dataBytes);
    hipMalloc((void **) &d_dataIn, dataBytes);

    hipMemcpy(d_dataIn, h_dataIn, dataBytes, hipMemcpyHostToDevice);

    // Execute kernel and record runtime
    const unsigned int blocks = 1;
    const unsigned int threads = (dataSize) / blocks;
    hipEventRecord(start);
    exclusiveScanKernel<<<blocks, threads, dataBytes>>>(d_dataOut, d_dataIn, dataSize);
    hipEventRecord(stop);

    // Copy back from GPU to CPU
    hipMemcpy(h_dataOut, d_dataOut, dataBytes, hipMemcpyDeviceToHost);

    hipEventSynchronize(stop);
    float timeInMs = 0;
    hipEventElapsedTime(&timeInMs, start, stop);
    *execTime = timeInMs;

    // Free memory
    hipFree(d_dataIn);
    hipFree(d_dataOut);
}

//template void launchScanKernel<int>(int *h_dataOut, const int *h_dataIn, const size_t dataSize);
	.text
	.file	"HillisSteeleScan.hip"
	.globl	_Z16launchScanKernelPiPKimPf    # -- Begin function _Z16launchScanKernelPiPKimPf
	.type	_Z16launchScanKernelPiPKimPf,@function
_Z16launchScanKernelPiPKimPf:           # @_Z16launchScanKernelPiPKimPf
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$56, %rsp
	.cfi_def_cfa_offset 112
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%rcx, 32(%rsp)                  # 8-byte Spill
	movq	%rdx, %r12
	movq	%rsi, %r13
	movq	%rdi, %r15
	leaq	(,%rdx,4), %r14
	leaq	40(%rsp), %rbp
	movq	%rbp, %rdi
	callq	hipEventCreate
	leaq	8(%rsp), %rdi
	callq	hipEventCreate
	leaq	16(%rsp), %rdi
	movq	%r14, %rsi
	callq	hipMalloc
	leaq	24(%rsp), %rbx
	movq	%rbx, %rdi
	movq	%r14, %rsi
	callq	hipMalloc
	movq	(%rbx), %rdi
	movq	%r13, %rsi
	movq	%r14, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%rbp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movl	%r12d, %edx
	btsq	$32, %rdx
	movabsq	$4294967296, %rdi               # imm = 0x100000000
	orq	$1, %rdi
	movl	$1, %esi
	movl	$1, %ecx
	movq	%r14, %r8
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB0_2
# %bb.1:
	movq	16(%rsp), %rdi
	movq	24(%rsp), %rsi
	movq	%r12, %rdx
	callq	_Z34__device_stub__exclusiveScanKernelIiEvPT_PKS0_m
.LBB0_2:
	movq	8(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	16(%rsp), %rsi
	movq	%r15, %rdi
	movq	%r14, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	movq	8(%rsp), %rdi
	callq	hipEventSynchronize
	leaq	52(%rsp), %rbx
	movl	$0, (%rbx)
	movq	40(%rsp), %rsi
	movq	8(%rsp), %rdx
	movq	%rbx, %rdi
	callq	hipEventElapsedTime
	movss	(%rbx), %xmm0                   # xmm0 = mem[0],zero,zero,zero
	movq	32(%rsp), %rax                  # 8-byte Reload
	movss	%xmm0, (%rax)
	movq	24(%rsp), %rdi
	callq	hipFree
	movq	16(%rsp), %rdi
	callq	hipFree
	addq	$56, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z16launchScanKernelPiPKimPf, .Lfunc_end0-_Z16launchScanKernelPiPKimPf
	.cfi_endproc
                                        # -- End function
	.section	.text._Z34__device_stub__exclusiveScanKernelIiEvPT_PKS0_m,"axG",@progbits,_Z34__device_stub__exclusiveScanKernelIiEvPT_PKS0_m,comdat
	.weak	_Z34__device_stub__exclusiveScanKernelIiEvPT_PKS0_m # -- Begin function _Z34__device_stub__exclusiveScanKernelIiEvPT_PKS0_m
	.type	_Z34__device_stub__exclusiveScanKernelIiEvPT_PKS0_m,@function
_Z34__device_stub__exclusiveScanKernelIiEvPT_PKS0_m: # @_Z34__device_stub__exclusiveScanKernelIiEvPT_PKS0_m
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z19exclusiveScanKernelIiEvPT_PKS0_m, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z34__device_stub__exclusiveScanKernelIiEvPT_PKS0_m, .Lfunc_end1-_Z34__device_stub__exclusiveScanKernelIiEvPT_PKS0_m
	.cfi_endproc
                                        # -- End function
	.text
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z19exclusiveScanKernelIiEvPT_PKS0_m, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z19exclusiveScanKernelIiEvPT_PKS0_m,@object # @_Z19exclusiveScanKernelIiEvPT_PKS0_m
	.section	.rodata._Z19exclusiveScanKernelIiEvPT_PKS0_m,"aG",@progbits,_Z19exclusiveScanKernelIiEvPT_PKS0_m,comdat
	.weak	_Z19exclusiveScanKernelIiEvPT_PKS0_m
	.p2align	3, 0x0
_Z19exclusiveScanKernelIiEvPT_PKS0_m:
	.quad	_Z34__device_stub__exclusiveScanKernelIiEvPT_PKS0_m
	.size	_Z19exclusiveScanKernelIiEvPT_PKS0_m, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z19exclusiveScanKernelIiEvPT_PKS0_m"
	.size	.L__unnamed_1, 37

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z34__device_stub__exclusiveScanKernelIiEvPT_PKS0_m
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z19exclusiveScanKernelIiEvPT_PKS0_m
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.section	.text._Z19exclusiveScanKernelIiEvPT_PKS0_m,"axG",@progbits,_Z19exclusiveScanKernelIiEvPT_PKS0_m,comdat
	.protected	_Z19exclusiveScanKernelIiEvPT_PKS0_m ; -- Begin function _Z19exclusiveScanKernelIiEvPT_PKS0_m
	.globl	_Z19exclusiveScanKernelIiEvPT_PKS0_m
	.p2align	8
	.type	_Z19exclusiveScanKernelIiEvPT_PKS0_m,@function
_Z19exclusiveScanKernelIiEvPT_PKS0_m:   ; @_Z19exclusiveScanKernelIiEvPT_PKS0_m
; %bb.0:
	s_clause 0x1
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b64 s[2:3], s[0:1], 0x10
	v_mov_b32_e32 v32, 0
	v_cmp_ne_u32_e32 vcc_lo, 0, v0
	v_dual_mov_b32 v33, 0 :: v_dual_mov_b32 v2, 0
	v_mov_b32_e32 v4, 0
	s_and_saveexec_b32 s8, vcc_lo
	s_cbranch_execz .LBB0_2
; %bb.1:
	v_lshlrev_b32_e32 v1, 2, v0
	s_waitcnt lgkmcnt(0)
	global_load_b32 v4, v1, s[6:7] offset:-4
	v_mov_b32_e32 v1, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_mov_b32 v33, v1 :: v_dual_mov_b32 v32, v0
.LBB0_2:                                ; %._crit_edge99
	s_or_b32 exec_lo, exec_lo, s8
	v_lshl_add_u32 v1, v0, 2, 0
	s_delay_alu instid0(VALU_DEP_2)
	v_lshlrev_b32_e32 v3, 2, v32
	s_waitcnt vmcnt(0)
	ds_store_b32 v1, v4
	s_and_saveexec_b32 s8, vcc_lo
	s_cbranch_execz .LBB0_4
; %bb.3:
	s_waitcnt lgkmcnt(0)
	global_load_b32 v2, v3, s[6:7] offset:-4
.LBB0_4:
	s_or_b32 exec_lo, exec_lo, s8
	s_waitcnt lgkmcnt(0)
	v_cmp_lt_u64_e64 s6, s[2:3], 2
	v_lshl_add_u32 v4, s2, 2, v1
	s_mov_b32 s8, 0
	s_waitcnt vmcnt(0)
	ds_store_b32 v4, v2
	s_and_b32 vcc_lo, exec_lo, s6
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_vccnz .LBB0_11
; %bb.5:                                ; %.lr.ph.preheader
	s_mov_b32 s6, 1
.LBB0_6:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_mov_b32 s7, exec_lo
                                        ; implicit-def: $vgpr2
	v_cmpx_le_i32_e64 s6, v0
	s_xor_b32 s7, exec_lo, s7
	s_cbranch_execz .LBB0_8
; %bb.7:                                ;   in Loop: Header=BB0_6 Depth=1
	v_mad_u64_u32 v[4:5], null, s8, s2, v[32:33]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v2, s6, v4
	v_lshl_add_u32 v4, v4, 2, 0
	v_lshl_add_u32 v2, v2, 2, 0
	ds_load_b32 v4, v4
	ds_load_b32 v2, v2
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v2, v2, v4
.LBB0_8:                                ; %Flow435
                                        ;   in Loop: Header=BB0_6 Depth=1
	s_and_not1_saveexec_b32 s7, s7
	s_cbranch_execz .LBB0_10
; %bb.9:                                ;   in Loop: Header=BB0_6 Depth=1
	s_mul_i32 s9, s8, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	v_lshl_add_u32 v2, s9, 2, v1
	ds_load_b32 v2, v2
.LBB0_10:                               ;   in Loop: Header=BB0_6 Depth=1
	s_or_b32 exec_lo, exec_lo, s7
	s_lshl_b32 s6, s6, 1
	s_sub_i32 s8, 1, s8
	s_ashr_i32 s7, s6, 31
	s_mul_i32 s9, s8, s2
	v_cmp_ge_u64_e64 s7, s[6:7], s[2:3]
	v_lshl_add_u32 v4, s9, 2, v1
	s_waitcnt lgkmcnt(0)
	ds_store_b32 v4, v2
	s_and_b32 vcc_lo, exec_lo, s7
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_vccz .LBB0_6
.LBB0_11:                               ; %._crit_edge
	s_mul_i32 s2, s8, s2
	v_mbcnt_lo_u32_b32 v31, -1, 0
	v_lshl_add_u32 v0, s2, 2, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_mov_b32_e32 v7, v31
	ds_load_b32 v2, v0
	v_mov_b32_e32 v0, 0
	v_mov_b32_e32 v1, 0
	s_waitcnt lgkmcnt(0)
	global_store_b32 v3, v2, s[4:5]
	s_load_b64 s[2:3], s[0:1], 0x68
	;;#ASMSTART
	;;#ASMEND
	v_readfirstlane_b32 s0, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_eq_u32_e64 s0, s0, v7
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_17
; %bb.12:
	v_mov_b32_e32 v3, 0
	s_mov_b32 s4, exec_lo
	s_waitcnt lgkmcnt(0)
	global_load_b64 v[10:11], v3, s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[0:1], v3, s[2:3] offset:40
	global_load_b64 v[4:5], v3, s[2:3]
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v0, v0, v10
	v_and_b32_e32 v1, v1, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v6, v0, 24
	v_mul_lo_u32 v1, v1, 24
	v_mul_lo_u32 v0, v0, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v1, v6, v1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v0, vcc_lo, v4, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, v5, v1, vcc_lo
	global_load_b64 v[8:9], v[0:1], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[0:1], v3, v[8:11], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[0:1], v[10:11]
	s_cbranch_execz .LBB0_16
; %bb.13:                               ; %.preheader3.i.i.i.preheader
	s_mov_b32 s5, 0
.LBB0_14:                               ; %.preheader3.i.i.i
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[4:5], v3, s[2:3] offset:40
	global_load_b64 v[8:9], v3, s[2:3]
	v_dual_mov_b32 v11, v1 :: v_dual_mov_b32 v10, v0
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v4, v4, v10
	v_and_b32_e32 v6, v5, v11
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[0:1], null, v4, 24, v[8:9]
	v_mad_u64_u32 v[4:5], null, v6, 24, v[1:2]
	s_delay_alu instid0(VALU_DEP_1)
	v_mov_b32_e32 v1, v4
	global_load_b64 v[8:9], v[0:1], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[0:1], v3, v[8:11], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[10:11]
	s_or_b32 s5, vcc_lo, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s5
	s_cbranch_execnz .LBB0_14
; %bb.15:                               ; %Flow432
	s_or_b32 exec_lo, exec_lo, s5
.LBB0_16:                               ; %Flow434
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s4
.LBB0_17:                               ; %.loopexit4.i.i.i
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	v_mov_b32_e32 v8, 0
	v_readfirstlane_b32 s4, v0
	v_readfirstlane_b32 s5, v1
	s_mov_b32 s10, exec_lo
	s_waitcnt lgkmcnt(0)
	s_clause 0x1
	global_load_b64 v[9:10], v8, s[2:3] offset:40
	global_load_b128 v[3:6], v8, s[2:3]
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s6, v9
	v_readfirstlane_b32 s7, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[6:7], s[4:5], s[6:7]
	s_mul_i32 s1, s7, 24
	s_mul_hi_u32 s8, s6, 24
	s_mul_i32 s9, s6, 24
	s_and_saveexec_b32 s11, s0
	s_cbranch_execz .LBB0_19
; %bb.18:
	v_dual_mov_b32 v9, s10 :: v_dual_mov_b32 v10, v8
	s_add_i32 s10, s8, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v0, vcc_lo, v3, s9
	v_add_co_ci_u32_e32 v1, vcc_lo, s10, v4, vcc_lo
	v_dual_mov_b32 v11, 2 :: v_dual_mov_b32 v12, 1
	global_store_b128 v[0:1], v[9:12], off offset:8
.LBB0_19:
	s_or_b32 exec_lo, exec_lo, s11
	s_lshl_b64 s[6:7], s[6:7], 12
	v_lshlrev_b64 v[0:1], 6, v[7:8]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v5, vcc_lo, v5, s6
	v_add_co_ci_u32_e32 v6, vcc_lo, s7, v6, vcc_lo
	s_mov_b32 s12, 0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v5, v0
	s_mov_b32 s13, s12
	s_mov_b32 s14, s12
	s_mov_b32 s15, s12
	v_add_co_ci_u32_e32 v1, vcc_lo, v6, v1, vcc_lo
	v_dual_mov_b32 v7, 33 :: v_dual_mov_b32 v10, v8
	v_mov_b32_e32 v9, v8
	v_dual_mov_b32 v11, s12 :: v_dual_mov_b32 v14, s15
	v_dual_mov_b32 v12, s13 :: v_dual_mov_b32 v13, s14
	s_clause 0x3
	global_store_b128 v[0:1], v[7:10], off
	global_store_b128 v[0:1], v[11:14], off offset:16
	global_store_b128 v[0:1], v[11:14], off offset:32
	global_store_b128 v[0:1], v[11:14], off offset:48
	s_and_saveexec_b32 s6, s0
	s_cbranch_execz .LBB0_27
; %bb.20:
	v_mov_b32_e32 v11, 0
	s_mov_b32 s7, exec_lo
	s_clause 0x1
	global_load_b64 v[14:15], v11, s[2:3] offset:32 glc
	global_load_b64 v[5:6], v11, s[2:3] offset:40
	v_dual_mov_b32 v12, s4 :: v_dual_mov_b32 v13, s5
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v6, s5, v6
	v_and_b32_e32 v5, s4, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v6, v6, 24
	v_mul_hi_u32 v7, v5, 24
	v_mul_lo_u32 v5, v5, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v6, v7, v6
	v_add_co_u32 v9, vcc_lo, v3, v5
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v10, vcc_lo, v4, v6, vcc_lo
	global_store_b64 v[9:10], v[14:15], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[7:8], v11, v[12:15], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[7:8], v[14:15]
	s_cbranch_execz .LBB0_23
; %bb.21:                               ; %.preheader1.i.i.i.preheader
	s_mov_b32 s10, 0
.LBB0_22:                               ; %.preheader1.i.i.i
                                        ; =>This Inner Loop Header: Depth=1
	v_dual_mov_b32 v5, s4 :: v_dual_mov_b32 v6, s5
	s_sleep 1
	global_store_b64 v[9:10], v[7:8], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[5:6], v11, v[5:8], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[5:6], v[7:8]
	v_dual_mov_b32 v8, v6 :: v_dual_mov_b32 v7, v5
	s_or_b32 s10, vcc_lo, s10
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s10
	s_cbranch_execnz .LBB0_22
.LBB0_23:                               ; %Flow430
	s_or_b32 exec_lo, exec_lo, s7
	v_mov_b32_e32 v8, 0
	s_mov_b32 s10, exec_lo
	s_mov_b32 s7, exec_lo
	v_mbcnt_lo_u32_b32 v7, s10, 0
	global_load_b64 v[5:6], v8, s[2:3] offset:16
	v_cmpx_eq_u32_e32 0, v7
	s_cbranch_execz .LBB0_25
; %bb.24:
	s_bcnt1_i32_b32 s10, s10
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v7, s10
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[5:6], v[7:8], off offset:8
.LBB0_25:
	s_or_b32 exec_lo, exec_lo, s7
	s_waitcnt vmcnt(0)
	global_load_b64 v[7:8], v[5:6], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[7:8]
	s_cbranch_vccnz .LBB0_27
; %bb.26:
	global_load_b32 v5, v[5:6], off offset:24
	v_mov_b32_e32 v6, 0
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s7, v5
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[7:8], v[5:6], off
	s_and_b32 m0, s7, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_27:                               ; %Flow431
	s_or_b32 exec_lo, exec_lo, s6
	s_add_i32 s8, s8, s1
	v_add_co_u32 v3, vcc_lo, v3, s9
	v_add_co_ci_u32_e32 v4, vcc_lo, s8, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, v3, 20
	v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
.LBB0_28:                               ; =>This Inner Loop Header: Depth=1
	v_mov_b32_e32 v5, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_30
; %bb.29:                               ;   in Loop: Header=BB0_28 Depth=1
	global_load_b32 v5, v[3:4], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v5, 1, v5
.LBB0_30:                               ;   in Loop: Header=BB0_28 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v5
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB0_32
; %bb.31:                               ;   in Loop: Header=BB0_28 Depth=1
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB0_33
.LBB0_32:                               ;   in Loop: Header=BB0_28 Depth=1
	s_mov_b32 s1, -1
.LBB0_33:                               ; %Flow425
                                        ;   in Loop: Header=BB0_28 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB0_28
; %bb.34:
	global_load_b64 v[3:4], v[0:1], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_38
; %bb.35:
	v_mov_b32_e32 v9, 0
	s_clause 0x2
	global_load_b64 v[0:1], v9, s[2:3] offset:40
	global_load_b64 v[10:11], v9, s[2:3] offset:24 glc
	global_load_b64 v[7:8], v9, s[2:3]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v12, vcc_lo, v0, 1
	v_add_co_ci_u32_e32 v13, vcc_lo, 0, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v5, vcc_lo, v12, s4
	v_add_co_ci_u32_e32 v6, vcc_lo, s5, v13, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[5:6]
	v_dual_cndmask_b32 v6, v6, v13 :: v_dual_cndmask_b32 v5, v5, v12
	v_and_b32_e32 v1, v6, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v0, v5, v0
	v_mul_lo_u32 v1, v1, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v12, v0, 24
	v_mul_lo_u32 v0, v0, 24
	v_add_nc_u32_e32 v1, v12, v1
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v0, vcc_lo, v7, v0
	v_mov_b32_e32 v7, v10
	v_add_co_ci_u32_e32 v1, vcc_lo, v8, v1, vcc_lo
	v_mov_b32_e32 v8, v11
	global_store_b64 v[0:1], v[10:11], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[7:8], v9, v[5:8], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[7:8], v[10:11]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_38
; %bb.36:                               ; %.preheader.i.i.i.preheader
	s_mov_b32 s0, 0
.LBB0_37:                               ; %.preheader.i.i.i
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	global_store_b64 v[0:1], v[7:8], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[10:11], v9, v[5:8], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[10:11], v[7:8]
	v_dual_mov_b32 v7, v10 :: v_dual_mov_b32 v8, v11
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB0_37
.LBB0_38:                               ; %__ockl_printf_begin.exit
	s_or_b32 exec_lo, exec_lo, s1
	s_getpc_b64 s[4:5]
	s_add_u32 s4, s4, .str@rel32@lo+4
	s_addc_u32 s5, s5, .str@rel32@hi+12
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u64 s[4:5], 0
	s_cbranch_scc0 .LBB0_124
; %bb.39:
	s_waitcnt vmcnt(0)
	v_dual_mov_b32 v1, 0 :: v_dual_and_b32 v34, 2, v3
	v_dual_mov_b32 v6, v4 :: v_dual_and_b32 v5, -3, v3
	v_dual_mov_b32 v9, 2 :: v_dual_mov_b32 v10, 1
	s_mov_b64 s[6:7], 16
.LBB0_40:                               ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_43 Depth 2
                                        ;     Child Loop BB0_50 Depth 2
                                        ;     Child Loop BB0_58 Depth 2
                                        ;     Child Loop BB0_66 Depth 2
                                        ;     Child Loop BB0_74 Depth 2
                                        ;     Child Loop BB0_82 Depth 2
                                        ;     Child Loop BB0_90 Depth 2
                                        ;     Child Loop BB0_98 Depth 2
                                        ;     Child Loop BB0_106 Depth 2
                                        ;     Child Loop BB0_112 Depth 2
                                        ;     Child Loop BB0_121 Depth 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_u64_e64 s0, s[6:7], 56
                                        ; implicit-def: $vgpr13_vgpr14
                                        ; implicit-def: $sgpr15
	s_and_b32 s0, s0, exec_lo
	s_cselect_b32 s8, s6, 56
	s_cselect_b32 s9, s7, 0
	s_cmp_gt_u32 s8, 7
	s_mov_b32 s0, -1
	s_cbranch_scc1 .LBB0_45
; %bb.41:                               ;   in Loop: Header=BB0_40 Depth=1
	v_mov_b32_e32 v13, 0
	v_mov_b32_e32 v14, 0
	s_cmp_eq_u32 s8, 0
	s_cbranch_scc1 .LBB0_44
; %bb.42:                               ; %.preheader31.i.preheader
                                        ;   in Loop: Header=BB0_40 Depth=1
	s_lshl_b64 s[0:1], s[8:9], 3
	s_mov_b64 s[10:11], 0
	s_mov_b64 s[12:13], s[4:5]
.LBB0_43:                               ; %.preheader31.i
                                        ;   Parent Loop BB0_40 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	global_load_u8 v0, v1, s[12:13]
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v0, 0xffff, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_lshlrev_b64 v[7:8], s10, v[0:1]
	s_add_u32 s10, s10, 8
	s_addc_u32 s11, s11, 0
	s_add_u32 s12, s12, 1
	s_addc_u32 s13, s13, 0
	s_cmp_lg_u32 s0, s10
	v_or_b32_e32 v13, v7, v13
	v_or_b32_e32 v14, v8, v14
	s_cbranch_scc1 .LBB0_43
.LBB0_44:                               ; %Flow401
                                        ;   in Loop: Header=BB0_40 Depth=1
	s_mov_b32 s0, 0
	s_mov_b32 s15, 0
.LBB0_45:                               ; %Flow403
                                        ;   in Loop: Header=BB0_40 Depth=1
	s_and_not1_b32 vcc_lo, exec_lo, s0
	s_mov_b64 s[0:1], s[4:5]
	s_cbranch_vccnz .LBB0_47
; %bb.46:                               ;   in Loop: Header=BB0_40 Depth=1
	global_load_b64 v[13:14], v1, s[4:5]
	s_add_i32 s15, s8, -8
	s_add_u32 s0, s4, 8
	s_addc_u32 s1, s5, 0
.LBB0_47:                               ; %.loopexit32.i
                                        ;   in Loop: Header=BB0_40 Depth=1
	s_cmp_gt_u32 s15, 7
	s_cbranch_scc1 .LBB0_52
; %bb.48:                               ;   in Loop: Header=BB0_40 Depth=1
	v_mov_b32_e32 v15, 0
	v_mov_b32_e32 v16, 0
	s_cmp_eq_u32 s15, 0
	s_cbranch_scc1 .LBB0_51
; %bb.49:                               ; %.preheader29.i.preheader
                                        ;   in Loop: Header=BB0_40 Depth=1
	s_mov_b64 s[10:11], 0
	s_mov_b64 s[12:13], 0
.LBB0_50:                               ; %.preheader29.i
                                        ;   Parent Loop BB0_40 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s16, s0, s12
	s_addc_u32 s17, s1, s13
	s_add_u32 s12, s12, 1
	global_load_u8 v0, v1, s[16:17]
	s_addc_u32 s13, s13, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v0, 0xffff, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[7:8], s10, v[0:1]
	s_add_u32 s10, s10, 8
	s_addc_u32 s11, s11, 0
	s_cmp_lg_u32 s15, s12
	v_or_b32_e32 v15, v7, v15
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v16, v8, v16
	s_cbranch_scc1 .LBB0_50
.LBB0_51:                               ; %Flow396
                                        ;   in Loop: Header=BB0_40 Depth=1
	s_mov_b32 s10, 0
	s_mov_b32 s14, 0
	s_branch .LBB0_53
.LBB0_52:                               ;   in Loop: Header=BB0_40 Depth=1
	s_mov_b32 s10, -1
                                        ; implicit-def: $vgpr15_vgpr16
                                        ; implicit-def: $sgpr14
.LBB0_53:                               ; %Flow398
                                        ;   in Loop: Header=BB0_40 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s10
	s_cbranch_vccnz .LBB0_55
; %bb.54:                               ;   in Loop: Header=BB0_40 Depth=1
	global_load_b64 v[15:16], v1, s[0:1]
	s_add_i32 s14, s15, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB0_55:                               ; %.loopexit30.i
                                        ;   in Loop: Header=BB0_40 Depth=1
	s_cmp_gt_u32 s14, 7
	s_cbranch_scc1 .LBB0_60
; %bb.56:                               ;   in Loop: Header=BB0_40 Depth=1
	v_mov_b32_e32 v17, 0
	v_mov_b32_e32 v18, 0
	s_cmp_eq_u32 s14, 0
	s_cbranch_scc1 .LBB0_59
; %bb.57:                               ; %.preheader27.i.preheader
                                        ;   in Loop: Header=BB0_40 Depth=1
	s_mov_b64 s[10:11], 0
	s_mov_b64 s[12:13], 0
.LBB0_58:                               ; %.preheader27.i
                                        ;   Parent Loop BB0_40 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s16, s0, s12
	s_addc_u32 s17, s1, s13
	s_add_u32 s12, s12, 1
	global_load_u8 v0, v1, s[16:17]
	s_addc_u32 s13, s13, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v0, 0xffff, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[7:8], s10, v[0:1]
	s_add_u32 s10, s10, 8
	s_addc_u32 s11, s11, 0
	s_cmp_lg_u32 s14, s12
	v_or_b32_e32 v17, v7, v17
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v18, v8, v18
	s_cbranch_scc1 .LBB0_58
.LBB0_59:                               ; %Flow391
                                        ;   in Loop: Header=BB0_40 Depth=1
	s_mov_b32 s10, 0
	s_mov_b32 s15, 0
	s_branch .LBB0_61
.LBB0_60:                               ;   in Loop: Header=BB0_40 Depth=1
	s_mov_b32 s10, -1
                                        ; implicit-def: $sgpr15
.LBB0_61:                               ; %Flow393
                                        ;   in Loop: Header=BB0_40 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s10
	s_cbranch_vccnz .LBB0_63
; %bb.62:                               ;   in Loop: Header=BB0_40 Depth=1
	global_load_b64 v[17:18], v1, s[0:1]
	s_add_i32 s15, s14, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB0_63:                               ; %.loopexit28.i
                                        ;   in Loop: Header=BB0_40 Depth=1
	s_cmp_gt_u32 s15, 7
	s_cbranch_scc1 .LBB0_68
; %bb.64:                               ;   in Loop: Header=BB0_40 Depth=1
	v_mov_b32_e32 v19, 0
	v_mov_b32_e32 v20, 0
	s_cmp_eq_u32 s15, 0
	s_cbranch_scc1 .LBB0_67
; %bb.65:                               ; %.preheader25.i.preheader
                                        ;   in Loop: Header=BB0_40 Depth=1
	s_mov_b64 s[10:11], 0
	s_mov_b64 s[12:13], 0
.LBB0_66:                               ; %.preheader25.i
                                        ;   Parent Loop BB0_40 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s16, s0, s12
	s_addc_u32 s17, s1, s13
	s_add_u32 s12, s12, 1
	global_load_u8 v0, v1, s[16:17]
	s_addc_u32 s13, s13, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v0, 0xffff, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[7:8], s10, v[0:1]
	s_add_u32 s10, s10, 8
	s_addc_u32 s11, s11, 0
	s_cmp_lg_u32 s15, s12
	v_or_b32_e32 v19, v7, v19
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v20, v8, v20
	s_cbranch_scc1 .LBB0_66
.LBB0_67:                               ; %Flow386
                                        ;   in Loop: Header=BB0_40 Depth=1
	s_mov_b32 s10, 0
	s_mov_b32 s14, 0
	s_branch .LBB0_69
.LBB0_68:                               ;   in Loop: Header=BB0_40 Depth=1
	s_mov_b32 s10, -1
                                        ; implicit-def: $vgpr19_vgpr20
                                        ; implicit-def: $sgpr14
.LBB0_69:                               ; %Flow388
                                        ;   in Loop: Header=BB0_40 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s10
	s_cbranch_vccnz .LBB0_71
; %bb.70:                               ;   in Loop: Header=BB0_40 Depth=1
	global_load_b64 v[19:20], v1, s[0:1]
	s_add_i32 s14, s15, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB0_71:                               ; %.loopexit26.i
                                        ;   in Loop: Header=BB0_40 Depth=1
	s_cmp_gt_u32 s14, 7
	s_cbranch_scc1 .LBB0_76
; %bb.72:                               ;   in Loop: Header=BB0_40 Depth=1
	v_mov_b32_e32 v21, 0
	v_mov_b32_e32 v22, 0
	s_cmp_eq_u32 s14, 0
	s_cbranch_scc1 .LBB0_75
; %bb.73:                               ; %.preheader23.i.preheader
                                        ;   in Loop: Header=BB0_40 Depth=1
	s_mov_b64 s[10:11], 0
	s_mov_b64 s[12:13], 0
.LBB0_74:                               ; %.preheader23.i
                                        ;   Parent Loop BB0_40 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s16, s0, s12
	s_addc_u32 s17, s1, s13
	s_add_u32 s12, s12, 1
	global_load_u8 v0, v1, s[16:17]
	s_addc_u32 s13, s13, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v0, 0xffff, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[7:8], s10, v[0:1]
	s_add_u32 s10, s10, 8
	s_addc_u32 s11, s11, 0
	s_cmp_lg_u32 s14, s12
	v_or_b32_e32 v21, v7, v21
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v22, v8, v22
	s_cbranch_scc1 .LBB0_74
.LBB0_75:                               ; %Flow381
                                        ;   in Loop: Header=BB0_40 Depth=1
	s_mov_b32 s10, 0
	s_mov_b32 s15, 0
	s_branch .LBB0_77
.LBB0_76:                               ;   in Loop: Header=BB0_40 Depth=1
	s_mov_b32 s10, -1
                                        ; implicit-def: $sgpr15
.LBB0_77:                               ; %Flow383
                                        ;   in Loop: Header=BB0_40 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s10
	s_cbranch_vccnz .LBB0_79
; %bb.78:                               ;   in Loop: Header=BB0_40 Depth=1
	global_load_b64 v[21:22], v1, s[0:1]
	s_add_i32 s15, s14, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB0_79:                               ; %.loopexit24.i
                                        ;   in Loop: Header=BB0_40 Depth=1
	s_cmp_gt_u32 s15, 7
	s_cbranch_scc1 .LBB0_84
; %bb.80:                               ;   in Loop: Header=BB0_40 Depth=1
	v_mov_b32_e32 v23, 0
	v_mov_b32_e32 v24, 0
	s_cmp_eq_u32 s15, 0
	s_cbranch_scc1 .LBB0_83
; %bb.81:                               ; %.preheader21.i.preheader
                                        ;   in Loop: Header=BB0_40 Depth=1
	s_mov_b64 s[10:11], 0
	s_mov_b64 s[12:13], 0
.LBB0_82:                               ; %.preheader21.i
                                        ;   Parent Loop BB0_40 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s16, s0, s12
	s_addc_u32 s17, s1, s13
	s_add_u32 s12, s12, 1
	global_load_u8 v0, v1, s[16:17]
	s_addc_u32 s13, s13, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v0, 0xffff, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[7:8], s10, v[0:1]
	s_add_u32 s10, s10, 8
	s_addc_u32 s11, s11, 0
	s_cmp_lg_u32 s15, s12
	v_or_b32_e32 v23, v7, v23
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v24, v8, v24
	s_cbranch_scc1 .LBB0_82
.LBB0_83:                               ; %Flow376
                                        ;   in Loop: Header=BB0_40 Depth=1
	s_mov_b32 s10, 0
	s_mov_b32 s14, 0
	s_branch .LBB0_85
.LBB0_84:                               ;   in Loop: Header=BB0_40 Depth=1
	s_mov_b32 s10, -1
                                        ; implicit-def: $vgpr23_vgpr24
                                        ; implicit-def: $sgpr14
.LBB0_85:                               ; %Flow378
                                        ;   in Loop: Header=BB0_40 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s10
	s_cbranch_vccnz .LBB0_87
; %bb.86:                               ;   in Loop: Header=BB0_40 Depth=1
	global_load_b64 v[23:24], v1, s[0:1]
	s_add_i32 s14, s15, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB0_87:                               ; %.loopexit22.i
                                        ;   in Loop: Header=BB0_40 Depth=1
	s_cmp_gt_u32 s14, 7
	s_cbranch_scc1 .LBB0_92
; %bb.88:                               ;   in Loop: Header=BB0_40 Depth=1
	v_mov_b32_e32 v25, 0
	v_mov_b32_e32 v26, 0
	s_cmp_eq_u32 s14, 0
	s_cbranch_scc1 .LBB0_91
; %bb.89:                               ; %.preheader.i.preheader
                                        ;   in Loop: Header=BB0_40 Depth=1
	s_mov_b64 s[10:11], 0
	s_mov_b64 s[12:13], s[0:1]
.LBB0_90:                               ; %.preheader.i
                                        ;   Parent Loop BB0_40 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	global_load_u8 v0, v1, s[12:13]
	s_add_i32 s14, s14, -1
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v0, 0xffff, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_lshlrev_b64 v[7:8], s10, v[0:1]
	s_add_u32 s10, s10, 8
	s_addc_u32 s11, s11, 0
	s_add_u32 s12, s12, 1
	s_addc_u32 s13, s13, 0
	s_cmp_lg_u32 s14, 0
	v_or_b32_e32 v25, v7, v25
	v_or_b32_e32 v26, v8, v26
	s_cbranch_scc1 .LBB0_90
.LBB0_91:                               ; %Flow371
                                        ;   in Loop: Header=BB0_40 Depth=1
	s_mov_b32 s10, 0
	s_branch .LBB0_93
.LBB0_92:                               ;   in Loop: Header=BB0_40 Depth=1
	s_mov_b32 s10, -1
.LBB0_93:                               ; %Flow373
                                        ;   in Loop: Header=BB0_40 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s10
	s_cbranch_vccnz .LBB0_95
; %bb.94:                               ;   in Loop: Header=BB0_40 Depth=1
	global_load_b64 v[25:26], v1, s[0:1]
.LBB0_95:                               ; %.loopexit.i
                                        ;   in Loop: Header=BB0_40 Depth=1
	s_waitcnt vmcnt(0)
	v_dual_mov_b32 v0, v31 :: v_dual_mov_b32 v7, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s0, v0
	v_mov_b32_e32 v8, 0
	v_cmp_eq_u32_e64 s0, s0, v0
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_101
; %bb.96:                               ;   in Loop: Header=BB0_40 Depth=1
	global_load_b64 v[29:30], v1, s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[7:8], v1, s[2:3] offset:40
	global_load_b64 v[11:12], v1, s[2:3]
	s_mov_b32 s10, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v8, v8, v30
	v_and_b32_e32 v7, v7, v29
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v8, v8, 24
	v_mul_hi_u32 v27, v7, 24
	v_mul_lo_u32 v7, v7, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v8, v27, v8
	s_waitcnt vmcnt(0)
	v_add_co_u32 v7, vcc_lo, v11, v7
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v8, vcc_lo, v12, v8, vcc_lo
	global_load_b64 v[27:28], v[7:8], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[7:8], v1, v[27:30], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[7:8], v[29:30]
	s_cbranch_execz .LBB0_100
; %bb.97:                               ; %.preheader3.i.i19.i.preheader
                                        ;   in Loop: Header=BB0_40 Depth=1
	s_mov_b32 s11, 0
.LBB0_98:                               ; %.preheader3.i.i19.i
                                        ;   Parent Loop BB0_40 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[11:12], v1, s[2:3] offset:40
	global_load_b64 v[27:28], v1, s[2:3]
	v_dual_mov_b32 v30, v8 :: v_dual_mov_b32 v29, v7
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v11, v11, v29
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[7:8], null, v11, 24, v[27:28]
	v_and_b32_e32 v27, v12, v30
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[11:12], null, v27, 24, v[8:9]
	v_mov_b32_e32 v8, v11
	global_load_b64 v[27:28], v[7:8], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[7:8], v1, v[27:30], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[29:30]
	s_or_b32 s11, vcc_lo, s11
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s11
	s_cbranch_execnz .LBB0_98
; %bb.99:                               ; %Flow366
                                        ;   in Loop: Header=BB0_40 Depth=1
	s_or_b32 exec_lo, exec_lo, s11
.LBB0_100:                              ; %Flow368
                                        ;   in Loop: Header=BB0_40 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s10
.LBB0_101:                              ; %.loopexit4.i.i14.i
                                        ;   in Loop: Header=BB0_40 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_clause 0x1
	global_load_b64 v[11:12], v1, s[2:3] offset:40
	global_load_b128 v[27:30], v1, s[2:3]
	v_readfirstlane_b32 s10, v7
	v_readfirstlane_b32 s11, v8
	s_mov_b32 s16, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s12, v11
	v_readfirstlane_b32 s13, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[12:13], s[10:11], s[12:13]
	s_mul_i32 s1, s13, 24
	s_mul_hi_u32 s14, s12, 24
	s_mul_i32 s15, s12, 24
	s_and_saveexec_b32 s17, s0
	s_cbranch_execz .LBB0_103
; %bb.102:                              ;   in Loop: Header=BB0_40 Depth=1
	v_dual_mov_b32 v7, s16 :: v_dual_mov_b32 v8, v1
	s_add_i32 s16, s14, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v11, vcc_lo, v27, s15
	v_add_co_ci_u32_e32 v12, vcc_lo, s16, v28, vcc_lo
	global_store_b128 v[11:12], v[7:10], off offset:8
.LBB0_103:                              ;   in Loop: Header=BB0_40 Depth=1
	s_or_b32 exec_lo, exec_lo, s17
	v_cmp_gt_u64_e64 vcc_lo, s[6:7], 56
	v_or_b32_e32 v7, 0, v6
	v_or_b32_e32 v8, v5, v34
	s_lshl_b64 s[12:13], s[12:13], 12
	s_lshl_b32 s16, s8, 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_add_i32 s16, s16, 28
	v_dual_cndmask_b32 v12, v7, v6 :: v_dual_cndmask_b32 v7, v8, v5
	v_lshlrev_b64 v[5:6], 6, v[0:1]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v0, vcc_lo, v29, s12
	v_add_co_ci_u32_e32 v8, vcc_lo, s13, v30, vcc_lo
	s_and_b32 s16, s16, 0x1e0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v29, vcc_lo, v0, v5
	v_and_or_b32 v11, 0xffffff1f, v7, s16
	v_add_co_ci_u32_e32 v30, vcc_lo, v8, v6, vcc_lo
	s_clause 0x3
	global_store_b128 v[29:30], v[11:14], off
	global_store_b128 v[29:30], v[15:18], off offset:16
	global_store_b128 v[29:30], v[19:22], off offset:32
	global_store_b128 v[29:30], v[23:26], off offset:48
	s_and_saveexec_b32 s12, s0
	s_cbranch_execz .LBB0_111
; %bb.104:                              ;   in Loop: Header=BB0_40 Depth=1
	s_clause 0x1
	global_load_b64 v[15:16], v1, s[2:3] offset:32 glc
	global_load_b64 v[5:6], v1, s[2:3] offset:40
	v_dual_mov_b32 v13, s10 :: v_dual_mov_b32 v14, s11
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s16, v5
	v_readfirstlane_b32 s17, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[16:17], s[16:17], s[10:11]
	s_mul_i32 s13, s17, 24
	s_mul_hi_u32 s17, s16, 24
	s_mul_i32 s16, s16, 24
	s_add_i32 s17, s17, s13
	v_add_co_u32 v11, vcc_lo, v27, s16
	v_add_co_ci_u32_e32 v12, vcc_lo, s17, v28, vcc_lo
	s_mov_b32 s13, exec_lo
	global_store_b64 v[11:12], v[15:16], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[7:8], v1, v[13:16], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[7:8], v[15:16]
	s_cbranch_execz .LBB0_107
; %bb.105:                              ; %.preheader1.i.i17.i.preheader
                                        ;   in Loop: Header=BB0_40 Depth=1
	s_mov_b32 s16, 0
.LBB0_106:                              ; %.preheader1.i.i17.i
                                        ;   Parent Loop BB0_40 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_dual_mov_b32 v5, s10 :: v_dual_mov_b32 v6, s11
	s_sleep 1
	global_store_b64 v[11:12], v[7:8], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[5:6], v1, v[5:8], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[5:6], v[7:8]
	v_dual_mov_b32 v8, v6 :: v_dual_mov_b32 v7, v5
	s_or_b32 s16, vcc_lo, s16
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s16
	s_cbranch_execnz .LBB0_106
.LBB0_107:                              ; %Flow364
                                        ;   in Loop: Header=BB0_40 Depth=1
	s_or_b32 exec_lo, exec_lo, s13
	global_load_b64 v[5:6], v1, s[2:3] offset:16
	s_mov_b32 s16, exec_lo
	s_mov_b32 s13, exec_lo
	v_mbcnt_lo_u32_b32 v0, s16, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB0_109
; %bb.108:                              ;   in Loop: Header=BB0_40 Depth=1
	s_bcnt1_i32_b32 s16, s16
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v0, s16
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[5:6], v[0:1], off offset:8
.LBB0_109:                              ;   in Loop: Header=BB0_40 Depth=1
	s_or_b32 exec_lo, exec_lo, s13
	s_waitcnt vmcnt(0)
	global_load_b64 v[7:8], v[5:6], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[7:8]
	s_cbranch_vccnz .LBB0_111
; %bb.110:                              ;   in Loop: Header=BB0_40 Depth=1
	global_load_b32 v0, v[5:6], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s13, v0
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[7:8], v[0:1], off
	s_and_b32 m0, s13, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_111:                              ; %Flow365
                                        ;   in Loop: Header=BB0_40 Depth=1
	s_or_b32 exec_lo, exec_lo, s12
	s_add_i32 s14, s14, s1
	v_add_co_u32 v0, vcc_lo, v27, s15
	v_add_co_ci_u32_e32 v6, vcc_lo, s14, v28, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v5, vcc_lo, v0, 20
	v_add_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
.LBB0_112:                              ;   Parent Loop BB0_40 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_mov_b32_e32 v0, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_114
; %bb.113:                              ;   in Loop: Header=BB0_112 Depth=2
	global_load_b32 v0, v[5:6], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v0, 1, v0
.LBB0_114:                              ;   in Loop: Header=BB0_112 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v0
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB0_116
; %bb.115:                              ;   in Loop: Header=BB0_112 Depth=2
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB0_117
.LBB0_116:                              ;   in Loop: Header=BB0_112 Depth=2
	s_mov_b32 s1, -1
.LBB0_117:                              ; %Flow359
                                        ;   in Loop: Header=BB0_112 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB0_112
; %bb.118:                              ;   in Loop: Header=BB0_40 Depth=1
	global_load_b128 v[5:8], v[29:30], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_122
; %bb.119:                              ;   in Loop: Header=BB0_40 Depth=1
	s_clause 0x2
	global_load_b64 v[7:8], v1, s[2:3] offset:40
	global_load_b64 v[15:16], v1, s[2:3] offset:24 glc
	global_load_b64 v[13:14], v1, s[2:3]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v0, vcc_lo, v7, 1
	v_add_co_ci_u32_e32 v17, vcc_lo, 0, v8, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v11, vcc_lo, v0, s10
	v_add_co_ci_u32_e32 v12, vcc_lo, s11, v17, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[11:12]
	v_dual_cndmask_b32 v12, v12, v17 :: v_dual_cndmask_b32 v11, v11, v0
	v_and_b32_e32 v0, v12, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v7, v11, v7
	v_mul_hi_u32 v8, v7, 24
	v_mul_lo_u32 v7, v7, 24
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_u32 v7, vcc_lo, v13, v7
	v_mov_b32_e32 v13, v15
	v_mul_lo_u32 v0, v0, 24
	v_add_nc_u32_e32 v0, v8, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e32 v8, vcc_lo, v14, v0, vcc_lo
	v_mov_b32_e32 v14, v16
	global_store_b64 v[7:8], v[15:16], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[13:14], v1, v[11:14], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[13:14], v[15:16]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_122
; %bb.120:                              ; %.preheader.i.i16.i.preheader
                                        ;   in Loop: Header=BB0_40 Depth=1
	s_mov_b32 s0, 0
.LBB0_121:                              ; %.preheader.i.i16.i
                                        ;   Parent Loop BB0_40 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	global_store_b64 v[7:8], v[13:14], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[15:16], v1, v[11:14], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[15:16], v[13:14]
	v_dual_mov_b32 v13, v15 :: v_dual_mov_b32 v14, v16
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB0_121
.LBB0_122:                              ; %__ockl_hostcall_preview.exit20.i
                                        ;   in Loop: Header=BB0_40 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_sub_u32 s6, s6, s8
	s_subb_u32 s7, s7, s9
	s_add_u32 s4, s4, s8
	s_addc_u32 s5, s5, s9
	s_cmp_lg_u64 s[6:7], 0
	s_cbranch_scc1 .LBB0_40
; %bb.123:                              ; %Flow404
	s_mov_b32 s0, 0
	s_branch .LBB0_125
.LBB0_124:
	s_mov_b32 s0, -1
                                        ; implicit-def: $vgpr5_vgpr6
.LBB0_125:                              ; %Flow419
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccz .LBB0_154
; %bb.126:
	s_waitcnt vmcnt(0)
	v_dual_mov_b32 v5, v31 :: v_dual_mov_b32 v0, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s0, v5
	v_mov_b32_e32 v1, 0
	v_cmp_eq_u32_e64 s0, s0, v5
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_132
; %bb.127:
	v_mov_b32_e32 v6, 0
	s_mov_b32 s4, exec_lo
	global_load_b64 v[9:10], v6, s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[0:1], v6, s[2:3] offset:40
	global_load_b64 v[7:8], v6, s[2:3]
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v1, v1, v10
	v_and_b32_e32 v0, v0, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v1, v1, 24
	v_mul_hi_u32 v11, v0, 24
	v_mul_lo_u32 v0, v0, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v1, v11, v1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v0, vcc_lo, v7, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, v8, v1, vcc_lo
	global_load_b64 v[7:8], v[0:1], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[0:1], v6, v[7:10], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[0:1], v[9:10]
	s_cbranch_execz .LBB0_131
; %bb.128:                              ; %.preheader3.i.i.i54.preheader
	s_mov_b32 s5, 0
.LBB0_129:                              ; %.preheader3.i.i.i54
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[7:8], v6, s[2:3] offset:40
	global_load_b64 v[11:12], v6, s[2:3]
	v_dual_mov_b32 v10, v1 :: v_dual_mov_b32 v9, v0
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v7, v7, v9
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[0:1], null, v7, 24, v[11:12]
	v_and_b32_e32 v11, v8, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[7:8], null, v11, 24, v[1:2]
	v_mov_b32_e32 v1, v7
	global_load_b64 v[7:8], v[0:1], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[0:1], v6, v[7:10], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[9:10]
	s_or_b32 s5, vcc_lo, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s5
	s_cbranch_execnz .LBB0_129
; %bb.130:                              ; %Flow416
	s_or_b32 exec_lo, exec_lo, s5
.LBB0_131:                              ; %Flow418
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s4
.LBB0_132:                              ; %.loopexit4.i.i.i49
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	v_mov_b32_e32 v6, 0
	v_readfirstlane_b32 s4, v0
	v_readfirstlane_b32 s5, v1
	s_mov_b32 s10, exec_lo
	s_clause 0x1
	global_load_b64 v[11:12], v6, s[2:3] offset:40
	global_load_b128 v[7:10], v6, s[2:3]
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s6, v11
	v_readfirstlane_b32 s7, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[6:7], s[4:5], s[6:7]
	s_mul_i32 s1, s7, 24
	s_mul_hi_u32 s8, s6, 24
	s_mul_i32 s9, s6, 24
	s_and_saveexec_b32 s11, s0
	s_cbranch_execz .LBB0_134
; %bb.133:
	v_dual_mov_b32 v11, s10 :: v_dual_mov_b32 v12, v6
	s_add_i32 s10, s8, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v0, vcc_lo, v7, s9
	v_add_co_ci_u32_e32 v1, vcc_lo, s10, v8, vcc_lo
	v_dual_mov_b32 v13, 2 :: v_dual_mov_b32 v14, 1
	global_store_b128 v[0:1], v[11:14], off offset:8
.LBB0_134:
	s_or_b32 exec_lo, exec_lo, s11
	s_lshl_b64 s[6:7], s[6:7], 12
	v_lshlrev_b64 v[0:1], 6, v[5:6]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v5, vcc_lo, v9, s6
	v_add_co_ci_u32_e32 v9, vcc_lo, s7, v10, vcc_lo
	s_mov_b32 s12, 0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v5, v0
	s_mov_b32 s13, s12
	s_mov_b32 s14, s12
	s_mov_b32 s15, s12
	v_and_or_b32 v3, 0xffffff1f, v3, 32
	v_add_co_ci_u32_e32 v1, vcc_lo, v9, v1, vcc_lo
	v_mov_b32_e32 v5, v6
	v_dual_mov_b32 v9, s12 :: v_dual_mov_b32 v12, s15
	v_dual_mov_b32 v10, s13 :: v_dual_mov_b32 v11, s14
	s_clause 0x3
	global_store_b128 v[0:1], v[3:6], off
	global_store_b128 v[0:1], v[9:12], off offset:16
	global_store_b128 v[0:1], v[9:12], off offset:32
	global_store_b128 v[0:1], v[9:12], off offset:48
	s_and_saveexec_b32 s6, s0
	s_cbranch_execz .LBB0_142
; %bb.135:
	v_dual_mov_b32 v11, 0 :: v_dual_mov_b32 v12, s4
	v_mov_b32_e32 v13, s5
	s_clause 0x1
	global_load_b64 v[14:15], v11, s[2:3] offset:32 glc
	global_load_b64 v[3:4], v11, s[2:3] offset:40
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s10, v3
	v_readfirstlane_b32 s11, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[10:11], s[10:11], s[4:5]
	s_mul_i32 s7, s11, 24
	s_mul_hi_u32 s11, s10, 24
	s_mul_i32 s10, s10, 24
	s_add_i32 s11, s11, s7
	v_add_co_u32 v9, vcc_lo, v7, s10
	v_add_co_ci_u32_e32 v10, vcc_lo, s11, v8, vcc_lo
	s_mov_b32 s7, exec_lo
	global_store_b64 v[9:10], v[14:15], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[5:6], v11, v[12:15], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[5:6], v[14:15]
	s_cbranch_execz .LBB0_138
; %bb.136:                              ; %.preheader1.i.i.i52.preheader
	s_mov_b32 s10, 0
.LBB0_137:                              ; %.preheader1.i.i.i52
                                        ; =>This Inner Loop Header: Depth=1
	v_dual_mov_b32 v3, s4 :: v_dual_mov_b32 v4, s5
	s_sleep 1
	global_store_b64 v[9:10], v[5:6], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[3:4], v11, v[3:6], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[3:4], v[5:6]
	v_dual_mov_b32 v6, v4 :: v_dual_mov_b32 v5, v3
	s_or_b32 s10, vcc_lo, s10
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s10
	s_cbranch_execnz .LBB0_137
.LBB0_138:                              ; %Flow414
	s_or_b32 exec_lo, exec_lo, s7
	v_mov_b32_e32 v6, 0
	s_mov_b32 s10, exec_lo
	s_mov_b32 s7, exec_lo
	v_mbcnt_lo_u32_b32 v5, s10, 0
	global_load_b64 v[3:4], v6, s[2:3] offset:16
	v_cmpx_eq_u32_e32 0, v5
	s_cbranch_execz .LBB0_140
; %bb.139:
	s_bcnt1_i32_b32 s10, s10
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v5, s10
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[3:4], v[5:6], off offset:8
.LBB0_140:
	s_or_b32 exec_lo, exec_lo, s7
	s_waitcnt vmcnt(0)
	global_load_b64 v[5:6], v[3:4], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[5:6]
	s_cbranch_vccnz .LBB0_142
; %bb.141:
	global_load_b32 v3, v[3:4], off offset:24
	v_mov_b32_e32 v4, 0
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s7, v3
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[5:6], v[3:4], off
	s_and_b32 m0, s7, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_142:                              ; %Flow415
	s_or_b32 exec_lo, exec_lo, s6
	s_add_i32 s8, s8, s1
	v_add_co_u32 v3, vcc_lo, v7, s9
	v_add_co_ci_u32_e32 v4, vcc_lo, s8, v8, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, v3, 20
	v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
.LBB0_143:                              ; =>This Inner Loop Header: Depth=1
	v_mov_b32_e32 v5, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_145
; %bb.144:                              ;   in Loop: Header=BB0_143 Depth=1
	global_load_b32 v5, v[3:4], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v5, 1, v5
.LBB0_145:                              ;   in Loop: Header=BB0_143 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v5
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB0_147
; %bb.146:                              ;   in Loop: Header=BB0_143 Depth=1
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB0_148
.LBB0_147:                              ;   in Loop: Header=BB0_143 Depth=1
	s_mov_b32 s1, -1
.LBB0_148:                              ; %Flow409
                                        ;   in Loop: Header=BB0_143 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB0_143
; %bb.149:
	global_load_b128 v[5:8], v[0:1], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_153
; %bb.150:
	v_mov_b32_e32 v3, 0
	s_clause 0x2
	global_load_b64 v[0:1], v3, s[2:3] offset:40
	global_load_b64 v[11:12], v3, s[2:3] offset:24 glc
	global_load_b64 v[9:10], v3, s[2:3]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v4, vcc_lo, v0, 1
	v_add_co_ci_u32_e32 v13, vcc_lo, 0, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v7, vcc_lo, v4, s4
	v_add_co_ci_u32_e32 v8, vcc_lo, s5, v13, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[7:8]
	v_dual_cndmask_b32 v8, v8, v13 :: v_dual_cndmask_b32 v7, v7, v4
	v_and_b32_e32 v1, v8, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v0, v7, v0
	v_mul_lo_u32 v1, v1, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v4, v0, 24
	v_mul_lo_u32 v0, v0, 24
	v_add_nc_u32_e32 v1, v4, v1
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v0, vcc_lo, v9, v0
	v_mov_b32_e32 v9, v11
	v_add_co_ci_u32_e32 v1, vcc_lo, v10, v1, vcc_lo
	v_mov_b32_e32 v10, v12
	global_store_b64 v[0:1], v[11:12], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[9:10], v3, v[7:10], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[9:10], v[11:12]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_153
; %bb.151:                              ; %.preheader.i.i.i51.preheader
	s_mov_b32 s0, 0
.LBB0_152:                              ; %.preheader.i.i.i51
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	global_store_b64 v[0:1], v[9:10], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[11:12], v3, v[7:10], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[11:12], v[9:10]
	v_dual_mov_b32 v9, v11 :: v_dual_mov_b32 v10, v12
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB0_152
.LBB0_153:                              ; %__ockl_hostcall_preview.exit.i
	s_or_b32 exec_lo, exec_lo, s1
.LBB0_154:                              ; %__ockl_printf_append_string_n.exit
	s_waitcnt vmcnt(0)
	v_dual_mov_b32 v0, v31 :: v_dual_mov_b32 v3, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s0, v0
	v_mov_b32_e32 v4, 0
	v_cmp_eq_u32_e64 s0, s0, v0
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_160
; %bb.155:
	v_mov_b32_e32 v1, 0
	s_mov_b32 s4, exec_lo
	global_load_b64 v[9:10], v1, s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[3:4], v1, s[2:3] offset:40
	global_load_b64 v[7:8], v1, s[2:3]
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v4, v4, v10
	v_and_b32_e32 v3, v3, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v4, v4, 24
	v_mul_hi_u32 v11, v3, 24
	v_mul_lo_u32 v3, v3, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v4, v11, v4
	s_waitcnt vmcnt(0)
	v_add_co_u32 v3, vcc_lo, v7, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, v8, v4, vcc_lo
	global_load_b64 v[7:8], v[3:4], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[3:4], v1, v[7:10], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[3:4], v[9:10]
	s_cbranch_execz .LBB0_159
; %bb.156:                              ; %.preheader3.i.i.i61.preheader
	s_mov_b32 s5, 0
.LBB0_157:                              ; %.preheader3.i.i.i61
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[7:8], v1, s[2:3] offset:40
	global_load_b64 v[11:12], v1, s[2:3]
	v_dual_mov_b32 v10, v4 :: v_dual_mov_b32 v9, v3
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v7, v7, v9
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[3:4], null, v7, 24, v[11:12]
	v_and_b32_e32 v11, v8, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[7:8], null, v11, 24, v[4:5]
	v_mov_b32_e32 v4, v7
	global_load_b64 v[7:8], v[3:4], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[3:4], v1, v[7:10], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[3:4], v[9:10]
	s_or_b32 s5, vcc_lo, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s5
	s_cbranch_execnz .LBB0_157
; %bb.158:                              ; %Flow352
	s_or_b32 exec_lo, exec_lo, s5
.LBB0_159:                              ; %Flow354
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s4
.LBB0_160:                              ; %.loopexit4.i.i.i55
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	v_mov_b32_e32 v1, 0
	v_readfirstlane_b32 s4, v3
	v_readfirstlane_b32 s5, v4
	s_mov_b32 s10, exec_lo
	s_clause 0x1
	global_load_b64 v[7:8], v1, s[2:3] offset:40
	global_load_b128 v[9:12], v1, s[2:3]
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s6, v7
	v_readfirstlane_b32 s7, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[6:7], s[4:5], s[6:7]
	s_mul_i32 s1, s7, 24
	s_mul_hi_u32 s8, s6, 24
	s_mul_i32 s9, s6, 24
	s_and_saveexec_b32 s11, s0
	s_cbranch_execz .LBB0_162
; %bb.161:
	v_dual_mov_b32 v13, s10 :: v_dual_mov_b32 v14, v1
	s_add_i32 s10, s8, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v3, vcc_lo, v9, s9
	v_add_co_ci_u32_e32 v4, vcc_lo, s10, v10, vcc_lo
	v_dual_mov_b32 v15, 2 :: v_dual_mov_b32 v16, 1
	global_store_b128 v[3:4], v[13:16], off offset:8
.LBB0_162:
	s_or_b32 exec_lo, exec_lo, s11
	s_lshl_b64 s[6:7], s[6:7], 12
	v_lshlrev_b64 v[0:1], 6, v[0:1]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v3, vcc_lo, v11, s6
	v_add_co_ci_u32_e32 v4, vcc_lo, s7, v12, vcc_lo
	s_mov_b32 s12, 0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v3, v0
	s_mov_b32 s13, s12
	s_mov_b32 s14, s12
	s_mov_b32 s15, s12
	v_and_or_b32 v5, 0xffffff1f, v5, 32
	v_add_co_ci_u32_e32 v1, vcc_lo, v4, v1, vcc_lo
	v_dual_mov_b32 v7, v32 :: v_dual_mov_b32 v8, v33
	v_dual_mov_b32 v11, s12 :: v_dual_mov_b32 v12, s13
	v_dual_mov_b32 v13, s14 :: v_dual_mov_b32 v14, s15
	s_clause 0x3
	global_store_b128 v[0:1], v[5:8], off
	global_store_b128 v[0:1], v[11:14], off offset:16
	global_store_b128 v[0:1], v[11:14], off offset:32
	global_store_b128 v[0:1], v[11:14], off offset:48
	s_and_saveexec_b32 s6, s0
	s_cbranch_execz .LBB0_170
; %bb.163:
	v_dual_mov_b32 v11, 0 :: v_dual_mov_b32 v12, s4
	v_mov_b32_e32 v13, s5
	s_clause 0x1
	global_load_b64 v[14:15], v11, s[2:3] offset:32 glc
	global_load_b64 v[3:4], v11, s[2:3] offset:40
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s10, v3
	v_readfirstlane_b32 s11, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[10:11], s[10:11], s[4:5]
	s_mul_i32 s7, s11, 24
	s_mul_hi_u32 s11, s10, 24
	s_mul_i32 s10, s10, 24
	s_add_i32 s11, s11, s7
	v_add_co_u32 v7, vcc_lo, v9, s10
	v_add_co_ci_u32_e32 v8, vcc_lo, s11, v10, vcc_lo
	s_mov_b32 s7, exec_lo
	global_store_b64 v[7:8], v[14:15], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[5:6], v11, v[12:15], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[5:6], v[14:15]
	s_cbranch_execz .LBB0_166
; %bb.164:                              ; %.preheader1.i.i.i59.preheader
	s_mov_b32 s10, 0
.LBB0_165:                              ; %.preheader1.i.i.i59
                                        ; =>This Inner Loop Header: Depth=1
	v_dual_mov_b32 v3, s4 :: v_dual_mov_b32 v4, s5
	s_sleep 1
	global_store_b64 v[7:8], v[5:6], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[3:4], v11, v[3:6], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[3:4], v[5:6]
	v_dual_mov_b32 v6, v4 :: v_dual_mov_b32 v5, v3
	s_or_b32 s10, vcc_lo, s10
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s10
	s_cbranch_execnz .LBB0_165
.LBB0_166:                              ; %Flow350
	s_or_b32 exec_lo, exec_lo, s7
	v_mov_b32_e32 v6, 0
	s_mov_b32 s10, exec_lo
	s_mov_b32 s7, exec_lo
	v_mbcnt_lo_u32_b32 v5, s10, 0
	global_load_b64 v[3:4], v6, s[2:3] offset:16
	v_cmpx_eq_u32_e32 0, v5
	s_cbranch_execz .LBB0_168
; %bb.167:
	s_bcnt1_i32_b32 s10, s10
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v5, s10
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[3:4], v[5:6], off offset:8
.LBB0_168:
	s_or_b32 exec_lo, exec_lo, s7
	s_waitcnt vmcnt(0)
	global_load_b64 v[5:6], v[3:4], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[5:6]
	s_cbranch_vccnz .LBB0_170
; %bb.169:
	global_load_b32 v3, v[3:4], off offset:24
	v_mov_b32_e32 v4, 0
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s7, v3
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[5:6], v[3:4], off
	s_and_b32 m0, s7, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_170:                              ; %Flow351
	s_or_b32 exec_lo, exec_lo, s6
	s_add_i32 s8, s8, s1
	v_add_co_u32 v3, vcc_lo, v9, s9
	v_add_co_ci_u32_e32 v4, vcc_lo, s8, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, v3, 20
	v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
.LBB0_171:                              ; =>This Inner Loop Header: Depth=1
	v_mov_b32_e32 v5, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_173
; %bb.172:                              ;   in Loop: Header=BB0_171 Depth=1
	global_load_b32 v5, v[3:4], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v5, 1, v5
.LBB0_173:                              ;   in Loop: Header=BB0_171 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v5
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB0_175
; %bb.174:                              ;   in Loop: Header=BB0_171 Depth=1
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB0_176
.LBB0_175:                              ;   in Loop: Header=BB0_171 Depth=1
	s_mov_b32 s1, -1
.LBB0_176:                              ; %Flow345
                                        ;   in Loop: Header=BB0_171 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB0_171
; %bb.177:
	global_load_b64 v[0:1], v[0:1], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_181
; %bb.178:
	v_mov_b32_e32 v9, 0
	s_clause 0x2
	global_load_b64 v[5:6], v9, s[2:3] offset:40
	global_load_b64 v[10:11], v9, s[2:3] offset:24 glc
	global_load_b64 v[7:8], v9, s[2:3]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v12, vcc_lo, v5, 1
	v_add_co_ci_u32_e32 v13, vcc_lo, 0, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, v12, s4
	v_add_co_ci_u32_e32 v4, vcc_lo, s5, v13, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[3:4]
	v_dual_cndmask_b32 v4, v4, v13 :: v_dual_cndmask_b32 v3, v3, v12
	v_and_b32_e32 v6, v4, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v5, v3, v5
	v_mul_lo_u32 v6, v6, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v12, v5, 24
	v_mul_lo_u32 v5, v5, 24
	v_add_nc_u32_e32 v6, v12, v6
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v7, vcc_lo, v7, v5
	v_mov_b32_e32 v5, v10
	v_add_co_ci_u32_e32 v8, vcc_lo, v8, v6, vcc_lo
	v_mov_b32_e32 v6, v11
	global_store_b64 v[7:8], v[10:11], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[5:6], v9, v[3:6], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[5:6], v[10:11]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_181
; %bb.179:                              ; %.preheader.i.i.i58.preheader
	s_mov_b32 s0, 0
.LBB0_180:                              ; %.preheader.i.i.i58
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	global_store_b64 v[7:8], v[5:6], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[10:11], v9, v[3:6], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[10:11], v[5:6]
	v_dual_mov_b32 v5, v10 :: v_dual_mov_b32 v6, v11
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB0_180
.LBB0_181:                              ; %__ockl_printf_append_args.exit
	s_or_b32 exec_lo, exec_lo, s1
	;;#ASMSTART
	;;#ASMEND
	v_readfirstlane_b32 s0, v31
	v_mov_b32_e32 v8, 0
	v_mov_b32_e32 v9, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_eq_u32_e64 s0, s0, v31
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_187
; %bb.182:
	v_mov_b32_e32 v3, 0
	s_mov_b32 s4, exec_lo
	global_load_b64 v[6:7], v3, s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[4:5], v3, s[2:3] offset:40
	global_load_b64 v[8:9], v3, s[2:3]
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v4, v4, v6
	v_and_b32_e32 v5, v5, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v10, v4, 24
	v_mul_lo_u32 v5, v5, 24
	v_mul_lo_u32 v4, v4, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v5, v10, v5
	s_waitcnt vmcnt(0)
	v_add_co_u32 v4, vcc_lo, v8, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, v9, v5, vcc_lo
	global_load_b64 v[4:5], v[4:5], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[8:9], v3, v[4:7], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[8:9], v[6:7]
	s_cbranch_execz .LBB0_186
; %bb.183:                              ; %.preheader3.i.i.i68.preheader
	s_mov_b32 s5, 0
.LBB0_184:                              ; %.preheader3.i.i.i68
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[4:5], v3, s[2:3] offset:40
	global_load_b64 v[10:11], v3, s[2:3]
	v_dual_mov_b32 v6, v8 :: v_dual_mov_b32 v7, v9
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v4, v4, v6
	v_and_b32_e32 v5, v5, v7
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[8:9], null, v4, 24, v[10:11]
	v_mov_b32_e32 v4, v9
	s_delay_alu instid0(VALU_DEP_1)
	v_mad_u64_u32 v[9:10], null, v5, 24, v[4:5]
	global_load_b64 v[4:5], v[8:9], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[8:9], v3, v[4:7], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[6:7]
	s_or_b32 s5, vcc_lo, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s5
	s_cbranch_execnz .LBB0_184
; %bb.185:                              ; %Flow338
	s_or_b32 exec_lo, exec_lo, s5
.LBB0_186:                              ; %Flow340
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s4
.LBB0_187:                              ; %.loopexit4.i.i.i62
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	v_mov_b32_e32 v32, 0
	v_readfirstlane_b32 s4, v8
	v_readfirstlane_b32 s5, v9
	s_mov_b32 s10, exec_lo
	s_clause 0x1
	global_load_b64 v[10:11], v32, s[2:3] offset:40
	global_load_b128 v[4:7], v32, s[2:3]
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s6, v10
	v_readfirstlane_b32 s7, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[6:7], s[4:5], s[6:7]
	s_mul_i32 s1, s7, 24
	s_mul_hi_u32 s8, s6, 24
	s_mul_i32 s9, s6, 24
	s_and_saveexec_b32 s11, s0
	s_cbranch_execz .LBB0_189
; %bb.188:
	v_dual_mov_b32 v8, s10 :: v_dual_mov_b32 v9, v32
	s_add_i32 s10, s8, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v12, vcc_lo, v4, s9
	v_add_co_ci_u32_e32 v13, vcc_lo, s10, v5, vcc_lo
	v_dual_mov_b32 v10, 2 :: v_dual_mov_b32 v11, 1
	global_store_b128 v[12:13], v[8:11], off offset:8
.LBB0_189:
	s_or_b32 exec_lo, exec_lo, s11
	s_lshl_b64 s[6:7], s[6:7], 12
	v_lshlrev_b64 v[8:9], 6, v[31:32]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v3, vcc_lo, v6, s6
	v_add_co_ci_u32_e32 v6, vcc_lo, s7, v7, vcc_lo
	s_mov_b32 s12, 0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v10, vcc_lo, v3, v8
	s_mov_b32 s13, s12
	s_mov_b32 s14, s12
	s_mov_b32 s15, s12
	v_and_or_b32 v0, 0xffffff1d, v0, 34
	v_add_co_ci_u32_e32 v11, vcc_lo, v6, v9, vcc_lo
	v_dual_mov_b32 v3, v32 :: v_dual_mov_b32 v6, s12
	v_dual_mov_b32 v7, s13 :: v_dual_mov_b32 v8, s14
	v_mov_b32_e32 v9, s15
	s_clause 0x3
	global_store_b128 v[10:11], v[0:3], off
	global_store_b128 v[10:11], v[6:9], off offset:16
	global_store_b128 v[10:11], v[6:9], off offset:32
	global_store_b128 v[10:11], v[6:9], off offset:48
	s_and_saveexec_b32 s6, s0
	s_cbranch_execz .LBB0_197
; %bb.190:
	v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v9, s4
	v_mov_b32_e32 v10, s5
	s_clause 0x1
	global_load_b64 v[11:12], v8, s[2:3] offset:32 glc
	global_load_b64 v[0:1], v8, s[2:3] offset:40
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s10, v0
	v_readfirstlane_b32 s11, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[10:11], s[10:11], s[4:5]
	s_mul_i32 s7, s11, 24
	s_mul_hi_u32 s11, s10, 24
	s_mul_i32 s10, s10, 24
	s_add_i32 s11, s11, s7
	v_add_co_u32 v6, vcc_lo, v4, s10
	v_add_co_ci_u32_e32 v7, vcc_lo, s11, v5, vcc_lo
	s_mov_b32 s7, exec_lo
	global_store_b64 v[6:7], v[11:12], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v8, v[9:12], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[2:3], v[11:12]
	s_cbranch_execz .LBB0_193
; %bb.191:                              ; %.preheader1.i.i.i66.preheader
	s_mov_b32 s10, 0
.LBB0_192:                              ; %.preheader1.i.i.i66
                                        ; =>This Inner Loop Header: Depth=1
	v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s5
	s_sleep 1
	global_store_b64 v[6:7], v[2:3], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[0:1], v8, v[0:3], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
	v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
	s_or_b32 s10, vcc_lo, s10
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s10
	s_cbranch_execnz .LBB0_192
.LBB0_193:                              ; %Flow336
	s_or_b32 exec_lo, exec_lo, s7
	v_mov_b32_e32 v3, 0
	s_mov_b32 s10, exec_lo
	s_mov_b32 s7, exec_lo
	v_mbcnt_lo_u32_b32 v2, s10, 0
	global_load_b64 v[0:1], v3, s[2:3] offset:16
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB0_195
; %bb.194:
	s_bcnt1_i32_b32 s10, s10
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v2, s10
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[0:1], v[2:3], off offset:8
.LBB0_195:
	s_or_b32 exec_lo, exec_lo, s7
	s_waitcnt vmcnt(0)
	global_load_b64 v[2:3], v[0:1], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
	s_cbranch_vccnz .LBB0_197
; %bb.196:
	global_load_b32 v0, v[0:1], off offset:24
	v_mov_b32_e32 v1, 0
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s7, v0
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[2:3], v[0:1], off
	s_and_b32 m0, s7, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_197:                              ; %Flow337
	s_or_b32 exec_lo, exec_lo, s6
	s_add_i32 s8, s8, s1
	v_add_co_u32 v0, vcc_lo, v4, s9
	v_add_co_ci_u32_e32 v1, vcc_lo, s8, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, 20
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
.LBB0_198:                              ; =>This Inner Loop Header: Depth=1
	v_mov_b32_e32 v2, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_200
; %bb.199:                              ;   in Loop: Header=BB0_198 Depth=1
	global_load_b32 v2, v[0:1], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v2, 1, v2
.LBB0_200:                              ;   in Loop: Header=BB0_198 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v2
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB0_202
; %bb.201:                              ;   in Loop: Header=BB0_198 Depth=1
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB0_203
.LBB0_202:                              ;   in Loop: Header=BB0_198 Depth=1
	s_mov_b32 s1, -1
.LBB0_203:                              ; %Flow331
                                        ;   in Loop: Header=BB0_198 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB0_198
; %bb.204:
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_208
; %bb.205:
	v_mov_b32_e32 v6, 0
	s_clause 0x2
	global_load_b64 v[2:3], v6, s[2:3] offset:40
	global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
	global_load_b64 v[4:5], v6, s[2:3]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v9, vcc_lo, v2, 1
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v9, s4
	v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
	v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
	v_and_b32_e32 v3, v1, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v2, v0, v2
	v_mul_lo_u32 v3, v3, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v9, v2, 24
	v_mul_lo_u32 v2, v2, 24
	v_add_nc_u32_e32 v3, v9, v3
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v4, vcc_lo, v4, v2
	v_mov_b32_e32 v2, v7
	v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
	v_mov_b32_e32 v3, v8
	global_store_b64 v[4:5], v[7:8], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_208
; %bb.206:                              ; %.preheader.i.i.i65.preheader
	s_mov_b32 s0, 0
.LBB0_207:                              ; %.preheader.i.i.i65
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	global_store_b64 v[4:5], v[2:3], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
	v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB0_207
.LBB0_208:                              ; %__ockl_printf_append_args.exit69
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z19exclusiveScanKernelIiEvPT_PKS0_m
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 35
		.amdhsa_next_free_sgpr 18
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z19exclusiveScanKernelIiEvPT_PKS0_m,"axG",@progbits,_Z19exclusiveScanKernelIiEvPT_PKS0_m,comdat
.Lfunc_end0:
	.size	_Z19exclusiveScanKernelIiEvPT_PKS0_m, .Lfunc_end0-_Z19exclusiveScanKernelIiEvPT_PKS0_m
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 8436
; NumSgprs: 20
; NumVgprs: 35
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 4
; NumSGPRsForWavesPerEU: 20
; NumVGPRsForWavesPerEU: 35
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	.str,@object                    ; @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.str:
	.asciz	"Thread %d = %d\n"
	.size	.str, 16

	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           8
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         104
        .size:           8
        .value_kind:     hidden_hostcall_buffer
      - .offset:         144
        .size:           4
        .value_kind:     hidden_dynamic_lds_size
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z19exclusiveScanKernelIiEvPT_PKS0_m
    .private_segment_fixed_size: 0
    .sgpr_count:     20
    .sgpr_spill_count: 0
    .symbol:         _Z19exclusiveScanKernelIiEvPT_PKS0_m.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     35
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
