#include <stdio.h>
#include <iostream>
#include <stdlib.h>

/**
* Computes the log of reaction rate.
* @param a: Pointer to coefficient matrix.
* @param temp: Pointer to temperature array.
* @param lam: Matrix to write the results to.
* @param nsets: Number of sets / number of rows in coefficient matrix.
* @param ncells: Number of cells / length of temperature array.
* @param ncoeff: Number of coefficients / number of columns in coefficient matrix.
*/
template <class dtype>
__device__ void rates(dtype *a, dtype *temp, dtype *lam, int nsets, int ncells, int ncoeff)
{
    int istart = blockIdx.x * blockDim.x + threadIdx.x;
    int istep = blockDim.x * gridDim.x;
    
    int jstart = blockIdx.y * blockDim.y + threadIdx.y;
    int jstep = blockDim.y * gridDim.y;
    
    int kstart = blockIdx.z * blockDim.z + threadIdx.z;
    int kstep = blockDim.z * gridDim.z;
    
    for(int i = istart; i < nsets; i += istep)
    {
        for(int j = jstart; j < ncells; j += jstep)
        {            
            for(int k = kstart; k < ncoeff; k += kstep)
            {
                atomicAdd(&lam[i * ncells + j], a[i * ncoeff + k] * temp[k * ncells + j]);
            }
        }
    }
}

template <class dtype, int nsets, int ncells, int ncoeff>
__global__ void exec(dtype *lam)
{
    int xInd = blockIdx.x * blockDim.x + threadIdx.x;
    int xSize = blockDim.x * gridDim.x;
    int yInd = blockIdx.y * blockDim.y + threadIdx.y;
    int ySize = blockDim.y * gridDim.y;
    int zInd = blockIdx.z * blockDim.z + threadIdx.z;
    int zSize = blockDim.z * gridDim.z;
    
    int ind = xInd * ySize * zSize + yInd * zSize + zInd;
    int numThreads = xSize * ySize * zSize;
    
    // Tensors
    __shared__ dtype a[nsets * ncoeff];
    
    // These are all of the sets in reaclib with two nuclei as reactants
    // where one of them is carbon-12.
    if(ind == 0)
    {
        // he4 + c12 -> o16 (1)
        a[0] = 69.6526;
        a[1] = -1.39254;
        a[2] = 58.9128;
        a[3] = -148.273;
        a[4] = 9.08324;
        a[5] = -0.541041;
        a[6] = 70.3554;
        
        // he4 + c12 -> o16 (2)
        a[7] = 254.634;
        a[8] = -1.84097;
        a[9] = 103.411;
        a[10] = -420.567;
        a[11] = 64.0874;
        a[12] = -12.4624;
        a[13] = 137.303;
        
        // he4 + c12 -> n + o15
        a[14] = 17.0115;
        a[15] = -98.6615;
        a[16] = 0.0;
        a[17] = 0.124787;
        a[18] = 0.0588937;
        a[19] = -0.00679206;
        a[20] = 0.0;
        
        // he4 + c12 -> p + n15 (1)
        a[21] = 27.118;
        a[22] = -57.6279;
        a[23] = -15.253;
        a[24] = 1.59318;
        a[25] = 2.4479;
        a[26] = -2.19708;
        a[27] = -0.666667;
        
        // he4 + c12 -> p + n15 (2)
        a[28] = -5.2319;
        a[29] = -59.6491;
        a[30] = 0.0;
        a[31] = 30.8497;
        a[32] = -8.50433;
        a[33] = -1.54426;
        a[34] = -1.5;
        
        // he4 + c12 -> p + n15 (3)
        a[35] = 20.5388;
        a[36] = -65.034;
        a[37] = 0.0;
        a[38] = 0.0;
        a[39] = 0.0;
        a[40] = 0.0;
        a[41] = -1.5;
        
        // he4 + c12 -> p + n15 (4)
        a[42] = -6.93365;
        a[43] = -58.7917;
        a[44] = 0.0;
        a[45] = 22.7105;
        a[46] = -2.90707;
        a[47] = 0.205754;
        a[48] = -1.5;
        
        // c12 + c12 -> n + mg23
        a[49] = -12.8056;
        a[50] = -30.1498;
        a[51] = 0.0;
        a[52] = 11.4826;
        a[53] = 1.82849;
        a[54] = -0.34844;
        a[55] = 0.0;
        
        // c12 + c12 -> p + na23
        a[56] = 60.9649;
        a[57] = 0.0;
        a[58] = -84.165;
        a[59] = -1.4191;
        a[60] = -0.114619;
        a[61] = -0.070307;
        a[62] = -0.666667;
        
        // c12 + c12 -> he4 + ne20
        a[63] = 61.2863;
        a[64] = 0.0;
        a[65] = -84.165;
        a[66] = -1.56627;
        a[67] = -0.0736084;
        a[68] = -0.072797;
        a[69] = -0.666667;
        
        // he4 + he4 + he4 -> c12 (1)
        a[70] = -0.971052;
        a[71] = 0.0;
        a[72] = -37.06;
        a[73] = 29.3493;
        a[74] = -115.507;
        a[75] = -10.0;
        a[76] = -1.33333;
        
        // he4 + he4 + he4 -> c12 (2)
        a[77] = -11.7884;
        a[78] = -1.02446;
        a[79] = -23.57;
        a[80] = 20.4886;
        a[81] = -12.9882;
        a[82] = -20.0;
        a[83] = -2.16667;
        
        // he4 + he4 + he4 -> c12 (3)
        a[84] = -24.3505;
        a[85] = -4.12656;
        a[86] = -13.49;
        a[87] = 21.4259;
        a[88] = -1.34769;
        a[89] = 0.0879816;
        a[90] = -13.1653;
    }
    
    __shared__ dtype temp[ncoeff * ncells];
    
    for(int i = ind; i < ncells; i += numThreads)
    {
        dtype val = pow(10.0, 7 + 3.0 / ncells * i) * 1.0e-9;
        
        temp[i] = 1.0;
        temp[ncells + i] = 1 / val;
        temp[2 * ncells + i] = pow(val, (dtype)(-1.0 / 3.0));
        temp[3 * ncells + i] = pow(val, (dtype)(1.0 / 3.0));
        temp[4 * ncells + i] = val;
        temp[5 * ncells + i] = pow(val, (dtype)(5.0 / 3.0));
        temp[6 * ncells + i] = log(val);
        temp[7 * ncells + i] = 0.0;
    }
    
    __syncthreads();
    
    /*******************************************
    * Compute ln(lambda) for each set and cell *
    *******************************************/
    rates<dtype>(a, temp, lam, nsets, ncells, ncoeff);
}

int main()
{
    // Tensor dimensions
    const int nsets = 13, ncells = 10, ncoeff = 7;
    
    // Results matrix
    float *lam;
    cudaMallocManaged(&lam, nsets * ncells * sizeof(float));
    
    for(int i = 0; i < nsets; i++)
    {
        for(int j = 0; j < ncells; j++)
        {
            lam[i * ncells + j] = 0.0f;
        }
        
        printf("\n");
    }
    
    // Compute the rates
    dim3 threadsPerBlock(nsets, ncells, ncoeff);
    dim3 numBlocks(1, 1, 1);
    exec<float, nsets, ncells, ncoeff><<<numBlocks, threadsPerBlock>>>(lam);
    
    // Print ln(lambda)
    cudaDeviceSynchronize();
    printf("lambda:\n");
    
    for(int i = 0; i < nsets; i++)
    {
        for(int j = 0; j < ncells; j++)
        {
            printf("%8.3f   ", lam[i * ncells + j]);
        }
        
        printf("\n");
    }
    
    return 0;
}

	.file	"tmpxft_00303a92_00000000-6_react_matrix.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3641:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3641:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.type	_ZL42__device_stub__Z4execIfLi13ELi10ELi7EEvPT_Pf, @function
_ZL42__device_stub__Z4execIfLi13ELi10ELi7EEvPT_Pf:
.LFB3663:
	.cfi_startproc
	subq	$104, %rsp
	.cfi_def_cfa_offset 112
	movq	%rdi, 8(%rsp)
	leaq	24(%rsp), %rcx
	leaq	16(%rsp), %rdx
	leaq	44(%rsp), %rsi
	leaq	32(%rsp), %rdi
	movq	%fs:40, %rax
	movq	%rax, 88(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 40(%rsp)
	movq	%rax, 80(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 32(%rsp)
	movq	%rax, 44(%rsp)
	movl	$1, 52(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	24(%rsp)
	.cfi_def_cfa_offset 120
	leaq	_Z4execIfLi13ELi10ELi7EEvPT_(%rip), %rdi
	pushq	24(%rsp)
	.cfi_def_cfa_offset 128
	movq	60(%rsp), %rcx
	movl	68(%rsp), %r8d
	movq	48(%rsp), %rsi
	movl	56(%rsp), %edx
	leaq	96(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 120
	popq	%rdx
	.cfi_def_cfa_offset 112
.L2:
	movq	88(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$104, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3663:
	.size	_ZL42__device_stub__Z4execIfLi13ELi10ELi7EEvPT_Pf, .-_ZL42__device_stub__Z4execIfLi13ELi10ELi7EEvPT_Pf
	.section	.text._Z4execIfLi13ELi10ELi7EEvPT_,"axG",@progbits,_Z4execIfLi13ELi10ELi7EEvPT_,comdat
	.weak	_Z4execIfLi13ELi10ELi7EEvPT_
	.type	_Z4execIfLi13ELi10ELi7EEvPT_, @function
_Z4execIfLi13ELi10ELi7EEvPT_:
.LFB3967:
	.cfi_startproc
	endbr64
	jmp	_ZL42__device_stub__Z4execIfLi13ELi10ELi7EEvPT_Pf
	.cfi_endproc
.LFE3967:
	.size	_Z4execIfLi13ELi10ELi7EEvPT_, .-_Z4execIfLi13ELi10ELi7EEvPT_
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"\n"
.LC1:
	.string	"lambda:\n"
.LC2:
	.string	"%8.3f   "
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB3638:
	.cfi_startproc
	endbr64
	pushq	%r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	movl	$1, %edx
	movl	$520, %esi
	pushq	%r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	leaq	.LC0(%rip), %r12
	pushq	%rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	xorl	%ebx, %ebx
	subq	$56, %rsp
	.cfi_def_cfa_offset 96
	movq	%fs:40, %rax
	movq	%rax, 40(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rdi
	call	cudaMallocManaged@PLT
.L9:
	movq	8(%rsp), %rdx
	xorl	%eax, %eax
	movl	$10, %ecx
	movq	%r12, %rsi
	addq	%rbx, %rdx
	addq	$40, %rbx
	movq	%rdx, %rdi
	rep stosl
	movl	$2, %edi
	call	__printf_chk@PLT
	cmpq	$520, %rbx
	jne	.L9
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$7, %ecx
	movl	$1, %esi
	movabsq	$42949672973, %rdx
	movl	$7, 24(%rsp)
	movabsq	$4294967297, %rdi
	movq	%rdx, 16(%rsp)
	movq	%rdi, 28(%rsp)
	movl	$1, 36(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L10
	movq	8(%rsp), %rdi
	call	_ZL42__device_stub__Z4execIfLi13ELi10ELi7EEvPT_Pf
.L10:
	call	cudaDeviceSynchronize@PLT
	leaq	.LC1(%rip), %rsi
	xorl	%eax, %eax
	xorl	%ebp, %ebp
	movl	$2, %edi
	leaq	.LC2(%rip), %r13
	call	__printf_chk@PLT
.L11:
	xorl	%ebx, %ebx
.L12:
	leaq	0(,%rbx,4), %rax
	addq	8(%rsp), %rax
	movq	%r13, %rsi
	movl	$2, %edi
	cvtss2sd	(%rax,%rbp), %xmm0
	incq	%rbx
	movb	$1, %al
	call	__printf_chk@PLT
	cmpq	$10, %rbx
	jne	.L12
	movq	%r12, %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	addq	$40, %rbp
	call	__printf_chk@PLT
	cmpq	$520, %rbp
	jne	.L11
	movq	40(%rsp), %rax
	subq	%fs:40, %rax
	je	.L14
	call	__stack_chk_fail@PLT
.L14:
	addq	$56, %rsp
	.cfi_def_cfa_offset 40
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3638:
	.size	main, .-main
	.section	.rodata.str1.1
.LC3:
	.string	"_Z4execIfLi13ELi10ELi7EEvPT_"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3666:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC3(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z4execIfLi13ELi10ELi7EEvPT_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3666:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include <stdio.h>
#include <iostream>
#include <stdlib.h>

/**
* Computes the log of reaction rate.
* @param a: Pointer to coefficient matrix.
* @param temp: Pointer to temperature array.
* @param lam: Matrix to write the results to.
* @param nsets: Number of sets / number of rows in coefficient matrix.
* @param ncells: Number of cells / length of temperature array.
* @param ncoeff: Number of coefficients / number of columns in coefficient matrix.
*/
template <class dtype>
__device__ void rates(dtype *a, dtype *temp, dtype *lam, int nsets, int ncells, int ncoeff)
{
    int istart = blockIdx.x * blockDim.x + threadIdx.x;
    int istep = blockDim.x * gridDim.x;
    
    int jstart = blockIdx.y * blockDim.y + threadIdx.y;
    int jstep = blockDim.y * gridDim.y;
    
    int kstart = blockIdx.z * blockDim.z + threadIdx.z;
    int kstep = blockDim.z * gridDim.z;
    
    for(int i = istart; i < nsets; i += istep)
    {
        for(int j = jstart; j < ncells; j += jstep)
        {            
            for(int k = kstart; k < ncoeff; k += kstep)
            {
                atomicAdd(&lam[i * ncells + j], a[i * ncoeff + k] * temp[k * ncells + j]);
            }
        }
    }
}

template <class dtype, int nsets, int ncells, int ncoeff>
__global__ void exec(dtype *lam)
{
    int xInd = blockIdx.x * blockDim.x + threadIdx.x;
    int xSize = blockDim.x * gridDim.x;
    int yInd = blockIdx.y * blockDim.y + threadIdx.y;
    int ySize = blockDim.y * gridDim.y;
    int zInd = blockIdx.z * blockDim.z + threadIdx.z;
    int zSize = blockDim.z * gridDim.z;
    
    int ind = xInd * ySize * zSize + yInd * zSize + zInd;
    int numThreads = xSize * ySize * zSize;
    
    // Tensors
    __shared__ dtype a[nsets * ncoeff];
    
    // These are all of the sets in reaclib with two nuclei as reactants
    // where one of them is carbon-12.
    if(ind == 0)
    {
        // he4 + c12 -> o16 (1)
        a[0] = 69.6526;
        a[1] = -1.39254;
        a[2] = 58.9128;
        a[3] = -148.273;
        a[4] = 9.08324;
        a[5] = -0.541041;
        a[6] = 70.3554;
        
        // he4 + c12 -> o16 (2)
        a[7] = 254.634;
        a[8] = -1.84097;
        a[9] = 103.411;
        a[10] = -420.567;
        a[11] = 64.0874;
        a[12] = -12.4624;
        a[13] = 137.303;
        
        // he4 + c12 -> n + o15
        a[14] = 17.0115;
        a[15] = -98.6615;
        a[16] = 0.0;
        a[17] = 0.124787;
        a[18] = 0.0588937;
        a[19] = -0.00679206;
        a[20] = 0.0;
        
        // he4 + c12 -> p + n15 (1)
        a[21] = 27.118;
        a[22] = -57.6279;
        a[23] = -15.253;
        a[24] = 1.59318;
        a[25] = 2.4479;
        a[26] = -2.19708;
        a[27] = -0.666667;
        
        // he4 + c12 -> p + n15 (2)
        a[28] = -5.2319;
        a[29] = -59.6491;
        a[30] = 0.0;
        a[31] = 30.8497;
        a[32] = -8.50433;
        a[33] = -1.54426;
        a[34] = -1.5;
        
        // he4 + c12 -> p + n15 (3)
        a[35] = 20.5388;
        a[36] = -65.034;
        a[37] = 0.0;
        a[38] = 0.0;
        a[39] = 0.0;
        a[40] = 0.0;
        a[41] = -1.5;
        
        // he4 + c12 -> p + n15 (4)
        a[42] = -6.93365;
        a[43] = -58.7917;
        a[44] = 0.0;
        a[45] = 22.7105;
        a[46] = -2.90707;
        a[47] = 0.205754;
        a[48] = -1.5;
        
        // c12 + c12 -> n + mg23
        a[49] = -12.8056;
        a[50] = -30.1498;
        a[51] = 0.0;
        a[52] = 11.4826;
        a[53] = 1.82849;
        a[54] = -0.34844;
        a[55] = 0.0;
        
        // c12 + c12 -> p + na23
        a[56] = 60.9649;
        a[57] = 0.0;
        a[58] = -84.165;
        a[59] = -1.4191;
        a[60] = -0.114619;
        a[61] = -0.070307;
        a[62] = -0.666667;
        
        // c12 + c12 -> he4 + ne20
        a[63] = 61.2863;
        a[64] = 0.0;
        a[65] = -84.165;
        a[66] = -1.56627;
        a[67] = -0.0736084;
        a[68] = -0.072797;
        a[69] = -0.666667;
        
        // he4 + he4 + he4 -> c12 (1)
        a[70] = -0.971052;
        a[71] = 0.0;
        a[72] = -37.06;
        a[73] = 29.3493;
        a[74] = -115.507;
        a[75] = -10.0;
        a[76] = -1.33333;
        
        // he4 + he4 + he4 -> c12 (2)
        a[77] = -11.7884;
        a[78] = -1.02446;
        a[79] = -23.57;
        a[80] = 20.4886;
        a[81] = -12.9882;
        a[82] = -20.0;
        a[83] = -2.16667;
        
        // he4 + he4 + he4 -> c12 (3)
        a[84] = -24.3505;
        a[85] = -4.12656;
        a[86] = -13.49;
        a[87] = 21.4259;
        a[88] = -1.34769;
        a[89] = 0.0879816;
        a[90] = -13.1653;
    }
    
    __shared__ dtype temp[ncoeff * ncells];
    
    for(int i = ind; i < ncells; i += numThreads)
    {
        dtype val = pow(10.0, 7 + 3.0 / ncells * i) * 1.0e-9;
        
        temp[i] = 1.0;
        temp[ncells + i] = 1 / val;
        temp[2 * ncells + i] = pow(val, (dtype)(-1.0 / 3.0));
        temp[3 * ncells + i] = pow(val, (dtype)(1.0 / 3.0));
        temp[4 * ncells + i] = val;
        temp[5 * ncells + i] = pow(val, (dtype)(5.0 / 3.0));
        temp[6 * ncells + i] = log(val);
        temp[7 * ncells + i] = 0.0;
    }
    
    __syncthreads();
    
    /*******************************************
    * Compute ln(lambda) for each set and cell *
    *******************************************/
    rates<dtype>(a, temp, lam, nsets, ncells, ncoeff);
}

int main()
{
    // Tensor dimensions
    const int nsets = 13, ncells = 10, ncoeff = 7;
    
    // Results matrix
    float *lam;
    hipMallocManaged(&lam, nsets * ncells * sizeof(float));
    
    for(int i = 0; i < nsets; i++)
    {
        for(int j = 0; j < ncells; j++)
        {
            lam[i * ncells + j] = 0.0f;
        }
        
        printf("\n");
    }
    
    // Compute the rates
    dim3 threadsPerBlock(nsets, ncells, ncoeff);
    dim3 numBlocks(1, 1, 1);
    exec<float, nsets, ncells, ncoeff><<<numBlocks, threadsPerBlock>>>(lam);
    
    // Print ln(lambda)
    hipDeviceSynchronize();
    printf("lambda:\n");
    
    for(int i = 0; i < nsets; i++)
    {
        for(int j = 0; j < ncells; j++)
        {
            printf("%8.3f   ", lam[i * ncells + j]);
        }
        
        printf("\n");
    }
    
    return 0;
}

	.text
	.file	"react_matrix.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	subq	$16, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	8(%rsp), %rdi
	movl	$520, %esi                      # imm = 0x208
	movl	$1, %edx
	callq	hipMallocManaged
	xorl	%ebx, %ebx
.LBB0_1:                                # %.preheader25
                                        # =>This Inner Loop Header: Depth=1
	movq	8(%rsp), %rax
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rax,%rbx)
	movups	%xmm0, (%rax,%rbx)
	movq	$0, 32(%rax,%rbx)
	movl	$10, %edi
	callq	putchar@PLT
	addq	$40, %rbx
	cmpq	$520, %rbx                      # imm = 0x208
	jne	.LBB0_1
# %bb.2:
	movabsq	$4294967297, %rdi               # imm = 0x100000001
	movabsq	$42949672973, %rdx              # imm = 0xA0000000D
	movl	$1, %esi
	movl	$7, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB0_4
# %bb.3:
	movq	8(%rsp), %rdi
	callq	_Z19__device_stub__execIfLi13ELi10ELi7EEvPT_
.LBB0_4:
	callq	hipDeviceSynchronize
	movl	$.Lstr, %edi
	callq	puts@PLT
	xorl	%ebx, %ebx
	xorl	%r14d, %r14d
.LBB0_5:                                # %.preheader
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB0_6 Depth 2
	xorl	%r15d, %r15d
.LBB0_6:                                #   Parent Loop BB0_5 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movq	8(%rsp), %rax
	addq	%rbx, %rax
	xorps	%xmm0, %xmm0
	cvtss2sd	(%rax,%r15,4), %xmm0
	movl	$.L.str.2, %edi
	movb	$1, %al
	callq	printf
	incq	%r15
	cmpq	$10, %r15
	jne	.LBB0_6
# %bb.7:                                #   in Loop: Header=BB0_5 Depth=1
	movl	$10, %edi
	callq	putchar@PLT
	incq	%r14
	addq	$40, %rbx
	cmpq	$13, %r14
	jne	.LBB0_5
# %bb.8:
	xorl	%eax, %eax
	addq	$16, %rsp
	.cfi_def_cfa_offset 32
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	main, .Lfunc_end0-main
	.cfi_endproc
                                        # -- End function
	.section	.text._Z19__device_stub__execIfLi13ELi10ELi7EEvPT_,"axG",@progbits,_Z19__device_stub__execIfLi13ELi10ELi7EEvPT_,comdat
	.weak	_Z19__device_stub__execIfLi13ELi10ELi7EEvPT_ # -- Begin function _Z19__device_stub__execIfLi13ELi10ELi7EEvPT_
	.type	_Z19__device_stub__execIfLi13ELi10ELi7EEvPT_,@function
_Z19__device_stub__execIfLi13ELi10ELi7EEvPT_: # @_Z19__device_stub__execIfLi13ELi10ELi7EEvPT_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$64, %rsp
	.cfi_def_cfa_offset 112
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	movq	%rsp, %rbx
	movq	%rax, (%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z4execIfLi13ELi10ELi7EEvPT_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$80, %rsp
	.cfi_adjust_cfa_offset -80
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z19__device_stub__execIfLi13ELi10ELi7EEvPT_, .Lfunc_end1-_Z19__device_stub__execIfLi13ELi10ELi7EEvPT_
	.cfi_endproc
                                        # -- End function
	.text
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z4execIfLi13ELi10ELi7EEvPT_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z4execIfLi13ELi10ELi7EEvPT_,@object # @_Z4execIfLi13ELi10ELi7EEvPT_
	.section	.rodata._Z4execIfLi13ELi10ELi7EEvPT_,"aG",@progbits,_Z4execIfLi13ELi10ELi7EEvPT_,comdat
	.weak	_Z4execIfLi13ELi10ELi7EEvPT_
	.p2align	3, 0x0
_Z4execIfLi13ELi10ELi7EEvPT_:
	.quad	_Z19__device_stub__execIfLi13ELi10ELi7EEvPT_
	.size	_Z4execIfLi13ELi10ELi7EEvPT_, 8

	.type	.L.str.2,@object                # @.str.2
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str.2:
	.asciz	"%8.3f   "
	.size	.L.str.2, 9

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z4execIfLi13ELi10ELi7EEvPT_"
	.size	.L__unnamed_1, 29

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.type	.Lstr,@object                   # @str
	.section	.rodata.str1.1,"aMS",@progbits,1
.Lstr:
	.asciz	"lambda:"
	.size	.Lstr, 8

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z19__device_stub__execIfLi13ELi10ELi7EEvPT_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z4execIfLi13ELi10ELi7EEvPT_
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.section	.text._Z4execIfLi13ELi10ELi7EEvPT_,"axG",@progbits,_Z4execIfLi13ELi10ELi7EEvPT_,comdat
	.protected	_Z4execIfLi13ELi10ELi7EEvPT_ ; -- Begin function _Z4execIfLi13ELi10ELi7EEvPT_
	.globl	_Z4execIfLi13ELi10ELi7EEvPT_
	.p2align	8
	.type	_Z4execIfLi13ELi10ELi7EEvPT_,@function
_Z4execIfLi13ELi10ELi7EEvPT_:           ; @_Z4execIfLi13ELi10ELi7EEvPT_
; %bb.0:
	s_clause 0x1
	s_load_b128 s[16:19], s[0:1], 0x8
	s_load_b32 s4, s[0:1], 0x18
	v_and_b32_e32 v4, 0x3ff, v0
	v_bfe_u32 v3, v0, 10, 10
	s_add_u32 s20, s0, 8
	s_addc_u32 s21, s1, 0
	v_bfe_u32 v0, v0, 20, 10
	s_mov_b32 s5, exec_lo
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s19, 16
	s_and_b32 s2, s19, 0xffff
	v_mad_u64_u32 v[1:2], null, s14, s3, v[3:4]
	s_and_b32 s4, s4, 0xffff
	v_mad_u64_u32 v[5:6], null, s13, s2, v[4:5]
	s_mul_i32 s12, s17, s3
	s_mul_i32 s33, s18, s4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[2:3], null, s15, s4, v[0:1]
	v_mad_u64_u32 v[7:8], null, s12, v5, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[5:6], null, v7, s33, v[2:3]
	v_cmpx_eq_u32_e32 0, v5
	s_cbranch_execz .LBB0_2
; %bb.1:
	v_dual_mov_b32 v7, 0xbfb23ec0 :: v_dual_mov_b32 v10, 0
	v_mov_b32_e32 v6, 0x428b4e22
	v_mov_b32_e32 v8, 0x426ba6b5
	v_mov_b32_e32 v9, 0xc31445e3
	s_delay_alu instid0(VALU_DEP_4)
	v_dual_mov_b32 v11, 0x411154f3 :: v_dual_mov_b32 v24, v10
	v_mov_b32_e32 v12, 0xbf0a81aa
	v_mov_b32_e32 v13, 0x428cb5f7
	v_mov_b32_e32 v14, 0x437ea24e
	v_mov_b32_e32 v15, 0xbfeba4e8
	v_mov_b32_e32 v16, 0x42ced26f
	v_mov_b32_e32 v17, 0xc3d24893
	v_mov_b32_e32 v18, 0x42802cc0
	v_mov_b32_e32 v19, 0xc14765fe
	v_mov_b32_e32 v20, 0x43094d91
	v_mov_b32_e32 v21, 0x4188178d
	v_dual_mov_b32 v22, 0xc2c552b0 :: v_dual_mov_b32 v23, v10
	v_mov_b32_e32 v25, v10
	ds_store_b128 v10, v[6:9]
	ds_store_b128 v10, v[11:14] offset:16
	ds_store_b128 v10, v[15:18] offset:32
	ds_store_b128 v10, v[19:22] offset:48
	v_mov_b32_e32 v11, 0x3dff9054
	v_mov_b32_e32 v12, 0x3d713a85
	v_mov_b32_e32 v13, 0xbbde8fee
	v_mov_b32_e32 v6, 0x3fcbed52
	v_mov_b32_e32 v7, 0x401caa65
	v_mov_b32_e32 v8, 0xc00c9cf5
	v_mov_b32_e32 v9, 0xbf2aaab0
	ds_store_b128 v10, v[10:13] offset:64
	v_mov_b32_e32 v11, 0x41d8f1aa
	v_mov_b32_e32 v12, 0xc26682f8
	v_mov_b32_e32 v13, 0xc1740c4a
	v_mov_b32_e32 v20, 0xbfc00000
	v_mov_b32_e32 v14, 0xc0a76bba
	v_mov_b32_e32 v15, 0xc26e98ae
	v_dual_mov_b32 v17, 0x41f6cc30 :: v_dual_mov_b32 v16, v10
	v_mov_b32_e32 v18, 0xc10811bc
	v_mov_b32_e32 v19, 0xbfc5aa50
	v_mov_b32_e32 v21, 0x41a44f76
	v_mov_b32_e32 v22, 0xc2821168
	ds_store_b128 v10, v[6:9] offset:96
	ds_store_b128 v10, v[10:13] offset:80
	ds_store_b128 v10, v[14:17] offset:112
	ds_store_b128 v10, v[18:21] offset:128
	ds_store_b128 v10, v[22:25] offset:144
	v_mov_b32_e32 v12, 0xc0dde076
	v_mov_b32_e32 v13, 0xc26b2ab3
	v_mov_b32_e32 v11, v20
	v_mov_b32_e32 v15, 0xc14ce3bd
	v_mov_b32_e32 v16, 0xc1f132ca
	v_dual_mov_b32 v14, v20 :: v_dual_mov_b32 v17, v10
	ds_store_b128 v10, v[10:13] offset:160
	v_mov_b32_e32 v11, 0x41b5af1b
	v_mov_b32_e32 v12, 0xc03a0d6f
	v_mov_b32_e32 v13, 0x3e52b12d
	ds_store_b128 v10, v[14:17] offset:192
	v_mov_b32_e32 v20, 0xc2a8547b
	v_mov_b32_e32 v14, 0x4137b8bb
	v_mov_b32_e32 v15, 0x3fea0bf6
	v_mov_b32_e32 v16, 0xbeb266ba
	ds_store_b128 v10, v[10:13] offset:176
	v_mov_b32_e32 v12, 0xbfc87b89
	v_mov_b32_e32 v13, 0xbd96c000
	v_dual_mov_b32 v11, v20 :: v_dual_mov_b32 v18, 0x4273dc0f
	v_mov_b32_e32 v21, 0xbfb5a512
	v_dual_mov_b32 v19, v10 :: v_dual_mov_b32 v22, 0xbdeabd5e
	v_mov_b32_e32 v23, 0xbd8ffd1e
	v_dual_mov_b32 v25, 0x4275252c :: v_dual_mov_b32 v24, v9
	v_mov_b32_e32 v6, 0xbd951698
	v_dual_mov_b32 v8, 0xbf7896dd :: v_dual_mov_b32 v7, v9
	v_mov_b32_e32 v9, v10
	ds_store_b128 v10, v[14:17] offset:208
	ds_store_b128 v10, v[18:21] offset:224
	ds_store_b128 v10, v[22:25] offset:240
	ds_store_b128 v10, v[10:13] offset:256
	ds_store_b128 v10, v[6:9] offset:272
	v_mov_b32_e32 v6, 0xc2143d71
	v_mov_b32_e32 v7, 0x41eacb5e
	v_mov_b32_e32 v8, 0xc2e70396
	v_mov_b32_e32 v9, 0xc1200000
	v_mov_b32_e32 v11, 0xbfaaaa8f
	v_mov_b32_e32 v12, 0xc13c9d49
	v_mov_b32_e32 v13, 0xbf832181
	v_mov_b32_e32 v14, 0xc1bc8f5c
	v_mov_b32_e32 v15, 0x41a3e8a7
	v_mov_b32_e32 v16, 0xc14fcfab
	v_mov_b32_e32 v17, 0xc1a00000
	v_mov_b32_e32 v18, 0xc00aaab9
	v_mov_b32_e32 v19, 0xc1c2cdd3
	v_mov_b32_e32 v20, 0xc0840cc8
	v_mov_b32_e32 v21, 0xc157d70a
	v_mov_b32_e32 v22, 0x41ab683e
	v_mov_b32_e32 v23, 0xbfac811b
	v_mov_b32_e32 v24, 0x3db42fb2
	v_mov_b32_e32 v25, 0xc152a512
	ds_store_b128 v10, v[6:9] offset:288
	ds_store_b128 v10, v[11:14] offset:304
	ds_store_b128 v10, v[15:18] offset:320
	ds_store_b128 v10, v[19:22] offset:336
	ds_store_b96 v10, v[23:25] offset:352
.LBB0_2:
	s_or_b32 exec_lo, exec_lo, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s76, exec_lo
	v_cmpx_gt_i32_e32 10, v5
	s_cbranch_execz .LBB0_5
; %bb.3:                                ; %.lr.ph.preheader
	s_mul_i32 s5, s16, s17
	s_mul_i32 s6, s16, s2
	s_mul_i32 s5, s5, s18
	v_lshl_add_u32 v0, v5, 2, 0x170
	s_mul_i32 s3, s5, s3
	v_dual_mov_b32 v3, 0x3ff00000 :: v_dual_mov_b32 v6, 0
	s_mul_i32 s3, s3, s4
	v_mov_b32_e32 v9, 1.0
	s_mul_i32 s77, s6, s12
	s_mul_i32 s3, s3, s2
	s_mov_b32 s14, 0x33333333
	s_mov_b32 s18, 0x55555555
	s_mov_b32 s22, 0x968915a9
	s_mov_b32 s24, 0x4222de17
	s_mov_b32 s26, 0x3abe935a
	s_mov_b32 s28, 0x47e6c9c2
	s_mov_b32 s30, 0xcfa74449
	s_mov_b32 s34, 0x71bf3c30
	s_mov_b32 s36, 0x1c7792ce
	s_mov_b32 s38, 0x924920da
	s_mov_b32 s40, 0x9999999c
	s_mov_b32 s42, 0xfefa39ef
	s_mov_b32 s44, 0x3b39803f
	s_mov_b32 s46, 0xd5df274d
	s_mov_b32 s48, 0x652b82fe
	s_mov_b32 s50, 0xfca7ab0c
	s_mov_b32 s52, 0x6a5dcb37
	s_mov_b32 s54, 0x623fde64
	s_mov_b32 s56, 0x7c89e6b0
	s_mov_b32 s58, 0x14761f6e
	s_mov_b32 s60, 0x1852b7b0
	s_mov_b32 s62, 0x11122322
	s_mov_b32 s64, 0x555502a1
	s_mov_b32 s66, 0x55555511
	s_mov_b32 s68, 11
	s_mov_b32 s70, 0xe826d695
	s_mov_b32 s17, 0
	s_mul_i32 s77, s77, s33
	s_lshl_b32 s78, s3, 2
	s_mov_b32 s15, 0x3fd33333
	s_mov_b32 s19, 0x3fe55555
	s_mov_b32 s23, 0x3fba6564
	s_mov_b32 s25, 0x3fbdee67
	s_mov_b32 s27, 0x3fbe25e4
	s_mov_b32 s29, 0x3fc110ef
	s_mov_b32 s31, 0x3fc3b13b
	s_mov_b32 s35, 0x3fc745d1
	s_mov_b32 s37, 0x3fcc71c7
	s_mov_b32 s39, 0x3fd24924
	s_mov_b32 s41, 0x3fd99999
	s_mov_b32 s43, 0x3fe62e42
	s_mov_b32 s45, 0x3c7abc9e
	s_mov_b32 s11, 0xbfe55555
	s_mov_b32 s47, 0x3c8543b0
	s_mov_b32 s49, 0x3ff71547
	s_mov_b32 s51, 0x3e928af3
	s_mov_b32 s53, 0x3e5ade15
	s_mov_b32 s55, 0x3ec71dee
	s_mov_b32 s57, 0x3efa0199
	s_mov_b32 s59, 0x3f2a01a0
	s_mov_b32 s61, 0x3f56c16c
	s_mov_b32 s63, 0x3f811111
	s_mov_b32 s65, 0x3fa55555
	s_mov_b32 s67, 0x3fc55555
	s_mov_b32 s69, 0x3fe00000
	s_mov_b32 s71, 0x3e112e0b
	s_mov_b32 s73, 0xbfe62e42
	s_mov_b32 s75, 0xbc7abc9e
	s_mov_b32 s79, 0x3e76c4e1
.LBB0_4:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	v_cvt_f64_i32_e32 v[7:8], v5
	s_mov_b32 s10, s18
	s_mov_b32 s72, s42
	s_mov_b32 s74, s44
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[10:11], v[7:8], s[14:15], 0x401c0000
	v_cmp_eq_f64_e32 vcc_lo, 0, v[10:11]
	v_cmp_eq_f64_e64 s3, |v[10:11]|, v[10:11]
	v_and_b32_e32 v8, 0x7fffffff, v11
	v_cndmask_b32_e32 v7, 0x40240000, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v8, 0, v8, s3
	v_frexp_mant_f64_e32 v[12:13], v[6:7]
	v_frexp_exp_i32_f64_e32 v14, v[6:7]
	v_cndmask_b32_e64 v7, 0, v10, s3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v32, v8, 0x3ff00000, vcc_lo
	v_cndmask_b32_e64 v33, v7, 0, vcc_lo
	v_cmp_gt_f64_e64 s3, s[18:19], v[12:13]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v8, 0, 1, s3
	v_subrev_co_ci_u32_e64 v14, vcc_lo, 0, v14, s3
	v_ldexp_f64 v[7:8], v[12:13], v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_f64_i32_e32 v[14:15], v14
	v_add_f64 v[12:13], v[7:8], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_f64 v[22:23], v[14:15], s[42:43]
	v_add_f64 v[16:17], v[7:8], -1.0
	v_rcp_f64_e32 v[20:21], v[12:13]
	v_add_f64 v[18:19], v[12:13], -1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[7:8], v[7:8], -v[18:19]
	v_fma_f64 v[18:19], v[14:15], s[42:43], -v[22:23]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[24:25], -v[12:13], v[20:21], 1.0
	v_fma_f64 v[14:15], v[14:15], s[44:45], v[18:19]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[18:19], v[24:25], v[20:21], v[20:21]
	v_add_f64 v[20:21], v[22:23], v[14:15]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[24:25], -v[12:13], v[18:19], 1.0
	v_add_f64 v[22:23], v[20:21], -v[22:23]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[18:19], v[24:25], v[18:19], v[18:19]
	v_add_f64 v[14:15], v[14:15], -v[22:23]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[22:23], v[16:17], v[18:19]
	v_mul_f64 v[24:25], v[12:13], v[22:23]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[12:13], v[22:23], v[12:13], -v[24:25]
	v_fma_f64 v[7:8], v[22:23], v[7:8], v[12:13]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[12:13], v[24:25], v[7:8]
	v_add_f64 v[26:27], v[16:17], -v[12:13]
	v_add_f64 v[24:25], v[12:13], -v[24:25]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[16:17], v[16:17], -v[26:27]
	v_add_f64 v[7:8], v[24:25], -v[7:8]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[12:13], v[16:17], -v[12:13]
	v_add_f64 v[7:8], v[7:8], v[12:13]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[7:8], v[26:27], v[7:8]
	v_mul_f64 v[7:8], v[18:19], v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[12:13], v[22:23], v[7:8]
	v_add_f64 v[16:17], v[12:13], -v[22:23]
	v_mul_f64 v[18:19], v[12:13], v[12:13]
	v_ldexp_f64 v[22:23], v[12:13], 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[7:8], v[7:8], -v[16:17]
	v_fma_f64 v[16:17], v[12:13], v[12:13], -v[18:19]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[24:25], v[7:8], v[7:8]
	v_ldexp_f64 v[26:27], v[7:8], 1
	v_fma_f64 v[16:17], v[12:13], v[24:25], v[16:17]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[24:25], v[18:19], v[16:17]
	v_fma_f64 v[28:29], v[24:25], s[24:25], s[22:23]
	v_add_f64 v[18:19], v[24:25], -v[18:19]
	v_mul_f64 v[30:31], v[12:13], v[24:25]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[28:29], v[24:25], v[28:29], s[26:27]
	v_add_f64 v[16:17], v[16:17], -v[18:19]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[18:19], v[24:25], v[12:13], -v[30:31]
	v_fma_f64 v[28:29], v[24:25], v[28:29], s[28:29]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[7:8], v[24:25], v[7:8], v[18:19]
	v_fma_f64 v[18:19], v[24:25], v[28:29], s[30:31]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[7:8], v[16:17], v[12:13], v[7:8]
	v_fma_f64 v[12:13], v[24:25], v[18:19], s[34:35]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[18:19], v[30:31], v[7:8]
	v_fma_f64 v[12:13], v[24:25], v[12:13], s[36:37]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[28:29], v[18:19], -v[30:31]
	v_fma_f64 v[12:13], v[24:25], v[12:13], s[38:39]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[7:8], v[7:8], -v[28:29]
	v_fma_f64 v[12:13], v[24:25], v[12:13], s[40:41]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[28:29], v[24:25], v[12:13]
	v_fma_f64 v[24:25], v[24:25], v[12:13], -v[28:29]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[12:13], v[16:17], v[12:13], v[24:25]
	v_add_f64 v[16:17], v[28:29], v[12:13]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[24:25], v[16:17], s[18:19]
	v_add_f64 v[28:29], v[16:17], -v[28:29]
	v_add_f64 v[30:31], v[24:25], s[10:11]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[12:13], v[12:13], -v[28:29]
	v_add_f64 v[16:17], v[16:17], -v[30:31]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[12:13], v[12:13], s[46:47]
	v_add_f64 v[12:13], v[12:13], v[16:17]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[16:17], v[24:25], v[12:13]
	v_add_f64 v[24:25], v[24:25], -v[16:17]
	v_mul_f64 v[28:29], v[18:19], v[16:17]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[12:13], v[12:13], v[24:25]
	v_fma_f64 v[24:25], v[18:19], v[16:17], -v[28:29]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[12:13], v[18:19], v[12:13], v[24:25]
	v_fma_f64 v[7:8], v[7:8], v[16:17], v[12:13]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[12:13], v[28:29], v[7:8]
	v_add_f64 v[16:17], v[22:23], v[12:13]
	v_add_f64 v[18:19], v[12:13], -v[28:29]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[22:23], v[16:17], -v[22:23]
	v_add_f64 v[7:8], v[7:8], -v[18:19]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[12:13], v[12:13], -v[22:23]
	v_add_f64 v[7:8], v[26:27], v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[7:8], v[7:8], v[12:13]
	v_add_f64 v[12:13], v[16:17], v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[18:19], v[20:21], v[12:13]
	v_add_f64 v[16:17], v[12:13], -v[16:17]
	v_add_f64 v[22:23], v[18:19], -v[20:21]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[7:8], v[7:8], -v[16:17]
	v_add_f64 v[16:17], v[18:19], -v[22:23]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[24:25], v[14:15], v[7:8]
	v_add_f64 v[12:13], v[12:13], -v[22:23]
	v_add_f64 v[16:17], v[20:21], -v[16:17]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[20:21], v[24:25], -v[14:15]
	v_add_f64 v[12:13], v[12:13], v[16:17]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[16:17], v[24:25], -v[20:21]
	v_add_f64 v[7:8], v[7:8], -v[20:21]
	v_add_f64 v[12:13], v[24:25], v[12:13]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[14:15], v[14:15], -v[16:17]
	v_add_f64 v[16:17], v[18:19], v[12:13]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[7:8], v[7:8], v[14:15]
	v_add_f64 v[14:15], v[16:17], -v[18:19]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[12:13], v[12:13], -v[14:15]
	v_add_f64 v[7:8], v[7:8], v[12:13]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[12:13], v[16:17], v[7:8]
	v_add_f64 v[14:15], v[12:13], -v[16:17]
	v_mul_f64 v[16:17], v[10:11], v[12:13]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[7:8], v[7:8], -v[14:15]
	v_fma_f64 v[12:13], v[10:11], v[12:13], -v[16:17]
	v_cmp_class_f64_e64 vcc_lo, v[16:17], 0x204
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[7:8], v[10:11], v[7:8], v[12:13]
	v_add_f64 v[12:13], v[16:17], v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v14, v12, v16 :: v_dual_add_nc_u32 v5, s77, v5
	v_cndmask_b32_e32 v15, v13, v17, vcc_lo
	v_add_f64 v[12:13], v[12:13], -v[16:17]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_lt_i32_e64 s2, 9, v5
	v_mul_f64 v[16:17], v[14:15], s[48:49]
	v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[14:15]|
	v_cmp_ngt_f64_e64 s3, 0xc090cc00, v[14:15]
	v_add_f64 v[7:8], v[7:8], -v[12:13]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rndne_f64_e32 v[12:13], v[16:17]
	v_dual_cndmask_b32 v8, 0, v8 :: v_dual_cndmask_b32 v7, 0, v7
	v_cmp_nlt_f64_e32 vcc_lo, 0x40900000, v[14:15]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f64 v[16:17], v[12:13], s[72:73], v[14:15]
	v_cvt_i32_f64_e32 v18, v[12:13]
	v_fma_f64 v[12:13], v[12:13], s[74:75], v[16:17]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[16:17], v[12:13], s[52:53], s[50:51]
	v_fma_f64 v[16:17], v[12:13], v[16:17], s[54:55]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[16:17], v[12:13], v[16:17], s[56:57]
	v_fma_f64 v[16:17], v[12:13], v[16:17], s[58:59]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[16:17], v[12:13], v[16:17], s[60:61]
	v_fma_f64 v[16:17], v[12:13], v[16:17], s[62:63]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[16:17], v[12:13], v[16:17], s[64:65]
	v_fma_f64 v[16:17], v[12:13], v[16:17], s[66:67]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[16:17], v[12:13], v[16:17], s[68:69]
	v_fma_f64 v[16:17], v[12:13], v[16:17], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[12:13], v[12:13], v[16:17], 1.0
	v_ldexp_f64 v[12:13], v[12:13], v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v13, 0x7ff00000, v13, vcc_lo
	s_and_b32 vcc_lo, s3, vcc_lo
	v_cndmask_b32_e32 v12, 0, v12, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v13, 0, v13, s3
	v_fma_f64 v[7:8], v[12:13], v[7:8], v[12:13]
	v_cmp_class_f64_e64 vcc_lo, v[12:13], 0x204
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v8, v8, v13 :: v_dual_cndmask_b32 v7, v7, v12
	v_cmp_class_f64_e64 vcc_lo, v[10:11], 0x204
	v_and_b32_e32 v8, 0x7fffffff, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_cndmask_b32 v8, v8, v32 :: v_dual_cndmask_b32 v7, v7, v33
	v_mul_f64 v[7:8], v[7:8], s[70:71]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f32_f64_e32 v7, v[7:8]
	v_frexp_mant_f32_e32 v12, v7
	v_cmp_eq_f32_e64 s5, 1.0, v7
	v_div_scale_f32 v8, null, v7, v7, 1.0
	v_frexp_exp_i32_f32_e32 v13, v7
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cmp_gt_f32_e64 s7, 0x3f2aaaab, v12
	v_cndmask_b32_e64 v11, 0xbeaaaaab, 1.0, s5
	v_cmp_gt_f32_e64 s6, 0x800000, v7
	v_rcp_f32_e32 v16, v8
	v_cndmask_b32_e64 v20, 0x3eaaaaab, 1.0, s5
	v_cndmask_b32_e64 v17, 0, 1, s7
	v_mul_f32_e32 v19, 0.5, v11
	v_cndmask_b32_e64 v21, 0x3fd55555, 1.0, s5
	v_cndmask_b32_e64 v15, 1.0, 0x4f800000, s6
	v_subrev_co_ci_u32_e64 v13, s5, 0, v13, s7
	v_ldexp_f32 v12, v12, v17
	v_cmp_eq_f32_e64 s4, 0, v7
	s_delay_alu instid0(VALU_DEP_4)
	v_mul_f32_e32 v15, v7, v15
	v_trunc_f32_e32 v18, v11
	v_cmp_gt_f32_e64 s8, 0, v11
	v_trunc_f32_e32 v17, v19
	v_mul_f32_e32 v24, 0.5, v20
	v_dual_mul_f32 v26, 0.5, v21 :: v_dual_add_f32 v29, 1.0, v12
	v_trunc_f32_e32 v23, v20
	v_fma_f32 v27, -v8, v16, 1.0
	v_cvt_f32_i32_e32 v13, v13
	v_cndmask_b32_e64 v22, 0, 0x41b17218, s6
	v_cmp_eq_f32_e64 s5, v18, v11
	s_xor_b32 s6, s4, s8
	v_trunc_f32_e32 v25, v21
	v_cmp_neq_f32_e64 s8, v17, v19
	v_trunc_f32_e32 v17, v24
	v_trunc_f32_e32 v19, v26
	v_div_scale_f32 v10, vcc_lo, 1.0, v7, 1.0
	v_cndmask_b32_e64 v18, 0x7f800000, 0, s6
	v_log_f32_e32 v15, v15
	v_cmp_eq_f32_e64 s6, v23, v20
	v_dual_fmac_f32 v16, v27, v16 :: v_dual_add_f32 v23, -1.0, v29
	v_mul_f32_e32 v27, 0x3f317218, v13
	v_cmp_eq_f32_e64 s7, v25, v21
	s_and_b32 s8, s5, s8
	v_cmp_neq_f32_e64 s9, v17, v24
	v_mul_f32_e32 v24, v10, v16
	v_cmp_neq_f32_e64 s10, v19, v26
	v_add_f32_e32 v28, -1.0, v12
	v_rcp_f32_e32 v25, v29
	v_cndmask_b32_e64 v19, 0, v7, s8
	v_sub_f32_e32 v12, v12, v23
	v_fma_f32 v23, 0x3f317218, v13, -v27
	v_cndmask_b32_e64 v30, 1.0, v7, s8
	s_and_b32 s8, s6, s9
	s_and_b32 s9, s7, s10
	v_cndmask_b32_e64 v14, 0x7f800000, 0, s4
	v_fmac_f32_e32 v23, 0xb102e308, v13
	v_bfi_b32 v18, 0x7fffffff, v18, v19
	v_cndmask_b32_e64 v19, 0, v7, s8
	v_cndmask_b32_e64 v33, 0, v7, s9
	v_fma_f32 v34, -v8, v24, v10
	v_mul_f32_e32 v17, 0x3f317217, v15
	v_cndmask_b32_e64 v26, 1.0, v7, s8
	v_bfi_b32 v13, 0x7fffffff, v14, v19
	v_bfi_b32 v14, 0x7fffffff, v14, v33
	v_fmac_f32_e32 v24, v34, v16
	v_fma_f32 v32, 0x3f317217, v15, -v17
	v_mul_f32_e32 v35, v28, v25
	v_add_f32_e32 v33, v27, v23
	v_cmp_gt_f32_e64 s8, 0x7f800000, |v15|
	v_fma_f32 v8, -v8, v24, v10
	v_fmac_f32_e32 v32, 0x3377d1cf, v15
	v_cndmask_b32_e64 v31, 1.0, v7, s9
	v_sub_f32_e32 v10, v33, v27
	v_mul_f32_e32 v19, v29, v35
	v_div_fmas_f32 v8, v8, v16, v24
	v_add_f32_e32 v17, v17, v32
	v_cmp_eq_f32_e64 s3, 0x7f800000, v7
	v_sub_f32_e32 v10, v23, v10
	v_fma_f32 v29, v35, v29, -v19
	v_div_fixup_f32 v8, v8, v7, 1.0
	v_cndmask_b32_e64 v15, v15, v17, s8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v29, v35, v12
	v_sub_f32_e32 v12, v15, v22
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v15, v19, v29
	v_sub_f32_e32 v17, v15, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v16, v28, v15 :: v_dual_sub_f32 v17, v17, v29
	v_sub_f32_e32 v19, v28, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v15, v19, v15
	v_add_f32_e32 v15, v17, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v15, v16, v15
	v_mul_f32_e32 v15, v25, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v16, v35, v15
	v_sub_f32_e32 v17, v16, v35
	v_ldexp_f32 v22, v16, 1
	v_mul_f32_e32 v19, v16, v16
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v15, v15, v17
	v_fma_f32 v17, v16, v16, -v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f32_e32 v23, v15, v15
	v_ldexp_f32 v24, v15, 1
	v_fmac_f32_e32 v17, v16, v23
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v23, v19, v17
	v_fmaak_f32 v25, s79, v23, 0x3e91f4c4
	v_sub_f32_e32 v19, v23, v19
	v_mul_f32_e32 v27, v16, v23
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmaak_f32 v25, v23, v25, 0x3ecccdef
	v_sub_f32_e32 v17, v17, v19
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v19, v23, v16, -v27
	v_mul_f32_e32 v28, v23, v25
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v19, v23, v15
	v_fma_f32 v15, v23, v25, -v28
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v19, v17, v16
	v_dual_fmac_f32 v15, v17, v25 :: v_dual_add_f32 v16, v27, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v17, v28, v15
	v_sub_f32_e32 v23, v16, v27
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v25, v17, v28
	v_add_f32_e32 v27, 0x3f2aaaaa, v17
	v_sub_f32_e32 v19, v19, v23
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v15, v15, v25
	v_add_f32_e32 v23, 0xbf2aaaaa, v27
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v15, 0x31739010, v15
	v_sub_f32_e32 v17, v17, v23
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v15, v15, v17
	v_add_f32_e32 v17, v27, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v23, v27, v17
	v_mul_f32_e32 v25, v16, v17
	v_add_f32_e32 v15, v15, v23
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v23, v16, v17, -v25
	v_fmac_f32_e32 v23, v16, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v23, v19, v17
	v_add_f32_e32 v15, v25, v23
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v16, v22, v15 :: v_dual_sub_f32 v17, v15, v25
	v_sub_f32_e32 v19, v16, v22
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v17, v23, v17
	v_sub_f32_e32 v15, v15, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v17, v24, v17
	v_add_f32_e32 v15, v17, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v17, v16, v15
	v_sub_f32_e32 v16, v17, v16
	v_add_f32_e32 v19, v33, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v15, v15, v16
	v_dual_sub_f32 v22, v19, v33 :: v_dual_add_f32 v23, v10, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v16, v19, v22
	v_sub_f32_e32 v17, v17, v22
	v_sub_f32_e32 v22, v23, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v16, v33, v16 :: v_dual_sub_f32 v15, v15, v22
	v_dual_add_f32 v16, v17, v16 :: v_dual_sub_f32 v17, v23, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v16, v23, v16
	v_dual_sub_f32 v10, v10, v17 :: v_dual_add_f32 v17, v19, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v10, v15, v10 :: v_dual_sub_f32 v15, v17, v19
	v_sub_f32_e32 v15, v16, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v10, v10, v15
	v_add_f32_e32 v15, v17, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v16, v15, v17
	v_mul_f32_e32 v17, v11, v15
	v_mul_f32_e32 v19, v20, v15
	v_mul_f32_e32 v22, v21, v15
	v_sub_f32_e32 v10, v10, v16
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f32 v16, v11, v15, -v17
	v_fma_f32 v23, v20, v15, -v19
	s_delay_alu instid0(VALU_DEP_4)
	v_fma_f32 v15, v21, v15, -v22
	v_cmp_class_f32_e64 vcc_lo, v19, 0x204
	v_cmp_class_f32_e64 s8, v22, 0x204
	v_fmac_f32_e32 v16, v11, v10
	v_fmac_f32_e32 v23, v20, v10
	v_fmac_f32_e32 v15, v21, v10
	v_cmp_class_f32_e64 s9, v17, 0x204
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_add_f32 v10, v17, v16 :: v_dual_add_f32 v11, v19, v23
	v_add_f32_e32 v20, v22, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v21, v10, v17
	v_cndmask_b32_e64 v10, v10, v17, s9
	s_delay_alu instid0(VALU_DEP_4)
	v_sub_f32_e32 v17, v11, v19
	v_cndmask_b32_e32 v11, v11, v19, vcc_lo
	v_sub_f32_e32 v19, v20, v22
	v_cndmask_b32_e64 v20, v20, v22, s8
	v_cmp_eq_f32_e32 vcc_lo, 0x42b17218, v10
	v_sub_f32_e32 v16, v16, v21
	v_cmp_eq_f32_e64 s8, 0x42b17218, v11
	v_sub_f32_e32 v17, v23, v17
	v_cmp_eq_f32_e64 s9, 0x42b17218, v20
	v_cndmask_b32_e64 v21, 0, 0x37000000, vcc_lo
	v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v11|
	v_cndmask_b32_e64 v22, 0, 0x37000000, s8
	v_sub_f32_e32 v15, v15, v19
	v_cndmask_b32_e64 v19, 0, 0x37000000, s9
	v_cmp_neq_f32_e64 s9, 0x7f800000, |v10|
	v_cmp_neq_f32_e64 s8, 0x7f800000, |v20|
	v_sub_f32_e32 v10, v10, v21
	v_cndmask_b32_e32 v17, 0, v17, vcc_lo
	v_sub_f32_e32 v11, v11, v22
	v_cndmask_b32_e64 v16, 0, v16, s9
	v_cndmask_b32_e64 v15, 0, v15, s8
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_sub_f32 v20, v20, v19 :: v_dual_add_f32 v17, v22, v17
	v_mul_f32_e32 v22, 0x3fb8aa3b, v11
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_add_f32 v16, v21, v16 :: v_dual_mul_f32 v21, 0x3fb8aa3b, v10
	v_add_f32_e32 v15, v19, v15
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mul_f32_e32 v19, 0x3fb8aa3b, v20
	v_fma_f32 v25, 0x3fb8aa3b, v11, -v22
	v_rndne_f32_e32 v27, v22
	v_fma_f32 v23, 0x3fb8aa3b, v10, -v21
	v_rndne_f32_e32 v24, v21
	v_fma_f32 v28, 0x3fb8aa3b, v20, -v19
	v_rndne_f32_e32 v29, v19
	v_fmac_f32_e32 v25, 0x32a5705f, v11
	v_fmac_f32_e32 v23, 0x32a5705f, v10
	v_dual_sub_f32 v21, v21, v24 :: v_dual_sub_f32 v22, v22, v27
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_fmac_f32 v28, 0x32a5705f, v20 :: v_dual_sub_f32 v19, v19, v29
	v_cvt_i32_f32_e32 v24, v24
	v_dual_add_f32 v21, v21, v23 :: v_dual_add_f32 v22, v22, v25
	v_cvt_i32_f32_e32 v27, v27
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f32_e32 v19, v19, v28
	v_cvt_i32_f32_e32 v23, v29
	v_exp_f32_e32 v21, v21
	v_exp_f32_e32 v22, v22
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v11
	v_exp_f32_e32 v19, v19
	v_cmp_ngt_f32_e64 s9, 0xc2ce8ed0, v10
	v_cmp_ngt_f32_e64 s8, 0xc2ce8ed0, v20
	s_delay_alu instid0(TRANS32_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3)
	v_ldexp_f32 v21, v21, v24
	s_waitcnt_depctr 0xfff
	v_ldexp_f32 v22, v22, v27
	v_ldexp_f32 v19, v19, v23
	v_cndmask_b32_e64 v21, 0, v21, s9
	v_cndmask_b32_e32 v22, 0, v22, vcc_lo
	v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v11
	v_cmp_nlt_f32_e64 s9, 0x42b17218, v10
	v_cndmask_b32_e64 v11, 0, v19, s8
	v_cmp_nlt_f32_e64 s8, 0x42b17218, v20
	v_cndmask_b32_e32 v19, 0x7f800000, v22, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v10, 0x7f800000, v21, s9
	v_cndmask_b32_e64 v11, 0x7f800000, v11, s8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v17, v19, v17, v19
	v_fma_f32 v16, v10, v16, v10
	v_cmp_eq_f32_e32 vcc_lo, 0x7f800000, v19
	v_cmp_eq_f32_e64 s9, 0x7f800000, v10
	v_fma_f32 v15, v11, v15, v11
	v_cmp_eq_f32_e64 s8, 0x7f800000, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v10, v16, v10, s9
	v_cndmask_b32_e32 v16, v17, v19, vcc_lo
	v_cndmask_b32_e64 v11, v15, v11, s8
	v_cmp_gt_f32_e32 vcc_lo, 0, v7
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_bfi_b32 v10, 0x7fffffff, v10, v30
	v_bfi_b32 v15, 0x7fffffff, v16, v26
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_bfi_b32 v11, 0x7fffffff, v11, v31
	v_cndmask_b32_e64 v16, 0x7fc00000, v10, s5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v17, 0x7fc00000, v15, s6
	v_cndmask_b32_e64 v19, 0x7fc00000, v11, s7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v10, v10, v16 :: v_dual_cndmask_b32 v15, v15, v17
	v_cndmask_b32_e32 v11, v11, v19, vcc_lo
	s_or_b32 vcc_lo, s4, s3
	v_cmp_u_f32_e64 s3, v7, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v10, v10, v18 :: v_dual_cndmask_b32 v13, v15, v13
	v_cndmask_b32_e32 v11, v11, v14, vcc_lo
	s_or_b32 s17, s2, s17
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v10, v10, 0x7fc00000, s3
	v_cndmask_b32_e64 v13, v13, 0x7fc00000, s3
	s_delay_alu instid0(VALU_DEP_3)
	v_cndmask_b32_e64 v11, v11, 0x7fc00000, s3
	ds_store_2addr_b32 v0, v12, v6 offset0:60 offset1:70
	ds_store_2addr_b32 v0, v9, v8 offset1:10
	ds_store_2addr_b32 v0, v10, v13 offset0:20 offset1:30
	ds_store_2addr_b32 v0, v7, v11 offset0:40 offset1:50
	v_add_nc_u32_e32 v0, s78, v0
	s_and_not1_b32 exec_lo, exec_lo, s17
	s_cbranch_execnz .LBB0_4
.LBB0_5:                                ; %Flow58
	s_or_b32 exec_lo, exec_lo, s76
	s_cmp_lt_u32 s13, s16
	s_waitcnt lgkmcnt(0)
	s_cselect_b32 s2, 12, 18
	s_barrier
	v_mov_b32_e32 v0, s2
	buffer_gl0_inv
	s_mov_b32 s2, exec_lo
	global_load_u16 v0, v0, s[20:21]
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[5:6], null, s13, v0, v[4:5]
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e32 13, v5
	s_cbranch_execz .LBB0_16
; %bb.6:                                ; %.preheader39.lr.ph.i
	s_load_b64 s[2:3], s[0:1], 0x0
	v_mul_lo_u32 v8, s16, v0
	v_cmp_gt_i32_e32 vcc_lo, 10, v1
	v_cmp_gt_i32_e64 s0, 7, v2
	s_mov_b32 s4, 0
.LBB0_7:                                ; %.preheader39.i
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_9 Depth 2
                                        ;       Child Loop BB0_11 Depth 3
                                        ;         Child Loop BB0_12 Depth 4
	s_and_saveexec_b32 s5, vcc_lo
	s_cbranch_execz .LBB0_15
; %bb.8:                                ; %.preheader.lr.ph.i
                                        ;   in Loop: Header=BB0_7 Depth=1
	v_mul_lo_u32 v9, v5, 10
	v_mul_lo_u32 v10, v5, 28
	v_mov_b32_e32 v11, v1
	s_mov_b32 s6, 0
.LBB0_9:                                ; %.preheader.i
                                        ;   Parent Loop BB0_7 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB0_11 Depth 3
                                        ;         Child Loop BB0_12 Depth 4
	s_and_saveexec_b32 s7, s0
	s_cbranch_execz .LBB0_14
; %bb.10:                               ; %.lr.ph.i
                                        ;   in Loop: Header=BB0_9 Depth=2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_dual_mov_b32 v12, v2 :: v_dual_add_nc_u32 v3, v11, v9
	v_lshl_add_u32 v0, v11, 2, 0x170
	s_mov_b32 s8, 0
	v_ashrrev_i32_e32 v4, 31, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v3, s1, s2, v3
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v4, s1, s3, v4, s1
.LBB0_11:                               ;   Parent Loop BB0_7 Depth=1
                                        ;     Parent Loop BB0_9 Depth=2
                                        ; =>    This Loop Header: Depth=3
                                        ;         Child Loop BB0_12 Depth 4
	global_load_b32 v7, v[3:4], off
	v_mad_u64_u32 v[13:14], null, v12, 40, v[0:1]
	v_lshl_add_u32 v6, v12, 2, v10
	s_mov_b32 s9, 0
	ds_load_b32 v6, v6
	ds_load_b32 v13, v13
	s_waitcnt lgkmcnt(0)
	v_mul_f32_e32 v13, v6, v13
.LBB0_12:                               ; %atomicrmw.start
                                        ;   Parent Loop BB0_7 Depth=1
                                        ;     Parent Loop BB0_9 Depth=2
                                        ;       Parent Loop BB0_11 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
	v_add_f32_e32 v6, v7, v13
	global_atomic_cmpswap_b32 v6, v[3:4], v[6:7], off glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u32_e64 s1, v6, v7
	v_mov_b32_e32 v7, v6
	s_or_b32 s9, s1, s9
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s9
	s_cbranch_execnz .LBB0_12
; %bb.13:                               ; %atomicrmw.end
                                        ;   in Loop: Header=BB0_11 Depth=3
	s_or_b32 exec_lo, exec_lo, s9
	v_add_nc_u32_e32 v12, s33, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_i32_e64 s1, 6, v12
	s_or_b32 s8, s1, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s8
	s_cbranch_execnz .LBB0_11
.LBB0_14:                               ; %Flow52
                                        ;   in Loop: Header=BB0_9 Depth=2
	s_or_b32 exec_lo, exec_lo, s7
	v_add_nc_u32_e32 v11, s12, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_i32_e64 s1, 9, v11
	s_or_b32 s6, s1, s6
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s6
	s_cbranch_execnz .LBB0_9
.LBB0_15:                               ; %Flow54
                                        ;   in Loop: Header=BB0_7 Depth=1
	s_or_b32 exec_lo, exec_lo, s5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v5, v5, v8
	v_cmp_lt_i32_e64 s1, 12, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s4, s1, s4
	s_and_not1_b32 exec_lo, exec_lo, s4
	s_cbranch_execnz .LBB0_7
.LBB0_16:                               ; %_Z5ratesIfEvPT_S1_S1_iii.exit
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z4execIfLi13ELi10ELi7EEvPT_
		.amdhsa_group_segment_fixed_size 648
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 264
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 36
		.amdhsa_next_free_sgpr 80
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z4execIfLi13ELi10ELi7EEvPT_,"axG",@progbits,_Z4execIfLi13ELi10ELi7EEvPT_,comdat
.Lfunc_end0:
	.size	_Z4execIfLi13ELi10ELi7EEvPT_, .Lfunc_end0-_Z4execIfLi13ELi10ELi7EEvPT_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 5500
; NumSgprs: 82
; NumVgprs: 36
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 648 bytes/workgroup (compile time only)
; SGPRBlocks: 10
; VGPRBlocks: 4
; NumSGPRsForWavesPerEU: 82
; NumVGPRsForWavesPerEU: 36
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         12
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         16
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         20
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         22
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         24
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         26
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         28
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         30
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         48
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         56
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         72
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 648
    .kernarg_segment_align: 8
    .kernarg_segment_size: 264
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z4execIfLi13ELi10ELi7EEvPT_
    .private_segment_fixed_size: 0
    .sgpr_count:     82
    .sgpr_spill_count: 0
    .symbol:         _Z4execIfLi13ELi10ELi7EEvPT_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     36
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
