#include "cufft.h"
#ifndef pi
#define pi 4.0f*atanf(1.0f)
#endif
#ifndef threads_num
#define threads_num 256
#endif

static __global__ void DataTypeConvertFloatToComplex_1d(float *d_in, cufftComplex *d_out, int n);
static __global__ void DataGetBackFft_1d(cufftComplex *d_in, float *d_out, float dx, int n);
static __global__ void PhaseShiftForwFft_1d(cufftComplex *d_in, cufftComplex *d_out, int n);
static __global__ void PhaseShiftBackFft_1d(cufftComplex *d_in, cufftComplex *d_out, int n);

void cufft_fftf_1d(float *d_in, float *d_out, float dx, int n)
{
	/* Data conversion from float to Complex */
	cufftComplex *d_in_data;
	cudaMalloc((void **)&d_in_data, n*sizeof(cufftComplex));
	DataTypeConvertFloatToComplex_1d<<<(n+threads_num-1)/threads_num, threads_num>>>(d_in, d_in_data, n);

	/* Create a 1D forward/inverse FFT plan */
	cufftHandle plan;
	cufftPlan1d(&plan, n, CUFFT_C2C, 1);

	/* Use the CUFFT plan to transform the array */
	cufftComplex *d_tmp_data;
	cudaMalloc((void **)&d_tmp_data, n*sizeof(cufftComplex));
	cufftExecC2C(plan, d_in_data, d_tmp_data, CUFFT_FORWARD);

	/* 1/2 phase shift for staggered grid */
	cufftComplex *d_tmp_data_shift;
	cudaMalloc((void **)&d_tmp_data_shift, n*sizeof(cufftComplex));
	PhaseShiftForwFft_1d<<<(n+threads_num-1)/threads_num, threads_num>>>(d_tmp_data, d_tmp_data_shift, n);

	/* Inverse fourier transform */
	cufftComplex *d_out_data;
	cudaMalloc((void **)&d_out_data, n*sizeof(cufftComplex));
	cufftExecC2C(plan, d_tmp_data_shift, d_out_data, CUFFT_INVERSE);

	/* Data normalization*/
	DataGetBackFft_1d<<<(n+threads_num-1)/threads_num, threads_num>>>(d_out_data, d_out, dx, n);

	cufftDestroy(plan);
	cudaFree(d_in_data);
	cudaFree(d_tmp_data);
	cudaFree(d_tmp_data_shift);
	cudaFree(d_out_data);
}

void cufft_fftb_1d(float *d_in, float *d_out, float dx, int n)
{
	/* Data conversion from float to Complex */
	cufftComplex *d_in_data;
	cudaMalloc((void **)&d_in_data, n*sizeof(cufftComplex));
	DataTypeConvertFloatToComplex_1d<<<(n+threads_num-1)/threads_num, threads_num>>>(d_in, d_in_data, n);

	/* Create a 1D forward/inverse FFT plan */
	cufftHandle plan;
	cufftPlan1d(&plan, n, CUFFT_C2C, 1);

	/* Use the CUFFT plan to transform the array */
	cufftComplex *d_tmp_data;
	cudaMalloc((void **)&d_tmp_data, n*sizeof(cufftComplex));
	cufftExecC2C(plan, d_in_data, d_tmp_data, CUFFT_FORWARD);

	/* -1/2 phase shift for staggered grid */
	cufftComplex *d_tmp_data_shift;
	cudaMalloc((void **)&d_tmp_data_shift, n*sizeof(cufftComplex));
	PhaseShiftBackFft_1d<<<(n+threads_num-1)/threads_num, threads_num>>>(d_tmp_data, d_tmp_data_shift, n);

	/* Inverse fourier transform */
	cufftComplex *d_out_data;
	cudaMalloc((void **)&d_out_data, n*sizeof(cufftComplex));
	cufftExecC2C(plan, d_tmp_data_shift, d_out_data, CUFFT_INVERSE);

	/* Data normalization*/
	DataGetBackFft_1d<<<(n+threads_num-1)/threads_num, threads_num>>>(d_out_data, d_out, dx, n);

	cufftDestroy(plan);
	cudaFree(d_in_data);
	cudaFree(d_tmp_data);
	cudaFree(d_tmp_data_shift);
	cudaFree(d_out_data);
}

static __global__ void DataTypeConvertFloatToComplex_1d(float *d_in, cufftComplex *d_out, int n)
{
	//int tid = threadIdx.x;
	int ix = blockIdx.x * blockDim.x + threadIdx.x;

	//for (int ix=tid; ix<n; ix+=threads_num)
	if (ix < n)
	{
		d_out[ix].x = d_in[ix];
		d_out[ix].y = 0.0f;
	}
}

static __global__ void DataGetBackFft_1d(cufftComplex *d_in, float *d_out, float dx, int n)
{
	//int tid = threadIdx.x;
	int ix = blockIdx.x * blockDim.x + threadIdx.x;

	//for (int ix=tid; ix<n; ix+=threads_num)
	if (ix < n)
		d_out[ix] = d_in[ix].x/((float)n*dx);
}

static __global__ void PhaseShiftForwFft_1d(cufftComplex *d_in, cufftComplex *d_out, int n)
{
	//int tid = threadIdx.x;
	int ix = blockIdx.x * blockDim.x + threadIdx.x;
	float d_k;

	//for (int ix=tid; ix<n; ix+=threads_num)
	if (ix < n)
	{
		if (ix<n/2)
			d_k = (float)ix*pi/(float)(n/2);
		else
			d_k = -pi+(float)(ix-n/2)*pi/(float)(n/2);
		
		d_out[ix].y = d_k*(d_in[ix].x*cosf(d_k/2.0f)+d_in[ix].y*sinf(d_k/2.0f));
		d_out[ix].x = d_k*(-d_in[ix].x*sinf(d_k/2.0f)+d_in[ix].y*cosf(d_k/2.0f));
	}
}

static __global__ void PhaseShiftBackFft_1d(cufftComplex *d_in, cufftComplex *d_out, int n)
{
	//int tid = threadIdx.x;
	int ix = blockIdx.x * blockDim.x + threadIdx.x;
	float d_k;

	//for (int ix=tid; ix<n; ix+=threads_num)
	if (ix < n)
	{
		if (ix<n/2)
			d_k = (float)ix*pi/(float)(n/2);
		else
			d_k = -pi+(float)(ix-n/2)*pi/(float)(n/2);
		
		d_out[ix].y = d_k*(d_in[ix].x*cosf(d_k/2.0f)-d_in[ix].y*sinf(d_k/2.0f));
		d_out[ix].x = d_k*(d_in[ix].x*sinf(d_k/2.0f)+d_in[ix].y*cosf(d_k/2.0f));
	}
}

void data_fft_derv(float *h_in, float *h_out, float dx, int n)
{
	float *d_in;
	cudaMalloc((void **)&d_in, n*sizeof(float));
	cudaMemcpy(d_in, h_in, n*sizeof(float), cudaMemcpyHostToDevice);
	
	float *d_out;
	cudaMalloc((void **)&d_out, n*sizeof(float));
	
	cufft_fftb_1d(d_in, d_out, dx, n);

	cudaMemcpy(h_out, d_out, n*sizeof(float), cudaMemcpyDeviceToHost);

	cudaFree(d_in);
	cudaFree(d_out);
}

	.file	"tmpxft_0031972f_00000000-6_cufft_fft_1d.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2036:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2036:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.type	_ZL50__device_stub__Z20PhaseShiftBackFft_1dP6float2S0_iP6float2S0_i, @function
_ZL50__device_stub__Z20PhaseShiftBackFft_1dP6float2S0_iP6float2S0_i:
.LFB2064:
	.cfi_startproc
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_ZL20PhaseShiftBackFft_1dP6float2S0_i(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L2:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2064:
	.size	_ZL50__device_stub__Z20PhaseShiftBackFft_1dP6float2S0_iP6float2S0_i, .-_ZL50__device_stub__Z20PhaseShiftBackFft_1dP6float2S0_iP6float2S0_i
	.type	_ZL20PhaseShiftBackFft_1dP6float2S0_i, @function
_ZL20PhaseShiftBackFft_1dP6float2S0_i:
.LFB2065:
	.cfi_startproc
	endbr64
	jmp	_ZL50__device_stub__Z20PhaseShiftBackFft_1dP6float2S0_iP6float2S0_i
	.cfi_endproc
.LFE2065:
	.size	_ZL20PhaseShiftBackFft_1dP6float2S0_i, .-_ZL20PhaseShiftBackFft_1dP6float2S0_i
	.type	_ZL61__device_stub__Z32DataTypeConvertFloatToComplex_1dPfP6float2iPfP6float2i, @function
_ZL61__device_stub__Z32DataTypeConvertFloatToComplex_1dPfP6float2iPfP6float2i:
.LFB2058:
	.cfi_startproc
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L8
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_ZL32DataTypeConvertFloatToComplex_1dPfP6float2i(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L8:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L10
	call	__stack_chk_fail@PLT
.L10:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2058:
	.size	_ZL61__device_stub__Z32DataTypeConvertFloatToComplex_1dPfP6float2iPfP6float2i, .-_ZL61__device_stub__Z32DataTypeConvertFloatToComplex_1dPfP6float2iPfP6float2i
	.type	_ZL32DataTypeConvertFloatToComplex_1dPfP6float2i, @function
_ZL32DataTypeConvertFloatToComplex_1dPfP6float2i:
.LFB2059:
	.cfi_startproc
	endbr64
	jmp	_ZL61__device_stub__Z32DataTypeConvertFloatToComplex_1dPfP6float2iPfP6float2i
	.cfi_endproc
.LFE2059:
	.size	_ZL32DataTypeConvertFloatToComplex_1dPfP6float2i, .-_ZL32DataTypeConvertFloatToComplex_1dPfP6float2i
	.type	_ZL50__device_stub__Z20PhaseShiftForwFft_1dP6float2S0_iP6float2S0_i, @function
_ZL50__device_stub__Z20PhaseShiftForwFft_1dP6float2S0_iP6float2S0_i:
.LFB2062:
	.cfi_startproc
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L13
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_ZL20PhaseShiftForwFft_1dP6float2S0_i(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L13:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L15
	call	__stack_chk_fail@PLT
.L15:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2062:
	.size	_ZL50__device_stub__Z20PhaseShiftForwFft_1dP6float2S0_iP6float2S0_i, .-_ZL50__device_stub__Z20PhaseShiftForwFft_1dP6float2S0_iP6float2S0_i
	.type	_ZL20PhaseShiftForwFft_1dP6float2S0_i, @function
_ZL20PhaseShiftForwFft_1dP6float2S0_i:
.LFB2063:
	.cfi_startproc
	endbr64
	jmp	_ZL50__device_stub__Z20PhaseShiftForwFft_1dP6float2S0_iP6float2S0_i
	.cfi_endproc
.LFE2063:
	.size	_ZL20PhaseShiftForwFft_1dP6float2S0_i, .-_ZL20PhaseShiftForwFft_1dP6float2S0_i
	.type	_ZL47__device_stub__Z17DataGetBackFft_1dP6float2PffiP6float2Pffi, @function
_ZL47__device_stub__Z17DataGetBackFft_1dP6float2PffiP6float2Pffi:
.LFB2060:
	.cfi_startproc
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movss	%xmm0, 12(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L18
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_ZL17DataGetBackFft_1dP6float2Pffi(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L18:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L20
	call	__stack_chk_fail@PLT
.L20:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2060:
	.size	_ZL47__device_stub__Z17DataGetBackFft_1dP6float2PffiP6float2Pffi, .-_ZL47__device_stub__Z17DataGetBackFft_1dP6float2PffiP6float2Pffi
	.type	_ZL17DataGetBackFft_1dP6float2Pffi, @function
_ZL17DataGetBackFft_1dP6float2Pffi:
.LFB2061:
	.cfi_startproc
	endbr64
	jmp	_ZL47__device_stub__Z17DataGetBackFft_1dP6float2PffiP6float2Pffi
	.cfi_endproc
.LFE2061:
	.size	_ZL17DataGetBackFft_1dP6float2Pffi, .-_ZL17DataGetBackFft_1dP6float2Pffi
	.globl	_Z13cufft_fftf_1dPfS_fi
	.type	_Z13cufft_fftf_1dPfS_fi, @function
_Z13cufft_fftf_1dPfS_fi:
.LFB2031:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movd	%xmm0, %r15d
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	movq	%rdi, %r14
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movq	%rsi, %r13
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movslq	%edx, %r12
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movq	%r12, %rbx
	salq	$3, %r12
	movq	%r12, %rsi
	subq	$88, %rsp
	.cfi_def_cfa_offset 144
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	xorl	%eax, %eax
	leaq	16(%rsp), %rdi
	call	cudaMalloc@PLT
	movl	$256, %esi
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	leal	255(%rbx), %eax
	movl	$16777217, %ecx
	movl	$1, 68(%rsp)
	cltd
	salq	$8, %rcx
	idivl	%esi
	movq	%rcx, 60(%rsp)
	movq	%rcx, %rdx
	movl	$1, %ecx
	movl	%eax, 48(%rsp)
	movl	%eax, %ebp
	movabsq	$4294967297, %rax
	movq	%rax, 52(%rsp)
	movq	48(%rsp), %rdi
	movl	56(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L24
	movq	16(%rsp), %rsi
	movl	%ebx, %edx
	movq	%r14, %rdi
	call	_ZL61__device_stub__Z32DataTypeConvertFloatToComplex_1dPfP6float2iPfP6float2i
.L24:
	movl	$1, %ecx
	movl	$41, %edx
	leaq	12(%rsp), %rdi
	movl	%ebx, %esi
	call	cufftPlan1d@PLT
	leaq	24(%rsp), %rdi
	movq	%r12, %rsi
	call	cudaMalloc@PLT
	movq	24(%rsp), %rdx
	movq	16(%rsp), %rsi
	orl	$-1, %ecx
	movl	12(%rsp), %edi
	call	cufftExecC2C@PLT
	leaq	32(%rsp), %rdi
	movq	%r12, %rsi
	call	cudaMalloc@PLT
	movl	%ebp, 48(%rsp)
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movabsq	$4294967297, %rax
	movl	$16777217, %edx
	movl	$1, %ecx
	movl	$1, 68(%rsp)
	movq	%rax, 52(%rsp)
	movq	48(%rsp), %rdi
	salq	$8, %rdx
	movl	56(%rsp), %esi
	movq	%rdx, 60(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L25
	movq	32(%rsp), %rsi
	movq	24(%rsp), %rdi
	movl	%ebx, %edx
	call	_ZL50__device_stub__Z20PhaseShiftForwFft_1dP6float2S0_iP6float2S0_i
.L25:
	leaq	40(%rsp), %rdi
	movq	%r12, %rsi
	call	cudaMalloc@PLT
	movq	40(%rsp), %rdx
	movq	32(%rsp), %rsi
	movl	$1, %ecx
	movl	12(%rsp), %edi
	call	cufftExecC2C@PLT
	movl	%ebp, 48(%rsp)
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movabsq	$4294967297, %rax
	movl	$16777217, %edx
	movl	$1, %ecx
	movl	$1, 68(%rsp)
	movq	%rax, 52(%rsp)
	movq	48(%rsp), %rdi
	salq	$8, %rdx
	movl	56(%rsp), %esi
	movq	%rdx, 60(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L26
	movq	40(%rsp), %rdi
	movl	%ebx, %edx
	movd	%r15d, %xmm0
	movq	%r13, %rsi
	call	_ZL47__device_stub__Z17DataGetBackFft_1dP6float2PffiP6float2Pffi
.L26:
	movl	12(%rsp), %edi
	call	cufftDestroy@PLT
	movq	16(%rsp), %rdi
	call	cudaFree@PLT
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	movq	32(%rsp), %rdi
	call	cudaFree@PLT
	movq	40(%rsp), %rdi
	call	cudaFree@PLT
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L27
	call	__stack_chk_fail@PLT
.L27:
	addq	$88, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2031:
	.size	_Z13cufft_fftf_1dPfS_fi, .-_Z13cufft_fftf_1dPfS_fi
	.globl	_Z13cufft_fftb_1dPfS_fi
	.type	_Z13cufft_fftb_1dPfS_fi, @function
_Z13cufft_fftb_1dPfS_fi:
.LFB2032:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movd	%xmm0, %r15d
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	movq	%rdi, %r14
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movq	%rsi, %r13
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movslq	%edx, %r12
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movq	%r12, %rbx
	salq	$3, %r12
	movq	%r12, %rsi
	subq	$88, %rsp
	.cfi_def_cfa_offset 144
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	xorl	%eax, %eax
	leaq	16(%rsp), %rdi
	call	cudaMalloc@PLT
	movl	$256, %esi
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	leal	255(%rbx), %eax
	movl	$16777217, %ecx
	movl	$1, 68(%rsp)
	cltd
	salq	$8, %rcx
	idivl	%esi
	movq	%rcx, 60(%rsp)
	movq	%rcx, %rdx
	movl	$1, %ecx
	movl	%eax, 48(%rsp)
	movl	%eax, %ebp
	movabsq	$4294967297, %rax
	movq	%rax, 52(%rsp)
	movq	48(%rsp), %rdi
	movl	56(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L30
	movq	16(%rsp), %rsi
	movl	%ebx, %edx
	movq	%r14, %rdi
	call	_ZL61__device_stub__Z32DataTypeConvertFloatToComplex_1dPfP6float2iPfP6float2i
.L30:
	movl	$1, %ecx
	movl	$41, %edx
	leaq	12(%rsp), %rdi
	movl	%ebx, %esi
	call	cufftPlan1d@PLT
	leaq	24(%rsp), %rdi
	movq	%r12, %rsi
	call	cudaMalloc@PLT
	movq	24(%rsp), %rdx
	movq	16(%rsp), %rsi
	orl	$-1, %ecx
	movl	12(%rsp), %edi
	call	cufftExecC2C@PLT
	leaq	32(%rsp), %rdi
	movq	%r12, %rsi
	call	cudaMalloc@PLT
	movl	%ebp, 48(%rsp)
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movabsq	$4294967297, %rax
	movl	$16777217, %edx
	movl	$1, %ecx
	movl	$1, 68(%rsp)
	movq	%rax, 52(%rsp)
	movq	48(%rsp), %rdi
	salq	$8, %rdx
	movl	56(%rsp), %esi
	movq	%rdx, 60(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L31
	movq	32(%rsp), %rsi
	movq	24(%rsp), %rdi
	movl	%ebx, %edx
	call	_ZL50__device_stub__Z20PhaseShiftBackFft_1dP6float2S0_iP6float2S0_i
.L31:
	leaq	40(%rsp), %rdi
	movq	%r12, %rsi
	call	cudaMalloc@PLT
	movq	40(%rsp), %rdx
	movq	32(%rsp), %rsi
	movl	$1, %ecx
	movl	12(%rsp), %edi
	call	cufftExecC2C@PLT
	movl	%ebp, 48(%rsp)
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movabsq	$4294967297, %rax
	movl	$16777217, %edx
	movl	$1, %ecx
	movl	$1, 68(%rsp)
	movq	%rax, 52(%rsp)
	movq	48(%rsp), %rdi
	salq	$8, %rdx
	movl	56(%rsp), %esi
	movq	%rdx, 60(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L32
	movq	40(%rsp), %rdi
	movl	%ebx, %edx
	movd	%r15d, %xmm0
	movq	%r13, %rsi
	call	_ZL47__device_stub__Z17DataGetBackFft_1dP6float2PffiP6float2Pffi
.L32:
	movl	12(%rsp), %edi
	call	cufftDestroy@PLT
	movq	16(%rsp), %rdi
	call	cudaFree@PLT
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	movq	32(%rsp), %rdi
	call	cudaFree@PLT
	movq	40(%rsp), %rdi
	call	cudaFree@PLT
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L33
	call	__stack_chk_fail@PLT
.L33:
	addq	$88, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2032:
	.size	_Z13cufft_fftb_1dPfS_fi, .-_Z13cufft_fftb_1dPfS_fi
	.globl	_Z13data_fft_dervPfS_fi
	.type	_Z13data_fft_dervPfS_fi, @function
_Z13data_fft_dervPfS_fi:
.LFB2033:
	.cfi_startproc
	endbr64
	pushq	%r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	movq	%rdi, %r13
	pushq	%r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	movq	%rsi, %r12
	pushq	%rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	movslq	%edx, %rbx
	movq	%rbx, %rbp
	salq	$2, %rbx
	movq	%rbx, %rsi
	subq	$56, %rsp
	.cfi_def_cfa_offset 96
	movss	%xmm0, 12(%rsp)
	leaq	24(%rsp), %rdi
	movq	%fs:40, %rax
	movq	%rax, 40(%rsp)
	xorl	%eax, %eax
	call	cudaMalloc@PLT
	movq	24(%rsp), %rdi
	movq	%rbx, %rdx
	movq	%r13, %rsi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	leaq	32(%rsp), %rdi
	movq	%rbx, %rsi
	call	cudaMalloc@PLT
	movss	12(%rsp), %xmm0
	movq	32(%rsp), %rsi
	movl	%ebp, %edx
	movq	24(%rsp), %rdi
	call	_Z13cufft_fftb_1dPfS_fi
	movq	32(%rsp), %rsi
	movq	%rbx, %rdx
	movq	%r12, %rdi
	movl	$2, %ecx
	call	cudaMemcpy@PLT
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	movq	32(%rsp), %rdi
	call	cudaFree@PLT
	movq	40(%rsp), %rax
	subq	%fs:40, %rax
	je	.L36
	call	__stack_chk_fail@PLT
.L36:
	addq	$56, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2033:
	.size	_Z13data_fft_dervPfS_fi, .-_Z13data_fft_dervPfS_fi
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z20PhaseShiftBackFft_1dP6float2S0_i"
.LC1:
	.string	"_Z20PhaseShiftForwFft_1dP6float2S0_i"
.LC2:
	.string	"_Z17DataGetBackFft_1dP6float2Pffi"
.LC3:
	.string	"_Z32DataTypeConvertFloatToComplex_1dPfP6float2i"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2067:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_ZL20PhaseShiftBackFft_1dP6float2S0_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC1(%rip), %rdx
	orl	$-1, %r8d
	leaq	_ZL20PhaseShiftForwFft_1dP6float2S0_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC2(%rip), %rdx
	orl	$-1, %r8d
	leaq	_ZL17DataGetBackFft_1dP6float2Pffi(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC3(%rip), %rdx
	orl	$-1, %r8d
	leaq	_ZL32DataTypeConvertFloatToComplex_1dPfP6float2i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2067:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include "hipfft/hipfft.h"
#ifndef pi
#define pi 4.0f*atanf(1.0f)
#endif
#ifndef threads_num
#define threads_num 256
#endif

static __global__ void DataTypeConvertFloatToComplex_1d(float *d_in, hipfftComplex *d_out, int n);
static __global__ void DataGetBackFft_1d(hipfftComplex *d_in, float *d_out, float dx, int n);
static __global__ void PhaseShiftForwFft_1d(hipfftComplex *d_in, hipfftComplex *d_out, int n);
static __global__ void PhaseShiftBackFft_1d(hipfftComplex *d_in, hipfftComplex *d_out, int n);

void cufft_fftf_1d(float *d_in, float *d_out, float dx, int n)
{
	/* Data conversion from float to Complex */
	hipfftComplex *d_in_data;
	hipMalloc((void **)&d_in_data, n*sizeof(hipfftComplex));
	DataTypeConvertFloatToComplex_1d<<<(n+threads_num-1)/threads_num, threads_num>>>(d_in, d_in_data, n);

	/* Create a 1D forward/inverse FFT plan */
	hipfftHandle plan;
	hipfftPlan1d(&plan, n, HIPFFT_C2C, 1);

	/* Use the CUFFT plan to transform the array */
	hipfftComplex *d_tmp_data;
	hipMalloc((void **)&d_tmp_data, n*sizeof(hipfftComplex));
	hipfftExecC2C(plan, d_in_data, d_tmp_data, HIPFFT_FORWARD);

	/* 1/2 phase shift for staggered grid */
	hipfftComplex *d_tmp_data_shift;
	hipMalloc((void **)&d_tmp_data_shift, n*sizeof(hipfftComplex));
	PhaseShiftForwFft_1d<<<(n+threads_num-1)/threads_num, threads_num>>>(d_tmp_data, d_tmp_data_shift, n);

	/* Inverse fourier transform */
	hipfftComplex *d_out_data;
	hipMalloc((void **)&d_out_data, n*sizeof(hipfftComplex));
	hipfftExecC2C(plan, d_tmp_data_shift, d_out_data, HIPFFT_BACKWARD);

	/* Data normalization*/
	DataGetBackFft_1d<<<(n+threads_num-1)/threads_num, threads_num>>>(d_out_data, d_out, dx, n);

	hipfftDestroy(plan);
	hipFree(d_in_data);
	hipFree(d_tmp_data);
	hipFree(d_tmp_data_shift);
	hipFree(d_out_data);
}

void cufft_fftb_1d(float *d_in, float *d_out, float dx, int n)
{
	/* Data conversion from float to Complex */
	hipfftComplex *d_in_data;
	hipMalloc((void **)&d_in_data, n*sizeof(hipfftComplex));
	DataTypeConvertFloatToComplex_1d<<<(n+threads_num-1)/threads_num, threads_num>>>(d_in, d_in_data, n);

	/* Create a 1D forward/inverse FFT plan */
	hipfftHandle plan;
	hipfftPlan1d(&plan, n, HIPFFT_C2C, 1);

	/* Use the CUFFT plan to transform the array */
	hipfftComplex *d_tmp_data;
	hipMalloc((void **)&d_tmp_data, n*sizeof(hipfftComplex));
	hipfftExecC2C(plan, d_in_data, d_tmp_data, HIPFFT_FORWARD);

	/* -1/2 phase shift for staggered grid */
	hipfftComplex *d_tmp_data_shift;
	hipMalloc((void **)&d_tmp_data_shift, n*sizeof(hipfftComplex));
	PhaseShiftBackFft_1d<<<(n+threads_num-1)/threads_num, threads_num>>>(d_tmp_data, d_tmp_data_shift, n);

	/* Inverse fourier transform */
	hipfftComplex *d_out_data;
	hipMalloc((void **)&d_out_data, n*sizeof(hipfftComplex));
	hipfftExecC2C(plan, d_tmp_data_shift, d_out_data, HIPFFT_BACKWARD);

	/* Data normalization*/
	DataGetBackFft_1d<<<(n+threads_num-1)/threads_num, threads_num>>>(d_out_data, d_out, dx, n);

	hipfftDestroy(plan);
	hipFree(d_in_data);
	hipFree(d_tmp_data);
	hipFree(d_tmp_data_shift);
	hipFree(d_out_data);
}

static __global__ void DataTypeConvertFloatToComplex_1d(float *d_in, hipfftComplex *d_out, int n)
{
	//int tid = threadIdx.x;
	int ix = blockIdx.x * blockDim.x + threadIdx.x;

	//for (int ix=tid; ix<n; ix+=threads_num)
	if (ix < n)
	{
		d_out[ix].x = d_in[ix];
		d_out[ix].y = 0.0f;
	}
}

static __global__ void DataGetBackFft_1d(hipfftComplex *d_in, float *d_out, float dx, int n)
{
	//int tid = threadIdx.x;
	int ix = blockIdx.x * blockDim.x + threadIdx.x;

	//for (int ix=tid; ix<n; ix+=threads_num)
	if (ix < n)
		d_out[ix] = d_in[ix].x/((float)n*dx);
}

static __global__ void PhaseShiftForwFft_1d(hipfftComplex *d_in, hipfftComplex *d_out, int n)
{
	//int tid = threadIdx.x;
	int ix = blockIdx.x * blockDim.x + threadIdx.x;
	float d_k;

	//for (int ix=tid; ix<n; ix+=threads_num)
	if (ix < n)
	{
		if (ix<n/2)
			d_k = (float)ix*pi/(float)(n/2);
		else
			d_k = -pi+(float)(ix-n/2)*pi/(float)(n/2);
		
		d_out[ix].y = d_k*(d_in[ix].x*cosf(d_k/2.0f)+d_in[ix].y*sinf(d_k/2.0f));
		d_out[ix].x = d_k*(-d_in[ix].x*sinf(d_k/2.0f)+d_in[ix].y*cosf(d_k/2.0f));
	}
}

static __global__ void PhaseShiftBackFft_1d(hipfftComplex *d_in, hipfftComplex *d_out, int n)
{
	//int tid = threadIdx.x;
	int ix = blockIdx.x * blockDim.x + threadIdx.x;
	float d_k;

	//for (int ix=tid; ix<n; ix+=threads_num)
	if (ix < n)
	{
		if (ix<n/2)
			d_k = (float)ix*pi/(float)(n/2);
		else
			d_k = -pi+(float)(ix-n/2)*pi/(float)(n/2);
		
		d_out[ix].y = d_k*(d_in[ix].x*cosf(d_k/2.0f)-d_in[ix].y*sinf(d_k/2.0f));
		d_out[ix].x = d_k*(d_in[ix].x*sinf(d_k/2.0f)+d_in[ix].y*cosf(d_k/2.0f));
	}
}

void data_fft_derv(float *h_in, float *h_out, float dx, int n)
{
	float *d_in;
	hipMalloc((void **)&d_in, n*sizeof(float));
	hipMemcpy(d_in, h_in, n*sizeof(float), hipMemcpyHostToDevice);
	
	float *d_out;
	hipMalloc((void **)&d_out, n*sizeof(float));
	
	cufft_fftb_1d(d_in, d_out, dx, n);

	hipMemcpy(h_out, d_out, n*sizeof(float), hipMemcpyDeviceToHost);

	hipFree(d_in);
	hipFree(d_out);
}

	.text
	.file	"cufft_fft_1d.hip"
	.globl	_Z13cufft_fftf_1dPfS_fi         # -- Begin function _Z13cufft_fftf_1dPfS_fi
	.type	_Z13cufft_fftf_1dPfS_fi,@function
_Z13cufft_fftf_1dPfS_fi:                # @_Z13cufft_fftf_1dPfS_fi
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$56, %rsp
	.cfi_def_cfa_offset 112
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%edx, %ebx
	movss	%xmm0, 20(%rsp)                 # 4-byte Spill
	movq	%rsi, 48(%rsp)                  # 8-byte Spill
	movq	%rdi, %rbp
	movabsq	$4294967552, %r15               # imm = 0x100000100
	movslq	%edx, %r14
	leaq	(,%r14,8), %r12
	leaq	8(%rsp), %rdi
	movq	%r12, %rsi
	callq	hipMalloc
	leal	255(%r14), %eax
	addl	$510, %r14d                     # imm = 0x1FE
	testl	%eax, %eax
	cmovnsl	%eax, %r14d
	sarl	$8, %r14d
	leaq	(%r14,%r15), %r13
	addq	$-256, %r13
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r15, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB0_2
# %bb.1:
	movq	8(%rsp), %rsi
	movq	%rbp, %rdi
	movl	%ebx, %edx
	callq	_ZL47__device_stub__DataTypeConvertFloatToComplex_1dPfP15HIP_vector_typeIfLj2EEi
.LBB0_2:
	leaq	40(%rsp), %rbp
	movq	%rbp, %rdi
	movl	%ebx, %esi
	movl	$41, %edx
	movl	$1, %ecx
	callq	hipfftPlan1d
	leaq	32(%rsp), %r14
	movq	%r14, %rdi
	movq	%r12, %rsi
	callq	hipMalloc
	movq	(%rbp), %rdi
	movq	8(%rsp), %rsi
	movq	(%r14), %rdx
	movl	$-1, %ecx
	callq	hipfftExecC2C
	movq	%rsp, %rdi
	movq	%r12, %rsi
	callq	hipMalloc
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r15, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB0_4
# %bb.3:
	movq	32(%rsp), %rdi
	movq	(%rsp), %rsi
	movl	%ebx, %edx
	callq	_ZL35__device_stub__PhaseShiftForwFft_1dP15HIP_vector_typeIfLj2EES1_i
.LBB0_4:
	leaq	24(%rsp), %r14
	movq	%r14, %rdi
	movq	%r12, %rsi
	callq	hipMalloc
	movq	40(%rsp), %rdi
	movq	(%rsp), %rsi
	movq	(%r14), %rdx
	movl	$1, %ecx
	callq	hipfftExecC2C
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r15, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB0_6
# %bb.5:
	movq	24(%rsp), %rdi
	movq	48(%rsp), %rsi                  # 8-byte Reload
	movss	20(%rsp), %xmm0                 # 4-byte Reload
                                        # xmm0 = mem[0],zero,zero,zero
	movl	%ebx, %edx
	callq	_ZL32__device_stub__DataGetBackFft_1dP15HIP_vector_typeIfLj2EEPffi
.LBB0_6:
	movq	40(%rsp), %rdi
	callq	hipfftDestroy
	movq	8(%rsp), %rdi
	callq	hipFree
	movq	32(%rsp), %rdi
	callq	hipFree
	movq	(%rsp), %rdi
	callq	hipFree
	movq	24(%rsp), %rdi
	callq	hipFree
	addq	$56, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z13cufft_fftf_1dPfS_fi, .Lfunc_end0-_Z13cufft_fftf_1dPfS_fi
	.cfi_endproc
                                        # -- End function
	.type	_ZL47__device_stub__DataTypeConvertFloatToComplex_1dPfP15HIP_vector_typeIfLj2EEi,@function # -- Begin function _ZL47__device_stub__DataTypeConvertFloatToComplex_1dPfP15HIP_vector_typeIfLj2EEi
_ZL47__device_stub__DataTypeConvertFloatToComplex_1dPfP15HIP_vector_typeIfLj2EEi: # @_ZL47__device_stub__DataTypeConvertFloatToComplex_1dPfP15HIP_vector_typeIfLj2EEi
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_ZL32DataTypeConvertFloatToComplex_1dPfP15HIP_vector_typeIfLj2EEi, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_ZL47__device_stub__DataTypeConvertFloatToComplex_1dPfP15HIP_vector_typeIfLj2EEi, .Lfunc_end1-_ZL47__device_stub__DataTypeConvertFloatToComplex_1dPfP15HIP_vector_typeIfLj2EEi
	.cfi_endproc
                                        # -- End function
	.type	_ZL35__device_stub__PhaseShiftForwFft_1dP15HIP_vector_typeIfLj2EES1_i,@function # -- Begin function _ZL35__device_stub__PhaseShiftForwFft_1dP15HIP_vector_typeIfLj2EES1_i
_ZL35__device_stub__PhaseShiftForwFft_1dP15HIP_vector_typeIfLj2EES1_i: # @_ZL35__device_stub__PhaseShiftForwFft_1dP15HIP_vector_typeIfLj2EES1_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_ZL20PhaseShiftForwFft_1dP15HIP_vector_typeIfLj2EES1_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_ZL35__device_stub__PhaseShiftForwFft_1dP15HIP_vector_typeIfLj2EES1_i, .Lfunc_end2-_ZL35__device_stub__PhaseShiftForwFft_1dP15HIP_vector_typeIfLj2EES1_i
	.cfi_endproc
                                        # -- End function
	.type	_ZL32__device_stub__DataGetBackFft_1dP15HIP_vector_typeIfLj2EEPffi,@function # -- Begin function _ZL32__device_stub__DataGetBackFft_1dP15HIP_vector_typeIfLj2EEPffi
_ZL32__device_stub__DataGetBackFft_1dP15HIP_vector_typeIfLj2EEPffi: # @_ZL32__device_stub__DataGetBackFft_1dP15HIP_vector_typeIfLj2EEPffi
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movss	%xmm0, (%rsi)
	leaq	8(%rsp), %rdi
	movl	%edx, (%rdi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdi, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_ZL17DataGetBackFft_1dP15HIP_vector_typeIfLj2EEPffi, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	_ZL32__device_stub__DataGetBackFft_1dP15HIP_vector_typeIfLj2EEPffi, .Lfunc_end3-_ZL32__device_stub__DataGetBackFft_1dP15HIP_vector_typeIfLj2EEPffi
	.cfi_endproc
                                        # -- End function
	.globl	_Z13cufft_fftb_1dPfS_fi         # -- Begin function _Z13cufft_fftb_1dPfS_fi
	.type	_Z13cufft_fftb_1dPfS_fi,@function
_Z13cufft_fftb_1dPfS_fi:                # @_Z13cufft_fftb_1dPfS_fi
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$56, %rsp
	.cfi_def_cfa_offset 112
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%edx, %ebx
	movss	%xmm0, 20(%rsp)                 # 4-byte Spill
	movq	%rsi, 48(%rsp)                  # 8-byte Spill
	movq	%rdi, %rbp
	movabsq	$4294967552, %r15               # imm = 0x100000100
	movslq	%edx, %r14
	leaq	(,%r14,8), %r12
	leaq	8(%rsp), %rdi
	movq	%r12, %rsi
	callq	hipMalloc
	leal	255(%r14), %eax
	addl	$510, %r14d                     # imm = 0x1FE
	testl	%eax, %eax
	cmovnsl	%eax, %r14d
	sarl	$8, %r14d
	leaq	(%r14,%r15), %r13
	addq	$-256, %r13
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r15, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB4_2
# %bb.1:
	movq	8(%rsp), %rsi
	movq	%rbp, %rdi
	movl	%ebx, %edx
	callq	_ZL47__device_stub__DataTypeConvertFloatToComplex_1dPfP15HIP_vector_typeIfLj2EEi
.LBB4_2:
	leaq	40(%rsp), %rbp
	movq	%rbp, %rdi
	movl	%ebx, %esi
	movl	$41, %edx
	movl	$1, %ecx
	callq	hipfftPlan1d
	leaq	32(%rsp), %r14
	movq	%r14, %rdi
	movq	%r12, %rsi
	callq	hipMalloc
	movq	(%rbp), %rdi
	movq	8(%rsp), %rsi
	movq	(%r14), %rdx
	movl	$-1, %ecx
	callq	hipfftExecC2C
	movq	%rsp, %rdi
	movq	%r12, %rsi
	callq	hipMalloc
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r15, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB4_4
# %bb.3:
	movq	32(%rsp), %rdi
	movq	(%rsp), %rsi
	movl	%ebx, %edx
	callq	_ZL35__device_stub__PhaseShiftBackFft_1dP15HIP_vector_typeIfLj2EES1_i
.LBB4_4:
	leaq	24(%rsp), %r14
	movq	%r14, %rdi
	movq	%r12, %rsi
	callq	hipMalloc
	movq	40(%rsp), %rdi
	movq	(%rsp), %rsi
	movq	(%r14), %rdx
	movl	$1, %ecx
	callq	hipfftExecC2C
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r15, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB4_6
# %bb.5:
	movq	24(%rsp), %rdi
	movq	48(%rsp), %rsi                  # 8-byte Reload
	movss	20(%rsp), %xmm0                 # 4-byte Reload
                                        # xmm0 = mem[0],zero,zero,zero
	movl	%ebx, %edx
	callq	_ZL32__device_stub__DataGetBackFft_1dP15HIP_vector_typeIfLj2EEPffi
.LBB4_6:
	movq	40(%rsp), %rdi
	callq	hipfftDestroy
	movq	8(%rsp), %rdi
	callq	hipFree
	movq	32(%rsp), %rdi
	callq	hipFree
	movq	(%rsp), %rdi
	callq	hipFree
	movq	24(%rsp), %rdi
	callq	hipFree
	addq	$56, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end4:
	.size	_Z13cufft_fftb_1dPfS_fi, .Lfunc_end4-_Z13cufft_fftb_1dPfS_fi
	.cfi_endproc
                                        # -- End function
	.type	_ZL35__device_stub__PhaseShiftBackFft_1dP15HIP_vector_typeIfLj2EES1_i,@function # -- Begin function _ZL35__device_stub__PhaseShiftBackFft_1dP15HIP_vector_typeIfLj2EES1_i
_ZL35__device_stub__PhaseShiftBackFft_1dP15HIP_vector_typeIfLj2EES1_i: # @_ZL35__device_stub__PhaseShiftBackFft_1dP15HIP_vector_typeIfLj2EES1_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_ZL20PhaseShiftBackFft_1dP15HIP_vector_typeIfLj2EES1_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end5:
	.size	_ZL35__device_stub__PhaseShiftBackFft_1dP15HIP_vector_typeIfLj2EES1_i, .Lfunc_end5-_ZL35__device_stub__PhaseShiftBackFft_1dP15HIP_vector_typeIfLj2EES1_i
	.cfi_endproc
                                        # -- End function
	.globl	_Z13data_fft_dervPfS_fi         # -- Begin function _Z13data_fft_dervPfS_fi
	.type	_Z13data_fft_dervPfS_fi,@function
_Z13data_fft_dervPfS_fi:                # @_Z13data_fft_dervPfS_fi
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$32, %rsp
	.cfi_def_cfa_offset 80
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movss	%xmm0, 12(%rsp)                 # 4-byte Spill
	movq	%rsi, %r14
	movq	%rdi, %r12
	movslq	%edx, %r13
	leaq	(,%r13,4), %r15
	leaq	24(%rsp), %rbx
	movq	%rbx, %rdi
	movq	%r15, %rsi
	callq	hipMalloc
	movq	(%rbx), %rdi
	movq	%r12, %rsi
	movq	%r15, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	16(%rsp), %r12
	movq	%r12, %rdi
	movq	%r15, %rsi
	callq	hipMalloc
	movq	(%rbx), %rdi
	movq	(%r12), %rsi
	movss	12(%rsp), %xmm0                 # 4-byte Reload
                                        # xmm0 = mem[0],zero,zero,zero
	movl	%r13d, %edx
	callq	_Z13cufft_fftb_1dPfS_fi
	movq	(%r12), %rsi
	movq	%r14, %rdi
	movq	%r15, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	movq	(%rbx), %rdi
	callq	hipFree
	movq	(%r12), %rdi
	callq	hipFree
	addq	$32, %rsp
	.cfi_def_cfa_offset 48
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end6:
	.size	_Z13data_fft_dervPfS_fi, .Lfunc_end6-_Z13data_fft_dervPfS_fi
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB7_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB7_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_ZL32DataTypeConvertFloatToComplex_1dPfP15HIP_vector_typeIfLj2EEi, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_ZL17DataGetBackFft_1dP15HIP_vector_typeIfLj2EEPffi, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_ZL20PhaseShiftForwFft_1dP15HIP_vector_typeIfLj2EES1_i, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_ZL20PhaseShiftBackFft_1dP15HIP_vector_typeIfLj2EES1_i, %esi
	movl	$.L__unnamed_4, %edx
	movl	$.L__unnamed_4, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end7:
	.size	__hip_module_ctor, .Lfunc_end7-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB8_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB8_2:
	retq
.Lfunc_end8:
	.size	__hip_module_dtor, .Lfunc_end8-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_ZL32DataTypeConvertFloatToComplex_1dPfP15HIP_vector_typeIfLj2EEi,@object # @_ZL32DataTypeConvertFloatToComplex_1dPfP15HIP_vector_typeIfLj2EEi
	.section	.rodata,"a",@progbits
	.p2align	3, 0x0
_ZL32DataTypeConvertFloatToComplex_1dPfP15HIP_vector_typeIfLj2EEi:
	.quad	_ZL47__device_stub__DataTypeConvertFloatToComplex_1dPfP15HIP_vector_typeIfLj2EEi
	.size	_ZL32DataTypeConvertFloatToComplex_1dPfP15HIP_vector_typeIfLj2EEi, 8

	.type	_ZL20PhaseShiftForwFft_1dP15HIP_vector_typeIfLj2EES1_i,@object # @_ZL20PhaseShiftForwFft_1dP15HIP_vector_typeIfLj2EES1_i
	.p2align	3, 0x0
_ZL20PhaseShiftForwFft_1dP15HIP_vector_typeIfLj2EES1_i:
	.quad	_ZL35__device_stub__PhaseShiftForwFft_1dP15HIP_vector_typeIfLj2EES1_i
	.size	_ZL20PhaseShiftForwFft_1dP15HIP_vector_typeIfLj2EES1_i, 8

	.type	_ZL17DataGetBackFft_1dP15HIP_vector_typeIfLj2EEPffi,@object # @_ZL17DataGetBackFft_1dP15HIP_vector_typeIfLj2EEPffi
	.p2align	3, 0x0
_ZL17DataGetBackFft_1dP15HIP_vector_typeIfLj2EEPffi:
	.quad	_ZL32__device_stub__DataGetBackFft_1dP15HIP_vector_typeIfLj2EEPffi
	.size	_ZL17DataGetBackFft_1dP15HIP_vector_typeIfLj2EEPffi, 8

	.type	_ZL20PhaseShiftBackFft_1dP15HIP_vector_typeIfLj2EES1_i,@object # @_ZL20PhaseShiftBackFft_1dP15HIP_vector_typeIfLj2EES1_i
	.p2align	3, 0x0
_ZL20PhaseShiftBackFft_1dP15HIP_vector_typeIfLj2EES1_i:
	.quad	_ZL35__device_stub__PhaseShiftBackFft_1dP15HIP_vector_typeIfLj2EES1_i
	.size	_ZL20PhaseShiftBackFft_1dP15HIP_vector_typeIfLj2EES1_i, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_ZL32DataTypeConvertFloatToComplex_1dPfP15HIP_vector_typeIfLj2EEi"
	.size	.L__unnamed_1, 66

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_ZL17DataGetBackFft_1dP15HIP_vector_typeIfLj2EEPffi"
	.size	.L__unnamed_2, 52

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_ZL20PhaseShiftForwFft_1dP15HIP_vector_typeIfLj2EES1_i"
	.size	.L__unnamed_3, 55

	.type	.L__unnamed_4,@object           # @3
.L__unnamed_4:
	.asciz	"_ZL20PhaseShiftBackFft_1dP15HIP_vector_typeIfLj2EES1_i"
	.size	.L__unnamed_4, 55

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _ZL47__device_stub__DataTypeConvertFloatToComplex_1dPfP15HIP_vector_typeIfLj2EEi
	.addrsig_sym _ZL35__device_stub__PhaseShiftForwFft_1dP15HIP_vector_typeIfLj2EES1_i
	.addrsig_sym _ZL32__device_stub__DataGetBackFft_1dP15HIP_vector_typeIfLj2EEPffi
	.addrsig_sym _ZL35__device_stub__PhaseShiftBackFft_1dP15HIP_vector_typeIfLj2EES1_i
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _ZL32DataTypeConvertFloatToComplex_1dPfP15HIP_vector_typeIfLj2EEi
	.addrsig_sym _ZL20PhaseShiftForwFft_1dP15HIP_vector_typeIfLj2EES1_i
	.addrsig_sym _ZL17DataGetBackFft_1dP15HIP_vector_typeIfLj2EEPffi
	.addrsig_sym _ZL20PhaseShiftBackFft_1dP15HIP_vector_typeIfLj2EES1_i
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.section	.text._ZL32DataTypeConvertFloatToComplex_1dPfP15HIP_vector_typeIfLj2EEi,"axG",@progbits,_ZL32DataTypeConvertFloatToComplex_1dPfP15HIP_vector_typeIfLj2EEi,comdat
	.globl	_ZL32DataTypeConvertFloatToComplex_1dPfP15HIP_vector_typeIfLj2EEi ; -- Begin function _ZL32DataTypeConvertFloatToComplex_1dPfP15HIP_vector_typeIfLj2EEi
	.p2align	8
	.type	_ZL32DataTypeConvertFloatToComplex_1dPfP15HIP_vector_typeIfLj2EEi,@function
_ZL32DataTypeConvertFloatToComplex_1dPfP15HIP_vector_typeIfLj2EEi: ; @_ZL32DataTypeConvertFloatToComplex_1dPfP15HIP_vector_typeIfLj2EEi
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x24
	s_load_b32 s3, s[0:1], 0x10
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_i32_e64 s3, v1
	s_cbranch_execz .LBB0_2
; %bb.1:
	s_load_b128 s[0:3], s[0:1], 0x0
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[3:4], 2, v[1:2]
	v_lshlrev_b64 v[1:2], 3, v[1:2]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v3, vcc_lo, s0, v3
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
	global_load_b32 v0, v[3:4], off
	v_add_co_u32 v3, vcc_lo, s2, v1
	v_add_co_ci_u32_e32 v4, vcc_lo, s3, v2, vcc_lo
	v_mov_b32_e32 v1, 0
	s_waitcnt vmcnt(0)
	global_store_b64 v[3:4], v[0:1], off
.LBB0_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _ZL32DataTypeConvertFloatToComplex_1dPfP15HIP_vector_typeIfLj2EEi
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 5
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._ZL32DataTypeConvertFloatToComplex_1dPfP15HIP_vector_typeIfLj2EEi,"axG",@progbits,_ZL32DataTypeConvertFloatToComplex_1dPfP15HIP_vector_typeIfLj2EEi,comdat
.Lfunc_end0:
	.size	_ZL32DataTypeConvertFloatToComplex_1dPfP15HIP_vector_typeIfLj2EEi, .Lfunc_end0-_ZL32DataTypeConvertFloatToComplex_1dPfP15HIP_vector_typeIfLj2EEi
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 160
; NumSgprs: 18
; NumVgprs: 5
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 5
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.section	.text._ZL17DataGetBackFft_1dP15HIP_vector_typeIfLj2EEPffi,"axG",@progbits,_ZL17DataGetBackFft_1dP15HIP_vector_typeIfLj2EEPffi,comdat
	.globl	_ZL17DataGetBackFft_1dP15HIP_vector_typeIfLj2EEPffi ; -- Begin function _ZL17DataGetBackFft_1dP15HIP_vector_typeIfLj2EEPffi
	.p2align	8
	.type	_ZL17DataGetBackFft_1dP15HIP_vector_typeIfLj2EEPffi,@function
_ZL17DataGetBackFft_1dP15HIP_vector_typeIfLj2EEPffi: ; @_ZL17DataGetBackFft_1dP15HIP_vector_typeIfLj2EEPffi
; %bb.0:
	s_clause 0x1
	s_load_b32 s4, s[0:1], 0x24
	s_load_b64 s[2:3], s[0:1], 0x10
	s_waitcnt lgkmcnt(0)
	s_and_b32 s4, s4, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
	s_mov_b32 s4, exec_lo
	v_cmpx_gt_i32_e64 s3, v1
	s_cbranch_execz .LBB1_2
; %bb.1:
	s_load_b128 s[4:7], s[0:1], 0x0
	v_ashrrev_i32_e32 v2, 31, v1
	v_cvt_f32_i32_e32 v0, s3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 3, v[1:2]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v3, vcc_lo, s4, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
	global_load_b32 v3, v[3:4], off
	v_mul_f32_e32 v4, s2, v0
	s_waitcnt vmcnt(0)
	v_div_scale_f32 v0, null, v4, v4, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v5, v0
	s_waitcnt_depctr 0xfff
	v_fma_f32 v6, -v0, v5, 1.0
	v_fmac_f32_e32 v5, v6, v5
	v_div_scale_f32 v6, vcc_lo, v3, v4, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v7, v6, v5
	v_fma_f32 v8, -v0, v7, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v7, v8, v5
	v_fma_f32 v6, -v0, v7, v6
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fmas_f32 v2, v6, v5, v7
	v_add_co_u32 v0, vcc_lo, s6, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
	v_div_fixup_f32 v2, v2, v4, v3
	global_store_b32 v[0:1], v2, off
.LBB1_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _ZL17DataGetBackFft_1dP15HIP_vector_typeIfLj2EEPffi
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 9
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._ZL17DataGetBackFft_1dP15HIP_vector_typeIfLj2EEPffi,"axG",@progbits,_ZL17DataGetBackFft_1dP15HIP_vector_typeIfLj2EEPffi,comdat
.Lfunc_end1:
	.size	_ZL17DataGetBackFft_1dP15HIP_vector_typeIfLj2EEPffi, .Lfunc_end1-_ZL17DataGetBackFft_1dP15HIP_vector_typeIfLj2EEPffi
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 260
; NumSgprs: 18
; NumVgprs: 9
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 9
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.section	.text._ZL20PhaseShiftForwFft_1dP15HIP_vector_typeIfLj2EES1_i,"axG",@progbits,_ZL20PhaseShiftForwFft_1dP15HIP_vector_typeIfLj2EES1_i,comdat
	.globl	_ZL20PhaseShiftForwFft_1dP15HIP_vector_typeIfLj2EES1_i ; -- Begin function _ZL20PhaseShiftForwFft_1dP15HIP_vector_typeIfLj2EES1_i
	.p2align	8
	.type	_ZL20PhaseShiftForwFft_1dP15HIP_vector_typeIfLj2EES1_i,@function
_ZL20PhaseShiftForwFft_1dP15HIP_vector_typeIfLj2EES1_i: ; @_ZL20PhaseShiftForwFft_1dP15HIP_vector_typeIfLj2EES1_i
; %bb.0:
	s_clause 0x1
	s_load_b32 s3, s[0:1], 0x24
	s_load_b32 s2, s[0:1], 0x10
	s_waitcnt lgkmcnt(0)
	s_and_b32 s3, s3, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
	s_mov_b32 s3, exec_lo
	v_cmpx_gt_i32_e64 s2, v1
	s_cbranch_execz .LBB2_22
; %bb.1:
	s_lshr_b32 s3, s2, 31
                                        ; implicit-def: $vgpr4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s2, s2, s3
	s_ashr_i32 s3, s2, 1
	s_mov_b32 s2, exec_lo
	v_cvt_f32_i32_e32 v0, s3
	v_cmpx_le_i32_e64 s3, v1
	s_xor_b32 s2, exec_lo, s2
	s_cbranch_execz .LBB2_3
; %bb.2:
	v_subrev_nc_u32_e32 v2, s3, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f32_i32_e32 v2, v2
	v_mul_f32_e32 v2, 4.0, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v2, 0x3f490fdb, v2
	v_div_scale_f32 v3, null, v0, v0, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v4, v3
	s_waitcnt_depctr 0xfff
	v_fma_f32 v5, -v3, v4, 1.0
	v_fmac_f32_e32 v4, v5, v4
	v_div_scale_f32 v5, vcc_lo, v2, v0, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v6, v5, v4
	v_fma_f32 v7, -v3, v6, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v6, v7, v4
	v_fma_f32 v3, -v3, v6, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v3, v3, v4, v6
	v_div_fixup_f32 v0, v3, v0, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f32_e32 v4, 0xc0490fdb, v0
                                        ; implicit-def: $vgpr0
.LBB2_3:                                ; %Flow71
	s_and_not1_saveexec_b32 s2, s2
	s_cbranch_execz .LBB2_5
; %bb.4:
	v_cvt_f32_i32_e32 v2, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v2, 4.0, v2
	v_mul_f32_e32 v2, 0x3f490fdb, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_scale_f32 v3, null, v0, v0, v2
	v_rcp_f32_e32 v4, v3
	s_waitcnt_depctr 0xfff
	v_fma_f32 v5, -v3, v4, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v4, v5, v4
	v_div_scale_f32 v5, vcc_lo, v2, v0, v2
	v_mul_f32_e32 v6, v5, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v7, -v3, v6, v5
	v_fmac_f32_e32 v6, v7, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v3, -v3, v6, v5
	v_div_fmas_f32 v3, v3, v4, v6
	s_delay_alu instid0(VALU_DEP_1)
	v_div_fixup_f32 v4, v3, v0, v2
.LBB2_5:
	s_or_b32 exec_lo, exec_lo, s2
	s_load_b128 s[0:3], s[0:1], 0x0
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v5, 0.5, v4
                                        ; implicit-def: $vgpr11
                                        ; implicit-def: $vgpr10
	v_lshlrev_b64 v[2:3], 3, v[1:2]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_and_b32_e32 v6, 0x7fffffff, v5
	v_cmp_ngt_f32_e64 s4, 0x48000000, |v5|
	v_lshrrev_b32_e32 v7, 23, v6
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
	v_add_co_u32 v0, vcc_lo, s0, v2
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v3, vcc_lo
	global_load_b32 v9, v[0:1], off
	s_and_saveexec_b32 s0, s4
	s_xor_b32 s5, exec_lo, s0
	s_cbranch_execz .LBB2_7
; %bb.6:
	s_mov_b32 s0, 0x7fffff
	v_mov_b32_e32 v12, 0
	v_and_or_b32 v8, v6, s0, 0x800000
	v_add_nc_u32_e32 v18, 0xffffff88, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[10:11], null, 0xfe5163ab, v8, 0
	v_cmp_lt_u32_e32 vcc_lo, 63, v18
	v_cndmask_b32_e64 v19, 0, 0xffffffc0, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[13:14], null, 0x3c439041, v8, v[11:12]
	v_add_nc_u32_e32 v19, v19, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v11, v14
	v_cmp_lt_u32_e64 s0, 31, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[14:15], null, 0xdb629599, v8, v[11:12]
	v_cndmask_b32_e64 v20, 0, 0xffffffe0, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_mov_b32 v11, v15 :: v_dual_add_nc_u32 v20, v20, v19
	v_cndmask_b32_e32 v10, v14, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_lt_u32_e64 s1, 31, v20
	v_mad_u64_u32 v[15:16], null, 0xf534ddc0, v8, v[11:12]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v11, v16
	v_cndmask_b32_e32 v13, v15, v13, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[16:17], null, 0xfc2757d1, v8, v[11:12]
	v_mov_b32_e32 v11, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[17:18], null, 0x4e441529, v8, v[11:12]
	v_mov_b32_e32 v11, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[18:19], null, 0xa2f9836e, v8, v[11:12]
	v_cndmask_b32_e64 v8, 0, 0xffffffe0, s1
	v_dual_cndmask_b32 v11, v17, v15 :: v_dual_add_nc_u32 v8, v8, v20
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v12, v18, v16 :: v_dual_cndmask_b32 v17, v19, v17
	v_cndmask_b32_e32 v16, v16, v14, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 0, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v15, v12, v11, s0
	v_cndmask_b32_e64 v12, v17, v12, s0
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v11, v11, v16, s0
	v_sub_nc_u32_e32 v17, 32, v8
	v_cndmask_b32_e64 v16, v16, v13, s0
	v_cndmask_b32_e64 v12, v12, v15, s1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v15, v15, v11, s1
	v_cndmask_b32_e64 v11, v11, v16, s1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_alignbit_b32 v18, v12, v15, v17
	v_alignbit_b32 v14, v15, v11, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v8, v18, v12, vcc_lo
	v_cndmask_b32_e32 v12, v14, v15, vcc_lo
	v_cndmask_b32_e64 v10, v13, v10, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_bfe_u32 v13, v8, 29, 1
	v_alignbit_b32 v14, v8, v12, 30
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v10, v16, v10, s1
	v_sub_nc_u32_e32 v15, 0, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_alignbit_b32 v16, v11, v10, v17
	v_xor_b32_e32 v14, v14, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v11, v16, v11, vcc_lo
	v_clz_i32_u32_e32 v16, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_alignbit_b32 v12, v12, v11, 30
	v_alignbit_b32 v10, v11, v10, 30
	v_min_u32_e32 v16, 32, v16
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v11, v12, v15
	v_xor_b32_e32 v10, v10, v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v12, 31, v16
	v_lshlrev_b32_e32 v18, 23, v16
	v_alignbit_b32 v14, v14, v11, v12
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_alignbit_b32 v10, v11, v10, v12
	v_lshrrev_b32_e32 v12, 29, v8
	v_lshrrev_b32_e32 v8, 30, v8
	v_alignbit_b32 v11, v14, v10, 9
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_lshlrev_b32_e32 v12, 31, v12
	v_lshrrev_b32_e32 v14, 9, v14
	v_clz_i32_u32_e32 v15, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or_b32_e32 v17, 0.5, v12
	v_min_u32_e32 v15, 32, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v17, v17, v18
	v_sub_nc_u32_e32 v19, 31, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v10, v11, v10, v19
	v_or_b32_e32 v11, v14, v17
	v_add_lshl_u32 v14, v15, v16, 23
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshrrev_b32_e32 v10, 9, v10
	v_mul_f32_e32 v15, 0x3fc90fda, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v10, v10, v14
	v_fma_f32 v14, 0x3fc90fda, v11, -v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v10, 0x33000000, v10
	v_fmamk_f32 v11, v11, 0x33a22168, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or_b32_e32 v10, v10, v12
	v_fmac_f32_e32 v11, 0x3fc90fda, v10
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_add_f32 v10, v15, v11 :: v_dual_add_nc_u32 v11, v13, v8
.LBB2_7:                                ; %Flow70
	s_or_saveexec_b32 s0, s5
	v_mul_f32_e64 v8, 0x3f22f983, |v5|
	s_xor_b32 exec_lo, exec_lo, s0
; %bb.8:
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f32_e32 v11, v8
	v_fma_f32 v10, 0xbfc90fda, v11, |v5|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmamk_f32 v10, v11, 0xb3a22168, v10
	v_fmamk_f32 v10, v11, 0xa7c234c4, v10
	v_cvt_i32_f32_e32 v11, v11
; %bb.9:                                ; %_ZL4cosff.exit
	s_or_b32 exec_lo, exec_lo, s0
	global_load_b32 v12, v[0:1], off offset:4
                                        ; implicit-def: $vgpr14
                                        ; implicit-def: $vgpr13
	s_and_saveexec_b32 s0, s4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s5, exec_lo, s0
	s_cbranch_execz .LBB2_11
; %bb.10:
	s_mov_b32 s0, 0x7fffff
	v_mov_b32_e32 v15, 0
	v_and_or_b32 v23, v6, s0, 0x800000
	v_add_nc_u32_e32 v21, 0xffffff88, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[13:14], null, 0xfe5163ab, v23, 0
	v_cmp_lt_u32_e32 vcc_lo, 63, v21
	v_cndmask_b32_e64 v22, 0, 0xffffffc0, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[16:17], null, 0x3c439041, v23, v[14:15]
	v_add_nc_u32_e32 v22, v22, v21
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v14, v17
	v_cmp_lt_u32_e64 s0, 31, v22
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[17:18], null, 0xdb629599, v23, v[14:15]
	v_cndmask_b32_e64 v24, 0, 0xffffffe0, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v13, v17, v13 :: v_dual_add_nc_u32 v24, v24, v22
	v_mov_b32_e32 v14, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_lt_u32_e64 s1, 31, v24
	v_mad_u64_u32 v[18:19], null, 0xf534ddc0, v23, v[14:15]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v14, v19
	v_cndmask_b32_e32 v16, v18, v16, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[19:20], null, 0xfc2757d1, v23, v[14:15]
	v_cndmask_b32_e64 v13, v16, v13, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v14, v20
	v_mad_u64_u32 v[20:21], null, 0x4e441529, v23, v[14:15]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v14, v21
	v_mad_u64_u32 v[21:22], null, 0xa2f9836e, v23, v[14:15]
	v_cndmask_b32_e64 v14, 0, 0xffffffe0, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v15, v20, v18 :: v_dual_add_nc_u32 v14, v14, v24
	v_dual_cndmask_b32 v21, v21, v19 :: v_dual_cndmask_b32 v20, v22, v20
	v_cndmask_b32_e32 v19, v19, v17, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_eq_u32_e32 vcc_lo, 0, v14
	v_cndmask_b32_e64 v18, v21, v15, s0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v20, v20, v21, s0
	v_cndmask_b32_e64 v15, v15, v19, s0
	v_sub_nc_u32_e32 v21, 32, v14
	v_cndmask_b32_e64 v19, v19, v16, s0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v20, v20, v18, s1
	v_cndmask_b32_e64 v18, v18, v15, s1
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v15, v15, v19, s1
	v_cndmask_b32_e64 v13, v19, v13, s1
	v_alignbit_b32 v22, v20, v18, v21
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_alignbit_b32 v17, v18, v15, v21
	v_cndmask_b32_e32 v14, v22, v20, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v20, v15, v13, v21
	v_cndmask_b32_e32 v16, v17, v18, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_bfe_u32 v17, v14, 29, 1
	v_cndmask_b32_e32 v15, v20, v15, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v18, v14, v16, 30
	v_sub_nc_u32_e32 v19, 0, v17
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_alignbit_b32 v16, v16, v15, 30
	v_alignbit_b32 v13, v15, v13, 30
	v_xor_b32_e32 v18, v18, v19
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v15, v16, v19
	v_xor_b32_e32 v13, v13, v19
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_clz_i32_u32_e32 v20, v18
	v_min_u32_e32 v20, 32, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v16, 31, v20
	v_lshlrev_b32_e32 v22, 23, v20
	v_alignbit_b32 v18, v18, v15, v16
	v_alignbit_b32 v13, v15, v13, v16
	v_lshrrev_b32_e32 v16, 29, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_alignbit_b32 v15, v18, v13, 9
	v_lshlrev_b32_e32 v16, 31, v16
	v_lshrrev_b32_e32 v18, 9, v18
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_clz_i32_u32_e32 v19, v15
	v_or_b32_e32 v21, 0.5, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_min_u32_e32 v19, 32, v19
	v_sub_nc_u32_e32 v21, v21, v22
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v23, 31, v19
	v_alignbit_b32 v13, v15, v13, v23
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_or_b32_e32 v15, v18, v21
	v_add_lshl_u32 v18, v19, v20, 23
	v_lshrrev_b32_e32 v13, 9, v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v19, 0x3fc90fda, v15
	v_sub_nc_u32_e32 v13, v13, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v18, 0x3fc90fda, v15, -v19
	v_add_nc_u32_e32 v13, 0x33000000, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmamk_f32 v15, v15, 0x33a22168, v18
	v_or_b32_e32 v13, v13, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v15, 0x3fc90fda, v13
	v_lshrrev_b32_e32 v14, 30, v14
	v_dual_add_f32 v13, v19, v15 :: v_dual_add_nc_u32 v14, v17, v14
.LBB2_11:                               ; %Flow69
	s_and_not1_saveexec_b32 s0, s5
; %bb.12:
	v_rndne_f32_e32 v14, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v13, 0xbfc90fda, v14, |v5|
	v_fmamk_f32 v13, v14, 0xb3a22168, v13
	s_delay_alu instid0(VALU_DEP_1)
	v_fmamk_f32 v13, v14, 0xa7c234c4, v13
	v_cvt_i32_f32_e32 v14, v14
; %bb.13:                               ; %_ZL4sinff.exit
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v15, v10, v10 :: v_dual_mul_f32 v16, v13, v13
	s_mov_b32 s0, 0xb94c1982
	s_mov_b32 s1, 0x37d75334
	v_dual_fmaak_f32 v17, s0, v15, 0x3c0881c4 :: v_dual_lshlrev_b32 v22, 30, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_dual_fmaak_f32 v20, s1, v16, 0xbab64f3b :: v_dual_and_b32 v21, 1, v11
	v_and_b32_e32 v14, 1, v14
	v_lshlrev_b32_e32 v11, 30, v11
	v_fmaak_f32 v17, v15, v17, 0xbe2aaa9d
	v_fmaak_f32 v18, s1, v15, 0xbab64f3b
	v_cmp_eq_u32_e32 vcc_lo, 0, v21
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_and_b32_e32 v11, 0x80000000, v11
	v_mul_f32_e32 v17, v15, v17
	v_fmaak_f32 v19, s0, v16, 0x3c0881c4
	v_fmaak_f32 v18, v15, v18, 0x3d2aabf7
	v_add_co_u32 v2, s0, s2, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_fmac_f32 v10, v10, v17 :: v_dual_fmaak_f32 v19, v16, v19, 0xbe2aaa9d
	v_fmaak_f32 v18, v15, v18, 0xbf000004
	v_and_b32_e32 v17, 0x80000000, v22
	v_add_co_ci_u32_e64 v3, s0, s3, v3, s0
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v19, v16, v19
	v_fmaak_f32 v20, v16, v20, 0x3d2aabf7
	v_fma_f32 v15, v15, v18, 1.0
	v_dual_fmac_f32 v13, v13, v19 :: v_dual_fmaak_f32 v20, v16, v20, 0xbf000004
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v10, -v10, v15, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 0, v14
	v_xor_b32_e32 v14, v6, v17
	v_fma_f32 v16, v16, v20, 1.0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v10, v11, v10
	v_cndmask_b32_e32 v13, v16, v13, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v5, 0x1f8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor3_b32 v11, v14, v13, v5
	v_cndmask_b32_e32 v11, 0x7fc00000, v11, vcc_lo
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_cndmask_b32 v10, 0x7fc00000, v10 :: v_dual_mul_f32 v11, v12, v11
	v_fmac_f32_e32 v11, v9, v10
                                        ; implicit-def: $vgpr10
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
	v_mul_f32_e32 v9, v4, v11
                                        ; implicit-def: $vgpr11
	global_store_b32 v[2:3], v9, off offset:4
	global_load_b32 v9, v[0:1], off
	s_and_saveexec_b32 s0, s4
	s_xor_b32 s3, exec_lo, s0
	s_cbranch_execz .LBB2_15
; %bb.14:
	s_mov_b32 s0, 0x7fffff
	v_mov_b32_e32 v12, 0
	v_and_or_b32 v20, v6, s0, 0x800000
	v_add_nc_u32_e32 v18, 0xffffff88, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[10:11], null, 0xfe5163ab, v20, 0
	v_cmp_lt_u32_e64 s0, 63, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v19, 0, 0xffffffc0, s0
	v_mad_u64_u32 v[13:14], null, 0x3c439041, v20, v[11:12]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v19, v19, v18
	v_mov_b32_e32 v11, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_lt_u32_e64 s1, 31, v19
	v_mad_u64_u32 v[14:15], null, 0xdb629599, v20, v[11:12]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v21, 0, 0xffffffe0, s1
	v_add_nc_u32_e32 v21, v21, v19
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mov_b32_e32 v11, v15
	v_cndmask_b32_e64 v10, v14, v10, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_lt_u32_e64 s2, 31, v21
	v_mad_u64_u32 v[15:16], null, 0xf534ddc0, v20, v[11:12]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v11, v16
	v_cndmask_b32_e64 v13, v15, v13, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[16:17], null, 0xfc2757d1, v20, v[11:12]
	v_cndmask_b32_e64 v10, v13, v10, s1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v11, v17
	v_mad_u64_u32 v[17:18], null, 0x4e441529, v20, v[11:12]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v11, v18
	v_mad_u64_u32 v[18:19], null, 0xa2f9836e, v20, v[11:12]
	v_cndmask_b32_e64 v11, 0, 0xffffffe0, s2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v12, v17, v15, s0
	v_add_nc_u32_e32 v11, v11, v21
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v18, v18, v16, s0
	v_cndmask_b32_e64 v17, v19, v17, s0
	v_cndmask_b32_e64 v16, v16, v14, s0
	v_cmp_eq_u32_e64 s0, 0, v11
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v15, v18, v12, s1
	v_cndmask_b32_e64 v17, v17, v18, s1
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v12, v12, v16, s1
	v_sub_nc_u32_e32 v18, 32, v11
	v_cndmask_b32_e64 v16, v16, v13, s1
	v_cndmask_b32_e64 v17, v17, v15, s2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v15, v15, v12, s2
	v_cndmask_b32_e64 v12, v12, v16, s2
	v_cndmask_b32_e64 v10, v16, v10, s2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v19, v17, v15, v18
	v_alignbit_b32 v14, v15, v12, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v11, v19, v17, s0
	v_alignbit_b32 v17, v12, v10, v18
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v13, v14, v15, s0
	v_bfe_u32 v14, v11, 29, 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v12, v17, v12, s0
	v_alignbit_b32 v15, v11, v13, 30
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v16, 0, v14
	v_alignbit_b32 v13, v13, v12, 30
	v_alignbit_b32 v10, v12, v10, 30
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v15, v15, v16
	v_xor_b32_e32 v12, v13, v16
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v10, v10, v16
	v_clz_i32_u32_e32 v17, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_min_u32_e32 v17, 32, v17
	v_sub_nc_u32_e32 v13, 31, v17
	v_lshlrev_b32_e32 v19, 23, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_alignbit_b32 v15, v15, v12, v13
	v_alignbit_b32 v10, v12, v10, v13
	v_lshrrev_b32_e32 v13, 29, v11
	v_lshrrev_b32_e32 v11, 30, v11
	v_alignbit_b32 v12, v15, v10, 9
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_lshlrev_b32_e32 v13, 31, v13
	v_lshrrev_b32_e32 v15, 9, v15
	v_add_nc_u32_e32 v11, v14, v11
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_clz_i32_u32_e32 v16, v12
	v_or_b32_e32 v18, 0.5, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_min_u32_e32 v16, 32, v16
	v_sub_nc_u32_e32 v18, v18, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v20, 31, v16
	v_alignbit_b32 v10, v12, v10, v20
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_or_b32_e32 v12, v15, v18
	v_add_lshl_u32 v15, v16, v17, 23
	v_lshrrev_b32_e32 v10, 9, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v16, 0x3fc90fda, v12
	v_sub_nc_u32_e32 v10, v10, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v15, 0x3fc90fda, v12, -v16
	v_add_nc_u32_e32 v10, 0x33000000, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmamk_f32 v12, v12, 0x33a22168, v15
	v_or_b32_e32 v10, v10, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v12, 0x3fc90fda, v10
	v_add_f32_e32 v10, v16, v12
.LBB2_15:                               ; %Flow68
	s_and_not1_saveexec_b32 s0, s3
; %bb.16:
	v_rndne_f32_e32 v11, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v10, 0xbfc90fda, v11, |v5|
	v_fmamk_f32 v10, v11, 0xb3a22168, v10
	s_delay_alu instid0(VALU_DEP_1)
	v_fmamk_f32 v10, v11, 0xa7c234c4, v10
	v_cvt_i32_f32_e32 v11, v11
; %bb.17:                               ; %_ZL4sinff.exit43
	s_or_b32 exec_lo, exec_lo, s0
	global_load_b32 v0, v[0:1], off offset:4
                                        ; implicit-def: $vgpr12
                                        ; implicit-def: $vgpr1
	s_and_saveexec_b32 s0, s4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s3, exec_lo, s0
	s_cbranch_execz .LBB2_19
; %bb.18:
	s_mov_b32 s0, 0x7fffff
	v_mov_b32_e32 v14, 0
	v_and_or_b32 v1, v6, s0, 0x800000
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[12:13], null, 0xfe5163ab, v1, 0
	v_mad_u64_u32 v[15:16], null, 0x3c439041, v1, v[13:14]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v13, v16
	v_mad_u64_u32 v[16:17], null, 0xdb629599, v1, v[13:14]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v13, v17
	v_mad_u64_u32 v[17:18], null, 0xf534ddc0, v1, v[13:14]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v13, v18 :: v_dual_add_nc_u32 v18, 0xffffff88, v7
	v_mad_u64_u32 v[7:8], null, 0xfc2757d1, v1, v[13:14]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_u32_e64 s0, 63, v18
	v_cndmask_b32_e64 v19, 0, 0xffffffc0, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mov_b32_e32 v13, v8
	v_cndmask_b32_e64 v12, v16, v12, s0
	v_add_nc_u32_e32 v8, v19, v18
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[18:19], null, 0x4e441529, v1, v[13:14]
	v_cmp_lt_u32_e64 s1, 31, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v20, 0, 0xffffffe0, s1
	v_dual_mov_b32 v13, v19 :: v_dual_add_nc_u32 v8, v20, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[19:20], null, 0xa2f9836e, v1, v[13:14]
	v_cndmask_b32_e64 v13, v18, v17, s0
	v_cmp_lt_u32_e64 s2, 31, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v14, v19, v7, s0
	v_cndmask_b32_e64 v1, 0, 0xffffffe0, s2
	v_cndmask_b32_e64 v18, v20, v18, s0
	v_cndmask_b32_e64 v7, v7, v16, s0
	s_delay_alu instid0(VALU_DEP_3)
	v_add_nc_u32_e32 v1, v1, v8
	v_cndmask_b32_e64 v8, v17, v15, s0
	v_cndmask_b32_e64 v15, v14, v13, s1
	v_cndmask_b32_e64 v14, v18, v14, s1
	v_cndmask_b32_e64 v13, v13, v7, s1
	v_sub_nc_u32_e32 v17, 32, v1
	v_cndmask_b32_e64 v7, v7, v8, s1
	v_cmp_eq_u32_e64 s0, 0, v1
	v_cndmask_b32_e64 v14, v14, v15, s2
	v_cndmask_b32_e64 v15, v15, v13, s2
	v_cndmask_b32_e64 v8, v8, v12, s1
	v_cndmask_b32_e64 v13, v13, v7, s2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v18, v14, v15, v17
	v_cndmask_b32_e64 v7, v7, v8, s2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v16, v15, v13, v17
	v_cndmask_b32_e64 v1, v18, v14, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v12, v16, v15, s0
	v_alignbit_b32 v16, v13, v7, v17
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_bfe_u32 v14, v1, 29, 1
	v_alignbit_b32 v8, v1, v12, 30
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v13, v16, v13, s0
	v_sub_nc_u32_e32 v15, 0, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_alignbit_b32 v12, v12, v13, 30
	v_alignbit_b32 v7, v13, v7, 30
	v_xor_b32_e32 v8, v8, v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v12, v12, v15
	v_xor_b32_e32 v7, v7, v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_clz_i32_u32_e32 v16, v8
	v_min_u32_e32 v16, 32, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v13, 31, v16
	v_lshlrev_b32_e32 v18, 23, v16
	v_alignbit_b32 v8, v8, v12, v13
	v_alignbit_b32 v7, v12, v7, v13
	v_lshrrev_b32_e32 v13, 29, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_alignbit_b32 v12, v8, v7, 9
	v_lshlrev_b32_e32 v13, 31, v13
	v_lshrrev_b32_e32 v8, 9, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_clz_i32_u32_e32 v15, v12
	v_or_b32_e32 v17, 0.5, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_min_u32_e32 v15, 32, v15
	v_sub_nc_u32_e32 v17, v17, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v19, 31, v15
	v_or_b32_e32 v8, v8, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_alignbit_b32 v7, v12, v7, v19
	v_add_lshl_u32 v12, v15, v16, 23
	v_mul_f32_e32 v15, 0x3fc90fda, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshrrev_b32_e32 v7, 9, v7
	v_sub_nc_u32_e32 v7, v7, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v12, 0x3fc90fda, v8, -v15
	v_add_nc_u32_e32 v7, 0x33000000, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmamk_f32 v8, v8, 0x33a22168, v12
	v_or_b32_e32 v7, v7, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v8, 0x3fc90fda, v7
	v_lshrrev_b32_e32 v7, 30, v1
	v_dual_add_f32 v1, v15, v8 :: v_dual_add_nc_u32 v12, v14, v7
                                        ; implicit-def: $vgpr8
.LBB2_19:                               ; %Flow
	s_and_not1_saveexec_b32 s0, s3
; %bb.20:
	v_rndne_f32_e32 v7, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v1, 0xbfc90fda, v7, |v5|
	v_cvt_i32_f32_e32 v12, v7
	v_fmamk_f32 v1, v7, 0xb3a22168, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_fmamk_f32 v1, v7, 0xa7c234c4, v1
; %bb.21:                               ; %_ZL4cosff.exit49
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v7, v10, v10 :: v_dual_mul_f32 v8, v1, v1
	s_mov_b32 s0, 0xb94c1982
	s_mov_b32 s1, 0x37d75334
	v_dual_fmaak_f32 v13, s0, v7, 0x3c0881c4 :: v_dual_and_b32 v18, 1, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_fmaak_f32 v16, s0, v8, 0x3c0881c4
	v_dual_fmaak_f32 v14, s1, v7, 0xbab64f3b :: v_dual_fmaak_f32 v17, s1, v8, 0xbab64f3b
	v_and_b32_e32 v15, 1, v11
	v_dual_fmaak_f32 v13, v7, v13, 0xbe2aaa9d :: v_dual_fmaak_f32 v16, v8, v16, 0xbe2aaa9d
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_fmaak_f32 v14, v7, v14, 0x3d2aabf7 :: v_dual_lshlrev_b32 v11, 30, v11
	v_fmaak_f32 v17, v8, v17, 0x3d2aabf7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_mul_f32 v13, v7, v13 :: v_dual_mul_f32 v16, v8, v16
	v_fmaak_f32 v14, v7, v14, 0xbf000004
	v_cmp_eq_u32_e64 s0, 0, v15
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fmaak_f32 v17, v8, v17, 0xbf000004
	v_dual_fmac_f32 v10, v10, v13 :: v_dual_and_b32 v11, 0x80000000, v11
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v7, v7, v14, 1.0
	v_xor_b32_e32 v6, v6, v11
	s_delay_alu instid0(VALU_DEP_2)
	v_cndmask_b32_e64 v7, v7, v10, s0
	v_lshlrev_b32_e32 v10, 30, v12
	v_fmac_f32_e32 v1, v1, v16
	v_fma_f32 v8, v8, v17, 1.0
	v_cmp_eq_u32_e64 s0, 0, v18
	v_xor3_b32 v5, v6, v7, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v1, -v1, v8, s0
	v_and_b32_e32 v8, 0x80000000, v10
	v_cndmask_b32_e32 v5, 0x7fc00000, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v1, v8, v1
	s_waitcnt vmcnt(1)
	v_mul_f32_e32 v5, v9, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v1, 0x7fc00000, v1, vcc_lo
	s_waitcnt vmcnt(0)
	v_fma_f32 v0, v0, v1, -v5
	s_delay_alu instid0(VALU_DEP_1)
	v_mul_f32_e32 v0, v4, v0
	global_store_b32 v[2:3], v0, off
.LBB2_22:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _ZL20PhaseShiftForwFft_1dP15HIP_vector_typeIfLj2EES1_i
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 25
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._ZL20PhaseShiftForwFft_1dP15HIP_vector_typeIfLj2EES1_i,"axG",@progbits,_ZL20PhaseShiftForwFft_1dP15HIP_vector_typeIfLj2EES1_i,comdat
.Lfunc_end2:
	.size	_ZL20PhaseShiftForwFft_1dP15HIP_vector_typeIfLj2EES1_i, .Lfunc_end2-_ZL20PhaseShiftForwFft_1dP15HIP_vector_typeIfLj2EES1_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 4180
; NumSgprs: 18
; NumVgprs: 25
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 3
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 25
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.section	.text._ZL20PhaseShiftBackFft_1dP15HIP_vector_typeIfLj2EES1_i,"axG",@progbits,_ZL20PhaseShiftBackFft_1dP15HIP_vector_typeIfLj2EES1_i,comdat
	.globl	_ZL20PhaseShiftBackFft_1dP15HIP_vector_typeIfLj2EES1_i ; -- Begin function _ZL20PhaseShiftBackFft_1dP15HIP_vector_typeIfLj2EES1_i
	.p2align	8
	.type	_ZL20PhaseShiftBackFft_1dP15HIP_vector_typeIfLj2EES1_i,@function
_ZL20PhaseShiftBackFft_1dP15HIP_vector_typeIfLj2EES1_i: ; @_ZL20PhaseShiftBackFft_1dP15HIP_vector_typeIfLj2EES1_i
; %bb.0:
	s_clause 0x1
	s_load_b32 s3, s[0:1], 0x24
	s_load_b32 s2, s[0:1], 0x10
	s_waitcnt lgkmcnt(0)
	s_and_b32 s3, s3, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
	s_mov_b32 s3, exec_lo
	v_cmpx_gt_i32_e64 s2, v1
	s_cbranch_execz .LBB3_22
; %bb.1:
	s_lshr_b32 s3, s2, 31
                                        ; implicit-def: $vgpr4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s2, s2, s3
	s_ashr_i32 s3, s2, 1
	s_mov_b32 s2, exec_lo
	v_cvt_f32_i32_e32 v0, s3
	v_cmpx_le_i32_e64 s3, v1
	s_xor_b32 s2, exec_lo, s2
	s_cbranch_execz .LBB3_3
; %bb.2:
	v_subrev_nc_u32_e32 v2, s3, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f32_i32_e32 v2, v2
	v_mul_f32_e32 v2, 4.0, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v2, 0x3f490fdb, v2
	v_div_scale_f32 v3, null, v0, v0, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v4, v3
	s_waitcnt_depctr 0xfff
	v_fma_f32 v5, -v3, v4, 1.0
	v_fmac_f32_e32 v4, v5, v4
	v_div_scale_f32 v5, vcc_lo, v2, v0, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v6, v5, v4
	v_fma_f32 v7, -v3, v6, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v6, v7, v4
	v_fma_f32 v3, -v3, v6, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v3, v3, v4, v6
	v_div_fixup_f32 v0, v3, v0, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f32_e32 v4, 0xc0490fdb, v0
                                        ; implicit-def: $vgpr0
.LBB3_3:                                ; %Flow71
	s_and_not1_saveexec_b32 s2, s2
	s_cbranch_execz .LBB3_5
; %bb.4:
	v_cvt_f32_i32_e32 v2, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v2, 4.0, v2
	v_mul_f32_e32 v2, 0x3f490fdb, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_scale_f32 v3, null, v0, v0, v2
	v_rcp_f32_e32 v4, v3
	s_waitcnt_depctr 0xfff
	v_fma_f32 v5, -v3, v4, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v4, v5, v4
	v_div_scale_f32 v5, vcc_lo, v2, v0, v2
	v_mul_f32_e32 v6, v5, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v7, -v3, v6, v5
	v_fmac_f32_e32 v6, v7, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v3, -v3, v6, v5
	v_div_fmas_f32 v3, v3, v4, v6
	s_delay_alu instid0(VALU_DEP_1)
	v_div_fixup_f32 v4, v3, v0, v2
.LBB3_5:
	s_or_b32 exec_lo, exec_lo, s2
	s_load_b128 s[0:3], s[0:1], 0x0
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v5, 0.5, v4
                                        ; implicit-def: $vgpr11
                                        ; implicit-def: $vgpr10
	v_lshlrev_b64 v[2:3], 3, v[1:2]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_and_b32_e32 v6, 0x7fffffff, v5
	v_cmp_ngt_f32_e64 s4, 0x48000000, |v5|
	v_lshrrev_b32_e32 v7, 23, v6
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
	v_add_co_u32 v0, vcc_lo, s0, v2
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v3, vcc_lo
	global_load_b32 v9, v[0:1], off
	s_and_saveexec_b32 s0, s4
	s_xor_b32 s5, exec_lo, s0
	s_cbranch_execz .LBB3_7
; %bb.6:
	s_mov_b32 s0, 0x7fffff
	v_mov_b32_e32 v12, 0
	v_and_or_b32 v8, v6, s0, 0x800000
	v_add_nc_u32_e32 v18, 0xffffff88, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[10:11], null, 0xfe5163ab, v8, 0
	v_cmp_lt_u32_e32 vcc_lo, 63, v18
	v_cndmask_b32_e64 v19, 0, 0xffffffc0, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[13:14], null, 0x3c439041, v8, v[11:12]
	v_add_nc_u32_e32 v19, v19, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v11, v14
	v_cmp_lt_u32_e64 s0, 31, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[14:15], null, 0xdb629599, v8, v[11:12]
	v_cndmask_b32_e64 v20, 0, 0xffffffe0, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_mov_b32 v11, v15 :: v_dual_add_nc_u32 v20, v20, v19
	v_cndmask_b32_e32 v10, v14, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_lt_u32_e64 s1, 31, v20
	v_mad_u64_u32 v[15:16], null, 0xf534ddc0, v8, v[11:12]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v11, v16
	v_cndmask_b32_e32 v13, v15, v13, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[16:17], null, 0xfc2757d1, v8, v[11:12]
	v_mov_b32_e32 v11, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[17:18], null, 0x4e441529, v8, v[11:12]
	v_mov_b32_e32 v11, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[18:19], null, 0xa2f9836e, v8, v[11:12]
	v_cndmask_b32_e64 v8, 0, 0xffffffe0, s1
	v_dual_cndmask_b32 v11, v17, v15 :: v_dual_add_nc_u32 v8, v8, v20
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v12, v18, v16 :: v_dual_cndmask_b32 v17, v19, v17
	v_cndmask_b32_e32 v16, v16, v14, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 0, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v15, v12, v11, s0
	v_cndmask_b32_e64 v12, v17, v12, s0
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v11, v11, v16, s0
	v_sub_nc_u32_e32 v17, 32, v8
	v_cndmask_b32_e64 v16, v16, v13, s0
	v_cndmask_b32_e64 v12, v12, v15, s1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v15, v15, v11, s1
	v_cndmask_b32_e64 v11, v11, v16, s1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_alignbit_b32 v18, v12, v15, v17
	v_alignbit_b32 v14, v15, v11, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v8, v18, v12, vcc_lo
	v_cndmask_b32_e32 v12, v14, v15, vcc_lo
	v_cndmask_b32_e64 v10, v13, v10, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_bfe_u32 v13, v8, 29, 1
	v_alignbit_b32 v14, v8, v12, 30
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v10, v16, v10, s1
	v_sub_nc_u32_e32 v15, 0, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_alignbit_b32 v16, v11, v10, v17
	v_xor_b32_e32 v14, v14, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v11, v16, v11, vcc_lo
	v_clz_i32_u32_e32 v16, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_alignbit_b32 v12, v12, v11, 30
	v_alignbit_b32 v10, v11, v10, 30
	v_min_u32_e32 v16, 32, v16
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v11, v12, v15
	v_xor_b32_e32 v10, v10, v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v12, 31, v16
	v_lshlrev_b32_e32 v18, 23, v16
	v_alignbit_b32 v14, v14, v11, v12
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_alignbit_b32 v10, v11, v10, v12
	v_lshrrev_b32_e32 v12, 29, v8
	v_lshrrev_b32_e32 v8, 30, v8
	v_alignbit_b32 v11, v14, v10, 9
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_lshlrev_b32_e32 v12, 31, v12
	v_lshrrev_b32_e32 v14, 9, v14
	v_clz_i32_u32_e32 v15, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or_b32_e32 v17, 0.5, v12
	v_min_u32_e32 v15, 32, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v17, v17, v18
	v_sub_nc_u32_e32 v19, 31, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v10, v11, v10, v19
	v_or_b32_e32 v11, v14, v17
	v_add_lshl_u32 v14, v15, v16, 23
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshrrev_b32_e32 v10, 9, v10
	v_mul_f32_e32 v15, 0x3fc90fda, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v10, v10, v14
	v_fma_f32 v14, 0x3fc90fda, v11, -v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v10, 0x33000000, v10
	v_fmamk_f32 v11, v11, 0x33a22168, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or_b32_e32 v10, v10, v12
	v_fmac_f32_e32 v11, 0x3fc90fda, v10
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_add_f32 v10, v15, v11 :: v_dual_add_nc_u32 v11, v13, v8
.LBB3_7:                                ; %Flow70
	s_or_saveexec_b32 s0, s5
	v_mul_f32_e64 v8, 0x3f22f983, |v5|
	s_xor_b32 exec_lo, exec_lo, s0
; %bb.8:
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f32_e32 v11, v8
	v_fma_f32 v10, 0xbfc90fda, v11, |v5|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmamk_f32 v10, v11, 0xb3a22168, v10
	v_fmamk_f32 v10, v11, 0xa7c234c4, v10
	v_cvt_i32_f32_e32 v11, v11
; %bb.9:                                ; %_ZL4cosff.exit
	s_or_b32 exec_lo, exec_lo, s0
	global_load_b32 v12, v[0:1], off offset:4
                                        ; implicit-def: $vgpr14
                                        ; implicit-def: $vgpr13
	s_and_saveexec_b32 s0, s4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s5, exec_lo, s0
	s_cbranch_execz .LBB3_11
; %bb.10:
	s_mov_b32 s0, 0x7fffff
	v_mov_b32_e32 v15, 0
	v_and_or_b32 v23, v6, s0, 0x800000
	v_add_nc_u32_e32 v21, 0xffffff88, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[13:14], null, 0xfe5163ab, v23, 0
	v_cmp_lt_u32_e32 vcc_lo, 63, v21
	v_cndmask_b32_e64 v22, 0, 0xffffffc0, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[16:17], null, 0x3c439041, v23, v[14:15]
	v_add_nc_u32_e32 v22, v22, v21
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v14, v17
	v_cmp_lt_u32_e64 s0, 31, v22
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[17:18], null, 0xdb629599, v23, v[14:15]
	v_cndmask_b32_e64 v24, 0, 0xffffffe0, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v13, v17, v13 :: v_dual_add_nc_u32 v24, v24, v22
	v_mov_b32_e32 v14, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_lt_u32_e64 s1, 31, v24
	v_mad_u64_u32 v[18:19], null, 0xf534ddc0, v23, v[14:15]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v14, v19
	v_cndmask_b32_e32 v16, v18, v16, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[19:20], null, 0xfc2757d1, v23, v[14:15]
	v_cndmask_b32_e64 v13, v16, v13, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v14, v20
	v_mad_u64_u32 v[20:21], null, 0x4e441529, v23, v[14:15]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v14, v21
	v_mad_u64_u32 v[21:22], null, 0xa2f9836e, v23, v[14:15]
	v_cndmask_b32_e64 v14, 0, 0xffffffe0, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v15, v20, v18 :: v_dual_add_nc_u32 v14, v14, v24
	v_dual_cndmask_b32 v21, v21, v19 :: v_dual_cndmask_b32 v20, v22, v20
	v_cndmask_b32_e32 v19, v19, v17, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_eq_u32_e32 vcc_lo, 0, v14
	v_cndmask_b32_e64 v18, v21, v15, s0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v20, v20, v21, s0
	v_cndmask_b32_e64 v15, v15, v19, s0
	v_sub_nc_u32_e32 v21, 32, v14
	v_cndmask_b32_e64 v19, v19, v16, s0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v20, v20, v18, s1
	v_cndmask_b32_e64 v18, v18, v15, s1
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v15, v15, v19, s1
	v_cndmask_b32_e64 v13, v19, v13, s1
	v_alignbit_b32 v22, v20, v18, v21
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_alignbit_b32 v17, v18, v15, v21
	v_cndmask_b32_e32 v14, v22, v20, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v20, v15, v13, v21
	v_cndmask_b32_e32 v16, v17, v18, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_bfe_u32 v17, v14, 29, 1
	v_cndmask_b32_e32 v15, v20, v15, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v18, v14, v16, 30
	v_sub_nc_u32_e32 v19, 0, v17
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_alignbit_b32 v16, v16, v15, 30
	v_alignbit_b32 v13, v15, v13, 30
	v_xor_b32_e32 v18, v18, v19
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v15, v16, v19
	v_xor_b32_e32 v13, v13, v19
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_clz_i32_u32_e32 v20, v18
	v_min_u32_e32 v20, 32, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v16, 31, v20
	v_lshlrev_b32_e32 v22, 23, v20
	v_alignbit_b32 v18, v18, v15, v16
	v_alignbit_b32 v13, v15, v13, v16
	v_lshrrev_b32_e32 v16, 29, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_alignbit_b32 v15, v18, v13, 9
	v_lshlrev_b32_e32 v16, 31, v16
	v_lshrrev_b32_e32 v18, 9, v18
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_clz_i32_u32_e32 v19, v15
	v_or_b32_e32 v21, 0.5, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_min_u32_e32 v19, 32, v19
	v_sub_nc_u32_e32 v21, v21, v22
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v23, 31, v19
	v_alignbit_b32 v13, v15, v13, v23
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_or_b32_e32 v15, v18, v21
	v_add_lshl_u32 v18, v19, v20, 23
	v_lshrrev_b32_e32 v13, 9, v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v19, 0x3fc90fda, v15
	v_sub_nc_u32_e32 v13, v13, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v18, 0x3fc90fda, v15, -v19
	v_add_nc_u32_e32 v13, 0x33000000, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmamk_f32 v15, v15, 0x33a22168, v18
	v_or_b32_e32 v13, v13, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v15, 0x3fc90fda, v13
	v_lshrrev_b32_e32 v14, 30, v14
	v_dual_add_f32 v13, v19, v15 :: v_dual_add_nc_u32 v14, v17, v14
.LBB3_11:                               ; %Flow69
	s_and_not1_saveexec_b32 s0, s5
; %bb.12:
	v_rndne_f32_e32 v14, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v13, 0xbfc90fda, v14, |v5|
	v_fmamk_f32 v13, v14, 0xb3a22168, v13
	s_delay_alu instid0(VALU_DEP_1)
	v_fmamk_f32 v13, v14, 0xa7c234c4, v13
	v_cvt_i32_f32_e32 v14, v14
; %bb.13:                               ; %_ZL4sinff.exit
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v15, v10, v10 :: v_dual_mul_f32 v16, v13, v13
	s_mov_b32 s0, 0xb94c1982
	s_mov_b32 s1, 0x37d75334
	v_dual_fmaak_f32 v17, s0, v15, 0x3c0881c4 :: v_dual_lshlrev_b32 v22, 30, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_dual_fmaak_f32 v20, s1, v16, 0xbab64f3b :: v_dual_and_b32 v21, 1, v11
	v_and_b32_e32 v14, 1, v14
	v_lshlrev_b32_e32 v11, 30, v11
	v_fmaak_f32 v17, v15, v17, 0xbe2aaa9d
	v_fmaak_f32 v18, s1, v15, 0xbab64f3b
	v_cmp_eq_u32_e32 vcc_lo, 0, v21
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_and_b32_e32 v11, 0x80000000, v11
	v_mul_f32_e32 v17, v15, v17
	v_fmaak_f32 v19, s0, v16, 0x3c0881c4
	v_fmaak_f32 v18, v15, v18, 0x3d2aabf7
	v_add_co_u32 v2, s0, s2, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_fmac_f32 v10, v10, v17 :: v_dual_fmaak_f32 v19, v16, v19, 0xbe2aaa9d
	v_fmaak_f32 v18, v15, v18, 0xbf000004
	v_and_b32_e32 v17, 0x80000000, v22
	v_add_co_ci_u32_e64 v3, s0, s3, v3, s0
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v19, v16, v19
	v_fmaak_f32 v20, v16, v20, 0x3d2aabf7
	v_fma_f32 v15, v15, v18, 1.0
	v_dual_fmac_f32 v13, v13, v19 :: v_dual_fmaak_f32 v20, v16, v20, 0xbf000004
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v10, -v10, v15, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 0, v14
	v_xor_b32_e32 v14, v6, v17
	v_fma_f32 v16, v16, v20, 1.0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v10, v11, v10
	v_cndmask_b32_e32 v13, v16, v13, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v5, 0x1f8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor3_b32 v11, v14, v13, v5
	v_cndmask_b32_e32 v11, 0x7fc00000, v11, vcc_lo
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_cndmask_b32 v10, 0x7fc00000, v10 :: v_dual_mul_f32 v11, v12, v11
	v_fma_f32 v9, v9, v10, -v11
                                        ; implicit-def: $vgpr11
                                        ; implicit-def: $vgpr10
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
	v_mul_f32_e32 v9, v4, v9
	global_store_b32 v[2:3], v9, off offset:4
	global_load_b32 v9, v[0:1], off
	s_and_saveexec_b32 s0, s4
	s_xor_b32 s3, exec_lo, s0
	s_cbranch_execz .LBB3_15
; %bb.14:
	s_mov_b32 s0, 0x7fffff
	v_mov_b32_e32 v12, 0
	v_and_or_b32 v20, v6, s0, 0x800000
	v_add_nc_u32_e32 v18, 0xffffff88, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[10:11], null, 0xfe5163ab, v20, 0
	v_cmp_lt_u32_e64 s0, 63, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v19, 0, 0xffffffc0, s0
	v_mad_u64_u32 v[13:14], null, 0x3c439041, v20, v[11:12]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v19, v19, v18
	v_mov_b32_e32 v11, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_lt_u32_e64 s1, 31, v19
	v_mad_u64_u32 v[14:15], null, 0xdb629599, v20, v[11:12]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v21, 0, 0xffffffe0, s1
	v_add_nc_u32_e32 v21, v21, v19
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mov_b32_e32 v11, v15
	v_cndmask_b32_e64 v10, v14, v10, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_lt_u32_e64 s2, 31, v21
	v_mad_u64_u32 v[15:16], null, 0xf534ddc0, v20, v[11:12]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v11, v16
	v_cndmask_b32_e64 v13, v15, v13, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[16:17], null, 0xfc2757d1, v20, v[11:12]
	v_cndmask_b32_e64 v10, v13, v10, s1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v11, v17
	v_mad_u64_u32 v[17:18], null, 0x4e441529, v20, v[11:12]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v11, v18
	v_mad_u64_u32 v[18:19], null, 0xa2f9836e, v20, v[11:12]
	v_cndmask_b32_e64 v11, 0, 0xffffffe0, s2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v12, v17, v15, s0
	v_add_nc_u32_e32 v11, v11, v21
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v18, v18, v16, s0
	v_cndmask_b32_e64 v17, v19, v17, s0
	v_cndmask_b32_e64 v16, v16, v14, s0
	v_cmp_eq_u32_e64 s0, 0, v11
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v15, v18, v12, s1
	v_cndmask_b32_e64 v17, v17, v18, s1
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v12, v12, v16, s1
	v_sub_nc_u32_e32 v18, 32, v11
	v_cndmask_b32_e64 v16, v16, v13, s1
	v_cndmask_b32_e64 v17, v17, v15, s2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v15, v15, v12, s2
	v_cndmask_b32_e64 v12, v12, v16, s2
	v_cndmask_b32_e64 v10, v16, v10, s2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v19, v17, v15, v18
	v_alignbit_b32 v14, v15, v12, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v11, v19, v17, s0
	v_alignbit_b32 v17, v12, v10, v18
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v13, v14, v15, s0
	v_bfe_u32 v14, v11, 29, 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v12, v17, v12, s0
	v_alignbit_b32 v15, v11, v13, 30
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v16, 0, v14
	v_alignbit_b32 v13, v13, v12, 30
	v_alignbit_b32 v10, v12, v10, 30
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v15, v15, v16
	v_xor_b32_e32 v12, v13, v16
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v10, v10, v16
	v_clz_i32_u32_e32 v17, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_min_u32_e32 v17, 32, v17
	v_sub_nc_u32_e32 v13, 31, v17
	v_lshlrev_b32_e32 v19, 23, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_alignbit_b32 v15, v15, v12, v13
	v_alignbit_b32 v10, v12, v10, v13
	v_lshrrev_b32_e32 v13, 29, v11
	v_lshrrev_b32_e32 v11, 30, v11
	v_alignbit_b32 v12, v15, v10, 9
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_lshlrev_b32_e32 v13, 31, v13
	v_lshrrev_b32_e32 v15, 9, v15
	v_add_nc_u32_e32 v11, v14, v11
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_clz_i32_u32_e32 v16, v12
	v_or_b32_e32 v18, 0.5, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_min_u32_e32 v16, 32, v16
	v_sub_nc_u32_e32 v18, v18, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v20, 31, v16
	v_alignbit_b32 v10, v12, v10, v20
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_or_b32_e32 v12, v15, v18
	v_add_lshl_u32 v15, v16, v17, 23
	v_lshrrev_b32_e32 v10, 9, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v16, 0x3fc90fda, v12
	v_sub_nc_u32_e32 v10, v10, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v15, 0x3fc90fda, v12, -v16
	v_add_nc_u32_e32 v10, 0x33000000, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmamk_f32 v12, v12, 0x33a22168, v15
	v_or_b32_e32 v10, v10, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v12, 0x3fc90fda, v10
	v_add_f32_e32 v10, v16, v12
.LBB3_15:                               ; %Flow68
	s_and_not1_saveexec_b32 s0, s3
; %bb.16:
	v_rndne_f32_e32 v11, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v10, 0xbfc90fda, v11, |v5|
	v_fmamk_f32 v10, v11, 0xb3a22168, v10
	s_delay_alu instid0(VALU_DEP_1)
	v_fmamk_f32 v10, v11, 0xa7c234c4, v10
	v_cvt_i32_f32_e32 v11, v11
; %bb.17:                               ; %_ZL4sinff.exit43
	s_or_b32 exec_lo, exec_lo, s0
	global_load_b32 v0, v[0:1], off offset:4
                                        ; implicit-def: $vgpr12
                                        ; implicit-def: $vgpr1
	s_and_saveexec_b32 s0, s4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s3, exec_lo, s0
	s_cbranch_execz .LBB3_19
; %bb.18:
	s_mov_b32 s0, 0x7fffff
	v_mov_b32_e32 v14, 0
	v_and_or_b32 v1, v6, s0, 0x800000
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[12:13], null, 0xfe5163ab, v1, 0
	v_mad_u64_u32 v[15:16], null, 0x3c439041, v1, v[13:14]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v13, v16
	v_mad_u64_u32 v[16:17], null, 0xdb629599, v1, v[13:14]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v13, v17
	v_mad_u64_u32 v[17:18], null, 0xf534ddc0, v1, v[13:14]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v13, v18 :: v_dual_add_nc_u32 v18, 0xffffff88, v7
	v_mad_u64_u32 v[7:8], null, 0xfc2757d1, v1, v[13:14]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_u32_e64 s0, 63, v18
	v_cndmask_b32_e64 v19, 0, 0xffffffc0, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mov_b32_e32 v13, v8
	v_cndmask_b32_e64 v12, v16, v12, s0
	v_add_nc_u32_e32 v8, v19, v18
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[18:19], null, 0x4e441529, v1, v[13:14]
	v_cmp_lt_u32_e64 s1, 31, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v20, 0, 0xffffffe0, s1
	v_dual_mov_b32 v13, v19 :: v_dual_add_nc_u32 v8, v20, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[19:20], null, 0xa2f9836e, v1, v[13:14]
	v_cndmask_b32_e64 v13, v18, v17, s0
	v_cmp_lt_u32_e64 s2, 31, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v14, v19, v7, s0
	v_cndmask_b32_e64 v1, 0, 0xffffffe0, s2
	v_cndmask_b32_e64 v18, v20, v18, s0
	v_cndmask_b32_e64 v7, v7, v16, s0
	s_delay_alu instid0(VALU_DEP_3)
	v_add_nc_u32_e32 v1, v1, v8
	v_cndmask_b32_e64 v8, v17, v15, s0
	v_cndmask_b32_e64 v15, v14, v13, s1
	v_cndmask_b32_e64 v14, v18, v14, s1
	v_cndmask_b32_e64 v13, v13, v7, s1
	v_sub_nc_u32_e32 v17, 32, v1
	v_cndmask_b32_e64 v7, v7, v8, s1
	v_cmp_eq_u32_e64 s0, 0, v1
	v_cndmask_b32_e64 v14, v14, v15, s2
	v_cndmask_b32_e64 v15, v15, v13, s2
	v_cndmask_b32_e64 v8, v8, v12, s1
	v_cndmask_b32_e64 v13, v13, v7, s2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v18, v14, v15, v17
	v_cndmask_b32_e64 v7, v7, v8, s2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v16, v15, v13, v17
	v_cndmask_b32_e64 v1, v18, v14, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v12, v16, v15, s0
	v_alignbit_b32 v16, v13, v7, v17
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_bfe_u32 v14, v1, 29, 1
	v_alignbit_b32 v8, v1, v12, 30
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v13, v16, v13, s0
	v_sub_nc_u32_e32 v15, 0, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_alignbit_b32 v12, v12, v13, 30
	v_alignbit_b32 v7, v13, v7, 30
	v_xor_b32_e32 v8, v8, v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v12, v12, v15
	v_xor_b32_e32 v7, v7, v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_clz_i32_u32_e32 v16, v8
	v_min_u32_e32 v16, 32, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v13, 31, v16
	v_lshlrev_b32_e32 v18, 23, v16
	v_alignbit_b32 v8, v8, v12, v13
	v_alignbit_b32 v7, v12, v7, v13
	v_lshrrev_b32_e32 v13, 29, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_alignbit_b32 v12, v8, v7, 9
	v_lshlrev_b32_e32 v13, 31, v13
	v_lshrrev_b32_e32 v8, 9, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_clz_i32_u32_e32 v15, v12
	v_or_b32_e32 v17, 0.5, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_min_u32_e32 v15, 32, v15
	v_sub_nc_u32_e32 v17, v17, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v19, 31, v15
	v_or_b32_e32 v8, v8, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_alignbit_b32 v7, v12, v7, v19
	v_add_lshl_u32 v12, v15, v16, 23
	v_mul_f32_e32 v15, 0x3fc90fda, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshrrev_b32_e32 v7, 9, v7
	v_sub_nc_u32_e32 v7, v7, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v12, 0x3fc90fda, v8, -v15
	v_add_nc_u32_e32 v7, 0x33000000, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmamk_f32 v8, v8, 0x33a22168, v12
	v_or_b32_e32 v7, v7, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v8, 0x3fc90fda, v7
	v_lshrrev_b32_e32 v7, 30, v1
	v_dual_add_f32 v1, v15, v8 :: v_dual_add_nc_u32 v12, v14, v7
                                        ; implicit-def: $vgpr8
.LBB3_19:                               ; %Flow
	s_and_not1_saveexec_b32 s0, s3
; %bb.20:
	v_rndne_f32_e32 v7, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v1, 0xbfc90fda, v7, |v5|
	v_cvt_i32_f32_e32 v12, v7
	v_fmamk_f32 v1, v7, 0xb3a22168, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_fmamk_f32 v1, v7, 0xa7c234c4, v1
; %bb.21:                               ; %_ZL4cosff.exit49
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v7, v10, v10 :: v_dual_mul_f32 v8, v1, v1
	s_mov_b32 s0, 0xb94c1982
	s_mov_b32 s1, 0x37d75334
	v_dual_fmaak_f32 v13, s0, v7, 0x3c0881c4 :: v_dual_and_b32 v18, 1, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_dual_fmaak_f32 v16, s1, v8, 0xbab64f3b :: v_dual_lshlrev_b32 v17, 30, v11
	v_lshlrev_b32_e32 v12, 30, v12
	v_and_b32_e32 v11, 1, v11
	v_fmaak_f32 v13, v7, v13, 0xbe2aaa9d
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_dual_fmaak_f32 v14, s1, v7, 0xbab64f3b :: v_dual_mul_f32 v13, v7, v13
	v_fmaak_f32 v15, s0, v8, 0x3c0881c4
	v_cmp_eq_u32_e64 s0, 0, v18
	v_dual_fmac_f32 v10, v10, v13 :: v_dual_fmaak_f32 v15, v8, v15, 0xbe2aaa9d
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fmaak_f32 v14, v7, v14, 0x3d2aabf7
	v_and_b32_e32 v13, 0x80000000, v17
	v_mul_f32_e32 v15, v8, v15
	v_fmaak_f32 v16, v8, v16, 0x3d2aabf7
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fmaak_f32 v14, v7, v14, 0xbf000004
	v_xor_b32_e32 v6, v6, v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_fmac_f32 v1, v1, v15 :: v_dual_fmaak_f32 v16, v8, v16, 0xbf000004
	v_fma_f32 v7, v7, v14, 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v8, v8, v16, 1.0
	v_cndmask_b32_e64 v1, -v1, v8, s0
	v_and_b32_e32 v8, 0x80000000, v12
	v_cmp_eq_u32_e64 s0, 0, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v1, v8, v1
	v_cndmask_b32_e64 v7, v7, v10, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v1, 0x7fc00000, v1, vcc_lo
	v_xor3_b32 v5, v6, v7, v5
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v0, v0, v1
	v_cndmask_b32_e32 v5, 0x7fc00000, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v0, v9, v5
	v_mul_f32_e32 v0, v4, v0
	global_store_b32 v[2:3], v0, off
.LBB3_22:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _ZL20PhaseShiftBackFft_1dP15HIP_vector_typeIfLj2EES1_i
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 25
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._ZL20PhaseShiftBackFft_1dP15HIP_vector_typeIfLj2EES1_i,"axG",@progbits,_ZL20PhaseShiftBackFft_1dP15HIP_vector_typeIfLj2EES1_i,comdat
.Lfunc_end3:
	.size	_ZL20PhaseShiftBackFft_1dP15HIP_vector_typeIfLj2EES1_i, .Lfunc_end3-_ZL20PhaseShiftBackFft_1dP15HIP_vector_typeIfLj2EES1_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 4184
; NumSgprs: 18
; NumVgprs: 25
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 3
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 25
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _ZL32DataTypeConvertFloatToComplex_1dPfP15HIP_vector_typeIfLj2EEi
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _ZL32DataTypeConvertFloatToComplex_1dPfP15HIP_vector_typeIfLj2EEi.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     5
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _ZL17DataGetBackFft_1dP15HIP_vector_typeIfLj2EEPffi
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _ZL17DataGetBackFft_1dP15HIP_vector_typeIfLj2EEPffi.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     9
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _ZL20PhaseShiftForwFft_1dP15HIP_vector_typeIfLj2EES1_i
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _ZL20PhaseShiftForwFft_1dP15HIP_vector_typeIfLj2EES1_i.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     25
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _ZL20PhaseShiftBackFft_1dP15HIP_vector_typeIfLj2EES1_i
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _ZL20PhaseShiftBackFft_1dP15HIP_vector_typeIfLj2EES1_i.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     25
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
