/* ==================================================================
  Programmers: Conner Wulf (connerwulf@mail.usf.edu),
               Derek Rodriguez (derek23@mail.usf.edu)
	             David Hoambrecker (david106@mail.usf.edu)

  To Compile use: nvcc -o queens proj3-Nqueens.cu
  you can specify the board size by compiling with: nvcc  -o queens proj3-Nqueens.cu -DNUM=a
  * where a must be >= 4 and <= 22

  The program reads in 2 arguments, the first is the number of tuples generated by blockIdx.x
                                    the second is the number of groups of columns, size multiple of board size.
                                    ex. ./queens 4 1000 (based on board size is 12)
   ==================================================================
*/

#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <string.h>
#include <sys/time.h>
#include <iostream>
#include <cuda_runtime.h>
#include <cuda.h>
#include <vector>

using namespace std;
static int total = 0;
unsigned long count = 0;
long *answer;
struct timezone Idunno;
struct timeval startTime, endTime;

 #ifndef NUM
 #define NUM 12
 #endif

//CPU helper function to test is a queen can be placed
int isAllowed(int **board, int row, int col, int n)
{
  int x,y;

  //left check
  for (x = 0; x < col; x++)
  {
    if(board[row][x] == 1)
    {
      return 0;
    }
  }
  //check left diagonal up
  for(x = row, y = col; x >= 0 && y >= 0; x--, y--)
    {
      if (board[x][y] == 1)
      {
        return 0;
      }
    }
  for(x = row, y = col; x < n && y >= 0; x++, y--)
  {
    if (board[x][y] == 1)
    {
      return 0;
    }
  }
 return 1;
}
// CPU Solver for N-queens problem
int Solver(int **board, int col, int n)
{
  if (col >= n)
  {
    total++;
    return 1;
  }

  int nextState = 0;

  for(int k = 0; k < n; k++)
  {
    if (isAllowed(board,k,col, n))
    {
      board[k][col] = 1;
      nextState = Solver(board, col + 1, n);
      board[k][col] = 0;
    }
  }
  return nextState;
}

// GPU parallel kernel for N-Queens
__global__ void kernel(long *answer, int SegSize, int nBX, int nBY, int genNum)
{
  __shared__ long sol[NUM][NUM];
  __shared__ char tup[NUM][NUM][NUM];

  int wrongCount = 0;
  sol[threadIdx.x][threadIdx.y] = 0;
  tup[threadIdx.x][threadIdx.y][0] = blockIdx.y % SegSize;
  int totalGenerated = powf(NUM, genNum);
  int blockYSeg = blockIdx.y / SegSize;
  int workLoad = totalGenerated / nBY;
  int runOff = totalGenerated - workLoad *nBY;




  int temp = blockIdx.x;
  for(int x = 1; x <=nBX; x++)
  {
    tup[threadIdx.x][threadIdx.y][x] = temp % NUM;
    temp = temp / NUM;

  }

  int tupCount = nBX;
  tup[threadIdx.x][threadIdx.y][++tupCount] = threadIdx.x;
  tup[threadIdx.x][threadIdx.y][++tupCount] = threadIdx.y;

  for(int k = tupCount; k > 0; k--)
  {
    for(int m = k - 1, counter = 1; m >= 0; counter++, m--)
    {
      //Checks diagonal left, down
      wrongCount += (tup[threadIdx.x][threadIdx.y][k] + counter) == tup[threadIdx.x][threadIdx.y][m];
      //Checks row its in
      wrongCount += tup[threadIdx.x][threadIdx.y][k] == tup[threadIdx.x][threadIdx.y][m];
      // Checks diagonal left, up
      wrongCount  += (tup[threadIdx.x][threadIdx.y][k] - counter) == tup[threadIdx.x][threadIdx.y][m];

    }
  }






  if (wrongCount == 0)
  {
    int begin = blockYSeg * workLoad;
    for(int c = begin; c < begin + workLoad + (blockYSeg == nBY - 1) * runOff; c++)
    {
      //last values is made in tuple, convert and store to tup array
      int temp = c;
      for(int q = 0, z =tupCount + 1; q < genNum; z++, q++)
      {
        tup[threadIdx.x][threadIdx.y][q] = temp % NUM;
        temp = temp / NUM;
      }

      //checks that the genNum tuple values are indeed unique (saves work overall)
      for(int a = 0; a < genNum && wrongCount == 0; a++){
				for(int b = 0; b < genNum && wrongCount == 0; b++){
					wrongCount += tup[threadIdx.x][threadIdx.y][tupCount + 1 + a] == tup[threadIdx.x][threadIdx.y][tupCount + 1 + b] && a != b;
				}
			}

      for(int k = NUM -1; k > wrongCount; k--)
      {
        for(int m = k - 1, counter = 1; m >= 0; counter++, m--)
        {
          //Checks diagonal left, down
          wrongCount += (tup[threadIdx.x][threadIdx.y][k] + counter) == tup[threadIdx.x][threadIdx.y][m];
          //Checks row its in
          wrongCount += tup[threadIdx.x][threadIdx.y][k] == tup[threadIdx.x][threadIdx.y][m];
          // Checks diagonal left, up
          wrongCount  += (tup[threadIdx.x][threadIdx.y][k] - counter) == tup[threadIdx.x][threadIdx.y][m];

        }
      }

      sol[threadIdx.x][threadIdx.y] += !(wrongCount);
      wrongCount = 0;

    }
  }

  __syncthreads();

    // sum all threads in block to get total
  	if(threadIdx.x == 0 && threadIdx.y == 0)
    {

  		long total = 0;

  		for(int i =0; i < NUM; i++){
  			for(int j = 0; j < NUM; j++){
  				total += sol[i][j];
  			}
  		}
  		answer[gridDim.x * blockIdx.y + blockIdx.x] = total;
  	}


  	__syncthreads();
}


double report_running_time() {
	long sec_diff, usec_diff;
	gettimeofday(&endTime, &Idunno);
	sec_diff = endTime.tv_sec - startTime.tv_sec;
	usec_diff= endTime.tv_usec-startTime.tv_usec;
	if(usec_diff < 0) {
		sec_diff --;
		usec_diff += 1000000;
	}
	printf("CPU Time: %ld.%06ld\n", sec_diff, usec_diff);
	return (double)(sec_diff*1.0 + usec_diff/1000000.0);
}


int main(int argc, char **argv) {

  if(argc < 3) {

    printf("\nError, too few arguments. Usage: ./CHANGE THIS\n");
    return -1;
  }

  const int NUM_TUPLEX = atoi(argv[1]);
  const int NUM_TUPLEY = atoi(argv[2]);
  const int generatedNum = NUM - 3 - NUM_TUPLEX;
  cudaEvent_t start, stop;
  float elapsedTime;

  if(generatedNum < 0){
    printf("\nThe numbers generated iteratively cannot be less than 0.\n");
    exit(1);
  }

  //ensure N is in the correct range
  if(NUM < 4  || NUM > 22){
    printf("\nN(%d) must be between 4 and 22 inclusive\n", NUM);
    exit(1);
  }

  //ensure that at least one of the tuple values is generated by the block's X coordinate value
  if(NUM_TUPLEX < 1){
    printf("\nThe number of tuples generated by each block's X coordinate value must be >= 1\n");
    exit(1);
  }

  	//ensure that the number of Y segments that the numGen work is divided into
  	//is at least one per work segment
  	if(NUM_TUPLEY > pow(NUM, generatedNum)){
  		printf("\n number of groups of columns must be less than or equal to N^(N - 3 - (1st ARG))\n");
  		exit(1);
  	}

  //CPU setup
  int **board;
  board = (int **) malloc(NUM * sizeof(int *));

  for (int i = 0; i < NUM; i++) {
    board[i] = (int *) malloc(NUM * sizeof(int));

  }
  for (int i = 0; i < NUM; i++) {
    for (int j = 0; j < NUM; j++) {
      board[i][j] = 0;

    }
  }

  int WIDTH, HEIGHT, NUM_BLOCKS, YSegmentSize;
  WIDTH = pow(NUM, NUM_TUPLEX);
  YSegmentSize = (NUM / 2) + (NUM % 2);
  HEIGHT = YSegmentSize + NUM_TUPLEY;
  NUM_BLOCKS = WIDTH * HEIGHT;


  long *d_answer;
  answer = new long[NUM_BLOCKS];

  cudaMalloc((void **) &d_answer, sizeof(long) * NUM_BLOCKS);

  dim3 block(NUM, NUM); //threads w x h
  dim3 grid(WIDTH, HEIGHT); //blocks w x h

  cudaEventCreate(&start);
  cudaEventCreate(&stop);
  cudaEventRecord(start, 0);

  kernel<<<grid, block>>>(d_answer, YSegmentSize, NUM_TUPLEX, NUM_TUPLEY, generatedNum);
  cudaThreadSynchronize();

  cudaEventRecord(stop, 0);
  cudaEventSynchronize(stop);
  cudaEventElapsedTime(&elapsedTime, start, stop);

  cudaMemcpy(answer,d_answer, sizeof(long) * NUM_BLOCKS, cudaMemcpyDeviceToHost);





	srand(1);
  gettimeofday(&startTime, &Idunno);
  Solver(board, 0, NUM);


  printf("\nTotal Solutions: %d boards\n\n",total);
  report_running_time();
  printf("GPU Time: %f secs\n", (elapsedTime / 1000.00));
  return 0;

}

	.file	"tmpxft_003327ab_00000000-6_FinalProject-NQueens.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4004:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE4004:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z9isAllowedPPiiii
	.type	_Z9isAllowedPPiiii, @function
_Z9isAllowedPPiiii:
.LFB3998:
	.cfi_startproc
	endbr64
	movl	%ecx, %r9d
	movslq	%esi, %rcx
	movl	%edx, %eax
	xorl	%edx, %edx
	leaq	(%rdi,%rcx,8), %r8
.L3:
	cmpl	%edx, %eax
	jle	.L22
	movq	(%r8), %r10
	movl	(%r10,%rdx,4), %r10d
	incq	%rdx
	decl	%r10d
	jne	.L3
	xorl	%eax, %eax
	ret
.L22:
	movslq	%eax, %rdx
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	movl	%eax, %r11d
	movq	%rcx, %r8
	salq	$2, %rdx
	subl	%esi, %r11d
	movq	%rdx, %r10
.L6:
	movl	%r11d, %ebx
	addl	%r8d, %ebx
	js	.L15
	testl	%r8d, %r8d
	js	.L15
	movq	(%rdi,%r8,8), %rbx
	decq	%r8
	movl	(%rbx,%r10), %ebx
	subq	$4, %r10
	decl	%ebx
	jne	.L6
	jmp	.L14
.L15:
	addl	%esi, %eax
.L9:
	cmpl	%ecx, %eax
	js	.L16
	cmpl	%ecx, %r9d
	jle	.L16
	movq	(%rdi,%rcx,8), %rsi
	incq	%rcx
	movl	(%rsi,%rdx), %esi
	subq	$4, %rdx
	decl	%esi
	jne	.L9
	jmp	.L14
.L16:
	movl	$1, %eax
	jmp	.L2
.L14:
	xorl	%eax, %eax
.L2:
	popq	%rbx
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3998:
	.size	_Z9isAllowedPPiiii, .-_Z9isAllowedPPiiii
	.globl	_Z6SolverPPiii
	.type	_Z6SolverPPiii, @function
_Z6SolverPPiii:
.LFB3999:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$24, %rsp
	.cfi_def_cfa_offset 80
	cmpl	%edx, %esi
	jge	.L24
	movslq	%esi, %r14
	movq	%rdi, %r13
	movl	%esi, %ebp
	movl	%edx, %ebx
	leaq	0(,%r14,4), %rax
	xorl	%r15d, %r15d
	xorl	%r12d, %r12d
	movq	%rax, (%rsp)
	leal	1(%rsi), %eax
	movl	%eax, 12(%rsp)
	jmp	.L25
.L24:
	incl	_ZL5total(%rip)
	movl	$1, %r12d
	jmp	.L23
.L28:
	movl	%ebx, %ecx
	movl	%ebp, %edx
	movq	%r13, %rdi
	call	_Z9isAllowedPPiiii
	testl	%eax, %eax
	je	.L27
	movq	(%rsp), %r14
	addq	0(%r13,%r15,8), %r14
	movl	%ebx, %edx
	movl	$1, (%r14)
	movl	12(%rsp), %esi
	call	_Z6SolverPPiii
	movl	%eax, %r12d
	xorl	%eax, %eax
	movl	%eax, (%r14)
.L27:
	incq	%r15
.L25:
	movl	%r15d, %esi
	cmpl	%r15d, %ebx
	jg	.L28
.L23:
	addq	$24, %rsp
	.cfi_def_cfa_offset 56
	movl	%r12d, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3999:
	.size	_Z6SolverPPiii, .-_Z6SolverPPiii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"CPU Time: %ld.%06ld\n"
	.text
	.globl	_Z19report_running_timev
	.type	_Z19report_running_timev, @function
_Z19report_running_timev:
.LFB4000:
	.cfi_startproc
	endbr64
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	leaq	Idunno(%rip), %rsi
	leaq	endTime(%rip), %rdi
	pushq	%rbx
	.cfi_def_cfa_offset 24
	.cfi_offset 3, -24
	pushq	%rdx
	.cfi_def_cfa_offset 32
	call	gettimeofday@PLT
	movq	endTime(%rip), %rbp
	movq	8+endTime(%rip), %rbx
	subq	startTime(%rip), %rbp
	subq	8+startTime(%rip), %rbx
	jns	.L34
	decq	%rbp
	addq	$1000000, %rbx
.L34:
	movq	%rbx, %rcx
	movq	%rbp, %rdx
	leaq	.LC0(%rip), %rsi
	xorl	%eax, %eax
	movl	$2, %edi
	call	__printf_chk@PLT
	cvtsi2sdq	%rbp, %xmm1
	cvtsi2sdq	%rbx, %xmm0
	divsd	.LC1(%rip), %xmm0
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	addsd	%xmm1, %xmm0
	ret
	.cfi_endproc
.LFE4000:
	.size	_Z19report_running_timev, .-_Z19report_running_timev
	.globl	_Z29__device_stub__Z6kernelPliiiiPliiii
	.type	_Z29__device_stub__Z6kernelPliiiiPliiii, @function
_Z29__device_stub__Z6kernelPliiiiPliiii:
.LFB4026:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rdi
	movl	%esi, 20(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 16(%rsp)
	leaq	32(%rsp), %rdx
	movl	%ecx, 12(%rsp)
	leaq	40(%rsp), %rcx
	movl	%r8d, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L36
	pushq	40(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z6kernelPliiii(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 176
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L36:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L38
	call	__stack_chk_fail@PLT
.L38:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4026:
	.size	_Z29__device_stub__Z6kernelPliiiiPliiii, .-_Z29__device_stub__Z6kernelPliiiiPliiii
	.globl	_Z6kernelPliiii
	.type	_Z6kernelPliiii, @function
_Z6kernelPliiii:
.LFB4027:
	.cfi_startproc
	endbr64
	jmp	_Z29__device_stub__Z6kernelPliiiiPliiii
	.cfi_endproc
.LFE4027:
	.size	_Z6kernelPliiii, .-_Z6kernelPliiii
	.section	.rodata.str1.1
.LC2:
	.string	"\nError, too few arguments. Usage: ./CHANGE THIS\n"
.LC3:
	.string	"\nThe numbers generated iteratively cannot be less than 0.\n"
.LC4:
	.string	"\nThe number of tuples generated by each block's X coordinate value must be >= 1\n"
.LC6:
	.string	"\n number of groups of columns must be less than or equal to N^(N - 3 - (1st ARG))\n"
.LC7:
	.string	"\nTotal Solutions: %d boards\n\n"
.LC9:
	.string	"GPU Time: %f secs\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB4001:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$88, %rsp
	.cfi_def_cfa_offset 144
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	xorl	%eax, %eax
	cmpl	$2, %edi
	jg	.L42
	leaq	.LC2(%rip), %rsi
	movl	$2, %edi
	call	__printf_chk@PLT
	orl	$-1, %eax
	jmp	.L41
.L42:
	movq	8(%rsi), %rdi
	movq	%rsi, %rbx
	movl	$9, %r14d
	call	atoi@PLT
	movq	16(%rbx), %rdi
	movl	%eax, %ebp
	call	atoi@PLT
	subl	%ebp, %r14d
	leaq	.LC3(%rip), %rsi
	movl	%eax, %r13d
	js	.L61
	testl	%ebp, %ebp
	jg	.L45
	leaq	.LC4(%rip), %rsi
.L61:
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movl	$1, %edi
	call	exit@PLT
.L45:
	cvtsi2sdl	%r14d, %xmm1
	movsd	.LC5(%rip), %xmm0
	call	pow@PLT
	cvtsi2sdl	%r13d, %xmm1
	leaq	.LC6(%rip), %rsi
	comisd	%xmm0, %xmm1
	ja	.L61
	movl	$96, %edi
	xorl	%ebx, %ebx
	call	malloc@PLT
	movq	%rax, %r12
.L48:
	movl	$48, %edi
	call	malloc@PLT
	movq	%rax, (%r12,%rbx,8)
	incq	%rbx
	cmpq	$12, %rbx
	jne	.L48
	xorl	%edx, %edx
	xorl	%eax, %eax
.L49:
	movq	(%r12,%rdx,8), %rdi
	movl	$12, %ecx
	incq	%rdx
	rep stosl
	cmpq	$12, %rdx
	jne	.L49
	cvtsi2sdl	%ebp, %xmm1
	movsd	.LC5(%rip), %xmm0
	leal	6(%r13), %r15d
	call	pow@PLT
	movabsq	$1152921504606846975, %rax
	cvttsd2sil	%xmm0, %edx
	movl	%edx, %ebx
	movl	%edx, 12(%rsp)
	imull	%r15d, %ebx
	movslq	%ebx, %rbx
	cmpq	%rbx, %rax
	jb	.L50
	salq	$3, %rbx
	movq	%rbx, %rdi
	call	_Znam@PLT
	movq	%rbx, %rsi
	leaq	40(%rsp), %rdi
	movq	%rax, answer(%rip)
	call	cudaMalloc@PLT
	movl	12(%rsp), %edx
	leaq	24(%rsp), %rdi
	movabsq	$51539607564, %rax
	movq	%rax, 48(%rsp)
	movl	%edx, 60(%rsp)
	movl	$1, 56(%rsp)
	movl	%r15d, 64(%rsp)
	movl	$1, 68(%rsp)
	call	cudaEventCreate@PLT
	leaq	32(%rsp), %rdi
	call	cudaEventCreate@PLT
	movq	24(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movl	56(%rsp), %ecx
	movl	68(%rsp), %esi
	xorl	%r9d, %r9d
	movq	48(%rsp), %rdx
	movq	60(%rsp), %rdi
	xorl	%r8d, %r8d
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L51
	movq	40(%rsp), %rdi
	movl	%r14d, %r8d
	movl	%r13d, %ecx
	movl	%ebp, %edx
	movl	$6, %esi
	call	_Z29__device_stub__Z6kernelPliiiiPliiii
	jmp	.L51
.L50:
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	jne	.L62
	call	__cxa_throw_bad_array_new_length@PLT
.L51:
	call	cudaThreadSynchronize@PLT
	movq	32(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movq	32(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movq	32(%rsp), %rdx
	movq	24(%rsp), %rsi
	leaq	20(%rsp), %rdi
	call	cudaEventElapsedTime@PLT
	movq	40(%rsp), %rsi
	movl	$2, %ecx
	movq	%rbx, %rdx
	movq	answer(%rip), %rdi
	call	cudaMemcpy@PLT
	movl	$1, %edi
	call	srand@PLT
	leaq	Idunno(%rip), %rsi
	leaq	startTime(%rip), %rdi
	call	gettimeofday@PLT
	movl	$12, %edx
	xorl	%esi, %esi
	movq	%r12, %rdi
	call	_Z6SolverPPiii
	movl	_ZL5total(%rip), %edx
	leaq	.LC7(%rip), %rsi
	xorl	%eax, %eax
	movl	$2, %edi
	call	__printf_chk@PLT
	call	_Z19report_running_timev
	leaq	.LC9(%rip), %rsi
	movl	$2, %edi
	movb	$1, %al
	cvtss2sd	20(%rsp), %xmm0
	divsd	.LC8(%rip), %xmm0
	call	__printf_chk@PLT
	xorl	%eax, %eax
.L41:
	movq	72(%rsp), %rdx
	subq	%fs:40, %rdx
	je	.L54
.L62:
	call	__stack_chk_fail@PLT
.L54:
	addq	$88, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4001:
	.size	main, .-main
	.section	.rodata.str1.1
.LC10:
	.string	"_Z6kernelPliiii"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4029:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC10(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z6kernelPliiii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE4029:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.globl	endTime
	.bss
	.align 16
	.type	endTime, @object
	.size	endTime, 16
endTime:
	.zero	16
	.globl	startTime
	.align 16
	.type	startTime, @object
	.size	startTime, 16
startTime:
	.zero	16
	.globl	Idunno
	.align 8
	.type	Idunno, @object
	.size	Idunno, 8
Idunno:
	.zero	8
	.globl	answer
	.align 8
	.type	answer, @object
	.size	answer, 8
answer:
	.zero	8
	.globl	count
	.align 8
	.type	count, @object
	.size	count, 8
count:
	.zero	8
	.local	_ZL5total
	.comm	_ZL5total,4,4
	.section	.rodata.cst8,"aM",@progbits,8
	.align 8
.LC1:
	.long	0
	.long	1093567616
	.align 8
.LC5:
	.long	0
	.long	1076363264
	.align 8
.LC8:
	.long	0
	.long	1083129856
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

/* ==================================================================
  Programmers: Conner Wulf (connerwulf@mail.usf.edu),
               Derek Rodriguez (derek23@mail.usf.edu)
	             David Hoambrecker (david106@mail.usf.edu)

  To Compile use: nvcc -o queens proj3-Nqueens.cu
  you can specify the board size by compiling with: nvcc  -o queens proj3-Nqueens.cu -DNUM=a
  * where a must be >= 4 and <= 22

  The program reads in 2 arguments, the first is the number of tuples generated by blockIdx.x
                                    the second is the number of groups of columns, size multiple of board size.
                                    ex. ./queens 4 1000 (based on board size is 12)
   ==================================================================
*/

#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <string.h>
#include <sys/time.h>
#include <iostream>
#include <hip/hip_runtime.h>

#include <vector>

using namespace std;
static int total = 0;
unsigned long count = 0;
long *answer;
struct timezone Idunno;
struct timeval startTime, endTime;

 #ifndef NUM
 #define NUM 12
 #endif

//CPU helper function to test is a queen can be placed
int isAllowed(int **board, int row, int col, int n)
{
  int x,y;

  //left check
  for (x = 0; x < col; x++)
  {
    if(board[row][x] == 1)
    {
      return 0;
    }
  }
  //check left diagonal up
  for(x = row, y = col; x >= 0 && y >= 0; x--, y--)
    {
      if (board[x][y] == 1)
      {
        return 0;
      }
    }
  for(x = row, y = col; x < n && y >= 0; x++, y--)
  {
    if (board[x][y] == 1)
    {
      return 0;
    }
  }
 return 1;
}
// CPU Solver for N-queens problem
int Solver(int **board, int col, int n)
{
  if (col >= n)
  {
    total++;
    return 1;
  }

  int nextState = 0;

  for(int k = 0; k < n; k++)
  {
    if (isAllowed(board,k,col, n))
    {
      board[k][col] = 1;
      nextState = Solver(board, col + 1, n);
      board[k][col] = 0;
    }
  }
  return nextState;
}

// GPU parallel kernel for N-Queens
__global__ void kernel(long *answer, int SegSize, int nBX, int nBY, int genNum)
{
  __shared__ long sol[NUM][NUM];
  __shared__ char tup[NUM][NUM][NUM];

  int wrongCount = 0;
  sol[threadIdx.x][threadIdx.y] = 0;
  tup[threadIdx.x][threadIdx.y][0] = blockIdx.y % SegSize;
  int totalGenerated = powf(NUM, genNum);
  int blockYSeg = blockIdx.y / SegSize;
  int workLoad = totalGenerated / nBY;
  int runOff = totalGenerated - workLoad *nBY;




  int temp = blockIdx.x;
  for(int x = 1; x <=nBX; x++)
  {
    tup[threadIdx.x][threadIdx.y][x] = temp % NUM;
    temp = temp / NUM;

  }

  int tupCount = nBX;
  tup[threadIdx.x][threadIdx.y][++tupCount] = threadIdx.x;
  tup[threadIdx.x][threadIdx.y][++tupCount] = threadIdx.y;

  for(int k = tupCount; k > 0; k--)
  {
    for(int m = k - 1, counter = 1; m >= 0; counter++, m--)
    {
      //Checks diagonal left, down
      wrongCount += (tup[threadIdx.x][threadIdx.y][k] + counter) == tup[threadIdx.x][threadIdx.y][m];
      //Checks row its in
      wrongCount += tup[threadIdx.x][threadIdx.y][k] == tup[threadIdx.x][threadIdx.y][m];
      // Checks diagonal left, up
      wrongCount  += (tup[threadIdx.x][threadIdx.y][k] - counter) == tup[threadIdx.x][threadIdx.y][m];

    }
  }






  if (wrongCount == 0)
  {
    int begin = blockYSeg * workLoad;
    for(int c = begin; c < begin + workLoad + (blockYSeg == nBY - 1) * runOff; c++)
    {
      //last values is made in tuple, convert and store to tup array
      int temp = c;
      for(int q = 0, z =tupCount + 1; q < genNum; z++, q++)
      {
        tup[threadIdx.x][threadIdx.y][q] = temp % NUM;
        temp = temp / NUM;
      }

      //checks that the genNum tuple values are indeed unique (saves work overall)
      for(int a = 0; a < genNum && wrongCount == 0; a++){
				for(int b = 0; b < genNum && wrongCount == 0; b++){
					wrongCount += tup[threadIdx.x][threadIdx.y][tupCount + 1 + a] == tup[threadIdx.x][threadIdx.y][tupCount + 1 + b] && a != b;
				}
			}

      for(int k = NUM -1; k > wrongCount; k--)
      {
        for(int m = k - 1, counter = 1; m >= 0; counter++, m--)
        {
          //Checks diagonal left, down
          wrongCount += (tup[threadIdx.x][threadIdx.y][k] + counter) == tup[threadIdx.x][threadIdx.y][m];
          //Checks row its in
          wrongCount += tup[threadIdx.x][threadIdx.y][k] == tup[threadIdx.x][threadIdx.y][m];
          // Checks diagonal left, up
          wrongCount  += (tup[threadIdx.x][threadIdx.y][k] - counter) == tup[threadIdx.x][threadIdx.y][m];

        }
      }

      sol[threadIdx.x][threadIdx.y] += !(wrongCount);
      wrongCount = 0;

    }
  }

  __syncthreads();

    // sum all threads in block to get total
  	if(threadIdx.x == 0 && threadIdx.y == 0)
    {

  		long total = 0;

  		for(int i =0; i < NUM; i++){
  			for(int j = 0; j < NUM; j++){
  				total += sol[i][j];
  			}
  		}
  		answer[gridDim.x * blockIdx.y + blockIdx.x] = total;
  	}


  	__syncthreads();
}


double report_running_time() {
	long sec_diff, usec_diff;
	gettimeofday(&endTime, &Idunno);
	sec_diff = endTime.tv_sec - startTime.tv_sec;
	usec_diff= endTime.tv_usec-startTime.tv_usec;
	if(usec_diff < 0) {
		sec_diff --;
		usec_diff += 1000000;
	}
	printf("CPU Time: %ld.%06ld\n", sec_diff, usec_diff);
	return (double)(sec_diff*1.0 + usec_diff/1000000.0);
}


int main(int argc, char **argv) {

  if(argc < 3) {

    printf("\nError, too few arguments. Usage: ./CHANGE THIS\n");
    return -1;
  }

  const int NUM_TUPLEX = atoi(argv[1]);
  const int NUM_TUPLEY = atoi(argv[2]);
  const int generatedNum = NUM - 3 - NUM_TUPLEX;
  hipEvent_t start, stop;
  float elapsedTime;

  if(generatedNum < 0){
    printf("\nThe numbers generated iteratively cannot be less than 0.\n");
    exit(1);
  }

  //ensure N is in the correct range
  if(NUM < 4  || NUM > 22){
    printf("\nN(%d) must be between 4 and 22 inclusive\n", NUM);
    exit(1);
  }

  //ensure that at least one of the tuple values is generated by the block's X coordinate value
  if(NUM_TUPLEX < 1){
    printf("\nThe number of tuples generated by each block's X coordinate value must be >= 1\n");
    exit(1);
  }

  	//ensure that the number of Y segments that the numGen work is divided into
  	//is at least one per work segment
  	if(NUM_TUPLEY > pow(NUM, generatedNum)){
  		printf("\n number of groups of columns must be less than or equal to N^(N - 3 - (1st ARG))\n");
  		exit(1);
  	}

  //CPU setup
  int **board;
  board = (int **) malloc(NUM * sizeof(int *));

  for (int i = 0; i < NUM; i++) {
    board[i] = (int *) malloc(NUM * sizeof(int));

  }
  for (int i = 0; i < NUM; i++) {
    for (int j = 0; j < NUM; j++) {
      board[i][j] = 0;

    }
  }

  int WIDTH, HEIGHT, NUM_BLOCKS, YSegmentSize;
  WIDTH = pow(NUM, NUM_TUPLEX);
  YSegmentSize = (NUM / 2) + (NUM % 2);
  HEIGHT = YSegmentSize + NUM_TUPLEY;
  NUM_BLOCKS = WIDTH * HEIGHT;


  long *d_answer;
  answer = new long[NUM_BLOCKS];

  hipMalloc((void **) &d_answer, sizeof(long) * NUM_BLOCKS);

  dim3 block(NUM, NUM); //threads w x h
  dim3 grid(WIDTH, HEIGHT); //blocks w x h

  hipEventCreate(&start);
  hipEventCreate(&stop);
  hipEventRecord(start, 0);

  kernel<<<grid, block>>>(d_answer, YSegmentSize, NUM_TUPLEX, NUM_TUPLEY, generatedNum);
  hipDeviceSynchronize();

  hipEventRecord(stop, 0);
  hipEventSynchronize(stop);
  hipEventElapsedTime(&elapsedTime, start, stop);

  hipMemcpy(answer,d_answer, sizeof(long) * NUM_BLOCKS, hipMemcpyDeviceToHost);





	srand(1);
  gettimeofday(&startTime, &Idunno);
  Solver(board, 0, NUM);


  printf("\nTotal Solutions: %d boards\n\n",total);
  report_running_time();
  printf("GPU Time: %f secs\n", (elapsedTime / 1000.00));
  return 0;

}

	.text
	.file	"FinalProject-NQueens.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z9isAllowedPPiiii              # -- Begin function _Z9isAllowedPPiiii
	.type	_Z9isAllowedPPiiii,@function
_Z9isAllowedPPiiii:                     # @_Z9isAllowedPPiiii
	.cfi_startproc
# %bb.0:
                                        # kill: def $edx killed $edx def $rdx
	testl	%edx, %edx
	jle	.LBB0_4
# %bb.1:                                # %.lr.ph
	movslq	%esi, %rax
	movq	(%rdi,%rax,8), %r8
	movl	%edx, %r9d
	xorl	%eax, %eax
	xorl	%r10d, %r10d
.LBB0_2:                                # =>This Inner Loop Header: Depth=1
	cmpl	$1, (%r8,%r10,4)
	je	.LBB0_15
# %bb.3:                                #   in Loop: Header=BB0_2 Depth=1
	incq	%r10
	cmpq	%r10, %r9
	jne	.LBB0_2
.LBB0_4:                                # %.preheader29
	movl	%esi, %eax
	orl	%edx, %eax
	js	.LBB0_9
# %bb.5:
	movl	%edx, %r8d
	movl	%esi, %eax
.LBB0_6:                                # %.lr.ph35
                                        # =>This Inner Loop Header: Depth=1
	movl	%eax, %r9d
	movq	(%rdi,%r9,8), %r9
	movl	%r8d, %r10d
	cmpl	$1, (%r9,%r10,4)
	je	.LBB0_16
# %bb.7:                                #   in Loop: Header=BB0_6 Depth=1
	testl	%eax, %eax
	jle	.LBB0_9
# %bb.8:                                #   in Loop: Header=BB0_6 Depth=1
	decl	%eax
	leal	-1(%r8), %r9d
	testl	%r8d, %r8d
	movl	%r9d, %r8d
	jg	.LBB0_6
.LBB0_9:                                # %.preheader
	movl	$1, %eax
	cmpl	%ecx, %esi
	jge	.LBB0_15
# %bb.10:                               # %.preheader
	testl	%edx, %edx
	js	.LBB0_15
# %bb.11:                               # %.lr.ph38.preheader
	movslq	%esi, %rsi
	movslq	%ecx, %rcx
	incq	%rsi
.LBB0_12:                               # %.lr.ph38
                                        # =>This Inner Loop Header: Depth=1
	movq	-8(%rdi,%rsi,8), %r8
	movl	%edx, %r9d
	cmpl	$1, (%r8,%r9,4)
	je	.LBB0_16
# %bb.13:                               #   in Loop: Header=BB0_12 Depth=1
	cmpq	%rcx, %rsi
	jge	.LBB0_15
# %bb.14:                               #   in Loop: Header=BB0_12 Depth=1
	leal	-1(%rdx), %r8d
	incq	%rsi
	testl	%edx, %edx
	movl	%r8d, %edx
	jg	.LBB0_12
.LBB0_15:                               # %.loopexit
                                        # kill: def $eax killed $eax killed $rax
	retq
.LBB0_16:
	xorl	%eax, %eax
                                        # kill: def $eax killed $eax killed $rax
	retq
.Lfunc_end0:
	.size	_Z9isAllowedPPiiii, .Lfunc_end0-_Z9isAllowedPPiiii
	.cfi_endproc
                                        # -- End function
	.globl	_Z6SolverPPiii                  # -- Begin function _Z6SolverPPiii
	.type	_Z6SolverPPiii,@function
_Z6SolverPPiii:                         # @_Z6SolverPPiii
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	pushq	%rax
	.cfi_def_cfa_offset 64
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	cmpl	%edx, %esi
	jge	.LBB1_3
# %bb.1:                                # %.preheader
	testl	%edx, %edx
	jle	.LBB1_2
# %bb.4:                                # %.lr.ph
	movl	%esi, %r14d
	movq	%rdi, %r15
	movl	%edx, 4(%rsp)                   # 4-byte Spill
	movl	%edx, %r12d
	movslq	%esi, %rbx
	leal	1(%r14), %eax
	movl	%eax, (%rsp)                    # 4-byte Spill
	xorl	%r13d, %r13d
	xorl	%ebp, %ebp
.LBB1_5:                                # =>This Inner Loop Header: Depth=1
	movq	%r15, %rdi
	movl	%r13d, %esi
	movl	%r14d, %edx
	movl	%r12d, %ecx
	callq	_Z9isAllowedPPiiii
	testl	%eax, %eax
	je	.LBB1_7
# %bb.6:                                #   in Loop: Header=BB1_5 Depth=1
	movq	(%r15,%r13,8), %rax
	movl	$1, (%rax,%rbx,4)
	movq	%r15, %rdi
	movl	(%rsp), %esi                    # 4-byte Reload
	movl	4(%rsp), %edx                   # 4-byte Reload
	callq	_Z6SolverPPiii
	movl	%eax, %ebp
	movq	(%r15,%r13,8), %rax
	movl	$0, (%rax,%rbx,4)
.LBB1_7:                                #   in Loop: Header=BB1_5 Depth=1
	incq	%r13
	cmpq	%r13, %r12
	jne	.LBB1_5
	jmp	.LBB1_8
.LBB1_3:
	incl	_ZL5total(%rip)
	movl	$1, %ebp
	jmp	.LBB1_8
.LBB1_2:
	xorl	%ebp, %ebp
.LBB1_8:                                # %.loopexit
	movl	%ebp, %eax
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z6SolverPPiii, .Lfunc_end1-_Z6SolverPPiii
	.cfi_endproc
                                        # -- End function
	.globl	_Z21__device_stub__kernelPliiii # -- Begin function _Z21__device_stub__kernelPliiii
	.type	_Z21__device_stub__kernelPliiii,@function
_Z21__device_stub__kernelPliiii:        # @_Z21__device_stub__kernelPliiii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	20(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	16(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	12(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	8(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z6kernelPliiii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z21__device_stub__kernelPliiii, .Lfunc_end2-_Z21__device_stub__kernelPliiii
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0                          # -- Begin function _Z19report_running_timev
.LCPI3_0:
	.quad	0x412e848000000000              # double 1.0E+6
	.text
	.globl	_Z19report_running_timev
	.type	_Z19report_running_timev,@function
_Z19report_running_timev:               # @_Z19report_running_timev
	.cfi_startproc
# %bb.0:
	pushq	%r14
	.cfi_def_cfa_offset 16
	pushq	%rbx
	.cfi_def_cfa_offset 24
	pushq	%rax
	.cfi_def_cfa_offset 32
	.cfi_offset %rbx, -24
	.cfi_offset %r14, -16
	movl	$endTime, %edi
	movl	$Idunno, %esi
	callq	gettimeofday
	movq	endTime(%rip), %rax
	subq	startTime(%rip), %rax
	movq	endTime+8(%rip), %rcx
	subq	startTime+8(%rip), %rcx
	leaq	1000000(%rcx), %rbx
	movq	%rcx, %r14
	sarq	$63, %r14
	addq	%rax, %r14
	testq	%rcx, %rcx
	cmovnsq	%rcx, %rbx
	movl	$.L.str, %edi
	movq	%r14, %rsi
	movq	%rbx, %rdx
	xorl	%eax, %eax
	callq	printf
	cvtsi2sd	%r14, %xmm1
	cvtsi2sd	%rbx, %xmm0
	divsd	.LCPI3_0(%rip), %xmm0
	addsd	%xmm1, %xmm0
	addq	$8, %rsp
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	_Z19report_running_timev, .Lfunc_end3-_Z19report_running_timev
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0                          # -- Begin function main
.LCPI4_0:
	.quad	0x4028000000000000              # double 12
.LCPI4_1:
	.quad	0x408f400000000000              # double 1000
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$40, %rsp
	.cfi_def_cfa_offset 96
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	cmpl	$2, %edi
	jg	.LBB4_2
# %bb.1:
	movl	$.Lstr.3, %edi
	callq	puts@PLT
	movl	$-1, %r12d
	jmp	.LBB4_16
.LBB4_2:
	movq	%rsi, %rbx
	movq	8(%rsi), %rdi
	callq	atoi
	movl	%eax, %ebp
	movq	16(%rbx), %rdi
	callq	atoi
	cmpl	$10, %ebp
	jge	.LBB4_3
# %bb.5:
	testl	%ebp, %ebp
	jle	.LBB4_6
# %bb.7:
	movl	%eax, %r13d
	movl	$9, %r15d
	subl	%ebp, %r15d
	cvtsi2sd	%eax, %xmm0
	movsd	%xmm0, (%rsp)                   # 8-byte Spill
	cvtsi2sd	%r15d, %xmm1
	movsd	.LCPI4_0(%rip), %xmm0           # xmm0 = mem[0],zero
	callq	pow
	movsd	(%rsp), %xmm1                   # 8-byte Reload
                                        # xmm1 = mem[0],zero
	ucomisd	%xmm0, %xmm1
	ja	.LBB4_8
# %bb.9:
	movl	$96, %edi
	callq	malloc
	movq	%rax, %rbx
	xorl	%r14d, %r14d
.LBB4_10:                               # =>This Inner Loop Header: Depth=1
	movl	$48, %edi
	callq	malloc
	movq	%rax, (%rbx,%r14,8)
	incq	%r14
	cmpq	$12, %r14
	jne	.LBB4_10
# %bb.11:                               # %.preheader.preheader
	xorl	%eax, %eax
	xorpd	%xmm0, %xmm0
.LBB4_12:                               # %.preheader
                                        # =>This Inner Loop Header: Depth=1
	movq	(%rbx,%rax,8), %rcx
	movupd	%xmm0, 32(%rcx)
	movupd	%xmm0, 16(%rcx)
	movupd	%xmm0, (%rcx)
	incq	%rax
	cmpq	$12, %rax
	jne	.LBB4_12
# %bb.13:
	xorps	%xmm1, %xmm1
	cvtsi2sd	%ebp, %xmm1
	movsd	.LCPI4_0(%rip), %xmm0           # xmm0 = mem[0],zero
	callq	pow
	cvttsd2si	%xmm0, %r12d
	movl	%r13d, %r14d
	addl	$6, %r14d
	movl	%r14d, %eax
	imull	%r12d, %eax
	cltq
	movl	%r13d, (%rsp)                   # 4-byte Spill
	leaq	(,%rax,8), %r13
	testl	%eax, %eax
	movq	$-1, %rdi
	cmovnsq	%r13, %rdi
	callq	_Znam
	movq	%rax, answer(%rip)
	leaq	16(%rsp), %rdi
	movq	%r13, %rsi
	callq	hipMalloc
	shlq	$32, %r14
	orq	%r12, %r14
	leaq	24(%rsp), %r12
	movq	%r12, %rdi
	callq	hipEventCreate
	leaq	8(%rsp), %rdi
	callq	hipEventCreate
	movq	(%r12), %rdi
	xorl	%r12d, %r12d
	xorl	%esi, %esi
	callq	hipEventRecord
	movabsq	$51539607564, %rdx              # imm = 0xC0000000C
	movq	%r14, %rdi
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB4_15
# %bb.14:
	movq	16(%rsp), %rdi
	movl	$6, %esi
	movl	%ebp, %edx
	movl	(%rsp), %ecx                    # 4-byte Reload
	movl	%r15d, %r8d
	callq	_Z21__device_stub__kernelPliiii
.LBB4_15:
	callq	hipDeviceSynchronize
	movq	8(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	8(%rsp), %rdi
	callq	hipEventSynchronize
	movq	24(%rsp), %rsi
	movq	8(%rsp), %rdx
	leaq	36(%rsp), %r14
	movq	%r14, %rdi
	callq	hipEventElapsedTime
	movq	answer(%rip), %rdi
	movq	16(%rsp), %rsi
	movq	%r13, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	movl	$1, %edi
	callq	srand
	movl	$startTime, %edi
	movl	$Idunno, %esi
	callq	gettimeofday
	movq	%rbx, %rdi
	xorl	%esi, %esi
	movl	$12, %edx
	callq	_Z6SolverPPiii
	movl	_ZL5total(%rip), %esi
	movl	$.L.str.5, %edi
	xorl	%eax, %eax
	callq	printf
	callq	_Z19report_running_timev
	xorps	%xmm0, %xmm0
	cvtss2sd	(%r14), %xmm0
	divsd	.LCPI4_1(%rip), %xmm0
	movl	$.L.str.6, %edi
	movb	$1, %al
	callq	printf
.LBB4_16:
	movl	%r12d, %eax
	addq	$40, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB4_3:
	.cfi_def_cfa_offset 96
	movl	$.Lstr.2, %edi
	jmp	.LBB4_4
.LBB4_6:
	movl	$.Lstr.1, %edi
	jmp	.LBB4_4
.LBB4_8:
	movl	$.Lstr, %edi
.LBB4_4:
	callq	puts@PLT
	movl	$1, %edi
	callq	exit
.Lfunc_end4:
	.size	main, .Lfunc_end4-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB5_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB5_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z6kernelPliiii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end5:
	.size	__hip_module_ctor, .Lfunc_end5-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB6_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB6_2:
	retq
.Lfunc_end6:
	.size	__hip_module_dtor, .Lfunc_end6-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	count,@object                   # @count
	.bss
	.globl	count
	.p2align	3, 0x0
count:
	.quad	0                               # 0x0
	.size	count, 8

	.type	answer,@object                  # @answer
	.globl	answer
	.p2align	3, 0x0
answer:
	.quad	0
	.size	answer, 8

	.type	Idunno,@object                  # @Idunno
	.globl	Idunno
	.p2align	2, 0x0
Idunno:
	.zero	8
	.size	Idunno, 8

	.type	startTime,@object               # @startTime
	.globl	startTime
	.p2align	3, 0x0
startTime:
	.zero	16
	.size	startTime, 16

	.type	endTime,@object                 # @endTime
	.globl	endTime
	.p2align	3, 0x0
endTime:
	.zero	16
	.size	endTime, 16

	.type	_ZL5total,@object               # @_ZL5total
	.local	_ZL5total
	.comm	_ZL5total,4,4
	.type	_Z6kernelPliiii,@object         # @_Z6kernelPliiii
	.section	.rodata,"a",@progbits
	.globl	_Z6kernelPliiii
	.p2align	3, 0x0
_Z6kernelPliiii:
	.quad	_Z21__device_stub__kernelPliiii
	.size	_Z6kernelPliiii, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"CPU Time: %ld.%06ld\n"
	.size	.L.str, 21

	.type	.L.str.5,@object                # @.str.5
.L.str.5:
	.asciz	"\nTotal Solutions: %d boards\n\n"
	.size	.L.str.5, 30

	.type	.L.str.6,@object                # @.str.6
.L.str.6:
	.asciz	"GPU Time: %f secs\n"
	.size	.L.str.6, 19

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z6kernelPliiii"
	.size	.L__unnamed_1, 16

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.type	.Lstr,@object                   # @str
	.section	.rodata.str1.1,"aMS",@progbits,1
.Lstr:
	.asciz	"\n number of groups of columns must be less than or equal to N^(N - 3 - (1st ARG))"
	.size	.Lstr, 82

	.type	.Lstr.1,@object                 # @str.1
.Lstr.1:
	.asciz	"\nThe number of tuples generated by each block's X coordinate value must be >= 1"
	.size	.Lstr.1, 80

	.type	.Lstr.2,@object                 # @str.2
.Lstr.2:
	.asciz	"\nThe numbers generated iteratively cannot be less than 0."
	.size	.Lstr.2, 58

	.type	.Lstr.3,@object                 # @str.3
.Lstr.3:
	.asciz	"\nError, too few arguments. Usage: ./CHANGE THIS"
	.size	.Lstr.3, 48

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z21__device_stub__kernelPliiii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym Idunno
	.addrsig_sym startTime
	.addrsig_sym endTime
	.addrsig_sym _Z6kernelPliiii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z6kernelPliiii         ; -- Begin function _Z6kernelPliiii
	.globl	_Z6kernelPliiii
	.p2align	8
	.type	_Z6kernelPliiii,@function
_Z6kernelPliiii:                        ; @_Z6kernelPliiii
; %bb.0:
	s_load_b128 s[4:7], s[0:1], 0x8
	v_bfe_u32 v3, v0, 10, 10
	v_mov_b32_e32 v6, 0
	v_and_b32_e32 v2, 0x3ff, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_mul_u32_u24_e32 v4, 12, v3
	v_lshlrev_b32_e32 v0, 3, v3
	s_waitcnt lgkmcnt(0)
	v_cvt_f32_u32_e32 v1, s4
	s_sub_i32 s3, 0, s4
	v_rcp_iflag_f32_e32 v1, v1
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v1, 0x4f7ffffe, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v1, v1
	v_readfirstlane_b32 s2, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s3, s3, s2
	s_mul_hi_u32 s3, s2, s3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s2, s2, s3
	s_mul_hi_u32 s2, s15, s2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_mul_i32 s3, s2, s4
	s_add_i32 s8, s2, 1
	s_sub_i32 s3, s15, s3
	s_sub_i32 s9, s3, s4
	s_cmp_ge_u32 s3, s4
	s_cselect_b32 s2, s8, s2
	s_cselect_b32 s3, s9, s3
	s_add_i32 s8, s2, 1
	s_cmp_ge_u32 s3, s4
	s_cselect_b32 s3, s8, s2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s2, s3, s4
	s_sub_i32 s2, s15, s2
	s_cmp_lt_i32 s5, 1
	v_mov_b32_e32 v1, s2
	v_mov_b32_e32 v7, v6
	v_mad_u32_u24 v0, 0x60, v2, v0
	v_mad_u32_u24 v5, 0x90, v2, v4
	ds_store_b64 v0, v[6:7] offset:1728
	ds_store_b8 v5, v1
	s_cbranch_scc1 .LBB0_3
; %bb.1:                                ; %.lr.ph.preheader
	v_or_b32_e32 v1, 1, v5
	s_mov_b32 s2, s5
	s_mov_b32 s4, s14
.LBB0_2:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
	s_mul_hi_i32 s8, s4, 0x2aaaaaab
	s_add_i32 s2, s2, -1
	s_lshr_b32 s9, s8, 31
	s_ashr_i32 s8, s8, 1
	s_add_i32 s8, s8, s9
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s9, s8, 12
	s_sub_i32 s4, s4, s9
	s_cmp_eq_u32 s2, 0
	v_mov_b32_e32 v6, s4
	s_mov_b32 s4, s8
	ds_store_b8 v1, v6
	v_add_nc_u32_e32 v1, 1, v1
	s_cbranch_scc0 .LBB0_2
.LBB0_3:                                ; %._crit_edge
	v_mul_u32_u24_e32 v6, 0x90, v2
	s_mov_b32 s4, -1
	s_cmp_lt_i32 s5, -1
	s_delay_alu instid0(VALU_DEP_1)
	v_add3_u32 v7, v6, v4, s5
	ds_store_b8 v7, v2 offset:1
	ds_store_b8 v7, v3 offset:2
	s_cbranch_scc1 .LBB0_10
; %bb.4:                                ; %.preheader124.preheader
	v_or_b32_e32 v1, 1, v5
	v_mov_b32_e32 v8, 0
	s_add_i32 s2, s5, 2
.LBB0_5:                                ; %.preheader124
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_6 Depth 2
	s_delay_alu instid0(SALU_CYCLE_1)
	v_add3_u32 v9, v6, v4, s2
	s_mov_b32 s4, s5
	ds_load_u8 v11, v9
	s_waitcnt lgkmcnt(0)
	v_bfe_i32 v10, v11, 0, 8
	v_and_b32_e32 v11, 0xff, v11
	s_delay_alu instid0(VALU_DEP_2)
	v_add_nc_u32_e32 v9, 1, v10
	v_add_nc_u32_e32 v10, -1, v10
.LBB0_6:                                ;   Parent Loop BB0_5 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_add_nc_u32_e32 v12, s4, v1
	s_add_i32 s8, s4, 2
	s_add_i32 s4, s4, -1
	s_cmp_lt_u32 s8, 2
	ds_load_u8 v12, v12
	s_waitcnt lgkmcnt(0)
	v_cmp_eq_u16_e32 vcc_lo, v11, v12
	v_bfe_i32 v13, v12, 0, 8
	v_add_co_ci_u32_e32 v8, vcc_lo, 0, v8, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_3)
	v_cmp_eq_u32_e32 vcc_lo, v9, v13
	v_add_nc_u32_e32 v9, 1, v9
	v_cndmask_b32_e64 v12, 0, 1, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, v10, v13
	v_add_nc_u32_e32 v10, -1, v10
	v_add_co_ci_u32_e32 v8, vcc_lo, v8, v12, vcc_lo
	s_cbranch_scc0 .LBB0_6
; %bb.7:                                ;   in Loop: Header=BB0_5 Depth=1
	s_add_i32 s4, s2, -1
	s_add_i32 s5, s5, -1
	s_cmp_lt_i32 s2, 2
	s_cbranch_scc1 .LBB0_9
; %bb.8:                                ;   in Loop: Header=BB0_5 Depth=1
	s_mov_b32 s2, s4
	s_branch .LBB0_5
.LBB0_9:                                ; %._crit_edge133.loopexit
	v_cmp_eq_u32_e64 s4, 0, v8
.LBB0_10:                               ; %Flow246
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s2, s4
	s_cbranch_execz .LBB0_29
; %bb.11:                               ; %.critedge
	s_cmp_eq_u32 s7, 0
	s_cselect_b32 s4, -1, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v1, 0x41400000, 1.0, s4
	s_mov_b32 s4, 0x3e76c4e1
	v_frexp_mant_f32_e32 v8, v1
	v_frexp_exp_i32_f32_e32 v1, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cmp_gt_f32_e32 vcc_lo, 0x3f2aaaab, v8
	v_cndmask_b32_e64 v9, 0, 1, vcc_lo
	v_subrev_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ldexp_f32 v8, v8, v9
	v_cvt_f32_i32_e32 v1, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f32_e32 v11, -1.0, v8
	v_add_f32_e32 v9, 1.0, v8
	v_rcp_f32_e32 v10, v9
	s_waitcnt_depctr 0xfff
	v_dual_mul_f32 v12, v11, v10 :: v_dual_add_f32 v13, -1.0, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v14, v9, v12
	v_sub_f32_e32 v8, v8, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v9, v12, v9, -v14
	v_fmac_f32_e32 v9, v12, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v8, v14, v9
	v_dual_sub_f32 v13, v11, v8 :: v_dual_sub_f32 v14, v8, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v9, v14, v9
	v_sub_f32_e32 v11, v11, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v8, v11, v8
	v_add_f32_e32 v8, v9, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v8, v13, v8
	v_mul_f32_e32 v8, v10, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v9, v12, v8
	v_mul_f32_e32 v11, v9, v9
	v_sub_f32_e32 v10, v9, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v8, v8, v10
	v_fma_f32 v10, v9, v9, -v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v12, v8, v8
	v_fmac_f32_e32 v10, v9, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v12, v11, v10
	v_fmaak_f32 v13, s4, v12, 0x3e91f4c4
	v_sub_f32_e32 v11, v12, v11
	s_ashr_i32 s4, s6, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_add_i32 s5, s6, s4
	v_dual_fmaak_f32 v13, v12, v13, 0x3ecccdef :: v_dual_sub_f32 v10, v10, v11
	s_xor_b32 s5, s5, s4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_sub_i32 s10, 0, s5
	v_mul_f32_e32 v14, v12, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v11, v12, v13, -v14
	v_dual_fmac_f32 v11, v10, v13 :: v_dual_mul_f32 v16, v9, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v13, v14, v11
	v_fma_f32 v17, v12, v9, -v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_dual_sub_f32 v14, v13, v14 :: v_dual_fmac_f32 v17, v12, v8
	v_add_f32_e32 v15, 0x3f2aaaaa, v13
	v_ldexp_f32 v8, v8, 1
	v_sub_f32_e32 v11, v11, v14
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v17, v10, v9
	v_ldexp_f32 v9, v9, 1
	v_add_f32_e32 v11, 0x31739010, v11
	v_add_f32_e32 v14, 0xbf2aaaaa, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v13, v13, v14
	v_add_f32_e32 v11, v11, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v10, v15, v11
	v_dual_add_f32 v12, v16, v17 :: v_dual_sub_f32 v13, v15, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v14, v12, v10
	v_sub_f32_e32 v15, v12, v16
	v_add_f32_e32 v11, v11, v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v13, v12, v10, -v14
	v_sub_f32_e32 v15, v17, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v13, v12, v11
	v_fmac_f32_e32 v13, v15, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v10, v14, v13
	v_sub_f32_e32 v12, v10, v14
	v_mul_f32_e32 v14, 0x3f317218, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v12, v13, v12
	v_fma_f32 v13, 0x3f317218, v1, -v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v8, v8, v12 :: v_dual_add_f32 v11, v9, v10
	v_sub_f32_e32 v9, v11, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v9, v10, v9
	v_add_f32_e32 v8, v8, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v10, v11, v8 :: v_dual_fmamk_f32 v1, v1, 0xb102e308, v13
	v_sub_f32_e32 v11, v10, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v8, v8, v11 :: v_dual_add_f32 v9, v14, v1
	v_add_f32_e32 v12, v9, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v14, v9, v14 :: v_dual_sub_f32 v13, v12, v9
	v_sub_f32_e32 v15, v12, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v10, v10, v13 :: v_dual_sub_f32 v1, v1, v14
	v_add_f32_e32 v11, v1, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v9, v9, v15
	v_add_f32_e32 v9, v10, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v10, v11, v1
	v_dual_add_f32 v9, v11, v9 :: v_dual_sub_f32 v8, v8, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v13, v12, v9
	v_dual_sub_f32 v11, v11, v10 :: v_dual_sub_f32 v10, v13, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v1, v1, v11
	v_dual_add_f32 v1, v8, v1 :: v_dual_sub_f32 v8, v9, v10
	v_cvt_f32_i32_e32 v9, s7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v1, v1, v8
	v_add_f32_e32 v8, v13, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v10, v8, v13
	v_mul_f32_e32 v11, v8, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v1, v1, v10
	v_fma_f32 v8, v9, v8, -v11
	v_cmp_class_f32_e64 vcc_lo, v11, 0x204
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v8, v9, v1
	v_add_f32_e32 v1, v11, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v9, v1, v11, vcc_lo
	v_sub_f32_e32 v1, v1, v11
	v_cmp_eq_f32_e32 vcc_lo, 0x42b17218, v9
	v_cndmask_b32_e64 v10, 0, 0x37000000, vcc_lo
	v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v9|
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v12, v9, v10
	v_mul_f32_e32 v13, 0x3fb8aa3b, v12
	v_sub_f32_e32 v1, v8, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fma_f32 v14, 0x3fb8aa3b, v12, -v13
	v_rndne_f32_e32 v15, v13
	v_cndmask_b32_e32 v1, 0, v1, vcc_lo
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_dual_fmamk_f32 v14, v12, 0x32a5705f, v14 :: v_dual_sub_f32 v13, v13, v15
	v_cvt_i32_f32_e32 v11, v15
	v_add_f32_e32 v1, v10, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v13, v13, v14
	v_exp_f32_e32 v13, v13
	s_waitcnt_depctr 0xfff
	v_ldexp_f32 v8, v13, v11
	v_cvt_f32_u32_e32 v11, s5
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v8, 0, v8, vcc_lo
	v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v12
	v_rcp_iflag_f32_e32 v9, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v8, 0x7f800000, v8, vcc_lo
	v_fma_f32 v1, v8, v1, v8
	v_cmp_eq_f32_e32 vcc_lo, 0x7f800000, v8
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v9, 0x4f7ffffe, v9
	v_cndmask_b32_e32 v1, v1, v8, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_u32_f32_e32 v8, v9
	v_cvt_i32_f32_e64 v1, |v1|
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s8, v8
	v_readfirstlane_b32 s9, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s10, s10, s8
	s_mul_hi_u32 s10, s8, s10
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
	s_ashr_i32 s11, s9, 31
	s_add_i32 s8, s8, s10
	s_add_i32 s12, s9, s11
	s_xor_b32 s4, s11, s4
	s_xor_b32 s10, s12, s11
	s_mul_hi_u32 s8, s10, s8
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_mul_i32 s12, s8, s5
	s_add_i32 s11, s8, 1
	s_sub_i32 s10, s10, s12
	s_sub_i32 s12, s10, s5
	s_cmp_ge_u32 s10, s5
	s_cselect_b32 s8, s11, s8
	s_cselect_b32 s10, s12, s10
	s_add_i32 s11, s8, 1
	s_cmp_ge_u32 s10, s5
	s_cselect_b32 s5, s11, s8
	s_add_i32 s8, s6, -1
	s_xor_b32 s5, s5, s4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_sub_i32 s5, s5, s4
	s_mul_i32 s6, s5, s6
	s_mul_i32 s4, s5, s3
	s_sub_i32 s6, s9, s6
	s_add_i32 s5, s4, s5
	s_cmp_eq_u32 s3, s8
	s_cselect_b32 s3, s6, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s3, s5, s3
	s_cmp_ge_i32 s4, s3
	s_cbranch_scc1 .LBB0_29
; %bb.12:                               ; %.lr.ph156
	v_add_nc_u32_e32 v8, 0x6c0, v0
	s_cmp_gt_i32 s7, 0
	s_cselect_b32 s5, -1, 0
	ds_load_b64 v[0:1], v8
.LBB0_13:                               ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_15 Depth 2
                                        ;     Child Loop BB0_17 Depth 2
                                        ;       Child Loop BB0_18 Depth 3
                                        ;     Child Loop BB0_23 Depth 2
                                        ;       Child Loop BB0_25 Depth 3
	s_and_not1_b32 vcc_lo, exec_lo, s5
	s_cbranch_vccnz .LBB0_21
; %bb.14:                               ; %.lr.ph137.preheader
                                        ;   in Loop: Header=BB0_13 Depth=1
	s_mov_b32 s6, 0
	s_mov_b32 s8, s4
.LBB0_15:                               ; %.lr.ph137
                                        ;   Parent Loop BB0_13 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_hi_i32 s9, s8, 0x2aaaaaab
	s_lshr_b32 s10, s9, 31
	s_ashr_i32 s9, s9, 1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s9, s9, s10
	s_mul_i32 s10, s9, 12
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_sub_i32 s8, s8, s10
	v_dual_mov_b32 v10, s8 :: v_dual_add_nc_u32 v9, s6, v5
	s_add_i32 s6, s6, 1
	s_mov_b32 s8, s9
	s_cmp_eq_u32 s7, s6
	ds_store_b8 v9, v10
	s_cbranch_scc0 .LBB0_15
; %bb.16:                               ; %.preheader123
                                        ;   in Loop: Header=BB0_13 Depth=1
	s_mov_b32 s6, 0
	s_mov_b32 s8, 0
                                        ; implicit-def: $sgpr9
.LBB0_17:                               ; %.preheader121
                                        ;   Parent Loop BB0_13 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB0_18 Depth 3
	s_delay_alu instid0(SALU_CYCLE_1)
	v_add_nc_u32_e32 v9, s8, v7
	s_mov_b32 s11, 0
	s_mov_b32 s12, 0
                                        ; implicit-def: $sgpr10
	ds_load_u8 v9, v9 offset:3
	s_waitcnt lgkmcnt(0)
	v_and_b32_e32 v9, 0xff, v9
.LBB0_18:                               ;   Parent Loop BB0_13 Depth=1
                                        ;     Parent Loop BB0_17 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	v_add_nc_u32_e32 v10, s12, v7
	s_cmp_lg_u32 s8, s12
	s_cselect_b32 s13, -1, 0
	s_add_i32 s12, s12, 1
	ds_load_u8 v10, v10 offset:3
	s_waitcnt lgkmcnt(0)
	v_cmp_eq_u16_e32 vcc_lo, v9, v10
	s_and_b32 s13, s13, vcc_lo
	s_cmp_ge_i32 s12, s7
	s_cselect_b32 s16, -1, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s16, s16, s13
	s_and_b32 s16, exec_lo, s16
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_or_b32 s11, s16, s11
	s_and_not1_b32 s10, s10, exec_lo
	s_and_b32 s13, s13, exec_lo
	s_or_b32 s10, s10, s13
	s_and_not1_b32 exec_lo, exec_lo, s11
	s_cbranch_execnz .LBB0_18
; %bb.19:                               ; %._crit_edge140
                                        ;   in Loop: Header=BB0_17 Depth=2
	s_or_b32 exec_lo, exec_lo, s11
	s_add_i32 s8, s8, 1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_cmp_ge_i32 s8, s7
	s_cselect_b32 s11, -1, 0
	s_or_b32 s11, s11, s10
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s11, exec_lo, s11
	s_or_b32 s6, s11, s6
	s_and_not1_b32 s9, s9, exec_lo
	s_and_b32 s10, s10, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s9, s9, s10
	s_and_not1_b32 exec_lo, exec_lo, s6
	s_cbranch_execnz .LBB0_17
; %bb.20:                               ; %.preheader122.loopexit
                                        ;   in Loop: Header=BB0_13 Depth=1
	s_or_b32 exec_lo, exec_lo, s6
	v_cndmask_b32_e64 v9, 0, 1, s9
	s_branch .LBB0_22
.LBB0_21:                               ;   in Loop: Header=BB0_13 Depth=1
	v_mov_b32_e32 v9, 0
.LBB0_22:                               ; %Flow244
                                        ;   in Loop: Header=BB0_13 Depth=1
	s_mov_b32 s6, 11
	s_mov_b32 s9, 10
	s_mov_b32 s8, 0
.LBB0_23:                               ; %.preheader120
                                        ;   Parent Loop BB0_13 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB0_25 Depth 3
	s_cmp_lt_i32 s6, 1
	s_cbranch_scc1 .LBB0_26
; %bb.24:                               ; %.lr.ph147
                                        ;   in Loop: Header=BB0_23 Depth=2
	v_add3_u32 v10, v6, v4, s6
	s_mov_b32 s10, s9
	ds_load_u8 v12, v10
	s_waitcnt lgkmcnt(0)
	v_bfe_i32 v11, v12, 0, 8
	v_and_b32_e32 v12, 0xff, v12
	s_delay_alu instid0(VALU_DEP_2)
	v_add_nc_u32_e32 v10, 1, v11
	v_add_nc_u32_e32 v11, -1, v11
.LBB0_25:                               ;   Parent Loop BB0_13 Depth=1
                                        ;     Parent Loop BB0_23 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	v_add_nc_u32_e32 v13, s10, v5
	s_add_i32 s11, s10, 1
	s_add_i32 s10, s10, -1
	s_cmp_lt_u32 s11, 2
	ds_load_u8 v13, v13
	s_waitcnt lgkmcnt(0)
	v_cmp_eq_u16_e32 vcc_lo, v12, v13
	v_bfe_i32 v14, v13, 0, 8
	v_add_co_ci_u32_e32 v9, vcc_lo, 0, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_3)
	v_cmp_eq_u32_e32 vcc_lo, v10, v14
	v_add_nc_u32_e32 v10, 1, v10
	v_cndmask_b32_e64 v13, 0, 1, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, v11, v14
	v_add_nc_u32_e32 v11, -1, v11
	v_add_co_ci_u32_e32 v9, vcc_lo, v9, v13, vcc_lo
	s_cbranch_scc0 .LBB0_25
.LBB0_26:                               ; %Flow243
                                        ;   in Loop: Header=BB0_23 Depth=2
	s_add_i32 s6, s6, -1
	s_add_i32 s9, s9, -1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_le_i32_e32 vcc_lo, s6, v9
	s_or_b32 s8, vcc_lo, s8
	s_and_not1_b32 exec_lo, exec_lo, s8
	s_cbranch_execnz .LBB0_23
; %bb.27:                               ; %._crit_edge152
                                        ;   in Loop: Header=BB0_13 Depth=1
	s_or_b32 exec_lo, exec_lo, s8
	v_cmp_eq_u32_e32 vcc_lo, 0, v9
	s_add_i32 s4, s4, 1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	s_cmp_eq_u32 s4, s3
	v_cndmask_b32_e64 v9, 0, 1, vcc_lo
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v0, vcc_lo, v0, v9
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
	s_cbranch_scc0 .LBB0_13
; %bb.28:                               ; %..loopexit_crit_edge
	ds_store_b64 v8, v[0:1]
.LBB0_29:                               ; %.loopexit
	s_or_b32 exec_lo, exec_lo, s2
	v_or_b32_e32 v0, v2, v3
	s_mov_b32 s3, 0
	s_mov_b32 s2, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB0_35
; %bb.30:                               ; %.preheader.preheader
	v_mov_b32_e32 v0, 0
	v_mov_b32_e32 v1, 0
	s_movk_i32 s4, 0x6c0
.LBB0_31:                               ; %.preheader
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_32 Depth 2
	s_mov_b32 s5, 0
.LBB0_32:                               ;   Parent Loop BB0_31 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_i32 s6, s4, s5
	s_add_i32 s5, s5, 8
	v_mov_b32_e32 v2, s6
	s_cmpk_eq_i32 s5, 0x60
	ds_load_b64 v[2:3], v2
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v0, vcc_lo, v2, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, v3, v1, vcc_lo
	s_cbranch_scc0 .LBB0_32
; %bb.33:                               ;   in Loop: Header=BB0_31 Depth=1
	s_add_i32 s3, s3, 1
	s_addk_i32 s4, 0x60
	s_cmp_eq_u32 s3, 12
	s_cbranch_scc0 .LBB0_31
; %bb.34:
	s_clause 0x1
	s_load_b32 s3, s[0:1], 0x18
	s_load_b64 s[0:1], s[0:1], 0x0
	s_mov_b32 s5, 0
	v_mov_b32_e32 v2, 0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s3, s3, s15
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s4, s3, s14
	s_lshl_b64 s[4:5], s[4:5], 3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s0, s0, s4
	s_addc_u32 s1, s1, s5
	global_store_b64 v2, v[0:1], s[0:1]
.LBB0_35:                               ; %Flow
	s_or_b32 exec_lo, exec_lo, s2
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z6kernelPliiii
		.amdhsa_group_segment_fixed_size 2880
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 18
		.amdhsa_next_free_sgpr 17
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z6kernelPliiii, .Lfunc_end0-_Z6kernelPliiii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 2412
; NumSgprs: 19
; NumVgprs: 18
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 2880 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 19
; NumVGPRsForWavesPerEU: 18
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .offset:         12
        .size:           4
        .value_kind:     by_value
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 2880
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z6kernelPliiii
    .private_segment_fixed_size: 0
    .sgpr_count:     19
    .sgpr_spill_count: 0
    .symbol:         _Z6kernelPliiii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     18
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
