

/********************************************************************************************

	
  source Code :  globalMemoryAccessPatterns.cu

  Objective   :  Example code to demonstrate the different access patterns of the global 
                 memory and the corresponding advantages in terms of the bandwidth that 
                 is achievable.

  Description : The six patterns that are discussed in the programming guide which the 
                program is implementing

		1) coalesced float memory access, resulting in a single memory transaction
		2) coalesced float memory access (divergent warp), resulting in a single 
                   memory transaction
		3) non-sequential float memory access, resulting in 16 memory transactions
		4) access with a misaligned starting address, resulting in 16 memory transactions
		5) non-contiguous float memory access, resulting in 16 memory transactions
		6) non-coalesced float3 memory access, resulting in 16 memory transactions

                 the six patterns along with the cudaMemcpy, the bandwidth is being calculated 

input       :   none

output      :	The different bandwidths that are achieved for different access patterns

Modified    :   Aug 2011
                

Author 	    :   RarchK		

*****************************************************************************************/

#include <cuda.h>
#include <stdio.h>
#include <float.h>

// there are six patterns that have been quoted in programming guide 2.3.1 for devices with compute capability 1.1
#define NO_OF_PATTERNS 6 

#define ARRAY_SIZE 20000000 // 20 MB
#define BLOCK_SIZE 512

#define NTIMES 10 

#define MIN(x,y) ((x)<(y)?(x):(y))
#define MAX(x,y) ((x)>(y)?(x):(y))

void printResults(void); // function declaration

//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
//
// the access pattern where successive threads are acceessing the successive memory locations in the Global memory
// and the array is aligned at (128)
// the first scenario from the performance guidelines of the programming guide
// coalesced float memory access, resulting in a single memory transaction
//
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////

__global__ void coalescedGMAccess(float* dest,float* src,long size)
{
	int idx = blockIdx.x * blockDim.x + threadIdx.x;
	if(idx < size)
		dest[idx] = src[idx];
}

///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////


///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
//
// the access pattern where successive threads are accessing the successive memory locations in the Global memory
// and array is aligned but some of the threads are not acessing any memory location
// the second scenario from the performance guide lines of the programming guide
// coalesced float memory access (divergent warp), resulting in a single memory transaction
//
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////

__global__ void coalescedGMAccessDivergent(float* dest,float* src,long size)
{
	int idx = blockIdx.x * blockDim.x + threadIdx.x;
	if(idx < size)
	//every warp there will be 4 threads that will not be accessing any memory location
		if(idx % 8 != 0) 
			dest[idx] = src[idx];
}

//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////


//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// 
// kernel for setting the array with given element
//
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////

__global__ void setArray(float *array,  float value, int size)
{
	int idx = threadIdx.x + blockIdx.x * blockDim.x;
	if (idx < size)
		array[idx] = value;
}

///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////


////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
//
// the access pattern where successive threads are accessing the successive memory locations in the Global memory 
// but the starting address is misaligned
// the fourth scenario from the performance guidelines of the programming guide
// access with a misaligned starting address, resulting in 16 memory transactions.
//
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////

__global__ void nonCoalescedGMAccessMisalign(float* dest,float* src,long size)
{
	int idx = blockIdx.x * blockDim.x + threadIdx.x;
	if(idx < size-1) // the last thread is skipped, it will not access any location
		dest[idx+1] = src[idx+1];
}

////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////




///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
//
// the access pattern where successive threads are not accessing the successive memory locations in the Global memory
// the starting address is aligned
// the third scenario from the performance guidelines of the programming guide
// non-sequential float memory access, resulting in 16 memory transactions
//
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////

__global__ void nonCoalescedGMAccessNonSeq(float* dest,float* src,long size)
{
	int idx = blockIdx.x * blockDim.x + threadIdx.x;
	if(idx < size)
	{

	//in each half warp the third thread accesses the location which would have been accessed by the fourth thread in coalesced access
	//and fourth thread accesses the location of the third thread in the coalesced access

		if(idx % 16 == 3)
			idx = 4;
		else if(idx % 16 == 4)
			idx = 3;
					
		dest[idx] = src[idx];

	}
}

///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////



/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
//
// the access pattern where the successive threads are not accessing the successive memory locations
// the starting address is aligned
// the fifth scenario from the performance guidelines of the programming guide
// non-contiguous float memory access, resulting in 16 memory transactions
//
/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////

__global__ void nonCoalescedGMAccessNonContiguous(float* dest,float* src,long size)
{
	int idx = blockIdx.x * blockDim.x + threadIdx.x;

	if(idx < size)
	{
		if(idx > 3) // threads with their id more than 3 will access the location id+1
			idx++;

		dest[idx] = src[idx];
	}


}

///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////



///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
//
// access pattern involves accessing contiguous float3 elements' first component by the contiguous threads
// the starting address is aligned
// the sixth scenario from the performance guidelines of the programming guide
// non-coalesced float3 memory access, resulting in 16 memory transactions
//
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////

__global__ void nonCoalescedGMAccessFloat3(float3 *src, float* dest,long size)
{
	int idx = blockIdx.x * blockDim.x + threadIdx.x;

	if(idx < size)
	{
		dest[idx] = src[idx].x;
	}

}

///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////




// one extra location to hold results for cudaMemcpy also other than the 6 patterns 

static double  avgtime[NO_OF_PATTERNS+1] = {0}, maxtime[NO_OF_PATTERNS+1] = {0}, mintime[NO_OF_PATTERNS+1];
static float bandWidths[NO_OF_PATTERNS+1] = {0}; 

////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
//
// the main routene 
// for timing the different access patterns 
// finding the band widths
//
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////

int main(int argc,char* argv[])
{
	float *srcArray , *destArray;
	float3 *srcArray3; // the array of float3 datatype
	float elapsedTimes[NO_OF_PATTERNS+1][NTIMES];
	cudaEvent_t start,stop;
	cudaError_t err = cudaSuccess;
	
	double bytes = 2 * sizeof(float) * ARRAY_SIZE;

	// allocating the memory for the two arrays on the device
	// the memory allocated using cudaMalloc will give the memory address that is aligned (128)
	err = cudaMalloc((void **)&srcArray,ARRAY_SIZE*sizeof(float));
	if(err == cudaErrorMemoryAllocation)
	{
		printf("error in device memory allocation for - srcArray\n exiting out of the program.....\n");
		exit(-1);
	}
	
	err = cudaMalloc((void **)&destArray,ARRAY_SIZE*sizeof(float));
	if(err == cudaErrorMemoryAllocation)
	{
		printf("error in device memory allocation for -  destArray\n exiting out of the program.....\n");
		exit(-1);
	}
	
	err = cudaMalloc((void **)&srcArray3,ARRAY_SIZE*sizeof(float3));
	if(err == cudaErrorMemoryAllocation)
	{
		printf("error in device memory allocation for - srcArray3\n exiting out of the program.....\n");
		exit(-1);
	}
	
	// event creation, which will be used for timing the code
	cudaEventCreate(&start);
	cudaEventCreate(&stop);
	
	//finding the 1D grid size 
	int gridSize = ARRAY_SIZE/BLOCK_SIZE;
	
	if( ARRAY_SIZE % BLOCK_SIZE != 0 ) 
			gridSize += 1;
	
	// intializing the arrays on the device
	setArray <<< gridSize,BLOCK_SIZE >>> (srcArray,1.0f,ARRAY_SIZE);
	setArray <<< gridSize,BLOCK_SIZE >>> (destArray,0.0f,ARRAY_SIZE);

	cudaThreadSynchronize();

	// running each pattern NTIMES
	for(int k=0; k < NTIMES; k++)
	{
		// timing the kernels corresponding to different access patterns
			
			// PATTERN 1
   		// timing the code with coalesced float memory access, resulting in a single memory transaction from the Global memory
			cudaEventRecord(start,0);
			coalescedGMAccess <<< gridSize,BLOCK_SIZE >>> (destArray,srcArray,ARRAY_SIZE);
			cudaEventRecord(stop,0);
			cudaEventSynchronize(stop);
			cudaEventElapsedTime(&elapsedTimes[0][k],start,stop);


			// PATTERN 2
			// timing the code with coalesced float memory access (divergent warp), resulting in a single memory transaction from the Global memory
			cudaEventRecord(start,0);
			coalescedGMAccessDivergent <<< gridSize,BLOCK_SIZE >>> (destArray,srcArray,ARRAY_SIZE);
			cudaEventRecord(stop,0);
			cudaEventSynchronize(stop);
			cudaEventElapsedTime(&elapsedTimes[1][k],start,stop);


			// PATTERN 3
			//timing the code with non-sequential float memory access, resulting in 16 memory transactions from the Global memory
			cudaEventRecord(start,0);
			nonCoalescedGMAccessNonSeq <<< gridSize,BLOCK_SIZE >>> (destArray,srcArray,ARRAY_SIZE);
			cudaEventRecord(stop,0);
			cudaEventSynchronize(stop);
			cudaEventElapsedTime(&elapsedTimes[2][k],start,stop);


			// PATTERN 4
			//timing the code of access pattern with a misaligned starting address, resulting in 16 memory transactions from the Global memory
			cudaEventRecord(start,0);
			nonCoalescedGMAccessMisalign <<< gridSize,BLOCK_SIZE >>> (destArray,srcArray,ARRAY_SIZE);
			cudaEventRecord(stop,0);
			cudaEventSynchronize(stop);
			cudaEventElapsedTime(&elapsedTimes[3][k],start,stop);


			//PATTERN 5
			//timing the code with non-contiguous float memory access, resulting in 16 memory transactions
			cudaEventRecord(start,0);
			nonCoalescedGMAccessNonContiguous <<< gridSize,BLOCK_SIZE >>> (destArray,srcArray,ARRAY_SIZE);
			cudaEventRecord(stop,0);
			cudaEventSynchronize(stop);
			cudaEventElapsedTime(&elapsedTimes[4][k],start,stop);


			//PATTERN 6
			//timing the code for no-coalesced access of float3 array
			cudaEventRecord(start,0);
			nonCoalescedGMAccessFloat3 <<< gridSize,BLOCK_SIZE >>> (srcArray3,destArray,ARRAY_SIZE);
			cudaEventRecord(stop,0);
			cudaEventSynchronize(stop);
			cudaEventElapsedTime(&elapsedTimes[5][k],start,stop);
			
			//PATTERN 7
			//timing the code that uses the cudaMemcpy API call
			cudaEventRecord(start,0);
			cudaMemcpy(destArray,srcArray,ARRAY_SIZE * sizeof(float),cudaMemcpyDeviceToDevice);
			cudaEventRecord(stop,0);
			cudaEventSynchronize(stop);
			cudaEventElapsedTime(&elapsedTimes[6][k],start,stop);

	} // end of the for loop involving NTIMES


	// intializing the mintime array
	for(int i=0; i < NO_OF_PATTERNS+1;i++)
		mintime[i] = FLT_MAX;


   for (int k=1; k < NTIMES; k++) // skiping the first iteration
	{
	   for (int i=0; i < NO_OF_PATTERNS+1; i++)
	   {
	       avgtime[i] = avgtime[i] + elapsedTimes[i][k];
	       mintime[i] = MIN(mintime[i],elapsedTimes[i][k]);
	       maxtime[i] = MAX(maxtime[i], elapsedTimes[i][k]);
	   }
	}


	// calculation of the different band widths that are achieved by different access patterns that are given in the performane guide lines 
	
	for(int i=0; i < NO_OF_PATTERNS+1; i++)
	{
		avgtime[i] = avgtime[i]/(double)(NTIMES-1); // finding the average time
		bandWidths[i] = bytes/mintime[i];
	}

	printResults();

	printf("\n\n**** successful termination of the program  ****\n\n");
		

	cudaEventDestroy(start);
	cudaEventDestroy(stop);

	cudaFree(srcArray);
	cudaFree(destArray);

	return 0;
}

/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////



////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
//
// prints the results containig the minimum, maximum, average times that the different access patterns have taken
// the associated maximum bandwidth of the different patterns
//
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////

void printResults()
{

  printf("\nComparing different access patterns of the global memory for the devices with compute capability <= 1.1\n");
  printf("The array size (single precision): %d\n",ARRAY_SIZE);

  printf("\n-------------------------------------------------------------------------------------------------------------------------------\n");
  printf("Pattern \t\t\t\t Bandwidth (GB/sec) \t Avg time (ms)  \t Min time (ms)  \t Max time (ms)\n");
  printf("-------------------------------------------------------------------------------------------------------------------------------\n");

	// printing the results for different access patterns
	for(int i=0; i < NO_OF_PATTERNS+1; i++)
	{
		
		switch(i)
		{
			case 0: printf("coalesced access                  ");
					  break;

			case 1: printf("coalesced access (divergent warp) ");
					  break;
			
			case 2: printf("non-sequential access             ");
					  break;

			case 3: printf("accessing  misaligned address     ");
					  break;

			case 4: printf("non-contiguous access             ");
					  break;

			case 5: printf("non-coalesced float3 access       ");
					  break;

			case 6: printf("using cudaMemcpy                  ");
					  break;

		}
		
		printf("\t %.6f \t\t %f \t\t  %f \t\t  %f\n",bandWidths[i]/1000000,avgtime[i],mintime[i],maxtime[i]);

  }
	
  
  printf("\n ------------------------------------------------------------------------------------------------------------------------------\n");

}

//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////


	.file	"tmpxft_0034815c_00000000-6_globalMemoryAccessPatterns.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2031:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"\nComparing different access patterns of the global memory for the devices with compute capability <= 1.1\n"
.LC1:
	.string	"The array size (single precision): %d\n"
.LC2:
	.string	"\n-------------------------------------------------------------------------------------------------------------------------------\n"
.LC3:
	.string	"Pattern \t\t\t\t Bandwidth (GB/sec) \t Avg time (ms)  \t Min time (ms)  \t Max time (ms)\n"
.LC4:
	.string	"-------------------------------------------------------------------------------------------------------------------------------\n"
.LC5:
	.string	"coalesced access                  "
.LC6:
	.string	"coalesced access (divergent warp) "
.LC7:
	.string	"non-sequential access             "
.LC8:
	.string	"accessing  misaligned address     "
.LC9:
	.string	"non-contiguous access             "
.LC10:
	.string	"non-coalesced float3 access       "
.LC11:
	.string	"using cudaMemcpy                  "
.LC13:
	.string	"\t %.6f \t\t %f \t\t  %f \t\t  %f\n"
.LC14:
	.string	"\n ------------------------------------------------------------------------------------------------------------------------------\n"
	.text
	.globl	_Z12printResultsv
	.type	_Z12printResultsv, @function
_Z12printResultsv:
.LFB2028:
	.cfi_startproc
	endbr64
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	leaq	.LC0(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	pushq	%rbx
	.cfi_def_cfa_offset 24
	.cfi_offset 3, -24
	leaq	.L5(%rip), %rbp
	xorl	%ebx, %ebx
	pushq	%rcx
	.cfi_def_cfa_offset 32
	call	__printf_chk@PLT
	movl	$20000000, %edx
	leaq	.LC1(%rip), %rsi
	xorl	%eax, %eax
	movl	$2, %edi
	call	__printf_chk@PLT
	leaq	.LC2(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	leaq	.LC3(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	leaq	.LC4(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
.L12:
	leal	-1(%rbx), %eax
	leaq	.LC5(%rip), %rsi
	cmpl	$5, %eax
	ja	.L15
	movslq	0(%rbp,%rax,4), %rax
	addq	%rbp, %rax
	notrack jmp	*%rax
	.section	.rodata
	.align 4
	.align 4
.L5:
	.long	.L10-.L5
	.long	.L9-.L5
	.long	.L8-.L5
	.long	.L7-.L5
	.long	.L6-.L5
	.long	.L4-.L5
	.text
.L10:
	leaq	.LC6(%rip), %rsi
	jmp	.L15
.L9:
	leaq	.LC7(%rip), %rsi
	jmp	.L15
.L8:
	leaq	.LC8(%rip), %rsi
	jmp	.L15
.L7:
	leaq	.LC9(%rip), %rsi
	jmp	.L15
.L6:
	leaq	.LC10(%rip), %rsi
	jmp	.L15
.L4:
	leaq	.LC11(%rip), %rsi
.L15:
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	leaq	_ZL10bandWidths(%rip), %rax
	movl	$2, %edi
	leaq	.LC13(%rip), %rsi
	movss	(%rax,%rbx,4), %xmm0
	leaq	_ZL7maxtime(%rip), %rax
	divss	.LC12(%rip), %xmm0
	cvtss2sd	%xmm0, %xmm0
	movsd	(%rax,%rbx,8), %xmm3
	leaq	_ZL7mintime(%rip), %rax
	movsd	(%rax,%rbx,8), %xmm2
	leaq	_ZL7avgtime(%rip), %rax
	movsd	(%rax,%rbx,8), %xmm1
	movb	$4, %al
	incq	%rbx
	call	__printf_chk@PLT
	cmpq	$7, %rbx
	jne	.L12
	popq	%rdx
	.cfi_def_cfa_offset 24
	leaq	.LC14(%rip), %rsi
	popq	%rbx
	.cfi_def_cfa_offset 16
	movl	$2, %edi
	xorl	%eax, %eax
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	__printf_chk@PLT
	.cfi_endproc
.LFE2028:
	.size	_Z12printResultsv, .-_Z12printResultsv
	.globl	_Z40__device_stub__Z17coalescedGMAccessPfS_lPfS_l
	.type	_Z40__device_stub__Z17coalescedGMAccessPfS_lPfS_l, @function
_Z40__device_stub__Z17coalescedGMAccessPfS_lPfS_l:
.LFB2053:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L17
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z17coalescedGMAccessPfS_l(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L17:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L19
	call	__stack_chk_fail@PLT
.L19:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2053:
	.size	_Z40__device_stub__Z17coalescedGMAccessPfS_lPfS_l, .-_Z40__device_stub__Z17coalescedGMAccessPfS_lPfS_l
	.globl	_Z17coalescedGMAccessPfS_l
	.type	_Z17coalescedGMAccessPfS_l, @function
_Z17coalescedGMAccessPfS_l:
.LFB2054:
	.cfi_startproc
	endbr64
	jmp	_Z40__device_stub__Z17coalescedGMAccessPfS_lPfS_l
	.cfi_endproc
.LFE2054:
	.size	_Z17coalescedGMAccessPfS_l, .-_Z17coalescedGMAccessPfS_l
	.globl	_Z49__device_stub__Z26coalescedGMAccessDivergentPfS_lPfS_l
	.type	_Z49__device_stub__Z26coalescedGMAccessDivergentPfS_lPfS_l, @function
_Z49__device_stub__Z26coalescedGMAccessDivergentPfS_lPfS_l:
.LFB2055:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L22
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z26coalescedGMAccessDivergentPfS_l(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L22:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L24
	call	__stack_chk_fail@PLT
.L24:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2055:
	.size	_Z49__device_stub__Z26coalescedGMAccessDivergentPfS_lPfS_l, .-_Z49__device_stub__Z26coalescedGMAccessDivergentPfS_lPfS_l
	.globl	_Z26coalescedGMAccessDivergentPfS_l
	.type	_Z26coalescedGMAccessDivergentPfS_l, @function
_Z26coalescedGMAccessDivergentPfS_l:
.LFB2056:
	.cfi_startproc
	endbr64
	jmp	_Z49__device_stub__Z26coalescedGMAccessDivergentPfS_lPfS_l
	.cfi_endproc
.LFE2056:
	.size	_Z26coalescedGMAccessDivergentPfS_l, .-_Z26coalescedGMAccessDivergentPfS_l
	.globl	_Z29__device_stub__Z8setArrayPffiPffi
	.type	_Z29__device_stub__Z8setArrayPffiPffi, @function
_Z29__device_stub__Z8setArrayPffiPffi:
.LFB2057:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 8(%rsp)
	leaq	24(%rsp), %rcx
	leaq	16(%rsp), %rdx
	movl	%esi, (%rsp)
	leaq	32(%rsp), %rdi
	leaq	44(%rsp), %rsi
	movss	%xmm0, 4(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 40(%rsp)
	movq	%rax, 80(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 88(%rsp)
	movq	%rsp, %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 32(%rsp)
	movq	%rax, 44(%rsp)
	movl	$1, 52(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L27
	pushq	24(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z8setArrayPffi(%rip), %rdi
	pushq	24(%rsp)
	.cfi_def_cfa_offset 144
	movq	60(%rsp), %rcx
	movl	68(%rsp), %r8d
	movq	48(%rsp), %rsi
	movl	56(%rsp), %edx
	leaq	96(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L27:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L29
	call	__stack_chk_fail@PLT
.L29:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2057:
	.size	_Z29__device_stub__Z8setArrayPffiPffi, .-_Z29__device_stub__Z8setArrayPffiPffi
	.globl	_Z8setArrayPffi
	.type	_Z8setArrayPffi, @function
_Z8setArrayPffi:
.LFB2058:
	.cfi_startproc
	endbr64
	jmp	_Z29__device_stub__Z8setArrayPffiPffi
	.cfi_endproc
.LFE2058:
	.size	_Z8setArrayPffi, .-_Z8setArrayPffi
	.globl	_Z51__device_stub__Z28nonCoalescedGMAccessMisalignPfS_lPfS_l
	.type	_Z51__device_stub__Z28nonCoalescedGMAccessMisalignPfS_lPfS_l, @function
_Z51__device_stub__Z28nonCoalescedGMAccessMisalignPfS_lPfS_l:
.LFB2059:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L32
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z28nonCoalescedGMAccessMisalignPfS_l(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L32:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L34
	call	__stack_chk_fail@PLT
.L34:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2059:
	.size	_Z51__device_stub__Z28nonCoalescedGMAccessMisalignPfS_lPfS_l, .-_Z51__device_stub__Z28nonCoalescedGMAccessMisalignPfS_lPfS_l
	.globl	_Z28nonCoalescedGMAccessMisalignPfS_l
	.type	_Z28nonCoalescedGMAccessMisalignPfS_l, @function
_Z28nonCoalescedGMAccessMisalignPfS_l:
.LFB2060:
	.cfi_startproc
	endbr64
	jmp	_Z51__device_stub__Z28nonCoalescedGMAccessMisalignPfS_lPfS_l
	.cfi_endproc
.LFE2060:
	.size	_Z28nonCoalescedGMAccessMisalignPfS_l, .-_Z28nonCoalescedGMAccessMisalignPfS_l
	.globl	_Z49__device_stub__Z26nonCoalescedGMAccessNonSeqPfS_lPfS_l
	.type	_Z49__device_stub__Z26nonCoalescedGMAccessNonSeqPfS_lPfS_l, @function
_Z49__device_stub__Z26nonCoalescedGMAccessNonSeqPfS_lPfS_l:
.LFB2061:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L37
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z26nonCoalescedGMAccessNonSeqPfS_l(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L37:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L39
	call	__stack_chk_fail@PLT
.L39:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2061:
	.size	_Z49__device_stub__Z26nonCoalescedGMAccessNonSeqPfS_lPfS_l, .-_Z49__device_stub__Z26nonCoalescedGMAccessNonSeqPfS_lPfS_l
	.globl	_Z26nonCoalescedGMAccessNonSeqPfS_l
	.type	_Z26nonCoalescedGMAccessNonSeqPfS_l, @function
_Z26nonCoalescedGMAccessNonSeqPfS_l:
.LFB2062:
	.cfi_startproc
	endbr64
	jmp	_Z49__device_stub__Z26nonCoalescedGMAccessNonSeqPfS_lPfS_l
	.cfi_endproc
.LFE2062:
	.size	_Z26nonCoalescedGMAccessNonSeqPfS_l, .-_Z26nonCoalescedGMAccessNonSeqPfS_l
	.globl	_Z56__device_stub__Z33nonCoalescedGMAccessNonContiguousPfS_lPfS_l
	.type	_Z56__device_stub__Z33nonCoalescedGMAccessNonContiguousPfS_lPfS_l, @function
_Z56__device_stub__Z33nonCoalescedGMAccessNonContiguousPfS_lPfS_l:
.LFB2063:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L42
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z33nonCoalescedGMAccessNonContiguousPfS_l(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L42:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L44
	call	__stack_chk_fail@PLT
.L44:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2063:
	.size	_Z56__device_stub__Z33nonCoalescedGMAccessNonContiguousPfS_lPfS_l, .-_Z56__device_stub__Z33nonCoalescedGMAccessNonContiguousPfS_lPfS_l
	.globl	_Z33nonCoalescedGMAccessNonContiguousPfS_l
	.type	_Z33nonCoalescedGMAccessNonContiguousPfS_l, @function
_Z33nonCoalescedGMAccessNonContiguousPfS_l:
.LFB2064:
	.cfi_startproc
	endbr64
	jmp	_Z56__device_stub__Z33nonCoalescedGMAccessNonContiguousPfS_lPfS_l
	.cfi_endproc
.LFE2064:
	.size	_Z33nonCoalescedGMAccessNonContiguousPfS_l, .-_Z33nonCoalescedGMAccessNonContiguousPfS_l
	.globl	_Z55__device_stub__Z26nonCoalescedGMAccessFloat3P6float3PflP6float3Pfl
	.type	_Z55__device_stub__Z26nonCoalescedGMAccessFloat3P6float3PflP6float3Pfl, @function
_Z55__device_stub__Z26nonCoalescedGMAccessFloat3P6float3PflP6float3Pfl:
.LFB2065:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L47
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z26nonCoalescedGMAccessFloat3P6float3Pfl(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L47:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L49
	call	__stack_chk_fail@PLT
.L49:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2065:
	.size	_Z55__device_stub__Z26nonCoalescedGMAccessFloat3P6float3PflP6float3Pfl, .-_Z55__device_stub__Z26nonCoalescedGMAccessFloat3P6float3PflP6float3Pfl
	.globl	_Z26nonCoalescedGMAccessFloat3P6float3Pfl
	.type	_Z26nonCoalescedGMAccessFloat3P6float3Pfl, @function
_Z26nonCoalescedGMAccessFloat3P6float3Pfl:
.LFB2066:
	.cfi_startproc
	endbr64
	jmp	_Z55__device_stub__Z26nonCoalescedGMAccessFloat3P6float3PflP6float3Pfl
	.cfi_endproc
.LFE2066:
	.size	_Z26nonCoalescedGMAccessFloat3P6float3Pfl, .-_Z26nonCoalescedGMAccessFloat3P6float3Pfl
	.section	.rodata.str1.1
.LC15:
	.string	"error in device memory allocation for - srcArray\n exiting out of the program.....\n"
.LC16:
	.string	"error in device memory allocation for -  destArray\n exiting out of the program.....\n"
.LC17:
	.string	"error in device memory allocation for - srcArray3\n exiting out of the program.....\n"
.LC23:
	.string	"\n\n**** successful termination of the program  ****\n\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	movl	$80000000, %esi
	pushq	%r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	pushq	%rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	subq	$360, %rsp
	.cfi_def_cfa_offset 400
	movq	%fs:40, %rax
	movq	%rax, 344(%rsp)
	xorl	%eax, %eax
	movq	%rsp, %rdi
	call	cudaMalloc@PLT
	leaq	.LC15(%rip), %rsi
	cmpl	$2, %eax
	je	.L80
	leaq	8(%rsp), %rdi
	movl	$80000000, %esi
	call	cudaMalloc@PLT
	cmpl	$2, %eax
	jne	.L54
	leaq	.LC16(%rip), %rsi
.L80:
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	orl	$-1, %edi
	call	exit@PLT
.L54:
	movl	$240000000, %esi
	leaq	16(%rsp), %rdi
	call	cudaMalloc@PLT
	leaq	.LC17(%rip), %rsi
	cmpl	$2, %eax
	je	.L80
	leaq	24(%rsp), %rdi
	call	cudaEventCreate@PLT
	leaq	32(%rsp), %rdi
	call	cudaEventCreate@PLT
	movl	$8388609, %edx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	salq	$9, %rdx
	movl	$1, %ecx
	movabsq	$4295006359, %rdi
	movl	$1, %esi
	movq	%rdx, 52(%rsp)
	movl	$1, 60(%rsp)
	movq	%rdi, 40(%rsp)
	movl	$1, 48(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L56
	movss	.LC18(%rip), %xmm0
	movq	(%rsp), %rdi
	movl	$20000000, %esi
	call	_Z29__device_stub__Z8setArrayPffiPffi
.L56:
	movl	$8388609, %edx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$1, %ecx
	salq	$9, %rdx
	movl	$1, %esi
	movabsq	$4295006359, %rdi
	movl	$1, 60(%rsp)
	movq	%rdx, 52(%rsp)
	movq	%rdi, 40(%rsp)
	movl	$1, 48(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L57
	movq	8(%rsp), %rdi
	movl	$20000000, %esi
	xorps	%xmm0, %xmm0
	call	_Z29__device_stub__Z8setArrayPffiPffi
.L57:
	movl	$8388609, %ebx
	leaq	64(%rsp), %r12
	leaq	104(%rsp), %r13
	movabsq	$4295006359, %rbp
	call	cudaThreadSynchronize@PLT
	salq	$9, %rbx
.L64:
	movq	24(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	%rbx, %rdx
	movl	$1, %ecx
	movq	%rbp, %rdi
	movl	$1, %esi
	movq	%rbx, 52(%rsp)
	movl	$1, 60(%rsp)
	movq	%rbp, 40(%rsp)
	movl	$1, 48(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L58
	movq	(%rsp), %rsi
	movq	8(%rsp), %rdi
	movl	$20000000, %edx
	call	_Z40__device_stub__Z17coalescedGMAccessPfS_lPfS_l
.L58:
	movq	32(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movq	32(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movq	32(%rsp), %rdx
	movq	24(%rsp), %rsi
	movq	%r12, %rdi
	call	cudaEventElapsedTime@PLT
	movq	24(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	%rbx, %rdx
	movl	$1, %ecx
	movq	%rbp, %rdi
	movl	$1, %esi
	movq	%rbx, 52(%rsp)
	movl	$1, 60(%rsp)
	movq	%rbp, 40(%rsp)
	movl	$1, 48(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L59
	movq	(%rsp), %rsi
	movq	8(%rsp), %rdi
	movl	$20000000, %edx
	call	_Z49__device_stub__Z26coalescedGMAccessDivergentPfS_lPfS_l
.L59:
	movq	32(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movq	32(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movq	32(%rsp), %rdx
	movq	24(%rsp), %rsi
	leaq	40(%r12), %rdi
	call	cudaEventElapsedTime@PLT
	movq	24(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	%rbx, %rdx
	movl	$1, %ecx
	movq	%rbp, %rdi
	movl	$1, %esi
	movq	%rbx, 52(%rsp)
	movl	$1, 60(%rsp)
	movq	%rbp, 40(%rsp)
	movl	$1, 48(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L60
	movq	(%rsp), %rsi
	movq	8(%rsp), %rdi
	movl	$20000000, %edx
	call	_Z49__device_stub__Z26nonCoalescedGMAccessNonSeqPfS_lPfS_l
.L60:
	movq	32(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movq	32(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movq	32(%rsp), %rdx
	movq	24(%rsp), %rsi
	leaq	80(%r12), %rdi
	call	cudaEventElapsedTime@PLT
	movq	24(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	%rbx, %rdx
	movl	$1, %ecx
	movq	%rbp, %rdi
	movl	$1, %esi
	movq	%rbx, 52(%rsp)
	movl	$1, 60(%rsp)
	movq	%rbp, 40(%rsp)
	movl	$1, 48(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L61
	movq	(%rsp), %rsi
	movq	8(%rsp), %rdi
	movl	$20000000, %edx
	call	_Z51__device_stub__Z28nonCoalescedGMAccessMisalignPfS_lPfS_l
.L61:
	movq	32(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movq	32(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movq	32(%rsp), %rdx
	movq	24(%rsp), %rsi
	leaq	120(%r12), %rdi
	call	cudaEventElapsedTime@PLT
	movq	24(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	%rbx, %rdx
	movl	$1, %ecx
	movq	%rbp, %rdi
	movl	$1, %esi
	movq	%rbx, 52(%rsp)
	movl	$1, 60(%rsp)
	movq	%rbp, 40(%rsp)
	movl	$1, 48(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L62
	movq	(%rsp), %rsi
	movq	8(%rsp), %rdi
	movl	$20000000, %edx
	call	_Z56__device_stub__Z33nonCoalescedGMAccessNonContiguousPfS_lPfS_l
.L62:
	movq	32(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movq	32(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movq	32(%rsp), %rdx
	movq	24(%rsp), %rsi
	leaq	160(%r12), %rdi
	call	cudaEventElapsedTime@PLT
	movq	24(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	%rbx, %rdx
	movl	$1, %ecx
	movq	%rbp, %rdi
	movl	$1, %esi
	movq	%rbx, 52(%rsp)
	movl	$1, 60(%rsp)
	movq	%rbp, 40(%rsp)
	movl	$1, 48(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L63
	movq	8(%rsp), %rsi
	movq	16(%rsp), %rdi
	movl	$20000000, %edx
	call	_Z55__device_stub__Z26nonCoalescedGMAccessFloat3P6float3PflP6float3Pfl
.L63:
	movq	32(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movq	32(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movq	32(%rsp), %rdx
	movq	24(%rsp), %rsi
	leaq	200(%r12), %rdi
	call	cudaEventElapsedTime@PLT
	movq	24(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movq	(%rsp), %rsi
	movq	8(%rsp), %rdi
	movl	$3, %ecx
	movl	$80000000, %edx
	call	cudaMemcpy@PLT
	movq	32(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movq	32(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movq	32(%rsp), %rdx
	movq	24(%rsp), %rsi
	leaq	240(%r12), %rdi
	addq	$4, %r12
	call	cudaEventElapsedTime@PLT
	cmpq	%r12, %r13
	jne	.L64
	movsd	.LC20(%rip), %xmm0
	leaq	68(%rsp), %rcx
	leaq	_ZL7avgtime(%rip), %rdx
	leaq	_ZL7mintime(%rip), %rsi
	leaq	_ZL7maxtime(%rip), %r8
	movsd	%xmm0, _ZL7mintime(%rip)
	movsd	%xmm0, 8+_ZL7mintime(%rip)
	movsd	%xmm0, 16+_ZL7mintime(%rip)
	movsd	%xmm0, 24+_ZL7mintime(%rip)
	movsd	%xmm0, 32+_ZL7mintime(%rip)
	movsd	%xmm0, 40+_ZL7mintime(%rip)
	movsd	%xmm0, 48+_ZL7mintime(%rip)
.L65:
	movq	%rcx, %rdi
	xorl	%eax, %eax
.L70:
	movsd	(%rdx,%rax), %xmm1
	cvtss2sd	(%rdi), %xmm0
	addq	$40, %rdi
	addsd	%xmm0, %xmm1
	movsd	%xmm1, (%rdx,%rax)
	movsd	(%rsi,%rax), %xmm1
	minsd	%xmm0, %xmm1
	movsd	%xmm1, (%rsi,%rax)
	movsd	(%r8,%rax), %xmm1
	maxsd	%xmm0, %xmm1
	movsd	%xmm1, (%r8,%rax)
	addq	$8, %rax
	cmpq	$56, %rax
	jne	.L70
	addq	$4, %rcx
	cmpq	%rcx, %r13
	jne	.L65
	movsd	.LC21(%rip), %xmm2
	xorl	%eax, %eax
	movsd	.LC22(%rip), %xmm1
	leaq	_ZL10bandWidths(%rip), %rcx
.L71:
	movsd	(%rdx,%rax,8), %xmm0
	divsd	%xmm2, %xmm0
	movsd	%xmm0, (%rdx,%rax,8)
	movaps	%xmm1, %xmm0
	divsd	(%rsi,%rax,8), %xmm0
	cvtsd2ss	%xmm0, %xmm0
	movss	%xmm0, (%rcx,%rax,4)
	incq	%rax
	cmpq	$7, %rax
	jne	.L71
	call	_Z12printResultsv
	leaq	.LC23(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movq	24(%rsp), %rdi
	call	cudaEventDestroy@PLT
	movq	32(%rsp), %rdi
	call	cudaEventDestroy@PLT
	movq	(%rsp), %rdi
	call	cudaFree@PLT
	movq	8(%rsp), %rdi
	call	cudaFree@PLT
	movq	344(%rsp), %rax
	subq	%fs:40, %rax
	je	.L72
	call	__stack_chk_fail@PLT
.L72:
	addq	$360, %rsp
	.cfi_def_cfa_offset 40
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2027:
	.size	main, .-main
	.section	.rodata.str1.1
.LC24:
	.string	"_Z26nonCoalescedGMAccessFloat3P6float3Pfl"
.LC25:
	.string	"_Z33nonCoalescedGMAccessNonContiguousPfS_l"
.LC26:
	.string	"_Z26nonCoalescedGMAccessNonSeqPfS_l"
.LC27:
	.string	"_Z28nonCoalescedGMAccessMisalignPfS_l"
.LC28:
	.string	"_Z8setArrayPffi"
.LC29:
	.string	"_Z26coalescedGMAccessDivergentPfS_l"
.LC30:
	.string	"_Z17coalescedGMAccessPfS_l"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2068:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC24(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z26nonCoalescedGMAccessFloat3P6float3Pfl(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC25(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z33nonCoalescedGMAccessNonContiguousPfS_l(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC26(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z26nonCoalescedGMAccessNonSeqPfS_l(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC27(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z28nonCoalescedGMAccessMisalignPfS_l(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC28(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z8setArrayPffi(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC29(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z26coalescedGMAccessDivergentPfS_l(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC30(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z17coalescedGMAccessPfS_l(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2068:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.local	_ZL10bandWidths
	.comm	_ZL10bandWidths,28,16
	.local	_ZL7mintime
	.comm	_ZL7mintime,56,32
	.local	_ZL7maxtime
	.comm	_ZL7maxtime,56,32
	.local	_ZL7avgtime
	.comm	_ZL7avgtime,56,32
	.section	.rodata.cst4,"aM",@progbits,4
	.align 4
.LC12:
	.long	1232348160
	.align 4
.LC18:
	.long	1065353216
	.section	.rodata.cst8,"aM",@progbits,8
	.align 8
.LC20:
	.long	-536870912
	.long	1206910975
	.align 8
.LC21:
	.long	0
	.long	1075970048
	.align 8
.LC22:
	.long	0
	.long	1101206224
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:



/********************************************************************************************

	
  source Code :  globalMemoryAccessPatterns.cu

  Objective   :  Example code to demonstrate the different access patterns of the global 
                 memory and the corresponding advantages in terms of the bandwidth that 
                 is achievable.

  Description : The six patterns that are discussed in the programming guide which the 
                program is implementing

		1) coalesced float memory access, resulting in a single memory transaction
		2) coalesced float memory access (divergent warp), resulting in a single 
                   memory transaction
		3) non-sequential float memory access, resulting in 16 memory transactions
		4) access with a misaligned starting address, resulting in 16 memory transactions
		5) non-contiguous float memory access, resulting in 16 memory transactions
		6) non-coalesced float3 memory access, resulting in 16 memory transactions

                 the six patterns along with the cudaMemcpy, the bandwidth is being calculated 

input       :   none

output      :	The different bandwidths that are achieved for different access patterns

Modified    :   Aug 2011
                

Author 	    :   RarchK		

*****************************************************************************************/

#include <hip/hip_runtime.h>
#include <stdio.h>
#include <float.h>

// there are six patterns that have been quoted in programming guide 2.3.1 for devices with compute capability 1.1
#define NO_OF_PATTERNS 6 

#define ARRAY_SIZE 20000000 // 20 MB
#define BLOCK_SIZE 512

#define NTIMES 10 

#define MIN(x,y) ((x)<(y)?(x):(y))
#define MAX(x,y) ((x)>(y)?(x):(y))

void printResults(void); // function declaration

//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
//
// the access pattern where successive threads are acceessing the successive memory locations in the Global memory
// and the array is aligned at (128)
// the first scenario from the performance guidelines of the programming guide
// coalesced float memory access, resulting in a single memory transaction
//
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////

__global__ void coalescedGMAccess(float* dest,float* src,long size)
{
	int idx = blockIdx.x * blockDim.x + threadIdx.x;
	if(idx < size)
		dest[idx] = src[idx];
}

///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////


///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
//
// the access pattern where successive threads are accessing the successive memory locations in the Global memory
// and array is aligned but some of the threads are not acessing any memory location
// the second scenario from the performance guide lines of the programming guide
// coalesced float memory access (divergent warp), resulting in a single memory transaction
//
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////

__global__ void coalescedGMAccessDivergent(float* dest,float* src,long size)
{
	int idx = blockIdx.x * blockDim.x + threadIdx.x;
	if(idx < size)
	//every warp there will be 4 threads that will not be accessing any memory location
		if(idx % 8 != 0) 
			dest[idx] = src[idx];
}

//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////


//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// 
// kernel for setting the array with given element
//
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////

__global__ void setArray(float *array,  float value, int size)
{
	int idx = threadIdx.x + blockIdx.x * blockDim.x;
	if (idx < size)
		array[idx] = value;
}

///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////


////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
//
// the access pattern where successive threads are accessing the successive memory locations in the Global memory 
// but the starting address is misaligned
// the fourth scenario from the performance guidelines of the programming guide
// access with a misaligned starting address, resulting in 16 memory transactions.
//
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////

__global__ void nonCoalescedGMAccessMisalign(float* dest,float* src,long size)
{
	int idx = blockIdx.x * blockDim.x + threadIdx.x;
	if(idx < size-1) // the last thread is skipped, it will not access any location
		dest[idx+1] = src[idx+1];
}

////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////




///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
//
// the access pattern where successive threads are not accessing the successive memory locations in the Global memory
// the starting address is aligned
// the third scenario from the performance guidelines of the programming guide
// non-sequential float memory access, resulting in 16 memory transactions
//
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////

__global__ void nonCoalescedGMAccessNonSeq(float* dest,float* src,long size)
{
	int idx = blockIdx.x * blockDim.x + threadIdx.x;
	if(idx < size)
	{

	//in each half warp the third thread accesses the location which would have been accessed by the fourth thread in coalesced access
	//and fourth thread accesses the location of the third thread in the coalesced access

		if(idx % 16 == 3)
			idx = 4;
		else if(idx % 16 == 4)
			idx = 3;
					
		dest[idx] = src[idx];

	}
}

///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////



/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
//
// the access pattern where the successive threads are not accessing the successive memory locations
// the starting address is aligned
// the fifth scenario from the performance guidelines of the programming guide
// non-contiguous float memory access, resulting in 16 memory transactions
//
/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////

__global__ void nonCoalescedGMAccessNonContiguous(float* dest,float* src,long size)
{
	int idx = blockIdx.x * blockDim.x + threadIdx.x;

	if(idx < size)
	{
		if(idx > 3) // threads with their id more than 3 will access the location id+1
			idx++;

		dest[idx] = src[idx];
	}


}

///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////



///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
//
// access pattern involves accessing contiguous float3 elements' first component by the contiguous threads
// the starting address is aligned
// the sixth scenario from the performance guidelines of the programming guide
// non-coalesced float3 memory access, resulting in 16 memory transactions
//
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////

__global__ void nonCoalescedGMAccessFloat3(float3 *src, float* dest,long size)
{
	int idx = blockIdx.x * blockDim.x + threadIdx.x;

	if(idx < size)
	{
		dest[idx] = src[idx].x;
	}

}

///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////




// one extra location to hold results for cudaMemcpy also other than the 6 patterns 

static double  avgtime[NO_OF_PATTERNS+1] = {0}, maxtime[NO_OF_PATTERNS+1] = {0}, mintime[NO_OF_PATTERNS+1];
static float bandWidths[NO_OF_PATTERNS+1] = {0}; 

////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
//
// the main routene 
// for timing the different access patterns 
// finding the band widths
//
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////

int main(int argc,char* argv[])
{
	float *srcArray , *destArray;
	float3 *srcArray3; // the array of float3 datatype
	float elapsedTimes[NO_OF_PATTERNS+1][NTIMES];
	hipEvent_t start,stop;
	hipError_t err = hipSuccess;
	
	double bytes = 2 * sizeof(float) * ARRAY_SIZE;

	// allocating the memory for the two arrays on the device
	// the memory allocated using cudaMalloc will give the memory address that is aligned (128)
	err = hipMalloc((void **)&srcArray,ARRAY_SIZE*sizeof(float));
	if(err == hipErrorOutOfMemory)
	{
		printf("error in device memory allocation for - srcArray\n exiting out of the program.....\n");
		exit(-1);
	}
	
	err = hipMalloc((void **)&destArray,ARRAY_SIZE*sizeof(float));
	if(err == hipErrorOutOfMemory)
	{
		printf("error in device memory allocation for -  destArray\n exiting out of the program.....\n");
		exit(-1);
	}
	
	err = hipMalloc((void **)&srcArray3,ARRAY_SIZE*sizeof(float3));
	if(err == hipErrorOutOfMemory)
	{
		printf("error in device memory allocation for - srcArray3\n exiting out of the program.....\n");
		exit(-1);
	}
	
	// event creation, which will be used for timing the code
	hipEventCreate(&start);
	hipEventCreate(&stop);
	
	//finding the 1D grid size 
	int gridSize = ARRAY_SIZE/BLOCK_SIZE;
	
	if( ARRAY_SIZE % BLOCK_SIZE != 0 ) 
			gridSize += 1;
	
	// intializing the arrays on the device
	setArray <<< gridSize,BLOCK_SIZE >>> (srcArray,1.0f,ARRAY_SIZE);
	setArray <<< gridSize,BLOCK_SIZE >>> (destArray,0.0f,ARRAY_SIZE);

	hipDeviceSynchronize();

	// running each pattern NTIMES
	for(int k=0; k < NTIMES; k++)
	{
		// timing the kernels corresponding to different access patterns
			
			// PATTERN 1
   		// timing the code with coalesced float memory access, resulting in a single memory transaction from the Global memory
			hipEventRecord(start,0);
			coalescedGMAccess <<< gridSize,BLOCK_SIZE >>> (destArray,srcArray,ARRAY_SIZE);
			hipEventRecord(stop,0);
			hipEventSynchronize(stop);
			hipEventElapsedTime(&elapsedTimes[0][k],start,stop);


			// PATTERN 2
			// timing the code with coalesced float memory access (divergent warp), resulting in a single memory transaction from the Global memory
			hipEventRecord(start,0);
			coalescedGMAccessDivergent <<< gridSize,BLOCK_SIZE >>> (destArray,srcArray,ARRAY_SIZE);
			hipEventRecord(stop,0);
			hipEventSynchronize(stop);
			hipEventElapsedTime(&elapsedTimes[1][k],start,stop);


			// PATTERN 3
			//timing the code with non-sequential float memory access, resulting in 16 memory transactions from the Global memory
			hipEventRecord(start,0);
			nonCoalescedGMAccessNonSeq <<< gridSize,BLOCK_SIZE >>> (destArray,srcArray,ARRAY_SIZE);
			hipEventRecord(stop,0);
			hipEventSynchronize(stop);
			hipEventElapsedTime(&elapsedTimes[2][k],start,stop);


			// PATTERN 4
			//timing the code of access pattern with a misaligned starting address, resulting in 16 memory transactions from the Global memory
			hipEventRecord(start,0);
			nonCoalescedGMAccessMisalign <<< gridSize,BLOCK_SIZE >>> (destArray,srcArray,ARRAY_SIZE);
			hipEventRecord(stop,0);
			hipEventSynchronize(stop);
			hipEventElapsedTime(&elapsedTimes[3][k],start,stop);


			//PATTERN 5
			//timing the code with non-contiguous float memory access, resulting in 16 memory transactions
			hipEventRecord(start,0);
			nonCoalescedGMAccessNonContiguous <<< gridSize,BLOCK_SIZE >>> (destArray,srcArray,ARRAY_SIZE);
			hipEventRecord(stop,0);
			hipEventSynchronize(stop);
			hipEventElapsedTime(&elapsedTimes[4][k],start,stop);


			//PATTERN 6
			//timing the code for no-coalesced access of float3 array
			hipEventRecord(start,0);
			nonCoalescedGMAccessFloat3 <<< gridSize,BLOCK_SIZE >>> (srcArray3,destArray,ARRAY_SIZE);
			hipEventRecord(stop,0);
			hipEventSynchronize(stop);
			hipEventElapsedTime(&elapsedTimes[5][k],start,stop);
			
			//PATTERN 7
			//timing the code that uses the cudaMemcpy API call
			hipEventRecord(start,0);
			hipMemcpy(destArray,srcArray,ARRAY_SIZE * sizeof(float),hipMemcpyDeviceToDevice);
			hipEventRecord(stop,0);
			hipEventSynchronize(stop);
			hipEventElapsedTime(&elapsedTimes[6][k],start,stop);

	} // end of the for loop involving NTIMES


	// intializing the mintime array
	for(int i=0; i < NO_OF_PATTERNS+1;i++)
		mintime[i] = FLT_MAX;


   for (int k=1; k < NTIMES; k++) // skiping the first iteration
	{
	   for (int i=0; i < NO_OF_PATTERNS+1; i++)
	   {
	       avgtime[i] = avgtime[i] + elapsedTimes[i][k];
	       mintime[i] = MIN(mintime[i],elapsedTimes[i][k]);
	       maxtime[i] = MAX(maxtime[i], elapsedTimes[i][k]);
	   }
	}


	// calculation of the different band widths that are achieved by different access patterns that are given in the performane guide lines 
	
	for(int i=0; i < NO_OF_PATTERNS+1; i++)
	{
		avgtime[i] = avgtime[i]/(double)(NTIMES-1); // finding the average time
		bandWidths[i] = bytes/mintime[i];
	}

	printResults();

	printf("\n\n**** successful termination of the program  ****\n\n");
		

	hipEventDestroy(start);
	hipEventDestroy(stop);

	hipFree(srcArray);
	hipFree(destArray);

	return 0;
}

/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////



////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
//
// prints the results containig the minimum, maximum, average times that the different access patterns have taken
// the associated maximum bandwidth of the different patterns
//
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////

void printResults()
{

  printf("\nComparing different access patterns of the global memory for the devices with compute capability <= 1.1\n");
  printf("The array size (single precision): %d\n",ARRAY_SIZE);

  printf("\n-------------------------------------------------------------------------------------------------------------------------------\n");
  printf("Pattern \t\t\t\t Bandwidth (GB/sec) \t Avg time (ms)  \t Min time (ms)  \t Max time (ms)\n");
  printf("-------------------------------------------------------------------------------------------------------------------------------\n");

	// printing the results for different access patterns
	for(int i=0; i < NO_OF_PATTERNS+1; i++)
	{
		
		switch(i)
		{
			case 0: printf("coalesced access                  ");
					  break;

			case 1: printf("coalesced access (divergent warp) ");
					  break;
			
			case 2: printf("non-sequential access             ");
					  break;

			case 3: printf("accessing  misaligned address     ");
					  break;

			case 4: printf("non-contiguous access             ");
					  break;

			case 5: printf("non-coalesced float3 access       ");
					  break;

			case 6: printf("using hipMemcpy                  ");
					  break;

		}
		
		printf("\t %.6f \t\t %f \t\t  %f \t\t  %f\n",bandWidths[i]/1000000,avgtime[i],mintime[i],maxtime[i]);

  }
	
  
  printf("\n ------------------------------------------------------------------------------------------------------------------------------\n");

}

//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////


	.text
	.file	"globalMemoryAccessPatterns.hip"
	.globl	_Z32__device_stub__coalescedGMAccessPfS_l # -- Begin function _Z32__device_stub__coalescedGMAccessPfS_l
	.type	_Z32__device_stub__coalescedGMAccessPfS_l,@function
_Z32__device_stub__coalescedGMAccessPfS_l: # @_Z32__device_stub__coalescedGMAccessPfS_l
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z17coalescedGMAccessPfS_l, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z32__device_stub__coalescedGMAccessPfS_l, .Lfunc_end0-_Z32__device_stub__coalescedGMAccessPfS_l
	.cfi_endproc
                                        # -- End function
	.globl	_Z41__device_stub__coalescedGMAccessDivergentPfS_l # -- Begin function _Z41__device_stub__coalescedGMAccessDivergentPfS_l
	.type	_Z41__device_stub__coalescedGMAccessDivergentPfS_l,@function
_Z41__device_stub__coalescedGMAccessDivergentPfS_l: # @_Z41__device_stub__coalescedGMAccessDivergentPfS_l
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z26coalescedGMAccessDivergentPfS_l, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z41__device_stub__coalescedGMAccessDivergentPfS_l, .Lfunc_end1-_Z41__device_stub__coalescedGMAccessDivergentPfS_l
	.cfi_endproc
                                        # -- End function
	.globl	_Z23__device_stub__setArrayPffi # -- Begin function _Z23__device_stub__setArrayPffi
	.type	_Z23__device_stub__setArrayPffi,@function
_Z23__device_stub__setArrayPffi:        # @_Z23__device_stub__setArrayPffi
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$96, %rsp
	.cfi_def_cfa_offset 144
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	4(%rsp), %rcx
	movss	%xmm0, (%rcx)
	movq	%rsp, %rdx
	movl	%esi, (%rdx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rdx, 16(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z8setArrayPffi, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$112, %rsp
	.cfi_adjust_cfa_offset -112
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z23__device_stub__setArrayPffi, .Lfunc_end2-_Z23__device_stub__setArrayPffi
	.cfi_endproc
                                        # -- End function
	.globl	_Z43__device_stub__nonCoalescedGMAccessMisalignPfS_l # -- Begin function _Z43__device_stub__nonCoalescedGMAccessMisalignPfS_l
	.type	_Z43__device_stub__nonCoalescedGMAccessMisalignPfS_l,@function
_Z43__device_stub__nonCoalescedGMAccessMisalignPfS_l: # @_Z43__device_stub__nonCoalescedGMAccessMisalignPfS_l
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z28nonCoalescedGMAccessMisalignPfS_l, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	_Z43__device_stub__nonCoalescedGMAccessMisalignPfS_l, .Lfunc_end3-_Z43__device_stub__nonCoalescedGMAccessMisalignPfS_l
	.cfi_endproc
                                        # -- End function
	.globl	_Z41__device_stub__nonCoalescedGMAccessNonSeqPfS_l # -- Begin function _Z41__device_stub__nonCoalescedGMAccessNonSeqPfS_l
	.type	_Z41__device_stub__nonCoalescedGMAccessNonSeqPfS_l,@function
_Z41__device_stub__nonCoalescedGMAccessNonSeqPfS_l: # @_Z41__device_stub__nonCoalescedGMAccessNonSeqPfS_l
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z26nonCoalescedGMAccessNonSeqPfS_l, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end4:
	.size	_Z41__device_stub__nonCoalescedGMAccessNonSeqPfS_l, .Lfunc_end4-_Z41__device_stub__nonCoalescedGMAccessNonSeqPfS_l
	.cfi_endproc
                                        # -- End function
	.globl	_Z48__device_stub__nonCoalescedGMAccessNonContiguousPfS_l # -- Begin function _Z48__device_stub__nonCoalescedGMAccessNonContiguousPfS_l
	.type	_Z48__device_stub__nonCoalescedGMAccessNonContiguousPfS_l,@function
_Z48__device_stub__nonCoalescedGMAccessNonContiguousPfS_l: # @_Z48__device_stub__nonCoalescedGMAccessNonContiguousPfS_l
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z33nonCoalescedGMAccessNonContiguousPfS_l, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end5:
	.size	_Z48__device_stub__nonCoalescedGMAccessNonContiguousPfS_l, .Lfunc_end5-_Z48__device_stub__nonCoalescedGMAccessNonContiguousPfS_l
	.cfi_endproc
                                        # -- End function
	.globl	_Z41__device_stub__nonCoalescedGMAccessFloat3P15HIP_vector_typeIfLj3EEPfl # -- Begin function _Z41__device_stub__nonCoalescedGMAccessFloat3P15HIP_vector_typeIfLj3EEPfl
	.type	_Z41__device_stub__nonCoalescedGMAccessFloat3P15HIP_vector_typeIfLj3EEPfl,@function
_Z41__device_stub__nonCoalescedGMAccessFloat3P15HIP_vector_typeIfLj3EEPfl: # @_Z41__device_stub__nonCoalescedGMAccessFloat3P15HIP_vector_typeIfLj3EEPfl
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z26nonCoalescedGMAccessFloat3P15HIP_vector_typeIfLj3EEPfl, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end6:
	.size	_Z41__device_stub__nonCoalescedGMAccessFloat3P15HIP_vector_typeIfLj3EEPfl, .Lfunc_end6-_Z41__device_stub__nonCoalescedGMAccessFloat3P15HIP_vector_typeIfLj3EEPfl
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0                          # -- Begin function main
.LCPI7_0:
	.long	0x3f800000                      # float 1
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0
.LCPI7_1:
	.quad	0x4022000000000000              # double 9
.LCPI7_2:
	.quad	0x41a312d000000000              # double 1.6E+8
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	subq	$336, %rsp                      # imm = 0x150
	.cfi_def_cfa_offset 368
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	32(%rsp), %rdi
	movl	$80000000, %esi                 # imm = 0x4C4B400
	callq	hipMalloc
	cmpl	$2, %eax
	je	.LBB7_1
# %bb.3:
	leaq	24(%rsp), %rdi
	movl	$80000000, %esi                 # imm = 0x4C4B400
	callq	hipMalloc
	cmpl	$2, %eax
	je	.LBB7_4
# %bb.5:
	leaq	40(%rsp), %rdi
	movl	$240000000, %esi                # imm = 0xE4E1C00
	callq	hipMalloc
	cmpl	$2, %eax
	je	.LBB7_6
# %bb.7:
	movabsq	$4294967808, %rbx               # imm = 0x100000200
	leaq	16(%rsp), %rdi
	callq	hipEventCreate
	leaq	8(%rsp), %rdi
	callq	hipEventCreate
	leaq	38551(%rbx), %r14
	movq	%r14, %rdi
	movl	$1, %esi
	movq	%rbx, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB7_9
# %bb.8:
	movq	32(%rsp), %rdi
	movss	.LCPI7_0(%rip), %xmm0           # xmm0 = mem[0],zero,zero,zero
	movl	$20000000, %esi                 # imm = 0x1312D00
	callq	_Z23__device_stub__setArrayPffi
.LBB7_9:
	movq	%r14, %rdi
	movl	$1, %esi
	movq	%rbx, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB7_11
# %bb.10:
	movq	24(%rsp), %rdi
	xorps	%xmm0, %xmm0
	movl	$20000000, %esi                 # imm = 0x1312D00
	callq	_Z23__device_stub__setArrayPffi
.LBB7_11:
	callq	hipDeviceSynchronize
	xorl	%r15d, %r15d
.LBB7_12:                               # =>This Inner Loop Header: Depth=1
	movq	16(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	%r14, %rdi
	movl	$1, %esi
	movq	%rbx, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB7_14
# %bb.13:                               #   in Loop: Header=BB7_12 Depth=1
	movq	24(%rsp), %rdi
	movq	32(%rsp), %rsi
	movl	$20000000, %edx                 # imm = 0x1312D00
	callq	_Z32__device_stub__coalescedGMAccessPfS_l
.LBB7_14:                               #   in Loop: Header=BB7_12 Depth=1
	movq	8(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	8(%rsp), %rdi
	callq	hipEventSynchronize
	leaq	(%rsp,%r15), %rdi
	addq	$48, %rdi
	movq	16(%rsp), %rsi
	movq	8(%rsp), %rdx
	callq	hipEventElapsedTime
	movq	16(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	%r14, %rdi
	movl	$1, %esi
	movq	%rbx, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB7_16
# %bb.15:                               #   in Loop: Header=BB7_12 Depth=1
	movq	24(%rsp), %rdi
	movq	32(%rsp), %rsi
	movl	$20000000, %edx                 # imm = 0x1312D00
	callq	_Z41__device_stub__coalescedGMAccessDivergentPfS_l
.LBB7_16:                               #   in Loop: Header=BB7_12 Depth=1
	movq	8(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	8(%rsp), %rdi
	callq	hipEventSynchronize
	leaq	(%rsp,%r15), %rdi
	addq	$88, %rdi
	movq	16(%rsp), %rsi
	movq	8(%rsp), %rdx
	callq	hipEventElapsedTime
	movq	16(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	%r14, %rdi
	movl	$1, %esi
	movq	%rbx, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB7_18
# %bb.17:                               #   in Loop: Header=BB7_12 Depth=1
	movq	24(%rsp), %rdi
	movq	32(%rsp), %rsi
	movl	$20000000, %edx                 # imm = 0x1312D00
	callq	_Z41__device_stub__nonCoalescedGMAccessNonSeqPfS_l
.LBB7_18:                               #   in Loop: Header=BB7_12 Depth=1
	movq	8(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	8(%rsp), %rdi
	callq	hipEventSynchronize
	leaq	(%rsp,%r15), %rdi
	addq	$128, %rdi
	movq	16(%rsp), %rsi
	movq	8(%rsp), %rdx
	callq	hipEventElapsedTime
	movq	16(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	%r14, %rdi
	movl	$1, %esi
	movq	%rbx, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB7_20
# %bb.19:                               #   in Loop: Header=BB7_12 Depth=1
	movq	24(%rsp), %rdi
	movq	32(%rsp), %rsi
	movl	$20000000, %edx                 # imm = 0x1312D00
	callq	_Z43__device_stub__nonCoalescedGMAccessMisalignPfS_l
.LBB7_20:                               #   in Loop: Header=BB7_12 Depth=1
	movq	8(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	8(%rsp), %rdi
	callq	hipEventSynchronize
	leaq	(%rsp,%r15), %rdi
	addq	$168, %rdi
	movq	16(%rsp), %rsi
	movq	8(%rsp), %rdx
	callq	hipEventElapsedTime
	movq	16(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	%r14, %rdi
	movl	$1, %esi
	movq	%rbx, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB7_22
# %bb.21:                               #   in Loop: Header=BB7_12 Depth=1
	movq	24(%rsp), %rdi
	movq	32(%rsp), %rsi
	movl	$20000000, %edx                 # imm = 0x1312D00
	callq	_Z48__device_stub__nonCoalescedGMAccessNonContiguousPfS_l
.LBB7_22:                               #   in Loop: Header=BB7_12 Depth=1
	movq	8(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	8(%rsp), %rdi
	callq	hipEventSynchronize
	leaq	(%rsp,%r15), %rdi
	addq	$208, %rdi
	movq	16(%rsp), %rsi
	movq	8(%rsp), %rdx
	callq	hipEventElapsedTime
	movq	16(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	%r14, %rdi
	movl	$1, %esi
	movq	%rbx, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB7_24
# %bb.23:                               #   in Loop: Header=BB7_12 Depth=1
	movq	40(%rsp), %rdi
	movq	24(%rsp), %rsi
	movl	$20000000, %edx                 # imm = 0x1312D00
	callq	_Z41__device_stub__nonCoalescedGMAccessFloat3P15HIP_vector_typeIfLj3EEPfl
.LBB7_24:                               #   in Loop: Header=BB7_12 Depth=1
	movq	8(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	8(%rsp), %rdi
	callq	hipEventSynchronize
	leaq	(%rsp,%r15), %rdi
	addq	$248, %rdi
	movq	16(%rsp), %rsi
	movq	8(%rsp), %rdx
	callq	hipEventElapsedTime
	movq	16(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	24(%rsp), %rdi
	movq	32(%rsp), %rsi
	movl	$80000000, %edx                 # imm = 0x4C4B400
	movl	$3, %ecx
	callq	hipMemcpy
	movq	8(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	8(%rsp), %rdi
	callq	hipEventSynchronize
	leaq	(%rsp,%r15), %rdi
	addq	$288, %rdi                      # imm = 0x120
	movq	16(%rsp), %rsi
	movq	8(%rsp), %rdx
	callq	hipEventElapsedTime
	addq	$4, %r15
	cmpq	$40, %r15
	jne	.LBB7_12
# %bb.25:                               # %.preheader148.preheader
	movq	$-56, %rax
	movabsq	$5183643170566569984, %rcx      # imm = 0x47EFFFFFE0000000
.LBB7_26:                               # %.preheader148
                                        # =>This Inner Loop Header: Depth=1
	movq	%rcx, _ZL7mintime+56(%rax)
	addq	$8, %rax
	jne	.LBB7_26
# %bb.27:                               # %.preheader146.preheader
	movl	$1, %eax
	leaq	52(%rsp), %rcx
.LBB7_28:                               # %.preheader146
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB7_29 Depth 2
	movq	$-56, %rdx
	movq	%rcx, %rsi
.LBB7_29:                               #   Parent Loop BB7_28 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	xorps	%xmm0, %xmm0
	cvtss2sd	(%rsi), %xmm0
	movsd	_ZL7avgtime+56(%rdx), %xmm1     # xmm1 = mem[0],zero
	addsd	%xmm0, %xmm1
	movsd	%xmm1, _ZL7avgtime+56(%rdx)
	movsd	_ZL7mintime+56(%rdx), %xmm1     # xmm1 = mem[0],zero
	minsd	%xmm0, %xmm1
	movsd	%xmm1, _ZL7mintime+56(%rdx)
	movsd	_ZL7maxtime+56(%rdx), %xmm1     # xmm1 = mem[0],zero
	maxsd	%xmm0, %xmm1
	movsd	%xmm1, _ZL7maxtime+56(%rdx)
	addq	$40, %rsi
	addq	$8, %rdx
	jne	.LBB7_29
# %bb.30:                               #   in Loop: Header=BB7_28 Depth=1
	incq	%rax
	addq	$4, %rcx
	cmpq	$10, %rax
	jne	.LBB7_28
# %bb.31:                               # %.preheader.preheader
	movq	$-28, %rax
	movsd	.LCPI7_1(%rip), %xmm0           # xmm0 = mem[0],zero
	movsd	.LCPI7_2(%rip), %xmm1           # xmm1 = mem[0],zero
.LBB7_32:                               # %.preheader
                                        # =>This Inner Loop Header: Depth=1
	movsd	_ZL7avgtime+56(%rax,%rax), %xmm2 # xmm2 = mem[0],zero
	divsd	%xmm0, %xmm2
	movsd	%xmm2, _ZL7avgtime+56(%rax,%rax)
	movapd	%xmm1, %xmm2
	divsd	_ZL7mintime+56(%rax,%rax), %xmm2
	cvtsd2ss	%xmm2, %xmm2
	movss	%xmm2, _ZL10bandWidths+28(%rax)
	addq	$4, %rax
	jne	.LBB7_32
# %bb.33:
	callq	_Z12printResultsv
	movl	$.Lstr, %edi
	callq	puts@PLT
	movq	16(%rsp), %rdi
	callq	hipEventDestroy
	movq	8(%rsp), %rdi
	callq	hipEventDestroy
	movq	32(%rsp), %rdi
	callq	hipFree
	movq	24(%rsp), %rdi
	callq	hipFree
	xorl	%eax, %eax
	addq	$336, %rsp                      # imm = 0x150
	.cfi_def_cfa_offset 32
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.LBB7_1:
	.cfi_def_cfa_offset 368
	movl	$.Lstr.3, %edi
	jmp	.LBB7_2
.LBB7_4:
	movl	$.Lstr.2, %edi
	jmp	.LBB7_2
.LBB7_6:
	movl	$.Lstr.1, %edi
.LBB7_2:
	callq	puts@PLT
	movl	$-1, %edi
	callq	exit
.Lfunc_end7:
	.size	main, .Lfunc_end7-main
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0                          # -- Begin function _Z12printResultsv
.LCPI8_0:
	.long	0x49742400                      # float 1.0E+6
	.text
	.globl	_Z12printResultsv
	.type	_Z12printResultsv,@function
_Z12printResultsv:                      # @_Z12printResultsv
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset %rbx, -16
	movl	$.Lstr.4, %edi
	callq	puts@PLT
	movl	$.L.str.5, %edi
	movl	$20000000, %esi                 # imm = 0x1312D00
	xorl	%eax, %eax
	callq	printf
	movl	$.Lstr.5, %edi
	callq	puts@PLT
	movl	$.Lstr.6, %edi
	callq	puts@PLT
	movl	$.Lstr.7, %edi
	callq	puts@PLT
	xorl	%ebx, %ebx
.LBB8_1:                                # =>This Inner Loop Header: Depth=1
	cmpl	$6, %ebx
	ja	.LBB8_3
# %bb.2:                                # %switch.lookup
                                        #   in Loop: Header=BB8_1 Depth=1
	movq	.Lswitch.table._Z12printResultsv(,%rbx,8), %rdi
	xorl	%eax, %eax
	callq	printf
.LBB8_3:                                #   in Loop: Header=BB8_1 Depth=1
	movss	_ZL10bandWidths(,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
	divss	.LCPI8_0(%rip), %xmm0
	cvtss2sd	%xmm0, %xmm0
	movsd	_ZL7avgtime(,%rbx,8), %xmm1     # xmm1 = mem[0],zero
	movsd	_ZL7mintime(,%rbx,8), %xmm2     # xmm2 = mem[0],zero
	movsd	_ZL7maxtime(,%rbx,8), %xmm3     # xmm3 = mem[0],zero
	movl	$.L.str.16, %edi
	movb	$4, %al
	callq	printf
	incq	%rbx
	cmpq	$7, %rbx
	jne	.LBB8_1
# %bb.4:
	movl	$.Lstr.8, %edi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	puts@PLT                        # TAILCALL
.Lfunc_end8:
	.size	_Z12printResultsv, .Lfunc_end8-_Z12printResultsv
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB9_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB9_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z17coalescedGMAccessPfS_l, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z26coalescedGMAccessDivergentPfS_l, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z8setArrayPffi, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z28nonCoalescedGMAccessMisalignPfS_l, %esi
	movl	$.L__unnamed_4, %edx
	movl	$.L__unnamed_4, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z26nonCoalescedGMAccessNonSeqPfS_l, %esi
	movl	$.L__unnamed_5, %edx
	movl	$.L__unnamed_5, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z33nonCoalescedGMAccessNonContiguousPfS_l, %esi
	movl	$.L__unnamed_6, %edx
	movl	$.L__unnamed_6, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z26nonCoalescedGMAccessFloat3P15HIP_vector_typeIfLj3EEPfl, %esi
	movl	$.L__unnamed_7, %edx
	movl	$.L__unnamed_7, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end9:
	.size	__hip_module_ctor, .Lfunc_end9-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB10_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB10_2:
	retq
.Lfunc_end10:
	.size	__hip_module_dtor, .Lfunc_end10-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z17coalescedGMAccessPfS_l,@object # @_Z17coalescedGMAccessPfS_l
	.section	.rodata,"a",@progbits
	.globl	_Z17coalescedGMAccessPfS_l
	.p2align	3, 0x0
_Z17coalescedGMAccessPfS_l:
	.quad	_Z32__device_stub__coalescedGMAccessPfS_l
	.size	_Z17coalescedGMAccessPfS_l, 8

	.type	_Z26coalescedGMAccessDivergentPfS_l,@object # @_Z26coalescedGMAccessDivergentPfS_l
	.globl	_Z26coalescedGMAccessDivergentPfS_l
	.p2align	3, 0x0
_Z26coalescedGMAccessDivergentPfS_l:
	.quad	_Z41__device_stub__coalescedGMAccessDivergentPfS_l
	.size	_Z26coalescedGMAccessDivergentPfS_l, 8

	.type	_Z8setArrayPffi,@object         # @_Z8setArrayPffi
	.globl	_Z8setArrayPffi
	.p2align	3, 0x0
_Z8setArrayPffi:
	.quad	_Z23__device_stub__setArrayPffi
	.size	_Z8setArrayPffi, 8

	.type	_Z28nonCoalescedGMAccessMisalignPfS_l,@object # @_Z28nonCoalescedGMAccessMisalignPfS_l
	.globl	_Z28nonCoalescedGMAccessMisalignPfS_l
	.p2align	3, 0x0
_Z28nonCoalescedGMAccessMisalignPfS_l:
	.quad	_Z43__device_stub__nonCoalescedGMAccessMisalignPfS_l
	.size	_Z28nonCoalescedGMAccessMisalignPfS_l, 8

	.type	_Z26nonCoalescedGMAccessNonSeqPfS_l,@object # @_Z26nonCoalescedGMAccessNonSeqPfS_l
	.globl	_Z26nonCoalescedGMAccessNonSeqPfS_l
	.p2align	3, 0x0
_Z26nonCoalescedGMAccessNonSeqPfS_l:
	.quad	_Z41__device_stub__nonCoalescedGMAccessNonSeqPfS_l
	.size	_Z26nonCoalescedGMAccessNonSeqPfS_l, 8

	.type	_Z33nonCoalescedGMAccessNonContiguousPfS_l,@object # @_Z33nonCoalescedGMAccessNonContiguousPfS_l
	.globl	_Z33nonCoalescedGMAccessNonContiguousPfS_l
	.p2align	3, 0x0
_Z33nonCoalescedGMAccessNonContiguousPfS_l:
	.quad	_Z48__device_stub__nonCoalescedGMAccessNonContiguousPfS_l
	.size	_Z33nonCoalescedGMAccessNonContiguousPfS_l, 8

	.type	_Z26nonCoalescedGMAccessFloat3P15HIP_vector_typeIfLj3EEPfl,@object # @_Z26nonCoalescedGMAccessFloat3P15HIP_vector_typeIfLj3EEPfl
	.globl	_Z26nonCoalescedGMAccessFloat3P15HIP_vector_typeIfLj3EEPfl
	.p2align	3, 0x0
_Z26nonCoalescedGMAccessFloat3P15HIP_vector_typeIfLj3EEPfl:
	.quad	_Z41__device_stub__nonCoalescedGMAccessFloat3P15HIP_vector_typeIfLj3EEPfl
	.size	_Z26nonCoalescedGMAccessFloat3P15HIP_vector_typeIfLj3EEPfl, 8

	.type	_ZL7mintime,@object             # @_ZL7mintime
	.local	_ZL7mintime
	.comm	_ZL7mintime,56,16
	.type	_ZL7avgtime,@object             # @_ZL7avgtime
	.local	_ZL7avgtime
	.comm	_ZL7avgtime,56,16
	.type	_ZL7maxtime,@object             # @_ZL7maxtime
	.local	_ZL7maxtime
	.comm	_ZL7maxtime,56,16
	.type	_ZL10bandWidths,@object         # @_ZL10bandWidths
	.local	_ZL10bandWidths
	.comm	_ZL10bandWidths,28,16
	.type	.L.str.5,@object                # @.str.5
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str.5:
	.asciz	"The array size (single precision): %d\n"
	.size	.L.str.5, 39

	.type	.L.str.9,@object                # @.str.9
.L.str.9:
	.asciz	"coalesced access                  "
	.size	.L.str.9, 35

	.type	.L.str.10,@object               # @.str.10
.L.str.10:
	.asciz	"coalesced access (divergent warp) "
	.size	.L.str.10, 35

	.type	.L.str.11,@object               # @.str.11
.L.str.11:
	.asciz	"non-sequential access             "
	.size	.L.str.11, 35

	.type	.L.str.12,@object               # @.str.12
.L.str.12:
	.asciz	"accessing  misaligned address     "
	.size	.L.str.12, 35

	.type	.L.str.13,@object               # @.str.13
.L.str.13:
	.asciz	"non-contiguous access             "
	.size	.L.str.13, 35

	.type	.L.str.14,@object               # @.str.14
.L.str.14:
	.asciz	"non-coalesced float3 access       "
	.size	.L.str.14, 35

	.type	.L.str.15,@object               # @.str.15
.L.str.15:
	.asciz	"using hipMemcpy                  "
	.size	.L.str.15, 34

	.type	.L.str.16,@object               # @.str.16
.L.str.16:
	.asciz	"\t %.6f \t\t %f \t\t  %f \t\t  %f\n"
	.size	.L.str.16, 28

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z17coalescedGMAccessPfS_l"
	.size	.L__unnamed_1, 27

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z26coalescedGMAccessDivergentPfS_l"
	.size	.L__unnamed_2, 36

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z8setArrayPffi"
	.size	.L__unnamed_3, 16

	.type	.L__unnamed_4,@object           # @3
.L__unnamed_4:
	.asciz	"_Z28nonCoalescedGMAccessMisalignPfS_l"
	.size	.L__unnamed_4, 38

	.type	.L__unnamed_5,@object           # @4
.L__unnamed_5:
	.asciz	"_Z26nonCoalescedGMAccessNonSeqPfS_l"
	.size	.L__unnamed_5, 36

	.type	.L__unnamed_6,@object           # @5
.L__unnamed_6:
	.asciz	"_Z33nonCoalescedGMAccessNonContiguousPfS_l"
	.size	.L__unnamed_6, 43

	.type	.L__unnamed_7,@object           # @6
.L__unnamed_7:
	.asciz	"_Z26nonCoalescedGMAccessFloat3P15HIP_vector_typeIfLj3EEPfl"
	.size	.L__unnamed_7, 59

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.type	.Lstr,@object                   # @str
	.section	.rodata.str1.1,"aMS",@progbits,1
.Lstr:
	.asciz	"\n\n**** successful termination of the program  ****\n"
	.size	.Lstr, 52

	.type	.Lstr.1,@object                 # @str.1
.Lstr.1:
	.asciz	"error in device memory allocation for - srcArray3\n exiting out of the program....."
	.size	.Lstr.1, 83

	.type	.Lstr.2,@object                 # @str.2
.Lstr.2:
	.asciz	"error in device memory allocation for -  destArray\n exiting out of the program....."
	.size	.Lstr.2, 84

	.type	.Lstr.3,@object                 # @str.3
.Lstr.3:
	.asciz	"error in device memory allocation for - srcArray\n exiting out of the program....."
	.size	.Lstr.3, 82

	.type	.Lstr.4,@object                 # @str.4
.Lstr.4:
	.asciz	"\nComparing different access patterns of the global memory for the devices with compute capability <= 1.1"
	.size	.Lstr.4, 105

	.type	.Lstr.5,@object                 # @str.5
.Lstr.5:
	.asciz	"\n-------------------------------------------------------------------------------------------------------------------------------"
	.size	.Lstr.5, 129

	.type	.Lstr.6,@object                 # @str.6
.Lstr.6:
	.asciz	"Pattern \t\t\t\t Bandwidth (GB/sec) \t Avg time (ms)  \t Min time (ms)  \t Max time (ms)"
	.size	.Lstr.6, 82

	.type	.Lstr.7,@object                 # @str.7
.Lstr.7:
	.asciz	"-------------------------------------------------------------------------------------------------------------------------------"
	.size	.Lstr.7, 128

	.type	.Lstr.8,@object                 # @str.8
.Lstr.8:
	.asciz	"\n ------------------------------------------------------------------------------------------------------------------------------"
	.size	.Lstr.8, 129

	.type	.Lswitch.table._Z12printResultsv,@object # @switch.table._Z12printResultsv
	.section	.rodata,"a",@progbits
	.p2align	3, 0x0
.Lswitch.table._Z12printResultsv:
	.quad	.L.str.9
	.quad	.L.str.10
	.quad	.L.str.11
	.quad	.L.str.12
	.quad	.L.str.13
	.quad	.L.str.14
	.quad	.L.str.15
	.size	.Lswitch.table._Z12printResultsv, 56

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z32__device_stub__coalescedGMAccessPfS_l
	.addrsig_sym _Z41__device_stub__coalescedGMAccessDivergentPfS_l
	.addrsig_sym _Z23__device_stub__setArrayPffi
	.addrsig_sym _Z43__device_stub__nonCoalescedGMAccessMisalignPfS_l
	.addrsig_sym _Z41__device_stub__nonCoalescedGMAccessNonSeqPfS_l
	.addrsig_sym _Z48__device_stub__nonCoalescedGMAccessNonContiguousPfS_l
	.addrsig_sym _Z41__device_stub__nonCoalescedGMAccessFloat3P15HIP_vector_typeIfLj3EEPfl
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z17coalescedGMAccessPfS_l
	.addrsig_sym _Z26coalescedGMAccessDivergentPfS_l
	.addrsig_sym _Z8setArrayPffi
	.addrsig_sym _Z28nonCoalescedGMAccessMisalignPfS_l
	.addrsig_sym _Z26nonCoalescedGMAccessNonSeqPfS_l
	.addrsig_sym _Z33nonCoalescedGMAccessNonContiguousPfS_l
	.addrsig_sym _Z26nonCoalescedGMAccessFloat3P15HIP_vector_typeIfLj3EEPfl
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z17coalescedGMAccessPfS_l ; -- Begin function _Z17coalescedGMAccessPfS_l
	.globl	_Z17coalescedGMAccessPfS_l
	.p2align	8
	.type	_Z17coalescedGMAccessPfS_l,@function
_Z17coalescedGMAccessPfS_l:             ; @_Z17coalescedGMAccessPfS_l
; %bb.0:
	s_clause 0x1
	s_load_b32 s4, s[0:1], 0x24
	s_load_b64 s[2:3], s[0:1], 0x10
	s_waitcnt lgkmcnt(0)
	s_and_b32 s4, s4, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_i64_e32 vcc_lo, s[2:3], v[1:2]
	s_and_saveexec_b32 s2, vcc_lo
	s_cbranch_execz .LBB0_2
; %bb.1:
	s_load_b128 s[0:3], s[0:1], 0x0
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s2, v0
	v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
	v_add_co_u32 v0, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	global_load_b32 v2, v[2:3], off
	s_waitcnt vmcnt(0)
	global_store_b32 v[0:1], v2, off
.LBB0_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z17coalescedGMAccessPfS_l
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 4
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z17coalescedGMAccessPfS_l, .Lfunc_end0-_Z17coalescedGMAccessPfS_l
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 144
; NumSgprs: 18
; NumVgprs: 4
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 4
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z26coalescedGMAccessDivergentPfS_l ; -- Begin function _Z26coalescedGMAccessDivergentPfS_l
	.globl	_Z26coalescedGMAccessDivergentPfS_l
	.p2align	8
	.type	_Z26coalescedGMAccessDivergentPfS_l,@function
_Z26coalescedGMAccessDivergentPfS_l:    ; @_Z26coalescedGMAccessDivergentPfS_l
; %bb.0:
	s_clause 0x1
	s_load_b32 s4, s[0:1], 0x24
	s_load_b64 s[2:3], s[0:1], 0x10
	s_waitcnt lgkmcnt(0)
	s_and_b32 s4, s4, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
	v_ashrrev_i32_e32 v2, 31, v1
	v_and_b32_e32 v0, 7, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_i64_e32 vcc_lo, s[2:3], v[1:2]
	v_cmp_ne_u32_e64 s2, 0, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, vcc_lo, s2
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB1_2
; %bb.1:
	s_load_b128 s[0:3], s[0:1], 0x0
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s2, v0
	v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
	v_add_co_u32 v0, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	global_load_b32 v2, v[2:3], off
	s_waitcnt vmcnt(0)
	global_store_b32 v[0:1], v2, off
.LBB1_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z26coalescedGMAccessDivergentPfS_l
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 4
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z26coalescedGMAccessDivergentPfS_l, .Lfunc_end1-_Z26coalescedGMAccessDivergentPfS_l
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 164
; NumSgprs: 18
; NumVgprs: 4
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 4
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z8setArrayPffi         ; -- Begin function _Z8setArrayPffi
	.globl	_Z8setArrayPffi
	.p2align	8
	.type	_Z8setArrayPffi,@function
_Z8setArrayPffi:                        ; @_Z8setArrayPffi
; %bb.0:
	s_clause 0x1
	s_load_b32 s4, s[0:1], 0x1c
	s_load_b64 s[2:3], s[0:1], 0x8
	s_waitcnt lgkmcnt(0)
	s_and_b32 s4, s4, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
	v_cmp_gt_i32_e32 vcc_lo, s3, v1
	s_and_saveexec_b32 s3, vcc_lo
	s_cbranch_execz .LBB2_2
; %bb.1:
	s_load_b64 s[0:1], s[0:1], 0x0
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	v_mov_b32_e32 v2, s2
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v0, vcc_lo, s0, v0
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	global_store_b32 v[0:1], v2, off
.LBB2_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z8setArrayPffi
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 3
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_Z8setArrayPffi, .Lfunc_end2-_Z8setArrayPffi
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 124
; NumSgprs: 18
; NumVgprs: 3
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 3
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z28nonCoalescedGMAccessMisalignPfS_l ; -- Begin function _Z28nonCoalescedGMAccessMisalignPfS_l
	.globl	_Z28nonCoalescedGMAccessMisalignPfS_l
	.p2align	8
	.type	_Z28nonCoalescedGMAccessMisalignPfS_l,@function
_Z28nonCoalescedGMAccessMisalignPfS_l:  ; @_Z28nonCoalescedGMAccessMisalignPfS_l
; %bb.0:
	s_clause 0x1
	s_load_b32 s4, s[0:1], 0x24
	s_load_b64 s[2:3], s[0:1], 0x10
	s_waitcnt lgkmcnt(0)
	s_and_b32 s4, s4, 0xffff
	s_add_u32 s2, s2, -1
	v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
	s_addc_u32 s3, s3, -1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v2, 31, v1
	v_cmp_gt_i64_e32 vcc_lo, s[2:3], v[1:2]
	s_and_saveexec_b32 s2, vcc_lo
	s_cbranch_execz .LBB3_2
; %bb.1:
	s_load_b128 s[0:3], s[0:1], 0x0
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s2, v0
	v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
	v_add_co_u32 v0, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	global_load_b32 v2, v[2:3], off offset:4
	s_waitcnt vmcnt(0)
	global_store_b32 v[0:1], v2, off offset:4
.LBB3_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z28nonCoalescedGMAccessMisalignPfS_l
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 4
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end3:
	.size	_Z28nonCoalescedGMAccessMisalignPfS_l, .Lfunc_end3-_Z28nonCoalescedGMAccessMisalignPfS_l
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 148
; NumSgprs: 18
; NumVgprs: 4
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 4
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z26nonCoalescedGMAccessNonSeqPfS_l ; -- Begin function _Z26nonCoalescedGMAccessNonSeqPfS_l
	.globl	_Z26nonCoalescedGMAccessNonSeqPfS_l
	.p2align	8
	.type	_Z26nonCoalescedGMAccessNonSeqPfS_l,@function
_Z26nonCoalescedGMAccessNonSeqPfS_l:    ; @_Z26nonCoalescedGMAccessNonSeqPfS_l
; %bb.0:
	s_clause 0x1
	s_load_b32 s4, s[0:1], 0x24
	s_load_b64 s[2:3], s[0:1], 0x10
	s_waitcnt lgkmcnt(0)
	s_and_b32 s4, s4, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_i64_e32 vcc_lo, s[2:3], v[1:2]
	s_and_saveexec_b32 s2, vcc_lo
	s_cbranch_execz .LBB4_2
; %bb.1:
	v_lshrrev_b32_e32 v0, 28, v2
	s_load_b128 s[0:3], s[0:1], 0x0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v0, v1, v0
	v_and_b32_e32 v0, -16, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v0, v1, v0
	v_cmp_ne_u32_e32 vcc_lo, 4, v0
	v_cndmask_b32_e32 v1, 3, v1, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, 3, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v0, 4, v1, vcc_lo
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v2, vcc_lo, s2, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
	v_add_co_u32 v0, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	global_load_b32 v2, v[2:3], off
	s_waitcnt vmcnt(0)
	global_store_b32 v[0:1], v2, off
.LBB4_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z26nonCoalescedGMAccessNonSeqPfS_l
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 4
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end4:
	.size	_Z26nonCoalescedGMAccessNonSeqPfS_l, .Lfunc_end4-_Z26nonCoalescedGMAccessNonSeqPfS_l
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 196
; NumSgprs: 18
; NumVgprs: 4
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 4
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z33nonCoalescedGMAccessNonContiguousPfS_l ; -- Begin function _Z33nonCoalescedGMAccessNonContiguousPfS_l
	.globl	_Z33nonCoalescedGMAccessNonContiguousPfS_l
	.p2align	8
	.type	_Z33nonCoalescedGMAccessNonContiguousPfS_l,@function
_Z33nonCoalescedGMAccessNonContiguousPfS_l: ; @_Z33nonCoalescedGMAccessNonContiguousPfS_l
; %bb.0:
	s_clause 0x1
	s_load_b32 s4, s[0:1], 0x24
	s_load_b64 s[2:3], s[0:1], 0x10
	s_waitcnt lgkmcnt(0)
	s_and_b32 s4, s4, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_i64_e32 vcc_lo, s[2:3], v[1:2]
	s_and_saveexec_b32 s2, vcc_lo
	s_cbranch_execz .LBB5_2
; %bb.1:
	v_cmp_lt_i32_e32 vcc_lo, 3, v1
	s_load_b128 s[0:3], s[0:1], 0x0
	v_add_co_ci_u32_e32 v0, vcc_lo, 0, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v1, 31, v0
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s2, v0
	v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
	v_add_co_u32 v0, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	global_load_b32 v2, v[2:3], off
	s_waitcnt vmcnt(0)
	global_store_b32 v[0:1], v2, off
.LBB5_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z33nonCoalescedGMAccessNonContiguousPfS_l
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 4
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end5:
	.size	_Z33nonCoalescedGMAccessNonContiguousPfS_l, .Lfunc_end5-_Z33nonCoalescedGMAccessNonContiguousPfS_l
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 160
; NumSgprs: 18
; NumVgprs: 4
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 4
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z26nonCoalescedGMAccessFloat3P15HIP_vector_typeIfLj3EEPfl ; -- Begin function _Z26nonCoalescedGMAccessFloat3P15HIP_vector_typeIfLj3EEPfl
	.globl	_Z26nonCoalescedGMAccessFloat3P15HIP_vector_typeIfLj3EEPfl
	.p2align	8
	.type	_Z26nonCoalescedGMAccessFloat3P15HIP_vector_typeIfLj3EEPfl,@function
_Z26nonCoalescedGMAccessFloat3P15HIP_vector_typeIfLj3EEPfl: ; @_Z26nonCoalescedGMAccessFloat3P15HIP_vector_typeIfLj3EEPfl
; %bb.0:
	s_clause 0x1
	s_load_b32 s4, s[0:1], 0x24
	s_load_b64 s[2:3], s[0:1], 0x10
	s_waitcnt lgkmcnt(0)
	s_and_b32 s4, s4, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_i64_e32 vcc_lo, s[2:3], v[1:2]
	s_and_saveexec_b32 s2, vcc_lo
	s_cbranch_execz .LBB6_2
; %bb.1:
	s_load_b128 s[0:3], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	v_mad_i64_i32 v[3:4], null, v1, 12, s[0:1]
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_u32 v0, vcc_lo, s2, v0
	global_load_b32 v3, v[3:4], off
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b32 v[0:1], v3, off
.LBB6_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z26nonCoalescedGMAccessFloat3P15HIP_vector_typeIfLj3EEPfl
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 5
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end6:
	.size	_Z26nonCoalescedGMAccessFloat3P15HIP_vector_typeIfLj3EEPfl, .Lfunc_end6-_Z26nonCoalescedGMAccessFloat3P15HIP_vector_typeIfLj3EEPfl
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 140
; NumSgprs: 18
; NumVgprs: 5
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 5
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
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amdhsa.version:
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  - 2
...

	.end_amdgpu_metadata
