#include <cuda.h>
#include <math_constants.h>

#define ARRAY_SIZE(array) (sizeof(array) / sizeof((array)[0]))
#define NODES_PER_LAYER 4

struct Parameters {
  float ih[NODES_PER_LAYER][19];			// input->hidden edge weight
  float c[NODES_PER_LAYER][19];				// RBF center
  float w[NODES_PER_LAYER];					// RBF width
  float w2[NODES_PER_LAYER];				// RBF width second layer
  float ho[NODES_PER_LAYER];				// hidden->output edge weight
  float hh[NODES_PER_LAYER][NODES_PER_LAYER];// hidden->hidden edge weight
  float c2[NODES_PER_LAYER][NODES_PER_LAYER];// RBF center second layer
};

__global__ void evaluate(
  const float *trainSet,
  unsigned int trainSize,
  const Parameters *params,
  unsigned int popSize,
  float *outputs
) {
  const int trainIndex = blockIdx.x * blockDim.x + threadIdx.x;
  const int paramsIndex = blockIdx.y;
  const int outputIndex = paramsIndex * trainSize + trainIndex;
  
  if (trainIndex < trainSize && paramsIndex < popSize) {
    // Read input features.
    float inputs[19];
	float l2inputs[NODES_PER_LAYER] = {0.f};
    for (int i = 0; i < ARRAY_SIZE(inputs); i++) {
      inputs[i] = trainSet[i * trainSize + trainIndex];
    }
    
    // TODO: Read parameters into shared memory.
    const Parameters * const p = &params[paramsIndex];

    // Calculate network output.
	float output = 0.f;
    
    // TODO: Make sure this gets unrolled
    for (int j = 0; j < NODES_PER_LAYER; j++) {
      float d2 = 0.f; // input to hidden node j
      for (int i = 0; i < 19; i++) {
        const float d = inputs[i] * p->ih[j][i] - p->c[j][i];
        d2 += d * d;
      }
      
      const float h = __expf(-p->w[j] * d2); // Gaussian RBF

	  for (int i = 0; i < NODES_PER_LAYER; i++) {
		const float d = h * p->hh[j][i] - p->c2[j][i];
		l2inputs[i] += d * d;
	  }
    }

	for (int j = 0; j < NODES_PER_LAYER; j++) {
	  const float h = __expf(-p->w[j] * l2inputs[j]); // Gaussian RBF
      output += h * p->ho[j];
	}
    
    outputs[outputIndex] = output;
  }
}

#define heapparent(i) (((i) - 1) / 2)
#define heapleft(i)   (2 * ((i) + 1) - 1)
#define heapright(i)  (2 * ((i) + 1))
#define swap(a, b)    {float temp = (a); (a) = (b); (b) = temp; }

__device__ void heapreplace(
  float *heap,
  unsigned int size,
  float value
) {
  if (value < heap[0]) {
    return;
  }
  
  // Replace min (root) with new value.
  heap[0] = value;
  
  // Down-heap.
  int i = 0;
  while (heapleft(i) < size) { // stop before leaf level
    const int left = heapleft(i);
    const int right = heapright(i);
    
    int smallest;
    if (left < size && heap[left] < heap[i]) {
      smallest = left;
    } else {
      smallest = i;
    }
    
    if (right < size && heap[right] < heap[smallest]) {
      smallest = right;
    }
    
    if (smallest != i) {
      swap(heap[smallest], heap[i]);
      i = smallest;
    } else {
      break;
    }
  }
}

__global__ void nlargest(
  const float *outputs,
  unsigned int trainSize,
  unsigned int popSize,
  unsigned int n,
  float *thresholds,
  unsigned int *thresholdCounts
) {
  const int paramsIndex = blockIdx.y;
  
  if (paramsIndex < popSize) {
    float maxValue = thresholds[paramsIndex];
    unsigned int maxCount = thresholdCounts[paramsIndex];
    extern __shared__ float heap[/* n */];
    
    // First n values sink to the bottom of the heap.
    for (int i = 0; i < n; i++) {
      heap[i] = -CUDART_INF_F;
    }
    
    for (int trainIndex = 0; trainIndex < trainSize; trainIndex++) {
      const int outputIndex = paramsIndex * trainSize + trainIndex;
      const float output = outputs[outputIndex];
      if (isnan(output)) {
        continue;
      }
      
      if (output < maxValue) {
        heapreplace(heap, n, output);
      } else if (output == maxValue) {
        if (maxCount == 0) {
          heapreplace(heap, n, output);
        } else {
          maxCount--;
        }
      }
    }
    
    // If maxValue hasn't changed, carry over the number of occurrences from the
    // previous pass.
    if (maxValue == heap[0]) {
      maxCount = thresholdCounts[paramsIndex];
    } else {
      maxValue = heap[0];
      maxCount = 0;
    }
    
    // During the next pass, skip the occurrences of maxValue that were already
    // accounted for in this pass.
    for (int i = 0; i < n; i++) {
      if (maxValue == heap[i]) {
        maxCount++;
      }
    }
    
    thresholds[paramsIndex] = maxValue;
    thresholdCounts[paramsIndex] = maxCount;
  }
}

__global__ void count(
  const float *outputs,
  unsigned int trainSize,
  unsigned int trainPositives,
  unsigned int popSize,
  const float *thresholds,
  unsigned int *counts
) {
  const int paramsIndex = blockIdx.y;
  
  if (paramsIndex < popSize) {
    const float threshold = thresholds[paramsIndex];
    unsigned int count = 0;
    
    const int gridDimX = (trainSize + blockDim.x - 1) / blockDim.x;

    for (int blockX = 0; blockX < gridDimX; blockX++) {
      const int trainIndex = blockX * blockDim.x + threadIdx.x;
      
      if (trainIndex < trainPositives) {
        const float output = outputs[paramsIndex * trainSize + trainIndex];
        
        if (output > threshold) {
          count++;
        }
      }
    }
    
    counts[paramsIndex * blockDim.x + threadIdx.x] = count;
  }
}

	.file	"tmpxft_00278d77_00000000-6_ann_kernels_twolayer.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2011:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2011:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z11heapreplacePfjf
	.type	_Z11heapreplacePfjf, @function
_Z11heapreplacePfjf:
.LFB2008:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2008:
	.size	_Z11heapreplacePfjf, .-_Z11heapreplacePfjf
	.globl	_Z46__device_stub__Z8evaluatePKfjPK10ParametersjPfPKfjPK10ParametersjPf
	.type	_Z46__device_stub__Z8evaluatePKfjPK10ParametersjPfPKfjPK10ParametersjPf, @function
_Z46__device_stub__Z8evaluatePKfjPK10ParametersjPfPKfjPK10ParametersjPf:
.LFB2033:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rdi
	movl	%esi, 20(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	32(%rsp), %rdx
	movl	%ecx, 16(%rsp)
	leaq	40(%rsp), %rcx
	movq	%r8, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L4
	pushq	40(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z8evaluatePKfjPK10ParametersjPf(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 176
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L4:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L6
	call	__stack_chk_fail@PLT
.L6:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2033:
	.size	_Z46__device_stub__Z8evaluatePKfjPK10ParametersjPfPKfjPK10ParametersjPf, .-_Z46__device_stub__Z8evaluatePKfjPK10ParametersjPfPKfjPK10ParametersjPf
	.globl	_Z8evaluatePKfjPK10ParametersjPf
	.type	_Z8evaluatePKfjPK10ParametersjPf, @function
_Z8evaluatePKfjPK10ParametersjPf:
.LFB2034:
	.cfi_startproc
	endbr64
	jmp	_Z46__device_stub__Z8evaluatePKfjPK10ParametersjPfPKfjPK10ParametersjPf
	.cfi_endproc
.LFE2034:
	.size	_Z8evaluatePKfjPK10ParametersjPf, .-_Z8evaluatePKfjPK10ParametersjPf
	.globl	_Z35__device_stub__Z8nlargestPKfjjjPfPjPKfjjjPfPj
	.type	_Z35__device_stub__Z8nlargestPKfjjjPfPjPKfjjjPfPj, @function
_Z35__device_stub__Z8nlargestPKfjjjPfPjPKfjjjPfPj:
.LFB2035:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movl	%esi, 36(%rsp)
	leaq	84(%rsp), %rsi
	movl	%edx, 32(%rsp)
	leaq	56(%rsp), %rdx
	movl	%ecx, 28(%rsp)
	leaq	64(%rsp), %rcx
	movq	%r8, 16(%rsp)
	movq	%r9, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	36(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	28(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L10
	pushq	64(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z8nlargestPKfjjjPfPj(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 208
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L10:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L12
	call	__stack_chk_fail@PLT
.L12:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2035:
	.size	_Z35__device_stub__Z8nlargestPKfjjjPfPjPKfjjjPfPj, .-_Z35__device_stub__Z8nlargestPKfjjjPfPjPKfjjjPfPj
	.globl	_Z8nlargestPKfjjjPfPj
	.type	_Z8nlargestPKfjjjPfPj, @function
_Z8nlargestPKfjjjPfPj:
.LFB2036:
	.cfi_startproc
	endbr64
	jmp	_Z35__device_stub__Z8nlargestPKfjjjPfPjPKfjjjPfPj
	.cfi_endproc
.LFE2036:
	.size	_Z8nlargestPKfjjjPfPj, .-_Z8nlargestPKfjjjPfPj
	.globl	_Z33__device_stub__Z5countPKfjjjS0_PjPKfjjjS0_Pj
	.type	_Z33__device_stub__Z5countPKfjjjS0_PjPKfjjjS0_Pj, @function
_Z33__device_stub__Z5countPKfjjjS0_PjPKfjjjS0_Pj:
.LFB2037:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movl	%esi, 36(%rsp)
	leaq	84(%rsp), %rsi
	movl	%edx, 32(%rsp)
	leaq	56(%rsp), %rdx
	movl	%ecx, 28(%rsp)
	leaq	64(%rsp), %rcx
	movq	%r8, 16(%rsp)
	movq	%r9, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	36(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	28(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L15
	pushq	64(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z5countPKfjjjS0_Pj(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 208
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L15:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L17
	call	__stack_chk_fail@PLT
.L17:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2037:
	.size	_Z33__device_stub__Z5countPKfjjjS0_PjPKfjjjS0_Pj, .-_Z33__device_stub__Z5countPKfjjjS0_PjPKfjjjS0_Pj
	.globl	_Z5countPKfjjjS0_Pj
	.type	_Z5countPKfjjjS0_Pj, @function
_Z5countPKfjjjS0_Pj:
.LFB2038:
	.cfi_startproc
	endbr64
	jmp	_Z33__device_stub__Z5countPKfjjjS0_PjPKfjjjS0_Pj
	.cfi_endproc
.LFE2038:
	.size	_Z5countPKfjjjS0_Pj, .-_Z5countPKfjjjS0_Pj
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z5countPKfjjjS0_Pj"
.LC1:
	.string	"_Z8nlargestPKfjjjPfPj"
.LC2:
	.string	"_Z8evaluatePKfjPK10ParametersjPf"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2040:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z5countPKfjjjS0_Pj(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC1(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z8nlargestPKfjjjPfPj(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC2(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z8evaluatePKfjPK10ParametersjPf(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2040:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <hip/hip_runtime.h>
#include <hip/hip_math_constants.h>

#define ARRAY_SIZE(array) (sizeof(array) / sizeof((array)[0]))
#define NODES_PER_LAYER 4

struct Parameters {
  float ih[NODES_PER_LAYER][19];			// input->hidden edge weight
  float c[NODES_PER_LAYER][19];				// RBF center
  float w[NODES_PER_LAYER];					// RBF width
  float w2[NODES_PER_LAYER];				// RBF width second layer
  float ho[NODES_PER_LAYER];				// hidden->output edge weight
  float hh[NODES_PER_LAYER][NODES_PER_LAYER];// hidden->hidden edge weight
  float c2[NODES_PER_LAYER][NODES_PER_LAYER];// RBF center second layer
};

__global__ void evaluate(
  const float *trainSet,
  unsigned int trainSize,
  const Parameters *params,
  unsigned int popSize,
  float *outputs
) {
  const int trainIndex = blockIdx.x * blockDim.x + threadIdx.x;
  const int paramsIndex = blockIdx.y;
  const int outputIndex = paramsIndex * trainSize + trainIndex;
  
  if (trainIndex < trainSize && paramsIndex < popSize) {
    // Read input features.
    float inputs[19];
	float l2inputs[NODES_PER_LAYER] = {0.f};
    for (int i = 0; i < ARRAY_SIZE(inputs); i++) {
      inputs[i] = trainSet[i * trainSize + trainIndex];
    }
    
    // TODO: Read parameters into shared memory.
    const Parameters * const p = &params[paramsIndex];

    // Calculate network output.
	float output = 0.f;
    
    // TODO: Make sure this gets unrolled
    for (int j = 0; j < NODES_PER_LAYER; j++) {
      float d2 = 0.f; // input to hidden node j
      for (int i = 0; i < 19; i++) {
        const float d = inputs[i] * p->ih[j][i] - p->c[j][i];
        d2 += d * d;
      }
      
      const float h = __expf(-p->w[j] * d2); // Gaussian RBF

	  for (int i = 0; i < NODES_PER_LAYER; i++) {
		const float d = h * p->hh[j][i] - p->c2[j][i];
		l2inputs[i] += d * d;
	  }
    }

	for (int j = 0; j < NODES_PER_LAYER; j++) {
	  const float h = __expf(-p->w[j] * l2inputs[j]); // Gaussian RBF
      output += h * p->ho[j];
	}
    
    outputs[outputIndex] = output;
  }
}

#define heapparent(i) (((i) - 1) / 2)
#define heapleft(i)   (2 * ((i) + 1) - 1)
#define heapright(i)  (2 * ((i) + 1))
#define swap(a, b)    {float temp = (a); (a) = (b); (b) = temp; }

__device__ void heapreplace(
  float *heap,
  unsigned int size,
  float value
) {
  if (value < heap[0]) {
    return;
  }
  
  // Replace min (root) with new value.
  heap[0] = value;
  
  // Down-heap.
  int i = 0;
  while (heapleft(i) < size) { // stop before leaf level
    const int left = heapleft(i);
    const int right = heapright(i);
    
    int smallest;
    if (left < size && heap[left] < heap[i]) {
      smallest = left;
    } else {
      smallest = i;
    }
    
    if (right < size && heap[right] < heap[smallest]) {
      smallest = right;
    }
    
    if (smallest != i) {
      swap(heap[smallest], heap[i]);
      i = smallest;
    } else {
      break;
    }
  }
}

__global__ void nlargest(
  const float *outputs,
  unsigned int trainSize,
  unsigned int popSize,
  unsigned int n,
  float *thresholds,
  unsigned int *thresholdCounts
) {
  const int paramsIndex = blockIdx.y;
  
  if (paramsIndex < popSize) {
    float maxValue = thresholds[paramsIndex];
    unsigned int maxCount = thresholdCounts[paramsIndex];
    extern __shared__ float heap[/* n */];
    
    // First n values sink to the bottom of the heap.
    for (int i = 0; i < n; i++) {
      heap[i] = -HIP_INF_F;
    }
    
    for (int trainIndex = 0; trainIndex < trainSize; trainIndex++) {
      const int outputIndex = paramsIndex * trainSize + trainIndex;
      const float output = outputs[outputIndex];
      if (isnan(output)) {
        continue;
      }
      
      if (output < maxValue) {
        heapreplace(heap, n, output);
      } else if (output == maxValue) {
        if (maxCount == 0) {
          heapreplace(heap, n, output);
        } else {
          maxCount--;
        }
      }
    }
    
    // If maxValue hasn't changed, carry over the number of occurrences from the
    // previous pass.
    if (maxValue == heap[0]) {
      maxCount = thresholdCounts[paramsIndex];
    } else {
      maxValue = heap[0];
      maxCount = 0;
    }
    
    // During the next pass, skip the occurrences of maxValue that were already
    // accounted for in this pass.
    for (int i = 0; i < n; i++) {
      if (maxValue == heap[i]) {
        maxCount++;
      }
    }
    
    thresholds[paramsIndex] = maxValue;
    thresholdCounts[paramsIndex] = maxCount;
  }
}

__global__ void count(
  const float *outputs,
  unsigned int trainSize,
  unsigned int trainPositives,
  unsigned int popSize,
  const float *thresholds,
  unsigned int *counts
) {
  const int paramsIndex = blockIdx.y;
  
  if (paramsIndex < popSize) {
    const float threshold = thresholds[paramsIndex];
    unsigned int count = 0;
    
    const int gridDimX = (trainSize + blockDim.x - 1) / blockDim.x;

    for (int blockX = 0; blockX < gridDimX; blockX++) {
      const int trainIndex = blockX * blockDim.x + threadIdx.x;
      
      if (trainIndex < trainPositives) {
        const float output = outputs[paramsIndex * trainSize + trainIndex];
        
        if (output > threshold) {
          count++;
        }
      }
    }
    
    counts[paramsIndex * blockDim.x + threadIdx.x] = count;
  }
}

	.text
	.file	"ann_kernels_twolayer.hip"
	.globl	_Z23__device_stub__evaluatePKfjPK10ParametersjPf # -- Begin function _Z23__device_stub__evaluatePKfjPK10ParametersjPf
	.type	_Z23__device_stub__evaluatePKfjPK10ParametersjPf,@function
_Z23__device_stub__evaluatePKfjPK10ParametersjPf: # @_Z23__device_stub__evaluatePKfjPK10ParametersjPf
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	4(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	32(%rsp), %rsi
	movq	%rdx, (%rsi)
	movq	%rsp, %rdx
	movl	%ecx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z8evaluatePKfjPK10ParametersjPf, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z23__device_stub__evaluatePKfjPK10ParametersjPf, .Lfunc_end0-_Z23__device_stub__evaluatePKfjPK10ParametersjPf
	.cfi_endproc
                                        # -- End function
	.globl	_Z23__device_stub__nlargestPKfjjjPfPj # -- Begin function _Z23__device_stub__nlargestPKfjjjPfPj
	.type	_Z23__device_stub__nlargestPKfjjjPfPj,@function
_Z23__device_stub__nlargestPKfjjjPfPj:  # @_Z23__device_stub__nlargestPKfjjjPfPj
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	20(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	16(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	12(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	48(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	40(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z8nlargestPKfjjjPfPj, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z23__device_stub__nlargestPKfjjjPfPj, .Lfunc_end1-_Z23__device_stub__nlargestPKfjjjPfPj
	.cfi_endproc
                                        # -- End function
	.globl	_Z20__device_stub__countPKfjjjS0_Pj # -- Begin function _Z20__device_stub__countPKfjjjS0_Pj
	.type	_Z20__device_stub__countPKfjjjS0_Pj,@function
_Z20__device_stub__countPKfjjjS0_Pj:    # @_Z20__device_stub__countPKfjjjS0_Pj
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	20(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	16(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	12(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	48(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	40(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z5countPKfjjjS0_Pj, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z20__device_stub__countPKfjjjS0_Pj, .Lfunc_end2-_Z20__device_stub__countPKfjjjS0_Pj
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB3_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB3_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z8evaluatePKfjPK10ParametersjPf, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z8nlargestPKfjjjPfPj, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z5countPKfjjjS0_Pj, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end3:
	.size	__hip_module_ctor, .Lfunc_end3-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB4_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB4_2:
	retq
.Lfunc_end4:
	.size	__hip_module_dtor, .Lfunc_end4-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z8evaluatePKfjPK10ParametersjPf,@object # @_Z8evaluatePKfjPK10ParametersjPf
	.section	.rodata,"a",@progbits
	.globl	_Z8evaluatePKfjPK10ParametersjPf
	.p2align	3, 0x0
_Z8evaluatePKfjPK10ParametersjPf:
	.quad	_Z23__device_stub__evaluatePKfjPK10ParametersjPf
	.size	_Z8evaluatePKfjPK10ParametersjPf, 8

	.type	_Z8nlargestPKfjjjPfPj,@object   # @_Z8nlargestPKfjjjPfPj
	.globl	_Z8nlargestPKfjjjPfPj
	.p2align	3, 0x0
_Z8nlargestPKfjjjPfPj:
	.quad	_Z23__device_stub__nlargestPKfjjjPfPj
	.size	_Z8nlargestPKfjjjPfPj, 8

	.type	_Z5countPKfjjjS0_Pj,@object     # @_Z5countPKfjjjS0_Pj
	.globl	_Z5countPKfjjjS0_Pj
	.p2align	3, 0x0
_Z5countPKfjjjS0_Pj:
	.quad	_Z20__device_stub__countPKfjjjS0_Pj
	.size	_Z5countPKfjjjS0_Pj, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z8evaluatePKfjPK10ParametersjPf"
	.size	.L__unnamed_1, 33

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z8nlargestPKfjjjPfPj"
	.size	.L__unnamed_2, 22

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z5countPKfjjjS0_Pj"
	.size	.L__unnamed_3, 20

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z23__device_stub__evaluatePKfjPK10ParametersjPf
	.addrsig_sym _Z23__device_stub__nlargestPKfjjjPfPj
	.addrsig_sym _Z20__device_stub__countPKfjjjS0_Pj
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z8evaluatePKfjPK10ParametersjPf
	.addrsig_sym _Z8nlargestPKfjjjPfPj
	.addrsig_sym _Z5countPKfjjjS0_Pj
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z8evaluatePKfjPK10ParametersjPf ; -- Begin function _Z8evaluatePKfjPK10ParametersjPf
	.globl	_Z8evaluatePKfjPK10ParametersjPf
	.p2align	8
	.type	_Z8evaluatePKfjPK10ParametersjPf,@function
_Z8evaluatePKfjPK10ParametersjPf:       ; @_Z8evaluatePKfjPK10ParametersjPf
; %bb.0:
	s_clause 0x2
	s_load_b32 s2, s[0:1], 0x34
	s_load_b32 s20, s[0:1], 0x8
	s_load_b32 s3, s[0:1], 0x18
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[4:5], null, s14, s2, v[0:1]
	s_cmp_lt_u32 s15, s3
	s_cselect_b32 s2, -1, 0
	v_cmp_gt_u32_e32 vcc_lo, s20, v4
	s_and_b32 s2, s2, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_12
; %bb.1:
	s_load_b64 s[2:3], s[0:1], 0x0
	v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, v4
	s_mov_b32 s4, 0
.LBB0_2:                                ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
	v_lshlrev_b64 v[2:3], 2, v[0:1]
	v_add_nc_u32_e32 v0, s20, v0
	s_add_i32 s5, s4, 16
	s_add_i32 s4, s4, 4
	s_cmpk_eq_i32 s4, 0x4c
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v2, vcc_lo, s2, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
	global_load_b32 v2, v[2:3], off
	s_waitcnt vmcnt(0)
	scratch_store_b32 off, v2, s5
	s_cbranch_scc0 .LBB0_2
; %bb.3:
	s_load_b64 s[6:7], s[0:1], 0x10
	s_mov_b32 s9, 0
	s_mul_i32 s14, s15, 0x310
	s_mul_hi_i32 s5, s15, 0x310
	s_mov_b32 s8, s9
	s_mov_b32 s10, s9
	s_mov_b32 s11, s9
	v_dual_mov_b32 v0, s8 :: v_dual_mov_b32 v1, s9
	v_dual_mov_b32 v2, s10 :: v_dual_mov_b32 v3, s11
	s_mul_hi_i32 s21, s15, 0x310
	s_mul_i32 s22, s15, 0x310
	s_waitcnt lgkmcnt(0)
	s_add_u32 s2, s14, s6
	s_addc_u32 s3, s5, s7
	s_add_u32 s10, s2, 0x130
	s_addc_u32 s11, s3, 0
	s_add_u32 s12, s2, 0x290
	s_addc_u32 s13, s3, 0
.LBB0_4:                                ; %.preheader70
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_5 Depth 2
                                        ;     Child Loop BB0_7 Depth 2
	v_mov_b32_e32 v5, 0
	s_mov_b64 s[2:3], s[10:11]
	s_mov_b32 s4, 0
.LBB0_5:                                ;   Parent Loop BB0_4 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_i32 s16, s4, 16
	scratch_load_b32 v6, off, s16
	s_add_u32 s16, s2, 0xfffffed0
	s_addc_u32 s17, s3, -1
	s_clause 0x1
	s_load_b32 s16, s[16:17], 0x0
	s_load_b32 s17, s[2:3], 0x0
	s_add_i32 s4, s4, 4
	s_add_u32 s2, s2, 4
	s_addc_u32 s3, s3, 0
	s_cmpk_eq_i32 s4, 0x4c
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_fma_f32 v6, v6, s16, -s17
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v5, v6, v6
	s_cbranch_scc0 .LBB0_5
; %bb.6:                                ;   in Loop: Header=BB0_4 Depth=1
	s_add_u32 s4, s6, s22
	s_addc_u32 s16, s7, s21
	s_lshl_b64 s[2:3], s[8:9], 2
	s_mov_b64 s[18:19], s[12:13]
	s_add_u32 s2, s4, s2
	s_addc_u32 s3, s16, s3
	s_mov_b64 s[16:17], 0
	s_load_b32 s2, s[2:3], 0x260
	s_waitcnt lgkmcnt(0)
	v_mul_f32_e32 v5, s2, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v5, 0xbfb8aa3b, v5
	v_exp_f32_e32 v5, v5
.LBB0_7:                                ;   Parent Loop BB0_4 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_clause 0x1
	s_load_b32 s4, s[18:19], 0x0
	s_load_b32 s23, s[18:19], 0x40
	s_cmp_eq_u32 s16, 1
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s16, 2
	v_cndmask_b32_e32 v6, v0, v1, vcc_lo
	s_cselect_b32 s2, -1, 0
	s_cmp_eq_u32 s16, 3
	s_cselect_b32 s3, -1, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v6, v6, v2, s2
	s_cmp_eq_u32 s16, 0
	v_cndmask_b32_e64 v6, v6, v3, s3
	s_waitcnt lgkmcnt(0)
	s_waitcnt_depctr 0xfff
	v_fma_f32 v7, v5, s4, -s23
	s_cselect_b32 s4, -1, 0
	s_add_u32 s16, s16, 1
	s_addc_u32 s17, s17, 0
	s_add_u32 s18, s18, 4
	v_fmac_f32_e32 v6, v7, v7
	s_addc_u32 s19, s19, 0
	s_cmp_eq_u32 s16, 4
	s_delay_alu instid0(VALU_DEP_1)
	v_cndmask_b32_e64 v3, v3, v6, s3
	v_cndmask_b32_e64 v2, v2, v6, s2
	v_cndmask_b32_e32 v1, v1, v6, vcc_lo
	v_cndmask_b32_e64 v0, v0, v6, s4
	s_cbranch_scc0 .LBB0_7
; %bb.8:                                ;   in Loop: Header=BB0_4 Depth=1
	s_add_i32 s8, s8, 1
	s_add_u32 s10, s10, 0x4c
	s_addc_u32 s11, s11, 0
	s_add_u32 s12, s12, 16
	s_addc_u32 s13, s13, 0
	s_cmp_lg_u32 s8, 4
	s_cbranch_scc1 .LBB0_4
; %bb.9:                                ; %.preheader.preheader
	s_add_u32 s2, s14, s6
	v_mov_b32_e32 v5, 0
	s_addc_u32 s3, s5, s7
	s_add_u32 s2, s2, 0x260
	s_addc_u32 s3, s3, 0
	s_mov_b64 s[4:5], 0
.LBB0_10:                               ; %.preheader
                                        ; =>This Inner Loop Header: Depth=1
	s_clause 0x1
	s_load_b32 s6, s[2:3], 0x0
	s_load_b32 s7, s[2:3], 0x20
	s_cmp_eq_u32 s4, 1
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s4, 2
	v_cndmask_b32_e32 v6, v0, v1, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s4, 3
	s_waitcnt_depctr 0xfff
	v_cndmask_b32_e32 v6, v6, v2, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_add_u32 s4, s4, 1
	s_addc_u32 s5, s5, 0
	s_add_u32 s2, s2, 4
	v_cndmask_b32_e32 v6, v6, v3, vcc_lo
	s_addc_u32 s3, s3, 0
	s_cmp_eq_u32 s4, 4
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v6, s6, v6
	v_mul_f32_e32 v6, 0xbfb8aa3b, v6
	s_delay_alu instid0(VALU_DEP_1)
	v_exp_f32_e32 v6, v6
	s_waitcnt_depctr 0xfff
	v_fmac_f32_e32 v5, s7, v6
	s_cbranch_scc0 .LBB0_10
; %bb.11:
	s_load_b64 s[0:1], s[0:1], 0x20
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[0:1], null, s15, s20, v[4:5]
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v0, vcc_lo, s0, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	global_store_b32 v[0:1], v5, off
.LBB0_12:
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z8evaluatePKfjPK10ParametersjPf
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 96
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 1
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 8
		.amdhsa_next_free_sgpr 24
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z8evaluatePKfjPK10ParametersjPf, .Lfunc_end0-_Z8evaluatePKfjPK10ParametersjPf
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 836
; NumSgprs: 26
; NumVgprs: 8
; ScratchSize: 96
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 26
; NumVGPRsForWavesPerEU: 8
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 1
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z8nlargestPKfjjjPfPj   ; -- Begin function _Z8nlargestPKfjjjPfPj
	.globl	_Z8nlargestPKfjjjPfPj
	.p2align	8
	.type	_Z8nlargestPKfjjjPfPj,@function
_Z8nlargestPKfjjjPfPj:                  ; @_Z8nlargestPKfjjjPfPj
; %bb.0:
	s_load_b128 s[4:7], s[0:1], 0x8
	s_waitcnt lgkmcnt(0)
	s_cmp_ge_u32 s15, s5
	s_cbranch_scc1 .LBB1_40
; %bb.1:
	s_mov_b32 s10, s15
	s_load_b128 s[12:15], s[0:1], 0x18
	s_ashr_i32 s11, s10, 31
	s_mov_b32 s7, 0
	s_lshl_b64 s[8:9], s[10:11], 2
	s_waitcnt lgkmcnt(0)
	s_add_u32 s2, s12, s8
	s_addc_u32 s3, s13, s9
	s_add_u32 s8, s14, s8
	s_addc_u32 s9, s15, s9
	s_cmp_lg_u32 s6, 0
	s_cselect_b32 s5, -1, 0
	s_cmp_eq_u32 s6, 0
	s_cbranch_scc1 .LBB1_4
; %bb.2:                                ; %.lr.ph.preheader
	v_mov_b32_e32 v0, 0xff800000
	s_mov_b32 s11, s6
.LBB1_3:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	v_mov_b32_e32 v1, s7
	s_add_i32 s11, s11, -1
	s_add_i32 s7, s7, 4
	s_cmp_eq_u32 s11, 0
	ds_store_b32 v1, v0
	s_cbranch_scc0 .LBB1_3
.LBB1_4:                                ; %.preheader
	s_load_b32 s7, s[8:9], 0x0
	s_load_b32 s11, s[2:3], 0x0
	s_cmp_eq_u32 s4, 0
	s_cbranch_scc1 .LBB1_37
; %bb.5:                                ; %.lr.ph68
	s_load_b64 s[0:1], s[0:1], 0x0
	v_mov_b32_e32 v0, 0
	s_mul_i32 s10, s10, s4
	s_mov_b32 s12, 0
	s_waitcnt lgkmcnt(0)
	s_mov_b32 s13, s7
.LBB1_6:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB1_15 Depth 2
                                        ;     Child Loop BB1_27 Depth 2
	s_add_i32 s14, s12, s10
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_ashr_i32 s15, s14, 31
	s_lshl_b64 s[14:15], s[14:15], 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	s_add_u32 s14, s0, s14
	s_addc_u32 s15, s1, s15
	s_load_b32 s14, s[14:15], 0x0
	s_waitcnt lgkmcnt(0)
	v_cmp_u_f32_e64 s15, s14, s14
	s_and_b32 vcc_lo, exec_lo, s15
	s_cbranch_vccnz .LBB1_36
; %bb.7:                                ;   in Loop: Header=BB1_6 Depth=1
	v_cmp_nlt_f32_e64 s15, s14, s11
	s_mov_b32 s16, -1
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 vcc_lo, exec_lo, s15
                                        ; implicit-def: $sgpr15
	s_cbranch_vccz .LBB1_24
; %bb.8:                                ;   in Loop: Header=BB1_6 Depth=1
	v_cmp_neq_f32_e64 s15, s14, s11
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 vcc_lo, exec_lo, s15
	s_mov_b32 s15, s13
	s_cbranch_vccnz .LBB1_23
; %bb.9:                                ;   in Loop: Header=BB1_6 Depth=1
	s_cmp_lg_u32 s13, 0
	s_cbranch_scc0 .LBB1_11
; %bb.10:                               ;   in Loop: Header=BB1_6 Depth=1
	s_add_i32 s15, s13, -1
	s_mov_b32 s16, 0
	s_branch .LBB1_12
.LBB1_11:                               ;   in Loop: Header=BB1_6 Depth=1
                                        ; implicit-def: $sgpr15
.LBB1_12:                               ; %Flow108
                                        ;   in Loop: Header=BB1_6 Depth=1
	s_and_not1_b32 vcc_lo, exec_lo, s16
	s_cbranch_vccnz .LBB1_23
; %bb.13:                               ;   in Loop: Header=BB1_6 Depth=1
	ds_load_b32 v1, v0
	s_waitcnt lgkmcnt(0)
	v_cmp_lt_f32_e32 vcc_lo, s14, v1
	s_cbranch_vccnz .LBB1_22
; %bb.14:                               ;   in Loop: Header=BB1_6 Depth=1
	v_mov_b32_e32 v1, s14
	s_mov_b32 s15, 0
	ds_store_b32 v0, v1
.LBB1_15:                               ;   Parent Loop BB1_6 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_lshl_b32 s19, s15, 1
	s_mov_b32 s18, -1
	s_or_b32 s17, s19, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_ge_u32 s17, s6
	s_cbranch_scc1 .LBB1_21
; %bb.16:                               ;   in Loop: Header=BB1_15 Depth=2
	s_lshl_b32 s16, s19, 2
	s_lshl_b32 s18, s15, 2
	s_add_i32 s20, s16, 0
	s_add_i32 s16, s18, 0
	s_delay_alu instid0(SALU_CYCLE_1)
	v_dual_mov_b32 v1, s20 :: v_dual_mov_b32 v2, s16
	s_add_i32 s18, s19, 2
	ds_load_b32 v3, v1 offset:4
	ds_load_b32 v1, v2
	s_waitcnt lgkmcnt(0)
	v_cmp_lt_f32_e32 vcc_lo, v3, v1
	s_and_b32 s19, vcc_lo, exec_lo
	s_cselect_b32 s17, s17, s15
	s_cmp_ge_u32 s18, s6
	s_cbranch_scc1 .LBB1_19
; %bb.17:                               ;   in Loop: Header=BB1_15 Depth=2
	s_lshl_b32 s19, s17, 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s19, s19, 0
	v_dual_mov_b32 v2, s20 :: v_dual_mov_b32 v3, s19
	ds_load_b32 v2, v2 offset:8
	ds_load_b32 v3, v3
	s_waitcnt lgkmcnt(0)
	v_cmp_nlt_f32_e32 vcc_lo, v2, v3
	s_cbranch_vccnz .LBB1_19
; %bb.18:                               ;   in Loop: Header=BB1_15 Depth=2
	s_mov_b32 s17, s18
.LBB1_19:                               ;   in Loop: Header=BB1_15 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_cmp_eq_u32 s17, s15
	s_cselect_b32 s18, -1, 0
	s_and_b32 vcc_lo, exec_lo, s18
	s_cbranch_vccnz .LBB1_21
; %bb.20:                               ;   in Loop: Header=BB1_15 Depth=2
	s_lshl_b32 s15, s17, 2
	v_mov_b32_e32 v4, s16
	s_add_i32 s15, s15, 0
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v2, s15
	s_mov_b32 s15, s17
	ds_load_b32 v3, v2
	ds_store_b32 v2, v1
	s_waitcnt lgkmcnt(1)
	ds_store_b32 v4, v3
.LBB1_21:                               ; %Flow105
                                        ;   in Loop: Header=BB1_15 Depth=2
	s_and_b32 vcc_lo, exec_lo, s18
	s_cbranch_vccz .LBB1_15
.LBB1_22:                               ; %Flow107
                                        ;   in Loop: Header=BB1_6 Depth=1
	s_mov_b32 s15, 0
.LBB1_23:                               ; %Flow110
                                        ;   in Loop: Header=BB1_6 Depth=1
	s_mov_b32 s16, 0
.LBB1_24:                               ; %Flow115
                                        ;   in Loop: Header=BB1_6 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s16
	s_cbranch_vccnz .LBB1_35
; %bb.25:                               ;   in Loop: Header=BB1_6 Depth=1
	ds_load_b32 v1, v0
	s_waitcnt lgkmcnt(0)
	v_cmp_lt_f32_e32 vcc_lo, s14, v1
	s_cbranch_vccnz .LBB1_34
; %bb.26:                               ;   in Loop: Header=BB1_6 Depth=1
	v_mov_b32_e32 v1, s14
	s_mov_b32 s14, 0
	ds_store_b32 v0, v1
.LBB1_27:                               ;   Parent Loop BB1_6 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_lshl_b32 s18, s14, 1
	s_mov_b32 s17, -1
	s_or_b32 s16, s18, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_ge_u32 s16, s6
	s_cbranch_scc1 .LBB1_33
; %bb.28:                               ;   in Loop: Header=BB1_27 Depth=2
	s_lshl_b32 s15, s18, 2
	s_lshl_b32 s17, s14, 2
	s_add_i32 s19, s15, 0
	s_add_i32 s15, s17, 0
	s_delay_alu instid0(SALU_CYCLE_1)
	v_dual_mov_b32 v1, s19 :: v_dual_mov_b32 v2, s15
	s_add_i32 s17, s18, 2
	ds_load_b32 v3, v1 offset:4
	ds_load_b32 v1, v2
	s_waitcnt lgkmcnt(0)
	v_cmp_lt_f32_e32 vcc_lo, v3, v1
	s_and_b32 s18, vcc_lo, exec_lo
	s_cselect_b32 s16, s16, s14
	s_cmp_ge_u32 s17, s6
	s_cbranch_scc1 .LBB1_31
; %bb.29:                               ;   in Loop: Header=BB1_27 Depth=2
	s_lshl_b32 s18, s16, 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s18, s18, 0
	v_dual_mov_b32 v2, s19 :: v_dual_mov_b32 v3, s18
	ds_load_b32 v2, v2 offset:8
	ds_load_b32 v3, v3
	s_waitcnt lgkmcnt(0)
	v_cmp_nlt_f32_e32 vcc_lo, v2, v3
	s_cbranch_vccnz .LBB1_31
; %bb.30:                               ;   in Loop: Header=BB1_27 Depth=2
	s_mov_b32 s16, s17
.LBB1_31:                               ;   in Loop: Header=BB1_27 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_cmp_eq_u32 s16, s14
	s_cselect_b32 s17, -1, 0
	s_and_b32 vcc_lo, exec_lo, s17
	s_cbranch_vccnz .LBB1_33
; %bb.32:                               ;   in Loop: Header=BB1_27 Depth=2
	s_lshl_b32 s14, s16, 2
	v_mov_b32_e32 v4, s15
	s_add_i32 s14, s14, 0
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v2, s14
	s_mov_b32 s14, s16
	ds_load_b32 v3, v2
	ds_store_b32 v2, v1
	s_waitcnt lgkmcnt(1)
	ds_store_b32 v4, v3
.LBB1_33:                               ; %Flow112
                                        ;   in Loop: Header=BB1_27 Depth=2
	s_and_b32 vcc_lo, exec_lo, s17
	s_cbranch_vccz .LBB1_27
.LBB1_34:                               ; %Flow113
                                        ;   in Loop: Header=BB1_6 Depth=1
	s_mov_b32 s15, s13
.LBB1_35:                               ; %Flow116
                                        ;   in Loop: Header=BB1_6 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s13, s15
.LBB1_36:                               ; %_Z11heapreplacePfjf.exit
                                        ;   in Loop: Header=BB1_6 Depth=1
	s_add_i32 s12, s12, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s12, s4
	s_cbranch_scc0 .LBB1_6
.LBB1_37:                               ; %._crit_edge
	v_mov_b32_e32 v0, 0
	s_mov_b32 s1, 0
	ds_load_b32 v0, v0
	s_waitcnt lgkmcnt(0)
	v_cmp_eq_f32_e32 vcc_lo, s11, v0
	v_cndmask_b32_e64 v0, v0, s11, vcc_lo
	s_and_b32 s0, vcc_lo, exec_lo
	s_cselect_b32 s0, s7, 0
	s_and_not1_b32 vcc_lo, exec_lo, s5
	s_cbranch_vccnz .LBB1_39
.LBB1_38:                               ; %.lr.ph72
                                        ; =>This Inner Loop Header: Depth=1
	v_mov_b32_e32 v1, s1
	ds_load_b32 v1, v1
	s_waitcnt lgkmcnt(0)
	v_cmp_eq_f32_e32 vcc_lo, v0, v1
	s_cmp_lg_u32 vcc_lo, 0
	s_addc_u32 s0, s0, 0
	s_add_i32 s6, s6, -1
	s_add_i32 s1, s1, 4
	s_cmp_eq_u32 s6, 0
	s_cbranch_scc0 .LBB1_38
.LBB1_39:                               ; %Flow103
	v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v2, s0
	s_clause 0x1
	global_store_b32 v1, v0, s[2:3]
	global_store_b32 v1, v2, s[8:9]
.LBB1_40:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z8nlargestPKfjjjPfPj
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 40
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 5
		.amdhsa_next_free_sgpr 21
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z8nlargestPKfjjjPfPj, .Lfunc_end1-_Z8nlargestPKfjjjPfPj
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1012
; NumSgprs: 23
; NumVgprs: 5
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 23
; NumVGPRsForWavesPerEU: 5
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z5countPKfjjjS0_Pj     ; -- Begin function _Z5countPKfjjjS0_Pj
	.globl	_Z5countPKfjjjS0_Pj
	.p2align	8
	.type	_Z5countPKfjjjS0_Pj,@function
_Z5countPKfjjjS0_Pj:                    ; @_Z5countPKfjjjS0_Pj
; %bb.0:
	s_load_b128 s[4:7], s[0:1], 0x8
	s_waitcnt lgkmcnt(0)
	s_cmp_ge_u32 s15, s6
	s_cbranch_scc1 .LBB2_7
; %bb.1:
	s_load_b32 s3, s[0:1], 0x34
	v_mov_b32_e32 v3, 0
	s_mov_b32 s2, s15
	s_waitcnt lgkmcnt(0)
	s_and_b32 s6, s3, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_cvt_f32_u32_e32 v1, s6
	s_sub_i32 s7, 0, s6
	s_add_i32 s8, s4, s6
	s_add_i32 s12, s8, -1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v1, v1
	s_load_b128 s[8:11], s[0:1], 0x18
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v1, 0x4f7ffffe, v1
	v_cvt_u32_f32_e32 v1, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s3, v1
	s_mul_i32 s7, s7, s3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_hi_u32 s7, s3, s7
	s_add_i32 s3, s3, s7
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_hi_u32 s3, s12, s3
	s_mul_i32 s7, s3, s6
	s_delay_alu instid0(SALU_CYCLE_1)
	s_sub_i32 s7, s12, s7
	s_add_i32 s12, s3, 1
	s_sub_i32 s13, s7, s6
	s_cmp_ge_u32 s7, s6
	s_cselect_b32 s3, s12, s3
	s_cselect_b32 s7, s13, s7
	s_add_i32 s12, s3, 1
	s_cmp_ge_u32 s7, s6
	s_cselect_b32 s7, s12, s3
	s_mov_b32 s12, 0
	s_cmp_lt_i32 s7, 1
	s_cbranch_scc1 .LBB2_6
; %bb.2:                                ; %.lr.ph
	s_ashr_i32 s3, s2, 31
	v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v2, 0
	s_lshl_b64 s[14:15], s[2:3], 2
	v_mov_b32_e32 v4, v0
	s_waitcnt lgkmcnt(0)
	s_add_u32 s8, s8, s14
	s_addc_u32 s9, s9, s15
	s_load_b32 s3, s[8:9], 0x0
	s_load_b64 s[0:1], s[0:1], 0x0
	s_mul_i32 s4, s2, s4
.LBB2_3:                                ; =>This Inner Loop Header: Depth=1
	s_mov_b32 s8, exec_lo
	v_cmpx_gt_u32_e64 s5, v4
	s_cbranch_execz .LBB2_5
; %bb.4:                                ;   in Loop: Header=BB2_3 Depth=1
	v_add_nc_u32_e32 v1, s4, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[5:6], 2, v[1:2]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v5, vcc_lo, s0, v5
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v6, vcc_lo, s1, v6, vcc_lo
	global_load_b32 v1, v[5:6], off
	s_waitcnt vmcnt(0)
	v_cmp_lt_f32_e32 vcc_lo, s3, v1
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
.LBB2_5:                                ;   in Loop: Header=BB2_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s8
	v_add_nc_u32_e32 v4, s6, v4
	s_add_i32 s12, s12, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_ge_i32 s12, s7
	s_cbranch_scc0 .LBB2_3
.LBB2_6:                                ; %Flow44
	v_mad_u64_u32 v[1:2], null, s2, s6, v[0:1]
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v0, vcc_lo, s10, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s11, v1, vcc_lo
	global_store_b32 v[0:1], v3, off
.LBB2_7:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z5countPKfjjjS0_Pj
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 7
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_Z5countPKfjjjS0_Pj, .Lfunc_end2-_Z5countPKfjjjS0_Pj
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 400
; NumSgprs: 18
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         44
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         52
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         54
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         56
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         58
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         60
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         62
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         104
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 296
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z8evaluatePKfjPK10ParametersjPf
    .private_segment_fixed_size: 96
    .sgpr_count:     26
    .sgpr_spill_count: 0
    .symbol:         _Z8evaluatePKfjPK10ParametersjPf.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     8
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .offset:         12
        .size:           4
        .value_kind:     by_value
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 40
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z8nlargestPKfjjjPfPj
    .private_segment_fixed_size: 0
    .sgpr_count:     23
    .sgpr_spill_count: 0
    .symbol:         _Z8nlargestPKfjjjPfPj.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     5
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .offset:         12
        .size:           4
        .value_kind:     by_value
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         44
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         52
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         54
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         56
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         58
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         60
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         62
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         104
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 296
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z5countPKfjjjS0_Pj
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z5countPKfjjjS0_Pj.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     7
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
