/* 
* INPUT:
* m: total num of points
* n: n dimensions
* k: num of nearest points
* V: point coordinates
* OUTPUT:
* out: k nearest neighbors
*/

#include<stdio.h>
#include<cuda.h>
#include<stdlib.h>

#define INIT_MAX 10000000
#define TILE_WIDTH 32
#define TILE_DEPTH 128
#define MAX_BLOCK_SIZE 256
#define MAX_PTRNUM_IN_SMEM 1024 

void showResult(int m, int k, int *out);

// compute the square of distance of the ith point and jth point
__global__ void computeDist(int m, int n, int *V, int *D)
{
	__shared__ int rowVector[TILE_WIDTH][TILE_DEPTH];
	__shared__ int colVector[TILE_DEPTH][TILE_WIDTH];
	__shared__ int dist[TILE_WIDTH][TILE_WIDTH];

	int bx = blockIdx.x;
   	int by = blockIdx.y;
	int tx = threadIdx.x;
	int ty = threadIdx.y;
	int row;
	int col;
	int px;
	int py;	

	for(py=ty; py<TILE_WIDTH; py+=blockDim.y)
	{
		for(px=tx; px<TILE_WIDTH; px+=blockDim.x)
		{
			row = by*TILE_WIDTH+py;
			col = bx*TILE_WIDTH+px;
			dist[py][px] = 0;
			__syncthreads();
		
			for(int i=0; i<(int)(ceil((float)n/TILE_DEPTH)); i++)
			{
				for(int j=tx; j<TILE_DEPTH; j+=blockDim.x)
				{
					rowVector[py][j] = V[row*n+i*TILE_DEPTH+j];
				}
				for(int j=ty; j<TILE_DEPTH; j+=blockDim.y)
				{		
					colVector[j][px] = V[col*n+i*TILE_DEPTH+j];
				}
				__syncthreads();
		
				for(int j=0; j<TILE_DEPTH; j++)
				{
					dist[py][px] += (rowVector[py][j]-colVector[j][px])*(rowVector[py][j]-colVector[j][px]);
				}
				__syncthreads();
			}
			D[row*m+col] = dist[py][px];
		}
	}
}

extern __shared__ int SMem[];

//find the min value and index in the count^th loop
__device__ int findMin(int m, int k, int count, int *D, int *out)
{
	int i = blockIdx.x;
  	int tid = threadIdx.x;

	int s = blockDim.x/2;
	int resultValue = INIT_MAX;
	int resultIndex = INIT_MAX;
	int indexBase = (m<MAX_PTRNUM_IN_SMEM)? m: MAX_PTRNUM_IN_SMEM;
	
	for(int num=0; num<m; num+=MAX_PTRNUM_IN_SMEM)
	{
		for(int j=tid; j<indexBase; j+=blockDim.x)
		{
			if(j+num == i)
			{
				SMem[j] = INIT_MAX;
			}
			else
			{
				SMem[j] = D[i*m+num+j];
			}
			//index
			SMem[indexBase+j] = j+num;
			__syncthreads();
		}
		if(tid < count)
		{
			if(out[i*k+tid]-num>=0 && out[i*k+tid]-num<indexBase)
			{
				SMem[ out[i*k+tid]-num ] = INIT_MAX;
			}
			__syncthreads();
		}
		__syncthreads();

//		for(s=indexBase/2; s>0; s>>=1) 
		for(s=indexBase/2; s>32; s>>=1) 
		{
			for(int j=tid; j<indexBase; j+=blockDim.x)
			{
				if(j < s) 
				{
					if(SMem[j] == SMem[j+s])
					{
						if(SMem[indexBase+j] > SMem[indexBase+j+s])
						{
							SMem[indexBase+j] = SMem[indexBase+j+s];
						}
					}
					else if(SMem[j] > SMem[j+s])
					{
						SMem[j] = SMem[j+s];
						SMem[indexBase+j] = SMem[indexBase+j+s];
					}
				}
				__syncthreads();
			}
		}
/*
		if(indexBase >= 1024)
		{
			if(tid < 512) 
			{
				if(SMem[tid] == SMem[tid+512])
				{
					if(SMem[indexBase+tid] > SMem[indexBase+tid+512])
					{
						SMem[indexBase+tid] = SMem[indexBase+tid+512];
					}
				}
				else if(SMem[tid] > SMem[tid+512])
				{
					SMem[tid] = SMem[tid+512];
					SMem[indexBase+tid] = SMem[indexBase+tid+512];
				}
			}
			__syncthreads();
		}

		if(indexBase >= 512)
		{
			if(tid < 256) 
			{
				if(SMem[tid] == SMem[tid+256])
				{
					if(SMem[indexBase+tid] > SMem[indexBase+tid+256])
					{
						SMem[indexBase+tid] = SMem[indexBase+tid+256];
					}
				}
				else if(SMem[tid] > SMem[tid+256])
				{
					SMem[tid] = SMem[tid+256];
					SMem[indexBase+tid] = SMem[indexBase+tid+256];
				}
			}
			__syncthreads();
		}

		if(indexBase >= 256)
		{
			if(tid < 128) 
			{
				if(SMem[tid] == SMem[tid+128])
				{
					if(SMem[indexBase+tid] > SMem[indexBase+tid+128])
					{
						SMem[indexBase+tid] = SMem[indexBase+tid+128];
					}
				}
				else if(SMem[tid] > SMem[tid+128])
				{
					SMem[tid] = SMem[tid+128];
					SMem[indexBase+tid] = SMem[indexBase+tid+128];
				}
			}
			__syncthreads();
		}

		if(indexBase >= 128)
		{
			if(tid < 64) 
			{
				if(SMem[tid] == SMem[tid+64])
				{
					if(SMem[indexBase+tid] > SMem[indexBase+tid+64])
					{
						SMem[indexBase+tid] = SMem[indexBase+tid+64];
					}
				}
				else if(SMem[tid] > SMem[tid+64])
				{
					SMem[tid] = SMem[tid+64];
					SMem[indexBase+tid] = SMem[indexBase+tid+64];
				}
			}
			__syncthreads();
		}
*/
		if(tid < 32)
		{
			/*
			#pragma unroll 5
			for(s=32; s>0; s>>=1)
			{ 
				if(SMem[tid] == SMem[tid+s])
				{
					if(SMem[indexBase+tid] > SMem[indexBase+tid+s])
					{
						SMem[indexBase+tid] = SMem[indexBase+tid+s];
					}
				}
				else if(SMem[tid] > SMem[tid+s])
				{
					SMem[tid] = SMem[tid+s];
					SMem[indexBase+tid] = SMem[indexBase+tid+s];
				}
			}
			*/
			if(SMem[tid] == SMem[tid+32])
			{
				if(SMem[indexBase+tid] > SMem[indexBase+tid+32])
				{
					SMem[indexBase+tid] = SMem[indexBase+tid+32];
				}
			}
			else if(SMem[tid] > SMem[tid+32])
			{
				SMem[tid] = SMem[tid+32];
				SMem[indexBase+tid] = SMem[indexBase+tid+32];
			}
			if(SMem[tid] == SMem[tid+16])
			{
				if(SMem[indexBase+tid] > SMem[indexBase+tid+16])
				{
					SMem[indexBase+tid] = SMem[indexBase+tid+16];
				}
			}
			else if(SMem[tid] > SMem[tid+16])
			{
				SMem[tid] = SMem[tid+16];
				SMem[indexBase+tid] = SMem[indexBase+tid+16];
			}
			if(SMem[tid] == SMem[tid+8])
			{
				if(SMem[indexBase+tid] > SMem[indexBase+tid+8])
				{
					SMem[indexBase+tid] = SMem[indexBase+tid+8];
				}
			}
			else if(SMem[tid] > SMem[tid+8])
			{
				SMem[tid] = SMem[tid+8];
				SMem[indexBase+tid] = SMem[indexBase+tid+8];
			}
			if(SMem[tid] == SMem[tid+4])
			{
				if(SMem[indexBase+tid] > SMem[indexBase+tid+4])
				{
					SMem[indexBase+tid] = SMem[indexBase+tid+4];
				}
			}
			else if(SMem[tid] > SMem[tid+4])
			{
				SMem[tid] = SMem[tid+4];
				SMem[indexBase+tid] = SMem[indexBase+tid+4];
			}
			if(SMem[tid] == SMem[tid+2])
			{
				if(SMem[indexBase+tid] > SMem[indexBase+tid+2])
				{
					SMem[indexBase+tid] = SMem[indexBase+tid+2];
				}
			}
			else if(SMem[tid] > SMem[tid+2])
			{
				SMem[tid] = SMem[tid+2];
				SMem[indexBase+tid] = SMem[indexBase+tid+2];
			}
			if(SMem[tid] == SMem[tid+1])
			{
				if(SMem[indexBase+tid] > SMem[indexBase+tid+1])
				{
					SMem[indexBase+tid] = SMem[indexBase+tid+1];
				}
			}
			else if(SMem[tid] > SMem[tid+1])
			{
				SMem[tid] = SMem[tid+1];
				SMem[indexBase+tid] = SMem[indexBase+tid+1];
			}
		}
	
		__syncthreads();
		if(resultValue == SMem[0])
		{
			if(resultIndex > SMem[indexBase])
			{
				resultIndex = SMem[indexBase];
			}
		} 
		else if (resultValue > SMem[0])
		{
			resultValue = SMem[0];
			resultIndex = SMem[indexBase];
		}
		__syncthreads();
	}
	return resultIndex;

}

// compute the k nearest neighbors
__global__ void knn(int m, int k, int *V, int *D, int *out)
{
	int i;
	int count;

	i = blockIdx.x;
	__syncthreads();
	for(count=0; count<k; count++)
	{
		out[i*k+count] = findMin(m, k, count, D, out);
		__syncthreads();
	}
}

void showResult(int m, int k, int *out)
{
	int i,j;
	for(i=0; i<m; i++)
	{
		for(j=0; j<k; j++)
		{
			printf("%d ", out[i*k+j]);
			if(j == k-1)
			{
				printf("\n");
			}	
		}    	
	}        	
}            	

int main(int argc, char *argv[]) 
{ 
	int m,n,k;
	int i;
	int *V, *out;				//host copies
	int *d_V, *d_out;			//device copies
	int *D;						
	FILE *fp;
	if(argc != 2)
	{
		printf("Usage: knn <inputfile>\n");
		exit(1);
	}
	if((fp = fopen(argv[1], "r")) == NULL)
	{
		printf("Error open input file!\n");
		exit(1);
	}
	while(fscanf(fp, "%d %d %d", &m, &n, &k) != EOF)
	{
		V = (int *) malloc(m*n*sizeof(int));
		out = (int *) malloc(m*k*sizeof(int));

		for(i=0; i<m*n; i++)
		{
			fscanf(fp, "%d", &V[i]);
		}

		// compute the execution time
		cudaEvent_t start, stop;
		// create event
		cudaEventCreate(&start);
		cudaEventCreate(&stop);
		// record event
		cudaEventRecord(start);

		// allocate space for devices copies
		cudaMalloc((void **)&d_V, m*n*sizeof(int));
		cudaMalloc((void **)&d_out, m*k*sizeof(int));
		cudaMalloc((void **)&D, m*m*sizeof(int));

		// copy host values to devices copies
		cudaMemcpy(d_V, V, m*n*sizeof(int), cudaMemcpyHostToDevice);

		int gridDimX = (int)(ceil((float)m/TILE_WIDTH));
		int gridDimY = (int)(ceil((float)m/TILE_WIDTH));

		dim3 grid(gridDimX, gridDimY);
		dim3 block(TILE_WIDTH, TILE_WIDTH);

		// launch knn() kernel on GPU
		computeDist<<<grid, block>>>(m, n, d_V, D);
		cudaDeviceSynchronize();

		int threadNum = (m<MAX_BLOCK_SIZE)? m: MAX_BLOCK_SIZE;
		int ptrNumInSMEM = (m<MAX_PTRNUM_IN_SMEM)? m: MAX_PTRNUM_IN_SMEM;
		knn<<<m, threadNum, 2*ptrNumInSMEM*sizeof(int)>>>(m, k, d_V, D, d_out);

		// copy result back to host
		cudaMemcpy(out, d_out, m*k*sizeof(int), cudaMemcpyDeviceToHost);

		// cleanup
		cudaFree(d_V);
		cudaFree(d_out);
		cudaFree(D);

		// record event and synchronize
		cudaEventRecord(stop);
		cudaEventSynchronize(stop);
		float time;
		// get event elapsed time
		cudaEventElapsedTime(&time, start, stop);

		showResult(m, k, out);
		if(m == 1024) {
			printf("SMALL:");
		} else if(m == 4096) {
			printf("MIDDLE:");
		} else if(m == 16384) {
			printf("LARGE:");
		}
		printf("%f\n", time);

		free(V);
		free(out);
	}
	fclose(fp);
	return 0;
}


	.file	"tmpxft_00322d1d_00000000-6_knn.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2032:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2032:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z7findMiniiiPiS_
	.type	_Z7findMiniiiPiS_, @function
_Z7findMiniiiPiS_:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2027:
	.size	_Z7findMiniiiPiS_, .-_Z7findMiniiiPiS_
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"%d "
.LC1:
	.string	"\n"
	.text
	.globl	_Z10showResultiiPi
	.type	_Z10showResultiiPi, @function
_Z10showResultiiPi:
.LFB2028:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	movl	%edi, %r14d
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	xorl	%r13d, %r13d
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	xorl	%r12d, %r12d
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movl	%esi, %ebx
	subq	$24, %rsp
	.cfi_def_cfa_offset 80
	movq	%rdx, 8(%rsp)
.L5:
	cmpl	%r14d, %r13d
	jge	.L4
	movq	8(%rsp), %rcx
	movslq	%r12d, %rax
	xorl	%ebp, %ebp
	leaq	(%rcx,%rax,4), %r15
.L9:
	cmpl	%ebp, %ebx
	jle	.L12
	movl	(%r15,%rbp,4), %edx
	leaq	.LC0(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	leal	-1(%rbx), %eax
	cmpl	%ebp, %eax
	jne	.L6
	leaq	.LC1(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
.L6:
	incq	%rbp
	jmp	.L9
.L12:
	incl	%r13d
	addl	%ebx, %r12d
	jmp	.L5
.L4:
	addq	$24, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2028:
	.size	_Z10showResultiiPi, .-_Z10showResultiiPi
	.globl	_Z35__device_stub__Z11computeDistiiPiS_iiPiS_
	.type	_Z35__device_stub__Z11computeDistiiPiS_iiPiS_, @function
_Z35__device_stub__Z11computeDistiiPiS_iiPiS_:
.LFB2054:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movl	%edi, 28(%rsp)
	leaq	56(%rsp), %rdi
	movl	%esi, 24(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 16(%rsp)
	leaq	40(%rsp), %rdx
	movq	%rcx, 8(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	28(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L13
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z11computeDistiiPiS_(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L13:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L15
	call	__stack_chk_fail@PLT
.L15:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2054:
	.size	_Z35__device_stub__Z11computeDistiiPiS_iiPiS_, .-_Z35__device_stub__Z11computeDistiiPiS_iiPiS_
	.globl	_Z11computeDistiiPiS_
	.type	_Z11computeDistiiPiS_, @function
_Z11computeDistiiPiS_:
.LFB2055:
	.cfi_startproc
	endbr64
	jmp	_Z35__device_stub__Z11computeDistiiPiS_iiPiS_
	.cfi_endproc
.LFE2055:
	.size	_Z11computeDistiiPiS_, .-_Z11computeDistiiPiS_
	.globl	_Z28__device_stub__Z3knniiPiS_S_iiPiS_S_
	.type	_Z28__device_stub__Z3knniiPiS_S_iiPiS_S_, @function
_Z28__device_stub__Z3knniiPiS_S_iiPiS_S_:
.LFB2056:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movl	%edi, 28(%rsp)
	leaq	48(%rsp), %rdi
	movl	%esi, 24(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 16(%rsp)
	leaq	32(%rsp), %rdx
	movq	%rcx, 8(%rsp)
	leaq	40(%rsp), %rcx
	movq	%r8, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	28(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L18
	pushq	40(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z3knniiPiS_S_(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 176
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L18:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L20
	call	__stack_chk_fail@PLT
.L20:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2056:
	.size	_Z28__device_stub__Z3knniiPiS_S_iiPiS_S_, .-_Z28__device_stub__Z3knniiPiS_S_iiPiS_S_
	.globl	_Z3knniiPiS_S_
	.type	_Z3knniiPiS_S_, @function
_Z3knniiPiS_S_:
.LFB2057:
	.cfi_startproc
	endbr64
	jmp	_Z28__device_stub__Z3knniiPiS_S_iiPiS_S_
	.cfi_endproc
.LFE2057:
	.size	_Z3knniiPiS_S_, .-_Z3knniiPiS_S_
	.section	.rodata.str1.1
.LC2:
	.string	"Usage: knn <inputfile>\n"
.LC3:
	.string	"r"
.LC4:
	.string	"Error open input file!\n"
.LC5:
	.string	"%d"
.LC7:
	.string	"SMALL:"
.LC8:
	.string	"MIDDLE:"
.LC9:
	.string	"LARGE:"
.LC10:
	.string	"%f\n"
.LC11:
	.string	"%d %d %d"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2029:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$136, %rsp
	.cfi_def_cfa_offset 192
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	cmpl	$2, %edi
	je	.L24
	leaq	.LC2(%rip), %rsi
	movl	$2, %edi
	jmp	.L38
.L24:
	movq	8(%rsi), %rdi
	leaq	.LC3(%rip), %rsi
	leaq	.LC11(%rip), %r13
	call	fopen@PLT
	movq	%rax, %rbx
	testq	%rax, %rax
	jne	.L25
	leaq	.LC4(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
.L38:
	call	__printf_chk@PLT
	movl	$1, %edi
	call	exit@PLT
.L41:
	leaq	56(%rsp), %rdi
	call	cudaEventCreate@PLT
	leaq	64(%rsp), %rdi
	call	cudaEventCreate@PLT
	movq	56(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movl	20(%rsp), %esi
	imull	24(%rsp), %esi
	leaq	32(%rsp), %rdi
	movslq	%esi, %rsi
	salq	$2, %rsi
	call	cudaMalloc@PLT
	movl	20(%rsp), %esi
	imull	28(%rsp), %esi
	leaq	40(%rsp), %rdi
	movslq	%esi, %rsi
	salq	$2, %rsi
	call	cudaMalloc@PLT
	movl	20(%rsp), %esi
	leaq	48(%rsp), %rdi
	imull	%esi, %esi
	movslq	%esi, %rsi
	salq	$2, %rsi
	call	cudaMalloc@PLT
	movl	20(%rsp), %edx
	imull	24(%rsp), %edx
	movq	%r12, %rsi
	movq	32(%rsp), %rdi
	movl	$1, %ecx
	movslq	%edx, %rdx
	salq	$2, %rdx
	call	cudaMemcpy@PLT
	cvtsi2ssl	20(%rsp), %xmm0
	mulss	.LC6(%rip), %xmm0
	call	ceilf@PLT
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$1, %ecx
	cvttss2sil	%xmm0, %eax
	movl	$1, %esi
	movabsq	$137438953504, %rdx
	movl	%eax, 72(%rsp)
	movl	%eax, 76(%rsp)
	movq	72(%rsp), %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L28
	movq	48(%rsp), %rcx
	movq	32(%rsp), %rdx
	movl	24(%rsp), %esi
	movl	20(%rsp), %edi
	call	_Z35__device_stub__Z11computeDistiiPiS_iiPiS_
.L28:
	call	cudaDeviceSynchronize@PLT
	movl	20(%rsp), %eax
	movl	$256, %edx
	cmpl	%edx, %eax
	movl	%eax, 96(%rsp)
	cmovle	%eax, %edx
	movl	%edx, 108(%rsp)
	movabsq	$4294967297, %rdx
	movq	%rdx, 112(%rsp)
	movl	116(%rsp), %ecx
	movq	%rdx, 100(%rsp)
	movl	$1024, %edx
	movq	96(%rsp), %rdi
	cmpl	%edx, %eax
	movl	104(%rsp), %esi
	cmovg	%edx, %eax
	movq	108(%rsp), %rdx
	xorl	%r9d, %r9d
	addl	%eax, %eax
	cltq
	leaq	0(,%rax,4), %r8
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L29
	movq	40(%rsp), %r8
	movq	48(%rsp), %rcx
	movq	32(%rsp), %rdx
	movl	28(%rsp), %esi
	movl	20(%rsp), %edi
	call	_Z28__device_stub__Z3knniiPiS_S_iiPiS_S_
.L29:
	movl	20(%rsp), %edx
	imull	28(%rsp), %edx
	movl	$2, %ecx
	movq	40(%rsp), %rsi
	movq	8(%rsp), %rdi
	movslq	%edx, %rdx
	salq	$2, %rdx
	call	cudaMemcpy@PLT
	movq	32(%rsp), %rdi
	call	cudaFree@PLT
	movq	40(%rsp), %rdi
	call	cudaFree@PLT
	movq	48(%rsp), %rdi
	call	cudaFree@PLT
	movq	64(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movq	64(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movq	64(%rsp), %rdx
	movq	56(%rsp), %rsi
	leaq	108(%rsp), %rdi
	call	cudaEventElapsedTime@PLT
	movl	28(%rsp), %esi
	movq	8(%rsp), %rdx
	movl	20(%rsp), %edi
	call	_Z10showResultiiPi
	movl	20(%rsp), %eax
	leaq	.LC7(%rip), %rsi
	cmpl	$1024, %eax
	jne	.L39
.L37:
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
.L31:
	leaq	.LC10(%rip), %rsi
	movl	$2, %edi
	movb	$1, %al
	cvtss2sd	108(%rsp), %xmm0
	call	__printf_chk@PLT
	movq	%r12, %rdi
	call	free@PLT
	movq	8(%rsp), %rdi
	call	free@PLT
.L25:
	xorl	%eax, %eax
	leaq	24(%rsp), %rcx
	leaq	20(%rsp), %rdx
	movq	%r13, %rsi
	leaq	28(%rsp), %r8
	movq	%rbx, %rdi
	call	__isoc23_fscanf@PLT
	incl	%eax
	je	.L40
	movl	20(%rsp), %ebp
	movl	24(%rsp), %edi
	xorl	%r14d, %r14d
	leaq	.LC5(%rip), %r15
	imull	%ebp, %edi
	movslq	%edi, %rdi
	salq	$2, %rdi
	call	malloc@PLT
	imull	28(%rsp), %ebp
	movq	%rax, %r12
	movslq	%ebp, %rdi
	movq	%r12, %rbp
	salq	$2, %rdi
	call	malloc@PLT
	movq	%rax, 8(%rsp)
.L26:
	movl	20(%rsp), %eax
	imull	24(%rsp), %eax
	cmpl	%r14d, %eax
	jle	.L41
	movq	%rbp, %rdx
	movq	%r15, %rsi
	movq	%rbx, %rdi
	xorl	%eax, %eax
	call	__isoc23_fscanf@PLT
	incl	%r14d
	addq	$4, %rbp
	jmp	.L26
.L39:
	leaq	.LC8(%rip), %rsi
	cmpl	$4096, %eax
	je	.L37
	cmpl	$16384, %eax
	jne	.L31
	leaq	.LC9(%rip), %rsi
	jmp	.L37
.L40:
	movq	%rbx, %rdi
	call	fclose@PLT
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L34
	call	__stack_chk_fail@PLT
.L34:
	addq	$136, %rsp
	.cfi_def_cfa_offset 56
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2029:
	.size	main, .-main
	.section	.rodata.str1.1
.LC12:
	.string	"_Z3knniiPiS_S_"
.LC13:
	.string	"_Z11computeDistiiPiS_"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2059:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC12(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z3knniiPiS_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC13(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z11computeDistiiPiS_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2059:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst4,"aM",@progbits,4
	.align 4
.LC6:
	.long	1023410176
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

/* 
* INPUT:
* m: total num of points
* n: n dimensions
* k: num of nearest points
* V: point coordinates
* OUTPUT:
* out: k nearest neighbors
*/

#include<stdio.h>
#include<hip/hip_runtime.h>
#include<stdlib.h>

#define INIT_MAX 10000000
#define TILE_WIDTH 32
#define TILE_DEPTH 128
#define MAX_BLOCK_SIZE 256
#define MAX_PTRNUM_IN_SMEM 1024 

void showResult(int m, int k, int *out);

// compute the square of distance of the ith point and jth point
__global__ void computeDist(int m, int n, int *V, int *D)
{
	__shared__ int rowVector[TILE_WIDTH][TILE_DEPTH];
	__shared__ int colVector[TILE_DEPTH][TILE_WIDTH];
	__shared__ int dist[TILE_WIDTH][TILE_WIDTH];

	int bx = blockIdx.x;
   	int by = blockIdx.y;
	int tx = threadIdx.x;
	int ty = threadIdx.y;
	int row;
	int col;
	int px;
	int py;	

	for(py=ty; py<TILE_WIDTH; py+=blockDim.y)
	{
		for(px=tx; px<TILE_WIDTH; px+=blockDim.x)
		{
			row = by*TILE_WIDTH+py;
			col = bx*TILE_WIDTH+px;
			dist[py][px] = 0;
			__syncthreads();
		
			for(int i=0; i<(int)(ceil((float)n/TILE_DEPTH)); i++)
			{
				for(int j=tx; j<TILE_DEPTH; j+=blockDim.x)
				{
					rowVector[py][j] = V[row*n+i*TILE_DEPTH+j];
				}
				for(int j=ty; j<TILE_DEPTH; j+=blockDim.y)
				{		
					colVector[j][px] = V[col*n+i*TILE_DEPTH+j];
				}
				__syncthreads();
		
				for(int j=0; j<TILE_DEPTH; j++)
				{
					dist[py][px] += (rowVector[py][j]-colVector[j][px])*(rowVector[py][j]-colVector[j][px]);
				}
				__syncthreads();
			}
			D[row*m+col] = dist[py][px];
		}
	}
}

extern __shared__ int SMem[];

//find the min value and index in the count^th loop
__device__ int findMin(int m, int k, int count, int *D, int *out)
{
	int i = blockIdx.x;
  	int tid = threadIdx.x;

	int s = blockDim.x/2;
	int resultValue = INIT_MAX;
	int resultIndex = INIT_MAX;
	int indexBase = (m<MAX_PTRNUM_IN_SMEM)? m: MAX_PTRNUM_IN_SMEM;
	
	for(int num=0; num<m; num+=MAX_PTRNUM_IN_SMEM)
	{
		for(int j=tid; j<indexBase; j+=blockDim.x)
		{
			if(j+num == i)
			{
				SMem[j] = INIT_MAX;
			}
			else
			{
				SMem[j] = D[i*m+num+j];
			}
			//index
			SMem[indexBase+j] = j+num;
			__syncthreads();
		}
		if(tid < count)
		{
			if(out[i*k+tid]-num>=0 && out[i*k+tid]-num<indexBase)
			{
				SMem[ out[i*k+tid]-num ] = INIT_MAX;
			}
			__syncthreads();
		}
		__syncthreads();

//		for(s=indexBase/2; s>0; s>>=1) 
		for(s=indexBase/2; s>32; s>>=1) 
		{
			for(int j=tid; j<indexBase; j+=blockDim.x)
			{
				if(j < s) 
				{
					if(SMem[j] == SMem[j+s])
					{
						if(SMem[indexBase+j] > SMem[indexBase+j+s])
						{
							SMem[indexBase+j] = SMem[indexBase+j+s];
						}
					}
					else if(SMem[j] > SMem[j+s])
					{
						SMem[j] = SMem[j+s];
						SMem[indexBase+j] = SMem[indexBase+j+s];
					}
				}
				__syncthreads();
			}
		}
/*
		if(indexBase >= 1024)
		{
			if(tid < 512) 
			{
				if(SMem[tid] == SMem[tid+512])
				{
					if(SMem[indexBase+tid] > SMem[indexBase+tid+512])
					{
						SMem[indexBase+tid] = SMem[indexBase+tid+512];
					}
				}
				else if(SMem[tid] > SMem[tid+512])
				{
					SMem[tid] = SMem[tid+512];
					SMem[indexBase+tid] = SMem[indexBase+tid+512];
				}
			}
			__syncthreads();
		}

		if(indexBase >= 512)
		{
			if(tid < 256) 
			{
				if(SMem[tid] == SMem[tid+256])
				{
					if(SMem[indexBase+tid] > SMem[indexBase+tid+256])
					{
						SMem[indexBase+tid] = SMem[indexBase+tid+256];
					}
				}
				else if(SMem[tid] > SMem[tid+256])
				{
					SMem[tid] = SMem[tid+256];
					SMem[indexBase+tid] = SMem[indexBase+tid+256];
				}
			}
			__syncthreads();
		}

		if(indexBase >= 256)
		{
			if(tid < 128) 
			{
				if(SMem[tid] == SMem[tid+128])
				{
					if(SMem[indexBase+tid] > SMem[indexBase+tid+128])
					{
						SMem[indexBase+tid] = SMem[indexBase+tid+128];
					}
				}
				else if(SMem[tid] > SMem[tid+128])
				{
					SMem[tid] = SMem[tid+128];
					SMem[indexBase+tid] = SMem[indexBase+tid+128];
				}
			}
			__syncthreads();
		}

		if(indexBase >= 128)
		{
			if(tid < 64) 
			{
				if(SMem[tid] == SMem[tid+64])
				{
					if(SMem[indexBase+tid] > SMem[indexBase+tid+64])
					{
						SMem[indexBase+tid] = SMem[indexBase+tid+64];
					}
				}
				else if(SMem[tid] > SMem[tid+64])
				{
					SMem[tid] = SMem[tid+64];
					SMem[indexBase+tid] = SMem[indexBase+tid+64];
				}
			}
			__syncthreads();
		}
*/
		if(tid < 32)
		{
			/*
			#pragma unroll 5
			for(s=32; s>0; s>>=1)
			{ 
				if(SMem[tid] == SMem[tid+s])
				{
					if(SMem[indexBase+tid] > SMem[indexBase+tid+s])
					{
						SMem[indexBase+tid] = SMem[indexBase+tid+s];
					}
				}
				else if(SMem[tid] > SMem[tid+s])
				{
					SMem[tid] = SMem[tid+s];
					SMem[indexBase+tid] = SMem[indexBase+tid+s];
				}
			}
			*/
			if(SMem[tid] == SMem[tid+32])
			{
				if(SMem[indexBase+tid] > SMem[indexBase+tid+32])
				{
					SMem[indexBase+tid] = SMem[indexBase+tid+32];
				}
			}
			else if(SMem[tid] > SMem[tid+32])
			{
				SMem[tid] = SMem[tid+32];
				SMem[indexBase+tid] = SMem[indexBase+tid+32];
			}
			if(SMem[tid] == SMem[tid+16])
			{
				if(SMem[indexBase+tid] > SMem[indexBase+tid+16])
				{
					SMem[indexBase+tid] = SMem[indexBase+tid+16];
				}
			}
			else if(SMem[tid] > SMem[tid+16])
			{
				SMem[tid] = SMem[tid+16];
				SMem[indexBase+tid] = SMem[indexBase+tid+16];
			}
			if(SMem[tid] == SMem[tid+8])
			{
				if(SMem[indexBase+tid] > SMem[indexBase+tid+8])
				{
					SMem[indexBase+tid] = SMem[indexBase+tid+8];
				}
			}
			else if(SMem[tid] > SMem[tid+8])
			{
				SMem[tid] = SMem[tid+8];
				SMem[indexBase+tid] = SMem[indexBase+tid+8];
			}
			if(SMem[tid] == SMem[tid+4])
			{
				if(SMem[indexBase+tid] > SMem[indexBase+tid+4])
				{
					SMem[indexBase+tid] = SMem[indexBase+tid+4];
				}
			}
			else if(SMem[tid] > SMem[tid+4])
			{
				SMem[tid] = SMem[tid+4];
				SMem[indexBase+tid] = SMem[indexBase+tid+4];
			}
			if(SMem[tid] == SMem[tid+2])
			{
				if(SMem[indexBase+tid] > SMem[indexBase+tid+2])
				{
					SMem[indexBase+tid] = SMem[indexBase+tid+2];
				}
			}
			else if(SMem[tid] > SMem[tid+2])
			{
				SMem[tid] = SMem[tid+2];
				SMem[indexBase+tid] = SMem[indexBase+tid+2];
			}
			if(SMem[tid] == SMem[tid+1])
			{
				if(SMem[indexBase+tid] > SMem[indexBase+tid+1])
				{
					SMem[indexBase+tid] = SMem[indexBase+tid+1];
				}
			}
			else if(SMem[tid] > SMem[tid+1])
			{
				SMem[tid] = SMem[tid+1];
				SMem[indexBase+tid] = SMem[indexBase+tid+1];
			}
		}
	
		__syncthreads();
		if(resultValue == SMem[0])
		{
			if(resultIndex > SMem[indexBase])
			{
				resultIndex = SMem[indexBase];
			}
		} 
		else if (resultValue > SMem[0])
		{
			resultValue = SMem[0];
			resultIndex = SMem[indexBase];
		}
		__syncthreads();
	}
	return resultIndex;

}

// compute the k nearest neighbors
__global__ void knn(int m, int k, int *V, int *D, int *out)
{
	int i;
	int count;

	i = blockIdx.x;
	__syncthreads();
	for(count=0; count<k; count++)
	{
		out[i*k+count] = findMin(m, k, count, D, out);
		__syncthreads();
	}
}

void showResult(int m, int k, int *out)
{
	int i,j;
	for(i=0; i<m; i++)
	{
		for(j=0; j<k; j++)
		{
			printf("%d ", out[i*k+j]);
			if(j == k-1)
			{
				printf("\n");
			}	
		}    	
	}        	
}            	

int main(int argc, char *argv[]) 
{ 
	int m,n,k;
	int i;
	int *V, *out;				//host copies
	int *d_V, *d_out;			//device copies
	int *D;						
	FILE *fp;
	if(argc != 2)
	{
		printf("Usage: knn <inputfile>\n");
		exit(1);
	}
	if((fp = fopen(argv[1], "r")) == NULL)
	{
		printf("Error open input file!\n");
		exit(1);
	}
	while(fscanf(fp, "%d %d %d", &m, &n, &k) != EOF)
	{
		V = (int *) malloc(m*n*sizeof(int));
		out = (int *) malloc(m*k*sizeof(int));

		for(i=0; i<m*n; i++)
		{
			fscanf(fp, "%d", &V[i]);
		}

		// compute the execution time
		hipEvent_t start, stop;
		// create event
		hipEventCreate(&start);
		hipEventCreate(&stop);
		// record event
		hipEventRecord(start);

		// allocate space for devices copies
		hipMalloc((void **)&d_V, m*n*sizeof(int));
		hipMalloc((void **)&d_out, m*k*sizeof(int));
		hipMalloc((void **)&D, m*m*sizeof(int));

		// copy host values to devices copies
		hipMemcpy(d_V, V, m*n*sizeof(int), hipMemcpyHostToDevice);

		int gridDimX = (int)(ceil((float)m/TILE_WIDTH));
		int gridDimY = (int)(ceil((float)m/TILE_WIDTH));

		dim3 grid(gridDimX, gridDimY);
		dim3 block(TILE_WIDTH, TILE_WIDTH);

		// launch knn() kernel on GPU
		computeDist<<<grid, block>>>(m, n, d_V, D);
		hipDeviceSynchronize();

		int threadNum = (m<MAX_BLOCK_SIZE)? m: MAX_BLOCK_SIZE;
		int ptrNumInSMEM = (m<MAX_PTRNUM_IN_SMEM)? m: MAX_PTRNUM_IN_SMEM;
		knn<<<m, threadNum, 2*ptrNumInSMEM*sizeof(int)>>>(m, k, d_V, D, d_out);

		// copy result back to host
		hipMemcpy(out, d_out, m*k*sizeof(int), hipMemcpyDeviceToHost);

		// cleanup
		hipFree(d_V);
		hipFree(d_out);
		hipFree(D);

		// record event and synchronize
		hipEventRecord(stop);
		hipEventSynchronize(stop);
		float time;
		// get event elapsed time
		hipEventElapsedTime(&time, start, stop);

		showResult(m, k, out);
		if(m == 1024) {
			printf("SMALL:");
		} else if(m == 4096) {
			printf("MIDDLE:");
		} else if(m == 16384) {
			printf("LARGE:");
		}
		printf("%f\n", time);

		free(V);
		free(out);
	}
	fclose(fp);
	return 0;
}


	.text
	.file	"knn.hip"
	.globl	_Z26__device_stub__computeDistiiPiS_ # -- Begin function _Z26__device_stub__computeDistiiPiS_
	.type	_Z26__device_stub__computeDistiiPiS_,@function
_Z26__device_stub__computeDistiiPiS_:   # @_Z26__device_stub__computeDistiiPiS_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	12(%rsp), %rax
	movl	%edi, (%rax)
	leaq	8(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z11computeDistiiPiS_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z26__device_stub__computeDistiiPiS_, .Lfunc_end0-_Z26__device_stub__computeDistiiPiS_
	.cfi_endproc
                                        # -- End function
	.globl	_Z18__device_stub__knniiPiS_S_  # -- Begin function _Z18__device_stub__knniiPiS_S_
	.type	_Z18__device_stub__knniiPiS_S_,@function
_Z18__device_stub__knniiPiS_S_:         # @_Z18__device_stub__knniiPiS_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	4(%rsp), %rax
	movl	%edi, (%rax)
	movq	%rsp, %rdi
	movl	%esi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z3knniiPiS_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z18__device_stub__knniiPiS_S_, .Lfunc_end1-_Z18__device_stub__knniiPiS_S_
	.cfi_endproc
                                        # -- End function
	.globl	_Z10showResultiiPi              # -- Begin function _Z10showResultiiPi
	.type	_Z10showResultiiPi,@function
_Z10showResultiiPi:                     # @_Z10showResultiiPi
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$24, %rsp
	.cfi_def_cfa_offset 80
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%rdx, (%rsp)                    # 8-byte Spill
                                        # kill: def $esi killed $esi def $rsi
	testl	%edi, %edi
	jle	.LBB2_8
# %bb.1:                                # %.preheader.lr.ph
	leal	-1(%rsi), %r15d
	movl	%edi, %eax
	movq	%rax, 8(%rsp)                   # 8-byte Spill
	movl	%esi, %r13d
	xorl	%ebp, %ebp
	xorl	%ebx, %ebx
	movq	%rsi, 16(%rsp)                  # 8-byte Spill
.LBB2_2:                                # %.preheader
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB2_4 Depth 2
	testl	%esi, %esi
	jle	.LBB2_7
# %bb.3:                                # %.lr.ph
                                        #   in Loop: Header=BB2_2 Depth=1
	movl	%ebp, %eax
	movq	(%rsp), %rcx                    # 8-byte Reload
	leaq	(%rcx,%rax,4), %r12
	xorl	%r14d, %r14d
.LBB2_4:                                #   Parent Loop BB2_2 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movl	(%r12,%r14,4), %esi
	movl	$.L.str, %edi
	xorl	%eax, %eax
	callq	printf
	cmpq	%r14, %r15
	jne	.LBB2_6
# %bb.5:                                #   in Loop: Header=BB2_4 Depth=2
	movl	$10, %edi
	callq	putchar@PLT
.LBB2_6:                                #   in Loop: Header=BB2_4 Depth=2
	incq	%r14
	cmpq	%r14, %r13
	jne	.LBB2_4
.LBB2_7:                                # %._crit_edge
                                        #   in Loop: Header=BB2_2 Depth=1
	incq	%rbx
	movq	16(%rsp), %rsi                  # 8-byte Reload
	addl	%esi, %ebp
	cmpq	8(%rsp), %rbx                   # 8-byte Folded Reload
	jne	.LBB2_2
.LBB2_8:                                # %._crit_edge15
	addq	$24, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z10showResultiiPi, .Lfunc_end2-_Z10showResultiiPi
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0                          # -- Begin function main
.LCPI3_0:
	.long	0x3d000000                      # float 0.03125
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$72, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	cmpl	$2, %edi
	jne	.LBB3_1
# %bb.3:
	movq	8(%rsi), %rdi
	movl	$.L.str.3, %esi
	callq	fopen
	testq	%rax, %rax
	je	.LBB3_22
# %bb.4:                                # %.preheader
	movq	%rax, %rbx
	leaq	12(%rsp), %rdx
	leaq	20(%rsp), %rcx
	leaq	16(%rsp), %r8
	movl	$.L.str.5, %esi
	movq	%rax, %rdi
	xorl	%eax, %eax
	callq	__isoc23_fscanf
	cmpl	$-1, %eax
	je	.LBB3_21
# %bb.5:                                # %.lr.ph40.preheader
	movabsq	$4294967296, %rax               # imm = 0x100000000
	leaq	1(%rax), %rbp
.LBB3_6:                                # %.lr.ph40
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB3_8 Depth 2
	movslq	12(%rsp), %r14
	movslq	20(%rsp), %r13
	imulq	%r14, %r13
	movq	%r13, %rdi
	shlq	$2, %rdi
	callq	malloc
	movq	%rax, %r12
	movslq	16(%rsp), %rdi
	imulq	%r14, %rdi
	shlq	$2, %rdi
	callq	malloc
	movq	%rax, %r15
	testl	%r13d, %r13d
	jle	.LBB3_9
# %bb.7:                                # %.lr.ph.preheader
                                        #   in Loop: Header=BB3_6 Depth=1
	movq	%r12, %r14
	xorl	%r13d, %r13d
.LBB3_8:                                # %.lr.ph
                                        #   Parent Loop BB3_6 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movl	$.L.str.6, %esi
	movq	%rbx, %rdi
	movq	%r14, %rdx
	xorl	%eax, %eax
	callq	__isoc23_fscanf
	incq	%r13
	movslq	12(%rsp), %rax
	movslq	20(%rsp), %rcx
	imulq	%rax, %rcx
	addq	$4, %r14
	cmpq	%rcx, %r13
	jl	.LBB3_8
.LBB3_9:                                # %._crit_edge
                                        #   in Loop: Header=BB3_6 Depth=1
	leaq	64(%rsp), %rdi
	callq	hipEventCreate
	leaq	32(%rsp), %rdi
	callq	hipEventCreate
	movq	64(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movslq	12(%rsp), %rax
	movslq	20(%rsp), %rsi
	imulq	%rax, %rsi
	shlq	$2, %rsi
	leaq	24(%rsp), %rdi
	callq	hipMalloc
	movslq	12(%rsp), %rax
	movslq	16(%rsp), %rsi
	imulq	%rax, %rsi
	shlq	$2, %rsi
	leaq	48(%rsp), %rdi
	callq	hipMalloc
	movl	12(%rsp), %esi
	imull	%esi, %esi
	shlq	$2, %rsi
	leaq	40(%rsp), %rdi
	callq	hipMalloc
	movq	24(%rsp), %rdi
	movslq	12(%rsp), %rax
	movslq	20(%rsp), %rdx
	imulq	%rax, %rdx
	shlq	$2, %rdx
	movq	%r12, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	xorps	%xmm0, %xmm0
	cvtsi2ssl	12(%rsp), %xmm0
	mulss	.LCPI3_0(%rip), %xmm0
	callq	ceilf@PLT
	cvttss2si	%xmm0, %edi
	imulq	%rbp, %rdi
	movl	$1, %esi
	movabsq	$137438953504, %rdx             # imm = 0x2000000020
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB3_11
# %bb.10:                               #   in Loop: Header=BB3_6 Depth=1
	movl	12(%rsp), %edi
	movl	20(%rsp), %esi
	movq	24(%rsp), %rdx
	movq	40(%rsp), %rcx
	callq	_Z26__device_stub__computeDistiiPiS_
.LBB3_11:                               #   in Loop: Header=BB3_6 Depth=1
	callq	hipDeviceSynchronize
	movl	12(%rsp), %edi
	movl	$256, %eax                      # imm = 0x100
	cmpl	%eax, %edi
	movl	$256, %edx                      # imm = 0x100
	cmovll	%edi, %edx
	movl	$1024, %eax                     # imm = 0x400
	cmpl	%eax, %edi
	cmovll	%edi, %eax
	addl	%eax, %eax
	movslq	%eax, %r8
	shlq	$2, %r8
	movabsq	$4294967296, %rax               # imm = 0x100000000
	orq	%rax, %rdi
	orq	%rax, %rdx
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB3_13
# %bb.12:                               #   in Loop: Header=BB3_6 Depth=1
	movl	12(%rsp), %edi
	movl	16(%rsp), %esi
	movq	24(%rsp), %rdx
	movq	40(%rsp), %rcx
	movq	48(%rsp), %r8
	callq	_Z18__device_stub__knniiPiS_S_
.LBB3_13:                               #   in Loop: Header=BB3_6 Depth=1
	movq	48(%rsp), %rsi
	movslq	12(%rsp), %rax
	movslq	16(%rsp), %rdx
	imulq	%rax, %rdx
	shlq	$2, %rdx
	movq	%r15, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movq	24(%rsp), %rdi
	callq	hipFree
	movq	48(%rsp), %rdi
	callq	hipFree
	movq	40(%rsp), %rdi
	callq	hipFree
	movq	32(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	32(%rsp), %rdi
	callq	hipEventSynchronize
	movq	64(%rsp), %rsi
	movq	32(%rsp), %rdx
	leaq	60(%rsp), %rdi
	callq	hipEventElapsedTime
	movl	12(%rsp), %edi
	movl	16(%rsp), %esi
	movq	%r15, %rdx
	callq	_Z10showResultiiPi
	movl	12(%rsp), %eax
	cmpl	$1024, %eax                     # imm = 0x400
	je	.LBB3_14
# %bb.15:                               #   in Loop: Header=BB3_6 Depth=1
	cmpl	$16384, %eax                    # imm = 0x4000
	je	.LBB3_18
# %bb.16:                               #   in Loop: Header=BB3_6 Depth=1
	cmpl	$4096, %eax                     # imm = 0x1000
	jne	.LBB3_20
# %bb.17:                               #   in Loop: Header=BB3_6 Depth=1
	movl	$.L.str.8, %edi
	jmp	.LBB3_19
.LBB3_18:                               #   in Loop: Header=BB3_6 Depth=1
	movl	$.L.str.9, %edi
	jmp	.LBB3_19
.LBB3_14:                               #   in Loop: Header=BB3_6 Depth=1
	movl	$.L.str.7, %edi
.LBB3_19:                               # %.sink.split
                                        #   in Loop: Header=BB3_6 Depth=1
	xorl	%eax, %eax
	callq	printf
.LBB3_20:                               #   in Loop: Header=BB3_6 Depth=1
	cvtss2sd	60(%rsp), %xmm0
	movl	$.L.str.10, %edi
	movb	$1, %al
	callq	printf
	movq	%r12, %rdi
	callq	free
	movq	%r15, %rdi
	callq	free
	movl	$.L.str.5, %esi
	movq	%rbx, %rdi
	leaq	12(%rsp), %rdx
	leaq	20(%rsp), %rcx
	leaq	16(%rsp), %r8
	xorl	%eax, %eax
	callq	__isoc23_fscanf
	cmpl	$-1, %eax
	jne	.LBB3_6
.LBB3_21:                               # %._crit_edge41
	movq	%rbx, %rdi
	callq	fclose
	xorl	%eax, %eax
	addq	$72, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB3_1:
	.cfi_def_cfa_offset 128
	movl	$.Lstr.1, %edi
	jmp	.LBB3_2
.LBB3_22:
	movl	$.Lstr, %edi
.LBB3_2:
	callq	puts@PLT
	movl	$1, %edi
	callq	exit
.Lfunc_end3:
	.size	main, .Lfunc_end3-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB4_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB4_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z11computeDistiiPiS_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z3knniiPiS_S_, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end4:
	.size	__hip_module_ctor, .Lfunc_end4-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB5_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB5_2:
	retq
.Lfunc_end5:
	.size	__hip_module_dtor, .Lfunc_end5-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z11computeDistiiPiS_,@object   # @_Z11computeDistiiPiS_
	.section	.rodata,"a",@progbits
	.globl	_Z11computeDistiiPiS_
	.p2align	3, 0x0
_Z11computeDistiiPiS_:
	.quad	_Z26__device_stub__computeDistiiPiS_
	.size	_Z11computeDistiiPiS_, 8

	.type	_Z3knniiPiS_S_,@object          # @_Z3knniiPiS_S_
	.globl	_Z3knniiPiS_S_
	.p2align	3, 0x0
_Z3knniiPiS_S_:
	.quad	_Z18__device_stub__knniiPiS_S_
	.size	_Z3knniiPiS_S_, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"%d "
	.size	.L.str, 4

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"r"
	.size	.L.str.3, 2

	.type	.L.str.5,@object                # @.str.5
.L.str.5:
	.asciz	"%d %d %d"
	.size	.L.str.5, 9

	.type	.L.str.6,@object                # @.str.6
.L.str.6:
	.asciz	"%d"
	.size	.L.str.6, 3

	.type	.L.str.7,@object                # @.str.7
.L.str.7:
	.asciz	"SMALL:"
	.size	.L.str.7, 7

	.type	.L.str.8,@object                # @.str.8
.L.str.8:
	.asciz	"MIDDLE:"
	.size	.L.str.8, 8

	.type	.L.str.9,@object                # @.str.9
.L.str.9:
	.asciz	"LARGE:"
	.size	.L.str.9, 7

	.type	.L.str.10,@object               # @.str.10
.L.str.10:
	.asciz	"%f\n"
	.size	.L.str.10, 4

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z11computeDistiiPiS_"
	.size	.L__unnamed_1, 22

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z3knniiPiS_S_"
	.size	.L__unnamed_2, 15

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.type	.Lstr,@object                   # @str
	.section	.rodata.str1.1,"aMS",@progbits,1
.Lstr:
	.asciz	"Error open input file!"
	.size	.Lstr, 23

	.type	.Lstr.1,@object                 # @str.1
.Lstr.1:
	.asciz	"Usage: knn <inputfile>"
	.size	.Lstr.1, 23

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z26__device_stub__computeDistiiPiS_
	.addrsig_sym _Z18__device_stub__knniiPiS_S_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z11computeDistiiPiS_
	.addrsig_sym _Z3knniiPiS_S_
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z11computeDistiiPiS_   ; -- Begin function _Z11computeDistiiPiS_
	.globl	_Z11computeDistiiPiS_
	.p2align	8
	.type	_Z11computeDistiiPiS_,@function
_Z11computeDistiiPiS_:                  ; @_Z11computeDistiiPiS_
; %bb.0:
	v_bfe_u32 v1, v0, 10, 10
	s_mov_b32 s2, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e32 32, v1
	s_cbranch_execz .LBB0_15
; %bb.1:                                ; %.preheader63.lr.ph
	s_clause 0x2
	s_load_b64 s[8:9], s[0:1], 0x0
	s_load_b32 s2, s[0:1], 0x24
	s_load_b128 s[4:7], s[0:1], 0x8
	s_lshl_b32 s3, s15, 5
	v_dual_mov_b32 v19, v1 :: v_dual_and_b32 v0, 0x3ff, v0
	v_add_nc_u32_e32 v4, s3, v1
	s_lshl_b32 s12, s14, 5
	v_lshl_add_u32 v13, v1, 9, 0x4000
	s_delay_alu instid0(VALU_DEP_3)
	v_add_nc_u32_e32 v6, s12, v0
	v_dual_mov_b32 v14, 0 :: v_dual_lshlrev_b32 v15, 2, v0
	s_add_u32 s10, s0, 24
	s_addc_u32 s11, s1, 0
	v_cmp_gt_u32_e64 s0, 32, v0
	s_mov_b32 s13, 0
	v_add_nc_u32_e32 v16, v13, v15
	v_lshl_add_u32 v17, v1, 7, v15
	s_waitcnt lgkmcnt(0)
	v_cvt_f32_i32_e32 v2, s9
	s_lshr_b32 s14, s2, 16
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_mul_i32 s15, s9, s14
	s_lshl_b32 s16, s14, 9
	v_mul_f32_e32 v2, 0x3c000000, v2
	s_lshl_b32 s17, s14, 2
	s_lshl_b32 s18, s14, 7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ceil_f32_e32 v2, v2
	v_cvt_i32_f32_e32 v18, v2
	v_mad_u64_u32 v[2:3], null, s9, v4, v[0:1]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_lt_i32_e64 s1, 0, v18
	v_mad_u64_u32 v[4:5], null, s9, v6, v[1:2]
.LBB0_2:                                ; %.preheader63
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_4 Depth 2
                                        ;       Child Loop BB0_6 Depth 3
                                        ;         Child Loop BB0_7 Depth 4
                                        ;         Child Loop BB0_9 Depth 4
                                        ;         Child Loop BB0_11 Depth 4
	s_and_saveexec_b32 s19, s0
	s_cbranch_execz .LBB0_14
; %bb.3:                                ; %.lr.ph71
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_load_b32 s2, s[10:11], 0xc
	v_ashrrev_i32_e32 v3, 31, v2
	v_dual_mov_b32 v20, v15 :: v_dual_add_nc_u32 v7, s3, v19
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_mov_b32 v21, v17 :: v_dual_mov_b32 v22, v4
	v_lshlrev_b64 v[5:6], 2, v[2:3]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_mul_lo_u32 v24, v7, s8
	v_mov_b32_e32 v23, v0
	s_mov_b32 s23, 0
	v_add_co_u32 v5, vcc_lo, s4, v5
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
	s_waitcnt lgkmcnt(0)
	s_and_b32 s20, s2, 0xffff
	s_lshl_b32 s21, s20, 2
	s_mul_i32 s22, s9, s20
.LBB0_4:                                ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB0_6 Depth 3
                                        ;         Child Loop BB0_7 Depth 4
                                        ;         Child Loop BB0_9 Depth 4
                                        ;         Child Loop BB0_11 Depth 4
	v_lshlrev_b32_e32 v3, 2, v23
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshl_add_u32 v3, v19, 7, v3
	v_add_nc_u32_e32 v25, 0x8000, v3
	ds_store_b32 v3, v14 offset:32768
	s_waitcnt lgkmcnt(0)
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_cbranch_vccnz .LBB0_13
; %bb.5:                                ; %.preheader62.lr.ph
                                        ;   in Loop: Header=BB0_4 Depth=2
	v_mov_b32_e32 v7, v22
	v_dual_mov_b32 v10, v6 :: v_dual_mov_b32 v9, v5
	s_mov_b32 s24, 0
.LBB0_6:                                ; %.preheader62
                                        ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_4 Depth=2
                                        ; =>    This Loop Header: Depth=3
                                        ;         Child Loop BB0_7 Depth 4
                                        ;         Child Loop BB0_9 Depth 4
                                        ;         Child Loop BB0_11 Depth 4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_mov_b32 v3, v16 :: v_dual_mov_b32 v12, v10
	v_dual_mov_b32 v11, v9 :: v_dual_mov_b32 v8, v0
	s_mov_b32 s25, 0
.LBB0_7:                                ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_4 Depth=2
                                        ;       Parent Loop BB0_6 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	global_load_b32 v26, v[11:12], off
	v_add_nc_u32_e32 v8, s20, v8
	v_add_co_u32 v11, vcc_lo, v11, s21
	v_add_co_ci_u32_e32 v12, vcc_lo, 0, v12, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_u32_e64 s2, 0x7f, v8
	s_or_b32 s25, s2, s25
	s_waitcnt vmcnt(0)
	ds_store_b32 v3, v26
	v_add_nc_u32_e32 v3, s21, v3
	s_and_not1_b32 exec_lo, exec_lo, s25
	s_cbranch_execnz .LBB0_7
; %bb.8:                                ; %.lr.ph66
                                        ;   in Loop: Header=BB0_6 Depth=3
	s_or_b32 exec_lo, exec_lo, s25
	v_ashrrev_i32_e32 v8, 31, v7
	v_mov_b32_e32 v3, v21
	s_mov_b32 s25, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[11:12], 2, v[7:8]
	v_mov_b32_e32 v8, v1
	v_add_co_u32 v11, vcc_lo, s4, v11
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v12, vcc_lo, s5, v12, vcc_lo
.LBB0_9:                                ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_4 Depth=2
                                        ;       Parent Loop BB0_6 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	global_load_b32 v26, v[11:12], off
	v_add_nc_u32_e32 v8, s14, v8
	v_add_co_u32 v11, vcc_lo, v11, s17
	v_add_co_ci_u32_e32 v12, vcc_lo, 0, v12, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_u32_e64 s2, 0x7f, v8
	s_or_b32 s25, s2, s25
	s_waitcnt vmcnt(0)
	ds_store_b32 v3, v26
	v_add_nc_u32_e32 v3, s18, v3
	s_and_not1_b32 exec_lo, exec_lo, s25
	s_cbranch_execnz .LBB0_9
; %bb.10:                               ; %._crit_edge
                                        ;   in Loop: Header=BB0_6 Depth=3
	s_or_b32 exec_lo, exec_lo, s25
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_b32 v3, v25
	v_mov_b32_e32 v8, v20
	s_mov_b32 s2, 0
.LBB0_11:                               ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_4 Depth=2
                                        ;       Parent Loop BB0_6 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	s_delay_alu instid0(SALU_CYCLE_1)
	v_add_nc_u32_e32 v11, s2, v13
	s_add_i32 s2, s2, 4
	ds_load_b32 v12, v8
	ds_load_b32 v11, v11
	s_cmpk_eq_i32 s2, 0x200
	s_waitcnt lgkmcnt(0)
	v_sub_nc_u32_e32 v26, v11, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[11:12], null, v26, v26, v[3:4]
	v_dual_mov_b32 v3, v11 :: v_dual_add_nc_u32 v8, 0x80, v8
	s_cbranch_scc0 .LBB0_11
; %bb.12:                               ;   in Loop: Header=BB0_6 Depth=3
	s_add_i32 s24, s24, 1
	v_add_co_u32 v9, s2, 0x200, v9
	v_cmp_eq_u32_e32 vcc_lo, s24, v18
	v_add_co_ci_u32_e64 v10, s2, 0, v10, s2
	v_add_nc_u32_e32 v7, 0x80, v7
	ds_store_b32 v25, v11
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_vccz .LBB0_6
.LBB0_13:                               ; %._crit_edge69
                                        ;   in Loop: Header=BB0_4 Depth=2
	v_add3_u32 v7, v23, s12, v24
	ds_load_b32 v3, v25
	v_add_nc_u32_e32 v23, s20, v23
	v_add_nc_u32_e32 v22, s22, v22
	v_add_nc_u32_e32 v21, s21, v21
	v_ashrrev_i32_e32 v8, 31, v7
	v_add_nc_u32_e32 v20, s21, v20
	v_cmp_lt_u32_e32 vcc_lo, 31, v23
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[7:8], 2, v[7:8]
	s_or_b32 s23, vcc_lo, s23
	v_add_co_u32 v7, s2, s6, v7
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v8, s2, s7, v8, s2
	s_waitcnt lgkmcnt(0)
	global_store_b32 v[7:8], v3, off
	s_and_not1_b32 exec_lo, exec_lo, s23
	s_cbranch_execnz .LBB0_4
.LBB0_14:                               ; %Flow121
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s19
	v_add_nc_u32_e32 v19, s14, v19
	v_add_nc_u32_e32 v2, s15, v2
	v_add_nc_u32_e32 v16, s16, v16
	v_add_nc_u32_e32 v13, s16, v13
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_lt_u32_e32 vcc_lo, 31, v19
	s_or_b32 s13, vcc_lo, s13
	s_and_not1_b32 exec_lo, exec_lo, s13
	s_cbranch_execnz .LBB0_2
.LBB0_15:                               ; %._crit_edge74
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z11computeDistiiPiS_
		.amdhsa_group_segment_fixed_size 36864
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 27
		.amdhsa_next_free_sgpr 26
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z11computeDistiiPiS_, .Lfunc_end0-_Z11computeDistiiPiS_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 920
; NumSgprs: 28
; NumVgprs: 27
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 36864 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 3
; NumSGPRsForWavesPerEU: 28
; NumVGPRsForWavesPerEU: 27
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z3knniiPiS_S_          ; -- Begin function _Z3knniiPiS_S_
	.globl	_Z3knniiPiS_S_
	.p2align	8
	.type	_Z3knniiPiS_S_,@function
_Z3knniiPiS_S_:                         ; @_Z3knniiPiS_S_
; %bb.0:
	s_load_b64 s[8:9], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cmp_lt_i32 s9, 1
	s_cbranch_scc1 .LBB1_85
; %bb.1:                                ; %.lr.ph
	s_load_b128 s[4:7], s[0:1], 0x10
	s_mul_i32 s12, s15, s9
	s_delay_alu instid0(SALU_CYCLE_1)
	v_dual_mov_b32 v10, 0 :: v_dual_add_nc_u32 v1, s12, v0
	v_lshlrev_b32_e32 v5, 2, v0
	s_min_i32 s13, s8, 0x400
	s_cmp_gt_i32 s8, 0
	v_cmp_gt_u32_e64 s2, s8, v0
	v_ashrrev_i32_e32 v2, 31, v1
	s_cselect_b32 s16, -1, 0
	s_add_u32 s10, s0, 32
	s_addc_u32 s11, s1, 0
	v_dual_mov_b32 v9, 0x989680 :: v_dual_add_nc_u32 v6, 0, v5
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_cmpk_gt_u32 s8, 0x41
	v_cmp_gt_u32_e64 s3, 32, v0
	s_cselect_b32 s1, -1, 0
	s_lshl_b32 s17, s13, 2
	v_add_nc_u32_e32 v7, 0x80, v6
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v1, vcc_lo, s6, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
	v_add_nc_u32_e32 v8, s17, v6
	s_mov_b32 s14, 0
	s_mul_i32 s18, s15, s8
	s_add_i32 s19, s17, 0
	s_sub_i32 s15, 0, s15
.LBB1_2:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB1_4 Depth 2
                                        ;       Child Loop BB1_6 Depth 3
                                        ;       Child Loop BB1_14 Depth 3
                                        ;         Child Loop BB1_16 Depth 4
	v_mov_b32_e32 v3, 0x989680
	s_and_not1_b32 vcc_lo, exec_lo, s16
	s_cbranch_vccnz .LBB1_84
; %bb.3:                                ; %.preheader227.lr.ph.i
                                        ;   in Loop: Header=BB1_2 Depth=1
	s_load_b32 s20, s[10:11], 0xc
	v_cmp_gt_u32_e64 s0, s14, v0
	v_dual_mov_b32 v11, 0x989680 :: v_dual_mov_b32 v12, 0x989680
	s_mov_b32 s21, 0
	s_mov_b32 s23, s18
	s_waitcnt lgkmcnt(0)
	s_and_b32 s20, s20, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1)
	s_lshl_b32 s22, s20, 2
.LBB1_4:                                ; %.preheader227.i
                                        ;   Parent Loop BB1_2 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB1_6 Depth 3
                                        ;       Child Loop BB1_14 Depth 3
                                        ;         Child Loop BB1_16 Depth 4
	s_and_saveexec_b32 s24, s2
	s_cbranch_execz .LBB1_9
; %bb.5:                                ; %.lr.ph.i
                                        ;   in Loop: Header=BB1_4 Depth=2
	v_dual_mov_b32 v3, v6 :: v_dual_mov_b32 v4, v0
	s_add_i32 s25, s15, s21
	s_mov_b32 s26, 0
.LBB1_6:                                ;   Parent Loop BB1_2 Depth=1
                                        ;     Parent Loop BB1_4 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v13, s25, v4
	v_cmp_ne_u32_e32 vcc_lo, 0, v13
	v_mov_b32_e32 v13, 0x989680
	s_and_saveexec_b32 s27, vcc_lo
	s_cbranch_execz .LBB1_8
; %bb.7:                                ;   in Loop: Header=BB1_6 Depth=3
	v_add_nc_u32_e32 v13, s23, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v14, 31, v13
	v_lshlrev_b64 v[13:14], 2, v[13:14]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v13, vcc_lo, s4, v13
	v_add_co_ci_u32_e32 v14, vcc_lo, s5, v14, vcc_lo
	global_load_b32 v13, v[13:14], off
.LBB1_8:                                ;   in Loop: Header=BB1_6 Depth=3
	s_or_b32 exec_lo, exec_lo, s27
	v_add_nc_u32_e32 v14, s21, v4
	v_add_nc_u32_e32 v4, s20, v4
	v_add_nc_u32_e32 v15, s17, v3
	s_waitcnt vmcnt(0)
	ds_store_b32 v3, v13
	ds_store_b32 v15, v14
	v_cmp_le_i32_e32 vcc_lo, s13, v4
	v_add_nc_u32_e32 v3, s22, v3
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_or_b32 s26, vcc_lo, s26
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s26
	s_cbranch_execnz .LBB1_6
.LBB1_9:                                ; %Flow95
                                        ;   in Loop: Header=BB1_4 Depth=2
	s_or_b32 exec_lo, exec_lo, s24
	s_and_saveexec_b32 s24, s0
	s_cbranch_execz .LBB1_13
; %bb.10:                               ;   in Loop: Header=BB1_4 Depth=2
	global_load_b32 v3, v[1:2], off
	s_waitcnt vmcnt(0)
	v_subrev_nc_u32_e32 v3, s21, v3
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u32_e32 vcc_lo, s13, v3
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB1_12
; %bb.11:                               ;   in Loop: Header=BB1_4 Depth=2
	v_lshl_add_u32 v3, v3, 2, 0
	ds_store_b32 v3, v9
.LBB1_12:                               ;   in Loop: Header=BB1_4 Depth=2
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
.LBB1_13:                               ; %Flow93
                                        ;   in Loop: Header=BB1_4 Depth=2
	s_or_b32 exec_lo, exec_lo, s24
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_mov_b32 s24, s13
	s_barrier
	buffer_gl0_inv
	s_cbranch_vccnz .LBB1_26
.LBB1_14:                               ; %.preheader.i
                                        ;   Parent Loop BB1_2 Depth=1
                                        ;     Parent Loop BB1_4 Depth=2
                                        ; =>    This Loop Header: Depth=3
                                        ;         Child Loop BB1_16 Depth 4
	s_lshr_b32 s25, s24, 1
	s_and_saveexec_b32 s26, s2
	s_cbranch_execz .LBB1_25
; %bb.15:                               ; %.lr.ph230.i.preheader
                                        ;   in Loop: Header=BB1_14 Depth=3
	v_dual_mov_b32 v3, v5 :: v_dual_mov_b32 v4, v0
	s_lshl_b32 s28, s25, 2
	s_mov_b32 s29, 0
	s_add_i32 s27, s19, s28
	s_add_i32 s28, s28, 0
.LBB1_16:                               ; %.lr.ph230.i
                                        ;   Parent Loop BB1_2 Depth=1
                                        ;     Parent Loop BB1_4 Depth=2
                                        ;       Parent Loop BB1_14 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	s_mov_b32 s30, exec_lo
	v_cmpx_gt_i32_e64 s25, v4
	s_cbranch_execz .LBB1_24
; %bb.17:                               ;   in Loop: Header=BB1_16 Depth=4
	v_add_nc_u32_e32 v13, 0, v3
	v_add_nc_u32_e32 v14, s28, v3
	s_mov_b32 s31, exec_lo
	ds_load_b32 v15, v13
	ds_load_b32 v14, v14
	s_waitcnt lgkmcnt(0)
	v_cmpx_ne_u32_e64 v15, v14
	s_xor_b32 s31, exec_lo, s31
	s_cbranch_execz .LBB1_21
; %bb.18:                               ;   in Loop: Header=BB1_16 Depth=4
	s_mov_b32 s33, exec_lo
	v_cmpx_gt_i32_e64 v15, v14
	s_cbranch_execz .LBB1_20
; %bb.19:                               ;   in Loop: Header=BB1_16 Depth=4
	v_add_nc_u32_e32 v15, s27, v3
	ds_store_b32 v13, v14
	v_add_nc_u32_e32 v14, s19, v3
	ds_load_b32 v13, v15
	s_waitcnt lgkmcnt(0)
	ds_store_b32 v14, v13
.LBB1_20:                               ; %Flow85
                                        ;   in Loop: Header=BB1_16 Depth=4
	s_or_b32 exec_lo, exec_lo, s33
.LBB1_21:                               ; %Flow87
                                        ;   in Loop: Header=BB1_16 Depth=4
	s_and_not1_saveexec_b32 s31, s31
	s_cbranch_execz .LBB1_24
; %bb.22:                               ;   in Loop: Header=BB1_16 Depth=4
	v_add_nc_u32_e32 v13, s19, v3
	v_add_nc_u32_e32 v14, s27, v3
	ds_load_b32 v15, v13
	ds_load_b32 v14, v14
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_i32_e32 vcc_lo, v15, v14
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB1_24
; %bb.23:                               ;   in Loop: Header=BB1_16 Depth=4
	ds_store_b32 v13, v14
.LBB1_24:                               ;   in Loop: Header=BB1_16 Depth=4
	s_or_b32 exec_lo, exec_lo, s30
	v_add_nc_u32_e32 v4, s20, v4
	v_add_nc_u32_e32 v3, s22, v3
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmp_le_i32_e32 vcc_lo, s13, v4
	s_or_b32 s29, vcc_lo, s29
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s29
	s_cbranch_execnz .LBB1_16
.LBB1_25:                               ; %Flow90
                                        ;   in Loop: Header=BB1_14 Depth=3
	s_or_b32 exec_lo, exec_lo, s26
	s_cmpk_lt_u32 s24, 0x84
	s_mov_b32 s24, s25
	s_cbranch_scc0 .LBB1_14
.LBB1_26:                               ; %._crit_edge233.i
                                        ;   in Loop: Header=BB1_4 Depth=2
	s_and_saveexec_b32 s24, s3
	s_cbranch_execz .LBB1_75
; %bb.27:                               ;   in Loop: Header=BB1_4 Depth=2
	ds_load_b32 v13, v6
	ds_load_b32 v3, v7
	s_mov_b32 s25, 0
	s_mov_b32 s26, exec_lo
                                        ; implicit-def: $vgpr4
	s_waitcnt lgkmcnt(0)
	v_cmpx_ne_u32_e64 v13, v3
	s_xor_b32 s26, exec_lo, s26
	s_cbranch_execz .LBB1_31
; %bb.28:                               ;   in Loop: Header=BB1_4 Depth=2
	s_mov_b32 s27, exec_lo
                                        ; implicit-def: $vgpr4
	v_cmpx_gt_i32_e64 v13, v3
	s_xor_b32 s27, exec_lo, s27
	s_cbranch_execz .LBB1_30
; %bb.29:                               ;   in Loop: Header=BB1_4 Depth=2
	ds_store_b32 v6, v3
	ds_load_b32 v4, v8 offset:128
	s_mov_b32 s25, exec_lo
                                        ; implicit-def: $vgpr13
.LBB1_30:                               ; %Flow82
                                        ;   in Loop: Header=BB1_4 Depth=2
	s_or_b32 exec_lo, exec_lo, s27
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s25, s25, exec_lo
.LBB1_31:                               ; %Flow81
                                        ;   in Loop: Header=BB1_4 Depth=2
	s_and_not1_saveexec_b32 s26, s26
	s_cbranch_execz .LBB1_33
; %bb.32:                               ;   in Loop: Header=BB1_4 Depth=2
	s_waitcnt lgkmcnt(0)
	ds_load_2addr_b32 v[3:4], v8 offset1:32
	s_and_not1_b32 s25, s25, exec_lo
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_i32_e32 vcc_lo, v3, v4
	s_and_b32 s27, vcc_lo, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s25, s25, s27
.LBB1_33:                               ; %Flow83
                                        ;   in Loop: Header=BB1_4 Depth=2
	s_or_b32 exec_lo, exec_lo, s26
	s_and_saveexec_b32 s26, s25
	s_cbranch_execz .LBB1_35
; %bb.34:                               ; %.sink.split.i
                                        ;   in Loop: Header=BB1_4 Depth=2
	s_waitcnt lgkmcnt(0)
	ds_store_b32 v8, v4
	ds_load_b32 v13, v6
.LBB1_35:                               ;   in Loop: Header=BB1_4 Depth=2
	s_or_b32 exec_lo, exec_lo, s26
	ds_load_b32 v3, v6 offset:64
	s_mov_b32 s25, 0
	s_mov_b32 s26, exec_lo
                                        ; implicit-def: $vgpr4
	s_waitcnt lgkmcnt(0)
	v_cmpx_ne_u32_e64 v13, v3
	s_xor_b32 s26, exec_lo, s26
	s_cbranch_execz .LBB1_39
; %bb.36:                               ;   in Loop: Header=BB1_4 Depth=2
	s_mov_b32 s27, exec_lo
                                        ; implicit-def: $vgpr4
	v_cmpx_gt_i32_e64 v13, v3
	s_xor_b32 s27, exec_lo, s27
	s_cbranch_execz .LBB1_38
; %bb.37:                               ;   in Loop: Header=BB1_4 Depth=2
	ds_store_b32 v6, v3
	ds_load_b32 v4, v8 offset:64
	s_mov_b32 s25, exec_lo
                                        ; implicit-def: $vgpr13
.LBB1_38:                               ; %Flow79
                                        ;   in Loop: Header=BB1_4 Depth=2
	s_or_b32 exec_lo, exec_lo, s27
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s25, s25, exec_lo
.LBB1_39:                               ; %Flow78
                                        ;   in Loop: Header=BB1_4 Depth=2
	s_and_not1_saveexec_b32 s26, s26
	s_cbranch_execz .LBB1_41
; %bb.40:                               ;   in Loop: Header=BB1_4 Depth=2
	s_waitcnt lgkmcnt(0)
	ds_load_2addr_b32 v[3:4], v8 offset1:16
	s_and_not1_b32 s25, s25, exec_lo
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_i32_e32 vcc_lo, v3, v4
	s_and_b32 s27, vcc_lo, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s25, s25, s27
.LBB1_41:                               ; %Flow80
                                        ;   in Loop: Header=BB1_4 Depth=2
	s_or_b32 exec_lo, exec_lo, s26
	s_and_saveexec_b32 s26, s25
	s_cbranch_execz .LBB1_43
; %bb.42:                               ; %.sink.split239.i
                                        ;   in Loop: Header=BB1_4 Depth=2
	s_waitcnt lgkmcnt(0)
	ds_store_b32 v8, v4
	ds_load_b32 v13, v6
.LBB1_43:                               ;   in Loop: Header=BB1_4 Depth=2
	s_or_b32 exec_lo, exec_lo, s26
	ds_load_b32 v3, v6 offset:32
	s_mov_b32 s25, 0
	s_mov_b32 s26, exec_lo
                                        ; implicit-def: $vgpr4
	s_waitcnt lgkmcnt(0)
	v_cmpx_ne_u32_e64 v13, v3
	s_xor_b32 s26, exec_lo, s26
	s_cbranch_execz .LBB1_47
; %bb.44:                               ;   in Loop: Header=BB1_4 Depth=2
	s_mov_b32 s27, exec_lo
                                        ; implicit-def: $vgpr4
	v_cmpx_gt_i32_e64 v13, v3
	s_xor_b32 s27, exec_lo, s27
	s_cbranch_execz .LBB1_46
; %bb.45:                               ;   in Loop: Header=BB1_4 Depth=2
	ds_store_b32 v6, v3
	ds_load_b32 v4, v8 offset:32
	s_mov_b32 s25, exec_lo
                                        ; implicit-def: $vgpr13
.LBB1_46:                               ; %Flow76
                                        ;   in Loop: Header=BB1_4 Depth=2
	s_or_b32 exec_lo, exec_lo, s27
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s25, s25, exec_lo
.LBB1_47:                               ; %Flow75
                                        ;   in Loop: Header=BB1_4 Depth=2
	s_and_not1_saveexec_b32 s26, s26
	s_cbranch_execz .LBB1_49
; %bb.48:                               ;   in Loop: Header=BB1_4 Depth=2
	s_waitcnt lgkmcnt(0)
	ds_load_2addr_b32 v[3:4], v8 offset1:8
	s_and_not1_b32 s25, s25, exec_lo
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_i32_e32 vcc_lo, v3, v4
	s_and_b32 s27, vcc_lo, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s25, s25, s27
.LBB1_49:                               ; %Flow77
                                        ;   in Loop: Header=BB1_4 Depth=2
	s_or_b32 exec_lo, exec_lo, s26
	s_and_saveexec_b32 s26, s25
	s_cbranch_execz .LBB1_51
; %bb.50:                               ; %.sink.split241.i
                                        ;   in Loop: Header=BB1_4 Depth=2
	s_waitcnt lgkmcnt(0)
	ds_store_b32 v8, v4
	ds_load_b32 v13, v6
.LBB1_51:                               ;   in Loop: Header=BB1_4 Depth=2
	s_or_b32 exec_lo, exec_lo, s26
	ds_load_b32 v3, v6 offset:16
	s_mov_b32 s25, 0
	s_mov_b32 s26, exec_lo
                                        ; implicit-def: $vgpr4
	s_waitcnt lgkmcnt(0)
	v_cmpx_ne_u32_e64 v13, v3
	s_xor_b32 s26, exec_lo, s26
	s_cbranch_execz .LBB1_55
; %bb.52:                               ;   in Loop: Header=BB1_4 Depth=2
	s_mov_b32 s27, exec_lo
                                        ; implicit-def: $vgpr4
	v_cmpx_gt_i32_e64 v13, v3
	s_xor_b32 s27, exec_lo, s27
	s_cbranch_execz .LBB1_54
; %bb.53:                               ;   in Loop: Header=BB1_4 Depth=2
	ds_store_b32 v6, v3
	ds_load_b32 v4, v8 offset:16
	s_mov_b32 s25, exec_lo
                                        ; implicit-def: $vgpr13
.LBB1_54:                               ; %Flow73
                                        ;   in Loop: Header=BB1_4 Depth=2
	s_or_b32 exec_lo, exec_lo, s27
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s25, s25, exec_lo
.LBB1_55:                               ; %Flow72
                                        ;   in Loop: Header=BB1_4 Depth=2
	s_and_not1_saveexec_b32 s26, s26
	s_cbranch_execz .LBB1_57
; %bb.56:                               ;   in Loop: Header=BB1_4 Depth=2
	s_waitcnt lgkmcnt(0)
	ds_load_2addr_b32 v[3:4], v8 offset1:4
	s_and_not1_b32 s25, s25, exec_lo
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_i32_e32 vcc_lo, v3, v4
	s_and_b32 s27, vcc_lo, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s25, s25, s27
.LBB1_57:                               ; %Flow74
                                        ;   in Loop: Header=BB1_4 Depth=2
	s_or_b32 exec_lo, exec_lo, s26
	s_and_saveexec_b32 s26, s25
	s_cbranch_execz .LBB1_59
; %bb.58:                               ; %.sink.split243.i
                                        ;   in Loop: Header=BB1_4 Depth=2
	s_waitcnt lgkmcnt(0)
	ds_store_b32 v8, v4
	ds_load_b32 v13, v6
.LBB1_59:                               ;   in Loop: Header=BB1_4 Depth=2
	s_or_b32 exec_lo, exec_lo, s26
	ds_load_b32 v3, v6 offset:8
	s_mov_b32 s25, 0
	s_mov_b32 s26, exec_lo
                                        ; implicit-def: $vgpr4
	s_waitcnt lgkmcnt(0)
	v_cmpx_ne_u32_e64 v13, v3
	s_xor_b32 s26, exec_lo, s26
	s_cbranch_execz .LBB1_63
; %bb.60:                               ;   in Loop: Header=BB1_4 Depth=2
	s_mov_b32 s27, exec_lo
                                        ; implicit-def: $vgpr4
	v_cmpx_gt_i32_e64 v13, v3
	s_xor_b32 s27, exec_lo, s27
	s_cbranch_execz .LBB1_62
; %bb.61:                               ;   in Loop: Header=BB1_4 Depth=2
	ds_store_b32 v6, v3
	ds_load_b32 v4, v8 offset:8
	s_mov_b32 s25, exec_lo
                                        ; implicit-def: $vgpr13
.LBB1_62:                               ; %Flow70
                                        ;   in Loop: Header=BB1_4 Depth=2
	s_or_b32 exec_lo, exec_lo, s27
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s25, s25, exec_lo
.LBB1_63:                               ; %Flow69
                                        ;   in Loop: Header=BB1_4 Depth=2
	s_and_not1_saveexec_b32 s26, s26
	s_cbranch_execz .LBB1_65
; %bb.64:                               ;   in Loop: Header=BB1_4 Depth=2
	s_waitcnt lgkmcnt(0)
	ds_load_2addr_b32 v[3:4], v8 offset1:2
	s_and_not1_b32 s25, s25, exec_lo
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_i32_e32 vcc_lo, v3, v4
	s_and_b32 s27, vcc_lo, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s25, s25, s27
.LBB1_65:                               ; %Flow71
                                        ;   in Loop: Header=BB1_4 Depth=2
	s_or_b32 exec_lo, exec_lo, s26
	s_and_saveexec_b32 s26, s25
	s_cbranch_execz .LBB1_67
; %bb.66:                               ; %.sink.split245.i
                                        ;   in Loop: Header=BB1_4 Depth=2
	s_waitcnt lgkmcnt(0)
	ds_store_b32 v8, v4
	ds_load_b32 v13, v6
.LBB1_67:                               ;   in Loop: Header=BB1_4 Depth=2
	s_or_b32 exec_lo, exec_lo, s26
	ds_load_b32 v3, v6 offset:4
	s_mov_b32 s25, 0
	s_mov_b32 s26, exec_lo
                                        ; implicit-def: $vgpr4
	s_waitcnt lgkmcnt(0)
	v_cmpx_ne_u32_e64 v13, v3
	s_xor_b32 s26, exec_lo, s26
	s_cbranch_execz .LBB1_71
; %bb.68:                               ;   in Loop: Header=BB1_4 Depth=2
	s_mov_b32 s27, exec_lo
                                        ; implicit-def: $vgpr4
	v_cmpx_gt_i32_e64 v13, v3
	s_xor_b32 s27, exec_lo, s27
	s_cbranch_execz .LBB1_70
; %bb.69:                               ;   in Loop: Header=BB1_4 Depth=2
	ds_store_b32 v6, v3
	ds_load_b32 v4, v8 offset:4
	s_mov_b32 s25, exec_lo
.LBB1_70:                               ; %Flow66
                                        ;   in Loop: Header=BB1_4 Depth=2
	s_or_b32 exec_lo, exec_lo, s27
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s25, s25, exec_lo
.LBB1_71:                               ; %Flow65
                                        ;   in Loop: Header=BB1_4 Depth=2
	s_and_not1_saveexec_b32 s26, s26
	s_cbranch_execz .LBB1_73
; %bb.72:                               ;   in Loop: Header=BB1_4 Depth=2
	s_waitcnt lgkmcnt(0)
	ds_load_2addr_b32 v[3:4], v8 offset1:1
	s_and_not1_b32 s25, s25, exec_lo
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_i32_e32 vcc_lo, v3, v4
	s_and_b32 s27, vcc_lo, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s25, s25, s27
.LBB1_73:                               ; %Flow67
                                        ;   in Loop: Header=BB1_4 Depth=2
	s_or_b32 exec_lo, exec_lo, s26
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 exec_lo, exec_lo, s25
	s_cbranch_execz .LBB1_75
; %bb.74:                               ; %.sink.split247.i
                                        ;   in Loop: Header=BB1_4 Depth=2
	s_waitcnt lgkmcnt(0)
	ds_store_b32 v8, v4
.LBB1_75:                               ; %Flow84
                                        ;   in Loop: Header=BB1_4 Depth=2
	s_or_b32 exec_lo, exec_lo, s24
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_b32 v13, v10
	s_waitcnt lgkmcnt(0)
	v_cmp_ne_u32_e32 vcc_lo, v12, v13
	s_cbranch_vccz .LBB1_79
; %bb.76:                               ;   in Loop: Header=BB1_4 Depth=2
	v_cmp_le_i32_e32 vcc_lo, v12, v13
	v_dual_mov_b32 v3, v11 :: v_dual_mov_b32 v4, v12
	s_cbranch_vccnz .LBB1_78
; %bb.77:                               ;   in Loop: Header=BB1_4 Depth=2
	v_dual_mov_b32 v3, s19 :: v_dual_mov_b32 v4, v13
	ds_load_b32 v3, v3
.LBB1_78:                               ; %Flow
                                        ;   in Loop: Header=BB1_4 Depth=2
	s_mov_b32 s24, 0
	s_branch .LBB1_80
.LBB1_79:                               ;   in Loop: Header=BB1_4 Depth=2
	s_mov_b32 s24, -1
                                        ; implicit-def: $vgpr3
                                        ; implicit-def: $vgpr4
.LBB1_80:                               ; %Flow64
                                        ;   in Loop: Header=BB1_4 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s24
	s_cbranch_vccnz .LBB1_82
; %bb.81:                               ;   in Loop: Header=BB1_4 Depth=2
	s_waitcnt lgkmcnt(0)
	v_dual_mov_b32 v3, s19 :: v_dual_mov_b32 v4, v12
	ds_load_b32 v3, v3
	s_waitcnt lgkmcnt(0)
	v_min_i32_e32 v3, v11, v3
.LBB1_82:                               ;   in Loop: Header=BB1_4 Depth=2
	s_addk_i32 s21, 0x400
	s_addk_i32 s23, 0x400
	s_cmp_lt_i32 s21, s8
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc0 .LBB1_84
; %bb.83:                               ;   in Loop: Header=BB1_4 Depth=2
	v_dual_mov_b32 v11, v3 :: v_dual_mov_b32 v12, v4
	s_branch .LBB1_4
.LBB1_84:                               ; %_Z7findMiniiiPiS_.exit
                                        ;   in Loop: Header=BB1_2 Depth=1
	s_add_i32 s20, s14, s12
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_ashr_i32 s21, s20, 31
	s_lshl_b64 s[20:21], s[20:21], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s20, s6, s20
	s_addc_u32 s21, s7, s21
	s_add_i32 s14, s14, 1
	global_store_b32 v10, v3, s[20:21]
	s_cmp_lg_u32 s14, s9
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB1_2
.LBB1_85:                               ; %._crit_edge
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z3knniiPiS_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 16
		.amdhsa_next_free_sgpr 34
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z3knniiPiS_S_, .Lfunc_end1-_Z3knniiPiS_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 2060
; NumSgprs: 36
; NumVgprs: 16
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 4
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 36
; NumVGPRsForWavesPerEU: 16
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     by_value
      - .offset:         4
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 36864
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z11computeDistiiPiS_
    .private_segment_fixed_size: 0
    .sgpr_count:     28
    .sgpr_spill_count: 0
    .symbol:         _Z11computeDistiiPiS_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     27
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     by_value
      - .offset:         4
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         152
        .size:           4
        .value_kind:     hidden_dynamic_lds_size
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z3knniiPiS_S_
    .private_segment_fixed_size: 0
    .sgpr_count:     36
    .sgpr_spill_count: 0
    .symbol:         _Z3knniiPiS_S_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     16
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
