#include "includes.h"
__global__ void FF_calc ( float *q_S_ref_dS, float *WK, float *vdW, int num_q, int num_ele, float c1, float r_m, float *FF_table, float rho) {

__shared__ float q_pt, q_WK, C1, expC1;
__shared__ float FF_pt[7]; // num_ele + 1, the last one for water.
__shared__ float vdW_s[7];
__shared__ float WK_s[66];
__shared__ float C1_PI_43_rho;
if (blockIdx.x >= num_q) return; // out of q range
for (int ii = blockIdx.x; ii < num_q; ii += gridDim.x) {
q_pt = q_S_ref_dS[ii];
q_WK = q_pt / 4.0 / PI;
// FoXS C1 term
expC1 = -powf(4.0 * PI / 3.0, 1.5) * q_WK * q_WK * r_m * r_m * (c1 * c1 - 1.0) / 4.0 / PI;
C1 = powf(c1,3) * exp(expC1);
C1_PI_43_rho = C1 * PI * 4.0 / 3.0 * rho;
for (int jj = threadIdx.x; jj < 11 * num_ele; jj += blockDim.x) {
WK_s[jj] = WK[jj];
}
__syncthreads();

// Calculate Form factor for this block (or q vector)
for (int jj = threadIdx.x; jj < num_ele + 1; jj += blockDim.x) {
vdW_s[jj] = vdW[jj];
if (jj == num_ele) {
// water
FF_pt[jj] = WK_s[3*11+5];
FF_pt[jj] += 2.0 * WK_s[5];
FF_pt[jj] -= C1_PI_43_rho * powf(vdW_s[jj],3.0) * exp(-PI * vdW_s[jj] * vdW_s[jj] * q_WK * q_WK);
for (int kk = 0; kk < 5; kk ++) {
FF_pt[jj] += WK_s[3*11+kk] * exp(-WK_s[3*11+kk+6] * q_WK * q_WK);
FF_pt[jj] += WK_s[kk] * exp(-WK_s[kk+6] * q_WK * q_WK);
FF_pt[jj] += WK_s[kk] * exp(-WK_s[kk+6] * q_WK * q_WK);
}
} else {
FF_pt[jj] = WK_s[jj*11+5];
// The part is for excluded volume
FF_pt[jj] -= C1_PI_43_rho * powf(vdW_s[jj],3.0) * exp(-PI * vdW_s[jj] * vdW_s[jj] * q_WK * q_WK);
for (int kk = 0; kk < 5; kk++) {
FF_pt[jj] += WK_s[jj*11+kk] * exp(-WK_s[jj*11+kk+6] * q_WK * q_WK);
}
}
FF_table[ii*(num_ele+1)+jj] = FF_pt[jj];
}
}
}
	.file	"tmpxft_002116d1_00000000-6_FF_calc.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2010:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2010:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z37__device_stub__Z7FF_calcPfS_S_iiffS_fPfS_S_iiffS_f
	.type	_Z37__device_stub__Z7FF_calcPfS_S_iiffS_fPfS_S_iiffS_f, @function
_Z37__device_stub__Z7FF_calcPfS_S_iiffS_fPfS_S_iiffS_f:
.LFB2032:
	.cfi_startproc
	endbr64
	subq	$216, %rsp
	.cfi_def_cfa_offset 224
	movq	%rdi, 56(%rsp)
	leaq	80(%rsp), %rdi
	movq	%rsi, 48(%rsp)
	leaq	92(%rsp), %rsi
	movq	%rdx, 40(%rsp)
	leaq	64(%rsp), %rdx
	movl	%ecx, 36(%rsp)
	leaq	72(%rsp), %rcx
	movl	%r8d, 32(%rsp)
	movq	%r9, 16(%rsp)
	movss	%xmm0, 28(%rsp)
	movss	%xmm1, 24(%rsp)
	movss	%xmm2, 12(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 200(%rsp)
	xorl	%eax, %eax
	leaq	56(%rsp), %rax
	movl	$1, 88(%rsp)
	movq	%rax, 128(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	36(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	28(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 192(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 80(%rsp)
	movq	%rax, 92(%rsp)
	movl	$1, 100(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	72(%rsp)
	.cfi_def_cfa_offset 232
	leaq	_Z7FF_calcPfS_S_iiffS_f(%rip), %rdi
	pushq	72(%rsp)
	.cfi_def_cfa_offset 240
	movq	108(%rsp), %rcx
	movl	116(%rsp), %r8d
	movq	96(%rsp), %rsi
	movl	104(%rsp), %edx
	leaq	144(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 232
	popq	%rdx
	.cfi_def_cfa_offset 224
.L2:
	movq	200(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$216, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2032:
	.size	_Z37__device_stub__Z7FF_calcPfS_S_iiffS_fPfS_S_iiffS_f, .-_Z37__device_stub__Z7FF_calcPfS_S_iiffS_fPfS_S_iiffS_f
	.globl	_Z7FF_calcPfS_S_iiffS_f
	.type	_Z7FF_calcPfS_S_iiffS_f, @function
_Z7FF_calcPfS_S_iiffS_f:
.LFB2033:
	.cfi_startproc
	endbr64
	jmp	_Z37__device_stub__Z7FF_calcPfS_S_iiffS_fPfS_S_iiffS_f
	.cfi_endproc
.LFE2033:
	.size	_Z7FF_calcPfS_S_iiffS_f, .-_Z7FF_calcPfS_S_iiffS_f
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z7FF_calcPfS_S_iiffS_f"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2035:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z7FF_calcPfS_S_iiffS_f(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2035:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void FF_calc ( float *q_S_ref_dS, float *WK, float *vdW, int num_q, int num_ele, float c1, float r_m, float *FF_table, float rho) {

__shared__ float q_pt, q_WK, C1, expC1;
__shared__ float FF_pt[7]; // num_ele + 1, the last one for water.
__shared__ float vdW_s[7];
__shared__ float WK_s[66];
__shared__ float C1_PI_43_rho;
if (blockIdx.x >= num_q) return; // out of q range
for (int ii = blockIdx.x; ii < num_q; ii += gridDim.x) {
q_pt = q_S_ref_dS[ii];
q_WK = q_pt / 4.0 / PI;
// FoXS C1 term
expC1 = -powf(4.0 * PI / 3.0, 1.5) * q_WK * q_WK * r_m * r_m * (c1 * c1 - 1.0) / 4.0 / PI;
C1 = powf(c1,3) * exp(expC1);
C1_PI_43_rho = C1 * PI * 4.0 / 3.0 * rho;
for (int jj = threadIdx.x; jj < 11 * num_ele; jj += blockDim.x) {
WK_s[jj] = WK[jj];
}
__syncthreads();

// Calculate Form factor for this block (or q vector)
for (int jj = threadIdx.x; jj < num_ele + 1; jj += blockDim.x) {
vdW_s[jj] = vdW[jj];
if (jj == num_ele) {
// water
FF_pt[jj] = WK_s[3*11+5];
FF_pt[jj] += 2.0 * WK_s[5];
FF_pt[jj] -= C1_PI_43_rho * powf(vdW_s[jj],3.0) * exp(-PI * vdW_s[jj] * vdW_s[jj] * q_WK * q_WK);
for (int kk = 0; kk < 5; kk ++) {
FF_pt[jj] += WK_s[3*11+kk] * exp(-WK_s[3*11+kk+6] * q_WK * q_WK);
FF_pt[jj] += WK_s[kk] * exp(-WK_s[kk+6] * q_WK * q_WK);
FF_pt[jj] += WK_s[kk] * exp(-WK_s[kk+6] * q_WK * q_WK);
}
} else {
FF_pt[jj] = WK_s[jj*11+5];
// The part is for excluded volume
FF_pt[jj] -= C1_PI_43_rho * powf(vdW_s[jj],3.0) * exp(-PI * vdW_s[jj] * vdW_s[jj] * q_WK * q_WK);
for (int kk = 0; kk < 5; kk++) {
FF_pt[jj] += WK_s[jj*11+kk] * exp(-WK_s[jj*11+kk+6] * q_WK * q_WK);
}
}
FF_table[ii*(num_ele+1)+jj] = FF_pt[jj];
}
}
}
	.text
	.file	"FF_calc.hip"
	.globl	_Z22__device_stub__FF_calcPfS_S_iiffS_f # -- Begin function _Z22__device_stub__FF_calcPfS_S_iiffS_f
	.type	_Z22__device_stub__FF_calcPfS_S_iiffS_f,@function
_Z22__device_stub__FF_calcPfS_S_iiffS_f: # @_Z22__device_stub__FF_calcPfS_S_iiffS_f
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$192, %rsp
	.cfi_def_cfa_offset 240
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	72(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	64(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	56(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	28(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	24(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	20(%rsp), %r8
	movss	%xmm0, (%r8)
	leaq	16(%rsp), %r10
	movss	%xmm1, (%r10)
	leaq	48(%rsp), %r11
	movq	%r9, (%r11)
	leaq	12(%rsp), %r9
	movss	%xmm2, (%r9)
	leaq	112(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	movq	%r10, 48(%rbx)
	movq	%r11, 56(%rbx)
	movq	%r9, 64(%rbx)
	leaq	96(%rsp), %r14
	leaq	80(%rsp), %r15
	leaq	40(%rsp), %r12
	leaq	32(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7FF_calcPfS_S_iiffS_f, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$208, %rsp
	.cfi_adjust_cfa_offset -208
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z22__device_stub__FF_calcPfS_S_iiffS_f, .Lfunc_end0-_Z22__device_stub__FF_calcPfS_S_iiffS_f
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z7FF_calcPfS_S_iiffS_f, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z7FF_calcPfS_S_iiffS_f,@object # @_Z7FF_calcPfS_S_iiffS_f
	.section	.rodata,"a",@progbits
	.globl	_Z7FF_calcPfS_S_iiffS_f
	.p2align	3, 0x0
_Z7FF_calcPfS_S_iiffS_f:
	.quad	_Z22__device_stub__FF_calcPfS_S_iiffS_f
	.size	_Z7FF_calcPfS_S_iiffS_f, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z7FF_calcPfS_S_iiffS_f"
	.size	.L__unnamed_1, 24

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z22__device_stub__FF_calcPfS_S_iiffS_f
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z7FF_calcPfS_S_iiffS_f
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z7FF_calcPfS_S_iiffS_f ; -- Begin function _Z7FF_calcPfS_S_iiffS_f
	.globl	_Z7FF_calcPfS_S_iiffS_f
	.p2align	8
	.type	_Z7FF_calcPfS_S_iiffS_f,@function
_Z7FF_calcPfS_S_iiffS_f:                ; @_Z7FF_calcPfS_S_iiffS_f
; %bb.0:
	s_load_b128 s[4:7], s[0:1], 0x18
	s_waitcnt lgkmcnt(0)
	s_cmp_ge_u32 s15, s4
	s_cselect_b32 s2, -1, 0
	s_cmp_ge_i32 s15, s4
	s_cselect_b32 s3, -1, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s2, s2, s3
	s_and_b32 vcc_lo, exec_lo, s2
	s_cbranch_vccnz .LBB0_16
; %bb.1:                                ; %.lr.ph84
	v_frexp_mant_f32_e64 v1, |s6|
	s_mov_b32 s33, 0x3e76c4e1
	v_cmp_eq_f32_e64 s2, s6, 1.0
	s_mov_b32 s12, s15
	s_clause 0x1
	s_load_b128 s[8:11], s[0:1], 0x0
	s_load_b64 s[14:15], s[0:1], 0x10
	v_cmp_gt_f32_e32 vcc_lo, 0x3f2aaaab, v1
	s_clause 0x2
	s_load_b64 s[18:19], s[0:1], 0x28
	s_load_b32 s30, s[0:1], 0x30
	s_load_b32 s53, s[0:1], 0x38
	v_cmp_eq_f32_e64 s46, s6, 0
	v_cmp_class_f32_e64 s13, s6, 0x204
	s_mul_i32 s52, s5, 11
	v_cndmask_b32_e64 v2, 0, 1, vcc_lo
	v_mul_u32_u24_e32 v15, 44, v0
	v_cndmask_b32_e64 v11, 0x7f800000, 0, s46
	s_mov_b32 s16, 11
	s_mov_b32 s20, 0x54442eea
	v_ldexp_f32 v1, v1, v2
	s_mov_b32 s22, 0x652b82fe
	s_mov_b32 s24, 0xfefa39ef
	s_mov_b32 s26, 0x3b39803f
	s_mov_b32 s28, 0xfca7ab0c
	v_add_f32_e32 v4, -1.0, v1
	v_add_f32_e32 v2, 1.0, v1
	s_mov_b32 s34, 0x623fde64
	s_mov_b32 s36, 0x7c89e6b0
	s_mov_b32 s40, 0x1852b7b0
	s_mov_b32 s42, 0x11122322
	v_rcp_f32_e32 v3, v2
	s_mov_b32 s44, 0x555502a1
	s_mov_b32 s17, 0x3fe00000
	s_mov_b32 s21, 0xc00921fb
	s_mov_b32 s23, 0x3ff71547
	s_mov_b32 s25, 0xbfe62e42
	s_mov_b32 s27, 0xbc7abc9e
	s_mov_b32 s29, 0x3e928af3
	s_mov_b32 s35, 0x3ec71dee
	s_mov_b32 s37, 0x3efa0199
	s_waitcnt_depctr 0xfff
	v_dual_mul_f32 v5, v4, v3 :: v_dual_add_f32 v6, -1.0, v2
	s_mov_b32 s41, 0x3f56c16c
	s_mov_b32 s43, 0x3f811111
	s_mov_b32 s45, 0x3fa55555
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v7, v2, v5
	v_sub_f32_e32 v1, v1, v6
	s_mov_b32 s51, 0x400921fb
	v_mov_b32_e32 v17, 0
	v_fma_f32 v2, v5, v2, -v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v2, v5, v1
	v_add_f32_e32 v1, v7, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v6, v4, v1 :: v_dual_sub_f32 v7, v1, v7
	v_sub_f32_e32 v2, v7, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v4, v4, v6
	v_sub_f32_e32 v1, v4, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v1, v2, v1
	v_add_f32_e32 v1, v6, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v1, v3, v1
	v_add_f32_e32 v2, v5, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v4, v2, v2
	v_sub_f32_e32 v3, v2, v5
	v_sub_f32_e32 v1, v1, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v3, v2, v2, -v4
	v_add_f32_e32 v5, v1, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v3, v2, v5
	v_add_f32_e32 v5, v4, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmaak_f32 v6, s33, v5, 0x3e91f4c4
	v_sub_f32_e32 v4, v5, v4
	v_dual_fmaak_f32 v6, v5, v6, 0x3ecccdef :: v_dual_sub_f32 v3, v3, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v7, v5, v6
	v_fma_f32 v4, v5, v6, -v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v4, v3, v6 :: v_dual_mul_f32 v9, v2, v5
	v_add_f32_e32 v6, v7, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v10, v5, v2, -v9
	v_dual_sub_f32 v7, v6, v7 :: v_dual_fmac_f32 v10, v5, v1
	v_add_f32_e32 v8, 0x3f2aaaaa, v6
	v_ldexp_f32 v1, v1, 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v4, v4, v7
	v_fmac_f32_e32 v10, v3, v2
	v_ldexp_f32 v2, v2, 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f32_e32 v4, 0x31739010, v4
	v_add_f32_e32 v7, 0xbf2aaaaa, v8
	v_sub_f32_e32 v6, v6, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v4, v4, v6
	v_add_f32_e32 v3, v8, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v5, v9, v10 :: v_dual_sub_f32 v6, v8, v3
	v_mul_f32_e32 v7, v5, v3
	v_sub_f32_e32 v8, v5, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v4, v4, v6
	v_fma_f32 v6, v5, v3, -v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v8, v10, v8
	v_fmac_f32_e32 v6, v5, v4
	v_frexp_exp_i32_f32_e32 v4, s6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v6, v8, v3
	v_subrev_co_ci_u32_e32 v3, vcc_lo, 0, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v4, v7, v6
	v_cvt_f32_i32_e32 v3, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v7, v4, v7
	v_add_f32_e32 v5, v2, v4
	v_sub_f32_e32 v6, v6, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v8, 0x3f317218, v3 :: v_dual_add_f32 v1, v1, v6
	v_fma_f32 v7, 0x3f317218, v3, -v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v7, 0xb102e308, v3 :: v_dual_sub_f32 v2, v5, v2
	v_sub_f32_e32 v2, v4, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v1, v1, v2
	v_dual_add_f32 v3, v5, v1 :: v_dual_add_f32 v2, v8, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v5, v3, v5 :: v_dual_add_f32 v4, v2, v3
	v_dual_sub_f32 v1, v1, v5 :: v_dual_sub_f32 v6, v4, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v3, v3, v6 :: v_dual_sub_f32 v8, v2, v8
	v_sub_f32_e32 v9, v4, v6
	v_sub_f32_e32 v7, v7, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v5, v7, v1
	v_sub_f32_e32 v2, v2, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v2, v3, v2 :: v_dual_sub_f32 v3, v5, v7
	v_sub_f32_e32 v1, v1, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f32_e32 v2, v5, v2
	v_sub_f32_e32 v5, v5, v3
	v_dual_sub_f32 v3, v7, v5 :: v_dual_add_f32 v6, v4, v2
	v_cndmask_b32_e64 v5, 0x40400000, 1.0, s2
	v_cmp_ge_i32_e64 s2, s5, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v1, v1, v3 :: v_dual_sub_f32 v4, v6, v4
	v_sub_f32_e32 v2, v2, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v1, v1, v2
	v_add_f32_e32 v2, v6, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v3, v2, v6
	v_mul_f32_e32 v6, v5, v2
	v_sub_f32_e32 v1, v1, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_fma_f32 v2, v5, v2, -v6
	v_cmp_class_f32_e64 vcc_lo, v6, 0x204
	v_mul_f32_e64 v3, s6, s6
	v_fmac_f32_e32 v2, v5, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_f64_f32_e32 v[3:4], v3
	v_add_f32_e32 v1, v6, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v7, v1, v6, vcc_lo
	v_cmp_eq_f32_e32 vcc_lo, 0x42b17218, v7
	v_cndmask_b32_e64 v8, 0, 0x37000000, vcc_lo
	v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v7|
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v9, v7, v8
	v_dual_mul_f32 v10, 0x3fb8aa3b, v9 :: v_dual_sub_f32 v1, v1, v6
	v_cmp_nlt_f32_e64 s3, 0x42b17218, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_fma_f32 v12, 0x3fb8aa3b, v9, -v10
	v_rndne_f32_e32 v13, v10
	v_sub_f32_e32 v1, v2, v1
	v_trunc_f32_e32 v2, v5
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v12, 0x32a5705f, v9
	v_sub_f32_e32 v10, v10, v13
	s_delay_alu instid0(VALU_DEP_4)
	v_cndmask_b32_e32 v1, 0, v1, vcc_lo
	v_cvt_i32_f32_e32 v6, v13
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v9
	v_lshlrev_b32_e32 v14, 2, v0
	v_add_f32_e32 v10, v10, v12
	v_add_f64 v[3:4], v[3:4], -1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_exp_f32_e32 v10, v10
	s_waitcnt_depctr 0xfff
	v_ldexp_f32 v6, v10, v6
	v_mul_f32_e32 v10, 0.5, v5
	v_cndmask_b32_e32 v6, 0, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_2)
	v_trunc_f32_e32 v7, v10
	v_cmp_eq_f32_e32 vcc_lo, v2, v5
	v_add_f32_e32 v5, v8, v1
	s_waitcnt lgkmcnt(0)
	v_cvt_f64_f32_e32 v[1:2], s30
	v_cndmask_b32_e64 v6, 0x7f800000, v6, s3
	v_cmp_neq_f32_e64 s3, v7, v10
	s_mov_b32 s30, 0x6a5dcb37
	s_mov_b32 s31, 0x3e5ade15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v5, v6, v5, v6
	s_and_b32 s38, vcc_lo, s3
	v_cmp_eq_f32_e64 s3, 0x7f800000, v6
	v_cndmask_b32_e64 v7, 1.0, s6, s38
	s_delay_alu instid0(VALU_DEP_2)
	v_cndmask_b32_e64 v5, v5, v6, s3
	v_cndmask_b32_e64 v6, 0, s6, s38
	v_cmp_gt_i32_e64 s3, s52, v0
	s_mov_b32 s38, 0x14761f6e
	s_mov_b32 s39, 0x3f2a01a0
	v_bfi_b32 v5, 0x7fffffff, v5, v7
	v_bfi_b32 v6, 0x7fffffff, v11, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v7, 0x7fc00000, v5, vcc_lo
	v_cmp_lt_f32_e64 vcc_lo, s6, 0
	v_cndmask_b32_e32 v5, v5, v7, vcc_lo
	s_or_b32 vcc_lo, s46, s13
	s_mov_b32 s46, 0x55555511
	s_add_u32 s48, s0, 56
	s_mov_b32 s47, 0x3fc55555
	v_cndmask_b32_e32 v5, v5, v6, vcc_lo
	v_cmp_o_f32_e64 vcc_lo, s6, s6
	s_addc_u32 s49, s1, 0
	s_add_i32 s6, s5, 1
	s_delay_alu instid0(VALU_DEP_2)
	v_cndmask_b32_e32 v16, 0x7fc00000, v5, vcc_lo
.LBB0_2:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_4 Depth 2
                                        ;     Child Loop BB0_7 Depth 2
                                        ;       Child Loop BB0_9 Depth 3
                                        ;       Child Loop BB0_13 Depth 3
	s_ashr_i32 s13, s12, 31
	s_mov_b32 s50, s20
	s_lshl_b64 s[0:1], s[12:13], 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	s_add_u32 s0, s8, s0
	s_addc_u32 s1, s9, s1
	global_load_b32 v5, v17, s[0:1]
	s_waitcnt vmcnt(0)
	v_cvt_f64_f32_e32 v[5:6], v5
	v_ldexp_f64 v[5:6], v[5:6], -2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f64 v[7:8], null, s[50:51], s[50:51], v[5:6]
	v_div_scale_f64 v[18:19], vcc_lo, v[5:6], s[50:51], v[5:6]
	v_rcp_f64_e32 v[9:10], v[7:8]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[11:12], -v[7:8], v[9:10], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[9:10], v[9:10], v[11:12], v[9:10]
	v_fma_f64 v[11:12], -v[7:8], v[9:10], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[9:10], v[9:10], v[11:12], v[9:10]
	v_mul_f64 v[11:12], v[18:19], v[9:10]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[7:8], -v[7:8], v[11:12], v[18:19]
	v_div_fmas_f64 v[7:8], v[7:8], v[9:10], v[11:12]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f64 v[5:6], v[7:8], s[50:51], v[5:6]
	v_cvt_f32_f64_e32 v6, v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v5, 0xc1092b04, v6
	v_mul_f32_e32 v5, v5, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v5, s7, v5
	v_mul_f32_e32 v5, s7, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f64_f32_e32 v[7:8], v5
	v_mul_f64 v[7:8], v[3:4], v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ldexp_f64 v[7:8], v[7:8], -2
	v_div_scale_f64 v[9:10], null, s[50:51], s[50:51], v[7:8]
	v_div_scale_f64 v[20:21], vcc_lo, v[7:8], s[50:51], v[7:8]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[11:12], v[9:10]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[18:19], -v[9:10], v[11:12], 1.0
	v_fma_f64 v[11:12], v[11:12], v[18:19], v[11:12]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[18:19], -v[9:10], v[11:12], 1.0
	v_fma_f64 v[11:12], v[11:12], v[18:19], v[11:12]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[18:19], v[20:21], v[11:12]
	v_fma_f64 v[9:10], -v[9:10], v[18:19], v[20:21]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f64 v[9:10], v[9:10], v[11:12], v[18:19]
	v_div_fixup_f64 v[7:8], v[9:10], s[50:51], v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f32_f64_e32 v5, v[7:8]
	v_mul_f32_e32 v7, 0x3fb8aa3b, v5
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v8, 0x3fb8aa3b, v5, -v7
	v_rndne_f32_e32 v9, v7
	v_fmac_f32_e32 v8, 0x32a5705f, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v7, v7, v9
	v_add_f32_e32 v7, v7, v8
	v_cvt_i32_f32_e32 v8, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_exp_f32_e32 v7, v7
	s_waitcnt_depctr 0xfff
	v_ldexp_f32 v7, v7, v8
	v_cndmask_b32_e32 v7, 0, v7, vcc_lo
	v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v5, 0x7f800000, v7, vcc_lo
	v_mul_f32_e32 v5, v16, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f64_f32_e32 v[7:8], v5
	v_mul_f64 v[7:8], v[7:8], s[50:51]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[7:8], v[7:8], 4.0
	v_div_scale_f64 v[9:10], null, 0x40080000, 0x40080000, v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[11:12], v[9:10]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[18:19], -v[9:10], v[11:12], 1.0
	v_fma_f64 v[11:12], v[11:12], v[18:19], v[11:12]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[18:19], -v[9:10], v[11:12], 1.0
	v_fma_f64 v[11:12], v[11:12], v[18:19], v[11:12]
	v_div_scale_f64 v[18:19], vcc_lo, v[7:8], 0x40080000, v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[20:21], v[18:19], v[11:12]
	v_fma_f64 v[9:10], -v[9:10], v[20:21], v[18:19]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f64 v[9:10], v[9:10], v[11:12], v[20:21]
	v_div_fixup_f64 v[7:8], v[9:10], 0x40080000, v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[7:8], v[7:8], v[1:2]
	v_cvt_f32_f64_e32 v5, v[7:8]
	ds_store_b64 v17, v[5:6] offset:264
	s_and_saveexec_b32 s0, s3
	s_cbranch_execz .LBB0_5
; %bb.3:                                ; %.lr.ph
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_load_b32 s1, s[48:49], 0xc
	v_mov_b32_e32 v7, v14
	v_mov_b32_e32 v5, v0
	s_mov_b32 s50, 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s1, s1, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1)
	s_lshl_b32 s13, s1, 2
.LBB0_4:                                ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_ashrrev_i32_e32 v6, 31, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[8:9], 2, v[5:6]
	v_add_nc_u32_e32 v5, s1, v5
	v_add_co_u32 v8, vcc_lo, s10, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v9, vcc_lo, s11, v9, vcc_lo
	v_cmp_le_i32_e32 vcc_lo, s52, v5
	global_load_b32 v6, v[8:9], off
	s_or_b32 s50, vcc_lo, s50
	s_waitcnt vmcnt(0)
	ds_store_b32 v7, v6
	v_add_nc_u32_e32 v7, s13, v7
	s_and_not1_b32 exec_lo, exec_lo, s50
	s_cbranch_execnz .LBB0_4
.LBB0_5:                                ; %Flow139
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	s_waitcnt lgkmcnt(0)
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s13, s2
	s_cbranch_execz .LBB0_15
; %bb.6:                                ; %.lr.ph81
                                        ;   in Loop: Header=BB0_2 Depth=1
	ds_load_2addr_b32 v[5:6], v17 offset0:5 offset1:38
	s_load_b32 s0, s[48:49], 0xc
	v_dual_mov_b32 v18, v15 :: v_dual_mov_b32 v11, v0
	s_mul_i32 s54, s12, s6
	s_mov_b32 s56, 0
	s_waitcnt lgkmcnt(0)
	v_cvt_f64_f32_e32 v[7:8], v5
	v_cvt_f64_f32_e32 v[5:6], v6
	s_and_b32 s50, s0, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_mul_i32 s55, s50, 44
	v_fma_f64 v[5:6], v[7:8], 2.0, v[5:6]
	s_delay_alu instid0(VALU_DEP_1)
	v_cvt_f32_f64_e32 v9, v[5:6]
	ds_load_b64 v[5:6], v17 offset:264
	s_waitcnt lgkmcnt(0)
	v_cvt_f64_f32_e32 v[7:8], v6
	v_cvt_f64_f32_e32 v[9:10], v9
.LBB0_7:                                ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB0_9 Depth 3
                                        ;       Child Loop BB0_13 Depth 3
	v_ashrrev_i32_e32 v12, 31, v11
                                        ; implicit-def: $vgpr22
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[12:13], 2, v[11:12]
	v_add_co_u32 v12, vcc_lo, s14, v12
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v13, vcc_lo, s15, v13, vcc_lo
	global_load_b32 v19, v[12:13], off
	s_waitcnt vmcnt(0)
	v_cvt_f64_f32_e32 v[12:13], v19
	v_frexp_mant_f32_e64 v21, |v19|
	v_frexp_exp_i32_f32_e32 v20, v19
	v_cmp_class_f32_e64 s57, v19, 0x204
	v_cmpx_ne_u32_e64 s5, v11
	s_xor_b32 s58, exec_lo, s0
	s_cbranch_execz .LBB0_11
; %bb.8:                                ;   in Loop: Header=BB0_7 Depth=2
	v_mul_f64 v[22:23], v[12:13], s[20:21]
	v_cmp_gt_f32_e32 vcc_lo, 0x3f2aaaab, v21
	v_cndmask_b32_e64 v28, 0, 1, vcc_lo
	v_subrev_co_ci_u32_e32 v20, vcc_lo, 0, v20, vcc_lo
	v_cmp_eq_f32_e32 vcc_lo, 1.0, v19
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ldexp_f32 v21, v21, v28
	v_add_f32_e32 v28, 1.0, v21
	v_add_f32_e32 v30, -1.0, v21
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v32, -1.0, v28
	v_sub_f32_e32 v21, v21, v32
	v_rcp_f32_e32 v29, v28
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v31, v30, v29
	v_mul_f64 v[12:13], v[22:23], v[12:13]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v33, v28, v31
	v_fma_f32 v28, v31, v28, -v33
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v28, v31, v21
	v_add_f32_e32 v21, v33, v28
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v33, v21, v33
	v_sub_f32_e32 v28, v33, v28
	v_sub_f32_e32 v32, v30, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v30, v30, v32
	v_mul_f64 v[12:13], v[12:13], v[7:8]
	v_sub_f32_e32 v21, v30, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v21, v28, v21
	v_add_f32_e32 v21, v32, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v21, v29, v21
	v_add_f32_e32 v28, v31, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v29, v28, v31
	v_dual_mul_f32 v30, v28, v28 :: v_dual_sub_f32 v21, v21, v29
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v29, v28, v28, -v30
	v_add_f32_e32 v31, v21, v21
	v_mul_f64 v[12:13], v[12:13], v[7:8]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v29, v28, v31
	v_add_f32_e32 v31, v30, v29
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmaak_f32 v32, s33, v31, 0x3e91f4c4
	v_sub_f32_e32 v30, v31, v30
	v_dual_fmaak_f32 v32, v31, v32, 0x3ecccdef :: v_dual_sub_f32 v29, v29, v30
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v33, v31, v32
	v_fma_f32 v30, v31, v32, -v33
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v30, v29, v32
	v_mul_f64 v[22:23], v[12:13], s[22:23]
	v_add_f32_e32 v32, v33, v30
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v33, v32, v33 :: v_dual_add_f32 v34, 0x3f2aaaaa, v32
	v_dual_sub_f32 v30, v30, v33 :: v_dual_add_f32 v33, 0xbf2aaaaa, v34
	v_mul_f32_e32 v35, v28, v31
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v32, v32, v33
	v_fma_f32 v36, v31, v28, -v35
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v36, v31, v21
	v_fmac_f32_e32 v36, v29, v28
	v_ldexp_f32 v28, v28, 1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_add_f32 v31, v35, v36 :: v_dual_add_f32 v30, 0x31739010, v30
	v_rndne_f64_e32 v[22:23], v[22:23]
	v_add_f32_e32 v30, v30, v32
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v29, v34, v30
	v_mul_f32_e32 v33, v31, v29
	v_sub_f32_e32 v32, v34, v29
	v_sub_f32_e32 v34, v31, v35
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f32_e32 v30, v30, v32
	v_fma_f32 v32, v31, v29, -v33
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v34, v36, v34
	v_fmac_f32_e32 v32, v31, v30
	v_cvt_f32_i32_e32 v30, v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v32, v34, v29
	v_ldexp_f32 v34, v21, 1
	v_add_f32_e32 v29, v33, v32
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_f32_e32 v31, v28, v29
	v_fma_f64 v[24:25], v[22:23], s[24:25], v[12:13]
	v_dual_sub_f32 v20, v29, v33 :: v_dual_mul_f32 v33, 0x3f317218, v30
	v_sub_f32_e32 v32, v32, v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v35, 0x3f317218, v30, -v33
	v_dual_sub_f32 v28, v31, v28 :: v_dual_fmac_f32 v35, 0xb102e308, v30
	v_fma_f64 v[24:25], v[22:23], s[26:27], v[24:25]
	v_cvt_i32_f64_e32 v22, v[22:23]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[26:27], v[24:25], s[30:31], s[28:29]
	v_fma_f64 v[26:27], v[24:25], v[26:27], s[34:35]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[26:27], v[24:25], v[26:27], s[36:37]
	v_fma_f64 v[26:27], v[24:25], v[26:27], s[38:39]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[26:27], v[24:25], v[26:27], s[40:41]
	v_fma_f64 v[26:27], v[24:25], v[26:27], s[42:43]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[26:27], v[24:25], v[26:27], s[44:45]
	v_fma_f64 v[20:21], v[24:25], v[26:27], s[46:47]
	v_sub_f32_e32 v26, v29, v28
	v_add_f32_e32 v27, v34, v32
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v26, v27, v26 :: v_dual_add_f32 v27, v33, v35
	v_add_f32_e32 v28, v31, v26
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v31, v28, v31
	v_add_f32_e32 v29, v27, v28
	v_sub_f32_e32 v32, v27, v33
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v30, v29, v27
	v_dual_sub_f32 v32, v35, v32 :: v_dual_sub_f32 v33, v29, v30
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v28, v28, v30 :: v_dual_sub_f32 v27, v27, v33
	v_add_f32_e32 v27, v28, v27
	v_sub_f32_e32 v26, v26, v31
	v_fma_f64 v[20:21], v[24:25], v[20:21], s[16:17]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v30, v32, v26
	v_add_f32_e32 v27, v30, v27
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v31, v29, v27 :: v_dual_sub_f32 v28, v30, v32
	v_dual_sub_f32 v29, v31, v29 :: v_dual_sub_f32 v30, v30, v28
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v26, v26, v28 :: v_dual_sub_f32 v27, v27, v29
	v_sub_f32_e32 v28, v32, v30
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f32_e32 v26, v26, v28
	v_cndmask_b32_e64 v28, 0x40400000, 1.0, vcc_lo
	v_add_f32_e32 v26, v26, v27
	v_fma_f64 v[20:21], v[24:25], v[20:21], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v27, v31, v26
	v_sub_f32_e32 v29, v27, v31
	v_mul_f32_e32 v30, v28, v27
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v26, v26, v29
	v_fma_f32 v27, v28, v27, -v30
	v_cmp_class_f32_e64 vcc_lo, v30, 0x204
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v27, v28, v26
	v_add_f32_e32 v26, v30, v27
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v29, v26, v30, vcc_lo
	v_cmp_eq_f32_e32 vcc_lo, 0x42b17218, v29
	v_cndmask_b32_e64 v31, 0, 0x37000000, vcc_lo
	v_fma_f64 v[20:21], v[24:25], v[20:21], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v32, v29, v31
	v_mul_f32_e32 v33, 0x3fb8aa3b, v32
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v23, 0x3fb8aa3b, v32, -v33
	v_rndne_f32_e32 v24, v33
	v_fmac_f32_e32 v23, 0x32a5705f, v32
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v25, v33, v24
	v_cvt_i32_f32_e32 v24, v24
	v_add_f32_e32 v23, v25, v23
	v_sub_f32_e32 v25, v26, v30
	v_trunc_f32_e32 v26, v28
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_exp_f32_e32 v23, v23
	v_sub_f32_e32 v25, v27, v25
	v_ldexp_f64 v[20:21], v[20:21], v22
	s_waitcnt_depctr 0xfff
	v_ldexp_f32 v23, v23, v24
	v_mul_f32_e32 v24, 0.5, v28
	v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v29|
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_trunc_f32_e32 v27, v24
	v_cndmask_b32_e32 v25, 0, v25, vcc_lo
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v32
	v_cmp_neq_f32_e64 s0, v27, v24
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_add_f32_e32 v25, v31, v25
	v_cndmask_b32_e32 v23, 0, v23, vcc_lo
	v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v32
	v_cndmask_b32_e32 v23, 0x7f800000, v23, vcc_lo
	v_cmp_eq_f32_e32 vcc_lo, v26, v28
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_fma_f32 v22, v23, v25, v23
	v_cmp_eq_f32_e64 s1, 0x7f800000, v23
	s_and_b32 s0, vcc_lo, s0
	v_cndmask_b32_e64 v24, 1.0, v19, s0
	v_cndmask_b32_e64 v25, 0, v19, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v22, v22, v23, s1
	v_cmp_eq_f32_e64 s1, 0, v19
	v_mul_lo_u32 v23, v11, 44
	v_cmp_ngt_f64_e64 s0, 0xc090cc00, v[12:13]
	v_bfi_b32 v22, 0x7fffffff, v22, v24
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v24, 0x7f800000, 0, s1
	v_cndmask_b32_e32 v26, 0x7fc00000, v22, vcc_lo
	v_cmp_gt_f32_e32 vcc_lo, 0, v19
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_bfi_b32 v24, 0x7fffffff, v24, v25
	ds_load_b32 v23, v23 offset:20
	v_cndmask_b32_e32 v22, v22, v26, vcc_lo
	s_or_b32 vcc_lo, s1, s57
	v_cndmask_b32_e32 v22, v22, v24, vcc_lo
	v_cmp_o_f32_e32 vcc_lo, v19, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v19, 0x7fc00000, v22, vcc_lo
	v_cmp_nlt_f64_e32 vcc_lo, 0x40900000, v[12:13]
	v_mul_f32_e32 v19, v19, v5
	s_waitcnt lgkmcnt(0)
	v_cvt_f64_f32_e32 v[12:13], v23
	v_cndmask_b32_e32 v24, 0x7ff00000, v21, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_cvt_f64_f32_e32 v[21:22], v19
	s_and_b32 vcc_lo, s0, vcc_lo
	v_cndmask_b32_e32 v23, 0, v20, vcc_lo
	v_cndmask_b32_e64 v24, 0, v24, s0
	s_mov_b32 s0, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[12:13], -v[23:24], v[21:22], v[12:13]
	v_cvt_f32_f64_e32 v22, v[12:13]
.LBB0_9:                                ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_7 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	v_add_nc_u32_e32 v12, s0, v18
	s_add_i32 s0, s0, 4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	s_cmp_lg_u32 s0, 20
	ds_load_2addr_b32 v[12:13], v12 offset1:6
	s_waitcnt lgkmcnt(0)
	v_mul_f32_e64 v13, v6, -v13
	v_mul_f32_e32 v13, v6, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v19, 0x3fb8aa3b, v13
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v13
	v_fma_f32 v20, 0x3fb8aa3b, v13, -v19
	v_rndne_f32_e32 v21, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v20, 0x32a5705f, v13
	v_sub_f32_e32 v19, v19, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f32_e32 v19, v19, v20
	v_cvt_i32_f32_e32 v20, v21
	v_exp_f32_e32 v19, v19
	s_waitcnt_depctr 0xfff
	v_ldexp_f32 v19, v19, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v19, 0, v19, vcc_lo
	v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v13
	v_cndmask_b32_e32 v13, 0x7f800000, v19, vcc_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v22, v12, v13
	s_cbranch_scc1 .LBB0_9
; %bb.10:                               ; %Flow
                                        ;   in Loop: Header=BB0_7 Depth=2
                                        ; implicit-def: $vgpr19
                                        ; implicit-def: $vgpr21
                                        ; implicit-def: $vgpr20
                                        ; implicit-def: $vgpr12_vgpr13
.LBB0_11:                               ; %Flow134
                                        ;   in Loop: Header=BB0_7 Depth=2
	s_and_not1_saveexec_b32 s58, s58
	s_cbranch_execz .LBB0_14
; %bb.12:                               ;   in Loop: Header=BB0_7 Depth=2
	v_mul_f64 v[22:23], v[12:13], s[20:21]
	v_cmp_gt_f32_e32 vcc_lo, 0x3f2aaaab, v21
	v_cndmask_b32_e64 v28, 0, 1, vcc_lo
	v_subrev_co_ci_u32_e32 v20, vcc_lo, 0, v20, vcc_lo
	v_cmp_eq_f32_e32 vcc_lo, 1.0, v19
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ldexp_f32 v21, v21, v28
	v_add_f32_e32 v28, 1.0, v21
	v_add_f32_e32 v30, -1.0, v21
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v32, -1.0, v28
	v_sub_f32_e32 v21, v21, v32
	v_rcp_f32_e32 v29, v28
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v31, v30, v29
	v_mul_f64 v[12:13], v[22:23], v[12:13]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v33, v28, v31
	v_fma_f32 v28, v31, v28, -v33
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v28, v31, v21
	v_add_f32_e32 v21, v33, v28
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v33, v21, v33
	v_sub_f32_e32 v28, v33, v28
	v_sub_f32_e32 v32, v30, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v30, v30, v32
	v_mul_f64 v[12:13], v[12:13], v[7:8]
	v_sub_f32_e32 v21, v30, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v21, v28, v21
	v_add_f32_e32 v21, v32, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v21, v29, v21
	v_add_f32_e32 v28, v31, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v29, v28, v31
	v_dual_mul_f32 v30, v28, v28 :: v_dual_sub_f32 v21, v21, v29
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v29, v28, v28, -v30
	v_add_f32_e32 v31, v21, v21
	v_mul_f64 v[12:13], v[12:13], v[7:8]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v29, v28, v31
	v_add_f32_e32 v31, v30, v29
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmaak_f32 v32, s33, v31, 0x3e91f4c4
	v_sub_f32_e32 v30, v31, v30
	v_dual_fmaak_f32 v32, v31, v32, 0x3ecccdef :: v_dual_sub_f32 v29, v29, v30
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v33, v31, v32
	v_fma_f32 v30, v31, v32, -v33
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v30, v29, v32
	v_mul_f64 v[22:23], v[12:13], s[22:23]
	v_add_f32_e32 v32, v33, v30
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v33, v32, v33 :: v_dual_add_f32 v34, 0x3f2aaaaa, v32
	v_dual_sub_f32 v30, v30, v33 :: v_dual_add_f32 v33, 0xbf2aaaaa, v34
	v_mul_f32_e32 v35, v28, v31
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v32, v32, v33
	v_fma_f32 v36, v31, v28, -v35
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v36, v31, v21
	v_fmac_f32_e32 v36, v29, v28
	v_ldexp_f32 v28, v28, 1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_add_f32 v31, v35, v36 :: v_dual_add_f32 v30, 0x31739010, v30
	v_rndne_f64_e32 v[22:23], v[22:23]
	v_add_f32_e32 v30, v30, v32
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v29, v34, v30
	v_mul_f32_e32 v33, v31, v29
	v_sub_f32_e32 v32, v34, v29
	v_sub_f32_e32 v34, v31, v35
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f32_e32 v30, v30, v32
	v_fma_f32 v32, v31, v29, -v33
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v34, v36, v34
	v_fmac_f32_e32 v32, v31, v30
	v_cvt_f32_i32_e32 v30, v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v32, v34, v29
	v_ldexp_f32 v34, v21, 1
	v_add_f32_e32 v29, v33, v32
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_f32_e32 v31, v28, v29
	v_fma_f64 v[24:25], v[22:23], s[24:25], v[12:13]
	v_dual_sub_f32 v20, v29, v33 :: v_dual_mul_f32 v33, 0x3f317218, v30
	v_sub_f32_e32 v32, v32, v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v35, 0x3f317218, v30, -v33
	v_dual_sub_f32 v28, v31, v28 :: v_dual_fmac_f32 v35, 0xb102e308, v30
	v_fma_f64 v[24:25], v[22:23], s[26:27], v[24:25]
	v_cvt_i32_f64_e32 v22, v[22:23]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[26:27], v[24:25], s[30:31], s[28:29]
	v_fma_f64 v[26:27], v[24:25], v[26:27], s[34:35]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[26:27], v[24:25], v[26:27], s[36:37]
	v_fma_f64 v[26:27], v[24:25], v[26:27], s[38:39]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[26:27], v[24:25], v[26:27], s[40:41]
	v_fma_f64 v[26:27], v[24:25], v[26:27], s[42:43]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[26:27], v[24:25], v[26:27], s[44:45]
	v_fma_f64 v[20:21], v[24:25], v[26:27], s[46:47]
	v_sub_f32_e32 v26, v29, v28
	v_add_f32_e32 v27, v34, v32
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v26, v27, v26 :: v_dual_add_f32 v27, v33, v35
	v_add_f32_e32 v28, v31, v26
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v31, v28, v31
	v_add_f32_e32 v29, v27, v28
	v_sub_f32_e32 v32, v27, v33
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v30, v29, v27
	v_dual_sub_f32 v32, v35, v32 :: v_dual_sub_f32 v33, v29, v30
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v28, v28, v30 :: v_dual_sub_f32 v27, v27, v33
	v_add_f32_e32 v27, v28, v27
	v_sub_f32_e32 v26, v26, v31
	v_fma_f64 v[20:21], v[24:25], v[20:21], s[16:17]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v30, v32, v26
	v_add_f32_e32 v27, v30, v27
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v31, v29, v27 :: v_dual_sub_f32 v28, v30, v32
	v_dual_sub_f32 v29, v31, v29 :: v_dual_sub_f32 v30, v30, v28
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v26, v26, v28 :: v_dual_sub_f32 v27, v27, v29
	v_sub_f32_e32 v28, v32, v30
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f32_e32 v26, v26, v28
	v_cndmask_b32_e64 v28, 0x40400000, 1.0, vcc_lo
	v_add_f32_e32 v26, v26, v27
	v_fma_f64 v[20:21], v[24:25], v[20:21], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v27, v31, v26
	v_sub_f32_e32 v29, v27, v31
	v_mul_f32_e32 v30, v28, v27
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v26, v26, v29
	v_fma_f32 v27, v28, v27, -v30
	v_cmp_class_f32_e64 vcc_lo, v30, 0x204
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v27, v28, v26
	v_add_f32_e32 v26, v30, v27
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v29, v26, v30, vcc_lo
	v_cmp_eq_f32_e32 vcc_lo, 0x42b17218, v29
	v_cndmask_b32_e64 v31, 0, 0x37000000, vcc_lo
	v_fma_f64 v[20:21], v[24:25], v[20:21], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v32, v29, v31
	v_mul_f32_e32 v33, 0x3fb8aa3b, v32
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v23, 0x3fb8aa3b, v32, -v33
	v_rndne_f32_e32 v24, v33
	v_fmac_f32_e32 v23, 0x32a5705f, v32
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v25, v33, v24
	v_cvt_i32_f32_e32 v24, v24
	v_add_f32_e32 v23, v25, v23
	v_sub_f32_e32 v25, v26, v30
	v_trunc_f32_e32 v26, v28
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_exp_f32_e32 v23, v23
	v_sub_f32_e32 v25, v27, v25
	v_ldexp_f64 v[20:21], v[20:21], v22
	s_waitcnt_depctr 0xfff
	v_ldexp_f32 v23, v23, v24
	v_mul_f32_e32 v24, 0.5, v28
	v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v29|
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_trunc_f32_e32 v27, v24
	v_cndmask_b32_e32 v25, 0, v25, vcc_lo
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v32
	v_cmp_neq_f32_e64 s0, v27, v24
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_add_f32_e32 v25, v31, v25
	v_cndmask_b32_e32 v23, 0, v23, vcc_lo
	v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v32
	v_cndmask_b32_e32 v23, 0x7f800000, v23, vcc_lo
	v_cmp_eq_f32_e32 vcc_lo, v26, v28
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_fma_f32 v22, v23, v25, v23
	v_cmp_eq_f32_e64 s1, 0x7f800000, v23
	s_and_b32 s0, vcc_lo, s0
	v_cndmask_b32_e64 v24, 1.0, v19, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v22, v22, v23, s1
	v_cmp_eq_f32_e64 s1, 0, v19
	v_bfi_b32 v22, 0x7fffffff, v22, v24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v23, 0x7f800000, 0, s1
	v_cndmask_b32_e64 v24, 0, v19, s0
	v_cmp_ngt_f64_e64 s0, 0xc090cc00, v[12:13]
	v_cndmask_b32_e32 v25, 0x7fc00000, v22, vcc_lo
	v_cmp_gt_f32_e32 vcc_lo, 0, v19
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_bfi_b32 v23, 0x7fffffff, v23, v24
	v_cndmask_b32_e32 v22, v22, v25, vcc_lo
	s_or_b32 vcc_lo, s1, s57
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v22, v22, v23, vcc_lo
	v_cmp_o_f32_e32 vcc_lo, v19, v19
	v_cndmask_b32_e32 v19, 0x7fc00000, v22, vcc_lo
	v_cmp_nlt_f64_e32 vcc_lo, 0x40900000, v[12:13]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v12, v19, v5
	v_cvt_f64_f32_e32 v[12:13], v12
	v_cndmask_b32_e32 v21, 0x7ff00000, v21, vcc_lo
	s_and_b32 vcc_lo, s0, vcc_lo
	v_cndmask_b32_e32 v20, 0, v20, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v21, 0, v21, s0
	s_mov_b32 s0, 0
	v_fma_f64 v[12:13], -v[20:21], v[12:13], v[9:10]
	s_delay_alu instid0(VALU_DEP_1)
	v_cvt_f32_f64_e32 v22, v[12:13]
.LBB0_13:                               ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_7 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	v_mov_b32_e32 v19, s0
	s_add_i32 s0, s0, 4
	ds_load_2addr_b32 v[12:13], v19 offset0:33 offset1:39
	ds_load_2addr_b32 v[19:20], v19 offset1:6
	s_cmp_eq_u32 s0, 20
	s_waitcnt lgkmcnt(1)
	v_mul_f32_e64 v13, v6, -v13
	s_waitcnt lgkmcnt(0)
	v_mul_f32_e64 v20, v6, -v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v20, v6, v20
	v_mul_f32_e32 v23, 0x3fb8aa3b, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_fma_f32 v26, 0x3fb8aa3b, v20, -v23
	v_mul_f32_e32 v13, v6, v13
	v_rndne_f32_e32 v27, v23
	v_fmac_f32_e32 v26, 0x32a5705f, v20
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_mul_f32_e32 v21, 0x3fb8aa3b, v13
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v13
	v_sub_f32_e32 v23, v23, v27
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v24, 0x3fb8aa3b, v13, -v21
	v_rndne_f32_e32 v25, v21
	v_dual_add_f32 v23, v23, v26 :: v_dual_fmac_f32 v24, 0x32a5705f, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v21, v21, v25
	v_exp_f32_e32 v23, v23
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_add_f32_e32 v21, v21, v24
	v_cvt_i32_f32_e32 v24, v25
	v_cvt_i32_f32_e32 v25, v27
	v_exp_f32_e32 v21, v21
	s_waitcnt_depctr 0xfff
	v_ldexp_f32 v23, v23, v25
	v_ldexp_f32 v21, v21, v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cndmask_b32_e32 v21, 0, v21, vcc_lo
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v20
	v_cndmask_b32_e32 v23, 0, v23, vcc_lo
	v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v13
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v13, 0x7f800000, v21, vcc_lo
	v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v20
	v_fmac_f32_e32 v22, v12, v13
	v_cndmask_b32_e32 v20, 0x7f800000, v23, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v22, v19, v20
	v_fmac_f32_e32 v22, v19, v20
	s_cbranch_scc0 .LBB0_13
.LBB0_14:                               ; %Flow135
                                        ;   in Loop: Header=BB0_7 Depth=2
	s_or_b32 exec_lo, exec_lo, s58
	v_add_nc_u32_e32 v12, s54, v11
	v_add_nc_u32_e32 v11, s50, v11
	v_add_nc_u32_e32 v18, s55, v18
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_ashrrev_i32_e32 v13, 31, v12
	v_cmp_lt_i32_e32 vcc_lo, s5, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[12:13], 2, v[12:13]
	s_or_b32 s56, vcc_lo, s56
	v_add_co_u32 v12, s0, s18, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v13, s0, s19, v13, s0
	global_store_b32 v[12:13], v22, off
	s_and_not1_b32 exec_lo, exec_lo, s56
	s_cbranch_execnz .LBB0_7
.LBB0_15:                               ; %Flow137
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s13
	s_add_i32 s12, s53, s12
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_ge_i32 s12, s4
	s_cbranch_scc0 .LBB0_2
.LBB0_16:                               ; %.loopexit72
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7FF_calcPfS_S_iiffS_f
		.amdhsa_group_segment_fixed_size 272
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 312
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 37
		.amdhsa_next_free_sgpr 59
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z7FF_calcPfS_S_iiffS_f, .Lfunc_end0-_Z7FF_calcPfS_S_iiffS_f
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 5508
; NumSgprs: 61
; NumVgprs: 37
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 272 bytes/workgroup (compile time only)
; SGPRBlocks: 7
; VGPRBlocks: 4
; NumSGPRsForWavesPerEU: 61
; NumVGPRsForWavesPerEU: 37
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         36
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .offset:         48
        .size:           4
        .value_kind:     by_value
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         60
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         64
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         68
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         70
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         72
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         74
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         76
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         78
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         112
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         120
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 272
    .kernarg_segment_align: 8
    .kernarg_segment_size: 312
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z7FF_calcPfS_S_iiffS_f
    .private_segment_fixed_size: 0
    .sgpr_count:     61
    .sgpr_spill_count: 0
    .symbol:         _Z7FF_calcPfS_S_iiffS_f.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     37
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
