#include <iostream>
#include <cuda.h>
#include <cuda_runtime.h>

/*
 * kernel function to be run parallel on device
 */
__global__
void rgb2gray_kernel(const uchar3 *rgb,
                   uchar1 *gray,
                   const int n_rows,
                   const int n_cols
                   ){
    // maximum index accessible in the image
    const int img_size = n_rows * n_cols;

    int pixelIdx_x = blockIdx.x * blockDim.x + threadIdx.x;
    int pixelIdx_y = blockIdx.y * blockDim.y + threadIdx.y;

    // be careful not to exceed image boundary
    if (pixelIdx_x < n_cols && pixelIdx_y < n_rows){

        int pixelIdx = pixelIdx_y * n_cols + pixelIdx_x;

        // gray = .299f * red + .587f * geen + .114f * blue;
        gray[pixelIdx].x = (unsigned char)(
                    0.299 * rgb[pixelIdx].x +
                    0.587 * rgb[pixelIdx].y +
                    0.114 * rgb[pixelIdx].z );
    }
}

void rgb2gray_caller(const uchar3 *rgb,
                     uchar1 *gray,
                     const int n_rows,
                     const int n_cols){
    
    // n_rows = n_threads_y
    // n_cols = n_threads_x
    const int n_threads_per_dim = 32;
    
    // number of blocks along x axis
    const int n_blocks_x = n_cols % n_threads_per_dim == 0 ? n_cols / n_threads_per_dim : n_cols / n_threads_per_dim + 1 ;
    const int n_blocks_y = n_rows % n_threads_per_dim == 0 ? n_rows / n_threads_per_dim : n_rows / n_threads_per_dim + 1 ;

    std::cout << "n_threads_per_dim: " << n_threads_per_dim << std::endl;
    std::cout << "n_threads_per_block: " << n_threads_per_dim * n_threads_per_dim << std::endl;
    std::cout << "n_blocks_x: " << n_blocks_x << ", ";
    std::cout << "n_blocks_y: " << n_blocks_y << std::endl;

    const dim3 grid(n_blocks_x, n_blocks_y, 1);
    const dim3 block(n_threads_per_dim, n_threads_per_dim, 1);

    rgb2gray_kernel<<<grid, block>>>(rgb, gray, n_rows, n_cols);
}

	.file	"tmpxft_001fe996_00000000-6_rgb2gray.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3638:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3638:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z52__device_stub__Z15rgb2gray_kernelPK6uchar3P6uchar1iiPK6uchar3P6uchar1ii
	.type	_Z52__device_stub__Z15rgb2gray_kernelPK6uchar3P6uchar1iiPK6uchar3P6uchar1ii, @function
_Z52__device_stub__Z15rgb2gray_kernelPK6uchar3P6uchar1iiPK6uchar3P6uchar1ii:
.LFB3660:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z15rgb2gray_kernelPK6uchar3P6uchar1ii(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L2:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3660:
	.size	_Z52__device_stub__Z15rgb2gray_kernelPK6uchar3P6uchar1iiPK6uchar3P6uchar1ii, .-_Z52__device_stub__Z15rgb2gray_kernelPK6uchar3P6uchar1iiPK6uchar3P6uchar1ii
	.globl	_Z15rgb2gray_kernelPK6uchar3P6uchar1ii
	.type	_Z15rgb2gray_kernelPK6uchar3P6uchar1ii, @function
_Z15rgb2gray_kernelPK6uchar3P6uchar1ii:
.LFB3661:
	.cfi_startproc
	endbr64
	jmp	_Z52__device_stub__Z15rgb2gray_kernelPK6uchar3P6uchar1iiPK6uchar3P6uchar1ii
	.cfi_endproc
.LFE3661:
	.size	_Z15rgb2gray_kernelPK6uchar3P6uchar1ii, .-_Z15rgb2gray_kernelPK6uchar3P6uchar1ii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"n_threads_per_dim: "
.LC1:
	.string	"n_threads_per_block: "
.LC2:
	.string	"n_blocks_x: "
.LC3:
	.string	", "
.LC4:
	.string	"n_blocks_y: "
	.text
	.globl	_Z15rgb2gray_callerPK6uchar3P6uchar1ii
	.type	_Z15rgb2gray_callerPK6uchar3P6uchar1ii, @function
_Z15rgb2gray_callerPK6uchar3P6uchar1ii:
.LFB3635:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movq	%rsi, %r15
	leaq	.LC0(%rip), %rsi
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	leaq	_ZSt4cout(%rip), %r14
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movl	%ecx, %ebp
	movl	$32, %ecx
	movl	%ebp, %eax
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movl	%edx, %ebx
	cltd
	idivl	%ecx
	movl	%ebp, %edx
	subq	$56, %rsp
	.cfi_def_cfa_offset 112
	andl	$31, %edx
	movq	%rdi, 8(%rsp)
	movq	%r14, %rdi
	cmpl	$1, %edx
	sbbl	$-1, %eax
	movl	%eax, %r13d
	movl	%ebx, %eax
	cltd
	idivl	%ecx
	movl	%ebx, %edx
	andl	$31, %edx
	cmpl	$1, %edx
	sbbl	$-1, %eax
	movl	%eax, %r12d
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	$32, %esi
	movq	%rax, %rdi
	call	_ZNSolsEi@PLT
	movq	%rax, %rdi
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
	leaq	.LC1(%rip), %rsi
	movq	%r14, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	$1024, %esi
	movq	%rax, %rdi
	call	_ZNSolsEi@PLT
	movq	%rax, %rdi
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
	leaq	.LC2(%rip), %rsi
	movq	%r14, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	%r13d, %esi
	movq	%rax, %rdi
	call	_ZNSolsEi@PLT
	leaq	.LC3(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	leaq	.LC4(%rip), %rsi
	movq	%r14, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	%r12d, %esi
	movq	%rax, %rdi
	call	_ZNSolsEi@PLT
	movq	%rax, %rdi
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
	movl	%r13d, 24(%rsp)
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	%r12d, 28(%rsp)
	movq	24(%rsp), %rdi
	movl	$1, %ecx
	movabsq	$137438953504, %rdx
	movl	$1, %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L8
	movq	8(%rsp), %rdi
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 56
	movl	%ebp, %ecx
	movl	%ebx, %edx
	movq	%r15, %rsi
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	_Z52__device_stub__Z15rgb2gray_kernelPK6uchar3P6uchar1iiPK6uchar3P6uchar1ii
.L8:
	.cfi_restore_state
	addq	$56, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3635:
	.size	_Z15rgb2gray_callerPK6uchar3P6uchar1ii, .-_Z15rgb2gray_callerPK6uchar3P6uchar1ii
	.section	.rodata.str1.1
.LC5:
	.string	"_Z15rgb2gray_kernelPK6uchar3P6uchar1ii"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3663:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC5(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z15rgb2gray_kernelPK6uchar3P6uchar1ii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3663:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <iostream>
#include <hip/hip_runtime.h>


/*
 * kernel function to be run parallel on device
 */
__global__
void rgb2gray_kernel(const uchar3 *rgb,
                   uchar1 *gray,
                   const int n_rows,
                   const int n_cols
                   ){
    // maximum index accessible in the image
    const int img_size = n_rows * n_cols;

    int pixelIdx_x = blockIdx.x * blockDim.x + threadIdx.x;
    int pixelIdx_y = blockIdx.y * blockDim.y + threadIdx.y;

    // be careful not to exceed image boundary
    if (pixelIdx_x < n_cols && pixelIdx_y < n_rows){

        int pixelIdx = pixelIdx_y * n_cols + pixelIdx_x;

        // gray = .299f * red + .587f * geen + .114f * blue;
        gray[pixelIdx].x = (unsigned char)(
                    0.299 * rgb[pixelIdx].x +
                    0.587 * rgb[pixelIdx].y +
                    0.114 * rgb[pixelIdx].z );
    }
}

void rgb2gray_caller(const uchar3 *rgb,
                     uchar1 *gray,
                     const int n_rows,
                     const int n_cols){
    
    // n_rows = n_threads_y
    // n_cols = n_threads_x
    const int n_threads_per_dim = 32;
    
    // number of blocks along x axis
    const int n_blocks_x = n_cols % n_threads_per_dim == 0 ? n_cols / n_threads_per_dim : n_cols / n_threads_per_dim + 1 ;
    const int n_blocks_y = n_rows % n_threads_per_dim == 0 ? n_rows / n_threads_per_dim : n_rows / n_threads_per_dim + 1 ;

    std::cout << "n_threads_per_dim: " << n_threads_per_dim << std::endl;
    std::cout << "n_threads_per_block: " << n_threads_per_dim * n_threads_per_dim << std::endl;
    std::cout << "n_blocks_x: " << n_blocks_x << ", ";
    std::cout << "n_blocks_y: " << n_blocks_y << std::endl;

    const dim3 grid(n_blocks_x, n_blocks_y, 1);
    const dim3 block(n_threads_per_dim, n_threads_per_dim, 1);

    rgb2gray_kernel<<<grid, block>>>(rgb, gray, n_rows, n_cols);
}

	.text
	.file	"rgb2gray.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z30__device_stub__rgb2gray_kernelPK15HIP_vector_typeIhLj3EEPS_IhLj1EEii # -- Begin function _Z30__device_stub__rgb2gray_kernelPK15HIP_vector_typeIhLj3EEPS_IhLj1EEii
	.type	_Z30__device_stub__rgb2gray_kernelPK15HIP_vector_typeIhLj3EEPS_IhLj1EEii,@function
_Z30__device_stub__rgb2gray_kernelPK15HIP_vector_typeIhLj3EEPS_IhLj1EEii: # @_Z30__device_stub__rgb2gray_kernelPK15HIP_vector_typeIhLj3EEPS_IhLj1EEii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z15rgb2gray_kernelPK15HIP_vector_typeIhLj3EEPS_IhLj1EEii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z30__device_stub__rgb2gray_kernelPK15HIP_vector_typeIhLj3EEPS_IhLj1EEii, .Lfunc_end0-_Z30__device_stub__rgb2gray_kernelPK15HIP_vector_typeIhLj3EEPS_IhLj1EEii
	.cfi_endproc
                                        # -- End function
	.globl	_Z15rgb2gray_callerPK15HIP_vector_typeIhLj3EEPS_IhLj1EEii # -- Begin function _Z15rgb2gray_callerPK15HIP_vector_typeIhLj3EEPS_IhLj1EEii
	.type	_Z15rgb2gray_callerPK15HIP_vector_typeIhLj3EEPS_IhLj1EEii,@function
_Z15rgb2gray_callerPK15HIP_vector_typeIhLj3EEPS_IhLj1EEii: # @_Z15rgb2gray_callerPK15HIP_vector_typeIhLj3EEPS_IhLj1EEii
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	pushq	%rax
	.cfi_def_cfa_offset 64
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%ecx, %ebx
	movl	%edx, %r14d
	movq	%rsi, (%rsp)                    # 8-byte Spill
	movq	%rdi, %r12
	testb	$31, %bl
	je	.LBB1_1
# %bb.2:
	leal	31(%rbx), %ebp
	testl	%ebx, %ebx
	cmovnsl	%ebx, %ebp
	sarl	$5, %ebp
	incl	%ebp
	jmp	.LBB1_3
.LBB1_1:
	movl	%ebx, %ebp
	sarl	$5, %ebp
.LBB1_3:
	testb	$31, %r14b
	je	.LBB1_4
# %bb.5:
	leal	31(%r14), %r13d
	testl	%r14d, %r14d
	cmovnsl	%r14d, %r13d
	sarl	$5, %r13d
	incl	%r13d
	jmp	.LBB1_6
.LBB1_4:
	movl	%r14d, %r13d
	sarl	$5, %r13d
.LBB1_6:
	movl	$_ZSt4cout, %edi
	movl	$.L.str, %esi
	movl	$19, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	$_ZSt4cout, %edi
	movl	$32, %esi
	callq	_ZNSolsEi
	movq	%rax, %r15
	movq	(%rax), %rax
	movq	-24(%rax), %rdi
	addq	%r15, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%r15, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movl	$_ZSt4cout, %edi
	movl	$.L.str.1, %esi
	movl	$21, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	$_ZSt4cout, %edi
	movl	$1024, %esi                     # imm = 0x400
	callq	_ZNSolsEi
	movq	%rax, %r15
	movq	(%rax), %rax
	movq	-24(%rax), %rdi
	addq	%r15, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%r15, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movl	$_ZSt4cout, %edi
	movl	$.L.str.2, %esi
	movl	$12, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	$_ZSt4cout, %edi
	movl	%ebp, %esi
	callq	_ZNSolsEi
	movl	$.L.str.3, %esi
	movl	$2, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	$_ZSt4cout, %edi
	movl	$.L.str.4, %esi
	movl	$12, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	$_ZSt4cout, %edi
	movl	%r13d, %esi
	callq	_ZNSolsEi
	movq	%rax, %r15
	movq	(%rax), %rax
	movq	-24(%rax), %rdi
	addq	%r15, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%r15, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movl	%ebp, %eax
	shlq	$32, %r13
	orq	%rax, %r13
	movabsq	$137438953504, %rdx             # imm = 0x2000000020
	movq	%r13, %rdi
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	je	.LBB1_8
# %bb.7:
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB1_8:
	.cfi_def_cfa_offset 64
	movq	%r12, %rdi
	movq	(%rsp), %rsi                    # 8-byte Reload
	movl	%r14d, %edx
	movl	%ebx, %ecx
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z30__device_stub__rgb2gray_kernelPK15HIP_vector_typeIhLj3EEPS_IhLj1EEii # TAILCALL
.Lfunc_end1:
	.size	_Z15rgb2gray_callerPK15HIP_vector_typeIhLj3EEPS_IhLj1EEii, .Lfunc_end1-_Z15rgb2gray_callerPK15HIP_vector_typeIhLj3EEPS_IhLj1EEii
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z15rgb2gray_kernelPK15HIP_vector_typeIhLj3EEPS_IhLj1EEii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z15rgb2gray_kernelPK15HIP_vector_typeIhLj3EEPS_IhLj1EEii,@object # @_Z15rgb2gray_kernelPK15HIP_vector_typeIhLj3EEPS_IhLj1EEii
	.section	.rodata,"a",@progbits
	.globl	_Z15rgb2gray_kernelPK15HIP_vector_typeIhLj3EEPS_IhLj1EEii
	.p2align	3, 0x0
_Z15rgb2gray_kernelPK15HIP_vector_typeIhLj3EEPS_IhLj1EEii:
	.quad	_Z30__device_stub__rgb2gray_kernelPK15HIP_vector_typeIhLj3EEPS_IhLj1EEii
	.size	_Z15rgb2gray_kernelPK15HIP_vector_typeIhLj3EEPS_IhLj1EEii, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"n_threads_per_dim: "
	.size	.L.str, 20

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"n_threads_per_block: "
	.size	.L.str.1, 22

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"n_blocks_x: "
	.size	.L.str.2, 13

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	", "
	.size	.L.str.3, 3

	.type	.L.str.4,@object                # @.str.4
.L.str.4:
	.asciz	"n_blocks_y: "
	.size	.L.str.4, 13

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z15rgb2gray_kernelPK15HIP_vector_typeIhLj3EEPS_IhLj1EEii"
	.size	.L__unnamed_1, 58

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z30__device_stub__rgb2gray_kernelPK15HIP_vector_typeIhLj3EEPS_IhLj1EEii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z15rgb2gray_kernelPK15HIP_vector_typeIhLj3EEPS_IhLj1EEii
	.addrsig_sym _ZSt4cout
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z15rgb2gray_kernelPK15HIP_vector_typeIhLj3EEPS_IhLj1EEii ; -- Begin function _Z15rgb2gray_kernelPK15HIP_vector_typeIhLj3EEPS_IhLj1EEii
	.globl	_Z15rgb2gray_kernelPK15HIP_vector_typeIhLj3EEPS_IhLj1EEii
	.p2align	8
	.type	_Z15rgb2gray_kernelPK15HIP_vector_typeIhLj3EEPS_IhLj1EEii,@function
_Z15rgb2gray_kernelPK15HIP_vector_typeIhLj3EEPS_IhLj1EEii: ; @_Z15rgb2gray_kernelPK15HIP_vector_typeIhLj3EEPS_IhLj1EEii
; %bb.0:
	s_clause 0x1
	s_load_b32 s4, s[0:1], 0x24
	s_load_b64 s[2:3], s[0:1], 0x10
	v_and_b32_e32 v2, 0x3ff, v0
	v_bfe_u32 v3, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s5, s4, 16
	s_and_b32 s4, s4, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[0:1], null, s14, s4, v[2:3]
	v_mad_u64_u32 v[1:2], null, s15, s5, v[3:4]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_i32_e32 vcc_lo, s3, v0
	v_cmp_gt_i32_e64 s2, s2, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, vcc_lo, s2
	s_and_saveexec_b32 s4, s2
	s_cbranch_execz .LBB0_2
; %bb.1:
	s_load_b128 s[4:7], s[0:1], 0x0
	v_mad_u64_u32 v[2:3], null, v1, s3, v[0:1]
	s_mov_b32 s0, 0x39581062
	s_mov_b32 s1, 0x3fe2c8b4
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_mad_i64_i32 v[0:1], null, v2, 3, s[4:5]
	s_clause 0x1
	global_load_u16 v3, v[0:1], off
	global_load_u8 v5, v[0:1], off offset:2
	s_waitcnt vmcnt(1)
	v_bfe_u32 v0, v3, 8, 8
	v_and_b32_e32 v3, 0xff, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_f64_u32_e32 v[0:1], v0
	v_and_b32_e32 v3, 0xffff, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cvt_f64_u32_e32 v[3:4], v3
	v_mul_f64 v[0:1], v[0:1], s[0:1]
	s_mov_b32 s0, 0xe5604189
	s_mov_b32 s1, 0x3fd322d0
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[0:1], v[3:4], s[0:1], v[0:1]
	s_waitcnt vmcnt(0)
	v_cvt_f64_u32_e32 v[3:4], v5
	s_mov_b32 s0, 0x9fbe76c9
	s_mov_b32 s1, 0x3fbd2f1a
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[0:1], v[3:4], s[0:1], v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_cvt_i32_f64_e32 v3, v[0:1]
	v_ashrrev_i32_e32 v1, 31, v2
	v_add_co_u32 v0, vcc_lo, s6, v2
	v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
	global_store_b8 v[0:1], v3, off
.LBB0_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z15rgb2gray_kernelPK15HIP_vector_typeIhLj3EEPS_IhLj1EEii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 6
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z15rgb2gray_kernelPK15HIP_vector_typeIhLj3EEPS_IhLj1EEii, .Lfunc_end0-_Z15rgb2gray_kernelPK15HIP_vector_typeIhLj3EEPS_IhLj1EEii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 332
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z15rgb2gray_kernelPK15HIP_vector_typeIhLj3EEPS_IhLj1EEii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z15rgb2gray_kernelPK15HIP_vector_typeIhLj3EEPS_IhLj1EEii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     6
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
