struct ArrayListNewCudaPixelData
{
	__device__  ArrayListNewCudaPixelData()
	{
	}
	unsigned char blue;
	unsigned char green;
	unsigned char red;
	unsigned char alpha;
};


// H264Images.ArrayListNewCuda
extern "C" __global__  void calGPU( unsigned char* dev_bitmap1, int dev_bitmap1Len0,  unsigned char* dev_bitmap2, int dev_bitmap2Len0,  unsigned char* dev_result, int dev_resultLen0,  int* imageWidth, int imageWidthLen0,  int* count, int countLen0,  int* possition, int possitionLen0);

// H264Images.ArrayListNewCuda
extern "C" __global__  void calGPU( unsigned char* dev_bitmap1, int dev_bitmap1Len0,  unsigned char* dev_bitmap2, int dev_bitmap2Len0,  unsigned char* dev_result, int dev_resultLen0,  int* imageWidth, int imageWidthLen0,  int* count, int countLen0,  int* possition, int possitionLen0)
{
	int i = blockIdx.x * blockDim.x + threadIdx.x;
	int j = blockIdx.y * blockDim.y + threadIdx.y;
	__shared__ int array[2];

	int arrayLen0 = 2;
	array[(0)] = 0;
	array[(1)] = 0;
	for (i = 0; i < imageWidth[(1)]; i++)
	{
		for (j = 0; j < imageWidth[(0)]; j++)
		{
			int num = (i * imageWidth[(0)] + j) * 4;
			ArrayListNewCudaPixelData pixelData = ArrayListNewCudaPixelData();
			ArrayListNewCudaPixelData pixelData2 = ArrayListNewCudaPixelData();
			pixelData.red = dev_bitmap1[(num + 2)];
			pixelData.green = dev_bitmap1[(num + 1)];
			pixelData.blue = dev_bitmap1[(num)];
			pixelData.alpha = dev_bitmap1[(num + 3)];
			pixelData2.green = dev_bitmap2[(num + 1)];
			pixelData2.red = dev_bitmap2[(num + 2)];
			pixelData2.blue = dev_bitmap2[(num)];
			pixelData2.alpha = dev_bitmap2[(num + 3)];
			bool flag = pixelData.red > pixelData2.red;
			int num2;
			if (flag)
			{
				num2 = (int)(pixelData.red - pixelData2.red);
			}
			else
			{
				num2 = (int)(pixelData2.red - pixelData.red);
			}
			bool flag2 = pixelData.alpha > pixelData2.alpha;
			int num3;
			if (flag2)
			{
				num3 = (int)(pixelData.alpha - pixelData2.alpha);
			}
			else
			{
				num3 = (int)(pixelData2.alpha - pixelData.alpha);
			}
			bool flag3 = pixelData.green > pixelData2.green;
			int num4;
			if (flag3)
			{
				num4 = (int)(pixelData.green - pixelData2.green);
			}
			else
			{
				num4 = (int)(pixelData2.green - pixelData.green);
			}
			bool flag4 = pixelData.blue > pixelData2.blue;
			int num5;
			if (flag4)
			{
				num5 = (int)(pixelData.blue - pixelData2.blue);
			}
			else
			{
				num5 = (int)(pixelData2.blue - pixelData.blue);
			}
			bool flag5 = num2 > 8 || num3 > 8 || num4 > 8 || num5 > 8;
			if (flag5)
			{
				 int* expr_1F9_cp_0 = array;
				int expr_1F9_cp_1 = 1;
				int num6 = expr_1F9_cp_0[(expr_1F9_cp_1)];
				expr_1F9_cp_0[(expr_1F9_cp_1)] = num6 + 1;
				possition[(num6)] = i;
				 int* expr_20F_cp_0 = array;
				int expr_20F_cp_1 = 1;
				num6 = expr_20F_cp_0[(expr_20F_cp_1)];
				expr_20F_cp_0[(expr_20F_cp_1)] = num6 + 1;
				possition[(num6)] = j;
				 int* expr_224_cp_0 = array;
				int expr_224_cp_1 = 0;
				num6 = expr_224_cp_0[(expr_224_cp_1)];
				expr_224_cp_0[(expr_224_cp_1)] = num6 + 1;
				dev_result[(num6)] = pixelData2.blue;
				 int* expr_23F_cp_0 = array;
				int expr_23F_cp_1 = 0;
				num6 = expr_23F_cp_0[(expr_23F_cp_1)];
				expr_23F_cp_0[(expr_23F_cp_1)] = num6 + 1;
				dev_result[(num6)] = pixelData2.green;
				 int* expr_25A_cp_0 = array;
				int expr_25A_cp_1 = 0;
				num6 = expr_25A_cp_0[(expr_25A_cp_1)];
				expr_25A_cp_0[(expr_25A_cp_1)] = num6 + 1;
				dev_result[(num6)] = pixelData2.red;
				 int* expr_275_cp_0 = array;
				int expr_275_cp_1 = 0;
				num6 = expr_275_cp_0[(expr_275_cp_1)];
				expr_275_cp_0[(expr_275_cp_1)] = num6 + 1;
				dev_result[(num6)] = pixelData2.alpha;
				count[(1)] = array[(1)];
				count[(0)] = array[(0)];
			}
		}
	}
}

	.file	"tmpxft_003aaadf_00000000-6_CUDAFYSOURCETEMP.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2013:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2013:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z43__device_stub__Z6calGPUPhiS_iS_iPiiS0_iS0_iPhiS_iS_iPiiS0_iS0_i
	.type	_Z43__device_stub__Z6calGPUPhiS_iS_iPiiS0_iS0_iPhiS_iS_iPiiS0_iS0_i, @function
_Z43__device_stub__Z6calGPUPhiS_iS_iPiiS0_iS0_iPhiS_iS_iPiiS0_iS0_i:
.LFB2035:
	.cfi_startproc
	endbr64
	subq	$248, %rsp
	.cfi_def_cfa_offset 256
	movq	256(%rsp), %rax
	movq	%rdi, 56(%rsp)
	leaq	88(%rsp), %rdi
	movl	%esi, 52(%rsp)
	leaq	100(%rsp), %rsi
	movq	%rax, 16(%rsp)
	movq	272(%rsp), %rax
	movq	%rdx, 40(%rsp)
	leaq	72(%rsp), %rdx
	movq	%rax, 8(%rsp)
	movq	288(%rsp), %rax
	movl	%ecx, 48(%rsp)
	leaq	80(%rsp), %rcx
	movq	%r8, 32(%rsp)
	movl	%r9d, 28(%rsp)
	movq	%rax, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 232(%rsp)
	xorl	%eax, %eax
	leaq	56(%rsp), %rax
	movl	$1, 96(%rsp)
	movq	%rax, 136(%rsp)
	leaq	52(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	28(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	264(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	280(%rsp), %rax
	movq	%rax, 208(%rsp)
	movq	%rsp, %rax
	movq	%rax, 216(%rsp)
	leaq	296(%rsp), %rax
	movq	%rax, 224(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 88(%rsp)
	movq	%rax, 100(%rsp)
	movl	$1, 108(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	80(%rsp)
	.cfi_def_cfa_offset 264
	leaq	calGPU(%rip), %rdi
	pushq	80(%rsp)
	.cfi_def_cfa_offset 272
	movq	116(%rsp), %rcx
	movl	124(%rsp), %r8d
	movq	104(%rsp), %rsi
	movl	112(%rsp), %edx
	leaq	152(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 264
	popq	%rdx
	.cfi_def_cfa_offset 256
.L2:
	movq	232(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$248, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2035:
	.size	_Z43__device_stub__Z6calGPUPhiS_iS_iPiiS0_iS0_iPhiS_iS_iPiiS0_iS0_i, .-_Z43__device_stub__Z6calGPUPhiS_iS_iPiiS0_iS0_iPhiS_iS_iPiiS0_iS0_i
	.globl	calGPU
	.type	calGPU, @function
calGPU:
.LFB2036:
	.cfi_startproc
	endbr64
	jmp	_Z43__device_stub__Z6calGPUPhiS_iS_iPiiS0_iS0_iPhiS_iS_iPiiS0_iS0_i
	.cfi_endproc
.LFE2036:
	.size	calGPU, .-calGPU
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"calGPU"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2038:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	calGPU(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2038:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
struct ArrayListNewCudaPixelData
{
	__device__  ArrayListNewCudaPixelData()
	{
	}
	unsigned char blue;
	unsigned char green;
	unsigned char red;
	unsigned char alpha;
};


// H264Images.ArrayListNewCuda
extern "C" __global__  void calGPU( unsigned char* dev_bitmap1, int dev_bitmap1Len0,  unsigned char* dev_bitmap2, int dev_bitmap2Len0,  unsigned char* dev_result, int dev_resultLen0,  int* imageWidth, int imageWidthLen0,  int* count, int countLen0,  int* possition, int possitionLen0);

// H264Images.ArrayListNewCuda
extern "C" __global__  void calGPU( unsigned char* dev_bitmap1, int dev_bitmap1Len0,  unsigned char* dev_bitmap2, int dev_bitmap2Len0,  unsigned char* dev_result, int dev_resultLen0,  int* imageWidth, int imageWidthLen0,  int* count, int countLen0,  int* possition, int possitionLen0)
{
	int i = blockIdx.x * blockDim.x + threadIdx.x;
	int j = blockIdx.y * blockDim.y + threadIdx.y;
	__shared__ int array[2];

	int arrayLen0 = 2;
	array[(0)] = 0;
	array[(1)] = 0;
	for (i = 0; i < imageWidth[(1)]; i++)
	{
		for (j = 0; j < imageWidth[(0)]; j++)
		{
			int num = (i * imageWidth[(0)] + j) * 4;
			ArrayListNewCudaPixelData pixelData = ArrayListNewCudaPixelData();
			ArrayListNewCudaPixelData pixelData2 = ArrayListNewCudaPixelData();
			pixelData.red = dev_bitmap1[(num + 2)];
			pixelData.green = dev_bitmap1[(num + 1)];
			pixelData.blue = dev_bitmap1[(num)];
			pixelData.alpha = dev_bitmap1[(num + 3)];
			pixelData2.green = dev_bitmap2[(num + 1)];
			pixelData2.red = dev_bitmap2[(num + 2)];
			pixelData2.blue = dev_bitmap2[(num)];
			pixelData2.alpha = dev_bitmap2[(num + 3)];
			bool flag = pixelData.red > pixelData2.red;
			int num2;
			if (flag)
			{
				num2 = (int)(pixelData.red - pixelData2.red);
			}
			else
			{
				num2 = (int)(pixelData2.red - pixelData.red);
			}
			bool flag2 = pixelData.alpha > pixelData2.alpha;
			int num3;
			if (flag2)
			{
				num3 = (int)(pixelData.alpha - pixelData2.alpha);
			}
			else
			{
				num3 = (int)(pixelData2.alpha - pixelData.alpha);
			}
			bool flag3 = pixelData.green > pixelData2.green;
			int num4;
			if (flag3)
			{
				num4 = (int)(pixelData.green - pixelData2.green);
			}
			else
			{
				num4 = (int)(pixelData2.green - pixelData.green);
			}
			bool flag4 = pixelData.blue > pixelData2.blue;
			int num5;
			if (flag4)
			{
				num5 = (int)(pixelData.blue - pixelData2.blue);
			}
			else
			{
				num5 = (int)(pixelData2.blue - pixelData.blue);
			}
			bool flag5 = num2 > 8 || num3 > 8 || num4 > 8 || num5 > 8;
			if (flag5)
			{
				 int* expr_1F9_cp_0 = array;
				int expr_1F9_cp_1 = 1;
				int num6 = expr_1F9_cp_0[(expr_1F9_cp_1)];
				expr_1F9_cp_0[(expr_1F9_cp_1)] = num6 + 1;
				possition[(num6)] = i;
				 int* expr_20F_cp_0 = array;
				int expr_20F_cp_1 = 1;
				num6 = expr_20F_cp_0[(expr_20F_cp_1)];
				expr_20F_cp_0[(expr_20F_cp_1)] = num6 + 1;
				possition[(num6)] = j;
				 int* expr_224_cp_0 = array;
				int expr_224_cp_1 = 0;
				num6 = expr_224_cp_0[(expr_224_cp_1)];
				expr_224_cp_0[(expr_224_cp_1)] = num6 + 1;
				dev_result[(num6)] = pixelData2.blue;
				 int* expr_23F_cp_0 = array;
				int expr_23F_cp_1 = 0;
				num6 = expr_23F_cp_0[(expr_23F_cp_1)];
				expr_23F_cp_0[(expr_23F_cp_1)] = num6 + 1;
				dev_result[(num6)] = pixelData2.green;
				 int* expr_25A_cp_0 = array;
				int expr_25A_cp_1 = 0;
				num6 = expr_25A_cp_0[(expr_25A_cp_1)];
				expr_25A_cp_0[(expr_25A_cp_1)] = num6 + 1;
				dev_result[(num6)] = pixelData2.red;
				 int* expr_275_cp_0 = array;
				int expr_275_cp_1 = 0;
				num6 = expr_275_cp_0[(expr_275_cp_1)];
				expr_275_cp_0[(expr_275_cp_1)] = num6 + 1;
				dev_result[(num6)] = pixelData2.alpha;
				count[(1)] = array[(1)];
				count[(0)] = array[(0)];
			}
		}
	}
}

	.text
	.file	"CUDAFYSOURCETEMP.hip"
	.globl	__device_stub__calGPU           # -- Begin function __device_stub__calGPU
	.type	__device_stub__calGPU,@function
__device_stub__calGPU:                  # @__device_stub__calGPU
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$192, %rsp
	.cfi_def_cfa_offset 240
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	20(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	48(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	16(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	40(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	12(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	240(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	248(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	256(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	264(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	272(%rsp), %rax
	movq	%rax, 80(%rbx)
	leaq	280(%rsp), %rax
	movq	%rax, 88(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$calGPU, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$208, %rsp
	.cfi_adjust_cfa_offset -208
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	__device_stub__calGPU, .Lfunc_end0-__device_stub__calGPU
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$calGPU, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	calGPU,@object                  # @calGPU
	.section	.rodata,"a",@progbits
	.globl	calGPU
	.p2align	3, 0x0
calGPU:
	.quad	__device_stub__calGPU
	.size	calGPU, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"calGPU"
	.size	.L__unnamed_1, 7

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __device_stub__calGPU
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym calGPU
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	calGPU                  ; -- Begin function calGPU
	.globl	calGPU
	.p2align	8
	.type	calGPU,@function
calGPU:                                 ; @calGPU
; %bb.0:
	s_load_b64 s[2:3], s[0:1], 0x30
	s_waitcnt lgkmcnt(0)
	s_load_b32 s12, s[2:3], 0x4
	s_waitcnt lgkmcnt(0)
	s_cmp_lt_i32 s12, 1
	s_cbranch_scc1 .LBB0_9
; %bb.1:                                ; %.preheader.lr.ph
	s_clause 0x4
	s_load_b64 s[4:5], s[0:1], 0x0
	s_load_b64 s[6:7], s[0:1], 0x10
	s_load_b64 s[8:9], s[0:1], 0x20
	s_load_b64 s[10:11], s[0:1], 0x40
	s_load_b64 s[0:1], s[0:1], 0x50
	s_load_b32 s13, s[2:3], 0x0
	v_dual_mov_b32 v1, s12 :: v_dual_mov_b32 v0, 0
	s_mov_b32 s14, 0
	s_mov_b32 s12, 0
	s_mov_b32 s15, 0
.LBB0_2:                                ; %.preheader
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_4 Depth 2
	s_waitcnt lgkmcnt(0)
	s_cmp_lt_i32 s13, 1
	s_cbranch_scc1 .LBB0_8
; %bb.3:                                ; %.lr.ph.preheader
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_mov_b32 s16, 0
.LBB0_4:                                ; %.lr.ph
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_mul_i32 s17, s14, s13
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s17, s16, s17
	s_lshl_b32 s17, s17, 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_ashr_i32 s20, s17, 31
	s_add_u32 s18, s4, s17
	s_addc_u32 s19, s5, s20
	global_load_b32 v2, v0, s[18:19]
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s21, v2
	v_bfe_u32 v2, v2, 8, 8
	s_delay_alu instid0(VALU_DEP_2)
	s_lshr_b32 s22, s21, 24
	s_add_u32 s18, s6, s17
	s_addc_u32 s19, s7, s20
	global_load_b32 v1, v0, s[18:19]
	s_bfe_u32 s19, s21, 0x80010
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s18, v1
	v_bfe_u32 v3, v1, 8, 8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_bfe_u32 s20, s18, 0x80010
	v_sub_nc_u32_e32 v4, v2, v3
	v_sub_nc_u32_e32 v5, v3, v2
	v_cmp_gt_u32_e32 vcc_lo, v2, v3
	s_lshr_b32 s17, s18, 24
	s_sub_i32 s23, s19, s20
	s_sub_i32 s24, s20, s19
	s_cmp_gt_u32 s19, s20
	v_cndmask_b32_e32 v2, v5, v4, vcc_lo
	s_cselect_b32 s19, s23, s24
	s_sub_i32 s20, s22, s17
	s_sub_i32 s23, s17, s22
	s_cmp_gt_u32 s22, s17
	s_cselect_b32 s20, s20, s23
	s_and_b32 s21, s21, 0xff
	s_and_b32 s18, s18, 0xff
	v_max3_i32 v2, s19, s20, v2
	s_sub_i32 s22, s21, s18
	s_sub_i32 s23, s18, s21
	s_cmp_gt_u32 s21, s18
	s_cselect_b32 s18, s22, s23
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_max_i32_e32 v2, s18, v2
	v_cmp_gt_i32_e32 vcc_lo, 9, v2
	s_cbranch_vccnz .LBB0_6
; %bb.5:                                ; %.critedge
                                        ;   in Loop: Header=BB0_4 Depth=2
	v_lshrrev_b32_e32 v2, 8, v1
	v_lshrrev_b32_e32 v3, 16, v1
	v_dual_mov_b32 v1, s14 :: v_dual_and_b32 v4, 0xff, v1
	v_lshlrev_b16 v5, 8, s17
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_lshlrev_b16 v6, 8, v2
	v_dual_mov_b32 v2, s16 :: v_dual_and_b32 v3, 0xff, v3
	s_ashr_i32 s13, s12, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	s_lshl_b64 s[18:19], s[12:13], 2
	v_or_b32_e32 v4, v4, v6
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v3, v3, v5
	s_add_u32 s18, s0, s18
	s_addc_u32 s19, s1, s19
	s_add_i32 s12, s12, 2
	s_ashr_i32 s13, s15, 31
	s_add_u32 s20, s8, s15
	v_lshlrev_b32_e32 v3, 16, v3
	s_addc_u32 s21, s9, s13
	s_add_i32 s15, s15, 4
	v_and_b32_e32 v4, 0xffff, v4
	s_delay_alu instid0(VALU_DEP_1)
	v_or_b32_e32 v5, v4, v3
	v_dual_mov_b32 v3, s15 :: v_dual_mov_b32 v4, s12
	s_clause 0x2
	global_store_b64 v0, v[1:2], s[18:19]
	global_store_b32 v0, v5, s[20:21]
	global_store_b64 v0, v[3:4], s[10:11]
	global_load_b32 v1, v0, s[2:3]
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s13, v1
.LBB0_6:                                ;   in Loop: Header=BB0_4 Depth=2
	s_add_i32 s16, s16, 1
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	s_cmp_lt_i32 s16, s13
	s_cbranch_scc1 .LBB0_4
; %bb.7:                                ; %._crit_edge.loopexit
                                        ;   in Loop: Header=BB0_2 Depth=1
	global_load_b32 v1, v0, s[2:3] offset:4
.LBB0_8:                                ; %._crit_edge
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_add_i32 s14, s14, 1
	s_waitcnt vmcnt(0)
	v_cmp_lt_i32_e32 vcc_lo, s14, v1
	s_cbranch_vccnz .LBB0_2
.LBB0_9:                                ; %._crit_edge131
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel calGPU
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 92
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 7
		.amdhsa_next_free_sgpr 25
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	calGPU, .Lfunc_end0-calGPU
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 572
; NumSgprs: 27
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 27
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .offset:         40
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         48
        .size:           8
        .value_kind:     global_buffer
      - .offset:         56
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         64
        .size:           8
        .value_kind:     global_buffer
      - .offset:         72
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         80
        .size:           8
        .value_kind:     global_buffer
      - .offset:         88
        .size:           4
        .value_kind:     by_value
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 92
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           calGPU
    .private_segment_fixed_size: 0
    .sgpr_count:     27
    .sgpr_spill_count: 0
    .symbol:         calGPU.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     7
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
