#include <stdio.h>
#include <stdlib.h>
#include <stdint.h>
#include <cuda.h>

#define SIZE(A) A*sizeof(int)

// for this method to work, (MULTIPLIER_SIZE <= NUM_MULTIPLIERS) must be true
#define MULTIPLIER_SIZE 32
#define NUM_MULTIPLIERS 32 // arbitrary size

typedef struct {
	int ibits, obits; // bit precision of neurons
	int stride; // filter stride length
	int nx, ny, nz; // input dimensions
	int f; // number of filters
	int sx, sy; // filter dimensions
	int ox, oy; // output dimensions
} conv_data;

__global__ void CLCTest(int *neuron, int *synapse, int *output, conv_data cd) {
	volatile int tid = threadIdx.x;
	int bid = blockIdx.x;
	bool last_block = (cd.ox*cd.oy / NUM_MULTIPLIERS + ((cd.ox*cd.oy) % NUM_MULTIPLIERS != 0) - 1) == bid;

	int window_size = cd.sx*cd.sy*cd.nz;
	int num_windows = cd.ox*cd.oy;

	for (int i = 0; i < window_size/NUM_MULTIPLIERS; i++) {
		volatile int out_neuron;
		volatile int j;

		// send groups of 4 neurons to the operand collector
		for (j = bid*MULTIPLIER_SIZE+3; (j < (bid+1)*MULTIPLIER_SIZE) && (j < num_windows); j += 4) {
			int temp[4];
			for (int k = 0; k < 4; k++) {
				temp[k] = i*NUM_MULTIPLIERS+tid + ((j-3+k)/cd.oy)*cd.ny*cd.nz*cd.stride + ((j-3+k)%cd.oy)*cd.nz*cd.stride;
			}

			asm("/*");
			asm("CPTX_BEGIN");
			asm("clp.s32 %0, %1, %2, %3;" :: "r"(neuron[temp[0]]), "r"(neuron[temp[1]]), "r"(neuron[temp[2]]), "r"(neuron[temp[3]]));
			asm("CPTX_END");
			asm("*/");
		}

		// send the remaining neurons individually to the operand collector
		if (last_block) { // this assumes MULTIPLIER_SIZE % 4 == 0
			j -= 3; // revert the last iteration from previous for loop and add 1
			for (; j < num_windows; j++) {
				asm("/*");
				asm("CPTX_BEGIN");
				asm("clp.s32 %0;" :: "r"(neuron[i+tid + (j/cd.oy)*cd.ny*cd.nz*cd.stride + (j%cd.oy)*cd.nz*cd.stride]));
				asm("CPTX_END");
				asm("*/");
			}
		}

		// compute the result
		asm("/*");
		asm("CPTX_BEGIN");
		asm("clc.s32 %0, %1, %2, %3;" : "=r"(out_neuron) : "r"(synapse[i*NUM_MULTIPLIERS+tid]), "r"(cd.ibits), "r"(cd.obits));
		asm("CPTX_END");
		asm("*/");

		// store the result, making sure the garbage return values are ignored
		if ((!last_block && (tid < MULTIPLIER_SIZE)) || (last_block && (tid < num_windows % MULTIPLIER_SIZE))) {
			output[bid*MULTIPLIER_SIZE + tid] += out_neuron;
		}
	}
}

int main(int argc, char** argv) {
	conv_data cd;
	cd.ibits = 4; cd.obits = 8; cd.stride = 2;
	cd.nx = 8; cd.ny = 8; cd.nz = 3; cd.f = 2;
	cd.sx = 4; cd.sy = 4; cd.ox = 3; cd.oy = 3;
	// ox = (nx-sx)/stride + 1;
	// oy = (ny-sy)/stride + 1;

	int neuron[cd.nx*cd.ny*cd.nz];
	int synapse[cd.f*cd.sx*cd.sy*cd.nz];
	int output[cd.f*cd.ox*cd.oy];
	memset(output, 0, SIZE(cd.ox*cd.oy*cd.f));

	FILE *fp;
	fp = fopen("input", "r");

	// collect neuron data
	for (int k = 0; k < cd.nz; k++) {
		for (int j = 0; j < cd.ny; j++) {
			for (int i = 0; i < cd.nx; i++) {
				fscanf(fp, "%d", &neuron[i*cd.ny*cd.nz + j*cd.nz + k]);
			}
		}
	}
	// collect synapse data
	for (int l = 0; l < cd.f; l++) {
		for (int k = 0; k < cd.nz; k++) {
			for (int j = 0; j < cd.sy; j++) {
				for (int i = 0; i < cd.sx; i++) {
					fscanf(fp, "%d", &synapse[l*cd.sx*cd.sy*cd.nz + i*cd.sy*cd.nz + j*cd.nz + k]);
				}
			}
		}
	}

	fclose(fp);
	
	int *d_neuron, *d_synapse, *d_output;
	cudaMalloc(&d_neuron, SIZE(cd.nx*cd.ny*cd.nz));
	cudaMalloc(&d_synapse, SIZE(cd.f*cd.sx*cd.sy*cd.nz));
	cudaMalloc(&d_output, SIZE(cd.ox*cd.oy*cd.f));
	cudaMemcpy(d_neuron, neuron, SIZE(cd.nx*cd.ny*cd.nz), cudaMemcpyHostToDevice);
	cudaMemcpy(d_synapse, synapse, SIZE(cd.f*cd.sx*cd.sy*cd.nz), cudaMemcpyHostToDevice);
	cudaMemcpy(d_output, output, SIZE(cd.ox*cd.oy*cd.f), cudaMemcpyHostToDevice);

	// one thread block is composed of MULTIPLIER_SIZE windows and NUM_MULTIPLIERS threads
	int blocks = cd.ox*cd.oy / NUM_MULTIPLIERS + ((cd.ox*cd.oy) % NUM_MULTIPLIERS != 0);
	// apply one filter per kernel
	for (int f = 0; f < cd.f; f++) {
		CLCTest<<<blocks, NUM_MULTIPLIERS>>>(d_neuron, d_synapse + f*cd.sx*cd.sy*cd.nz, d_output + f*cd.ox*cd.oy, cd);
	}

	cudaMemcpy(output, d_output, SIZE(cd.ox*cd.oy*cd.f), cudaMemcpyDeviceToHost);

	// print output
	for (int k = 0; k < cd.f; k++) {
		for (int j = 0; j < cd.oy; j++) {
			for (int i = 0; i < cd.ox; i++) {
				printf("%d ", output[k*cd.ox*cd.oy + i*cd.oy + j]);
			}
			printf("\n");
		}
		printf("\n");
	}

	cudaFree(d_neuron);
	cudaFree(d_synapse);
	cudaFree(d_output);

	return 0;
}

	.file	"tmpxft_00315cc5_00000000-6_clc.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2030:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z40__device_stub__Z7CLCTestPiS_S_9conv_dataPiS_S_R9conv_data
	.type	_Z40__device_stub__Z7CLCTestPiS_S_9conv_dataPiS_S_R9conv_data, @function
_Z40__device_stub__Z7CLCTestPiS_S_9conv_dataPiS_S_R9conv_data:
.LFB2052:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movq	%rcx, 128(%rsp)
	leaq	48(%rsp), %rcx
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movl	$1, 64(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z7CLCTestPiS_S_9conv_data(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L2:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2052:
	.size	_Z40__device_stub__Z7CLCTestPiS_S_9conv_dataPiS_S_R9conv_data, .-_Z40__device_stub__Z7CLCTestPiS_S_9conv_dataPiS_S_R9conv_data
	.globl	_Z7CLCTestPiS_S_9conv_data
	.type	_Z7CLCTestPiS_S_9conv_data, @function
_Z7CLCTestPiS_S_9conv_data:
.LFB2053:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	16(%rsp), %rcx
	call	_Z40__device_stub__Z7CLCTestPiS_S_9conv_dataPiS_S_R9conv_data
	popq	%rdx
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2053:
	.size	_Z7CLCTestPiS_S_9conv_data, .-_Z7CLCTestPiS_S_9conv_data
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"r"
.LC1:
	.string	"input"
.LC2:
	.string	"%d"
.LC3:
	.string	"%d "
.LC4:
	.string	"\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register 6
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$232, %rsp
	.cfi_offset 15, -24
	.cfi_offset 14, -32
	.cfi_offset 13, -40
	.cfi_offset 12, -48
	.cfi_offset 3, -56
	movq	%fs:40, %rax
	movq	%rax, -56(%rbp)
	movq	%rsp, %rax
.L10:
	cmpq	%rax, %rsp
	je	.L11
	subq	$4096, %rsp
	orq	$0, 4088(%rsp)
	jmp	.L10
.L11:
	subq	$768, %rsp
	orq	$0, 760(%rsp)
	movq	%rsp, -240(%rbp)
	movq	%rsp, %rax
.L13:
	cmpq	%rax, %rsp
	je	.L14
	subq	$4096, %rsp
	orq	$0, 4088(%rsp)
	jmp	.L13
.L14:
	subq	$384, %rsp
	orq	$0, 376(%rsp)
	xorl	%eax, %eax
	movl	$18, %ecx
	leaq	.LC0(%rip), %rsi
	xorl	%r15d, %r15d
	leaq	-128(%rbp), %rbx
	movq	%rsp, -248(%rbp)
	movq	%rbx, %rdi
	rep stosl
	leaq	.LC1(%rip), %rdi
	call	fopen@PLT
	movq	%rax, -232(%rbp)
.L16:
	movq	-240(%rbp), %rax
	xorl	%r13d, %r13d
	leaq	(%rax,%r15,4), %r14
.L20:
	movq	%r14, %rdx
	movl	$8, %r12d
.L17:
	movq	-232(%rbp), %rdi
	leaq	.LC2(%rip), %rsi
	xorl	%eax, %eax
	movq	%rdx, -256(%rbp)
	call	__isoc23_fscanf@PLT
	movq	-256(%rbp), %rdx
	addq	$96, %rdx
	decl	%r12d
	jne	.L17
	addl	$3, %r13d
	addq	$12, %r14
	cmpl	$24, %r13d
	jne	.L20
	incq	%r15
	cmpq	$3, %r15
	jne	.L16
	xorl	%r15d, %r15d
.L19:
	movq	-248(%rbp), %rax
	xorl	%r13d, %r13d
	leaq	(%rax,%r15,4), %r14
.L26:
	xorl	%r11d, %r11d
	movq	%r14, %r10
.L24:
	movq	%r10, %rdx
	movl	$4, %r12d
.L21:
	movq	-232(%rbp), %rdi
	xorl	%eax, %eax
	leaq	.LC2(%rip), %rsi
	movl	%r11d, -268(%rbp)
	movq	%r10, -264(%rbp)
	movq	%rdx, -256(%rbp)
	call	__isoc23_fscanf@PLT
	movq	-256(%rbp), %rdx
	movq	-264(%rbp), %r10
	movl	-268(%rbp), %r11d
	addq	$48, %rdx
	decl	%r12d
	jne	.L21
	addl	$3, %r11d
	addq	$12, %r10
	cmpl	$12, %r11d
	jne	.L24
	incq	%r13
	addq	$4, %r14
	cmpq	$3, %r13
	jne	.L26
	addq	$48, %r15
	cmpq	$96, %r15
	jne	.L19
	movq	-232(%rbp), %rdi
	xorl	%r14d, %r14d
	xorl	%r13d, %r13d
	movabsq	$4294967328, %r15
	call	fclose@PLT
	leaq	-224(%rbp), %rdi
	movl	$768, %esi
	call	cudaMalloc@PLT
	leaq	-216(%rbp), %rdi
	movl	$384, %esi
	call	cudaMalloc@PLT
	leaq	-208(%rbp), %rdi
	movl	$72, %esi
	call	cudaMalloc@PLT
	movl	$1, %ecx
	movl	$768, %edx
	movq	-240(%rbp), %rsi
	movq	-224(%rbp), %rdi
	call	cudaMemcpy@PLT
	movl	$1, %ecx
	movl	$384, %edx
	movq	-248(%rbp), %rsi
	movq	-216(%rbp), %rdi
	call	cudaMemcpy@PLT
	movq	-208(%rbp), %rdi
	movl	$1, %ecx
	movq	%rbx, %rsi
	movl	$72, %edx
	call	cudaMemcpy@PLT
.L28:
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	%r15, %rdx
	movl	$1, %ecx
	movabsq	$4294967297, %rdi
	movl	$1, %esi
	movq	%r15, -184(%rbp)
	movl	$1, -176(%rbp)
	movq	%rdi, -196(%rbp)
	movl	$1, -188(%rbp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L27
	movq	-208(%rbp), %rdx
	movq	-216(%rbp), %rsi
	movabsq	$34359738372, %rax
	leaq	-172(%rbp), %rcx
	movq	%rax, -172(%rbp)
	subq	$2, %rax
	movq	-224(%rbp), %rdi
	movq	%rax, -164(%rbp)
	addq	%r13, %rdx
	addq	%r14, %rsi
	movl	$1610612737, %eax
	movl	$3, -132(%rbp)
	salq	$3, %rax
	movq	%rax, -156(%rbp)
	movabsq	$17179869186, %rax
	movq	%rax, -148(%rbp)
	movl	$3221225473, %eax
	salq	$2, %rax
	movq	%rax, -140(%rbp)
	call	_Z40__device_stub__Z7CLCTestPiS_S_9conv_dataPiS_S_R9conv_data
.L27:
	addq	$192, %r14
	cmpq	$36, %r13
	je	.L41
	movl	$36, %r13d
	jmp	.L28
.L41:
	movq	-208(%rbp), %rsi
	movl	$2, %ecx
	movl	$72, %edx
	movq	%rbx, %rdi
	call	cudaMemcpy@PLT
.L29:
	movq	%rbx, %r14
	xorl	%r13d, %r13d
.L33:
	movq	%r14, %r8
	movl	$3, %r15d
.L30:
	movl	(%r8), %edx
	leaq	.LC3(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	movq	%r8, -232(%rbp)
	call	__printf_chk@PLT
	movq	-232(%rbp), %r8
	addq	$12, %r8
	decl	%r15d
	jne	.L30
	leaq	.LC4(%rip), %rsi
	xorl	%eax, %eax
	incl	%r13d
	addq	$4, %r14
	movl	$2, %edi
	call	__printf_chk@PLT
	cmpl	$3, %r13d
	leaq	.LC4(%rip), %rsi
	jne	.L33
	movl	$2, %edi
	xorl	%eax, %eax
	addl	$9, %r12d
	addq	$36, %rbx
	call	__printf_chk@PLT
	cmpl	$18, %r12d
	jne	.L29
	movq	-224(%rbp), %rdi
	call	cudaFree@PLT
	movq	-216(%rbp), %rdi
	call	cudaFree@PLT
	movq	-208(%rbp), %rdi
	call	cudaFree@PLT
	movq	-56(%rbp), %rax
	subq	%fs:40, %rax
	je	.L34
	call	__stack_chk_fail@PLT
.L34:
	leaq	-40(%rbp), %rsp
	xorl	%eax, %eax
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE2027:
	.size	main, .-main
	.section	.rodata.str1.1
.LC5:
	.string	"_Z7CLCTestPiS_S_9conv_data"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC5(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z7CLCTestPiS_S_9conv_data(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2055:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <stdio.h>
#include <stdlib.h>
#include <stdint.h>
#include <hip/hip_runtime.h>

#define SIZE(A) A*sizeof(int)

// for this method to work, (MULTIPLIER_SIZE <= NUM_MULTIPLIERS) must be true
#define MULTIPLIER_SIZE 32
#define NUM_MULTIPLIERS 32 // arbitrary size

typedef struct {
	int ibits, obits; // bit precision of neurons
	int stride; // filter stride length
	int nx, ny, nz; // input dimensions
	int f; // number of filters
	int sx, sy; // filter dimensions
	int ox, oy; // output dimensions
} conv_data;

__global__ void CLCTest(int *neuron, int *synapse, int *output, conv_data cd) {
	volatile int tid = threadIdx.x;
	int bid = blockIdx.x;
	bool last_block = (cd.ox*cd.oy / NUM_MULTIPLIERS + ((cd.ox*cd.oy) % NUM_MULTIPLIERS != 0) - 1) == bid;

	int window_size = cd.sx*cd.sy*cd.nz;
	int num_windows = cd.ox*cd.oy;

	for (int i = 0; i < window_size/NUM_MULTIPLIERS; i++) {
		volatile int out_neuron;
		volatile int j;

		// send groups of 4 neurons to the operand collector
		for (j = bid*MULTIPLIER_SIZE+3; (j < (bid+1)*MULTIPLIER_SIZE) && (j < num_windows); j += 4) {
			int temp[4];
			for (int k = 0; k < 4; k++) {
				temp[k] = i*NUM_MULTIPLIERS+tid + ((j-3+k)/cd.oy)*cd.ny*cd.nz*cd.stride + ((j-3+k)%cd.oy)*cd.nz*cd.stride;
			}

			asm("/*");
			asm("CPTX_BEGIN");
			asm("clp.s32 %0, %1, %2, %3;" :: "r"(neuron[temp[0]]), "r"(neuron[temp[1]]), "r"(neuron[temp[2]]), "r"(neuron[temp[3]]));
			asm("CPTX_END");
			asm("*/");
		}

		// send the remaining neurons individually to the operand collector
		if (last_block) { // this assumes MULTIPLIER_SIZE % 4 == 0
			j -= 3; // revert the last iteration from previous for loop and add 1
			for (; j < num_windows; j++) {
				asm("/*");
				asm("CPTX_BEGIN");
				asm("clp.s32 %0;" :: "r"(neuron[i+tid + (j/cd.oy)*cd.ny*cd.nz*cd.stride + (j%cd.oy)*cd.nz*cd.stride]));
				asm("CPTX_END");
				asm("*/");
			}
		}

		// compute the result
		asm("/*");
		asm("CPTX_BEGIN");
		asm("clc.s32 %0, %1, %2, %3;" : "=r"(out_neuron) : "r"(synapse[i*NUM_MULTIPLIERS+tid]), "r"(cd.ibits), "r"(cd.obits));
		asm("CPTX_END");
		asm("*/");

		// store the result, making sure the garbage return values are ignored
		if ((!last_block && (tid < MULTIPLIER_SIZE)) || (last_block && (tid < num_windows % MULTIPLIER_SIZE))) {
			output[bid*MULTIPLIER_SIZE + tid] += out_neuron;
		}
	}
}

int main(int argc, char** argv) {
	conv_data cd;
	cd.ibits = 4; cd.obits = 8; cd.stride = 2;
	cd.nx = 8; cd.ny = 8; cd.nz = 3; cd.f = 2;
	cd.sx = 4; cd.sy = 4; cd.ox = 3; cd.oy = 3;
	// ox = (nx-sx)/stride + 1;
	// oy = (ny-sy)/stride + 1;

	int neuron[cd.nx*cd.ny*cd.nz];
	int synapse[cd.f*cd.sx*cd.sy*cd.nz];
	int output[cd.f*cd.ox*cd.oy];
	memset(output, 0, SIZE(cd.ox*cd.oy*cd.f));

	FILE *fp;
	fp = fopen("input", "r");

	// collect neuron data
	for (int k = 0; k < cd.nz; k++) {
		for (int j = 0; j < cd.ny; j++) {
			for (int i = 0; i < cd.nx; i++) {
				fscanf(fp, "%d", &neuron[i*cd.ny*cd.nz + j*cd.nz + k]);
			}
		}
	}
	// collect synapse data
	for (int l = 0; l < cd.f; l++) {
		for (int k = 0; k < cd.nz; k++) {
			for (int j = 0; j < cd.sy; j++) {
				for (int i = 0; i < cd.sx; i++) {
					fscanf(fp, "%d", &synapse[l*cd.sx*cd.sy*cd.nz + i*cd.sy*cd.nz + j*cd.nz + k]);
				}
			}
		}
	}

	fclose(fp);
	
	int *d_neuron, *d_synapse, *d_output;
	hipMalloc(&d_neuron, SIZE(cd.nx*cd.ny*cd.nz));
	hipMalloc(&d_synapse, SIZE(cd.f*cd.sx*cd.sy*cd.nz));
	hipMalloc(&d_output, SIZE(cd.ox*cd.oy*cd.f));
	hipMemcpy(d_neuron, neuron, SIZE(cd.nx*cd.ny*cd.nz), hipMemcpyHostToDevice);
	hipMemcpy(d_synapse, synapse, SIZE(cd.f*cd.sx*cd.sy*cd.nz), hipMemcpyHostToDevice);
	hipMemcpy(d_output, output, SIZE(cd.ox*cd.oy*cd.f), hipMemcpyHostToDevice);

	// one thread block is composed of MULTIPLIER_SIZE windows and NUM_MULTIPLIERS threads
	int blocks = cd.ox*cd.oy / NUM_MULTIPLIERS + ((cd.ox*cd.oy) % NUM_MULTIPLIERS != 0);
	// apply one filter per kernel
	for (int f = 0; f < cd.f; f++) {
		CLCTest<<<blocks, NUM_MULTIPLIERS>>>(d_neuron, d_synapse + f*cd.sx*cd.sy*cd.nz, d_output + f*cd.ox*cd.oy, cd);
	}

	hipMemcpy(output, d_output, SIZE(cd.ox*cd.oy*cd.f), hipMemcpyDeviceToHost);

	// print output
	for (int k = 0; k < cd.f; k++) {
		for (int j = 0; j < cd.oy; j++) {
			for (int i = 0; i < cd.ox; i++) {
				printf("%d ", output[k*cd.ox*cd.oy + i*cd.oy + j]);
			}
			printf("\n");
		}
		printf("\n");
	}

	hipFree(d_neuron);
	hipFree(d_synapse);
	hipFree(d_output);

	return 0;
}

	.text
	.file	"clc.hip"
	.globl	_Z22__device_stub__CLCTestPiS_S_9conv_data # -- Begin function _Z22__device_stub__CLCTestPiS_S_9conv_data
	.type	_Z22__device_stub__CLCTestPiS_S_9conv_data,@function
_Z22__device_stub__CLCTestPiS_S_9conv_data: # @_Z22__device_stub__CLCTestPiS_S_9conv_data
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	160(%rsp), %rax
	movq	%rax, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7CLCTestPiS_S_9conv_data, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z22__device_stub__CLCTestPiS_S_9conv_data, .Lfunc_end0-_Z22__device_stub__CLCTestPiS_S_9conv_data
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst16,"aM",@progbits,16
	.p2align	4, 0x0                          # -- Begin function main
.LCPI1_0:
	.long	4                               # 0x4
	.long	8                               # 0x8
	.long	2                               # 0x2
	.long	8                               # 0x8
.LCPI1_1:
	.long	8                               # 0x8
	.long	3                               # 0x3
	.long	2                               # 0x2
	.long	4                               # 0x4
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$1368, %rsp                     # imm = 0x558
	.cfi_def_cfa_offset 1424
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	xorps	%xmm0, %xmm0
	movaps	%xmm0, 176(%rsp)
	movaps	%xmm0, 160(%rsp)
	movaps	%xmm0, 144(%rsp)
	movaps	%xmm0, 128(%rsp)
	movq	$0, 192(%rsp)
	movl	$.L.str, %edi
	movl	$.L.str.1, %esi
	callq	fopen
	movq	%rax, %rbx
	leaq	592(%rsp), %r14
	xorl	%r15d, %r15d
.LBB1_1:                                # %.preheader122
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB1_2 Depth 2
                                        #       Child Loop BB1_3 Depth 3
	movq	%r14, %r12
	xorl	%r13d, %r13d
.LBB1_2:                                # %.preheader121
                                        #   Parent Loop BB1_1 Depth=1
                                        # =>  This Loop Header: Depth=2
                                        #       Child Loop BB1_3 Depth 3
	xorl	%ebp, %ebp
.LBB1_3:                                #   Parent Loop BB1_1 Depth=1
                                        #     Parent Loop BB1_2 Depth=2
                                        # =>    This Inner Loop Header: Depth=3
	leaq	(%r12,%rbp), %rdx
	movl	$.L.str.2, %esi
	movq	%rbx, %rdi
	xorl	%eax, %eax
	callq	__isoc23_fscanf
	addq	$96, %rbp
	cmpq	$768, %rbp                      # imm = 0x300
	jne	.LBB1_3
# %bb.4:                                #   in Loop: Header=BB1_2 Depth=2
	incq	%r13
	addq	$12, %r12
	cmpq	$8, %r13
	jne	.LBB1_2
# %bb.5:                                #   in Loop: Header=BB1_1 Depth=1
	incq	%r15
	addq	$4, %r14
	cmpq	$3, %r15
	jne	.LBB1_1
# %bb.6:                                # %.preheader119.preheader
	movb	$1, %cl
	xorl	%eax, %eax
.LBB1_7:                                # %.preheader119
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB1_8 Depth 2
                                        #       Child Loop BB1_9 Depth 3
                                        #         Child Loop BB1_10 Depth 4
	movl	%ecx, 60(%rsp)                  # 4-byte Spill
	leaq	(%rsp,%rax,4), %r14
	addq	$208, %r14
	xorl	%r15d, %r15d
.LBB1_8:                                # %.preheader118
                                        #   Parent Loop BB1_7 Depth=1
                                        # =>  This Loop Header: Depth=2
                                        #       Child Loop BB1_9 Depth 3
                                        #         Child Loop BB1_10 Depth 4
	movq	%r14, %r12
	xorl	%r13d, %r13d
.LBB1_9:                                # %.preheader117
                                        #   Parent Loop BB1_7 Depth=1
                                        #     Parent Loop BB1_8 Depth=2
                                        # =>    This Loop Header: Depth=3
                                        #         Child Loop BB1_10 Depth 4
	xorl	%ebp, %ebp
.LBB1_10:                               #   Parent Loop BB1_7 Depth=1
                                        #     Parent Loop BB1_8 Depth=2
                                        #       Parent Loop BB1_9 Depth=3
                                        # =>      This Inner Loop Header: Depth=4
	leaq	(%r12,%rbp), %rdx
	movl	$.L.str.2, %esi
	movq	%rbx, %rdi
	xorl	%eax, %eax
	callq	__isoc23_fscanf
	addq	$48, %rbp
	cmpq	$192, %rbp
	jne	.LBB1_10
# %bb.11:                               #   in Loop: Header=BB1_9 Depth=3
	incq	%r13
	addq	$12, %r12
	cmpq	$4, %r13
	jne	.LBB1_9
# %bb.12:                               #   in Loop: Header=BB1_8 Depth=2
	incq	%r15
	addq	$4, %r14
	cmpq	$3, %r15
	jne	.LBB1_8
# %bb.13:                               #   in Loop: Header=BB1_7 Depth=1
	movl	$48, %eax
	testb	$1, 60(%rsp)                    # 1-byte Folded Reload
	movl	$0, %ecx
	jne	.LBB1_7
# %bb.14:
	movabsq	$4294967297, %r14               # imm = 0x100000001
	movq	%rbx, %rdi
	callq	fclose
	leaq	72(%rsp), %rbx
	movl	$768, %esi                      # imm = 0x300
	movq	%rbx, %rdi
	callq	hipMalloc
	leaq	64(%rsp), %r15
	movl	$384, %esi                      # imm = 0x180
	movq	%r15, %rdi
	callq	hipMalloc
	leaq	48(%rsp), %r12
	movl	$72, %esi
	movq	%r12, %rdi
	callq	hipMalloc
	movq	(%rbx), %rdi
	leaq	592(%rsp), %rsi
	movl	$768, %edx                      # imm = 0x300
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%r15), %rdi
	leaq	208(%rsp), %rsi
	movl	$384, %edx                      # imm = 0x180
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%r12), %rdi
	leaq	128(%rsp), %rsi
	movl	$72, %edx
	movl	$1, %ecx
	callq	hipMemcpy
	movb	$1, %bpl
	xorl	%r12d, %r12d
	leaq	31(%r14), %rbx
	movabsq	$12884901892, %r15              # imm = 0x300000004
.LBB1_15:                               # =>This Inner Loop Header: Depth=1
	movq	%r14, %rdi
	movl	$1, %esi
	movq	%rbx, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_17
# %bb.16:                               #   in Loop: Header=BB1_15 Depth=1
	movq	72(%rsp), %rdi
	leaq	(%r12,%r12,2), %rsi
	shlq	$6, %rsi
	addq	64(%rsp), %rsi
	leaq	(%r12,%r12,8), %rdx
	shlq	$2, %rdx
	addq	48(%rsp), %rdx
	movaps	.LCPI1_0(%rip), %xmm0           # xmm0 = [4,8,2,8]
	movups	%xmm0, 80(%rsp)
	movaps	.LCPI1_1(%rip), %xmm0           # xmm0 = [8,3,2,4]
	movups	%xmm0, 96(%rsp)
	movq	%r15, 112(%rsp)
	movl	$3, 120(%rsp)
	movups	80(%rsp), %xmm0
	movups	96(%rsp), %xmm1
	movups	108(%rsp), %xmm2
	movups	%xmm2, 28(%rsp)
	movups	%xmm1, 16(%rsp)
	movups	%xmm0, (%rsp)
	callq	_Z22__device_stub__CLCTestPiS_S_9conv_data
.LBB1_17:                               #   in Loop: Header=BB1_15 Depth=1
	movl	$1, %r12d
	testb	$1, %bpl
	movl	$0, %ebp
	jne	.LBB1_15
# %bb.18:
	movq	48(%rsp), %rsi
	leaq	128(%rsp), %rdi
	movl	$72, %edx
	movl	$2, %ecx
	callq	hipMemcpy
	movb	$1, %bl
	xorl	%eax, %eax
.LBB1_19:                               # %.preheader116
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB1_20 Depth 2
                                        #       Child Loop BB1_21 Depth 3
	leaq	(%rsp,%rax,4), %r14
	addq	$128, %r14
	xorl	%r15d, %r15d
.LBB1_20:                               # %.preheader
                                        #   Parent Loop BB1_19 Depth=1
                                        # =>  This Loop Header: Depth=2
                                        #       Child Loop BB1_21 Depth 3
	movq	$-36, %r12
.LBB1_21:                               #   Parent Loop BB1_19 Depth=1
                                        #     Parent Loop BB1_20 Depth=2
                                        # =>    This Inner Loop Header: Depth=3
	movl	36(%r14,%r12), %esi
	movl	$.L.str.3, %edi
	xorl	%eax, %eax
	callq	printf
	addq	$12, %r12
	jne	.LBB1_21
# %bb.22:                               #   in Loop: Header=BB1_20 Depth=2
	movl	$10, %edi
	callq	putchar@PLT
	incq	%r15
	addq	$4, %r14
	cmpq	$3, %r15
	jne	.LBB1_20
# %bb.23:                               #   in Loop: Header=BB1_19 Depth=1
	movl	$10, %edi
	callq	putchar@PLT
	movl	$9, %eax
	testb	$1, %bl
	movl	$0, %ebx
	jne	.LBB1_19
# %bb.24:
	movq	72(%rsp), %rdi
	callq	hipFree
	movq	64(%rsp), %rdi
	callq	hipFree
	movq	48(%rsp), %rdi
	callq	hipFree
	xorl	%eax, %eax
	addq	$1368, %rsp                     # imm = 0x558
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	main, .Lfunc_end1-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z7CLCTestPiS_S_9conv_data, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z7CLCTestPiS_S_9conv_data,@object # @_Z7CLCTestPiS_S_9conv_data
	.section	.rodata,"a",@progbits
	.globl	_Z7CLCTestPiS_S_9conv_data
	.p2align	3, 0x0
_Z7CLCTestPiS_S_9conv_data:
	.quad	_Z22__device_stub__CLCTestPiS_S_9conv_data
	.size	_Z7CLCTestPiS_S_9conv_data, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"input"
	.size	.L.str, 6

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"r"
	.size	.L.str.1, 2

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"%d"
	.size	.L.str.2, 3

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"%d "
	.size	.L.str.3, 4

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z7CLCTestPiS_S_9conv_data"
	.size	.L__unnamed_1, 27

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z22__device_stub__CLCTestPiS_S_9conv_data
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z7CLCTestPiS_S_9conv_data
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z7CLCTestPiS_S_9conv_data ; -- Begin function _Z7CLCTestPiS_S_9conv_data
	.globl	_Z7CLCTestPiS_S_9conv_data
	.p2align	8
	.type	_Z7CLCTestPiS_S_9conv_data,@function
_Z7CLCTestPiS_S_9conv_data:             ; @_Z7CLCTestPiS_S_9conv_data
; %bb.0:
	s_clause 0x1
	s_load_b64 s[2:3], s[0:1], 0x28
	s_load_b128 s[4:7], s[0:1], 0x34
	s_mov_b64 s[12:13], src_private_base
	s_mov_b32 s12, 4
	s_add_u32 s8, s0, 24
	v_dual_mov_b32 v1, s12 :: v_dual_mov_b32 v2, s13
	s_addc_u32 s9, s1, 0
	flat_store_b32 v[1:2], v0 dlc
	s_waitcnt_vscnt null, 0x0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s14, s4, s3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s14, s14, s5
	s_cmp_lt_i32 s14, 32
	s_cbranch_scc1 .LBB0_23
; %bb.1:                                ; %.lr.ph86
	s_mul_i32 s18, s7, s6
	s_mov_b32 s24, 0
	s_ashr_i32 s4, s18, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshr_b32 s4, s4, 27
	s_add_i32 s4, s18, s4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_and_b32 s5, s4, 0xffffffe0
	s_ashr_i32 s4, s4, 5
	s_sub_i32 s19, s18, s5
	s_cmp_lg_u32 s19, 0
	s_cselect_b32 s5, -1, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_cmp_lg_u32 s5, 0
	s_addc_u32 s4, s4, -1
	s_cmp_eq_u32 s4, s15
	s_cselect_b32 s20, -1, 0
	s_cmp_lg_u32 s4, s15
	s_cselect_b32 s21, -1, 0
	s_ashr_i32 s22, s7, 31
	s_lshl_b32 s25, s15, 5
	s_add_i32 s4, s7, s22
	s_add_i32 s26, s25, 32
	s_xor_b32 s23, s4, s22
	s_load_b128 s[4:7], s[8:9], 0x0
	v_cvt_f32_u32_e32 v0, s23
	s_clause 0x1
	s_load_b128 s[8:11], s[0:1], 0x0
	s_load_b64 s[16:17], s[0:1], 0x10
	s_mov_b32 s0, 12
	s_mov_b32 s1, s13
	s_waitcnt lgkmcnt(0)
	s_sub_i32 s7, 0, s23
	v_rcp_iflag_f32_e32 v0, v0
	s_waitcnt_depctr 0xfff
	v_dual_mov_b32 v5, s1 :: v_dual_mul_f32 v0, 0x4f7ffffe, v0
	s_mul_i32 s3, s3, s6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v0, v0
	s_mov_b32 s6, 8
	v_mul_lo_u32 v1, s7, v0
	s_mov_b32 s7, s13
	s_delay_alu instid0(VALU_DEP_1)
	v_mul_hi_u32 v1, v0, v1
	v_mov_b32_e32 v4, s0
	s_ashr_i32 s0, s14, 31
	s_or_b32 s1, s25, 3
	s_lshr_b32 s0, s0, 27
	v_mov_b32_e32 v6, s1
	s_add_i32 s14, s14, s0
	s_delay_alu instid0(VALU_DEP_3)
	v_add_nc_u32_e32 v7, v0, v1
	s_ashr_i32 s27, s14, 5
                                        ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3
.LBB0_2:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_4 Depth 2
                                        ;       Child Loop BB0_6 Depth 3
                                        ;     Child Loop BB0_13 Depth 2
	flat_store_b32 v[4:5], v6 dlc
	s_waitcnt_vscnt null, 0x0
	s_waitcnt lgkmcnt(1)
	flat_load_b32 v8, v[4:5] glc dlc
	s_waitcnt vmcnt(0)
	s_mov_b32 s28, exec_lo
	s_waitcnt lgkmcnt(0)
	v_cmpx_gt_i32_e64 s26, v8
	s_cbranch_execz .LBB0_10
; %bb.3:                                ; %.lr.ph
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_lshl_b32 s30, s24, 5
	s_mov_b32 s29, 0
                                        ; implicit-def: $sgpr31
.LBB0_4:                                ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB0_6 Depth 3
	flat_load_b32 v8, v[4:5] glc dlc
	s_waitcnt vmcnt(0)
	s_or_b32 s31, s31, exec_lo
	s_mov_b32 s33, exec_lo
	s_waitcnt lgkmcnt(0)
	v_cmpx_gt_i32_e64 s18, v8
	s_cbranch_execz .LBB0_8
; %bb.5:                                ; %.preheader.preheader
                                        ;   in Loop: Header=BB0_4 Depth=2
	s_mov_b64 s[14:15], 0
.LBB0_6:                                ; %.preheader
                                        ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_4 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	v_dual_mov_b32 v8, s12 :: v_dual_mov_b32 v9, s13
	s_cmp_eq_u32 s14, 3
	flat_load_b32 v11, v[8:9] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v8, v[4:5] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v9, v[4:5] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(1)
	v_add3_u32 v12, s14, v8, -3
	s_waitcnt lgkmcnt(0)
	v_add3_u32 v10, s14, v9, -3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v12, 31, v12
	v_ashrrev_i32_e32 v10, 31, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v8, v8, v12
	v_xor_b32_e32 v13, s22, v12
	v_add3_u32 v8, s14, v8, -3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v8, v8, v12
	v_mul_hi_u32 v14, v8, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v15, v14, s23
	v_add_nc_u32_e32 v16, 1, v14
	v_sub_nc_u32_e32 v8, v8, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_cmp_le_u32_e32 vcc_lo, s23, v8
	v_add_nc_u32_e32 v9, v9, v10
	v_subrev_nc_u32_e32 v15, s23, v8
	v_cndmask_b32_e32 v14, v14, v16, vcc_lo
	v_add3_u32 v9, s14, v9, -3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v8, v8, v15, vcc_lo
	v_xor_b32_e32 v9, v9, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_le_u32_e32 vcc_lo, s23, v8
	v_mul_hi_u32 v12, v9, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v12, v12, s23
	v_sub_nc_u32_e32 v9, v9, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_subrev_nc_u32_e32 v12, s23, v9
	v_cmp_le_u32_e64 s0, s23, v9
	v_cndmask_b32_e64 v9, v9, v12, s0
	v_add_nc_u32_e32 v12, 1, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v15, s23, v9
	v_cndmask_b32_e32 v8, v14, v12, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s23, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v8, v8, v13
	v_cndmask_b32_e32 v9, v9, v15, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s14, 2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v12, v8, v13
	v_xor_b32_e32 v9, v9, v10
	s_cselect_b32 s0, -1, 0
	s_cmp_eq_u32 s14, 1
	s_cselect_b32 s1, -1, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v8, v9, v10
	s_cmp_eq_u32 s14, 0
	v_mad_u64_u32 v[9:10], null, v12, s2, v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v8, s3, v9
	v_add3_u32 v8, v11, s30, v8
	s_delay_alu instid0(VALU_DEP_1)
	v_cndmask_b32_e32 v3, v3, v8, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	v_cndmask_b32_e64 v2, v2, v8, s0
	v_cndmask_b32_e64 v1, v1, v8, s1
	v_cndmask_b32_e32 v0, v0, v8, vcc_lo
	s_add_u32 s14, s14, 1
	s_addc_u32 s15, s15, 0
	s_cmp_eq_u32 s14, 4
	s_cbranch_scc0 .LBB0_6
; %bb.7:                                ;   in Loop: Header=BB0_4 Depth=2
	v_ashrrev_i32_e32 v9, 31, v0
	v_mov_b32_e32 v8, v0
	v_ashrrev_i32_e32 v11, 31, v1
	v_mov_b32_e32 v10, v1
	v_ashrrev_i32_e32 v13, 31, v2
	v_mov_b32_e32 v12, v2
	v_lshlrev_b64 v[8:9], 2, v[8:9]
	v_ashrrev_i32_e32 v15, 31, v3
	v_lshlrev_b64 v[10:11], 2, v[10:11]
	v_mov_b32_e32 v14, v3
	v_lshlrev_b64 v[12:13], 2, v[12:13]
	;;#ASMSTART
	/*
	;;#ASMEND
	v_add_co_u32 v8, vcc_lo, s8, v8
	v_add_co_ci_u32_e32 v9, vcc_lo, s9, v9, vcc_lo
	v_add_co_u32 v10, vcc_lo, s8, v10
	v_lshlrev_b64 v[14:15], 2, v[14:15]
	v_add_co_ci_u32_e32 v11, vcc_lo, s9, v11, vcc_lo
	v_add_co_u32 v12, vcc_lo, s8, v12
	v_add_co_ci_u32_e32 v13, vcc_lo, s9, v13, vcc_lo
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_u32 v14, vcc_lo, s8, v14
	v_add_co_ci_u32_e32 v15, vcc_lo, s9, v15, vcc_lo
	;;#ASMSTART
	CPTX_BEGIN
	;;#ASMEND
	s_clause 0x3
	global_load_b32 v8, v[8:9], off
	global_load_b32 v9, v[10:11], off
	global_load_b32 v10, v[12:13], off
	global_load_b32 v11, v[14:15], off
	s_and_not1_b32 s0, s31, exec_lo
	s_waitcnt vmcnt(0)
	;;#ASMSTART
	clp.s32 v8, v9, v10, v11;
	;;#ASMEND
	;;#ASMSTART
	CPTX_END
	;;#ASMEND
	;;#ASMSTART
	*/
	;;#ASMEND
	flat_load_b32 v8, v[4:5] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_nc_u32_e32 v8, 4, v8
	flat_store_b32 v[4:5], v8 dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b32 v8, v[4:5] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_cmp_le_i32_e32 vcc_lo, s26, v8
	s_and_b32 s1, vcc_lo, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s31, s0, s1
.LBB0_8:                                ; %Flow114
                                        ;   in Loop: Header=BB0_4 Depth=2
	s_or_b32 exec_lo, exec_lo, s33
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, exec_lo, s31
	s_or_b32 s29, s0, s29
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s29
	s_cbranch_execnz .LBB0_4
; %bb.9:                                ; %Flow115
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s29
.LBB0_10:                               ; %Flow116
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s28
	s_and_not1_b32 vcc_lo, exec_lo, s20
	s_cbranch_vccnz .LBB0_15
; %bb.11:                               ;   in Loop: Header=BB0_2 Depth=1
	flat_load_b32 v8, v[4:5] glc dlc
	s_waitcnt vmcnt(0)
	s_mov_b32 s1, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v8, -3, v8
	flat_store_b32 v[4:5], v8 dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b32 v8, v[4:5] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_cmpx_gt_i32_e64 s18, v8
	s_cbranch_execz .LBB0_14
; %bb.12:                               ; %.lr.ph82.preheader
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_mov_b32 s14, 0
.LBB0_13:                               ; %.lr.ph82
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_dual_mov_b32 v8, s12 :: v_dual_mov_b32 v9, s13
	;;#ASMSTART
	/*
	;;#ASMEND
	;;#ASMSTART
	CPTX_BEGIN
	;;#ASMEND
	flat_load_b32 v11, v[8:9] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v8, v[4:5] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v9, v[4:5] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(1)
	v_ashrrev_i32_e32 v12, 31, v8
	s_waitcnt lgkmcnt(0)
	v_ashrrev_i32_e32 v10, 31, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v8, v8, v12
	v_xor_b32_e32 v8, v8, v12
	v_xor_b32_e32 v12, s22, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v14, v8, v7
	v_mul_lo_u32 v15, v14, s23
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v8, v8, v15
	v_subrev_nc_u32_e32 v16, s23, v8
	v_cmp_le_u32_e32 vcc_lo, s23, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_cndmask_b32 v8, v8, v16 :: v_dual_add_nc_u32 v9, v9, v10
	v_xor_b32_e32 v9, v9, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v13, v9, v7
	v_mul_lo_u32 v13, v13, s23
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v9, v9, v13
	v_add_nc_u32_e32 v13, 1, v14
	v_subrev_nc_u32_e32 v15, s23, v9
	v_cmp_le_u32_e64 s0, s23, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v13, v14, v13, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s23, v8
	v_cndmask_b32_e64 v9, v9, v15, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_subrev_nc_u32_e32 v15, s23, v9
	v_add_nc_u32_e32 v14, 1, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v8, v13, v14, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s23, v9
	v_xor_b32_e32 v8, v8, v12
	v_cndmask_b32_e32 v9, v9, v15, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v12, v8, v12
	v_xor_b32_e32 v9, v9, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v8, v9, v10
	v_mad_u64_u32 v[9:10], null, v12, s2, v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v8, s3, v9
	v_add3_u32 v8, v11, s24, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v9, 31, v8
	v_lshlrev_b64 v[8:9], 2, v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v8, vcc_lo, s8, v8
	v_add_co_ci_u32_e32 v9, vcc_lo, s9, v9, vcc_lo
	global_load_b32 v8, v[8:9], off
	s_waitcnt vmcnt(0)
	;;#ASMSTART
	clp.s32 v8;
	;;#ASMEND
	;;#ASMSTART
	CPTX_END
	;;#ASMEND
	;;#ASMSTART
	*/
	;;#ASMEND
	flat_load_b32 v8, v[4:5] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_nc_u32_e32 v8, 1, v8
	flat_store_b32 v[4:5], v8 dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b32 v8, v[4:5] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_cmp_le_i32_e32 vcc_lo, s18, v8
	s_or_b32 s14, vcc_lo, s14
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s14
	s_cbranch_execnz .LBB0_13
.LBB0_14:                               ; %Flow112
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
.LBB0_15:                               ; %.loopexit
                                        ;   in Loop: Header=BB0_2 Depth=1
	v_dual_mov_b32 v8, s12 :: v_dual_mov_b32 v9, s13
	;;#ASMSTART
	/*
	;;#ASMEND
	;;#ASMSTART
	CPTX_BEGIN
	;;#ASMEND
	flat_load_b32 v10, v[8:9] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_lshl_add_u32 v10, s24, 5, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v11, 31, v10
	v_lshlrev_b64 v[10:11], 2, v[10:11]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v10, vcc_lo, s10, v10
	v_add_co_ci_u32_e32 v11, vcc_lo, s11, v11, vcc_lo
	s_and_not1_b32 vcc_lo, exec_lo, s21
	global_load_b32 v12, v[10:11], off
	v_dual_mov_b32 v11, s7 :: v_dual_mov_b32 v10, s6
	s_waitcnt vmcnt(0)
	;;#ASMSTART
	clc.s32 s0, v12, s4, s5;
	;;#ASMEND
	v_mov_b32_e32 v12, s0
	flat_store_b32 v[10:11], v12 dlc
	s_waitcnt_vscnt null, 0x0
	;;#ASMSTART
	CPTX_END
	;;#ASMEND
	;;#ASMSTART
	*/
	;;#ASMEND
	flat_load_b32 v8, v[8:9] glc dlc
	s_waitcnt vmcnt(0)
	s_cbranch_vccnz .LBB0_17
; %bb.16:                               ;   in Loop: Header=BB0_2 Depth=1
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_i32_e32 vcc_lo, 32, v8
	s_mov_b32 s1, 0
	s_and_b32 s0, vcc_lo, exec_lo
	s_branch .LBB0_18
.LBB0_17:                               ;   in Loop: Header=BB0_2 Depth=1
	s_mov_b32 s1, -1
	s_mov_b32 s0, 0
.LBB0_18:                               ; %Flow
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB0_20
; %bb.19:                               ; %.critedge67
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_i32_e32 vcc_lo, s19, v8
	s_and_not1_b32 s0, s0, exec_lo
	s_and_b32 s1, vcc_lo, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s0, s0, s1
.LBB0_20:                               ; %Flow109
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_22
; %bb.21:                               ;   in Loop: Header=BB0_2 Depth=1
	s_waitcnt lgkmcnt(0)
	v_dual_mov_b32 v9, s7 :: v_dual_mov_b32 v8, s6
	v_dual_mov_b32 v10, s12 :: v_dual_mov_b32 v11, s13
	flat_load_b32 v12, v[8:9] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v8, v[10:11] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_nc_u32_e32 v8, s25, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v9, 31, v8
	v_lshlrev_b64 v[8:9], 2, v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v8, vcc_lo, s16, v8
	v_add_co_ci_u32_e32 v9, vcc_lo, s17, v9, vcc_lo
	global_load_b32 v10, v[8:9], off
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v10, v10, v12
	global_store_b32 v[8:9], v10, off
.LBB0_22:                               ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_add_i32 s24, s24, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s24, s27
	s_cbranch_scc0 .LBB0_2
.LBB0_23:                               ; %._crit_edge
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7CLCTestPiS_S_9conv_data
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 16
		.amdhsa_kernarg_size 68
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 1
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 17
		.amdhsa_next_free_sgpr 34
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z7CLCTestPiS_S_9conv_data, .Lfunc_end0-_Z7CLCTestPiS_S_9conv_data
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 2132
; NumSgprs: 36
; NumVgprs: 17
; ScratchSize: 16
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 4
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 36
; NumVGPRsForWavesPerEU: 17
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 1
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           44
        .value_kind:     by_value
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 68
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z7CLCTestPiS_S_9conv_data
    .private_segment_fixed_size: 16
    .sgpr_count:     36
    .sgpr_spill_count: 0
    .symbol:         _Z7CLCTestPiS_S_9conv_data.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     17
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
