#include <stdio.h>
#include <stdlib.h>

#define _size 3	//Define size of matrix to be 3 by 3;
//__shared__ int result[_size*_size];
__global__ void multiply(int *result, int *A, int *B)
{
	/* OLD logic
	We have a 3 by 3 grid and each block has 3 threads.
	So rows = block x id, cols = block y id
	So Indices will be C[block X id][block Y id] = A[block X id][threads 0, 1, 2] * B[threads 0, 1, 2][block y id]
	*/
	//__shared__ int result[_size*_size] ;
	/*result[blockIdx.x*blockDim.x +blockIdx.y] += A[blockIdx.x*blockDim.x + threadIdx.x]*B[blockDim.x*threadIdx.x+blockIdx.y];
	printf("C[%d] = A[%d]*B[%d] = %d*%d\n",blockIdx.x*blockDim.x +blockIdx.y, blockIdx.x*blockDim.x + threadIdx.x, blockDim.x*threadIdx.x+blockIdx.y,
		A[blockIdx.x*blockDim.x + threadIdx.x],B[blockDim.x*threadIdx.x+blockIdx.y]);
	Res[blockIdx.x*blockDim.x +blockIdx.y]= result[blockIdx.x*blockDim.x +blockIdx.y];*/
	
	/* NEW logic
	I have 3 blocks and 3 threads. Each thread calculates entry for each position compared to the old one having each thread multiplying one value.
	So indices will be result[block x id][thread id] = A[block x id][i]* B[i][thread x id] 
	*/

	for(int i=0; i<_size;i++)
	{
		result[blockIdx.x*blockDim.x +threadIdx.x] += A[blockIdx.x*blockDim.x+i]*B[blockDim.x*i+threadIdx.x];
	}
}

int main(int argc, char const *argv[])
{
	int *d_c,*d_a,*d_b;
	int size = _size*sizeof(int)*_size;
	int *a = reinterpret_cast<int*>(malloc(size));
	int *b = reinterpret_cast<int*>(malloc(size));
	//*result = reinterpret_cast<int*>(malloc(size));
	int *c = reinterpret_cast<int*>(malloc(size));
	//Getting Matrix A
	printf("Enter matrix A\n");
	for (int i = 0; i < _size; ++i)
	{
		for (int j = 0; j < _size; ++j)
		{
			scanf("%d",&*(a+i*_size+j) );
		}
	}
	//Printing matrix A
	printf("A is: \n");
	for (int i = 0; i < _size; ++i)
	{
		for (int j = 0; j < _size; ++j)
		{
			printf("%d ",*(a+i*_size+j) );
		}
		printf("\n");
	}
	//Gtting matrix B
	printf("Enter matrix B\n");
	for (int i = 0; i < _size; ++i)
	{
		for (int j = 0; j < _size; ++j)
		{
			scanf("%d",&*(b+i*_size+j));
		}
	}
	//Printing matrix B
	printf("B is: \n");
	for (int i = 0; i < _size; ++i)
	{
		for (int j = 0; j < _size; ++j)
		{
			printf("%d ",*(b+i*_size+j) );
		}
		printf("\n");
	}
	memset(c,0,size);
	cudaMalloc((void **)&d_a,size);
	cudaMalloc((void **)&d_b,size);
	cudaMalloc((void **)&d_c,size);
	cudaMemcpy(d_a,a,size,cudaMemcpyHostToDevice);
	cudaMemcpy(d_b,b,size,cudaMemcpyHostToDevice);
	cudaMemcpy(d_c,c,size,cudaMemcpyHostToDevice);
	multiply<<<_size,_size>>>(d_c,d_a,d_b);
	cudaThreadSynchronize();
	cudaMemcpy(c,d_c,size,cudaMemcpyDeviceToHost);
	printf("C is: \n");
	for (int i = 0; i < _size; ++i)
	{
		for (int j = 0; j < _size; ++j)
		{
			printf("%d ",*(c+i*_size+j) );
		}
		printf("\n");
	}
	return 0;
}
	.file	"tmpxft_0020975f_00000000-6_2DmatrixMul.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2030:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z31__device_stub__Z8multiplyPiS_S_PiS_S_
	.type	_Z31__device_stub__Z8multiplyPiS_S_PiS_S_, @function
_Z31__device_stub__Z8multiplyPiS_S_PiS_S_:
.LFB2052:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z8multiplyPiS_S_(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L2:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2052:
	.size	_Z31__device_stub__Z8multiplyPiS_S_PiS_S_, .-_Z31__device_stub__Z8multiplyPiS_S_PiS_S_
	.globl	_Z8multiplyPiS_S_
	.type	_Z8multiplyPiS_S_, @function
_Z8multiplyPiS_S_:
.LFB2053:
	.cfi_startproc
	endbr64
	jmp	_Z31__device_stub__Z8multiplyPiS_S_PiS_S_
	.cfi_endproc
.LFE2053:
	.size	_Z8multiplyPiS_S_, .-_Z8multiplyPiS_S_
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"Enter matrix A\n"
.LC1:
	.string	"%d"
.LC2:
	.string	"A is: \n"
.LC3:
	.string	"%d "
.LC4:
	.string	"\n"
.LC5:
	.string	"Enter matrix B\n"
.LC6:
	.string	"B is: \n"
.LC7:
	.string	"C is: \n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movl	$36, %edi
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	xorl	%r13d, %r13d
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$72, %rsp
	.cfi_def_cfa_offset 128
	movq	%fs:40, %rax
	movq	%rax, 56(%rsp)
	xorl	%eax, %eax
	call	malloc@PLT
	movl	$36, %edi
	movq	%rax, %r12
	call	malloc@PLT
	movl	$36, %edi
	movq	%rax, %rbp
	call	malloc@PLT
	leaq	.LC0(%rip), %rsi
	movl	$2, %edi
	movq	%rax, %rbx
	xorl	%eax, %eax
	call	__printf_chk@PLT
.L9:
	leaq	(%r12,%r13,4), %r15
	movl	$3, %r14d
.L10:
	movq	%r15, %rsi
	leaq	.LC1(%rip), %rdi
	xorl	%eax, %eax
	addq	$4, %r15
	call	__isoc23_scanf@PLT
	decl	%r14d
	jne	.L10
	addq	$3, %r13
	cmpq	$9, %r13
	jne	.L9
	leaq	.LC2(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	xorl	%r13d, %r13d
	call	__printf_chk@PLT
.L12:
	leaq	(%r12,%r13,4), %r15
	xorl	%r14d, %r14d
.L13:
	movl	(%r15,%r14,4), %edx
	leaq	.LC3(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	incq	%r14
	call	__printf_chk@PLT
	cmpq	$3, %r14
	jne	.L13
	leaq	.LC4(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	addq	$3, %r13
	call	__printf_chk@PLT
	cmpq	$9, %r13
	jne	.L12
	leaq	.LC5(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	xorl	%r13d, %r13d
	call	__printf_chk@PLT
.L15:
	leaq	0(%rbp,%r13,4), %r15
	movl	$3, %r14d
.L16:
	movq	%r15, %rsi
	leaq	.LC1(%rip), %rdi
	xorl	%eax, %eax
	addq	$4, %r15
	call	__isoc23_scanf@PLT
	decl	%r14d
	jne	.L16
	addq	$3, %r13
	cmpq	$9, %r13
	jne	.L15
	leaq	.LC6(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	xorl	%r13d, %r13d
	call	__printf_chk@PLT
.L18:
	leaq	0(%rbp,%r13,4), %r14
	xorl	%r15d, %r15d
.L19:
	movl	(%r14,%r15,4), %edx
	leaq	.LC3(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	incq	%r15
	call	__printf_chk@PLT
	cmpq	$3, %r15
	jne	.L19
	leaq	.LC4(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	addq	$3, %r13
	call	__printf_chk@PLT
	cmpq	$9, %r13
	jne	.L18
	xorl	%eax, %eax
	movq	%rbx, %rdi
	movq	%r13, %rcx
	movl	$36, %esi
	rep stosl
	leaq	16(%rsp), %rdi
	call	cudaMalloc@PLT
	leaq	24(%rsp), %rdi
	movl	$36, %esi
	call	cudaMalloc@PLT
	leaq	8(%rsp), %rdi
	movl	$36, %esi
	call	cudaMalloc@PLT
	movq	16(%rsp), %rdi
	movl	$1, %ecx
	movq	%r12, %rsi
	movl	$36, %edx
	call	cudaMemcpy@PLT
	movq	24(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbp, %rsi
	movl	$36, %edx
	call	cudaMemcpy@PLT
	movq	8(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbx, %rsi
	movl	$36, %edx
	call	cudaMemcpy@PLT
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$1, %ecx
	movabsq	$4294967299, %rdi
	movl	$1, %esi
	movq	%rdi, %rdx
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L21
	movq	24(%rsp), %rdx
	movq	16(%rsp), %rsi
	movq	8(%rsp), %rdi
	call	_Z31__device_stub__Z8multiplyPiS_S_PiS_S_
.L21:
	call	cudaThreadSynchronize@PLT
	movq	8(%rsp), %rsi
	movq	%rbx, %rdi
	xorl	%r12d, %r12d
	movl	$2, %ecx
	movl	$36, %edx
	call	cudaMemcpy@PLT
	leaq	.LC7(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
.L22:
	leaq	(%rbx,%r12,4), %r13
	xorl	%ebp, %ebp
.L23:
	movl	0(%r13,%rbp,4), %edx
	leaq	.LC3(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	incq	%rbp
	call	__printf_chk@PLT
	cmpq	$3, %rbp
	jne	.L23
	leaq	.LC4(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	addq	$3, %r12
	call	__printf_chk@PLT
	cmpq	$9, %r12
	jne	.L22
	movq	56(%rsp), %rax
	subq	%fs:40, %rax
	je	.L25
	call	__stack_chk_fail@PLT
.L25:
	addq	$72, %rsp
	.cfi_def_cfa_offset 56
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2027:
	.size	main, .-main
	.section	.rodata.str1.1
.LC8:
	.string	"_Z8multiplyPiS_S_"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC8(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z8multiplyPiS_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2055:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>

#define _size 3	//Define size of matrix to be 3 by 3;
//__shared__ int result[_size*_size];
__global__ void multiply(int *result, int *A, int *B)
{
	/* OLD logic
	We have a 3 by 3 grid and each block has 3 threads.
	So rows = block x id, cols = block y id
	So Indices will be C[block X id][block Y id] = A[block X id][threads 0, 1, 2] * B[threads 0, 1, 2][block y id]
	*/
	//__shared__ int result[_size*_size] ;
	/*result[blockIdx.x*blockDim.x +blockIdx.y] += A[blockIdx.x*blockDim.x + threadIdx.x]*B[blockDim.x*threadIdx.x+blockIdx.y];
	printf("C[%d] = A[%d]*B[%d] = %d*%d\n",blockIdx.x*blockDim.x +blockIdx.y, blockIdx.x*blockDim.x + threadIdx.x, blockDim.x*threadIdx.x+blockIdx.y,
		A[blockIdx.x*blockDim.x + threadIdx.x],B[blockDim.x*threadIdx.x+blockIdx.y]);
	Res[blockIdx.x*blockDim.x +blockIdx.y]= result[blockIdx.x*blockDim.x +blockIdx.y];*/
	
	/* NEW logic
	I have 3 blocks and 3 threads. Each thread calculates entry for each position compared to the old one having each thread multiplying one value.
	So indices will be result[block x id][thread id] = A[block x id][i]* B[i][thread x id] 
	*/

	for(int i=0; i<_size;i++)
	{
		result[blockIdx.x*blockDim.x +threadIdx.x] += A[blockIdx.x*blockDim.x+i]*B[blockDim.x*i+threadIdx.x];
	}
}

int main(int argc, char const *argv[])
{
	int *d_c,*d_a,*d_b;
	int size = _size*sizeof(int)*_size;
	int *a = reinterpret_cast<int*>(malloc(size));
	int *b = reinterpret_cast<int*>(malloc(size));
	//*result = reinterpret_cast<int*>(malloc(size));
	int *c = reinterpret_cast<int*>(malloc(size));
	//Getting Matrix A
	printf("Enter matrix A\n");
	for (int i = 0; i < _size; ++i)
	{
		for (int j = 0; j < _size; ++j)
		{
			scanf("%d",&*(a+i*_size+j) );
		}
	}
	//Printing matrix A
	printf("A is: \n");
	for (int i = 0; i < _size; ++i)
	{
		for (int j = 0; j < _size; ++j)
		{
			printf("%d ",*(a+i*_size+j) );
		}
		printf("\n");
	}
	//Gtting matrix B
	printf("Enter matrix B\n");
	for (int i = 0; i < _size; ++i)
	{
		for (int j = 0; j < _size; ++j)
		{
			scanf("%d",&*(b+i*_size+j));
		}
	}
	//Printing matrix B
	printf("B is: \n");
	for (int i = 0; i < _size; ++i)
	{
		for (int j = 0; j < _size; ++j)
		{
			printf("%d ",*(b+i*_size+j) );
		}
		printf("\n");
	}
	memset(c,0,size);
	hipMalloc((void **)&d_a,size);
	hipMalloc((void **)&d_b,size);
	hipMalloc((void **)&d_c,size);
	hipMemcpy(d_a,a,size,hipMemcpyHostToDevice);
	hipMemcpy(d_b,b,size,hipMemcpyHostToDevice);
	hipMemcpy(d_c,c,size,hipMemcpyHostToDevice);
	multiply<<<_size,_size>>>(d_c,d_a,d_b);
	hipDeviceSynchronize();
	hipMemcpy(c,d_c,size,hipMemcpyDeviceToHost);
	printf("C is: \n");
	for (int i = 0; i < _size; ++i)
	{
		for (int j = 0; j < _size; ++j)
		{
			printf("%d ",*(c+i*_size+j) );
		}
		printf("\n");
	}
	return 0;
}
	.text
	.file	"2DmatrixMul.hip"
	.globl	_Z23__device_stub__multiplyPiS_S_ # -- Begin function _Z23__device_stub__multiplyPiS_S_
	.type	_Z23__device_stub__multiplyPiS_S_,@function
_Z23__device_stub__multiplyPiS_S_:      # @_Z23__device_stub__multiplyPiS_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z8multiplyPiS_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z23__device_stub__multiplyPiS_S_, .Lfunc_end0-_Z23__device_stub__multiplyPiS_S_
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$24, %rsp
	.cfi_def_cfa_offset 80
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	$36, %edi
	callq	malloc
	movq	%rax, %r15
	movl	$36, %edi
	callq	malloc
	movq	%rax, %r14
	movl	$36, %edi
	callq	malloc
	movq	%rax, %rbx
	movl	$.Lstr, %edi
	callq	puts@PLT
	movq	%r15, %r12
	xorl	%r13d, %r13d
.LBB1_1:                                # %.preheader74
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB1_2 Depth 2
	xorl	%ebp, %ebp
.LBB1_2:                                #   Parent Loop BB1_1 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	leaq	(%r12,%rbp), %rsi
	movl	$.L.str.1, %edi
	xorl	%eax, %eax
	callq	__isoc23_scanf
	addq	$4, %rbp
	cmpq	$12, %rbp
	jne	.LBB1_2
# %bb.3:                                #   in Loop: Header=BB1_1 Depth=1
	incq	%r13
	addq	$12, %r12
	cmpq	$3, %r13
	jne	.LBB1_1
# %bb.4:
	movl	$.Lstr.1, %edi
	callq	puts@PLT
	movq	%r15, %r12
	xorl	%r13d, %r13d
.LBB1_5:                                # %.preheader73
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB1_6 Depth 2
	xorl	%ebp, %ebp
.LBB1_6:                                #   Parent Loop BB1_5 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movl	(%r12,%rbp,4), %esi
	movl	$.L.str.3, %edi
	xorl	%eax, %eax
	callq	printf
	incq	%rbp
	cmpq	$3, %rbp
	jne	.LBB1_6
# %bb.7:                                #   in Loop: Header=BB1_5 Depth=1
	movl	$10, %edi
	callq	putchar@PLT
	incq	%r13
	addq	$12, %r12
	cmpq	$3, %r13
	jne	.LBB1_5
# %bb.8:
	movl	$.Lstr.2, %edi
	callq	puts@PLT
	movq	%r14, %r12
	xorl	%r13d, %r13d
.LBB1_9:                                # %.preheader72
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB1_10 Depth 2
	xorl	%ebp, %ebp
.LBB1_10:                               #   Parent Loop BB1_9 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	leaq	(%r12,%rbp), %rsi
	movl	$.L.str.1, %edi
	xorl	%eax, %eax
	callq	__isoc23_scanf
	addq	$4, %rbp
	cmpq	$12, %rbp
	jne	.LBB1_10
# %bb.11:                               #   in Loop: Header=BB1_9 Depth=1
	incq	%r13
	addq	$12, %r12
	cmpq	$3, %r13
	jne	.LBB1_9
# %bb.12:
	movl	$.Lstr.3, %edi
	callq	puts@PLT
	movq	%r14, %r12
	xorl	%r13d, %r13d
.LBB1_13:                               # %.preheader71
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB1_14 Depth 2
	xorl	%ebp, %ebp
.LBB1_14:                               #   Parent Loop BB1_13 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movl	(%r12,%rbp,4), %esi
	movl	$.L.str.3, %edi
	xorl	%eax, %eax
	callq	printf
	incq	%rbp
	cmpq	$3, %rbp
	jne	.LBB1_14
# %bb.15:                               #   in Loop: Header=BB1_13 Depth=1
	movl	$10, %edi
	callq	putchar@PLT
	incq	%r13
	addq	$12, %r12
	cmpq	$3, %r13
	jne	.LBB1_13
# %bb.16:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rbx)
	movups	%xmm0, (%rbx)
	movl	$0, 32(%rbx)
	leaq	16(%rsp), %r12
	movl	$36, %esi
	movq	%r12, %rdi
	callq	hipMalloc
	leaq	8(%rsp), %r13
	movl	$36, %esi
	movq	%r13, %rdi
	callq	hipMalloc
	movq	%rsp, %rbp
	movl	$36, %esi
	movq	%rbp, %rdi
	callq	hipMalloc
	movq	(%r12), %rdi
	movl	$36, %edx
	movq	%r15, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%r13), %rdi
	movl	$36, %edx
	movq	%r14, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%rbp), %rdi
	movl	$36, %edx
	movq	%rbx, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movabsq	$4294967299, %rdi               # imm = 0x100000003
	movl	$1, %esi
	movq	%rdi, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_18
# %bb.17:
	movq	(%rsp), %rdi
	movq	16(%rsp), %rsi
	movq	8(%rsp), %rdx
	callq	_Z23__device_stub__multiplyPiS_S_
.LBB1_18:
	callq	hipDeviceSynchronize
	movq	(%rsp), %rsi
	movl	$36, %edx
	movq	%rbx, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movl	$.Lstr.4, %edi
	callq	puts@PLT
	xorl	%r14d, %r14d
.LBB1_19:                               # %.preheader
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB1_20 Depth 2
	xorl	%r15d, %r15d
.LBB1_20:                               #   Parent Loop BB1_19 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movl	(%rbx,%r15,4), %esi
	movl	$.L.str.3, %edi
	xorl	%eax, %eax
	callq	printf
	incq	%r15
	cmpq	$3, %r15
	jne	.LBB1_20
# %bb.21:                               #   in Loop: Header=BB1_19 Depth=1
	movl	$10, %edi
	callq	putchar@PLT
	incq	%r14
	addq	$12, %rbx
	cmpq	$3, %r14
	jne	.LBB1_19
# %bb.22:
	xorl	%eax, %eax
	addq	$24, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	main, .Lfunc_end1-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z8multiplyPiS_S_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z8multiplyPiS_S_,@object       # @_Z8multiplyPiS_S_
	.section	.rodata,"a",@progbits
	.globl	_Z8multiplyPiS_S_
	.p2align	3, 0x0
_Z8multiplyPiS_S_:
	.quad	_Z23__device_stub__multiplyPiS_S_
	.size	_Z8multiplyPiS_S_, 8

	.type	.L.str.1,@object                # @.str.1
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str.1:
	.asciz	"%d"
	.size	.L.str.1, 3

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"%d "
	.size	.L.str.3, 4

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z8multiplyPiS_S_"
	.size	.L__unnamed_1, 18

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.type	.Lstr,@object                   # @str
	.section	.rodata.str1.1,"aMS",@progbits,1
.Lstr:
	.asciz	"Enter matrix A"
	.size	.Lstr, 15

	.type	.Lstr.1,@object                 # @str.1
.Lstr.1:
	.asciz	"A is: "
	.size	.Lstr.1, 7

	.type	.Lstr.2,@object                 # @str.2
.Lstr.2:
	.asciz	"Enter matrix B"
	.size	.Lstr.2, 15

	.type	.Lstr.3,@object                 # @str.3
.Lstr.3:
	.asciz	"B is: "
	.size	.Lstr.3, 7

	.type	.Lstr.4,@object                 # @str.4
.Lstr.4:
	.asciz	"C is: "
	.size	.Lstr.4, 7

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z23__device_stub__multiplyPiS_S_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z8multiplyPiS_S_
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z8multiplyPiS_S_       ; -- Begin function _Z8multiplyPiS_S_
	.globl	_Z8multiplyPiS_S_
	.p2align	8
	.type	_Z8multiplyPiS_S_,@function
_Z8multiplyPiS_S_:                      ; @_Z8multiplyPiS_S_
; %bb.0:
	s_clause 0x2
	s_load_b32 s2, s[0:1], 0x24
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b64 s[0:1], s[0:1], 0x10
	s_waitcnt lgkmcnt(0)
	s_and_b32 s3, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s2, s15, s3
	v_dual_mov_b32 v2, 0 :: v_dual_add_nc_u32 v1, s2, v0
	v_lshlrev_b32_e32 v0, 2, v0
	s_lshl_b32 s3, s3, 2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[3:4], 2, v[1:2]
	v_add_co_u32 v0, s0, s0, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v1, null, s1, 0, s0
	s_mov_b32 s1, 0
	v_add_co_u32 v3, vcc_lo, s4, v3
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
	s_mov_b32 s4, 0
	global_load_b32 v5, v[3:4], off
.LBB0_1:                                ; =>This Inner Loop Header: Depth=1
	s_add_i32 s0, s2, s4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[8:9], s[0:1], 2
	s_add_u32 s8, s6, s8
	s_addc_u32 s9, s7, s9
	global_load_b32 v8, v[0:1], off
	global_load_b32 v9, v2, s[8:9]
	v_add_co_u32 v0, vcc_lo, v0, s3
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
	s_add_i32 s4, s4, 1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	s_cmp_eq_u32 s4, 3
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[6:7], null, v8, v9, v[5:6]
	v_mov_b32_e32 v5, v6
	global_store_b32 v[3:4], v6, off
	s_cbranch_scc0 .LBB0_1
; %bb.2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z8multiplyPiS_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 10
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z8multiplyPiS_S_, .Lfunc_end0-_Z8multiplyPiS_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 228
; NumSgprs: 18
; NumVgprs: 10
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 10
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z8multiplyPiS_S_
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z8multiplyPiS_S_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     10
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
