#include <stdio.h>
#include <math.h>


__global__ void epsilon_of_p_GPU(double *output_arr, double *px_arr, double *py_arr,
                                 double *kxprime_arr, double *kyprime_arr,
                                 double *E_k_n, double *U_k,
                                 double mu, double q, double g, double theta,
                                 int N_kx, int N_ky, int debug)
{
    const int i = threadIdx.x + blockDim.x*blockIdx.x;
    const int j = threadIdx.y + blockDim.y*blockIdx.y;
    const int N_n = 3;
    const int N_l = 3;

    int iprime, jprime, n, l;

    const double px = px_arr[i];
    const double py = py_arr[j];

    double kxprime, kyprime;
    double px_pot, py_pot, potential;
    double evec_element, eigenval;
    double accumulator = 0;

    double pot_trig_terms = pow(cos(theta), 2) - pow(sin(theta), 2)*0;

    const double dpx = px_arr[1] - px_arr[0];
    const double dpy = py_arr[1] - py_arr[0];
    const double prefactor = dpx*dpy/(4*M_PI*M_PI);

    if ((i < N_kx) & (j < N_ky)){
        for (iprime=0; iprime<N_kx; iprime++){
            for (jprime=0; jprime<N_ky; jprime++){
                kxprime = kxprime_arr[iprime];
                kyprime = kyprime_arr[jprime];
                for (n=-1; n<2; n++){
                    px_pot = px - kxprime - n*q;
                    py_pot = py - kyprime;
                    potential = - g*sqrt(px_pot*px_pot + py_pot*py_pot) * pot_trig_terms;
                    for (l=0; l<3; l++){
                        eigenval = E_k_n[N_ky*N_l*iprime + N_l*jprime + l];
                        if (eigenval <= mu){
                            evec_element = U_k[N_ky*N_n*N_l*iprime + N_n*N_l*jprime + N_l*(n+1) + l];
                            // if ((debug > 0) & (i==7) & (j==5) & (iprime==22) & (jprime==33) & (n==0) & (l==0)){
                            //      printf("  epsilon_k[7,5] kprime[22,33] n=0, l=0 (CUDA):\n");
                            //      printf("    px is: %f\n", px);
                            //      printf("    py is: %f\n", py);
                            //      printf("    kxprime is: %f\n", kxprime);
                            //      printf("    kyprime is: %f\n", kyprime);
                            //      printf("    potential terms is %f\n",potential);
                            //      printf("    evec element is %f\n", evec_element);
                            //      printf("    value of term is: %f\n", potential*evec_element*evec_element);
                            //  }
                            accumulator += potential * evec_element*evec_element;
                        }
                    }
                }
            }
        }

        // Multiple the sum by the appropriate prefactor:
        accumulator *= prefactor;

        // Add the kinetic term:
        accumulator += (px*px + py*py);

        output_arr[N_ky*i + j] = accumulator;
        // if ((debug > 0) & (i==7) & (j==5)){
        //     printf("  epsilon_k[7,5] (CUDA): %f\n\n", accumulator);
        // }
    }
}

__global__ void h_of_p_GPU(double *output_arr, double *px_arr, double *py_arr,
                                 double *kxprime_arr, double *kyprime_arr,
                                 double *E_k_n, double *U_k,
                                 double mu, double q, double g, double theta,
                                 int N_kx, int N_ky, int debug)
{
    const int i = threadIdx.x + blockDim.x*blockIdx.x;
    const int j = threadIdx.y + blockDim.y*blockIdx.y;
    const int N_n = 3;
    const int N_l = 3;

    int iprime, jprime, l;

    double px = px_arr[i];
    double py = py_arr[j];

    double kxprime, kyprime;
    double px_pot, py_pot, potential_1, potential_2;
    double evec_element_1, evec_element_2, evec_element_3, eigenval;
    double accumulator = 0;

    double pot_trig_terms = pow(cos(theta), 2) - pow(sin(theta), 2)*0;
    double V_of_q = g*sqrt(q*q) * pot_trig_terms; // V(px=q, py=0)

    const double dpx = px_arr[1] - px_arr[0];
    const double dpy = py_arr[1] - py_arr[0];
    const double prefactor = dpx*dpy/(4*M_PI*M_PI);

    if ((i < N_kx) & (j < N_ky)){
        for (iprime=0; iprime<N_kx; iprime++){
            for (jprime=0; jprime<N_ky; jprime++){
                kxprime = kxprime_arr[iprime];
                kyprime = kyprime_arr[jprime];
                for (l=0; l<3; l++){
                    eigenval = E_k_n[N_ky*N_l*iprime + N_l*jprime + l];
                    if (eigenval <= mu){
                        evec_element_1 = U_k[N_ky*N_n*N_l*iprime + N_n*N_l*jprime + N_l*0 + l];
                        evec_element_2 = U_k[N_ky*N_n*N_l*iprime + N_n*N_l*jprime + N_l*1 + l];
                        evec_element_3 = U_k[N_ky*N_n*N_l*iprime + N_n*N_l*jprime + N_l*2 + l];

                        px_pot = px - kxprime + q;
                        py_pot = py - kyprime;
                        potential_1 = V_of_q - g*sqrt(px_pot*px_pot + py_pot*py_pot) * pot_trig_terms;

                        px_pot = px - kxprime;
                        py_pot = py - kyprime;
                        potential_2 = V_of_q - g*sqrt(px_pot*px_pot + py_pot*py_pot) * pot_trig_terms;

                        accumulator += potential_1 * evec_element_1*evec_element_2 + potential_2 * evec_element_2*evec_element_3;

                        // if ((debug > 0) & (i==7) & (j==5) & (iprime==22) & (jprime==33) & (l==0)){
                             // printf("  h_k[7,5] kprime[22,33], l=0 (CUDA):\n");
                             // printf("    px is: %f\n", px);
                             // printf("    py is: %f\n", py);
                             // printf("    kxprime is: %f\n", kxprime);
                             // printf("    kyprime is: %f\n", kyprime);
                             // printf("    potential term 1 is %f\n", potential_1);
                             // printf("    potential term 2 is %f\n", potential_2);
                             // printf("    value of term is: %f\n",
                             //        potential_1 * evec_element_1*evec_element_2 + potential_2 * evec_element_2*evec_element_3);
                         // }
                    }
                }
            }
        }
        // Multiple the sum by the appropriate prefactor:
        accumulator *= prefactor;

        output_arr[N_ky*i + j] = accumulator;
        // if ((debug > 0) & (i==7) & (j==5)){
        //     printf("  h_k[7,5] (CUDA): %f\n\n", accumulator);
        // }
    }
}

	.file	"tmpxft_00282ab1_00000000-6_cuda_module.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2029:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z55__device_stub__Z16epsilon_of_p_GPUPdS_S_S_S_S_S_ddddiiiPdS_S_S_S_S_S_ddddiii
	.type	_Z55__device_stub__Z16epsilon_of_p_GPUPdS_S_S_S_S_S_ddddiiiPdS_S_S_S_S_S_ddddiii, @function
_Z55__device_stub__Z16epsilon_of_p_GPUPdS_S_S_S_S_S_ddddiiiPdS_S_S_S_S_S_ddddiii:
.LFB2051:
	.cfi_startproc
	endbr64
	subq	$296, %rsp
	.cfi_def_cfa_offset 304
	movq	304(%rsp), %rax
	movq	%rdi, 88(%rsp)
	leaq	120(%rsp), %rdi
	movq	%rsi, 80(%rsp)
	leaq	132(%rsp), %rsi
	movq	%rdx, 72(%rsp)
	leaq	104(%rsp), %rdx
	movq	%rcx, 64(%rsp)
	leaq	112(%rsp), %rcx
	movq	%r8, 56(%rsp)
	movq	%r9, 48(%rsp)
	movq	%rax, 40(%rsp)
	movsd	%xmm0, 32(%rsp)
	movsd	%xmm1, 24(%rsp)
	movsd	%xmm2, 16(%rsp)
	movsd	%xmm3, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 280(%rsp)
	xorl	%eax, %eax
	leaq	88(%rsp), %rax
	movl	$1, 128(%rsp)
	movq	%rax, 168(%rsp)
	leaq	80(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	72(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	64(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	56(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 208(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 216(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 224(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 232(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 240(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 248(%rsp)
	leaq	312(%rsp), %rax
	movq	%rax, 256(%rsp)
	leaq	320(%rsp), %rax
	movq	%rax, 264(%rsp)
	leaq	328(%rsp), %rax
	movq	%rax, 272(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 120(%rsp)
	movq	%rax, 132(%rsp)
	movl	$1, 140(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	112(%rsp)
	.cfi_def_cfa_offset 312
	leaq	_Z16epsilon_of_p_GPUPdS_S_S_S_S_S_ddddiii(%rip), %rdi
	pushq	112(%rsp)
	.cfi_def_cfa_offset 320
	movq	148(%rsp), %rcx
	movl	156(%rsp), %r8d
	movq	136(%rsp), %rsi
	movl	144(%rsp), %edx
	leaq	184(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 312
	popq	%rdx
	.cfi_def_cfa_offset 304
.L2:
	movq	280(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$296, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2051:
	.size	_Z55__device_stub__Z16epsilon_of_p_GPUPdS_S_S_S_S_S_ddddiiiPdS_S_S_S_S_S_ddddiii, .-_Z55__device_stub__Z16epsilon_of_p_GPUPdS_S_S_S_S_S_ddddiiiPdS_S_S_S_S_S_ddddiii
	.globl	_Z16epsilon_of_p_GPUPdS_S_S_S_S_S_ddddiii
	.type	_Z16epsilon_of_p_GPUPdS_S_S_S_S_S_ddddiii, @function
_Z16epsilon_of_p_GPUPdS_S_S_S_S_S_ddddiii:
.LFB2052:
	.cfi_startproc
	endbr64
	jmp	_Z55__device_stub__Z16epsilon_of_p_GPUPdS_S_S_S_S_S_ddddiiiPdS_S_S_S_S_S_ddddiii
	.cfi_endproc
.LFE2052:
	.size	_Z16epsilon_of_p_GPUPdS_S_S_S_S_S_ddddiii, .-_Z16epsilon_of_p_GPUPdS_S_S_S_S_S_ddddiii
	.globl	_Z49__device_stub__Z10h_of_p_GPUPdS_S_S_S_S_S_ddddiiiPdS_S_S_S_S_S_ddddiii
	.type	_Z49__device_stub__Z10h_of_p_GPUPdS_S_S_S_S_S_ddddiiiPdS_S_S_S_S_S_ddddiii, @function
_Z49__device_stub__Z10h_of_p_GPUPdS_S_S_S_S_S_ddddiiiPdS_S_S_S_S_S_ddddiii:
.LFB2053:
	.cfi_startproc
	endbr64
	subq	$296, %rsp
	.cfi_def_cfa_offset 304
	movq	304(%rsp), %rax
	movq	%rdi, 88(%rsp)
	leaq	120(%rsp), %rdi
	movq	%rsi, 80(%rsp)
	leaq	132(%rsp), %rsi
	movq	%rdx, 72(%rsp)
	leaq	104(%rsp), %rdx
	movq	%rcx, 64(%rsp)
	leaq	112(%rsp), %rcx
	movq	%r8, 56(%rsp)
	movq	%r9, 48(%rsp)
	movq	%rax, 40(%rsp)
	movsd	%xmm0, 32(%rsp)
	movsd	%xmm1, 24(%rsp)
	movsd	%xmm2, 16(%rsp)
	movsd	%xmm3, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 280(%rsp)
	xorl	%eax, %eax
	leaq	88(%rsp), %rax
	movl	$1, 128(%rsp)
	movq	%rax, 168(%rsp)
	leaq	80(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	72(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	64(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	56(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 208(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 216(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 224(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 232(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 240(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 248(%rsp)
	leaq	312(%rsp), %rax
	movq	%rax, 256(%rsp)
	leaq	320(%rsp), %rax
	movq	%rax, 264(%rsp)
	leaq	328(%rsp), %rax
	movq	%rax, 272(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 120(%rsp)
	movq	%rax, 132(%rsp)
	movl	$1, 140(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L8
	pushq	112(%rsp)
	.cfi_def_cfa_offset 312
	leaq	_Z10h_of_p_GPUPdS_S_S_S_S_S_ddddiii(%rip), %rdi
	pushq	112(%rsp)
	.cfi_def_cfa_offset 320
	movq	148(%rsp), %rcx
	movl	156(%rsp), %r8d
	movq	136(%rsp), %rsi
	movl	144(%rsp), %edx
	leaq	184(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 312
	popq	%rdx
	.cfi_def_cfa_offset 304
.L8:
	movq	280(%rsp), %rax
	subq	%fs:40, %rax
	je	.L10
	call	__stack_chk_fail@PLT
.L10:
	addq	$296, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2053:
	.size	_Z49__device_stub__Z10h_of_p_GPUPdS_S_S_S_S_S_ddddiiiPdS_S_S_S_S_S_ddddiii, .-_Z49__device_stub__Z10h_of_p_GPUPdS_S_S_S_S_S_ddddiiiPdS_S_S_S_S_S_ddddiii
	.globl	_Z10h_of_p_GPUPdS_S_S_S_S_S_ddddiii
	.type	_Z10h_of_p_GPUPdS_S_S_S_S_S_ddddiii, @function
_Z10h_of_p_GPUPdS_S_S_S_S_S_ddddiii:
.LFB2054:
	.cfi_startproc
	endbr64
	jmp	_Z49__device_stub__Z10h_of_p_GPUPdS_S_S_S_S_S_ddddiiiPdS_S_S_S_S_S_ddddiii
	.cfi_endproc
.LFE2054:
	.size	_Z10h_of_p_GPUPdS_S_S_S_S_S_ddddiii, .-_Z10h_of_p_GPUPdS_S_S_S_S_S_ddddiii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z10h_of_p_GPUPdS_S_S_S_S_S_ddddiii"
.LC1:
	.string	"_Z16epsilon_of_p_GPUPdS_S_S_S_S_S_ddddiii"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2056:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z10h_of_p_GPUPdS_S_S_S_S_S_ddddiii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC1(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z16epsilon_of_p_GPUPdS_S_S_S_S_S_ddddiii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2056:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include <stdio.h>
#include <math.h>


__global__ void epsilon_of_p_GPU(double *output_arr, double *px_arr, double *py_arr,
                                 double *kxprime_arr, double *kyprime_arr,
                                 double *E_k_n, double *U_k,
                                 double mu, double q, double g, double theta,
                                 int N_kx, int N_ky, int debug)
{
    const int i = threadIdx.x + blockDim.x*blockIdx.x;
    const int j = threadIdx.y + blockDim.y*blockIdx.y;
    const int N_n = 3;
    const int N_l = 3;

    int iprime, jprime, n, l;

    const double px = px_arr[i];
    const double py = py_arr[j];

    double kxprime, kyprime;
    double px_pot, py_pot, potential;
    double evec_element, eigenval;
    double accumulator = 0;

    double pot_trig_terms = pow(cos(theta), 2) - pow(sin(theta), 2)*0;

    const double dpx = px_arr[1] - px_arr[0];
    const double dpy = py_arr[1] - py_arr[0];
    const double prefactor = dpx*dpy/(4*M_PI*M_PI);

    if ((i < N_kx) & (j < N_ky)){
        for (iprime=0; iprime<N_kx; iprime++){
            for (jprime=0; jprime<N_ky; jprime++){
                kxprime = kxprime_arr[iprime];
                kyprime = kyprime_arr[jprime];
                for (n=-1; n<2; n++){
                    px_pot = px - kxprime - n*q;
                    py_pot = py - kyprime;
                    potential = - g*sqrt(px_pot*px_pot + py_pot*py_pot) * pot_trig_terms;
                    for (l=0; l<3; l++){
                        eigenval = E_k_n[N_ky*N_l*iprime + N_l*jprime + l];
                        if (eigenval <= mu){
                            evec_element = U_k[N_ky*N_n*N_l*iprime + N_n*N_l*jprime + N_l*(n+1) + l];
                            // if ((debug > 0) & (i==7) & (j==5) & (iprime==22) & (jprime==33) & (n==0) & (l==0)){
                            //      printf("  epsilon_k[7,5] kprime[22,33] n=0, l=0 (CUDA):\n");
                            //      printf("    px is: %f\n", px);
                            //      printf("    py is: %f\n", py);
                            //      printf("    kxprime is: %f\n", kxprime);
                            //      printf("    kyprime is: %f\n", kyprime);
                            //      printf("    potential terms is %f\n",potential);
                            //      printf("    evec element is %f\n", evec_element);
                            //      printf("    value of term is: %f\n", potential*evec_element*evec_element);
                            //  }
                            accumulator += potential * evec_element*evec_element;
                        }
                    }
                }
            }
        }

        // Multiple the sum by the appropriate prefactor:
        accumulator *= prefactor;

        // Add the kinetic term:
        accumulator += (px*px + py*py);

        output_arr[N_ky*i + j] = accumulator;
        // if ((debug > 0) & (i==7) & (j==5)){
        //     printf("  epsilon_k[7,5] (CUDA): %f\n\n", accumulator);
        // }
    }
}

__global__ void h_of_p_GPU(double *output_arr, double *px_arr, double *py_arr,
                                 double *kxprime_arr, double *kyprime_arr,
                                 double *E_k_n, double *U_k,
                                 double mu, double q, double g, double theta,
                                 int N_kx, int N_ky, int debug)
{
    const int i = threadIdx.x + blockDim.x*blockIdx.x;
    const int j = threadIdx.y + blockDim.y*blockIdx.y;
    const int N_n = 3;
    const int N_l = 3;

    int iprime, jprime, l;

    double px = px_arr[i];
    double py = py_arr[j];

    double kxprime, kyprime;
    double px_pot, py_pot, potential_1, potential_2;
    double evec_element_1, evec_element_2, evec_element_3, eigenval;
    double accumulator = 0;

    double pot_trig_terms = pow(cos(theta), 2) - pow(sin(theta), 2)*0;
    double V_of_q = g*sqrt(q*q) * pot_trig_terms; // V(px=q, py=0)

    const double dpx = px_arr[1] - px_arr[0];
    const double dpy = py_arr[1] - py_arr[0];
    const double prefactor = dpx*dpy/(4*M_PI*M_PI);

    if ((i < N_kx) & (j < N_ky)){
        for (iprime=0; iprime<N_kx; iprime++){
            for (jprime=0; jprime<N_ky; jprime++){
                kxprime = kxprime_arr[iprime];
                kyprime = kyprime_arr[jprime];
                for (l=0; l<3; l++){
                    eigenval = E_k_n[N_ky*N_l*iprime + N_l*jprime + l];
                    if (eigenval <= mu){
                        evec_element_1 = U_k[N_ky*N_n*N_l*iprime + N_n*N_l*jprime + N_l*0 + l];
                        evec_element_2 = U_k[N_ky*N_n*N_l*iprime + N_n*N_l*jprime + N_l*1 + l];
                        evec_element_3 = U_k[N_ky*N_n*N_l*iprime + N_n*N_l*jprime + N_l*2 + l];

                        px_pot = px - kxprime + q;
                        py_pot = py - kyprime;
                        potential_1 = V_of_q - g*sqrt(px_pot*px_pot + py_pot*py_pot) * pot_trig_terms;

                        px_pot = px - kxprime;
                        py_pot = py - kyprime;
                        potential_2 = V_of_q - g*sqrt(px_pot*px_pot + py_pot*py_pot) * pot_trig_terms;

                        accumulator += potential_1 * evec_element_1*evec_element_2 + potential_2 * evec_element_2*evec_element_3;

                        // if ((debug > 0) & (i==7) & (j==5) & (iprime==22) & (jprime==33) & (l==0)){
                             // printf("  h_k[7,5] kprime[22,33], l=0 (CUDA):\n");
                             // printf("    px is: %f\n", px);
                             // printf("    py is: %f\n", py);
                             // printf("    kxprime is: %f\n", kxprime);
                             // printf("    kyprime is: %f\n", kyprime);
                             // printf("    potential term 1 is %f\n", potential_1);
                             // printf("    potential term 2 is %f\n", potential_2);
                             // printf("    value of term is: %f\n",
                             //        potential_1 * evec_element_1*evec_element_2 + potential_2 * evec_element_2*evec_element_3);
                         // }
                    }
                }
            }
        }
        // Multiple the sum by the appropriate prefactor:
        accumulator *= prefactor;

        output_arr[N_ky*i + j] = accumulator;
        // if ((debug > 0) & (i==7) & (j==5)){
        //     printf("  h_k[7,5] (CUDA): %f\n\n", accumulator);
        // }
    }
}

	.text
	.file	"cuda_module.hip"
	.globl	_Z31__device_stub__epsilon_of_p_GPUPdS_S_S_S_S_S_ddddiii # -- Begin function _Z31__device_stub__epsilon_of_p_GPUPdS_S_S_S_S_S_ddddiii
	.type	_Z31__device_stub__epsilon_of_p_GPUPdS_S_S_S_S_S_ddddiii,@function
_Z31__device_stub__epsilon_of_p_GPUPdS_S_S_S_S_S_ddddiii: # @_Z31__device_stub__epsilon_of_p_GPUPdS_S_S_S_S_S_ddddiii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$240, %rsp
	.cfi_def_cfa_offset 288
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	88(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	80(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	72(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	64(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	56(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	48(%rsp), %r8
	movq	%r9, (%r8)
	leaq	40(%rsp), %r9
	movsd	%xmm0, (%r9)
	leaq	32(%rsp), %r10
	movsd	%xmm1, (%r10)
	leaq	24(%rsp), %r11
	movsd	%xmm2, (%r11)
	leaq	16(%rsp), %r14
	movsd	%xmm3, (%r14)
	leaq	128(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	288(%rsp), %rax
	movq	%rax, 48(%rbx)
	movq	%r9, 56(%rbx)
	movq	%r10, 64(%rbx)
	movq	%r11, 72(%rbx)
	movq	%r14, 80(%rbx)
	leaq	296(%rsp), %rax
	movq	%rax, 88(%rbx)
	leaq	304(%rsp), %rax
	movq	%rax, 96(%rbx)
	leaq	312(%rsp), %rax
	movq	%rax, 104(%rbx)
	leaq	112(%rsp), %r14
	leaq	96(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z16epsilon_of_p_GPUPdS_S_S_S_S_S_ddddiii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$256, %rsp                      # imm = 0x100
	.cfi_adjust_cfa_offset -256
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z31__device_stub__epsilon_of_p_GPUPdS_S_S_S_S_S_ddddiii, .Lfunc_end0-_Z31__device_stub__epsilon_of_p_GPUPdS_S_S_S_S_S_ddddiii
	.cfi_endproc
                                        # -- End function
	.globl	_Z25__device_stub__h_of_p_GPUPdS_S_S_S_S_S_ddddiii # -- Begin function _Z25__device_stub__h_of_p_GPUPdS_S_S_S_S_S_ddddiii
	.type	_Z25__device_stub__h_of_p_GPUPdS_S_S_S_S_S_ddddiii,@function
_Z25__device_stub__h_of_p_GPUPdS_S_S_S_S_S_ddddiii: # @_Z25__device_stub__h_of_p_GPUPdS_S_S_S_S_S_ddddiii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$240, %rsp
	.cfi_def_cfa_offset 288
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	88(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	80(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	72(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	64(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	56(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	48(%rsp), %r8
	movq	%r9, (%r8)
	leaq	40(%rsp), %r9
	movsd	%xmm0, (%r9)
	leaq	32(%rsp), %r10
	movsd	%xmm1, (%r10)
	leaq	24(%rsp), %r11
	movsd	%xmm2, (%r11)
	leaq	16(%rsp), %r14
	movsd	%xmm3, (%r14)
	leaq	128(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	288(%rsp), %rax
	movq	%rax, 48(%rbx)
	movq	%r9, 56(%rbx)
	movq	%r10, 64(%rbx)
	movq	%r11, 72(%rbx)
	movq	%r14, 80(%rbx)
	leaq	296(%rsp), %rax
	movq	%rax, 88(%rbx)
	leaq	304(%rsp), %rax
	movq	%rax, 96(%rbx)
	leaq	312(%rsp), %rax
	movq	%rax, 104(%rbx)
	leaq	112(%rsp), %r14
	leaq	96(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z10h_of_p_GPUPdS_S_S_S_S_S_ddddiii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$256, %rsp                      # imm = 0x100
	.cfi_adjust_cfa_offset -256
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z25__device_stub__h_of_p_GPUPdS_S_S_S_S_S_ddddiii, .Lfunc_end1-_Z25__device_stub__h_of_p_GPUPdS_S_S_S_S_S_ddddiii
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z16epsilon_of_p_GPUPdS_S_S_S_S_S_ddddiii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z10h_of_p_GPUPdS_S_S_S_S_S_ddddiii, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z16epsilon_of_p_GPUPdS_S_S_S_S_S_ddddiii,@object # @_Z16epsilon_of_p_GPUPdS_S_S_S_S_S_ddddiii
	.section	.rodata,"a",@progbits
	.globl	_Z16epsilon_of_p_GPUPdS_S_S_S_S_S_ddddiii
	.p2align	3, 0x0
_Z16epsilon_of_p_GPUPdS_S_S_S_S_S_ddddiii:
	.quad	_Z31__device_stub__epsilon_of_p_GPUPdS_S_S_S_S_S_ddddiii
	.size	_Z16epsilon_of_p_GPUPdS_S_S_S_S_S_ddddiii, 8

	.type	_Z10h_of_p_GPUPdS_S_S_S_S_S_ddddiii,@object # @_Z10h_of_p_GPUPdS_S_S_S_S_S_ddddiii
	.globl	_Z10h_of_p_GPUPdS_S_S_S_S_S_ddddiii
	.p2align	3, 0x0
_Z10h_of_p_GPUPdS_S_S_S_S_S_ddddiii:
	.quad	_Z25__device_stub__h_of_p_GPUPdS_S_S_S_S_S_ddddiii
	.size	_Z10h_of_p_GPUPdS_S_S_S_S_S_ddddiii, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z16epsilon_of_p_GPUPdS_S_S_S_S_S_ddddiii"
	.size	.L__unnamed_1, 42

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z10h_of_p_GPUPdS_S_S_S_S_S_ddddiii"
	.size	.L__unnamed_2, 36

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z31__device_stub__epsilon_of_p_GPUPdS_S_S_S_S_S_ddddiii
	.addrsig_sym _Z25__device_stub__h_of_p_GPUPdS_S_S_S_S_S_ddddiii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z16epsilon_of_p_GPUPdS_S_S_S_S_S_ddddiii
	.addrsig_sym _Z10h_of_p_GPUPdS_S_S_S_S_S_ddddiii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z16epsilon_of_p_GPUPdS_S_S_S_S_S_ddddiii ; -- Begin function _Z16epsilon_of_p_GPUPdS_S_S_S_S_S_ddddiii
	.globl	_Z16epsilon_of_p_GPUPdS_S_S_S_S_S_ddddiii
	.p2align	8
	.type	_Z16epsilon_of_p_GPUPdS_S_S_S_S_S_ddddiii,@function
_Z16epsilon_of_p_GPUPdS_S_S_S_S_S_ddddiii: ; @_Z16epsilon_of_p_GPUPdS_S_S_S_S_S_ddddiii
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x74
	s_load_b64 s[4:5], s[0:1], 0x50
	v_and_b32_e32 v2, 0x3ff, v0
	v_bfe_u32 v4, v0, 10, 10
	s_load_b512 s[16:31], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s3, s2, 0xffff
	s_lshr_b32 s2, s2, 16
	v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
	v_mad_u64_u32 v[2:3], null, s15, s2, v[4:5]
	v_cmp_ngt_f64_e64 s3, 0x41d00000, |s[4:5]|
	v_trig_preop_f64 v[15:16], |s[4:5]|, 0
	v_trig_preop_f64 v[9:10], |s[4:5]|, 1
	v_cmp_le_f64_e64 s2, 0x7b000000, |s[4:5]|
	v_ashrrev_i32_e32 v1, 31, v0
	v_ldexp_f64 v[17:18], |s[4:5]|, 0xffffff80
	v_ashrrev_i32_e32 v3, 31, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[4:5], 3, v[0:1]
	v_lshlrev_b64 v[6:7], 3, v[2:3]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v3, vcc_lo, s18, v4
	v_add_co_ci_u32_e32 v4, vcc_lo, s19, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v5, vcc_lo, s20, v6
	v_add_co_ci_u32_e32 v6, vcc_lo, s21, v7, vcc_lo
	v_trig_preop_f64 v[7:8], |s[4:5]|, 2
	global_load_b64 v[3:4], v[3:4], off
	global_load_b64 v[5:6], v[5:6], off
	s_and_b32 vcc_lo, exec_lo, s3
	s_cbranch_vccz .LBB0_2
; %bb.1:
	s_and_b32 s6, s5, 0x7fffffff
	v_cndmask_b32_e64 v11, s4, v17, s2
	v_cndmask_b32_e64 v12, s6, v18, s2
	s_mov_b32 s6, 0
	s_mov_b32 s8, 0x54442d18
	s_mov_b32 s9, 0x3ff921fb
	s_mov_b32 s10, 0x33145c07
	v_mul_f64 v[13:14], v[15:16], v[11:12]
	v_mul_f64 v[19:20], v[9:10], v[11:12]
	v_mul_f64 v[31:32], v[7:8], v[11:12]
	s_mov_b32 s11, 0x3c91a626
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[21:22], v[15:16], v[11:12], -v[13:14]
	v_fma_f64 v[33:34], v[9:10], v[11:12], -v[19:20]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[11:12], v[7:8], v[11:12], -v[31:32]
	v_add_f64 v[23:24], v[19:20], v[21:22]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[25:26], v[23:24], -v[19:20]
	v_add_f64 v[29:30], v[13:14], v[23:24]
	v_add_f64 v[27:28], v[23:24], -v[25:26]
	v_add_f64 v[21:22], v[21:22], -v[25:26]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_ldexp_f64 v[25:26], v[29:30], -2
	v_add_f64 v[13:14], v[29:30], -v[13:14]
	v_add_f64 v[19:20], v[19:20], -v[27:28]
	v_add_f64 v[27:28], v[31:32], v[33:34]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[25:26]|
	v_add_f64 v[13:14], v[23:24], -v[13:14]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[19:20], v[21:22], v[19:20]
	v_fract_f64_e32 v[21:22], v[25:26]
	v_add_f64 v[23:24], v[27:28], v[19:20]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_cndmask_b32 v22, 0, v22 :: v_dual_cndmask_b32 v21, 0, v21
	v_ldexp_f64 v[21:22], v[21:22], 2
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[25:26], v[13:14], v[23:24]
	v_add_f64 v[35:36], v[23:24], -v[27:28]
	v_add_f64 v[29:30], v[25:26], v[21:22]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_add_f64 v[41:42], v[23:24], -v[35:36]
	v_add_f64 v[19:20], v[19:20], -v[35:36]
	v_add_f64 v[13:14], v[25:26], -v[13:14]
	v_cmp_gt_f64_e32 vcc_lo, 0, v[29:30]
	v_add_f64 v[29:30], v[27:28], -v[31:32]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_add_f64 v[13:14], v[23:24], -v[13:14]
	s_and_b32 s2, vcc_lo, exec_lo
	s_cselect_b32 s7, 0x40100000, 0
	v_add_f64 v[39:40], v[27:28], -v[29:30]
	v_add_f64 v[21:22], v[21:22], s[6:7]
	v_add_f64 v[29:30], v[33:34], -v[29:30]
	v_add_f64 v[27:28], v[27:28], -v[41:42]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[33:34], v[31:32], -v[39:40]
	v_add_f64 v[37:38], v[25:26], v[21:22]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[19:20], v[19:20], v[27:28]
	v_add_f64 v[29:30], v[29:30], v[33:34]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_i32_f64_e32 v1, v[37:38]
	v_add_f64 v[19:20], v[29:30], v[19:20]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_f64_i32_e32 v[35:36], v1
	v_add_f64 v[11:12], v[11:12], v[19:20]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[21:22], v[21:22], -v[35:36]
	v_add_f64 v[11:12], v[13:14], v[11:12]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[27:28], v[25:26], v[21:22]
	v_add_f64 v[19:20], v[27:28], -v[21:22]
	v_cmp_le_f64_e32 vcc_lo, 0.5, v[27:28]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_add_f64 v[13:14], v[25:26], -v[19:20]
	s_and_b32 s2, vcc_lo, exec_lo
	s_cselect_b32 s7, 0x3ff00000, 0
	v_add_co_ci_u32_e64 v1, s2, 0, v1, vcc_lo
	v_add_f64 v[11:12], v[11:12], v[13:14]
	v_add_f64 v[13:14], v[27:28], -s[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[19:20], v[13:14], v[11:12]
	v_mul_f64 v[21:22], v[19:20], s[8:9]
	v_add_f64 v[13:14], v[19:20], -v[13:14]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[23:24], v[19:20], s[8:9], -v[21:22]
	v_add_f64 v[11:12], v[11:12], -v[13:14]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[13:14], v[19:20], s[10:11], v[23:24]
	v_fma_f64 v[13:14], v[11:12], s[8:9], v[13:14]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[11:12], v[21:22], v[13:14]
	v_add_f64 v[19:20], v[11:12], -v[21:22]
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[13:14], v[13:14], -v[19:20]
	s_branch .LBB0_3
.LBB0_2:
	s_mov_b32 s6, -1
                                        ; implicit-def: $vgpr1
                                        ; implicit-def: $vgpr11_vgpr12
                                        ; implicit-def: $vgpr13_vgpr14
.LBB0_3:                                ; %Flow156
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s6
	s_cbranch_vccnz .LBB0_5
; %bb.4:
	s_mov_b32 s6, 0x6dc9c883
	s_mov_b32 s7, 0x3fe45f30
	s_mov_b32 s9, 0xbc91a626
	v_mul_f64 v[11:12], |s[4:5]|, s[6:7]
	s_mov_b32 s6, 0x54442d18
	s_mov_b32 s7, 0xbff921fb
	s_mov_b32 s8, 0x33145c00
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f64_e32 v[19:20], v[11:12]
	v_fma_f64 v[11:12], v[19:20], s[6:7], |s[4:5]|
	v_mul_f64 v[13:14], v[19:20], s[8:9]
	s_mov_b32 s6, 0x252049c0
	s_mov_b32 s7, 0xb97b839a
	v_cvt_i32_f64_e32 v1, v[19:20]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[23:24], v[19:20], s[8:9], v[11:12]
	v_add_f64 v[21:22], v[11:12], v[13:14]
	s_mov_b32 s9, 0x3c91a626
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[11:12], v[11:12], -v[21:22]
	v_add_f64 v[21:22], v[21:22], -v[23:24]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[11:12], v[11:12], v[13:14]
	v_fma_f64 v[13:14], v[19:20], s[8:9], v[13:14]
	v_add_f64 v[11:12], v[21:22], v[11:12]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[11:12], v[11:12], -v[13:14]
	v_fma_f64 v[13:14], v[19:20], s[6:7], v[11:12]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[11:12], v[23:24], v[13:14]
	v_add_f64 v[21:22], v[11:12], -v[23:24]
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[13:14], v[13:14], -v[21:22]
.LBB0_5:                                ; %_ZL3cosd.exit
	s_and_b32 vcc_lo, exec_lo, s3
	s_cbranch_vccz .LBB0_7
; %bb.6:
	v_cmp_le_f64_e64 vcc_lo, 0x7b000000, |s[4:5]|
	s_and_b32 s2, s5, 0x7fffffff
	s_mov_b32 s6, 0x54442d18
	s_mov_b32 s7, 0x3ff921fb
	s_mov_b32 s8, 0x33145c07
	s_mov_b32 s9, 0x3c91a626
	v_cndmask_b32_e32 v18, s2, v18, vcc_lo
	v_cndmask_b32_e32 v17, s4, v17, vcc_lo
	s_mov_b32 s2, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_mul_f64 v[19:20], v[15:16], v[17:18]
	v_mul_f64 v[21:22], v[9:10], v[17:18]
	v_mul_f64 v[31:32], v[7:8], v[17:18]
	v_fma_f64 v[15:16], v[15:16], v[17:18], -v[19:20]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[9:10], v[9:10], v[17:18], -v[21:22]
	v_fma_f64 v[7:8], v[7:8], v[17:18], -v[31:32]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[23:24], v[21:22], v[15:16]
	v_add_f64 v[25:26], v[23:24], -v[21:22]
	v_add_f64 v[29:30], v[19:20], v[23:24]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[27:28], v[23:24], -v[25:26]
	v_add_f64 v[15:16], v[15:16], -v[25:26]
	v_ldexp_f64 v[25:26], v[29:30], -2
	v_add_f64 v[19:20], v[29:30], -v[19:20]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f64 v[21:22], v[21:22], -v[27:28]
	v_add_f64 v[27:28], v[31:32], v[9:10]
	v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[25:26]|
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[19:20], v[23:24], -v[19:20]
	v_add_f64 v[15:16], v[15:16], v[21:22]
	v_fract_f64_e32 v[21:22], v[25:26]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[23:24], v[27:28], v[15:16]
	v_dual_cndmask_b32 v22, 0, v22 :: v_dual_cndmask_b32 v21, 0, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_ldexp_f64 v[21:22], v[21:22], 2
	v_add_f64 v[25:26], v[19:20], v[23:24]
	v_add_f64 v[33:34], v[23:24], -v[27:28]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[29:30], v[25:26], v[21:22]
	v_add_f64 v[39:40], v[23:24], -v[33:34]
	v_add_f64 v[15:16], v[15:16], -v[33:34]
	v_add_f64 v[17:18], v[25:26], -v[19:20]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cmp_gt_f64_e32 vcc_lo, 0, v[29:30]
	v_add_f64 v[29:30], v[27:28], -v[31:32]
	v_add_f64 v[17:18], v[23:24], -v[17:18]
	s_and_b32 s3, vcc_lo, exec_lo
	s_cselect_b32 s3, 0x40100000, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_add_f64 v[37:38], v[27:28], -v[29:30]
	v_add_f64 v[21:22], v[21:22], s[2:3]
	v_add_f64 v[9:10], v[9:10], -v[29:30]
	v_add_f64 v[27:28], v[27:28], -v[39:40]
	v_add_f64 v[29:30], v[31:32], -v[37:38]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[35:36], v[25:26], v[21:22]
	v_add_f64 v[15:16], v[15:16], v[27:28]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[9:10], v[9:10], v[29:30]
	v_cvt_i32_f64_e32 v35, v[35:36]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[9:10], v[9:10], v[15:16]
	v_cvt_f64_i32_e32 v[33:34], v35
	v_readfirstlane_b32 s3, v35
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[7:8], v[7:8], v[9:10]
	v_add_f64 v[21:22], v[21:22], -v[33:34]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[7:8], v[17:18], v[7:8]
	v_add_f64 v[15:16], v[25:26], v[21:22]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[9:10], v[15:16], -v[21:22]
	v_cmp_le_f64_e32 vcc_lo, 0.5, v[15:16]
	v_add_f64 v[9:10], v[25:26], -v[9:10]
	s_cmp_lg_u32 vcc_lo, 0
	s_addc_u32 s33, s3, 0
	s_and_b32 s3, vcc_lo, exec_lo
	s_cselect_b32 s3, 0x3ff00000, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f64 v[7:8], v[7:8], v[9:10]
	v_add_f64 v[9:10], v[15:16], -s[2:3]
	v_add_f64 v[15:16], v[9:10], v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_f64 v[17:18], v[15:16], s[6:7]
	v_add_f64 v[9:10], v[15:16], -v[9:10]
	v_fma_f64 v[19:20], v[15:16], s[6:7], -v[17:18]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[7:8], v[7:8], -v[9:10]
	v_fma_f64 v[9:10], v[15:16], s[8:9], v[19:20]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[9:10], v[7:8], s[6:7], v[9:10]
	v_add_f64 v[7:8], v[17:18], v[9:10]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[15:16], v[7:8], -v[17:18]
	v_add_f64 v[9:10], v[9:10], -v[15:16]
	s_branch .LBB0_8
.LBB0_7:
	s_mov_b32 s2, -1
                                        ; implicit-def: $sgpr33
                                        ; implicit-def: $vgpr7_vgpr8
                                        ; implicit-def: $vgpr9_vgpr10
.LBB0_8:                                ; %Flow155
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s2
	s_cbranch_vccnz .LBB0_10
; %bb.9:
	s_mov_b32 s2, 0x6dc9c883
	s_mov_b32 s3, 0x3fe45f30
	s_mov_b32 s7, 0xbc91a626
	v_mul_f64 v[7:8], |s[4:5]|, s[2:3]
	s_mov_b32 s2, 0x54442d18
	s_mov_b32 s3, 0xbff921fb
	s_mov_b32 s6, 0x33145c00
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f64_e32 v[9:10], v[7:8]
	v_fma_f64 v[7:8], v[9:10], s[2:3], |s[4:5]|
	v_mul_f64 v[15:16], v[9:10], s[6:7]
	s_mov_b32 s2, 0x252049c0
	s_mov_b32 s3, 0xb97b839a
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[21:22], v[9:10], s[6:7], v[7:8]
	v_add_f64 v[17:18], v[7:8], v[15:16]
	s_mov_b32 s7, 0x3c91a626
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[19:20], v[7:8], -v[17:18]
	v_add_f64 v[17:18], v[17:18], -v[21:22]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_add_f64 v[7:8], v[19:20], v[15:16]
	v_fma_f64 v[15:16], v[9:10], s[6:7], v[15:16]
	v_cvt_i32_f64_e32 v19, v[9:10]
	v_add_f64 v[7:8], v[17:18], v[7:8]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s33, v19
	v_add_f64 v[7:8], v[7:8], -v[15:16]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[15:16], v[9:10], s[2:3], v[7:8]
	v_add_f64 v[7:8], v[21:22], v[15:16]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[17:18], v[7:8], -v[21:22]
	v_add_f64 v[9:10], v[15:16], -v[17:18]
.LBB0_10:                               ; %_ZL3sind.exit
	s_load_b64 s[8:9], s[0:1], 0x58
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_i32_e32 vcc_lo, s8, v0
	v_cmp_gt_i32_e64 s2, s9, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, vcc_lo, s2
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_25
; %bb.11:                               ; %.preheader89
	s_cmp_lt_i32 s8, 1
	s_cbranch_scc1 .LBB0_23
; %bb.12:                               ; %.preheader.lr.ph
	v_mul_f64 v[15:16], v[11:12], v[11:12]
	s_mov_b32 s10, 0xb42fdfa7
	s_mov_b32 s12, 0xf9a43bb8
	s_mov_b32 s11, 0xbe5ae600
	s_mov_b32 s13, 0x3de5e0b2
	s_mov_b32 s34, 0x796cde01
	s_mov_b32 s35, 0x3ec71de3
	s_mov_b32 s14, 0x9037ab78
	s_mov_b32 s36, 0x46cc5e42
	s_mov_b32 s15, 0x3e21eeb6
	s_mov_b32 s37, 0xbda907db
	s_mov_b32 s40, 0x19e83e5c
	s_mov_b32 s41, 0xbf2a01a0
	s_mov_b32 s44, 0xa17f65f6
	s_mov_b32 s45, 0xbe927e4f
	s_mov_b32 s42, 0x11110bb3
	s_mov_b32 s43, 0x3f811111
	s_delay_alu instid0(VALU_DEP_4)
	v_mul_f64 v[25:26], v[13:14], 0.5
	s_mov_b32 s46, 0x19f4ec90
	s_mov_b32 s47, 0x3efa01a0
	s_mov_b32 s54, 0x16c16967
	s_mov_b32 s55, 0xbf56c16c
	s_mov_b32 s48, 0x55555555
	s_mov_b32 s49, 0x3fa55555
	s_mov_b32 s39, 0xbfc55555
	s_mov_b32 s38, s48
	v_cmp_class_f64_e64 vcc_lo, s[4:5], 0x1f8
	s_mov_b32 s7, 0x3fe55555
	s_mov_b32 s6, s48
	s_mov_b32 s50, 0x968915a9
	s_mov_b32 s52, 0x4222de17
	s_mov_b32 s51, 0x3fba6564
	s_mov_b32 s53, 0x3fbdee67
	s_mov_b32 s56, 0x3abe935a
	s_mov_b32 s57, 0x3fbe25e4
	s_mov_b32 s58, 0x47e6c9c2
	s_mov_b32 s59, 0x3fc110ef
	s_mov_b32 s60, 0xcfa74449
	v_fma_f64 v[17:18], v[15:16], s[12:13], s[10:11]
	v_mul_f64 v[21:22], v[15:16], 0.5
	v_fma_f64 v[19:20], v[15:16], s[36:37], s[14:15]
	v_mul_f64 v[27:28], v[11:12], -v[15:16]
	s_mov_b32 s61, 0x3fc3b13b
	s_mov_b32 s62, 0x71bf3c30
	s_mov_b32 s63, 0x3fc745d1
	s_mov_b32 s64, 0x1c7792ce
	s_mov_b32 s65, 0x3fcc71c7
	s_mov_b32 s66, 0x924920da
	s_mov_b32 s67, 0x3fd24924
	s_mov_b32 s68, 0x9999999c
	s_mov_b32 s69, 0x3fd99999
	s_mov_b32 s71, 0xbfe55555
	s_mov_b32 s70, s48
	s_mov_b32 s72, 0xd5df274d
	s_mov_b32 s73, 0x3c8543b0
	s_mov_b32 s74, 0xfefa39ef
	s_mov_b32 s75, 0x3fe62e42
	s_mov_b32 s78, 0x3b39803f
	s_mov_b32 s79, 0x3c7abc9e
	s_mov_b32 s76, 0x652b82fe
	s_mov_b32 s77, 0x3ff71547
	s_mov_b32 s81, 0xbfe62e42
	s_mov_b32 s80, s74
	s_mov_b32 s83, 0xbc7abc9e
	s_mov_b32 s82, s78
	s_mov_b32 s84, 0xfca7ab0c
	s_mov_b32 s86, 0x6a5dcb37
	s_mov_b32 s85, 0x3e928af3
	s_mov_b32 s87, 0x3e5ade15
	s_mov_b32 s88, 0x623fde64
	s_mov_b32 s89, 0x3ec71dee
	s_mov_b32 s90, 0x7c89e6b0
	s_mov_b32 s91, 0x3efa0199
	s_mov_b32 s92, 0x14761f6e
	s_mov_b32 s93, 0x3f2a01a0
	s_mov_b32 s94, 0x1852b7b0
	v_fma_f64 v[17:18], v[15:16], v[17:18], s[34:35]
	v_add_f64 v[23:24], -v[21:22], 1.0
	v_fma_f64 v[19:20], v[15:16], v[19:20], s[44:45]
	s_mov_b32 s95, 0x3f56c16c
	s_mov_b32 s96, 0x11122322
	s_mov_b32 s97, s43
	s_mov_b32 s98, 0x555502a1
	s_mov_b32 s99, s49
	s_mov_b32 s100, 0x55555511
	s_mov_b32 s101, 0x3fc55555
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[17:18], v[15:16], v[17:18], s[40:41]
	v_add_f64 v[29:30], -v[23:24], 1.0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[19:20], v[15:16], v[19:20], s[46:47]
	v_fma_f64 v[17:18], v[15:16], v[17:18], s[42:43]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[21:22], v[29:30], -v[21:22]
	v_fma_f64 v[19:20], v[15:16], v[19:20], s[54:55]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[17:18], v[27:28], v[17:18], v[25:26]
	v_fma_f64 v[21:22], v[11:12], -v[13:14], v[21:22]
	v_mul_f64 v[25:26], v[15:16], v[15:16]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[19:20], v[15:16], v[19:20], s[48:49]
	v_fma_f64 v[13:14], v[15:16], v[17:18], -v[13:14]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[15:16], v[25:26], v[19:20], v[21:22]
	v_fma_f64 v[13:14], v[27:28], s[38:39], v[13:14]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[15:16], v[23:24], v[15:16]
	v_add_f64 v[11:12], v[11:12], -v[13:14]
	v_and_b32_e32 v13, 1, v1
	v_lshlrev_b32_e32 v1, 30, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_eq_u32_e64 s2, 0, v13
	v_and_b32_e32 v1, 0x80000000, v1
	v_xor_b32_e32 v12, 0x80000000, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v11, v11, v15, s2
	v_cndmask_b32_e64 v12, v12, v16, s2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v11, 0, v11, vcc_lo
	v_xor_b32_e32 v1, v12, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v12, 0x7ff80000, v1, vcc_lo
	v_frexp_mant_f64_e64 v[13:14], |v[11:12]|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_gt_f64_e64 s2, s[6:7], v[13:14]
	v_cndmask_b32_e64 v1, 0, 1, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_ldexp_f64 v[13:14], v[13:14], v1
	v_frexp_exp_i32_f64_e32 v1, v[11:12]
	v_add_f64 v[15:16], v[13:14], 1.0
	v_add_f64 v[21:22], v[13:14], -1.0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_subrev_co_ci_u32_e64 v1, s2, 0, v1, s2
	v_rcp_f64_e32 v[17:18], v[15:16]
	v_add_f64 v[23:24], v[15:16], -1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_f64 v[13:14], v[13:14], -v[23:24]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[19:20], -v[15:16], v[17:18], 1.0
	v_fma_f64 v[17:18], v[19:20], v[17:18], v[17:18]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[19:20], -v[15:16], v[17:18], 1.0
	v_fma_f64 v[17:18], v[19:20], v[17:18], v[17:18]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[19:20], v[21:22], v[17:18]
	v_mul_f64 v[25:26], v[15:16], v[19:20]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[15:16], v[19:20], v[15:16], -v[25:26]
	v_fma_f64 v[13:14], v[19:20], v[13:14], v[15:16]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[15:16], v[25:26], v[13:14]
	v_add_f64 v[23:24], v[21:22], -v[15:16]
	v_add_f64 v[25:26], v[15:16], -v[25:26]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[21:22], v[21:22], -v[23:24]
	v_add_f64 v[13:14], v[25:26], -v[13:14]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[15:16], v[21:22], -v[15:16]
	v_add_f64 v[13:14], v[13:14], v[15:16]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[13:14], v[23:24], v[13:14]
	v_mul_f64 v[13:14], v[17:18], v[13:14]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[15:16], v[19:20], v[13:14]
	v_add_f64 v[17:18], v[15:16], -v[19:20]
	v_mul_f64 v[19:20], v[15:16], v[15:16]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[13:14], v[13:14], -v[17:18]
	v_fma_f64 v[17:18], v[15:16], v[15:16], -v[19:20]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[21:22], v[13:14], v[13:14]
	v_fma_f64 v[17:18], v[15:16], v[21:22], v[17:18]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[21:22], v[19:20], v[17:18]
	v_fma_f64 v[23:24], v[21:22], s[52:53], s[50:51]
	v_add_f64 v[19:20], v[21:22], -v[19:20]
	v_mul_f64 v[29:30], v[15:16], v[21:22]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[23:24], v[21:22], v[23:24], s[56:57]
	v_add_f64 v[17:18], v[17:18], -v[19:20]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[23:24], v[21:22], v[23:24], s[58:59]
	v_fma_f64 v[23:24], v[21:22], v[23:24], s[60:61]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[23:24], v[21:22], v[23:24], s[62:63]
	v_fma_f64 v[23:24], v[21:22], v[23:24], s[64:65]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[23:24], v[21:22], v[23:24], s[66:67]
	v_fma_f64 v[23:24], v[21:22], v[23:24], s[68:69]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[25:26], v[21:22], v[23:24]
	v_fma_f64 v[19:20], v[21:22], v[23:24], -v[25:26]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[19:20], v[17:18], v[23:24], v[19:20]
	v_add_f64 v[23:24], v[25:26], v[19:20]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[27:28], v[23:24], s[6:7]
	v_add_f64 v[25:26], v[23:24], -v[25:26]
	v_add_f64 v[31:32], v[27:28], s[70:71]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[19:20], v[19:20], -v[25:26]
	v_fma_f64 v[25:26], v[21:22], v[15:16], -v[29:30]
	v_add_f64 v[23:24], v[23:24], -v[31:32]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[19:20], v[19:20], s[72:73]
	v_fma_f64 v[21:22], v[21:22], v[13:14], v[25:26]
	v_ldexp_f64 v[13:14], v[13:14], 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[19:20], v[19:20], v[23:24]
	v_fma_f64 v[17:18], v[17:18], v[15:16], v[21:22]
	v_ldexp_f64 v[15:16], v[15:16], 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[21:22], v[27:28], v[19:20]
	v_add_f64 v[23:24], v[29:30], v[17:18]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[25:26], v[27:28], -v[21:22]
	v_mul_f64 v[27:28], v[23:24], v[21:22]
	v_add_f64 v[29:30], v[23:24], -v[29:30]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[19:20], v[19:20], v[25:26]
	v_fma_f64 v[25:26], v[23:24], v[21:22], -v[27:28]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[17:18], v[17:18], -v[29:30]
	v_fma_f64 v[19:20], v[23:24], v[19:20], v[25:26]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f64 v[17:18], v[17:18], v[21:22], v[19:20]
	v_cvt_f64_i32_e32 v[21:22], v1
	v_add_f64 v[19:20], v[27:28], v[17:18]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f64 v[23:24], v[15:16], v[19:20]
	v_add_f64 v[25:26], v[19:20], -v[27:28]
	v_mul_f64 v[27:28], v[21:22], s[74:75]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[15:16], v[23:24], -v[15:16]
	v_add_f64 v[17:18], v[17:18], -v[25:26]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[25:26], v[21:22], s[74:75], -v[27:28]
	v_add_f64 v[15:16], v[19:20], -v[15:16]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[13:14], v[13:14], v[17:18]
	v_fma_f64 v[17:18], v[21:22], s[78:79], v[25:26]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[13:14], v[13:14], v[15:16]
	v_add_f64 v[15:16], v[27:28], v[17:18]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[19:20], v[23:24], v[13:14]
	v_add_f64 v[27:28], v[15:16], -v[27:28]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[21:22], v[15:16], v[19:20]
	v_add_f64 v[23:24], v[19:20], -v[23:24]
	v_add_f64 v[17:18], v[17:18], -v[27:28]
	v_mul_f64 v[27:28], v[7:8], v[7:8]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[25:26], v[21:22], -v[15:16]
	v_add_f64 v[13:14], v[13:14], -v[23:24]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_fma_f64 v[31:32], v[27:28], s[36:37], s[14:15]
	v_mul_f64 v[33:34], v[27:28], 0.5
	s_mov_b32 s14, 0
	v_add_f64 v[29:30], v[21:22], -v[25:26]
	v_add_f64 v[19:20], v[19:20], -v[25:26]
	v_add_f64 v[23:24], v[17:18], v[13:14]
	v_fma_f64 v[31:32], v[27:28], v[31:32], s[44:45]
	v_add_f64 v[35:36], -v[33:34], 1.0
	v_add_f64 v[15:16], v[15:16], -v[29:30]
	v_fma_f64 v[29:30], v[27:28], s[12:13], s[10:11]
	s_mov_b32 s10, 11
	s_mov_b32 s11, 0x3fe00000
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[31:32], v[27:28], v[31:32], s[46:47]
	v_add_f64 v[37:38], -v[35:36], 1.0
	s_mul_i32 s12, s9, 9
	s_mov_b32 s13, 0
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_add_f64 v[15:16], v[19:20], v[15:16]
	v_add_f64 v[19:20], v[23:24], -v[17:18]
	v_fma_f64 v[29:30], v[27:28], v[29:30], s[34:35]
	v_add_f64 v[15:16], v[23:24], v[15:16]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f64 v[23:24], v[23:24], -v[19:20]
	v_add_f64 v[13:14], v[13:14], -v[19:20]
	v_fma_f64 v[29:30], v[27:28], v[29:30], s[40:41]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[25:26], v[21:22], v[15:16]
	v_add_f64 v[17:18], v[17:18], -v[23:24]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[29:30], v[27:28], v[29:30], s[42:43]
	v_add_f64 v[19:20], v[25:26], -v[21:22]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[13:14], v[13:14], v[17:18]
	v_add_f64 v[15:16], v[15:16], -v[19:20]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[13:14], v[13:14], v[15:16]
	v_add_f64 v[15:16], v[25:26], v[13:14]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[17:18], v[15:16], -v[25:26]
	v_add_f64 v[19:20], v[15:16], v[15:16]
	v_add_f64 v[13:14], v[13:14], -v[17:18]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f64 v[15:16], v[15:16], 2.0, -v[19:20]
	v_cmp_class_f64_e64 s2, v[19:20], 0x204
	v_fma_f64 v[13:14], v[13:14], 2.0, v[15:16]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[15:16], v[19:20], v[13:14]
	v_cndmask_b32_e64 v18, v16, v20, s2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v17, v15, v19, s2
	v_add_f64 v[15:16], v[15:16], -v[19:20]
	v_mul_f64 v[21:22], v[17:18], s[76:77]
	v_cmp_nlt_f64_e64 s3, 0x40900000, v[17:18]
	v_cmp_neq_f64_e64 s2, 0x7ff00000, |v[17:18]|
	v_cmp_ngt_f64_e64 s4, 0xc090cc00, v[17:18]
	v_add_f64 v[13:14], v[13:14], -v[15:16]
	v_mul_f64 v[15:16], v[27:28], v[27:28]
	v_rndne_f64_e32 v[21:22], v[21:22]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v14, 0, v14, s2
	v_cndmask_b32_e64 v13, 0, v13, s2
	s_and_b32 s2, s4, s3
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f64 v[23:24], v[21:22], s[80:81], v[17:18]
	v_cvt_i32_f64_e32 v1, v[21:22]
	v_fma_f64 v[23:24], v[21:22], s[82:83], v[23:24]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[25:26], v[23:24], s[86:87], s[84:85]
	v_fma_f64 v[25:26], v[23:24], v[25:26], s[88:89]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[25:26], v[23:24], v[25:26], s[90:91]
	v_fma_f64 v[25:26], v[23:24], v[25:26], s[92:93]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[25:26], v[23:24], v[25:26], s[94:95]
	v_fma_f64 v[25:26], v[23:24], v[25:26], s[96:97]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[25:26], v[23:24], v[25:26], s[98:99]
	v_fma_f64 v[25:26], v[23:24], v[25:26], s[100:101]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[25:26], v[23:24], v[25:26], s[10:11]
	v_fma_f64 v[25:26], v[23:24], v[25:26], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_fma_f64 v[21:22], v[23:24], v[25:26], 1.0
	v_mul_f64 v[23:24], v[9:10], 0.5
	v_mul_f64 v[25:26], v[7:8], -v[27:28]
	v_ldexp_f64 v[19:20], v[21:22], v1
	v_fma_f64 v[21:22], v[27:28], v[31:32], s[54:55]
	v_add_f64 v[31:32], v[37:38], -v[33:34]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[23:24], v[25:26], v[29:30], v[23:24]
	v_cndmask_b32_e64 v1, 0x7ff00000, v20, s3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[17:18], v[27:28], v[21:22], s[48:49]
	v_fma_f64 v[20:21], v[7:8], -v[9:10], v[31:32]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_3)
	v_fma_f64 v[9:10], v[27:28], v[23:24], -v[9:10]
	v_cndmask_b32_e64 v22, 0, v19, s2
	v_cndmask_b32_e64 v23, 0, v1, s4
	v_cmp_neq_f64_e64 s3, 0x7ff00000, |v[11:12]|
	v_cmp_neq_f64_e64 s4, 0, v[11:12]
	v_fma_f64 v[13:14], v[22:23], v[13:14], v[22:23]
	v_cmp_class_f64_e64 s2, v[22:23], 0x204
	v_fma_f64 v[15:16], v[15:16], v[17:18], v[20:21]
	v_fma_f64 v[9:10], v[25:26], s[38:39], v[9:10]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v1, v14, v23, s2
	v_cndmask_b32_e64 v30, v13, v22, s2
	s_and_b32 s2, s4, s3
	s_bitcmp0_b32 s33, 0
	v_and_b32_e32 v1, 0x7fffffff, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v1, 0x7ff00000, v1, s3
	s_cselect_b32 s3, -1, 0
	v_add_f64 v[11:12], v[35:36], v[15:16]
	v_add_f64 v[7:8], v[7:8], -v[9:10]
	v_cndmask_b32_e64 v9, 0, v1, s4
	s_lshl_b32 s4, s33, 30
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v1, v11, v7, s3
	v_cndmask_b32_e64 v7, v12, v8, s3
	s_xor_b32 s3, s4, s5
	s_mov_b32 s5, 0
	s_and_b32 s3, s3, 0x80000000
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_xor_b32_e32 v8, s3, v7
	v_cndmask_b32_e32 v7, 0, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v8, 0x7ff80000, v8, vcc_lo
	v_frexp_mant_f64_e64 v[10:11], |v[7:8]|
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_gt_f64_e32 vcc_lo, s[6:7], v[10:11]
	v_cndmask_b32_e64 v1, 0, 1, vcc_lo
	v_ldexp_f64 v[10:11], v[10:11], v1
	v_frexp_exp_i32_f64_e32 v1, v[7:8]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[12:13], v[10:11], 1.0
	v_add_f64 v[18:19], v[10:11], -1.0
	v_subrev_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[14:15], v[12:13]
	v_add_f64 v[20:21], v[12:13], -1.0
	v_add_f64 v[10:11], v[10:11], -v[20:21]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[16:17], -v[12:13], v[14:15], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[14:15], v[16:17], v[14:15], v[14:15]
	v_fma_f64 v[16:17], -v[12:13], v[14:15], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[14:15], v[16:17], v[14:15], v[14:15]
	v_mul_f64 v[16:17], v[18:19], v[14:15]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[22:23], v[12:13], v[16:17]
	v_fma_f64 v[12:13], v[16:17], v[12:13], -v[22:23]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[10:11], v[16:17], v[10:11], v[12:13]
	v_add_f64 v[12:13], v[22:23], v[10:11]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[20:21], v[18:19], -v[12:13]
	v_add_f64 v[22:23], v[12:13], -v[22:23]
	v_add_f64 v[18:19], v[18:19], -v[20:21]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[10:11], v[22:23], -v[10:11]
	v_add_f64 v[12:13], v[18:19], -v[12:13]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[10:11], v[10:11], v[12:13]
	v_add_f64 v[10:11], v[20:21], v[10:11]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[10:11], v[14:15], v[10:11]
	v_add_f64 v[12:13], v[16:17], v[10:11]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[14:15], v[12:13], -v[16:17]
	v_mul_f64 v[16:17], v[12:13], v[12:13]
	v_add_f64 v[10:11], v[10:11], -v[14:15]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[14:15], v[12:13], v[12:13], -v[16:17]
	v_add_f64 v[18:19], v[10:11], v[10:11]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[14:15], v[12:13], v[18:19], v[14:15]
	v_add_f64 v[18:19], v[16:17], v[14:15]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_fma_f64 v[20:21], v[18:19], s[52:53], s[50:51]
	v_add_f64 v[16:17], v[18:19], -v[16:17]
	v_mul_f64 v[26:27], v[12:13], v[18:19]
	v_fma_f64 v[20:21], v[18:19], v[20:21], s[56:57]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[14:15], v[14:15], -v[16:17]
	v_fma_f64 v[20:21], v[18:19], v[20:21], s[58:59]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[20:21], v[18:19], v[20:21], s[60:61]
	v_fma_f64 v[20:21], v[18:19], v[20:21], s[62:63]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[20:21], v[18:19], v[20:21], s[64:65]
	v_fma_f64 v[20:21], v[18:19], v[20:21], s[66:67]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[20:21], v[18:19], v[20:21], s[68:69]
	v_mul_f64 v[22:23], v[18:19], v[20:21]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[16:17], v[18:19], v[20:21], -v[22:23]
	v_fma_f64 v[16:17], v[14:15], v[20:21], v[16:17]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[20:21], v[22:23], v[16:17]
	v_add_f64 v[24:25], v[20:21], s[6:7]
	v_add_f64 v[22:23], v[20:21], -v[22:23]
	s_mov_b32 s6, s5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[28:29], v[24:25], s[70:71]
	v_add_f64 v[16:17], v[16:17], -v[22:23]
	v_fma_f64 v[22:23], v[18:19], v[12:13], -v[26:27]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[20:21], v[20:21], -v[28:29]
	v_add_f64 v[16:17], v[16:17], s[72:73]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fma_f64 v[18:19], v[18:19], v[10:11], v[22:23]
	v_ldexp_f64 v[10:11], v[10:11], 1
	v_add_f64 v[16:17], v[16:17], v[20:21]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fma_f64 v[14:15], v[14:15], v[12:13], v[18:19]
	v_ldexp_f64 v[12:13], v[12:13], 1
	v_add_f64 v[18:19], v[24:25], v[16:17]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[20:21], v[26:27], v[14:15]
	v_add_f64 v[22:23], v[24:25], -v[18:19]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_f64 v[24:25], v[20:21], v[18:19]
	v_add_f64 v[26:27], v[20:21], -v[26:27]
	v_add_f64 v[16:17], v[16:17], v[22:23]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[22:23], v[20:21], v[18:19], -v[24:25]
	v_add_f64 v[14:15], v[14:15], -v[26:27]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[16:17], v[20:21], v[16:17], v[22:23]
	v_fma_f64 v[14:15], v[14:15], v[18:19], v[16:17]
	v_cvt_f64_i32_e32 v[18:19], v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[16:17], v[24:25], v[14:15]
	v_add_f64 v[20:21], v[12:13], v[16:17]
	v_add_f64 v[22:23], v[16:17], -v[24:25]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f64 v[24:25], v[18:19], s[74:75]
	v_add_f64 v[12:13], v[20:21], -v[12:13]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[14:15], v[14:15], -v[22:23]
	v_fma_f64 v[22:23], v[18:19], s[74:75], -v[24:25]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[12:13], v[16:17], -v[12:13]
	v_add_f64 v[10:11], v[10:11], v[14:15]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[14:15], v[18:19], s[78:79], v[22:23]
	v_add_f64 v[10:11], v[10:11], v[12:13]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[12:13], v[24:25], v[14:15]
	v_add_f64 v[16:17], v[20:21], v[10:11]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[24:25], v[12:13], -v[24:25]
	v_add_f64 v[18:19], v[12:13], v[16:17]
	v_add_f64 v[20:21], v[16:17], -v[20:21]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[14:15], v[14:15], -v[24:25]
	v_add_f64 v[22:23], v[18:19], -v[12:13]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[10:11], v[10:11], -v[20:21]
	v_add_f64 v[26:27], v[18:19], -v[22:23]
	v_add_f64 v[16:17], v[16:17], -v[22:23]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[20:21], v[14:15], v[10:11]
	v_add_f64 v[12:13], v[12:13], -v[26:27]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[12:13], v[16:17], v[12:13]
	v_add_f64 v[16:17], v[20:21], -v[14:15]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[12:13], v[20:21], v[12:13]
	v_add_f64 v[20:21], v[20:21], -v[16:17]
	v_add_f64 v[10:11], v[10:11], -v[16:17]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[22:23], v[18:19], v[12:13]
	v_add_f64 v[14:15], v[14:15], -v[20:21]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[16:17], v[22:23], -v[18:19]
	v_add_f64 v[10:11], v[10:11], v[14:15]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[12:13], v[12:13], -v[16:17]
	v_add_f64 v[10:11], v[10:11], v[12:13]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[12:13], v[22:23], v[10:11]
	v_add_f64 v[14:15], v[12:13], -v[22:23]
	v_add_f64 v[16:17], v[12:13], v[12:13]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[10:11], v[10:11], -v[14:15]
	v_fma_f64 v[12:13], v[12:13], 2.0, -v[16:17]
	v_cmp_class_f64_e64 vcc_lo, v[16:17], 0x204
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[10:11], v[10:11], 2.0, v[12:13]
	v_add_f64 v[12:13], v[16:17], v[10:11]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v15, v13, v17 :: v_dual_cndmask_b32 v14, v12, v16
	v_add_f64 v[12:13], v[12:13], -v[16:17]
	v_mul_f64 v[18:19], v[14:15], s[76:77]
	v_cmp_nlt_f64_e64 s3, 0x40900000, v[14:15]
	v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[14:15]|
	v_cmp_ngt_f64_e64 s4, 0xc090cc00, v[14:15]
	v_add_f64 v[10:11], v[10:11], -v[12:13]
	v_rndne_f64_e32 v[18:19], v[18:19]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_cndmask_b32 v11, 0, v11 :: v_dual_cndmask_b32 v10, 0, v10
	s_and_b32 vcc_lo, s4, s3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f64 v[20:21], v[18:19], s[80:81], v[14:15]
	v_cvt_i32_f64_e32 v1, v[18:19]
	v_fma_f64 v[20:21], v[18:19], s[82:83], v[20:21]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[22:23], v[20:21], s[86:87], s[84:85]
	v_fma_f64 v[22:23], v[20:21], v[22:23], s[88:89]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[22:23], v[20:21], v[22:23], s[90:91]
	v_fma_f64 v[22:23], v[20:21], v[22:23], s[92:93]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[22:23], v[20:21], v[22:23], s[94:95]
	v_fma_f64 v[22:23], v[20:21], v[22:23], s[96:97]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[22:23], v[20:21], v[22:23], s[98:99]
	v_fma_f64 v[22:23], v[20:21], v[22:23], s[100:101]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f64 v[22:23], v[20:21], v[22:23], s[10:11]
	s_mul_i32 s11, s9, 3
	v_fma_f64 v[22:23], v[20:21], v[22:23], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[18:19], v[20:21], v[22:23], 1.0
	v_ldexp_f64 v[16:17], v[18:19], v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v1, 0x7ff00000, v17, s3
	v_cndmask_b32_e32 v12, 0, v16, vcc_lo
	v_cmp_neq_f64_e64 s3, 0, v[7:8]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v13, 0, v1, s4
	v_fma_f64 v[10:11], v[12:13], v[10:11], v[12:13]
	v_cmp_class_f64_e64 vcc_lo, v[12:13], 0x204
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v11, v11, v13 :: v_dual_cndmask_b32 v10, v10, v12
	v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[7:8]|
	v_cndmask_b32_e64 v8, 0, v30, s2
	v_mul_f64 v[10:11], |v[10:11]|, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e32 v1, 0x7ff80000, v11, vcc_lo
	s_and_b32 vcc_lo, s3, vcc_lo
	s_cmp_gt_i32 s9, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v10, 0, v10, vcc_lo
	s_cselect_b32 s10, -1, 0
	v_cndmask_b32_e64 v11, 0, v1, s3
	s_load_b128 s[0:3], s[0:1], 0x40
	v_add_f64 v[9:10], v[8:9], -v[10:11]
	v_mov_b32_e32 v7, 0
	v_mov_b32_e32 v8, 0
.LBB0_13:                               ; %.preheader
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_15 Depth 2
                                        ;       Child Loop BB0_16 Depth 3
                                        ;         Child Loop BB0_17 Depth 4
	s_and_not1_b32 vcc_lo, exec_lo, s10
	s_cbranch_vccnz .LBB0_22
; %bb.14:                               ; %.lr.ph
                                        ;   in Loop: Header=BB0_13 Depth=1
	s_mov_b32 s7, s5
	s_mov_b32 s4, 0
	s_lshl_b64 s[34:35], s[6:7], 3
	s_mov_b32 s7, s13
	s_add_u32 s34, s22, s34
	s_addc_u32 s35, s23, s35
	s_mov_b32 s15, s14
	s_load_b64 s[34:35], s[34:35], 0x0
	s_waitcnt vmcnt(1) lgkmcnt(0)
	v_add_f64 v[11:12], v[3:4], -s[34:35]
.LBB0_15:                               ;   Parent Loop BB0_13 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB0_16 Depth 3
                                        ;         Child Loop BB0_17 Depth 4
	s_lshl_b64 s[34:35], s[4:5], 3
	v_mov_b32_e32 v15, 0
	s_add_u32 s34, s24, s34
	s_addc_u32 s35, s25, s35
	v_mov_b32_e32 v16, 0xbff00000
	s_load_b64 s[34:35], s[34:35], 0x0
	s_mov_b32 s33, -1
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f64 v[13:14], v[5:6], -s[34:35]
	s_mov_b32 s34, s7
	s_delay_alu instid0(VALU_DEP_1)
	v_mul_f64 v[13:14], v[13:14], v[13:14]
.LBB0_16:                               ;   Parent Loop BB0_13 Depth=1
                                        ;     Parent Loop BB0_15 Depth=2
                                        ; =>    This Loop Header: Depth=3
                                        ;         Child Loop BB0_17 Depth 4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f64 v[17:18], -v[15:16], s[0:1], v[11:12]
	s_mov_b32 s35, 0
	v_fma_f64 v[17:18], v[17:18], v[17:18], v[13:14]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_gt_f64_e32 vcc_lo, 0x10000000, v[17:18]
	v_cndmask_b32_e64 v1, 0, 1, vcc_lo
	v_lshlrev_b32_e32 v1, 8, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_ldexp_f64 v[17:18], v[17:18], v1
	v_cndmask_b32_e64 v1, 0, 0xffffff80, vcc_lo
	v_rsq_f64_e32 v[19:20], v[17:18]
	v_cmp_class_f64_e64 vcc_lo, v[17:18], 0x260
	s_waitcnt_depctr 0xfff
	v_mul_f64 v[21:22], v[17:18], v[19:20]
	v_mul_f64 v[19:20], v[19:20], 0.5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[23:24], -v[19:20], v[21:22], 0.5
	v_fma_f64 v[21:22], v[21:22], v[23:24], v[21:22]
	v_fma_f64 v[19:20], v[19:20], v[23:24], v[19:20]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[23:24], -v[21:22], v[21:22], v[17:18]
	v_fma_f64 v[21:22], v[23:24], v[19:20], v[21:22]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[23:24], -v[21:22], v[21:22], v[17:18]
	v_fma_f64 v[19:20], v[23:24], v[19:20], v[21:22]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ldexp_f64 v[19:20], v[19:20], v1
	v_dual_cndmask_b32 v18, v20, v18 :: v_dual_cndmask_b32 v17, v19, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[17:18], v[17:18], -s[2:3]
	v_mul_f64 v[17:18], v[9:10], v[17:18]
.LBB0_17:                               ;   Parent Loop BB0_13 Depth=1
                                        ;     Parent Loop BB0_15 Depth=2
                                        ;       Parent Loop BB0_16 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	s_add_i32 s36, s15, s35
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_ashr_i32 s37, s36, 31
	s_lshl_b64 s[36:37], s[36:37], 3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	s_add_u32 s36, s26, s36
	s_addc_u32 s37, s27, s37
	s_load_b64 s[36:37], s[36:37], 0x0
	s_waitcnt lgkmcnt(0)
	v_cmp_nle_f64_e64 s36, s[36:37], s[30:31]
	s_and_b32 vcc_lo, exec_lo, s36
	s_cbranch_vccnz .LBB0_19
; %bb.18:                               ;   in Loop: Header=BB0_17 Depth=4
	s_add_i32 s36, s34, s35
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_ashr_i32 s37, s36, 31
	s_lshl_b64 s[36:37], s[36:37], 3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	s_add_u32 s36, s28, s36
	s_addc_u32 s37, s29, s37
	s_load_b64 s[36:37], s[36:37], 0x0
	s_waitcnt lgkmcnt(0)
	v_mul_f64 v[19:20], v[17:18], s[36:37]
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[7:8], s[36:37], v[19:20], v[7:8]
.LBB0_19:                               ;   in Loop: Header=BB0_17 Depth=4
	s_add_i32 s35, s35, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u32 s35, 3
	s_cbranch_scc1 .LBB0_17
; %bb.20:                               ;   in Loop: Header=BB0_16 Depth=3
	v_add_f64 v[15:16], v[15:16], 1.0
	s_add_i32 s33, s33, 1
	s_add_i32 s34, s34, 3
	s_cmp_lg_u32 s33, 2
	s_cbranch_scc1 .LBB0_16
; %bb.21:                               ;   in Loop: Header=BB0_15 Depth=2
	s_add_i32 s4, s4, 1
	s_add_i32 s15, s15, 3
	s_add_i32 s7, s7, 9
	s_cmp_lg_u32 s4, s9
	s_cbranch_scc1 .LBB0_15
.LBB0_22:                               ; %._crit_edge
                                        ;   in Loop: Header=BB0_13 Depth=1
	s_add_i32 s6, s6, 1
	s_add_i32 s14, s14, s11
	s_add_i32 s13, s13, s12
	s_cmp_lg_u32 s6, s8
	s_cbranch_scc1 .LBB0_13
	s_branch .LBB0_24
.LBB0_23:
	v_mov_b32_e32 v7, 0
	v_mov_b32_e32 v8, 0
.LBB0_24:                               ; %Flow153
	s_load_b128 s[4:7], s[18:19], 0x0
	s_waitcnt lgkmcnt(0)
	s_load_b128 s[0:3], s[20:21], 0x0
	s_waitcnt vmcnt(0)
	v_mul_f64 v[5:6], v[5:6], v[5:6]
	v_add_f64 v[9:10], s[6:7], -s[4:5]
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[11:12], s[2:3], -s[0:1]
	s_mov_b32 s0, 0xc9be45de
	s_mov_b32 s1, 0x4043bd3c
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[3:4], v[3:4], v[3:4], v[5:6]
	v_mul_f64 v[9:10], v[9:10], v[11:12]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f64 v[11:12], null, s[0:1], s[0:1], v[9:10]
	v_div_scale_f64 v[17:18], vcc_lo, v[9:10], s[0:1], v[9:10]
	v_rcp_f64_e32 v[13:14], v[11:12]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[15:16], -v[11:12], v[13:14], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[13:14], v[13:14], v[15:16], v[13:14]
	v_fma_f64 v[15:16], -v[11:12], v[13:14], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[13:14], v[13:14], v[15:16], v[13:14]
	v_mul_f64 v[15:16], v[17:18], v[13:14]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[11:12], -v[11:12], v[15:16], v[17:18]
	v_div_fmas_f64 v[11:12], v[11:12], v[13:14], v[15:16]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f64 v[9:10], v[11:12], s[0:1], v[9:10]
	v_fma_f64 v[3:4], v[9:10], v[7:8], v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[5:6], null, v0, s9, v[2:3]
	v_ashrrev_i32_e32 v6, 31, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 3, v[5:6]
	v_add_co_u32 v0, vcc_lo, s16, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s17, v1, vcc_lo
	global_store_b64 v[0:1], v[3:4], off
.LBB0_25:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z16epsilon_of_p_GPUPdS_S_S_S_S_S_ddddiii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 360
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 43
		.amdhsa_next_free_sgpr 102
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z16epsilon_of_p_GPUPdS_S_S_S_S_S_ddddiii, .Lfunc_end0-_Z16epsilon_of_p_GPUPdS_S_S_S_S_S_ddddiii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 7104
; NumSgprs: 104
; NumVgprs: 43
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 12
; VGPRBlocks: 5
; NumSGPRsForWavesPerEU: 104
; NumVGPRsForWavesPerEU: 43
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z10h_of_p_GPUPdS_S_S_S_S_S_ddddiii ; -- Begin function _Z10h_of_p_GPUPdS_S_S_S_S_S_ddddiii
	.globl	_Z10h_of_p_GPUPdS_S_S_S_S_S_ddddiii
	.p2align	8
	.type	_Z10h_of_p_GPUPdS_S_S_S_S_S_ddddiii,@function
_Z10h_of_p_GPUPdS_S_S_S_S_S_ddddiii:    ; @_Z10h_of_p_GPUPdS_S_S_S_S_S_ddddiii
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x74
	s_load_b64 s[4:5], s[0:1], 0x50
	v_and_b32_e32 v2, 0x3ff, v0
	v_bfe_u32 v4, v0, 10, 10
	s_load_b512 s[16:31], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s3, s2, 0xffff
	s_lshr_b32 s2, s2, 16
	v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
	v_mad_u64_u32 v[2:3], null, s15, s2, v[4:5]
	v_cmp_ngt_f64_e64 s3, 0x41d00000, |s[4:5]|
	v_trig_preop_f64 v[15:16], |s[4:5]|, 0
	v_trig_preop_f64 v[9:10], |s[4:5]|, 1
	v_cmp_le_f64_e64 s2, 0x7b000000, |s[4:5]|
	v_ashrrev_i32_e32 v1, 31, v0
	v_ldexp_f64 v[17:18], |s[4:5]|, 0xffffff80
	v_ashrrev_i32_e32 v3, 31, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[4:5], 3, v[0:1]
	v_lshlrev_b64 v[6:7], 3, v[2:3]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v3, vcc_lo, s18, v4
	v_add_co_ci_u32_e32 v4, vcc_lo, s19, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v5, vcc_lo, s20, v6
	v_add_co_ci_u32_e32 v6, vcc_lo, s21, v7, vcc_lo
	v_trig_preop_f64 v[7:8], |s[4:5]|, 2
	global_load_b64 v[3:4], v[3:4], off
	global_load_b64 v[5:6], v[5:6], off
	s_and_b32 vcc_lo, exec_lo, s3
	s_cbranch_vccz .LBB1_2
; %bb.1:
	s_and_b32 s6, s5, 0x7fffffff
	v_cndmask_b32_e64 v11, s4, v17, s2
	v_cndmask_b32_e64 v12, s6, v18, s2
	s_mov_b32 s6, 0
	s_mov_b32 s8, 0x54442d18
	s_mov_b32 s9, 0x3ff921fb
	s_mov_b32 s10, 0x33145c07
	v_mul_f64 v[13:14], v[15:16], v[11:12]
	v_mul_f64 v[19:20], v[9:10], v[11:12]
	v_mul_f64 v[31:32], v[7:8], v[11:12]
	s_mov_b32 s11, 0x3c91a626
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[21:22], v[15:16], v[11:12], -v[13:14]
	v_fma_f64 v[33:34], v[9:10], v[11:12], -v[19:20]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[11:12], v[7:8], v[11:12], -v[31:32]
	v_add_f64 v[23:24], v[19:20], v[21:22]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[25:26], v[23:24], -v[19:20]
	v_add_f64 v[29:30], v[13:14], v[23:24]
	v_add_f64 v[27:28], v[23:24], -v[25:26]
	v_add_f64 v[21:22], v[21:22], -v[25:26]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_ldexp_f64 v[25:26], v[29:30], -2
	v_add_f64 v[13:14], v[29:30], -v[13:14]
	v_add_f64 v[19:20], v[19:20], -v[27:28]
	v_add_f64 v[27:28], v[31:32], v[33:34]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[25:26]|
	v_add_f64 v[13:14], v[23:24], -v[13:14]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[19:20], v[21:22], v[19:20]
	v_fract_f64_e32 v[21:22], v[25:26]
	v_add_f64 v[23:24], v[27:28], v[19:20]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_cndmask_b32 v22, 0, v22 :: v_dual_cndmask_b32 v21, 0, v21
	v_ldexp_f64 v[21:22], v[21:22], 2
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[25:26], v[13:14], v[23:24]
	v_add_f64 v[35:36], v[23:24], -v[27:28]
	v_add_f64 v[29:30], v[25:26], v[21:22]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_add_f64 v[41:42], v[23:24], -v[35:36]
	v_add_f64 v[19:20], v[19:20], -v[35:36]
	v_add_f64 v[13:14], v[25:26], -v[13:14]
	v_cmp_gt_f64_e32 vcc_lo, 0, v[29:30]
	v_add_f64 v[29:30], v[27:28], -v[31:32]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_add_f64 v[13:14], v[23:24], -v[13:14]
	s_and_b32 s2, vcc_lo, exec_lo
	s_cselect_b32 s7, 0x40100000, 0
	v_add_f64 v[39:40], v[27:28], -v[29:30]
	v_add_f64 v[21:22], v[21:22], s[6:7]
	v_add_f64 v[29:30], v[33:34], -v[29:30]
	v_add_f64 v[27:28], v[27:28], -v[41:42]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[33:34], v[31:32], -v[39:40]
	v_add_f64 v[37:38], v[25:26], v[21:22]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[19:20], v[19:20], v[27:28]
	v_add_f64 v[29:30], v[29:30], v[33:34]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_i32_f64_e32 v1, v[37:38]
	v_add_f64 v[19:20], v[29:30], v[19:20]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_f64_i32_e32 v[35:36], v1
	v_add_f64 v[11:12], v[11:12], v[19:20]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[21:22], v[21:22], -v[35:36]
	v_add_f64 v[11:12], v[13:14], v[11:12]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[27:28], v[25:26], v[21:22]
	v_add_f64 v[19:20], v[27:28], -v[21:22]
	v_cmp_le_f64_e32 vcc_lo, 0.5, v[27:28]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_add_f64 v[13:14], v[25:26], -v[19:20]
	s_and_b32 s2, vcc_lo, exec_lo
	s_cselect_b32 s7, 0x3ff00000, 0
	v_add_co_ci_u32_e64 v1, s2, 0, v1, vcc_lo
	v_add_f64 v[11:12], v[11:12], v[13:14]
	v_add_f64 v[13:14], v[27:28], -s[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[19:20], v[13:14], v[11:12]
	v_mul_f64 v[21:22], v[19:20], s[8:9]
	v_add_f64 v[13:14], v[19:20], -v[13:14]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[23:24], v[19:20], s[8:9], -v[21:22]
	v_add_f64 v[11:12], v[11:12], -v[13:14]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[13:14], v[19:20], s[10:11], v[23:24]
	v_fma_f64 v[13:14], v[11:12], s[8:9], v[13:14]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[11:12], v[21:22], v[13:14]
	v_add_f64 v[19:20], v[11:12], -v[21:22]
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[13:14], v[13:14], -v[19:20]
	s_branch .LBB1_3
.LBB1_2:
	s_mov_b32 s6, -1
                                        ; implicit-def: $vgpr1
                                        ; implicit-def: $vgpr11_vgpr12
                                        ; implicit-def: $vgpr13_vgpr14
.LBB1_3:                                ; %Flow170
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s6
	s_cbranch_vccnz .LBB1_5
; %bb.4:
	s_mov_b32 s6, 0x6dc9c883
	s_mov_b32 s7, 0x3fe45f30
	s_mov_b32 s9, 0xbc91a626
	v_mul_f64 v[11:12], |s[4:5]|, s[6:7]
	s_mov_b32 s6, 0x54442d18
	s_mov_b32 s7, 0xbff921fb
	s_mov_b32 s8, 0x33145c00
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f64_e32 v[19:20], v[11:12]
	v_fma_f64 v[11:12], v[19:20], s[6:7], |s[4:5]|
	v_mul_f64 v[13:14], v[19:20], s[8:9]
	s_mov_b32 s6, 0x252049c0
	s_mov_b32 s7, 0xb97b839a
	v_cvt_i32_f64_e32 v1, v[19:20]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[23:24], v[19:20], s[8:9], v[11:12]
	v_add_f64 v[21:22], v[11:12], v[13:14]
	s_mov_b32 s9, 0x3c91a626
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[11:12], v[11:12], -v[21:22]
	v_add_f64 v[21:22], v[21:22], -v[23:24]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[11:12], v[11:12], v[13:14]
	v_fma_f64 v[13:14], v[19:20], s[8:9], v[13:14]
	v_add_f64 v[11:12], v[21:22], v[11:12]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[11:12], v[11:12], -v[13:14]
	v_fma_f64 v[13:14], v[19:20], s[6:7], v[11:12]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[11:12], v[23:24], v[13:14]
	v_add_f64 v[21:22], v[11:12], -v[23:24]
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[13:14], v[13:14], -v[21:22]
.LBB1_5:                                ; %_ZL3cosd.exit
	s_and_b32 vcc_lo, exec_lo, s3
	s_cbranch_vccz .LBB1_7
; %bb.6:
	v_cmp_le_f64_e64 vcc_lo, 0x7b000000, |s[4:5]|
	s_and_b32 s2, s5, 0x7fffffff
	s_mov_b32 s6, 0x54442d18
	s_mov_b32 s7, 0x3ff921fb
	s_mov_b32 s8, 0x33145c07
	s_mov_b32 s9, 0x3c91a626
	v_cndmask_b32_e32 v18, s2, v18, vcc_lo
	v_cndmask_b32_e32 v17, s4, v17, vcc_lo
	s_mov_b32 s2, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_mul_f64 v[19:20], v[15:16], v[17:18]
	v_mul_f64 v[21:22], v[9:10], v[17:18]
	v_mul_f64 v[31:32], v[7:8], v[17:18]
	v_fma_f64 v[15:16], v[15:16], v[17:18], -v[19:20]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[9:10], v[9:10], v[17:18], -v[21:22]
	v_fma_f64 v[7:8], v[7:8], v[17:18], -v[31:32]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[23:24], v[21:22], v[15:16]
	v_add_f64 v[25:26], v[23:24], -v[21:22]
	v_add_f64 v[29:30], v[19:20], v[23:24]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[27:28], v[23:24], -v[25:26]
	v_add_f64 v[15:16], v[15:16], -v[25:26]
	v_ldexp_f64 v[25:26], v[29:30], -2
	v_add_f64 v[19:20], v[29:30], -v[19:20]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f64 v[21:22], v[21:22], -v[27:28]
	v_add_f64 v[27:28], v[31:32], v[9:10]
	v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[25:26]|
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[19:20], v[23:24], -v[19:20]
	v_add_f64 v[15:16], v[15:16], v[21:22]
	v_fract_f64_e32 v[21:22], v[25:26]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[23:24], v[27:28], v[15:16]
	v_dual_cndmask_b32 v22, 0, v22 :: v_dual_cndmask_b32 v21, 0, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_ldexp_f64 v[21:22], v[21:22], 2
	v_add_f64 v[25:26], v[19:20], v[23:24]
	v_add_f64 v[33:34], v[23:24], -v[27:28]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[29:30], v[25:26], v[21:22]
	v_add_f64 v[39:40], v[23:24], -v[33:34]
	v_add_f64 v[15:16], v[15:16], -v[33:34]
	v_add_f64 v[17:18], v[25:26], -v[19:20]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cmp_gt_f64_e32 vcc_lo, 0, v[29:30]
	v_add_f64 v[29:30], v[27:28], -v[31:32]
	v_add_f64 v[17:18], v[23:24], -v[17:18]
	s_and_b32 s3, vcc_lo, exec_lo
	s_cselect_b32 s3, 0x40100000, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_add_f64 v[37:38], v[27:28], -v[29:30]
	v_add_f64 v[21:22], v[21:22], s[2:3]
	v_add_f64 v[9:10], v[9:10], -v[29:30]
	v_add_f64 v[27:28], v[27:28], -v[39:40]
	v_add_f64 v[29:30], v[31:32], -v[37:38]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[35:36], v[25:26], v[21:22]
	v_add_f64 v[15:16], v[15:16], v[27:28]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[9:10], v[9:10], v[29:30]
	v_cvt_i32_f64_e32 v35, v[35:36]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[9:10], v[9:10], v[15:16]
	v_cvt_f64_i32_e32 v[33:34], v35
	v_readfirstlane_b32 s3, v35
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[7:8], v[7:8], v[9:10]
	v_add_f64 v[21:22], v[21:22], -v[33:34]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[7:8], v[17:18], v[7:8]
	v_add_f64 v[15:16], v[25:26], v[21:22]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[9:10], v[15:16], -v[21:22]
	v_cmp_le_f64_e32 vcc_lo, 0.5, v[15:16]
	v_add_f64 v[9:10], v[25:26], -v[9:10]
	s_cmp_lg_u32 vcc_lo, 0
	s_addc_u32 s33, s3, 0
	s_and_b32 s3, vcc_lo, exec_lo
	s_cselect_b32 s3, 0x3ff00000, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f64 v[7:8], v[7:8], v[9:10]
	v_add_f64 v[9:10], v[15:16], -s[2:3]
	v_add_f64 v[15:16], v[9:10], v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_f64 v[17:18], v[15:16], s[6:7]
	v_add_f64 v[9:10], v[15:16], -v[9:10]
	v_fma_f64 v[19:20], v[15:16], s[6:7], -v[17:18]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[7:8], v[7:8], -v[9:10]
	v_fma_f64 v[9:10], v[15:16], s[8:9], v[19:20]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[9:10], v[7:8], s[6:7], v[9:10]
	v_add_f64 v[7:8], v[17:18], v[9:10]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[15:16], v[7:8], -v[17:18]
	v_add_f64 v[9:10], v[9:10], -v[15:16]
	s_branch .LBB1_8
.LBB1_7:
	s_mov_b32 s2, -1
                                        ; implicit-def: $sgpr33
                                        ; implicit-def: $vgpr7_vgpr8
                                        ; implicit-def: $vgpr9_vgpr10
.LBB1_8:                                ; %Flow169
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s2
	s_cbranch_vccnz .LBB1_10
; %bb.9:
	s_mov_b32 s2, 0x6dc9c883
	s_mov_b32 s3, 0x3fe45f30
	s_mov_b32 s7, 0xbc91a626
	v_mul_f64 v[7:8], |s[4:5]|, s[2:3]
	s_mov_b32 s2, 0x54442d18
	s_mov_b32 s3, 0xbff921fb
	s_mov_b32 s6, 0x33145c00
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f64_e32 v[9:10], v[7:8]
	v_fma_f64 v[7:8], v[9:10], s[2:3], |s[4:5]|
	v_mul_f64 v[15:16], v[9:10], s[6:7]
	s_mov_b32 s2, 0x252049c0
	s_mov_b32 s3, 0xb97b839a
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[21:22], v[9:10], s[6:7], v[7:8]
	v_add_f64 v[17:18], v[7:8], v[15:16]
	s_mov_b32 s7, 0x3c91a626
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[19:20], v[7:8], -v[17:18]
	v_add_f64 v[17:18], v[17:18], -v[21:22]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_add_f64 v[7:8], v[19:20], v[15:16]
	v_fma_f64 v[15:16], v[9:10], s[6:7], v[15:16]
	v_cvt_i32_f64_e32 v19, v[9:10]
	v_add_f64 v[7:8], v[17:18], v[7:8]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s33, v19
	v_add_f64 v[7:8], v[7:8], -v[15:16]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[15:16], v[9:10], s[2:3], v[7:8]
	v_add_f64 v[7:8], v[21:22], v[15:16]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[17:18], v[7:8], -v[21:22]
	v_add_f64 v[9:10], v[15:16], -v[17:18]
.LBB1_10:                               ; %_ZL3sind.exit
	s_load_b64 s[8:9], s[0:1], 0x58
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_i32_e32 vcc_lo, s8, v0
	v_cmp_gt_i32_e64 s2, s9, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, vcc_lo, s2
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB1_23
; %bb.11:                               ; %.preheader108
	s_cmp_lt_i32 s8, 1
	s_cbranch_scc1 .LBB1_21
; %bb.12:                               ; %.preheader.lr.ph
	v_mul_f64 v[15:16], v[11:12], v[11:12]
	s_mov_b32 s10, 0xb42fdfa7
	s_mov_b32 s12, 0xf9a43bb8
	s_mov_b32 s11, 0xbe5ae600
	s_mov_b32 s13, 0x3de5e0b2
	s_mov_b32 s34, 0x796cde01
	s_mov_b32 s35, 0x3ec71de3
	s_mov_b32 s14, 0x9037ab78
	s_mov_b32 s36, 0x46cc5e42
	s_mov_b32 s15, 0x3e21eeb6
	s_mov_b32 s37, 0xbda907db
	s_mov_b32 s40, 0x19e83e5c
	s_mov_b32 s41, 0xbf2a01a0
	s_mov_b32 s44, 0xa17f65f6
	s_mov_b32 s45, 0xbe927e4f
	s_mov_b32 s42, 0x11110bb3
	s_mov_b32 s43, 0x3f811111
	s_delay_alu instid0(VALU_DEP_4)
	v_mul_f64 v[25:26], v[13:14], 0.5
	s_mov_b32 s46, 0x19f4ec90
	s_mov_b32 s47, 0x3efa01a0
	s_mov_b32 s54, 0x16c16967
	s_mov_b32 s55, 0xbf56c16c
	s_mov_b32 s48, 0x55555555
	s_mov_b32 s49, 0x3fa55555
	s_mov_b32 s39, 0xbfc55555
	s_mov_b32 s38, s48
	v_cmp_class_f64_e64 vcc_lo, s[4:5], 0x1f8
	s_mov_b32 s7, 0x3fe55555
	s_mov_b32 s6, s48
	s_mov_b32 s50, 0x968915a9
	s_mov_b32 s52, 0x4222de17
	s_mov_b32 s51, 0x3fba6564
	s_mov_b32 s53, 0x3fbdee67
	s_mov_b32 s56, 0x3abe935a
	s_mov_b32 s57, 0x3fbe25e4
	s_mov_b32 s58, 0x47e6c9c2
	s_mov_b32 s59, 0x3fc110ef
	s_mov_b32 s60, 0xcfa74449
	v_fma_f64 v[17:18], v[15:16], s[12:13], s[10:11]
	v_mul_f64 v[21:22], v[15:16], 0.5
	v_fma_f64 v[19:20], v[15:16], s[36:37], s[14:15]
	v_mul_f64 v[27:28], v[11:12], -v[15:16]
	s_mov_b32 s61, 0x3fc3b13b
	s_mov_b32 s62, 0x71bf3c30
	s_mov_b32 s63, 0x3fc745d1
	s_mov_b32 s64, 0x1c7792ce
	s_mov_b32 s65, 0x3fcc71c7
	s_mov_b32 s66, 0x924920da
	s_mov_b32 s67, 0x3fd24924
	s_mov_b32 s68, 0x9999999c
	s_mov_b32 s69, 0x3fd99999
	s_mov_b32 s71, 0xbfe55555
	s_mov_b32 s70, s48
	s_mov_b32 s72, 0xd5df274d
	s_mov_b32 s73, 0x3c8543b0
	s_mov_b32 s74, 0xfefa39ef
	s_mov_b32 s75, 0x3fe62e42
	s_mov_b32 s78, 0x3b39803f
	s_mov_b32 s79, 0x3c7abc9e
	s_mov_b32 s76, 0x652b82fe
	s_mov_b32 s77, 0x3ff71547
	s_mov_b32 s81, 0xbfe62e42
	s_mov_b32 s80, s74
	s_mov_b32 s83, 0xbc7abc9e
	s_mov_b32 s82, s78
	s_mov_b32 s84, 0xfca7ab0c
	s_mov_b32 s86, 0x6a5dcb37
	s_mov_b32 s85, 0x3e928af3
	s_mov_b32 s87, 0x3e5ade15
	s_mov_b32 s88, 0x623fde64
	s_mov_b32 s89, 0x3ec71dee
	s_mov_b32 s90, 0x7c89e6b0
	s_mov_b32 s91, 0x3efa0199
	s_mov_b32 s92, 0x14761f6e
	s_mov_b32 s93, 0x3f2a01a0
	s_mov_b32 s94, 0x1852b7b0
	v_fma_f64 v[17:18], v[15:16], v[17:18], s[34:35]
	v_add_f64 v[23:24], -v[21:22], 1.0
	v_fma_f64 v[19:20], v[15:16], v[19:20], s[44:45]
	s_mov_b32 s95, 0x3f56c16c
	s_mov_b32 s96, 0x11122322
	s_mov_b32 s97, s43
	s_mov_b32 s98, 0x555502a1
	s_mov_b32 s99, s49
	s_mov_b32 s100, 0x55555511
	s_mov_b32 s101, 0x3fc55555
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[17:18], v[15:16], v[17:18], s[40:41]
	v_add_f64 v[29:30], -v[23:24], 1.0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[19:20], v[15:16], v[19:20], s[46:47]
	v_fma_f64 v[17:18], v[15:16], v[17:18], s[42:43]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[21:22], v[29:30], -v[21:22]
	v_fma_f64 v[19:20], v[15:16], v[19:20], s[54:55]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[17:18], v[27:28], v[17:18], v[25:26]
	v_fma_f64 v[21:22], v[11:12], -v[13:14], v[21:22]
	v_mul_f64 v[25:26], v[15:16], v[15:16]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[19:20], v[15:16], v[19:20], s[48:49]
	v_fma_f64 v[13:14], v[15:16], v[17:18], -v[13:14]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[15:16], v[25:26], v[19:20], v[21:22]
	v_fma_f64 v[13:14], v[27:28], s[38:39], v[13:14]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[15:16], v[23:24], v[15:16]
	v_add_f64 v[11:12], v[11:12], -v[13:14]
	v_and_b32_e32 v13, 1, v1
	v_lshlrev_b32_e32 v1, 30, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_eq_u32_e64 s2, 0, v13
	v_and_b32_e32 v1, 0x80000000, v1
	v_xor_b32_e32 v12, 0x80000000, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v11, v11, v15, s2
	v_cndmask_b32_e64 v12, v12, v16, s2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v11, 0, v11, vcc_lo
	v_xor_b32_e32 v1, v12, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v12, 0x7ff80000, v1, vcc_lo
	v_frexp_mant_f64_e64 v[13:14], |v[11:12]|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_gt_f64_e64 s2, s[6:7], v[13:14]
	v_cndmask_b32_e64 v1, 0, 1, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_ldexp_f64 v[13:14], v[13:14], v1
	v_frexp_exp_i32_f64_e32 v1, v[11:12]
	v_add_f64 v[15:16], v[13:14], 1.0
	v_add_f64 v[21:22], v[13:14], -1.0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_subrev_co_ci_u32_e64 v1, s2, 0, v1, s2
	v_rcp_f64_e32 v[17:18], v[15:16]
	v_add_f64 v[23:24], v[15:16], -1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_f64 v[13:14], v[13:14], -v[23:24]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[19:20], -v[15:16], v[17:18], 1.0
	v_fma_f64 v[17:18], v[19:20], v[17:18], v[17:18]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[19:20], -v[15:16], v[17:18], 1.0
	v_fma_f64 v[17:18], v[19:20], v[17:18], v[17:18]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[19:20], v[21:22], v[17:18]
	v_mul_f64 v[25:26], v[15:16], v[19:20]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[15:16], v[19:20], v[15:16], -v[25:26]
	v_fma_f64 v[13:14], v[19:20], v[13:14], v[15:16]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[15:16], v[25:26], v[13:14]
	v_add_f64 v[23:24], v[21:22], -v[15:16]
	v_add_f64 v[25:26], v[15:16], -v[25:26]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[21:22], v[21:22], -v[23:24]
	v_add_f64 v[13:14], v[25:26], -v[13:14]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[15:16], v[21:22], -v[15:16]
	v_add_f64 v[13:14], v[13:14], v[15:16]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[13:14], v[23:24], v[13:14]
	v_mul_f64 v[13:14], v[17:18], v[13:14]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[15:16], v[19:20], v[13:14]
	v_add_f64 v[17:18], v[15:16], -v[19:20]
	v_mul_f64 v[19:20], v[15:16], v[15:16]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[13:14], v[13:14], -v[17:18]
	v_fma_f64 v[17:18], v[15:16], v[15:16], -v[19:20]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[21:22], v[13:14], v[13:14]
	v_fma_f64 v[17:18], v[15:16], v[21:22], v[17:18]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[21:22], v[19:20], v[17:18]
	v_fma_f64 v[23:24], v[21:22], s[52:53], s[50:51]
	v_add_f64 v[19:20], v[21:22], -v[19:20]
	v_mul_f64 v[29:30], v[15:16], v[21:22]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[23:24], v[21:22], v[23:24], s[56:57]
	v_add_f64 v[17:18], v[17:18], -v[19:20]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[23:24], v[21:22], v[23:24], s[58:59]
	v_fma_f64 v[23:24], v[21:22], v[23:24], s[60:61]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[23:24], v[21:22], v[23:24], s[62:63]
	v_fma_f64 v[23:24], v[21:22], v[23:24], s[64:65]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[23:24], v[21:22], v[23:24], s[66:67]
	v_fma_f64 v[23:24], v[21:22], v[23:24], s[68:69]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[25:26], v[21:22], v[23:24]
	v_fma_f64 v[19:20], v[21:22], v[23:24], -v[25:26]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[19:20], v[17:18], v[23:24], v[19:20]
	v_add_f64 v[23:24], v[25:26], v[19:20]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[27:28], v[23:24], s[6:7]
	v_add_f64 v[25:26], v[23:24], -v[25:26]
	v_add_f64 v[31:32], v[27:28], s[70:71]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[19:20], v[19:20], -v[25:26]
	v_fma_f64 v[25:26], v[21:22], v[15:16], -v[29:30]
	v_add_f64 v[23:24], v[23:24], -v[31:32]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[19:20], v[19:20], s[72:73]
	v_fma_f64 v[21:22], v[21:22], v[13:14], v[25:26]
	v_ldexp_f64 v[13:14], v[13:14], 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[19:20], v[19:20], v[23:24]
	v_fma_f64 v[17:18], v[17:18], v[15:16], v[21:22]
	v_ldexp_f64 v[15:16], v[15:16], 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[21:22], v[27:28], v[19:20]
	v_add_f64 v[23:24], v[29:30], v[17:18]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[25:26], v[27:28], -v[21:22]
	v_mul_f64 v[27:28], v[23:24], v[21:22]
	v_add_f64 v[29:30], v[23:24], -v[29:30]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[19:20], v[19:20], v[25:26]
	v_fma_f64 v[25:26], v[23:24], v[21:22], -v[27:28]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[17:18], v[17:18], -v[29:30]
	v_fma_f64 v[19:20], v[23:24], v[19:20], v[25:26]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f64 v[17:18], v[17:18], v[21:22], v[19:20]
	v_cvt_f64_i32_e32 v[21:22], v1
	v_add_f64 v[19:20], v[27:28], v[17:18]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f64 v[23:24], v[15:16], v[19:20]
	v_add_f64 v[25:26], v[19:20], -v[27:28]
	v_mul_f64 v[27:28], v[21:22], s[74:75]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[15:16], v[23:24], -v[15:16]
	v_add_f64 v[17:18], v[17:18], -v[25:26]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[25:26], v[21:22], s[74:75], -v[27:28]
	v_add_f64 v[15:16], v[19:20], -v[15:16]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[13:14], v[13:14], v[17:18]
	v_fma_f64 v[17:18], v[21:22], s[78:79], v[25:26]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[13:14], v[13:14], v[15:16]
	v_add_f64 v[15:16], v[27:28], v[17:18]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[19:20], v[23:24], v[13:14]
	v_add_f64 v[27:28], v[15:16], -v[27:28]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[21:22], v[15:16], v[19:20]
	v_add_f64 v[23:24], v[19:20], -v[23:24]
	v_add_f64 v[17:18], v[17:18], -v[27:28]
	v_mul_f64 v[27:28], v[7:8], v[7:8]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[25:26], v[21:22], -v[15:16]
	v_add_f64 v[13:14], v[13:14], -v[23:24]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_fma_f64 v[31:32], v[27:28], s[36:37], s[14:15]
	v_mul_f64 v[33:34], v[27:28], 0.5
	s_mov_b32 s14, 0
	s_mov_b32 s15, 0
	v_add_f64 v[29:30], v[21:22], -v[25:26]
	v_add_f64 v[19:20], v[19:20], -v[25:26]
	v_add_f64 v[23:24], v[17:18], v[13:14]
	v_fma_f64 v[31:32], v[27:28], v[31:32], s[44:45]
	v_add_f64 v[35:36], -v[33:34], 1.0
	v_add_f64 v[15:16], v[15:16], -v[29:30]
	v_fma_f64 v[29:30], v[27:28], s[12:13], s[10:11]
	s_mov_b32 s10, 11
	s_mov_b32 s11, 0x3fe00000
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[31:32], v[27:28], v[31:32], s[46:47]
	v_add_f64 v[37:38], -v[35:36], 1.0
	s_mul_i32 s12, s9, 9
	s_mul_i32 s13, s9, 3
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_add_f64 v[15:16], v[19:20], v[15:16]
	v_add_f64 v[19:20], v[23:24], -v[17:18]
	v_fma_f64 v[29:30], v[27:28], v[29:30], s[34:35]
	v_add_f64 v[15:16], v[23:24], v[15:16]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f64 v[23:24], v[23:24], -v[19:20]
	v_add_f64 v[13:14], v[13:14], -v[19:20]
	v_fma_f64 v[29:30], v[27:28], v[29:30], s[40:41]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[25:26], v[21:22], v[15:16]
	v_add_f64 v[17:18], v[17:18], -v[23:24]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[29:30], v[27:28], v[29:30], s[42:43]
	v_add_f64 v[19:20], v[25:26], -v[21:22]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[13:14], v[13:14], v[17:18]
	v_add_f64 v[15:16], v[15:16], -v[19:20]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[13:14], v[13:14], v[15:16]
	v_add_f64 v[15:16], v[25:26], v[13:14]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[17:18], v[15:16], -v[25:26]
	v_add_f64 v[19:20], v[15:16], v[15:16]
	v_add_f64 v[13:14], v[13:14], -v[17:18]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f64 v[15:16], v[15:16], 2.0, -v[19:20]
	v_cmp_class_f64_e64 s2, v[19:20], 0x204
	v_fma_f64 v[13:14], v[13:14], 2.0, v[15:16]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[15:16], v[19:20], v[13:14]
	v_cndmask_b32_e64 v18, v16, v20, s2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v17, v15, v19, s2
	v_add_f64 v[15:16], v[15:16], -v[19:20]
	v_mul_f64 v[21:22], v[17:18], s[76:77]
	v_cmp_nlt_f64_e64 s3, 0x40900000, v[17:18]
	v_cmp_neq_f64_e64 s2, 0x7ff00000, |v[17:18]|
	v_cmp_ngt_f64_e64 s4, 0xc090cc00, v[17:18]
	v_add_f64 v[13:14], v[13:14], -v[15:16]
	v_mul_f64 v[15:16], v[27:28], v[27:28]
	v_rndne_f64_e32 v[21:22], v[21:22]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v14, 0, v14, s2
	v_cndmask_b32_e64 v13, 0, v13, s2
	s_and_b32 s2, s4, s3
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f64 v[23:24], v[21:22], s[80:81], v[17:18]
	v_cvt_i32_f64_e32 v1, v[21:22]
	v_fma_f64 v[23:24], v[21:22], s[82:83], v[23:24]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[25:26], v[23:24], s[86:87], s[84:85]
	v_fma_f64 v[25:26], v[23:24], v[25:26], s[88:89]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[25:26], v[23:24], v[25:26], s[90:91]
	v_fma_f64 v[25:26], v[23:24], v[25:26], s[92:93]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[25:26], v[23:24], v[25:26], s[94:95]
	v_fma_f64 v[25:26], v[23:24], v[25:26], s[96:97]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[25:26], v[23:24], v[25:26], s[98:99]
	v_fma_f64 v[25:26], v[23:24], v[25:26], s[100:101]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[25:26], v[23:24], v[25:26], s[10:11]
	v_fma_f64 v[25:26], v[23:24], v[25:26], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_fma_f64 v[21:22], v[23:24], v[25:26], 1.0
	v_mul_f64 v[23:24], v[9:10], 0.5
	v_mul_f64 v[25:26], v[7:8], -v[27:28]
	v_ldexp_f64 v[19:20], v[21:22], v1
	v_fma_f64 v[21:22], v[27:28], v[31:32], s[54:55]
	v_add_f64 v[31:32], v[37:38], -v[33:34]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[23:24], v[25:26], v[29:30], v[23:24]
	v_cndmask_b32_e64 v1, 0x7ff00000, v20, s3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[17:18], v[27:28], v[21:22], s[48:49]
	v_fma_f64 v[20:21], v[7:8], -v[9:10], v[31:32]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_3)
	v_fma_f64 v[9:10], v[27:28], v[23:24], -v[9:10]
	v_cndmask_b32_e64 v22, 0, v19, s2
	v_cndmask_b32_e64 v23, 0, v1, s4
	v_cmp_neq_f64_e64 s3, 0x7ff00000, |v[11:12]|
	v_cmp_neq_f64_e64 s4, 0, v[11:12]
	v_fma_f64 v[13:14], v[22:23], v[13:14], v[22:23]
	v_cmp_class_f64_e64 s2, v[22:23], 0x204
	v_fma_f64 v[15:16], v[15:16], v[17:18], v[20:21]
	v_fma_f64 v[9:10], v[25:26], s[38:39], v[9:10]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v1, v14, v23, s2
	v_cndmask_b32_e64 v30, v13, v22, s2
	s_and_b32 s2, s4, s3
	s_bitcmp0_b32 s33, 0
	v_and_b32_e32 v1, 0x7fffffff, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v1, 0x7ff00000, v1, s3
	s_cselect_b32 s3, -1, 0
	v_add_f64 v[11:12], v[35:36], v[15:16]
	v_add_f64 v[7:8], v[7:8], -v[9:10]
	v_cndmask_b32_e64 v9, 0, v1, s4
	s_lshl_b32 s4, s33, 30
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v1, v11, v7, s3
	v_cndmask_b32_e64 v7, v12, v8, s3
	s_xor_b32 s3, s4, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s3, s3, 0x80000000
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_xor_b32_e32 v8, s3, v7
	v_cndmask_b32_e32 v7, 0, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v8, 0x7ff80000, v8, vcc_lo
	v_frexp_mant_f64_e64 v[10:11], |v[7:8]|
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_gt_f64_e32 vcc_lo, s[6:7], v[10:11]
	v_cndmask_b32_e64 v1, 0, 1, vcc_lo
	v_ldexp_f64 v[10:11], v[10:11], v1
	v_frexp_exp_i32_f64_e32 v1, v[7:8]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[12:13], v[10:11], 1.0
	v_add_f64 v[18:19], v[10:11], -1.0
	v_subrev_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[14:15], v[12:13]
	v_add_f64 v[20:21], v[12:13], -1.0
	v_add_f64 v[10:11], v[10:11], -v[20:21]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[16:17], -v[12:13], v[14:15], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[14:15], v[16:17], v[14:15], v[14:15]
	v_fma_f64 v[16:17], -v[12:13], v[14:15], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[14:15], v[16:17], v[14:15], v[14:15]
	v_mul_f64 v[16:17], v[18:19], v[14:15]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[22:23], v[12:13], v[16:17]
	v_fma_f64 v[12:13], v[16:17], v[12:13], -v[22:23]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[10:11], v[16:17], v[10:11], v[12:13]
	v_add_f64 v[12:13], v[22:23], v[10:11]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[20:21], v[18:19], -v[12:13]
	v_add_f64 v[22:23], v[12:13], -v[22:23]
	v_add_f64 v[18:19], v[18:19], -v[20:21]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[10:11], v[22:23], -v[10:11]
	v_add_f64 v[12:13], v[18:19], -v[12:13]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[10:11], v[10:11], v[12:13]
	v_add_f64 v[10:11], v[20:21], v[10:11]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[10:11], v[14:15], v[10:11]
	v_add_f64 v[12:13], v[16:17], v[10:11]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[14:15], v[12:13], -v[16:17]
	v_mul_f64 v[16:17], v[12:13], v[12:13]
	v_add_f64 v[10:11], v[10:11], -v[14:15]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[14:15], v[12:13], v[12:13], -v[16:17]
	v_add_f64 v[18:19], v[10:11], v[10:11]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[14:15], v[12:13], v[18:19], v[14:15]
	v_add_f64 v[18:19], v[16:17], v[14:15]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_fma_f64 v[20:21], v[18:19], s[52:53], s[50:51]
	v_add_f64 v[16:17], v[18:19], -v[16:17]
	v_mul_f64 v[26:27], v[12:13], v[18:19]
	v_fma_f64 v[20:21], v[18:19], v[20:21], s[56:57]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[14:15], v[14:15], -v[16:17]
	v_fma_f64 v[20:21], v[18:19], v[20:21], s[58:59]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[20:21], v[18:19], v[20:21], s[60:61]
	v_fma_f64 v[20:21], v[18:19], v[20:21], s[62:63]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[20:21], v[18:19], v[20:21], s[64:65]
	v_fma_f64 v[20:21], v[18:19], v[20:21], s[66:67]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[20:21], v[18:19], v[20:21], s[68:69]
	v_mul_f64 v[22:23], v[18:19], v[20:21]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[16:17], v[18:19], v[20:21], -v[22:23]
	v_fma_f64 v[16:17], v[14:15], v[20:21], v[16:17]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[20:21], v[22:23], v[16:17]
	v_add_f64 v[24:25], v[20:21], s[6:7]
	v_add_f64 v[22:23], v[20:21], -v[22:23]
	s_load_b128 s[4:7], s[0:1], 0x40
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[28:29], v[24:25], s[70:71]
	v_add_f64 v[16:17], v[16:17], -v[22:23]
	v_fma_f64 v[22:23], v[18:19], v[12:13], -v[26:27]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[20:21], v[20:21], -v[28:29]
	v_add_f64 v[16:17], v[16:17], s[72:73]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fma_f64 v[18:19], v[18:19], v[10:11], v[22:23]
	v_ldexp_f64 v[10:11], v[10:11], 1
	v_add_f64 v[16:17], v[16:17], v[20:21]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fma_f64 v[14:15], v[14:15], v[12:13], v[18:19]
	v_ldexp_f64 v[12:13], v[12:13], 1
	v_add_f64 v[18:19], v[24:25], v[16:17]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[20:21], v[26:27], v[14:15]
	v_add_f64 v[22:23], v[24:25], -v[18:19]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_f64 v[24:25], v[20:21], v[18:19]
	v_add_f64 v[26:27], v[20:21], -v[26:27]
	v_add_f64 v[16:17], v[16:17], v[22:23]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[22:23], v[20:21], v[18:19], -v[24:25]
	v_add_f64 v[14:15], v[14:15], -v[26:27]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[16:17], v[20:21], v[16:17], v[22:23]
	v_fma_f64 v[14:15], v[14:15], v[18:19], v[16:17]
	v_cvt_f64_i32_e32 v[18:19], v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[16:17], v[24:25], v[14:15]
	v_add_f64 v[20:21], v[12:13], v[16:17]
	v_add_f64 v[22:23], v[16:17], -v[24:25]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f64 v[24:25], v[18:19], s[74:75]
	v_add_f64 v[12:13], v[20:21], -v[12:13]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[14:15], v[14:15], -v[22:23]
	v_fma_f64 v[22:23], v[18:19], s[74:75], -v[24:25]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[12:13], v[16:17], -v[12:13]
	v_add_f64 v[10:11], v[10:11], v[14:15]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[14:15], v[18:19], s[78:79], v[22:23]
	v_add_f64 v[10:11], v[10:11], v[12:13]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[12:13], v[24:25], v[14:15]
	v_add_f64 v[16:17], v[20:21], v[10:11]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[24:25], v[12:13], -v[24:25]
	v_add_f64 v[18:19], v[12:13], v[16:17]
	v_add_f64 v[20:21], v[16:17], -v[20:21]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_add_f64 v[14:15], v[14:15], -v[24:25]
	s_waitcnt lgkmcnt(0)
	v_mul_f64 v[24:25], s[4:5], s[4:5]
	v_add_f64 v[22:23], v[18:19], -v[12:13]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[10:11], v[10:11], -v[20:21]
	v_add_f64 v[26:27], v[18:19], -v[22:23]
	v_add_f64 v[16:17], v[16:17], -v[22:23]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[20:21], v[14:15], v[10:11]
	v_add_f64 v[12:13], v[12:13], -v[26:27]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[12:13], v[16:17], v[12:13]
	v_add_f64 v[16:17], v[20:21], -v[14:15]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[12:13], v[20:21], v[12:13]
	v_add_f64 v[20:21], v[20:21], -v[16:17]
	v_add_f64 v[10:11], v[10:11], -v[16:17]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[22:23], v[18:19], v[12:13]
	v_add_f64 v[14:15], v[14:15], -v[20:21]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[16:17], v[22:23], -v[18:19]
	v_add_f64 v[10:11], v[10:11], v[14:15]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[12:13], v[12:13], -v[16:17]
	v_add_f64 v[10:11], v[10:11], v[12:13]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[12:13], v[22:23], v[10:11]
	v_add_f64 v[14:15], v[12:13], -v[22:23]
	v_add_f64 v[16:17], v[12:13], v[12:13]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[10:11], v[10:11], -v[14:15]
	v_fma_f64 v[12:13], v[12:13], 2.0, -v[16:17]
	v_cmp_class_f64_e64 vcc_lo, v[16:17], 0x204
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[10:11], v[10:11], 2.0, v[12:13]
	v_add_f64 v[12:13], v[16:17], v[10:11]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v15, v13, v17 :: v_dual_cndmask_b32 v14, v12, v16
	v_cmp_gt_f64_e32 vcc_lo, 0x10000000, v[24:25]
	v_add_f64 v[12:13], v[12:13], -v[16:17]
	v_mul_f64 v[18:19], v[14:15], s[76:77]
	v_cmp_nlt_f64_e64 s1, 0x40900000, v[14:15]
	v_cmp_neq_f64_e64 s0, 0x7ff00000, |v[14:15]|
	v_cmp_ngt_f64_e64 s3, 0xc090cc00, v[14:15]
	v_cndmask_b32_e64 v1, 0, 1, vcc_lo
	v_add_f64 v[10:11], v[10:11], -v[12:13]
	v_rndne_f64_e32 v[18:19], v[18:19]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b32_e32 v1, 8, v1
	v_ldexp_f64 v[24:25], v[24:25], v1
	s_delay_alu instid0(VALU_DEP_4)
	v_cndmask_b32_e64 v11, 0, v11, s0
	v_cndmask_b32_e64 v10, 0, v10, s0
	s_and_b32 s0, s3, s1
	v_fma_f64 v[20:21], v[18:19], s[80:81], v[14:15]
	v_cvt_i32_f64_e32 v1, v[18:19]
	v_rsq_f64_e32 v[26:27], v[24:25]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_fma_f64 v[20:21], v[18:19], s[82:83], v[20:21]
	s_waitcnt_depctr 0xfff
	v_mul_f64 v[28:29], v[24:25], v[26:27]
	v_mul_f64 v[26:27], v[26:27], 0.5
	v_fma_f64 v[22:23], v[20:21], s[86:87], s[84:85]
	v_fma_f64 v[22:23], v[20:21], v[22:23], s[88:89]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[22:23], v[20:21], v[22:23], s[90:91]
	v_fma_f64 v[22:23], v[20:21], v[22:23], s[92:93]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[22:23], v[20:21], v[22:23], s[94:95]
	v_fma_f64 v[22:23], v[20:21], v[22:23], s[96:97]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[22:23], v[20:21], v[22:23], s[98:99]
	v_fma_f64 v[22:23], v[20:21], v[22:23], s[100:101]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[22:23], v[20:21], v[22:23], s[10:11]
	v_fma_f64 v[22:23], v[20:21], v[22:23], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f64 v[18:19], v[20:21], v[22:23], 1.0
	v_fma_f64 v[20:21], -v[26:27], v[28:29], 0.5
	v_ldexp_f64 v[16:17], v[18:19], v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fma_f64 v[18:19], v[28:29], v[20:21], v[28:29]
	v_fma_f64 v[12:13], v[26:27], v[20:21], v[26:27]
	v_cndmask_b32_e64 v1, 0x7ff00000, v17, s1
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_fma_f64 v[14:15], -v[18:19], v[18:19], v[24:25]
	v_cndmask_b32_e64 v16, 0, v16, s0
	v_cmp_neq_f64_e64 s1, 0, v[7:8]
	v_cndmask_b32_e64 v17, 0, v1, s3
	s_mov_b32 s3, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_mov_b32 s10, s3
	v_fma_f64 v[10:11], v[16:17], v[10:11], v[16:17]
	v_cmp_class_f64_e64 s0, v[16:17], 0x204
	v_fma_f64 v[14:15], v[14:15], v[12:13], v[18:19]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v11, v11, v17, s0
	v_cndmask_b32_e64 v10, v10, v16, s0
	v_cmp_neq_f64_e64 s0, 0x7ff00000, |v[7:8]|
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_f64 v[10:11], |v[10:11]|, 0
	v_fma_f64 v[16:17], -v[14:15], v[14:15], v[24:25]
	v_cndmask_b32_e64 v1, 0x7ff80000, v11, s0
	s_and_b32 s0, s1, s0
	s_delay_alu instid0(VALU_DEP_3) | instid1(SALU_CYCLE_1)
	v_cndmask_b32_e64 v10, 0, v10, s0
	s_delay_alu instid0(VALU_DEP_2)
	v_cndmask_b32_e64 v11, 0, v1, s1
	s_and_b32 s1, vcc_lo, exec_lo
	s_cselect_b32 s1, 0xffffff80, 0
	v_cmp_class_f64_e64 vcc_lo, v[24:25], 0x260
	s_cmp_gt_i32 s9, 0
	v_fma_f64 v[7:8], v[16:17], v[12:13], v[14:15]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_ldexp_f64 v[12:13], v[7:8], s1
	v_cndmask_b32_e64 v8, 0, v30, s2
	s_cselect_b32 s1, -1, 0
	v_add_f64 v[9:10], v[8:9], -v[10:11]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_cndmask_b32 v13, v13, v25 :: v_dual_cndmask_b32 v12, v12, v24
	v_mul_f64 v[7:8], v[12:13], s[6:7]
	s_delay_alu instid0(VALU_DEP_1)
	v_mul_f64 v[11:12], v[7:8], v[9:10]
	v_mov_b32_e32 v7, 0
	v_mov_b32_e32 v8, 0
.LBB1_13:                               ; %.preheader
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB1_15 Depth 2
                                        ;       Child Loop BB1_16 Depth 3
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB1_20
; %bb.14:                               ; %.lr.ph
                                        ;   in Loop: Header=BB1_13 Depth=1
	s_mov_b32 s11, s3
	s_mov_b32 s2, 0
	s_lshl_b64 s[34:35], s[10:11], 3
	s_mov_b32 s11, s14
	s_add_u32 s34, s22, s34
	s_addc_u32 s35, s23, s35
	s_mov_b32 s33, s15
	s_load_b64 s[34:35], s[34:35], 0x0
	s_waitcnt vmcnt(1) lgkmcnt(0)
	v_add_f64 v[15:16], v[3:4], -s[34:35]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[13:14], v[15:16], s[4:5]
	v_mul_f64 v[15:16], v[15:16], v[15:16]
	v_mul_f64 v[13:14], v[13:14], v[13:14]
.LBB1_15:                               ;   Parent Loop BB1_13 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB1_16 Depth 3
	s_lshl_b64 s[34:35], s[2:3], 3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	s_add_u32 s34, s24, s34
	s_addc_u32 s35, s25, s35
	s_load_b64 s[34:35], s[34:35], 0x0
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f64 v[17:18], v[5:6], -s[34:35]
	v_fma_f64 v[19:20], v[17:18], v[17:18], v[13:14]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[17:18], v[17:18], v[17:18], v[15:16]
	v_cmp_gt_f64_e32 vcc_lo, 0x10000000, v[19:20]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cmp_gt_f64_e64 s0, 0x10000000, v[17:18]
	v_cndmask_b32_e64 v1, 0, 1, vcc_lo
	v_cndmask_b32_e64 v21, 0, 1, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b32_e32 v1, 8, v1
	v_lshlrev_b32_e32 v21, 8, v21
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ldexp_f64 v[19:20], v[19:20], v1
	v_ldexp_f64 v[17:18], v[17:18], v21
	v_cndmask_b32_e64 v1, 0, 0xffffff80, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rsq_f64_e32 v[21:22], v[19:20]
	v_rsq_f64_e32 v[23:24], v[17:18]
	v_cmp_class_f64_e64 vcc_lo, v[19:20], 0x260
	s_waitcnt_depctr 0xfff
	v_mul_f64 v[25:26], v[19:20], v[21:22]
	v_mul_f64 v[21:22], v[21:22], 0.5
	v_mul_f64 v[27:28], v[17:18], v[23:24]
	v_mul_f64 v[23:24], v[23:24], 0.5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[29:30], -v[21:22], v[25:26], 0.5
	v_fma_f64 v[31:32], -v[23:24], v[27:28], 0.5
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fma_f64 v[25:26], v[25:26], v[29:30], v[25:26]
	v_fma_f64 v[21:22], v[21:22], v[29:30], v[21:22]
	v_fma_f64 v[27:28], v[27:28], v[31:32], v[27:28]
	v_fma_f64 v[23:24], v[23:24], v[31:32], v[23:24]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[29:30], -v[25:26], v[25:26], v[19:20]
	v_fma_f64 v[31:32], -v[27:28], v[27:28], v[17:18]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[25:26], v[29:30], v[21:22], v[25:26]
	v_fma_f64 v[27:28], v[31:32], v[23:24], v[27:28]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[29:30], -v[25:26], v[25:26], v[19:20]
	v_fma_f64 v[31:32], -v[27:28], v[27:28], v[17:18]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fma_f64 v[21:22], v[29:30], v[21:22], v[25:26]
	v_cndmask_b32_e64 v25, 0, 0xffffff80, s0
	v_fma_f64 v[23:24], v[31:32], v[23:24], v[27:28]
	v_cmp_class_f64_e64 s0, v[17:18], 0x260
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_ldexp_f64 v[21:22], v[21:22], v1
	v_ldexp_f64 v[23:24], v[23:24], v25
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v20, v22, v20 :: v_dual_cndmask_b32 v19, v21, v19
	v_cndmask_b32_e64 v18, v24, v18, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v17, v23, v17, s0
	s_mov_b32 s0, 0
	v_mul_f64 v[19:20], v[19:20], s[6:7]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[21:22], v[17:18], s[6:7]
	v_fma_f64 v[17:18], -v[9:10], v[19:20], v[11:12]
	s_delay_alu instid0(VALU_DEP_2)
	v_fma_f64 v[19:20], -v[9:10], v[21:22], v[11:12]
.LBB1_16:                               ;   Parent Loop BB1_13 Depth=1
                                        ;     Parent Loop BB1_15 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_add_i32 s34, s11, s0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_ashr_i32 s35, s34, 31
	s_lshl_b64 s[34:35], s[34:35], 3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	s_add_u32 s34, s26, s34
	s_addc_u32 s35, s27, s35
	s_load_b64 s[34:35], s[34:35], 0x0
	s_waitcnt lgkmcnt(0)
	v_cmp_nle_f64_e64 s34, s[34:35], s[30:31]
	s_and_b32 vcc_lo, exec_lo, s34
	s_cbranch_vccnz .LBB1_18
; %bb.17:                               ;   in Loop: Header=BB1_16 Depth=3
	s_add_i32 s34, s33, s0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_ashr_i32 s35, s34, 31
	s_lshl_b64 s[34:35], s[34:35], 3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s34, s28, s34
	s_addc_u32 s35, s29, s35
	s_clause 0x2
	s_load_b64 s[36:37], s[34:35], 0x18
	s_load_b64 s[38:39], s[34:35], 0x30
	s_load_b64 s[34:35], s[34:35], 0x0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mul_f64 v[21:22], v[19:20], s[36:37]
	v_mul_f64 v[23:24], v[17:18], s[34:35]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[21:22], v[21:22], s[38:39]
	v_fma_f64 v[21:22], v[23:24], s[36:37], v[21:22]
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[7:8], v[7:8], v[21:22]
.LBB1_18:                               ;   in Loop: Header=BB1_16 Depth=3
	s_add_i32 s0, s0, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u32 s0, 3
	s_cbranch_scc1 .LBB1_16
; %bb.19:                               ;   in Loop: Header=BB1_15 Depth=2
	s_add_i32 s2, s2, 1
	s_add_i32 s33, s33, 9
	s_add_i32 s11, s11, 3
	s_cmp_lg_u32 s2, s9
	s_cbranch_scc1 .LBB1_15
.LBB1_20:                               ; %._crit_edge
                                        ;   in Loop: Header=BB1_13 Depth=1
	s_add_i32 s10, s10, 1
	s_add_i32 s15, s15, s12
	s_add_i32 s14, s14, s13
	s_cmp_lg_u32 s10, s8
	s_cbranch_scc1 .LBB1_13
	s_branch .LBB1_22
.LBB1_21:
	v_mov_b32_e32 v7, 0
	v_mov_b32_e32 v8, 0
.LBB1_22:                               ; %Flow167
	s_load_b128 s[4:7], s[18:19], 0x0
	s_load_b128 s[0:3], s[20:21], 0x0
	s_waitcnt vmcnt(1) lgkmcnt(0)
	v_add_f64 v[3:4], s[6:7], -s[4:5]
	s_waitcnt vmcnt(0)
	v_add_f64 v[5:6], s[2:3], -s[0:1]
	s_mov_b32 s0, 0xc9be45de
	s_mov_b32 s1, 0x4043bd3c
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[3:4], v[3:4], v[5:6]
	v_div_scale_f64 v[5:6], null, s[0:1], s[0:1], v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[9:10], v[5:6]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[11:12], -v[5:6], v[9:10], 1.0
	v_fma_f64 v[9:10], v[9:10], v[11:12], v[9:10]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[11:12], -v[5:6], v[9:10], 1.0
	v_fma_f64 v[9:10], v[9:10], v[11:12], v[9:10]
	v_div_scale_f64 v[11:12], vcc_lo, v[3:4], s[0:1], v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[13:14], v[11:12], v[9:10]
	v_fma_f64 v[5:6], -v[5:6], v[13:14], v[11:12]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f64 v[5:6], v[5:6], v[9:10], v[13:14]
	v_div_fixup_f64 v[3:4], v[5:6], s[0:1], v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[3:4], v[3:4], v[7:8]
	v_mad_u64_u32 v[5:6], null, v0, s9, v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v6, 31, v5
	v_lshlrev_b64 v[0:1], 3, v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s16, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s17, v1, vcc_lo
	global_store_b64 v[0:1], v[3:4], off
.LBB1_23:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z10h_of_p_GPUPdS_S_S_S_S_S_ddddiii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 360
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 43
		.amdhsa_next_free_sgpr 102
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z10h_of_p_GPUPdS_S_S_S_S_S_ddddiii, .Lfunc_end1-_Z10h_of_p_GPUPdS_S_S_S_S_S_ddddiii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 7540
; NumSgprs: 104
; NumVgprs: 43
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 12
; VGPRBlocks: 5
; NumSGPRsForWavesPerEU: 104
; NumVGPRsForWavesPerEU: 43
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         48
        .size:           8
        .value_kind:     global_buffer
      - .offset:         56
        .size:           8
        .value_kind:     by_value
      - .offset:         64
        .size:           8
        .value_kind:     by_value
      - .offset:         72
        .size:           8
        .value_kind:     by_value
      - .offset:         80
        .size:           8
        .value_kind:     by_value
      - .offset:         88
        .size:           4
        .value_kind:     by_value
      - .offset:         92
        .size:           4
        .value_kind:     by_value
      - .offset:         96
        .size:           4
        .value_kind:     by_value
      - .offset:         104
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         108
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         112
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         116
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         118
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         120
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         122
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         124
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         126
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         144
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         152
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         160
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         168
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 360
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z16epsilon_of_p_GPUPdS_S_S_S_S_S_ddddiii
    .private_segment_fixed_size: 0
    .sgpr_count:     104
    .sgpr_spill_count: 0
    .symbol:         _Z16epsilon_of_p_GPUPdS_S_S_S_S_S_ddddiii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     43
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         48
        .size:           8
        .value_kind:     global_buffer
      - .offset:         56
        .size:           8
        .value_kind:     by_value
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        .size:           8
        .value_kind:     by_value
      - .offset:         72
        .size:           8
        .value_kind:     by_value
      - .offset:         80
        .size:           8
        .value_kind:     by_value
      - .offset:         88
        .size:           4
        .value_kind:     by_value
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        .size:           4
        .value_kind:     by_value
      - .offset:         96
        .size:           4
        .value_kind:     by_value
      - .offset:         104
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         108
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         112
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         116
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         118
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         120
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         122
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         124
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         126
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         144
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         152
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         160
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         168
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 360
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z10h_of_p_GPUPdS_S_S_S_S_S_ddddiii
    .private_segment_fixed_size: 0
    .sgpr_count:     104
    .sgpr_spill_count: 0
    .symbol:         _Z10h_of_p_GPUPdS_S_S_S_S_S_ddddiii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     43
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
