#include "includes.h"

//#define __OUTPUT_PIX__

#define BLOCK_SIZE 32
__constant__ __device__ float lTable_const[1064];
__constant__ __device__ float mr_const[3];
__constant__ __device__ float mg_const[3];
__constant__ __device__ float mb_const[3];


__global__ void lin2lin_resmpl_messy_gpu_kernel(float *dev_in_img, float *dev_out_img, float *dev_C0_tmp, float *dev_C1_tmp, float *dev_C2_tmp, int org_wd, int org_ht, int dst_wd, int dst_ht, int n_channels, float r, int hn, int wn, int xbd0, int xbd1, int ybd0, int ybd1, int *xas_const, int *xbs_const, float *xwts_const, int *yas_const, int *ybs_const, float *ywts_const)
{

unsigned int x_pos = threadIdx.x + (blockDim.x * blockIdx.x);
unsigned int y_pos = threadIdx.y + (blockDim.y * blockIdx.y);

if ((x_pos < dst_wd) && (y_pos < dst_ht)) {

int xa, ya, yb;
float wt, wt1;
float *A00, *A01, *A02, *A03, *B00;
float *A10, *A11, *A12, *A13, *B10;
float *A20, *A21, *A22, *A23, *B20;

float *A0 = dev_in_img + 0;
float *B0 = dev_out_img + (0 * dst_ht * dst_wd);
float *A1 = dev_in_img + 1;
float *B1 = dev_out_img + (1 * dst_ht * dst_wd);
float *A2 = dev_in_img + 2;
float *B2 = dev_out_img + (2 * dst_ht * dst_wd);
int y1 = 0;

if (org_ht > dst_ht) {
int m = 1;
for (int iter = 0; iter < y_pos; iter++) {
while (y1 + m < hn && yb == ybs_const[y1 + m])
m++;
y1 += m;
}
wt = ywts_const[y1];
wt1 = 1 - wt;
} else {
y1 = y_pos;
wt = ywts_const[y1];
wt1 = 1 - wt;
}

if (y_pos == 0)
y1 = 0;

ya = yas_const[y1];
A00 = A0 + (ya * org_wd * n_channels);
A01 = A00 + (org_wd * n_channels);
A02 = A01 + (org_wd * n_channels);
A03 = A02 + (org_wd * n_channels);

A10 = A1 + (ya * org_wd * n_channels);
A11 = A00 + (org_wd * n_channels);
A12 = A01 + (org_wd * n_channels);
A13 = A02 + (org_wd * n_channels);

A20 = A2 + (ya * org_wd * n_channels);
A21 = A00 + (org_wd * n_channels);
A22 = A01 + (org_wd * n_channels);
A23 = A02 + (org_wd * n_channels);

yb = ybs_const[y1];
B00 = B0 + (yb * dst_wd);
B10 = B1 + (yb * dst_wd);
B20 = B2 + (yb * dst_wd);

int x = 0;

if (org_wd < x_pos) {
// resample along y direction
if (org_ht > dst_ht) {
int m = 1;
while ((y1 + m < hn) && (yb == ybs_const[y1 + m]))
m++;

if (m == 1) {
dev_C0_tmp[x_pos] = A00[x_pos] * ywts_const[y1];
dev_C1_tmp[x_pos] = A10[x_pos] * ywts_const[y1];
dev_C2_tmp[x_pos] = A20[x_pos] * ywts_const[y1];
} else if (m == 2) {
dev_C0_tmp[x_pos] = (A00[x_pos] * ywts_const[y1 + 0]) +
(A01[x_pos] * ywts_const[y1 + 1]);
dev_C1_tmp[x_pos] = (A10[x_pos] * ywts_const[y1 + 0]) +
(A11[x_pos] * ywts_const[y1 + 1]);
dev_C2_tmp[x_pos] = (A20[x_pos] * ywts_const[y1 + 0]) +
(A21[x_pos] * ywts_const[y1 + 1]);
} else if (m == 3) {
dev_C0_tmp[x_pos] = (A00[x_pos] * ywts_const[y1 + 0]) +
(A01[x_pos] * ywts_const[y1 + 1]) +
(A02[x_pos] * ywts_const[y1 + 2]);
dev_C1_tmp[x_pos] = (A10[x_pos] * ywts_const[y1 + 0]) +
(A11[x_pos] * ywts_const[y1 + 1]) +
(A12[x_pos] * ywts_const[y1 + 2]);
dev_C2_tmp[x_pos] = (A20[x_pos] * ywts_const[y1 + 0]) +
(A21[x_pos] * ywts_const[y1 + 1]) +
(A22[x_pos] * ywts_const[y1 + 2]);
} else if (m >= 4) {
dev_C0_tmp[x_pos] = (A00[x_pos] * ywts_const[y1 + 0]) +
(A01[x_pos] * ywts_const[y1 + 1]) +
(A02[x_pos] * ywts_const[y1 + 2]) +
(A03[x_pos] * ywts_const[y1 + 3]);
dev_C1_tmp[x_pos] = (A10[x_pos] * ywts_const[y1 + 0]) +
(A11[x_pos] * ywts_const[y1 + 1]) +
(A12[x_pos] * ywts_const[y1 + 2]) +
(A13[x_pos] * ywts_const[y1 + 3]);
dev_C2_tmp[x_pos] = (A20[x_pos] * ywts_const[y1 + 0]) +
(A21[x_pos] * ywts_const[y1 + 1]) +
(A22[x_pos] * ywts_const[y1 + 2]) +
(A23[x_pos] * ywts_const[y1 + 3]);
}

for (int y0 = 4; y0 < m; y0++) {
A01 = A00 + (y0 * org_wd);
A11 = A10 + (y0 * org_wd);
A11 = A10 + (y0 * org_wd);
wt1 = ywts_const[y1 + y0];
dev_C0_tmp[x_pos] = dev_C0_tmp[x_pos] + (A01[x_pos] * wt1);
dev_C1_tmp[x_pos] = dev_C1_tmp[x_pos] + (A11[x_pos] * wt1);
dev_C2_tmp[x_pos] = dev_C2_tmp[x_pos] + (A21[x_pos] * wt1);
}

} else {
bool yBd = y_pos < ybd0 || y_pos >= dst_ht - ybd1;

if (yBd) {
dev_C0_tmp[x_pos] = A00[x_pos];
dev_C1_tmp[x_pos] = A10[x_pos];
dev_C2_tmp[x_pos] = A20[x_pos];
} else {
dev_C0_tmp[x_pos] = (A00[x_pos] * wt) + (A01[x_pos] * wt1);
dev_C1_tmp[x_pos] = (A10[x_pos] * wt) + (A11[x_pos] * wt1);
dev_C2_tmp[x_pos] = (A20[x_pos] * wt) + (A21[x_pos] * wt1);
}
}
}

/* ensure that all threads have calculated the values for C until this point */
__syncthreads();

// resample along x direction (B -> C)
if (x_pos < dst_wd) {
if (org_wd > dst_wd) {
if (xbd0 == 2) {
xa = xas_const[x_pos * 4];
B00[x_pos] = (dev_C0_tmp[xa + 0] * xwts_const[(4 * x_pos) + 0]) +
(dev_C0_tmp[xa + 1] * xwts_const[(4 * x_pos) + 1]);
B10[x_pos] = (dev_C1_tmp[xa + 0] * xwts_const[(4 * x_pos) + 0]) +
(dev_C1_tmp[xa + 1] * xwts_const[(4 * x_pos) + 1]);
B20[x_pos] = (dev_C2_tmp[xa + 0] * xwts_const[(4 * x_pos) + 0]) +
(dev_C2_tmp[xa + 1] * xwts_const[(4 * x_pos) + 1]);
} else if (xbd0 == 3) {
xa = xas_const[x_pos * 4];
B00[x_pos] = (dev_C0_tmp[xa + 0] * xwts_const[(4 * x_pos) + 0]) +
(dev_C0_tmp[xa + 1] * xwts_const[(4 * x_pos) + 1]) +
(dev_C0_tmp[xa + 2] * xwts_const[(4 * x_pos) + 2]);
B10[x_pos] = (dev_C1_tmp[xa + 0] * xwts_const[(4 * x_pos) + 0]) +
(dev_C1_tmp[xa + 1] * xwts_const[(4 * x_pos) + 1]) +
(dev_C1_tmp[xa + 2] * xwts_const[(4 * x_pos) + 2]);
B20[x_pos] = (dev_C2_tmp[xa + 0] * xwts_const[(4 * x_pos) + 0]) +
(dev_C2_tmp[xa + 1] * xwts_const[(4 * x_pos) + 1]) +
(dev_C2_tmp[xa + 2] * xwts_const[(4 * x_pos) + 2]);
} else if (xbd0 == 4) {
xa = xas_const[x_pos * 4];
B00[x_pos] = (dev_C0_tmp[xa + 0] * xwts_const[(4 * x_pos) + 0]) +
(dev_C0_tmp[xa + 1] * xwts_const[(4 * x_pos) + 1]) +
(dev_C0_tmp[xa + 2] * xwts_const[(4 * x_pos) + 2]) +
(dev_C0_tmp[xa + 3] * xwts_const[(4 * x_pos) + 3]);
B10[x_pos] = (dev_C1_tmp[xa + 0] * xwts_const[(4 * x_pos) + 0]) +
(dev_C1_tmp[xa + 1] * xwts_const[(4 * x_pos) + 1]) +
(dev_C1_tmp[xa + 2] * xwts_const[(4 * x_pos) + 2]) +
(dev_C1_tmp[xa + 3] * xwts_const[(4 * x_pos) + 3]);
B20[x_pos] = (dev_C2_tmp[xa + 0] * xwts_const[(4 * x_pos) + 0]) +
(dev_C2_tmp[xa + 1] * xwts_const[(4 * x_pos) + 1]) +
(dev_C2_tmp[xa + 2] * xwts_const[(4 * x_pos) + 2]) +
(dev_C2_tmp[xa + 3] * xwts_const[(4 * x_pos) + 3]);
} else if (xbd0 > 4) {
for(x = 0; x < wn; x++) {
B00[xbs_const[x]] += dev_C0_tmp[xas_const[x]] * xwts_const[x];
B10[xbs_const[x]] += dev_C1_tmp[xas_const[x]] * xwts_const[x];
B20[xbs_const[x]] += dev_C2_tmp[xas_const[x]] * xwts_const[x];
}
}
} else {

for (x = 0; x < xbd0; x++) {
B00[x] = dev_C0_tmp[xas_const[x]] * xwts_const[x];
B10[x] = dev_C1_tmp[xas_const[x]] * xwts_const[x];
B20[x] = dev_C2_tmp[xas_const[x]] * xwts_const[x];
}
for (; x < dst_wd - xbd1; x++) {
B00[x] = dev_C0_tmp[xas_const[x]] * xwts_const[x] + dev_C0_tmp[xas_const[x] + 1] * (r - xwts_const[x]);
B10[x] = dev_C1_tmp[xas_const[x]] * xwts_const[x] + dev_C1_tmp[xas_const[x] + 1] * (r - xwts_const[x]);
B20[x] = dev_C2_tmp[xas_const[x]] * xwts_const[x] + dev_C2_tmp[xas_const[x] + 1] * (r - xwts_const[x]);
}
for (; x < dst_wd; x++) {
B00[x] = dev_C0_tmp[xas_const[x]] * xwts_const[x];
B10[x] = dev_C1_tmp[xas_const[x]] * xwts_const[x];
B20[x] = dev_C2_tmp[xas_const[x]] * xwts_const[x];
}
}
}

__syncthreads();
}
}
	.file	"tmpxft_002def6d_00000000-6_lin2lin_resmpl_messy_gpu_kernel.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2010:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2010:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z86__device_stub__Z31lin2lin_resmpl_messy_gpu_kernelPfS_S_S_S_iiiiifiiiiiiPiS0_S_S0_S0_S_PfS_S_S_S_iiiiifiiiiiiPiS0_S_S0_S0_S_
	.type	_Z86__device_stub__Z31lin2lin_resmpl_messy_gpu_kernelPfS_S_S_S_iiiiifiiiiiiPiS0_S_S0_S0_S_PfS_S_S_S_iiiiifiiiiiiPiS0_S_S0_S0_S_, @function
_Z86__device_stub__Z31lin2lin_resmpl_messy_gpu_kernelPfS_S_S_S_iiiiifiiiiiiPiS0_S_S0_S0_S_PfS_S_S_S_iiiiifiiiiiiPiS0_S_S0_S0_S_:
.LFB2032:
	.cfi_startproc
	endbr64
	subq	$360, %rsp
	.cfi_def_cfa_offset 368
	movq	448(%rsp), %rax
	movq	%rdi, 88(%rsp)
	leaq	112(%rsp), %rdi
	movq	%rsi, 80(%rsp)
	leaq	124(%rsp), %rsi
	movq	%rax, 40(%rsp)
	movq	456(%rsp), %rax
	movq	%rdx, 72(%rsp)
	leaq	96(%rsp), %rdx
	movq	%rax, 32(%rsp)
	movq	464(%rsp), %rax
	movq	%rcx, 64(%rsp)
	leaq	104(%rsp), %rcx
	movq	%rax, 24(%rsp)
	movq	472(%rsp), %rax
	movq	%r8, 56(%rsp)
	movq	%rax, 16(%rsp)
	movq	480(%rsp), %rax
	movl	%r9d, 52(%rsp)
	movq	%rax, 8(%rsp)
	movq	488(%rsp), %rax
	movss	%xmm0, 48(%rsp)
	movq	%rax, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 344(%rsp)
	xorl	%eax, %eax
	leaq	88(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	80(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	72(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	64(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	56(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	52(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	368(%rsp), %rax
	movq	%rax, 208(%rsp)
	leaq	376(%rsp), %rax
	movq	%rax, 216(%rsp)
	leaq	384(%rsp), %rax
	movq	%rax, 224(%rsp)
	leaq	392(%rsp), %rax
	movq	%rax, 232(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 240(%rsp)
	leaq	400(%rsp), %rax
	movq	%rax, 248(%rsp)
	leaq	408(%rsp), %rax
	movq	%rax, 256(%rsp)
	leaq	416(%rsp), %rax
	movq	%rax, 264(%rsp)
	leaq	424(%rsp), %rax
	movq	%rax, 272(%rsp)
	leaq	432(%rsp), %rax
	movq	%rax, 280(%rsp)
	leaq	440(%rsp), %rax
	movq	%rax, 288(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 296(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 304(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 312(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 320(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 328(%rsp)
	movq	%rsp, %rax
	movq	%rax, 336(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 112(%rsp)
	movl	$1, 120(%rsp)
	movq	%rax, 124(%rsp)
	movl	$1, 132(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	104(%rsp)
	.cfi_def_cfa_offset 376
	leaq	_Z31lin2lin_resmpl_messy_gpu_kernelPfS_S_S_S_iiiiifiiiiiiPiS0_S_S0_S0_S_(%rip), %rdi
	pushq	104(%rsp)
	.cfi_def_cfa_offset 384
	movq	140(%rsp), %rcx
	movl	148(%rsp), %r8d
	movq	128(%rsp), %rsi
	movl	136(%rsp), %edx
	leaq	176(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 376
	popq	%rdx
	.cfi_def_cfa_offset 368
.L2:
	movq	344(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$360, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2032:
	.size	_Z86__device_stub__Z31lin2lin_resmpl_messy_gpu_kernelPfS_S_S_S_iiiiifiiiiiiPiS0_S_S0_S0_S_PfS_S_S_S_iiiiifiiiiiiPiS0_S_S0_S0_S_, .-_Z86__device_stub__Z31lin2lin_resmpl_messy_gpu_kernelPfS_S_S_S_iiiiifiiiiiiPiS0_S_S0_S0_S_PfS_S_S_S_iiiiifiiiiiiPiS0_S_S0_S0_S_
	.globl	_Z31lin2lin_resmpl_messy_gpu_kernelPfS_S_S_S_iiiiifiiiiiiPiS0_S_S0_S0_S_
	.type	_Z31lin2lin_resmpl_messy_gpu_kernelPfS_S_S_S_iiiiifiiiiiiPiS0_S_S0_S0_S_, @function
_Z31lin2lin_resmpl_messy_gpu_kernelPfS_S_S_S_iiiiifiiiiiiPiS0_S_S0_S0_S_:
.LFB2033:
	.cfi_startproc
	endbr64
	jmp	_Z86__device_stub__Z31lin2lin_resmpl_messy_gpu_kernelPfS_S_S_S_iiiiifiiiiiiPiS0_S_S0_S0_S_PfS_S_S_S_iiiiifiiiiiiPiS0_S_S0_S0_S_
	.cfi_endproc
.LFE2033:
	.size	_Z31lin2lin_resmpl_messy_gpu_kernelPfS_S_S_S_iiiiifiiiiiiPiS0_S_S0_S0_S_, .-_Z31lin2lin_resmpl_messy_gpu_kernelPfS_S_S_S_iiiiifiiiiiiPiS0_S_S0_S0_S_
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z31lin2lin_resmpl_messy_gpu_kernelPfS_S_S_S_iiiiifiiiiiiPiS0_S_S0_S0_S_"
.LC1:
	.string	"lTable_const"
.LC2:
	.string	"mr_const"
.LC3:
	.string	"mg_const"
.LC4:
	.string	"mb_const"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2035:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z31lin2lin_resmpl_messy_gpu_kernelPfS_S_S_S_iiiiifiiiiiiPiS0_S_S0_S0_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC1(%rip), %rdx
	movl	$4256, %r9d
	leaq	_ZL12lTable_const(%rip), %rsi
	pushq	$1
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC2(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$12, %r9d
	leaq	_ZL8mr_const(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC3(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$12, %r9d
	leaq	_ZL8mg_const(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	popq	%r8
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC4(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movl	$12, %r9d
	movq	%rdx, %rcx
	leaq	_ZL8mb_const(%rip), %rsi
	call	__cudaRegisterVar@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	popq	%r9
	.cfi_def_cfa_offset 24
	popq	%r10
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2035:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.local	_ZL8mb_const
	.comm	_ZL8mb_const,12,8
	.local	_ZL8mg_const
	.comm	_ZL8mg_const,12,8
	.local	_ZL8mr_const
	.comm	_ZL8mr_const,12,8
	.local	_ZL12lTable_const
	.comm	_ZL12lTable_const,4256,32
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include "includes.h"

//#define __OUTPUT_PIX__

#define BLOCK_SIZE 32
__constant__ __device__ float lTable_const[1064];
__constant__ __device__ float mr_const[3];
__constant__ __device__ float mg_const[3];
__constant__ __device__ float mb_const[3];


__global__ void lin2lin_resmpl_messy_gpu_kernel(float *dev_in_img, float *dev_out_img, float *dev_C0_tmp, float *dev_C1_tmp, float *dev_C2_tmp, int org_wd, int org_ht, int dst_wd, int dst_ht, int n_channels, float r, int hn, int wn, int xbd0, int xbd1, int ybd0, int ybd1, int *xas_const, int *xbs_const, float *xwts_const, int *yas_const, int *ybs_const, float *ywts_const)
{

unsigned int x_pos = threadIdx.x + (blockDim.x * blockIdx.x);
unsigned int y_pos = threadIdx.y + (blockDim.y * blockIdx.y);

if ((x_pos < dst_wd) && (y_pos < dst_ht)) {

int xa, ya, yb;
float wt, wt1;
float *A00, *A01, *A02, *A03, *B00;
float *A10, *A11, *A12, *A13, *B10;
float *A20, *A21, *A22, *A23, *B20;

float *A0 = dev_in_img + 0;
float *B0 = dev_out_img + (0 * dst_ht * dst_wd);
float *A1 = dev_in_img + 1;
float *B1 = dev_out_img + (1 * dst_ht * dst_wd);
float *A2 = dev_in_img + 2;
float *B2 = dev_out_img + (2 * dst_ht * dst_wd);
int y1 = 0;

if (org_ht > dst_ht) {
int m = 1;
for (int iter = 0; iter < y_pos; iter++) {
while (y1 + m < hn && yb == ybs_const[y1 + m])
m++;
y1 += m;
}
wt = ywts_const[y1];
wt1 = 1 - wt;
} else {
y1 = y_pos;
wt = ywts_const[y1];
wt1 = 1 - wt;
}

if (y_pos == 0)
y1 = 0;

ya = yas_const[y1];
A00 = A0 + (ya * org_wd * n_channels);
A01 = A00 + (org_wd * n_channels);
A02 = A01 + (org_wd * n_channels);
A03 = A02 + (org_wd * n_channels);

A10 = A1 + (ya * org_wd * n_channels);
A11 = A00 + (org_wd * n_channels);
A12 = A01 + (org_wd * n_channels);
A13 = A02 + (org_wd * n_channels);

A20 = A2 + (ya * org_wd * n_channels);
A21 = A00 + (org_wd * n_channels);
A22 = A01 + (org_wd * n_channels);
A23 = A02 + (org_wd * n_channels);

yb = ybs_const[y1];
B00 = B0 + (yb * dst_wd);
B10 = B1 + (yb * dst_wd);
B20 = B2 + (yb * dst_wd);

int x = 0;

if (org_wd < x_pos) {
// resample along y direction
if (org_ht > dst_ht) {
int m = 1;
while ((y1 + m < hn) && (yb == ybs_const[y1 + m]))
m++;

if (m == 1) {
dev_C0_tmp[x_pos] = A00[x_pos] * ywts_const[y1];
dev_C1_tmp[x_pos] = A10[x_pos] * ywts_const[y1];
dev_C2_tmp[x_pos] = A20[x_pos] * ywts_const[y1];
} else if (m == 2) {
dev_C0_tmp[x_pos] = (A00[x_pos] * ywts_const[y1 + 0]) +
(A01[x_pos] * ywts_const[y1 + 1]);
dev_C1_tmp[x_pos] = (A10[x_pos] * ywts_const[y1 + 0]) +
(A11[x_pos] * ywts_const[y1 + 1]);
dev_C2_tmp[x_pos] = (A20[x_pos] * ywts_const[y1 + 0]) +
(A21[x_pos] * ywts_const[y1 + 1]);
} else if (m == 3) {
dev_C0_tmp[x_pos] = (A00[x_pos] * ywts_const[y1 + 0]) +
(A01[x_pos] * ywts_const[y1 + 1]) +
(A02[x_pos] * ywts_const[y1 + 2]);
dev_C1_tmp[x_pos] = (A10[x_pos] * ywts_const[y1 + 0]) +
(A11[x_pos] * ywts_const[y1 + 1]) +
(A12[x_pos] * ywts_const[y1 + 2]);
dev_C2_tmp[x_pos] = (A20[x_pos] * ywts_const[y1 + 0]) +
(A21[x_pos] * ywts_const[y1 + 1]) +
(A22[x_pos] * ywts_const[y1 + 2]);
} else if (m >= 4) {
dev_C0_tmp[x_pos] = (A00[x_pos] * ywts_const[y1 + 0]) +
(A01[x_pos] * ywts_const[y1 + 1]) +
(A02[x_pos] * ywts_const[y1 + 2]) +
(A03[x_pos] * ywts_const[y1 + 3]);
dev_C1_tmp[x_pos] = (A10[x_pos] * ywts_const[y1 + 0]) +
(A11[x_pos] * ywts_const[y1 + 1]) +
(A12[x_pos] * ywts_const[y1 + 2]) +
(A13[x_pos] * ywts_const[y1 + 3]);
dev_C2_tmp[x_pos] = (A20[x_pos] * ywts_const[y1 + 0]) +
(A21[x_pos] * ywts_const[y1 + 1]) +
(A22[x_pos] * ywts_const[y1 + 2]) +
(A23[x_pos] * ywts_const[y1 + 3]);
}

for (int y0 = 4; y0 < m; y0++) {
A01 = A00 + (y0 * org_wd);
A11 = A10 + (y0 * org_wd);
A11 = A10 + (y0 * org_wd);
wt1 = ywts_const[y1 + y0];
dev_C0_tmp[x_pos] = dev_C0_tmp[x_pos] + (A01[x_pos] * wt1);
dev_C1_tmp[x_pos] = dev_C1_tmp[x_pos] + (A11[x_pos] * wt1);
dev_C2_tmp[x_pos] = dev_C2_tmp[x_pos] + (A21[x_pos] * wt1);
}

} else {
bool yBd = y_pos < ybd0 || y_pos >= dst_ht - ybd1;

if (yBd) {
dev_C0_tmp[x_pos] = A00[x_pos];
dev_C1_tmp[x_pos] = A10[x_pos];
dev_C2_tmp[x_pos] = A20[x_pos];
} else {
dev_C0_tmp[x_pos] = (A00[x_pos] * wt) + (A01[x_pos] * wt1);
dev_C1_tmp[x_pos] = (A10[x_pos] * wt) + (A11[x_pos] * wt1);
dev_C2_tmp[x_pos] = (A20[x_pos] * wt) + (A21[x_pos] * wt1);
}
}
}

/* ensure that all threads have calculated the values for C until this point */
__syncthreads();

// resample along x direction (B -> C)
if (x_pos < dst_wd) {
if (org_wd > dst_wd) {
if (xbd0 == 2) {
xa = xas_const[x_pos * 4];
B00[x_pos] = (dev_C0_tmp[xa + 0] * xwts_const[(4 * x_pos) + 0]) +
(dev_C0_tmp[xa + 1] * xwts_const[(4 * x_pos) + 1]);
B10[x_pos] = (dev_C1_tmp[xa + 0] * xwts_const[(4 * x_pos) + 0]) +
(dev_C1_tmp[xa + 1] * xwts_const[(4 * x_pos) + 1]);
B20[x_pos] = (dev_C2_tmp[xa + 0] * xwts_const[(4 * x_pos) + 0]) +
(dev_C2_tmp[xa + 1] * xwts_const[(4 * x_pos) + 1]);
} else if (xbd0 == 3) {
xa = xas_const[x_pos * 4];
B00[x_pos] = (dev_C0_tmp[xa + 0] * xwts_const[(4 * x_pos) + 0]) +
(dev_C0_tmp[xa + 1] * xwts_const[(4 * x_pos) + 1]) +
(dev_C0_tmp[xa + 2] * xwts_const[(4 * x_pos) + 2]);
B10[x_pos] = (dev_C1_tmp[xa + 0] * xwts_const[(4 * x_pos) + 0]) +
(dev_C1_tmp[xa + 1] * xwts_const[(4 * x_pos) + 1]) +
(dev_C1_tmp[xa + 2] * xwts_const[(4 * x_pos) + 2]);
B20[x_pos] = (dev_C2_tmp[xa + 0] * xwts_const[(4 * x_pos) + 0]) +
(dev_C2_tmp[xa + 1] * xwts_const[(4 * x_pos) + 1]) +
(dev_C2_tmp[xa + 2] * xwts_const[(4 * x_pos) + 2]);
} else if (xbd0 == 4) {
xa = xas_const[x_pos * 4];
B00[x_pos] = (dev_C0_tmp[xa + 0] * xwts_const[(4 * x_pos) + 0]) +
(dev_C0_tmp[xa + 1] * xwts_const[(4 * x_pos) + 1]) +
(dev_C0_tmp[xa + 2] * xwts_const[(4 * x_pos) + 2]) +
(dev_C0_tmp[xa + 3] * xwts_const[(4 * x_pos) + 3]);
B10[x_pos] = (dev_C1_tmp[xa + 0] * xwts_const[(4 * x_pos) + 0]) +
(dev_C1_tmp[xa + 1] * xwts_const[(4 * x_pos) + 1]) +
(dev_C1_tmp[xa + 2] * xwts_const[(4 * x_pos) + 2]) +
(dev_C1_tmp[xa + 3] * xwts_const[(4 * x_pos) + 3]);
B20[x_pos] = (dev_C2_tmp[xa + 0] * xwts_const[(4 * x_pos) + 0]) +
(dev_C2_tmp[xa + 1] * xwts_const[(4 * x_pos) + 1]) +
(dev_C2_tmp[xa + 2] * xwts_const[(4 * x_pos) + 2]) +
(dev_C2_tmp[xa + 3] * xwts_const[(4 * x_pos) + 3]);
} else if (xbd0 > 4) {
for(x = 0; x < wn; x++) {
B00[xbs_const[x]] += dev_C0_tmp[xas_const[x]] * xwts_const[x];
B10[xbs_const[x]] += dev_C1_tmp[xas_const[x]] * xwts_const[x];
B20[xbs_const[x]] += dev_C2_tmp[xas_const[x]] * xwts_const[x];
}
}
} else {

for (x = 0; x < xbd0; x++) {
B00[x] = dev_C0_tmp[xas_const[x]] * xwts_const[x];
B10[x] = dev_C1_tmp[xas_const[x]] * xwts_const[x];
B20[x] = dev_C2_tmp[xas_const[x]] * xwts_const[x];
}
for (; x < dst_wd - xbd1; x++) {
B00[x] = dev_C0_tmp[xas_const[x]] * xwts_const[x] + dev_C0_tmp[xas_const[x] + 1] * (r - xwts_const[x]);
B10[x] = dev_C1_tmp[xas_const[x]] * xwts_const[x] + dev_C1_tmp[xas_const[x] + 1] * (r - xwts_const[x]);
B20[x] = dev_C2_tmp[xas_const[x]] * xwts_const[x] + dev_C2_tmp[xas_const[x] + 1] * (r - xwts_const[x]);
}
for (; x < dst_wd; x++) {
B00[x] = dev_C0_tmp[xas_const[x]] * xwts_const[x];
B10[x] = dev_C1_tmp[xas_const[x]] * xwts_const[x];
B20[x] = dev_C2_tmp[xas_const[x]] * xwts_const[x];
}
}
}

__syncthreads();
}
}
	.text
	.file	"lin2lin_resmpl_messy_gpu_kernel.hip"
	.globl	_Z46__device_stub__lin2lin_resmpl_messy_gpu_kernelPfS_S_S_S_iiiiifiiiiiiPiS0_S_S0_S0_S_ # -- Begin function _Z46__device_stub__lin2lin_resmpl_messy_gpu_kernelPfS_S_S_S_iiiiifiiiiiiPiS0_S_S0_S0_S_
	.type	_Z46__device_stub__lin2lin_resmpl_messy_gpu_kernelPfS_S_S_S_iiiiifiiiiiiPiS0_S_S0_S0_S_,@function
_Z46__device_stub__lin2lin_resmpl_messy_gpu_kernelPfS_S_S_S_iiiiifiiiiiiPiS0_S_S0_S0_S_: # @_Z46__device_stub__lin2lin_resmpl_messy_gpu_kernelPfS_S_S_S_iiiiifiiiiiiPiS0_S_S0_S0_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$288, %rsp                      # imm = 0x120
	.cfi_def_cfa_offset 336
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	4(%rsp), %r8
	movl	%r9d, (%r8)
	movq	%rsp, %r9
	movss	%xmm0, (%r9)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	336(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	344(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	352(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	360(%rsp), %rax
	movq	%rax, 72(%rbx)
	movq	%r9, 80(%rbx)
	leaq	368(%rsp), %rax
	movq	%rax, 88(%rbx)
	leaq	376(%rsp), %rax
	movq	%rax, 96(%rbx)
	leaq	384(%rsp), %rax
	movq	%rax, 104(%rbx)
	leaq	392(%rsp), %rax
	movq	%rax, 112(%rbx)
	leaq	400(%rsp), %rax
	movq	%rax, 120(%rbx)
	leaq	408(%rsp), %rax
	movq	%rax, 128(%rbx)
	leaq	416(%rsp), %rax
	movq	%rax, 136(%rbx)
	leaq	424(%rsp), %rax
	movq	%rax, 144(%rbx)
	leaq	432(%rsp), %rax
	movq	%rax, 152(%rbx)
	leaq	440(%rsp), %rax
	movq	%rax, 160(%rbx)
	leaq	448(%rsp), %rax
	movq	%rax, 168(%rbx)
	leaq	456(%rsp), %rax
	movq	%rax, 176(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z31lin2lin_resmpl_messy_gpu_kernelPfS_S_S_S_iiiiifiiiiiiPiS0_S_S0_S0_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$304, %rsp                      # imm = 0x130
	.cfi_adjust_cfa_offset -304
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z46__device_stub__lin2lin_resmpl_messy_gpu_kernelPfS_S_S_S_iiiiifiiiiiiPiS0_S_S0_S0_S_, .Lfunc_end0-_Z46__device_stub__lin2lin_resmpl_messy_gpu_kernelPfS_S_S_S_iiiiifiiiiiiPiS0_S_S0_S0_S_
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	subq	$32, %rsp
	.cfi_adjust_cfa_offset 32
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z31lin2lin_resmpl_messy_gpu_kernelPfS_S_S_S_iiiiifiiiiiiPiS0_S_S0_S0_S_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	addq	$32, %rsp
	.cfi_adjust_cfa_offset -32
	movl	$lTable_const, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movl	$4256, %r9d                     # imm = 0x10A0
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$mr_const, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movl	$12, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$mg_const, %esi
	movl	$.L__unnamed_4, %edx
	movl	$.L__unnamed_4, %ecx
	movl	$12, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$mb_const, %esi
	movl	$.L__unnamed_5, %edx
	movl	$.L__unnamed_5, %ecx
	movl	$12, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$__hip_module_dtor, %edi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	lTable_const,@object            # @lTable_const
	.local	lTable_const
	.comm	lTable_const,4256,16
	.type	mr_const,@object                # @mr_const
	.local	mr_const
	.comm	mr_const,12,4
	.type	mg_const,@object                # @mg_const
	.local	mg_const
	.comm	mg_const,12,4
	.type	mb_const,@object                # @mb_const
	.local	mb_const
	.comm	mb_const,12,4
	.type	_Z31lin2lin_resmpl_messy_gpu_kernelPfS_S_S_S_iiiiifiiiiiiPiS0_S_S0_S0_S_,@object # @_Z31lin2lin_resmpl_messy_gpu_kernelPfS_S_S_S_iiiiifiiiiiiPiS0_S_S0_S0_S_
	.section	.rodata,"a",@progbits
	.globl	_Z31lin2lin_resmpl_messy_gpu_kernelPfS_S_S_S_iiiiifiiiiiiPiS0_S_S0_S0_S_
	.p2align	3, 0x0
_Z31lin2lin_resmpl_messy_gpu_kernelPfS_S_S_S_iiiiifiiiiiiPiS0_S_S0_S0_S_:
	.quad	_Z46__device_stub__lin2lin_resmpl_messy_gpu_kernelPfS_S_S_S_iiiiifiiiiiiPiS0_S_S0_S0_S_
	.size	_Z31lin2lin_resmpl_messy_gpu_kernelPfS_S_S_S_iiiiifiiiiiiPiS0_S_S0_S0_S_, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z31lin2lin_resmpl_messy_gpu_kernelPfS_S_S_S_iiiiifiiiiiiPiS0_S_S0_S0_S_"
	.size	.L__unnamed_1, 73

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"lTable_const"
	.size	.L__unnamed_2, 13

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"mr_const"
	.size	.L__unnamed_3, 9

	.type	.L__unnamed_4,@object           # @3
.L__unnamed_4:
	.asciz	"mg_const"
	.size	.L__unnamed_4, 9

	.type	.L__unnamed_5,@object           # @4
.L__unnamed_5:
	.asciz	"mb_const"
	.size	.L__unnamed_5, 9

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z46__device_stub__lin2lin_resmpl_messy_gpu_kernelPfS_S_S_S_iiiiifiiiiiiPiS0_S_S0_S0_S_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym lTable_const
	.addrsig_sym mr_const
	.addrsig_sym mg_const
	.addrsig_sym mb_const
	.addrsig_sym _Z31lin2lin_resmpl_messy_gpu_kernelPfS_S_S_S_iiiiifiiiiiiPiS0_S_S0_S0_S_
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z31lin2lin_resmpl_messy_gpu_kernelPfS_S_S_S_iiiiifiiiiiiPiS0_S_S0_S0_S_ ; -- Begin function _Z31lin2lin_resmpl_messy_gpu_kernelPfS_S_S_S_iiiiifiiiiiiPiS0_S_S0_S0_S_
	.globl	_Z31lin2lin_resmpl_messy_gpu_kernelPfS_S_S_S_iiiiifiiiiiiPiS0_S_S0_S0_S_
	.p2align	8
	.type	_Z31lin2lin_resmpl_messy_gpu_kernelPfS_S_S_S_iiiiifiiiiiiPiS0_S_S0_S0_S_,@function
_Z31lin2lin_resmpl_messy_gpu_kernelPfS_S_S_S_iiiiifiiiiiiPiS0_S_S0_S0_S_: ; @_Z31lin2lin_resmpl_messy_gpu_kernelPfS_S_S_S_iiiiifiiiiiiPiS0_S_S0_S0_S_
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x94
	s_load_b256 s[20:27], s[0:1], 0x28
	v_and_b32_e32 v2, 0x3ff, v0
	v_bfe_u32 v4, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s2, 16
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[0:1], null, s14, s2, v[2:3]
	v_mad_u64_u32 v[2:3], null, s15, s3, v[4:5]
	v_cmp_gt_u32_e32 vcc_lo, s22, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_gt_u32_e64 s2, s23, v2
	s_and_b32 s2, vcc_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_73
; %bb.1:
	s_load_b128 s[36:39], s[0:1], 0x78
	v_ashrrev_i32_e32 v3, 31, v2
	s_mov_b32 s33, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 2, v[2:3]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v6, vcc_lo, s36, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v7, vcc_lo, s37, v5, vcc_lo
	global_load_b32 v11, v[6:7], off
	s_clause 0x3
	s_load_b256 s[4:11], s[0:1], 0x0
	s_load_b128 s[28:31], s[0:1], 0x48
	s_load_b64 s[2:3], s[0:1], 0x20
	s_load_b256 s[12:19], s[0:1], 0x58
	v_cmpx_lt_u32_e64 s20, v0
	s_cbranch_execz .LBB0_36
; %bb.2:
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v6, vcc_lo, s18, v4
	v_add_co_ci_u32_e32 v7, vcc_lo, s19, v5, vcc_lo
	s_mul_i32 s18, s24, s20
	s_cmp_gt_i32 s21, s23
	s_cselect_b32 vcc_lo, -1, 0
	global_load_b32 v1, v[6:7], off
	s_ashr_i32 s19, s18, 31
	s_waitcnt vmcnt(0)
	v_mul_lo_u32 v6, s18, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v7, 31, v6
	v_lshlrev_b64 v[6:7], 2, v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v13, s0, s4, v6
	v_add_co_ci_u32_e64 v14, s0, s5, v7, s0
	s_lshl_b64 s[4:5], s[18:19], 2
	s_cmp_le_i32 s21, s23
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v10, s0, v13, s4
	v_add_co_ci_u32_e64 v12, s0, s5, v14, s0
	s_mov_b32 s0, -1
	s_cbranch_scc0 .LBB0_8
; %bb.3:
	v_mov_b32_e32 v1, 0
	s_sub_i32 s1, s23, s31
                                        ; implicit-def: $vgpr15
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_u32_e64 s1, s1, v2
	v_lshlrev_b64 v[6:7], 2, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v8, s0, v13, v6
	v_add_co_ci_u32_e64 v9, s0, v14, v7, s0
	v_cmp_le_u32_e64 s0, s30, v2
	global_load_b32 v1, v[8:9], off
	s_and_b32 s0, s0, s1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_saveexec_b32 s1, s0
	s_xor_b32 s0, exec_lo, s1
	s_cbranch_execz .LBB0_5
; %bb.4:
	v_cndmask_b32_e64 v16, v3, 0, vcc_lo
	v_cndmask_b32_e32 v15, v2, v2, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[15:16], 2, v[15:16]
	v_add_co_u32 v15, vcc_lo, s38, v15
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v16, vcc_lo, s39, v16, vcc_lo
	v_add_co_u32 v17, vcc_lo, v10, v6
	v_add_co_ci_u32_e32 v18, vcc_lo, v12, v7, vcc_lo
	global_load_b32 v3, v[15:16], off
	global_load_b32 v15, v[17:18], off
	s_waitcnt vmcnt(1)
	v_sub_f32_e32 v19, 1.0, v3
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v20, v19, v15
	v_add_co_u32 v15, vcc_lo, s8, v6
	v_add_co_ci_u32_e32 v16, vcc_lo, s9, v7, vcc_lo
	v_fmac_f32_e32 v20, v3, v1
	global_store_b32 v[15:16], v20, off
	s_clause 0x1
	global_load_b32 v1, v[17:18], off
	global_load_b32 v15, v[8:9], off offset:4
	s_waitcnt vmcnt(1)
	v_mul_f32_e32 v1, v19, v1
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v1, v3, v15
	v_add_co_u32 v15, vcc_lo, s10, v6
	v_add_co_ci_u32_e32 v16, vcc_lo, s11, v7, vcc_lo
	global_store_b32 v[15:16], v1, off
	s_clause 0x1
	global_load_b32 v1, v[17:18], off
	global_load_b32 v8, v[8:9], off offset:8
	s_waitcnt vmcnt(1)
	v_mul_f32_e32 v15, v19, v1
                                        ; implicit-def: $vgpr1
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v15, v3, v8
                                        ; implicit-def: $vgpr8_vgpr9
.LBB0_5:                                ; %Flow813
	s_and_not1_saveexec_b32 s0, s0
	s_cbranch_execz .LBB0_7
; %bb.6:
	v_add_co_u32 v15, vcc_lo, s8, v6
	v_add_co_ci_u32_e32 v16, vcc_lo, s9, v7, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b32 v[15:16], v1, off
	global_load_b32 v1, v[8:9], off offset:4
	v_add_co_u32 v15, vcc_lo, s10, v6
	v_add_co_ci_u32_e32 v16, vcc_lo, s11, v7, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b32 v[15:16], v1, off
	global_load_b32 v15, v[8:9], off offset:8
.LBB0_7:                                ; %.loopexit622.sink.split
	s_or_b32 exec_lo, exec_lo, s0
	v_add_co_u32 v6, vcc_lo, s2, v6
	v_add_co_ci_u32_e32 v7, vcc_lo, s3, v7, vcc_lo
	s_mov_b32 s0, 0
	s_waitcnt vmcnt(0)
	global_store_b32 v[6:7], v15, off
.LBB0_8:                                ; %Flow829
	s_and_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccz .LBB0_36
; %bb.9:                                ; %.preheader623
	v_add_nc_u32_e32 v1, 1, v2
	v_mov_b32_e32 v15, 1
	s_mov_b32 s1, 1
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_2)
	v_cmpx_gt_i32_e64 s26, v1
	s_cbranch_execz .LBB0_15
; %bb.10:                               ; %.lr.ph.preheader
	s_mov_b32 s18, 0
                                        ; implicit-def: $sgpr19
.LBB0_11:                               ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	v_dual_mov_b32 v15, s1 :: v_dual_add_nc_u32 v6, s1, v2
	s_or_b32 s19, s19, exec_lo
	s_mov_b32 s21, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v7, 31, v6
	v_lshlrev_b64 v[6:7], 2, v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v6, vcc_lo, s36, v6
	v_add_co_ci_u32_e32 v7, vcc_lo, s37, v7, vcc_lo
	global_load_b32 v1, v[6:7], off
	s_waitcnt vmcnt(0)
	v_cmpx_eq_u32_e64 v11, v1
; %bb.12:                               ;   in Loop: Header=BB0_11 Depth=1
	s_add_i32 s1, s1, 1
	s_and_not1_b32 s19, s19, exec_lo
	v_add_nc_u32_e32 v1, s1, v2
	v_mov_b32_e32 v15, s1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_le_i32_e32 vcc_lo, s26, v1
	s_and_b32 s24, vcc_lo, exec_lo
	s_or_b32 s19, s19, s24
; %bb.13:                               ; %Flow825
                                        ;   in Loop: Header=BB0_11 Depth=1
	s_or_b32 exec_lo, exec_lo, s21
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s21, exec_lo, s19
	s_or_b32 s18, s21, s18
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s18
	s_cbranch_execnz .LBB0_11
; %bb.14:                               ; %Flow826
	s_or_b32 exec_lo, exec_lo, s18
.LBB0_15:                               ; %Flow827
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s0
	v_add_co_u32 v3, vcc_lo, v10, s4
	v_add_co_ci_u32_e32 v6, vcc_lo, s5, v12, vcc_lo
	s_mov_b32 s0, 0
	s_mov_b32 s19, 0
	s_mov_b32 s1, 0
	s_mov_b32 s18, exec_lo
                                        ; implicit-def: $vgpr7
	v_cmpx_lt_i32_e32 1, v15
	s_xor_b32 s18, exec_lo, s18
	s_cbranch_execz .LBB0_23
; %bb.16:                               ; %NodeBlock
	s_mov_b32 s21, 0
	s_mov_b32 s1, exec_lo
                                        ; implicit-def: $vgpr7
	v_cmpx_lt_i32_e32 2, v15
	s_xor_b32 s1, exec_lo, s1
	s_cbranch_execz .LBB0_20
; %bb.17:                               ; %LeafBlock784
	s_mov_b32 s24, -1
	s_mov_b32 s21, exec_lo
                                        ; implicit-def: $vgpr7
	v_cmpx_eq_u32_e32 3, v15
	s_cbranch_execz .LBB0_19
; %bb.18:
	v_add_co_u32 v16, vcc_lo, s38, v4
	v_add_co_ci_u32_e32 v17, vcc_lo, s39, v5, vcc_lo
	s_mov_b32 s19, exec_lo
	s_xor_b32 s24, exec_lo, -1
	global_load_b96 v[7:9], v[16:17], off
	v_mov_b32_e32 v1, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[18:19], 2, v[0:1]
	v_add_co_u32 v20, vcc_lo, v10, v18
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v21, vcc_lo, v12, v19, vcc_lo
	v_add_co_u32 v22, vcc_lo, v13, v18
	v_add_co_ci_u32_e32 v23, vcc_lo, v14, v19, vcc_lo
	global_load_b32 v26, v[20:21], off
	v_add_co_u32 v24, vcc_lo, v3, v18
	v_add_co_ci_u32_e32 v25, vcc_lo, v6, v19, vcc_lo
	s_clause 0x1
	global_load_b32 v27, v[22:23], off
	global_load_b32 v28, v[24:25], off
	s_waitcnt vmcnt(2)
	v_mul_f32_e32 v26, v26, v8
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v26, v27, v7
	v_add_co_u32 v7, vcc_lo, s8, v18
	v_add_co_ci_u32_e32 v8, vcc_lo, s9, v19, vcc_lo
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v26, v28, v9
	global_store_b32 v[7:8], v26, off
	global_load_b96 v[7:9], v[16:17], off
	s_clause 0x2
	global_load_b32 v26, v[20:21], off
	global_load_b32 v27, v[22:23], off offset:4
	global_load_b32 v28, v[24:25], off
	s_waitcnt vmcnt(2)
	v_mul_f32_e32 v26, v26, v8
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v26, v27, v7
	v_add_co_u32 v7, vcc_lo, s10, v18
	v_add_co_ci_u32_e32 v8, vcc_lo, s11, v19, vcc_lo
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v26, v28, v9
	global_store_b32 v[7:8], v26, off
	global_load_b96 v[16:18], v[16:17], off
	s_clause 0x2
	global_load_b32 v7, v[20:21], off
	global_load_b32 v8, v[22:23], off offset:8
	global_load_b32 v9, v[24:25], off
	s_waitcnt vmcnt(2)
	v_mul_f32_e32 v7, v7, v17
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v7, v8, v16
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v7, v9, v18
.LBB0_19:                               ; %Flow818
	s_or_b32 exec_lo, exec_lo, s21
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s21, s19, exec_lo
	s_and_b32 s19, s24, exec_lo
.LBB0_20:                               ; %Flow817
	s_and_not1_saveexec_b32 s1, s1
	s_cbranch_execz .LBB0_22
; %bb.21:
	v_mov_b32_e32 v1, 0
	v_add_co_u32 v7, vcc_lo, s38, v4
	v_add_co_ci_u32_e32 v8, vcc_lo, s39, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_3)
	v_lshlrev_b64 v[16:17], 2, v[0:1]
	s_or_b32 s21, s21, exec_lo
	global_load_b64 v[18:19], v[7:8], off
	v_add_co_u32 v20, vcc_lo, v10, v16
	v_add_co_ci_u32_e32 v21, vcc_lo, v12, v17, vcc_lo
	v_add_co_u32 v22, vcc_lo, v13, v16
	v_add_co_ci_u32_e32 v23, vcc_lo, v14, v17, vcc_lo
	v_add_co_u32 v24, vcc_lo, s8, v16
	s_clause 0x1
	global_load_b32 v9, v[20:21], off
	global_load_b32 v26, v[22:23], off
	v_add_co_ci_u32_e32 v25, vcc_lo, s9, v17, vcc_lo
	v_add_co_u32 v16, vcc_lo, s10, v16
	v_add_co_ci_u32_e32 v17, vcc_lo, s11, v17, vcc_lo
	s_waitcnt vmcnt(1)
	v_mul_f32_e32 v9, v9, v19
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v9, v26, v18
	global_store_b32 v[24:25], v9, off
	global_load_b64 v[18:19], v[7:8], off
	s_clause 0x1
	global_load_b32 v9, v[20:21], off
	global_load_b32 v24, v[22:23], off offset:4
	s_waitcnt vmcnt(1)
	v_mul_f32_e32 v9, v9, v19
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v9, v24, v18
	global_store_b32 v[16:17], v9, off
	global_load_b64 v[8:9], v[7:8], off
	s_clause 0x1
	global_load_b32 v7, v[20:21], off
	global_load_b32 v16, v[22:23], off offset:8
	s_waitcnt vmcnt(1)
	v_mul_f32_e32 v7, v7, v9
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v7, v16, v8
.LBB0_22:                               ; %Flow819
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s1, s21, exec_lo
	s_and_b32 s19, s19, exec_lo
.LBB0_23:                               ; %Flow816
	s_and_not1_saveexec_b32 s18, s18
; %bb.24:                               ; %LeafBlock
	v_cmp_ne_u32_e32 vcc_lo, 1, v15
	s_and_not1_b32 s19, s19, exec_lo
	s_mov_b32 s0, exec_lo
                                        ; implicit-def: $vgpr7
	s_and_b32 s21, vcc_lo, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s19, s19, s21
; %bb.25:                               ; %Flow820
	s_or_b32 exec_lo, exec_lo, s18
	s_and_saveexec_b32 s18, s19
	s_cbranch_execz .LBB0_29
; %bb.26:
	s_mov_b32 s21, s1
	s_mov_b32 s19, exec_lo
                                        ; implicit-def: $vgpr7
	v_cmpx_lt_u32_e32 3, v15
	s_xor_b32 s19, exec_lo, s19
	s_cbranch_execz .LBB0_28
; %bb.27:
	v_mov_b32_e32 v1, 0
	v_add_co_u32 v20, vcc_lo, s38, v4
	v_add_co_ci_u32_e32 v21, vcc_lo, s39, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_3)
	v_lshlrev_b64 v[22:23], 2, v[0:1]
	s_or_b32 s21, s1, exec_lo
	global_load_b128 v[16:19], v[20:21], off
	v_add_co_u32 v24, vcc_lo, v10, v22
	v_add_co_ci_u32_e32 v25, vcc_lo, v12, v23, vcc_lo
	v_add_co_u32 v26, vcc_lo, v13, v22
	v_add_co_ci_u32_e32 v27, vcc_lo, v14, v23, vcc_lo
	global_load_b32 v7, v[24:25], off
	v_add_co_u32 v28, vcc_lo, v3, v22
	global_load_b32 v3, v[26:27], off
	v_add_co_ci_u32_e32 v29, vcc_lo, v6, v23, vcc_lo
	v_add_co_u32 v30, vcc_lo, v28, s4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v31, vcc_lo, s5, v29, vcc_lo
	s_clause 0x1
	global_load_b32 v6, v[28:29], off
	global_load_b32 v8, v[30:31], off
	s_waitcnt vmcnt(3)
	v_mul_f32_e32 v9, v7, v17
	s_waitcnt vmcnt(2)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v9, v3, v16
	s_waitcnt vmcnt(1)
	v_fmac_f32_e32 v9, v6, v18
	v_add_co_u32 v6, vcc_lo, s8, v22
	v_add_co_ci_u32_e32 v7, vcc_lo, s9, v23, vcc_lo
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_3)
	v_fmac_f32_e32 v9, v8, v19
	global_store_b32 v[6:7], v9, off
	global_load_b128 v[6:9], v[20:21], off
	s_clause 0x3
	global_load_b32 v3, v[24:25], off
	global_load_b32 v16, v[26:27], off offset:4
	global_load_b32 v17, v[28:29], off
	global_load_b32 v18, v[30:31], off
	s_waitcnt vmcnt(3)
	v_mul_f32_e32 v3, v3, v7
	s_waitcnt vmcnt(2)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v3, v16, v6
	v_add_co_u32 v6, vcc_lo, s10, v22
	v_add_co_ci_u32_e32 v7, vcc_lo, s11, v23, vcc_lo
	s_waitcnt vmcnt(1)
	v_fmac_f32_e32 v3, v17, v8
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v3, v18, v9
	global_store_b32 v[6:7], v3, off
	global_load_b128 v[6:9], v[20:21], off
	s_clause 0x3
	global_load_b32 v3, v[24:25], off
	global_load_b32 v16, v[26:27], off offset:8
	global_load_b32 v17, v[28:29], off
	global_load_b32 v18, v[30:31], off
	s_waitcnt vmcnt(3)
	v_mul_f32_e32 v7, v3, v7
	s_waitcnt vmcnt(2)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v7, v16, v6
	s_waitcnt vmcnt(1)
	v_fmac_f32_e32 v7, v17, v8
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v7, v18, v9
.LBB0_28:                               ; %Flow822
	s_or_b32 exec_lo, exec_lo, s19
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 s1, s1, exec_lo
	s_and_b32 s4, s21, exec_lo
	s_and_not1_b32 s0, s0, exec_lo
	s_or_b32 s1, s1, s4
.LBB0_29:                               ; %Flow821
	s_or_b32 exec_lo, exec_lo, s18
	s_and_saveexec_b32 s4, s0
	s_cbranch_execz .LBB0_31
; %bb.30:
	v_mov_b32_e32 v1, 0
	v_add_co_u32 v3, vcc_lo, s38, v4
	v_add_co_ci_u32_e32 v4, vcc_lo, s39, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[6:7], 2, v[0:1]
	s_or_b32 s1, s1, exec_lo
	v_add_co_u32 v8, vcc_lo, v13, v6
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v9, vcc_lo, v14, v7, vcc_lo
	v_add_co_u32 v16, vcc_lo, s8, v6
	global_load_b32 v5, v[3:4], off
	global_load_b32 v18, v[8:9], off
	v_add_co_ci_u32_e32 v17, vcc_lo, s9, v7, vcc_lo
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v5, v18, v5
	global_store_b32 v[16:17], v5, off
	global_load_b32 v16, v[8:9], off offset:4
	global_load_b32 v17, v[3:4], off
	v_add_co_u32 v5, vcc_lo, s10, v6
	v_add_co_ci_u32_e32 v6, vcc_lo, s11, v7, vcc_lo
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v7, v16, v17
	global_store_b32 v[5:6], v7, off
	global_load_b32 v5, v[8:9], off offset:8
	global_load_b32 v3, v[3:4], off
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v7, v5, v3
.LBB0_31:                               ; %Flow823
	s_or_b32 exec_lo, exec_lo, s4
	s_and_saveexec_b32 s0, s1
	s_cbranch_execz .LBB0_33
; %bb.32:                               ; %.sink.split
	v_lshlrev_b64 v[3:4], 2, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, s2, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
	global_store_b32 v[3:4], v7, off
.LBB0_33:
	s_or_b32 exec_lo, exec_lo, s0
	v_cmp_lt_u32_e32 vcc_lo, 4, v15
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_36
; %bb.34:                               ; %.lr.ph633
	v_mov_b32_e32 v1, 0
	s_lshl_b32 s0, s20, 2
	s_mov_b32 s4, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[16:17], 2, v[0:1]
	v_add_nc_u32_e32 v1, 4, v2
	v_add_co_u32 v3, vcc_lo, s8, v16
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v4, vcc_lo, s9, v17, vcc_lo
	v_add_co_u32 v13, vcc_lo, v13, v16
	v_add_co_ci_u32_e32 v14, vcc_lo, v14, v17, vcc_lo
	v_add_co_u32 v5, vcc_lo, s10, v16
	v_add_co_ci_u32_e32 v6, vcc_lo, s11, v17, vcc_lo
	v_add_co_u32 v7, vcc_lo, s2, v16
	v_add_co_ci_u32_e32 v8, vcc_lo, s3, v17, vcc_lo
	v_add_co_u32 v9, vcc_lo, v10, v16
	v_add_co_ci_u32_e32 v10, vcc_lo, v12, v17, vcc_lo
	v_add_nc_u32_e32 v12, -4, v15
.LBB0_35:                               ; =>This Inner Loop Header: Depth=1
	v_ashrrev_i32_e32 v2, 31, v1
	s_ashr_i32 s1, s0, 31
	s_delay_alu instid0(VALU_DEP_2)
	v_add_nc_u32_e32 v12, -1, v12
	s_lshl_b64 s[18:19], s[0:1], 2
	s_add_i32 s0, s0, s20
	v_lshlrev_b64 v[15:16], 2, v[1:2]
	v_add_co_u32 v17, vcc_lo, v13, s18
	v_add_co_ci_u32_e32 v18, vcc_lo, s19, v14, vcc_lo
	v_add_nc_u32_e32 v1, 1, v1
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_u32 v15, vcc_lo, s38, v15
	v_add_co_ci_u32_e32 v16, vcc_lo, s39, v16, vcc_lo
	global_load_b32 v2, v[3:4], off
	global_load_b32 v19, v[17:18], off
	global_load_b32 v15, v[15:16], off
	v_cmp_eq_u32_e32 vcc_lo, 0, v12
	s_or_b32 s4, vcc_lo, s4
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v2, v15, v19
	global_store_b32 v[3:4], v2, off
	global_load_b32 v2, v[5:6], off
	global_load_b32 v16, v[17:18], off offset:4
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v2, v15, v16
	global_store_b32 v[5:6], v2, off
	global_load_b32 v2, v[7:8], off
	global_load_b32 v16, v[9:10], off
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v2, v15, v16
	global_store_b32 v[7:8], v2, off
	s_and_not1_b32 exec_lo, exec_lo, s4
	s_cbranch_execnz .LBB0_35
.LBB0_36:                               ; %.loopexit622
	s_or_b32 exec_lo, exec_lo, s33
	s_waitcnt vmcnt(0)
	v_mul_lo_u32 v1, v11, s22
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s18, s23, s22
	s_mov_b32 s0, s12
	s_lshl_b32 s30, s18, 1
	s_ashr_i32 s19, s18, 31
	s_ashr_i32 s31, s30, 31
	s_mov_b32 s1, s13
	s_mov_b32 s4, s16
	v_ashrrev_i32_e32 v2, 31, v1
	s_mov_b32 s5, s17
	s_cmp_gt_i32 s20, s22
	s_mov_b32 s20, -1
	s_waitcnt_vscnt null, 0x0
	v_lshlrev_b64 v[4:5], 2, v[1:2]
	s_barrier
	buffer_gl0_inv
	v_add_co_u32 v2, vcc_lo, s6, v4
	v_add_co_ci_u32_e32 v3, vcc_lo, s7, v5, vcc_lo
	s_cbranch_scc1 .LBB0_49
; %bb.37:                               ; %.preheader621
	s_cmp_lt_i32 s28, 1
	s_cbranch_scc1 .LBB0_41
; %bb.38:                               ; %.lr.ph637.preheader
	s_delay_alu instid0(VALU_DEP_1)
	v_mov_b32_e32 v7, v3
	v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v6, v2
	s_lshl_b64 s[20:21], s[18:19], 2
	s_lshl_b64 s[34:35], s[30:31], 2
	s_mov_b64 s[36:37], s[4:5]
	s_mov_b64 s[38:39], s[0:1]
	s_mov_b32 s23, s28
.LBB0_39:                               ; %.lr.ph637
                                        ; =>This Inner Loop Header: Depth=1
	s_load_b32 s40, s[38:39], 0x0
	s_waitcnt lgkmcnt(0)
	s_ashr_i32 s41, s40, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[40:41], s[40:41], 2
	s_add_u32 s42, s8, s40
	s_addc_u32 s43, s9, s41
	s_clause 0x1
	global_load_b32 v8, v1, s[42:43]
	global_load_b32 v9, v1, s[36:37]
	s_add_u32 s42, s10, s40
	s_addc_u32 s43, s11, s41
	s_add_u32 s40, s2, s40
	s_addc_u32 s41, s3, s41
	s_add_i32 s23, s23, -1
	s_add_u32 s38, s38, 4
	s_addc_u32 s39, s39, 0
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v8, v8, v9
	global_store_b32 v[6:7], v8, off
	s_clause 0x1
	global_load_b32 v10, v1, s[42:43]
	global_load_b32 v11, v1, s[36:37]
	v_add_co_u32 v8, vcc_lo, v6, s20
	v_add_co_ci_u32_e32 v9, vcc_lo, s21, v7, vcc_lo
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v10, v10, v11
	global_store_b32 v[8:9], v10, off
	s_clause 0x1
	global_load_b32 v10, v1, s[40:41]
	global_load_b32 v11, v1, s[36:37]
	v_add_co_u32 v8, vcc_lo, v6, s34
	v_add_co_ci_u32_e32 v9, vcc_lo, s35, v7, vcc_lo
	v_add_co_u32 v6, vcc_lo, v6, 4
	v_add_co_ci_u32_e32 v7, vcc_lo, 0, v7, vcc_lo
	s_add_u32 s36, s36, 4
	s_addc_u32 s37, s37, 0
	s_cmp_eq_u32 s23, 0
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v10, v10, v11
	global_store_b32 v[8:9], v10, off
	s_cbranch_scc0 .LBB0_39
; %bb.40:
	s_mov_b32 s20, s28
	s_branch .LBB0_42
.LBB0_41:
	s_mov_b32 s20, 0
.LBB0_42:                               ; %.preheader620
	s_sub_i32 s23, s22, s29
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_ge_i32 s20, s23
	s_cbranch_scc1 .LBB0_45
; %bb.43:                               ; %.lr.ph640.preheader
	s_mov_b32 s21, 0
	v_mov_b32_e32 v1, 0
	s_lshl_b64 s[38:39], s[20:21], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s34, s12, s38
	s_addc_u32 s35, s13, s39
	s_add_u32 s36, s16, s38
	s_addc_u32 s37, s17, s39
	s_add_u32 s21, s6, s38
	s_addc_u32 s24, s7, s39
	v_add_co_u32 v6, vcc_lo, s21, v4
	v_add_co_ci_u32_e32 v7, vcc_lo, s24, v5, vcc_lo
	s_lshl_b64 s[38:39], s[18:19], 2
	s_lshl_b64 s[40:41], s[30:31], 2
.LBB0_44:                               ; %.lr.ph640
                                        ; =>This Inner Loop Header: Depth=1
	s_load_b32 s42, s[34:35], 0x0
	s_waitcnt lgkmcnt(0)
	s_ashr_i32 s43, s42, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[42:43], s[42:43], 2
	s_add_u32 s44, s8, s42
	s_addc_u32 s45, s9, s43
	s_clause 0x1
	global_load_b32 v10, v1, s[36:37]
	global_load_b64 v[8:9], v1, s[44:45]
	s_add_u32 s44, s10, s42
	s_addc_u32 s45, s11, s43
	s_add_u32 s42, s2, s42
	s_addc_u32 s43, s3, s43
	s_add_i32 s20, s20, 1
	s_add_u32 s34, s34, 4
	s_addc_u32 s35, s35, 0
	s_waitcnt vmcnt(1)
	v_sub_f32_e32 v11, s25, v10
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v9, v9, v11
	v_fmac_f32_e32 v9, v8, v10
	global_store_b32 v[6:7], v9, off
	s_clause 0x1
	global_load_b32 v11, v1, s[36:37]
	global_load_b64 v[8:9], v1, s[44:45]
	s_waitcnt vmcnt(1)
	v_sub_f32_e32 v10, s25, v11
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v12, v9, v10
	v_add_co_u32 v9, vcc_lo, v6, s38
	v_add_co_ci_u32_e32 v10, vcc_lo, s39, v7, vcc_lo
	v_fmac_f32_e32 v12, v8, v11
	global_store_b32 v[9:10], v12, off
	s_clause 0x1
	global_load_b32 v12, v1, s[36:37]
	global_load_b64 v[8:9], v1, s[42:43]
	v_add_co_u32 v10, vcc_lo, v6, s40
	v_add_co_ci_u32_e32 v11, vcc_lo, s41, v7, vcc_lo
	v_add_co_u32 v6, vcc_lo, v6, 4
	v_add_co_ci_u32_e32 v7, vcc_lo, 0, v7, vcc_lo
	s_add_u32 s36, s36, 4
	s_addc_u32 s37, s37, 0
	s_cmp_ge_i32 s20, s23
	s_waitcnt vmcnt(1)
	v_sub_f32_e32 v13, s25, v12
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v9, v9, v13
	v_fmac_f32_e32 v9, v8, v12
	global_store_b32 v[10:11], v9, off
	s_cbranch_scc0 .LBB0_44
.LBB0_45:                               ; %.preheader618
	s_cmp_ge_i32 s20, s22
	s_cbranch_scc1 .LBB0_48
; %bb.46:                               ; %.lr.ph643.preheader
	s_mov_b32 s21, 0
	v_mov_b32_e32 v1, 0
	s_lshl_b64 s[36:37], s[20:21], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s24, s12, s36
	s_addc_u32 s25, s13, s37
	s_add_u32 s34, s16, s36
	s_addc_u32 s35, s17, s37
	s_add_u32 s21, s6, s36
	s_addc_u32 s23, s7, s37
	v_add_co_u32 v6, vcc_lo, s21, v4
	v_add_co_ci_u32_e32 v7, vcc_lo, s23, v5, vcc_lo
	s_lshl_b64 s[36:37], s[18:19], 2
	s_lshl_b64 s[38:39], s[30:31], 2
.LBB0_47:                               ; %.lr.ph643
                                        ; =>This Inner Loop Header: Depth=1
	s_load_b32 s40, s[24:25], 0x0
	s_waitcnt lgkmcnt(0)
	s_ashr_i32 s41, s40, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[40:41], s[40:41], 2
	s_add_u32 s42, s8, s40
	s_addc_u32 s43, s9, s41
	s_clause 0x1
	global_load_b32 v8, v1, s[42:43]
	global_load_b32 v9, v1, s[34:35]
	s_add_u32 s42, s10, s40
	s_addc_u32 s43, s11, s41
	s_add_u32 s40, s2, s40
	s_addc_u32 s41, s3, s41
	s_add_i32 s20, s20, 1
	s_add_u32 s24, s24, 4
	s_addc_u32 s25, s25, 0
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v8, v8, v9
	global_store_b32 v[6:7], v8, off
	s_clause 0x1
	global_load_b32 v10, v1, s[42:43]
	global_load_b32 v11, v1, s[34:35]
	v_add_co_u32 v8, vcc_lo, v6, s36
	v_add_co_ci_u32_e32 v9, vcc_lo, s37, v7, vcc_lo
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v10, v10, v11
	global_store_b32 v[8:9], v10, off
	s_clause 0x1
	global_load_b32 v10, v1, s[40:41]
	global_load_b32 v11, v1, s[34:35]
	v_add_co_u32 v8, vcc_lo, v6, s38
	v_add_co_ci_u32_e32 v9, vcc_lo, s39, v7, vcc_lo
	v_add_co_u32 v6, vcc_lo, v6, 4
	v_add_co_ci_u32_e32 v7, vcc_lo, 0, v7, vcc_lo
	s_add_u32 s34, s34, 4
	s_addc_u32 s35, s35, 0
	s_cmp_ge_i32 s20, s22
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v10, v10, v11
	global_store_b32 v[8:9], v10, off
	s_cbranch_scc0 .LBB0_47
.LBB0_48:                               ; %Flow796
	s_mov_b32 s20, 0
.LBB0_49:                               ; %Flow811
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s20
	s_cbranch_vccz .LBB0_72
; %bb.50:                               ; %NodeBlock794
	s_lshl_b64 s[18:19], s[18:19], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s20, s6, s18
	s_addc_u32 s21, s7, s19
	v_add_co_u32 v10, vcc_lo, s20, v4
	s_lshl_b64 s[18:19], s[30:31], 2
	v_add_co_ci_u32_e32 v11, vcc_lo, s21, v5, vcc_lo
	s_add_u32 s18, s6, s18
	s_addc_u32 s7, s7, s19
	s_cmp_lt_i32 s28, 3
	s_mov_b32 s6, 0
	s_cbranch_scc1 .LBB0_54
; %bb.51:                               ; %NodeBlock792
	s_cmp_gt_i32 s28, 3
	s_cbranch_scc0 .LBB0_55
; %bb.52:                               ; %LeafBlock790
	s_cmp_eq_u32 s28, 4
	s_mov_b32 s21, 0
	s_cbranch_scc0 .LBB0_56
; %bb.53:
	v_dual_mov_b32 v16, 0 :: v_dual_lshlrev_b32 v15, 2, v0
	s_mov_b32 s20, 0
	s_mov_b32 s19, -1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[6:7], 2, v[15:16]
	v_add_co_u32 v8, vcc_lo, s12, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v9, vcc_lo, s13, v7, vcc_lo
	global_load_b32 v19, v[8:9], off
	v_mov_b32_e32 v1, v16
	v_lshlrev_b64 v[22:23], 2, v[0:1]
	s_waitcnt vmcnt(0)
	v_ashrrev_i32_e32 v20, 31, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[17:18], 2, v[19:20]
	v_add_co_u32 v20, vcc_lo, s16, v6
	v_add_co_ci_u32_e32 v21, vcc_lo, s17, v7, vcc_lo
	v_add_co_u32 v12, vcc_lo, s8, v17
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v13, vcc_lo, s9, v18, vcc_lo
	global_load_b128 v[6:9], v[20:21], off
	global_load_b128 v[12:15], v[12:13], off
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v13, v13, v7
	v_fmac_f32_e32 v13, v12, v6
	v_add_co_u32 v6, vcc_lo, v2, v22
	v_add_co_ci_u32_e32 v7, vcc_lo, v3, v23, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v13, v14, v8
	v_add_co_u32 v8, vcc_lo, s10, v17
	v_fmac_f32_e32 v13, v15, v9
	v_add_co_ci_u32_e32 v9, vcc_lo, s11, v18, vcc_lo
	global_store_b32 v[6:7], v13, off
	global_load_b128 v[6:9], v[8:9], off
	global_load_b128 v[12:15], v[20:21], off
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v13, v7, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v13, v6, v12
	v_add_co_u32 v6, vcc_lo, v10, v22
	v_add_co_ci_u32_e32 v7, vcc_lo, v11, v23, vcc_lo
	v_fmac_f32_e32 v13, v8, v14
	v_add_co_u32 v8, vcc_lo, s2, v17
	s_delay_alu instid0(VALU_DEP_2)
	v_fmac_f32_e32 v13, v9, v15
	v_add_co_ci_u32_e32 v9, vcc_lo, s3, v18, vcc_lo
	global_store_b32 v[6:7], v13, off
	global_load_b96 v[13:15], v[8:9], off
	global_load_b96 v[16:18], v[20:21], off
	v_add_nc_u32_e32 v8, 3, v19
	v_add_co_u32 v6, vcc_lo, v20, 12
	v_add_co_ci_u32_e32 v7, vcc_lo, 0, v21, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v9, 31, v8
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v12, v14, v17
	v_fmac_f32_e32 v12, v13, v16
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v12, v15, v18
	s_branch .LBB0_58
.LBB0_54:
	s_mov_b32 s21, -1
	s_mov_b32 s19, 0
	s_mov_b32 s20, 0
                                        ; implicit-def: $vgpr12
                                        ; implicit-def: $vgpr6_vgpr7
                                        ; implicit-def: $vgpr8_vgpr9
	s_branch .LBB0_61
.LBB0_55:
	s_mov_b32 s21, -1
	s_mov_b32 s19, 0
	s_mov_b32 s20, 0
	s_branch .LBB0_57
.LBB0_56:
	s_mov_b32 s20, -1
	s_mov_b32 s19, 0
.LBB0_57:                               ; %Flow804
                                        ; implicit-def: $vgpr12
                                        ; implicit-def: $vgpr6_vgpr7
                                        ; implicit-def: $vgpr8_vgpr9
.LBB0_58:                               ; %Flow804
	s_and_b32 vcc_lo, exec_lo, s21
	s_cbranch_vccz .LBB0_60
; %bb.59:
	v_dual_mov_b32 v9, 0 :: v_dual_lshlrev_b32 v8, 2, v0
	s_mov_b32 s19, -1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[6:7], 2, v[8:9]
	v_add_co_u32 v12, vcc_lo, s12, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v13, vcc_lo, s13, v7, vcc_lo
	v_add_co_u32 v18, vcc_lo, s16, v6
	v_add_co_ci_u32_e32 v19, vcc_lo, s17, v7, vcc_lo
	global_load_b32 v15, v[12:13], off
	v_mov_b32_e32 v1, v9
	v_lshlrev_b64 v[20:21], 2, v[0:1]
	s_waitcnt vmcnt(0)
	v_ashrrev_i32_e32 v16, 31, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[16:17], 2, v[15:16]
	v_add_co_u32 v12, vcc_lo, s8, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v13, vcc_lo, s9, v17, vcc_lo
	global_load_b96 v[6:8], v[18:19], off
	global_load_b96 v[12:14], v[12:13], off
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v13, v13, v7
	v_fmac_f32_e32 v13, v12, v6
	v_add_co_u32 v6, vcc_lo, v2, v20
	v_add_co_ci_u32_e32 v7, vcc_lo, v3, v21, vcc_lo
	s_delay_alu instid0(VALU_DEP_3)
	v_fmac_f32_e32 v13, v14, v8
	v_add_co_u32 v8, vcc_lo, s10, v16
	v_add_co_ci_u32_e32 v9, vcc_lo, s11, v17, vcc_lo
	global_store_b32 v[6:7], v13, off
	global_load_b96 v[6:8], v[8:9], off
	global_load_b96 v[12:14], v[18:19], off
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v13, v7, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v13, v6, v12
	v_add_co_u32 v6, vcc_lo, v10, v20
	v_add_co_ci_u32_e32 v7, vcc_lo, v11, v21, vcc_lo
	v_fmac_f32_e32 v13, v8, v14
	v_add_co_u32 v8, vcc_lo, s2, v16
	v_add_co_ci_u32_e32 v9, vcc_lo, s3, v17, vcc_lo
	global_store_b32 v[6:7], v13, off
	global_load_b64 v[13:14], v[8:9], off
	global_load_b64 v[16:17], v[18:19], off
	v_add_nc_u32_e32 v8, 2, v15
	v_add_co_u32 v6, vcc_lo, v18, 8
	v_add_co_ci_u32_e32 v7, vcc_lo, 0, v19, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v9, 31, v8
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v12, v14, v17
	v_fmac_f32_e32 v12, v13, v16
.LBB0_60:                               ; %Flow806
	s_mov_b32 s21, 0
.LBB0_61:                               ; %Flow803
	v_add_co_u32 v4, vcc_lo, s18, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s7, v5, vcc_lo
	s_and_b32 vcc_lo, exec_lo, s21
	s_cbranch_vccz .LBB0_63
; %bb.62:                               ; %LeafBlock788
	s_cmp_lg_u32 s28, 2
	s_mov_b32 s6, -1
	s_cselect_b32 s20, -1, 0
                                        ; implicit-def: $vgpr12
                                        ; implicit-def: $vgpr6_vgpr7
                                        ; implicit-def: $vgpr8_vgpr9
.LBB0_63:                               ; %Flow807
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s20
	s_cbranch_vccnz .LBB0_68
; %bb.64:
	s_cmp_lt_i32 s28, 5
	s_cselect_b32 s6, -1, 0
	s_cmp_lt_i32 s27, 1
	s_cselect_b32 s7, -1, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s6, s6, s7
	s_and_b32 vcc_lo, exec_lo, s6
	s_cbranch_vccnz .LBB0_67
; %bb.65:                               ; %.lr.ph645.preheader
	v_mov_b32_e32 v1, 0
.LBB0_66:                               ; %.lr.ph645
                                        ; =>This Inner Loop Header: Depth=1
	s_load_b32 s6, s[0:1], 0x0
	s_load_b32 s20, s[14:15], 0x0
	s_waitcnt lgkmcnt(0)
	s_ashr_i32 s7, s6, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[6:7], s[6:7], 2
	s_add_u32 s22, s8, s6
	s_addc_u32 s23, s9, s7
	s_ashr_i32 s21, s20, 31
	s_clause 0x1
	global_load_b32 v12, v1, s[22:23]
	global_load_b32 v13, v1, s[4:5]
	s_lshl_b64 s[20:21], s[20:21], 2
	s_add_u32 s22, s10, s6
	v_add_co_u32 v6, vcc_lo, v2, s20
	v_add_co_ci_u32_e32 v7, vcc_lo, s21, v3, vcc_lo
	v_add_co_u32 v8, vcc_lo, v10, s20
	v_add_co_ci_u32_e32 v9, vcc_lo, s21, v11, vcc_lo
	global_load_b32 v14, v[6:7], off
	s_addc_u32 s23, s11, s7
	s_add_u32 s6, s2, s6
	s_addc_u32 s7, s3, s7
	s_add_i32 s27, s27, -1
	s_add_u32 s0, s0, 4
	s_addc_u32 s1, s1, 0
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v14, v12, v13
	global_store_b32 v[6:7], v14, off
	s_clause 0x1
	global_load_b32 v12, v1, s[22:23]
	global_load_b32 v13, v1, s[4:5]
	global_load_b32 v14, v[8:9], off
	v_add_co_u32 v6, vcc_lo, v4, s20
	v_add_co_ci_u32_e32 v7, vcc_lo, s21, v5, vcc_lo
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v14, v12, v13
	global_store_b32 v[8:9], v14, off
	s_clause 0x1
	global_load_b32 v8, v1, s[6:7]
	global_load_b32 v9, v1, s[4:5]
	global_load_b32 v12, v[6:7], off
	s_add_u32 s4, s4, 4
	s_addc_u32 s5, s5, 0
	s_add_u32 s14, s14, 4
	s_addc_u32 s15, s15, 0
	s_cmp_eq_u32 s27, 0
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v12, v8, v9
	global_store_b32 v[6:7], v12, off
	s_cbranch_scc0 .LBB0_66
.LBB0_67:                               ; %Flow802
	s_mov_b32 s6, 0
                                        ; implicit-def: $vgpr12
                                        ; implicit-def: $vgpr6_vgpr7
                                        ; implicit-def: $vgpr8_vgpr9
.LBB0_68:                               ; %Flow808
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s6
	s_cbranch_vccnz .LBB0_70
; %bb.69:
	v_dual_mov_b32 v7, 0 :: v_dual_lshlrev_b32 v6, 2, v0
	s_mov_b32 s19, -1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[8:9], 2, v[6:7]
	v_add_co_u32 v12, vcc_lo, s12, v8
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v13, vcc_lo, s13, v9, vcc_lo
	v_add_co_u32 v15, vcc_lo, s16, v8
	v_add_co_ci_u32_e32 v16, vcc_lo, s17, v9, vcc_lo
	global_load_b32 v12, v[12:13], off
	s_waitcnt vmcnt(0)
	v_ashrrev_i32_e32 v13, 31, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[13:14], 2, v[12:13]
	v_add_co_u32 v8, vcc_lo, s8, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v9, vcc_lo, s9, v14, vcc_lo
	global_load_b64 v[17:18], v[15:16], off
	global_load_b64 v[8:9], v[8:9], off
	s_waitcnt vmcnt(0)
	v_dual_mov_b32 v1, v7 :: v_dual_mul_f32 v18, v9, v18
	v_lshlrev_b64 v[6:7], 2, v[0:1]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v18, v8, v17
	v_add_co_u32 v2, vcc_lo, v2, v6
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v3, vcc_lo, v3, v7, vcc_lo
	v_add_co_u32 v8, vcc_lo, s10, v13
	v_add_co_ci_u32_e32 v9, vcc_lo, s11, v14, vcc_lo
	global_store_b32 v[2:3], v18, off
	global_load_b64 v[2:3], v[8:9], off
	global_load_b64 v[8:9], v[15:16], off
	v_add_co_u32 v6, vcc_lo, v10, v6
	v_add_co_ci_u32_e32 v7, vcc_lo, v11, v7, vcc_lo
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v9, v3, v9
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v9, v2, v8
	v_add_nc_u32_e32 v8, 1, v12
	v_add_co_u32 v2, vcc_lo, s2, v13
	v_add_co_ci_u32_e32 v3, vcc_lo, s3, v14, vcc_lo
	global_store_b32 v[6:7], v9, off
	global_load_b32 v2, v[2:3], off
	global_load_b32 v3, v[15:16], off
	v_add_co_u32 v6, vcc_lo, v15, 4
	v_ashrrev_i32_e32 v9, 31, v8
	v_add_co_ci_u32_e32 v7, vcc_lo, 0, v16, vcc_lo
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v12, v2, v3
.LBB0_70:                               ; %Flow809
	s_and_not1_b32 vcc_lo, exec_lo, s19
	s_cbranch_vccnz .LBB0_72
; %bb.71:                               ; %.loopexit.sink.split
	v_lshlrev_b64 v[2:3], 2, v[8:9]
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v2, vcc_lo, s2, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_u32 v0, vcc_lo, v4, v0
	global_load_b32 v6, v[6:7], off
	global_load_b32 v2, v[2:3], off
	v_add_co_ci_u32_e32 v1, vcc_lo, v5, v1, vcc_lo
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v12, v2, v6
	global_store_b32 v[0:1], v12, off
.LBB0_72:                               ; %.loopexit
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
.LBB0_73:
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z31lin2lin_resmpl_messy_gpu_kernelPfS_S_S_S_iiiiifiiiiiiPiS0_S_S0_S0_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 392
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 32
		.amdhsa_next_free_sgpr 46
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z31lin2lin_resmpl_messy_gpu_kernelPfS_S_S_S_iiiiifiiiiiiPiS0_S_S0_S0_S_, .Lfunc_end0-_Z31lin2lin_resmpl_messy_gpu_kernelPfS_S_S_S_iiiiifiiiiiiPiS0_S_S0_S0_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 5080
; NumSgprs: 48
; NumVgprs: 32
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 5
; VGPRBlocks: 3
; NumSGPRsForWavesPerEU: 48
; NumVGPRsForWavesPerEU: 32
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.protected	lTable_const            ; @lTable_const
	.type	lTable_const,@object
	.section	.bss,"aw",@nobits
	.globl	lTable_const
	.p2align	4, 0x0
lTable_const:
	.zero	4256
	.size	lTable_const, 4256

	.protected	mr_const                ; @mr_const
	.type	mr_const,@object
	.globl	mr_const
	.p2align	2, 0x0
mr_const:
	.zero	12
	.size	mr_const, 12

	.protected	mg_const                ; @mg_const
	.type	mg_const,@object
	.globl	mg_const
	.p2align	2, 0x0
mg_const:
	.zero	12
	.size	mg_const, 12

	.protected	mb_const                ; @mb_const
	.type	mb_const,@object
	.globl	mb_const
	.p2align	2, 0x0
mb_const:
	.zero	12
	.size	mb_const, 12

	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .offset:         40
        .size:           4
        .value_kind:     by_value
      - .offset:         44
        .size:           4
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     by_value
      - .offset:         52
        .size:           4
        .value_kind:     by_value
      - .offset:         56
        .size:           4
        .value_kind:     by_value
      - .offset:         60
        .size:           4
        .value_kind:     by_value
      - .offset:         64
        .size:           4
        .value_kind:     by_value
      - .offset:         68
        .size:           4
        .value_kind:     by_value
      - .offset:         72
        .size:           4
        .value_kind:     by_value
      - .offset:         76
        .size:           4
        .value_kind:     by_value
      - .offset:         80
        .size:           4
        .value_kind:     by_value
      - .offset:         84
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         88
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         96
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         104
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         112
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         120
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         128
        .size:           8
        .value_kind:     global_buffer
      - .offset:         136
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         140
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         144
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         148
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         150
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         152
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         154
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         156
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         158
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         176
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         184
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         192
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         200
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 392
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z31lin2lin_resmpl_messy_gpu_kernelPfS_S_S_S_iiiiifiiiiiiPiS0_S_S0_S0_S_
    .private_segment_fixed_size: 0
    .sgpr_count:     48
    .sgpr_spill_count: 0
    .symbol:         _Z31lin2lin_resmpl_messy_gpu_kernelPfS_S_S_S_iiiiifiiiiiiPiS0_S_S0_S0_S_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     32
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
