/**
    Merges to array A and B in M using a path

    @file pathMerge.cu
    @author Dang Vu Laurent Durand Homer
    @version 1.0 14/12/20
*/

#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <ctime>
#include <string>
#include <iostream>
#include <stdlib.h>


/**
    Verify cuda calls and return cuda error if any
*/
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(cudaError_t code, const char *file, int line, bool abort=true)
{
   if (code != cudaSuccess)
   {
      fprintf(stderr,"GPUassert: %s %s %d\n", cudaGetErrorString(code), file, line);
      if (abort) exit(code);
   }
}


/**
    Initialise ascendant array with random values
    @param array : the array to fill with random ascendant values
          size : Size of the arrays
          adder : Each x_i is higher than x_i-1 of a random value between 0 and adder
*/
void init_array(int* array, int size, int const adder=10)
{
    array[0] = rand()%adder;
    for(int i = 0; i < size;i++)
    {
        array[i] = array[i-1] + rand()%adder;
    }
}

/**
    Print an array of size size
    @param a : array to print
           size : size of arrays
*/
void print_array(int* a, int size)
{
    printf("[");
    for(int i = 0; i < size;i++)
    {
        printf("%d " , a[i]);
    }
    printf("]\n");
}

/**
    Sequential version of merge
    @param a_k, b_k : array to merge
           m_k : merge of a and b
           n_a, n_b, n_b : respective sizes of a_k, b_k, m_k
*/
void mergeSeq(int *a_k, int *b_k, int *m_k, int n_a, int n_b, int n_m)
{
  int i, j;
  i=0;
  j=0;
  while(i+j < n_m)
  {
    if (i>= n_a)
    {
      m_k[i+j]=b_k[j];
      j++;
    }
    else if (j>= n_b || a_k[i] < b_k[j])
    {
      m_k[i+j]=a_k[i];
      i++;
    }
    else
    {
      m_k[i+j]=b_k[j];
      j++;
    }
  }
}


/**
    Parallel version of merge of A and B with |A| + |B| <= 1024
    @param d_a, d_b : device versions of arrays to merge
           d_m : device version of merge of a and b
           n_a, n_b, n_b : respective sizes of d_a, d_b, d_m
*/
__device__ void mergeSmall_k(int* d_a, int* d_b, int* d_m, int n_a, int n_b, int n_m){
    int i = threadIdx.x;
    if(i < n_m)
    {
        int2 K;
        int2 P;
        int2 Q;
        if(i > n_a)
        {
            K.x = i - n_a;
            K.y = n_a;
            P.x = n_a;
            P.y = i - n_a;
        }
        else
        {
            K.x = 0;
            K.y = i;
            P.x = i;
            P.y = 0;
        }

        int offset = 0;
        while(1)
        {
            offset = abs(K.y - P.y)/2;
            Q.x = K.x + offset;
            Q.y = K.y - offset;
            if(Q.y >= 0 && Q.x <= n_b && (Q.y == n_a || Q.x == 0 || d_a[Q.y] > d_b[Q.x - 1]))
            {
                if(Q.x == n_b || Q.y == 0 || d_a[Q.y - 1] <= d_b[Q.x])
                {
                    if(Q.y < n_a && (Q.x == n_b || d_a[Q.y] <= d_b[Q.x]))
                    {
                        d_m[i] = d_a[Q.y];
                    }
                    else
                    {
                        d_m[i] = d_b[Q.x];
                    }
                    break;
                }
                else
                {
                    K.x = Q.x + 1;
                    K.y = Q.y - 1;
                }
            }
            else
            {
              P.x = Q.x - 1;
              P.y = Q.y + 1;

            }

        }
    }
}


/**
    Parallel version of merge of A and B of any sizes
    @param a, b : device versions of arrays to merge
           m : device version of merge of a and b
           n_a, n_b, n_b : respective sizes of d_a, d_b, d_m
           path : points of the path to cut A and B to pieces to merge
           n_path : number of points in the path
           nb_partition : number of pieces of A and B (a_k and b_k) to merge with mergeSmall_k
*/
__global__ void mergeBig_k(int *m, int n_m, int *a, int n_a, int *b, int n_b, int2 *path, int n_path, int nbPartitions)
{
  int blockId = blockIdx.x;
  int threadId = threadIdx.x;
  int i = blockId * blockDim.x + threadId;
  if (blockId <= nbPartitions)//On utilise un block pour chaque partition
  {
    int x0, y0, x1, y1;
    x0 = path[blockId].x;
    y0 = path[blockId].y;
    x1 = path[blockId+1].x;
    y1 = path[blockId+1].y;

    const int dimx=x1-x0;
    const int dimy = y1-y0;

    //A modifier par dimx dimy dimx+dimy
     __shared__ int a_k[1024];
     __shared__ int b_k[1024];
     __shared__ int m_k[1024];

    if (threadId < dimx) //On rempli a_k[i] :  0 <= i < dimx
    {
      a_k[threadId] = a[x0+threadId];
    }
    else if (threadId < dimy+dimx)//On rempli b_k[i] : indice dimx <= i < dimx+dimy+1
    {
      b_k[threadId-dimx] = b[y0+threadId-dimx];
    }
    __syncthreads();
    mergeSmall_k(a_k, b_k, m_k, dimx, dimy, dimx+dimy);
    m[i] = m_k[threadId];

  }
}

/**
    Genearte the path to devide A and B to pieces that we'll give to mergeSmall_k
    @param pas: size of pieces
           path : store the points of the path
           n_path : number of points in the path
           nb_partition : number of pieces of A and B (a_k and b_k) to merge with mergeSmall_k
           d_a, d_b : device versions of arrays to merge
           n_a, n_b : respective sizes of d_a, d_b
*/
__global__ void pathBig_k(int pas, int2* path, int n_path , int* d_a, int n_a ,int* d_b, int n_b)
{
    int thread_i = blockIdx.x * blockDim.x + threadIdx.x;
    if(thread_i <= (n_a + n_b)/pas)        //<------------//On vérifie que l'indice du thread est inférieur à la taille du tableau de retour et qu'il est un multiple du pas
    {
        int i = thread_i*pas;
        int2 K;
        int2 P;
        int2 Q;
        if(i > n_a)
        {
            K.x = i - n_a;
            K.y = n_a;
            P.x = n_a;
            P.y = i - n_a;
        }
        else
        {
            K.x = 0;
            K.y = i;
            P.x = i;
            P.y = 0;
        }

        int offset = 0;
        while(1)
        {
            //Calcul des coordonnées du milieu de P et K
            offset = abs(K.y - P.y)/2;
            Q.x = K.x + offset;
            Q.y = K.y - offset;

            //
            if(Q.y >= 0 && Q.x <= n_b && (Q.y == n_a || Q.x == 0 || d_a[Q.y] > d_b[Q.x - 1]))
            {
                //
                if(Q.x == n_b || Q.y == 0 || d_a[Q.y - 1] <= d_b[Q.x])
                {
                  break;
                }
                else
                {
                    K.x = Q.x + 1;
                    K.y = Q.y - 1;
                }
            }
            else
            {
              P.x = Q.x - 1;
              P.y = Q.y + 1;

            }

        }
        //printf("thread : %d => (%d, %d)\n", thread_i, Q.y, Q.x);
        //!\\ Problème ordre x et y
        path[thread_i].x=Q.y;
        path[thread_i].y=Q.x;
    }
    //Si |m| n'est pas un mutliple de pas, le thread 0 ajoute (n_a, n_b) à la fin du tableau
    if (thread_i==0 && (n_a+n_b)%pas!=0)
    {
      //printf("thread : %d => (%d, %d)\n", thread_i, n_a, n_b);
      path[n_path-1].x=n_a;
      path[n_path-1].y=n_b;
    }

}

/**
    verify that A and B are correctly merge in M
*/
int assertMerge(int *tab, int *tab2, int size)
{
  for (int i=0; i<size-1; i++)
  {
    if (tab[i] > tab[i+1] || tab[i] != tab2[i] || (i>10000 && tab[i] == 0))
    {
      printf("WARNING : Unsuccessful merge on indice %d ...\n", i);
      return 0;
    }
  }
  printf("Successful merge !\n");
  return 1;

}


/**
    Merge 2 lists of arrays {A_i} and {B_i} in {M_i}1<=i<=N
    @param argv[1] : size of A
           argv[2] : size of B
*/
int main(int argc, char *argv[])
{
    std::clock_t startS, endS;
    float seqMergeTime, parMergeTime, DoH, HoD;

    srand(time(NULL));
    int n_a, n_b;
    int pas;
    if(argc>= 3)
    {
      n_a = atoi(argv[1]);
      n_b = atoi(argv[2]);
      pas = atoi(argv[3]);
    }
    else
    {
      n_a = 100;
      n_b = 100;
      pas = 1024;
    }
    int n_m = n_a+n_b;
     // <1024
    int nbPartitions = n_m/pas+(n_m%pas!=0); // On ajoute 1 si n_m n'est pas un mutliple de p
    int n_path = (1 + nbPartitions); //1(pour (0,0)) + |m|/pas(nbr de morceau de taille pas) + 1(si dernier morceau de taille < pas))
    printf("========== Merge of A and B ==========\n");
    printf("* Size of A : %d\n", n_a);
    printf("* Size of B : %d\n", n_b);
    printf("* Step : %d\n* Nbr of partitions : %d\n\n", pas, nbPartitions);

    //Initialisation des tableaux a et b
    int *a, *aGPU;
    a = (int*)malloc(n_a*sizeof(int));
    init_array(a, n_a, 10);
    gpuErrchk(cudaMalloc(&aGPU, n_a*sizeof(int)));

    int *b, *bGPU;
    b = (int*)malloc(n_b*sizeof(int));
    init_array(b, n_b, 10);
    gpuErrchk(cudaMalloc(&bGPU, n_b*sizeof(int)));

    // print_array(b, n_b);
    // print_array(a, n_a);

    int *m, *mGPU, *mseq;
    m = (int*)malloc(n_m*sizeof(int));
    mseq = (int*)malloc(n_m*sizeof(int));
    gpuErrchk(cudaMalloc(&mGPU, n_m*sizeof(int)));

    //Declaration et allocation de path
    int2 *pathGPU;
    gpuErrchk(cudaMalloc(&pathGPU, n_path*sizeof(int2)));

    startS = std::clock();
    gpuErrchk(cudaMemcpy(aGPU, a, n_a*sizeof(int), cudaMemcpyHostToDevice));
    gpuErrchk(cudaMemcpy(bGPU, b, n_b*sizeof(int), cudaMemcpyHostToDevice));
    endS = std::clock();
    HoD = (endS - startS) / (float) CLOCKS_PER_SEC;

    printf("Merge of A and B of size %d and %d runing...\n", n_a, n_b);
    startS = std::clock();
    //================ Parallel : =======================\\

    pathBig_k<<<nbPartitions/1024+1, 1024>>>(pas, pathGPU, n_path, aGPU, n_a, bGPU, n_b);

    mergeBig_k<<<nbPartitions, pas>>>(mGPU, n_m, aGPU, n_a, bGPU, n_b, pathGPU, n_path, nbPartitions);

    cudaDeviceSynchronize();
    endS = std::clock();
    parMergeTime = (endS - startS) / (float) CLOCKS_PER_SEC;

    //Copy device to host
    startS = std::clock();
    cudaMemcpy(m, mGPU, n_m*sizeof(int), cudaMemcpyDeviceToHost);
    endS = std::clock();
    DoH = (endS - startS) / (float) CLOCKS_PER_SEC;

    printf("Merge done !\n\n");

    //================ Sequential : =======================\\
    startS = std::clock();
    mergeSeq(a, b, mseq, n_a, n_b, n_m);
    endS = std::clock();
    seqMergeTime = (endS - startS) / (float) CLOCKS_PER_SEC;

    //print_array(m, n_m);
    // print_array(mseq, n_m);

    printf("\n========= Sequential merge : =============\n");
    printf("Total time elapsed : %f s\n", seqMergeTime);
    printf("\n");

    printf("========= Parallel merge : =============\n");
    printf("Total time elapsed : %f s\n", parMergeTime+DoH+HoD);
    printf("Time running algorithm : %f s\n", parMergeTime);
    printf("Time to copy Host to Device : %f s\n", HoD);
    printf("Time to copy Device to Host : %f s\n", DoH);
    assertMerge(m, mseq, n_m);
    printf("Parrallel algorithm is %f times faster than sequential merge !\n", seqMergeTime/parMergeTime);
    printf("Parrallel merge is %f times faster than sequential merge !\n", seqMergeTime/(parMergeTime+HoD+DoH));






    //desallocation
    cudaFree(aGPU);
    cudaFree(bGPU);
    cudaFree(pathGPU);

    return 0;
}

	.file	"tmpxft_0029b5b2_00000000-6_pathMerge.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3644:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3644:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.section	.rodata._Z9gpuAssert9cudaErrorPKcib.str1.1,"aMS",@progbits,1
.LC0:
	.string	"GPUassert: %s %s %d\n"
	.section	.text._Z9gpuAssert9cudaErrorPKcib,"axG",@progbits,_Z9gpuAssert9cudaErrorPKcib,comdat
	.weak	_Z9gpuAssert9cudaErrorPKcib
	.type	_Z9gpuAssert9cudaErrorPKcib, @function
_Z9gpuAssert9cudaErrorPKcib:
.LFB3635:
	.cfi_startproc
	endbr64
	testl	%edi, %edi
	je	.L8
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	movl	%ecx, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 24
	.cfi_offset 3, -24
	movl	%edi, %ebx
	subq	$24, %rsp
	.cfi_def_cfa_offset 48
	movl	%edx, 12(%rsp)
	movq	%rsi, (%rsp)
	call	cudaGetErrorString@PLT
	movl	12(%rsp), %r9d
	movq	(%rsp), %r8
	leaq	.LC0(%rip), %rdx
	movq	stderr(%rip), %rdi
	movq	%rax, %rcx
	movl	$2, %esi
	xorl	%eax, %eax
	call	__fprintf_chk@PLT
	testb	%bpl, %bpl
	je	.L2
	movl	%ebx, %edi
	call	exit@PLT
.L2:
	addq	$24, %rsp
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	ret
.L8:
	.cfi_restore 3
	.cfi_restore 6
	ret
	.cfi_endproc
.LFE3635:
	.size	_Z9gpuAssert9cudaErrorPKcib, .-_Z9gpuAssert9cudaErrorPKcib
	.text
	.globl	_Z10init_arrayPiii
	.type	_Z10init_arrayPiii, @function
_Z10init_arrayPiii:
.LFB3636:
	.cfi_startproc
	endbr64
	pushq	%r14
	.cfi_def_cfa_offset 16
	.cfi_offset 14, -16
	pushq	%r13
	.cfi_def_cfa_offset 24
	.cfi_offset 13, -24
	movl	%esi, %r13d
	pushq	%r12
	.cfi_def_cfa_offset 32
	.cfi_offset 12, -32
	movq	%rdi, %r12
	pushq	%rbp
	.cfi_def_cfa_offset 40
	.cfi_offset 6, -40
	xorl	%ebp, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 48
	.cfi_offset 3, -48
	movl	%edx, %ebx
	call	rand@PLT
	cltd
	idivl	%ebx
	movl	%edx, (%r12)
.L13:
	cmpl	%ebp, %r13d
	jle	.L16
	movl	-4(%r12,%rbp,4), %r14d
	call	rand@PLT
	cltd
	idivl	%ebx
	addl	%r14d, %edx
	movl	%edx, (%r12,%rbp,4)
	incq	%rbp
	jmp	.L13
.L16:
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%rbp
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r13
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3636:
	.size	_Z10init_arrayPiii, .-_Z10init_arrayPiii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC1:
	.string	"["
.LC2:
	.string	"%d "
.LC3:
	.string	"]\n"
	.text
	.globl	_Z11print_arrayPii
	.type	_Z11print_arrayPii, @function
_Z11print_arrayPii:
.LFB3637:
	.cfi_startproc
	endbr64
	pushq	%r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	xorl	%eax, %eax
	leaq	.LC2(%rip), %r13
	pushq	%r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	movq	%rdi, %r12
	movl	$2, %edi
	pushq	%rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	movl	%esi, %ebp
	leaq	.LC1(%rip), %rsi
	pushq	%rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	xorl	%ebx, %ebx
	pushq	%rcx
	.cfi_def_cfa_offset 48
	call	__printf_chk@PLT
.L18:
	cmpl	%ebx, %ebp
	jle	.L21
	movl	(%r12,%rbx,4), %edx
	movq	%r13, %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	incq	%rbx
	call	__printf_chk@PLT
	jmp	.L18
.L21:
	popq	%rdx
	.cfi_def_cfa_offset 40
	leaq	.LC3(%rip), %rsi
	popq	%rbx
	.cfi_def_cfa_offset 32
	movl	$2, %edi
	popq	%rbp
	.cfi_def_cfa_offset 24
	xorl	%eax, %eax
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	__printf_chk@PLT
	.cfi_endproc
.LFE3637:
	.size	_Z11print_arrayPii, .-_Z11print_arrayPii
	.globl	_Z8mergeSeqPiS_S_iii
	.type	_Z8mergeSeqPiS_S_iii, @function
_Z8mergeSeqPiS_S_iii:
.LFB3638:
	.cfi_startproc
	endbr64
	movq	%rdx, %r10
	xorl	%eax, %eax
	xorl	%edx, %edx
	movl	%ecx, %r11d
	leal	(%rdx,%rax), %ecx
	cmpl	%r9d, %ecx
	jl	.L31
	ret
.L31:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	pushq	%rbx
	.cfi_def_cfa_offset 24
	.cfi_offset 3, -24
.L28:
	movslq	%ecx, %rcx
	leaq	(%r10,%rcx,4), %rbp
	cmpl	%r11d, %edx
	jl	.L24
	movslq	%eax, %rcx
	movl	(%rsi,%rcx,4), %ecx
	jmp	.L27
.L24:
	movslq	%edx, %rcx
	movl	(%rdi,%rcx,4), %ebx
	cmpl	%r8d, %eax
	jge	.L26
	movslq	%eax, %rcx
	movl	(%rsi,%rcx,4), %ecx
	cmpl	%ebx, %ecx
	jle	.L27
.L26:
	incl	%edx
	movl	%ebx, %ecx
	jmp	.L25
.L27:
	incl	%eax
.L25:
	movl	%ecx, 0(%rbp)
	leal	(%rdx,%rax), %ecx
	cmpl	%r9d, %ecx
	jl	.L28
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3638:
	.size	_Z8mergeSeqPiS_S_iii, .-_Z8mergeSeqPiS_S_iii
	.globl	_Z12mergeSmall_kPiS_S_iii
	.type	_Z12mergeSmall_kPiS_S_iii, @function
_Z12mergeSmall_kPiS_S_iii:
.LFB3639:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE3639:
	.size	_Z12mergeSmall_kPiS_S_iii, .-_Z12mergeSmall_kPiS_S_iii
	.section	.rodata.str1.1
.LC4:
	.string	"WARNING : Unsuccessful merge on indice %d ...\n"
.LC5:
	.string	"Successful merge !\n"
	.text
	.globl	_Z11assertMergePiS_i
	.type	_Z11assertMergePiS_i, @function
_Z11assertMergePiS_i:
.LFB3640:
	.cfi_startproc
	endbr64
	pushq	%rcx
	.cfi_def_cfa_offset 16
	movl	%edx, %eax
	xorl	%edx, %edx
	decl	%eax
.L35:
	movl	%edx, %r8d
	cmpl	%edx, %eax
	jle	.L46
	movl	(%rdi,%rdx,4), %ecx
	cmpl	4(%rdi,%rdx,4), %ecx
	jle	.L36
.L38:
	leaq	.LC4(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	xorl	%eax, %eax
	jmp	.L34
.L36:
	cmpl	(%rsi,%rdx,4), %ecx
	jne	.L38
	leaq	1(%rdx), %r9
	testl	%ecx, %ecx
	jne	.L41
	cmpl	$10000, %r8d
	jg	.L38
.L41:
	movq	%r9, %rdx
	jmp	.L35
.L46:
	leaq	.LC5(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movl	$1, %eax
.L34:
	popq	%rdx
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3640:
	.size	_Z11assertMergePiS_i, .-_Z11assertMergePiS_i
	.globl	_Z45__device_stub__Z10mergeBig_kPiiS_iS_iP4int2iiPiiS_iS_iP4int2ii
	.type	_Z45__device_stub__Z10mergeBig_kPiiS_iS_iP4int2iiPiiS_iS_iP4int2ii, @function
_Z45__device_stub__Z10mergeBig_kPiiS_iS_iP4int2iiPiiS_iS_iP4int2ii:
.LFB3666:
	.cfi_startproc
	endbr64
	subq	$200, %rsp
	.cfi_def_cfa_offset 208
	movq	208(%rsp), %rax
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movl	%esi, 36(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	48(%rsp), %rdx
	movl	%ecx, 32(%rsp)
	leaq	56(%rsp), %rcx
	movq	%r8, 16(%rsp)
	movl	%r9d, 12(%rsp)
	movq	%rax, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 184(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 112(%rsp)
	leaq	36(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 152(%rsp)
	movq	%rsp, %rax
	movq	%rax, 160(%rsp)
	leaq	216(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	224(%rsp), %rax
	movq	%rax, 176(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L47
	pushq	56(%rsp)
	.cfi_def_cfa_offset 216
	leaq	_Z10mergeBig_kPiiS_iS_iP4int2ii(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 224
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 216
	popq	%rdx
	.cfi_def_cfa_offset 208
.L47:
	movq	184(%rsp), %rax
	subq	%fs:40, %rax
	je	.L49
	call	__stack_chk_fail@PLT
.L49:
	addq	$200, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3666:
	.size	_Z45__device_stub__Z10mergeBig_kPiiS_iS_iP4int2iiPiiS_iS_iP4int2ii, .-_Z45__device_stub__Z10mergeBig_kPiiS_iS_iP4int2iiPiiS_iS_iP4int2ii
	.globl	_Z10mergeBig_kPiiS_iS_iP4int2ii
	.type	_Z10mergeBig_kPiiS_iS_iP4int2ii, @function
_Z10mergeBig_kPiiS_iS_iP4int2ii:
.LFB3667:
	.cfi_startproc
	endbr64
	jmp	_Z45__device_stub__Z10mergeBig_kPiiS_iS_iP4int2iiPiiS_iS_iP4int2ii
	.cfi_endproc
.LFE3667:
	.size	_Z10mergeBig_kPiiS_iS_iP4int2ii, .-_Z10mergeBig_kPiiS_iS_iP4int2ii
	.globl	_Z41__device_stub__Z9pathBig_kiP4int2iPiiS1_iiP4int2iPiiS1_i
	.type	_Z41__device_stub__Z9pathBig_kiP4int2iPiiS1_iiP4int2iPiiS1_i, @function
_Z41__device_stub__Z9pathBig_kiP4int2iPiiS1_iiP4int2iPiiS1_i:
.LFB3668:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movl	%edi, 44(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movl	%edx, 40(%rsp)
	leaq	48(%rsp), %rdx
	movq	%rcx, 24(%rsp)
	leaq	56(%rsp), %rcx
	movl	%r8d, 20(%rsp)
	movq	%r9, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	44(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 112(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	192(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L52
	pushq	56(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z9pathBig_kiP4int2iPiiS1_i(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 208
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L52:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L54
	call	__stack_chk_fail@PLT
.L54:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3668:
	.size	_Z41__device_stub__Z9pathBig_kiP4int2iPiiS1_iiP4int2iPiiS1_i, .-_Z41__device_stub__Z9pathBig_kiP4int2iPiiS1_iiP4int2iPiiS1_i
	.globl	_Z9pathBig_kiP4int2iPiiS1_i
	.type	_Z9pathBig_kiP4int2iPiiS1_i, @function
_Z9pathBig_kiP4int2iPiiS1_i:
.LFB3669:
	.cfi_startproc
	endbr64
	jmp	_Z41__device_stub__Z9pathBig_kiP4int2iPiiS1_iiP4int2iPiiS1_i
	.cfi_endproc
.LFE3669:
	.size	_Z9pathBig_kiP4int2iPiiS1_i, .-_Z9pathBig_kiP4int2iPiiS1_i
	.section	.rodata.str1.1
.LC6:
	.string	"========== Merge of A and B ==========\n"
.LC7:
	.string	"* Size of A : %d\n"
.LC8:
	.string	"* Size of B : %d\n"
.LC9:
	.string	"* Step : %d\n* Nbr of partitions : %d\n\n"
.LC10:
	.string	"/home/ubuntu/Datasets/stackv2/train-structured/homerdurand/HPCA/main/pathMerge.cu"
.LC12:
	.string	"Merge of A and B of size %d and %d runing...\n"
.LC13:
	.string	"Merge done !\n\n"
.LC14:
	.string	"\n========= Sequential merge : =============\n"
.LC15:
	.string	"Total time elapsed : %f s\n"
.LC16:
	.string	"\n"
.LC17:
	.string	"========= Parallel merge : =============\n"
.LC18:
	.string	"Time running algorithm : %f s\n"
.LC19:
	.string	"Time to copy Host to Device : %f s\n"
.LC20:
	.string	"Time to copy Device to Host : %f s\n"
.LC21:
	.string	"Parrallel algorithm is %f times faster than sequential merge !\n"
.LC22:
	.string	"Parrallel merge is %f times faster than sequential merge !\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB3641:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movq	%rsi, %r12
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movl	%edi, %ebx
	xorl	%edi, %edi
	subq	$136, %rsp
	.cfi_def_cfa_offset 192
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	call	time@PLT
	movl	%eax, %edi
	call	srand@PLT
	cmpl	$2, %ebx
	jle	.L62
	movq	8(%r12), %rdi
	call	atoi@PLT
	movq	16(%r12), %rdi
	movl	%eax, %ebx
	call	atoi@PLT
	movq	24(%r12), %rdi
	movl	%eax, %ebp
	call	atoi@PLT
	movl	%eax, %r13d
	jmp	.L58
.L62:
	movl	$1024, %r13d
	movl	$100, %ebp
	movl	$100, %ebx
.L58:
	leal	(%rbx,%rbp), %eax
	leaq	.LC6(%rip), %rsi
	movl	$2, %edi
	cltd
	movl	%eax, 12(%rsp)
	idivl	%r13d
	cmpl	$1, %edx
	sbbl	$-1, %eax
	movl	%eax, %r12d
	leal	1(%rax), %r15d
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movl	%ebx, %edx
	leaq	.LC7(%rip), %rsi
	xorl	%eax, %eax
	movl	$2, %edi
	call	__printf_chk@PLT
	movl	%ebp, %edx
	leaq	.LC8(%rip), %rsi
	xorl	%eax, %eax
	movl	$2, %edi
	call	__printf_chk@PLT
	movl	%r12d, %ecx
	movl	%r13d, %edx
	movl	$2, %edi
	leaq	.LC9(%rip), %rsi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movslq	%ebx, %rax
	salq	$2, %rax
	movq	%rax, %rdi
	movq	%rax, 16(%rsp)
	call	malloc@PLT
	movl	$10, %edx
	movl	%ebx, %esi
	movq	%rax, %rdi
	movq	%rax, 32(%rsp)
	call	_Z10init_arrayPiii
	movq	16(%rsp), %rsi
	leaq	64(%rsp), %rdi
	call	cudaMalloc@PLT
	movl	$1, %ecx
	movl	$340, %edx
	leaq	.LC10(%rip), %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKcib
	movslq	%ebp, %rax
	salq	$2, %rax
	movq	%rax, %rdi
	movq	%rax, 24(%rsp)
	call	malloc@PLT
	movl	$10, %edx
	movl	%ebp, %esi
	movq	%rax, %rdi
	movq	%rax, 40(%rsp)
	call	_Z10init_arrayPiii
	movq	24(%rsp), %rsi
	leaq	72(%rsp), %rdi
	call	cudaMalloc@PLT
	movl	$1, %ecx
	movl	$345, %edx
	leaq	.LC10(%rip), %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKcib
	movslq	12(%rsp), %rax
	salq	$2, %rax
	movq	%rax, %rdi
	movq	%rax, (%rsp)
	call	malloc@PLT
	movq	(%rsp), %rdi
	movq	%rax, 48(%rsp)
	call	malloc@PLT
	movq	(%rsp), %rsi
	leaq	80(%rsp), %rdi
	movq	%rax, 56(%rsp)
	call	cudaMalloc@PLT
	movl	$1, %ecx
	movl	$353, %edx
	leaq	.LC10(%rip), %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKcib
	movslq	%r15d, %rsi
	leaq	88(%rsp), %rdi
	salq	$3, %rsi
	call	cudaMalloc@PLT
	movl	$1, %ecx
	movl	$357, %edx
	leaq	.LC10(%rip), %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKcib
	call	clock@PLT
	movq	16(%rsp), %rdx
	movq	32(%rsp), %rsi
	movl	$1, %ecx
	movq	64(%rsp), %rdi
	movq	%rax, %r14
	call	cudaMemcpy@PLT
	movl	$1, %ecx
	movl	$360, %edx
	leaq	.LC10(%rip), %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKcib
	movq	24(%rsp), %rdx
	movq	40(%rsp), %rsi
	movl	$1, %ecx
	movq	72(%rsp), %rdi
	call	cudaMemcpy@PLT
	movl	$1, %ecx
	movl	$361, %edx
	leaq	.LC10(%rip), %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKcib
	call	clock@PLT
	movl	%ebp, %ecx
	movl	%ebx, %edx
	leaq	.LC12(%rip), %rsi
	subq	%r14, %rax
	movl	$2, %edi
	cvtsi2ssq	%rax, %xmm0
	xorl	%eax, %eax
	divss	.LC11(%rip), %xmm0
	movss	%xmm0, 24(%rsp)
	call	__printf_chk@PLT
	call	clock@PLT
	movl	$1024, %esi
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	%rax, %r14
	movl	%r12d, %eax
	movl	$4194305, %ecx
	movl	$1, 116(%rsp)
	cltd
	salq	$10, %rcx
	idivl	%esi
	movq	%rcx, 108(%rsp)
	movq	%rcx, %rdx
	movl	$1, %ecx
	incl	%eax
	movl	%eax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 100(%rsp)
	movq	96(%rsp), %rdi
	movl	104(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L59
	pushq	%rdx
	.cfi_def_cfa_offset 200
	movl	%ebx, %r8d
	movl	%r15d, %edx
	movl	%r13d, %edi
	pushq	%rbp
	.cfi_def_cfa_offset 208
	movq	88(%rsp), %r9
	movq	80(%rsp), %rcx
	movq	104(%rsp), %rsi
	call	_Z41__device_stub__Z9pathBig_kiP4int2iPiiS1_iiP4int2iPiiS1_i
	popq	%rcx
	.cfi_def_cfa_offset 200
	popq	%rsi
	.cfi_def_cfa_offset 192
.L59:
	movabsq	$4294967297, %rax
	movl	%r13d, 108(%rsp)
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	%rax, 112(%rsp)
	movl	116(%rsp), %ecx
	movq	%rax, 100(%rsp)
	movq	108(%rsp), %rdx
	movl	%r12d, 96(%rsp)
	movl	104(%rsp), %esi
	movq	96(%rsp), %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L60
	pushq	%rax
	.cfi_def_cfa_offset 200
	movl	%ebp, %r9d
	movl	%ebx, %ecx
	pushq	%r12
	.cfi_def_cfa_offset 208
	pushq	%r15
	.cfi_def_cfa_offset 216
	pushq	112(%rsp)
	.cfi_def_cfa_offset 224
	movq	104(%rsp), %r8
	movq	96(%rsp), %rdx
	movl	44(%rsp), %esi
	movq	112(%rsp), %rdi
	call	_Z45__device_stub__Z10mergeBig_kPiiS_iS_iP4int2iiPiiS_iS_iP4int2ii
	addq	$32, %rsp
	.cfi_def_cfa_offset 192
.L60:
	call	cudaDeviceSynchronize@PLT
	call	clock@PLT
	subq	%r14, %rax
	cvtsi2ssq	%rax, %xmm0
	divss	.LC11(%rip), %xmm0
	movss	%xmm0, 16(%rsp)
	call	clock@PLT
	movq	(%rsp), %rdx
	movq	80(%rsp), %rsi
	movl	$2, %ecx
	movq	48(%rsp), %rdi
	movq	%rax, %r12
	call	cudaMemcpy@PLT
	call	clock@PLT
	leaq	.LC13(%rip), %rsi
	movl	$2, %edi
	subq	%r12, %rax
	cvtsi2ssq	%rax, %xmm0
	xorl	%eax, %eax
	divss	.LC11(%rip), %xmm0
	movss	%xmm0, (%rsp)
	call	__printf_chk@PLT
	movl	12(%rsp), %r9d
	movl	%ebp, %r8d
	movl	%ebx, %ecx
	movq	56(%rsp), %rdx
	movq	40(%rsp), %rsi
	leaq	.LC15(%rip), %rbp
	movq	32(%rsp), %rdi
	call	_Z8mergeSeqPiS_S_iii
	call	clock@PLT
	leaq	.LC14(%rip), %rsi
	movl	$2, %edi
	subq	%r12, %rax
	cvtsi2ssq	%rax, %xmm0
	xorl	%eax, %eax
	divss	.LC11(%rip), %xmm0
	movd	%xmm0, %ebx
	call	__printf_chk@PLT
	movd	%ebx, %xmm2
	movq	%rbp, %rsi
	movb	$1, %al
	movl	$2, %edi
	cvtss2sd	%xmm2, %xmm0
	call	__printf_chk@PLT
	leaq	.LC16(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	leaq	.LC17(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movss	16(%rsp), %xmm0
	movq	%rbp, %rsi
	movb	$1, %al
	addss	(%rsp), %xmm0
	addss	24(%rsp), %xmm0
	movl	$2, %edi
	cvtss2sd	%xmm0, %xmm0
	call	__printf_chk@PLT
	movl	$2, %edi
	leaq	.LC18(%rip), %rsi
	movb	$1, %al
	cvtss2sd	16(%rsp), %xmm0
	call	__printf_chk@PLT
	leaq	.LC19(%rip), %rsi
	movl	$2, %edi
	movb	$1, %al
	cvtss2sd	24(%rsp), %xmm0
	call	__printf_chk@PLT
	movl	$2, %edi
	leaq	.LC20(%rip), %rsi
	movb	$1, %al
	cvtss2sd	(%rsp), %xmm0
	call	__printf_chk@PLT
	movl	12(%rsp), %edx
	movq	56(%rsp), %rsi
	movq	48(%rsp), %rdi
	call	_Z11assertMergePiS_i
	movl	$2, %edi
	movb	$1, %al
	movd	%ebx, %xmm0
	leaq	.LC21(%rip), %rsi
	divss	16(%rsp), %xmm0
	cvtss2sd	%xmm0, %xmm0
	call	__printf_chk@PLT
	movd	%ebx, %xmm0
	movl	$2, %edi
	movb	$1, %al
	movss	24(%rsp), %xmm1
	addss	16(%rsp), %xmm1
	leaq	.LC22(%rip), %rsi
	addss	(%rsp), %xmm1
	divss	%xmm1, %xmm0
	cvtss2sd	%xmm0, %xmm0
	call	__printf_chk@PLT
	movq	64(%rsp), %rdi
	call	cudaFree@PLT
	movq	72(%rsp), %rdi
	call	cudaFree@PLT
	movq	88(%rsp), %rdi
	call	cudaFree@PLT
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L61
	call	__stack_chk_fail@PLT
.L61:
	addq	$136, %rsp
	.cfi_def_cfa_offset 56
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3641:
	.size	main, .-main
	.section	.rodata.str1.1
.LC23:
	.string	"_Z9pathBig_kiP4int2iPiiS1_i"
.LC24:
	.string	"_Z10mergeBig_kPiiS_iS_iP4int2ii"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3671:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC23(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z9pathBig_kiP4int2iPiiS1_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC24(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z10mergeBig_kPiiS_iS_iP4int2ii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3671:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst4,"aM",@progbits,4
	.align 4
.LC11:
	.long	1232348160
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

/**
    Merges to array A and B in M using a path

    @file pathMerge.cu
    @author Dang Vu Laurent Durand Homer
    @version 1.0 14/12/20
*/


#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <ctime>
#include <string>
#include <iostream>
#include <stdlib.h>


/**
    Verify cuda calls and return cuda error if any
*/
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(hipError_t code, const char *file, int line, bool abort=true)
{
   if (code != hipSuccess)
   {
      fprintf(stderr,"GPUassert: %s %s %d\n", hipGetErrorString(code), file, line);
      if (abort) exit(code);
   }
}


/**
    Initialise ascendant array with random values
    @param array : the array to fill with random ascendant values
          size : Size of the arrays
          adder : Each x_i is higher than x_i-1 of a random value between 0 and adder
*/
void init_array(int* array, int size, int const adder=10)
{
    array[0] = rand()%adder;
    for(int i = 0; i < size;i++)
    {
        array[i] = array[i-1] + rand()%adder;
    }
}

/**
    Print an array of size size
    @param a : array to print
           size : size of arrays
*/
void print_array(int* a, int size)
{
    printf("[");
    for(int i = 0; i < size;i++)
    {
        printf("%d " , a[i]);
    }
    printf("]\n");
}

/**
    Sequential version of merge
    @param a_k, b_k : array to merge
           m_k : merge of a and b
           n_a, n_b, n_b : respective sizes of a_k, b_k, m_k
*/
void mergeSeq(int *a_k, int *b_k, int *m_k, int n_a, int n_b, int n_m)
{
  int i, j;
  i=0;
  j=0;
  while(i+j < n_m)
  {
    if (i>= n_a)
    {
      m_k[i+j]=b_k[j];
      j++;
    }
    else if (j>= n_b || a_k[i] < b_k[j])
    {
      m_k[i+j]=a_k[i];
      i++;
    }
    else
    {
      m_k[i+j]=b_k[j];
      j++;
    }
  }
}


/**
    Parallel version of merge of A and B with |A| + |B| <= 1024
    @param d_a, d_b : device versions of arrays to merge
           d_m : device version of merge of a and b
           n_a, n_b, n_b : respective sizes of d_a, d_b, d_m
*/
__device__ void mergeSmall_k(int* d_a, int* d_b, int* d_m, int n_a, int n_b, int n_m){
    int i = threadIdx.x;
    if(i < n_m)
    {
        int2 K;
        int2 P;
        int2 Q;
        if(i > n_a)
        {
            K.x = i - n_a;
            K.y = n_a;
            P.x = n_a;
            P.y = i - n_a;
        }
        else
        {
            K.x = 0;
            K.y = i;
            P.x = i;
            P.y = 0;
        }

        int offset = 0;
        while(1)
        {
            offset = abs(K.y - P.y)/2;
            Q.x = K.x + offset;
            Q.y = K.y - offset;
            if(Q.y >= 0 && Q.x <= n_b && (Q.y == n_a || Q.x == 0 || d_a[Q.y] > d_b[Q.x - 1]))
            {
                if(Q.x == n_b || Q.y == 0 || d_a[Q.y - 1] <= d_b[Q.x])
                {
                    if(Q.y < n_a && (Q.x == n_b || d_a[Q.y] <= d_b[Q.x]))
                    {
                        d_m[i] = d_a[Q.y];
                    }
                    else
                    {
                        d_m[i] = d_b[Q.x];
                    }
                    break;
                }
                else
                {
                    K.x = Q.x + 1;
                    K.y = Q.y - 1;
                }
            }
            else
            {
              P.x = Q.x - 1;
              P.y = Q.y + 1;

            }

        }
    }
}


/**
    Parallel version of merge of A and B of any sizes
    @param a, b : device versions of arrays to merge
           m : device version of merge of a and b
           n_a, n_b, n_b : respective sizes of d_a, d_b, d_m
           path : points of the path to cut A and B to pieces to merge
           n_path : number of points in the path
           nb_partition : number of pieces of A and B (a_k and b_k) to merge with mergeSmall_k
*/
__global__ void mergeBig_k(int *m, int n_m, int *a, int n_a, int *b, int n_b, int2 *path, int n_path, int nbPartitions)
{
  int blockId = blockIdx.x;
  int threadId = threadIdx.x;
  int i = blockId * blockDim.x + threadId;
  if (blockId <= nbPartitions)//On utilise un block pour chaque partition
  {
    int x0, y0, x1, y1;
    x0 = path[blockId].x;
    y0 = path[blockId].y;
    x1 = path[blockId+1].x;
    y1 = path[blockId+1].y;

    const int dimx=x1-x0;
    const int dimy = y1-y0;

    //A modifier par dimx dimy dimx+dimy
     __shared__ int a_k[1024];
     __shared__ int b_k[1024];
     __shared__ int m_k[1024];

    if (threadId < dimx) //On rempli a_k[i] :  0 <= i < dimx
    {
      a_k[threadId] = a[x0+threadId];
    }
    else if (threadId < dimy+dimx)//On rempli b_k[i] : indice dimx <= i < dimx+dimy+1
    {
      b_k[threadId-dimx] = b[y0+threadId-dimx];
    }
    __syncthreads();
    mergeSmall_k(a_k, b_k, m_k, dimx, dimy, dimx+dimy);
    m[i] = m_k[threadId];

  }
}

/**
    Genearte the path to devide A and B to pieces that we'll give to mergeSmall_k
    @param pas: size of pieces
           path : store the points of the path
           n_path : number of points in the path
           nb_partition : number of pieces of A and B (a_k and b_k) to merge with mergeSmall_k
           d_a, d_b : device versions of arrays to merge
           n_a, n_b : respective sizes of d_a, d_b
*/
__global__ void pathBig_k(int pas, int2* path, int n_path , int* d_a, int n_a ,int* d_b, int n_b)
{
    int thread_i = blockIdx.x * blockDim.x + threadIdx.x;
    if(thread_i <= (n_a + n_b)/pas)        //<------------//On vérifie que l'indice du thread est inférieur à la taille du tableau de retour et qu'il est un multiple du pas
    {
        int i = thread_i*pas;
        int2 K;
        int2 P;
        int2 Q;
        if(i > n_a)
        {
            K.x = i - n_a;
            K.y = n_a;
            P.x = n_a;
            P.y = i - n_a;
        }
        else
        {
            K.x = 0;
            K.y = i;
            P.x = i;
            P.y = 0;
        }

        int offset = 0;
        while(1)
        {
            //Calcul des coordonnées du milieu de P et K
            offset = abs(K.y - P.y)/2;
            Q.x = K.x + offset;
            Q.y = K.y - offset;

            //
            if(Q.y >= 0 && Q.x <= n_b && (Q.y == n_a || Q.x == 0 || d_a[Q.y] > d_b[Q.x - 1]))
            {
                //
                if(Q.x == n_b || Q.y == 0 || d_a[Q.y - 1] <= d_b[Q.x])
                {
                  break;
                }
                else
                {
                    K.x = Q.x + 1;
                    K.y = Q.y - 1;
                }
            }
            else
            {
              P.x = Q.x - 1;
              P.y = Q.y + 1;

            }

        }
        //printf("thread : %d => (%d, %d)\n", thread_i, Q.y, Q.x);
        //!\\ Problème ordre x et y
        path[thread_i].x=Q.y;
        path[thread_i].y=Q.x;
    }
    //Si |m| n'est pas un mutliple de pas, le thread 0 ajoute (n_a, n_b) à la fin du tableau
    if (thread_i==0 && (n_a+n_b)%pas!=0)
    {
      //printf("thread : %d => (%d, %d)\n", thread_i, n_a, n_b);
      path[n_path-1].x=n_a;
      path[n_path-1].y=n_b;
    }

}

/**
    verify that A and B are correctly merge in M
*/
int assertMerge(int *tab, int *tab2, int size)
{
  for (int i=0; i<size-1; i++)
  {
    if (tab[i] > tab[i+1] || tab[i] != tab2[i] || (i>10000 && tab[i] == 0))
    {
      printf("WARNING : Unsuccessful merge on indice %d ...\n", i);
      return 0;
    }
  }
  printf("Successful merge !\n");
  return 1;

}


/**
    Merge 2 lists of arrays {A_i} and {B_i} in {M_i}1<=i<=N
    @param argv[1] : size of A
           argv[2] : size of B
*/
int main(int argc, char *argv[])
{
    std::clock_t startS, endS;
    float seqMergeTime, parMergeTime, DoH, HoD;

    srand(time(NULL));
    int n_a, n_b;
    int pas;
    if(argc>= 3)
    {
      n_a = atoi(argv[1]);
      n_b = atoi(argv[2]);
      pas = atoi(argv[3]);
    }
    else
    {
      n_a = 100;
      n_b = 100;
      pas = 1024;
    }
    int n_m = n_a+n_b;
     // <1024
    int nbPartitions = n_m/pas+(n_m%pas!=0); // On ajoute 1 si n_m n'est pas un mutliple de p
    int n_path = (1 + nbPartitions); //1(pour (0,0)) + |m|/pas(nbr de morceau de taille pas) + 1(si dernier morceau de taille < pas))
    printf("========== Merge of A and B ==========\n");
    printf("* Size of A : %d\n", n_a);
    printf("* Size of B : %d\n", n_b);
    printf("* Step : %d\n* Nbr of partitions : %d\n\n", pas, nbPartitions);

    //Initialisation des tableaux a et b
    int *a, *aGPU;
    a = (int*)malloc(n_a*sizeof(int));
    init_array(a, n_a, 10);
    gpuErrchk(hipMalloc(&aGPU, n_a*sizeof(int)));

    int *b, *bGPU;
    b = (int*)malloc(n_b*sizeof(int));
    init_array(b, n_b, 10);
    gpuErrchk(hipMalloc(&bGPU, n_b*sizeof(int)));

    // print_array(b, n_b);
    // print_array(a, n_a);

    int *m, *mGPU, *mseq;
    m = (int*)malloc(n_m*sizeof(int));
    mseq = (int*)malloc(n_m*sizeof(int));
    gpuErrchk(hipMalloc(&mGPU, n_m*sizeof(int)));

    //Declaration et allocation de path
    int2 *pathGPU;
    gpuErrchk(hipMalloc(&pathGPU, n_path*sizeof(int2)));

    startS = std::clock();
    gpuErrchk(hipMemcpy(aGPU, a, n_a*sizeof(int), hipMemcpyHostToDevice));
    gpuErrchk(hipMemcpy(bGPU, b, n_b*sizeof(int), hipMemcpyHostToDevice));
    endS = std::clock();
    HoD = (endS - startS) / (float) CLOCKS_PER_SEC;

    printf("Merge of A and B of size %d and %d runing...\n", n_a, n_b);
    startS = std::clock();
    //================ Parallel : =======================\\

    pathBig_k<<<nbPartitions/1024+1, 1024>>>(pas, pathGPU, n_path, aGPU, n_a, bGPU, n_b);

    mergeBig_k<<<nbPartitions, pas>>>(mGPU, n_m, aGPU, n_a, bGPU, n_b, pathGPU, n_path, nbPartitions);

    hipDeviceSynchronize();
    endS = std::clock();
    parMergeTime = (endS - startS) / (float) CLOCKS_PER_SEC;

    //Copy device to host
    startS = std::clock();
    hipMemcpy(m, mGPU, n_m*sizeof(int), hipMemcpyDeviceToHost);
    endS = std::clock();
    DoH = (endS - startS) / (float) CLOCKS_PER_SEC;

    printf("Merge done !\n\n");

    //================ Sequential : =======================\\
    startS = std::clock();
    mergeSeq(a, b, mseq, n_a, n_b, n_m);
    endS = std::clock();
    seqMergeTime = (endS - startS) / (float) CLOCKS_PER_SEC;

    //print_array(m, n_m);
    // print_array(mseq, n_m);

    printf("\n========= Sequential merge : =============\n");
    printf("Total time elapsed : %f s\n", seqMergeTime);
    printf("\n");

    printf("========= Parallel merge : =============\n");
    printf("Total time elapsed : %f s\n", parMergeTime+DoH+HoD);
    printf("Time running algorithm : %f s\n", parMergeTime);
    printf("Time to copy Host to Device : %f s\n", HoD);
    printf("Time to copy Device to Host : %f s\n", DoH);
    assertMerge(m, mseq, n_m);
    printf("Parrallel algorithm is %f times faster than sequential merge !\n", seqMergeTime/parMergeTime);
    printf("Parrallel merge is %f times faster than sequential merge !\n", seqMergeTime/(parMergeTime+HoD+DoH));






    //desallocation
    hipFree(aGPU);
    hipFree(bGPU);
    hipFree(pathGPU);

    return 0;
}

	.text
	.file	"pathMerge.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z10init_arrayPiii              # -- Begin function _Z10init_arrayPiii
	.type	_Z10init_arrayPiii,@function
_Z10init_arrayPiii:                     # @_Z10init_arrayPiii
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%edx, %ebx
	movl	%esi, %ebp
	movq	%rdi, %r14
	callq	rand
	cltd
	idivl	%ebx
	movl	%edx, (%r14)
	testl	%ebp, %ebp
	jle	.LBB0_3
# %bb.1:                                # %.lr.ph.preheader
	movl	%ebp, %r15d
	xorl	%r12d, %r12d
.LBB0_2:                                # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	movl	-4(%r14,%r12,4), %ebp
	callq	rand
	cltd
	idivl	%ebx
	addl	%ebp, %edx
	movl	%edx, (%r14,%r12,4)
	incq	%r12
	cmpq	%r12, %r15
	jne	.LBB0_2
.LBB0_3:                                # %._crit_edge
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z10init_arrayPiii, .Lfunc_end0-_Z10init_arrayPiii
	.cfi_endproc
                                        # -- End function
	.globl	_Z11print_arrayPii              # -- Begin function _Z11print_arrayPii
	.type	_Z11print_arrayPii,@function
_Z11print_arrayPii:                     # @_Z11print_arrayPii
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	pushq	%rax
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%esi, %ebp
	movq	%rdi, %rbx
	movl	$91, %edi
	callq	putchar@PLT
	testl	%ebp, %ebp
	jle	.LBB1_3
# %bb.1:                                # %.lr.ph.preheader
	movl	%ebp, %r14d
	xorl	%r15d, %r15d
.LBB1_2:                                # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	movl	(%rbx,%r15,4), %esi
	movl	$.L.str.1, %edi
	xorl	%eax, %eax
	callq	printf
	incq	%r15
	cmpq	%r15, %r14
	jne	.LBB1_2
.LBB1_3:                                # %._crit_edge
	movl	$.Lstr, %edi
	addq	$8, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	puts@PLT                        # TAILCALL
.Lfunc_end1:
	.size	_Z11print_arrayPii, .Lfunc_end1-_Z11print_arrayPii
	.cfi_endproc
                                        # -- End function
	.globl	_Z8mergeSeqPiS_S_iii            # -- Begin function _Z8mergeSeqPiS_S_iii
	.type	_Z8mergeSeqPiS_S_iii,@function
_Z8mergeSeqPiS_S_iii:                   # @_Z8mergeSeqPiS_S_iii
	.cfi_startproc
# %bb.0:
	testl	%r9d, %r9d
	jle	.LBB2_11
# %bb.1:                                # %.lr.ph.preheader
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	.cfi_offset %rbp, -16
	xorl	%r11d, %r11d
	xorl	%eax, %eax
	xorl	%r10d, %r10d
.LBB2_2:                                # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	cmpl	%ecx, %r10d
	jge	.LBB2_3
# %bb.4:                                #   in Loop: Header=BB2_2 Depth=1
	movslq	%r10d, %rbx
	movl	(%rdi,%rbx,4), %ebx
	cmpl	%r8d, %eax
	jge	.LBB2_6
# %bb.5:                                #   in Loop: Header=BB2_2 Depth=1
	movslq	%eax, %r14
	movl	(%rsi,%r14,4), %ebp
	cmpl	%ebp, %ebx
	jge	.LBB2_7
.LBB2_6:                                # %._crit_edge35
                                        #   in Loop: Header=BB2_2 Depth=1
	movslq	%r11d, %r11
	movl	%ebx, (%rdx,%r11,4)
	incl	%r10d
	jmp	.LBB2_9
.LBB2_3:                                #   in Loop: Header=BB2_2 Depth=1
	cltq
	movl	(%rsi,%rax,4), %ebx
	movslq	%r11d, %r11
	movl	%ebx, (%rdx,%r11,4)
.LBB2_8:                                #   in Loop: Header=BB2_2 Depth=1
	incl	%eax
.LBB2_9:                                #   in Loop: Header=BB2_2 Depth=1
	leal	(%rax,%r10), %r11d
	cmpl	%r9d, %r11d
	jl	.LBB2_2
	jmp	.LBB2_10
.LBB2_7:                                #   in Loop: Header=BB2_2 Depth=1
	movslq	%r11d, %r11
	movl	%ebp, (%rdx,%r11,4)
	jmp	.LBB2_8
.LBB2_10:
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	.cfi_restore %rbx
	.cfi_restore %r14
	.cfi_restore %rbp
.LBB2_11:                               # %._crit_edge
	retq
.Lfunc_end2:
	.size	_Z8mergeSeqPiS_S_iii, .Lfunc_end2-_Z8mergeSeqPiS_S_iii
	.cfi_endproc
                                        # -- End function
	.globl	_Z25__device_stub__mergeBig_kPiiS_iS_iP15HIP_vector_typeIiLj2EEii # -- Begin function _Z25__device_stub__mergeBig_kPiiS_iS_iP15HIP_vector_typeIiLj2EEii
	.type	_Z25__device_stub__mergeBig_kPiiS_iS_iP15HIP_vector_typeIiLj2EEii,@function
_Z25__device_stub__mergeBig_kPiiS_iS_iP15HIP_vector_typeIiLj2EEii: # @_Z25__device_stub__mergeBig_kPiiS_iS_iP15HIP_vector_typeIiLj2EEii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$176, %rsp
	.cfi_def_cfa_offset 224
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	20(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	48(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	16(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	40(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	12(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	224(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	232(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	240(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z10mergeBig_kPiiS_iS_iP15HIP_vector_typeIiLj2EEii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$192, %rsp
	.cfi_adjust_cfa_offset -192
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	_Z25__device_stub__mergeBig_kPiiS_iS_iP15HIP_vector_typeIiLj2EEii, .Lfunc_end3-_Z25__device_stub__mergeBig_kPiiS_iS_iP15HIP_vector_typeIiLj2EEii
	.cfi_endproc
                                        # -- End function
	.globl	_Z24__device_stub__pathBig_kiP15HIP_vector_typeIiLj2EEiPiiS2_i # -- Begin function _Z24__device_stub__pathBig_kiP15HIP_vector_typeIiLj2EEiPiiS2_i
	.type	_Z24__device_stub__pathBig_kiP15HIP_vector_typeIiLj2EEiPiiS2_i,@function
_Z24__device_stub__pathBig_kiP15HIP_vector_typeIiLj2EEiPiiS2_i: # @_Z24__device_stub__pathBig_kiP15HIP_vector_typeIiLj2EEiPiiS2_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	20(%rsp), %rax
	movl	%edi, (%rax)
	leaq	56(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	16(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	48(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	12(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	40(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z9pathBig_kiP15HIP_vector_typeIiLj2EEiPiiS2_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end4:
	.size	_Z24__device_stub__pathBig_kiP15HIP_vector_typeIiLj2EEiPiiS2_i, .Lfunc_end4-_Z24__device_stub__pathBig_kiP15HIP_vector_typeIiLj2EEiPiiS2_i
	.cfi_endproc
                                        # -- End function
	.globl	_Z11assertMergePiS_i            # -- Begin function _Z11assertMergePiS_i
	.type	_Z11assertMergePiS_i,@function
_Z11assertMergePiS_i:                   # @_Z11assertMergePiS_i
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset %rbx, -16
	cmpl	$2, %edx
	movl	$1, %ecx
	cmovgel	%edx, %ecx
	decl	%ecx
	xorl	%r8d, %r8d
.LBB5_1:                                # =>This Inner Loop Header: Depth=1
	cmpq	%r8, %rcx
	je	.LBB5_7
# %bb.2:                                #   in Loop: Header=BB5_1 Depth=1
	movq	%r8, %rax
	movl	(%rdi,%r8,4), %edx
	cmpl	4(%rdi,%r8,4), %edx
	jg	.LBB5_6
# %bb.3:                                #   in Loop: Header=BB5_1 Depth=1
	cmpl	(%rsi,%rax,4), %edx
	jne	.LBB5_6
# %bb.4:                                #   in Loop: Header=BB5_1 Depth=1
	leaq	1(%rax), %r8
	cmpq	$10001, %rax                    # imm = 0x2711
	jb	.LBB5_1
# %bb.5:                                #   in Loop: Header=BB5_1 Depth=1
	testl	%edx, %edx
	jne	.LBB5_1
.LBB5_6:
	xorl	%ebx, %ebx
	movl	$.L.str.3, %edi
	movl	%eax, %esi
	xorl	%eax, %eax
	callq	printf
	jmp	.LBB5_8
.LBB5_7:
	movl	$.Lstr.1, %edi
	callq	puts@PLT
	movl	$1, %ebx
.LBB5_8:
	movl	%ebx, %eax
	popq	%rbx
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end5:
	.size	_Z11assertMergePiS_i, .Lfunc_end5-_Z11assertMergePiS_i
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0                          # -- Begin function main
.LCPI6_0:
	.long	0x49742400                      # float 1.0E+6
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$104, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%rsi, %rbx
	movl	%edi, %ebp
	xorl	%edi, %edi
	callq	time
	movl	%eax, %edi
	callq	srand
	cmpl	$3, %ebp
	jl	.LBB6_1
# %bb.2:
	movq	8(%rbx), %rdi
	callq	atoi
	movl	%eax, %r14d
	movq	16(%rbx), %rdi
	callq	atoi
	movl	%eax, %r15d
	movq	24(%rbx), %rdi
	callq	atoi
	movl	%eax, %ebx
	jmp	.LBB6_3
.LBB6_1:
	movl	$100, %r15d
	movl	$1024, %ebx                     # imm = 0x400
	movl	$100, %r14d
.LBB6_3:
	leal	(%r14,%r15), %eax
	movl	%eax, 4(%rsp)                   # 4-byte Spill
	cltd
	idivl	%ebx
	movl	%eax, %r12d
	cmpl	$1, %edx
	sbbl	$-1, %r12d
	movl	$.Lstr.2, %edi
	callq	puts@PLT
	movl	$.L.str.6, %edi
	movl	%r14d, %esi
	xorl	%eax, %eax
	callq	printf
	movl	$.L.str.7, %edi
	movl	%r15d, %esi
	xorl	%eax, %eax
	callq	printf
	movl	$.L.str.8, %edi
	movl	%ebx, (%rsp)                    # 4-byte Spill
	movl	%ebx, %esi
	movl	%r12d, %edx
	xorl	%eax, %eax
	callq	printf
	movq	%r14, 96(%rsp)                  # 8-byte Spill
	movslq	%r14d, %r14
	leaq	(,%r14,4), %rbx
	movq	%rbx, %rdi
	callq	malloc
	movq	%rax, 8(%rsp)                   # 8-byte Spill
	movq	%rax, %rdi
	movl	%r14d, %esi
	movl	$10, %edx
	callq	_Z10init_arrayPiii
	leaq	40(%rsp), %rdi
	movq	%rbx, %rsi
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB6_4
# %bb.6:                                # %_Z9gpuAssert10hipError_tPKcib.exit
	movslq	%r15d, %r13
	shlq	$2, %r13
	movq	%r13, %rdi
	callq	malloc
	movq	%rax, 64(%rsp)                  # 8-byte Spill
	movq	%rax, %rdi
	movl	%r15d, %esi
	movl	$10, %edx
	callq	_Z10init_arrayPiii
	leaq	32(%rsp), %rdi
	movq	%r13, %rsi
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB6_7
# %bb.8:                                # %_Z9gpuAssert10hipError_tPKcib.exit89
	movslq	4(%rsp), %rbp                   # 4-byte Folded Reload
	shlq	$2, %rbp
	movq	%rbp, %rdi
	callq	malloc
	movq	%rax, 88(%rsp)                  # 8-byte Spill
	movq	%rbp, %rdi
	callq	malloc
	movq	%rax, 80(%rsp)                  # 8-byte Spill
	leaq	72(%rsp), %rdi
	movq	%rbp, %rsi
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB6_9
# %bb.11:                               # %_Z9gpuAssert10hipError_tPKcib.exit91
	leal	1(%r12), %eax
	movq	%rax, 56(%rsp)                  # 8-byte Spill
	movslq	%eax, %rsi
	shlq	$3, %rsi
	leaq	48(%rsp), %rdi
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB6_12
# %bb.13:                               # %_Z9gpuAssert10hipError_tPKcib.exit93
	callq	clock
	movq	%rax, %r14
	movq	40(%rsp), %rdi
	movq	8(%rsp), %rsi                   # 8-byte Reload
	movq	%rbx, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	testl	%eax, %eax
	jne	.LBB6_14
# %bb.16:                               # %_Z9gpuAssert10hipError_tPKcib.exit95
	movq	%r14, 24(%rsp)                  # 8-byte Spill
	movq	32(%rsp), %rdi
	movq	64(%rsp), %rsi                  # 8-byte Reload
	movq	%r13, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	testl	%eax, %eax
	jne	.LBB6_17
# %bb.18:                               # %_Z9gpuAssert10hipError_tPKcib.exit97
	movabsq	$4294967296, %r14               # imm = 0x100000000
	callq	clock
	movq	%rax, %rbx
	movl	$.L.str.10, %edi
	movq	96(%rsp), %r13                  # 8-byte Reload
	movl	%r13d, %esi
	movl	%r15d, %edx
	xorl	%eax, %eax
	callq	printf
	callq	clock
	movq	%rax, 16(%rsp)                  # 8-byte Spill
	leal	1023(%r12), %edi
	testl	%r12d, %r12d
	cmovnsl	%r12d, %edi
	sarl	$10, %edi
	incl	%edi
	btsq	$32, %rdi
	leaq	1024(%r14), %rdx
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB6_20
# %bb.19:
	movq	48(%rsp), %rsi
	movq	40(%rsp), %rcx
	movq	32(%rsp), %r9
	subq	$8, %rsp
	.cfi_adjust_cfa_offset 8
	movl	8(%rsp), %edi                   # 4-byte Reload
	movq	64(%rsp), %rdx                  # 8-byte Reload
                                        # kill: def $edx killed $edx killed $rdx
	movl	%r13d, %r8d
	pushq	%r15
	.cfi_adjust_cfa_offset 8
	callq	_Z24__device_stub__pathBig_kiP15HIP_vector_typeIiLj2EEiPiiS2_i
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
.LBB6_20:
	movl	%r12d, %edi
	orq	%r14, %rdi
	movl	(%rsp), %edx                    # 4-byte Reload
	orq	%r14, %rdx
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB6_22
# %bb.21:
	movq	72(%rsp), %rdi
	movq	40(%rsp), %rdx
	movq	32(%rsp), %r8
	subq	$8, %rsp
	.cfi_adjust_cfa_offset 8
	movl	12(%rsp), %esi                  # 4-byte Reload
	movl	%r13d, %ecx
	movl	%r15d, %r9d
	pushq	%r12
	.cfi_adjust_cfa_offset 8
	pushq	72(%rsp)                        # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	72(%rsp)
	.cfi_adjust_cfa_offset 8
	callq	_Z25__device_stub__mergeBig_kPiiS_iS_iP15HIP_vector_typeIiLj2EEii
	addq	$32, %rsp
	.cfi_adjust_cfa_offset -32
.LBB6_22:
	subq	24(%rsp), %rbx                  # 8-byte Folded Reload
	cvtsi2ss	%rbx, %xmm0
	divss	.LCPI6_0(%rip), %xmm0
	movss	%xmm0, 24(%rsp)                 # 4-byte Spill
	callq	hipDeviceSynchronize
	callq	clock
	subq	16(%rsp), %rax                  # 8-byte Folded Reload
	xorps	%xmm0, %xmm0
	cvtsi2ss	%rax, %xmm0
	divss	.LCPI6_0(%rip), %xmm0
	movss	%xmm0, (%rsp)                   # 4-byte Spill
	callq	clock
	movq	%rax, %rbx
	movq	72(%rsp), %rsi
	movq	88(%rsp), %r14                  # 8-byte Reload
	movq	%r14, %rdi
	movq	%rbp, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	callq	clock
	subq	%rbx, %rax
	xorps	%xmm0, %xmm0
	cvtsi2ss	%rax, %xmm0
	divss	.LCPI6_0(%rip), %xmm0
	movss	%xmm0, 16(%rsp)                 # 4-byte Spill
	movl	$.Lstr.3, %edi
	callq	puts@PLT
	movq	8(%rsp), %rdi                   # 8-byte Reload
	movq	64(%rsp), %rsi                  # 8-byte Reload
	movq	80(%rsp), %r12                  # 8-byte Reload
	movq	%r12, %rdx
	movl	%r13d, %ecx
	movl	%r15d, %r8d
	movl	4(%rsp), %ebp                   # 4-byte Reload
	movl	%ebp, %r9d
	callq	_Z8mergeSeqPiS_S_iii
	callq	clock
	subq	%rbx, %rax
	xorps	%xmm0, %xmm0
	cvtsi2ss	%rax, %xmm0
	divss	.LCPI6_0(%rip), %xmm0
	movss	%xmm0, 8(%rsp)                  # 4-byte Spill
	movl	$.Lstr.4, %edi
	callq	puts@PLT
	xorps	%xmm0, %xmm0
	cvtss2sd	8(%rsp), %xmm0                  # 4-byte Folded Reload
	movl	$.L.str.13, %edi
	movb	$1, %al
	callq	printf
	movl	$10, %edi
	callq	putchar@PLT
	movl	$.Lstr.5, %edi
	callq	puts@PLT
	movss	(%rsp), %xmm0                   # 4-byte Reload
                                        # xmm0 = mem[0],zero,zero,zero
	addss	16(%rsp), %xmm0                 # 4-byte Folded Reload
	addss	24(%rsp), %xmm0                 # 4-byte Folded Reload
	cvtss2sd	%xmm0, %xmm0
	movl	$.L.str.13, %edi
	movb	$1, %al
	callq	printf
	xorps	%xmm0, %xmm0
	cvtss2sd	(%rsp), %xmm0                   # 4-byte Folded Reload
	movl	$.L.str.16, %edi
	movb	$1, %al
	callq	printf
	xorps	%xmm0, %xmm0
	cvtss2sd	24(%rsp), %xmm0                 # 4-byte Folded Reload
	movl	$.L.str.17, %edi
	movb	$1, %al
	callq	printf
	xorps	%xmm0, %xmm0
	cvtss2sd	16(%rsp), %xmm0                 # 4-byte Folded Reload
	movl	$.L.str.18, %edi
	movb	$1, %al
	callq	printf
	movq	%r14, %rdi
	movq	%r12, %rsi
	movl	%ebp, %edx
	callq	_Z11assertMergePiS_i
	movss	8(%rsp), %xmm0                  # 4-byte Reload
                                        # xmm0 = mem[0],zero,zero,zero
	divss	(%rsp), %xmm0                   # 4-byte Folded Reload
	cvtss2sd	%xmm0, %xmm0
	movl	$.L.str.19, %edi
	movb	$1, %al
	callq	printf
	movss	(%rsp), %xmm0                   # 4-byte Reload
                                        # xmm0 = mem[0],zero,zero,zero
	addss	24(%rsp), %xmm0                 # 4-byte Folded Reload
	addss	16(%rsp), %xmm0                 # 4-byte Folded Reload
	movss	8(%rsp), %xmm1                  # 4-byte Reload
                                        # xmm1 = mem[0],zero,zero,zero
	divss	%xmm0, %xmm1
	xorps	%xmm0, %xmm0
	cvtss2sd	%xmm1, %xmm0
	movl	$.L.str.20, %edi
	movb	$1, %al
	callq	printf
	movq	40(%rsp), %rdi
	callq	hipFree
	movq	32(%rsp), %rdi
	callq	hipFree
	movq	48(%rsp), %rdi
	callq	hipFree
	xorl	%eax, %eax
	addq	$104, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB6_4:
	.cfi_def_cfa_offset 160
	movl	%eax, %ebp
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.21, %esi
	movl	$.L.str.9, %ecx
	movq	%rbx, %rdi
	movq	%rax, %rdx
	movl	$342, %r8d                      # imm = 0x156
	jmp	.LBB6_5
.LBB6_7:
	movl	%eax, %ebp
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.21, %esi
	movl	$.L.str.9, %ecx
	movq	%rbx, %rdi
	movq	%rax, %rdx
	movl	$347, %r8d                      # imm = 0x15B
.LBB6_5:
	xorl	%eax, %eax
	callq	fprintf
	movl	%ebp, %edi
	callq	exit
.LBB6_9:
	movl	%eax, %r14d
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.21, %esi
	movl	$.L.str.9, %ecx
	movq	%rbx, %rdi
	movq	%rax, %rdx
	movl	$355, %r8d                      # imm = 0x163
	jmp	.LBB6_10
.LBB6_12:
	movl	%eax, %r14d
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.21, %esi
	movl	$.L.str.9, %ecx
	movq	%rbx, %rdi
	movq	%rax, %rdx
	movl	$359, %r8d                      # imm = 0x167
.LBB6_10:
	xorl	%eax, %eax
	callq	fprintf
	movl	%r14d, %edi
	callq	exit
.LBB6_14:
	movl	%eax, %ebx
	movq	stderr(%rip), %r14
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.21, %esi
	movl	$.L.str.9, %ecx
	movq	%r14, %rdi
	movq	%rax, %rdx
	movl	$362, %r8d                      # imm = 0x16A
	jmp	.LBB6_15
.LBB6_17:
	movl	%eax, %ebx
	movq	stderr(%rip), %r14
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.21, %esi
	movl	$.L.str.9, %ecx
	movq	%r14, %rdi
	movq	%rax, %rdx
	movl	$363, %r8d                      # imm = 0x16B
.LBB6_15:
	xorl	%eax, %eax
	callq	fprintf
	movl	%ebx, %edi
	callq	exit
.Lfunc_end6:
	.size	main, .Lfunc_end6-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB7_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB7_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z10mergeBig_kPiiS_iS_iP15HIP_vector_typeIiLj2EEii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z9pathBig_kiP15HIP_vector_typeIiLj2EEiPiiS2_i, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end7:
	.size	__hip_module_ctor, .Lfunc_end7-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB8_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB8_2:
	retq
.Lfunc_end8:
	.size	__hip_module_dtor, .Lfunc_end8-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	.L.str.1,@object                # @.str.1
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str.1:
	.asciz	"%d "
	.size	.L.str.1, 4

	.type	_Z10mergeBig_kPiiS_iS_iP15HIP_vector_typeIiLj2EEii,@object # @_Z10mergeBig_kPiiS_iS_iP15HIP_vector_typeIiLj2EEii
	.section	.rodata,"a",@progbits
	.globl	_Z10mergeBig_kPiiS_iS_iP15HIP_vector_typeIiLj2EEii
	.p2align	3, 0x0
_Z10mergeBig_kPiiS_iS_iP15HIP_vector_typeIiLj2EEii:
	.quad	_Z25__device_stub__mergeBig_kPiiS_iS_iP15HIP_vector_typeIiLj2EEii
	.size	_Z10mergeBig_kPiiS_iS_iP15HIP_vector_typeIiLj2EEii, 8

	.type	_Z9pathBig_kiP15HIP_vector_typeIiLj2EEiPiiS2_i,@object # @_Z9pathBig_kiP15HIP_vector_typeIiLj2EEiPiiS2_i
	.globl	_Z9pathBig_kiP15HIP_vector_typeIiLj2EEiPiiS2_i
	.p2align	3, 0x0
_Z9pathBig_kiP15HIP_vector_typeIiLj2EEiPiiS2_i:
	.quad	_Z24__device_stub__pathBig_kiP15HIP_vector_typeIiLj2EEiPiiS2_i
	.size	_Z9pathBig_kiP15HIP_vector_typeIiLj2EEiPiiS2_i, 8

	.type	.L.str.3,@object                # @.str.3
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str.3:
	.asciz	"WARNING : Unsuccessful merge on indice %d ...\n"
	.size	.L.str.3, 47

	.type	.L.str.6,@object                # @.str.6
.L.str.6:
	.asciz	"* Size of A : %d\n"
	.size	.L.str.6, 18

	.type	.L.str.7,@object                # @.str.7
.L.str.7:
	.asciz	"* Size of B : %d\n"
	.size	.L.str.7, 18

	.type	.L.str.8,@object                # @.str.8
.L.str.8:
	.asciz	"* Step : %d\n* Nbr of partitions : %d\n\n"
	.size	.L.str.8, 39

	.type	.L.str.9,@object                # @.str.9
.L.str.9:
	.asciz	"/home/ubuntu/Datasets/stackv2/train-structured-repos-hip-sm89/homerdurand/HPCA/main/pathMerge.hip"
	.size	.L.str.9, 98

	.type	.L.str.10,@object               # @.str.10
.L.str.10:
	.asciz	"Merge of A and B of size %d and %d runing...\n"
	.size	.L.str.10, 46

	.type	.L.str.13,@object               # @.str.13
.L.str.13:
	.asciz	"Total time elapsed : %f s\n"
	.size	.L.str.13, 27

	.type	.L.str.16,@object               # @.str.16
.L.str.16:
	.asciz	"Time running algorithm : %f s\n"
	.size	.L.str.16, 31

	.type	.L.str.17,@object               # @.str.17
.L.str.17:
	.asciz	"Time to copy Host to Device : %f s\n"
	.size	.L.str.17, 36

	.type	.L.str.18,@object               # @.str.18
.L.str.18:
	.asciz	"Time to copy Device to Host : %f s\n"
	.size	.L.str.18, 36

	.type	.L.str.19,@object               # @.str.19
.L.str.19:
	.asciz	"Parrallel algorithm is %f times faster than sequential merge !\n"
	.size	.L.str.19, 64

	.type	.L.str.20,@object               # @.str.20
.L.str.20:
	.asciz	"Parrallel merge is %f times faster than sequential merge !\n"
	.size	.L.str.20, 60

	.type	.L.str.21,@object               # @.str.21
.L.str.21:
	.asciz	"GPUassert: %s %s %d\n"
	.size	.L.str.21, 21

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z10mergeBig_kPiiS_iS_iP15HIP_vector_typeIiLj2EEii"
	.size	.L__unnamed_1, 51

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z9pathBig_kiP15HIP_vector_typeIiLj2EEiPiiS2_i"
	.size	.L__unnamed_2, 47

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.type	.Lstr,@object                   # @str
	.section	.rodata.str1.1,"aMS",@progbits,1
.Lstr:
	.asciz	"]"
	.size	.Lstr, 2

	.type	.Lstr.1,@object                 # @str.1
.Lstr.1:
	.asciz	"Successful merge !"
	.size	.Lstr.1, 19

	.type	.Lstr.2,@object                 # @str.2
.Lstr.2:
	.asciz	"========== Merge of A and B =========="
	.size	.Lstr.2, 39

	.type	.Lstr.3,@object                 # @str.3
.Lstr.3:
	.asciz	"Merge done !\n"
	.size	.Lstr.3, 14

	.type	.Lstr.4,@object                 # @str.4
.Lstr.4:
	.asciz	"\n========= Sequential merge : ============="
	.size	.Lstr.4, 44

	.type	.Lstr.5,@object                 # @str.5
.Lstr.5:
	.asciz	"========= Parallel merge : ============="
	.size	.Lstr.5, 41

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z25__device_stub__mergeBig_kPiiS_iS_iP15HIP_vector_typeIiLj2EEii
	.addrsig_sym _Z24__device_stub__pathBig_kiP15HIP_vector_typeIiLj2EEiPiiS2_i
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z10mergeBig_kPiiS_iS_iP15HIP_vector_typeIiLj2EEii
	.addrsig_sym _Z9pathBig_kiP15HIP_vector_typeIiLj2EEiPiiS2_i
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z10mergeBig_kPiiS_iS_iP15HIP_vector_typeIiLj2EEii ; -- Begin function _Z10mergeBig_kPiiS_iS_iP15HIP_vector_typeIiLj2EEii
	.globl	_Z10mergeBig_kPiiS_iS_iP15HIP_vector_typeIiLj2EEii
	.p2align	8
	.type	_Z10mergeBig_kPiiS_iS_iP15HIP_vector_typeIiLj2EEii,@function
_Z10mergeBig_kPiiS_iS_iP15HIP_vector_typeIiLj2EEii: ; @_Z10mergeBig_kPiiS_iS_iP15HIP_vector_typeIiLj2EEii
; %bb.0:
	s_load_b32 s2, s[0:1], 0x3c
	s_waitcnt lgkmcnt(0)
	s_cmp_gt_i32 s15, s2
	s_cbranch_scc1 .LBB0_34
; %bb.1:
	s_load_b64 s[2:3], s[0:1], 0x30
	s_mov_b32 s8, s15
	s_ashr_i32 s9, s15, 31
	s_delay_alu instid0(SALU_CYCLE_1)
	s_lshl_b64 s[4:5], s[8:9], 3
	s_load_b32 s9, s[0:1], 0x4c
	s_waitcnt lgkmcnt(0)
	s_add_u32 s2, s2, s4
	s_addc_u32 s3, s3, s5
	s_load_b128 s[4:7], s[2:3], 0x0
	s_mov_b32 s3, exec_lo
                                        ; implicit-def: $sgpr2
	s_waitcnt lgkmcnt(0)
	s_sub_i32 s6, s6, s4
	s_sub_i32 s7, s7, s5
	v_cmpx_le_i32_e64 s6, v0
	s_xor_b32 s3, exec_lo, s3
	s_cbranch_execz .LBB0_5
; %bb.2:
	s_add_i32 s2, s7, s6
	s_mov_b32 s10, exec_lo
	v_cmpx_gt_i32_e64 s2, v0
	s_cbranch_execz .LBB0_4
; %bb.3:
	v_add_nc_u32_e32 v1, s5, v0
	s_load_b64 s[12:13], s[0:1], 0x20
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_subrev_nc_u32_e32 v1, s6, v1
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v1, vcc_lo, s12, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v2, vcc_lo, s13, v2, vcc_lo
	global_load_b32 v1, v[1:2], off
	v_subrev_nc_u32_e32 v2, s6, v0
	v_lshlrev_b32_e32 v2, 2, v2
	s_waitcnt vmcnt(0)
	ds_store_b32 v2, v1 offset:4096
.LBB0_4:                                ; %Flow82
	s_or_b32 exec_lo, exec_lo, s10
.LBB0_5:                                ; %Flow83
	s_or_saveexec_b32 s3, s3
	v_dual_mov_b32 v2, s2 :: v_dual_lshlrev_b32 v1, 2, v0
	s_xor_b32 exec_lo, exec_lo, s3
	s_cbranch_execz .LBB0_7
; %bb.6:
	s_load_b64 s[10:11], s[0:1], 0x10
	v_add_nc_u32_e32 v2, s4, v0
	s_add_i32 s2, s7, s6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s10, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s11, v3, vcc_lo
	global_load_b32 v3, v[2:3], off
	v_mov_b32_e32 v2, s2
	s_waitcnt vmcnt(0)
	ds_store_b32 v1, v3
.LBB0_7:
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
	v_cmp_ge_i32_e32 vcc_lo, v0, v2
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
                                        ; implicit-def: $vgpr2
	s_and_saveexec_b32 s2, vcc_lo
	s_xor_b32 s2, exec_lo, s2
	s_cbranch_execz .LBB0_9
; %bb.8:                                ; %._Z12mergeSmall_kPiS_S_iii.exit_crit_edge
	ds_load_b32 v2, v1 offset:8192
                                        ; implicit-def: $vgpr1
.LBB0_9:                                ; %Flow80
	s_and_not1_saveexec_b32 s4, s2
	s_cbranch_execz .LBB0_33
; %bb.10:
	s_waitcnt lgkmcnt(0)
	v_subrev_nc_u32_e32 v2, s6, v0
	v_cmp_lt_i32_e32 vcc_lo, s6, v0
	v_min_i32_e32 v8, s6, v0
	s_mov_b32 s10, 0
                                        ; implicit-def: $sgpr5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v3, 0, v2, vcc_lo
	v_mov_b32_e32 v2, v3
.LBB0_11:                               ; %.outer
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_12 Depth 2
	s_delay_alu instid0(VALU_DEP_3)
	v_mov_b32_e32 v6, v8
	s_mov_b32 s11, 0
                                        ; implicit-def: $sgpr16
                                        ; implicit-def: $sgpr14
                                        ; implicit-def: $sgpr12
                                        ; implicit-def: $sgpr15
                                        ; implicit-def: $sgpr13
.LBB0_12:                               ;   Parent Loop BB0_11 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v4, v6, v3
	s_or_b32 s13, s13, exec_lo
	s_and_not1_b32 s15, s15, exec_lo
	s_or_b32 s12, s12, exec_lo
                                        ; implicit-def: $vgpr7
	v_sub_nc_u32_e32 v5, 0, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_max_i32_e32 v4, v4, v5
	v_lshrrev_b32_e32 v8, 1, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v5, v6, v8
	v_add_nc_u32_e32 v4, v8, v2
	v_cmp_lt_i32_e32 vcc_lo, -1, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_ge_i32_e64 s2, s7, v4
	s_and_b32 s2, vcc_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s17, s2
	s_cbranch_execz .LBB0_22
; %bb.13:                               ;   in Loop: Header=BB0_12 Depth=2
	v_cmp_eq_u32_e32 vcc_lo, s6, v5
	v_cmp_eq_u32_e64 s2, 0, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s3, vcc_lo, s2
	s_xor_b32 s18, s3, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s2, s18
	s_cbranch_execz .LBB0_15
; %bb.14:                               ;   in Loop: Header=BB0_12 Depth=2
	v_lshlrev_b32_e32 v7, 2, v5
	v_lshlrev_b32_e32 v9, 2, v4
	s_and_not1_b32 s3, s3, exec_lo
	ds_load_b32 v7, v7
	ds_load_b32 v9, v9 offset:4092
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_i32_e32 vcc_lo, v7, v9
	s_and_b32 s18, vcc_lo, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s3, s3, s18
.LBB0_15:                               ; %Flow75
                                        ;   in Loop: Header=BB0_12 Depth=2
	s_or_b32 exec_lo, exec_lo, s2
	s_mov_b32 s2, -1
	s_mov_b32 s20, -1
                                        ; implicit-def: $sgpr19
                                        ; implicit-def: $vgpr7
	s_and_saveexec_b32 s18, s3
	s_cbranch_execz .LBB0_21
; %bb.16:                               ;   in Loop: Header=BB0_12 Depth=2
	v_cmp_ne_u32_e64 s2, s7, v4
	v_cmp_ne_u32_e64 s3, v6, v8
	v_cmp_eq_u32_e32 vcc_lo, s7, v4
                                        ; implicit-def: $vgpr7
	s_delay_alu instid0(VALU_DEP_2)
	s_and_b32 s19, s3, s2
	s_mov_b32 s2, -1
	s_and_saveexec_b32 s3, s19
	s_cbranch_execz .LBB0_20
; %bb.17:                               ;   in Loop: Header=BB0_12 Depth=2
	v_add_nc_u32_e32 v7, -1, v5
	v_lshlrev_b32_e32 v9, 2, v4
	s_mov_b32 s19, -1
	s_mov_b32 s20, exec_lo
	s_delay_alu instid0(VALU_DEP_2)
	v_lshlrev_b32_e32 v8, 2, v7
	ds_load_b32 v8, v8
	ds_load_b32 v9, v9 offset:4096
	s_waitcnt lgkmcnt(0)
	v_cmpx_gt_i32_e64 v8, v9
; %bb.18:                               ;   in Loop: Header=BB0_12 Depth=2
	v_add_nc_u32_e32 v2, 1, v4
	s_xor_b32 s19, exec_lo, -1
                                        ; implicit-def: $vgpr6
                                        ; implicit-def: $vgpr4
                                        ; implicit-def: $vgpr5
; %bb.19:                               ; %Flow78
                                        ;   in Loop: Header=BB0_12 Depth=2
	s_or_b32 exec_lo, exec_lo, s20
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, vcc_lo, exec_lo
	s_or_not1_b32 s2, s19, exec_lo
.LBB0_20:                               ; %Flow77
                                        ;   in Loop: Header=BB0_12 Depth=2
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s20, exec_lo, -1
	s_and_b32 s19, vcc_lo, exec_lo
	s_or_not1_b32 s2, s2, exec_lo
.LBB0_21:                               ; %Flow76
                                        ;   in Loop: Header=BB0_12 Depth=2
	s_or_b32 exec_lo, exec_lo, s18
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 s3, s13, exec_lo
	s_and_b32 s13, s20, exec_lo
	s_and_not1_b32 s12, s12, exec_lo
	s_or_b32 s13, s3, s13
	s_and_not1_b32 s3, s15, exec_lo
	s_and_b32 s15, s19, exec_lo
	s_and_b32 s2, s2, exec_lo
	s_or_b32 s15, s3, s15
	s_or_b32 s12, s12, s2
.LBB0_22:                               ; %Flow74
                                        ;   in Loop: Header=BB0_12 Depth=2
	s_or_b32 exec_lo, exec_lo, s17
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s2, exec_lo, s12
	v_mov_b32_e32 v8, v6
	s_or_b32 s11, s2, s11
	v_mov_b32_e32 v6, v7
	s_and_not1_b32 s2, s14, exec_lo
	s_and_b32 s3, s13, exec_lo
	s_and_not1_b32 s16, s16, exec_lo
	s_and_b32 s17, s15, exec_lo
	s_or_b32 s14, s2, s3
	s_or_b32 s16, s16, s17
	s_and_not1_b32 exec_lo, exec_lo, s11
	s_cbranch_execnz .LBB0_12
; %bb.23:                               ; %loop.exit.guard
                                        ;   in Loop: Header=BB0_11 Depth=1
	s_or_b32 exec_lo, exec_lo, s11
	s_mov_b32 s3, -1
	s_xor_b32 s2, s16, -1
                                        ; implicit-def: $vgpr3
	s_and_saveexec_b32 s11, s14
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s11, exec_lo, s11
; %bb.24:                               ;   in Loop: Header=BB0_11 Depth=1
	v_add_nc_u32_e32 v3, 1, v5
	s_xor_b32 s3, exec_lo, -1
; %bb.25:                               ; %Flow79
                                        ;   in Loop: Header=BB0_11 Depth=1
	s_or_b32 exec_lo, exec_lo, s11
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s3, exec_lo, s3
	s_or_b32 s10, s3, s10
	s_and_not1_b32 s3, s5, exec_lo
	s_and_b32 s2, s2, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s5, s3, s2
	s_and_not1_b32 exec_lo, exec_lo, s10
	s_cbranch_execnz .LBB0_11
; %bb.26:
	s_or_b32 exec_lo, exec_lo, s10
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s2, exec_lo
                                        ; implicit-def: $vgpr2
	v_cmpx_le_i32_e64 s6, v5
	s_xor_b32 s2, exec_lo, s2
	s_cbranch_execz .LBB0_28
; %bb.27:                               ; %._crit_edge.i
	v_lshlrev_b32_e32 v2, 2, v4
	ds_load_b32 v2, v2 offset:4096
.LBB0_28:                               ; %Flow73
	s_and_not1_saveexec_b32 s2, s2
	s_cbranch_execz .LBB0_32
; %bb.29:
	s_waitcnt lgkmcnt(0)
	v_lshlrev_b32_e32 v2, 2, v5
	ds_load_b32 v2, v2
	s_and_saveexec_b32 s3, s5
	s_cbranch_execz .LBB0_31
; %bb.30:
	v_lshlrev_b32_e32 v3, 2, v4
	ds_load_b32 v3, v3 offset:4096
	s_waitcnt lgkmcnt(0)
	v_min_i32_e32 v2, v2, v3
.LBB0_31:                               ; %Flow
	s_or_b32 exec_lo, exec_lo, s3
.LBB0_32:                               ; %.sink.split.i
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s2
	s_waitcnt lgkmcnt(0)
	ds_store_b32 v1, v2 offset:8192
.LBB0_33:                               ; %Flow81
	s_or_b32 exec_lo, exec_lo, s4
	s_and_b32 s2, 0xffff, s9
	s_load_b64 s[0:1], s[0:1], 0x0
	v_mad_u64_u32 v[3:4], null, s8, s2, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v4, 31, v3
	v_lshlrev_b64 v[0:1], 2, v[3:4]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	global_store_b32 v[0:1], v2, off
.LBB0_34:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z10mergeBig_kPiiS_iS_iP15HIP_vector_typeIiLj2EEii
		.amdhsa_group_segment_fixed_size 12288
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 320
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 10
		.amdhsa_next_free_sgpr 21
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z10mergeBig_kPiiS_iS_iP15HIP_vector_typeIiLj2EEii, .Lfunc_end0-_Z10mergeBig_kPiiS_iS_iP15HIP_vector_typeIiLj2EEii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1100
; NumSgprs: 23
; NumVgprs: 10
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 12288 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 23
; NumVGPRsForWavesPerEU: 10
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z9pathBig_kiP15HIP_vector_typeIiLj2EEiPiiS2_i ; -- Begin function _Z9pathBig_kiP15HIP_vector_typeIiLj2EEiPiiS2_i
	.globl	_Z9pathBig_kiP15HIP_vector_typeIiLj2EEiPiiS2_i
	.p2align	8
	.type	_Z9pathBig_kiP15HIP_vector_typeIiLj2EEiPiiS2_i,@function
_Z9pathBig_kiP15HIP_vector_typeIiLj2EEiPiiS2_i: ; @_Z9pathBig_kiP15HIP_vector_typeIiLj2EEiPiiS2_i
; %bb.0:
	s_clause 0x4
	s_load_b32 s11, s[0:1], 0x0
	s_load_b64 s[4:5], s[0:1], 0x8
	s_load_b32 s10, s[0:1], 0x20
	s_load_b32 s3, s[0:1], 0x30
	s_load_b32 s2, s[0:1], 0x44
	s_waitcnt lgkmcnt(0)
	s_ashr_i32 s6, s11, 31
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_i32 s7, s11, s6
	s_add_i32 s12, s3, s10
	s_xor_b32 s7, s7, s6
	s_ashr_i32 s13, s12, 31
	v_cvt_f32_u32_e32 v1, s7
	s_sub_i32 s9, 0, s7
	s_add_i32 s14, s12, s13
	s_and_b32 s2, s2, 0xffff
	s_xor_b32 s14, s14, s13
	v_rcp_iflag_f32_e32 v1, v1
	s_xor_b32 s6, s13, s6
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v1, 0x4f7ffffe, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v1, v1
	v_readfirstlane_b32 s8, v1
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mov_b32 s15, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s9, s9, s8
	s_mul_hi_u32 s9, s8, s9
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s8, s8, s9
	s_mul_hi_u32 s8, s14, s8
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_mul_i32 s9, s8, s7
	s_add_i32 s13, s8, 1
	s_sub_i32 s9, s14, s9
	s_sub_i32 s14, s9, s7
	s_cmp_ge_u32 s9, s7
	s_cselect_b32 s2, s13, s8
	s_cselect_b32 s8, s14, s9
	s_add_i32 s9, s2, 1
	s_cmp_ge_u32 s8, s7
	s_mov_b32 s14, exec_lo
	s_cselect_b32 s2, s9, s2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b32 s2, s2, s6
	s_sub_i32 s13, s2, s6
	s_delay_alu instid0(SALU_CYCLE_1)
	v_cmpx_ge_i32_e64 s13, v1
	s_cbranch_execz .LBB1_18
; %bb.1:
	s_clause 0x1
	s_load_b64 s[6:7], s[0:1], 0x28
	s_load_b64 s[8:9], s[0:1], 0x18
	v_mul_lo_u32 v2, v1, s11
	v_mov_b32_e32 v3, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_subrev_nc_u32_e32 v0, s10, v2
	v_cmp_lt_i32_e32 vcc_lo, s10, v2
	v_min_i32_e32 v5, s10, v2
	v_cndmask_b32_e32 v0, 0, v0, vcc_lo
	s_waitcnt lgkmcnt(0)
	s_add_u32 s16, s6, -4
	s_delay_alu instid0(VALU_DEP_1)
	v_mov_b32_e32 v8, v0
	s_addc_u32 s17, s7, -1
.LBB1_2:                                ; %.outer
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB1_3 Depth 2
	v_mov_b32_e32 v9, v5
	s_mov_b32 s18, 0
                                        ; implicit-def: $sgpr19
                                        ; implicit-def: $sgpr20
                                        ; implicit-def: $sgpr21
.LBB1_3:                                ;   Parent Loop BB1_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v2, v9, v0
	s_or_b32 s21, s21, exec_lo
	s_or_b32 s20, s20, exec_lo
	v_sub_nc_u32_e32 v4, 0, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_max_i32_e32 v2, v2, v4
	v_lshrrev_b32_e32 v2, 1, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v6, v9, v2
	v_add_nc_u32_e32 v4, v2, v8
	v_cmp_lt_i32_e32 vcc_lo, -1, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_ge_i32_e64 s2, s3, v4
	s_and_b32 s2, vcc_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s22, s2
	s_cbranch_execz .LBB1_13
; %bb.4:                                ;   in Loop: Header=BB1_3 Depth=2
	v_cmp_eq_u32_e32 vcc_lo, s10, v6
	v_cmp_eq_u32_e64 s2, 0, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s2, vcc_lo, s2
	s_xor_b32 s24, s2, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s23, s24
	s_cbranch_execz .LBB1_6
; %bb.5:                                ;   in Loop: Header=BB1_3 Depth=2
	v_mov_b32_e32 v7, v3
	v_ashrrev_i32_e32 v5, 31, v4
	s_and_not1_b32 s2, s2, exec_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[10:11], 2, v[6:7]
	v_lshlrev_b64 v[12:13], 2, v[4:5]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v10, vcc_lo, s8, v10
	v_add_co_ci_u32_e32 v11, vcc_lo, s9, v11, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v12, vcc_lo, s16, v12
	v_add_co_ci_u32_e32 v13, vcc_lo, s17, v13, vcc_lo
	global_load_b32 v5, v[10:11], off
	global_load_b32 v7, v[12:13], off
	s_waitcnt vmcnt(0)
	v_cmp_gt_i32_e32 vcc_lo, v5, v7
	s_and_b32 s24, vcc_lo, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s2, s2, s24
.LBB1_6:                                ; %Flow108
                                        ;   in Loop: Header=BB1_3 Depth=2
	s_or_b32 exec_lo, exec_lo, s23
	s_mov_b32 s24, -1
	s_mov_b32 s25, -1
	s_and_saveexec_b32 s23, s2
	s_cbranch_execz .LBB1_12
; %bb.7:                                ;   in Loop: Header=BB1_3 Depth=2
	v_cmp_ne_u32_e32 vcc_lo, s3, v4
	v_cmp_ne_u32_e64 s2, v9, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s25, s2, vcc_lo
	s_and_saveexec_b32 s2, s25
	s_cbranch_execz .LBB1_11
; %bb.8:                                ;   in Loop: Header=BB1_3 Depth=2
	v_add_nc_u32_e32 v2, -1, v6
	v_ashrrev_i32_e32 v5, 31, v4
	s_mov_b32 s25, exec_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[10:11], 2, v[2:3]
	v_lshlrev_b64 v[12:13], 2, v[4:5]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v10, vcc_lo, s8, v10
	v_add_co_ci_u32_e32 v11, vcc_lo, s9, v11, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v12, vcc_lo, s6, v12
	v_add_co_ci_u32_e32 v13, vcc_lo, s7, v13, vcc_lo
	global_load_b32 v5, v[10:11], off
	global_load_b32 v7, v[12:13], off
	s_waitcnt vmcnt(0)
	v_cmpx_gt_i32_e64 v5, v7
; %bb.9:                                ;   in Loop: Header=BB1_3 Depth=2
	v_add_nc_u32_e32 v8, 1, v4
	s_xor_b32 s24, exec_lo, -1
                                        ; implicit-def: $vgpr9
                                        ; implicit-def: $vgpr4
                                        ; implicit-def: $vgpr6
; %bb.10:                               ; %Flow111
                                        ;   in Loop: Header=BB1_3 Depth=2
	s_or_b32 exec_lo, exec_lo, s25
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_not1_b32 s24, s24, exec_lo
.LBB1_11:                               ; %Flow110
                                        ;   in Loop: Header=BB1_3 Depth=2
	s_or_b32 exec_lo, exec_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s25, exec_lo, -1
	s_or_not1_b32 s24, s24, exec_lo
.LBB1_12:                               ; %Flow109
                                        ;   in Loop: Header=BB1_3 Depth=2
	s_or_b32 exec_lo, exec_lo, s23
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 s2, s21, exec_lo
	s_and_b32 s21, s25, exec_lo
	s_and_not1_b32 s20, s20, exec_lo
	s_and_b32 s23, s24, exec_lo
	s_or_b32 s21, s2, s21
	s_or_b32 s20, s20, s23
.LBB1_13:                               ; %Flow107
                                        ;   in Loop: Header=BB1_3 Depth=2
	s_or_b32 exec_lo, exec_lo, s22
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s2, exec_lo, s20
	v_mov_b32_e32 v5, v9
	s_or_b32 s18, s2, s18
	v_mov_b32_e32 v9, v2
	s_and_not1_b32 s2, s19, exec_lo
	s_and_b32 s19, s21, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s19, s2, s19
	s_and_not1_b32 exec_lo, exec_lo, s18
	s_cbranch_execnz .LBB1_3
; %bb.14:                               ; %loop.exit.guard
                                        ;   in Loop: Header=BB1_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s18
	s_mov_b32 s2, -1
                                        ; implicit-def: $vgpr0
	s_and_saveexec_b32 s18, s19
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s18, exec_lo, s18
; %bb.15:                               ;   in Loop: Header=BB1_2 Depth=1
	v_add_nc_u32_e32 v0, 1, v6
	s_xor_b32 s2, exec_lo, -1
; %bb.16:                               ; %Flow112
                                        ;   in Loop: Header=BB1_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s18
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, exec_lo, s2
	s_or_b32 s15, s2, s15
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s15
	s_cbranch_execnz .LBB1_2
; %bb.17:
	s_or_b32 exec_lo, exec_lo, s15
	v_ashrrev_i32_e32 v2, 31, v1
	v_mov_b32_e32 v7, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 3, v[1:2]
	v_add_co_u32 v2, vcc_lo, s4, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
	global_store_b64 v[2:3], v[6:7], off
.LBB1_18:                               ; %Flow113
	s_or_b32 exec_lo, exec_lo, s14
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s2, exec_lo
	v_cmpx_eq_u32_e32 0, v1
	s_cbranch_execz .LBB1_21
; %bb.19:
	s_mul_i32 s13, s13, s11
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_sub_i32 s2, s12, s13
	s_cmp_eq_u32 s2, 0
	s_cbranch_scc1 .LBB1_21
; %bb.20:
	s_load_b32 s0, s[0:1], 0x10
	v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s3
	v_mov_b32_e32 v0, s10
	s_waitcnt lgkmcnt(0)
	s_ashr_i32 s1, s0, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[0:1], s[0:1], 3
	s_add_u32 s0, s4, s0
	s_addc_u32 s1, s5, s1
	global_store_b64 v2, v[0:1], s[0:1] offset:-8
.LBB1_21:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z9pathBig_kiP15HIP_vector_typeIiLj2EEiPiiS2_i
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 312
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 14
		.amdhsa_next_free_sgpr 26
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z9pathBig_kiP15HIP_vector_typeIiLj2EEiPiiS2_i, .Lfunc_end1-_Z9pathBig_kiP15HIP_vector_typeIiLj2EEiPiiS2_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 996
; NumSgprs: 28
; NumVgprs: 14
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 28
; NumVGPRsForWavesPerEU: 14
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .offset:         40
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         48
        .size:           8
        .value_kind:     global_buffer
      - .offset:         56
        .size:           4
        .value_kind:     by_value
      - .offset:         60
        .size:           4
        .value_kind:     by_value
      - .offset:         64
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         68
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         72
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         76
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         78
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         80
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         82
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         84
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         86
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         112
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         120
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         128
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 12288
    .kernarg_segment_align: 8
    .kernarg_segment_size: 320
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z10mergeBig_kPiiS_iS_iP15HIP_vector_typeIiLj2EEii
    .private_segment_fixed_size: 0
    .sgpr_count:     23
    .sgpr_spill_count: 0
    .symbol:         _Z10mergeBig_kPiiS_iS_iP15HIP_vector_typeIiLj2EEii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     10
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .offset:         48
        .size:           4
        .value_kind:     by_value
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         60
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         64
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         68
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         70
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         72
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         74
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         76
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         78
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         112
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         120
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 312
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z9pathBig_kiP15HIP_vector_typeIiLj2EEiPiiS2_i
    .private_segment_fixed_size: 0
    .sgpr_count:     28
    .sgpr_spill_count: 0
    .symbol:         _Z9pathBig_kiP15HIP_vector_typeIiLj2EEiPiiS2_i.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     14
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
