#include "includes.h"
/*****************************************************************************/
// nvcc -O1 -o bpsw bpsw.cu -lrt -lm


// Assertion to check for errors
__global__ void kernel_lucas(long* nArray, long* dArray, int* rArray, long len) {
int bx = blockIdx.x;      // ID thread
int tx = threadIdx.x;
int i, length;
long long d, n;
long long q, q2, u, u2, uold, v, v2, t;

// Identify the row and column of the Pd element to work on
long memIndex = bx*TILE_WIDTH + tx;
if (memIndex < len)							//out of bounds checking - some threads will be doing nothing
{
d = (long long) dArray[memIndex];
n = (long long) nArray[memIndex];
q = (1 - d) / 4;
u = 0;
v = 2;
u2 = 1;
v2 = 1;
q2 = 2 * q;
t = (n + 1) / 2;						//theta
length = 32 - __clz(t); //length of our number in bits. //clz(b00010010) = 3

for (i = 0; i < length; i++)
{
u2 = (u2 * v2) % n;
v2 = (v2 * v2 - q2) % n;
if (t & 1)				//mask = 1
{
uold = u;
u = (u2 * v) + (u * v2);
u = (u % 2 == 1) ? u + n : u;
u = (u / 2) % n;
v = (v2 * v) + (u2 * uold * d);
v = (v % 2 == 1) ? v + n : v;
v = (v / 2) % n;
}

q = (q*q) % n;
q2 = q + q;

t = t >> 1;
}

}
__syncthreads();
if (memIndex < len)
rArray[memIndex] = (u == 0);

}
	.file	"tmpxft_002d0b75_00000000-6_kernel_lucas.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2010:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2010:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z37__device_stub__Z12kernel_lucasPlS_PilPlS_Pil
	.type	_Z37__device_stub__Z12kernel_lucasPlS_PilPlS_Pil, @function
_Z37__device_stub__Z12kernel_lucasPlS_PilPlS_Pil:
.LFB2032:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movq	%rcx, (%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z12kernel_lucasPlS_Pil(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L2:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2032:
	.size	_Z37__device_stub__Z12kernel_lucasPlS_PilPlS_Pil, .-_Z37__device_stub__Z12kernel_lucasPlS_PilPlS_Pil
	.globl	_Z12kernel_lucasPlS_Pil
	.type	_Z12kernel_lucasPlS_Pil, @function
_Z12kernel_lucasPlS_Pil:
.LFB2033:
	.cfi_startproc
	endbr64
	jmp	_Z37__device_stub__Z12kernel_lucasPlS_PilPlS_Pil
	.cfi_endproc
.LFE2033:
	.size	_Z12kernel_lucasPlS_Pil, .-_Z12kernel_lucasPlS_Pil
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z12kernel_lucasPlS_Pil"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2035:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z12kernel_lucasPlS_Pil(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2035:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include "includes.h"
/*****************************************************************************/
// nvcc -O1 -o bpsw bpsw.cu -lrt -lm


// Assertion to check for errors
__global__ void kernel_lucas(long* nArray, long* dArray, int* rArray, long len) {
int bx = blockIdx.x;      // ID thread
int tx = threadIdx.x;
int i, length;
long long d, n;
long long q, q2, u, u2, uold, v, v2, t;

// Identify the row and column of the Pd element to work on
long memIndex = bx*TILE_WIDTH + tx;
if (memIndex < len)							//out of bounds checking - some threads will be doing nothing
{
d = (long long) dArray[memIndex];
n = (long long) nArray[memIndex];
q = (1 - d) / 4;
u = 0;
v = 2;
u2 = 1;
v2 = 1;
q2 = 2 * q;
t = (n + 1) / 2;						//theta
length = 32 - __clz(t); //length of our number in bits. //clz(b00010010) = 3

for (i = 0; i < length; i++)
{
u2 = (u2 * v2) % n;
v2 = (v2 * v2 - q2) % n;
if (t & 1)				//mask = 1
{
uold = u;
u = (u2 * v) + (u * v2);
u = (u % 2 == 1) ? u + n : u;
u = (u / 2) % n;
v = (v2 * v) + (u2 * uold * d);
v = (v % 2 == 1) ? v + n : v;
v = (v / 2) % n;
}

q = (q*q) % n;
q2 = q + q;

t = t >> 1;
}

}
__syncthreads();
if (memIndex < len)
rArray[memIndex] = (u == 0);

}
	.text
	.file	"kernel_lucas.hip"
	.globl	_Z27__device_stub__kernel_lucasPlS_Pil # -- Begin function _Z27__device_stub__kernel_lucasPlS_Pil
	.type	_Z27__device_stub__kernel_lucasPlS_Pil,@function
_Z27__device_stub__kernel_lucasPlS_Pil: # @_Z27__device_stub__kernel_lucasPlS_Pil
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	16(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z12kernel_lucasPlS_Pil, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z27__device_stub__kernel_lucasPlS_Pil, .Lfunc_end0-_Z27__device_stub__kernel_lucasPlS_Pil
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z12kernel_lucasPlS_Pil, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z12kernel_lucasPlS_Pil,@object # @_Z12kernel_lucasPlS_Pil
	.section	.rodata,"a",@progbits
	.globl	_Z12kernel_lucasPlS_Pil
	.p2align	3, 0x0
_Z12kernel_lucasPlS_Pil:
	.quad	_Z27__device_stub__kernel_lucasPlS_Pil
	.size	_Z12kernel_lucasPlS_Pil, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z12kernel_lucasPlS_Pil"
	.size	.L__unnamed_1, 24

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z27__device_stub__kernel_lucasPlS_Pil
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z12kernel_lucasPlS_Pil
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z12kernel_lucasPlS_Pil ; -- Begin function _Z12kernel_lucasPlS_Pil
	.globl	_Z12kernel_lucasPlS_Pil
	.p2align	8
	.type	_Z12kernel_lucasPlS_Pil,@function
_Z12kernel_lucasPlS_Pil:                ; @_Z12kernel_lucasPlS_Pil
; %bb.0:
	s_load_b256 s[4:11], s[0:1], 0x0
	v_lshl_add_u32 v0, s15, 7, v0
	v_mov_b32_e32 v8, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v1, 31, v0
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_i64_e64 s0, s[10:11], v[0:1]
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s10, s0
	s_cbranch_execz .LBB0_8
; %bb.1:
	v_lshlrev_b64 v[6:7], 3, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s4, v6
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v7, vcc_lo
	s_mov_b32 s5, 0
	s_mov_b32 s4, exec_lo
	global_load_b64 v[2:3], v[2:3], off
	s_waitcnt vmcnt(0)
	v_add_co_u32 v4, vcc_lo, v2, 1
	v_add_co_ci_u32_e32 v5, vcc_lo, 0, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshrrev_b32_e32 v8, 31, v5
	v_add_co_u32 v4, vcc_lo, v4, v8
	v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
	v_mov_b32_e32 v8, 1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i64 v[4:5], 1, v[4:5]
	v_cmpx_ne_u32_e32 0, v4
	s_cbranch_execz .LBB0_7
; %bb.2:                                ; %.lr.ph.preheader
	v_add_co_u32 v6, vcc_lo, s6, v6
	v_add_co_ci_u32_e32 v7, vcc_lo, s7, v7, vcc_lo
	v_ashrrev_i32_e32 v8, 31, v3
	v_mov_b32_e32 v18, 1
	v_clz_i32_u32_e32 v14, v4
	global_load_b64 v[6:7], v[6:7], off
	v_mov_b32_e32 v19, 0
	v_add_co_u32 v9, vcc_lo, v2, v8
	v_add_co_ci_u32_e32 v10, vcc_lo, v3, v8, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_mov_b32 v16, 2 :: v_dual_mov_b32 v23, v19
	v_xor_b32_e32 v24, v9, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v25, v10, v8
	v_subrev_nc_u32_e32 v30, 32, v14
	v_dual_mov_b32 v22, v18 :: v_dual_mov_b32 v17, 0
	v_cvt_f32_u32_e32 v8, v24
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_cvt_f32_u32_e32 v9, v25
	v_sub_co_u32 v26, vcc_lo, 0, v24
	v_sub_co_ci_u32_e32 v27, vcc_lo, 0, v25, vcc_lo
	v_fmac_f32_e32 v8, 0x4f800000, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v8, v8
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v8, 0x5f7ffffc, v8
	v_mul_f32_e32 v9, 0x2f800000, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_trunc_f32_e32 v9, v9
	v_fmac_f32_e32 v8, 0xcf800000, v9
	v_cvt_u32_f32_e32 v28, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_u32_f32_e32 v29, v8
	v_mul_lo_u32 v8, v26, v28
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v9, v27, v29
	v_mad_u64_u32 v[10:11], null, v26, v29, 0
	v_add3_u32 v20, v11, v8, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v31, v29, v10
	v_mad_u64_u32 v[8:9], null, v28, v10, 0
	s_waitcnt vmcnt(0)
	v_sub_co_u32 v12, vcc_lo, 1, v6
	v_sub_co_ci_u32_e32 v13, vcc_lo, 0, v7, vcc_lo
	v_ashrrev_i32_e32 v15, 31, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshrrev_b32_e32 v11, 30, v15
	v_add_co_u32 v14, vcc_lo, v12, v11
	v_add_co_ci_u32_e32 v15, vcc_lo, 0, v13, vcc_lo
	v_mad_u64_u32 v[10:11], null, v29, v20, 0
	v_mad_u64_u32 v[12:13], null, v28, v20, 0
	s_delay_alu instid0(VALU_DEP_3)
	v_ashrrev_i64 v[14:15], 2, v[14:15]
	v_mov_b32_e32 v20, 0
	v_mov_b32_e32 v21, 0
.LBB0_3:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	v_add_co_u32 v32, vcc_lo, v31, v10
	v_add_co_ci_u32_e32 v33, vcc_lo, 0, v11, vcc_lo
	v_mul_lo_u32 v44, v19, v22
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v34, vcc_lo, v32, v8
	v_add_co_ci_u32_e32 v34, vcc_lo, v33, v9, vcc_lo
	v_add_co_ci_u32_e32 v35, vcc_lo, 0, v13, vcc_lo
	v_mul_lo_u32 v45, v18, v23
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v34, vcc_lo, v34, v12
	v_add_co_ci_u32_e32 v35, vcc_lo, 0, v35, vcc_lo
	v_mad_u64_u32 v[36:37], null, v18, v22, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v42, vcc_lo, v29, v34
	v_add_co_ci_u32_e32 v43, vcc_lo, v28, v35, vcc_lo
	v_mul_lo_u32 v47, v18, v19
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_mul_lo_u32 v38, v27, v42
	v_mad_u64_u32 v[34:35], null, v26, v42, 0
	v_mul_lo_u32 v39, v26, v43
	v_mad_u64_u32 v[40:41], null, v18, v18, 0
	v_add3_u32 v37, v37, v45, v44
	v_lshlrev_b64 v[22:23], 1, v[14:15]
	s_mov_b32 s6, exec_lo
	v_mul_hi_u32 v48, v42, v34
	v_mad_u64_u32 v[18:19], null, v43, v34, 0
	v_add3_u32 v46, v35, v39, v38
	v_ashrrev_i32_e32 v44, 31, v37
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[38:39], null, v42, v46, 0
	v_mad_u64_u32 v[34:35], null, v43, v46, 0
	v_add_co_u32 v38, vcc_lo, v48, v38
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v39, vcc_lo, 0, v39, vcc_lo
	v_add_co_u32 v18, vcc_lo, v38, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_add_co_ci_u32_e32 v18, vcc_lo, v39, v19, vcc_lo
	v_add_co_ci_u32_e32 v19, vcc_lo, 0, v35, vcc_lo
	v_add_co_u32 v35, vcc_lo, v36, v44
	v_add_co_ci_u32_e32 v36, vcc_lo, v37, v44, vcc_lo
	v_add_co_u32 v18, vcc_lo, v18, v34
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_ci_u32_e32 v19, vcc_lo, 0, v19, vcc_lo
	v_xor_b32_e32 v37, v35, v44
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v38, vcc_lo, v42, v18
	v_add_co_ci_u32_e32 v39, vcc_lo, v43, v19, vcc_lo
	v_add3_u32 v34, v41, v47, v47
	v_xor_b32_e32 v36, v36, v44
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mul_hi_u32 v41, v37, v38
	v_mad_u64_u32 v[18:19], null, v37, v39, 0
	v_sub_co_u32 v40, vcc_lo, v40, v22
	v_sub_co_ci_u32_e32 v42, vcc_lo, v34, v23, vcc_lo
	v_mad_u64_u32 v[22:23], null, v36, v38, 0
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_add_co_u32 v18, vcc_lo, v41, v18
	v_mad_u64_u32 v[34:35], null, v36, v39, 0
	v_add_co_ci_u32_e32 v19, vcc_lo, 0, v19, vcc_lo
	v_ashrrev_i32_e32 v41, 31, v42
	v_add_co_u32 v18, vcc_lo, v18, v22
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_co_ci_u32_e32 v18, vcc_lo, v19, v23, vcc_lo
	v_add_co_ci_u32_e32 v19, vcc_lo, 0, v35, vcc_lo
	v_add_co_u32 v22, vcc_lo, v40, v41
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v23, s1, v18, v34
	v_add_co_ci_u32_e64 v18, s1, 0, v19, s1
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v40, v22, v41
	v_add_co_ci_u32_e32 v34, vcc_lo, v42, v41, vcc_lo
	v_mul_lo_u32 v35, v25, v23
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
	v_mul_lo_u32 v42, v24, v18
	v_mad_u64_u32 v[18:19], null, v24, v23, 0
	v_mul_hi_u32 v43, v40, v38
	v_mad_u64_u32 v[22:23], null, v40, v39, 0
	v_xor_b32_e32 v45, v34, v41
	v_add3_u32 v42, v19, v42, v35
	v_sub_co_u32 v37, s1, v37, v18
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_2)
	v_add_co_u32 v19, vcc_lo, v43, v22
	v_add_co_ci_u32_e32 v43, vcc_lo, 0, v23, vcc_lo
	v_mad_u64_u32 v[22:23], null, v45, v38, 0
	v_sub_nc_u32_e32 v46, v36, v42
	v_mad_u64_u32 v[34:35], null, v45, v39, 0
	v_sub_co_ci_u32_e64 v38, vcc_lo, v46, v25, s1
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_co_u32 v18, vcc_lo, v19, v22
	v_add_co_ci_u32_e32 v18, vcc_lo, v43, v23, vcc_lo
	v_add_co_ci_u32_e32 v19, vcc_lo, 0, v35, vcc_lo
	v_sub_co_u32 v22, vcc_lo, v37, v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_subrev_co_ci_u32_e64 v23, s2, 0, v38, vcc_lo
	v_add_co_u32 v34, s2, v18, v34
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v18, s2, 0, v19, s2
	v_cmp_ge_u32_e64 s2, v23, v25
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_lo_u32 v43, v25, v34
	v_mul_lo_u32 v46, v24, v18
	v_mad_u64_u32 v[18:19], null, v24, v34, 0
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v35, 0, -1, s2
	v_cmp_ge_u32_e64 s2, v22, v24
	v_cndmask_b32_e64 v39, 0, -1, s2
	v_cmp_eq_u32_e64 s2, v23, v25
	v_add3_u32 v19, v19, v46, v43
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v34, v35, v39, s2
	v_sub_co_ci_u32_e32 v35, vcc_lo, v38, v25, vcc_lo
	v_sub_co_u32 v38, vcc_lo, v22, v24
	v_sub_nc_u32_e32 v39, v45, v19
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_subrev_co_ci_u32_e32 v35, vcc_lo, 0, v35, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, 0, v34
	v_sub_co_u32 v18, s2, v40, v18
	v_sub_co_ci_u32_e64 v34, s3, v39, v25, s2
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_dual_cndmask_b32 v23, v23, v35 :: v_dual_cndmask_b32 v22, v22, v38
	v_sub_co_ci_u32_e64 v35, s1, v36, v42, s1
	v_sub_co_u32 v36, s1, v18, v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_subrev_co_ci_u32_e64 v39, s3, 0, v34, s1
	v_cmp_ge_u32_e64 s3, v35, v25
	v_sub_co_ci_u32_e64 v19, s2, v45, v19, s2
	v_sub_co_ci_u32_e64 v34, s1, v34, v25, s1
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v40, 0, -1, s3
	v_cmp_ge_u32_e64 s3, v37, v24
	v_cmp_eq_u32_e64 s2, v39, v25
	v_cmp_ge_u32_e64 s1, v19, v25
	v_cndmask_b32_e64 v42, 0, -1, s3
	v_cmp_ge_u32_e64 s3, v39, v25
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v43, 0, -1, s3
	v_cmp_ge_u32_e64 s3, v36, v24
	v_cndmask_b32_e64 v46, 0, -1, s3
	v_cmp_eq_u32_e64 s3, v35, v25
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v40, v40, v42, s3
	v_cndmask_b32_e64 v42, v43, v46, s2
	v_cndmask_b32_e64 v43, 0, -1, s1
	v_cmp_ge_u32_e64 s1, v18, v24
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_ne_u32_e64 s2, 0, v40
	v_cndmask_b32_e64 v45, 0, -1, s1
	v_sub_co_u32 v46, s1, v36, v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_subrev_co_ci_u32_e64 v34, s1, 0, v34, s1
	v_cmp_eq_u32_e64 s1, v19, v25
	v_cndmask_b32_e64 v22, v37, v22, s2
	v_cndmask_b32_e64 v23, v35, v23, s2
	v_cndmask_b32_e64 v43, v43, v45, s1
	v_cmp_ne_u32_e64 s1, 0, v42
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v22, v22, v44
	v_xor_b32_e32 v23, v23, v44
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cmp_ne_u32_e32 vcc_lo, 0, v43
	v_cndmask_b32_e64 v34, v39, v34, s1
	v_cndmask_b32_e64 v36, v36, v46, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v19, v19, v34 :: v_dual_cndmask_b32 v18, v18, v36
	v_sub_co_u32 v22, vcc_lo, v22, v44
	v_sub_co_ci_u32_e32 v23, vcc_lo, v23, v44, vcc_lo
	v_xor_b32_e32 v18, v18, v41
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v19, v19, v41
	v_and_b32_e32 v34, 1, v4
	v_sub_co_u32 v18, vcc_lo, v18, v41
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_co_ci_u32_e32 v19, vcc_lo, v19, v41, vcc_lo
	v_cmpx_eq_u32_e32 1, v34
	s_cbranch_execz .LBB0_5
; %bb.4:                                ;   in Loop: Header=BB0_3 Depth=1
	v_mul_lo_u32 v36, v23, v16
	v_mul_lo_u32 v37, v22, v17
	v_mad_u64_u32 v[34:35], null, v22, v16, 0
	v_mul_lo_u32 v38, v18, v21
	v_mul_lo_u32 v39, v19, v20
	v_mul_lo_u32 v40, v21, v6
	v_mul_lo_u32 v17, v18, v17
	v_add3_u32 v35, v35, v37, v36
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[36:37], null, v18, v20, v[34:35]
	v_mad_u64_u32 v[34:35], null, v20, v6, 0
	v_add3_u32 v37, v39, v37, v38
	v_mul_lo_u32 v38, v20, v7
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_and_b32_e32 v20, 1, v36
	v_add_co_u32 v39, vcc_lo, v32, v8
	v_and_b32_e32 v21, 0x80000000, v37
	v_add_co_ci_u32_e32 v39, vcc_lo, v33, v9, vcc_lo
	v_mul_lo_u32 v44, v34, v23
	v_add3_u32 v40, v35, v38, v40
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_cmp_eq_u64_e64 s1, 1, v[20:21]
	v_add_co_ci_u32_e32 v20, vcc_lo, 0, v13, vcc_lo
	v_add_co_u32 v35, vcc_lo, v39, v12
	v_mul_lo_u32 v46, v40, v22
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v38, 0, v2, s1
	v_cndmask_b32_e64 v21, 0, v3, s1
	v_add_co_ci_u32_e32 v20, vcc_lo, 0, v20, vcc_lo
	v_add_co_u32 v43, vcc_lo, v29, v35
	v_add_co_u32 v35, s1, v38, v36
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_ci_u32_e64 v36, s1, v21, v37, s1
	v_add_co_ci_u32_e32 v45, vcc_lo, v28, v20, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_lo_u32 v39, v27, v43
	v_lshrrev_b32_e32 v37, 31, v36
	v_mad_u64_u32 v[20:21], null, v26, v43, 0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_lo_u32 v41, v26, v45
	v_add_co_u32 v35, vcc_lo, v35, v37
	v_add_co_ci_u32_e32 v36, vcc_lo, 0, v36, vcc_lo
	v_mad_u64_u32 v[37:38], null, v34, v22, 0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add3_u32 v47, v21, v41, v39
	v_ashrrev_i64 v[34:35], 1, v[35:36]
	v_mul_hi_u32 v21, v43, v20
	v_ashrrev_i32_e32 v36, 31, v36
	v_mad_u64_u32 v[41:42], null, v45, v20, 0
	v_mad_u64_u32 v[39:40], null, v43, v47, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_add_co_u32 v48, vcc_lo, v34, v36
	v_add_co_ci_u32_e32 v49, vcc_lo, v35, v36, vcc_lo
	v_add3_u32 v38, v38, v44, v46
	v_add_co_u32 v34, vcc_lo, v21, v39
	v_mad_u64_u32 v[20:21], null, v45, v47, 0
	v_add_co_ci_u32_e32 v35, vcc_lo, 0, v40, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v34, vcc_lo, v34, v41
	v_xor_b32_e32 v41, v49, v36
	v_add_co_ci_u32_e32 v39, vcc_lo, v35, v42, vcc_lo
	v_mad_u64_u32 v[34:35], null, v18, v16, v[37:38]
	v_mul_lo_u32 v16, v19, v16
	v_add_co_ci_u32_e32 v21, vcc_lo, 0, v21, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v20, vcc_lo, v39, v20
	v_xor_b32_e32 v37, v48, v36
	v_add_co_ci_u32_e32 v21, vcc_lo, 0, v21, vcc_lo
	v_add3_u32 v35, v16, v35, v17
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v38, vcc_lo, v43, v20
	v_add_co_ci_u32_e32 v39, vcc_lo, v45, v21, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_and_b32_e32 v21, 0x80000000, v35
	v_and_b32_e32 v20, 1, v34
	v_mul_hi_u32 v40, v37, v38
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[16:17], null, v37, v39, 0
	v_cmp_eq_u64_e32 vcc_lo, 1, v[20:21]
	v_mad_u64_u32 v[20:21], null, v41, v39, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)
	v_add_co_u32 v40, s1, v40, v16
	v_cndmask_b32_e32 v44, 0, v2, vcc_lo
	v_add_co_ci_u32_e64 v42, s1, 0, v17, s1
	v_cndmask_b32_e32 v43, 0, v3, vcc_lo
	v_mad_u64_u32 v[16:17], null, v41, v38, 0
	v_add_co_u32 v34, vcc_lo, v44, v34
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v35, vcc_lo, v43, v35, vcc_lo
	v_add_co_u32 v16, vcc_lo, v40, v16
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v16, vcc_lo, v42, v17, vcc_lo
	v_lshrrev_b32_e32 v17, 31, v35
	v_add_co_ci_u32_e32 v21, vcc_lo, 0, v21, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v40, vcc_lo, v16, v20
	v_add_co_u32 v16, s1, v34, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_ci_u32_e64 v17, s1, 0, v35, s1
	v_add_co_ci_u32_e32 v34, vcc_lo, 0, v21, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_lo_u32 v35, v25, v40
	v_ashrrev_i64 v[20:21], 1, v[16:17]
	v_ashrrev_i32_e32 v42, 31, v17
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_lo_u32 v34, v24, v34
	v_mad_u64_u32 v[16:17], null, v24, v40, 0
	v_add_co_u32 v20, vcc_lo, v20, v42
	v_add_co_ci_u32_e32 v40, vcc_lo, v21, v42, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v43, v20, v42
	v_add3_u32 v44, v17, v34, v35
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v40, v40, v42
	v_sub_co_u32 v37, s1, v37, v16
	v_mad_u64_u32 v[20:21], null, v43, v39, 0
	v_mul_hi_u32 v17, v43, v38
	v_sub_nc_u32_e32 v45, v41, v44
	v_mad_u64_u32 v[34:35], null, v40, v39, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_add_co_u32 v17, vcc_lo, v17, v20
	v_add_co_ci_u32_e32 v46, vcc_lo, 0, v21, vcc_lo
	v_mad_u64_u32 v[20:21], null, v40, v38, 0
	v_sub_co_ci_u32_e64 v38, vcc_lo, v45, v25, s1
	v_add_co_u32 v16, vcc_lo, v17, v20
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v16, vcc_lo, v46, v21, vcc_lo
	v_add_co_ci_u32_e32 v17, vcc_lo, 0, v35, vcc_lo
	v_sub_co_u32 v20, vcc_lo, v37, v24
	v_subrev_co_ci_u32_e64 v21, s2, 0, v38, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v34, s2, v16, v34
	v_add_co_ci_u32_e64 v16, s2, 0, v17, s2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_ge_u32_e64 s2, v21, v25
	v_mul_lo_u32 v45, v25, v34
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_mul_lo_u32 v46, v24, v16
	v_mad_u64_u32 v[16:17], null, v24, v34, 0
	v_cndmask_b32_e64 v35, 0, -1, s2
	v_cmp_ge_u32_e64 s2, v20, v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v39, 0, -1, s2
	v_cmp_eq_u32_e64 s2, v21, v25
	v_add3_u32 v17, v17, v46, v45
	v_cndmask_b32_e64 v34, v35, v39, s2
	v_sub_co_ci_u32_e32 v35, vcc_lo, v38, v25, vcc_lo
	v_sub_co_u32 v38, vcc_lo, v20, v24
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v39, v40, v17
	v_subrev_co_ci_u32_e32 v35, vcc_lo, 0, v35, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, 0, v34
	v_sub_co_u32 v16, s2, v43, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_sub_co_ci_u32_e64 v34, s3, v39, v25, s2
	v_cndmask_b32_e32 v21, v21, v35, vcc_lo
	v_sub_co_ci_u32_e64 v35, s1, v41, v44, s1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_co_u32 v39, s1, v16, v24
	v_subrev_co_ci_u32_e64 v41, s3, 0, v34, s1
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_cmp_ge_u32_e64 s3, v35, v25
	v_sub_co_ci_u32_e64 v17, s2, v40, v17, s2
	v_sub_co_ci_u32_e64 v34, s1, v34, v25, s1
	v_cndmask_b32_e64 v43, 0, -1, s3
	v_cmp_ge_u32_e64 s3, v37, v24
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_cmp_ge_u32_e64 s1, v17, v25
	v_cmp_eq_u32_e64 s2, v41, v25
	v_cndmask_b32_e32 v20, v20, v38, vcc_lo
	v_cndmask_b32_e64 v44, 0, -1, s3
	v_cmp_ge_u32_e64 s3, v41, v25
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v45, 0, -1, s3
	v_cmp_ge_u32_e64 s3, v39, v24
	v_cndmask_b32_e64 v46, 0, -1, s3
	v_cmp_eq_u32_e64 s3, v35, v25
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v40, v45, v46, s2
	v_cndmask_b32_e64 v43, v43, v44, s3
	v_cndmask_b32_e64 v44, 0, -1, s1
	v_cmp_ge_u32_e64 s1, v16, v24
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_ne_u32_e64 s2, 0, v43
	v_cndmask_b32_e64 v45, 0, -1, s1
	v_sub_co_u32 v46, s1, v39, v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_subrev_co_ci_u32_e64 v34, s1, 0, v34, s1
	v_cmp_eq_u32_e64 s1, v17, v25
	v_cndmask_b32_e64 v20, v37, v20, s2
	v_cndmask_b32_e64 v21, v35, v21, s2
	v_cndmask_b32_e64 v44, v44, v45, s1
	v_cmp_ne_u32_e64 s1, 0, v40
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v20, v20, v36
	v_xor_b32_e32 v21, v21, v36
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cmp_ne_u32_e32 vcc_lo, 0, v44
	v_cndmask_b32_e64 v38, v39, v46, s1
	v_cndmask_b32_e64 v34, v41, v34, s1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v16, v16, v38, vcc_lo
	v_cndmask_b32_e32 v17, v17, v34, vcc_lo
	v_sub_co_u32 v20, vcc_lo, v20, v36
	v_sub_co_ci_u32_e32 v21, vcc_lo, v21, v36, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v16, v16, v42
	v_xor_b32_e32 v17, v17, v42
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_co_u32 v16, vcc_lo, v16, v42
	v_sub_co_ci_u32_e32 v17, vcc_lo, v17, v42, vcc_lo
.LBB0_5:                                ;   in Loop: Header=BB0_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s6
	v_add_co_u32 v32, vcc_lo, v32, v8
	v_add_co_ci_u32_e32 v32, vcc_lo, v33, v9, vcc_lo
	v_add_co_ci_u32_e32 v33, vcc_lo, 0, v13, vcc_lo
	v_mul_lo_u32 v40, v14, v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v32, vcc_lo, v32, v12
	v_add_co_ci_u32_e32 v33, vcc_lo, 0, v33, vcc_lo
	v_mad_u64_u32 v[34:35], null, v14, v14, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v37, vcc_lo, v29, v32
	v_add_co_ci_u32_e32 v38, vcc_lo, v28, v33, vcc_lo
	v_ashrrev_i64 v[4:5], 1, v[4:5]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_mul_lo_u32 v36, v27, v37
	v_mad_u64_u32 v[32:33], null, v26, v37, 0
	v_mul_lo_u32 v39, v26, v38
	v_add3_u32 v40, v35, v40, v40
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_hi_u32 v41, v37, v32
	v_add3_u32 v39, v33, v39, v36
	v_mad_u64_u32 v[35:36], null, v38, v32, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[14:15], null, v37, v39, 0
	v_mad_u64_u32 v[32:33], null, v38, v39, 0
	v_ashrrev_i32_e32 v39, 31, v40
	v_add_co_u32 v14, vcc_lo, v41, v14
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v15, vcc_lo, 0, v15, vcc_lo
	v_add_co_u32 v14, vcc_lo, v14, v35
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_add_co_ci_u32_e32 v14, vcc_lo, v15, v36, vcc_lo
	v_add_co_ci_u32_e32 v15, vcc_lo, 0, v33, vcc_lo
	v_add_co_u32 v33, vcc_lo, v34, v39
	v_add_co_ci_u32_e32 v34, vcc_lo, v40, v39, vcc_lo
	v_add_co_u32 v14, vcc_lo, v14, v32
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_ci_u32_e32 v15, vcc_lo, 0, v15, vcc_lo
	v_xor_b32_e32 v36, v33, v39
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v35, vcc_lo, v37, v14
	v_add_co_ci_u32_e32 v37, vcc_lo, v38, v15, vcc_lo
	v_xor_b32_e32 v38, v34, v39
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_hi_u32 v40, v36, v35
	v_mad_u64_u32 v[14:15], null, v36, v37, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[32:33], null, v38, v35, 0
	v_mad_u64_u32 v[34:35], null, v38, v37, 0
	v_add_co_u32 v14, vcc_lo, v40, v14
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v15, vcc_lo, 0, v15, vcc_lo
	v_add_co_u32 v14, vcc_lo, v14, v32
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v14, vcc_lo, v15, v33, vcc_lo
	v_add_co_ci_u32_e32 v15, vcc_lo, 0, v35, vcc_lo
	v_add_co_u32 v32, vcc_lo, v14, v34
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v33, vcc_lo, 0, v15, vcc_lo
	v_mul_lo_u32 v34, v25, v32
	v_mad_u64_u32 v[14:15], null, v24, v32, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v32, v24, v33
	v_sub_co_u32 v14, vcc_lo, v36, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v15, v15, v32, v34
	v_sub_nc_u32_e32 v32, v38, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_sub_co_ci_u32_e64 v32, s1, v32, v25, vcc_lo
	v_sub_co_ci_u32_e32 v15, vcc_lo, v38, v15, vcc_lo
	v_sub_co_u32 v33, vcc_lo, v14, v24
	v_subrev_co_ci_u32_e64 v34, s1, 0, v32, vcc_lo
	v_cmp_ge_u32_e64 s1, v14, v24
	v_sub_co_ci_u32_e32 v32, vcc_lo, v32, v25, vcc_lo
	v_cmp_ge_u32_e32 vcc_lo, v15, v25
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v35, 0, -1, s1
	v_cmp_ge_u32_e64 s1, v33, v24
	v_cndmask_b32_e64 v38, 0, -1, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, v34, v25
	v_cndmask_b32_e64 v36, 0, -1, s1
	v_cmp_ge_u32_e64 s1, v34, v25
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v37, 0, -1, s1
	v_cmp_eq_u32_e64 s1, v15, v25
	v_cndmask_b32_e32 v36, v37, v36, vcc_lo
	v_sub_co_u32 v37, vcc_lo, v33, v24
	v_subrev_co_ci_u32_e32 v32, vcc_lo, 0, v32, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, 0, v36
	v_cndmask_b32_e64 v35, v38, v35, s1
	v_add_co_u32 v30, s1, v30, 1
	s_or_b32 s5, s1, s5
	v_dual_cndmask_b32 v32, v34, v32 :: v_dual_cndmask_b32 v33, v33, v37
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_ne_u32_e32 vcc_lo, 0, v35
	v_dual_cndmask_b32 v15, v15, v32 :: v_dual_cndmask_b32 v14, v14, v33
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v15, v15, v39
	v_xor_b32_e32 v14, v14, v39
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_co_u32 v14, vcc_lo, v14, v39
	v_sub_co_ci_u32_e32 v15, vcc_lo, v15, v39, vcc_lo
	s_and_not1_b32 exec_lo, exec_lo, s5
	s_cbranch_execnz .LBB0_3
; %bb.6:                                ; %.loopexit.loopexit
	s_or_b32 exec_lo, exec_lo, s5
	v_cmp_eq_u64_e32 vcc_lo, 0, v[20:21]
	v_cndmask_b32_e64 v8, 0, 1, vcc_lo
.LBB0_7:                                ; %Flow
	s_or_b32 exec_lo, exec_lo, s4
.LBB0_8:                                ; %.loopexit
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s10
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_10
; %bb.9:
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s8, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s9, v1, vcc_lo
	global_store_b32 v[0:1], v8, off
.LBB0_10:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z12kernel_lucasPlS_Pil
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 32
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 50
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z12kernel_lucasPlS_Pil, .Lfunc_end0-_Z12kernel_lucasPlS_Pil
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 3584
; NumSgprs: 18
; NumVgprs: 50
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 6
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 50
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           8
        .value_kind:     by_value
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 32
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z12kernel_lucasPlS_Pil
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z12kernel_lucasPlS_Pil.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     50
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
