#include <cuda_runtime_api.h>
#include <stdint.h>

#define OFFSET_BANK(idx) ({ __typeof__ (idx) _idx = idx; ((_idx) + ((_idx) / 32)); })

__global__ void im2col_gpu_kernel(
    const int n,
    const float* data_im,
    const int height, const int width,
    const int kernel_h, const int kernel_w,
    const int pad_h, const int pad_w,
    const int stride_h, const int stride_w,
    const int dilation_h, const int dilation_w,
    const int height_col, const int width_col,
    float* data_col)
{
  int index = threadIdx.x + blockDim.x * blockIdx.x;
  if (index < n) {
    const int h_index = index / width_col;
    const int h_col = h_index % height_col;
    const int w_col = index % width_col;
    const int c_im = h_index / height_col;
    const int c_col = c_im * kernel_h * kernel_w;
    const int h_offset = h_col * stride_h - pad_h;
    const int w_offset = w_col * stride_w - pad_w;
    float* data_col_ptr = data_col;
    data_col_ptr += (c_col * height_col + h_col) * width_col + w_col;
    const float* data_im_ptr = data_im;
    data_im_ptr += (c_im * height + h_offset) * width + w_offset;
    for (int i = 0; i < kernel_h; ++i) {
      for (int j = 0; j < kernel_w; ++j) {
        int h_im = h_offset + i * dilation_h;
        int w_im = w_offset + j * dilation_w;
        *data_col_ptr =
            (h_im >= 0 && w_im >= 0 && h_im < height && w_im < width) ?
            data_im_ptr[i * dilation_h * width + j * dilation_w] : 0;
        data_col_ptr += height_col * width_col;
      }
    }
  }
}

extern "C" void neuralops_cuda_caffe_im2col(
    const float* data_im,
    const int channels,
    const int height, const int width,
    const int kernel_h, const int kernel_w,
    const int pad_h, const int pad_w,
    const int stride_h, const int stride_w,
    const int dilation_h, const int dilation_w,
    float* data_col,
    cudaStream_t stream)
{
  // We are going to launch channels * height_col * width_col kernels, each
  // kernel responsible for copying a single-channel grid.
  int height_col = (height + 2 * pad_h -
      (dilation_h * (kernel_h - 1) + 1)) / stride_h + 1;
  int width_col = (width + 2 * pad_w -
      (dilation_w * (kernel_w - 1) + 1)) / stride_w + 1;
  int num_kernels = channels * height_col * width_col;
  // NOLINT_NEXT_LINE(whitespace/operators)
  im2col_gpu_kernel<<<(num_kernels+1024-1)/1024, 1024, 0, stream>>>(
      num_kernels, data_im, height, width, kernel_h, kernel_w, pad_h,
      pad_w, stride_h, stride_w, dilation_h, dilation_w, height_col,
      width_col, data_col);
}

__global__ void col2im_gpu_kernel(
    const int n,
    const float* data_col,
    const int height, const int width, const int channels,
    const int kernel_h, const int kernel_w,
    const int pad_h, const int pad_w,
    const int stride_h, const int stride_w,
    const int dilation_h, const int dilation_w,
    const int height_col, const int width_col,
    float* data_im)
{
  int index = threadIdx.x + blockDim.x * blockIdx.x;
  if (index < n) {
    float val = 0;
    const int w_im = index % width + pad_w;
    const int h_im = (index / width) % height + pad_h;
    const int c_im = index / (width * height);
    int kernel_extent_w = (kernel_w - 1) * dilation_w + 1;
    int kernel_extent_h = (kernel_h - 1) * dilation_h + 1;
    // compute the start and end of the output
    const int w_col_start =
        (w_im < kernel_extent_w) ? 0 : (w_im - kernel_extent_w) / stride_w + 1;
    const int w_col_end = min(w_im / stride_w + 1, width_col);
    const int h_col_start =
        (h_im < kernel_extent_h) ? 0 : (h_im - kernel_extent_h) / stride_h + 1;
    const int h_col_end = min(h_im / stride_h + 1, height_col);
    // TODO: use LCM of stride and dilation to avoid unnecessary loops
    for (int h_col = h_col_start; h_col < h_col_end; h_col += 1) {
      for (int w_col = w_col_start; w_col < w_col_end; w_col += 1) {
        int h_k = (h_im - h_col * stride_h);
        int w_k = (w_im - w_col * stride_w);
        if (h_k % dilation_h == 0 && w_k % dilation_w == 0) {
          h_k /= dilation_h;
          w_k /= dilation_w;
          int data_col_index = (((c_im * kernel_h + h_k) * kernel_w + w_k) *
                                height_col + h_col) * width_col + w_col;
          val += data_col[data_col_index];
        }
      }
    }
    data_im[index] = val;
  }
}

extern "C" void neuralops_cuda_caffe_col2im(
    const float* data_col,
    const int channels,
    const int height, const int width,
    const int kernel_h, const int kernel_w,
    const int pad_h, const int pad_w,
    const int stride_h, const int stride_w,
    const int dilation_h, const int dilation_w,
    float* data_im,
    cudaStream_t stream)
{
  int height_col = (height + 2 * pad_h - (dilation_h * (kernel_h - 1) + 1)) /
      stride_h + 1;
  int width_col = (width + 2 * pad_w - (dilation_w * (kernel_w - 1) + 1)) /
      stride_w + 1;
  int num_kernels = channels * height * width;
  // To avoid involving atomic operations, we will launch one kernel per
  // bottom dimension, and then in the kernel add up the top dimensions.
  // NOLINT_NEXT_LINE(whitespace/operators)
  col2im_gpu_kernel<<<(num_kernels+1024-1)/1024, 1024, 0, stream>>>(
      num_kernels, data_col, height, width, channels, kernel_h, kernel_w,
      pad_h, pad_w, stride_h, stride_w, dilation_h, dilation_w,
      height_col, width_col, data_im);
}

__global__ void conv_diag_affine_fwd_batch_kernel(
    const float *in_act,
    int spatial_dim,
    int num_channels,
    int batch_size,
    const float *scale,
    const float *bias,
    float *out_act)
{
  int idx = threadIdx.x + blockIdx.x * blockDim.x;
  int u = idx % spatial_dim;
  int c = (idx / spatial_dim) % num_channels;
  int batch_idx = idx / (spatial_dim * num_channels);
  if (u < spatial_dim && c < num_channels && batch_idx < batch_size) {
    float gamma = scale[c];
    float beta = bias[c];
    float y = gamma * in_act[idx] + beta;
    out_act[idx] = y;
  }
}

extern "C" void neuralops_cuda_conv2d_scale_fwd(
    const float *in_act,
    size_t spatial_dim,
    size_t num_channels,
    size_t batch_size,
    const float *scale,
    const float *bias,
    float *out_act,
    cudaStream_t stream)
{
  int n = spatial_dim * num_channels * batch_size;
  conv_diag_affine_fwd_batch_kernel<<<(n+1024-1)/1024, 1024, 0, stream>>>(
      in_act, spatial_dim, num_channels, batch_size, scale, bias, out_act);
}

__global__ void conv_diag_affine_bwd_batch_kernel(
    const float *in_act,
    int spatial_dim,
    int num_channels,
    int batch_size,
    const float *out_delta,
    const float *scale,
    float *scale_grad,
    float *bias_grad,
    float *in_delta)
{
  __shared__ float scale_grad_cache[1024+32];
  __shared__ float bias_grad_cache[1024+32];
  int idx = threadIdx.x + blockIdx.x * blockDim.x;
  int bank_idx = OFFSET_BANK(threadIdx.x);
  int block_spatial_dim = (spatial_dim+16*32-1)/(16*32);
  int warp_idx = idx % 32;
  int c = (idx / 32) % num_channels;
  int u0 = warp_idx + ((idx / (32 * num_channels)) % block_spatial_dim) * (16*32);
  int batch_idx = idx / (32 * num_channels * block_spatial_dim);
  if (c < num_channels && u0 < spatial_dim && batch_idx < batch_size) {
    float gamma = scale[c];
    float d_gamma = 0.0f;
    float d_beta = 0.0f;
    int i0 = c * spatial_dim + batch_idx * spatial_dim * num_channels;
    int u_limit = min(spatial_dim, u0 + 16*32);
    for (int u = u0; u < u_limit; u += 32) {
      int i = i0 + u;
      float dy = out_delta[i];
      d_gamma += dy * in_act[i];
      d_beta += dy;
      in_delta[i] = dy * gamma;
      //in_delta[i] += dy * gamma;
      //atomicAdd(&in_delta[i], dy * gamma);
    }
    scale_grad_cache[bank_idx] = d_gamma;
    bias_grad_cache[bank_idx] = d_beta;
  } else {
    scale_grad_cache[bank_idx] = 0.0f;
    bias_grad_cache[bank_idx] = 0.0f;
  }
  __syncthreads();
  if (c < num_channels && batch_idx < batch_size) {
    if (threadIdx.x % 2 == 0) {
      scale_grad_cache[bank_idx] += scale_grad_cache[bank_idx+1];
      bias_grad_cache[bank_idx] += bias_grad_cache[bank_idx+1];
    }
  }
  __syncthreads();
  if (c < num_channels && batch_idx < batch_size) {
    if (threadIdx.x % 4 == 0) {
      scale_grad_cache[bank_idx] += scale_grad_cache[bank_idx+2];
      bias_grad_cache[bank_idx] += bias_grad_cache[bank_idx+2];
    }
  }
  __syncthreads();
  if (c < num_channels && batch_idx < batch_size) {
    if (threadIdx.x % 8 == 0) {
      scale_grad_cache[bank_idx] += scale_grad_cache[bank_idx+4];
      bias_grad_cache[bank_idx] += bias_grad_cache[bank_idx+4];
    }
  }
  __syncthreads();
  if (c < num_channels && batch_idx < batch_size) {
    if (threadIdx.x % 16 == 0) {
      scale_grad_cache[bank_idx] += scale_grad_cache[bank_idx+8];
      bias_grad_cache[bank_idx] += bias_grad_cache[bank_idx+8];
    }
  }
  __syncthreads();
  if (c < num_channels && batch_idx < batch_size) {
    if (threadIdx.x % 32 == 0 && u0 < spatial_dim) {
      float d_gamma = scale_grad_cache[bank_idx] + scale_grad_cache[bank_idx+16];
      atomicAdd(&scale_grad[c], d_gamma);
      float d_beta = bias_grad_cache[bank_idx] + bias_grad_cache[bank_idx+16];
      atomicAdd(&bias_grad[c], d_beta);
    }
  }
}

extern "C" void neuralops_cuda_conv2d_scale_bwd(
    const float *in_act,
    size_t spatial_dim,
    size_t num_channels,
    size_t batch_size,
    const float *out_delta,
    const float *scale,
    float *scale_grad,
    float *bias_grad,
    float *in_delta,
    cudaStream_t stream)
{
  int block_spatial_dim = (spatial_dim+16*32-1)/(16*32);
  int n = 32 * num_channels * block_spatial_dim * batch_size;
  conv_diag_affine_bwd_batch_kernel<<<(n+1024-1)/1024, 1024, 0, stream>>>(
      in_act, spatial_dim, num_channels, batch_size, out_delta, scale, scale_grad, bias_grad, in_delta);
}

__global__ void conv_scale_rfwd_kernel(
    const float *in_val,
    uint32_t spatial_dim,
    uint32_t num_channels,
    uint32_t batch_size,
    const float *in_r_val,
    const float *scale,
    const float *scale_r_dir,
    const float *bias_r_dir,
    float *out_r_val)
{
  uint32_t idx = threadIdx.x + blockIdx.x * blockDim.x;
  uint32_t u = idx % spatial_dim;
  uint32_t c = (idx / spatial_dim) % num_channels;
  uint32_t batch_idx = idx / (spatial_dim * num_channels);
  if (u < spatial_dim && c < num_channels && batch_idx < batch_size) {
    float alpha = scale[c];
    float r_alpha = scale_r_dir[c];
    float r_beta = bias_r_dir[c];
    float r_y = alpha * in_r_val[idx] + r_alpha * in_val[idx] + r_beta;
    out_r_val[idx] = r_y;
  }
}

extern "C" void neuralops_cuda_conv_scale_rfwd(
    const float *in_val,
    size_t spatial_dim,
    size_t num_channels,
    size_t batch_size,
    const float *in_r_val,
    const float *scale,
    const float *scale_r_dir,
    const float *bias_r_dir,
    float *out_r_val,
    cudaStream_t stream)
{
  uint32_t n = spatial_dim * num_channels * batch_size;
  conv_scale_rfwd_kernel<<<(n+1024-1)/1024, 1024, 0, stream>>>(
      in_val, spatial_dim, num_channels, batch_size, in_r_val, scale, scale_r_dir, bias_r_dir, out_r_val);
}

	.file	"tmpxft_00226103_00000000-6_conv.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2015:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2015:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z53__device_stub__Z17im2col_gpu_kerneliPKfiiiiiiiiiiiiPfiPKfiiiiiiiiiiiiPf
	.type	_Z53__device_stub__Z17im2col_gpu_kerneliPKfiiiiiiiiiiiiPfiPKfiiiiiiiiiiiiPf, @function
_Z53__device_stub__Z17im2col_gpu_kerneliPKfiiiiiiiiiiiiPfiPKfiiiiiiiiiiiiPf:
.LFB2037:
	.cfi_startproc
	endbr64
	subq	$248, %rsp
	.cfi_def_cfa_offset 256
	movq	320(%rsp), %rax
	movl	%edi, 44(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movl	%edx, 40(%rsp)
	leaq	48(%rsp), %rdx
	movl	%ecx, 28(%rsp)
	leaq	56(%rsp), %rcx
	movl	%r8d, 24(%rsp)
	movl	%r9d, 20(%rsp)
	movq	%rax, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 232(%rsp)
	xorl	%eax, %eax
	leaq	44(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 112(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	28(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	256(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	264(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	272(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	280(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	288(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	296(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	304(%rsp), %rax
	movq	%rax, 208(%rsp)
	leaq	312(%rsp), %rax
	movq	%rax, 216(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 224(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	56(%rsp)
	.cfi_def_cfa_offset 264
	leaq	_Z17im2col_gpu_kerneliPKfiiiiiiiiiiiiPf(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 272
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 264
	popq	%rdx
	.cfi_def_cfa_offset 256
.L2:
	movq	232(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$248, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2037:
	.size	_Z53__device_stub__Z17im2col_gpu_kerneliPKfiiiiiiiiiiiiPfiPKfiiiiiiiiiiiiPf, .-_Z53__device_stub__Z17im2col_gpu_kerneliPKfiiiiiiiiiiiiPfiPKfiiiiiiiiiiiiPf
	.globl	_Z17im2col_gpu_kerneliPKfiiiiiiiiiiiiPf
	.type	_Z17im2col_gpu_kerneliPKfiiiiiiiiiiiiPf, @function
_Z17im2col_gpu_kerneliPKfiiiiiiiiiiiiPf:
.LFB2038:
	.cfi_startproc
	endbr64
	jmp	_Z53__device_stub__Z17im2col_gpu_kerneliPKfiiiiiiiiiiiiPfiPKfiiiiiiiiiiiiPf
	.cfi_endproc
.LFE2038:
	.size	_Z17im2col_gpu_kerneliPKfiiiiiiiiiiiiPf, .-_Z17im2col_gpu_kerneliPKfiiiiiiiiiiiiPf
	.globl	neuralops_cuda_caffe_im2col
	.type	neuralops_cuda_caffe_im2col, @function
neuralops_cuda_caffe_im2col:
.LFB2008:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movl	%r8d, %r15d
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	movl	%ecx, %r14d
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movl	%edx, %r13d
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$56, %rsp
	.cfi_def_cfa_offset 112
	movl	112(%rsp), %eax
	movq	%rdi, (%rsp)
	movl	%r9d, 12(%rsp)
	leal	(%rdx,%rax,2), %eax
	leal	-1(%r8), %edx
	xorl	%r8d, %r8d
	imull	144(%rsp), %edx
	incl	%edx
	subl	%edx, %eax
	cltd
	idivl	128(%rsp)
	leal	-1(%r9), %edx
	movq	168(%rsp), %r9
	imull	152(%rsp), %edx
	incl	%edx
	leal	1(%rax), %ebx
	movl	120(%rsp), %eax
	imull	%ebx, %esi
	leal	(%rcx,%rax,2), %eax
	movl	$1024, %ecx
	subl	%edx, %eax
	cltd
	movl	%esi, %r12d
	idivl	136(%rsp)
	leal	1(%rax), %ebp
	imull	%ebp, %r12d
	leal	1023(%r12), %eax
	cltd
	idivl	%ecx
	movl	$4194305, %edx
	movl	$1, %ecx
	salq	$10, %rdx
	movl	%eax, 24(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 28(%rsp)
	movq	24(%rsp), %rdi
	movl	32(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	movl	12(%rsp), %r11d
	testl	%eax, %eax
	jne	.L8
	pushq	%rax
	.cfi_def_cfa_offset 120
	movl	%r11d, %r9d
	movl	%r15d, %r8d
	movl	%r14d, %ecx
	pushq	168(%rsp)
	.cfi_def_cfa_offset 128
	movl	%r13d, %edx
	movl	%r12d, %edi
	pushq	%rbp
	.cfi_def_cfa_offset 136
	pushq	%rbx
	.cfi_def_cfa_offset 144
	movl	184(%rsp), %eax
	pushq	%rax
	.cfi_def_cfa_offset 152
	movl	184(%rsp), %eax
	pushq	%rax
	.cfi_def_cfa_offset 160
	movl	184(%rsp), %eax
	pushq	%rax
	.cfi_def_cfa_offset 168
	movl	184(%rsp), %eax
	pushq	%rax
	.cfi_def_cfa_offset 176
	movl	184(%rsp), %eax
	pushq	%rax
	.cfi_def_cfa_offset 184
	movl	184(%rsp), %eax
	pushq	%rax
	.cfi_def_cfa_offset 192
	movq	80(%rsp), %rsi
	call	_Z53__device_stub__Z17im2col_gpu_kerneliPKfiiiiiiiiiiiiPfiPKfiiiiiiiiiiiiPf
	addq	$80, %rsp
	.cfi_def_cfa_offset 112
.L8:
	addq	$56, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2008:
	.size	neuralops_cuda_caffe_im2col, .-neuralops_cuda_caffe_im2col
	.globl	_Z54__device_stub__Z17col2im_gpu_kerneliPKfiiiiiiiiiiiiiPfiPKfiiiiiiiiiiiiiPf
	.type	_Z54__device_stub__Z17col2im_gpu_kerneliPKfiiiiiiiiiiiiiPfiPKfiiiiiiiiiiiiiPf, @function
_Z54__device_stub__Z17col2im_gpu_kerneliPKfiiiiiiiiiiiiiPfiPKfiiiiiiiiiiiiiPf:
.LFB2039:
	.cfi_startproc
	endbr64
	subq	$264, %rsp
	.cfi_def_cfa_offset 272
	movq	344(%rsp), %rax
	movl	%edi, 44(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movl	%edx, 40(%rsp)
	leaq	56(%rsp), %rdx
	movl	%ecx, 28(%rsp)
	leaq	64(%rsp), %rcx
	movl	%r8d, 24(%rsp)
	movl	%r9d, 20(%rsp)
	movq	%rax, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 248(%rsp)
	xorl	%eax, %eax
	leaq	44(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	28(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	272(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	280(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	288(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	296(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	304(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	312(%rsp), %rax
	movq	%rax, 208(%rsp)
	leaq	320(%rsp), %rax
	movq	%rax, 216(%rsp)
	leaq	328(%rsp), %rax
	movq	%rax, 224(%rsp)
	leaq	336(%rsp), %rax
	movq	%rax, 232(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 240(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L11
	pushq	64(%rsp)
	.cfi_def_cfa_offset 280
	leaq	_Z17col2im_gpu_kerneliPKfiiiiiiiiiiiiiPf(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 288
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 280
	popq	%rdx
	.cfi_def_cfa_offset 272
.L11:
	movq	248(%rsp), %rax
	subq	%fs:40, %rax
	je	.L13
	call	__stack_chk_fail@PLT
.L13:
	addq	$264, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2039:
	.size	_Z54__device_stub__Z17col2im_gpu_kerneliPKfiiiiiiiiiiiiiPfiPKfiiiiiiiiiiiiiPf, .-_Z54__device_stub__Z17col2im_gpu_kerneliPKfiiiiiiiiiiiiiPfiPKfiiiiiiiiiiiiiPf
	.globl	_Z17col2im_gpu_kerneliPKfiiiiiiiiiiiiiPf
	.type	_Z17col2im_gpu_kerneliPKfiiiiiiiiiiiiiPf, @function
_Z17col2im_gpu_kerneliPKfiiiiiiiiiiiiiPf:
.LFB2040:
	.cfi_startproc
	endbr64
	jmp	_Z54__device_stub__Z17col2im_gpu_kerneliPKfiiiiiiiiiiiiiPfiPKfiiiiiiiiiiiiiPf
	.cfi_endproc
.LFE2040:
	.size	_Z17col2im_gpu_kerneliPKfiiiiiiiiiiiiiPf, .-_Z17col2im_gpu_kerneliPKfiiiiiiiiiiiiiPf
	.globl	neuralops_cuda_caffe_col2im
	.type	neuralops_cuda_caffe_col2im, @function
neuralops_cuda_caffe_col2im:
.LFB2009:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movl	%r9d, %r15d
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	movl	%r8d, %r14d
	xorl	%r8d, %r8d
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movl	%esi, %r13d
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movl	%edx, %r12d
	imull	%esi, %r12d
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movl	%ecx, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movl	%edx, %ebx
	imull	%ecx, %r12d
	movl	$1024, %ecx
	subq	$56, %rsp
	.cfi_def_cfa_offset 112
	movq	%rdi, 8(%rsp)
	movq	168(%rsp), %r9
	leal	1023(%r12), %eax
	cltd
	idivl	%ecx
	movl	$4194305, %edx
	movl	$1, %ecx
	salq	$10, %rdx
	movl	%eax, 24(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 28(%rsp)
	movq	24(%rsp), %rdi
	movl	32(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L16
	pushq	160(%rsp)
	.cfi_def_cfa_offset 120
	leal	-1(%r15), %edx
	movl	%r14d, %r9d
	movl	%ebp, %ecx
	imull	160(%rsp), %edx
	movl	%r13d, %r8d
	movl	%r12d, %edi
	movl	128(%rsp), %eax
	incl	%edx
	leal	0(%rbp,%rax,2), %eax
	subl	%edx, %eax
	cltd
	idivl	144(%rsp)
	leal	-1(%r14), %edx
	incl	%eax
	pushq	%rax
	.cfi_def_cfa_offset 128
	imull	160(%rsp), %edx
	movl	128(%rsp), %eax
	incl	%edx
	leal	(%rbx,%rax,2), %eax
	subl	%edx, %eax
	cltd
	idivl	144(%rsp)
	movl	%ebx, %edx
	incl	%eax
	pushq	%rax
	.cfi_def_cfa_offset 136
	movl	176(%rsp), %eax
	pushq	%rax
	.cfi_def_cfa_offset 144
	movl	176(%rsp), %eax
	pushq	%rax
	.cfi_def_cfa_offset 152
	movl	176(%rsp), %eax
	pushq	%rax
	.cfi_def_cfa_offset 160
	movl	176(%rsp), %eax
	pushq	%rax
	.cfi_def_cfa_offset 168
	movl	176(%rsp), %eax
	pushq	%rax
	.cfi_def_cfa_offset 176
	movl	176(%rsp), %eax
	pushq	%rax
	.cfi_def_cfa_offset 184
	pushq	%r15
	.cfi_def_cfa_offset 192
	movq	88(%rsp), %rsi
	call	_Z54__device_stub__Z17col2im_gpu_kerneliPKfiiiiiiiiiiiiiPfiPKfiiiiiiiiiiiiiPf
	addq	$80, %rsp
	.cfi_def_cfa_offset 112
.L16:
	addq	$56, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2009:
	.size	neuralops_cuda_caffe_col2im, .-neuralops_cuda_caffe_col2im
	.globl	_Z65__device_stub__Z33conv_diag_affine_fwd_batch_kernelPKfiiiS0_S0_PfPKfiiiS0_S0_Pf
	.type	_Z65__device_stub__Z33conv_diag_affine_fwd_batch_kernelPKfiiiS0_S0_PfPKfiiiS0_S0_Pf, @function
_Z65__device_stub__Z33conv_diag_affine_fwd_batch_kernelPKfiiiS0_S0_PfPKfiiiS0_S0_Pf:
.LFB2041:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	192(%rsp), %rax
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movl	%esi, 36(%rsp)
	leaq	76(%rsp), %rsi
	movl	%edx, 32(%rsp)
	leaq	48(%rsp), %rdx
	movl	%ecx, 28(%rsp)
	leaq	56(%rsp), %rcx
	movq	%r8, 16(%rsp)
	movq	%r9, 8(%rsp)
	movq	%rax, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 112(%rsp)
	leaq	36(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	28(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 152(%rsp)
	movq	%rsp, %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L19
	pushq	56(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z33conv_diag_affine_fwd_batch_kernelPKfiiiS0_S0_Pf(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 208
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L19:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L21
	call	__stack_chk_fail@PLT
.L21:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2041:
	.size	_Z65__device_stub__Z33conv_diag_affine_fwd_batch_kernelPKfiiiS0_S0_PfPKfiiiS0_S0_Pf, .-_Z65__device_stub__Z33conv_diag_affine_fwd_batch_kernelPKfiiiS0_S0_PfPKfiiiS0_S0_Pf
	.globl	_Z33conv_diag_affine_fwd_batch_kernelPKfiiiS0_S0_Pf
	.type	_Z33conv_diag_affine_fwd_batch_kernelPKfiiiS0_S0_Pf, @function
_Z33conv_diag_affine_fwd_batch_kernelPKfiiiS0_S0_Pf:
.LFB2042:
	.cfi_startproc
	endbr64
	jmp	_Z65__device_stub__Z33conv_diag_affine_fwd_batch_kernelPKfiiiS0_S0_PfPKfiiiS0_S0_Pf
	.cfi_endproc
.LFE2042:
	.size	_Z33conv_diag_affine_fwd_batch_kernelPKfiiiS0_S0_Pf, .-_Z33conv_diag_affine_fwd_batch_kernelPKfiiiS0_S0_Pf
	.globl	neuralops_cuda_conv2d_scale_fwd
	.type	neuralops_cuda_conv2d_scale_fwd, @function
neuralops_cuda_conv2d_scale_fwd:
.LFB2010:
	.cfi_startproc
	endbr64
	movl	%edx, %eax
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movq	%rcx, %r15
	imull	%ecx, %eax
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	movl	$1024, %ecx
	movq	%r9, %r14
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movq	%r8, %r13
	xorl	%r8d, %r8d
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	imull	%esi, %eax
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movq	%rdx, %rbp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movq	%rsi, %rbx
	addl	$1023, %eax
	cltd
	subq	$56, %rsp
	.cfi_def_cfa_offset 112
	idivl	%ecx
	movq	%rdi, 8(%rsp)
	movq	120(%rsp), %r9
	movq	112(%rsp), %r12
	movl	$4194305, %edx
	movl	$1, %ecx
	salq	$10, %rdx
	movl	%eax, 24(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 28(%rsp)
	movq	24(%rsp), %rdi
	movl	32(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L24
	movq	%r12, 112(%rsp)
	movq	8(%rsp), %rdi
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 56
	movl	%ebp, %edx
	movq	%r14, %r9
	movq	%r13, %r8
	movl	%r15d, %ecx
	movl	%ebx, %esi
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	_Z65__device_stub__Z33conv_diag_affine_fwd_batch_kernelPKfiiiS0_S0_PfPKfiiiS0_S0_Pf
.L24:
	.cfi_restore_state
	addq	$56, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2010:
	.size	neuralops_cuda_conv2d_scale_fwd, .-neuralops_cuda_conv2d_scale_fwd
	.globl	_Z71__device_stub__Z33conv_diag_affine_bwd_batch_kernelPKfiiiS0_S0_PfS1_S1_PKfiiiS0_S0_PfS1_S1_
	.type	_Z71__device_stub__Z33conv_diag_affine_bwd_batch_kernelPKfiiiS0_S0_PfS1_S1_PKfiiiS0_S0_PfS1_S1_, @function
_Z71__device_stub__Z33conv_diag_affine_bwd_batch_kernelPKfiiiS0_S0_PfS1_S1_PKfiiiS0_S0_PfS1_S1_:
.LFB2043:
	.cfi_startproc
	endbr64
	subq	$216, %rsp
	.cfi_def_cfa_offset 224
	movq	224(%rsp), %rax
	movq	%rdi, 56(%rsp)
	leaq	80(%rsp), %rdi
	movl	%esi, 52(%rsp)
	leaq	92(%rsp), %rsi
	movq	%rax, 16(%rsp)
	movq	232(%rsp), %rax
	movl	%edx, 48(%rsp)
	leaq	64(%rsp), %rdx
	movq	%rax, 8(%rsp)
	movq	240(%rsp), %rax
	movl	%ecx, 44(%rsp)
	leaq	72(%rsp), %rcx
	movq	%r8, 32(%rsp)
	movq	%r9, 24(%rsp)
	movq	%rax, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 200(%rsp)
	xorl	%eax, %eax
	leaq	56(%rsp), %rax
	movl	$1, 88(%rsp)
	movq	%rax, 128(%rsp)
	leaq	52(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	44(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 184(%rsp)
	movq	%rsp, %rax
	movq	%rax, 192(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 80(%rsp)
	movq	%rax, 92(%rsp)
	movl	$1, 100(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L27
	pushq	72(%rsp)
	.cfi_def_cfa_offset 232
	leaq	_Z33conv_diag_affine_bwd_batch_kernelPKfiiiS0_S0_PfS1_S1_(%rip), %rdi
	pushq	72(%rsp)
	.cfi_def_cfa_offset 240
	movq	108(%rsp), %rcx
	movl	116(%rsp), %r8d
	movq	96(%rsp), %rsi
	movl	104(%rsp), %edx
	leaq	144(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 232
	popq	%rdx
	.cfi_def_cfa_offset 224
.L27:
	movq	200(%rsp), %rax
	subq	%fs:40, %rax
	je	.L29
	call	__stack_chk_fail@PLT
.L29:
	addq	$216, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2043:
	.size	_Z71__device_stub__Z33conv_diag_affine_bwd_batch_kernelPKfiiiS0_S0_PfS1_S1_PKfiiiS0_S0_PfS1_S1_, .-_Z71__device_stub__Z33conv_diag_affine_bwd_batch_kernelPKfiiiS0_S0_PfS1_S1_PKfiiiS0_S0_PfS1_S1_
	.globl	_Z33conv_diag_affine_bwd_batch_kernelPKfiiiS0_S0_PfS1_S1_
	.type	_Z33conv_diag_affine_bwd_batch_kernelPKfiiiS0_S0_PfS1_S1_, @function
_Z33conv_diag_affine_bwd_batch_kernelPKfiiiS0_S0_PfS1_S1_:
.LFB2044:
	.cfi_startproc
	endbr64
	jmp	_Z71__device_stub__Z33conv_diag_affine_bwd_batch_kernelPKfiiiS0_S0_PfS1_S1_PKfiiiS0_S0_PfS1_S1_
	.cfi_endproc
.LFE2044:
	.size	_Z33conv_diag_affine_bwd_batch_kernelPKfiiiS0_S0_PfS1_S1_, .-_Z33conv_diag_affine_bwd_batch_kernelPKfiiiS0_S0_PfS1_S1_
	.globl	neuralops_cuda_conv2d_scale_bwd
	.type	neuralops_cuda_conv2d_scale_bwd, @function
neuralops_cuda_conv2d_scale_bwd:
.LFB2011:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movq	%rcx, %r12
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movq	%rdx, %rbp
	leaq	511(%rsi), %rdx
	movl	%ebp, %eax
	shrq	$9, %rdx
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movq	%rsi, %rbx
	imull	%ecx, %eax
	movl	$1024, %ecx
	subq	$72, %rsp
	.cfi_def_cfa_offset 128
	imull	%edx, %eax
	movq	%rdi, 8(%rsp)
	movq	128(%rsp), %r15
	movq	%r9, 24(%rsp)
	movq	152(%rsp), %r9
	movq	%r8, 16(%rsp)
	xorl	%r8d, %r8d
	movq	136(%rsp), %r13
	sall	$5, %eax
	movq	144(%rsp), %r14
	addl	$1023, %eax
	cltd
	idivl	%ecx
	movl	$4194305, %edx
	movl	$1, %ecx
	salq	$10, %rdx
	movl	%eax, 40(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 44(%rsp)
	movq	40(%rsp), %rdi
	movl	48(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L32
	movq	%r14, 144(%rsp)
	movl	%r12d, %ecx
	movl	%ebp, %edx
	movl	%ebx, %esi
	movq	%r13, 136(%rsp)
	movq	24(%rsp), %r9
	movq	%r15, 128(%rsp)
	movq	16(%rsp), %r8
	movq	8(%rsp), %rdi
	addq	$72, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	_Z71__device_stub__Z33conv_diag_affine_bwd_batch_kernelPKfiiiS0_S0_PfS1_S1_PKfiiiS0_S0_PfS1_S1_
.L32:
	.cfi_restore_state
	addq	$72, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2011:
	.size	neuralops_cuda_conv2d_scale_bwd, .-neuralops_cuda_conv2d_scale_bwd
	.globl	_Z60__device_stub__Z22conv_scale_rfwd_kernelPKfjjjS0_S0_S0_S0_PfPKfjjjS0_S0_S0_S0_Pf
	.type	_Z60__device_stub__Z22conv_scale_rfwd_kernelPKfjjjS0_S0_S0_S0_PfPKfjjjS0_S0_S0_S0_Pf, @function
_Z60__device_stub__Z22conv_scale_rfwd_kernelPKfjjjS0_S0_S0_S0_PfPKfjjjS0_S0_S0_S0_Pf:
.LFB2045:
	.cfi_startproc
	endbr64
	subq	$216, %rsp
	.cfi_def_cfa_offset 224
	movq	224(%rsp), %rax
	movq	%rdi, 56(%rsp)
	leaq	80(%rsp), %rdi
	movl	%esi, 52(%rsp)
	leaq	92(%rsp), %rsi
	movq	%rax, 16(%rsp)
	movq	232(%rsp), %rax
	movl	%edx, 48(%rsp)
	leaq	64(%rsp), %rdx
	movq	%rax, 8(%rsp)
	movq	240(%rsp), %rax
	movl	%ecx, 44(%rsp)
	leaq	72(%rsp), %rcx
	movq	%r8, 32(%rsp)
	movq	%r9, 24(%rsp)
	movq	%rax, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 200(%rsp)
	xorl	%eax, %eax
	leaq	56(%rsp), %rax
	movl	$1, 88(%rsp)
	movq	%rax, 128(%rsp)
	leaq	52(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	44(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 184(%rsp)
	movq	%rsp, %rax
	movq	%rax, 192(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 80(%rsp)
	movq	%rax, 92(%rsp)
	movl	$1, 100(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L35
	pushq	72(%rsp)
	.cfi_def_cfa_offset 232
	leaq	_Z22conv_scale_rfwd_kernelPKfjjjS0_S0_S0_S0_Pf(%rip), %rdi
	pushq	72(%rsp)
	.cfi_def_cfa_offset 240
	movq	108(%rsp), %rcx
	movl	116(%rsp), %r8d
	movq	96(%rsp), %rsi
	movl	104(%rsp), %edx
	leaq	144(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 232
	popq	%rdx
	.cfi_def_cfa_offset 224
.L35:
	movq	200(%rsp), %rax
	subq	%fs:40, %rax
	je	.L37
	call	__stack_chk_fail@PLT
.L37:
	addq	$216, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2045:
	.size	_Z60__device_stub__Z22conv_scale_rfwd_kernelPKfjjjS0_S0_S0_S0_PfPKfjjjS0_S0_S0_S0_Pf, .-_Z60__device_stub__Z22conv_scale_rfwd_kernelPKfjjjS0_S0_S0_S0_PfPKfjjjS0_S0_S0_S0_Pf
	.globl	_Z22conv_scale_rfwd_kernelPKfjjjS0_S0_S0_S0_Pf
	.type	_Z22conv_scale_rfwd_kernelPKfjjjS0_S0_S0_S0_Pf, @function
_Z22conv_scale_rfwd_kernelPKfjjjS0_S0_S0_S0_Pf:
.LFB2046:
	.cfi_startproc
	endbr64
	jmp	_Z60__device_stub__Z22conv_scale_rfwd_kernelPKfjjjS0_S0_S0_S0_PfPKfjjjS0_S0_S0_S0_Pf
	.cfi_endproc
.LFE2046:
	.size	_Z22conv_scale_rfwd_kernelPKfjjjS0_S0_S0_S0_Pf, .-_Z22conv_scale_rfwd_kernelPKfjjjS0_S0_S0_S0_Pf
	.globl	neuralops_cuda_conv_scale_rfwd
	.type	neuralops_cuda_conv_scale_rfwd, @function
neuralops_cuda_conv_scale_rfwd:
.LFB2012:
	.cfi_startproc
	endbr64
	movabsq	$4294967297, %rax
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	movl	%ecx, %r14d
	imull	%edx, %ecx
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movl	%edx, %r13d
	movl	$4194305, %edx
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movl	%esi, %r12d
	salq	$10, %rdx
	imull	%esi, %ecx
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	addl	$1023, %ecx
	subq	$72, %rsp
	.cfi_def_cfa_offset 128
	shrl	$10, %ecx
	movl	%ecx, 40(%rsp)
	movl	$1, %ecx
	movq	128(%rsp), %r15
	movq	%rax, 44(%rsp)
	movl	48(%rsp), %esi
	movq	%rdi, 8(%rsp)
	movq	40(%rsp), %rdi
	movq	%r9, 24(%rsp)
	movq	152(%rsp), %r9
	movq	%r8, 16(%rsp)
	xorl	%r8d, %r8d
	movq	136(%rsp), %rbx
	movq	144(%rsp), %rbp
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L40
	movq	24(%rsp), %r9
	movq	16(%rsp), %r8
	movl	%r14d, %ecx
	movl	%r13d, %edx
	movq	%rbp, 144(%rsp)
	movq	8(%rsp), %rdi
	movl	%r12d, %esi
	movq	%rbx, 136(%rsp)
	movq	%r15, 128(%rsp)
	addq	$72, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	_Z60__device_stub__Z22conv_scale_rfwd_kernelPKfjjjS0_S0_S0_S0_PfPKfjjjS0_S0_S0_S0_Pf
.L40:
	.cfi_restore_state
	addq	$72, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2012:
	.size	neuralops_cuda_conv_scale_rfwd, .-neuralops_cuda_conv_scale_rfwd
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z22conv_scale_rfwd_kernelPKfjjjS0_S0_S0_S0_Pf"
.LC1:
	.string	"_Z33conv_diag_affine_bwd_batch_kernelPKfiiiS0_S0_PfS1_S1_"
.LC2:
	.string	"_Z33conv_diag_affine_fwd_batch_kernelPKfiiiS0_S0_Pf"
.LC3:
	.string	"_Z17col2im_gpu_kerneliPKfiiiiiiiiiiiiiPf"
.LC4:
	.string	"_Z17im2col_gpu_kerneliPKfiiiiiiiiiiiiPf"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2048:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z22conv_scale_rfwd_kernelPKfjjjS0_S0_S0_S0_Pf(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC1(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z33conv_diag_affine_bwd_batch_kernelPKfiiiS0_S0_PfS1_S1_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC2(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z33conv_diag_affine_fwd_batch_kernelPKfiiiS0_S0_Pf(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC3(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z17col2im_gpu_kerneliPKfiiiiiiiiiiiiiPf(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC4(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z17im2col_gpu_kerneliPKfiiiiiiiiiiiiPf(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2048:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include <hip/hip_runtime_api.h>
#include <stdint.h>

#define OFFSET_BANK(idx) ({ __typeof__ (idx) _idx = idx; ((_idx) + ((_idx) / 32)); })

__global__ void im2col_gpu_kernel(
    const int n,
    const float* data_im,
    const int height, const int width,
    const int kernel_h, const int kernel_w,
    const int pad_h, const int pad_w,
    const int stride_h, const int stride_w,
    const int dilation_h, const int dilation_w,
    const int height_col, const int width_col,
    float* data_col)
{
  int index = threadIdx.x + blockDim.x * blockIdx.x;
  if (index < n) {
    const int h_index = index / width_col;
    const int h_col = h_index % height_col;
    const int w_col = index % width_col;
    const int c_im = h_index / height_col;
    const int c_col = c_im * kernel_h * kernel_w;
    const int h_offset = h_col * stride_h - pad_h;
    const int w_offset = w_col * stride_w - pad_w;
    float* data_col_ptr = data_col;
    data_col_ptr += (c_col * height_col + h_col) * width_col + w_col;
    const float* data_im_ptr = data_im;
    data_im_ptr += (c_im * height + h_offset) * width + w_offset;
    for (int i = 0; i < kernel_h; ++i) {
      for (int j = 0; j < kernel_w; ++j) {
        int h_im = h_offset + i * dilation_h;
        int w_im = w_offset + j * dilation_w;
        *data_col_ptr =
            (h_im >= 0 && w_im >= 0 && h_im < height && w_im < width) ?
            data_im_ptr[i * dilation_h * width + j * dilation_w] : 0;
        data_col_ptr += height_col * width_col;
      }
    }
  }
}

extern "C" void neuralops_cuda_caffe_im2col(
    const float* data_im,
    const int channels,
    const int height, const int width,
    const int kernel_h, const int kernel_w,
    const int pad_h, const int pad_w,
    const int stride_h, const int stride_w,
    const int dilation_h, const int dilation_w,
    float* data_col,
    hipStream_t stream)
{
  // We are going to launch channels * height_col * width_col kernels, each
  // kernel responsible for copying a single-channel grid.
  int height_col = (height + 2 * pad_h -
      (dilation_h * (kernel_h - 1) + 1)) / stride_h + 1;
  int width_col = (width + 2 * pad_w -
      (dilation_w * (kernel_w - 1) + 1)) / stride_w + 1;
  int num_kernels = channels * height_col * width_col;
  // NOLINT_NEXT_LINE(whitespace/operators)
  im2col_gpu_kernel<<<(num_kernels+1024-1)/1024, 1024, 0, stream>>>(
      num_kernels, data_im, height, width, kernel_h, kernel_w, pad_h,
      pad_w, stride_h, stride_w, dilation_h, dilation_w, height_col,
      width_col, data_col);
}

__global__ void col2im_gpu_kernel(
    const int n,
    const float* data_col,
    const int height, const int width, const int channels,
    const int kernel_h, const int kernel_w,
    const int pad_h, const int pad_w,
    const int stride_h, const int stride_w,
    const int dilation_h, const int dilation_w,
    const int height_col, const int width_col,
    float* data_im)
{
  int index = threadIdx.x + blockDim.x * blockIdx.x;
  if (index < n) {
    float val = 0;
    const int w_im = index % width + pad_w;
    const int h_im = (index / width) % height + pad_h;
    const int c_im = index / (width * height);
    int kernel_extent_w = (kernel_w - 1) * dilation_w + 1;
    int kernel_extent_h = (kernel_h - 1) * dilation_h + 1;
    // compute the start and end of the output
    const int w_col_start =
        (w_im < kernel_extent_w) ? 0 : (w_im - kernel_extent_w) / stride_w + 1;
    const int w_col_end = min(w_im / stride_w + 1, width_col);
    const int h_col_start =
        (h_im < kernel_extent_h) ? 0 : (h_im - kernel_extent_h) / stride_h + 1;
    const int h_col_end = min(h_im / stride_h + 1, height_col);
    // TODO: use LCM of stride and dilation to avoid unnecessary loops
    for (int h_col = h_col_start; h_col < h_col_end; h_col += 1) {
      for (int w_col = w_col_start; w_col < w_col_end; w_col += 1) {
        int h_k = (h_im - h_col * stride_h);
        int w_k = (w_im - w_col * stride_w);
        if (h_k % dilation_h == 0 && w_k % dilation_w == 0) {
          h_k /= dilation_h;
          w_k /= dilation_w;
          int data_col_index = (((c_im * kernel_h + h_k) * kernel_w + w_k) *
                                height_col + h_col) * width_col + w_col;
          val += data_col[data_col_index];
        }
      }
    }
    data_im[index] = val;
  }
}

extern "C" void neuralops_cuda_caffe_col2im(
    const float* data_col,
    const int channels,
    const int height, const int width,
    const int kernel_h, const int kernel_w,
    const int pad_h, const int pad_w,
    const int stride_h, const int stride_w,
    const int dilation_h, const int dilation_w,
    float* data_im,
    hipStream_t stream)
{
  int height_col = (height + 2 * pad_h - (dilation_h * (kernel_h - 1) + 1)) /
      stride_h + 1;
  int width_col = (width + 2 * pad_w - (dilation_w * (kernel_w - 1) + 1)) /
      stride_w + 1;
  int num_kernels = channels * height * width;
  // To avoid involving atomic operations, we will launch one kernel per
  // bottom dimension, and then in the kernel add up the top dimensions.
  // NOLINT_NEXT_LINE(whitespace/operators)
  col2im_gpu_kernel<<<(num_kernels+1024-1)/1024, 1024, 0, stream>>>(
      num_kernels, data_col, height, width, channels, kernel_h, kernel_w,
      pad_h, pad_w, stride_h, stride_w, dilation_h, dilation_w,
      height_col, width_col, data_im);
}

__global__ void conv_diag_affine_fwd_batch_kernel(
    const float *in_act,
    int spatial_dim,
    int num_channels,
    int batch_size,
    const float *scale,
    const float *bias,
    float *out_act)
{
  int idx = threadIdx.x + blockIdx.x * blockDim.x;
  int u = idx % spatial_dim;
  int c = (idx / spatial_dim) % num_channels;
  int batch_idx = idx / (spatial_dim * num_channels);
  if (u < spatial_dim && c < num_channels && batch_idx < batch_size) {
    float gamma = scale[c];
    float beta = bias[c];
    float y = gamma * in_act[idx] + beta;
    out_act[idx] = y;
  }
}

extern "C" void neuralops_cuda_conv2d_scale_fwd(
    const float *in_act,
    size_t spatial_dim,
    size_t num_channels,
    size_t batch_size,
    const float *scale,
    const float *bias,
    float *out_act,
    hipStream_t stream)
{
  int n = spatial_dim * num_channels * batch_size;
  conv_diag_affine_fwd_batch_kernel<<<(n+1024-1)/1024, 1024, 0, stream>>>(
      in_act, spatial_dim, num_channels, batch_size, scale, bias, out_act);
}

__global__ void conv_diag_affine_bwd_batch_kernel(
    const float *in_act,
    int spatial_dim,
    int num_channels,
    int batch_size,
    const float *out_delta,
    const float *scale,
    float *scale_grad,
    float *bias_grad,
    float *in_delta)
{
  __shared__ float scale_grad_cache[1024+32];
  __shared__ float bias_grad_cache[1024+32];
  int idx = threadIdx.x + blockIdx.x * blockDim.x;
  int bank_idx = OFFSET_BANK(threadIdx.x);
  int block_spatial_dim = (spatial_dim+16*32-1)/(16*32);
  int warp_idx = idx % 32;
  int c = (idx / 32) % num_channels;
  int u0 = warp_idx + ((idx / (32 * num_channels)) % block_spatial_dim) * (16*32);
  int batch_idx = idx / (32 * num_channels * block_spatial_dim);
  if (c < num_channels && u0 < spatial_dim && batch_idx < batch_size) {
    float gamma = scale[c];
    float d_gamma = 0.0f;
    float d_beta = 0.0f;
    int i0 = c * spatial_dim + batch_idx * spatial_dim * num_channels;
    int u_limit = min(spatial_dim, u0 + 16*32);
    for (int u = u0; u < u_limit; u += 32) {
      int i = i0 + u;
      float dy = out_delta[i];
      d_gamma += dy * in_act[i];
      d_beta += dy;
      in_delta[i] = dy * gamma;
      //in_delta[i] += dy * gamma;
      //atomicAdd(&in_delta[i], dy * gamma);
    }
    scale_grad_cache[bank_idx] = d_gamma;
    bias_grad_cache[bank_idx] = d_beta;
  } else {
    scale_grad_cache[bank_idx] = 0.0f;
    bias_grad_cache[bank_idx] = 0.0f;
  }
  __syncthreads();
  if (c < num_channels && batch_idx < batch_size) {
    if (threadIdx.x % 2 == 0) {
      scale_grad_cache[bank_idx] += scale_grad_cache[bank_idx+1];
      bias_grad_cache[bank_idx] += bias_grad_cache[bank_idx+1];
    }
  }
  __syncthreads();
  if (c < num_channels && batch_idx < batch_size) {
    if (threadIdx.x % 4 == 0) {
      scale_grad_cache[bank_idx] += scale_grad_cache[bank_idx+2];
      bias_grad_cache[bank_idx] += bias_grad_cache[bank_idx+2];
    }
  }
  __syncthreads();
  if (c < num_channels && batch_idx < batch_size) {
    if (threadIdx.x % 8 == 0) {
      scale_grad_cache[bank_idx] += scale_grad_cache[bank_idx+4];
      bias_grad_cache[bank_idx] += bias_grad_cache[bank_idx+4];
    }
  }
  __syncthreads();
  if (c < num_channels && batch_idx < batch_size) {
    if (threadIdx.x % 16 == 0) {
      scale_grad_cache[bank_idx] += scale_grad_cache[bank_idx+8];
      bias_grad_cache[bank_idx] += bias_grad_cache[bank_idx+8];
    }
  }
  __syncthreads();
  if (c < num_channels && batch_idx < batch_size) {
    if (threadIdx.x % 32 == 0 && u0 < spatial_dim) {
      float d_gamma = scale_grad_cache[bank_idx] + scale_grad_cache[bank_idx+16];
      atomicAdd(&scale_grad[c], d_gamma);
      float d_beta = bias_grad_cache[bank_idx] + bias_grad_cache[bank_idx+16];
      atomicAdd(&bias_grad[c], d_beta);
    }
  }
}

extern "C" void neuralops_cuda_conv2d_scale_bwd(
    const float *in_act,
    size_t spatial_dim,
    size_t num_channels,
    size_t batch_size,
    const float *out_delta,
    const float *scale,
    float *scale_grad,
    float *bias_grad,
    float *in_delta,
    hipStream_t stream)
{
  int block_spatial_dim = (spatial_dim+16*32-1)/(16*32);
  int n = 32 * num_channels * block_spatial_dim * batch_size;
  conv_diag_affine_bwd_batch_kernel<<<(n+1024-1)/1024, 1024, 0, stream>>>(
      in_act, spatial_dim, num_channels, batch_size, out_delta, scale, scale_grad, bias_grad, in_delta);
}

__global__ void conv_scale_rfwd_kernel(
    const float *in_val,
    uint32_t spatial_dim,
    uint32_t num_channels,
    uint32_t batch_size,
    const float *in_r_val,
    const float *scale,
    const float *scale_r_dir,
    const float *bias_r_dir,
    float *out_r_val)
{
  uint32_t idx = threadIdx.x + blockIdx.x * blockDim.x;
  uint32_t u = idx % spatial_dim;
  uint32_t c = (idx / spatial_dim) % num_channels;
  uint32_t batch_idx = idx / (spatial_dim * num_channels);
  if (u < spatial_dim && c < num_channels && batch_idx < batch_size) {
    float alpha = scale[c];
    float r_alpha = scale_r_dir[c];
    float r_beta = bias_r_dir[c];
    float r_y = alpha * in_r_val[idx] + r_alpha * in_val[idx] + r_beta;
    out_r_val[idx] = r_y;
  }
}

extern "C" void neuralops_cuda_conv_scale_rfwd(
    const float *in_val,
    size_t spatial_dim,
    size_t num_channels,
    size_t batch_size,
    const float *in_r_val,
    const float *scale,
    const float *scale_r_dir,
    const float *bias_r_dir,
    float *out_r_val,
    hipStream_t stream)
{
  uint32_t n = spatial_dim * num_channels * batch_size;
  conv_scale_rfwd_kernel<<<(n+1024-1)/1024, 1024, 0, stream>>>(
      in_val, spatial_dim, num_channels, batch_size, in_r_val, scale, scale_r_dir, bias_r_dir, out_r_val);
}

	.text
	.file	"conv.hip"
	.globl	_Z32__device_stub__im2col_gpu_kerneliPKfiiiiiiiiiiiiPf # -- Begin function _Z32__device_stub__im2col_gpu_kerneliPKfiiiiiiiiiiiiPf
	.type	_Z32__device_stub__im2col_gpu_kerneliPKfiiiiiiiiiiiiPf,@function
_Z32__device_stub__im2col_gpu_kerneliPKfiiiiiiiiiiiiPf: # @_Z32__device_stub__im2col_gpu_kerneliPKfiiiiiiiiiiiiPf
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$208, %rsp
	.cfi_def_cfa_offset 256
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	20(%rsp), %rax
	movl	%edi, (%rax)
	leaq	40(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	16(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	12(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	8(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	4(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	256(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	264(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	272(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	280(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	288(%rsp), %rax
	movq	%rax, 80(%rbx)
	leaq	296(%rsp), %rax
	movq	%rax, 88(%rbx)
	leaq	304(%rsp), %rax
	movq	%rax, 96(%rbx)
	leaq	312(%rsp), %rax
	movq	%rax, 104(%rbx)
	leaq	320(%rsp), %rax
	movq	%rax, 112(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z17im2col_gpu_kerneliPKfiiiiiiiiiiiiPf, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$224, %rsp
	.cfi_adjust_cfa_offset -224
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z32__device_stub__im2col_gpu_kerneliPKfiiiiiiiiiiiiPf, .Lfunc_end0-_Z32__device_stub__im2col_gpu_kerneliPKfiiiiiiiiiiiiPf
	.cfi_endproc
                                        # -- End function
	.globl	neuralops_cuda_caffe_im2col     # -- Begin function neuralops_cuda_caffe_im2col
	.type	neuralops_cuda_caffe_im2col,@function
neuralops_cuda_caffe_im2col:            # @neuralops_cuda_caffe_im2col
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$24, %rsp
	.cfi_def_cfa_offset 80
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
                                        # kill: def $r9d killed $r9d def $r9
	movl	%r8d, %r14d
	movl	%ecx, %r15d
	movl	%edx, %r12d
	movl	%esi, %ebp
	movq	%rdi, 8(%rsp)                   # 8-byte Spill
	movl	120(%rsp), %r10d
	movl	112(%rsp), %edx
	movl	104(%rsp), %r8d
	movl	96(%rsp), %edi
	movl	88(%rsp), %esi
	movl	80(%rsp), %eax
	leal	(%r12,%rax,2), %ecx
	leal	-1(%r14), %eax
	imull	%edx, %eax
	notl	%eax
	addl	%ecx, %eax
	cltd
	idivl	%edi
	movl	%eax, %r13d
	incl	%r13d
	leal	(%r15,%rsi,2), %ecx
	movq	%r9, 16(%rsp)                   # 8-byte Spill
	leal	-1(%r9), %eax
	imull	%r10d, %eax
	notl	%eax
	addl	%ecx, %eax
	cltd
	idivl	%r8d
	movl	%eax, %ebx
	incl	%ebx
	imull	%r13d, %ebp
	imull	%ebx, %ebp
	leal	1023(%rbp), %eax
	testl	%eax, %eax
	leal	2046(%rbp), %edi
	cmovnsl	%eax, %edi
	sarl	$10, %edi
	btsq	$32, %rdi
	movabsq	$4294967296, %rdx               # imm = 0x100000000
	orq	$1024, %rdx                     # imm = 0x400
	movq	136(%rsp), %r9
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	je	.LBB1_1
# %bb.2:
	addq	$24, %rsp
	.cfi_def_cfa_offset 56
	jmp	.LBB1_3
.LBB1_1:
	.cfi_def_cfa_offset 80
	subq	$8, %rsp
	.cfi_adjust_cfa_offset 8
	movl	%ebp, %edi
	movq	16(%rsp), %rsi                  # 8-byte Reload
	movl	%r12d, %edx
	movl	%r15d, %ecx
	movl	%r14d, %r8d
	movq	24(%rsp), %r9                   # 8-byte Reload
                                        # kill: def $r9d killed $r9d killed $r9
	pushq	136(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	%rbx
	.cfi_adjust_cfa_offset 8
	pushq	%r13
	.cfi_adjust_cfa_offset 8
	movl	152(%rsp), %eax
	pushq	%rax
	.cfi_adjust_cfa_offset 8
	movl	152(%rsp), %eax
	pushq	%rax
	.cfi_adjust_cfa_offset 8
	movl	152(%rsp), %eax
	pushq	%rax
	.cfi_adjust_cfa_offset 8
	movl	152(%rsp), %eax
	pushq	%rax
	.cfi_adjust_cfa_offset 8
	movl	152(%rsp), %eax
	pushq	%rax
	.cfi_adjust_cfa_offset 8
	movl	152(%rsp), %eax
	pushq	%rax
	.cfi_adjust_cfa_offset 8
	callq	_Z32__device_stub__im2col_gpu_kerneliPKfiiiiiiiiiiiiPf
	addq	$104, %rsp
	.cfi_adjust_cfa_offset -104
.LBB1_3:
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	neuralops_cuda_caffe_im2col, .Lfunc_end1-neuralops_cuda_caffe_im2col
	.cfi_endproc
                                        # -- End function
	.globl	_Z32__device_stub__col2im_gpu_kerneliPKfiiiiiiiiiiiiiPf # -- Begin function _Z32__device_stub__col2im_gpu_kerneliPKfiiiiiiiiiiiiiPf
	.type	_Z32__device_stub__col2im_gpu_kerneliPKfiiiiiiiiiiiiiPf,@function
_Z32__device_stub__col2im_gpu_kerneliPKfiiiiiiiiiiiiiPf: # @_Z32__device_stub__col2im_gpu_kerneliPKfiiiiiiiiiiiiiPf
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$208, %rsp
	.cfi_def_cfa_offset 256
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	20(%rsp), %rax
	movl	%edi, (%rax)
	leaq	40(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	16(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	12(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	8(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	4(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	256(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	264(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	272(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	280(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	288(%rsp), %rax
	movq	%rax, 80(%rbx)
	leaq	296(%rsp), %rax
	movq	%rax, 88(%rbx)
	leaq	304(%rsp), %rax
	movq	%rax, 96(%rbx)
	leaq	312(%rsp), %rax
	movq	%rax, 104(%rbx)
	leaq	320(%rsp), %rax
	movq	%rax, 112(%rbx)
	leaq	328(%rsp), %rax
	movq	%rax, 120(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z17col2im_gpu_kerneliPKfiiiiiiiiiiiiiPf, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$224, %rsp
	.cfi_adjust_cfa_offset -224
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z32__device_stub__col2im_gpu_kerneliPKfiiiiiiiiiiiiiPf, .Lfunc_end2-_Z32__device_stub__col2im_gpu_kerneliPKfiiiiiiiiiiiiiPf
	.cfi_endproc
                                        # -- End function
	.globl	neuralops_cuda_caffe_col2im     # -- Begin function neuralops_cuda_caffe_col2im
	.type	neuralops_cuda_caffe_col2im,@function
neuralops_cuda_caffe_col2im:            # @neuralops_cuda_caffe_col2im
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	pushq	%rax
	.cfi_def_cfa_offset 64
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%r9d, %r13d
	movl	%r8d, %r14d
	movl	%ecx, %r15d
	movl	%edx, %ebx
	movl	%esi, %ebp
	movq	%rdi, (%rsp)                    # 8-byte Spill
	movq	120(%rsp), %r9
	movl	%edx, %r12d
	imull	%esi, %r12d
	imull	%ecx, %r12d
	leal	1023(%r12), %eax
	leal	2046(%r12), %edi
	testl	%eax, %eax
	cmovnsl	%eax, %edi
	sarl	$10, %edi
	btsq	$32, %rdi
	movabsq	$4294967296, %rdx               # imm = 0x100000000
	orq	$1024, %rdx                     # imm = 0x400
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	je	.LBB3_1
# %bb.2:
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	jmp	.LBB3_3
.LBB3_1:
	.cfi_def_cfa_offset 64
	movl	104(%rsp), %edx
	movl	96(%rsp), %r9d
	movl	88(%rsp), %r8d
	movl	80(%rsp), %r11d
	movl	72(%rsp), %eax
	movl	64(%rsp), %esi
	leal	(%r15,%rax,2), %ecx
	leal	-1(%r13), %eax
	imull	%edx, %eax
	notl	%eax
	addl	%ecx, %eax
	cltd
	idivl	%r8d
	movl	%eax, %r10d
	incl	%r10d
	leal	(%rbx,%rsi,2), %ecx
	leal	-1(%r14), %eax
	imull	%r9d, %eax
	notl	%eax
	addl	%ecx, %eax
	cltd
	idivl	%r11d
                                        # kill: def $eax killed $eax def $rax
	incl	%eax
	movl	%r12d, %edi
	movq	(%rsp), %rsi                    # 8-byte Reload
	movl	%ebx, %edx
	movl	%r15d, %ecx
	movl	%ebp, %r8d
	movl	%r14d, %r9d
	pushq	112(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	%r10
	.cfi_adjust_cfa_offset 8
	pushq	%rax
	.cfi_adjust_cfa_offset 8
	movl	128(%rsp), %eax
	pushq	%rax
	.cfi_adjust_cfa_offset 8
	movl	128(%rsp), %eax
	pushq	%rax
	.cfi_adjust_cfa_offset 8
	movl	128(%rsp), %eax
	pushq	%rax
	.cfi_adjust_cfa_offset 8
	pushq	%r11
	.cfi_adjust_cfa_offset 8
	movl	128(%rsp), %eax
	pushq	%rax
	.cfi_adjust_cfa_offset 8
	movl	128(%rsp), %eax
	pushq	%rax
	.cfi_adjust_cfa_offset 8
	pushq	%r13
	.cfi_adjust_cfa_offset 8
	callq	_Z32__device_stub__col2im_gpu_kerneliPKfiiiiiiiiiiiiiPf
	addq	$88, %rsp
	.cfi_adjust_cfa_offset -88
.LBB3_3:
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	neuralops_cuda_caffe_col2im, .Lfunc_end3-neuralops_cuda_caffe_col2im
	.cfi_endproc
                                        # -- End function
	.globl	_Z48__device_stub__conv_diag_affine_fwd_batch_kernelPKfiiiS0_S0_Pf # -- Begin function _Z48__device_stub__conv_diag_affine_fwd_batch_kernelPKfiiiS0_S0_Pf
	.type	_Z48__device_stub__conv_diag_affine_fwd_batch_kernelPKfiiiS0_S0_Pf,@function
_Z48__device_stub__conv_diag_affine_fwd_batch_kernelPKfiiiS0_S0_Pf: # @_Z48__device_stub__conv_diag_affine_fwd_batch_kernelPKfiiiS0_S0_Pf
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	20(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	16(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	12(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	48(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	40(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z33conv_diag_affine_fwd_batch_kernelPKfiiiS0_S0_Pf, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end4:
	.size	_Z48__device_stub__conv_diag_affine_fwd_batch_kernelPKfiiiS0_S0_Pf, .Lfunc_end4-_Z48__device_stub__conv_diag_affine_fwd_batch_kernelPKfiiiS0_S0_Pf
	.cfi_endproc
                                        # -- End function
	.globl	neuralops_cuda_conv2d_scale_fwd # -- Begin function neuralops_cuda_conv2d_scale_fwd
	.type	neuralops_cuda_conv2d_scale_fwd,@function
neuralops_cuda_conv2d_scale_fwd:        # @neuralops_cuda_conv2d_scale_fwd
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	pushq	%rax
	.cfi_def_cfa_offset 64
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%r9, %rbx
	movq	%r8, %r14
	movq	%rcx, %r15
	movq	%rdx, %r12
	movq	%rsi, %r13
	movq	%rdi, %rbp
	movq	72(%rsp), %r9
	movl	%r12d, %eax
	imull	%r13d, %eax
	movl	%r15d, %edi
	imull	%eax, %edi
	leal	1023(%rdi), %eax
	addl	$2046, %edi                     # imm = 0x7FE
	testl	%eax, %eax
	cmovnsl	%eax, %edi
	sarl	$10, %edi
	btsq	$32, %rdi
	movabsq	$4294967296, %rdx               # imm = 0x100000000
	orq	$1024, %rdx                     # imm = 0x400
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	je	.LBB5_2
# %bb.1:
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB5_2:
	.cfi_def_cfa_offset 64
	movq	%rbp, %rdi
	movl	%r13d, %esi
	movl	%r12d, %edx
	movl	%r15d, %ecx
	movq	%r14, %r8
	movq	%rbx, %r9
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z48__device_stub__conv_diag_affine_fwd_batch_kernelPKfiiiS0_S0_Pf # TAILCALL
.Lfunc_end5:
	.size	neuralops_cuda_conv2d_scale_fwd, .Lfunc_end5-neuralops_cuda_conv2d_scale_fwd
	.cfi_endproc
                                        # -- End function
	.globl	_Z48__device_stub__conv_diag_affine_bwd_batch_kernelPKfiiiS0_S0_PfS1_S1_ # -- Begin function _Z48__device_stub__conv_diag_affine_bwd_batch_kernelPKfiiiS0_S0_PfS1_S1_
	.type	_Z48__device_stub__conv_diag_affine_bwd_batch_kernelPKfiiiS0_S0_PfS1_S1_,@function
_Z48__device_stub__conv_diag_affine_bwd_batch_kernelPKfiiiS0_S0_PfS1_S1_: # @_Z48__device_stub__conv_diag_affine_bwd_batch_kernelPKfiiiS0_S0_PfS1_S1_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$176, %rsp
	.cfi_def_cfa_offset 224
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	20(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	16(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	12(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	48(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	40(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	224(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	232(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	240(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z33conv_diag_affine_bwd_batch_kernelPKfiiiS0_S0_PfS1_S1_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$192, %rsp
	.cfi_adjust_cfa_offset -192
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end6:
	.size	_Z48__device_stub__conv_diag_affine_bwd_batch_kernelPKfiiiS0_S0_PfS1_S1_, .Lfunc_end6-_Z48__device_stub__conv_diag_affine_bwd_batch_kernelPKfiiiS0_S0_PfS1_S1_
	.cfi_endproc
                                        # -- End function
	.globl	neuralops_cuda_conv2d_scale_bwd # -- Begin function neuralops_cuda_conv2d_scale_bwd
	.type	neuralops_cuda_conv2d_scale_bwd,@function
neuralops_cuda_conv2d_scale_bwd:        # @neuralops_cuda_conv2d_scale_bwd
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	pushq	%rax
	.cfi_def_cfa_offset 64
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%r9, %rbx
	movq	%r8, %r14
	movq	%rcx, %r15
	movq	%rdx, %r12
	movq	%rsi, %r13
	movq	%rdi, %rbp
	movq	%rsi, %rax
	shlq	$23, %rax
	movl	$4286578688, %edx               # imm = 0xFF800000
	addq	%rdx, %rax
	shrq	$32, %rax
	imull	%r12d, %ecx
	imull	%ecx, %eax
	shll	$5, %eax
	leal	1023(%rax), %ecx
	addl	$2046, %eax                     # imm = 0x7FE
	testl	%ecx, %ecx
	cmovnsl	%ecx, %eax
	movq	88(%rsp), %r9
	sarl	$10, %eax
	leaq	(%rax,%rdx), %rdi
	addq	$8388608, %rdi                  # imm = 0x800000
	addq	$8389632, %rdx                  # imm = 0x800400
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	je	.LBB7_2
# %bb.1:
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB7_2:
	.cfi_def_cfa_offset 64
	movq	%rbp, %rdi
	movl	%r13d, %esi
	movl	%r12d, %edx
	movl	%r15d, %ecx
	movq	%r14, %r8
	movq	%rbx, %r9
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z48__device_stub__conv_diag_affine_bwd_batch_kernelPKfiiiS0_S0_PfS1_S1_ # TAILCALL
.Lfunc_end7:
	.size	neuralops_cuda_conv2d_scale_bwd, .Lfunc_end7-neuralops_cuda_conv2d_scale_bwd
	.cfi_endproc
                                        # -- End function
	.globl	_Z37__device_stub__conv_scale_rfwd_kernelPKfjjjS0_S0_S0_S0_Pf # -- Begin function _Z37__device_stub__conv_scale_rfwd_kernelPKfjjjS0_S0_S0_S0_Pf
	.type	_Z37__device_stub__conv_scale_rfwd_kernelPKfjjjS0_S0_S0_S0_Pf,@function
_Z37__device_stub__conv_scale_rfwd_kernelPKfjjjS0_S0_S0_S0_Pf: # @_Z37__device_stub__conv_scale_rfwd_kernelPKfjjjS0_S0_S0_S0_Pf
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$176, %rsp
	.cfi_def_cfa_offset 224
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	20(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	16(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	12(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	48(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	40(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	224(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	232(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	240(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z22conv_scale_rfwd_kernelPKfjjjS0_S0_S0_S0_Pf, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$192, %rsp
	.cfi_adjust_cfa_offset -192
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end8:
	.size	_Z37__device_stub__conv_scale_rfwd_kernelPKfjjjS0_S0_S0_S0_Pf, .Lfunc_end8-_Z37__device_stub__conv_scale_rfwd_kernelPKfjjjS0_S0_S0_S0_Pf
	.cfi_endproc
                                        # -- End function
	.globl	neuralops_cuda_conv_scale_rfwd  # -- Begin function neuralops_cuda_conv_scale_rfwd
	.type	neuralops_cuda_conv_scale_rfwd,@function
neuralops_cuda_conv_scale_rfwd:         # @neuralops_cuda_conv_scale_rfwd
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	pushq	%rax
	.cfi_def_cfa_offset 64
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%r9, %rbx
	movq	%r8, %r14
	movq	%rcx, %r15
	movq	%rdx, %r12
	movq	%rsi, %r13
	movq	%rdi, %rbp
	movq	88(%rsp), %r9
	movl	%r12d, %eax
	imull	%r13d, %eax
	movl	%r15d, %edi
	imull	%eax, %edi
	addl	$1023, %edi                     # imm = 0x3FF
	shrl	$10, %edi
	btsq	$32, %rdi
	movabsq	$4294967296, %rdx               # imm = 0x100000000
	orq	$1024, %rdx                     # imm = 0x400
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	je	.LBB9_2
# %bb.1:
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB9_2:
	.cfi_def_cfa_offset 64
	movq	%rbp, %rdi
	movl	%r13d, %esi
	movl	%r12d, %edx
	movl	%r15d, %ecx
	movq	%r14, %r8
	movq	%rbx, %r9
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z37__device_stub__conv_scale_rfwd_kernelPKfjjjS0_S0_S0_S0_Pf # TAILCALL
.Lfunc_end9:
	.size	neuralops_cuda_conv_scale_rfwd, .Lfunc_end9-neuralops_cuda_conv_scale_rfwd
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB10_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB10_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z17im2col_gpu_kerneliPKfiiiiiiiiiiiiPf, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z17col2im_gpu_kerneliPKfiiiiiiiiiiiiiPf, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z33conv_diag_affine_fwd_batch_kernelPKfiiiS0_S0_Pf, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z33conv_diag_affine_bwd_batch_kernelPKfiiiS0_S0_PfS1_S1_, %esi
	movl	$.L__unnamed_4, %edx
	movl	$.L__unnamed_4, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z22conv_scale_rfwd_kernelPKfjjjS0_S0_S0_S0_Pf, %esi
	movl	$.L__unnamed_5, %edx
	movl	$.L__unnamed_5, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end10:
	.size	__hip_module_ctor, .Lfunc_end10-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB11_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB11_2:
	retq
.Lfunc_end11:
	.size	__hip_module_dtor, .Lfunc_end11-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z17im2col_gpu_kerneliPKfiiiiiiiiiiiiPf,@object # @_Z17im2col_gpu_kerneliPKfiiiiiiiiiiiiPf
	.section	.rodata,"a",@progbits
	.globl	_Z17im2col_gpu_kerneliPKfiiiiiiiiiiiiPf
	.p2align	3, 0x0
_Z17im2col_gpu_kerneliPKfiiiiiiiiiiiiPf:
	.quad	_Z32__device_stub__im2col_gpu_kerneliPKfiiiiiiiiiiiiPf
	.size	_Z17im2col_gpu_kerneliPKfiiiiiiiiiiiiPf, 8

	.type	_Z17col2im_gpu_kerneliPKfiiiiiiiiiiiiiPf,@object # @_Z17col2im_gpu_kerneliPKfiiiiiiiiiiiiiPf
	.globl	_Z17col2im_gpu_kerneliPKfiiiiiiiiiiiiiPf
	.p2align	3, 0x0
_Z17col2im_gpu_kerneliPKfiiiiiiiiiiiiiPf:
	.quad	_Z32__device_stub__col2im_gpu_kerneliPKfiiiiiiiiiiiiiPf
	.size	_Z17col2im_gpu_kerneliPKfiiiiiiiiiiiiiPf, 8

	.type	_Z33conv_diag_affine_fwd_batch_kernelPKfiiiS0_S0_Pf,@object # @_Z33conv_diag_affine_fwd_batch_kernelPKfiiiS0_S0_Pf
	.globl	_Z33conv_diag_affine_fwd_batch_kernelPKfiiiS0_S0_Pf
	.p2align	3, 0x0
_Z33conv_diag_affine_fwd_batch_kernelPKfiiiS0_S0_Pf:
	.quad	_Z48__device_stub__conv_diag_affine_fwd_batch_kernelPKfiiiS0_S0_Pf
	.size	_Z33conv_diag_affine_fwd_batch_kernelPKfiiiS0_S0_Pf, 8

	.type	_Z33conv_diag_affine_bwd_batch_kernelPKfiiiS0_S0_PfS1_S1_,@object # @_Z33conv_diag_affine_bwd_batch_kernelPKfiiiS0_S0_PfS1_S1_
	.globl	_Z33conv_diag_affine_bwd_batch_kernelPKfiiiS0_S0_PfS1_S1_
	.p2align	3, 0x0
_Z33conv_diag_affine_bwd_batch_kernelPKfiiiS0_S0_PfS1_S1_:
	.quad	_Z48__device_stub__conv_diag_affine_bwd_batch_kernelPKfiiiS0_S0_PfS1_S1_
	.size	_Z33conv_diag_affine_bwd_batch_kernelPKfiiiS0_S0_PfS1_S1_, 8

	.type	_Z22conv_scale_rfwd_kernelPKfjjjS0_S0_S0_S0_Pf,@object # @_Z22conv_scale_rfwd_kernelPKfjjjS0_S0_S0_S0_Pf
	.globl	_Z22conv_scale_rfwd_kernelPKfjjjS0_S0_S0_S0_Pf
	.p2align	3, 0x0
_Z22conv_scale_rfwd_kernelPKfjjjS0_S0_S0_S0_Pf:
	.quad	_Z37__device_stub__conv_scale_rfwd_kernelPKfjjjS0_S0_S0_S0_Pf
	.size	_Z22conv_scale_rfwd_kernelPKfjjjS0_S0_S0_S0_Pf, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z17im2col_gpu_kerneliPKfiiiiiiiiiiiiPf"
	.size	.L__unnamed_1, 40

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z17col2im_gpu_kerneliPKfiiiiiiiiiiiiiPf"
	.size	.L__unnamed_2, 41

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z33conv_diag_affine_fwd_batch_kernelPKfiiiS0_S0_Pf"
	.size	.L__unnamed_3, 52

	.type	.L__unnamed_4,@object           # @3
.L__unnamed_4:
	.asciz	"_Z33conv_diag_affine_bwd_batch_kernelPKfiiiS0_S0_PfS1_S1_"
	.size	.L__unnamed_4, 58

	.type	.L__unnamed_5,@object           # @4
.L__unnamed_5:
	.asciz	"_Z22conv_scale_rfwd_kernelPKfjjjS0_S0_S0_S0_Pf"
	.size	.L__unnamed_5, 47

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z32__device_stub__im2col_gpu_kerneliPKfiiiiiiiiiiiiPf
	.addrsig_sym _Z32__device_stub__col2im_gpu_kerneliPKfiiiiiiiiiiiiiPf
	.addrsig_sym _Z48__device_stub__conv_diag_affine_fwd_batch_kernelPKfiiiS0_S0_Pf
	.addrsig_sym _Z48__device_stub__conv_diag_affine_bwd_batch_kernelPKfiiiS0_S0_PfS1_S1_
	.addrsig_sym _Z37__device_stub__conv_scale_rfwd_kernelPKfjjjS0_S0_S0_S0_Pf
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z17im2col_gpu_kerneliPKfiiiiiiiiiiiiPf
	.addrsig_sym _Z17col2im_gpu_kerneliPKfiiiiiiiiiiiiiPf
	.addrsig_sym _Z33conv_diag_affine_fwd_batch_kernelPKfiiiS0_S0_Pf
	.addrsig_sym _Z33conv_diag_affine_bwd_batch_kernelPKfiiiS0_S0_PfS1_S1_
	.addrsig_sym _Z22conv_scale_rfwd_kernelPKfjjjS0_S0_S0_S0_Pf
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z17im2col_gpu_kerneliPKfiiiiiiiiiiiiPf ; -- Begin function _Z17im2col_gpu_kerneliPKfiiiiiiiiiiiiPf
	.globl	_Z17im2col_gpu_kerneliPKfiiiiiiiiiiiiPf
	.p2align	8
	.type	_Z17im2col_gpu_kerneliPKfiiiiiiiiiiiiPf,@function
_Z17im2col_gpu_kerneliPKfiiiiiiiiiiiiPf: ; @_Z17im2col_gpu_kerneliPKfiiiiiiiiiiiiPf
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x54
	s_load_b32 s3, s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_i32_e64 s3, v1
	s_cbranch_execz .LBB0_9
; %bb.1:
	s_load_b256 s[4:11], s[0:1], 0x10
	s_waitcnt lgkmcnt(0)
	s_cmp_lt_i32 s6, 1
	s_cbranch_scc1 .LBB0_9
; %bb.2:                                ; %.preheader.lr.ph
	s_clause 0x1
	s_load_b128 s[12:15], s[0:1], 0x30
	s_load_b64 s[16:17], s[0:1], 0x8
	v_ashrrev_i32_e32 v3, 31, v1
	s_load_b64 s[0:1], s[0:1], 0x40
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v4, v1, v3
	v_xor_b32_e32 v4, v4, v3
	s_waitcnt lgkmcnt(0)
	s_ashr_i32 s2, s15, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_add_i32 s3, s15, s2
	v_xor_b32_e32 v3, s2, v3
	s_xor_b32 s3, s3, s2
	v_cvt_f32_u32_e32 v0, s3
	s_sub_i32 s18, 0, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v0, v0
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v0, 0x4f7ffffe, v0
	v_cvt_u32_f32_e32 v0, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_mul_lo_u32 v2, s18, v0
	s_ashr_i32 s18, s14, 31
	s_add_i32 s19, s14, s18
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b32 s19, s19, s18
	v_cvt_f32_u32_e32 v5, s19
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v2, v0, v2
	s_sub_i32 s2, 0, s19
	s_cmp_gt_i32 s7, 0
	v_rcp_iflag_f32_e32 v5, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v0, v0, v2
	v_mul_hi_u32 v0, v4, v0
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v5, 0x4f7ffffe, v5
	v_mul_lo_u32 v2, v0, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v2, v4, v2
	v_add_nc_u32_e32 v4, 1, v0
	v_subrev_nc_u32_e32 v6, s3, v2
	v_cmp_le_u32_e32 vcc_lo, s3, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v0, v0, v4, vcc_lo
	v_cndmask_b32_e32 v2, v2, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v4, 1, v0
	v_cmp_le_u32_e32 vcc_lo, s3, v2
	v_cvt_u32_f32_e32 v2, v5
	s_mov_b32 s3, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v0, v0, v4, vcc_lo
	v_mul_lo_u32 v4, s2, v2
	s_mul_i32 s2, s7, s6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v0, v0, v3
	v_mul_hi_u32 v4, v2, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v0, v0, v3
	v_ashrrev_i32_e32 v3, 31, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v2, v2, v4
	v_add_nc_u32_e32 v5, v0, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v4, v5, v3
	v_xor_b32_e32 v3, s18, v3
	v_mul_hi_u32 v2, v4, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v5, v2, s19
	v_sub_nc_u32_e32 v4, v4, v5
	v_add_nc_u32_e32 v5, 1, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_subrev_nc_u32_e32 v6, s19, v4
	v_cmp_le_u32_e32 vcc_lo, s19, v4
	v_cndmask_b32_e32 v2, v2, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v4, v4, v6, vcc_lo
	v_add_nc_u32_e32 v5, 1, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_le_u32_e32 vcc_lo, s19, v4
	v_cndmask_b32_e32 v2, v2, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v2, v2, v3
	v_sub_nc_u32_e32 v7, v2, v3
	v_mul_lo_u32 v3, v0, s15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v6, v7, s14
	v_sub_nc_u32_e32 v3, v1, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v2, v0, v6
	v_mul_lo_u32 v1, v3, s11
	s_mul_i32 s11, s12, s5
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v0, v2, s10
	v_mad_u64_u32 v[4:5], null, v6, s2, v[2:3]
	s_cselect_b32 s10, -1, 0
	v_subrev_nc_u32_e32 v0, s8, v0
	s_mul_i32 s8, s15, s14
	s_mov_b32 s14, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_mad_u64_u32 v[5:6], null, v7, s4, v[0:1]
	v_subrev_nc_u32_e32 v1, s9, v1
	v_mad_u64_u32 v[6:7], null, v4, s15, v[3:4]
	s_ashr_i32 s9, s8, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	s_lshl_b64 s[8:9], s[8:9], 2
	v_mad_u64_u32 v[2:3], null, v5, s5, v[1:2]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v7, 31, v6
	v_ashrrev_i32_e32 v3, 31, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[4:5], 2, v[6:7]
	v_lshlrev_b64 v[6:7], 2, v[2:3]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v2, vcc_lo, s0, v4
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v4, vcc_lo, s16, v6
	v_add_co_ci_u32_e32 v5, vcc_lo, s17, v7, vcc_lo
.LBB0_3:                                ; %.preheader
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_5 Depth 2
	s_and_not1_b32 vcc_lo, exec_lo, s10
	s_cbranch_vccnz .LBB0_8
; %bb.4:                                ; %.lr.ph
                                        ;   in Loop: Header=BB0_3 Depth=1
	v_mad_u64_u32 v[6:7], null, s14, s12, v[0:1]
	s_mov_b32 s15, 0
	s_mov_b32 s16, s7
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_lt_i32_e32 vcc_lo, -1, v6
	v_cmp_gt_i32_e64 s0, s4, v6
.LBB0_5:                                ;   Parent Loop BB0_3 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_add_nc_u32_e32 v6, s15, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_cmp_lt_i32_e64 s1, -1, v6
	v_cmp_gt_i32_e64 s2, s5, v6
	v_mov_b32_e32 v6, 0
	s_and_b32 s1, vcc_lo, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s1, s0, s1
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	s_and_b32 s1, s1, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s2, s1
	s_cbranch_execz .LBB0_7
; %bb.6:                                ;   in Loop: Header=BB0_5 Depth=2
	s_add_i32 s18, s3, s15
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_ashr_i32 s19, s18, 31
	s_lshl_b64 s[18:19], s[18:19], 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v6, s1, v4, s18
	v_add_co_ci_u32_e64 v7, s1, s19, v5, s1
	global_load_b32 v6, v[6:7], off
.LBB0_7:                                ;   in Loop: Header=BB0_5 Depth=2
	s_or_b32 exec_lo, exec_lo, s2
	s_waitcnt vmcnt(0)
	global_store_b32 v[2:3], v6, off
	v_add_co_u32 v2, s1, v2, s8
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v3, s1, s9, v3, s1
	s_add_i32 s16, s16, -1
	s_add_i32 s15, s15, s13
	s_cmp_eq_u32 s16, 0
	s_cbranch_scc0 .LBB0_5
.LBB0_8:                                ; %Flow124
                                        ;   in Loop: Header=BB0_3 Depth=1
	s_add_i32 s14, s14, 1
	s_add_i32 s3, s3, s11
	s_cmp_eq_u32 s14, s6
	s_cbranch_scc0 .LBB0_3
.LBB0_9:                                ; %.loopexit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z17im2col_gpu_kerneliPKfiiiiiiiiiiiiPf
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 328
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 8
		.amdhsa_next_free_sgpr 20
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z17im2col_gpu_kerneliPKfiiiiiiiiiiiiPf, .Lfunc_end0-_Z17im2col_gpu_kerneliPKfiiiiiiiiiiiiPf
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 888
; NumSgprs: 22
; NumVgprs: 8
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 22
; NumVGPRsForWavesPerEU: 8
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z17col2im_gpu_kerneliPKfiiiiiiiiiiiiiPf ; -- Begin function _Z17col2im_gpu_kerneliPKfiiiiiiiiiiiiiPf
	.globl	_Z17col2im_gpu_kerneliPKfiiiiiiiiiiiiiPf
	.p2align	8
	.type	_Z17col2im_gpu_kerneliPKfiiiiiiiiiiiiiPf,@function
_Z17col2im_gpu_kerneliPKfiiiiiiiiiiiiiPf: ; @_Z17col2im_gpu_kerneliPKfiiiiiiiiiiiiiPf
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x5c
	s_load_b32 s3, s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_i32_e64 s3, v1
	s_cbranch_execz .LBB1_18
; %bb.1:
	s_clause 0x1
	s_load_b64 s[2:3], s[0:1], 0x10
	s_load_b64 s[12:13], s[0:1], 0x3c
	v_ashrrev_i32_e32 v2, 31, v1
	s_mov_b32 s14, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v4, v1, v2
	v_xor_b32_e32 v6, v4, v2
	s_waitcnt lgkmcnt(0)
	s_ashr_i32 s4, s3, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s5, s3, s4
	s_xor_b32 s5, s5, s4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cvt_f32_u32_e32 v0, s5
	s_sub_i32 s6, 0, s5
	v_rcp_iflag_f32_e32 v0, v0
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v0, 0x4f7ffffe, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v0, v0
	v_mul_lo_u32 v3, s6, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v3, v0, v3
	v_add_nc_u32_e32 v0, v0, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v0, v6, v0
	v_mul_lo_u32 v3, v0, s5
	v_add_nc_u32_e32 v4, 1, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v3, v6, v3
	v_subrev_nc_u32_e32 v5, s5, v3
	v_cmp_le_u32_e32 vcc_lo, s5, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v3, v3, v5 :: v_dual_cndmask_b32 v0, v0, v4
	v_xor_b32_e32 v5, s4, v2
	v_cmp_le_u32_e32 vcc_lo, s5, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v4, 1, v0
	s_load_b256 s[4:11], s[0:1], 0x1c
	v_cndmask_b32_e32 v0, v0, v4, vcc_lo
	v_mov_b32_e32 v4, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v0, v0, v5
	v_sub_nc_u32_e32 v5, v0, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_mul_lo_u32 v3, v5, s3
	s_waitcnt lgkmcnt(0)
	s_add_i32 s15, s5, -1
	s_mul_i32 s15, s15, s11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v0, v1, v3
	v_add_nc_u32_e32 v8, s7, v0
	v_mov_b32_e32 v0, 0
	s_delay_alu instid0(VALU_DEP_2)
	v_cmpx_lt_i32_e64 s15, v8
	s_cbranch_execz .LBB1_3
; %bb.2:
	s_ashr_i32 s16, s9, 31
	v_xad_u32 v9, s15, -1, v8
	s_add_i32 s17, s9, s16
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_xor_b32 s17, s17, s16
	v_ashrrev_i32_e32 v10, 31, v9
	v_cvt_f32_u32_e32 v4, s17
	s_sub_i32 s18, 0, s17
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v9, v9, v10
	v_rcp_iflag_f32_e32 v4, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v9, v9, v10
	v_xor_b32_e32 v10, s16, v10
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v4, 0x4f7ffffe, v4
	v_cvt_u32_f32_e32 v4, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v7, s18, v4
	v_mul_hi_u32 v7, v4, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v4, v4, v7
	v_mul_hi_u32 v4, v9, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v7, v4, s17
	v_sub_nc_u32_e32 v7, v9, v7
	v_add_nc_u32_e32 v9, 1, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v11, s17, v7
	v_cmp_le_u32_e32 vcc_lo, s17, v7
	v_dual_cndmask_b32 v4, v4, v9 :: v_dual_cndmask_b32 v7, v7, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v9, 1, v4
	v_cmp_le_u32_e32 vcc_lo, s17, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v4, v4, v9, vcc_lo
	v_xor_b32_e32 v4, v4, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v4, v4, v10
	v_add_nc_u32_e32 v4, 1, v4
.LBB1_3:
	s_or_b32 exec_lo, exec_lo, s14
	s_ashr_i32 s14, s2, 31
	v_ashrrev_i32_e32 v10, 31, v5
	s_add_i32 s15, s2, s14
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_xor_b32 s14, s15, s14
	v_add_nc_u32_e32 v5, v5, v10
	v_cvt_f32_u32_e32 v7, s14
	s_sub_i32 s15, 0, s14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v5, v5, v10
	v_rcp_iflag_f32_e32 v7, v7
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v7, 0x4f7ffffe, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v7, v7
	v_mul_lo_u32 v9, s15, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v9, v7, v9
	v_add_nc_u32_e32 v7, v7, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v7, v5, v7
	v_mul_lo_u32 v7, v7, s14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v5, v5, v7
	v_subrev_nc_u32_e32 v7, s14, v5
	v_cmp_le_u32_e32 vcc_lo, s14, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v5, v5, v7, vcc_lo
	v_subrev_nc_u32_e32 v7, s14, v5
	v_cmp_le_u32_e32 vcc_lo, s14, v5
	s_add_i32 s14, s4, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	s_mul_i32 s14, s14, s10
	v_cndmask_b32_e32 v5, v5, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v5, v5, v10
	v_sub_nc_u32_e32 v5, v5, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v5, s6, v5
	s_mov_b32 s6, exec_lo
	v_cmpx_lt_i32_e64 s14, v5
	s_cbranch_execz .LBB1_5
; %bb.4:
	s_ashr_i32 s15, s8, 31
	v_xad_u32 v9, s14, -1, v5
	s_add_i32 s16, s8, s15
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_xor_b32 s16, s16, s15
	v_ashrrev_i32_e32 v10, 31, v9
	v_cvt_f32_u32_e32 v0, s16
	s_sub_i32 s17, 0, s16
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v9, v9, v10
	v_rcp_iflag_f32_e32 v0, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v9, v9, v10
	v_xor_b32_e32 v10, s15, v10
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v0, 0x4f7ffffe, v0
	v_cvt_u32_f32_e32 v0, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v7, s17, v0
	v_mul_hi_u32 v7, v0, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v0, v0, v7
	v_mul_hi_u32 v0, v9, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v7, v0, s16
	v_sub_nc_u32_e32 v7, v9, v7
	v_add_nc_u32_e32 v9, 1, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v11, s16, v7
	v_cmp_le_u32_e32 vcc_lo, s16, v7
	v_dual_cndmask_b32 v0, v0, v9 :: v_dual_cndmask_b32 v7, v7, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v9, 1, v0
	v_cmp_le_u32_e32 vcc_lo, s16, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v0, v0, v9, vcc_lo
	v_xor_b32_e32 v0, v0, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v0, v0, v10
	v_add_nc_u32_e32 v0, 1, v0
.LBB1_5:
	s_or_b32 exec_lo, exec_lo, s6
	s_ashr_i32 s6, s8, 31
	v_ashrrev_i32_e32 v10, 31, v5
	s_add_i32 s14, s8, s6
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_xor_b32 s14, s14, s6
	v_add_nc_u32_e32 v11, v5, v10
	v_cvt_f32_u32_e32 v7, s14
	s_sub_i32 s15, 0, s14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v11, v11, v10
	v_rcp_iflag_f32_e32 v7, v7
	v_xor_b32_e32 v10, s6, v10
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v7, 0x4f7ffffe, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v7, v7
	v_mul_lo_u32 v9, s15, v7
	s_mov_b32 s15, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v9, v7, v9
	v_add_nc_u32_e32 v7, v7, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v7, v11, v7
	v_mul_lo_u32 v9, v7, s14
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v9, v11, v9
	v_add_nc_u32_e32 v11, 1, v7
	v_subrev_nc_u32_e32 v12, s14, v9
	v_cmp_le_u32_e32 vcc_lo, s14, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v7, v7, v11, vcc_lo
	v_cndmask_b32_e32 v9, v9, v12, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v11, 1, v7
	v_cmp_le_u32_e32 vcc_lo, s14, v9
	v_mov_b32_e32 v9, 0
	s_mov_b32 s14, exec_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v7, v7, v11, vcc_lo
	v_xor_b32_e32 v7, v7, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v7, v7, v10
	v_add_nc_u32_e32 v7, 1, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_min_i32_e32 v7, s12, v7
	v_cmpx_lt_i32_e64 v0, v7
	s_cbranch_execz .LBB1_17
; %bb.6:                                ; %.preheader.lr.ph
	s_ashr_i32 s6, s9, 31
	s_mul_i32 s2, s3, s2
	s_add_i32 s3, s9, s6
	s_ashr_i32 s20, s2, 31
	s_xor_b32 s3, s3, s6
	s_add_i32 s2, s2, s20
	v_cvt_f32_u32_e32 v9, s3
	s_xor_b32 s21, s2, s20
	s_sub_i32 s2, 0, s3
	v_cvt_f32_u32_e32 v10, s21
	s_ashr_i32 s16, s10, 31
	v_rcp_iflag_f32_e32 v9, v9
	s_ashr_i32 s17, s11, 31
	v_ashrrev_i32_e32 v13, 31, v8
	v_rcp_iflag_f32_e32 v10, v10
	v_mul_lo_u32 v16, v4, s9
	v_xor_b32_e32 v17, s20, v2
	s_waitcnt_depctr 0xfff
	v_dual_mul_f32 v9, 0x4f7ffffe, v9 :: v_dual_mul_f32 v10, 0x4f7ffffe, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_u32_f32_e32 v9, v9
	v_cvt_u32_f32_e32 v10, v10
	s_delay_alu instid0(VALU_DEP_2)
	v_mul_lo_u32 v11, s2, v9
	s_sub_i32 s2, 0, s21
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	v_mul_lo_u32 v12, s2, v10
	s_add_i32 s2, s10, s16
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	s_xor_b32 s18, s2, s16
	s_add_i32 s2, s11, s17
	v_mul_hi_u32 v11, v9, v11
	s_xor_b32 s19, s2, s17
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cvt_f32_u32_e32 v14, s19
	v_mul_hi_u32 v12, v10, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_rcp_iflag_f32_e32 v14, v14
	v_add_nc_u32_e32 v9, v9, v11
	v_cvt_f32_u32_e32 v11, s18
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v11, v11
	v_add_nc_u32_e32 v8, v8, v13
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v14, 0x4f7ffffe, v14
	v_cvt_u32_f32_e32 v14, v14
	v_mul_f32_e32 v11, 0x4f7ffffe, v11
	v_xor_b32_e32 v8, v8, v13
	v_xor_b32_e32 v13, s6, v13
	s_sub_i32 s6, 0, s18
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cvt_u32_f32_e32 v11, v11
	v_mul_hi_u32 v9, v8, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v15, v9, s3
	v_sub_nc_u32_e32 v8, v8, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_3)
	v_cmp_le_u32_e32 vcc_lo, s3, v8
	v_add_nc_u32_e32 v15, 1, v9
	v_add_nc_u32_e32 v10, v10, v12
	v_add_nc_u32_e32 v12, s7, v1
	s_sub_i32 s7, 0, s19
	v_cndmask_b32_e32 v9, v9, v15, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v10, v6, v10
	v_mul_lo_u32 v18, v10, s21
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v6, v6, v18
	v_subrev_nc_u32_e32 v18, s3, v8
	v_subrev_nc_u32_e32 v19, s21, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_cndmask_b32_e32 v8, v8, v18, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s21, v6
	v_add_nc_u32_e32 v15, 1, v10
	v_add_nc_u32_e32 v18, 1, v9
	v_cmp_le_u32_e64 s2, s3, v8
	v_cndmask_b32_e32 v6, v6, v19, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cndmask_b32_e32 v10, v10, v15, vcc_lo
	v_mul_lo_u32 v15, s6, v11
	v_cndmask_b32_e64 v8, v9, v18, s2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cmp_le_u32_e32 vcc_lo, s21, v6
	v_add_nc_u32_e32 v9, 1, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v8, v8, v13
	v_cndmask_b32_e32 v6, v10, v9, vcc_lo
	v_mul_lo_u32 v9, s7, v14
	s_load_b64 s[6:7], s[0:1], 0x8
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_sub_nc_u32_e32 v8, v8, v13
	v_sub_nc_u32_e32 v10, v12, v16
	v_xor_b32_e32 v6, v6, v17
	v_mul_hi_u32 v12, v11, v15
	v_add_nc_u32_e32 v8, 1, v8
	v_mul_hi_u32 v9, v14, v9
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v13, v6, v17
	v_min_i32_e32 v6, s13, v8
	v_sub_nc_u32_e32 v8, v10, v3
	v_add_nc_u32_e32 v10, v11, v12
	s_delay_alu instid0(VALU_DEP_4)
	v_mul_lo_u32 v11, v13, s4
	v_add_nc_u32_e32 v12, v14, v9
	v_cmp_lt_i32_e32 vcc_lo, v4, v6
	v_mov_b32_e32 v9, 0
.LBB1_7:                                ; %.preheader
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB1_9 Depth 2
	s_and_saveexec_b32 s4, vcc_lo
	s_cbranch_execz .LBB1_15
; %bb.8:                                ; %.lr.ph
                                        ;   in Loop: Header=BB1_7 Depth=1
	v_mul_lo_u32 v3, v0, s8
	s_mov_b32 s20, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v3, v5, v3
	v_ashrrev_i32_e32 v13, 31, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v14, v3, v13
	v_xor_b32_e32 v14, v14, v13
	v_xor_b32_e32 v13, s16, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v15, v14, v10
	v_mul_lo_u32 v16, v15, s18
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v14, v14, v16
	v_add_nc_u32_e32 v16, 1, v15
	v_subrev_nc_u32_e32 v17, s18, v14
	v_cmp_le_u32_e64 s2, s18, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v15, v15, v16, s2
	v_cndmask_b32_e64 v14, v14, v17, s2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v16, 1, v15
	v_cmp_le_u32_e64 s2, s18, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v14, v15, v16, s2
	v_xor_b32_e32 v14, v14, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v13, v14, v13
	v_mul_lo_u32 v14, v13, s10
	v_add_nc_u32_e32 v13, v13, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v3, v3, v14
	v_mov_b32_e32 v14, v8
	v_mul_lo_u32 v13, v13, s5
	s_delay_alu instid0(VALU_DEP_3)
	v_cmp_eq_u32_e64 s2, 0, v3
	v_mov_b32_e32 v3, v4
.LBB1_9:                                ;   Parent Loop BB1_7 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(VALU_DEP_2)
	s_and_saveexec_b32 s21, s2
	s_cbranch_execz .LBB1_13
; %bb.10:                               ;   in Loop: Header=BB1_9 Depth=2
	v_ashrrev_i32_e32 v15, 31, v14
	s_mov_b32 s22, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v16, v14, v15
	v_xor_b32_e32 v16, v16, v15
	v_xor_b32_e32 v15, s17, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v17, v16, v12
	v_mul_lo_u32 v18, v17, s19
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v16, v16, v18
	v_add_nc_u32_e32 v18, 1, v17
	v_subrev_nc_u32_e32 v19, s19, v16
	v_cmp_le_u32_e64 s3, s19, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v17, v17, v18, s3
	v_cndmask_b32_e64 v16, v16, v19, s3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v18, 1, v17
	v_cmp_le_u32_e64 s3, s19, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v16, v17, v18, s3
	v_xor_b32_e32 v16, v16, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v15, v16, v15
	v_mul_lo_u32 v16, v15, s11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v16, v14, v16
	v_cmpx_eq_u32_e32 0, v16
	s_cbranch_execz .LBB1_12
; %bb.11:                               ;   in Loop: Header=BB1_9 Depth=2
	v_add_nc_u32_e32 v17, v13, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[15:16], null, v17, s12, v[0:1]
	v_mad_u64_u32 v[16:17], null, s13, v15, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v17, 31, v16
	v_lshlrev_b64 v[15:16], 2, v[16:17]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v15, s3, s6, v15
	v_add_co_ci_u32_e64 v16, s3, s7, v16, s3
	global_load_b32 v15, v[15:16], off
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v9, v9, v15
.LBB1_12:                               ; %Flow
                                        ;   in Loop: Header=BB1_9 Depth=2
	s_or_b32 exec_lo, exec_lo, s22
.LBB1_13:                               ;   in Loop: Header=BB1_9 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_or_b32 exec_lo, exec_lo, s21
	v_add_nc_u32_e32 v3, 1, v3
	v_subrev_nc_u32_e32 v14, s9, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_ge_i32_e64 s3, v3, v6
	s_or_b32 s20, s3, s20
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s20
	s_cbranch_execnz .LBB1_9
; %bb.14:                               ; %Flow130
                                        ;   in Loop: Header=BB1_7 Depth=1
	s_or_b32 exec_lo, exec_lo, s20
.LBB1_15:                               ; %Flow131
                                        ;   in Loop: Header=BB1_7 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_or_b32 exec_lo, exec_lo, s4
	v_add_nc_u32_e32 v0, 1, v0
	v_cmp_ge_i32_e64 s2, v0, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s15, s2, s15
	s_and_not1_b32 exec_lo, exec_lo, s15
	s_cbranch_execnz .LBB1_7
; %bb.16:                               ; %Flow132
	s_or_b32 exec_lo, exec_lo, s15
.LBB1_17:                               ; %Flow133
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	s_or_b32 exec_lo, exec_lo, s14
	s_load_b64 s[0:1], s[0:1], 0x48
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v0, vcc_lo, s0, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	global_store_b32 v[0:1], v9, off
.LBB1_18:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z17col2im_gpu_kerneliPKfiiiiiiiiiiiiiPf
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 336
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 20
		.amdhsa_next_free_sgpr 23
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z17col2im_gpu_kerneliPKfiiiiiiiiiiiiiPf, .Lfunc_end1-_Z17col2im_gpu_kerneliPKfiiiiiiiiiiiiiPf
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 2228
; NumSgprs: 25
; NumVgprs: 20
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 25
; NumVGPRsForWavesPerEU: 20
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z33conv_diag_affine_fwd_batch_kernelPKfiiiS0_S0_Pf ; -- Begin function _Z33conv_diag_affine_fwd_batch_kernelPKfiiiS0_S0_Pf
	.globl	_Z33conv_diag_affine_fwd_batch_kernelPKfiiiS0_S0_Pf
	.p2align	8
	.type	_Z33conv_diag_affine_fwd_batch_kernelPKfiiiS0_S0_Pf,@function
_Z33conv_diag_affine_fwd_batch_kernelPKfiiiS0_S0_Pf: ; @_Z33conv_diag_affine_fwd_batch_kernelPKfiiiS0_S0_Pf
; %bb.0:
	s_clause 0x1
	s_load_b128 s[4:7], s[0:1], 0x8
	s_load_b32 s2, s[0:1], 0x3c
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s3, s5, s4
	s_and_b32 s2, s2, 0xffff
	s_ashr_i32 s7, s3, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s3, s3, s7
	s_xor_b32 s3, s3, s7
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f32_u32_e32 v1, s3
	v_rcp_iflag_f32_e32 v1, v1
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v1, 0x4f7ffffe, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_cvt_u32_f32_e32 v3, v1
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_sub_i32 s2, 0, s3
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	v_mul_lo_u32 v0, s2, v3
	s_or_b32 s2, s5, s4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	s_cmp_gt_i32 s2, -1
	v_ashrrev_i32_e32 v2, 31, v1
	s_cselect_b32 s2, -1, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v4, v3, v0
	v_add_nc_u32_e32 v0, v1, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v0, v0, v2
	v_add_nc_u32_e32 v3, v3, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v3, v0, v3
	v_mul_lo_u32 v4, v3, s3
	v_add_nc_u32_e32 v5, 1, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v4, v0, v4
	v_subrev_nc_u32_e32 v6, s3, v4
	v_cmp_le_u32_e32 vcc_lo, s3, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v3, v3, v5 :: v_dual_cndmask_b32 v4, v4, v6
	v_xor_b32_e32 v6, s7, v2
	v_add_nc_u32_e32 v5, 1, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_le_u32_e32 vcc_lo, s3, v4
	v_cndmask_b32_e32 v3, v3, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v3, v3, v6
	v_sub_nc_u32_e32 v3, v3, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_gt_i32_e32 vcc_lo, s6, v3
	s_and_b32 s2, s2, vcc_lo
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB2_2
; %bb.1:
	s_ashr_i32 s2, s4, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s3, s4, s2
	s_xor_b32 s3, s3, s2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cvt_f32_u32_e32 v3, s3
	s_sub_i32 s4, 0, s3
	v_rcp_iflag_f32_e32 v3, v3
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v3, 0x4f7ffffe, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v3, v3
	v_mul_lo_u32 v4, s4, v3
	s_ashr_i32 s4, s5, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s5, s5, s4
	s_xor_b32 s4, s5, s4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_f32_u32_e32 v5, s4
	v_mul_hi_u32 v4, v3, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v5, v5
	v_add_nc_u32_e32 v3, v3, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v3, v0, v3
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v5, 0x4f7ffffe, v5
	v_mul_lo_u32 v4, v3, s3
	v_sub_nc_u32_e32 v0, v0, v4
	v_add_nc_u32_e32 v4, 1, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v6, s3, v0
	v_cmp_le_u32_e32 vcc_lo, s3, v0
	v_dual_cndmask_b32 v3, v3, v4 :: v_dual_cndmask_b32 v0, v0, v6
	v_xor_b32_e32 v6, s2, v2
	s_sub_i32 s2, 0, s4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v4, 1, v3
	v_cmp_le_u32_e32 vcc_lo, s3, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v0, v3, v4, vcc_lo
	v_cvt_u32_f32_e32 v3, v5
	v_xor_b32_e32 v0, v0, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v4, s2, v3
	s_load_b64 s[2:3], s[0:1], 0x0
	v_sub_nc_u32_e32 v0, v0, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v4, v3, v4
	v_ashrrev_i32_e32 v5, 31, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v0, v0, v5
	v_add_nc_u32_e32 v3, v3, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v0, v0, v5
	v_mul_hi_u32 v3, v0, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v3, v3, s4
	v_sub_nc_u32_e32 v0, v0, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v3, s4, v0
	v_cmp_le_u32_e32 vcc_lo, s4, v0
	v_cndmask_b32_e32 v0, v0, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_subrev_nc_u32_e32 v3, s4, v0
	v_cmp_le_u32_e32 vcc_lo, s4, v0
	s_clause 0x1
	s_load_b128 s[4:7], s[0:1], 0x18
	s_load_b64 s[0:1], s[0:1], 0x28
	v_cndmask_b32_e32 v0, v0, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v0, v0, v5
	v_sub_nc_u32_e32 v3, v0, v5
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v4, 31, v3
	v_lshlrev_b64 v[2:3], 2, v[3:4]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v4, vcc_lo, s2, v0
	v_add_co_ci_u32_e32 v5, vcc_lo, s3, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v6, vcc_lo, s4, v2
	v_add_co_ci_u32_e32 v7, vcc_lo, s5, v3, vcc_lo
	v_add_co_u32 v2, vcc_lo, s6, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
	global_load_b32 v4, v[4:5], off
	global_load_b32 v5, v[6:7], off
	global_load_b32 v2, v[2:3], off
	v_add_co_u32 v0, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v2, v5, v4
	global_store_b32 v[0:1], v2, off
.LBB2_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z33conv_diag_affine_fwd_batch_kernelPKfiiiS0_S0_Pf
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 304
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 8
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_Z33conv_diag_affine_fwd_batch_kernelPKfiiiS0_S0_Pf, .Lfunc_end2-_Z33conv_diag_affine_fwd_batch_kernelPKfiiiS0_S0_Pf
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 744
; NumSgprs: 18
; NumVgprs: 8
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 8
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z33conv_diag_affine_bwd_batch_kernelPKfiiiS0_S0_PfS1_S1_ ; -- Begin function _Z33conv_diag_affine_bwd_batch_kernelPKfiiiS0_S0_PfS1_S1_
	.globl	_Z33conv_diag_affine_bwd_batch_kernelPKfiiiS0_S0_PfS1_S1_
	.p2align	8
	.type	_Z33conv_diag_affine_bwd_batch_kernelPKfiiiS0_S0_PfS1_S1_,@function
_Z33conv_diag_affine_bwd_batch_kernelPKfiiiS0_S0_PfS1_S1_: ; @_Z33conv_diag_affine_bwd_batch_kernelPKfiiiS0_S0_PfS1_S1_
; %bb.0:
	s_clause 0x2
	s_load_b128 s[16:19], s[0:1], 0x8
	s_load_b64 s[12:13], s[0:1], 0x38
	s_load_b32 s5, s[0:1], 0x4c
	s_waitcnt lgkmcnt(0)
	s_lshl_b32 s2, s17, 5
	s_bfe_i32 s3, s17, 0x1001a
	s_and_b32 s5, s5, 0xffff
	s_add_i32 s4, s2, s3
	s_ashr_i32 s6, s17, 31
	s_xor_b32 s4, s4, s3
	s_add_i32 s8, s17, s6
	v_cvt_f32_u32_e32 v1, s4
	s_xor_b32 s14, s8, s6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v1, v1
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v1, 0x4f7ffffe, v1
	v_cvt_u32_f32_e32 v3, v1
	v_mad_u64_u32 v[1:2], null, s15, s5, v[0:1]
	s_sub_i32 s5, 0, s4
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	v_mul_lo_u32 v2, s5, v3
	s_add_i32 s5, s16, 0x1ff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	s_ashr_i32 s7, s5, 31
	v_ashrrev_i32_e32 v4, 31, v1
	s_lshr_b32 s7, s7, 23
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	s_add_i32 s5, s5, s7
	v_mul_hi_u32 v2, v3, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_nc_u32_e32 v5, v1, v4
	s_ashr_i32 s6, s5, 9
	s_ashr_i32 s5, s5, 31
	s_mul_i32 s2, s2, s6
	s_add_i32 s8, s6, s5
	v_xor_b32_e32 v5, v5, v4
	s_xor_b32 s5, s8, s5
	v_add_nc_u32_e32 v2, v3, v2
	v_cvt_f32_u32_e32 v7, s5
	v_cvt_f32_u32_e32 v3, s14
	s_ashr_i32 s6, s2, 31
	v_xor_b32_e32 v11, s3, v4
	v_mul_hi_u32 v2, v5, v2
	v_rcp_iflag_f32_e32 v7, v7
	v_rcp_iflag_f32_e32 v3, v3
	s_add_i32 s2, s2, s6
	s_sub_i32 s8, 0, s5
	s_xor_b32 s2, s2, s6
	s_sub_i32 s7, 0, s14
	v_cvt_f32_u32_e32 v9, s2
	v_mul_lo_u32 v6, v2, s4
	v_add_nc_u32_e32 v8, 1, v2
	s_sub_i32 s3, 0, s2
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v7, 0x4f7ffffe, v7
	s_cmp_gt_i32 s17, -1
	v_mul_f32_e32 v3, 0x4f7ffffe, v3
	v_sub_nc_u32_e32 v6, v5, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_u32_f32_e32 v3, v3
	v_subrev_nc_u32_e32 v10, s4, v6
	v_cmp_le_u32_e32 vcc_lo, s4, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_mul_lo_u32 v12, s7, v3
	v_cndmask_b32_e32 v2, v2, v8, vcc_lo
	v_cndmask_b32_e32 v6, v6, v10, vcc_lo
	v_rcp_iflag_f32_e32 v8, v9
	v_lshrrev_b32_e32 v10, 27, v4
	v_xor_b32_e32 v4, s6, v4
	v_add_nc_u32_e32 v9, 1, v2
	v_cmp_le_u32_e32 vcc_lo, s4, v6
	v_cvt_u32_f32_e32 v6, v7
	v_mul_hi_u32 v12, v3, v12
	s_delay_alu instid0(TRANS32_DEP_1) | instid1(VALU_DEP_4)
	v_dual_cndmask_b32 v2, v2, v9 :: v_dual_mul_f32 v7, 0x4f7ffffe, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v9, s8, v6
	v_xor_b32_e32 v2, v2, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_u32_f32_e32 v7, v7
	v_sub_nc_u32_e32 v2, v2, v11
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_hi_u32 v9, v6, v9
	v_mul_lo_u32 v13, s3, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_ashrrev_i32_e32 v14, 31, v2
	v_add_nc_u32_e32 v6, v6, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v2, v2, v14
	v_mul_hi_u32 v13, v7, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v2, v2, v14
	v_mul_hi_u32 v6, v2, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v6, v6, s5
	v_sub_nc_u32_e32 v2, v2, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v6, s5, v2
	v_cmp_le_u32_e32 vcc_lo, s5, v2
	v_dual_cndmask_b32 v2, v2, v6 :: v_dual_add_nc_u32 v7, v7, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v7, v5, v7
	v_add_nc_u32_e32 v8, v1, v10
	v_add_nc_u32_e32 v3, v3, v12
	v_ashrrev_i32_e32 v10, 5, v8
	v_ashrrev_i32_e32 v11, 31, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v10, v10, v11
	v_xor_b32_e32 v9, v10, v11
	v_mul_lo_u32 v10, v7, s2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v3, v9, v3
	v_sub_nc_u32_e32 v5, v5, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v3, v3, s14
	v_subrev_nc_u32_e32 v6, s2, v5
	v_cmp_le_u32_e32 vcc_lo, s2, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e32 v5, v5, v6, vcc_lo
	v_sub_nc_u32_e32 v3, v9, v3
	v_add_nc_u32_e32 v9, 1, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v10, s14, v3
	v_cndmask_b32_e32 v7, v7, v9, vcc_lo
	v_subrev_nc_u32_e32 v9, s5, v2
	v_cmp_le_u32_e32 vcc_lo, s5, v2
	s_load_b256 s[4:11], s[0:1], 0x18
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v6, 1, v7
	v_cndmask_b32_e32 v2, v2, v9, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s14, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v2, v2, v14
	v_cndmask_b32_e32 v3, v3, v10, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s2, v5
	v_and_b32_e32 v8, 0xffffffe0, v8
	v_sub_nc_u32_e32 v2, v2, v14
	v_cndmask_b32_e32 v5, v7, v6, vcc_lo
	v_subrev_nc_u32_e32 v6, s14, v3
	v_cmp_le_u32_e32 vcc_lo, s14, v3
	v_sub_nc_u32_e32 v1, v1, v8
	s_cselect_b32 s14, -1, 0
	v_xor_b32_e32 v5, v5, v4
	v_cndmask_b32_e32 v7, v3, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_lshl_add_u32 v3, v2, 9, v1
	v_mov_b32_e32 v2, 0
	v_sub_nc_u32_e32 v6, v5, v4
	v_mov_b32_e32 v5, 0
	v_xor_b32_e32 v1, v7, v11
	v_cmp_gt_i32_e32 vcc_lo, s16, v3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_gt_i32_e64 s2, s18, v6
	v_sub_nc_u32_e32 v1, v1, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s3, vcc_lo, s2
	s_and_b32 s3, s3, s14
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s15, s3
	s_cbranch_execz .LBB3_4
; %bb.1:                                ; %.lr.ph
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[4:5], 2, v[1:2]
	v_mad_u64_u32 v[7:8], null, v6, s17, v[1:2]
	v_add_nc_u32_e32 v2, 0x200, v3
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v4, s3, s6, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_co_ci_u32_e64 v5, s3, s7, v5, s3
	s_load_b64 s[6:7], s[0:1], 0x0
	v_mul_lo_u32 v6, v7, s16
	s_mov_b32 s3, 0
	global_load_b32 v4, v[4:5], off
	v_mov_b32_e32 v5, 0
	v_min_i32_e32 v7, s16, v2
	v_mov_b32_e32 v2, 0
.LBB3_2:                                ; =>This Inner Loop Header: Depth=1
	v_add_nc_u32_e32 v8, v6, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v9, 31, v8
	v_lshlrev_b64 v[8:9], 2, v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v10, s0, s4, v8
	v_add_co_ci_u32_e64 v11, s0, s5, v9, s0
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v12, s0, s6, v8
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v13, s0, s7, v9, s0
	v_add_co_u32 v8, s1, s12, v8
	global_load_b32 v10, v[10:11], off
	global_load_b32 v11, v[12:13], off
	v_add_nc_u32_e32 v3, 32, v3
	v_add_co_ci_u32_e64 v9, s1, s13, v9, s1
	s_waitcnt vmcnt(1)
	v_add_f32_e32 v2, v2, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_cmp_ge_i32_e64 s0, v3, v7
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v5, v10, v11
	v_mul_f32_e32 v11, v4, v10
	s_or_b32 s3, s0, s3
	global_store_b32 v[8:9], v11, off
	s_and_not1_b32 exec_lo, exec_lo, s3
	s_cbranch_execnz .LBB3_2
; %bb.3:                                ; %Flow173
	s_or_b32 exec_lo, exec_lo, s3
.LBB3_4:                                ; %Flow174
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	s_or_b32 exec_lo, exec_lo, s15
	v_lshrrev_b32_e32 v3, 5, v0
	v_and_b32_e32 v4, 1, v0
	s_and_b32 s1, s14, s2
	v_add_lshl_u32 v6, v3, v0, 2
	s_delay_alu instid0(VALU_DEP_2)
	v_cmp_eq_u32_e64 s0, 0, v4
	ds_store_b32 v6, v5 offset:4224
	ds_store_b32 v6, v2
	v_add_nc_u32_e32 v4, 0x1080, v6
	s_and_b32 s2, s0, s1
	s_waitcnt lgkmcnt(0)
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s0, s2
	s_cbranch_execz .LBB3_6
; %bb.5:
	ds_load_2addr_b32 v[2:3], v4 offset1:1
	ds_load_2addr_b32 v[7:8], v6 offset1:1
	s_waitcnt lgkmcnt(0)
	v_dual_add_f32 v2, v3, v2 :: v_dual_add_f32 v3, v8, v7
	ds_store_b32 v4, v2
	ds_store_b32 v6, v3
.LBB3_6:
	s_or_b32 exec_lo, exec_lo, s0
	v_and_b32_e32 v2, 3, v0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmp_eq_u32_e64 s0, 0, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, s0, s1
	s_and_saveexec_b32 s0, s2
	s_cbranch_execz .LBB3_8
; %bb.7:
	ds_load_2addr_b32 v[2:3], v4 offset1:2
	ds_load_2addr_b32 v[7:8], v6 offset1:2
	s_waitcnt lgkmcnt(0)
	v_dual_add_f32 v2, v3, v2 :: v_dual_add_f32 v3, v8, v7
	ds_store_b32 v4, v2
	ds_store_b32 v6, v3
.LBB3_8:
	s_or_b32 exec_lo, exec_lo, s0
	v_and_b32_e32 v2, 7, v0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmp_eq_u32_e64 s0, 0, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, s0, s1
	s_and_saveexec_b32 s0, s2
	s_cbranch_execz .LBB3_10
; %bb.9:
	ds_load_2addr_b32 v[2:3], v4 offset1:4
	ds_load_2addr_b32 v[7:8], v6 offset1:4
	s_waitcnt lgkmcnt(0)
	v_dual_add_f32 v2, v3, v2 :: v_dual_add_f32 v3, v8, v7
	ds_store_b32 v4, v2
	ds_store_b32 v6, v3
.LBB3_10:
	s_or_b32 exec_lo, exec_lo, s0
	v_and_b32_e32 v2, 15, v0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmp_eq_u32_e64 s0, 0, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, s0, s1
	s_and_saveexec_b32 s0, s2
	s_cbranch_execz .LBB3_12
; %bb.11:
	ds_load_2addr_b32 v[2:3], v4 offset1:8
	ds_load_2addr_b32 v[7:8], v6 offset1:8
	s_waitcnt lgkmcnt(0)
	v_dual_add_f32 v2, v3, v2 :: v_dual_add_f32 v3, v8, v7
	ds_store_b32 v4, v2
	ds_store_b32 v6, v3
.LBB3_12:
	s_or_b32 exec_lo, exec_lo, s0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s0, s1
	s_cbranch_execz .LBB3_18
; %bb.13:
	v_and_b32_e32 v0, 31, v0
	s_mov_b32 s1, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_eq_u32_e64 s0, 0, v0
	s_and_b32 s0, s0, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB3_18
; %bb.14:
	v_ashrrev_i32_e32 v2, 31, v1
	ds_load_2addr_b32 v[7:8], v4 offset1:16
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s8, v0
	v_add_co_ci_u32_e32 v3, vcc_lo, s9, v1, vcc_lo
	global_load_b32 v5, v[2:3], off
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v7, v7, v8
.LBB3_15:                               ; %atomicrmw.start
                                        ; =>This Inner Loop Header: Depth=1
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f32_e32 v4, v5, v7
	global_atomic_cmpswap_b32 v4, v[2:3], v[4:5], off glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u32_e32 vcc_lo, v4, v5
	v_mov_b32_e32 v5, v4
	s_or_b32 s1, vcc_lo, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s1
	s_cbranch_execnz .LBB3_15
; %bb.16:                               ; %atomicrmw.end
	s_or_b32 exec_lo, exec_lo, s1
	v_add_co_u32 v0, vcc_lo, s10, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s11, v1, vcc_lo
	ds_load_2addr_b32 v[4:5], v6 offset1:16
	s_mov_b32 s0, 0
	global_load_b32 v3, v[0:1], off
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v4, v4, v5
.LBB3_17:                               ; %atomicrmw.start141
                                        ; =>This Inner Loop Header: Depth=1
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f32_e32 v2, v3, v4
	global_atomic_cmpswap_b32 v2, v[0:1], v[2:3], off glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u32_e32 vcc_lo, v2, v3
	v_mov_b32_e32 v3, v2
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB3_17
.LBB3_18:
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z33conv_diag_affine_bwd_batch_kernelPKfiiiS0_S0_PfS1_S1_
		.amdhsa_group_segment_fixed_size 8448
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 320
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 15
		.amdhsa_next_free_sgpr 20
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end3:
	.size	_Z33conv_diag_affine_bwd_batch_kernelPKfiiiS0_S0_PfS1_S1_, .Lfunc_end3-_Z33conv_diag_affine_bwd_batch_kernelPKfiiiS0_S0_PfS1_S1_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1708
; NumSgprs: 22
; NumVgprs: 15
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 8448 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 22
; NumVGPRsForWavesPerEU: 15
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z22conv_scale_rfwd_kernelPKfjjjS0_S0_S0_S0_Pf ; -- Begin function _Z22conv_scale_rfwd_kernelPKfjjjS0_S0_S0_S0_Pf
	.globl	_Z22conv_scale_rfwd_kernelPKfjjjS0_S0_S0_S0_Pf
	.p2align	8
	.type	_Z22conv_scale_rfwd_kernelPKfjjjS0_S0_S0_S0_Pf,@function
_Z22conv_scale_rfwd_kernelPKfjjjS0_S0_S0_S0_Pf: ; @_Z22conv_scale_rfwd_kernelPKfjjjS0_S0_S0_S0_Pf
; %bb.0:
	s_clause 0x1
	s_load_b128 s[16:19], s[0:1], 0x8
	s_load_b32 s2, s[0:1], 0x4c
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s3, s17, s16
	s_and_b32 s2, s2, 0xffff
	v_cvt_f32_u32_e32 v1, s3
	s_sub_i32 s4, 0, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v1, v1
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v1, 0x4f7ffffe, v1
	v_cvt_u32_f32_e32 v3, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v1, s4, v3
	v_mul_hi_u32 v4, v3, v1
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v0, v3, v4
	v_mul_hi_u32 v0, v1, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v2, v0, s3
	v_add_nc_u32_e32 v3, 1, v0
	v_sub_nc_u32_e32 v2, v1, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_subrev_nc_u32_e32 v4, s3, v2
	v_cmp_le_u32_e32 vcc_lo, s3, v2
	v_cndmask_b32_e32 v0, v0, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v2, v2, v4, vcc_lo
	v_add_nc_u32_e32 v3, 1, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_le_u32_e32 vcc_lo, s3, v2
	v_cndmask_b32_e32 v0, v0, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e64 s18, v0
	s_cbranch_execz .LBB4_2
; %bb.1:
	v_cvt_f32_u32_e32 v0, s16
	s_sub_i32 s2, 0, s16
	v_cvt_f32_u32_e32 v3, s17
	s_load_b256 s[4:11], s[0:1], 0x18
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v0, v0
	v_rcp_iflag_f32_e32 v3, v3
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v0, 0x4f7ffffe, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v0, v0
	v_mul_lo_u32 v2, s2, v0
	s_sub_i32 s2, 0, s17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v2, v0, v2
	v_add_nc_u32_e32 v0, v0, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v0, v1, v0
	v_dual_mul_f32 v2, 0x4f7ffffe, v3 :: v_dual_add_nc_u32 v5, 1, v0
	v_mul_lo_u32 v3, v0, s16
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v2, v2
	v_mul_lo_u32 v4, s2, v2
	s_load_b64 s[2:3], s[0:1], 0x0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v3, v1, v3
	s_load_b64 s[0:1], s[0:1], 0x38
	v_subrev_nc_u32_e32 v6, s16, v3
	v_cmp_le_u32_e32 vcc_lo, s16, v3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_hi_u32 v4, v2, v4
	v_dual_cndmask_b32 v0, v0, v5 :: v_dual_cndmask_b32 v3, v3, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v2, v2, v4
	v_add_nc_u32_e32 v5, 1, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_le_u32_e32 vcc_lo, s16, v3
	v_cndmask_b32_e32 v0, v0, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v2, v0, v2
	v_mul_lo_u32 v2, v2, s17
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v0, v0, v2
	v_mov_b32_e32 v2, 0
	v_subrev_nc_u32_e32 v3, s17, v0
	v_cmp_le_u32_e32 vcc_lo, s17, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e32 v6, v0, v3, vcc_lo
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	v_mov_b32_e32 v3, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_subrev_nc_u32_e32 v2, s17, v6
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v4, vcc_lo, s4, v0
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v1, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s17, v6
	v_cndmask_b32_e32 v2, v6, v2, vcc_lo
	v_add_co_u32 v6, vcc_lo, s2, v0
	v_add_co_ci_u32_e32 v7, vcc_lo, s3, v1, vcc_lo
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	global_load_b32 v8, v[4:5], off
	global_load_b32 v9, v[6:7], off
	v_add_co_u32 v4, vcc_lo, s8, v2
	v_add_co_ci_u32_e32 v5, vcc_lo, s9, v3, vcc_lo
	v_add_co_u32 v6, vcc_lo, s6, v2
	v_add_co_ci_u32_e32 v7, vcc_lo, s7, v3, vcc_lo
	global_load_b32 v4, v[4:5], off
	v_add_co_u32 v2, vcc_lo, s10, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s11, v3, vcc_lo
	global_load_b32 v5, v[6:7], off
	global_load_b32 v2, v[2:3], off
	v_add_co_u32 v0, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	s_waitcnt vmcnt(2)
	v_mul_f32_e32 v3, v4, v9
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v3, v5, v8
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v2, v2, v3
	global_store_b32 v[0:1], v2, off
.LBB4_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z22conv_scale_rfwd_kernelPKfjjjS0_S0_S0_S0_Pf
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 320
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 10
		.amdhsa_next_free_sgpr 20
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end4:
	.size	_Z22conv_scale_rfwd_kernelPKfjjjS0_S0_S0_S0_Pf, .Lfunc_end4-_Z22conv_scale_rfwd_kernelPKfjjjS0_S0_S0_S0_Pf
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 648
; NumSgprs: 22
; NumVgprs: 10
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 22
; NumVGPRsForWavesPerEU: 10
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         36
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     by_value
      - .offset:         44
        .size:           4
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     by_value
      - .offset:         52
        .size:           4
        .value_kind:     by_value
      - .offset:         56
        .size:           4
        .value_kind:     by_value
      - .offset:         60
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