#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <cuda.h>

#define THREADS 30
#define BLOCKS 200
#define SIZE 6000

__device__ float d_A[SIZE][SIZE];
__device__ float d_B[SIZE][SIZE];
__device__ float d_C[SIZE][SIZE];
__device__ float d_D[SIZE][SIZE];
__device__ float d_V[SIZE];
__device__ float d_VET[SIZE];
__device__ float ESCALAR = 1.25;

__global__ void load()
{
    for(int i = 0; i < SIZE; i++)
    {
        for(int j = 0; j < SIZE; j++) 
        {
            d_A[i][j] = i + j;
            d_B[i][j] = i + j;
            d_C[i][j] = 0;
            d_D[i][j] = 0;
        }

        d_V[i] = i;
        d_VET[i] = 0;
    }
}

__global__ void sumA_B()
{
    int i = blockIdx.x * blockDim.x + threadIdx.x;
    int j = blockIdx.y * blockDim.y + threadIdx.y;

    if(i < SIZE && j < SIZE)
        d_C[i][j] = d_A[i][j] + d_B[i][j];
}

__global__ void mulA_B()
{
    int i = blockIdx.x * blockDim.x + threadIdx.x;
    int j = blockIdx.y * blockDim.y + threadIdx.y;

    if(i < SIZE && j < SIZE)
    {
        for(int k = 0; k < SIZE; k++) 
            d_D[i][j] += d_A[i][k] * d_B[k][j];
    }
}

__global__ void mulA_ESCALAR()
{
    int i = blockIdx.x * blockDim.x + threadIdx.x;
    int j = blockIdx.y * blockDim.y + threadIdx.y;

    if(i < SIZE && j < SIZE)
        d_A[i][j] *= ESCALAR;
}

__global__ void mulB_V()
{
    int i = blockIdx.x * blockDim.x + threadIdx.x;

    if(i < SIZE)
    {
        for(int j = 0; j < SIZE; j++)
            d_VET[i] += d_B[i][j] * d_V[j];
    }
}

int main()
{  
    clock_t begin, end;

    cudaSetDevice(0);  
    load<<<1, 1>>>();
    cudaDeviceSynchronize();
    
    printf("Somar A e B e armazenar em C.\n");
    begin = clock();
    sumA_B<<<dim3(BLOCKS, BLOCKS), dim3(THREADS, THREADS)>>>();
    cudaDeviceSynchronize();
    end = clock();
    printf("Feito em %.3f segundos.\n", double(end - begin) / CLOCKS_PER_SEC);

    printf("Multiplicar A e B e armazenar em D.\n");
    begin = clock();
    mulA_B<<<dim3(BLOCKS, BLOCKS), dim3(THREADS, THREADS)>>>();
    cudaDeviceSynchronize();
    end = clock();
    printf("Feito em %.3f segundos.\n", double(end - begin) / CLOCKS_PER_SEC);

    printf("Multiplicar A e ESCALAR e armazenar em A.\n");
    begin = clock();
    mulA_ESCALAR<<<dim3(BLOCKS, BLOCKS), dim3(THREADS, THREADS)>>>();
    cudaDeviceSynchronize();
    end = clock();
    printf("Feito em %.3f segundos.\n", double(end - begin) / CLOCKS_PER_SEC);
    
    printf("Multiplicar B e V e armazenar em VET.\n");
    begin = clock();
    mulB_V<<<BLOCKS, THREADS>>>();    
    cudaDeviceSynchronize();
    end = clock();
    printf("Feito em %.3f segundos.\n", double(end - begin) / CLOCKS_PER_SEC);
}
	.file	"tmpxft_003328ec_00000000-6_main.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2030:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z22__device_stub__Z4loadvv
	.type	_Z22__device_stub__Z4loadvv, @function
_Z22__device_stub__Z4loadvv:
.LFB2052:
	.cfi_startproc
	endbr64
	subq	$88, %rsp
	.cfi_def_cfa_offset 96
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	movabsq	$4294967297, %rax
	leaq	8(%rsp), %rcx
	movq	%rsp, %rdx
	leaq	28(%rsp), %rsi
	leaq	16(%rsp), %rdi
	movl	$1, 24(%rsp)
	movl	$1, 36(%rsp)
	movq	%rax, 16(%rsp)
	movq	%rax, 28(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	8(%rsp)
	.cfi_def_cfa_offset 104
	leaq	_Z4loadv(%rip), %rdi
	pushq	8(%rsp)
	.cfi_def_cfa_offset 112
	movq	44(%rsp), %rcx
	movl	52(%rsp), %r8d
	movq	32(%rsp), %rsi
	movl	40(%rsp), %edx
	leaq	80(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 104
	popq	%rdx
	.cfi_def_cfa_offset 96
.L2:
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$88, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2052:
	.size	_Z22__device_stub__Z4loadvv, .-_Z22__device_stub__Z4loadvv
	.globl	_Z4loadv
	.type	_Z4loadv, @function
_Z4loadv:
.LFB2053:
	.cfi_startproc
	endbr64
	jmp	_Z22__device_stub__Z4loadvv
	.cfi_endproc
.LFE2053:
	.size	_Z4loadv, .-_Z4loadv
	.globl	_Z24__device_stub__Z6sumA_Bvv
	.type	_Z24__device_stub__Z6sumA_Bvv, @function
_Z24__device_stub__Z6sumA_Bvv:
.LFB2054:
	.cfi_startproc
	endbr64
	subq	$88, %rsp
	.cfi_def_cfa_offset 96
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	movabsq	$4294967297, %rax
	leaq	8(%rsp), %rcx
	movq	%rsp, %rdx
	leaq	28(%rsp), %rsi
	leaq	16(%rsp), %rdi
	movl	$1, 24(%rsp)
	movl	$1, 36(%rsp)
	movq	%rax, 16(%rsp)
	movq	%rax, 28(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L8
	pushq	8(%rsp)
	.cfi_def_cfa_offset 104
	leaq	_Z6sumA_Bv(%rip), %rdi
	pushq	8(%rsp)
	.cfi_def_cfa_offset 112
	movq	44(%rsp), %rcx
	movl	52(%rsp), %r8d
	movq	32(%rsp), %rsi
	movl	40(%rsp), %edx
	leaq	80(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 104
	popq	%rdx
	.cfi_def_cfa_offset 96
.L8:
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L10
	call	__stack_chk_fail@PLT
.L10:
	addq	$88, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2054:
	.size	_Z24__device_stub__Z6sumA_Bvv, .-_Z24__device_stub__Z6sumA_Bvv
	.globl	_Z6sumA_Bv
	.type	_Z6sumA_Bv, @function
_Z6sumA_Bv:
.LFB2055:
	.cfi_startproc
	endbr64
	jmp	_Z24__device_stub__Z6sumA_Bvv
	.cfi_endproc
.LFE2055:
	.size	_Z6sumA_Bv, .-_Z6sumA_Bv
	.globl	_Z24__device_stub__Z6mulA_Bvv
	.type	_Z24__device_stub__Z6mulA_Bvv, @function
_Z24__device_stub__Z6mulA_Bvv:
.LFB2056:
	.cfi_startproc
	endbr64
	subq	$88, %rsp
	.cfi_def_cfa_offset 96
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	movabsq	$4294967297, %rax
	leaq	8(%rsp), %rcx
	movq	%rsp, %rdx
	leaq	28(%rsp), %rsi
	leaq	16(%rsp), %rdi
	movl	$1, 24(%rsp)
	movl	$1, 36(%rsp)
	movq	%rax, 16(%rsp)
	movq	%rax, 28(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L13
	pushq	8(%rsp)
	.cfi_def_cfa_offset 104
	leaq	_Z6mulA_Bv(%rip), %rdi
	pushq	8(%rsp)
	.cfi_def_cfa_offset 112
	movq	44(%rsp), %rcx
	movl	52(%rsp), %r8d
	movq	32(%rsp), %rsi
	movl	40(%rsp), %edx
	leaq	80(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 104
	popq	%rdx
	.cfi_def_cfa_offset 96
.L13:
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L15
	call	__stack_chk_fail@PLT
.L15:
	addq	$88, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2056:
	.size	_Z24__device_stub__Z6mulA_Bvv, .-_Z24__device_stub__Z6mulA_Bvv
	.globl	_Z6mulA_Bv
	.type	_Z6mulA_Bv, @function
_Z6mulA_Bv:
.LFB2057:
	.cfi_startproc
	endbr64
	jmp	_Z24__device_stub__Z6mulA_Bvv
	.cfi_endproc
.LFE2057:
	.size	_Z6mulA_Bv, .-_Z6mulA_Bv
	.globl	_Z31__device_stub__Z12mulA_ESCALARvv
	.type	_Z31__device_stub__Z12mulA_ESCALARvv, @function
_Z31__device_stub__Z12mulA_ESCALARvv:
.LFB2058:
	.cfi_startproc
	endbr64
	subq	$88, %rsp
	.cfi_def_cfa_offset 96
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	movabsq	$4294967297, %rax
	leaq	8(%rsp), %rcx
	movq	%rsp, %rdx
	leaq	28(%rsp), %rsi
	leaq	16(%rsp), %rdi
	movl	$1, 24(%rsp)
	movl	$1, 36(%rsp)
	movq	%rax, 16(%rsp)
	movq	%rax, 28(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L18
	pushq	8(%rsp)
	.cfi_def_cfa_offset 104
	leaq	_Z12mulA_ESCALARv(%rip), %rdi
	pushq	8(%rsp)
	.cfi_def_cfa_offset 112
	movq	44(%rsp), %rcx
	movl	52(%rsp), %r8d
	movq	32(%rsp), %rsi
	movl	40(%rsp), %edx
	leaq	80(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 104
	popq	%rdx
	.cfi_def_cfa_offset 96
.L18:
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L20
	call	__stack_chk_fail@PLT
.L20:
	addq	$88, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2058:
	.size	_Z31__device_stub__Z12mulA_ESCALARvv, .-_Z31__device_stub__Z12mulA_ESCALARvv
	.globl	_Z12mulA_ESCALARv
	.type	_Z12mulA_ESCALARv, @function
_Z12mulA_ESCALARv:
.LFB2059:
	.cfi_startproc
	endbr64
	jmp	_Z31__device_stub__Z12mulA_ESCALARvv
	.cfi_endproc
.LFE2059:
	.size	_Z12mulA_ESCALARv, .-_Z12mulA_ESCALARv
	.globl	_Z24__device_stub__Z6mulB_Vvv
	.type	_Z24__device_stub__Z6mulB_Vvv, @function
_Z24__device_stub__Z6mulB_Vvv:
.LFB2060:
	.cfi_startproc
	endbr64
	subq	$88, %rsp
	.cfi_def_cfa_offset 96
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	movabsq	$4294967297, %rax
	leaq	8(%rsp), %rcx
	movq	%rsp, %rdx
	leaq	28(%rsp), %rsi
	leaq	16(%rsp), %rdi
	movl	$1, 24(%rsp)
	movl	$1, 36(%rsp)
	movq	%rax, 16(%rsp)
	movq	%rax, 28(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L23
	pushq	8(%rsp)
	.cfi_def_cfa_offset 104
	leaq	_Z6mulB_Vv(%rip), %rdi
	pushq	8(%rsp)
	.cfi_def_cfa_offset 112
	movq	44(%rsp), %rcx
	movl	52(%rsp), %r8d
	movq	32(%rsp), %rsi
	movl	40(%rsp), %edx
	leaq	80(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 104
	popq	%rdx
	.cfi_def_cfa_offset 96
.L23:
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L25
	call	__stack_chk_fail@PLT
.L25:
	addq	$88, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2060:
	.size	_Z24__device_stub__Z6mulB_Vvv, .-_Z24__device_stub__Z6mulB_Vvv
	.globl	_Z6mulB_Vv
	.type	_Z6mulB_Vv, @function
_Z6mulB_Vv:
.LFB2061:
	.cfi_startproc
	endbr64
	jmp	_Z24__device_stub__Z6mulB_Vvv
	.cfi_endproc
.LFE2061:
	.size	_Z6mulB_Vv, .-_Z6mulB_Vv
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"Somar A e B e armazenar em C.\n"
.LC2:
	.string	"Feito em %.3f segundos.\n"
.LC3:
	.string	"Multiplicar A e B e armazenar em D.\n"
.LC4:
	.string	"Multiplicar A e ESCALAR e armazenar em A.\n"
.LC5:
	.string	"Multiplicar B e V e armazenar em VET.\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	xorl	%edi, %edi
	pushq	%rbx
	.cfi_def_cfa_offset 24
	.cfi_offset 3, -24
	subq	$40, %rsp
	.cfi_def_cfa_offset 64
	call	cudaSetDevice@PLT
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$1, %ecx
	movabsq	$4294967297, %rdi
	movl	$1, %esi
	movl	$1, 28(%rsp)
	movq	%rdi, %rdx
	movq	%rdi, 20(%rsp)
	movq	%rdi, 8(%rsp)
	movl	$1, 16(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L29
	call	_Z22__device_stub__Z4loadvv
.L29:
	call	cudaDeviceSynchronize@PLT
	leaq	.LC0(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	call	clock@PLT
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$1, %ecx
	movl	$1, %esi
	movl	$1, 28(%rsp)
	movq	%rax, %rbx
	movabsq	$128849018910, %rdx
	movabsq	$858993459400, %rdi
	movq	%rdx, 20(%rsp)
	movq	%rdi, 8(%rsp)
	movl	$1, 16(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L30
	call	_Z24__device_stub__Z6sumA_Bvv
.L30:
	call	cudaDeviceSynchronize@PLT
	call	clock@PLT
	movl	$2, %edi
	subq	%rbx, %rax
	leaq	.LC2(%rip), %rbx
	cvtsi2sdq	%rax, %xmm0
	movq	%rbx, %rsi
	movb	$1, %al
	divsd	.LC1(%rip), %xmm0
	call	__printf_chk@PLT
	leaq	.LC3(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	call	clock@PLT
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$1, %ecx
	movl	$1, %esi
	movl	$1, 28(%rsp)
	movq	%rax, %rbp
	movabsq	$128849018910, %rdx
	movabsq	$858993459400, %rdi
	movq	%rdx, 20(%rsp)
	movq	%rdi, 8(%rsp)
	movl	$1, 16(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L31
	call	_Z24__device_stub__Z6mulA_Bvv
.L31:
	call	cudaDeviceSynchronize@PLT
	call	clock@PLT
	movq	%rbx, %rsi
	movl	$2, %edi
	subq	%rbp, %rax
	cvtsi2sdq	%rax, %xmm0
	movb	$1, %al
	divsd	.LC1(%rip), %xmm0
	call	__printf_chk@PLT
	leaq	.LC4(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	call	clock@PLT
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$1, %ecx
	movl	$1, %esi
	movl	$1, 28(%rsp)
	movq	%rax, %rbp
	movabsq	$128849018910, %rdx
	movabsq	$858993459400, %rdi
	movq	%rdx, 20(%rsp)
	movq	%rdi, 8(%rsp)
	movl	$1, 16(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L32
	call	_Z31__device_stub__Z12mulA_ESCALARvv
.L32:
	call	cudaDeviceSynchronize@PLT
	call	clock@PLT
	movq	%rbx, %rsi
	movl	$2, %edi
	subq	%rbp, %rax
	cvtsi2sdq	%rax, %xmm0
	movb	$1, %al
	divsd	.LC1(%rip), %xmm0
	call	__printf_chk@PLT
	leaq	.LC5(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	call	clock@PLT
	movl	$2147483663, %edx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$536870937, %edi
	addq	%rdx, %rdx
	movl	$1, %ecx
	movq	%rax, %rbp
	salq	$3, %rdi
	movl	$1, %esi
	movq	%rdx, 20(%rsp)
	movl	$1, 28(%rsp)
	movq	%rdi, 8(%rsp)
	movl	$1, 16(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L33
	call	_Z24__device_stub__Z6mulB_Vvv
.L33:
	call	cudaDeviceSynchronize@PLT
	call	clock@PLT
	movq	%rbx, %rsi
	movl	$2, %edi
	subq	%rbp, %rax
	cvtsi2sdq	%rax, %xmm0
	movb	$1, %al
	divsd	.LC1(%rip), %xmm0
	call	__printf_chk@PLT
	addq	$40, %rsp
	.cfi_def_cfa_offset 24
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2027:
	.size	main, .-main
	.section	.rodata.str1.1
.LC6:
	.string	"_Z6mulB_Vv"
.LC7:
	.string	"_Z12mulA_ESCALARv"
.LC8:
	.string	"_Z6mulA_Bv"
.LC9:
	.string	"_Z6sumA_Bv"
.LC10:
	.string	"_Z4loadv"
.LC11:
	.string	"d_A"
.LC12:
	.string	"d_B"
.LC13:
	.string	"d_C"
.LC14:
	.string	"d_D"
.LC15:
	.string	"d_V"
.LC16:
	.string	"d_VET"
.LC17:
	.string	"ESCALAR"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2063:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC6(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z6mulB_Vv(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC7(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z12mulA_ESCALARv(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC8(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z6mulA_Bv(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC9(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z6sumA_Bv(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC10(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z4loadv(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC11(%rip), %rdx
	movl	$144000000, %r9d
	leaq	_ZL3d_A(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC12(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$144000000, %r9d
	leaq	_ZL3d_B(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC13(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$144000000, %r9d
	leaq	_ZL3d_C(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	popq	%r8
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC14(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$144000000, %r9d
	leaq	_ZL3d_D(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r9
	.cfi_def_cfa_offset 24
	popq	%r10
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC15(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$24000, %r9d
	leaq	_ZL3d_V(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r11
	.cfi_def_cfa_offset 24
	popq	%rax
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC16(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$24000, %r9d
	leaq	_ZL5d_VET(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC17(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$4, %r9d
	leaq	_ZL7ESCALAR(%rip), %rsi
	call	__cudaRegisterVar@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2063:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.local	_ZL7ESCALAR
	.comm	_ZL7ESCALAR,4,4
	.local	_ZL5d_VET
	.comm	_ZL5d_VET,24000,32
	.local	_ZL3d_V
	.comm	_ZL3d_V,24000,32
	.local	_ZL3d_D
	.comm	_ZL3d_D,144000000,32
	.local	_ZL3d_C
	.comm	_ZL3d_C,144000000,32
	.local	_ZL3d_B
	.comm	_ZL3d_B,144000000,32
	.local	_ZL3d_A
	.comm	_ZL3d_A,144000000,32
	.section	.rodata.cst8,"aM",@progbits,8
	.align 8
.LC1:
	.long	0
	.long	1093567616
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <hip/hip_runtime.h>

#define THREADS 30
#define BLOCKS 200
#define SIZE 6000

__device__ float d_A[SIZE][SIZE];
__device__ float d_B[SIZE][SIZE];
__device__ float d_C[SIZE][SIZE];
__device__ float d_D[SIZE][SIZE];
__device__ float d_V[SIZE];
__device__ float d_VET[SIZE];
__device__ float ESCALAR = 1.25;

__global__ void load()
{
    for(int i = 0; i < SIZE; i++)
    {
        for(int j = 0; j < SIZE; j++) 
        {
            d_A[i][j] = i + j;
            d_B[i][j] = i + j;
            d_C[i][j] = 0;
            d_D[i][j] = 0;
        }

        d_V[i] = i;
        d_VET[i] = 0;
    }
}

__global__ void sumA_B()
{
    int i = blockIdx.x * blockDim.x + threadIdx.x;
    int j = blockIdx.y * blockDim.y + threadIdx.y;

    if(i < SIZE && j < SIZE)
        d_C[i][j] = d_A[i][j] + d_B[i][j];
}

__global__ void mulA_B()
{
    int i = blockIdx.x * blockDim.x + threadIdx.x;
    int j = blockIdx.y * blockDim.y + threadIdx.y;

    if(i < SIZE && j < SIZE)
    {
        for(int k = 0; k < SIZE; k++) 
            d_D[i][j] += d_A[i][k] * d_B[k][j];
    }
}

__global__ void mulA_ESCALAR()
{
    int i = blockIdx.x * blockDim.x + threadIdx.x;
    int j = blockIdx.y * blockDim.y + threadIdx.y;

    if(i < SIZE && j < SIZE)
        d_A[i][j] *= ESCALAR;
}

__global__ void mulB_V()
{
    int i = blockIdx.x * blockDim.x + threadIdx.x;

    if(i < SIZE)
    {
        for(int j = 0; j < SIZE; j++)
            d_VET[i] += d_B[i][j] * d_V[j];
    }
}

int main()
{  
    clock_t begin, end;

    hipSetDevice(0);  
    load<<<1, 1>>>();
    hipDeviceSynchronize();
    
    printf("Somar A e B e armazenar em C.\n");
    begin = clock();
    sumA_B<<<dim3(BLOCKS, BLOCKS), dim3(THREADS, THREADS)>>>();
    hipDeviceSynchronize();
    end = clock();
    printf("Feito em %.3f segundos.\n", double(end - begin) / CLOCKS_PER_SEC);

    printf("Multiplicar A e B e armazenar em D.\n");
    begin = clock();
    mulA_B<<<dim3(BLOCKS, BLOCKS), dim3(THREADS, THREADS)>>>();
    hipDeviceSynchronize();
    end = clock();
    printf("Feito em %.3f segundos.\n", double(end - begin) / CLOCKS_PER_SEC);

    printf("Multiplicar A e ESCALAR e armazenar em A.\n");
    begin = clock();
    mulA_ESCALAR<<<dim3(BLOCKS, BLOCKS), dim3(THREADS, THREADS)>>>();
    hipDeviceSynchronize();
    end = clock();
    printf("Feito em %.3f segundos.\n", double(end - begin) / CLOCKS_PER_SEC);
    
    printf("Multiplicar B e V e armazenar em VET.\n");
    begin = clock();
    mulB_V<<<BLOCKS, THREADS>>>();    
    hipDeviceSynchronize();
    end = clock();
    printf("Feito em %.3f segundos.\n", double(end - begin) / CLOCKS_PER_SEC);
}
	.text
	.file	"main.hip"
	.globl	_Z19__device_stub__loadv        # -- Begin function _Z19__device_stub__loadv
	.type	_Z19__device_stub__loadv,@function
_Z19__device_stub__loadv:               # @_Z19__device_stub__loadv
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r12
	.cfi_def_cfa_offset 32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	subq	$56, %rsp
	.cfi_def_cfa_offset 96
	.cfi_offset %rbx, -40
	.cfi_offset %r12, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rbx
	leaq	24(%rsp), %r14
	leaq	16(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rbx, %rdi
	movq	%r14, %rsi
	movq	%r15, %rdx
	movq	%r12, %rcx
	callq	__hipPopCallConfiguration
	movq	(%rbx), %rsi
	movl	8(%rbx), %edx
	movq	(%r14), %rcx
	movl	8(%r14), %r8d
	movq	%rsp, %r9
	movl	$_Z4loadv, %edi
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	pushq	(%r15)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$72, %rsp
	.cfi_adjust_cfa_offset -72
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z19__device_stub__loadv, .Lfunc_end0-_Z19__device_stub__loadv
	.cfi_endproc
                                        # -- End function
	.globl	_Z21__device_stub__sumA_Bv      # -- Begin function _Z21__device_stub__sumA_Bv
	.type	_Z21__device_stub__sumA_Bv,@function
_Z21__device_stub__sumA_Bv:             # @_Z21__device_stub__sumA_Bv
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r12
	.cfi_def_cfa_offset 32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	subq	$56, %rsp
	.cfi_def_cfa_offset 96
	.cfi_offset %rbx, -40
	.cfi_offset %r12, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rbx
	leaq	24(%rsp), %r14
	leaq	16(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rbx, %rdi
	movq	%r14, %rsi
	movq	%r15, %rdx
	movq	%r12, %rcx
	callq	__hipPopCallConfiguration
	movq	(%rbx), %rsi
	movl	8(%rbx), %edx
	movq	(%r14), %rcx
	movl	8(%r14), %r8d
	movq	%rsp, %r9
	movl	$_Z6sumA_Bv, %edi
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	pushq	(%r15)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$72, %rsp
	.cfi_adjust_cfa_offset -72
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z21__device_stub__sumA_Bv, .Lfunc_end1-_Z21__device_stub__sumA_Bv
	.cfi_endproc
                                        # -- End function
	.globl	_Z21__device_stub__mulA_Bv      # -- Begin function _Z21__device_stub__mulA_Bv
	.type	_Z21__device_stub__mulA_Bv,@function
_Z21__device_stub__mulA_Bv:             # @_Z21__device_stub__mulA_Bv
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r12
	.cfi_def_cfa_offset 32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	subq	$56, %rsp
	.cfi_def_cfa_offset 96
	.cfi_offset %rbx, -40
	.cfi_offset %r12, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rbx
	leaq	24(%rsp), %r14
	leaq	16(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rbx, %rdi
	movq	%r14, %rsi
	movq	%r15, %rdx
	movq	%r12, %rcx
	callq	__hipPopCallConfiguration
	movq	(%rbx), %rsi
	movl	8(%rbx), %edx
	movq	(%r14), %rcx
	movl	8(%r14), %r8d
	movq	%rsp, %r9
	movl	$_Z6mulA_Bv, %edi
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	pushq	(%r15)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$72, %rsp
	.cfi_adjust_cfa_offset -72
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z21__device_stub__mulA_Bv, .Lfunc_end2-_Z21__device_stub__mulA_Bv
	.cfi_endproc
                                        # -- End function
	.globl	_Z27__device_stub__mulA_ESCALARv # -- Begin function _Z27__device_stub__mulA_ESCALARv
	.type	_Z27__device_stub__mulA_ESCALARv,@function
_Z27__device_stub__mulA_ESCALARv:       # @_Z27__device_stub__mulA_ESCALARv
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r12
	.cfi_def_cfa_offset 32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	subq	$56, %rsp
	.cfi_def_cfa_offset 96
	.cfi_offset %rbx, -40
	.cfi_offset %r12, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rbx
	leaq	24(%rsp), %r14
	leaq	16(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rbx, %rdi
	movq	%r14, %rsi
	movq	%r15, %rdx
	movq	%r12, %rcx
	callq	__hipPopCallConfiguration
	movq	(%rbx), %rsi
	movl	8(%rbx), %edx
	movq	(%r14), %rcx
	movl	8(%r14), %r8d
	movq	%rsp, %r9
	movl	$_Z12mulA_ESCALARv, %edi
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	pushq	(%r15)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$72, %rsp
	.cfi_adjust_cfa_offset -72
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	_Z27__device_stub__mulA_ESCALARv, .Lfunc_end3-_Z27__device_stub__mulA_ESCALARv
	.cfi_endproc
                                        # -- End function
	.globl	_Z21__device_stub__mulB_Vv      # -- Begin function _Z21__device_stub__mulB_Vv
	.type	_Z21__device_stub__mulB_Vv,@function
_Z21__device_stub__mulB_Vv:             # @_Z21__device_stub__mulB_Vv
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r12
	.cfi_def_cfa_offset 32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	subq	$56, %rsp
	.cfi_def_cfa_offset 96
	.cfi_offset %rbx, -40
	.cfi_offset %r12, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rbx
	leaq	24(%rsp), %r14
	leaq	16(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rbx, %rdi
	movq	%r14, %rsi
	movq	%r15, %rdx
	movq	%r12, %rcx
	callq	__hipPopCallConfiguration
	movq	(%rbx), %rsi
	movl	8(%rbx), %edx
	movq	(%r14), %rcx
	movl	8(%r14), %r8d
	movq	%rsp, %r9
	movl	$_Z6mulB_Vv, %edi
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	pushq	(%r15)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$72, %rsp
	.cfi_adjust_cfa_offset -72
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end4:
	.size	_Z21__device_stub__mulB_Vv, .Lfunc_end4-_Z21__device_stub__mulB_Vv
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0                          # -- Begin function main
.LCPI5_0:
	.quad	0x412e848000000000              # double 1.0E+6
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r12
	.cfi_def_cfa_offset 32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	pushq	%rax
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -40
	.cfi_offset %r12, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movabsq	$4294967297, %rbx               # imm = 0x100000001
	xorl	%edi, %edi
	callq	hipSetDevice
	movq	%rbx, %rdi
	movl	$1, %esi
	movq	%rbx, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB5_2
# %bb.1:
	callq	_Z19__device_stub__loadv
.LBB5_2:
	movabsq	$858993459400, %r15             # imm = 0xC8000000C8
	movabsq	$128849018910, %r14             # imm = 0x1E0000001E
	callq	hipDeviceSynchronize
	movl	$.Lstr, %edi
	callq	puts@PLT
	callq	clock
	movq	%rax, %r12
	movq	%r15, %rdi
	movl	$1, %esi
	movq	%r14, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB5_4
# %bb.3:
	callq	_Z21__device_stub__sumA_Bv
.LBB5_4:
	callq	hipDeviceSynchronize
	callq	clock
	subq	%r12, %rax
	cvtsi2sd	%rax, %xmm0
	divsd	.LCPI5_0(%rip), %xmm0
	movl	$.L.str.1, %edi
	movb	$1, %al
	callq	printf
	movl	$.Lstr.1, %edi
	callq	puts@PLT
	callq	clock
	movq	%rax, %r12
	movq	%r15, %rdi
	movl	$1, %esi
	movq	%r14, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB5_6
# %bb.5:
	callq	_Z21__device_stub__mulA_Bv
.LBB5_6:
	callq	hipDeviceSynchronize
	callq	clock
	subq	%r12, %rax
	xorps	%xmm0, %xmm0
	cvtsi2sd	%rax, %xmm0
	divsd	.LCPI5_0(%rip), %xmm0
	movl	$.L.str.1, %edi
	movb	$1, %al
	callq	printf
	movl	$.Lstr.2, %edi
	callq	puts@PLT
	callq	clock
	movq	%rax, %r12
	movq	%r15, %rdi
	movl	$1, %esi
	movq	%r14, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB5_8
# %bb.7:
	callq	_Z27__device_stub__mulA_ESCALARv
.LBB5_8:
	callq	hipDeviceSynchronize
	callq	clock
	subq	%r12, %rax
	xorps	%xmm0, %xmm0
	cvtsi2sd	%rax, %xmm0
	divsd	.LCPI5_0(%rip), %xmm0
	movl	$.L.str.1, %edi
	movb	$1, %al
	callq	printf
	movl	$.Lstr.3, %edi
	callq	puts@PLT
	callq	clock
	movq	%rax, %r14
	leaq	29(%rbx), %rdx
	addq	$199, %rbx
	movq	%rbx, %rdi
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB5_10
# %bb.9:
	callq	_Z21__device_stub__mulB_Vv
.LBB5_10:
	callq	hipDeviceSynchronize
	callq	clock
	subq	%r14, %rax
	xorps	%xmm0, %xmm0
	cvtsi2sd	%rax, %xmm0
	divsd	.LCPI5_0(%rip), %xmm0
	movl	$.L.str.1, %edi
	movb	$1, %al
	callq	printf
	xorl	%eax, %eax
	addq	$8, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end5:
	.size	main, .Lfunc_end5-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB6_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB6_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z4loadv, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z6sumA_Bv, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z6mulA_Bv, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z12mulA_ESCALARv, %esi
	movl	$.L__unnamed_4, %edx
	movl	$.L__unnamed_4, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z6mulB_Vv, %esi
	movl	$.L__unnamed_5, %edx
	movl	$.L__unnamed_5, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$0, 8(%rsp)
	movl	$0, (%rsp)
	movl	$d_A, %esi
	movl	$.L__unnamed_6, %edx
	movl	$.L__unnamed_6, %ecx
	movl	$144000000, %r9d                # imm = 0x8954400
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	callq	__hipRegisterVar
	movl	$0, 8(%rsp)
	movl	$0, (%rsp)
	movl	$d_B, %esi
	movl	$.L__unnamed_7, %edx
	movl	$.L__unnamed_7, %ecx
	movl	$144000000, %r9d                # imm = 0x8954400
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	callq	__hipRegisterVar
	movl	$0, 8(%rsp)
	movl	$0, (%rsp)
	movl	$d_C, %esi
	movl	$.L__unnamed_8, %edx
	movl	$.L__unnamed_8, %ecx
	movl	$144000000, %r9d                # imm = 0x8954400
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	callq	__hipRegisterVar
	movl	$0, 8(%rsp)
	movl	$0, (%rsp)
	movl	$d_D, %esi
	movl	$.L__unnamed_9, %edx
	movl	$.L__unnamed_9, %ecx
	movl	$144000000, %r9d                # imm = 0x8954400
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	callq	__hipRegisterVar
	movl	$0, 8(%rsp)
	movl	$0, (%rsp)
	movl	$d_V, %esi
	movl	$.L__unnamed_10, %edx
	movl	$.L__unnamed_10, %ecx
	movl	$24000, %r9d                    # imm = 0x5DC0
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	callq	__hipRegisterVar
	movl	$0, 8(%rsp)
	movl	$0, (%rsp)
	movl	$d_VET, %esi
	movl	$.L__unnamed_11, %edx
	movl	$.L__unnamed_11, %ecx
	movl	$24000, %r9d                    # imm = 0x5DC0
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	callq	__hipRegisterVar
	movl	$0, 8(%rsp)
	movl	$0, (%rsp)
	movl	$ESCALAR, %esi
	movl	$.L__unnamed_12, %edx
	movl	$.L__unnamed_12, %ecx
	movl	$4, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	callq	__hipRegisterVar
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end6:
	.size	__hip_module_ctor, .Lfunc_end6-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB7_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB7_2:
	retq
.Lfunc_end7:
	.size	__hip_module_dtor, .Lfunc_end7-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	d_A,@object                     # @d_A
	.local	d_A
	.comm	d_A,144000000,16
	.type	d_B,@object                     # @d_B
	.local	d_B
	.comm	d_B,144000000,16
	.type	d_C,@object                     # @d_C
	.local	d_C
	.comm	d_C,144000000,16
	.type	d_D,@object                     # @d_D
	.local	d_D
	.comm	d_D,144000000,16
	.type	d_V,@object                     # @d_V
	.local	d_V
	.comm	d_V,24000,16
	.type	d_VET,@object                   # @d_VET
	.local	d_VET
	.comm	d_VET,24000,16
	.type	ESCALAR,@object                 # @ESCALAR
	.local	ESCALAR
	.comm	ESCALAR,4,4
	.type	_Z4loadv,@object                # @_Z4loadv
	.section	.rodata,"a",@progbits
	.globl	_Z4loadv
	.p2align	3, 0x0
_Z4loadv:
	.quad	_Z19__device_stub__loadv
	.size	_Z4loadv, 8

	.type	_Z6sumA_Bv,@object              # @_Z6sumA_Bv
	.globl	_Z6sumA_Bv
	.p2align	3, 0x0
_Z6sumA_Bv:
	.quad	_Z21__device_stub__sumA_Bv
	.size	_Z6sumA_Bv, 8

	.type	_Z6mulA_Bv,@object              # @_Z6mulA_Bv
	.globl	_Z6mulA_Bv
	.p2align	3, 0x0
_Z6mulA_Bv:
	.quad	_Z21__device_stub__mulA_Bv
	.size	_Z6mulA_Bv, 8

	.type	_Z12mulA_ESCALARv,@object       # @_Z12mulA_ESCALARv
	.globl	_Z12mulA_ESCALARv
	.p2align	3, 0x0
_Z12mulA_ESCALARv:
	.quad	_Z27__device_stub__mulA_ESCALARv
	.size	_Z12mulA_ESCALARv, 8

	.type	_Z6mulB_Vv,@object              # @_Z6mulB_Vv
	.globl	_Z6mulB_Vv
	.p2align	3, 0x0
_Z6mulB_Vv:
	.quad	_Z21__device_stub__mulB_Vv
	.size	_Z6mulB_Vv, 8

	.type	.L.str.1,@object                # @.str.1
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str.1:
	.asciz	"Feito em %.3f segundos.\n"
	.size	.L.str.1, 25

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z4loadv"
	.size	.L__unnamed_1, 9

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z6sumA_Bv"
	.size	.L__unnamed_2, 11

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z6mulA_Bv"
	.size	.L__unnamed_3, 11

	.type	.L__unnamed_4,@object           # @3
.L__unnamed_4:
	.asciz	"_Z12mulA_ESCALARv"
	.size	.L__unnamed_4, 18

	.type	.L__unnamed_5,@object           # @4
.L__unnamed_5:
	.asciz	"_Z6mulB_Vv"
	.size	.L__unnamed_5, 11

	.type	.L__unnamed_6,@object           # @5
.L__unnamed_6:
	.asciz	"d_A"
	.size	.L__unnamed_6, 4

	.type	.L__unnamed_7,@object           # @6
.L__unnamed_7:
	.asciz	"d_B"
	.size	.L__unnamed_7, 4

	.type	.L__unnamed_8,@object           # @7
.L__unnamed_8:
	.asciz	"d_C"
	.size	.L__unnamed_8, 4

	.type	.L__unnamed_9,@object           # @8
.L__unnamed_9:
	.asciz	"d_D"
	.size	.L__unnamed_9, 4

	.type	.L__unnamed_10,@object          # @9
.L__unnamed_10:
	.asciz	"d_V"
	.size	.L__unnamed_10, 4

	.type	.L__unnamed_11,@object          # @10
.L__unnamed_11:
	.asciz	"d_VET"
	.size	.L__unnamed_11, 6

	.type	.L__unnamed_12,@object          # @11
.L__unnamed_12:
	.asciz	"ESCALAR"
	.size	.L__unnamed_12, 8

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.type	.Lstr,@object                   # @str
	.section	.rodata.str1.1,"aMS",@progbits,1
.Lstr:
	.asciz	"Somar A e B e armazenar em C."
	.size	.Lstr, 30

	.type	.Lstr.1,@object                 # @str.1
.Lstr.1:
	.asciz	"Multiplicar A e B e armazenar em D."
	.size	.Lstr.1, 36

	.type	.Lstr.2,@object                 # @str.2
.Lstr.2:
	.asciz	"Multiplicar A e ESCALAR e armazenar em A."
	.size	.Lstr.2, 42

	.type	.Lstr.3,@object                 # @str.3
.Lstr.3:
	.asciz	"Multiplicar B e V e armazenar em VET."
	.size	.Lstr.3, 38

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z19__device_stub__loadv
	.addrsig_sym _Z21__device_stub__sumA_Bv
	.addrsig_sym _Z21__device_stub__mulA_Bv
	.addrsig_sym _Z27__device_stub__mulA_ESCALARv
	.addrsig_sym _Z21__device_stub__mulB_Vv
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym d_A
	.addrsig_sym d_B
	.addrsig_sym d_C
	.addrsig_sym d_D
	.addrsig_sym d_V
	.addrsig_sym d_VET
	.addrsig_sym ESCALAR
	.addrsig_sym _Z4loadv
	.addrsig_sym _Z6sumA_Bv
	.addrsig_sym _Z6mulA_Bv
	.addrsig_sym _Z12mulA_ESCALARv
	.addrsig_sym _Z6mulB_Vv
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z4loadv                ; -- Begin function _Z4loadv
	.globl	_Z4loadv
	.p2align	8
	.type	_Z4loadv,@function
_Z4loadv:                               ; @_Z4loadv
; %bb.0:
	v_mov_b32_e32 v0, 0
	s_mov_b32 s9, 0
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, d_A@rel32@lo+4
	s_addc_u32 s1, s1, d_A@rel32@hi+12
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, d_B@rel32@lo+4
	s_addc_u32 s3, s3, d_B@rel32@hi+12
	s_mov_b32 s8, s9
	s_getpc_b64 s[4:5]
	s_add_u32 s4, s4, d_C@rel32@lo+4
	s_addc_u32 s5, s5, d_C@rel32@hi+12
	s_getpc_b64 s[6:7]
	s_add_u32 s6, s6, d_D@rel32@lo+4
	s_addc_u32 s7, s7, d_D@rel32@hi+12
.LBB0_1:                                ; %.preheader
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_2 Depth 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b64 s[10:11], s[6:7]
	s_mov_b64 s[12:13], s[4:5]
	s_mov_b64 s[14:15], s[2:3]
	s_mov_b64 s[16:17], s[0:1]
	s_mov_b32 s18, s9
.LBB0_2:                                ;   Parent Loop BB0_1 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_i32 s19, s8, s18
	s_add_i32 s18, s18, 1
	v_cvt_f32_i32_e32 v1, s19
	s_clause 0x3
	global_store_b32 v0, v1, s[16:17]
	global_store_b32 v0, v1, s[14:15]
	global_store_b32 v0, v0, s[12:13]
	global_store_b32 v0, v0, s[10:11]
	s_add_u32 s16, s16, 4
	s_addc_u32 s17, s17, 0
	s_add_u32 s14, s14, 4
	s_addc_u32 s15, s15, 0
	s_add_u32 s12, s12, 4
	s_addc_u32 s13, s13, 0
	s_add_u32 s10, s10, 4
	s_addc_u32 s11, s11, 0
	s_cmpk_eq_i32 s18, 0x1770
	s_cbranch_scc0 .LBB0_2
; %bb.3:                                ;   in Loop: Header=BB0_1 Depth=1
	s_getpc_b64 s[10:11]
	s_add_u32 s10, s10, d_V@rel32@lo+4
	s_addc_u32 s11, s11, d_V@rel32@hi+12
	s_lshl_b64 s[12:13], s[8:9], 2
	v_cvt_f32_i32_e32 v1, s8
	s_add_u32 s10, s12, s10
	s_addc_u32 s11, s13, s11
	s_getpc_b64 s[14:15]
	s_add_u32 s14, s14, d_VET@rel32@lo+4
	s_addc_u32 s15, s15, d_VET@rel32@hi+12
	s_add_u32 s12, s12, s14
	s_addc_u32 s13, s13, s15
	s_add_i32 s8, s8, 1
	s_add_u32 s0, s0, 0x5dc0
	s_addc_u32 s1, s1, 0
	s_add_u32 s2, s2, 0x5dc0
	s_addc_u32 s3, s3, 0
	s_add_u32 s4, s4, 0x5dc0
	s_addc_u32 s5, s5, 0
	s_add_u32 s6, s6, 0x5dc0
	s_addc_u32 s7, s7, 0
	s_cmpk_eq_i32 s8, 0x1770
	s_clause 0x1
	global_store_b32 v0, v1, s[10:11]
	global_store_b32 v0, v0, s[12:13]
	s_cbranch_scc0 .LBB0_1
; %bb.4:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z4loadv
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 0
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 0
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 2
		.amdhsa_next_free_sgpr 20
		.amdhsa_reserve_vcc 0
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z4loadv, .Lfunc_end0-_Z4loadv
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 364
; NumSgprs: 20
; NumVgprs: 2
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 20
; NumVGPRsForWavesPerEU: 2
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z6sumA_Bv              ; -- Begin function _Z6sumA_Bv
	.globl	_Z6sumA_Bv
	.p2align	8
	.type	_Z6sumA_Bv,@function
_Z6sumA_Bv:                             ; @_Z6sumA_Bv
; %bb.0:
	s_load_b32 s0, s[0:1], 0xc
	v_and_b32_e32 v1, 0x3ff, v0
	v_bfe_u32 v4, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s1, s0, 16
	s_and_b32 s0, s0, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[2:3], null, s14, s0, v[1:2]
	v_mad_u64_u32 v[0:1], null, s15, s1, v[4:5]
	s_mov_b32 s0, exec_lo
	v_max_i32_e32 v1, v2, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e32 0x1770, v1
	s_cbranch_execz .LBB1_2
; %bb.1:
	v_ashrrev_i32_e32 v1, 31, v0
	v_mad_i64_i32 v[3:4], null, 0x5dc0, v2, 0
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, d_A@rel32@lo+4
	s_addc_u32 s1, s1, d_A@rel32@hi+12
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, d_B@rel32@lo+4
	s_addc_u32 s3, s3, d_B@rel32@hi+12
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v5, vcc_lo, v3, v0
	v_add_co_ci_u32_e32 v4, vcc_lo, v4, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v5, s0
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v4, vcc_lo
	v_add_co_u32 v2, vcc_lo, v5, s2
	v_add_co_ci_u32_e32 v3, vcc_lo, s3, v4, vcc_lo
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, d_C@rel32@lo+4
	s_addc_u32 s1, s1, d_C@rel32@hi+12
	global_load_b32 v6, v[0:1], off
	global_load_b32 v2, v[2:3], off
	v_add_co_u32 v0, vcc_lo, v5, s0
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v4, vcc_lo
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v2, v6, v2
	global_store_b32 v[0:1], v2, off
.LBB1_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z6sumA_Bv
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 256
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 7
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z6sumA_Bv, .Lfunc_end1-_Z6sumA_Bv
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 268
; NumSgprs: 18
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z6mulA_Bv              ; -- Begin function _Z6mulA_Bv
	.globl	_Z6mulA_Bv
	.p2align	8
	.type	_Z6mulA_Bv,@function
_Z6mulA_Bv:                             ; @_Z6mulA_Bv
; %bb.0:
	s_load_b32 s0, s[0:1], 0xc
	v_and_b32_e32 v1, 0x3ff, v0
	v_bfe_u32 v2, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s1, s0, 16
	s_and_b32 s0, s0, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[4:5], null, s14, s0, v[1:2]
	v_mad_u64_u32 v[0:1], null, s15, s1, v[2:3]
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_max_i32_e32 v1, v4, v0
	v_cmpx_gt_i32_e32 0x1770, v1
	s_cbranch_execz .LBB2_4
; %bb.1:                                ; %.preheader
	v_ashrrev_i32_e32 v1, 31, v0
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, d_D@rel32@lo+4
	s_addc_u32 s1, s1, d_D@rel32@hi+12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[7:8], 2, v[0:1]
	v_mad_i64_i32 v[0:1], null, 0x5dc0, v4, v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, s0
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, d_A@rel32@lo+4
	s_addc_u32 s1, s1, d_A@rel32@hi+12
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, d_B@rel32@lo+4
	s_addc_u32 s3, s3, d_B@rel32@hi+12
	v_mad_i64_i32 v[2:3], null, 0x5dc0, v4, s[0:1]
	global_load_b32 v6, v[0:1], off
	v_add_co_u32 v4, vcc_lo, v7, s2
	v_add_co_ci_u32_e32 v5, vcc_lo, s3, v8, vcc_lo
	s_mov_b64 s[0:1], 0
.LBB2_2:                                ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	v_add_co_u32 v7, vcc_lo, v2, s0
	v_add_co_ci_u32_e32 v8, vcc_lo, s1, v3, vcc_lo
	s_add_u32 s0, s0, 4
	s_addc_u32 s1, s1, 0
	global_load_b32 v9, v[4:5], off
	global_load_b32 v7, v[7:8], off
	v_add_co_u32 v4, vcc_lo, 0x5dc0, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
	s_cmpk_lg_i32 s0, 0x5dc0
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v6, v7, v9
	s_cbranch_scc1 .LBB2_2
; %bb.3:                                ; %.loopexit
	global_store_b32 v[0:1], v6, off
.LBB2_4:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z6mulA_Bv
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 256
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 10
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_Z6mulA_Bv, .Lfunc_end2-_Z6mulA_Bv
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 316
; NumSgprs: 18
; NumVgprs: 10
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 10
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z12mulA_ESCALARv       ; -- Begin function _Z12mulA_ESCALARv
	.globl	_Z12mulA_ESCALARv
	.p2align	8
	.type	_Z12mulA_ESCALARv,@function
_Z12mulA_ESCALARv:                      ; @_Z12mulA_ESCALARv
; %bb.0:
	s_load_b32 s0, s[0:1], 0xc
	v_and_b32_e32 v2, 0x3ff, v0
	v_bfe_u32 v3, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s1, s0, 16
	s_and_b32 s0, s0, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[0:1], null, s14, s0, v[2:3]
	v_mad_u64_u32 v[1:2], null, s15, s1, v[3:4]
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_max_i32_e32 v2, v0, v1
	v_cmpx_gt_i32_e32 0x1770, v2
	s_cbranch_execz .LBB3_2
; %bb.1:
	v_ashrrev_i32_e32 v2, 31, v1
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, d_A@rel32@lo+4
	s_addc_u32 s1, s1, d_A@rel32@hi+12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_mad_i64_i32 v[3:4], null, 0x5dc0, v0, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v3, s0
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v4, vcc_lo
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, ESCALAR@rel32@lo+4
	s_addc_u32 s1, s1, ESCALAR@rel32@hi+12
	s_load_b32 s0, s[0:1], 0x0
	global_load_b32 v2, v[0:1], off
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_mul_f32_e32 v2, s0, v2
	global_store_b32 v[0:1], v2, off
.LBB3_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z12mulA_ESCALARv
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 256
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 5
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end3:
	.size	_Z12mulA_ESCALARv, .Lfunc_end3-_Z12mulA_ESCALARv
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 212
; NumSgprs: 18
; NumVgprs: 5
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 5
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z6mulB_Vv              ; -- Begin function _Z6mulB_Vv
	.globl	_Z6mulB_Vv
	.p2align	8
	.type	_Z6mulB_Vv,@function
_Z6mulB_Vv:                             ; @_Z6mulB_Vv
; %bb.0:
	s_load_b32 s0, s[0:1], 0xc
	s_waitcnt lgkmcnt(0)
	s_and_b32 s0, s0, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[4:5], null, s15, s0, v[0:1]
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_i32_e32 0x1770, v4
	s_cbranch_execz .LBB4_4
; %bb.1:                                ; %.preheader
	v_ashrrev_i32_e32 v5, 31, v4
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, d_VET@rel32@lo+4
	s_addc_u32 s1, s1, d_VET@rel32@hi+12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[4:5]
	v_add_co_u32 v0, vcc_lo, v0, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, d_B@rel32@lo+4
	s_addc_u32 s1, s1, d_B@rel32@hi+12
	v_mad_i64_i32 v[2:3], null, 0x5dc0, v4, s[0:1]
	global_load_b32 v5, v[0:1], off
	s_mov_b64 s[0:1], 0
.LBB4_2:                                ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	v_add_co_u32 v6, vcc_lo, v2, s0
	v_add_co_ci_u32_e32 v7, vcc_lo, s1, v3, vcc_lo
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, d_V@rel32@lo+4
	s_addc_u32 s3, s3, d_V@rel32@hi+12
	s_add_u32 s2, s0, s2
	s_addc_u32 s3, s1, s3
	global_load_b32 v4, v[6:7], off
	s_load_b32 s2, s[2:3], 0x0
	s_add_u32 s0, s0, 4
	s_addc_u32 s1, s1, 0
	s_cmpk_lg_i32 s0, 0x5dc0
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_fmac_f32_e32 v5, s2, v4
	s_cbranch_scc1 .LBB4_2
; %bb.3:                                ; %.loopexit
	global_store_b32 v[0:1], v5, off
.LBB4_4:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z6mulB_Vv
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 256
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 8
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end4:
	.size	_Z6mulB_Vv, .Lfunc_end4-_Z6mulB_Vv
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 248
; NumSgprs: 18
; NumVgprs: 8
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 8
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.protected	d_A                     ; @d_A
	.type	d_A,@object
	.section	.bss,"aw",@nobits
	.globl	d_A
	.p2align	4, 0x0
d_A:
	.zero	144000000
	.size	d_A, 144000000

	.protected	d_B                     ; @d_B
	.type	d_B,@object
	.globl	d_B
	.p2align	4, 0x0
d_B:
	.zero	144000000
	.size	d_B, 144000000

	.protected	d_C                     ; @d_C
	.type	d_C,@object
	.globl	d_C
	.p2align	4, 0x0
d_C:
	.zero	144000000
	.size	d_C, 144000000

	.protected	d_D                     ; @d_D
	.type	d_D,@object
	.globl	d_D
	.p2align	4, 0x0
d_D:
	.zero	144000000
	.size	d_D, 144000000

	.protected	d_V                     ; @d_V
	.type	d_V,@object
	.globl	d_V
	.p2align	4, 0x0
d_V:
	.zero	24000
	.size	d_V, 24000

	.protected	d_VET                   ; @d_VET
	.type	d_VET,@object
	.globl	d_VET
	.p2align	4, 0x0
d_VET:
	.zero	24000
	.size	d_VET, 24000

	.protected	ESCALAR                 ; @ESCALAR
	.type	ESCALAR,@object
	.data
	.globl	ESCALAR
	.p2align	2, 0x0
ESCALAR:
	.long	0x3fa00000                      ; float 1.25
	.size	ESCALAR, 4

	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym d_A
	.addrsig_sym d_B
	.addrsig_sym d_C
	.addrsig_sym d_D
	.addrsig_sym d_V
	.addrsig_sym d_VET
	.addrsig_sym ESCALAR
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:           []
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 4
    .kernarg_segment_size: 0
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z4loadv
    .private_segment_fixed_size: 0
    .sgpr_count:     20
    .sgpr_spill_count: 0
    .symbol:         _Z4loadv.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     2
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         4
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         8
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         12
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         14
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         16
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         18
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         20
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         22
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         40
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         48
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         56
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         64
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 256
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z6sumA_Bv
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z6sumA_Bv.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     7
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         4
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         8
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         12
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         14
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         16
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         18
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         20
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         22
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         40
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         48
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         56
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         64
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 256
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z6mulA_Bv
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z6mulA_Bv.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     10
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         4
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         8
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         12
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         14
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         16
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         18
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         20
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         22
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         40
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         48
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         56
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         64
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 256
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z12mulA_ESCALARv
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z12mulA_ESCALARv.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     5
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         4
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         8
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         12
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         14
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         16
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         18
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         20
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         22
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         40
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         48
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         56
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         64
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 256
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z6mulB_Vv
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z6mulB_Vv.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     8
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
