/* 
 * 
 * Jason Yik
 * jyik@usc.edu
 * EE451 Final Project
 *
 * CUDA implementation of DCSC matrix multiplication.
 * Implementation without shared memory.
 * 
 * Run on USC HPC:
 * srun -n1 --gres=gpu:1 ./parallel <n> <nnz>
 *
 * Run with executable in a graphs folder containing n_nnz_x graphs
 *
 */ 

#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <math.h>

#define GRID_WIDTH 128
#define BLOCK_WIDTH 16
#define BLOCK_HEIGHT 32

//TODO: possibly increase block width, decrease block height since there will be max 8 nonzeroes per col on avg

typedef struct {
	char column;
	int *JC;
	int *IR;
	int *NUM;

	int n;   // number of columns
	int nzc; // non zero columns/rows
	int nnz; // number of nonzeroes
} cs_matrix_t;

typedef struct {
	char column;
	int *JC;
	int *CP;
	int *IR;
	int *NUM;

	int n;   // number of columns
	int nzc; // non zero columns/rows
	int nnz; // number of nonzeroes
} dcs_matrix_t;

//uses CUDA unified memory
void cuda_cs(cs_matrix_t *m, const char *file, int n, int nnz, char column, int random_seed) {
	m->column = column;
	m->n = n;

	FILE *fp = fopen(file, "r");
	int bufc, bufr;

	cudaMallocManaged(&(m->JC), sizeof(int) * (n+1));
	cudaMallocManaged(&(m->IR), sizeof(int) * nnz);
	cudaMallocManaged(&(m->NUM), sizeof(int) * nnz);
	
	srand(random_seed);
	//srand(time(0));

	int nzc = 0;

	int i = 0;
	int current_index = 0;
	fscanf(fp, "%d", &bufc);
	while(!feof(fp)) {
		//if blank columns, fill in JC
		while(i < bufc) {
			m->JC[i] = current_index;
			i++;
		}

		m->JC[i] = current_index;
		nzc++;
		while(!feof(fp) && i == bufc) {
			fscanf(fp, "%d", &bufr);
			m->IR[current_index] = bufr;
			m->NUM[current_index] = rand() % 100; 
			current_index++;
			
			fscanf(fp, "%d", &bufc);
		}
		i++;
	}
	//fill in the remainder of JC
	while(i <= n) {
		//current_index should now be greater than size of IR/NUM
		m->JC[i] = current_index; 
		i++;
	}

	m->nnz = current_index;
	m->nzc = nzc;

	fclose(fp);
	return;
}

//uses CUDA unified memory
void cuda_dcs(cs_matrix_t *m, dcs_matrix_t *d) {
	d->column = m->column;
	d->IR = m->IR;
	d->NUM = m->NUM;

	d->n = m->n;
	d->nnz = m->nnz;
	d->nzc = m->nzc;

	cudaMallocManaged(&(d->JC), sizeof(int) * m->nzc);
	cudaMallocManaged(&(d->CP), sizeof(int) * (m->nzc +1));

	int current_index = 0;
	for(int i = 0; i < m->n; i++) {
		if(m->JC[i] == m->JC[i+1]) {
			continue;
		}
		else {
			d->JC[current_index] = i;
			d->CP[current_index] = m->JC[i];
			current_index++;
		}
	}
	d->CP[current_index] = m->nnz;

	//invalidate m
	cudaFree(m->JC);

	return;
}

__device__ int binary_search(int *arr, int len, int target) {
	int left = 0;
	int right = len -1;
	int mid;

	while(left <= right) {
		mid = (left + right)/2;
		if(arr[mid] == target) return mid;
		if(arr[mid] < target) {
			left = mid +1;
			continue;
		}
		if(arr[mid] > target) {
			right = mid -1;
			continue;
		}
	}

	return -1;
}

__global__ void device_multiply(dcs_matrix_t A, dcs_matrix_t B, int *C, int num_cols_per_block, int n) {
	int block_first = blockIdx.x * num_cols_per_block;
	if(block_first > B.nzc) return; // more blocks than nzc
	int block_last = block_first + num_cols_per_block; //exclusive
	if(block_last > B.nzc) block_last = B.nzc;

	//TODO: setup shared memory --> while loop for each thread, once all threads break they can sync

	//loop for the columns that this will look at
	int x = block_first + threadIdx.x; // index in B.JC this thread col is working on
	while(x < block_last) {
		int j = B.JC[x];
		int first = B.CP[x];
		int last = B.CP[x+1];
		int curr = first + threadIdx.y; // row index in B.IR this thread is working on
		//loop for the nonzero elements that this thread will execute on
		while(curr < last) {
			//do the multiplication, remember to atomicAdd for C
			int brow = B.IR[curr];
			int bval = B.NUM[curr];

			int apos = binary_search(A.JC, A.nzc, brow);
			if(apos != -1) {
				int acurr = A.CP[apos];
				int alast = A.CP[apos+1];

				int i, aval;
				while(acurr != alast) { // iterate over elements in column brow of A
					i = A.IR[acurr];
					aval = A.NUM[acurr];

					// C[i * n + j] += aval * bval;
					atomicAdd(C + (i*n + j), aval * bval); // race conditions may occur within this thread row

					acurr++;
				}
			}

			curr += blockDim.y; // next non-zero assigned round robin
		}
		
		x += blockDim.x; // next column is assigned round robin
	}

	//note: threads don't have to wait for each other to sync, some can be on different columns than others no problem
}

void parallel_multiply(int *C, int n, int nnz, char *Afile, char *Bfile, int Arseed, int Brseed) {
	//start timer
	struct timespec start, computation_done;
	double time;
	if( clock_gettime(CLOCK_REALTIME, &start) == -1) { perror("clock gettime");}

	//setup
	cs_matrix_t m1;
	dcs_matrix_t A;
	cuda_cs(&m1, Afile, n, nnz, 1, Arseed);
	cuda_dcs(&m1, &A);

	cs_matrix_t m2;
	dcs_matrix_t B;
	cuda_cs(&m2, Bfile, n, nnz, 1, Brseed);
	cuda_dcs(&m2, &B);

	//call device multiply
	dim3 dimGrid(GRID_WIDTH);
	dim3 dimBlock(BLOCK_WIDTH, BLOCK_HEIGHT);

	double nd = (double)B.nzc / (double)GRID_WIDTH;
	int num_cols_per_block = (int) ceil(nd);

	device_multiply<<<dimGrid, dimBlock>>>(A, B, C, num_cols_per_block, n);
	cudaDeviceSynchronize(); // in order to access unified memory

	//stop timer for computation
	if( clock_gettime(CLOCK_REALTIME, &computation_done) == -1) { perror("clock gettime");}

	//print out time for finishing computation and copying back data
	time = (computation_done.tv_sec - start.tv_sec)+ (double)(computation_done.tv_nsec - start.tv_nsec)/1e9;
	printf("DCSC A nnz: %d, A nzc: %d, B nnz: %d, B nzc: %d\nExecution Time: %f\n", A.nnz, A.nzc, B.nnz, B.nzc, time);

	//free unified memory
	cudaFree(A.JC);
	cudaFree(A.CP);
	cudaFree(A.IR);
	cudaFree(A.NUM);

	cudaFree(B.JC);
	cudaFree(B.CP);
	cudaFree(B.IR);
	cudaFree(B.NUM);
}

int main(int argc, char **argv) {
	if(argc < 3) {
		printf("arguments: n nnz\n");
		return 1;
	}
	
	int n = atoi(argv[1]);
	int nnz = atoi(argv[2]);
	int num_iterations = 5;

	int *C = (int *) malloc (sizeof(int)*n*n);
	int *gpu_C;
	cudaMalloc((void**)&gpu_C, sizeof(int)*n*n);

	char Afile[20];
	char Bfile[20];

	//number of iterations of the program
	for(int it = 0; it < num_iterations; it++) {
		//initialize C
		for(int i = 0; i < n*n; i++) {
			C[i] = 0;
		}
		cudaMemcpy(gpu_C, C, sizeof(int)*n*n, cudaMemcpyHostToDevice);

		sprintf(Afile, "%d_%d_%d", n, nnz, it);
		sprintf(Bfile, "%d_%d_%d", n, nnz, (it+1) % num_iterations);

		//execute multiplication
		parallel_multiply(gpu_C, n, nnz, Afile, Bfile, 1, 1);

		//verify that C is correct here - deleted for sake of execution time

		
	}
	
	cudaFree(gpu_C);
	free(C);

	return 0;
}

	.file	"tmpxft_00293f2f_00000000-6_paralleldcsc_no_shared.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2034:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2034:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"r"
.LC1:
	.string	"%d"
	.text
	.globl	_Z7cuda_csP11cs_matrix_tPKciici
	.type	_Z7cuda_csP11cs_matrix_tPKciici, @function
_Z7cuda_csP11cs_matrix_tPKciici:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	xorl	%r15d, %r15d
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	xorl	%r14d, %r14d
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movl	%edx, %r13d
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movl	%r9d, %r12d
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movslq	%ecx, %rbp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movq	%rdi, %rbx
	movq	%rsi, %rdi
	leaq	.LC0(%rip), %rsi
	salq	$2, %rbp
	subq	$56, %rsp
	.cfi_def_cfa_offset 112
	movq	%fs:40, %rax
	movq	%rax, 40(%rsp)
	xorl	%eax, %eax
	movb	%r8b, (%rbx)
	movl	%edx, 32(%rbx)
	call	fopen@PLT
	leal	1(%r13), %esi
	leaq	8(%rbx), %rdi
	movl	$1, %edx
	movslq	%esi, %rsi
	movq	%rax, (%rsp)
	salq	$2, %rsi
	call	cudaMallocManaged@PLT
	movq	%rbp, %rsi
	leaq	16(%rbx), %rdi
	movl	$1, %edx
	call	cudaMallocManaged@PLT
	movq	%rbp, %rsi
	movl	$1, %edx
	xorl	%ebp, %ebp
	leaq	24(%rbx), %rdi
	call	cudaMallocManaged@PLT
	movl	%r12d, %edi
	call	srand@PLT
	leaq	32(%rsp), %rax
	movq	(%rsp), %rdi
	leaq	.LC1(%rip), %rsi
	movq	%rax, 16(%rsp)
	movq	%rax, %rdx
	xorl	%eax, %eax
	call	__isoc23_fscanf@PLT
	leaq	36(%rsp), %rax
	movq	%rax, 24(%rsp)
.L3:
	movq	(%rsp), %rdi
	call	feof@PLT
	testl	%eax, %eax
	movslq	%r15d, %rax
	jne	.L7
	movq	8(%rbx), %rsi
	salq	$2, %rax
.L8:
	leaq	(%rsi,%rax), %rdx
	leal	1(%r15), %ecx
	addq	$4, %rax
	cmpl	%r15d, 32(%rsp)
	movl	%ecx, 12(%rsp)
	movl	%ebp, (%rdx)
	jle	.L14
	movl	12(%rsp), %r15d
	jmp	.L8
.L14:
	movslq	%ebp, %r12
	incl	%r14d
	salq	$2, %r12
.L6:
	movq	(%rsp), %rdi
	call	feof@PLT
	testl	%eax, %eax
	jne	.L5
	cmpl	%r15d, 32(%rsp)
	jne	.L5
	movq	(%rsp), %rdi
	movq	24(%rsp), %rdx
	leaq	.LC1(%rip), %rsi
	incl	%ebp
	call	__isoc23_fscanf@PLT
	movl	36(%rsp), %edx
	movq	16(%rbx), %rax
	movl	%edx, (%rax,%r12)
	call	rand@PLT
	movl	$100, %esi
	movq	24(%rbx), %rdi
	cltd
	idivl	%esi
	leaq	.LC1(%rip), %rsi
	xorl	%eax, %eax
	movl	%edx, (%rdi,%r12)
	movq	16(%rsp), %rdx
	addq	$4, %r12
	movq	(%rsp), %rdi
	call	__isoc23_fscanf@PLT
	jmp	.L6
.L5:
	movl	12(%rsp), %r15d
	jmp	.L3
.L7:
	salq	$2, %rax
.L9:
	cmpl	%r13d, %r15d
	jg	.L15
	movq	8(%rbx), %rdx
	incl	%r15d
	movl	%ebp, (%rdx,%rax)
	addq	$4, %rax
	jmp	.L9
.L15:
	movl	%ebp, 40(%rbx)
	movq	(%rsp), %rdi
	movl	%r14d, 36(%rbx)
	call	fclose@PLT
	movq	40(%rsp), %rax
	subq	%fs:40, %rax
	je	.L11
	call	__stack_chk_fail@PLT
.L11:
	addq	$56, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2027:
	.size	_Z7cuda_csP11cs_matrix_tPKciici, .-_Z7cuda_csP11cs_matrix_tPKciici
	.globl	_Z8cuda_dcsP11cs_matrix_tP12dcs_matrix_t
	.type	_Z8cuda_dcsP11cs_matrix_tP12dcs_matrix_t, @function
_Z8cuda_dcsP11cs_matrix_tP12dcs_matrix_t:
.LFB2028:
	.cfi_startproc
	endbr64
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	movq	%rsi, %rbp
	pushq	%rbx
	.cfi_def_cfa_offset 24
	.cfi_offset 3, -24
	movq	%rdi, %rbx
	pushq	%rdx
	.cfi_def_cfa_offset 32
	movb	(%rdi), %al
	movl	$1, %edx
	movb	%al, (%rsi)
	movq	16(%rdi), %rax
	movq	%rax, 24(%rsi)
	movq	24(%rdi), %rax
	movq	%rax, 32(%rsi)
	movl	32(%rdi), %eax
	movl	%eax, 40(%rsi)
	movl	40(%rdi), %eax
	movl	%eax, 48(%rsi)
	movslq	36(%rdi), %rsi
	leaq	8(%rbp), %rdi
	movl	%esi, 44(%rbp)
	salq	$2, %rsi
	call	cudaMallocManaged@PLT
	movl	36(%rbx), %eax
	leaq	16(%rbp), %rdi
	movl	$1, %edx
	leal	1(%rax), %esi
	movslq	%esi, %rsi
	salq	$2, %rsi
	call	cudaMallocManaged@PLT
	movq	8(%rbx), %rdi
	movq	16(%rbp), %r10
	xorl	%edx, %edx
	xorl	%eax, %eax
	xorl	%ecx, %ecx
.L17:
	movslq	%ecx, %r8
	leaq	(%r10,%r8,4), %rsi
	cmpl	%eax, 32(%rbx)
	jle	.L21
	leaq	(%rdi,%rdx), %r9
	addq	$4, %rdx
	movl	(%rdi,%rdx), %r11d
	cmpl	%r11d, (%r9)
	je	.L18
	movq	8(%rbp), %r11
	incl	%ecx
	movl	%eax, (%r11,%r8,4)
	movl	(%r9), %r8d
	movl	%r8d, (%rsi)
.L18:
	incl	%eax
	jmp	.L17
.L21:
	movl	40(%rbx), %eax
	movl	%eax, (%rsi)
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	cudaFree@PLT
	.cfi_endproc
.LFE2028:
	.size	_Z8cuda_dcsP11cs_matrix_tP12dcs_matrix_t, .-_Z8cuda_dcsP11cs_matrix_tP12dcs_matrix_t
	.globl	_Z13binary_searchPiii
	.type	_Z13binary_searchPiii, @function
_Z13binary_searchPiii:
.LFB2029:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2029:
	.size	_Z13binary_searchPiii, .-_Z13binary_searchPiii
	.globl	_Z53__device_stub__Z15device_multiply12dcs_matrix_tS_PiiiR12dcs_matrix_tS0_Piii
	.type	_Z53__device_stub__Z15device_multiply12dcs_matrix_tS_PiiiR12dcs_matrix_tS0_Piii, @function
_Z53__device_stub__Z15device_multiply12dcs_matrix_tS_PiiiR12dcs_matrix_tS0_Piii:
.LFB2056:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdx, 8(%rsp)
	leaq	16(%rsp), %rdx
	movl	%ecx, 4(%rsp)
	leaq	24(%rsp), %rcx
	movl	%r8d, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movq	%rdi, 80(%rsp)
	leaq	32(%rsp), %rdi
	movq	%rax, 96(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 104(%rsp)
	movq	%rsp, %rax
	movq	%rsi, 88(%rsp)
	leaq	44(%rsp), %rsi
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 32(%rsp)
	movl	$1, 40(%rsp)
	movq	%rax, 44(%rsp)
	movl	$1, 52(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L24
	pushq	24(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z15device_multiply12dcs_matrix_tS_Piii(%rip), %rdi
	pushq	24(%rsp)
	.cfi_def_cfa_offset 160
	movq	60(%rsp), %rcx
	movl	68(%rsp), %r8d
	movq	48(%rsp), %rsi
	movl	56(%rsp), %edx
	leaq	96(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L24:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L26
	call	__stack_chk_fail@PLT
.L26:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2056:
	.size	_Z53__device_stub__Z15device_multiply12dcs_matrix_tS_PiiiR12dcs_matrix_tS0_Piii, .-_Z53__device_stub__Z15device_multiply12dcs_matrix_tS_PiiiR12dcs_matrix_tS0_Piii
	.globl	_Z15device_multiply12dcs_matrix_tS_Piii
	.type	_Z15device_multiply12dcs_matrix_tS_Piii, @function
_Z15device_multiply12dcs_matrix_tS_Piii:
.LFB2057:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	movl	%esi, %ecx
	movl	%edx, %r8d
	movq	%rdi, %rdx
	leaq	72(%rsp), %rsi
	leaq	16(%rsp), %rdi
	call	_Z53__device_stub__Z15device_multiply12dcs_matrix_tS_PiiiR12dcs_matrix_tS0_Piii
	popq	%rdx
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2057:
	.size	_Z15device_multiply12dcs_matrix_tS_Piii, .-_Z15device_multiply12dcs_matrix_tS_Piii
	.section	.rodata.str1.1
.LC2:
	.string	"clock gettime"
.LC5:
	.string	"DCSC A nnz: %d, A nzc: %d, B nnz: %d, B nzc: %d\nExecution Time: %f\n"
	.text
	.globl	_Z17parallel_multiplyPiiiPcS0_ii
	.type	_Z17parallel_multiplyPiiiPcS0_ii, @function
_Z17parallel_multiplyPiiiPcS0_ii:
.LFB2030:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movl	%r9d, %r15d
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	movq	%rcx, %r14
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movq	%rdi, %r13
	xorl	%edi, %edi
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movq	%r8, %r12
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movl	%edx, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movl	%esi, %ebx
	subq	$392, %rsp
	.cfi_def_cfa_offset 448
	movq	%fs:40, %rax
	movq	%rax, 376(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rsi
	call	clock_gettime@PLT
	incl	%eax
	jne	.L31
	leaq	.LC2(%rip), %rdi
	call	perror@PLT
.L31:
	movl	%r15d, %r9d
	movl	%ebp, %ecx
	leaq	56(%rsp), %rdi
	movl	$1, %r8d
	movl	%ebx, %edx
	movq	%r14, %rsi
	movq	%rdi, 8(%rsp)
	leaq	104(%rsp), %r15
	call	_Z7cuda_csP11cs_matrix_tPKciici
	leaq	152(%rsp), %r14
	movq	8(%rsp), %rdi
	movq	%r14, %rsi
	call	_Z8cuda_dcsP11cs_matrix_tP12dcs_matrix_t
	movl	%ebp, %ecx
	movl	$1, %r8d
	movl	%ebx, %edx
	movl	448(%rsp), %r9d
	movq	%r12, %rsi
	movq	%r15, %rdi
	leaq	208(%rsp), %r12
	leaq	320(%rsp), %rbp
	call	_Z7cuda_csP11cs_matrix_tPKciici
	movq	%r15, %rdi
	movq	%r12, %rsi
	call	_Z8cuda_dcsP11cs_matrix_tP12dcs_matrix_t
	movl	$33554433, %edi
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	salq	$7, %rdi
	movl	$1, %ecx
	movabsq	$137438953488, %rdx
	movl	$1, %esi
	movq	%rdi, 16(%rsp)
	movl	252(%rsp), %r15d
	movl	$1, 24(%rsp)
	movq	%rdx, 28(%rsp)
	movl	$1, 36(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L32
	leaq	264(%rsp), %rdi
	movl	$14, %ecx
	movq	%r14, %rsi
	rep movsl
	movl	$14, %ecx
	movq	%rbp, %rdi
	movq	%r12, %rsi
	rep movsl
	cvtsi2sdl	%r15d, %xmm0
	mulsd	.LC3(%rip), %xmm0
	call	ceil@PLT
	movl	%ebx, %r8d
	movq	%r13, %rdx
	movq	%rbp, %rsi
	cvttsd2sil	%xmm0, %ecx
	leaq	264(%rsp), %rdi
	call	_Z53__device_stub__Z15device_multiply12dcs_matrix_tS_PiiiR12dcs_matrix_tS0_Piii
.L32:
	call	cudaDeviceSynchronize@PLT
	xorl	%edi, %edi
	movq	%rbp, %rsi
	call	clock_gettime@PLT
	incl	%eax
	jne	.L33
	leaq	.LC2(%rip), %rdi
	call	perror@PLT
.L33:
	movq	328(%rsp), %rax
	subq	48(%rsp), %rax
	leaq	.LC5(%rip), %rsi
	movl	$2, %edi
	cvtsi2sdq	%rax, %xmm0
	movq	320(%rsp), %rax
	subq	40(%rsp), %rax
	divsd	.LC4(%rip), %xmm0
	cvtsi2sdq	%rax, %xmm1
	movl	196(%rsp), %ecx
	movb	$1, %al
	movl	252(%rsp), %r9d
	movl	256(%rsp), %r8d
	movl	200(%rsp), %edx
	addsd	%xmm1, %xmm0
	call	__printf_chk@PLT
	movq	160(%rsp), %rdi
	call	cudaFree@PLT
	movq	168(%rsp), %rdi
	call	cudaFree@PLT
	movq	176(%rsp), %rdi
	call	cudaFree@PLT
	movq	184(%rsp), %rdi
	call	cudaFree@PLT
	movq	216(%rsp), %rdi
	call	cudaFree@PLT
	movq	224(%rsp), %rdi
	call	cudaFree@PLT
	movq	232(%rsp), %rdi
	call	cudaFree@PLT
	movq	240(%rsp), %rdi
	call	cudaFree@PLT
	movq	376(%rsp), %rax
	subq	%fs:40, %rax
	je	.L34
	call	__stack_chk_fail@PLT
.L34:
	addq	$392, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2030:
	.size	_Z17parallel_multiplyPiiiPcS0_ii, .-_Z17parallel_multiplyPiiiPcS0_ii
	.section	.rodata.str1.1
.LC6:
	.string	"arguments: n nnz\n"
.LC7:
	.string	"%d_%d_%d"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2031:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$88, %rsp
	.cfi_def_cfa_offset 144
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	xorl	%eax, %eax
	cmpl	$2, %edi
	jg	.L37
	leaq	.LC6(%rip), %rsi
	movl	$2, %edi
	call	__printf_chk@PLT
	movl	$1, %eax
	jmp	.L36
.L37:
	movq	8(%rsi), %rdi
	movq	%rsi, %rbp
	call	atoi@PLT
	movq	16(%rbp), %rdi
	xorl	%ebp, %ebp
	movl	%eax, %ebx
	call	atoi@PLT
	movl	%ebx, %r15d
	movl	%eax, 12(%rsp)
	movslq	%ebx, %rax
	imull	%ebx, %r15d
	imulq	%rax, %rax
	salq	$2, %rax
	movq	%rax, %rdi
	movq	%rax, (%rsp)
	call	malloc@PLT
	movq	(%rsp), %rsi
	leaq	24(%rsp), %rdi
	movq	%rax, %r12
	call	cudaMalloc@PLT
.L39:
	xorl	%eax, %eax
.L42:
	cmpl	%eax, %r15d
	jle	.L45
	xorl	%esi, %esi
	movl	%esi, (%r12,%rax,4)
	incq	%rax
	jmp	.L42
.L45:
	movq	(%rsp), %rdx
	movq	24(%rsp), %rdi
	movl	$1, %ecx
	movq	%r12, %rsi
	leaq	32(%rsp), %r13
	call	cudaMemcpy@PLT
	movl	%ebx, %r8d
	movl	$20, %edx
	movq	%r13, %rdi
	pushq	%rax
	.cfi_def_cfa_offset 152
	leaq	.LC7(%rip), %rcx
	movl	$2, %esi
	xorl	%eax, %eax
	pushq	%rbp
	.cfi_def_cfa_offset 160
	movl	28(%rsp), %r9d
	incl	%ebp
	call	__sprintf_chk@PLT
	movl	%ebp, %eax
	movl	$5, %ecx
	movl	%ebx, %r8d
	cltd
	movl	28(%rsp), %r9d
	leaq	68(%rsp), %r14
	movl	$2, %esi
	idivl	%ecx
	movq	%r14, %rdi
	leaq	.LC7(%rip), %rcx
	xorl	%eax, %eax
	movl	%edx, (%rsp)
	movl	$20, %edx
	call	__sprintf_chk@PLT
	movl	28(%rsp), %edx
	movq	40(%rsp), %rdi
	movl	%ebx, %esi
	movq	%r13, %rcx
	movl	$1, %r9d
	movq	%r14, %r8
	movl	$1, (%rsp)
	call	_Z17parallel_multiplyPiiiPcS0_ii
	popq	%rdx
	.cfi_def_cfa_offset 152
	popq	%rcx
	.cfi_def_cfa_offset 144
	cmpl	$5, %ebp
	jne	.L39
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	movq	%r12, %rdi
	call	free@PLT
	xorl	%eax, %eax
.L36:
	movq	72(%rsp), %rdx
	subq	%fs:40, %rdx
	je	.L43
	call	__stack_chk_fail@PLT
.L43:
	addq	$88, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2031:
	.size	main, .-main
	.section	.rodata.str1.1
.LC8:
	.string	"_Z15device_multiply12dcs_matrix_tS_Piii"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2059:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC8(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z15device_multiply12dcs_matrix_tS_Piii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2059:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst8,"aM",@progbits,8
	.align 8
.LC3:
	.long	0
	.long	1065353216
	.align 8
.LC4:
	.long	0
	.long	1104006501
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

/* 
 * 
 * Jason Yik
 * jyik@usc.edu
 * EE451 Final Project
 *
 * CUDA implementation of DCSC matrix multiplication.
 * Implementation without shared memory.
 * 
 * Run on USC HPC:
 * srun -n1 --gres=gpu:1 ./parallel <n> <nnz>
 *
 * Run with executable in a graphs folder containing n_nnz_x graphs
 *
 */ 


#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <math.h>

#define GRID_WIDTH 128
#define BLOCK_WIDTH 16
#define BLOCK_HEIGHT 32

//TODO: possibly increase block width, decrease block height since there will be max 8 nonzeroes per col on avg

typedef struct {
	char column;
	int *JC;
	int *IR;
	int *NUM;

	int n;   // number of columns
	int nzc; // non zero columns/rows
	int nnz; // number of nonzeroes
} cs_matrix_t;

typedef struct {
	char column;
	int *JC;
	int *CP;
	int *IR;
	int *NUM;

	int n;   // number of columns
	int nzc; // non zero columns/rows
	int nnz; // number of nonzeroes
} dcs_matrix_t;

//uses CUDA unified memory
void cuda_cs(cs_matrix_t *m, const char *file, int n, int nnz, char column, int random_seed) {
	m->column = column;
	m->n = n;

	FILE *fp = fopen(file, "r");
	int bufc, bufr;

	hipMallocManaged(&(m->JC), sizeof(int) * (n+1));
	hipMallocManaged(&(m->IR), sizeof(int) * nnz);
	hipMallocManaged(&(m->NUM), sizeof(int) * nnz);
	
	srand(random_seed);
	//srand(time(0));

	int nzc = 0;

	int i = 0;
	int current_index = 0;
	fscanf(fp, "%d", &bufc);
	while(!feof(fp)) {
		//if blank columns, fill in JC
		while(i < bufc) {
			m->JC[i] = current_index;
			i++;
		}

		m->JC[i] = current_index;
		nzc++;
		while(!feof(fp) && i == bufc) {
			fscanf(fp, "%d", &bufr);
			m->IR[current_index] = bufr;
			m->NUM[current_index] = rand() % 100; 
			current_index++;
			
			fscanf(fp, "%d", &bufc);
		}
		i++;
	}
	//fill in the remainder of JC
	while(i <= n) {
		//current_index should now be greater than size of IR/NUM
		m->JC[i] = current_index; 
		i++;
	}

	m->nnz = current_index;
	m->nzc = nzc;

	fclose(fp);
	return;
}

//uses CUDA unified memory
void cuda_dcs(cs_matrix_t *m, dcs_matrix_t *d) {
	d->column = m->column;
	d->IR = m->IR;
	d->NUM = m->NUM;

	d->n = m->n;
	d->nnz = m->nnz;
	d->nzc = m->nzc;

	hipMallocManaged(&(d->JC), sizeof(int) * m->nzc);
	hipMallocManaged(&(d->CP), sizeof(int) * (m->nzc +1));

	int current_index = 0;
	for(int i = 0; i < m->n; i++) {
		if(m->JC[i] == m->JC[i+1]) {
			continue;
		}
		else {
			d->JC[current_index] = i;
			d->CP[current_index] = m->JC[i];
			current_index++;
		}
	}
	d->CP[current_index] = m->nnz;

	//invalidate m
	hipFree(m->JC);

	return;
}

__device__ int binary_search(int *arr, int len, int target) {
	int left = 0;
	int right = len -1;
	int mid;

	while(left <= right) {
		mid = (left + right)/2;
		if(arr[mid] == target) return mid;
		if(arr[mid] < target) {
			left = mid +1;
			continue;
		}
		if(arr[mid] > target) {
			right = mid -1;
			continue;
		}
	}

	return -1;
}

__global__ void device_multiply(dcs_matrix_t A, dcs_matrix_t B, int *C, int num_cols_per_block, int n) {
	int block_first = blockIdx.x * num_cols_per_block;
	if(block_first > B.nzc) return; // more blocks than nzc
	int block_last = block_first + num_cols_per_block; //exclusive
	if(block_last > B.nzc) block_last = B.nzc;

	//TODO: setup shared memory --> while loop for each thread, once all threads break they can sync

	//loop for the columns that this will look at
	int x = block_first + threadIdx.x; // index in B.JC this thread col is working on
	while(x < block_last) {
		int j = B.JC[x];
		int first = B.CP[x];
		int last = B.CP[x+1];
		int curr = first + threadIdx.y; // row index in B.IR this thread is working on
		//loop for the nonzero elements that this thread will execute on
		while(curr < last) {
			//do the multiplication, remember to atomicAdd for C
			int brow = B.IR[curr];
			int bval = B.NUM[curr];

			int apos = binary_search(A.JC, A.nzc, brow);
			if(apos != -1) {
				int acurr = A.CP[apos];
				int alast = A.CP[apos+1];

				int i, aval;
				while(acurr != alast) { // iterate over elements in column brow of A
					i = A.IR[acurr];
					aval = A.NUM[acurr];

					// C[i * n + j] += aval * bval;
					atomicAdd(C + (i*n + j), aval * bval); // race conditions may occur within this thread row

					acurr++;
				}
			}

			curr += blockDim.y; // next non-zero assigned round robin
		}
		
		x += blockDim.x; // next column is assigned round robin
	}

	//note: threads don't have to wait for each other to sync, some can be on different columns than others no problem
}

void parallel_multiply(int *C, int n, int nnz, char *Afile, char *Bfile, int Arseed, int Brseed) {
	//start timer
	struct timespec start, computation_done;
	double time;
	if( clock_gettime(CLOCK_REALTIME, &start) == -1) { perror("clock gettime");}

	//setup
	cs_matrix_t m1;
	dcs_matrix_t A;
	cuda_cs(&m1, Afile, n, nnz, 1, Arseed);
	cuda_dcs(&m1, &A);

	cs_matrix_t m2;
	dcs_matrix_t B;
	cuda_cs(&m2, Bfile, n, nnz, 1, Brseed);
	cuda_dcs(&m2, &B);

	//call device multiply
	dim3 dimGrid(GRID_WIDTH);
	dim3 dimBlock(BLOCK_WIDTH, BLOCK_HEIGHT);

	double nd = (double)B.nzc / (double)GRID_WIDTH;
	int num_cols_per_block = (int) ceil(nd);

	device_multiply<<<dimGrid, dimBlock>>>(A, B, C, num_cols_per_block, n);
	hipDeviceSynchronize(); // in order to access unified memory

	//stop timer for computation
	if( clock_gettime(CLOCK_REALTIME, &computation_done) == -1) { perror("clock gettime");}

	//print out time for finishing computation and copying back data
	time = (computation_done.tv_sec - start.tv_sec)+ (double)(computation_done.tv_nsec - start.tv_nsec)/1e9;
	printf("DCSC A nnz: %d, A nzc: %d, B nnz: %d, B nzc: %d\nExecution Time: %f\n", A.nnz, A.nzc, B.nnz, B.nzc, time);

	//free unified memory
	hipFree(A.JC);
	hipFree(A.CP);
	hipFree(A.IR);
	hipFree(A.NUM);

	hipFree(B.JC);
	hipFree(B.CP);
	hipFree(B.IR);
	hipFree(B.NUM);
}

int main(int argc, char **argv) {
	if(argc < 3) {
		printf("arguments: n nnz\n");
		return 1;
	}
	
	int n = atoi(argv[1]);
	int nnz = atoi(argv[2]);
	int num_iterations = 5;

	int *C = (int *) malloc (sizeof(int)*n*n);
	int *gpu_C;
	hipMalloc((void**)&gpu_C, sizeof(int)*n*n);

	char Afile[20];
	char Bfile[20];

	//number of iterations of the program
	for(int it = 0; it < num_iterations; it++) {
		//initialize C
		for(int i = 0; i < n*n; i++) {
			C[i] = 0;
		}
		hipMemcpy(gpu_C, C, sizeof(int)*n*n, hipMemcpyHostToDevice);

		sprintf(Afile, "%d_%d_%d", n, nnz, it);
		sprintf(Bfile, "%d_%d_%d", n, nnz, (it+1) % num_iterations);

		//execute multiplication
		parallel_multiply(gpu_C, n, nnz, Afile, Bfile, 1, 1);

		//verify that C is correct here - deleted for sake of execution time

		
	}
	
	hipFree(gpu_C);
	free(C);

	return 0;
}

	.text
	.file	"paralleldcsc_no_shared.hip"
	.globl	_Z7cuda_csP11cs_matrix_tPKciici # -- Begin function _Z7cuda_csP11cs_matrix_tPKciici
	.type	_Z7cuda_csP11cs_matrix_tPKciici,@function
_Z7cuda_csP11cs_matrix_tPKciici:        # @_Z7cuda_csP11cs_matrix_tPKciici
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$40, %rsp
	.cfi_def_cfa_offset 96
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%r9d, %ebx
	movl	%ecx, %ebp
	movl	%edx, %r12d
	movq	%rsi, %rax
	movq	%rdi, %r14
	movb	%r8b, (%rdi)
	movl	%edx, 32(%rdi)
	movl	$.L.str, %esi
	movq	%rax, %rdi
	callq	fopen
	movq	%rax, %r15
	leaq	8(%r14), %rdi
	movq	%r12, 24(%rsp)                  # 8-byte Spill
	leal	1(%r12), %eax
	movslq	%eax, %rsi
	shlq	$2, %rsi
	movq	%rdi, 16(%rsp)                  # 8-byte Spill
	movl	$1, %edx
	callq	hipMallocManaged
	leaq	16(%r14), %r13
	movslq	%ebp, %r12
	shlq	$2, %r12
	movq	%r13, %rdi
	movq	%r12, %rsi
	movl	$1, %edx
	callq	hipMallocManaged
	movq	%r14, 32(%rsp)                  # 8-byte Spill
	leaq	24(%r14), %rbp
	movq	%rbp, %rdi
	movq	%r12, %rsi
	movl	$1, %edx
	callq	hipMallocManaged
	movl	%ebx, %edi
	callq	srand
	movl	$0, 8(%rsp)                     # 4-byte Folded Spill
	leaq	4(%rsp), %rdx
	movl	$.L.str.1, %esi
	movq	%r15, %rdi
	xorl	%eax, %eax
	callq	__isoc23_fscanf
	movq	%r15, %rdi
	callq	feof
	movl	$0, %ebx
	movl	$0, %r14d
	testl	%eax, %eax
	jne	.LBB0_11
# %bb.1:                                # %.preheader48.preheader
	leaq	4(%rsp), %r12
	xorl	%r14d, %r14d
	xorl	%ebx, %ebx
	movl	$0, 8(%rsp)                     # 4-byte Folded Spill
.LBB0_2:                                # %.preheader48
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB0_4 Depth 2
                                        #     Child Loop BB0_8 Depth 2
	movq	16(%rsp), %rax                  # 8-byte Reload
	movq	(%rax), %rax
	cmpl	4(%rsp), %ebx
	jge	.LBB0_5
# %bb.3:                                # %.lr.ph
                                        #   in Loop: Header=BB0_2 Depth=1
	movslq	%ebx, %rbx
.LBB0_4:                                #   Parent Loop BB0_2 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movl	%r14d, (%rax,%rbx,4)
	incq	%rbx
	movslq	4(%rsp), %rcx
	cmpq	%rcx, %rbx
	jl	.LBB0_4
.LBB0_5:                                # %._crit_edge
                                        #   in Loop: Header=BB0_2 Depth=1
	movslq	%ebx, %rcx
	movl	%r14d, (%rax,%rcx,4)
	movq	%r15, %rdi
	callq	feof
	testl	%eax, %eax
	jne	.LBB0_10
# %bb.6:                                # %._crit_edge
                                        #   in Loop: Header=BB0_2 Depth=1
	cmpl	4(%rsp), %ebx
	jne	.LBB0_10
# %bb.7:                                # %.lr.ph53.preheader
                                        #   in Loop: Header=BB0_2 Depth=1
	movslq	%r14d, %r14
.LBB0_8:                                # %.lr.ph53
                                        #   Parent Loop BB0_2 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movl	$.L.str.1, %esi
	movq	%r15, %rdi
	leaq	12(%rsp), %rdx
	xorl	%eax, %eax
	callq	__isoc23_fscanf
	movl	12(%rsp), %eax
	movq	(%r13), %rcx
	movl	%eax, (%rcx,%r14,4)
	callq	rand
	cltq
	imulq	$1374389535, %rax, %rcx         # imm = 0x51EB851F
	movq	%rcx, %rdx
	shrq	$63, %rdx
	sarq	$37, %rcx
	addl	%edx, %ecx
	imull	$100, %ecx, %ecx
	subl	%ecx, %eax
	movq	(%rbp), %rcx
	movl	%eax, (%rcx,%r14,4)
	incq	%r14
	movl	$.L.str.1, %esi
	movq	%r15, %rdi
	movq	%r12, %rdx
	xorl	%eax, %eax
	callq	__isoc23_fscanf
	movq	%r15, %rdi
	callq	feof
	testl	%eax, %eax
	jne	.LBB0_10
# %bb.9:                                # %.lr.ph53
                                        #   in Loop: Header=BB0_8 Depth=2
	cmpl	4(%rsp), %ebx
	je	.LBB0_8
.LBB0_10:                               # %._crit_edge54
                                        #   in Loop: Header=BB0_2 Depth=1
	incl	8(%rsp)                         # 4-byte Folded Spill
	incl	%ebx
	movq	%r15, %rdi
	callq	feof
	testl	%eax, %eax
	je	.LBB0_2
.LBB0_11:                               # %.preheader
	movq	24(%rsp), %rdx                  # 8-byte Reload
	cmpl	%edx, %ebx
	jg	.LBB0_14
# %bb.12:                               # %.lr.ph65
	movslq	%ebx, %rax
	shlq	$2, %rax
	movq	16(%rsp), %rcx                  # 8-byte Reload
	addq	(%rcx), %rax
	subl	%ebx, %edx
	incl	%edx
	xorl	%ecx, %ecx
.LBB0_13:                               # =>This Inner Loop Header: Depth=1
	movl	%r14d, (%rax,%rcx,4)
	incq	%rcx
	cmpl	%ecx, %edx
	jne	.LBB0_13
.LBB0_14:                               # %._crit_edge66
	movq	32(%rsp), %rax                  # 8-byte Reload
	movl	%r14d, 40(%rax)
	movl	8(%rsp), %ecx                   # 4-byte Reload
	movl	%ecx, 36(%rax)
	movq	%r15, %rdi
	callq	fclose
	addq	$40, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z7cuda_csP11cs_matrix_tPKciici, .Lfunc_end0-_Z7cuda_csP11cs_matrix_tPKciici
	.cfi_endproc
                                        # -- End function
	.globl	_Z8cuda_dcsP11cs_matrix_tP12dcs_matrix_t # -- Begin function _Z8cuda_dcsP11cs_matrix_tP12dcs_matrix_t
	.type	_Z8cuda_dcsP11cs_matrix_tP12dcs_matrix_t,@function
_Z8cuda_dcsP11cs_matrix_tP12dcs_matrix_t: # @_Z8cuda_dcsP11cs_matrix_tP12dcs_matrix_t
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movq	%rsi, %rbx
	movq	%rdi, %r14
	movb	(%rdi), %al
	movb	%al, (%rsi)
	movq	16(%rdi), %rax
	movq	%rax, 24(%rsi)
	movq	24(%rdi), %rax
	movq	%rax, 32(%rsi)
	movl	32(%rdi), %eax
	movl	%eax, 40(%rsi)
	movl	40(%rdi), %eax
	movl	%eax, 48(%rsi)
	movslq	36(%rdi), %rsi
	movl	%esi, 44(%rbx)
	leaq	8(%rbx), %r15
	shlq	$2, %rsi
	movq	%r15, %rdi
	movl	$1, %edx
	callq	hipMallocManaged
	addq	$16, %rbx
	movslq	36(%r14), %rax
	leaq	4(,%rax,4), %rsi
	movq	%rbx, %rdi
	movl	$1, %edx
	callq	hipMallocManaged
	movl	32(%r14), %edx
	xorl	%eax, %eax
	movq	8(%r14), %rdi
	testl	%edx, %edx
	jle	.LBB1_6
# %bb.1:                                # %.lr.ph.preheader
	xorl	%ecx, %ecx
.LBB1_2:                                # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	movl	(%rdi,%rcx,4), %esi
	cmpl	4(%rdi,%rcx,4), %esi
	je	.LBB1_4
# %bb.3:                                #   in Loop: Header=BB1_2 Depth=1
	movq	(%r15), %rdx
	cltq
	movl	%ecx, (%rdx,%rax,4)
	movl	(%rdi,%rcx,4), %edx
	movq	(%rbx), %rsi
	movl	%edx, (%rsi,%rax,4)
	incl	%eax
	movl	32(%r14), %edx
.LBB1_4:                                #   in Loop: Header=BB1_2 Depth=1
	incq	%rcx
	movslq	%edx, %rsi
	cmpq	%rsi, %rcx
	jl	.LBB1_2
# %bb.5:                                # %._crit_edge.loopexit
	cltq
.LBB1_6:                                # %._crit_edge
	movl	40(%r14), %ecx
	movq	(%rbx), %rdx
	movl	%ecx, (%rdx,%rax,4)
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	hipFree                         # TAILCALL
.Lfunc_end1:
	.size	_Z8cuda_dcsP11cs_matrix_tP12dcs_matrix_t, .Lfunc_end1-_Z8cuda_dcsP11cs_matrix_tP12dcs_matrix_t
	.cfi_endproc
                                        # -- End function
	.globl	_Z30__device_stub__device_multiply12dcs_matrix_tS_Piii # -- Begin function _Z30__device_stub__device_multiply12dcs_matrix_tS_Piii
	.type	_Z30__device_stub__device_multiply12dcs_matrix_tS_Piii,@function
_Z30__device_stub__device_multiply12dcs_matrix_tS_Piii: # @_Z30__device_stub__device_multiply12dcs_matrix_tS_Piii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	4(%rsp), %rcx
	movl	%esi, (%rcx)
	movq	%rsp, %rsi
	movl	%edx, (%rsi)
	leaq	160(%rsp), %rdx
	leaq	64(%rsp), %rbx
	movq	%rdx, (%rbx)
	leaq	216(%rsp), %rdx
	movq	%rdx, 8(%rbx)
	movq	%rax, 16(%rbx)
	movq	%rcx, 24(%rbx)
	movq	%rsi, 32(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z15device_multiply12dcs_matrix_tS_Piii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z30__device_stub__device_multiply12dcs_matrix_tS_Piii, .Lfunc_end2-_Z30__device_stub__device_multiply12dcs_matrix_tS_Piii
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0                          # -- Begin function _Z17parallel_multiplyPiiiPcS0_ii
.LCPI3_0:
	.quad	0x3f80000000000000              # double 0.0078125
.LCPI3_1:
	.quad	0x41cdcd6500000000              # double 1.0E+9
	.text
	.globl	_Z17parallel_multiplyPiiiPcS0_ii
	.type	_Z17parallel_multiplyPiiiPcS0_ii,@function
_Z17parallel_multiplyPiiiPcS0_ii:       # @_Z17parallel_multiplyPiiiPcS0_ii
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$472, %rsp                      # imm = 0x1D8
	.cfi_def_cfa_offset 528
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%r9d, %r13d
	movq	%r8, %r15
	movq	%rcx, %r14
	movl	%edx, %ebp
	movl	%esi, %ebx
	movq	%rdi, 8(%rsp)                   # 8-byte Spill
	leaq	136(%rsp), %rsi
	xorl	%edi, %edi
	callq	clock_gettime
	cmpl	$-1, %eax
	je	.LBB3_1
.LBB3_2:
	leaq	368(%rsp), %r12
	movq	%r12, %rdi
	movq	%r14, %rsi
	movl	%ebx, %edx
	movl	%ebp, %ecx
	movl	$1, %r8d
	movl	%r13d, %r9d
	callq	_Z7cuda_csP11cs_matrix_tPKciici
	leaq	80(%rsp), %rsi
	movq	%r12, %rdi
	callq	_Z8cuda_dcsP11cs_matrix_tP12dcs_matrix_t
	leaq	320(%rsp), %r14
	movq	%r14, %rdi
	movq	%r15, %rsi
	movl	%ebx, %edx
	movl	%ebp, %ecx
	movl	$1, %r8d
	movl	528(%rsp), %r9d
	callq	_Z7cuda_csP11cs_matrix_tPKciici
	leaq	24(%rsp), %r15
	movq	%r14, %rdi
	movq	%r15, %rsi
	callq	_Z8cuda_dcsP11cs_matrix_tP12dcs_matrix_t
	movl	44(%r15), %ebp
	movabsq	$4294967424, %rdi               # imm = 0x100000080
	movabsq	$137438953488, %rdx             # imm = 0x2000000010
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB3_4
# %bb.3:
	cvtsi2sd	%ebp, %xmm0
	mulsd	.LCPI3_0(%rip), %xmm0
	callq	ceil@PLT
	cvttsd2si	%xmm0, %eax
	movq	128(%rsp), %rcx
	leaq	416(%rsp), %rdx
	movq	%rcx, 48(%rdx)
	movups	80(%rsp), %xmm0
	movups	96(%rsp), %xmm1
	movups	112(%rsp), %xmm2
	movaps	%xmm2, 32(%rdx)
	movaps	%xmm1, 16(%rdx)
	movaps	%xmm0, (%rdx)
	movq	72(%rsp), %rcx
	leaq	208(%rsp), %rsi
	movq	%rcx, 48(%rsi)
	movups	24(%rsp), %xmm0
	movups	40(%rsp), %xmm1
	movups	56(%rsp), %xmm2
	movaps	%xmm2, 32(%rsi)
	movaps	%xmm1, 16(%rsi)
	movaps	%xmm0, (%rsi)
	leaq	168(%rsp), %rcx
	movq	8(%rsp), %rdi                   # 8-byte Reload
	movq	%rdi, (%rcx)
	leaq	20(%rsp), %rdi
	movl	%eax, (%rdi)
	leaq	16(%rsp), %rax
	movl	%ebx, (%rax)
	leaq	272(%rsp), %rbx
	movq	%rdx, (%rbx)
	movq	%rsi, 8(%rbx)
	movq	%rcx, 16(%rbx)
	movq	%rdi, 24(%rbx)
	movq	%rax, 32(%rbx)
	leaq	192(%rsp), %r14
	leaq	176(%rsp), %r15
	leaq	160(%rsp), %r12
	leaq	152(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z15device_multiply12dcs_matrix_tS_Piii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
.LBB3_4:
	callq	hipDeviceSynchronize
	leaq	208(%rsp), %rsi
	xorl	%edi, %edi
	callq	clock_gettime
	cmpl	$-1, %eax
	je	.LBB3_5
.LBB3_6:
	movq	208(%rsp), %rax
	movq	216(%rsp), %rcx
	subq	136(%rsp), %rax
	xorps	%xmm1, %xmm1
	cvtsi2sd	%rax, %xmm1
	subq	144(%rsp), %rcx
	xorps	%xmm0, %xmm0
	cvtsi2sd	%rcx, %xmm0
	divsd	.LCPI3_1(%rip), %xmm0
	addsd	%xmm1, %xmm0
	movl	124(%rsp), %edx
	movl	128(%rsp), %esi
	movl	68(%rsp), %r8d
	movl	72(%rsp), %ecx
	movl	$.L.str.3, %edi
	movb	$1, %al
	callq	printf
	movq	88(%rsp), %rdi
	callq	hipFree
	movq	96(%rsp), %rdi
	callq	hipFree
	movq	104(%rsp), %rdi
	callq	hipFree
	movq	112(%rsp), %rdi
	callq	hipFree
	movq	32(%rsp), %rdi
	callq	hipFree
	movq	40(%rsp), %rdi
	callq	hipFree
	movq	48(%rsp), %rdi
	callq	hipFree
	movq	56(%rsp), %rdi
	callq	hipFree
	addq	$472, %rsp                      # imm = 0x1D8
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB3_1:
	.cfi_def_cfa_offset 528
	movl	$.L.str.2, %edi
	callq	perror
	jmp	.LBB3_2
.LBB3_5:
	movl	$.L.str.2, %edi
	callq	perror
	jmp	.LBB3_6
.Lfunc_end3:
	.size	_Z17parallel_multiplyPiiiPcS0_ii, .Lfunc_end3-_Z17parallel_multiplyPiiiPcS0_ii
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$88, %rsp
	.cfi_def_cfa_offset 144
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	cmpl	$2, %edi
	jg	.LBB4_2
# %bb.1:
	movl	$.Lstr, %edi
	callq	puts@PLT
	movl	$1, %eax
	jmp	.LBB4_7
.LBB4_2:
	movq	%rsi, %r14
	movq	8(%rsi), %rdi
	callq	atoi
	movl	%eax, %ebx
	movq	16(%r14), %rdi
	callq	atoi
	movl	%eax, %ebp
	movslq	%ebx, %r14
	movq	%r14, %r15
	imulq	%r14, %r15
	shlq	$2, %r15
	movq	%r15, %rdi
	callq	malloc
	movq	%rax, %r12
	leaq	8(%rsp), %rdi
	movq	%r15, 24(%rsp)                  # 8-byte Spill
	movq	%r15, %rsi
	callq	hipMalloc
	imull	%r14d, %r14d
	cmpl	$1, %r14d
	adcl	$0, %r14d
	shlq	$2, %r14
	movq	%r14, 16(%rsp)                  # 8-byte Spill
	xorl	%r15d, %r15d
.LBB4_3:                                # %.preheader
                                        # =>This Inner Loop Header: Depth=1
	testl	%ebx, %ebx
	je	.LBB4_5
# %bb.4:                                # %.lr.ph.preheader
                                        #   in Loop: Header=BB4_3 Depth=1
	movq	%r12, %rdi
	xorl	%esi, %esi
	movq	16(%rsp), %rdx                  # 8-byte Reload
	callq	memset@PLT
.LBB4_5:                                # %._crit_edge
                                        #   in Loop: Header=BB4_3 Depth=1
	movq	8(%rsp), %rdi
	movq	%r12, %rsi
	movq	24(%rsp), %rdx                  # 8-byte Reload
	movl	$1, %ecx
	callq	hipMemcpy
	movl	$.L.str.5, %esi
	leaq	64(%rsp), %r14
	movq	%r14, %rdi
	movl	%ebx, %edx
	movl	%ebp, %ecx
	movl	%r15d, %r8d
	xorl	%eax, %eax
	callq	sprintf
	leal	1(%r15), %r13d
	cmpl	$4, %r15d
	movl	%r13d, %r8d
	movl	$0, %eax
	cmovel	%eax, %r8d
	movl	$.L.str.5, %esi
	leaq	32(%rsp), %r15
	movq	%r15, %rdi
	movl	%ebx, %edx
	movl	%ebp, %ecx
	xorl	%eax, %eax
	callq	sprintf
	movq	8(%rsp), %rdi
	movl	$1, (%rsp)
	movl	%ebx, %esi
	movl	%ebp, %edx
	movq	%r14, %rcx
	movq	%r15, %r8
	movl	$1, %r9d
	callq	_Z17parallel_multiplyPiiiPcS0_ii
	movl	%r13d, %r15d
	cmpl	$5, %r13d
	jne	.LBB4_3
# %bb.6:
	movq	8(%rsp), %rdi
	callq	hipFree
	movq	%r12, %rdi
	callq	free
	xorl	%eax, %eax
.LBB4_7:
	addq	$88, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end4:
	.size	main, .Lfunc_end4-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB5_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB5_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z15device_multiply12dcs_matrix_tS_Piii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end5:
	.size	__hip_module_ctor, .Lfunc_end5-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB6_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB6_2:
	retq
.Lfunc_end6:
	.size	__hip_module_dtor, .Lfunc_end6-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"r"
	.size	.L.str, 2

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"%d"
	.size	.L.str.1, 3

	.type	_Z15device_multiply12dcs_matrix_tS_Piii,@object # @_Z15device_multiply12dcs_matrix_tS_Piii
	.section	.rodata,"a",@progbits
	.globl	_Z15device_multiply12dcs_matrix_tS_Piii
	.p2align	3, 0x0
_Z15device_multiply12dcs_matrix_tS_Piii:
	.quad	_Z30__device_stub__device_multiply12dcs_matrix_tS_Piii
	.size	_Z15device_multiply12dcs_matrix_tS_Piii, 8

	.type	.L.str.2,@object                # @.str.2
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str.2:
	.asciz	"clock gettime"
	.size	.L.str.2, 14

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"DCSC A nnz: %d, A nzc: %d, B nnz: %d, B nzc: %d\nExecution Time: %f\n"
	.size	.L.str.3, 68

	.type	.L.str.5,@object                # @.str.5
.L.str.5:
	.asciz	"%d_%d_%d"
	.size	.L.str.5, 9

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z15device_multiply12dcs_matrix_tS_Piii"
	.size	.L__unnamed_1, 40

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.type	.Lstr,@object                   # @str
	.section	.rodata.str1.1,"aMS",@progbits,1
.Lstr:
	.asciz	"arguments: n nnz"
	.size	.Lstr, 17

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z30__device_stub__device_multiply12dcs_matrix_tS_Piii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z15device_multiply12dcs_matrix_tS_Piii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z15device_multiply12dcs_matrix_tS_Piii ; -- Begin function _Z15device_multiply12dcs_matrix_tS_Piii
	.globl	_Z15device_multiply12dcs_matrix_tS_Piii
	.p2align	8
	.type	_Z15device_multiply12dcs_matrix_tS_Piii,@function
_Z15device_multiply12dcs_matrix_tS_Piii: ; @_Z15device_multiply12dcs_matrix_tS_Piii
; %bb.0:
	s_clause 0x1
	s_load_b64 s[2:3], s[0:1], 0x78
	s_load_b32 s4, s[0:1], 0x64
	s_add_u32 s12, s0, 56
	s_addc_u32 s13, s1, 0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s5, s15, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_gt_i32 s5, s4
	s_cbranch_scc1 .LBB0_23
; %bb.1:
	v_and_b32_e32 v1, 0x3ff, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_add_nc_u32_e32 v1, s5, v1
	s_add_i32 s5, s5, s2
	s_min_i32 s2, s5, s4
	s_mov_b32 s4, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e64 s2, v1
	s_cbranch_execz .LBB0_23
; %bb.2:                                ; %.lr.ph63
	s_clause 0x4
	s_load_b32 s26, s[0:1], 0x2c
	s_load_b64 s[20:21], s[0:1], 0x70
	s_load_b32 s27, s[0:1], 0x8c
	s_load_b256 s[4:11], s[0:1], 0x8
	s_load_b256 s[12:19], s[12:13], 0x8
	v_bfe_u32 v9, v0, 10, 10
	s_mov_b32 s24, 0
	s_waitcnt lgkmcnt(0)
	s_cmp_gt_i32 s26, 0
	s_cselect_b32 s25, -1, 0
	s_add_i32 s26, s26, -1
	s_add_u32 s22, s0, 0x80
	s_addc_u32 s23, s1, 0
	s_and_b32 s1, s27, 0xffff
.LBB0_3:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_5 Depth 2
                                        ;       Child Loop BB0_7 Depth 3
                                        ;         Child Loop BB0_8 Depth 4
                                        ;       Child Loop BB0_20 Depth 3
	s_waitcnt vmcnt(0)
	v_ashrrev_i32_e32 v2, 31, v1
	s_mov_b32 s27, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[5:6], 2, v[1:2]
	v_add_co_u32 v2, vcc_lo, s14, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v3, vcc_lo, s15, v6, vcc_lo
	global_load_b64 v[2:3], v[2:3], off
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v4, v2, v9
	v_cmpx_lt_i32_e64 v4, v3
	s_cbranch_execz .LBB0_22
; %bb.4:                                ; %.lr.ph60
                                        ;   in Loop: Header=BB0_3 Depth=1
	v_add_co_u32 v5, vcc_lo, s12, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, s13, v6, vcc_lo
	s_load_b32 s0, s[22:23], 0xc
	s_mov_b32 s29, 0
	global_load_b32 v0, v[5:6], off
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s28, s0, 16
.LBB0_5:                                ;   Parent Loop BB0_3 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB0_7 Depth 3
                                        ;         Child Loop BB0_8 Depth 4
                                        ;       Child Loop BB0_20 Depth 3
	v_ashrrev_i32_e32 v5, 31, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[7:8], 2, v[4:5]
	v_add_co_u32 v5, vcc_lo, s18, v7
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v6, vcc_lo, s19, v8, vcc_lo
	s_and_not1_b32 vcc_lo, exec_lo, s25
	global_load_b32 v2, v[5:6], off
	v_mov_b32_e32 v6, -1
	s_cbranch_vccnz .LBB0_17
; %bb.6:                                ; %.lr.ph.i.preheader
                                        ;   in Loop: Header=BB0_5 Depth=2
	v_add_co_u32 v5, vcc_lo, s16, v7
	v_add_co_ci_u32_e32 v6, vcc_lo, s17, v8, vcc_lo
	v_mov_b32_e32 v10, s26
	v_mov_b32_e32 v8, 0
	s_mov_b32 s0, 0
	global_load_b32 v7, v[5:6], off
.LBB0_7:                                ; %.lr.ph.i
                                        ;   Parent Loop BB0_3 Depth=1
                                        ;     Parent Loop BB0_5 Depth=2
                                        ; =>    This Loop Header: Depth=3
                                        ;         Child Loop BB0_8 Depth 4
	v_mov_b32_e32 v11, v10
	s_mov_b32 s31, 0
                                        ; implicit-def: $sgpr30
                                        ; implicit-def: $sgpr33
                                        ; implicit-def: $sgpr34
.LBB0_8:                                ;   Parent Loop BB0_3 Depth=1
                                        ;     Parent Loop BB0_5 Depth=2
                                        ;       Parent Loop BB0_7 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v10, v11
	s_or_b32 s34, s34, exec_lo
	s_or_b32 s33, s33, exec_lo
	s_mov_b32 s35, exec_lo
	v_add_nc_u32_e32 v5, v10, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshrrev_b32_e32 v6, 31, v5
	v_add_nc_u32_e32 v5, v5, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v5, 1, v5
	v_ashrrev_i32_e32 v6, 31, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[11:12], 2, v[5:6]
	v_mov_b32_e32 v6, v5
	v_add_co_u32 v11, vcc_lo, s4, v11
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v12, vcc_lo, s5, v12, vcc_lo
	global_load_b32 v12, v[11:12], off
                                        ; implicit-def: $vgpr11
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u32_e64 v12, v7
	s_cbranch_execz .LBB0_12
; %bb.9:                                ;   in Loop: Header=BB0_8 Depth=4
	s_mov_b32 s37, -1
	s_mov_b32 s36, 0
	s_mov_b32 s38, exec_lo
                                        ; implicit-def: $vgpr11
                                        ; implicit-def: $sgpr39
	v_cmpx_ge_i32_e64 v12, v7
; %bb.10:                               ;   in Loop: Header=BB0_8 Depth=4
	v_add_nc_u32_e32 v6, -1, v5
	v_cmp_gt_i32_e32 vcc_lo, v12, v7
	s_mov_b32 s36, exec_lo
	s_mov_b32 s39, -1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v11, v10, v6, vcc_lo
	v_cmp_gt_i32_e32 vcc_lo, v8, v11
	s_or_not1_b32 s37, vcc_lo, exec_lo
; %bb.11:                               ; %Flow104
                                        ;   in Loop: Header=BB0_8 Depth=4
	s_or_b32 exec_lo, exec_lo, s38
	v_mov_b32_e32 v6, s39
	s_and_not1_b32 s34, s34, exec_lo
	s_and_b32 s36, s36, exec_lo
	s_and_not1_b32 s33, s33, exec_lo
	s_and_b32 s37, s37, exec_lo
	s_or_b32 s34, s34, s36
	s_or_b32 s33, s33, s37
.LBB0_12:                               ; %Flow103
                                        ;   in Loop: Header=BB0_8 Depth=4
	s_or_b32 exec_lo, exec_lo, s35
	s_xor_b32 s35, s34, -1
	s_and_b32 s36, exec_lo, s33
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_or_b32 s31, s36, s31
	s_and_not1_b32 s30, s30, exec_lo
	s_and_b32 s35, s35, exec_lo
	s_or_b32 s30, s30, s35
	s_and_not1_b32 exec_lo, exec_lo, s31
	s_cbranch_execnz .LBB0_8
; %bb.13:                               ; %loop.exit.guard
                                        ;   in Loop: Header=BB0_7 Depth=3
	s_or_b32 exec_lo, exec_lo, s31
	s_mov_b32 s31, -1
                                        ; implicit-def: $vgpr8
	s_and_saveexec_b32 s33, s30
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s30, exec_lo, s33
; %bb.14:                               ; %.outer.i
                                        ;   in Loop: Header=BB0_7 Depth=3
	v_cmp_ge_i32_e32 vcc_lo, v5, v10
	v_add_nc_u32_e32 v8, 1, v5
	v_mov_b32_e32 v6, -1
	s_or_not1_b32 s31, vcc_lo, exec_lo
; %bb.15:                               ; %Flow105
                                        ;   in Loop: Header=BB0_7 Depth=3
	s_or_b32 exec_lo, exec_lo, s30
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s30, exec_lo, s31
	s_or_b32 s0, s30, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB0_7
; %bb.16:                               ; %Flow106
                                        ;   in Loop: Header=BB0_5 Depth=2
	s_or_b32 exec_lo, exec_lo, s0
.LBB0_17:                               ; %_Z13binary_searchPiii.exit
                                        ;   in Loop: Header=BB0_5 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_mov_b32 s30, exec_lo
	v_cmpx_ne_u32_e32 -1, v6
	s_cbranch_execz .LBB0_21
; %bb.18:                               ;   in Loop: Header=BB0_5 Depth=2
	v_ashrrev_i32_e32 v7, 31, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[5:6], 2, v[6:7]
	v_add_co_u32 v5, vcc_lo, s6, v5
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v6, vcc_lo, s7, v6, vcc_lo
	global_load_b64 v[5:6], v[5:6], off
	s_waitcnt vmcnt(0)
	v_cmp_ne_u32_e32 vcc_lo, v6, v5
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_21
; %bb.19:                               ; %.lr.ph.preheader
                                        ;   in Loop: Header=BB0_5 Depth=2
	v_sub_nc_u32_e32 v10, v6, v5
	v_ashrrev_i32_e32 v6, 31, v5
	s_mov_b32 s31, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[7:8], 2, v[5:6]
	v_add_co_u32 v5, vcc_lo, s8, v7
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v6, vcc_lo, s9, v8, vcc_lo
	v_add_co_u32 v7, vcc_lo, s10, v7
	v_add_co_ci_u32_e32 v8, vcc_lo, s11, v8, vcc_lo
.LBB0_20:                               ; %.lr.ph
                                        ;   Parent Loop BB0_3 Depth=1
                                        ;     Parent Loop BB0_5 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	global_load_b32 v13, v[5:6], off
	global_load_b32 v14, v[7:8], off
	v_add_nc_u32_e32 v10, -1, v10
	v_add_co_u32 v7, s0, v7, 4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e64 v8, s0, 0, v8, s0
	s_waitcnt vmcnt(1)
	v_mad_u64_u32 v[11:12], null, v13, s3, v[0:1]
	s_waitcnt vmcnt(0)
	v_mul_lo_u32 v13, v14, v2
	v_ashrrev_i32_e32 v12, 31, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[11:12], 2, v[11:12]
	v_add_co_u32 v11, vcc_lo, s20, v11
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v12, vcc_lo, s21, v12, vcc_lo
	v_add_co_u32 v5, vcc_lo, v5, 4
	v_add_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
	global_atomic_add_u32 v[11:12], v13, off
	v_cmp_eq_u32_e32 vcc_lo, 0, v10
	s_or_b32 s31, vcc_lo, s31
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s31
	s_cbranch_execnz .LBB0_20
.LBB0_21:                               ; %.loopexit
                                        ;   in Loop: Header=BB0_5 Depth=2
	s_or_b32 exec_lo, exec_lo, s30
	v_add_nc_u32_e32 v4, s28, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_ge_i32_e32 vcc_lo, v4, v3
	s_or_b32 s29, vcc_lo, s29
	s_and_not1_b32 exec_lo, exec_lo, s29
	s_cbranch_execnz .LBB0_5
.LBB0_22:                               ; %Flow110
                                        ;   in Loop: Header=BB0_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s27
	v_add_nc_u32_e32 v1, s1, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_le_i32_e32 vcc_lo, s2, v1
	s_or_b32 s24, vcc_lo, s24
	s_and_not1_b32 exec_lo, exec_lo, s24
	s_cbranch_execnz .LBB0_3
.LBB0_23:                               ; %.loopexit54
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z15device_multiply12dcs_matrix_tS_Piii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 384
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 15
		.amdhsa_next_free_sgpr 40
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z15device_multiply12dcs_matrix_tS_Piii, .Lfunc_end0-_Z15device_multiply12dcs_matrix_tS_Piii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1008
; NumSgprs: 42
; NumVgprs: 15
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 5
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 42
; NumVGPRsForWavesPerEU: 15
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .offset:         0
        .size:           56
        .value_kind:     by_value
      - .offset:         56
        .size:           56
        .value_kind:     by_value
      - .address_space:  global
        .offset:         112
        .size:           8
        .value_kind:     global_buffer
      - .offset:         120
        .size:           4
        .value_kind:     by_value
      - .offset:         124
        .size:           4
        .value_kind:     by_value
      - .offset:         128
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         132
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         136
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         140
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         142
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         144
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         146
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         148
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         150
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         168
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         176
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         184
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         192
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 384
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z15device_multiply12dcs_matrix_tS_Piii
    .private_segment_fixed_size: 0
    .sgpr_count:     42
    .sgpr_spill_count: 0
    .symbol:         _Z15device_multiply12dcs_matrix_tS_Piii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     15
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
