#include <bits/stdint-uintn.h>
#include <stdio.h>
#include <sys/param.h>

struct RenderSettings {
    uint32_t *outputBuffer;
    int width;
    int height;
    double zoom;
    double xoffset;
    double yoffset;
    unsigned int iterations;
    uint32_t *deviceBuffer;
};

uint32_t *deviceBuffer;
char cudaInitialized = 0;

__global__ void mandelbrotCalc(struct RenderSettings rs) {
    int *deviceBuffer = (int *)rs.deviceBuffer;
    int index = blockIdx.x * blockDim.x + threadIdx.x;
    int stride = blockDim.x * gridDim.x;

    double cReal, cImag, zReal, zImag, z2Real, z2Imag, zrzi;
    int color;
    int colorbias;

    double x1 = rs.xoffset - 2.0 / rs.zoom * rs.width / rs.height;
    double x2 = rs.xoffset + 2.0 / rs.zoom * rs.width / rs.height;
    double y1 = rs.yoffset + 2.0 / rs.zoom;

    double pixel_pitch = (x2 - x1) / rs.width;

    int x, y;

    for (int w = index; w < rs.height * rs.width; w += stride) {

        y = w / rs.width;
        if (y > 0) {
            x = w % rs.width;
        } else {
            x = w;
        }

        cImag = y1 - pixel_pitch * y;
        cReal = x1 + pixel_pitch * x;

        zReal = cReal;
        zImag = cImag;

        color = 0x000000FF; // black as default for values that converge to 0

        for (int i = 0; i < rs.iterations; i++) {
            z2Real = zReal * zReal;
            z2Imag = zImag * zImag;
            zrzi = zReal * zImag;

            zReal = cReal + z2Real - z2Imag;
            zImag = zrzi + zrzi + cImag;

            if (z2Real + z2Imag > 4.0f) {
                colorbias = MIN(255, i * 510.0 / rs.iterations);
                color = (color | (colorbias << 24) | (colorbias << 16) | colorbias << 8);
                break;
            }
        }
        deviceBuffer[w] = color;
    }
}

__global__ void mandelbrotCalcSP(struct RenderSettings rs) {
    int *deviceBuffer = (int *)rs.deviceBuffer;
    int index = blockIdx.x * blockDim.x + threadIdx.x;
    int stride = blockDim.x * gridDim.x;

    float cReal, cImag, zReal, zImag, z2Real, z2Imag, zrzi;
    int color;
    int colorbias;

    float x1 = rs.xoffset - 2.0 / rs.zoom * rs.width / rs.height;
    float x2 = rs.xoffset + 2.0 / rs.zoom * rs.width / rs.height;
    float y1 = rs.yoffset + 2.0 / rs.zoom;

    float pixel_pitch = (x2 - x1) / rs.width;

    int x, y;

    for (int w = index; w < rs.height * rs.width; w += stride) {

        y = w / rs.width;
        if (y > 0) {
            x = w % rs.width;
        } else {
            x = w;
        }

        cImag = y1 - pixel_pitch * y;
        cReal = x1 + pixel_pitch * x;

        zReal = cReal;
        zImag = cImag;

        color = 0x000000FF; // black as default for values that converge to 0

        for (int i = 0; i < rs.iterations; i++) {
            z2Real = zReal * zReal;
            z2Imag = zImag * zImag;
            zrzi = zReal * zImag;

            zReal = cReal + z2Real - z2Imag;
            zImag = zrzi + zrzi + cImag;

            if (z2Real + z2Imag > 4.0f) {
                colorbias = MIN(255, i * 510.0 / rs.iterations);
                color = (color | (colorbias << 24) | (colorbias << 16) | colorbias << 8);
                break;
            }
        }
        deviceBuffer[w] = color;
    }
}

extern "C" void freeCUDA() {
    if (cudaInitialized == 1) {
        cudaFree(deviceBuffer);
        cudaInitialized = 0;
    }
}

extern "C" void initCUDA(struct RenderSettings rs) {
    // allocates device buffer on first run
    // destroys and re-allocates buffer if window dimensions change

    static int width = 0;
    static int height = 0;
    if (cudaInitialized == 0) {
        cudaMalloc((void **)&deviceBuffer, rs.width * rs.height * 4);
        width = rs.width;
        height = rs.height;
        cudaInitialized = 1;
    } else {
        if (rs.width != width || rs.height != height) {
            freeCUDA();
            initCUDA(rs);
        }
    }
}

extern "C" void mandelbrotCUDA(struct RenderSettings rs) {
    initCUDA(rs);
    uint32_t *screenBuffer = rs.outputBuffer;
    rs.deviceBuffer = deviceBuffer;
    mandelbrotCalc<<<2048, 1024>>>(rs);
    cudaDeviceSynchronize();
    cudaMemcpy(screenBuffer, deviceBuffer, rs.width * rs.height * 4, cudaMemcpyDeviceToHost);
}

extern "C" void mandelbrotCUDAsp(struct RenderSettings rs) {
    initCUDA(rs);
    uint32_t *screenBuffer = rs.outputBuffer;
    rs.deviceBuffer = deviceBuffer;
    mandelbrotCalcSP<<<2048, 1024>>>(rs);
    cudaDeviceSynchronize();
    cudaMemcpy(screenBuffer, deviceBuffer, rs.width * rs.height * 4, cudaMemcpyDeviceToHost);
}

	.file	"tmpxft_002c0c1e_00000000-6_mandelcuda.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2046:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2046:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	freeCUDA
	.type	freeCUDA, @function
freeCUDA:
.LFB2040:
	.cfi_startproc
	endbr64
	cmpb	$1, cudaInitialized(%rip)
	jne	.L5
	pushq	%rax
	.cfi_def_cfa_offset 16
	movq	deviceBuffer(%rip), %rdi
	call	cudaFree@PLT
	movb	$0, cudaInitialized(%rip)
	popq	%rdx
	.cfi_def_cfa_offset 8
	ret
.L5:
	ret
	.cfi_endproc
.LFE2040:
	.size	freeCUDA, .-freeCUDA
	.globl	initCUDA
	.type	initCUDA, @function
initCUDA:
.LFB2041:
	.cfi_startproc
	endbr64
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	pushq	%rbx
	.cfi_def_cfa_offset 24
	.cfi_offset 3, -24
	pushq	%rdx
	.cfi_def_cfa_offset 32
.L13:
	cmpb	$0, cudaInitialized(%rip)
	movl	40(%rsp), %ebp
	movl	44(%rsp), %ebx
	jne	.L10
	movl	%ebp, %esi
	leaq	deviceBuffer(%rip), %rdi
	imull	%ebx, %esi
	sall	$2, %esi
	movslq	%esi, %rsi
	call	cudaMalloc@PLT
	movl	%ebp, _ZZ8initCUDAE5width(%rip)
	movl	%ebx, _ZZ8initCUDAE6height(%rip)
	movb	$1, cudaInitialized(%rip)
	jmp	.L9
.L10:
	cmpl	%ebp, _ZZ8initCUDAE5width(%rip)
	jne	.L12
	cmpl	%ebx, _ZZ8initCUDAE6height(%rip)
	je	.L9
.L12:
	call	freeCUDA
	jmp	.L13
.L9:
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2041:
	.size	initCUDA, .-initCUDA
	.globl	_Z48__device_stub__Z14mandelbrotCalc14RenderSettingsR14RenderSettings
	.type	_Z48__device_stub__Z14mandelbrotCalc14RenderSettingsR14RenderSettings, @function
_Z48__device_stub__Z14mandelbrotCalc14RenderSettingsR14RenderSettings:
.LFB2068:
	.cfi_startproc
	endbr64
	subq	$88, %rsp
	.cfi_def_cfa_offset 96
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rcx
	movq	%rdi, 64(%rsp)
	movq	%rsp, %rdx
	movabsq	$4294967297, %rax
	leaq	28(%rsp), %rsi
	leaq	16(%rsp), %rdi
	movl	$1, 24(%rsp)
	movq	%rax, 16(%rsp)
	movq	%rax, 28(%rsp)
	movl	$1, 36(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L15
	pushq	8(%rsp)
	.cfi_def_cfa_offset 104
	leaq	_Z14mandelbrotCalc14RenderSettings(%rip), %rdi
	pushq	8(%rsp)
	.cfi_def_cfa_offset 112
	movq	44(%rsp), %rcx
	movl	52(%rsp), %r8d
	movq	32(%rsp), %rsi
	movl	40(%rsp), %edx
	leaq	80(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 104
	popq	%rdx
	.cfi_def_cfa_offset 96
.L15:
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L17
	call	__stack_chk_fail@PLT
.L17:
	addq	$88, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2068:
	.size	_Z48__device_stub__Z14mandelbrotCalc14RenderSettingsR14RenderSettings, .-_Z48__device_stub__Z14mandelbrotCalc14RenderSettingsR14RenderSettings
	.globl	_Z14mandelbrotCalc14RenderSettings
	.type	_Z14mandelbrotCalc14RenderSettings, @function
_Z14mandelbrotCalc14RenderSettings:
.LFB2069:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	16(%rsp), %rdi
	call	_Z48__device_stub__Z14mandelbrotCalc14RenderSettingsR14RenderSettings
	popq	%rdx
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2069:
	.size	_Z14mandelbrotCalc14RenderSettings, .-_Z14mandelbrotCalc14RenderSettings
	.globl	mandelbrotCUDA
	.type	mandelbrotCUDA, @function
mandelbrotCUDA:
.LFB2042:
	.cfi_startproc
	endbr64
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	movl	$14, %ecx
	pushq	%rbx
	.cfi_def_cfa_offset 24
	.cfi_offset 3, -24
	subq	$168, %rsp
	.cfi_def_cfa_offset 192
	movq	%fs:40, %rax
	movq	%rax, 152(%rsp)
	xorl	%eax, %eax
	movq	%rsp, %rdi
	leaq	192(%rsp), %rsi
	rep movsl
	call	initCUDA
	movl	$4194305, %edx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$2097153, %edi
	salq	$10, %rdx
	movl	$1, %ecx
	movq	192(%rsp), %rbx
	salq	$11, %rdi
	addq	$64, %rsp
	.cfi_def_cfa_offset 128
	movl	$1, %esi
	movq	deviceBuffer(%rip), %rbp
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L22
	movq	%rbp, 176(%rsp)
	leaq	32(%rsp), %rdi
	movl	$14, %ecx
	leaq	128(%rsp), %rsi
	rep movsl
	leaq	32(%rsp), %rdi
	call	_Z48__device_stub__Z14mandelbrotCalc14RenderSettingsR14RenderSettings
.L22:
	call	cudaDeviceSynchronize@PLT
	movq	88(%rsp), %rax
	subq	%fs:40, %rax
	je	.L23
	call	__stack_chk_fail@PLT
.L23:
	movl	136(%rsp), %edx
	imull	140(%rsp), %edx
	movq	%rbx, %rdi
	movl	$2, %ecx
	movq	deviceBuffer(%rip), %rsi
	addq	$104, %rsp
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	sall	$2, %edx
	movslq	%edx, %rdx
	jmp	cudaMemcpy@PLT
	.cfi_endproc
.LFE2042:
	.size	mandelbrotCUDA, .-mandelbrotCUDA
	.globl	_Z50__device_stub__Z16mandelbrotCalcSP14RenderSettingsR14RenderSettings
	.type	_Z50__device_stub__Z16mandelbrotCalcSP14RenderSettingsR14RenderSettings, @function
_Z50__device_stub__Z16mandelbrotCalcSP14RenderSettingsR14RenderSettings:
.LFB2070:
	.cfi_startproc
	endbr64
	subq	$88, %rsp
	.cfi_def_cfa_offset 96
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rcx
	movq	%rdi, 64(%rsp)
	movq	%rsp, %rdx
	movabsq	$4294967297, %rax
	leaq	28(%rsp), %rsi
	leaq	16(%rsp), %rdi
	movl	$1, 24(%rsp)
	movq	%rax, 16(%rsp)
	movq	%rax, 28(%rsp)
	movl	$1, 36(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L26
	pushq	8(%rsp)
	.cfi_def_cfa_offset 104
	leaq	_Z16mandelbrotCalcSP14RenderSettings(%rip), %rdi
	pushq	8(%rsp)
	.cfi_def_cfa_offset 112
	movq	44(%rsp), %rcx
	movl	52(%rsp), %r8d
	movq	32(%rsp), %rsi
	movl	40(%rsp), %edx
	leaq	80(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 104
	popq	%rdx
	.cfi_def_cfa_offset 96
.L26:
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L28
	call	__stack_chk_fail@PLT
.L28:
	addq	$88, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2070:
	.size	_Z50__device_stub__Z16mandelbrotCalcSP14RenderSettingsR14RenderSettings, .-_Z50__device_stub__Z16mandelbrotCalcSP14RenderSettingsR14RenderSettings
	.globl	_Z16mandelbrotCalcSP14RenderSettings
	.type	_Z16mandelbrotCalcSP14RenderSettings, @function
_Z16mandelbrotCalcSP14RenderSettings:
.LFB2071:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	16(%rsp), %rdi
	call	_Z50__device_stub__Z16mandelbrotCalcSP14RenderSettingsR14RenderSettings
	popq	%rdx
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2071:
	.size	_Z16mandelbrotCalcSP14RenderSettings, .-_Z16mandelbrotCalcSP14RenderSettings
	.globl	mandelbrotCUDAsp
	.type	mandelbrotCUDAsp, @function
mandelbrotCUDAsp:
.LFB2043:
	.cfi_startproc
	endbr64
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	movl	$14, %ecx
	pushq	%rbx
	.cfi_def_cfa_offset 24
	.cfi_offset 3, -24
	subq	$168, %rsp
	.cfi_def_cfa_offset 192
	movq	%fs:40, %rax
	movq	%rax, 152(%rsp)
	xorl	%eax, %eax
	movq	%rsp, %rdi
	leaq	192(%rsp), %rsi
	rep movsl
	call	initCUDA
	movl	$4194305, %edx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$2097153, %edi
	salq	$10, %rdx
	movl	$1, %ecx
	movq	192(%rsp), %rbx
	salq	$11, %rdi
	addq	$64, %rsp
	.cfi_def_cfa_offset 128
	movl	$1, %esi
	movq	deviceBuffer(%rip), %rbp
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L33
	movq	%rbp, 176(%rsp)
	leaq	32(%rsp), %rdi
	movl	$14, %ecx
	leaq	128(%rsp), %rsi
	rep movsl
	leaq	32(%rsp), %rdi
	call	_Z50__device_stub__Z16mandelbrotCalcSP14RenderSettingsR14RenderSettings
.L33:
	call	cudaDeviceSynchronize@PLT
	movq	88(%rsp), %rax
	subq	%fs:40, %rax
	je	.L34
	call	__stack_chk_fail@PLT
.L34:
	movl	136(%rsp), %edx
	imull	140(%rsp), %edx
	movq	%rbx, %rdi
	movl	$2, %ecx
	movq	deviceBuffer(%rip), %rsi
	addq	$104, %rsp
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	sall	$2, %edx
	movslq	%edx, %rdx
	jmp	cudaMemcpy@PLT
	.cfi_endproc
.LFE2043:
	.size	mandelbrotCUDAsp, .-mandelbrotCUDAsp
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z16mandelbrotCalcSP14RenderSettings"
.LC1:
	.string	"_Z14mandelbrotCalc14RenderSettings"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2073:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z16mandelbrotCalcSP14RenderSettings(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC1(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z14mandelbrotCalc14RenderSettings(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2073:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.local	_ZZ8initCUDAE6height
	.comm	_ZZ8initCUDAE6height,4,4
	.local	_ZZ8initCUDAE5width
	.comm	_ZZ8initCUDAE5width,4,4
	.globl	cudaInitialized
	.bss
	.type	cudaInitialized, @object
	.size	cudaInitialized, 1
cudaInitialized:
	.zero	1
	.globl	deviceBuffer
	.align 8
	.type	deviceBuffer, @object
	.size	deviceBuffer, 8
deviceBuffer:
	.zero	8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include <bits/stdint-uintn.h>
#include <stdio.h>
#include <sys/param.h>

struct RenderSettings {
    uint32_t *outputBuffer;
    int width;
    int height;
    double zoom;
    double xoffset;
    double yoffset;
    unsigned int iterations;
    uint32_t *deviceBuffer;
};

uint32_t *deviceBuffer;
char cudaInitialized = 0;

__global__ void mandelbrotCalc(struct RenderSettings rs) {
    int *deviceBuffer = (int *)rs.deviceBuffer;
    int index = blockIdx.x * blockDim.x + threadIdx.x;
    int stride = blockDim.x * gridDim.x;

    double cReal, cImag, zReal, zImag, z2Real, z2Imag, zrzi;
    int color;
    int colorbias;

    double x1 = rs.xoffset - 2.0 / rs.zoom * rs.width / rs.height;
    double x2 = rs.xoffset + 2.0 / rs.zoom * rs.width / rs.height;
    double y1 = rs.yoffset + 2.0 / rs.zoom;

    double pixel_pitch = (x2 - x1) / rs.width;

    int x, y;

    for (int w = index; w < rs.height * rs.width; w += stride) {

        y = w / rs.width;
        if (y > 0) {
            x = w % rs.width;
        } else {
            x = w;
        }

        cImag = y1 - pixel_pitch * y;
        cReal = x1 + pixel_pitch * x;

        zReal = cReal;
        zImag = cImag;

        color = 0x000000FF; // black as default for values that converge to 0

        for (int i = 0; i < rs.iterations; i++) {
            z2Real = zReal * zReal;
            z2Imag = zImag * zImag;
            zrzi = zReal * zImag;

            zReal = cReal + z2Real - z2Imag;
            zImag = zrzi + zrzi + cImag;

            if (z2Real + z2Imag > 4.0f) {
                colorbias = MIN(255, i * 510.0 / rs.iterations);
                color = (color | (colorbias << 24) | (colorbias << 16) | colorbias << 8);
                break;
            }
        }
        deviceBuffer[w] = color;
    }
}

__global__ void mandelbrotCalcSP(struct RenderSettings rs) {
    int *deviceBuffer = (int *)rs.deviceBuffer;
    int index = blockIdx.x * blockDim.x + threadIdx.x;
    int stride = blockDim.x * gridDim.x;

    float cReal, cImag, zReal, zImag, z2Real, z2Imag, zrzi;
    int color;
    int colorbias;

    float x1 = rs.xoffset - 2.0 / rs.zoom * rs.width / rs.height;
    float x2 = rs.xoffset + 2.0 / rs.zoom * rs.width / rs.height;
    float y1 = rs.yoffset + 2.0 / rs.zoom;

    float pixel_pitch = (x2 - x1) / rs.width;

    int x, y;

    for (int w = index; w < rs.height * rs.width; w += stride) {

        y = w / rs.width;
        if (y > 0) {
            x = w % rs.width;
        } else {
            x = w;
        }

        cImag = y1 - pixel_pitch * y;
        cReal = x1 + pixel_pitch * x;

        zReal = cReal;
        zImag = cImag;

        color = 0x000000FF; // black as default for values that converge to 0

        for (int i = 0; i < rs.iterations; i++) {
            z2Real = zReal * zReal;
            z2Imag = zImag * zImag;
            zrzi = zReal * zImag;

            zReal = cReal + z2Real - z2Imag;
            zImag = zrzi + zrzi + cImag;

            if (z2Real + z2Imag > 4.0f) {
                colorbias = MIN(255, i * 510.0 / rs.iterations);
                color = (color | (colorbias << 24) | (colorbias << 16) | colorbias << 8);
                break;
            }
        }
        deviceBuffer[w] = color;
    }
}

extern "C" void freeCUDA() {
    if (cudaInitialized == 1) {
        hipFree(deviceBuffer);
        cudaInitialized = 0;
    }
}

extern "C" void initCUDA(struct RenderSettings rs) {
    // allocates device buffer on first run
    // destroys and re-allocates buffer if window dimensions change

    static int width = 0;
    static int height = 0;
    if (cudaInitialized == 0) {
        hipMalloc((void **)&deviceBuffer, rs.width * rs.height * 4);
        width = rs.width;
        height = rs.height;
        cudaInitialized = 1;
    } else {
        if (rs.width != width || rs.height != height) {
            freeCUDA();
            initCUDA(rs);
        }
    }
}

extern "C" void mandelbrotCUDA(struct RenderSettings rs) {
    initCUDA(rs);
    uint32_t *screenBuffer = rs.outputBuffer;
    rs.deviceBuffer = deviceBuffer;
    mandelbrotCalc<<<2048, 1024>>>(rs);
    hipDeviceSynchronize();
    hipMemcpy(screenBuffer, deviceBuffer, rs.width * rs.height * 4, hipMemcpyDeviceToHost);
}

extern "C" void mandelbrotCUDAsp(struct RenderSettings rs) {
    initCUDA(rs);
    uint32_t *screenBuffer = rs.outputBuffer;
    rs.deviceBuffer = deviceBuffer;
    mandelbrotCalcSP<<<2048, 1024>>>(rs);
    hipDeviceSynchronize();
    hipMemcpy(screenBuffer, deviceBuffer, rs.width * rs.height * 4, hipMemcpyDeviceToHost);
}

	.text
	.file	"mandelcuda.hip"
	.globl	_Z29__device_stub__mandelbrotCalc14RenderSettings # -- Begin function _Z29__device_stub__mandelbrotCalc14RenderSettings
	.type	_Z29__device_stub__mandelbrotCalc14RenderSettings,@function
_Z29__device_stub__mandelbrotCalc14RenderSettings: # @_Z29__device_stub__mandelbrotCalc14RenderSettings
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$64, %rsp
	.cfi_def_cfa_offset 112
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	112(%rsp), %rax
	movq	%rsp, %rbx
	movq	%rax, (%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z14mandelbrotCalc14RenderSettings, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$80, %rsp
	.cfi_adjust_cfa_offset -80
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z29__device_stub__mandelbrotCalc14RenderSettings, .Lfunc_end0-_Z29__device_stub__mandelbrotCalc14RenderSettings
	.cfi_endproc
                                        # -- End function
	.globl	_Z31__device_stub__mandelbrotCalcSP14RenderSettings # -- Begin function _Z31__device_stub__mandelbrotCalcSP14RenderSettings
	.type	_Z31__device_stub__mandelbrotCalcSP14RenderSettings,@function
_Z31__device_stub__mandelbrotCalcSP14RenderSettings: # @_Z31__device_stub__mandelbrotCalcSP14RenderSettings
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$64, %rsp
	.cfi_def_cfa_offset 112
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	112(%rsp), %rax
	movq	%rsp, %rbx
	movq	%rax, (%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z16mandelbrotCalcSP14RenderSettings, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$80, %rsp
	.cfi_adjust_cfa_offset -80
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z31__device_stub__mandelbrotCalcSP14RenderSettings, .Lfunc_end1-_Z31__device_stub__mandelbrotCalcSP14RenderSettings
	.cfi_endproc
                                        # -- End function
	.globl	freeCUDA                        # -- Begin function freeCUDA
	.type	freeCUDA,@function
freeCUDA:                               # @freeCUDA
	.cfi_startproc
# %bb.0:
	cmpb	$1, cudaInitialized(%rip)
	jne	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	movq	deviceBuffer(%rip), %rdi
	callq	hipFree
	movb	$0, cudaInitialized(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	freeCUDA, .Lfunc_end2-freeCUDA
	.cfi_endproc
                                        # -- End function
	.globl	initCUDA                        # -- Begin function initCUDA
	.type	initCUDA,@function
initCUDA:                               # @initCUDA
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	.cfi_offset %rbp, -16
	leaq	32(%rsp), %rbx
	movb	cudaInitialized(%rip), %al
	testb	%al, %al
	je	.LBB3_7
# %bb.1:                                # %.lr.ph
	movl	_ZZ8initCUDAE5width(%rip), %ecx
	movl	8(%rbx), %ebp
	movl	12(%rbx), %r14d
.LBB3_2:                                # =>This Inner Loop Header: Depth=1
	cmpl	%ecx, %ebp
	jne	.LBB3_4
# %bb.3:                                #   in Loop: Header=BB3_2 Depth=1
	cmpl	_ZZ8initCUDAE6height(%rip), %r14d
	je	.LBB3_8
.LBB3_4:                                #   in Loop: Header=BB3_2 Depth=1
	cmpb	$1, %al
	jne	.LBB3_6
# %bb.5:                                #   in Loop: Header=BB3_2 Depth=1
	movq	deviceBuffer(%rip), %rdi
	callq	hipFree
	movb	$0, cudaInitialized(%rip)
	xorl	%eax, %eax
	movl	_ZZ8initCUDAE5width(%rip), %ecx
.LBB3_6:                                # %freeCUDA.exit
                                        #   in Loop: Header=BB3_2 Depth=1
	testb	%al, %al
	jne	.LBB3_2
.LBB3_7:                                # %tailrecurse._crit_edge
	movl	8(%rbx), %ebp
	movl	12(%rbx), %ebx
	movl	%ebp, %eax
	imull	%ebx, %eax
	shll	$2, %eax
	movslq	%eax, %rsi
	movl	$deviceBuffer, %edi
	callq	hipMalloc
	movl	%ebp, _ZZ8initCUDAE5width(%rip)
	movl	%ebx, _ZZ8initCUDAE6height(%rip)
	movb	$1, cudaInitialized(%rip)
.LBB3_8:                                # %.loopexit
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	initCUDA, .Lfunc_end3-initCUDA
	.cfi_endproc
                                        # -- End function
	.globl	mandelbrotCUDA                  # -- Begin function mandelbrotCUDA
	.type	mandelbrotCUDA,@function
mandelbrotCUDA:                         # @mandelbrotCUDA
	.cfi_startproc
# %bb.0:
	pushq	%r14
	.cfi_def_cfa_offset 16
	pushq	%rbx
	.cfi_def_cfa_offset 24
	subq	$56, %rsp
	.cfi_def_cfa_offset 80
	.cfi_offset %rbx, -24
	.cfi_offset %r14, -16
	leaq	80(%rsp), %r14
	movq	48(%r14), %rax
	movq	%rax, 48(%rsp)
	movaps	(%r14), %xmm0
	movaps	16(%r14), %xmm1
	movaps	32(%r14), %xmm2
	movups	%xmm2, 32(%rsp)
	movups	%xmm1, 16(%rsp)
	movups	%xmm0, (%rsp)
	callq	initCUDA
	movq	(%r14), %rbx
	movq	deviceBuffer(%rip), %rax
	movq	%rax, 48(%r14)
	movabsq	$4294968320, %rdx               # imm = 0x100000400
	leaq	1024(%rdx), %rdi
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB4_2
# %bb.1:
	movq	48(%r14), %rax
	movq	%rax, 48(%rsp)
	movups	(%r14), %xmm0
	movups	16(%r14), %xmm1
	movups	32(%r14), %xmm2
	movups	%xmm2, 32(%rsp)
	movups	%xmm1, 16(%rsp)
	movups	%xmm0, (%rsp)
	callq	_Z29__device_stub__mandelbrotCalc14RenderSettings
.LBB4_2:
	callq	hipDeviceSynchronize
	movq	deviceBuffer(%rip), %rsi
	movl	8(%r14), %eax
	imull	12(%r14), %eax
	shll	$2, %eax
	movslq	%eax, %rdx
	movq	%rbx, %rdi
	movl	$2, %ecx
	addq	$56, %rsp
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	jmp	hipMemcpy                       # TAILCALL
.Lfunc_end4:
	.size	mandelbrotCUDA, .Lfunc_end4-mandelbrotCUDA
	.cfi_endproc
                                        # -- End function
	.globl	mandelbrotCUDAsp                # -- Begin function mandelbrotCUDAsp
	.type	mandelbrotCUDAsp,@function
mandelbrotCUDAsp:                       # @mandelbrotCUDAsp
	.cfi_startproc
# %bb.0:
	pushq	%r14
	.cfi_def_cfa_offset 16
	pushq	%rbx
	.cfi_def_cfa_offset 24
	subq	$56, %rsp
	.cfi_def_cfa_offset 80
	.cfi_offset %rbx, -24
	.cfi_offset %r14, -16
	leaq	80(%rsp), %r14
	movq	48(%r14), %rax
	movq	%rax, 48(%rsp)
	movaps	(%r14), %xmm0
	movaps	16(%r14), %xmm1
	movaps	32(%r14), %xmm2
	movups	%xmm2, 32(%rsp)
	movups	%xmm1, 16(%rsp)
	movups	%xmm0, (%rsp)
	callq	initCUDA
	movq	(%r14), %rbx
	movq	deviceBuffer(%rip), %rax
	movq	%rax, 48(%r14)
	movabsq	$4294968320, %rdx               # imm = 0x100000400
	leaq	1024(%rdx), %rdi
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB5_2
# %bb.1:
	movq	48(%r14), %rax
	movq	%rax, 48(%rsp)
	movups	(%r14), %xmm0
	movups	16(%r14), %xmm1
	movups	32(%r14), %xmm2
	movups	%xmm2, 32(%rsp)
	movups	%xmm1, 16(%rsp)
	movups	%xmm0, (%rsp)
	callq	_Z31__device_stub__mandelbrotCalcSP14RenderSettings
.LBB5_2:
	callq	hipDeviceSynchronize
	movq	deviceBuffer(%rip), %rsi
	movl	8(%r14), %eax
	imull	12(%r14), %eax
	shll	$2, %eax
	movslq	%eax, %rdx
	movq	%rbx, %rdi
	movl	$2, %ecx
	addq	$56, %rsp
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	jmp	hipMemcpy                       # TAILCALL
.Lfunc_end5:
	.size	mandelbrotCUDAsp, .Lfunc_end5-mandelbrotCUDAsp
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB6_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB6_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z14mandelbrotCalc14RenderSettings, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z16mandelbrotCalcSP14RenderSettings, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end6:
	.size	__hip_module_ctor, .Lfunc_end6-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB7_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB7_2:
	retq
.Lfunc_end7:
	.size	__hip_module_dtor, .Lfunc_end7-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	deviceBuffer,@object            # @deviceBuffer
	.bss
	.globl	deviceBuffer
	.p2align	3, 0x0
deviceBuffer:
	.quad	0
	.size	deviceBuffer, 8

	.type	cudaInitialized,@object         # @cudaInitialized
	.globl	cudaInitialized
cudaInitialized:
	.byte	0                               # 0x0
	.size	cudaInitialized, 1

	.type	_Z14mandelbrotCalc14RenderSettings,@object # @_Z14mandelbrotCalc14RenderSettings
	.section	.rodata,"a",@progbits
	.globl	_Z14mandelbrotCalc14RenderSettings
	.p2align	3, 0x0
_Z14mandelbrotCalc14RenderSettings:
	.quad	_Z29__device_stub__mandelbrotCalc14RenderSettings
	.size	_Z14mandelbrotCalc14RenderSettings, 8

	.type	_Z16mandelbrotCalcSP14RenderSettings,@object # @_Z16mandelbrotCalcSP14RenderSettings
	.globl	_Z16mandelbrotCalcSP14RenderSettings
	.p2align	3, 0x0
_Z16mandelbrotCalcSP14RenderSettings:
	.quad	_Z31__device_stub__mandelbrotCalcSP14RenderSettings
	.size	_Z16mandelbrotCalcSP14RenderSettings, 8

	.type	_ZZ8initCUDAE5width,@object     # @_ZZ8initCUDAE5width
	.local	_ZZ8initCUDAE5width
	.comm	_ZZ8initCUDAE5width,4,4
	.type	_ZZ8initCUDAE6height,@object    # @_ZZ8initCUDAE6height
	.local	_ZZ8initCUDAE6height
	.comm	_ZZ8initCUDAE6height,4,4
	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z14mandelbrotCalc14RenderSettings"
	.size	.L__unnamed_1, 35

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z16mandelbrotCalcSP14RenderSettings"
	.size	.L__unnamed_2, 37

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z29__device_stub__mandelbrotCalc14RenderSettings
	.addrsig_sym _Z31__device_stub__mandelbrotCalcSP14RenderSettings
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym deviceBuffer
	.addrsig_sym _Z14mandelbrotCalc14RenderSettings
	.addrsig_sym _Z16mandelbrotCalcSP14RenderSettings
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z14mandelbrotCalc14RenderSettings ; -- Begin function _Z14mandelbrotCalc14RenderSettings
	.globl	_Z14mandelbrotCalc14RenderSettings
	.p2align	8
	.type	_Z14mandelbrotCalc14RenderSettings,@function
_Z14mandelbrotCalc14RenderSettings:     ; @_Z14mandelbrotCalc14RenderSettings
; %bb.0:
	s_clause 0x1
	s_load_b32 s4, s[0:1], 0x44
	s_load_b64 s[2:3], s[0:1], 0x8
	s_add_u32 s6, s0, 56
	s_addc_u32 s7, s1, 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s11, s4, 0xffff
	s_mul_i32 s8, s3, s2
	v_mad_u64_u32 v[1:2], null, s15, s11, v[0:1]
	s_mov_b32 s4, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e64 s8, v1
	s_cbranch_execz .LBB0_14
; %bb.1:                                ; %.lr.ph66
	s_clause 0x1
	s_load_b128 s[12:15], s[0:1], 0x10
	s_load_b64 s[16:17], s[0:1], 0x20
	s_waitcnt lgkmcnt(0)
	v_div_scale_f64 v[2:3], null, s[12:13], s[12:13], 2.0
	v_div_scale_f64 v[8:9], vcc_lo, 2.0, s[12:13], 2.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[4:5], v[2:3]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0
	v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0
	v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[6:7], v[8:9], v[4:5]
	v_fma_f64 v[2:3], -v[2:3], v[6:7], v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_fmas_f64 v[2:3], v[2:3], v[4:5], v[6:7]
	v_cvt_f64_i32_e32 v[7:8], s2
	v_div_fixup_f64 v[5:6], v[2:3], s[12:13], 2.0
	v_cvt_f64_i32_e32 v[2:3], s3
	s_clause 0x1
	s_load_b32 s3, s[0:1], 0x28
	s_load_b64 s[4:5], s[0:1], 0x30
	s_load_b32 s6, s[6:7], 0x0
	s_mov_b32 s7, 0
	s_waitcnt lgkmcnt(0)
	s_cmp_lg_u32 s3, 0
	s_cselect_b32 s1, -1, 0
	s_ashr_i32 s9, s2, 31
	s_mul_i32 s6, s6, s11
	s_add_i32 s0, s2, s9
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b32 s10, s0, s9
	v_cvt_f32_u32_e32 v0, s10
	s_sub_i32 s0, 0, s10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_rcp_iflag_f32_e32 v0, v0
	v_mul_f64 v[9:10], v[5:6], v[7:8]
	v_add_f64 v[5:6], v[5:6], s[16:17]
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v0, 0x4f7ffffe, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_cvt_u32_f32_e32 v0, v0
	v_div_scale_f64 v[11:12], null, v[2:3], v[2:3], v[9:10]
	v_div_scale_f64 v[17:18], vcc_lo, v[9:10], v[2:3], v[9:10]
	v_rcp_f64_e32 v[13:14], v[11:12]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[15:16], -v[11:12], v[13:14], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[13:14], v[13:14], v[15:16], v[13:14]
	v_fma_f64 v[15:16], -v[11:12], v[13:14], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[13:14], v[13:14], v[15:16], v[13:14]
	v_mul_f64 v[15:16], v[17:18], v[13:14]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[11:12], -v[11:12], v[15:16], v[17:18]
	v_div_fmas_f64 v[11:12], v[11:12], v[13:14], v[15:16]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_div_fixup_f64 v[9:10], v[11:12], v[2:3], v[9:10]
	v_mul_lo_u32 v2, s0, v0
	v_mul_hi_u32 v2, v0, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v0, v0, v2
	v_add_f64 v[3:4], s[14:15], -v[9:10]
	v_add_f64 v[9:10], s[14:15], v[9:10]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[9:10], v[9:10], -v[3:4]
	v_div_scale_f64 v[11:12], null, v[7:8], v[7:8], v[9:10]
	v_div_scale_f64 v[17:18], vcc_lo, v[9:10], v[7:8], v[9:10]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[13:14], v[11:12]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[15:16], -v[11:12], v[13:14], 1.0
	v_fma_f64 v[13:14], v[13:14], v[15:16], v[13:14]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[15:16], -v[11:12], v[13:14], 1.0
	v_fma_f64 v[13:14], v[13:14], v[15:16], v[13:14]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[15:16], v[17:18], v[13:14]
	v_fma_f64 v[11:12], -v[11:12], v[15:16], v[17:18]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f64 v[11:12], v[11:12], v[13:14], v[15:16]
	v_div_fixup_f64 v[7:8], v[11:12], v[7:8], v[9:10]
	v_cvt_f64_u32_e32 v[9:10], s3
.LBB0_2:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_6 Depth 2
	v_ashrrev_i32_e32 v2, 31, v1
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v11, v1, v2
	v_xor_b32_e32 v11, v11, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v12, v11, v0
	v_mul_lo_u32 v13, v12, s10
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v11, v11, v13
	v_add_nc_u32_e32 v13, 1, v12
	v_subrev_nc_u32_e32 v14, s10, v11
	v_cmp_le_u32_e32 vcc_lo, s10, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v12, v12, v13 :: v_dual_cndmask_b32 v11, v11, v14
	v_xor_b32_e32 v14, s9, v2
	v_add_nc_u32_e32 v13, 1, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_le_u32_e32 vcc_lo, s10, v11
	v_dual_cndmask_b32 v11, v12, v13 :: v_dual_mov_b32 v12, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v11, v11, v14
	v_sub_nc_u32_e32 v11, v11, v14
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e32 0, v11
; %bb.3:                                ;   in Loop: Header=BB0_2 Depth=1
	v_mul_lo_u32 v12, v11, s2
	s_delay_alu instid0(VALU_DEP_1)
	v_sub_nc_u32_e32 v12, v1, v12
; %bb.4:                                ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB0_12
; %bb.5:                                ; %.lr.ph.preheader
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_cvt_f64_i32_e32 v[12:13], v12
	v_cvt_f64_i32_e32 v[14:15], v11
	s_mov_b32 s0, 0
	s_mov_b32 s14, 0
                                        ; implicit-def: $sgpr11
                                        ; implicit-def: $sgpr13
                                        ; implicit-def: $sgpr12
	v_fma_f64 v[11:12], v[7:8], v[12:13], v[3:4]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[13:14], -v[7:8], v[14:15], v[5:6]
	v_dual_mov_b32 v16, v12 :: v_dual_mov_b32 v15, v11
	s_delay_alu instid0(VALU_DEP_2)
	v_dual_mov_b32 v18, v14 :: v_dual_mov_b32 v17, v13
.LBB0_6:                                ; %.lr.ph
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_mul_f64 v[19:20], v[15:16], v[15:16]
	s_or_b32 s12, s12, exec_lo
	s_or_b32 s13, s13, exec_lo
	s_mov_b32 s16, exec_lo
                                        ; implicit-def: $sgpr15
                                        ; implicit-def: $sgpr17
	v_fma_f64 v[21:22], v[17:18], v[17:18], v[19:20]
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_nlt_f64_e32 4.0, v[21:22]
	s_cbranch_execz .LBB0_8
; %bb.7:                                ;   in Loop: Header=BB0_6 Depth=2
	v_mul_f64 v[21:22], v[17:18], v[17:18]
	v_mul_f64 v[15:16], v[17:18], v[15:16]
	v_add_f64 v[19:20], v[11:12], v[19:20]
	s_add_i32 s15, s14, 1
	s_movk_i32 s17, 0xff
	s_cmp_eq_u32 s3, s15
	s_cselect_b32 s18, -1, 0
	s_and_not1_b32 s13, s13, exec_lo
	s_and_b32 s18, s18, exec_lo
	s_and_not1_b32 s12, s12, exec_lo
	s_or_b32 s13, s13, s18
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[17:18], v[15:16], 2.0, v[13:14]
	v_add_f64 v[15:16], v[19:20], -v[21:22]
.LBB0_8:                                ; %Flow80
                                        ;   in Loop: Header=BB0_6 Depth=2
	s_or_b32 exec_lo, exec_lo, s16
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
	s_and_b32 s16, exec_lo, s13
	v_dual_mov_b32 v19, s17 :: v_dual_mov_b32 v20, s14
	s_or_b32 s0, s16, s0
	s_and_not1_b32 s11, s11, exec_lo
	s_and_b32 s14, s12, exec_lo
	s_or_b32 s11, s11, s14
	s_mov_b32 s14, s15
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB0_6
; %bb.9:                                ; %loop.exit.guard
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	s_and_saveexec_b32 s0, s11
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s0, exec_lo, s0
	s_cbranch_execz .LBB0_11
; %bb.10:                               ;   in Loop: Header=BB0_2 Depth=1
	v_cvt_f64_i32_e32 v[11:12], v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[11:12], 0x407fe000, v[11:12]
	v_div_scale_f64 v[13:14], null, v[9:10], v[9:10], v[11:12]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[15:16], v[13:14]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[17:18], -v[13:14], v[15:16], 1.0
	v_fma_f64 v[15:16], v[15:16], v[17:18], v[15:16]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[17:18], -v[13:14], v[15:16], 1.0
	v_fma_f64 v[15:16], v[15:16], v[17:18], v[15:16]
	v_div_scale_f64 v[17:18], vcc_lo, v[11:12], v[9:10], v[11:12]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[19:20], v[17:18], v[15:16]
	v_fma_f64 v[13:14], -v[13:14], v[19:20], v[17:18]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f64 v[13:14], v[13:14], v[15:16], v[19:20]
	v_div_fixup_f64 v[11:12], v[13:14], v[9:10], v[11:12]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_cmp_nlt_f64_e32 vcc_lo, 0x406fe000, v[11:12]
	v_cndmask_b32_e32 v12, 0x406fe000, v12, vcc_lo
	v_cndmask_b32_e32 v11, 0, v11, vcc_lo
	v_cvt_i32_f64_e32 v11, v[11:12]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b32_e32 v13, 8, v11
	v_lshlrev_b32_e32 v12, 24, v11
	v_lshl_or_b32 v11, v11, 16, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_or3_b32 v19, v11, v13, 0xff
.LBB0_11:                               ; %Flow
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	s_branch .LBB0_13
.LBB0_12:                               ;   in Loop: Header=BB0_2 Depth=1
	v_mov_b32_e32 v19, 0xff
.LBB0_13:                               ; %.loopexit
                                        ;   in Loop: Header=BB0_2 Depth=1
	v_lshlrev_b64 v[11:12], 2, v[1:2]
	v_add_nc_u32_e32 v1, s6, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_le_i32_e32 vcc_lo, s8, v1
	v_add_co_u32 v11, s0, s4, v11
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v12, s0, s5, v12, s0
	s_or_b32 s7, vcc_lo, s7
	global_store_b32 v[11:12], v19, off
	s_and_not1_b32 exec_lo, exec_lo, s7
	s_cbranch_execnz .LBB0_2
.LBB0_14:                               ; %Flow83
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z14mandelbrotCalc14RenderSettings
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 312
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 23
		.amdhsa_next_free_sgpr 19
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z14mandelbrotCalc14RenderSettings, .Lfunc_end0-_Z14mandelbrotCalc14RenderSettings
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1260
; NumSgprs: 21
; NumVgprs: 23
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 21
; NumVGPRsForWavesPerEU: 23
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z16mandelbrotCalcSP14RenderSettings ; -- Begin function _Z16mandelbrotCalcSP14RenderSettings
	.globl	_Z16mandelbrotCalcSP14RenderSettings
	.p2align	8
	.type	_Z16mandelbrotCalcSP14RenderSettings,@function
_Z16mandelbrotCalcSP14RenderSettings:   ; @_Z16mandelbrotCalcSP14RenderSettings
; %bb.0:
	s_clause 0x1
	s_load_b32 s4, s[0:1], 0x44
	s_load_b64 s[2:3], s[0:1], 0x8
	s_add_u32 s6, s0, 56
	s_addc_u32 s7, s1, 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s11, s4, 0xffff
	s_mul_i32 s8, s3, s2
	v_mad_u64_u32 v[1:2], null, s15, s11, v[0:1]
	s_mov_b32 s4, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e64 s8, v1
	s_cbranch_execz .LBB1_14
; %bb.1:                                ; %.lr.ph66
	s_clause 0x1
	s_load_b128 s[12:15], s[0:1], 0x10
	s_load_b64 s[4:5], s[0:1], 0x20
	s_load_b32 s6, s[6:7], 0x0
	s_mov_b32 s7, 0
	s_waitcnt lgkmcnt(0)
	v_div_scale_f64 v[2:3], null, s[12:13], s[12:13], 2.0
	v_div_scale_f64 v[8:9], vcc_lo, 2.0, s[12:13], 2.0
	s_mul_i32 s6, s6, s11
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[4:5], v[2:3]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0
	v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0
	v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[6:7], v[8:9], v[4:5]
	v_fma_f64 v[2:3], -v[2:3], v[6:7], v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_div_fmas_f64 v[2:3], v[2:3], v[4:5], v[6:7]
	v_cvt_f64_i32_e32 v[4:5], s2
	v_cvt_f64_i32_e32 v[6:7], s3
	s_load_b32 s3, s[0:1], 0x28
	v_div_fixup_f64 v[2:3], v[2:3], s[12:13], 2.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[4:5], v[2:3], v[4:5]
	v_div_scale_f64 v[8:9], null, v[6:7], v[6:7], v[4:5]
	v_div_scale_f64 v[14:15], vcc_lo, v[4:5], v[6:7], v[4:5]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[10:11], v[8:9]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[12:13], -v[8:9], v[10:11], 1.0
	v_fma_f64 v[10:11], v[10:11], v[12:13], v[10:11]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[12:13], -v[8:9], v[10:11], 1.0
	v_fma_f64 v[10:11], v[10:11], v[12:13], v[10:11]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[12:13], v[14:15], v[10:11]
	v_fma_f64 v[8:9], -v[8:9], v[12:13], v[14:15]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f64 v[8:9], v[8:9], v[10:11], v[12:13]
	v_div_fixup_f64 v[4:5], v[8:9], v[6:7], v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[6:7], s[14:15], -v[4:5]
	v_add_f64 v[4:5], s[14:15], v[4:5]
	v_cvt_f32_f64_e32 v0, v[6:7]
	s_delay_alu instid0(VALU_DEP_2)
	v_cvt_f32_f64_e32 v4, v[4:5]
	v_add_f64 v[5:6], v[2:3], s[4:5]
	s_load_b64 s[4:5], s[0:1], 0x30
	s_waitcnt lgkmcnt(0)
	s_cmp_lg_u32 s3, 0
	v_cvt_f32_i32_e32 v2, s2
	s_cselect_b32 s1, -1, 0
	s_ashr_i32 s9, s2, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s0, s2, s9
	s_xor_b32 s10, s0, s9
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cvt_f32_u32_e32 v3, s10
	s_sub_i32 s0, 0, s10
	v_rcp_iflag_f32_e32 v10, v3
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v10, 0x4f7ffffe, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v10, v10
	v_mul_lo_u32 v13, s0, v10
	v_sub_f32_e32 v7, v4, v0
	v_cvt_f64_u32_e32 v[3:4], s3
	v_cvt_f32_f64_e32 v5, v[5:6]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f32 v8, null, v2, v2, v7
	v_div_scale_f32 v6, vcc_lo, v7, v2, v7
	v_rcp_f32_e32 v9, v8
	s_waitcnt_depctr 0xfff
	v_fma_f32 v11, -v8, v9, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v9, v11, v9
	v_mul_f32_e32 v11, v6, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v12, -v8, v11, v6
	v_fmac_f32_e32 v11, v12, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v6, -v8, v11, v6
	v_mul_hi_u32 v8, v10, v13
	v_div_fmas_f32 v9, v6, v9, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v6, v10, v8
	v_div_fixup_f32 v7, v9, v2, v7
.LBB1_2:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB1_6 Depth 2
	v_ashrrev_i32_e32 v2, 31, v1
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v8, v1, v2
	v_xor_b32_e32 v8, v8, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v9, v8, v6
	v_mul_lo_u32 v10, v9, s10
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v8, v8, v10
	v_add_nc_u32_e32 v10, 1, v9
	v_subrev_nc_u32_e32 v11, s10, v8
	v_cmp_le_u32_e32 vcc_lo, s10, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v9, v9, v10 :: v_dual_cndmask_b32 v8, v8, v11
	v_xor_b32_e32 v11, s9, v2
	v_add_nc_u32_e32 v10, 1, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_le_u32_e32 vcc_lo, s10, v8
	v_cndmask_b32_e32 v8, v9, v10, vcc_lo
	v_mov_b32_e32 v9, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v8, v8, v11
	v_sub_nc_u32_e32 v8, v8, v11
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e32 0, v8
; %bb.3:                                ;   in Loop: Header=BB1_2 Depth=1
	v_mul_lo_u32 v9, v8, s2
	s_delay_alu instid0(VALU_DEP_1)
	v_sub_nc_u32_e32 v9, v1, v9
; %bb.4:                                ;   in Loop: Header=BB1_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB1_12
; %bb.5:                                ; %.lr.ph.preheader
                                        ;   in Loop: Header=BB1_2 Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_cvt_f32_i32_e32 v9, v9
	v_cvt_f32_i32_e32 v10, v8
	s_mov_b32 s0, 0
	s_mov_b32 s14, 0
                                        ; implicit-def: $sgpr11
                                        ; implicit-def: $sgpr13
                                        ; implicit-def: $sgpr12
	v_fma_f32 v8, v7, v9, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v9, -v7, v10, v5
	v_dual_mov_b32 v10, v8 :: v_dual_mov_b32 v11, v9
.LBB1_6:                                ; %.lr.ph
                                        ;   Parent Loop BB1_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v12, v10, v10
	s_or_b32 s12, s12, exec_lo
	s_or_b32 s13, s13, exec_lo
	s_mov_b32 s16, exec_lo
                                        ; implicit-def: $sgpr15
                                        ; implicit-def: $sgpr17
	v_fma_f32 v13, v11, v11, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_nlt_f32_e32 4.0, v13
	s_cbranch_execz .LBB1_8
; %bb.7:                                ;   in Loop: Header=BB1_6 Depth=2
	v_dual_mul_f32 v13, v11, v11 :: v_dual_add_f32 v12, v8, v12
	v_mul_f32_e32 v10, v11, v10
	s_add_i32 s15, s14, 1
	s_movk_i32 s17, 0xff
	s_cmp_eq_u32 s3, s15
	s_cselect_b32 s18, -1, 0
	v_fma_f32 v11, 2.0, v10, v9
	v_sub_f32_e32 v10, v12, v13
	s_and_not1_b32 s13, s13, exec_lo
	s_and_b32 s18, s18, exec_lo
	s_and_not1_b32 s12, s12, exec_lo
	s_or_b32 s13, s13, s18
.LBB1_8:                                ; %Flow80
                                        ;   in Loop: Header=BB1_6 Depth=2
	s_or_b32 exec_lo, exec_lo, s16
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
	s_and_b32 s16, exec_lo, s13
	v_dual_mov_b32 v12, s17 :: v_dual_mov_b32 v13, s14
	s_or_b32 s0, s16, s0
	s_and_not1_b32 s11, s11, exec_lo
	s_and_b32 s14, s12, exec_lo
	s_or_b32 s11, s11, s14
	s_mov_b32 s14, s15
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB1_6
; %bb.9:                                ; %loop.exit.guard
                                        ;   in Loop: Header=BB1_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	s_and_saveexec_b32 s0, s11
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s0, exec_lo, s0
	s_cbranch_execz .LBB1_11
; %bb.10:                               ;   in Loop: Header=BB1_2 Depth=1
	v_cvt_f64_i32_e32 v[8:9], v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[8:9], 0x407fe000, v[8:9]
	v_div_scale_f64 v[10:11], null, v[3:4], v[3:4], v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[12:13], v[10:11]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[14:15], -v[10:11], v[12:13], 1.0
	v_fma_f64 v[12:13], v[12:13], v[14:15], v[12:13]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[14:15], -v[10:11], v[12:13], 1.0
	v_fma_f64 v[12:13], v[12:13], v[14:15], v[12:13]
	v_div_scale_f64 v[14:15], vcc_lo, v[8:9], v[3:4], v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[16:17], v[14:15], v[12:13]
	v_fma_f64 v[10:11], -v[10:11], v[16:17], v[14:15]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f64 v[10:11], v[10:11], v[12:13], v[16:17]
	v_div_fixup_f64 v[8:9], v[10:11], v[3:4], v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_cmp_nlt_f64_e32 vcc_lo, 0x406fe000, v[8:9]
	v_cndmask_b32_e32 v9, 0x406fe000, v9, vcc_lo
	v_cndmask_b32_e32 v8, 0, v8, vcc_lo
	v_cvt_i32_f64_e32 v8, v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b32_e32 v10, 8, v8
	v_lshlrev_b32_e32 v9, 24, v8
	v_lshl_or_b32 v8, v8, 16, v9
	s_delay_alu instid0(VALU_DEP_1)
	v_or3_b32 v12, v8, v10, 0xff
.LBB1_11:                               ; %Flow
                                        ;   in Loop: Header=BB1_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	s_branch .LBB1_13
.LBB1_12:                               ;   in Loop: Header=BB1_2 Depth=1
	v_mov_b32_e32 v12, 0xff
.LBB1_13:                               ; %.loopexit
                                        ;   in Loop: Header=BB1_2 Depth=1
	v_lshlrev_b64 v[8:9], 2, v[1:2]
	v_add_nc_u32_e32 v1, s6, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_le_i32_e32 vcc_lo, s8, v1
	v_add_co_u32 v8, s0, s4, v8
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v9, s0, s5, v9, s0
	s_or_b32 s7, vcc_lo, s7
	global_store_b32 v[8:9], v12, off
	s_and_not1_b32 exec_lo, exec_lo, s7
	s_cbranch_execnz .LBB1_2
.LBB1_14:                               ; %Flow83
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z16mandelbrotCalcSP14RenderSettings
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 312
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 18
		.amdhsa_next_free_sgpr 19
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z16mandelbrotCalcSP14RenderSettings, .Lfunc_end1-_Z16mandelbrotCalcSP14RenderSettings
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1228
; NumSgprs: 21
; NumVgprs: 18
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 21
; NumVGPRsForWavesPerEU: 18
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .offset:         0
        .size:           56
        .value_kind:     by_value
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         60
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         64
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         68
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         70
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         72
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         74
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         76
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         78
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         112
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         120
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 312
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z14mandelbrotCalc14RenderSettings
    .private_segment_fixed_size: 0
    .sgpr_count:     21
    .sgpr_spill_count: 0
    .symbol:         _Z14mandelbrotCalc14RenderSettings.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     23
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .offset:         0
        .size:           56
        .value_kind:     by_value
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         60
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         64
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         68
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         70
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         72
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         74
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         76
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         78
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         112
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         120
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 312
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z16mandelbrotCalcSP14RenderSettings
    .private_segment_fixed_size: 0
    .sgpr_count:     21
    .sgpr_spill_count: 0
    .symbol:         _Z16mandelbrotCalcSP14RenderSettings.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     18
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
