extern "C"
__global__ void setDomainPoolKernel(
  int nBatch, int rbs, int nDegree, int nD, int dScale, int rScale,
  int expansion, int isCenAlign, float regularize,

  float *data,float *dataRev, // array of data and reverse data
  // arrays pointer
  float *DA,
  float *AA,
  float *IA,
  // pointer of array of pointer to pointer of array in arrays, nevermind i just stun you.
  // p(i) = data(i + size(data))
  float **DP,
  float **AP,
  float **IP
)
{
  int taskIdx = blockIdx.x * blockDim.x + threadIdx.x;
  if (taskIdx < nBatch){
    // initialize domain arrays
    // array structure
    // DA = rbs-rows , 1 + D_1^1 + D_2^1 + D_3^1 + ... + D_ds^2
    // nCoeff is power of Domains. start from power 0
    // nDegree determine the number of degree (maximum degree + 1)
    // nD determine the number of domain blocks
    // dScale determing the scale of domain size compare to rbs
    // dpOffset determine the number of bytes padded for each Array

    int nCoeff = ((nDegree - 1) * nD + 1);

    // pointing array of pointers to array
    const int daOffset = taskIdx * rbs * rScale * nCoeff;
    const int aaOffset = taskIdx * nCoeff * nCoeff;
    const int iaOffset = taskIdx * nCoeff * nCoeff;

    DP[taskIdx] = &DA[daOffset];
    AP[taskIdx] = &AA[aaOffset];
    IP[taskIdx] = &IA[iaOffset];

    // initialize covariance matrix with regularization
    for(int i = 0; i < nCoeff * nCoeff; i++){
      AA[aaOffset + i] = 0.0f;
    }
    for(int i = 0; i < nCoeff * nCoeff; i+= nCoeff+1){
      // set diagonal to regularization parameter
      AA[aaOffset + i] = regularize * regularize;
    }

    // initialize first column covariance matrix
    for(int i = 0; i < rbs * rScale; i++){
      DA[daOffset + i] = 1.0f; // power 0
    }

    int dIdx = taskIdx % (nBatch/2);

    // for each block number dn
    for(int dn = 1; dn <= nD; dn++){
      // set reference domain block
      // compute sumScale
      int sumScale = 0;
      for(int k = 1; k <= nD && k < dn; k++){
        sumScale += (int) powf( (float) dScale, (float) (1 + expansion * (k - 1))) ;
      }
      int dnScale = (int) powf( (float) dScale, (float) (1 + expansion * (dn - 1)));

      //int dnIdx = dIdx + rbs * sumScale; // * domian location factor
      int dnIdx = dIdx;
      if( isCenAlign == 0 ){
        // if left aligned
        dnIdx = dIdx + rbs * sumScale + 1;
      } else {
        // if center aligned
        dnIdx = dIdx + rbs/2 * (1 - dnScale) + 1;
      }

      int padDA = rbs * rScale * dn; // number of row of DA

      // initialize column dn-th index
      for(int i = 0; i < rbs * rScale; i++){
        DA[daOffset + padDA + i] = 0.0f; // power 1
      }

      // construct DA from domain blocks at power 1
      // copy elements
      for(int i = 0; i < rbs * rScale; i++){
        int datIdx = dnIdx + i*dnScale/rScale;
        if(datIdx >=0 && datIdx < (nBatch/2)){
          if(taskIdx < (nBatch/2)){
            DA[daOffset + padDA + i] =
            DA[daOffset + padDA + i] + data[datIdx];
          }else{ // gen reverse domain
            DA[daOffset + padDA + i] =
            DA[daOffset + padDA + i] + dataRev[datIdx];
          }
        }
      }

      // // handling if domain blocks are larger than rbs (by downsample)
      for(int ds = 1; ds < dnScale / rScale; ds++){
        // vec sumation
        for(int i = 0; i < rbs * rScale; i++){
          int datIdx = dnIdx + ds + i*dnScale/rScale;
          if(datIdx >=0 && datIdx < (nBatch/2)){
            if(taskIdx < (nBatch/2)){
              DA[daOffset + padDA + i] =
              DA[daOffset  + padDA + i] + data[datIdx];
            }else{ // gen reverse domain
              DA[daOffset + padDA + i] =
              DA[daOffset  + padDA + i] + dataRev[datIdx];
            }
          }
        }
      }

      // vec scalig after resample
      for(int i = 0; i < rbs * rScale; i++){
        DA[daOffset + padDA + i] = DA[daOffset + padDA + i] / (dnScale/rScale);
      }

      // calculate next degree
      for(int deg = 2; deg <= nDegree - 1; deg++){
        int degPad = rbs * nD * (deg - 2) + rbs * dn;
        int nextDegPad = rbs * nD * (deg - 1) + rbs * dn;
        for(int i = 0; i < rbs * rScale; i++){
          // power n>=2
          // D^n = D^1 * D^(n-1)
          DA[daOffset + nextDegPad + i] =
          DA[daOffset + rbs*dn + i] * DA[daOffset + degPad + i] ;
        }
      }
    }
  }
}

	.file	"tmpxft_002be98c_00000000-6_setDomainPoolKernel.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2010:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2010:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z65__device_stub__Z19setDomainPoolKerneliiiiiiiifPfS_S_S_S_PS_S0_S0_iiiiiiiifPfS_S_S_S_PS_S0_S0_
	.type	_Z65__device_stub__Z19setDomainPoolKerneliiiiiiiifPfS_S_S_S_PS_S0_S0_iiiiiiiifPfS_S_S_S_PS_S0_S0_, @function
_Z65__device_stub__Z19setDomainPoolKerneliiiiiiiifPfS_S_S_S_PS_S0_S0_iiiiiiiifPfS_S_S_S_PS_S0_S0_:
.LFB2032:
	.cfi_startproc
	endbr64
	subq	$312, %rsp
	.cfi_def_cfa_offset 320
	movq	336(%rsp), %rax
	movl	%edi, 92(%rsp)
	leaq	112(%rsp), %rdi
	movl	%esi, 88(%rsp)
	leaq	124(%rsp), %rsi
	movq	%rax, 56(%rsp)
	movq	344(%rsp), %rax
	movl	%edx, 84(%rsp)
	leaq	96(%rsp), %rdx
	movq	%rax, 48(%rsp)
	movq	352(%rsp), %rax
	movl	%ecx, 80(%rsp)
	leaq	104(%rsp), %rcx
	movq	%rax, 40(%rsp)
	movq	360(%rsp), %rax
	movl	%r8d, 76(%rsp)
	movq	%rax, 32(%rsp)
	movq	368(%rsp), %rax
	movl	%r9d, 72(%rsp)
	movq	%rax, 24(%rsp)
	movq	376(%rsp), %rax
	movss	%xmm0, 68(%rsp)
	movq	%rax, 16(%rsp)
	movq	384(%rsp), %rax
	movq	%rax, 8(%rsp)
	movq	392(%rsp), %rax
	movq	%rax, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 296(%rsp)
	xorl	%eax, %eax
	leaq	92(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	88(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	84(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	80(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	76(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	72(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	320(%rsp), %rax
	movq	%rax, 208(%rsp)
	leaq	328(%rsp), %rax
	movq	%rax, 216(%rsp)
	leaq	68(%rsp), %rax
	movq	%rax, 224(%rsp)
	leaq	56(%rsp), %rax
	movq	%rax, 232(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 240(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 248(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 256(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 264(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 272(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 280(%rsp)
	movq	%rsp, %rax
	movq	%rax, 288(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 112(%rsp)
	movl	$1, 120(%rsp)
	movq	%rax, 124(%rsp)
	movl	$1, 132(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	104(%rsp)
	.cfi_def_cfa_offset 328
	leaq	setDomainPoolKernel(%rip), %rdi
	pushq	104(%rsp)
	.cfi_def_cfa_offset 336
	movq	140(%rsp), %rcx
	movl	148(%rsp), %r8d
	movq	128(%rsp), %rsi
	movl	136(%rsp), %edx
	leaq	176(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 328
	popq	%rdx
	.cfi_def_cfa_offset 320
.L2:
	movq	296(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$312, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2032:
	.size	_Z65__device_stub__Z19setDomainPoolKerneliiiiiiiifPfS_S_S_S_PS_S0_S0_iiiiiiiifPfS_S_S_S_PS_S0_S0_, .-_Z65__device_stub__Z19setDomainPoolKerneliiiiiiiifPfS_S_S_S_PS_S0_S0_iiiiiiiifPfS_S_S_S_PS_S0_S0_
	.globl	setDomainPoolKernel
	.type	setDomainPoolKernel, @function
setDomainPoolKernel:
.LFB2033:
	.cfi_startproc
	endbr64
	jmp	_Z65__device_stub__Z19setDomainPoolKerneliiiiiiiifPfS_S_S_S_PS_S0_S0_iiiiiiiifPfS_S_S_S_PS_S0_S0_
	.cfi_endproc
.LFE2033:
	.size	setDomainPoolKernel, .-setDomainPoolKernel
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"setDomainPoolKernel"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2035:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	setDomainPoolKernel(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2035:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
extern "C"
__global__ void setDomainPoolKernel(
  int nBatch, int rbs, int nDegree, int nD, int dScale, int rScale,
  int expansion, int isCenAlign, float regularize,

  float *data,float *dataRev, // array of data and reverse data
  // arrays pointer
  float *DA,
  float *AA,
  float *IA,
  // pointer of array of pointer to pointer of array in arrays, nevermind i just stun you.
  // p(i) = data(i + size(data))
  float **DP,
  float **AP,
  float **IP
)
{
  int taskIdx = blockIdx.x * blockDim.x + threadIdx.x;
  if (taskIdx < nBatch){
    // initialize domain arrays
    // array structure
    // DA = rbs-rows , 1 + D_1^1 + D_2^1 + D_3^1 + ... + D_ds^2
    // nCoeff is power of Domains. start from power 0
    // nDegree determine the number of degree (maximum degree + 1)
    // nD determine the number of domain blocks
    // dScale determing the scale of domain size compare to rbs
    // dpOffset determine the number of bytes padded for each Array

    int nCoeff = ((nDegree - 1) * nD + 1);

    // pointing array of pointers to array
    const int daOffset = taskIdx * rbs * rScale * nCoeff;
    const int aaOffset = taskIdx * nCoeff * nCoeff;
    const int iaOffset = taskIdx * nCoeff * nCoeff;

    DP[taskIdx] = &DA[daOffset];
    AP[taskIdx] = &AA[aaOffset];
    IP[taskIdx] = &IA[iaOffset];

    // initialize covariance matrix with regularization
    for(int i = 0; i < nCoeff * nCoeff; i++){
      AA[aaOffset + i] = 0.0f;
    }
    for(int i = 0; i < nCoeff * nCoeff; i+= nCoeff+1){
      // set diagonal to regularization parameter
      AA[aaOffset + i] = regularize * regularize;
    }

    // initialize first column covariance matrix
    for(int i = 0; i < rbs * rScale; i++){
      DA[daOffset + i] = 1.0f; // power 0
    }

    int dIdx = taskIdx % (nBatch/2);

    // for each block number dn
    for(int dn = 1; dn <= nD; dn++){
      // set reference domain block
      // compute sumScale
      int sumScale = 0;
      for(int k = 1; k <= nD && k < dn; k++){
        sumScale += (int) powf( (float) dScale, (float) (1 + expansion * (k - 1))) ;
      }
      int dnScale = (int) powf( (float) dScale, (float) (1 + expansion * (dn - 1)));

      //int dnIdx = dIdx + rbs * sumScale; // * domian location factor
      int dnIdx = dIdx;
      if( isCenAlign == 0 ){
        // if left aligned
        dnIdx = dIdx + rbs * sumScale + 1;
      } else {
        // if center aligned
        dnIdx = dIdx + rbs/2 * (1 - dnScale) + 1;
      }

      int padDA = rbs * rScale * dn; // number of row of DA

      // initialize column dn-th index
      for(int i = 0; i < rbs * rScale; i++){
        DA[daOffset + padDA + i] = 0.0f; // power 1
      }

      // construct DA from domain blocks at power 1
      // copy elements
      for(int i = 0; i < rbs * rScale; i++){
        int datIdx = dnIdx + i*dnScale/rScale;
        if(datIdx >=0 && datIdx < (nBatch/2)){
          if(taskIdx < (nBatch/2)){
            DA[daOffset + padDA + i] =
            DA[daOffset + padDA + i] + data[datIdx];
          }else{ // gen reverse domain
            DA[daOffset + padDA + i] =
            DA[daOffset + padDA + i] + dataRev[datIdx];
          }
        }
      }

      // // handling if domain blocks are larger than rbs (by downsample)
      for(int ds = 1; ds < dnScale / rScale; ds++){
        // vec sumation
        for(int i = 0; i < rbs * rScale; i++){
          int datIdx = dnIdx + ds + i*dnScale/rScale;
          if(datIdx >=0 && datIdx < (nBatch/2)){
            if(taskIdx < (nBatch/2)){
              DA[daOffset + padDA + i] =
              DA[daOffset  + padDA + i] + data[datIdx];
            }else{ // gen reverse domain
              DA[daOffset + padDA + i] =
              DA[daOffset  + padDA + i] + dataRev[datIdx];
            }
          }
        }
      }

      // vec scalig after resample
      for(int i = 0; i < rbs * rScale; i++){
        DA[daOffset + padDA + i] = DA[daOffset + padDA + i] / (dnScale/rScale);
      }

      // calculate next degree
      for(int deg = 2; deg <= nDegree - 1; deg++){
        int degPad = rbs * nD * (deg - 2) + rbs * dn;
        int nextDegPad = rbs * nD * (deg - 1) + rbs * dn;
        for(int i = 0; i < rbs * rScale; i++){
          // power n>=2
          // D^n = D^1 * D^(n-1)
          DA[daOffset + nextDegPad + i] =
          DA[daOffset + rbs*dn + i] * DA[daOffset + degPad + i] ;
        }
      }
    }
  }
}

	.text
	.file	"setDomainPoolKernel.hip"
	.globl	__device_stub__setDomainPoolKernel # -- Begin function __device_stub__setDomainPoolKernel
	.type	__device_stub__setDomainPoolKernel,@function
__device_stub__setDomainPoolKernel:     # @__device_stub__setDomainPoolKernel
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$224, %rsp
	.cfi_def_cfa_offset 272
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	28(%rsp), %rax
	movl	%edi, (%rax)
	leaq	24(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	20(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	16(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	12(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	8(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	4(%rsp), %r9
	movss	%xmm0, (%r9)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	272(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	280(%rsp), %rax
	movq	%rax, 56(%rbx)
	movq	%r9, 64(%rbx)
	leaq	288(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	296(%rsp), %rax
	movq	%rax, 80(%rbx)
	leaq	304(%rsp), %rax
	movq	%rax, 88(%rbx)
	leaq	312(%rsp), %rax
	movq	%rax, 96(%rbx)
	leaq	320(%rsp), %rax
	movq	%rax, 104(%rbx)
	leaq	328(%rsp), %rax
	movq	%rax, 112(%rbx)
	leaq	336(%rsp), %rax
	movq	%rax, 120(%rbx)
	leaq	344(%rsp), %rax
	movq	%rax, 128(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	40(%rsp), %r12
	leaq	32(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$setDomainPoolKernel, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$240, %rsp
	.cfi_adjust_cfa_offset -240
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	__device_stub__setDomainPoolKernel, .Lfunc_end0-__device_stub__setDomainPoolKernel
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$setDomainPoolKernel, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	setDomainPoolKernel,@object     # @setDomainPoolKernel
	.section	.rodata,"a",@progbits
	.globl	setDomainPoolKernel
	.p2align	3, 0x0
setDomainPoolKernel:
	.quad	__device_stub__setDomainPoolKernel
	.size	setDomainPoolKernel, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"setDomainPoolKernel"
	.size	.L__unnamed_1, 20

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __device_stub__setDomainPoolKernel
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym setDomainPoolKernel
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	setDomainPoolKernel     ; -- Begin function setDomainPoolKernel
	.globl	setDomainPoolKernel
	.p2align	8
	.type	setDomainPoolKernel,@function
setDomainPoolKernel:                    ; @setDomainPoolKernel
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x74
	s_load_b256 s[20:27], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[3:4], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_i32_e64 s20, v3
	s_cbranch_execz .LBB0_42
; %bb.1:
	s_add_i32 s28, s22, -1
	s_load_b512 s[4:19], s[0:1], 0x28
	s_mul_i32 s28, s28, s23
	s_mul_i32 s2, s25, s21
	v_add_co_u32 v2, s29, s28, 1
	v_ashrrev_i32_e32 v4, 31, v3
	s_load_b32 s1, s[0:1], 0x20
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_readfirstlane_b32 s3, v2
	v_mul_lo_u32 v1, s2, v2
	v_lshlrev_b64 v[7:8], 3, v[3:4]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s3, s3, s3
	v_mul_lo_u32 v0, s3, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_lo_u32 v9, v1, v3
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v11, vcc_lo, s14, v7
	v_add_co_ci_u32_e32 v12, vcc_lo, s15, v8, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_ashrrev_i32_e32 v1, 31, v0
	v_ashrrev_i32_e32 v10, 31, v9
	v_add_co_u32 v13, vcc_lo, s16, v7
	v_add_co_ci_u32_e32 v14, vcc_lo, s17, v8, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_lshlrev_b64 v[5:6], 2, v[0:1]
	v_lshlrev_b64 v[0:1], 2, v[9:10]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v9, vcc_lo, s10, v5
	v_add_co_ci_u32_e32 v10, vcc_lo, s11, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v15, vcc_lo, s8, v0
	v_add_co_ci_u32_e32 v16, vcc_lo, s9, v1, vcc_lo
	v_add_co_u32 v17, vcc_lo, s12, v5
	v_add_co_ci_u32_e32 v18, vcc_lo, s13, v6, vcc_lo
	v_add_co_u32 v7, vcc_lo, s18, v7
	v_add_co_ci_u32_e32 v8, vcc_lo, s19, v8, vcc_lo
	s_and_b32 vcc_lo, exec_lo, s29
	global_store_b64 v[11:12], v[15:16], off
	global_store_b64 v[13:14], v[9:10], off
	global_store_b64 v[7:8], v[17:18], off
	s_cbranch_vccnz .LBB0_6
; %bb.2:                                ; %.lr.ph.preheader
	v_add_co_u32 v5, vcc_lo, s10, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, s11, v6, vcc_lo
	v_mov_b32_e32 v9, 0
	s_max_u32 s0, s3, 1
	s_delay_alu instid0(VALU_DEP_2)
	v_dual_mov_b32 v8, v6 :: v_dual_mov_b32 v7, v5
.LBB0_3:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	global_store_b32 v[7:8], v9, off
	v_add_co_u32 v7, vcc_lo, v7, 4
	v_add_co_ci_u32_e32 v8, vcc_lo, 0, v8, vcc_lo
	s_add_i32 s0, s0, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s0, 0
	s_cbranch_scc0 .LBB0_3
; %bb.4:                                ; %.preheader238
	s_add_i32 s0, s28, 2
	v_mul_f32_e64 v7, s1, s1
	s_ashr_i32 s1, s0, 31
	s_delay_alu instid0(SALU_CYCLE_1)
	s_lshl_b64 s[10:11], s[0:1], 2
	s_mov_b32 s1, 0
.LBB0_5:                                ; =>This Inner Loop Header: Depth=1
	global_store_b32 v[5:6], v7, off
	v_add_co_u32 v5, vcc_lo, v5, s10
	v_add_co_ci_u32_e32 v6, vcc_lo, s11, v6, vcc_lo
	s_add_i32 s1, s1, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_ge_i32 s1, s3
	s_cbranch_scc0 .LBB0_5
.LBB0_6:                                ; %.preheader237
	s_cmp_gt_i32 s2, 0
	s_cselect_b32 s3, -1, 0
	s_cmp_lt_i32 s2, 1
	s_cbranch_scc1 .LBB0_9
; %bb.7:                                ; %.lr.ph245.preheader
	v_add_co_u32 v0, vcc_lo, s8, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s9, v1, vcc_lo
	v_mov_b32_e32 v5, 1.0
	s_mov_b32 s0, s2
.LBB0_8:                                ; %.lr.ph245
                                        ; =>This Inner Loop Header: Depth=1
	global_store_b32 v[0:1], v5, off
	v_add_co_u32 v0, vcc_lo, v0, 4
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
	s_add_i32 s0, s0, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s0, 0
	s_cbranch_scc0 .LBB0_8
.LBB0_9:                                ; %._crit_edge
	s_cmp_lt_i32 s23, 1
	s_mov_b32 s10, 1
	s_cbranch_scc1 .LBB0_42
; %bb.10:                               ; %.preheader236.lr.ph
	s_lshr_b32 s0, s20, 31
	v_dual_mov_b32 v6, s5 :: v_dual_add_nc_u32 v5, v3, v4
	s_add_i32 s0, s20, s0
	v_mul_lo_u32 v2, v3, v2
	s_ashr_i32 s11, s0, 1
	s_ashr_i32 s0, s0, 31
	v_xor_b32_e32 v5, v5, v4
	s_add_i32 s1, s11, s0
	v_cvt_f32_i32_e32 v15, s24
	s_xor_b32 s0, s1, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	v_cvt_f32_u32_e32 v0, s0
	s_sub_i32 s1, 0, s0
	s_cmp_eq_u32 s24, 1
	v_mul_lo_u32 v7, v2, s25
	s_cselect_b32 s12, -1, 0
	v_rcp_iflag_f32_e32 v0, v0
	s_cmp_lg_u32 s27, 0
	s_cselect_b32 s13, -1, 0
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v0, 0x4f7ffffe, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v0, v0
	v_mul_lo_u32 v1, s1, v0
	s_lshr_b32 s1, s21, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s1, s21, s1
	s_ashr_i32 s14, s1, 1
	s_cmp_gt_i32 s22, 2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_mul_hi_u32 v1, v0, v1
	s_cselect_b32 s15, -1, 0
	s_ashr_i32 s16, s25, 31
	s_add_i32 s1, s25, s16
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_xor_b32 s17, s1, s16
	v_add_nc_u32_e32 v0, v0, v1
	v_cvt_f32_u32_e32 v1, s17
	s_sub_i32 s1, 0, s17
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v0, v5, v0
	v_rcp_iflag_f32_e32 v1, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v0, v0, s0
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v1, 0x4f7ffffe, v1
	v_sub_nc_u32_e32 v0, v5, v0
	v_subrev_nc_u32_e32 v5, s0, v0
	v_cmp_le_u32_e32 vcc_lo, s0, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_cndmask_b32_e32 v0, v0, v5, vcc_lo
	v_cmp_gt_i32_e32 vcc_lo, s11, v3
	v_mov_b32_e32 v5, s4
	v_cvt_u32_f32_e32 v3, v1
	s_mov_b32 s4, s21
	v_subrev_nc_u32_e32 v8, s0, v0
	v_cmp_le_u32_e64 s0, s0, v0
	v_cndmask_b32_e32 v16, s7, v6, vcc_lo
	v_cndmask_b32_e32 v17, s6, v5, vcc_lo
	s_mov_b32 s6, 0x3e76c4e1
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v6, v0, v8, s0
	v_mad_u64_u32 v[0:1], null, s2, v2, s[2:3]
	v_add_nc_u32_e32 v1, s23, v7
	v_readfirstlane_b32 s0, v3
	v_xor_b32_e32 v5, v6, v4
	v_mov_b32_e32 v6, 0
	v_mad_u64_u32 v[2:3], null, s21, v7, s[4:5]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	s_mul_i32 s1, s1, s0
	v_sub_nc_u32_e32 v3, v5, v4
	v_mad_u64_u32 v[4:5], null, s21, v1, s[4:5]
	s_mul_hi_u32 s1, s0, s1
	s_mul_i32 s4, s23, s21
	s_delay_alu instid0(VALU_DEP_2)
	v_add_nc_u32_e32 v18, 1, v3
	s_add_i32 s5, s0, s1
.LBB0_11:                               ; %.preheader236
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_13 Depth 2
                                        ;     Child Loop BB0_20 Depth 2
                                        ;     Child Loop BB0_22 Depth 2
                                        ;     Child Loop BB0_27 Depth 2
                                        ;       Child Loop BB0_29 Depth 3
                                        ;     Child Loop BB0_35 Depth 2
                                        ;     Child Loop BB0_38 Depth 2
                                        ;       Child Loop BB0_39 Depth 3
	v_mov_b32_e32 v1, v6
	s_cmp_lt_u32 s10, 2
	s_cbranch_scc1 .LBB0_14
; %bb.12:                               ; %.lr.ph249.preheader
                                        ;   in Loop: Header=BB0_11 Depth=1
	v_mov_b32_e32 v1, 0
	s_mov_b32 s7, 1
	s_mov_b32 s18, 1
.LBB0_13:                               ; %.lr.ph249
                                        ;   Parent Loop BB0_11 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_cvt_f32_i32_e32 v3, s7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v3, v3, 1.0, s12
	v_cmp_neq_f32_e32 vcc_lo, 0, v3
	v_trunc_f32_e32 v7, v3
	v_mul_f32_e32 v8, 0.5, v3
	v_cndmask_b32_e32 v5, 1.0, v15, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_eq_f32_e32 vcc_lo, v7, v3
	v_trunc_f32_e32 v7, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_frexp_mant_f32_e64 v9, |v5|
	v_cmp_neq_f32_e64 s1, v7, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_gt_f32_e64 s0, 0x3f2aaaab, v9
	v_cndmask_b32_e64 v11, 0, 1, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ldexp_f32 v7, v9, v11
	v_add_f32_e32 v9, 1.0, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f32_e32 v12, -1.0, v9
	v_frexp_exp_i32_f32_e32 v10, v5
	v_subrev_co_ci_u32_e64 v8, s0, 0, v10, s0
	s_and_b32 s0, vcc_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cvt_f32_i32_e32 v8, v8
	v_dual_add_f32 v10, -1.0, v7 :: v_dual_sub_f32 v7, v7, v12
	v_mul_f32_e32 v13, 0x3f317218, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v12, 0x3f317218, v8, -v13
	v_fmac_f32_e32 v12, 0xb102e308, v8
	v_rcp_f32_e32 v11, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_f32_e32 v19, v13, v12
	s_waitcnt_depctr 0xfff
	v_dual_sub_f32 v13, v19, v13 :: v_dual_mul_f32 v14, v10, v11
	v_mul_f32_e32 v8, v9, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v9, v14, v9, -v8
	v_fmac_f32_e32 v9, v14, v7
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v7, v12, v13
	v_add_f32_e32 v12, v8, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v8, v12, v8
	v_dual_sub_f32 v13, v10, v12 :: v_dual_sub_f32 v8, v8, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v10, v10, v13
	v_sub_f32_e32 v9, v10, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v8, v8, v9
	v_add_f32_e32 v8, v13, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v8, v11, v8
	v_add_f32_e32 v9, v14, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v11, v9, v9
	v_sub_f32_e32 v10, v9, v14
	v_ldexp_f32 v12, v9, 1
	v_sub_f32_e32 v8, v8, v10
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v10, v9, v9, -v11
	v_add_f32_e32 v13, v8, v8
	v_ldexp_f32 v14, v8, 1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v10, v9, v13
	v_add_f32_e32 v13, v11, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmaak_f32 v20, s6, v13, 0x3e91f4c4 :: v_dual_sub_f32 v11, v13, v11
	v_dual_mul_f32 v21, v9, v13 :: v_dual_sub_f32 v10, v10, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v11, v13, v9, -v21
	v_fmac_f32_e32 v11, v13, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmaak_f32 v20, v13, v20, 0x3ecccdef :: v_dual_fmac_f32 v11, v10, v9
	v_mul_f32_e32 v22, v13, v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v9, v21, v11
	v_fma_f32 v8, v13, v20, -v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v13, v9, v21 :: v_dual_fmac_f32 v8, v10, v20
	v_dual_sub_f32 v11, v11, v13 :: v_dual_add_f32 v10, v22, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v21, 0x3f2aaaaa, v10
	v_dual_sub_f32 v20, v10, v22 :: v_dual_add_f32 v13, 0xbf2aaaaa, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v8, v8, v20
	v_sub_f32_e32 v10, v10, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v8, 0x31739010, v8
	v_add_f32_e32 v8, v8, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v10, v21, v8
	v_sub_f32_e32 v13, v21, v10
	v_mul_f32_e32 v20, v9, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v8, v8, v13
	v_fma_f32 v13, v9, v10, -v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v13, v9, v8
	v_fmac_f32_e32 v13, v11, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v8, v20, v13
	v_add_f32_e32 v9, v12, v8
	v_sub_f32_e32 v10, v8, v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v11, v9, v12
	v_sub_f32_e32 v10, v13, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v8, v8, v11
	v_add_f32_e32 v10, v14, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v8, v10, v8
	v_add_f32_e32 v10, v9, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v11, v19, v10
	v_dual_sub_f32 v9, v10, v9 :: v_dual_sub_f32 v12, v11, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v8, v8, v9 :: v_dual_sub_f32 v9, v11, v12
	v_add_f32_e32 v13, v7, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v10, v10, v12 :: v_dual_sub_f32 v9, v19, v9
	v_dual_sub_f32 v12, v13, v7 :: v_dual_add_f32 v9, v10, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v10, v13, v12
	v_dual_sub_f32 v8, v8, v12 :: v_dual_add_f32 v9, v13, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v7, v7, v10
	v_dual_add_f32 v10, v11, v9 :: v_dual_add_f32 v7, v8, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v8, v10, v11
	v_sub_f32_e32 v8, v9, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v7, v7, v8
	v_add_f32_e32 v8, v10, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v9, v8, v10 :: v_dual_mul_f32 v10, v3, v8
	v_sub_f32_e32 v7, v7, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v8, v3, v8, -v10
	v_cmp_class_f32_e64 s1, v10, 0x204
	v_fmac_f32_e32 v8, v3, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v7, v10, v8
	v_cndmask_b32_e64 v9, v7, v10, s1
	v_sub_f32_e32 v7, v7, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_eq_f32_e64 s1, 0x42b17218, v9
	v_sub_f32_e32 v7, v8, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v10, 0, 0x37000000, s1
	v_cmp_neq_f32_e64 s1, 0x7f800000, |v9|
	v_sub_f32_e32 v11, v9, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v7, 0, v7, s1
	v_mul_f32_e32 v12, 0x3fb8aa3b, v11
	v_cmp_ngt_f32_e64 s1, 0xc2ce8ed0, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v7, v10, v7
	v_fma_f32 v13, 0x3fb8aa3b, v11, -v12
	v_rndne_f32_e32 v14, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_fmac_f32 v13, 0x32a5705f, v11 :: v_dual_sub_f32 v12, v12, v14
	v_cvt_i32_f32_e32 v9, v14
	v_add_f32_e32 v8, v12, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_exp_f32_e32 v8, v8
	s_waitcnt_depctr 0xfff
	v_ldexp_f32 v8, v8, v9
	v_cndmask_b32_e64 v9, 1.0, v5, s0
	v_cndmask_b32_e64 v8, 0, v8, s1
	v_cmp_nlt_f32_e64 s1, 0x42b17218, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v8, 0x7f800000, v8, s1
	v_fma_f32 v7, v8, v7, v8
	v_cmp_eq_f32_e64 s1, 0x7f800000, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v7, v7, v8, s1
	v_cmp_gt_f32_e64 s1, 0, v3
	v_bfi_b32 v7, 0x7fffffff, v7, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v3, 0x7fc00000, v7, vcc_lo
	v_cmp_gt_f32_e32 vcc_lo, 0, v5
	v_cndmask_b32_e32 v3, v7, v3, vcc_lo
	v_cmp_eq_f32_e32 vcc_lo, 0, v5
	v_cndmask_b32_e64 v5, 0, v5, s0
	s_xor_b32 s0, s1, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	v_cndmask_b32_e64 v7, 0x7f800000, 0, s0
	s_add_i32 s0, s18, 1
	s_cmp_ge_i32 s18, s23
	s_mov_b32 s18, s0
	s_cselect_b32 s1, -1, 0
	v_bfi_b32 v5, 0x7fffffff, v7, v5
	s_cmp_ge_u32 s0, s10
	s_cselect_b32 s0, -1, 0
	s_add_i32 s7, s7, s26
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cndmask_b32_e32 v3, v3, v5, vcc_lo
	s_or_b32 s0, s1, s0
	s_and_b32 vcc_lo, exec_lo, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_i32_f32_e32 v3, v3
	v_add_nc_u32_e32 v1, v1, v3
	s_cbranch_vccz .LBB0_13
.LBB0_14:                               ; %._crit_edge250
                                        ;   in Loop: Header=BB0_11 Depth=1
	s_add_i32 s0, s10, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s0, s0, s26
	s_add_i32 s0, s0, 1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f32_i32_e32 v3, s0
	v_cndmask_b32_e64 v3, v3, 1.0, s12
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_neq_f32_e32 vcc_lo, 0, v3
	v_cndmask_b32_e32 v5, 1.0, v15, vcc_lo
	v_frexp_mant_f32_e64 v7, |v5|
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_gt_f32_e32 vcc_lo, 0x3f2aaaab, v7
	v_cndmask_b32_e64 v8, 0, 1, vcc_lo
	v_ldexp_f32 v7, v7, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f32_e32 v10, -1.0, v7
	v_add_f32_e32 v8, 1.0, v7
	v_rcp_f32_e32 v9, v8
	s_waitcnt_depctr 0xfff
	v_dual_mul_f32 v11, v10, v9 :: v_dual_add_f32 v12, -1.0, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v7, v7, v12
	v_mul_f32_e32 v13, v8, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v8, v11, v8, -v13
	v_fmac_f32_e32 v8, v11, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v7, v13, v8
	v_sub_f32_e32 v12, v10, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v10, v10, v12 :: v_dual_sub_f32 v13, v7, v13
	v_dual_sub_f32 v7, v10, v7 :: v_dual_sub_f32 v8, v13, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v7, v8, v7
	v_add_f32_e32 v7, v12, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v7, v9, v7
	v_add_f32_e32 v8, v11, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v9, v8, v11
	v_dual_mul_f32 v10, v8, v8 :: v_dual_sub_f32 v7, v7, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v9, v8, v8, -v10
	v_add_f32_e32 v11, v7, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v9, v8, v11
	v_add_f32_e32 v11, v10, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmaak_f32 v12, s6, v11, 0x3e91f4c4
	v_sub_f32_e32 v10, v11, v10
	v_dual_fmaak_f32 v12, v11, v12, 0x3ecccdef :: v_dual_sub_f32 v9, v9, v10
	v_mul_f32_e32 v19, v8, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v13, v11, v12
	v_fma_f32 v20, v11, v8, -v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v10, v11, v12, -v13
	v_fmac_f32_e32 v10, v9, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v20, v11, v7
	v_ldexp_f32 v7, v7, 1
	v_add_f32_e32 v12, v13, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v20, v9, v8
	v_ldexp_f32 v8, v8, 1
	v_dual_sub_f32 v13, v12, v13 :: v_dual_add_f32 v14, 0x3f2aaaaa, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v10, v10, v13 :: v_dual_add_f32 v13, 0xbf2aaaaa, v14
	v_add_f32_e32 v10, 0x31739010, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v12, v12, v13
	v_add_f32_e32 v10, v10, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v9, v14, v10
	v_dual_add_f32 v11, v19, v20 :: v_dual_sub_f32 v12, v14, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v13, v11, v9
	v_sub_f32_e32 v14, v11, v19
	v_add_f32_e32 v10, v10, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v12, v11, v9, -v13
	v_sub_f32_e32 v14, v20, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v12, v11, v10
	v_frexp_exp_i32_f32_e32 v10, v5
	v_fmac_f32_e32 v12, v14, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_subrev_co_ci_u32_e32 v9, vcc_lo, 0, v10, vcc_lo
	v_add_f32_e32 v10, v13, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_f32_i32_e32 v9, v9
	v_add_f32_e32 v11, v8, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v13, v10, v13 :: v_dual_sub_f32 v8, v11, v8
	v_sub_f32_e32 v12, v12, v13
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v14, 0x3f317218, v9
	v_sub_f32_e32 v8, v10, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v7, v7, v12
	v_fma_f32 v13, 0x3f317218, v9, -v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v7, v7, v8
	v_fmac_f32_e32 v13, 0xb102e308, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v9, v11, v7 :: v_dual_add_f32 v8, v14, v13
	v_sub_f32_e32 v11, v9, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v7, v7, v11 :: v_dual_add_f32 v10, v8, v9
	v_sub_f32_e32 v12, v10, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v9, v9, v12 :: v_dual_sub_f32 v14, v8, v14
	v_sub_f32_e32 v13, v13, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f32_e32 v11, v13, v7
	v_sub_f32_e32 v19, v10, v12
	v_sub_f32_e32 v8, v8, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v8, v9, v8 :: v_dual_sub_f32 v9, v11, v13
	v_sub_f32_e32 v7, v7, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f32_e32 v8, v11, v8
	v_sub_f32_e32 v11, v11, v9
	v_dual_sub_f32 v9, v13, v11 :: v_dual_add_f32 v12, v10, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v7, v7, v9 :: v_dual_sub_f32 v10, v12, v10
	v_sub_f32_e32 v8, v8, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v7, v7, v8
	v_add_f32_e32 v8, v12, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v9, v8, v12
	v_mul_f32_e32 v10, v3, v8
	v_sub_f32_e32 v7, v7, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v8, v3, v8, -v10
	v_cmp_class_f32_e64 vcc_lo, v10, 0x204
	v_fmac_f32_e32 v8, v3, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v7, v10, v8
	v_cndmask_b32_e32 v9, v7, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_cmp_eq_f32_e32 vcc_lo, 0x42b17218, v9
	v_cndmask_b32_e64 v11, 0, 0x37000000, vcc_lo
	v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v9|
	v_sub_f32_e32 v12, v9, v11
	v_trunc_f32_e32 v9, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v13, 0x3fb8aa3b, v12
	v_fma_f32 v14, 0x3fb8aa3b, v12, -v13
	v_rndne_f32_e32 v19, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v13, v13, v19 :: v_dual_fmac_f32 v14, 0x32a5705f, v12
	v_sub_f32_e32 v7, v7, v10
	v_cvt_i32_f32_e32 v10, v19
	v_sub_f32_e32 v7, v8, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v7, 0, v7, vcc_lo
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v12
	v_add_f32_e32 v13, v13, v14
	v_add_f32_e32 v7, v11, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_exp_f32_e32 v13, v13
	s_waitcnt_depctr 0xfff
	v_ldexp_f32 v8, v13, v10
	v_mul_f32_e32 v10, 0.5, v3
	v_cndmask_b32_e32 v8, 0, v8, vcc_lo
	v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_trunc_f32_e32 v13, v10
	v_cndmask_b32_e32 v8, 0x7f800000, v8, vcc_lo
	v_cmp_eq_f32_e32 vcc_lo, v9, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_neq_f32_e64 s0, v13, v10
	v_fma_f32 v7, v8, v7, v8
	v_cmp_eq_f32_e64 s1, 0x7f800000, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, vcc_lo, s0
	v_cndmask_b32_e64 v9, 1.0, v5, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v7, v7, v8, s1
	v_cmp_gt_f32_e64 s1, 0, v5
	v_bfi_b32 v7, 0x7fffffff, v7, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v8, 0x7fc00000, v7, vcc_lo
	v_cmp_gt_f32_e32 vcc_lo, 0, v3
	v_cndmask_b32_e64 v3, v7, v8, s1
	v_cmp_eq_f32_e64 s1, 0, v5
	v_cndmask_b32_e64 v5, 0, v5, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	s_xor_b32 s0, vcc_lo, s1
	s_and_b32 vcc_lo, exec_lo, s13
	v_cndmask_b32_e64 v7, 0x7f800000, 0, s0
	v_bfi_b32 v5, 0x7fffffff, v7, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v3, v3, v5, s1
	v_cvt_i32_f32_e32 v3, v3
	s_delay_alu instid0(VALU_DEP_1)
	v_readfirstlane_b32 s1, v3
	s_cbranch_vccz .LBB0_16
; %bb.15:                               ;   in Loop: Header=BB0_11 Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_sub_i32 s0, 1, s1
	s_mul_i32 s7, s0, s14
	s_mov_b32 s0, 0
	s_branch .LBB0_17
.LBB0_16:                               ;   in Loop: Header=BB0_11 Depth=1
	s_mov_b32 s0, -1
                                        ; implicit-def: $sgpr7
.LBB0_17:                               ; %Flow399
                                        ;   in Loop: Header=BB0_11 Depth=1
	v_mov_b32_e32 v3, s7
	s_and_not1_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccnz .LBB0_19
; %bb.18:                               ;   in Loop: Header=BB0_11 Depth=1
	v_mul_lo_u32 v3, v1, s21
.LBB0_19:                               ;   in Loop: Header=BB0_11 Depth=1
	v_ashrrev_i32_e32 v1, 31, v0
	s_mov_b32 s0, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[7:8], 2, v[0:1]
	v_add_co_u32 v7, vcc_lo, s8, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v8, vcc_lo, s9, v8, vcc_lo
	v_add_nc_u32_e32 v1, v18, v3
	s_and_not1_b32 vcc_lo, exec_lo, s3
	v_dual_mov_b32 v10, v8 :: v_dual_mov_b32 v9, v7
	s_cbranch_vccnz .LBB0_25
.LBB0_20:                               ;   Parent Loop BB0_11 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	global_store_b32 v[9:10], v6, off
	v_add_co_u32 v9, vcc_lo, v9, 4
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v10, vcc_lo
	s_add_i32 s0, s0, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s0, 0
	s_cbranch_scc0 .LBB0_20
; %bb.21:                               ; %.preheader235
                                        ;   in Loop: Header=BB0_11 Depth=1
	s_mov_b32 s7, 0
	s_mov_b32 s18, 0
.LBB0_22:                               ;   Parent Loop BB0_11 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_ashr_i32 s0, s7, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s19, s7, s0
	s_xor_b32 s19, s19, s0
	s_xor_b32 s0, s0, s16
	s_mul_hi_u32 s20, s19, s5
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s24, s20, s17
	s_sub_i32 s19, s19, s24
	s_add_i32 s24, s20, 1
	s_sub_i32 s25, s19, s17
	s_cmp_ge_u32 s19, s17
	s_cselect_b32 s20, s24, s20
	s_cselect_b32 s19, s25, s19
	s_add_i32 s24, s20, 1
	s_cmp_ge_u32 s19, s17
	s_cselect_b32 s19, s24, s20
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b32 s19, s19, s0
	s_sub_i32 s0, s19, s0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v5, s0, v1
	v_cmp_lt_i32_e32 vcc_lo, -1, v5
	v_cmp_gt_i32_e64 s0, s11, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s19, vcc_lo, s0
	s_and_saveexec_b32 s0, s19
	s_cbranch_execz .LBB0_24
; %bb.23:                               ; %.sink.split
                                        ;   in Loop: Header=BB0_22 Depth=2
	v_add_nc_u32_e32 v9, s18, v0
	v_lshlrev_b64 v[11:12], 2, v[5:6]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v10, 31, v9
	v_lshlrev_b64 v[9:10], 2, v[9:10]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v9, vcc_lo, s8, v9
	v_add_co_ci_u32_e32 v10, vcc_lo, s9, v10, vcc_lo
	v_add_co_u32 v11, vcc_lo, v17, v11
	v_add_co_ci_u32_e32 v12, vcc_lo, v16, v12, vcc_lo
	global_load_b32 v3, v[9:10], off
	global_load_b32 v5, v[11:12], off
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v3, v3, v5
	global_store_b32 v[9:10], v3, off
.LBB0_24:                               ;   in Loop: Header=BB0_22 Depth=2
	s_or_b32 exec_lo, exec_lo, s0
	s_add_i32 s18, s18, 1
	s_add_i32 s7, s7, s1
	s_cmp_eq_u32 s2, s18
	s_cbranch_scc0 .LBB0_22
.LBB0_25:                               ; %.preheader234
                                        ;   in Loop: Header=BB0_11 Depth=1
	s_ashr_i32 s0, s1, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s7, s1, s0
	s_xor_b32 s7, s7, s0
	s_xor_b32 s0, s0, s16
	s_mul_hi_u32 s18, s7, s5
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s19, s18, s17
	s_sub_i32 s7, s7, s19
	s_add_i32 s19, s18, 1
	s_sub_i32 s20, s7, s17
	s_cmp_ge_u32 s7, s17
	s_cselect_b32 s18, s19, s18
	s_cselect_b32 s7, s20, s7
	s_add_i32 s19, s18, 1
	s_cmp_ge_u32 s7, s17
	s_cselect_b32 s7, s19, s18
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b32 s7, s7, s0
	s_sub_i32 s7, s7, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lt_i32 s7, 2
	s_cbranch_scc1 .LBB0_33
; %bb.26:                               ; %.preheader.lr.ph
                                        ;   in Loop: Header=BB0_11 Depth=1
	s_mov_b32 s18, 1
.LBB0_27:                               ; %.preheader
                                        ;   Parent Loop BB0_11 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB0_29 Depth 3
	s_and_not1_b32 vcc_lo, exec_lo, s3
	s_cbranch_vccnz .LBB0_32
; %bb.28:                               ; %.lr.ph258
                                        ;   in Loop: Header=BB0_27 Depth=2
	v_add_nc_u32_e32 v3, s18, v1
	s_mov_b32 s19, 0
	s_mov_b32 s20, 0
.LBB0_29:                               ;   Parent Loop BB0_11 Depth=1
                                        ;     Parent Loop BB0_27 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_ashr_i32 s0, s19, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s24, s19, s0
	s_xor_b32 s24, s24, s0
	s_xor_b32 s0, s0, s16
	s_mul_hi_u32 s25, s24, s5
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s27, s25, s17
	s_sub_i32 s24, s24, s27
	s_add_i32 s27, s25, 1
	s_sub_i32 s28, s24, s17
	s_cmp_ge_u32 s24, s17
	s_cselect_b32 s25, s27, s25
	s_cselect_b32 s24, s28, s24
	s_add_i32 s27, s25, 1
	s_cmp_ge_u32 s24, s17
	s_cselect_b32 s24, s27, s25
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b32 s24, s24, s0
	s_sub_i32 s0, s24, s0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v5, s0, v3
	v_cmp_lt_i32_e32 vcc_lo, -1, v5
	v_cmp_gt_i32_e64 s0, s11, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s24, vcc_lo, s0
	s_and_saveexec_b32 s0, s24
	s_cbranch_execz .LBB0_31
; %bb.30:                               ; %.sink.split287
                                        ;   in Loop: Header=BB0_29 Depth=3
	v_add_nc_u32_e32 v9, s20, v0
	v_lshlrev_b64 v[11:12], 2, v[5:6]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v10, 31, v9
	v_lshlrev_b64 v[9:10], 2, v[9:10]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v9, vcc_lo, s8, v9
	v_add_co_ci_u32_e32 v10, vcc_lo, s9, v10, vcc_lo
	v_add_co_u32 v11, vcc_lo, v17, v11
	v_add_co_ci_u32_e32 v12, vcc_lo, v16, v12, vcc_lo
	global_load_b32 v5, v[9:10], off
	global_load_b32 v11, v[11:12], off
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v5, v5, v11
	global_store_b32 v[9:10], v5, off
.LBB0_31:                               ;   in Loop: Header=BB0_29 Depth=3
	s_or_b32 exec_lo, exec_lo, s0
	s_add_i32 s20, s20, 1
	s_add_i32 s19, s19, s1
	s_cmp_eq_u32 s2, s20
	s_cbranch_scc0 .LBB0_29
.LBB0_32:                               ; %._crit_edge259
                                        ;   in Loop: Header=BB0_27 Depth=2
	s_add_i32 s18, s18, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s18, s7
	s_cbranch_scc0 .LBB0_27
.LBB0_33:                               ; %.preheader233
                                        ;   in Loop: Header=BB0_11 Depth=1
	s_and_not1_b32 vcc_lo, exec_lo, s3
	s_cbranch_vccnz .LBB0_36
; %bb.34:                               ; %.lr.ph263
                                        ;   in Loop: Header=BB0_11 Depth=1
	v_cvt_f32_i32_e32 v1, s7
	s_mov_b32 s0, s2
.LBB0_35:                               ;   Parent Loop BB0_11 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	global_load_b32 v3, v[7:8], off
	s_add_i32 s0, s0, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	s_cmp_eq_u32 s0, 0
	s_waitcnt vmcnt(0)
	v_div_scale_f32 v5, null, v1, v1, v3
	v_div_scale_f32 v11, vcc_lo, v3, v1, v3
	v_rcp_f32_e32 v9, v5
	s_waitcnt_depctr 0xfff
	v_fma_f32 v10, -v5, v9, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v9, v10, v9
	v_mul_f32_e32 v10, v11, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v12, -v5, v10, v11
	v_fmac_f32_e32 v10, v12, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v5, -v5, v10, v11
	v_div_fmas_f32 v5, v5, v9, v10
	s_delay_alu instid0(VALU_DEP_1)
	v_div_fixup_f32 v3, v5, v1, v3
	global_store_b32 v[7:8], v3, off
	v_add_co_u32 v7, vcc_lo, v7, 4
	v_add_co_ci_u32_e32 v8, vcc_lo, 0, v8, vcc_lo
	s_cbranch_scc0 .LBB0_35
.LBB0_36:                               ; %.preheader232
                                        ;   in Loop: Header=BB0_11 Depth=1
	s_and_not1_b32 vcc_lo, exec_lo, s15
	s_cbranch_vccnz .LBB0_41
; %bb.37:                               ; %.lr.ph270
                                        ;   in Loop: Header=BB0_11 Depth=1
	v_ashrrev_i32_e32 v3, 31, v2
	v_mov_b32_e32 v1, v2
	s_mov_b32 s0, 2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[7:8], 2, v[2:3]
	v_mov_b32_e32 v3, v4
	v_add_co_u32 v7, vcc_lo, s8, v7
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v8, vcc_lo, s9, v8, vcc_lo
.LBB0_38:                               ;   Parent Loop BB0_11 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB0_39 Depth 3
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_mov_b32 v10, v8 :: v_dual_mov_b32 v9, v7
	v_mov_b32_e32 v11, v1
	v_mov_b32_e32 v13, v3
	s_and_not1_b32 vcc_lo, exec_lo, s3
	s_mov_b32 s1, s2
	s_cbranch_vccnz .LBB0_40
.LBB0_39:                               ;   Parent Loop BB0_11 Depth=1
                                        ;     Parent Loop BB0_38 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	v_ashrrev_i32_e32 v12, 31, v11
	v_ashrrev_i32_e32 v14, 31, v13
	s_add_i32 s1, s1, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	s_cmp_eq_u32 s1, 0
	v_lshlrev_b64 v[19:20], 2, v[11:12]
	v_add_nc_u32_e32 v11, 1, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v19, vcc_lo, s8, v19
	v_add_co_ci_u32_e32 v20, vcc_lo, s9, v20, vcc_lo
	global_load_b32 v5, v[9:10], off
	global_load_b32 v12, v[19:20], off
	v_lshlrev_b64 v[19:20], 2, v[13:14]
	v_add_co_u32 v9, vcc_lo, v9, 4
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v10, vcc_lo
	v_add_nc_u32_e32 v13, 1, v13
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_u32 v19, vcc_lo, s8, v19
	v_add_co_ci_u32_e32 v20, vcc_lo, s9, v20, vcc_lo
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v5, v5, v12
	global_store_b32 v[19:20], v5, off
	s_cbranch_scc0 .LBB0_39
.LBB0_40:                               ; %._crit_edge267
                                        ;   in Loop: Header=BB0_38 Depth=2
	v_add_nc_u32_e32 v3, s4, v3
	v_add_nc_u32_e32 v1, s4, v1
	s_add_i32 s0, s0, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s0, s22
	s_cbranch_scc0 .LBB0_38
.LBB0_41:                               ; %._crit_edge271
                                        ;   in Loop: Header=BB0_11 Depth=1
	v_add_nc_u32_e32 v0, s2, v0
	v_add_nc_u32_e32 v4, s21, v4
	v_add_nc_u32_e32 v2, s21, v2
	s_add_i32 s0, s10, 1
	s_cmp_eq_u32 s10, s23
	s_mov_b32 s10, s0
	s_cbranch_scc0 .LBB0_11
.LBB0_42:                               ; %.loopexit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel setDomainPoolKernel
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 360
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 23
		.amdhsa_next_free_sgpr 30
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	setDomainPoolKernel, .Lfunc_end0-setDomainPoolKernel
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 4280
; NumSgprs: 32
; NumVgprs: 23
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 32
; NumVGPRsForWavesPerEU: 23
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     by_value
      - .offset:         4
        .size:           4
        .value_kind:     by_value
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .offset:         12
        .size:           4
        .value_kind:     by_value
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
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        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
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        .value_kind:     global_buffer
      - .address_space:  global
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        .value_kind:     global_buffer
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        .value_kind:     global_buffer
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        .value_kind:     global_buffer
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        .value_kind:     global_buffer
      - .address_space:  global
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        .size:           8
        .value_kind:     global_buffer
      - .offset:         104
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         108
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         112
        .size:           4
        .value_kind:     hidden_block_count_z
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        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         118
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        .value_kind:     hidden_group_size_y
      - .offset:         120
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         122
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         124
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        .value_kind:     hidden_remainder_y
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        .size:           2
        .value_kind:     hidden_remainder_z
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        .value_kind:     hidden_global_offset_z
      - .offset:         168
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 360
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           setDomainPoolKernel
    .private_segment_fixed_size: 0
    .sgpr_count:     32
    .sgpr_spill_count: 0
    .symbol:         setDomainPoolKernel.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     23
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
