#include <complex>
#include <iostream>
#include <sys/time.h>
#include <thrust/complex.h>

using namespace std;

__global__ void make_fractal(char *mat, int max_n, int max_row, int max_column){

   int r = threadIdx.x;

   using namespace std;


		for(int c = 0; c < max_column; ++c){
			thrust::complex<float> z;
			int n = 0;

         while(z.real() < 2 && ++n < max_n)
				z = pow(z, 2) + decltype(z)(
					(float)c * 2 / max_column - 1.5,
					(float)r * 2 / max_row - 1
				);
			mat[r*max_column + c]=(n == max_n ? '#' : '.');
		}


}

int main(int argc, char *argv[]){
	int max_row, max_column, max_n, print;

	if (argc != 5){
      std::cout << "Faltam argumentos, devem ser no formato: ./executavel max_row max_column max_n" << std::endl;
      exit(-1);
	}
	max_row = atoi(argv[1]);
	max_column = atoi(argv[2]);
	max_n = atoi(argv[3]);
	print = atoi(argv[4]);
	char *mat;
	cudaMallocManaged(&mat, max_row*max_column*sizeof(unsigned char));





   timeval start, end;
   gettimeofday(&start, NULL);

   make_fractal<<<1, max_row>>>(mat, max_n, max_row, max_column);

   cudaDeviceSynchronize();


	gettimeofday(&end, NULL);
   double runtime = end.tv_sec + end.tv_usec / 1000000.0 - start.tv_sec - start.tv_usec / 1000000.0;
   std::cout << "compute time: " << runtime << " s\n";

   if(print){
      for(int r = 0; r < max_row; ++r){
         for(int c = 0; c < max_column; ++c)
            std::cout << mat[r*max_column + c];
         cout << '\n';
      }
   }
}

	.file	"tmpxft_0021ca5f_00000000-6_mandelbrot.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB5943:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE5943:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.type	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.isra.0, @function
_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.isra.0:
.LFB6651:
	.cfi_startproc
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	(%rdi), %rax
	movb	%sil, 12(%rsp)
	movq	-24(%rax), %rax
	cmpq	$0, 16(%rdi,%rax)
	je	.L3
	leaq	12(%rsp), %rsi
	movl	$1, %edx
	call	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
	jmp	.L2
.L3:
	movsbl	12(%rsp), %esi
	call	_ZNSo3putEc@PLT
.L2:
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6651:
	.size	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.isra.0, .-_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.isra.0
	.globl	_Z35__device_stub__Z12make_fractalPciiiPciii
	.type	_Z35__device_stub__Z12make_fractalPciiiPciii, @function
_Z35__device_stub__Z12make_fractalPciiiPciii:
.LFB5965:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movl	%esi, 20(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 16(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 12(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L7
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z12make_fractalPciii(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L7:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L9
	call	__stack_chk_fail@PLT
.L9:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE5965:
	.size	_Z35__device_stub__Z12make_fractalPciiiPciii, .-_Z35__device_stub__Z12make_fractalPciiiPciii
	.globl	_Z12make_fractalPciii
	.type	_Z12make_fractalPciii, @function
_Z12make_fractalPciii:
.LFB5966:
	.cfi_startproc
	endbr64
	jmp	_Z35__device_stub__Z12make_fractalPciiiPciii
	.cfi_endproc
.LFE5966:
	.size	_Z12make_fractalPciii, .-_Z12make_fractalPciii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"Faltam argumentos, devem ser no formato: ./executavel max_row max_column max_n"
.LC2:
	.string	"compute time: "
.LC3:
	.string	" s\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB5940:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$88, %rsp
	.cfi_def_cfa_offset 144
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	xorl	%eax, %eax
	cmpl	$5, %edi
	je	.L13
	leaq	.LC0(%rip), %rsi
	leaq	_ZSt4cout(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%rax, %rdi
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
	orl	$-1, %edi
	call	exit@PLT
.L13:
	movq	8(%rsi), %rdi
	movq	%rsi, %r13
	call	atoi@PLT
	movq	16(%r13), %rdi
	movl	%eax, %ebx
	call	atoi@PLT
	movq	24(%r13), %rdi
	movl	%eax, %ebp
	call	atoi@PLT
	movq	32(%r13), %rdi
	movl	%eax, %r14d
	call	atoi@PLT
	movl	%ebx, %esi
	movl	$1, %edx
	leaq	16(%rsp), %rdi
	imull	%ebp, %esi
	movl	%eax, %r13d
	movslq	%esi, %rsi
	call	cudaMallocManaged@PLT
	xorl	%esi, %esi
	leaq	40(%rsp), %rdi
	call	gettimeofday@PLT
	movl	%ebx, 56(%rsp)
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movabsq	$4294967297, %rdi
	movl	$1, %esi
	movl	$1, 36(%rsp)
	movq	%rdi, 60(%rsp)
	movl	64(%rsp), %ecx
	movq	56(%rsp), %rdx
	movq	%rdi, 28(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L14
	movq	16(%rsp), %rdi
	movl	%ebp, %ecx
	movl	%ebx, %edx
	movl	%r14d, %esi
	call	_Z35__device_stub__Z12make_fractalPciiiPciii
.L14:
	call	cudaDeviceSynchronize@PLT
	xorl	%esi, %esi
	leaq	56(%rsp), %rdi
	call	gettimeofday@PLT
	cvtsi2sdq	64(%rsp), %xmm0
	movsd	.LC1(%rip), %xmm2
	leaq	.LC2(%rip), %rsi
	cvtsi2sdq	56(%rsp), %xmm1
	leaq	_ZSt4cout(%rip), %rdi
	divsd	%xmm2, %xmm0
	addsd	%xmm1, %xmm0
	cvtsi2sdq	40(%rsp), %xmm1
	subsd	%xmm1, %xmm0
	cvtsi2sdq	48(%rsp), %xmm1
	divsd	%xmm2, %xmm1
	subsd	%xmm1, %xmm0
	movsd	%xmm0, 8(%rsp)
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movsd	8(%rsp), %xmm0
	movq	%rax, %rdi
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	leaq	.LC3(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	testl	%r13d, %r13d
	je	.L15
	xorl	%r14d, %r14d
	xorl	%r15d, %r15d
.L16:
	cmpl	%ebx, %r15d
	jge	.L15
	xorl	%r13d, %r13d
	movslq	%r14d, %r12
.L18:
	cmpl	%r13d, %ebp
	jle	.L24
	movq	16(%rsp), %rdx
	leaq	_ZSt4cout(%rip), %rdi
	addq	%r13, %rdx
	incq	%r13
	movsbl	(%rdx,%r12), %esi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.isra.0
	jmp	.L18
.L24:
	movl	$10, %esi
	leaq	_ZSt4cout(%rip), %rdi
	incl	%r15d
	addl	%ebp, %r14d
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.isra.0
	jmp	.L16
.L15:
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L19
	call	__stack_chk_fail@PLT
.L19:
	addq	$88, %rsp
	.cfi_def_cfa_offset 56
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE5940:
	.size	main, .-main
	.section	.rodata.str1.1
.LC4:
	.string	"_Z12make_fractalPciii"
.LC5:
	.string	"_ZN44_INTERNAL_419e6329_13_mandelbrot_cu_7ec67d3b4cuda3std3__45__cpo5beginE"
.LC6:
	.string	"_ZN44_INTERNAL_419e6329_13_mandelbrot_cu_7ec67d3b4cuda3std3__45__cpo3endE"
.LC7:
	.string	"_ZN44_INTERNAL_419e6329_13_mandelbrot_cu_7ec67d3b4cuda3std3__45__cpo6cbeginE"
.LC8:
	.string	"_ZN44_INTERNAL_419e6329_13_mandelbrot_cu_7ec67d3b4cuda3std3__45__cpo4cendE"
.LC9:
	.string	"_ZN44_INTERNAL_419e6329_13_mandelbrot_cu_7ec67d3b4cuda3std3__446_GLOBAL__N__419e6329_13_mandelbrot_cu_7ec67d3b6ignoreE"
.LC10:
	.string	"_ZN44_INTERNAL_419e6329_13_mandelbrot_cu_7ec67d3b4cuda3std3__419piecewise_constructE"
.LC11:
	.string	"_ZN44_INTERNAL_419e6329_13_mandelbrot_cu_7ec67d3b4cuda3std3__48in_placeE"
.LC12:
	.string	"_ZN44_INTERNAL_419e6329_13_mandelbrot_cu_7ec67d3b4cuda3std6ranges3__45__cpo4swapE"
.LC13:
	.string	"_ZN44_INTERNAL_419e6329_13_mandelbrot_cu_7ec67d3b4cuda3std6ranges3__45__cpo9iter_moveE"
.LC14:
	.string	"_ZN44_INTERNAL_419e6329_13_mandelbrot_cu_7ec67d3b4cuda3std6ranges3__45__cpo7advanceE"
.LC15:
	.string	"_ZN44_INTERNAL_419e6329_13_mandelbrot_cu_7ec67d3b6thrust20THRUST_200700_890_NS6system6detail10sequential3seqE"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB5968:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC4(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z12make_fractalPciii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC5(%rip), %rdx
	movl	$1, %r9d
	leaq	_ZN4cuda3std3__45__cpo5beginE(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC6(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN4cuda3std3__45__cpo3endE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC7(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN4cuda3std3__45__cpo6cbeginE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	popq	%r8
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC8(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN4cuda3std3__45__cpo4cendE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r9
	.cfi_def_cfa_offset 24
	popq	%r10
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC9(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN4cuda3std3__446_GLOBAL__N__419e6329_13_mandelbrot_cu_7ec67d3b6ignoreE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r11
	.cfi_def_cfa_offset 24
	popq	%rax
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC10(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN4cuda3std3__419piecewise_constructE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC11(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN4cuda3std3__48in_placeE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC12(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN4cuda3std6ranges3__45__cpo4swapE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	popq	%r8
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC13(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN4cuda3std6ranges3__45__cpo9iter_moveE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r9
	.cfi_def_cfa_offset 24
	popq	%r10
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC14(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN4cuda3std6ranges3__45__cpo7advanceE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r11
	.cfi_def_cfa_offset 24
	popq	%rax
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC15(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN6thrust20THRUST_200700_890_NS6system6detail10sequentialL3seqE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE5968:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata
	.type	_ZN6thrust20THRUST_200700_890_NS6system6detail10sequentialL3seqE, @object
	.size	_ZN6thrust20THRUST_200700_890_NS6system6detail10sequentialL3seqE, 1
_ZN6thrust20THRUST_200700_890_NS6system6detail10sequentialL3seqE:
	.zero	1
	.weak	_ZN4cuda3std6ranges3__45__cpo7advanceE
	.section	.rodata._ZN4cuda3std6ranges3__45__cpo7advanceE,"aG",@progbits,_ZN4cuda3std6ranges3__45__cpo7advanceE,comdat
	.type	_ZN4cuda3std6ranges3__45__cpo7advanceE, @gnu_unique_object
	.size	_ZN4cuda3std6ranges3__45__cpo7advanceE, 1
_ZN4cuda3std6ranges3__45__cpo7advanceE:
	.zero	1
	.hidden	_ZN4cuda3std3__446_GLOBAL__N__419e6329_13_mandelbrot_cu_7ec67d3b6ignoreE
	.weak	_ZN4cuda3std3__446_GLOBAL__N__419e6329_13_mandelbrot_cu_7ec67d3b6ignoreE
	.section	.rodata._ZN4cuda3std3__446_GLOBAL__N__419e6329_13_mandelbrot_cu_7ec67d3b6ignoreE,"aG",@progbits,_ZN4cuda3std3__446_GLOBAL__N__419e6329_13_mandelbrot_cu_7ec67d3b6ignoreE,comdat
	.type	_ZN4cuda3std3__446_GLOBAL__N__419e6329_13_mandelbrot_cu_7ec67d3b6ignoreE, @gnu_unique_object
	.size	_ZN4cuda3std3__446_GLOBAL__N__419e6329_13_mandelbrot_cu_7ec67d3b6ignoreE, 1
_ZN4cuda3std3__446_GLOBAL__N__419e6329_13_mandelbrot_cu_7ec67d3b6ignoreE:
	.zero	1
	.weak	_ZN4cuda3std3__48in_placeE
	.section	.rodata._ZN4cuda3std3__48in_placeE,"aG",@progbits,_ZN4cuda3std3__48in_placeE,comdat
	.type	_ZN4cuda3std3__48in_placeE, @gnu_unique_object
	.size	_ZN4cuda3std3__48in_placeE, 1
_ZN4cuda3std3__48in_placeE:
	.zero	1
	.weak	_ZN4cuda3std3__45__cpo4cendE
	.section	.rodata._ZN4cuda3std3__45__cpo4cendE,"aG",@progbits,_ZN4cuda3std3__45__cpo4cendE,comdat
	.type	_ZN4cuda3std3__45__cpo4cendE, @gnu_unique_object
	.size	_ZN4cuda3std3__45__cpo4cendE, 1
_ZN4cuda3std3__45__cpo4cendE:
	.zero	1
	.weak	_ZN4cuda3std3__45__cpo6cbeginE
	.section	.rodata._ZN4cuda3std3__45__cpo6cbeginE,"aG",@progbits,_ZN4cuda3std3__45__cpo6cbeginE,comdat
	.type	_ZN4cuda3std3__45__cpo6cbeginE, @gnu_unique_object
	.size	_ZN4cuda3std3__45__cpo6cbeginE, 1
_ZN4cuda3std3__45__cpo6cbeginE:
	.zero	1
	.weak	_ZN4cuda3std3__45__cpo3endE
	.section	.rodata._ZN4cuda3std3__45__cpo3endE,"aG",@progbits,_ZN4cuda3std3__45__cpo3endE,comdat
	.type	_ZN4cuda3std3__45__cpo3endE, @gnu_unique_object
	.size	_ZN4cuda3std3__45__cpo3endE, 1
_ZN4cuda3std3__45__cpo3endE:
	.zero	1
	.weak	_ZN4cuda3std3__45__cpo5beginE
	.section	.rodata._ZN4cuda3std3__45__cpo5beginE,"aG",@progbits,_ZN4cuda3std3__45__cpo5beginE,comdat
	.type	_ZN4cuda3std3__45__cpo5beginE, @gnu_unique_object
	.size	_ZN4cuda3std3__45__cpo5beginE, 1
_ZN4cuda3std3__45__cpo5beginE:
	.zero	1
	.weak	_ZN4cuda3std3__419piecewise_constructE
	.section	.rodata._ZN4cuda3std3__419piecewise_constructE,"aG",@progbits,_ZN4cuda3std3__419piecewise_constructE,comdat
	.type	_ZN4cuda3std3__419piecewise_constructE, @gnu_unique_object
	.size	_ZN4cuda3std3__419piecewise_constructE, 1
_ZN4cuda3std3__419piecewise_constructE:
	.zero	1
	.weak	_ZN4cuda3std6ranges3__45__cpo9iter_moveE
	.section	.rodata._ZN4cuda3std6ranges3__45__cpo9iter_moveE,"aG",@progbits,_ZN4cuda3std6ranges3__45__cpo9iter_moveE,comdat
	.type	_ZN4cuda3std6ranges3__45__cpo9iter_moveE, @gnu_unique_object
	.size	_ZN4cuda3std6ranges3__45__cpo9iter_moveE, 1
_ZN4cuda3std6ranges3__45__cpo9iter_moveE:
	.zero	1
	.weak	_ZN4cuda3std6ranges3__45__cpo4swapE
	.section	.rodata._ZN4cuda3std6ranges3__45__cpo4swapE,"aG",@progbits,_ZN4cuda3std6ranges3__45__cpo4swapE,comdat
	.type	_ZN4cuda3std6ranges3__45__cpo4swapE, @gnu_unique_object
	.size	_ZN4cuda3std6ranges3__45__cpo4swapE, 1
_ZN4cuda3std6ranges3__45__cpo4swapE:
	.zero	1
	.section	.rodata.cst8,"aM",@progbits,8
	.align 8
.LC1:
	.long	0
	.long	1093567616
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include <complex>
#include <iostream>
#include <sys/time.h>
#include <thrust/complex.h>

using namespace std;

__global__ void make_fractal(char *mat, int max_n, int max_row, int max_column){

   int r = threadIdx.x;

   using namespace std;


		for(int c = 0; c < max_column; ++c){
			thrust::complex<float> z;
			int n = 0;

         while(z.real() < 2 && ++n < max_n)
				z = pow(z, 2) + decltype(z)(
					(float)c * 2 / max_column - 1.5,
					(float)r * 2 / max_row - 1
				);
			mat[r*max_column + c]=(n == max_n ? '#' : '.');
		}


}

int main(int argc, char *argv[]){
	int max_row, max_column, max_n, print;

	if (argc != 5){
      std::cout << "Faltam argumentos, devem ser no formato: ./executavel max_row max_column max_n" << std::endl;
      exit(-1);
	}
	max_row = atoi(argv[1]);
	max_column = atoi(argv[2]);
	max_n = atoi(argv[3]);
	print = atoi(argv[4]);
	char *mat;
	hipMallocManaged(&mat, max_row*max_column*sizeof(unsigned char));





   timeval start, end;
   gettimeofday(&start, NULL);

   make_fractal<<<1, max_row>>>(mat, max_n, max_row, max_column);

   hipDeviceSynchronize();


	gettimeofday(&end, NULL);
   double runtime = end.tv_sec + end.tv_usec / 1000000.0 - start.tv_sec - start.tv_usec / 1000000.0;
   std::cout << "compute time: " << runtime << " s\n";

   if(print){
      for(int r = 0; r < max_row; ++r){
         for(int c = 0; c < max_column; ++c)
            std::cout << mat[r*max_column + c];
         cout << '\n';
      }
   }
}

	.text
	.file	"mandelbrot.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z27__device_stub__make_fractalPciii # -- Begin function _Z27__device_stub__make_fractalPciii
	.type	_Z27__device_stub__make_fractalPciii,@function
_Z27__device_stub__make_fractalPciii:   # @_Z27__device_stub__make_fractalPciii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	20(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	16(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	12(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z12make_fractalPciii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z27__device_stub__make_fractalPciii, .Lfunc_end0-_Z27__device_stub__make_fractalPciii
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0                          # -- Begin function main
.LCPI1_0:
	.quad	0x412e848000000000              # double 1.0E+6
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$72, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	cmpl	$5, %edi
	jne	.LBB1_16
# %bb.1:
	movq	%rsi, %r12
	movq	8(%rsi), %rdi
	callq	atoi
	movl	%eax, %r14d
	movq	16(%r12), %rdi
	callq	atoi
	movl	%eax, %ebx
	movq	24(%r12), %rdi
	callq	atoi
	movl	%eax, %r15d
	movq	32(%r12), %rdi
	callq	atoi
	movl	%eax, %ebp
	movl	%ebx, %eax
	imull	%r14d, %eax
	movslq	%eax, %rsi
	leaq	32(%rsp), %rdi
	movl	$1, %edx
	callq	hipMallocManaged
	leaq	40(%rsp), %rdi
	xorl	%esi, %esi
	callq	gettimeofday
	movl	%r14d, %edx
	movq	%rdx, 24(%rsp)                  # 8-byte Spill
	btsq	$32, %rdx
	movabsq	$4294967296, %rdi               # imm = 0x100000000
	orq	$1, %rdi
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_3
# %bb.2:
	movq	32(%rsp), %rdi
	movl	%r15d, %esi
	movq	24(%rsp), %rdx                  # 8-byte Reload
                                        # kill: def $edx killed $edx killed $rdx
	movl	%ebx, %ecx
	callq	_Z27__device_stub__make_fractalPciii
.LBB1_3:
	callq	hipDeviceSynchronize
	leaq	56(%rsp), %r15
	movq	%r15, %rdi
	xorl	%esi, %esi
	callq	gettimeofday
	cvtsi2sdq	(%r15), %xmm0
	cvtsi2sdq	8(%r15), %xmm2
	movsd	.LCPI1_0(%rip), %xmm1           # xmm1 = mem[0],zero
	divsd	%xmm1, %xmm2
	addsd	%xmm0, %xmm2
	xorps	%xmm0, %xmm0
	cvtsi2sdq	40(%rsp), %xmm0
	subsd	%xmm0, %xmm2
	xorps	%xmm0, %xmm0
	cvtsi2sdq	48(%rsp), %xmm0
	divsd	%xmm1, %xmm0
	subsd	%xmm0, %xmm2
	movsd	%xmm2, 16(%rsp)                 # 8-byte Spill
	movl	$_ZSt4cout, %edi
	movl	$.L.str.1, %esi
	movl	$14, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	$_ZSt4cout, %edi
	movsd	16(%rsp), %xmm0                 # 8-byte Reload
                                        # xmm0 = mem[0],zero
	callq	_ZNSo9_M_insertIdEERSoT_
	movl	$.L.str.2, %esi
	movl	$3, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	testl	%ebp, %ebp
	je	.LBB1_11
# %bb.4:
	cmpl	$0, 24(%rsp)                    # 4-byte Folded Reload
	jle	.LBB1_11
# %bb.5:                                # %.preheader.lr.ph
	movl	%ebx, %eax
	movq	%rax, 16(%rsp)                  # 8-byte Spill
	xorl	%r14d, %r14d
	leaq	15(%rsp), %r15
	xorl	%ebp, %ebp
.LBB1_6:                                # %.preheader
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB1_12 Depth 2
	movl	%r14d, %r14d
	movq	16(%rsp), %r12                  # 8-byte Reload
	movq	%r14, %r13
	testl	%ebx, %ebx
	jle	.LBB1_7
.LBB1_12:                               #   Parent Loop BB1_6 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movq	32(%rsp), %rax
	movb	(%rax,%r13), %al
	movb	%al, 15(%rsp)
	movq	_ZSt4cout(%rip), %rcx
	movq	-24(%rcx), %rcx
	cmpq	$0, _ZSt4cout+16(%rcx)
	je	.LBB1_14
# %bb.13:                               #   in Loop: Header=BB1_12 Depth=2
	movl	$_ZSt4cout, %edi
	movl	$1, %edx
	movq	%r15, %rsi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	jmp	.LBB1_15
.LBB1_14:                               #   in Loop: Header=BB1_12 Depth=2
	movsbl	%al, %esi
	movl	$_ZSt4cout, %edi
	callq	_ZNSo3putEc
.LBB1_15:                               # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.exit30
                                        #   in Loop: Header=BB1_12 Depth=2
	incq	%r13
	decq	%r12
	jne	.LBB1_12
.LBB1_7:                                # %._crit_edge
                                        #   in Loop: Header=BB1_6 Depth=1
	movb	$10, 15(%rsp)
	movq	_ZSt4cout(%rip), %rax
	movq	-24(%rax), %rax
	cmpq	$0, _ZSt4cout+16(%rax)
	je	.LBB1_9
# %bb.8:                                #   in Loop: Header=BB1_6 Depth=1
	movl	$_ZSt4cout, %edi
	movl	$1, %edx
	movq	%r15, %rsi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	jmp	.LBB1_10
.LBB1_9:                                #   in Loop: Header=BB1_6 Depth=1
	movl	$_ZSt4cout, %edi
	movl	$10, %esi
	callq	_ZNSo3putEc
.LBB1_10:                               # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.exit
                                        #   in Loop: Header=BB1_6 Depth=1
	incq	%rbp
	addl	%ebx, %r14d
	cmpq	24(%rsp), %rbp                  # 8-byte Folded Reload
	jne	.LBB1_6
.LBB1_11:                               # %.loopexit
	xorl	%eax, %eax
	addq	$72, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB1_16:
	.cfi_def_cfa_offset 128
	movl	$_ZSt4cout, %edi
	movl	$.L.str, %esi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movq	%rax, %rdi
	callq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
	movl	$-1, %edi
	callq	exit
.Lfunc_end1:
	.size	main, .Lfunc_end1-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z12make_fractalPciii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z12make_fractalPciii,@object   # @_Z12make_fractalPciii
	.section	.rodata,"a",@progbits
	.globl	_Z12make_fractalPciii
	.p2align	3, 0x0
_Z12make_fractalPciii:
	.quad	_Z27__device_stub__make_fractalPciii
	.size	_Z12make_fractalPciii, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"Faltam argumentos, devem ser no formato: ./executavel max_row max_column max_n"
	.size	.L.str, 79

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"compute time: "
	.size	.L.str.1, 15

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	" s\n"
	.size	.L.str.2, 4

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z12make_fractalPciii"
	.size	.L__unnamed_1, 22

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z27__device_stub__make_fractalPciii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z12make_fractalPciii
	.addrsig_sym _ZSt4cout
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z12make_fractalPciii   ; -- Begin function _Z12make_fractalPciii
	.globl	_Z12make_fractalPciii
	.p2align	8
	.type	_Z12make_fractalPciii,@function
_Z12make_fractalPciii:                  ; @_Z12make_fractalPciii
; %bb.0:
	s_load_b128 s[4:7], s[0:1], 0x8
	s_waitcnt lgkmcnt(0)
	s_cmp_lt_i32 s6, 1
	s_cbranch_scc1 .LBB0_92
; %bb.1:                                ; %.preheader.lr.ph
	v_cvt_f32_i32_e32 v1, v0
	v_cvt_f32_i32_e32 v2, s5
	s_load_b64 s[8:9], s[0:1], 0x0
	v_mul_lo_u32 v14, v0, s6
	v_cvt_f32_i32_e32 v13, s6
	v_add_f32_e32 v1, v1, v1
	s_max_i32 s3, s4, 1
	s_mov_b32 s5, 0
	s_mov_b32 s7, 0x3e9b6dac
	s_mov_b32 s10, 0x3b2d2a58
	v_div_scale_f32 v3, null, v2, v2, v1
	v_div_scale_f32 v6, vcc_lo, v1, v2, v1
	s_mov_b32 s11, 0x7fffff
	s_delay_alu instid0(VALU_DEP_2)
	v_rcp_f32_e32 v4, v3
	s_add_i32 s12, s3, -1
	s_mov_b32 s13, 0xb94c1982
	s_mov_b32 s14, 0x37d75334
	s_mov_b32 s15, 0x7f000000
                                        ; implicit-def: $vgpr18
                                        ; implicit-def: $vgpr19
	v_dual_mov_b32 v15, 0x4016cbe4 :: v_dual_mov_b32 v12, 0
	s_waitcnt_depctr 0xfff
	v_fma_f32 v5, -v3, v4, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v4, v5, v4
	v_mul_f32_e32 v5, v6, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v7, -v3, v5, v6
	v_fmac_f32_e32 v5, v7, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v3, -v3, v5, v6
	v_div_fmas_f32 v3, v3, v4, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f32 v0, v3, v2, v1
	v_add_f32_e32 v16, -1.0, v0
.LBB0_2:                                ; %.preheader
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_4 Depth 2
                                        ;       Child Loop BB0_16 Depth 3
                                        ;         Child Loop BB0_17 Depth 4
                                        ;       Child Loop BB0_20 Depth 3
	v_mov_b32_e32 v0, v12
	s_mov_b32 s16, exec_lo
	v_cmpx_gt_f32_e32 2.0, v19
	s_cbranch_execz .LBB0_91
; %bb.3:                                ; %.lr.ph
                                        ;   in Loop: Header=BB0_2 Depth=1
	v_cvt_f32_i32_e32 v0, s5
	s_mov_b32 s17, 0
	s_mov_b32 s18, 0
                                        ; implicit-def: $sgpr0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v0, v0, v0
	v_div_scale_f32 v1, null, v13, v13, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v2, v1
	s_waitcnt_depctr 0xfff
	v_fma_f32 v3, -v1, v2, 1.0
	v_fmac_f32_e32 v2, v3, v2
	v_div_scale_f32 v3, vcc_lo, v0, v13, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v4, v3, v2
	v_fma_f32 v5, -v1, v4, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v4, v5, v2
	v_fma_f32 v1, -v1, v4, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v1, v1, v2, v4
	v_div_fixup_f32 v0, v1, v13, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f32_e32 v17, 0xbfc00000, v0
.LBB0_4:                                ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB0_16 Depth 3
                                        ;         Child Loop BB0_17 Depth 4
                                        ;       Child Loop BB0_20 Depth 3
	s_or_b32 s0, s0, exec_lo
	s_cmp_eq_u32 s18, s12
	s_cbranch_scc1 .LBB0_88
; %bb.5:                                ;   in Loop: Header=BB0_4 Depth=2
                                        ; implicit-def: $vgpr2
                                        ; implicit-def: $vgpr0
	s_mov_b32 s0, exec_lo
	v_cmpx_o_f32_e32 v18, v19
	s_xor_b32 s19, exec_lo, s0
	s_cbranch_execz .LBB0_37
; %bb.6:                                ;   in Loop: Header=BB0_4 Depth=2
	v_cmp_lt_f32_e64 s0, |v19|, |v18|
                                        ; implicit-def: $vgpr2
                                        ; implicit-def: $vgpr0
	s_mov_b32 s1, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v1, |v18|, |v19|, s0
	v_cmpx_nlt_f32_e32 0x77f684df, v1
	s_xor_b32 s20, exec_lo, s1
	s_cbranch_execz .LBB0_34
; %bb.7:                                ;   in Loop: Header=BB0_4 Depth=2
	v_and_b32_e32 v0, 0x7fffffff, v18
                                        ; implicit-def: $vgpr2
	s_mov_b32 s1, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v3, |v19|, v0, s0
                                        ; implicit-def: $vgpr0
	v_cmpx_neq_f32_e32 1.0, v3
	s_xor_b32 s2, exec_lo, s1
	s_cbranch_execz .LBB0_27
; %bb.8:                                ;   in Loop: Header=BB0_4 Depth=2
	v_max_f32_e32 v0, v1, v1
	v_max_f32_e32 v2, v3, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_min_f32_e32 v4, v2, v0
	v_max_f32_e32 v0, v2, v0
                                        ; implicit-def: $vgpr2
	v_cmp_ngt_f32_e32 vcc_lo, 0x358637bd, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_nlt_f32_e64 s1, 0x49742400, v0
                                        ; implicit-def: $vgpr0
	s_and_b32 s1, s1, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_saveexec_b32 s21, s1
	s_xor_b32 s21, exec_lo, s21
	s_cbranch_execz .LBB0_24
; %bb.9:                                ;   in Loop: Header=BB0_4 Depth=2
                                        ; implicit-def: $vgpr2
                                        ; implicit-def: $vgpr0
	s_mov_b32 s1, exec_lo
	v_cmpx_le_f32_e32 1.0, v3
	s_xor_b32 s22, exec_lo, s1
	s_cbranch_execz .LBB0_11
; %bb.10:                               ;   in Loop: Header=BB0_4 Depth=2
	v_add_f32_e32 v0, -1.0, v3
	v_add_f32_e32 v2, 1.0, v3
	v_cmp_class_f32_e64 s23, v19, 0x204
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v0, v0, v2
	v_fmac_f32_e32 v0, v1, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v1, 1.0, v0
	v_frexp_mant_f32_e32 v2, v1
	v_frexp_exp_i32_f32_e32 v3, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_f32_e32 vcc_lo, 0x3f2aaaab, v2
	v_subrev_co_ci_u32_e32 v2, vcc_lo, 0, v3, vcc_lo
	v_add_f32_e32 v3, -1.0, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v4, 0, v2
	v_cvt_f32_i32_e32 v2, v2
	v_sub_f32_e32 v5, v3, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ldexp_f32 v1, v1, v4
	v_dual_sub_f32 v3, v0, v3 :: v_dual_add_f32 v6, 1.0, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v5, 1.0, v5
	v_add_f32_e32 v3, v3, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_add_f32_e32 v5, -1.0, v6
	v_cmp_eq_f32_e32 vcc_lo, 0x7f800000, v0
	v_cmp_neq_f32_e64 s1, -1.0, v0
	v_ldexp_f32 v3, v3, v4
	v_add_f32_e32 v4, -1.0, v1
	v_sub_f32_e32 v5, v1, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v7, 1.0, v4
	v_sub_f32_e32 v1, v1, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v1, v3, v1
	v_add_f32_e32 v8, v4, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v4, v8, v4 :: v_dual_add_f32 v5, v3, v5
	v_add_f32_e32 v7, v6, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v3, v7
	v_sub_f32_e32 v6, v7, v6
	v_sub_f32_e32 v5, v5, v6
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v9, v8, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v10, v7, v9
	v_fma_f32 v6, v9, v7, -v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v6, v9, v5
	v_add_f32_e32 v11, v10, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v20, v8, v11
	v_sub_f32_e32 v8, v8, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v8, v8, v11 :: v_dual_sub_f32 v1, v1, v4
	v_sub_f32_e32 v4, v11, v10
	v_dual_sub_f32 v4, v4, v6 :: v_dual_add_f32 v1, v1, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v1, v4, v1
	v_add_f32_e32 v4, v20, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v6, v3, v4
	v_dual_sub_f32 v11, v20, v4 :: v_dual_mul_f32 v8, v7, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v7, v6, v7, -v8
	v_fmac_f32_e32 v7, v6, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v5, v8, v7
	v_sub_f32_e32 v8, v5, v8
	v_dual_sub_f32 v10, v4, v5 :: v_dual_add_f32 v1, v1, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v4, v4, v10
	v_sub_f32_e32 v4, v4, v5
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v5, v8, v7
	v_max_f32_e64 v7, |v18|, |v18|
	v_add_f32_e32 v1, v1, v4
	v_add_f32_e32 v4, v9, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v1, v5, v1
	v_sub_f32_e32 v5, v4, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_add_f32 v1, v10, v1 :: v_dual_mul_f32 v10, 0x3f317218, v2
	v_sub_f32_e32 v5, v6, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v1, v3, v1
	v_fma_f32 v11, 0x3f317218, v2, -v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v1, v5, v1
	v_fmac_f32_e32 v11, 0xb102e308, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v3, v4, v1
	v_mul_f32_e32 v5, v3, v3
	v_ldexp_f32 v9, v3, 1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmaak_f32 v6, s7, v5, 0x3ecc95a3
	v_dual_mul_f32 v8, v3, v5 :: v_dual_fmaak_f32 v5, v5, v6, 0x3f2aaada
	v_max_f32_e64 v6, |v19|, |v19|
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_mul_f32 v5, v8, v5 :: v_dual_max_f32 v8, v6, v7
	v_dual_min_f32 v6, v6, v7 :: v_dual_sub_f32 v3, v3, v4
	v_add_f32_e32 v4, v9, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_frexp_mant_f32_e32 v7, v8
	v_frexp_exp_i32_f32_e32 v8, v8
	v_sub_f32_e32 v1, v1, v3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v3, v4, v9
	v_rcp_f32_e32 v7, v7
	v_frexp_exp_i32_f32_e32 v9, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_ldexp_f32 v1, v1, 1
	v_sub_f32_e32 v3, v5, v3
	v_frexp_mant_f32_e32 v5, v6
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v6, v9, v8
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v2, v5, v7
	v_ldexp_f32 v2, v2, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v7, v2, v2
	v_add_f32_e32 v1, v1, v3
	v_add_f32_e32 v3, v10, v11
	v_fmaak_f32 v9, s10, v7, 0xbc7a590c
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_add_f32 v5, v4, v1 :: v_dual_sub_f32 v10, v3, v10
	v_fmaak_f32 v9, v7, v9, 0x3d29fb3f
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f32_e32 v6, v3, v5
	v_sub_f32_e32 v4, v5, v4
	v_sub_f32_e32 v10, v11, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v8, v6, v3 :: v_dual_sub_f32 v1, v1, v4
	v_sub_f32_e32 v20, v6, v8
	v_dual_sub_f32 v4, v5, v8 :: v_dual_fmaak_f32 v5, v7, v9, 0xbd97d4d7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v8, v10, v1 :: v_dual_sub_f32 v3, v3, v20
	v_dual_add_f32 v3, v4, v3 :: v_dual_fmaak_f32 v4, v7, v5, 0x3dd931b2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v5, v8, v10 :: v_dual_fmaak_f32 v4, v7, v4, 0xbe1160e6
	v_dual_sub_f32 v1, v1, v5 :: v_dual_fmaak_f32 v4, v7, v4, 0x3e4cb8bf
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_fmaak_f32 v4, v7, v4, 0xbeaaaa62 :: v_dual_add_f32 v3, v8, v3
	v_sub_f32_e32 v8, v8, v5
	v_dual_mul_f32 v4, v7, v4 :: v_dual_add_f32 v9, v6, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v5, v10, v8
	v_fmac_f32_e32 v2, v2, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v6, v9, v6
	v_add_f32_e32 v1, v1, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v3, v3, v6
	v_add_f32_e32 v1, v1, v3
	v_sub_f32_e32 v3, 0x3fc90fdb, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v1, v9, v1
	v_cndmask_b32_e64 v2, v2, v3, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v1, v1, v0, vcc_lo
	v_cmp_gt_i32_e32 vcc_lo, 0, v19
	v_sub_f32_e32 v4, 0x40490fdb, v2
	v_cndmask_b32_e64 v3, 0, 0x40490fdb, vcc_lo
	v_cmp_ngt_f32_e32 vcc_lo, -1.0, v0
	v_cndmask_b32_e32 v1, 0x7fc00000, v1, vcc_lo
	v_cmp_gt_f32_e32 vcc_lo, 0, v19
                                        ; implicit-def: $vgpr19
	s_delay_alu instid0(VALU_DEP_2)
	v_cndmask_b32_e64 v1, 0xff800000, v1, s1
	v_cndmask_b32_e32 v2, v2, v4, vcc_lo
	v_cndmask_b32_e32 v4, 0x3f490fdb, v15, vcc_lo
	v_cmp_gt_f32_e64 vcc_lo, 0x33800000, |v0|
	v_cmp_class_f32_e64 s1, v18, 0x204
	v_cndmask_b32_e32 v0, v1, v0, vcc_lo
	v_cmp_eq_f32_e32 vcc_lo, 0, v18
	v_cndmask_b32_e32 v1, v2, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	s_and_b32 vcc_lo, s23, s1
	v_mul_f32_e32 v2, 0.5, v0
                                        ; implicit-def: $vgpr3
	s_delay_alu instid0(VALU_DEP_2)
	v_cndmask_b32_e32 v0, v1, v4, vcc_lo
                                        ; implicit-def: $vgpr1
.LBB0_11:                               ; %Flow99
                                        ;   in Loop: Header=BB0_4 Depth=2
	s_and_not1_saveexec_b32 s22, s22
	s_cbranch_execz .LBB0_23
; %bb.12:                               ;   in Loop: Header=BB0_4 Depth=2
	v_mul_f32_e32 v4, v1, v1
                                        ; implicit-def: $vgpr2
                                        ; implicit-def: $vgpr0
	s_mov_b32 s1, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v4, v3, v3
	v_cmpx_ge_f32_e32 0x3f333333, v4
	s_xor_b32 s23, exec_lo, s1
	s_cbranch_execz .LBB0_14
; %bb.13:                               ;   in Loop: Header=BB0_4 Depth=2
	v_max_f32_e64 v0, |v18|, |v18|
	v_max_f32_e64 v1, |v19|, |v19|
	v_cmp_gt_f32_e32 vcc_lo, 0x800000, v4
	v_cmp_gt_i32_e64 s1, 0, v19
	v_cmp_class_f32_e64 s24, v19, 0x204
	v_cmp_class_f32_e64 s25, v18, 0x204
	v_max_f32_e32 v2, v1, v0
	v_min_f32_e32 v0, v1, v0
	v_cndmask_b32_e64 v5, 0, 0x41b17218, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_frexp_mant_f32_e32 v3, v2
	v_frexp_exp_i32_f32_e32 v2, v2
	v_rcp_f32_e32 v1, v3
	v_frexp_exp_i32_f32_e32 v3, v0
	v_frexp_mant_f32_e32 v0, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v2, v3, v2
	v_cndmask_b32_e64 v3, 1.0, 0x4f800000, vcc_lo
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v0, v0, v1
	v_mul_f32_e32 v3, v4, v3
	v_ldexp_f32 v0, v0, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_log_f32_e32 v3, v3
	v_mul_f32_e32 v1, v0, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_fmaak_f32 v2, s10, v1, 0xbc7a590c
	s_waitcnt_depctr 0xfff
	v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v3|
	v_fmaak_f32 v2, v1, v2, 0x3d29fb3f
	v_fmaak_f32 v2, v1, v2, 0xbd97d4d7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmaak_f32 v2, v1, v2, 0x3dd931b2
	v_fmaak_f32 v2, v1, v2, 0xbe1160e6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmaak_f32 v2, v1, v2, 0x3e4cb8bf
	v_fmaak_f32 v2, v1, v2, 0xbeaaaa62
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v1, v1, v2 :: v_dual_mul_f32 v2, 0x3f317217, v3
	v_fmac_f32_e32 v0, v0, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v1, 0x3f317217, v3, -v2
	v_fmac_f32_e32 v1, 0x3377d1cf, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_add_f32_e32 v1, v2, v1
	v_cndmask_b32_e64 v2, 0, 0x40490fdb, s1
	v_cmp_eq_f32_e64 s1, 0, v18
	v_cndmask_b32_e32 v1, v3, v1, vcc_lo
	v_cmp_gt_f32_e32 vcc_lo, 0, v19
                                        ; implicit-def: $vgpr19
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v1, v1, v5
	v_cndmask_b32_e32 v3, 0x3f490fdb, v15, vcc_lo
	v_sub_f32_e32 v4, 0x3fc90fdb, v0
	v_cndmask_b32_e64 v0, v0, v4, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v4, 0x40490fdb, v0
	v_cndmask_b32_e32 v0, v0, v4, vcc_lo
	s_and_b32 vcc_lo, s24, s25
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v0, v0, v2, s1
	v_mul_f32_e32 v2, 0.5, v1
                                        ; implicit-def: $vgpr1
	v_cndmask_b32_e32 v0, v0, v3, vcc_lo
                                        ; implicit-def: $vgpr3
.LBB0_14:                               ; %Flow97
                                        ;   in Loop: Header=BB0_4 Depth=2
	s_and_not1_saveexec_b32 s23, s23
	s_cbranch_execz .LBB0_22
; %bb.15:                               ;   in Loop: Header=BB0_4 Depth=2
	v_and_b32_e32 v4, 0xffff0000, v1
	v_and_b32_e32 v2, 0xffff0000, v3
	s_mov_b32 s1, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v5, v1, v4
	v_sub_f32_e32 v3, v3, v2
	v_mul_f32_e32 v0, v2, v2
	v_dual_add_f32 v8, v2, v2 :: v_dual_mul_f32 v1, v4, v4
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_and_b32_e32 v7, 0xffff0000, v5
	v_dual_add_f32 v9, v4, v4 :: v_dual_and_b32 v6, 0xffff0000, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_dual_sub_f32 v11, v5, v7 :: v_dual_sub_f32 v10, v3, v6
	v_dual_mul_f32 v4, v6, v6 :: v_dual_add_f32 v21, v7, v7
	v_dual_add_f32 v20, v6, v6 :: v_dual_mul_f32 v5, v7, v7
	v_dual_mul_f32 v2, v8, v6 :: v_dual_mul_f32 v3, v9, v7
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_mul_f32 v6, v8, v10 :: v_dual_mul_f32 v7, v9, v11
	v_dual_mul_f32 v8, v20, v10 :: v_dual_mul_f32 v9, v21, v11
	v_dual_mul_f32 v10, v10, v10 :: v_dual_mul_f32 v11, v11, v11
.LBB0_16:                               ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_4 Depth=2
                                        ; =>    This Loop Header: Depth=3
                                        ;         Child Loop BB0_17 Depth 4
	v_dual_mov_b32 v20, 1 :: v_dual_mov_b32 v21, v0
	s_mov_b32 s24, 0
.LBB0_17:                               ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_4 Depth=2
                                        ;       Parent Loop BB0_16 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	s_add_i32 s25, s24, 1
	v_dual_mov_b32 v33, v11 :: v_dual_mov_b32 v32, v10
	s_mov_b32 m0, s25
	v_dual_mov_b32 v23, v1 :: v_dual_mov_b32 v22, v0
	v_movrels_b32_e32 v34, v0
	s_mov_b32 m0, s24
	v_dual_mov_b32 v31, v9 :: v_dual_mov_b32 v30, v8
	v_dual_mov_b32 v29, v7 :: v_dual_mov_b32 v28, v6
	s_delay_alu instid0(VALU_DEP_3)
	v_cmp_lt_f32_e32 vcc_lo, v21, v34
	v_dual_mov_b32 v27, v5 :: v_dual_mov_b32 v26, v4
	v_dual_mov_b32 v25, v3 :: v_dual_mov_b32 v24, v2
	v_movreld_b32_e32 v22, v34
	s_mov_b32 m0, s25
	v_cndmask_b32_e64 v20, v20, 0, vcc_lo
	v_movreld_b32_e32 v22, v21
	v_dual_cndmask_b32 v11, v11, v33 :: v_dual_cndmask_b32 v10, v10, v32
	v_dual_cndmask_b32 v9, v9, v31 :: v_dual_cndmask_b32 v8, v8, v30
	v_dual_cndmask_b32 v7, v7, v29 :: v_dual_cndmask_b32 v6, v6, v28
	v_dual_cndmask_b32 v5, v5, v27 :: v_dual_cndmask_b32 v4, v4, v26
	v_dual_cndmask_b32 v3, v3, v25 :: v_dual_cndmask_b32 v2, v2, v24
	v_dual_cndmask_b32 v1, v1, v23 :: v_dual_cndmask_b32 v0, v0, v22
	v_cndmask_b32_e32 v21, v34, v21, vcc_lo
	s_cmp_lg_u32 s25, 11
	s_mov_b32 s24, s25
	s_cbranch_scc1 .LBB0_17
; %bb.18:                               ;   in Loop: Header=BB0_16 Depth=3
	v_cmp_ne_u32_e32 vcc_lo, 0, v20
	s_or_b32 s1, vcc_lo, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s1
	s_cbranch_execnz .LBB0_16
; %bb.19:                               ; %.preheader.i.i.i.preheader
                                        ;   in Loop: Header=BB0_4 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	v_mov_b32_e32 v20, -1.0
	s_mov_b32 s1, 0
.LBB0_20:                               ; %.preheader.i.i.i
                                        ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_4 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	s_mov_b32 m0, s1
	s_add_i32 s1, s1, 1
	v_movrels_b32_e32 v21, v0
	s_cmp_lg_u32 s1, 12
	v_add_f32_e32 v20, v20, v21
	s_cbranch_scc1 .LBB0_20
; %bb.21:                               ;   in Loop: Header=BB0_4 Depth=2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_add_f32_e32 v0, 1.0, v20
	v_cmp_neq_f32_e64 s1, -1.0, v20
	v_cmp_class_f32_e64 s24, v19, 0x204
	v_frexp_mant_f32_e32 v1, v0
	v_frexp_exp_i32_f32_e32 v2, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_f32_e32 vcc_lo, 0x3f2aaaab, v1
	v_subrev_co_ci_u32_e32 v1, vcc_lo, 0, v2, vcc_lo
	v_add_f32_e32 v2, -1.0, v0
	v_cmp_eq_f32_e32 vcc_lo, 0x7f800000, v20
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_sub_nc_u32_e32 v3, 0, v1
	v_cvt_f32_i32_e32 v1, v1
	v_sub_f32_e32 v4, v2, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_ldexp_f32 v0, v0, v3
	v_sub_f32_e32 v2, v20, v2
	v_add_f32_e32 v4, 1.0, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v5, 1.0, v0
	v_add_f32_e32 v2, v2, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v4, -1.0, v5
	v_ldexp_f32 v2, v2, v3
	v_add_f32_e32 v3, -1.0, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v4, v0, v4
	v_add_f32_e32 v6, 1.0, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v4, v2, v4
	v_sub_f32_e32 v0, v0, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v6, v5, v4
	v_add_f32_e32 v0, v2, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v2, v6
	v_sub_f32_e32 v5, v6, v5
	v_dual_add_f32 v7, v3, v0 :: v_dual_sub_f32 v4, v4, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v3, v7, v3
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v8, v7, v2
	v_dual_sub_f32 v0, v0, v3 :: v_dual_mul_f32 v9, v6, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v5, v8, v6, -v9
	v_fmac_f32_e32 v5, v8, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v10, v9, v5
	v_sub_f32_e32 v11, v7, v10
	v_sub_f32_e32 v3, v10, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v7, v7, v11
	v_sub_f32_e32 v3, v3, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v7, v7, v10
	v_add_f32_e32 v0, v0, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v0, v3, v0
	v_add_f32_e32 v3, v11, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v5, v2, v3
	v_dual_sub_f32 v10, v11, v3 :: v_dual_mul_f32 v7, v6, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v6, v5, v6, -v7
	v_fmac_f32_e32 v6, v5, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v4, v7, v6
	v_sub_f32_e32 v9, v3, v4
	v_sub_f32_e32 v7, v4, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v0, v0, v10 :: v_dual_sub_f32 v3, v3, v9
	v_sub_f32_e32 v3, v3, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f32_e32 v0, v0, v3
	v_dual_add_f32 v3, v8, v5 :: v_dual_sub_f32 v4, v7, v6
	v_max_f32_e64 v6, |v18|, |v18|
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v0, v4, v0
	v_sub_f32_e32 v4, v3, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v0, v9, v0 :: v_dual_mul_f32 v9, 0x3f317218, v1
	v_mul_f32_e32 v0, v2, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v10, 0x3f317218, v1, -v9
	v_fmac_f32_e32 v10, 0xb102e308, v1
	v_sub_f32_e32 v4, v5, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v0, v4, v0
	v_add_f32_e32 v2, v3, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v4, v2, v2
	v_ldexp_f32 v8, v2, 1
	v_fmaak_f32 v5, s7, v4, 0x3ecc95a3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v7, v2, v4 :: v_dual_fmaak_f32 v4, v4, v5, 0x3f2aaada
	v_max_f32_e64 v5, |v19|, |v19|
	v_dual_mul_f32 v4, v7, v4 :: v_dual_max_f32 v7, v5, v6
	v_dual_min_f32 v5, v5, v6 :: v_dual_sub_f32 v2, v2, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v3, v8, v4
	v_frexp_mant_f32_e32 v6, v7
	v_frexp_exp_i32_f32_e32 v7, v7
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v0, v0, v2
	v_sub_f32_e32 v2, v3, v8
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_rcp_f32_e32 v6, v6
	v_frexp_exp_i32_f32_e32 v8, v5
	v_ldexp_f32 v0, v0, 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v2, v4, v2
	v_frexp_mant_f32_e32 v4, v5
	v_sub_nc_u32_e32 v5, v8, v7
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v1, v4, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ldexp_f32 v1, v1, v5
	v_mul_f32_e32 v6, v1, v1
	v_add_f32_e32 v0, v0, v2
	v_add_f32_e32 v2, v9, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmaak_f32 v8, s10, v6, 0xbc7a590c
	v_dual_add_f32 v4, v3, v0 :: v_dual_sub_f32 v9, v2, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmaak_f32 v8, v6, v8, 0x3d29fb3f
	v_add_f32_e32 v5, v2, v4
	v_sub_f32_e32 v3, v4, v3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v9, v10, v9
	v_dual_sub_f32 v7, v5, v2 :: v_dual_sub_f32 v0, v0, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v11, v5, v7
	v_dual_sub_f32 v3, v4, v7 :: v_dual_fmaak_f32 v4, v6, v8, 0xbd97d4d7
	v_dual_add_f32 v7, v9, v0 :: v_dual_sub_f32 v2, v2, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_add_f32 v2, v3, v2 :: v_dual_fmaak_f32 v3, v6, v4, 0x3dd931b2
	v_sub_f32_e32 v4, v7, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_add_f32 v2, v7, v2 :: v_dual_fmaak_f32 v3, v6, v3, 0xbe1160e6
	v_sub_f32_e32 v7, v7, v4
	v_sub_f32_e32 v0, v0, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v8, v5, v2 :: v_dual_fmaak_f32 v3, v6, v3, 0x3e4cb8bf
	v_dual_sub_f32 v4, v9, v7 :: v_dual_sub_f32 v5, v8, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_fmaak_f32 v3, v6, v3, 0xbeaaaa62 :: v_dual_add_f32 v0, v0, v4
	v_sub_f32_e32 v2, v2, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v3, v6, v3 :: v_dual_add_f32 v0, v0, v2
	v_dual_fmac_f32 v1, v1, v3 :: v_dual_add_f32 v0, v8, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v2, 0x3fc90fdb, v1
	v_cndmask_b32_e32 v0, v0, v20, vcc_lo
	v_cmp_gt_i32_e32 vcc_lo, 0, v19
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v1, v1, v2, s0
	v_cndmask_b32_e64 v2, 0, 0x40490fdb, vcc_lo
	v_cmp_ngt_f32_e32 vcc_lo, -1.0, v20
	v_sub_f32_e32 v3, 0x40490fdb, v1
	v_cndmask_b32_e32 v0, 0x7fc00000, v0, vcc_lo
	v_cmp_gt_f32_e32 vcc_lo, 0, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v0, 0xff800000, v0, s1
	v_cndmask_b32_e32 v1, v1, v3, vcc_lo
	v_cndmask_b32_e32 v3, 0x3f490fdb, v15, vcc_lo
	v_cmp_gt_f32_e64 vcc_lo, 0x33800000, |v20|
	v_cmp_class_f32_e64 s1, v18, 0x204
	v_cndmask_b32_e32 v0, v0, v20, vcc_lo
	v_cmp_eq_f32_e32 vcc_lo, 0, v18
	v_cndmask_b32_e32 v1, v1, v2, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	s_and_b32 vcc_lo, s24, s1
	v_mul_f32_e32 v2, 0.5, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_cndmask_b32_e32 v0, v1, v3, vcc_lo
.LBB0_22:                               ; %Flow98
                                        ;   in Loop: Header=BB0_4 Depth=2
	s_or_b32 exec_lo, exec_lo, s23
.LBB0_23:                               ; %Flow100
                                        ;   in Loop: Header=BB0_4 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s22
                                        ; implicit-def: $vgpr19
.LBB0_24:                               ; %Flow101
                                        ;   in Loop: Header=BB0_4 Depth=2
	s_and_not1_saveexec_b32 s21, s21
	s_cbranch_execz .LBB0_26
; %bb.25:                               ;   in Loop: Header=BB0_4 Depth=2
	v_max_f32_e64 v0, |v18|, |v18|
	v_max_f32_e64 v1, |v19|, |v19|
	v_cmp_gt_i32_e64 s1, 0, v19
	v_cmp_class_f32_e64 s22, v19, 0x204
	v_cmp_class_f32_e64 s23, v18, 0x204
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_max_f32_e32 v2, v1, v0
	v_min_f32_e32 v0, v1, v0
	v_frexp_mant_f32_e32 v3, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_frexp_exp_i32_f32_e32 v4, v0
	v_frexp_mant_f32_e32 v0, v0
	v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v2|
	v_rcp_f32_e32 v1, v3
	v_frexp_exp_i32_f32_e32 v3, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v5, 0, v3
	v_sub_nc_u32_e32 v4, v4, v3
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v0, v0, v1
	v_ldexp_f32 v1, |v18|, v5
	v_ldexp_f32 v0, v0, v4
	v_ldexp_f32 v4, |v19|, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v1, v1, v1
	v_mul_f32_e32 v5, v0, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v1, v4, v4 :: v_dual_fmaak_f32 v4, s10, v5, 0xbc7a590c
	v_sqrt_f32_e32 v1, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmaak_f32 v4, v5, v4, 0x3d29fb3f
	v_fmaak_f32 v4, v5, v4, 0xbd97d4d7
	s_waitcnt_depctr 0xfff
	v_ldexp_f32 v1, v1, v3
	v_fmaak_f32 v3, v5, v4, 0x3dd931b2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v1, 0x7f800000, v1, vcc_lo
	v_fmaak_f32 v2, v5, v3, 0xbe1160e6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_f32_e32 vcc_lo, 0x800000, v1
	v_fmaak_f32 v2, v5, v2, 0x3e4cb8bf
	v_cndmask_b32_e64 v3, 1.0, 0x4f800000, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmaak_f32 v2, v5, v2, 0xbeaaaa62
	v_mul_f32_e32 v1, v1, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v2, v5, v2
	v_log_f32_e32 v1, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v0, v0, v2
	v_sub_f32_e32 v3, 0x3fc90fdb, v0
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v2, 0x3f317217, v1
	v_cndmask_b32_e64 v0, v0, v3, s0
	v_cndmask_b32_e64 v3, 0, 0x40490fdb, s1
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v4, 0x3f317217, v1, -v2
	v_cmp_gt_f32_e64 s1, 0, v19
	v_fmac_f32_e32 v4, 0x3377d1cf, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_add_f32_e32 v2, v2, v4
	v_cndmask_b32_e64 v4, 0, 0x41b17218, vcc_lo
	v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v1|
	v_cndmask_b32_e32 v1, v1, v2, vcc_lo
	v_cmp_eq_f32_e32 vcc_lo, 0, v18
	v_sub_f32_e32 v5, 0x40490fdb, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v2, v1, v4
	v_cndmask_b32_e64 v0, v0, v5, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v0, v0, v3, vcc_lo
	v_cndmask_b32_e64 v3, 0x3f490fdb, v15, s1
	s_and_b32 vcc_lo, s22, s23
	v_cndmask_b32_e32 v0, v0, v3, vcc_lo
.LBB0_26:                               ; %Flow102
                                        ;   in Loop: Header=BB0_4 Depth=2
	s_or_b32 exec_lo, exec_lo, s21
                                        ; implicit-def: $vgpr1
                                        ; implicit-def: $vgpr19
.LBB0_27:                               ; %Flow105
                                        ;   in Loop: Header=BB0_4 Depth=2
	s_and_not1_saveexec_b32 s21, s2
	s_cbranch_execz .LBB0_33
; %bb.28:                               ;   in Loop: Header=BB0_4 Depth=2
                                        ; implicit-def: $vgpr2
                                        ; implicit-def: $vgpr0
	s_mov_b32 s1, exec_lo
	v_cmpx_ngt_f32_e32 0x1fec1e4a, v1
	s_xor_b32 s22, exec_lo, s1
	s_cbranch_execz .LBB0_30
; %bb.29:                               ;   in Loop: Header=BB0_4 Depth=2
	v_mul_f32_e32 v0, v1, v1
	v_cmp_gt_f32_e64 s1, 0, v19
	v_cmp_class_f32_e64 s23, v19, 0x204
	v_cmp_class_f32_e64 s24, v18, 0x204
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v1, 1.0, v0
	v_frexp_mant_f32_e32 v2, v1
	v_frexp_exp_i32_f32_e32 v3, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_f32_e32 vcc_lo, 0x3f2aaaab, v2
	v_subrev_co_ci_u32_e32 v2, vcc_lo, 0, v3, vcc_lo
	v_add_f32_e32 v3, -1.0, v1
	v_cmp_gt_i32_e32 vcc_lo, 0, v19
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_sub_nc_u32_e32 v4, 0, v2
	v_cvt_f32_i32_e32 v2, v2
	v_sub_f32_e32 v5, v3, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_ldexp_f32 v1, v1, v4
	v_sub_f32_e32 v3, v0, v3
	v_add_f32_e32 v5, 1.0, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v6, 1.0, v1
	v_add_f32_e32 v3, v3, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f32_e32 v5, -1.0, v6
	v_cmp_gt_f32_e64 s2, 0x33800000, v0
	v_ldexp_f32 v3, v3, v4
	v_add_f32_e32 v4, -1.0, v1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v5, v1, v5
	v_add_f32_e32 v7, 1.0, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v5, v3, v5
	v_sub_f32_e32 v1, v1, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v7, v6, v5
	v_add_f32_e32 v1, v3, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v3, v7
	v_sub_f32_e32 v6, v6, v7
	v_dual_add_f32 v8, v4, v1 :: v_dual_add_f32 v5, v5, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v4, v4, v8
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v9, v8, v3
	v_dual_add_f32 v1, v1, v4 :: v_dual_mul_f32 v10, v7, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v6, v9, v7, -v10
	v_fmac_f32_e32 v6, v9, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v11, v10, v6
	v_sub_f32_e32 v20, v8, v11
	v_sub_f32_e32 v4, v11, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v8, v8, v20
	v_sub_f32_e32 v4, v4, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v8, v8, v11
	v_add_f32_e32 v1, v1, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v1, v4, v1
	v_add_f32_e32 v4, v20, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v6, v3, v4
	v_dual_sub_f32 v11, v20, v4 :: v_dual_mul_f32 v8, v7, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v7, v6, v7, -v8
	v_fmac_f32_e32 v7, v6, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v5, v8, v7
	v_sub_f32_e32 v10, v4, v5
	v_sub_f32_e32 v8, v5, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v1, v1, v11 :: v_dual_sub_f32 v4, v4, v10
	v_sub_f32_e32 v4, v4, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f32_e32 v1, v1, v4
	v_dual_add_f32 v4, v9, v6 :: v_dual_sub_f32 v5, v8, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v1, v5, v1
	v_sub_f32_e32 v5, v4, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v1, v10, v1
	v_sub_f32_e32 v5, v6, v5
	v_max_f32_e64 v6, |v19|, |v19|
                                        ; implicit-def: $vgpr19
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v1, v3, v1
	v_max_f32_e64 v3, |v18|, |v18|
	v_dual_add_f32 v1, v5, v1 :: v_dual_max_f32 v8, v6, v3
	v_min_f32_e32 v3, v6, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v5, v4, v1
	v_frexp_mant_f32_e32 v10, v8
	v_frexp_exp_i32_f32_e32 v6, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v7, v5, v5
	v_ldexp_f32 v11, v5, 1
	v_dual_sub_f32 v4, v5, v4 :: v_dual_fmaak_f32 v9, s7, v7, 0x3ecc95a3
	v_mul_f32_e32 v8, v5, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v1, v1, v4
	v_fmaak_f32 v7, v7, v9, 0x3f2aaada
	v_rcp_f32_e32 v9, v10
	v_frexp_exp_i32_f32_e32 v10, v3
	v_frexp_mant_f32_e32 v3, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_mul_f32 v7, v8, v7 :: v_dual_mul_f32 v8, 0x3f317218, v2
	v_sub_nc_u32_e32 v6, v10, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_f32_e32 v5, v11, v7
	s_waitcnt_depctr 0xfff
	v_dual_mul_f32 v3, v3, v9 :: v_dual_sub_f32 v4, v5, v11
	v_ldexp_f32 v3, v3, v6
	v_fma_f32 v6, 0x3f317218, v2, -v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v4, v7, v4
	v_dual_mul_f32 v7, v3, v3 :: v_dual_fmac_f32 v6, 0xb102e308, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmaak_f32 v2, s10, v7, 0xbc7a590c
	v_fmaak_f32 v2, v7, v2, 0x3d29fb3f
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmaak_f32 v2, v7, v2, 0xbd97d4d7
	v_fmaak_f32 v2, v7, v2, 0x3dd931b2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmaak_f32 v2, v7, v2, 0xbe1160e6
	v_ldexp_f32 v1, v1, 1
	v_dual_add_f32 v1, v1, v4 :: v_dual_add_f32 v4, v8, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v9, v5, v1 :: v_dual_sub_f32 v8, v4, v8
	v_add_f32_e32 v10, v4, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v6, v6, v8
	v_sub_f32_e32 v11, v10, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v20, v10, v11
	v_dual_sub_f32 v4, v4, v20 :: v_dual_sub_f32 v5, v9, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v1, v1, v5
	v_dual_sub_f32 v5, v9, v11 :: v_dual_add_f32 v8, v6, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f32_e32 v4, v5, v4
	v_fmaak_f32 v2, v7, v2, 0x3e4cb8bf
	v_sub_f32_e32 v5, v8, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v4, v8, v4
	v_fmaak_f32 v2, v7, v2, 0xbeaaaa62
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v2, v7, v2
	v_fmac_f32_e32 v3, v3, v2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v7, v8, v5 :: v_dual_add_f32 v8, v10, v4
	v_dual_sub_f32 v2, v6, v7 :: v_dual_sub_f32 v1, v1, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v5, v8, v10
	v_dual_add_f32 v1, v1, v2 :: v_dual_sub_f32 v2, v4, v5
	v_sub_f32_e32 v6, 0x3fc90fdb, v3
	v_cndmask_b32_e64 v4, 0, 0x40490fdb, vcc_lo
	v_cmp_eq_f32_e32 vcc_lo, 0x7f800000, v0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f32_e32 v1, v1, v2
	v_cndmask_b32_e64 v3, v3, v6, s0
	s_or_b32 vcc_lo, s2, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v1, v8, v1 :: v_dual_sub_f32 v2, 0x40490fdb, v3
	v_cndmask_b32_e32 v0, v1, v0, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v2, v3, v2, s1
	v_cmp_eq_f32_e32 vcc_lo, 0, v18
	v_cndmask_b32_e64 v3, 0x3f490fdb, v15, s1
	v_cndmask_b32_e32 v1, v2, v4, vcc_lo
	s_and_b32 vcc_lo, s23, s24
	v_mul_f32_e32 v2, 0.5, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_cndmask_b32_e32 v0, v1, v3, vcc_lo
                                        ; implicit-def: $vgpr1
.LBB0_30:                               ; %Flow103
                                        ;   in Loop: Header=BB0_4 Depth=2
	s_and_not1_saveexec_b32 s2, s22
	s_cbranch_execz .LBB0_32
; %bb.31:                               ;   in Loop: Header=BB0_4 Depth=2
	v_max_f32_e64 v0, |v18|, |v18|
	v_max_f32_e64 v2, |v19|, |v19|
	v_cmp_gt_i32_e32 vcc_lo, 0, v19
	v_cmp_eq_f32_e64 s1, 0, v18
	v_cmp_class_f32_e64 s22, v19, 0x204
	v_cmp_class_f32_e64 s23, v18, 0x204
	v_max_f32_e32 v3, v2, v0
	v_min_f32_e32 v0, v2, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_frexp_mant_f32_e32 v4, v3
	v_rcp_f32_e32 v2, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_frexp_exp_i32_f32_e32 v4, v0
	v_frexp_mant_f32_e32 v0, v0
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v0, v0, v2
	v_frexp_exp_i32_f32_e32 v3, v3
	v_sub_nc_u32_e32 v3, v4, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ldexp_f32 v0, v0, v3
	v_mul_f32_e32 v2, v0, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmaak_f32 v3, s10, v2, 0xbc7a590c
	v_fmaak_f32 v3, v2, v3, 0x3d29fb3f
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmaak_f32 v3, v2, v3, 0xbd97d4d7
	v_fmaak_f32 v3, v2, v3, 0x3dd931b2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmaak_f32 v3, v2, v3, 0xbe1160e6
	v_fmaak_f32 v3, v2, v3, 0x3e4cb8bf
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmaak_f32 v3, v2, v3, 0xbeaaaa62
	v_mul_f32_e32 v2, v2, v3
	v_cndmask_b32_e64 v3, 0, 0x40490fdb, vcc_lo
	v_cmp_gt_f32_e32 vcc_lo, 0, v19
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v0, v0, v2
	v_sub_f32_e32 v2, 0x3fc90fdb, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v0, v0, v2, s0
	v_sub_f32_e32 v2, 0x40490fdb, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v0, v0, v2, vcc_lo
	v_mul_f32_e32 v2, 0.5, v1
	v_cndmask_b32_e64 v0, v0, v3, s1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v2, v1, v2 :: v_dual_cndmask_b32 v3, 0x3f490fdb, v15
	s_and_b32 vcc_lo, s22, s23
	v_cndmask_b32_e32 v0, v0, v3, vcc_lo
.LBB0_32:                               ; %Flow104
                                        ;   in Loop: Header=BB0_4 Depth=2
	s_or_b32 exec_lo, exec_lo, s2
.LBB0_33:                               ; %Flow106
                                        ;   in Loop: Header=BB0_4 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s21
                                        ; implicit-def: $vgpr19
.LBB0_34:                               ; %Flow107
                                        ;   in Loop: Header=BB0_4 Depth=2
	s_and_not1_saveexec_b32 s2, s20
	s_cbranch_execz .LBB0_36
; %bb.35:                               ;   in Loop: Header=BB0_4 Depth=2
	v_div_scale_f32 v0, null, 0x402df854, 0x402df854, v19
	v_div_scale_f32 v1, null, 0x402df854, 0x402df854, v18
	v_div_scale_f32 v6, vcc_lo, v19, 0x402df854, v19
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rcp_f32_e32 v2, v0
	v_rcp_f32_e32 v3, v1
	v_cmp_class_f32_e64 s20, v18, 0x204
	s_waitcnt_depctr 0xfff
	v_fma_f32 v4, -v0, v2, 1.0
	v_fma_f32 v5, -v1, v3, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_fmac_f32 v2, v4, v2 :: v_dual_fmac_f32 v3, v5, v3
	v_div_scale_f32 v4, s1, v18, 0x402df854, v18
	v_mul_f32_e32 v5, v6, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v8, -v0, v5, v6
	v_fmac_f32_e32 v5, v8, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v0, -v0, v5, v6
	v_div_fmas_f32 v0, v0, v2, v5
	v_max_f32_e64 v2, |v18|, |v18|
	v_mul_f32_e32 v7, v4, v3
	s_mov_b32 vcc_lo, s1
	v_cmp_class_f32_e64 s1, v19, 0x204
	v_div_fixup_f32 v0, v0, 0x402df854, v19
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v9, -v1, v7, v4
	v_fmac_f32_e32 v7, v9, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v1, -v1, v7, v4
	v_div_fmas_f32 v1, v1, v3, v7
	v_max_f32_e64 v3, |v19|, |v19|
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fixup_f32 v1, v1, 0x402df854, v18
	v_max_f32_e32 v4, v3, v2
	v_min_f32_e32 v2, v3, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_max_f32_e64 v5, |v0|, |v1|
	v_frexp_mant_f32_e32 v6, v4
	v_frexp_exp_i32_f32_e32 v4, v4
	s_delay_alu instid0(VALU_DEP_4)
	v_frexp_exp_i32_f32_e32 v8, v2
	v_frexp_mant_f32_e32 v2, v2
	v_frexp_exp_i32_f32_e32 v7, v5
	v_rcp_f32_e32 v3, v6
	v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v5|
	v_sub_nc_u32_e32 v4, v8, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v6, 0, v7
	v_ldexp_f32 v1, |v1|, v6
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v2, v2, v3
	v_ldexp_f32 v0, |v0|, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_ldexp_f32 v2, v2, v4
	v_mul_f32_e32 v1, v1, v1
	v_dual_fmac_f32 v1, v0, v0 :: v_dual_mul_f32 v0, v2, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_sqrt_f32_e32 v1, v1
	s_waitcnt_depctr 0xfff
	v_ldexp_f32 v1, v1, v7
	v_cndmask_b32_e32 v1, 0x7f800000, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_cmp_gt_f32_e32 vcc_lo, 0x800000, v1
	v_cndmask_b32_e64 v4, 1.0, 0x4f800000, vcc_lo
	v_cndmask_b32_e64 v5, 0, 0x41b17218, vcc_lo
	v_fmaak_f32 v3, s10, v0, 0xbc7a590c
	v_mul_f32_e32 v1, v1, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmaak_f32 v3, v0, v3, 0x3d29fb3f
	v_log_f32_e32 v1, v1
	s_waitcnt_depctr 0xfff
	v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v1|
	v_fmaak_f32 v3, v0, v3, 0xbd97d4d7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmaak_f32 v3, v0, v3, 0x3dd931b2
	v_fmaak_f32 v3, v0, v3, 0xbe1160e6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmaak_f32 v3, v0, v3, 0x3e4cb8bf
	v_fmaak_f32 v3, v0, v3, 0xbeaaaa62
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v0, v0, v3 :: v_dual_mul_f32 v3, 0x3f317217, v1
	v_fmac_f32_e32 v2, v2, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v0, 0x3f317217, v1, -v3
	v_sub_f32_e32 v4, 0x3fc90fdb, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v2, v2, v4, s0
	v_cmp_gt_i32_e64 s0, 0, v19
	v_cndmask_b32_e64 v4, 0, 0x40490fdb, s0
	v_fmac_f32_e32 v0, 0x3377d1cf, v1
	v_cmp_gt_f32_e64 s0, 0, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v0, v3, v0 :: v_dual_sub_f32 v3, 0x40490fdb, v2
	v_cndmask_b32_e32 v0, v1, v0, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v1, v2, v3, s0
	v_cmp_eq_f32_e32 vcc_lo, 0, v18
	v_cndmask_b32_e64 v3, 0x3f490fdb, v15, s0
	v_dual_sub_f32 v0, v0, v5 :: v_dual_cndmask_b32 v1, v1, v4
	s_and_b32 vcc_lo, s1, s20
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v2, 1.0, v0
	v_cndmask_b32_e32 v0, v1, v3, vcc_lo
.LBB0_36:                               ; %Flow108
                                        ;   in Loop: Header=BB0_4 Depth=2
	s_or_b32 exec_lo, exec_lo, s2
                                        ; implicit-def: $vgpr19
.LBB0_37:                               ; %Flow110
                                        ;   in Loop: Header=BB0_4 Depth=2
	s_and_not1_saveexec_b32 s0, s19
	s_cbranch_execz .LBB0_43
; %bb.38:                               ;   in Loop: Header=BB0_4 Depth=2
	v_cmp_ngt_f32_e64 s1, 0x20000000, |v19|
	v_cmp_ngt_f32_e64 s2, 0x20000000, |v18|
                                        ; implicit-def: $vgpr0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s1, s1, s2
	s_and_saveexec_b32 s2, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s1, exec_lo, s2
; %bb.39:                               ; %._crit_edge.i.i.i.i
                                        ;   in Loop: Header=BB0_4 Depth=2
	v_mul_f32_e32 v0, v18, v18
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v0, v19, v19
                                        ; implicit-def: $vgpr19
; %bb.40:                               ; %Flow109
                                        ;   in Loop: Header=BB0_4 Depth=2
	s_and_not1_saveexec_b32 s1, s1
; %bb.41:                               ;   in Loop: Header=BB0_4 Depth=2
	v_dual_mul_f32 v0, 4.0, v18 :: v_dual_mul_f32 v1, 4.0, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v0, v0, v0
	v_fmac_f32_e32 v0, v1, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_mul_f32_e32 v0, 0x3d800000, v0
; %bb.42:                               ; %_ZN6thrust4normIfEET_RKNS_7complexIS1_EE.exit.i.i.i
                                        ;   in Loop: Header=BB0_4 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
	v_cndmask_b32_e64 v1, 1.0, 0x4f800000, vcc_lo
	v_mul_f32_e32 v0, v0, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_log_f32_e32 v0, v0
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v1, 0x3f317217, v0
	v_fma_f32 v2, 0x3f317217, v0, -v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v2, 0x3377d1cf, v0
	v_add_f32_e32 v1, v1, v2
	v_cndmask_b32_e64 v2, 0, 0x41b17218, vcc_lo
	v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v0|
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v0, v0, v1, vcc_lo
	v_sub_f32_e32 v2, v0, v2
	v_mov_b32_e32 v0, 0x7fc00000
.LBB0_43:                               ; %Flow111
                                        ;   in Loop: Header=BB0_4 Depth=2
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_bfi_b32 v0, 0x7fffffff, v0, v18
                                        ; implicit-def: $vgpr3
	s_mov_b32 s0, exec_lo
	v_add_f32_e32 v2, v2, v2
	v_add_f32_e32 v0, v0, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v1, 0x7fffffff, v0
	v_cmpx_ne_u32_e32 0, v1
	s_xor_b32 s2, exec_lo, s0
	s_cbranch_execz .LBB0_85
; %bb.44:                               ;   in Loop: Header=BB0_4 Depth=2
	v_and_b32_e32 v4, 0x7fffffff, v2
                                        ; implicit-def: $vgpr3
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_ne_u32_e32 0, v4
	s_xor_b32 s19, exec_lo, s0
	s_cbranch_execz .LBB0_74
; %bb.45:                               ;   in Loop: Header=BB0_4 Depth=2
                                        ; implicit-def: $vgpr3
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 0x7f800000, v1
	s_xor_b32 s20, exec_lo, s0
	s_cbranch_execz .LBB0_67
; %bb.46:                               ;   in Loop: Header=BB0_4 Depth=2
	v_add_nc_u32_e32 v3, 0xbd4e8de8, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_lt_u32_e32 vcc_lo, 0x8e8e5c, v3
                                        ; implicit-def: $vgpr3
	s_and_saveexec_b32 s0, vcc_lo
	s_xor_b32 s21, exec_lo, s0
	s_cbranch_execz .LBB0_56
; %bb.47:                               ;   in Loop: Header=BB0_4 Depth=2
	v_cmp_ngt_f32_e64 s22, 0x48000000, |v0|
                                        ; implicit-def: $vgpr4
                                        ; implicit-def: $vgpr3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_saveexec_b32 s0, s22
	s_xor_b32 s23, exec_lo, s0
	s_cbranch_execz .LBB0_49
; %bb.48:                               ;   in Loop: Header=BB0_4 Depth=2
	v_lshrrev_b32_e32 v8, 23, v1
	v_and_or_b32 v18, v1, s11, 0x800000
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v9, 0xffffff88, v8
	v_mad_u64_u32 v[3:4], null, 0xfe5163ab, v18, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_lt_u32_e32 vcc_lo, 63, v9
	v_cndmask_b32_e64 v10, 0, 0xffffffc0, vcc_lo
	v_dual_mov_b32 v11, v4 :: v_dual_add_nc_u32 v10, v10, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[4:5], null, 0x3c439041, v18, v[11:12]
	v_cmp_lt_u32_e64 s0, 31, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v11, v5
	v_cndmask_b32_e64 v19, 0, 0xffffffe0, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[5:6], null, 0xdb629599, v18, v[11:12]
	v_add_nc_u32_e32 v19, v19, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_lt_u32_e64 s1, 31, v19
	v_mov_b32_e32 v11, v6
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v3, v5, v3, vcc_lo
	v_mad_u64_u32 v[6:7], null, 0xf534ddc0, v18, v[11:12]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v11, v7 :: v_dual_cndmask_b32 v4, v6, v4
	v_mad_u64_u32 v[7:8], null, 0xfc2757d1, v18, v[11:12]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v3, v4, v3, s0
	v_mov_b32_e32 v11, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[8:9], null, 0x4e441529, v18, v[11:12]
	v_mov_b32_e32 v11, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[9:10], null, 0xa2f9836e, v18, v[11:12]
	v_cndmask_b32_e64 v11, 0, 0xffffffe0, s1
	v_dual_cndmask_b32 v18, v8, v6 :: v_dual_cndmask_b32 v9, v9, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v8, v10, v8 :: v_dual_cndmask_b32 v7, v7, v5
	v_add_nc_u32_e32 v10, v11, v19
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v6, v9, v18, s0
	v_cndmask_b32_e64 v8, v8, v9, s0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v9, v18, v7, s0
	v_sub_nc_u32_e32 v11, 32, v10
	v_cndmask_b32_e64 v7, v7, v4, s0
	v_cmp_eq_u32_e32 vcc_lo, 0, v10
	v_cndmask_b32_e64 v8, v8, v6, s1
	v_cndmask_b32_e64 v6, v6, v9, s1
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v9, v9, v7, s1
	v_cndmask_b32_e64 v3, v7, v3, s1
	v_alignbit_b32 v18, v8, v6, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v5, v6, v9, v11
	v_alignbit_b32 v10, v9, v3, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v8, v18, v8, vcc_lo
	v_cndmask_b32_e32 v4, v5, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_bfe_u32 v5, v8, 29, 1
	v_cndmask_b32_e32 v9, v10, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v6, v8, v4, 30
	v_sub_nc_u32_e32 v7, 0, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_alignbit_b32 v4, v4, v9, 30
	v_alignbit_b32 v3, v9, v3, 30
	v_xor_b32_e32 v6, v6, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v4, v4, v7
	v_xor_b32_e32 v3, v3, v7
	v_lshrrev_b32_e32 v7, 29, v8
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_clz_i32_u32_e32 v10, v6
	v_lshlrev_b32_e32 v7, 31, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_min_u32_e32 v10, 32, v10
	v_or_b32_e32 v11, 0.5, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v9, 31, v10
	v_lshlrev_b32_e32 v18, 23, v10
	v_alignbit_b32 v6, v6, v4, v9
	v_alignbit_b32 v3, v4, v3, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v11, v11, v18
	v_alignbit_b32 v4, v6, v3, 9
	v_lshrrev_b32_e32 v6, 9, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_clz_i32_u32_e32 v9, v4
	v_min_u32_e32 v9, 32, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v19, 31, v9
	v_alignbit_b32 v3, v4, v3, v19
	v_or_b32_e32 v4, v6, v11
	v_add_lshl_u32 v6, v9, v10, 23
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshrrev_b32_e32 v3, 9, v3
	v_mul_f32_e32 v9, 0x3fc90fda, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v3, v3, v6
	v_fma_f32 v6, 0x3fc90fda, v4, -v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v3, 0x33000000, v3
	v_fmac_f32_e32 v6, 0x33a22168, v4
	v_lshrrev_b32_e32 v4, 30, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or_b32_e32 v3, v3, v7
	v_add_nc_u32_e32 v4, v5, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v6, 0x3fc90fda, v3
	v_add_f32_e32 v3, v9, v6
.LBB0_49:                               ; %Flow83
                                        ;   in Loop: Header=BB0_4 Depth=2
	s_and_not1_saveexec_b32 s0, s23
; %bb.50:                               ;   in Loop: Header=BB0_4 Depth=2
	v_mul_f32_e64 v3, 0x3f22f983, |v0|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f32_e32 v4, v3
	v_fma_f32 v3, 0xbfc90fda, v4, |v0|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v3, 0xb3a22168, v4
	v_fmac_f32_e32 v3, 0xa7c234c4, v4
	v_cvt_i32_f32_e32 v4, v4
; %bb.51:                               ; %_ZL3cosf.exit21.i.i.i
                                        ;   in Loop: Header=BB0_4 Depth=2
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $vgpr6
                                        ; implicit-def: $vgpr5
	s_and_saveexec_b32 s0, s22
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s22, exec_lo, s0
	s_cbranch_execz .LBB0_53
; %bb.52:                               ;   in Loop: Header=BB0_4 Depth=2
	v_and_or_b32 v21, v1, s11, 0x800000
	v_lshrrev_b32_e32 v10, 23, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[5:6], null, 0xfe5163ab, v21, 0
	v_add_nc_u32_e32 v18, 0xffffff88, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_lt_u32_e32 vcc_lo, 63, v18
	v_mov_b32_e32 v11, v6
	v_cndmask_b32_e64 v19, 0, 0xffffffc0, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[6:7], null, 0x3c439041, v21, v[11:12]
	v_mov_b32_e32 v11, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[7:8], null, 0xdb629599, v21, v[11:12]
	v_mov_b32_e32 v11, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v5, v7, v5, vcc_lo
	v_mad_u64_u32 v[8:9], null, 0xf534ddc0, v21, v[11:12]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v11, v9 :: v_dual_cndmask_b32 v6, v8, v6
	v_mad_u64_u32 v[9:10], null, 0xfc2757d1, v21, v[11:12]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v11, v10 :: v_dual_add_nc_u32 v10, v19, v18
	v_mad_u64_u32 v[18:19], null, 0x4e441529, v21, v[11:12]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_u32_e64 s0, 31, v10
	v_cndmask_b32_e64 v20, 0, 0xffffffe0, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mov_b32_e32 v11, v19
	v_cndmask_b32_e64 v5, v6, v5, s0
	v_add_nc_u32_e32 v10, v20, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[19:20], null, 0xa2f9836e, v21, v[11:12]
	v_cmp_lt_u32_e64 s1, 31, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v19, v19, v9, vcc_lo
	v_cndmask_b32_e64 v11, 0, 0xffffffe0, s1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v21, v18, v8 :: v_dual_cndmask_b32 v18, v20, v18
	v_dual_cndmask_b32 v9, v9, v7 :: v_dual_add_nc_u32 v10, v11, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v8, v19, v21, s0
	v_cndmask_b32_e64 v11, v18, v19, s0
	s_delay_alu instid0(VALU_DEP_3)
	v_cndmask_b32_e64 v18, v21, v9, s0
	v_cndmask_b32_e64 v9, v9, v6, s0
	v_sub_nc_u32_e32 v19, 32, v10
	v_cmp_eq_u32_e32 vcc_lo, 0, v10
	v_cndmask_b32_e64 v11, v11, v8, s1
	v_cndmask_b32_e64 v8, v8, v18, s1
	v_cndmask_b32_e64 v18, v18, v9, s1
	v_cndmask_b32_e64 v5, v9, v5, s1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v20, v11, v8, v19
	v_alignbit_b32 v7, v8, v18, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v10, v20, v11, vcc_lo
	v_cndmask_b32_e32 v6, v7, v8, vcc_lo
	v_alignbit_b32 v11, v18, v5, v19
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_bfe_u32 v7, v10, 29, 1
	v_alignbit_b32 v8, v10, v6, 30
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v11, v11, v18, vcc_lo
	v_sub_nc_u32_e32 v9, 0, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_alignbit_b32 v6, v6, v11, 30
	v_alignbit_b32 v5, v11, v5, 30
	v_xor_b32_e32 v8, v8, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v6, v6, v9
	v_xor_b32_e32 v5, v5, v9
	v_lshrrev_b32_e32 v9, 29, v10
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_clz_i32_u32_e32 v18, v8
	v_lshlrev_b32_e32 v9, 31, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_min_u32_e32 v18, 32, v18
	v_or_b32_e32 v19, 0.5, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v11, 31, v18
	v_lshlrev_b32_e32 v20, 23, v18
	v_alignbit_b32 v8, v8, v6, v11
	v_alignbit_b32 v5, v6, v5, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v19, v19, v20
	v_alignbit_b32 v6, v8, v5, 9
	v_lshrrev_b32_e32 v8, 9, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_clz_i32_u32_e32 v11, v6
	v_min_u32_e32 v11, 32, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v21, 31, v11
	v_alignbit_b32 v5, v6, v5, v21
	v_or_b32_e32 v6, v8, v19
	v_add_lshl_u32 v8, v11, v18, 23
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshrrev_b32_e32 v5, 9, v5
	v_mul_f32_e32 v11, 0x3fc90fda, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v5, v5, v8
	v_fma_f32 v8, 0x3fc90fda, v6, -v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v5, 0x33000000, v5
	v_fmac_f32_e32 v8, 0x33a22168, v6
	v_lshrrev_b32_e32 v6, 30, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or_b32_e32 v5, v5, v9
	v_add_nc_u32_e32 v6, v7, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v8, 0x3fc90fda, v5
	v_add_f32_e32 v5, v11, v8
.LBB0_53:                               ; %Flow
                                        ;   in Loop: Header=BB0_4 Depth=2
	s_and_not1_saveexec_b32 s0, s22
; %bb.54:                               ;   in Loop: Header=BB0_4 Depth=2
	v_mul_f32_e64 v5, 0x3f22f983, |v0|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f32_e32 v6, v5
	v_fma_f32 v5, 0xbfc90fda, v6, |v0|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v5, 0xb3a22168, v6
	v_fmac_f32_e32 v5, 0xa7c234c4, v6
	v_cvt_i32_f32_e32 v6, v6
; %bb.55:                               ; %_ZL3sinf.exit29.i.i.i
                                        ;   in Loop: Header=BB0_4 Depth=2
	s_or_b32 exec_lo, exec_lo, s0
	v_dual_mul_f32 v7, 0x3fb8aa3b, v2 :: v_dual_mul_f32 v8, v3, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_mul_f32 v18, v5, v5 :: v_dual_and_b32 v9, 1, v4
	v_and_b32_e32 v19, 1, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_rndne_f32_e32 v10, v7
	v_fmaak_f32 v20, s13, v8, 0x3c0881c4
	v_fma_f32 v11, 0x3fb8aa3b, v2, -v7
	v_lshlrev_b32_e32 v4, 30, v4
	v_dual_fmaak_f32 v21, s14, v8, 0xbab64f3b :: v_dual_lshlrev_b32 v6, 30, v6
	v_sub_f32_e32 v7, v7, v10
	s_delay_alu instid0(VALU_DEP_4)
	v_fmac_f32_e32 v11, 0x32a5705f, v2
	v_fmaak_f32 v22, s13, v18, 0x3c0881c4
	v_fmaak_f32 v23, s14, v18, 0xbab64f3b
	v_cmp_eq_u32_e32 vcc_lo, 0, v9
	v_cvt_i32_f32_e32 v10, v10
	v_add_f32_e32 v7, v7, v11
	v_fmaak_f32 v11, v8, v20, 0xbe2aaa9d
	v_and_or_b32 v1, 0x80000000, v6, v1
	v_cmp_nlt_f32_e64 s0, 0x42b17218, v2
	v_and_b32_e32 v4, 0x80000000, v4
	v_exp_f32_e32 v7, v7
	v_mul_f32_e32 v11, v8, v11
	v_fmaak_f32 v20, v8, v21, 0x3d2aabf7
	v_fmaak_f32 v21, v18, v22, 0xbe2aaa9d
	s_delay_alu instid0(VALU_DEP_1)
	v_mul_f32_e32 v21, v18, v21
	v_fmaak_f32 v22, v18, v23, 0x3d2aabf7
	s_waitcnt_depctr 0xfff
	v_ldexp_f32 v7, v7, v10
	v_dual_fmac_f32 v5, v5, v21 :: v_dual_fmaak_f32 v22, v18, v22, 0xbf000004
	v_fmac_f32_e32 v3, v3, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f32 v11, v18, v22, 1.0
	v_fmaak_f32 v20, v8, v20, 0xbf000004
	v_fma_f32 v8, v8, v20, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v3, -v3, v8, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 0, v19
	v_xor_b32_e32 v3, v4, v3
	v_cndmask_b32_e32 v5, v11, v5, vcc_lo
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v2
	v_cndmask_b32_e32 v6, 0, v7, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v0, 0x1f8
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor3_b32 v0, v1, v5, v0
	v_cndmask_b32_e64 v1, 0x7f800000, v6, s0
	v_cndmask_b32_e32 v2, 0x7fc00000, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_cndmask_b32 v0, 0x7fc00000, v0 :: v_dual_mul_f32 v3, v1, v2
	v_mul_f32_e32 v0, v1, v0
                                        ; implicit-def: $vgpr2
                                        ; implicit-def: $vgpr1
.LBB0_56:                               ; %Flow86
                                        ;   in Loop: Header=BB0_4 Depth=2
	s_and_not1_saveexec_b32 s21, s21
	s_cbranch_execz .LBB0_66
; %bb.57:                               ;   in Loop: Header=BB0_4 Depth=2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_ngt_f32_e64 s22, 0x48000000, |v0|
                                        ; implicit-def: $vgpr4
                                        ; implicit-def: $vgpr3
	s_and_saveexec_b32 s0, s22
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s23, exec_lo, s0
	s_cbranch_execz .LBB0_59
; %bb.58:                               ;   in Loop: Header=BB0_4 Depth=2
	v_lshrrev_b32_e32 v8, 23, v1
	v_and_or_b32 v18, v1, s11, 0x800000
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v9, 0xffffff88, v8
	v_mad_u64_u32 v[3:4], null, 0xfe5163ab, v18, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_lt_u32_e32 vcc_lo, 63, v9
	v_cndmask_b32_e64 v10, 0, 0xffffffc0, vcc_lo
	v_dual_mov_b32 v11, v4 :: v_dual_add_nc_u32 v10, v10, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[4:5], null, 0x3c439041, v18, v[11:12]
	v_cmp_lt_u32_e64 s0, 31, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v11, v5
	v_cndmask_b32_e64 v19, 0, 0xffffffe0, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[5:6], null, 0xdb629599, v18, v[11:12]
	v_add_nc_u32_e32 v19, v19, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_lt_u32_e64 s1, 31, v19
	v_mov_b32_e32 v11, v6
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v3, v5, v3, vcc_lo
	v_mad_u64_u32 v[6:7], null, 0xf534ddc0, v18, v[11:12]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v11, v7 :: v_dual_cndmask_b32 v4, v6, v4
	v_mad_u64_u32 v[7:8], null, 0xfc2757d1, v18, v[11:12]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v3, v4, v3, s0
	v_mov_b32_e32 v11, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[8:9], null, 0x4e441529, v18, v[11:12]
	v_mov_b32_e32 v11, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[9:10], null, 0xa2f9836e, v18, v[11:12]
	v_cndmask_b32_e64 v11, 0, 0xffffffe0, s1
	v_dual_cndmask_b32 v18, v8, v6 :: v_dual_cndmask_b32 v9, v9, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v8, v10, v8 :: v_dual_cndmask_b32 v7, v7, v5
	v_add_nc_u32_e32 v10, v11, v19
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v6, v9, v18, s0
	v_cndmask_b32_e64 v8, v8, v9, s0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v9, v18, v7, s0
	v_sub_nc_u32_e32 v11, 32, v10
	v_cndmask_b32_e64 v7, v7, v4, s0
	v_cmp_eq_u32_e32 vcc_lo, 0, v10
	v_cndmask_b32_e64 v8, v8, v6, s1
	v_cndmask_b32_e64 v6, v6, v9, s1
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v9, v9, v7, s1
	v_cndmask_b32_e64 v3, v7, v3, s1
	v_alignbit_b32 v18, v8, v6, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v5, v6, v9, v11
	v_alignbit_b32 v10, v9, v3, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v8, v18, v8, vcc_lo
	v_cndmask_b32_e32 v4, v5, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_bfe_u32 v5, v8, 29, 1
	v_cndmask_b32_e32 v9, v10, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v6, v8, v4, 30
	v_sub_nc_u32_e32 v7, 0, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_alignbit_b32 v4, v4, v9, 30
	v_alignbit_b32 v3, v9, v3, 30
	v_xor_b32_e32 v6, v6, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v4, v4, v7
	v_xor_b32_e32 v3, v3, v7
	v_lshrrev_b32_e32 v7, 29, v8
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_clz_i32_u32_e32 v10, v6
	v_lshlrev_b32_e32 v7, 31, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_min_u32_e32 v10, 32, v10
	v_or_b32_e32 v11, 0.5, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v9, 31, v10
	v_lshlrev_b32_e32 v18, 23, v10
	v_alignbit_b32 v6, v6, v4, v9
	v_alignbit_b32 v3, v4, v3, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v11, v11, v18
	v_alignbit_b32 v4, v6, v3, 9
	v_lshrrev_b32_e32 v6, 9, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_clz_i32_u32_e32 v9, v4
	v_min_u32_e32 v9, 32, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v19, 31, v9
	v_alignbit_b32 v3, v4, v3, v19
	v_or_b32_e32 v4, v6, v11
	v_add_lshl_u32 v6, v9, v10, 23
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshrrev_b32_e32 v3, 9, v3
	v_mul_f32_e32 v9, 0x3fc90fda, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v3, v3, v6
	v_fma_f32 v6, 0x3fc90fda, v4, -v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v3, 0x33000000, v3
	v_fmac_f32_e32 v6, 0x33a22168, v4
	v_lshrrev_b32_e32 v4, 30, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or_b32_e32 v3, v3, v7
	v_add_nc_u32_e32 v4, v5, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v6, 0x3fc90fda, v3
	v_add_f32_e32 v3, v9, v6
.LBB0_59:                               ; %Flow85
                                        ;   in Loop: Header=BB0_4 Depth=2
	s_and_not1_saveexec_b32 s0, s23
; %bb.60:                               ;   in Loop: Header=BB0_4 Depth=2
	v_mul_f32_e64 v3, 0x3f22f983, |v0|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f32_e32 v4, v3
	v_fma_f32 v3, 0xbfc90fda, v4, |v0|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v3, 0xb3a22168, v4
	v_fmac_f32_e32 v3, 0xa7c234c4, v4
	v_cvt_i32_f32_e32 v4, v4
; %bb.61:                               ; %_ZL3cosf.exit.i.i.i.i
                                        ;   in Loop: Header=BB0_4 Depth=2
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $vgpr6
                                        ; implicit-def: $vgpr5
	s_and_saveexec_b32 s0, s22
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s22, exec_lo, s0
	s_cbranch_execz .LBB0_63
; %bb.62:                               ;   in Loop: Header=BB0_4 Depth=2
	v_and_or_b32 v21, v1, s11, 0x800000
	v_lshrrev_b32_e32 v10, 23, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[5:6], null, 0xfe5163ab, v21, 0
	v_add_nc_u32_e32 v18, 0xffffff88, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_lt_u32_e32 vcc_lo, 63, v18
	v_mov_b32_e32 v11, v6
	v_cndmask_b32_e64 v19, 0, 0xffffffc0, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[6:7], null, 0x3c439041, v21, v[11:12]
	v_mov_b32_e32 v11, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[7:8], null, 0xdb629599, v21, v[11:12]
	v_mov_b32_e32 v11, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v5, v7, v5, vcc_lo
	v_mad_u64_u32 v[8:9], null, 0xf534ddc0, v21, v[11:12]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v11, v9 :: v_dual_cndmask_b32 v6, v8, v6
	v_mad_u64_u32 v[9:10], null, 0xfc2757d1, v21, v[11:12]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v11, v10 :: v_dual_add_nc_u32 v10, v19, v18
	v_mad_u64_u32 v[18:19], null, 0x4e441529, v21, v[11:12]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_u32_e64 s0, 31, v10
	v_cndmask_b32_e64 v20, 0, 0xffffffe0, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mov_b32_e32 v11, v19
	v_cndmask_b32_e64 v5, v6, v5, s0
	v_add_nc_u32_e32 v10, v20, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[19:20], null, 0xa2f9836e, v21, v[11:12]
	v_cmp_lt_u32_e64 s1, 31, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v19, v19, v9, vcc_lo
	v_cndmask_b32_e64 v11, 0, 0xffffffe0, s1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v21, v18, v8 :: v_dual_cndmask_b32 v18, v20, v18
	v_dual_cndmask_b32 v9, v9, v7 :: v_dual_add_nc_u32 v10, v11, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v8, v19, v21, s0
	v_cndmask_b32_e64 v11, v18, v19, s0
	s_delay_alu instid0(VALU_DEP_3)
	v_cndmask_b32_e64 v18, v21, v9, s0
	v_cndmask_b32_e64 v9, v9, v6, s0
	v_sub_nc_u32_e32 v19, 32, v10
	v_cmp_eq_u32_e32 vcc_lo, 0, v10
	v_cndmask_b32_e64 v11, v11, v8, s1
	v_cndmask_b32_e64 v8, v8, v18, s1
	v_cndmask_b32_e64 v18, v18, v9, s1
	v_cndmask_b32_e64 v5, v9, v5, s1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v20, v11, v8, v19
	v_alignbit_b32 v7, v8, v18, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v10, v20, v11, vcc_lo
	v_cndmask_b32_e32 v6, v7, v8, vcc_lo
	v_alignbit_b32 v11, v18, v5, v19
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_bfe_u32 v7, v10, 29, 1
	v_alignbit_b32 v8, v10, v6, 30
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v11, v11, v18, vcc_lo
	v_sub_nc_u32_e32 v9, 0, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_alignbit_b32 v6, v6, v11, 30
	v_alignbit_b32 v5, v11, v5, 30
	v_xor_b32_e32 v8, v8, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v6, v6, v9
	v_xor_b32_e32 v5, v5, v9
	v_lshrrev_b32_e32 v9, 29, v10
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_clz_i32_u32_e32 v18, v8
	v_lshlrev_b32_e32 v9, 31, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_min_u32_e32 v18, 32, v18
	v_or_b32_e32 v19, 0.5, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v11, 31, v18
	v_lshlrev_b32_e32 v20, 23, v18
	v_alignbit_b32 v8, v8, v6, v11
	v_alignbit_b32 v5, v6, v5, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v19, v19, v20
	v_alignbit_b32 v6, v8, v5, 9
	v_lshrrev_b32_e32 v8, 9, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_clz_i32_u32_e32 v11, v6
	v_min_u32_e32 v11, 32, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v21, 31, v11
	v_alignbit_b32 v5, v6, v5, v21
	v_or_b32_e32 v6, v8, v19
	v_add_lshl_u32 v8, v11, v18, 23
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshrrev_b32_e32 v5, 9, v5
	v_mul_f32_e32 v11, 0x3fc90fda, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v5, v5, v8
	v_fma_f32 v8, 0x3fc90fda, v6, -v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v5, 0x33000000, v5
	v_fmac_f32_e32 v8, 0x33a22168, v6
	v_lshrrev_b32_e32 v6, 30, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or_b32_e32 v5, v5, v9
	v_add_nc_u32_e32 v6, v7, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v8, 0x3fc90fda, v5
	v_add_f32_e32 v5, v11, v8
.LBB0_63:                               ; %Flow84
                                        ;   in Loop: Header=BB0_4 Depth=2
	s_and_not1_saveexec_b32 s0, s22
; %bb.64:                               ;   in Loop: Header=BB0_4 Depth=2
	v_mul_f32_e64 v5, 0x3f22f983, |v0|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f32_e32 v6, v5
	v_fma_f32 v5, 0xbfc90fda, v6, |v0|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v5, 0xb3a22168, v6
	v_fmac_f32_e32 v5, 0xa7c234c4, v6
	v_cvt_i32_f32_e32 v6, v6
; %bb.65:                               ; %_ZN6thrust6detail7complex11ldexp_cexpfENS_7complexIfEEi.exit.i.i.i
                                        ;   in Loop: Header=BB0_4 Depth=2
	s_or_b32 exec_lo, exec_lo, s0
	v_add_f32_e32 v2, 0xc322e3bc, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_mul_f32 v10, v3, v3 :: v_dual_mul_f32 v11, v5, v5
	v_mul_f32_e32 v7, 0x3fb8aa3b, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_fmaak_f32 v19, s13, v10, 0x3c0881c4 :: v_dual_fmaak_f32 v20, s13, v11, 0x3c0881c4
	v_fmaak_f32 v18, s14, v10, 0xbab64f3b
	v_fma_f32 v8, 0x3fb8aa3b, v2, -v7
	v_rndne_f32_e32 v9, v7
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmaak_f32 v20, v11, v20, 0xbe2aaa9d
	v_dual_sub_f32 v7, v7, v9 :: v_dual_fmac_f32 v8, 0x32a5705f, v2
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v20, v11, v20
	v_add_f32_e32 v7, v7, v8
	v_cvt_i32_f32_e32 v8, v9
	v_lshlrev_b32_e32 v9, 30, v4
	v_and_b32_e32 v4, 1, v4
	v_fmac_f32_e32 v5, v5, v20
	v_exp_f32_e32 v7, v7
	s_waitcnt_depctr 0xfff
	v_ldexp_f32 v7, v7, v8
	v_and_b32_e32 v8, 1, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v7, 0, v7 :: v_dual_lshlrev_b32 v6, 30, v6
	v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v2
	v_and_or_b32 v1, 0x80000000, v6, v1
	s_delay_alu instid0(VALU_DEP_3)
	v_cndmask_b32_e32 v2, 0x7f800000, v7, vcc_lo
	v_fmaak_f32 v7, s14, v11, 0xbab64f3b
	v_fmaak_f32 v6, v10, v18, 0x3d2aabf7
	v_fmaak_f32 v18, v10, v19, 0xbe2aaa9d
	v_and_b32_e32 v9, 0x80000000, v9
	v_cmp_eq_u32_e32 vcc_lo, 0, v4
	v_fmaak_f32 v7, v11, v7, 0x3d2aabf7
	v_fmaak_f32 v6, v10, v6, 0xbf000004
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_mul_f32 v18, v10, v18 :: v_dual_fmaak_f32 v7, v11, v7, 0xbf000004
	v_fma_f32 v6, v10, v6, 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v3, v3, v18
	v_lshrrev_b32_e32 v19, 23, v2
	v_and_or_b32 v2, 0x7fffff, v2, s15
	v_fma_f32 v7, v11, v7, 1.0
	v_cndmask_b32_e64 v3, -v3, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_subrev_nc_u32_e32 v19, 19, v19
	v_cmp_eq_u32_e32 vcc_lo, 0, v8
	v_xor_b32_e32 v3, v9, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_lshrrev_b16 v10, 15, v19
	v_cndmask_b32_e32 v5, v7, v5, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v0, 0x1f8
	v_add_nc_u16 v4, v19, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor3_b32 v1, v1, v5, v0
	v_ashrrev_i16 v4, 1, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v1, 0x7fc00000, v1, vcc_lo
	v_dual_mul_f32 v1, v1, v2 :: v_dual_cndmask_b32 v0, 0x7fc00000, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_bfe_i32 v3, v4, 0, 16
	v_lshl_add_u32 v4, v3, 23, 1.0
	v_sub_nc_u32_e32 v3, v19, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_mul_f32 v1, v1, v4 :: v_dual_mul_f32 v0, v0, v2
	v_lshl_add_u32 v2, v3, 23, 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v0, v0, v4
	v_mul_f32_e32 v3, v0, v2
	s_delay_alu instid0(VALU_DEP_4)
	v_mul_f32_e32 v0, v1, v2
.LBB0_66:                               ; %Flow87
                                        ;   in Loop: Header=BB0_4 Depth=2
	s_or_b32 exec_lo, exec_lo, s21
                                        ; implicit-def: $vgpr2
                                        ; implicit-def: $vgpr4
.LBB0_67:                               ; %Flow90
                                        ;   in Loop: Header=BB0_4 Depth=2
	s_and_not1_saveexec_b32 s0, s20
	s_cbranch_execz .LBB0_73
; %bb.68:                               ;   in Loop: Header=BB0_4 Depth=2
	s_delay_alu instid0(VALU_DEP_1)
	v_sub_f32_e32 v0, v0, v0
	s_mov_b32 s1, exec_lo
	v_cmpx_ne_u32_e32 0x7f800000, v4
	s_xor_b32 s1, exec_lo, s1
; %bb.69:                               ;   in Loop: Header=BB0_4 Depth=2
                                        ; implicit-def: $vgpr2
; %bb.70:                               ; %Flow88
                                        ;   in Loop: Header=BB0_4 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_saveexec_b32 s1, s1
	v_mov_b32_e32 v3, v0
	s_xor_b32 exec_lo, exec_lo, s1
; %bb.71:                               ;   in Loop: Header=BB0_4 Depth=2
	v_cmp_lt_i32_e32 vcc_lo, -1, v2
	v_dual_cndmask_b32 v3, 0, v2 :: v_dual_cndmask_b32 v0, 0, v0
; %bb.72:                               ; %Flow89
                                        ;   in Loop: Header=BB0_4 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
.LBB0_73:                               ; %Flow91
                                        ;   in Loop: Header=BB0_4 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $vgpr1
.LBB0_74:                               ; %Flow94
                                        ;   in Loop: Header=BB0_4 Depth=2
	s_and_not1_saveexec_b32 s19, s19
	s_cbranch_execz .LBB0_84
; %bb.75:                               ;   in Loop: Header=BB0_4 Depth=2
	v_cmp_ngt_f32_e64 s20, 0x48000000, |v0|
	v_lshrrev_b32_e32 v5, 23, v1
	v_and_or_b32 v4, v1, s11, 0x800000
                                        ; implicit-def: $vgpr3
                                        ; implicit-def: $vgpr2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_saveexec_b32 s0, s20
	s_xor_b32 s21, exec_lo, s0
	s_cbranch_execz .LBB0_77
; %bb.76:                               ;   in Loop: Header=BB0_4 Depth=2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[2:3], null, 0xfe5163ab, v4, 0
	v_mov_b32_e32 v11, v3
	v_add_nc_u32_e32 v3, 0xffffff88, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[6:7], null, 0x3c439041, v4, v[11:12]
	v_cmp_lt_u32_e32 vcc_lo, 63, v3
	v_cndmask_b32_e64 v18, 0, 0xffffffc0, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v11, v7
	v_add_nc_u32_e32 v3, v18, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[7:8], null, 0xdb629599, v4, v[11:12]
	v_cmp_lt_u32_e64 s0, 31, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v11, v8 :: v_dual_cndmask_b32 v2, v7, v2
	v_mad_u64_u32 v[8:9], null, 0xf534ddc0, v4, v[11:12]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v11, v9 :: v_dual_cndmask_b32 v6, v8, v6
	v_mad_u64_u32 v[9:10], null, 0xfc2757d1, v4, v[11:12]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v2, v6, v2, s0
	v_mov_b32_e32 v11, v10
	v_cndmask_b32_e64 v10, 0, 0xffffffe0, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[18:19], null, 0x4e441529, v4, v[11:12]
	v_add_nc_u32_e32 v3, v10, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_lt_u32_e64 s1, 31, v3
	v_mov_b32_e32 v11, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v10, 0, 0xffffffe0, s1
	v_mad_u64_u32 v[19:20], null, 0xa2f9836e, v4, v[11:12]
	v_cndmask_b32_e32 v11, v18, v8, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v3, v10, v3
	v_dual_cndmask_b32 v19, v19, v9 :: v_dual_cndmask_b32 v18, v20, v18
	v_cndmask_b32_e32 v9, v9, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_eq_u32_e32 vcc_lo, 0, v3
	v_cndmask_b32_e64 v8, v19, v11, s0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v10, v18, v19, s0
	v_cndmask_b32_e64 v11, v11, v9, s0
	v_sub_nc_u32_e32 v18, 32, v3
	v_cndmask_b32_e64 v9, v9, v6, s0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v10, v10, v8, s1
	v_cndmask_b32_e64 v8, v8, v11, s1
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v11, v11, v9, s1
	v_cndmask_b32_e64 v2, v9, v2, s1
	v_alignbit_b32 v19, v10, v8, v18
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_alignbit_b32 v7, v8, v11, v18
	v_cndmask_b32_e32 v3, v19, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v10, v11, v2, v18
	v_cndmask_b32_e32 v6, v7, v8, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_bfe_u32 v7, v3, 29, 1
	v_cndmask_b32_e32 v10, v10, v11, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v8, v3, v6, 30
	v_sub_nc_u32_e32 v9, 0, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_alignbit_b32 v6, v6, v10, 30
	v_alignbit_b32 v2, v10, v2, 30
	v_xor_b32_e32 v8, v8, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v6, v6, v9
	v_xor_b32_e32 v2, v2, v9
	v_lshrrev_b32_e32 v9, 29, v3
	v_lshrrev_b32_e32 v3, 30, v3
	v_clz_i32_u32_e32 v11, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b32_e32 v9, 31, v9
	v_add_nc_u32_e32 v3, v7, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_min_u32_e32 v11, 32, v11
	v_or_b32_e32 v18, 0.5, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v10, 31, v11
	v_lshlrev_b32_e32 v19, 23, v11
	v_alignbit_b32 v8, v8, v6, v10
	v_alignbit_b32 v2, v6, v2, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v18, v18, v19
	v_alignbit_b32 v6, v8, v2, 9
	v_lshrrev_b32_e32 v8, 9, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_clz_i32_u32_e32 v10, v6
	v_min_u32_e32 v10, 32, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v20, 31, v10
	v_alignbit_b32 v2, v6, v2, v20
	v_or_b32_e32 v6, v8, v18
	v_add_lshl_u32 v8, v10, v11, 23
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshrrev_b32_e32 v2, 9, v2
	v_mul_f32_e32 v10, 0x3fc90fda, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v2, v2, v8
	v_fma_f32 v8, 0x3fc90fda, v6, -v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v2, 0x33000000, v2
	v_fmac_f32_e32 v8, 0x33a22168, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or_b32_e32 v2, v2, v9
	v_fmac_f32_e32 v8, 0x3fc90fda, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f32_e32 v2, v10, v8
.LBB0_77:                               ; %Flow93
                                        ;   in Loop: Header=BB0_4 Depth=2
	s_or_saveexec_b32 s0, s21
	v_mul_f32_e64 v8, 0x3f22f983, |v0|
	s_xor_b32 exec_lo, exec_lo, s0
; %bb.78:                               ;   in Loop: Header=BB0_4 Depth=2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f32_e32 v3, v8
	v_fma_f32 v2, 0xbfc90fda, v3, |v0|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v2, 0xb3a22168, v3
	v_fmac_f32_e32 v2, 0xa7c234c4, v3
	v_cvt_i32_f32_e32 v3, v3
; %bb.79:                               ; %_ZL3cosf.exit.i.i.i
                                        ;   in Loop: Header=BB0_4 Depth=2
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $vgpr7
                                        ; implicit-def: $vgpr6
	s_and_saveexec_b32 s0, s20
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s20, exec_lo, s0
	s_cbranch_execz .LBB0_81
; %bb.80:                               ;   in Loop: Header=BB0_4 Depth=2
	v_mad_u64_u32 v[6:7], null, 0xfe5163ab, v4, 0
	v_add_nc_u32_e32 v5, 0xffffff88, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_lt_u32_e32 vcc_lo, 63, v5
	v_mov_b32_e32 v11, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[7:8], null, 0x3c439041, v4, v[11:12]
	v_mov_b32_e32 v11, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[8:9], null, 0xdb629599, v4, v[11:12]
	v_dual_mov_b32 v11, v9 :: v_dual_cndmask_b32 v6, v8, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[9:10], null, 0xf534ddc0, v4, v[11:12]
	v_mov_b32_e32 v11, v10
	v_cndmask_b32_e64 v10, 0, 0xffffffc0, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[18:19], null, 0xfc2757d1, v4, v[11:12]
	v_add_nc_u32_e32 v5, v10, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_lt_u32_e64 s0, 31, v5
	v_mov_b32_e32 v11, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v10, 0, 0xffffffe0, s0
	v_mad_u64_u32 v[19:20], null, 0x4e441529, v4, v[11:12]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v5, v10, v5
	v_mov_b32_e32 v11, v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cmp_lt_u32_e64 s1, 31, v5
	v_cndmask_b32_e32 v10, v19, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[20:21], null, 0xa2f9836e, v4, v[11:12]
	v_cndmask_b32_e64 v4, 0, 0xffffffe0, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v4, v4, v5
	v_cndmask_b32_e32 v11, v20, v18, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_dual_cndmask_b32 v19, v21, v19 :: v_dual_cndmask_b32 v18, v18, v8
	v_cndmask_b32_e32 v5, v9, v7, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 0, v4
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v7, v11, v10, s0
	v_cndmask_b32_e64 v9, v19, v11, s0
	v_cndmask_b32_e64 v10, v10, v18, s0
	v_sub_nc_u32_e32 v11, 32, v4
	v_cndmask_b32_e64 v18, v18, v5, s0
	v_cndmask_b32_e64 v5, v5, v6, s0
	v_cndmask_b32_e64 v9, v9, v7, s1
	v_cndmask_b32_e64 v7, v7, v10, s1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v10, v10, v18, s1
	v_cndmask_b32_e64 v5, v18, v5, s1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v19, v9, v7, v11
	v_alignbit_b32 v8, v7, v10, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v11, v10, v5, v11
	v_cndmask_b32_e32 v4, v19, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v6, v8, v7, vcc_lo
	v_cndmask_b32_e32 v10, v11, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_bfe_u32 v7, v4, 29, 1
	v_alignbit_b32 v8, v4, v6, 30
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_alignbit_b32 v6, v6, v10, 30
	v_alignbit_b32 v5, v10, v5, 30
	v_sub_nc_u32_e32 v9, 0, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v8, v8, v9
	v_xor_b32_e32 v6, v6, v9
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v5, v5, v9
	v_lshrrev_b32_e32 v9, 29, v4
	v_lshrrev_b32_e32 v4, 30, v4
	v_clz_i32_u32_e32 v11, v8
	v_lshlrev_b32_e32 v9, 31, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v7, v7, v4
	v_min_u32_e32 v11, 32, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or_b32_e32 v18, 0.5, v9
	v_sub_nc_u32_e32 v10, 31, v11
	v_lshlrev_b32_e32 v19, 23, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_alignbit_b32 v8, v8, v6, v10
	v_alignbit_b32 v5, v6, v5, v10
	v_sub_nc_u32_e32 v18, v18, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_alignbit_b32 v6, v8, v5, 9
	v_lshrrev_b32_e32 v8, 9, v8
	v_clz_i32_u32_e32 v10, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_min_u32_e32 v10, 32, v10
	v_sub_nc_u32_e32 v20, 31, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_alignbit_b32 v5, v6, v5, v20
	v_or_b32_e32 v6, v8, v18
	v_add_lshl_u32 v8, v10, v11, 23
	v_lshrrev_b32_e32 v5, 9, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v10, 0x3fc90fda, v6
	v_sub_nc_u32_e32 v5, v5, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v8, 0x3fc90fda, v6, -v10
	v_add_nc_u32_e32 v5, 0x33000000, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v8, 0x33a22168, v6
	v_or_b32_e32 v5, v5, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v8, 0x3fc90fda, v5
	v_add_f32_e32 v6, v10, v8
                                        ; implicit-def: $vgpr8
.LBB0_81:                               ; %Flow92
                                        ;   in Loop: Header=BB0_4 Depth=2
	s_and_not1_saveexec_b32 s0, s20
; %bb.82:                               ;   in Loop: Header=BB0_4 Depth=2
	v_rndne_f32_e32 v4, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v6, 0xbfc90fda, v4, |v0|
	v_cvt_i32_f32_e32 v7, v4
	v_fmac_f32_e32 v6, 0xb3a22168, v4
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v6, 0xa7c234c4, v4
; %bb.83:                               ; %_ZL3sinf.exit.i.i.i
                                        ;   in Loop: Header=BB0_4 Depth=2
	s_or_b32 exec_lo, exec_lo, s0
	v_dual_mul_f32 v5, v2, v2 :: v_dual_and_b32 v8, 1, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_mul_f32 v4, v6, v6 :: v_dual_lshlrev_b32 v3, 30, v3
	v_and_b32_e32 v19, 1, v7
	v_fmaak_f32 v11, s13, v5, 0x3c0881c4
	v_dual_fmaak_f32 v18, s14, v5, 0xbab64f3b :: v_dual_lshlrev_b32 v7, 30, v7
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_fmaak_f32 v10, s14, v4, 0xbab64f3b
	v_and_b32_e32 v3, 0x80000000, v3
	v_fmaak_f32 v11, v5, v11, 0xbe2aaa9d
	v_cmp_eq_u32_e32 vcc_lo, 0, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_fmaak_f32 v10, v4, v10, 0x3d2aabf7 :: v_dual_mul_f32 v11, v5, v11
	v_fmaak_f32 v9, s13, v4, 0x3c0881c4
	v_fmaak_f32 v10, v4, v10, 0xbf000004
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v2, v2, v11 :: v_dual_fmaak_f32 v9, v4, v9, 0xbe2aaa9d
	v_dual_fmaak_f32 v18, v5, v18, 0x3d2aabf7 :: v_dual_mul_f32 v9, v4, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fmaak_f32 v18, v5, v18, 0xbf000004
	v_fma_f32 v4, v4, v10, 1.0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_fmac_f32 v6, v6, v9 :: v_dual_and_b32 v7, 0x80000000, v7
	v_fma_f32 v5, v5, v18, 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v4, v4, v6, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 0, v8
	v_xor_b32_e32 v4, v7, v4
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v2, -v2, v5, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v0, 0x1f8
	v_xor3_b32 v1, v4, v0, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v2, v3, v2
	v_cndmask_b32_e32 v0, 0x7fc00000, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_2)
	v_cndmask_b32_e32 v3, 0x7fc00000, v2, vcc_lo
.LBB0_84:                               ; %Flow95
                                        ;   in Loop: Header=BB0_4 Depth=2
	s_or_b32 exec_lo, exec_lo, s19
                                        ; implicit-def: $vgpr2
.LBB0_85:                               ; %Flow96
                                        ;   in Loop: Header=BB0_4 Depth=2
	s_and_not1_saveexec_b32 s0, s2
	s_cbranch_execz .LBB0_87
; %bb.86:                               ;   in Loop: Header=BB0_4 Depth=2
	v_mul_f32_e32 v1, 0x3fb8aa3b, v2
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_rndne_f32_e32 v3, v1
	v_fma_f32 v4, 0x3fb8aa3b, v2, -v1
	v_dual_sub_f32 v1, v1, v3 :: v_dual_fmac_f32 v4, 0x32a5705f, v2
	v_cvt_i32_f32_e32 v3, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v1, v1, v4
	v_exp_f32_e32 v1, v1
	s_waitcnt_depctr 0xfff
	v_ldexp_f32 v1, v1, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v1, 0, v1, vcc_lo
	v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v2
	v_cndmask_b32_e32 v3, 0x7f800000, v1, vcc_lo
.LBB0_87:                               ; %_ZN6thrust3powIfiEENS_7complexINS_6detail23promoted_numerical_typeIT_T0_vE4typeEEERKNS1_IS4_EERKS5_.exit
                                        ;   in Loop: Header=BB0_4 Depth=2
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_dual_add_f32 v19, v17, v3 :: v_dual_add_f32 v18, v16, v0
	s_add_i32 s18, s18, 1
	v_cmp_ngt_f32_e64 s0, 2.0, v19
	s_branch .LBB0_89
.LBB0_88:                               ;   in Loop: Header=BB0_4 Depth=2
	s_mov_b32 s18, s3
.LBB0_89:                               ; %Flow112
                                        ;   in Loop: Header=BB0_4 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v0, s18
	s_and_b32 s1, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s17, s1, s17
	s_and_not1_b32 exec_lo, exec_lo, s17
	s_cbranch_execnz .LBB0_4
; %bb.90:                               ; %Flow113
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s17
.LBB0_91:                               ; %Flow114
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s16
	v_cmp_eq_u32_e32 vcc_lo, s4, v0
	v_add_nc_u32_e32 v1, s5, v14
	s_add_i32 s5, s5, 1
	s_cmp_eq_u32 s5, s6
	v_cndmask_b32_e64 v0, 46, 35, vcc_lo
	s_waitcnt lgkmcnt(0)
	global_store_b8 v1, v0, s[8:9]
	s_cbranch_scc0 .LBB0_2
.LBB0_92:                               ; %._crit_edge
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z12make_fractalPciii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 20
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 35
		.amdhsa_next_free_sgpr 26
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z12make_fractalPciii, .Lfunc_end0-_Z12make_fractalPciii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 12012
; NumSgprs: 28
; NumVgprs: 35
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 4
; NumSGPRsForWavesPerEU: 28
; NumVGPRsForWavesPerEU: 35
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .offset:         12
        .size:           4
        .value_kind:     by_value
      - .offset:         16
        .size:           4
        .value_kind:     by_value
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 20
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z12make_fractalPciii
    .private_segment_fixed_size: 0
    .sgpr_count:     28
    .sgpr_spill_count: 0
    .symbol:         _Z12make_fractalPciii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     35
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
