// nnIndex: B*M*K;
// nnCount: B*M;
// input:   B*N*C;
// filter:  filter_size*C*r;
// output:  B*M*(C*r)
__global__ void depthwise_conv3d_forward(int B, int N, int M, int C, int r, int K, const int* nnIndex,
                                         const int* nnCount, const int* binIndex, const float* input,
                                         const float* filter, float* output)
{
    for(int i=blockIdx.x;i<B;i+=gridDim.x)
    {
        for(int j=blockIdx.y*blockDim.x+threadIdx.x;j<M*(C*r);j+=blockDim.x*gridDim.y)
        {
            int cout = j%(C*r); // output channel ID
            int cin = cout/r;   // input channel ID
            int m = j/(C*r);    // output point ID
            int nnSize = nnCount[i*M+m];

            for(int k=0;k<nnSize;k++)
            {
                int n = nnIndex[i*M*K+m*K+k];   // input point ID
                int f = binIndex[i*M*K+m*K+k];

                output[i*M*C*r+j] += input[i*N*C+n*C+cin]*filter[f*C*r+cout]/nnSize;
            }
        }
    }
}


__global__ void depthwise_input_backward(int B, int N, int M, int C, int r, int K, const int* nnIndex,
                                         const int* nnCount, const int* binIndex, const float* input,
                                         const float* filter, const float* gradOutput, float* gradInput)
{
    for(int i=blockIdx.x;i<B;i+=gridDim.x)
    {
        for(int j=blockIdx.y*blockDim.x+threadIdx.x;j<M*(C*r);j+=blockDim.x*gridDim.y)
        {
            int cout = j%(C*r); // output channel ID
            int cin = cout/r;   // input channel ID
            int m = j/(C*r);    // output point ID
            int nnSize = nnCount[i*M+m];

            for(int k=0;k<nnSize;k++)
            {
                int n = nnIndex[i*M*K+m*K+k];   // input point ID
                int f = binIndex[i*M*K+m*K+k];

                float derIn = gradOutput[i*M*C*r+j]*filter[f*C*r+cout]/nnSize;
                atomicAdd(&gradInput[i*N*C+n*C+cin],derIn);
            }
        }
    }
}


__global__ void depthwise_filter_backward(int B, int N, int M, int C, int r, int K, const int* nnIndex,
                                          const int* nnCount, const int* binIndex, const float* input,
                                          const float* gradOutput, float* gradFilter, int sharedMemSize,
                                          int startIdx)
{
    extern __shared__ float gradPerBlock[]; // the gradient on each block
    for (int i=threadIdx.x;i<sharedMemSize;i+=blockDim.x)
    {
        gradPerBlock[i] = 0; // for 1D block
    }
    __syncthreads();

    int endIdx = sharedMemSize+startIdx;
    for(int i=blockIdx.x;i<B;i+=gridDim.x)
    {
        for(int j=blockIdx.y*blockDim.x+threadIdx.x;j<M*(C*r);j+=blockDim.x*gridDim.y)
        {
            int cout = j%(C*r); // output channel ID
            int cin = cout/r;   // input channel ID
            int m = j/(C*r);    // output point ID
            int nnSize = nnCount[i*M+m];

            for(int k=0;k<nnSize;k++)
            {
                int n = nnIndex[i*M*K+m*K+k];   // input point ID
                int f = binIndex[i*M*K+m*K+k];

                float derFilt = gradOutput[i*M*C*r+j]*input[i*N*C+n*C+cin]/nnSize;

                int currIdx = f*C*r+cout;
                if((currIdx>=startIdx) && (currIdx<endIdx)) // within the shared memory
                {
                    atomicAdd(&gradPerBlock[currIdx-startIdx],derFilt);
                }
            }
        }
    }
    __syncthreads();

    for (int i=threadIdx.x;i<sharedMemSize;i+=blockDim.x)
    {
        atomicAdd(&gradFilter[i+startIdx],gradPerBlock[i]); // for 1D block
    }
}


// nnIndex: B*M*K;
// nnCount: B*M;
// input:   B*N*C;
// filter:  filter_size*C*r;
// output:  B*M*(C*r)
__global__ void fuzzy_depthwise_conv3d_forward(int B, int N, int M, int C, int r, int K, const int* nnIndex,
                                               const int* nnCount, const int* binIndex, const float* binCoeff,
                                               const float* input, const float* filter, float* output)
{
    // T is the number of fuzzy bins each neighbor locates in
    const int T = 4;

    for(int i=blockIdx.x;i<B;i+=gridDim.x)
    {
        for(int j=blockIdx.y*blockDim.x+threadIdx.x;j<M*(C*r);j+=blockDim.x*gridDim.y)
        {
            int cout = j%(C*r); // output channel ID
            int cin = cout/r;   // input channel ID
            int m = j/(C*r);    // output point ID
            int nnSize = nnCount[i*M+m];

            for(int k=0;k<nnSize;k++)
            {
                int n = nnIndex[i*M*K+m*K+k];   // input point ID

                float weight = 0;
                for(int idx=0;idx<T;idx++)
                {
                    int f = binIndex[i*M*K*T+m*K*T+k*T+idx];
                    float coeff = binCoeff[i*M*K*T+m*K*T+k*T+idx];

                    if (coeff>0)
                    {
                        weight += coeff*filter[f*C*r+cout];
                    }
                }

                output[i*M*C*r+j] += input[i*N*C+n*C+cin]*weight/nnSize;
            }
        }
    }
}


__global__ void fuzzy_depthwise_input_backward(int B, int N, int M, int C, int r, int K,
                                               const int* nnIndex, const int* nnCount, const int* binIndex,
                                               const float* binCoeff, const float* input, const float* filter,
                                               const float* gradOutput, float* gradInput)
{
    const int T = 4;

    for(int i=blockIdx.x;i<B;i+=gridDim.x)
    {
        for(int j=blockIdx.y*blockDim.x+threadIdx.x;j<M*(C*r);j+=blockDim.x*gridDim.y)
        {
            int cout = j%(C*r); // output channel ID
            int cin = cout/r;   // input channel ID
            int m = j/(C*r);    // output point ID
            int nnSize = nnCount[i*M+m];

            for(int k=0;k<nnSize;k++)
            {
                int n = nnIndex[i*M*K+m*K+k];   // input point ID

                float weight = 0;
                for(int idx=0;idx<T;idx++)
                {
                    int f = binIndex[i*M*K*T+m*K*T+k*T+idx];
                    float coeff = binCoeff[i*M*K*T+m*K*T+k*T+idx];

                    if (coeff>0)
                    {
                        weight += coeff*filter[f*C*r+cout];
                    }
                }

                float derIn = gradOutput[i*M*C*r+j]*weight/nnSize;
                atomicAdd(&gradInput[i*N*C+n*C+cin],derIn);
            }
        }
    }
}


__global__ void fuzzy_depthwise_filter_backward(int B, int N, int M, int C, int r, int K, const int* nnIndex,
                                                const int* nnCount, const int* binIndex, const float* binCoeff,
                                                const float* input, const float* gradOutput, float* gradFilter,
                                                int sharedMemSize, int startIdx)
{
    const int T = 4;

    extern __shared__ float gradPerBlock[]; // the gradient on each block
    for (int i=threadIdx.x;i<sharedMemSize;i+=blockDim.x)
    {
        gradPerBlock[i] = 0; // for 1D block
    }
    __syncthreads();

    int endIdx = sharedMemSize+startIdx;
    for(int i=blockIdx.x;i<B;i+=gridDim.x)
    {
        for(int j=blockIdx.y*blockDim.x+threadIdx.x;j<M*(C*r);j+=blockDim.x*gridDim.y)
        {
            int cout = j%(C*r); // output channel ID
            int cin = cout/r;   // input channel ID
            int m = j/(C*r);    // output point ID
            int nnSize = nnCount[i*M+m];

            for(int k=0;k<nnSize;k++)
            {
                int n = nnIndex[i*M*K+m*K+k];   // input point ID
                float derFilt = gradOutput[i*M*C*r+j]*input[i*N*C+n*C+cin]/nnSize;

                for(int idx=0;idx<T;idx++)
                {
                    int f = binIndex[i*M*K*T+m*K*T+k*T+idx];
                    float coeff = binCoeff[i*M*K*T+m*K*T+k*T+idx];

                    if (coeff>0)
                    {
                        int currIdx = f*C*r+cout;
                        if((currIdx>=startIdx) && (currIdx<endIdx)) // within the shared memory
                        {
                            atomicAdd(&gradPerBlock[currIdx-startIdx],coeff*derFilt);
                        }
                    }
                }
            }
        }
    }
    __syncthreads();

    for (int i=threadIdx.x;i<sharedMemSize;i+=blockDim.x)
    {
        atomicAdd(&gradFilter[i+startIdx],gradPerBlock[i]); // for 1D block
    }
}




void depthwiseConv3dLauncher(int B, int N, int M, int C, int r, int K, const int* nnIndex,
                             const int* nnCount, const int* binIndex, const float* input,
                             const float* filter, float* output)
{
    depthwise_conv3d_forward<<<B,1024>>>(B, N, M, C, r, K, nnIndex, nnCount, binIndex,
                                          input, filter, output);
}

void depthwiseConv3dGradLauncher(int B, int N, int M, int F, int C, int r, int K,
                                 const int* nnIndex, const int* nnCount, const int* binIndex,
                                 const float* input,  const float* filter, const float* gradOutput,
                                 float* gradInput, float* gradFilter)
{
    // titan xp has shared memory of 49152 bytes, each float value takes 4 bytes in the memory
    int maxSharedMemSize = int(49152/sizeof(float));

    depthwise_input_backward<<<B,1024>>>(B, N, M, C, r, K, nnIndex, nnCount, binIndex,
                                          input, filter, gradOutput, gradInput);

    int maxIter = (F*C*r)/maxSharedMemSize;
    int remainder = (F*C*r)%maxSharedMemSize;
    for(int iter=0;iter<maxIter;iter++)
    {
        depthwise_filter_backward<<<B,1024,sizeof(float)*maxSharedMemSize>>>(B, N, M, C, r, K, nnIndex, nnCount,
                                                                             binIndex, input, gradOutput, gradFilter,
                                                                             maxSharedMemSize, maxSharedMemSize*iter);
    }
    if(remainder>0) // fill the remainder
    {
        depthwise_filter_backward<<<B,1024,sizeof(float)*remainder>>>(B, N, M, C, r, K, nnIndex, nnCount,
                                                                      binIndex, input, gradOutput, gradFilter,
                                                                      remainder, maxSharedMemSize*maxIter);
    }
}


void fuzzyDepthwiseConv3dLauncher(int B, int N, int M, int C, int r, int K, const int* nnIndex,
                                  const int* nnCount, const int* binIndex, const float* binCoeff,
                                  const float* input, const float* filter, float* output)
{
    fuzzy_depthwise_conv3d_forward<<<B,1024>>>(B, N, M, C, r, K, nnIndex, nnCount, binIndex,
                                               binCoeff, input, filter, output);
}

void fuzzyDepthwiseConv3dGradLauncher(int B, int N, int M, int F, int C, int r, int K, const int* nnIndex,
                                      const int* nnCount, const int* binIndex, const float* binCoeff,
                                      const float* input,  const float* filter, const float* gradOutput,
                                      float* gradInput, float* gradFilter)
{
    // titan xp has shared memory of 49152 bytes, each float value takes 4 bytes in the memory
    int maxSharedMemSize = int(49152/sizeof(float));

    fuzzy_depthwise_input_backward<<<B,1024>>>(B, N, M, C, r, K, nnIndex, nnCount, binIndex, binCoeff,
                                               input, filter, gradOutput, gradInput);

    int maxIter = (F*C*r)/maxSharedMemSize;
    int remainder = (F*C*r)%maxSharedMemSize;
    for(int iter=0;iter<maxIter;iter++)
    {
        fuzzy_depthwise_filter_backward<<<B,1024,sizeof(float)*maxSharedMemSize>>>(B, N, M, C, r, K, nnIndex, nnCount,
                                                                                   binIndex, binCoeff, input, gradOutput,
                                                                                   gradFilter, maxSharedMemSize,
                                                                                   maxSharedMemSize*iter);
    }
    if(remainder>0) // fill the remainder
    {
        fuzzy_depthwise_filter_backward<<<B,1024,sizeof(float)*remainder>>>(B, N, M, C, r, K, nnIndex, nnCount,
                                                                            binIndex, binCoeff, input, gradOutput,
                                                                            gradFilter, remainder,
                                                                            maxSharedMemSize*maxIter);
    }
}
	.file	"tmpxft_00234a96_00000000-6_tf_conv3d_gpu.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2014:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2014:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z65__device_stub__Z24depthwise_conv3d_forwardiiiiiiPKiS0_S0_PKfS2_PfiiiiiiPKiS0_S0_PKfS2_Pf
	.type	_Z65__device_stub__Z24depthwise_conv3d_forwardiiiiiiPKiS0_S0_PKfS2_PfiiiiiiPKiS0_S0_PKfS2_Pf, @function
_Z65__device_stub__Z24depthwise_conv3d_forwardiiiiiiPKiS0_S0_PKfS2_PfiiiiiiPKiS0_S0_PKfS2_Pf:
.LFB2036:
	.cfi_startproc
	endbr64
	subq	$264, %rsp
	.cfi_def_cfa_offset 272
	movq	272(%rsp), %rax
	movl	%edi, 76(%rsp)
	leaq	104(%rsp), %rdi
	movl	%esi, 72(%rsp)
	leaq	116(%rsp), %rsi
	movq	%rax, 48(%rsp)
	movq	280(%rsp), %rax
	movl	%edx, 68(%rsp)
	leaq	88(%rsp), %rdx
	movq	%rax, 40(%rsp)
	movq	288(%rsp), %rax
	movl	%ecx, 64(%rsp)
	leaq	96(%rsp), %rcx
	movq	%rax, 32(%rsp)
	movq	296(%rsp), %rax
	movl	%r8d, 60(%rsp)
	movq	%rax, 24(%rsp)
	movq	304(%rsp), %rax
	movl	%r9d, 56(%rsp)
	movq	%rax, 16(%rsp)
	movq	312(%rsp), %rax
	movq	%rax, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 248(%rsp)
	xorl	%eax, %eax
	leaq	76(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	72(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	68(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	64(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	60(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	56(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 208(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 216(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 224(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 232(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 240(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 104(%rsp)
	movl	$1, 112(%rsp)
	movq	%rax, 116(%rsp)
	movl	$1, 124(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	96(%rsp)
	.cfi_def_cfa_offset 280
	leaq	_Z24depthwise_conv3d_forwardiiiiiiPKiS0_S0_PKfS2_Pf(%rip), %rdi
	pushq	96(%rsp)
	.cfi_def_cfa_offset 288
	movq	132(%rsp), %rcx
	movl	140(%rsp), %r8d
	movq	120(%rsp), %rsi
	movl	128(%rsp), %edx
	leaq	168(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 280
	popq	%rdx
	.cfi_def_cfa_offset 272
.L2:
	movq	248(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$264, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2036:
	.size	_Z65__device_stub__Z24depthwise_conv3d_forwardiiiiiiPKiS0_S0_PKfS2_PfiiiiiiPKiS0_S0_PKfS2_Pf, .-_Z65__device_stub__Z24depthwise_conv3d_forwardiiiiiiPKiS0_S0_PKfS2_PfiiiiiiPKiS0_S0_PKfS2_Pf
	.globl	_Z24depthwise_conv3d_forwardiiiiiiPKiS0_S0_PKfS2_Pf
	.type	_Z24depthwise_conv3d_forwardiiiiiiPKiS0_S0_PKfS2_Pf, @function
_Z24depthwise_conv3d_forwardiiiiiiPKiS0_S0_PKfS2_Pf:
.LFB2037:
	.cfi_startproc
	endbr64
	jmp	_Z65__device_stub__Z24depthwise_conv3d_forwardiiiiiiPKiS0_S0_PKfS2_PfiiiiiiPKiS0_S0_PKfS2_Pf
	.cfi_endproc
.LFE2037:
	.size	_Z24depthwise_conv3d_forwardiiiiiiPKiS0_S0_PKfS2_Pf, .-_Z24depthwise_conv3d_forwardiiiiiiPKiS0_S0_PKfS2_Pf
	.globl	_Z23depthwiseConv3dLauncheriiiiiiPKiS0_S0_PKfS2_Pf
	.type	_Z23depthwiseConv3dLauncheriiiiiiPKiS0_S0_PKfS2_Pf, @function
_Z23depthwiseConv3dLauncheriiiiiiPKiS0_S0_PKfS2_Pf:
.LFB2008:
	.cfi_startproc
	endbr64
	movabsq	$4294967297, %rax
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movl	%edi, %ebx
	subq	$72, %rsp
	.cfi_def_cfa_offset 128
	movq	%rax, 44(%rsp)
	movq	168(%rsp), %r11
	movl	%esi, 4(%rsp)
	movl	48(%rsp), %esi
	movl	%edx, 8(%rsp)
	movl	$4194305, %edx
	movq	128(%rsp), %r12
	movl	%edi, 40(%rsp)
	movq	40(%rsp), %rdi
	salq	$10, %rdx
	movl	%ecx, 12(%rsp)
	movl	$1, %ecx
	movq	136(%rsp), %r13
	movl	%r8d, 16(%rsp)
	xorl	%r8d, %r8d
	movq	144(%rsp), %r14
	movl	%r9d, 20(%rsp)
	xorl	%r9d, %r9d
	movq	152(%rsp), %r15
	movq	%r11, 24(%rsp)
	movq	160(%rsp), %rbp
	call	__cudaPushCallConfiguration@PLT
	movq	24(%rsp), %r11
	testl	%eax, %eax
	jne	.L8
	movq	%rbp, 160(%rsp)
	movl	20(%rsp), %r9d
	movl	%ebx, %edi
	movq	%r15, 152(%rsp)
	movl	16(%rsp), %r8d
	movq	%r14, 144(%rsp)
	movl	12(%rsp), %ecx
	movl	8(%rsp), %edx
	movl	4(%rsp), %esi
	movq	%r13, 136(%rsp)
	movq	%r12, 128(%rsp)
	movq	%r11, 168(%rsp)
	addq	$72, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	_Z65__device_stub__Z24depthwise_conv3d_forwardiiiiiiPKiS0_S0_PKfS2_PfiiiiiiPKiS0_S0_PKfS2_Pf
.L8:
	.cfi_restore_state
	addq	$72, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2008:
	.size	_Z23depthwiseConv3dLauncheriiiiiiPKiS0_S0_PKfS2_Pf, .-_Z23depthwiseConv3dLauncheriiiiiiPKiS0_S0_PKfS2_Pf
	.globl	_Z68__device_stub__Z24depthwise_input_backwardiiiiiiPKiS0_S0_PKfS2_S2_PfiiiiiiPKiS0_S0_PKfS2_S2_Pf
	.type	_Z68__device_stub__Z24depthwise_input_backwardiiiiiiPKiS0_S0_PKfS2_S2_PfiiiiiiPKiS0_S0_PKfS2_S2_Pf, @function
_Z68__device_stub__Z24depthwise_input_backwardiiiiiiPKiS0_S0_PKfS2_S2_PfiiiiiiPKiS0_S0_PKfS2_S2_Pf:
.LFB2038:
	.cfi_startproc
	endbr64
	subq	$264, %rsp
	.cfi_def_cfa_offset 272
	movq	272(%rsp), %rax
	movl	%edi, 76(%rsp)
	leaq	96(%rsp), %rdi
	movl	%esi, 72(%rsp)
	leaq	108(%rsp), %rsi
	movq	%rax, 48(%rsp)
	movq	280(%rsp), %rax
	movl	%edx, 68(%rsp)
	leaq	80(%rsp), %rdx
	movq	%rax, 40(%rsp)
	movq	288(%rsp), %rax
	movl	%ecx, 64(%rsp)
	leaq	88(%rsp), %rcx
	movq	%rax, 32(%rsp)
	movq	296(%rsp), %rax
	movl	%r8d, 60(%rsp)
	movq	%rax, 24(%rsp)
	movq	304(%rsp), %rax
	movl	%r9d, 56(%rsp)
	movq	%rax, 16(%rsp)
	movq	312(%rsp), %rax
	movq	%rax, 8(%rsp)
	movq	320(%rsp), %rax
	movq	%rax, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 248(%rsp)
	xorl	%eax, %eax
	leaq	76(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	72(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	68(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	64(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	60(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	56(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 208(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 216(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 224(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 232(%rsp)
	movq	%rsp, %rax
	movq	%rax, 240(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 96(%rsp)
	movl	$1, 104(%rsp)
	movq	%rax, 108(%rsp)
	movl	$1, 116(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L11
	pushq	88(%rsp)
	.cfi_def_cfa_offset 280
	leaq	_Z24depthwise_input_backwardiiiiiiPKiS0_S0_PKfS2_S2_Pf(%rip), %rdi
	pushq	88(%rsp)
	.cfi_def_cfa_offset 288
	movq	124(%rsp), %rcx
	movl	132(%rsp), %r8d
	movq	112(%rsp), %rsi
	movl	120(%rsp), %edx
	leaq	160(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 280
	popq	%rdx
	.cfi_def_cfa_offset 272
.L11:
	movq	248(%rsp), %rax
	subq	%fs:40, %rax
	je	.L13
	call	__stack_chk_fail@PLT
.L13:
	addq	$264, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2038:
	.size	_Z68__device_stub__Z24depthwise_input_backwardiiiiiiPKiS0_S0_PKfS2_S2_PfiiiiiiPKiS0_S0_PKfS2_S2_Pf, .-_Z68__device_stub__Z24depthwise_input_backwardiiiiiiPKiS0_S0_PKfS2_S2_PfiiiiiiPKiS0_S0_PKfS2_S2_Pf
	.globl	_Z24depthwise_input_backwardiiiiiiPKiS0_S0_PKfS2_S2_Pf
	.type	_Z24depthwise_input_backwardiiiiiiPKiS0_S0_PKfS2_S2_Pf, @function
_Z24depthwise_input_backwardiiiiiiPKiS0_S0_PKfS2_S2_Pf:
.LFB2039:
	.cfi_startproc
	endbr64
	jmp	_Z68__device_stub__Z24depthwise_input_backwardiiiiiiPKiS0_S0_PKfS2_S2_PfiiiiiiPKiS0_S0_PKfS2_S2_Pf
	.cfi_endproc
.LFE2039:
	.size	_Z24depthwise_input_backwardiiiiiiPKiS0_S0_PKfS2_S2_Pf, .-_Z24depthwise_input_backwardiiiiiiPKiS0_S0_PKfS2_S2_Pf
	.globl	_Z68__device_stub__Z25depthwise_filter_backwardiiiiiiPKiS0_S0_PKfS2_PfiiiiiiiiPKiS0_S0_PKfS2_Pfii
	.type	_Z68__device_stub__Z25depthwise_filter_backwardiiiiiiPKiS0_S0_PKfS2_PfiiiiiiiiPKiS0_S0_PKfS2_Pfii, @function
_Z68__device_stub__Z25depthwise_filter_backwardiiiiiiPKiS0_S0_PKfS2_PfiiiiiiiiPKiS0_S0_PKfS2_Pfii:
.LFB2040:
	.cfi_startproc
	endbr64
	subq	$280, %rsp
	.cfi_def_cfa_offset 288
	movq	288(%rsp), %rax
	movl	%edi, 76(%rsp)
	leaq	104(%rsp), %rdi
	movl	%esi, 72(%rsp)
	leaq	116(%rsp), %rsi
	movq	%rax, 48(%rsp)
	movq	296(%rsp), %rax
	movl	%edx, 68(%rsp)
	leaq	88(%rsp), %rdx
	movq	%rax, 40(%rsp)
	movq	304(%rsp), %rax
	movl	%ecx, 64(%rsp)
	leaq	96(%rsp), %rcx
	movq	%rax, 32(%rsp)
	movq	312(%rsp), %rax
	movl	%r8d, 60(%rsp)
	movq	%rax, 24(%rsp)
	movq	320(%rsp), %rax
	movl	%r9d, 56(%rsp)
	movq	%rax, 16(%rsp)
	movq	328(%rsp), %rax
	movq	%rax, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 264(%rsp)
	xorl	%eax, %eax
	leaq	76(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	72(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	68(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	64(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	60(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	56(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 208(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 216(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 224(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 232(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 240(%rsp)
	leaq	336(%rsp), %rax
	movq	%rax, 248(%rsp)
	leaq	344(%rsp), %rax
	movq	%rax, 256(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 104(%rsp)
	movl	$1, 112(%rsp)
	movq	%rax, 116(%rsp)
	movl	$1, 124(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L16
	pushq	96(%rsp)
	.cfi_def_cfa_offset 296
	leaq	_Z25depthwise_filter_backwardiiiiiiPKiS0_S0_PKfS2_Pfii(%rip), %rdi
	pushq	96(%rsp)
	.cfi_def_cfa_offset 304
	movq	132(%rsp), %rcx
	movl	140(%rsp), %r8d
	movq	120(%rsp), %rsi
	movl	128(%rsp), %edx
	leaq	168(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 296
	popq	%rdx
	.cfi_def_cfa_offset 288
.L16:
	movq	264(%rsp), %rax
	subq	%fs:40, %rax
	je	.L18
	call	__stack_chk_fail@PLT
.L18:
	addq	$280, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2040:
	.size	_Z68__device_stub__Z25depthwise_filter_backwardiiiiiiPKiS0_S0_PKfS2_PfiiiiiiiiPKiS0_S0_PKfS2_Pfii, .-_Z68__device_stub__Z25depthwise_filter_backwardiiiiiiPKiS0_S0_PKfS2_PfiiiiiiiiPKiS0_S0_PKfS2_Pfii
	.globl	_Z25depthwise_filter_backwardiiiiiiPKiS0_S0_PKfS2_Pfii
	.type	_Z25depthwise_filter_backwardiiiiiiPKiS0_S0_PKfS2_Pfii, @function
_Z25depthwise_filter_backwardiiiiiiPKiS0_S0_PKfS2_Pfii:
.LFB2041:
	.cfi_startproc
	endbr64
	jmp	_Z68__device_stub__Z25depthwise_filter_backwardiiiiiiPKiS0_S0_PKfS2_PfiiiiiiiiPKiS0_S0_PKfS2_Pfii
	.cfi_endproc
.LFE2041:
	.size	_Z25depthwise_filter_backwardiiiiiiPKiS0_S0_PKfS2_Pfii, .-_Z25depthwise_filter_backwardiiiiiiPKiS0_S0_PKfS2_Pfii
	.globl	_Z27depthwiseConv3dGradLauncheriiiiiiiPKiS0_S0_PKfS2_S2_PfS3_
	.type	_Z27depthwiseConv3dGradLauncheriiiiiiiPKiS0_S0_PKfS2_S2_PfS3_, @function
_Z27depthwiseConv3dGradLauncheriiiiiiiPKiS0_S0_PKfS2_S2_PfS3_:
.LFB2009:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movl	%edi, %r12d
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movl	%ecx, %ebx
	movl	$1, %ecx
	subq	$104, %rsp
	.cfi_def_cfa_offset 160
	movl	160(%rsp), %eax
	movq	200(%rsp), %r10
	movl	%edx, 24(%rsp)
	movl	$4194305, %edx
	movq	216(%rsp), %r11
	salq	$10, %rdx
	movl	%esi, 20(%rsp)
	movl	%eax, 28(%rsp)
	movq	176(%rsp), %rax
	movq	%r10, 56(%rsp)
	movq	168(%rsp), %rbp
	movq	%rax, 32(%rsp)
	movq	224(%rsp), %rax
	movq	%r11, 40(%rsp)
	movq	184(%rsp), %r13
	movq	%rax, 48(%rsp)
	movq	192(%rsp), %r14
	movabsq	$4294967297, %rax
	movl	%r8d, 12(%rsp)
	movq	208(%rsp), %r15
	xorl	%r8d, %r8d
	movl	%r9d, 16(%rsp)
	xorl	%r9d, %r9d
	movq	%rdx, 84(%rsp)
	movq	%rax, 76(%rsp)
	movl	80(%rsp), %esi
	movl	%edi, 72(%rsp)
	movq	72(%rsp), %rdi
	movl	$1, 92(%rsp)
	call	__cudaPushCallConfiguration@PLT
	movq	40(%rsp), %r11
	movq	56(%rsp), %r10
	testl	%eax, %eax
	jne	.L22
	pushq	%rax
	.cfi_def_cfa_offset 168
	movl	%r12d, %edi
	pushq	%r11
	.cfi_def_cfa_offset 176
	pushq	%r15
	.cfi_def_cfa_offset 184
	pushq	%r10
	.cfi_def_cfa_offset 192
	pushq	%r14
	.cfi_def_cfa_offset 200
	pushq	%r13
	.cfi_def_cfa_offset 208
	pushq	80(%rsp)
	.cfi_def_cfa_offset 216
	pushq	%rbp
	.cfi_def_cfa_offset 224
	movl	92(%rsp), %r9d
	movl	80(%rsp), %r8d
	movl	76(%rsp), %ecx
	movl	88(%rsp), %edx
	movl	84(%rsp), %esi
	call	_Z68__device_stub__Z24depthwise_input_backwardiiiiiiPKiS0_S0_PKfS2_S2_PfiiiiiiPKiS0_S0_PKfS2_S2_Pf
	addq	$64, %rsp
	.cfi_def_cfa_offset 160
.L22:
	movl	12(%rsp), %eax
	imull	%ebx, %eax
	movl	16(%rsp), %ebx
	imull	%ebx, %eax
	movl	$12288, %ebx
	cltd
	idivl	%ebx
	xorl	%ebx, %ebx
	movl	%edx, 40(%rsp)
	movl	%eax, 56(%rsp)
.L23:
	movl	56(%rsp), %eax
	cmpl	%eax, %ebx
	jge	.L29
	movl	$4194305, %eax
	movl	%r12d, 72(%rsp)
	movl	$4194305, %edx
	xorl	%r9d, %r9d
	salq	$10, %rax
	salq	$10, %rdx
	movl	$49152, %r8d
	movl	$1, %ecx
	movq	%rax, 84(%rsp)
	subq	$1023, %rax
	movq	%rax, 76(%rsp)
	movq	72(%rsp), %rdi
	movl	80(%rsp), %esi
	movl	$1, 92(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L24
	imull	$12288, %ebx, %eax
	movl	%r12d, %edi
	pushq	%rax
	.cfi_def_cfa_offset 168
	pushq	$12288
	.cfi_def_cfa_offset 176
	pushq	64(%rsp)
	.cfi_def_cfa_offset 184
	pushq	%r15
	.cfi_def_cfa_offset 192
	pushq	%r14
	.cfi_def_cfa_offset 200
	pushq	%r13
	.cfi_def_cfa_offset 208
	pushq	80(%rsp)
	.cfi_def_cfa_offset 216
	pushq	%rbp
	.cfi_def_cfa_offset 224
	movl	92(%rsp), %r9d
	movl	80(%rsp), %r8d
	movl	76(%rsp), %ecx
	movl	88(%rsp), %edx
	movl	84(%rsp), %esi
	call	_Z68__device_stub__Z25depthwise_filter_backwardiiiiiiPKiS0_S0_PKfS2_PfiiiiiiiiPKiS0_S0_PKfS2_Pfii
	addq	$64, %rsp
	.cfi_def_cfa_offset 160
.L24:
	incl	%ebx
	jmp	.L23
.L29:
	cmpl	$0, 40(%rsp)
	jle	.L21
	movl	%r12d, 72(%rsp)
	movl	$4194305, %edx
	xorl	%r9d, %r9d
	movl	$1, %ecx
	movabsq	$4294967297, %rax
	salq	$10, %rdx
	movl	$1, 92(%rsp)
	movq	%rax, 76(%rsp)
	movslq	40(%rsp), %rax
	movq	72(%rsp), %rdi
	movl	80(%rsp), %esi
	movq	%rdx, 84(%rsp)
	leaq	0(,%rax,4), %r8
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L21
	movq	%r15, 192(%rsp)
	movl	28(%rsp), %r9d
	movl	%r12d, %edi
	imull	$12288, 56(%rsp), %eax
	movq	%r14, 184(%rsp)
	movl	12(%rsp), %ecx
	movl	24(%rsp), %edx
	movq	%r13, 176(%rsp)
	movq	%rbp, 160(%rsp)
	movl	16(%rsp), %r8d
	movl	%eax, 216(%rsp)
	movl	40(%rsp), %eax
	movl	20(%rsp), %esi
	movl	%eax, 208(%rsp)
	movq	48(%rsp), %rax
	movq	%rax, 200(%rsp)
	movq	32(%rsp), %rax
	movq	%rax, 168(%rsp)
	addq	$104, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	_Z68__device_stub__Z25depthwise_filter_backwardiiiiiiPKiS0_S0_PKfS2_PfiiiiiiiiPKiS0_S0_PKfS2_Pfii
.L21:
	.cfi_restore_state
	addq	$104, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2009:
	.size	_Z27depthwiseConv3dGradLauncheriiiiiiiPKiS0_S0_PKfS2_S2_PfS3_, .-_Z27depthwiseConv3dGradLauncheriiiiiiiPKiS0_S0_PKfS2_S2_PfS3_
	.globl	_Z74__device_stub__Z30fuzzy_depthwise_conv3d_forwardiiiiiiPKiS0_S0_PKfS2_S2_PfiiiiiiPKiS0_S0_PKfS2_S2_Pf
	.type	_Z74__device_stub__Z30fuzzy_depthwise_conv3d_forwardiiiiiiPKiS0_S0_PKfS2_S2_PfiiiiiiPKiS0_S0_PKfS2_S2_Pf, @function
_Z74__device_stub__Z30fuzzy_depthwise_conv3d_forwardiiiiiiPKiS0_S0_PKfS2_S2_PfiiiiiiPKiS0_S0_PKfS2_S2_Pf:
.LFB2042:
	.cfi_startproc
	endbr64
	subq	$264, %rsp
	.cfi_def_cfa_offset 272
	movq	272(%rsp), %rax
	movl	%edi, 76(%rsp)
	leaq	96(%rsp), %rdi
	movl	%esi, 72(%rsp)
	leaq	108(%rsp), %rsi
	movq	%rax, 48(%rsp)
	movq	280(%rsp), %rax
	movl	%edx, 68(%rsp)
	leaq	80(%rsp), %rdx
	movq	%rax, 40(%rsp)
	movq	288(%rsp), %rax
	movl	%ecx, 64(%rsp)
	leaq	88(%rsp), %rcx
	movq	%rax, 32(%rsp)
	movq	296(%rsp), %rax
	movl	%r8d, 60(%rsp)
	movq	%rax, 24(%rsp)
	movq	304(%rsp), %rax
	movl	%r9d, 56(%rsp)
	movq	%rax, 16(%rsp)
	movq	312(%rsp), %rax
	movq	%rax, 8(%rsp)
	movq	320(%rsp), %rax
	movq	%rax, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 248(%rsp)
	xorl	%eax, %eax
	leaq	76(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	72(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	68(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	64(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	60(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	56(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 208(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 216(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 224(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 232(%rsp)
	movq	%rsp, %rax
	movq	%rax, 240(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 96(%rsp)
	movl	$1, 104(%rsp)
	movq	%rax, 108(%rsp)
	movl	$1, 116(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L30
	pushq	88(%rsp)
	.cfi_def_cfa_offset 280
	leaq	_Z30fuzzy_depthwise_conv3d_forwardiiiiiiPKiS0_S0_PKfS2_S2_Pf(%rip), %rdi
	pushq	88(%rsp)
	.cfi_def_cfa_offset 288
	movq	124(%rsp), %rcx
	movl	132(%rsp), %r8d
	movq	112(%rsp), %rsi
	movl	120(%rsp), %edx
	leaq	160(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 280
	popq	%rdx
	.cfi_def_cfa_offset 272
.L30:
	movq	248(%rsp), %rax
	subq	%fs:40, %rax
	je	.L32
	call	__stack_chk_fail@PLT
.L32:
	addq	$264, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2042:
	.size	_Z74__device_stub__Z30fuzzy_depthwise_conv3d_forwardiiiiiiPKiS0_S0_PKfS2_S2_PfiiiiiiPKiS0_S0_PKfS2_S2_Pf, .-_Z74__device_stub__Z30fuzzy_depthwise_conv3d_forwardiiiiiiPKiS0_S0_PKfS2_S2_PfiiiiiiPKiS0_S0_PKfS2_S2_Pf
	.globl	_Z30fuzzy_depthwise_conv3d_forwardiiiiiiPKiS0_S0_PKfS2_S2_Pf
	.type	_Z30fuzzy_depthwise_conv3d_forwardiiiiiiPKiS0_S0_PKfS2_S2_Pf, @function
_Z30fuzzy_depthwise_conv3d_forwardiiiiiiPKiS0_S0_PKfS2_S2_Pf:
.LFB2043:
	.cfi_startproc
	endbr64
	jmp	_Z74__device_stub__Z30fuzzy_depthwise_conv3d_forwardiiiiiiPKiS0_S0_PKfS2_S2_PfiiiiiiPKiS0_S0_PKfS2_S2_Pf
	.cfi_endproc
.LFE2043:
	.size	_Z30fuzzy_depthwise_conv3d_forwardiiiiiiPKiS0_S0_PKfS2_S2_Pf, .-_Z30fuzzy_depthwise_conv3d_forwardiiiiiiPKiS0_S0_PKfS2_S2_Pf
	.globl	_Z28fuzzyDepthwiseConv3dLauncheriiiiiiPKiS0_S0_PKfS2_S2_Pf
	.type	_Z28fuzzyDepthwiseConv3dLauncheriiiiiiPKiS0_S0_PKfS2_S2_Pf, @function
_Z28fuzzyDepthwiseConv3dLauncheriiiiiiPKiS0_S0_PKfS2_S2_Pf:
.LFB2010:
	.cfi_startproc
	endbr64
	movabsq	$4294967297, %rax
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movl	%edi, %ebx
	subq	$88, %rsp
	.cfi_def_cfa_offset 144
	movq	%rax, 60(%rsp)
	movq	184(%rsp), %r10
	movq	192(%rsp), %r11
	movl	%esi, 12(%rsp)
	movl	%edx, 16(%rsp)
	movl	64(%rsp), %esi
	movl	$4194305, %edx
	movl	%edi, 56(%rsp)
	movq	56(%rsp), %rdi
	salq	$10, %rdx
	movl	%ecx, 20(%rsp)
	movl	$1, %ecx
	movq	144(%rsp), %rbp
	movl	%r8d, 24(%rsp)
	xorl	%r8d, %r8d
	movq	152(%rsp), %r12
	movl	%r9d, 28(%rsp)
	xorl	%r9d, %r9d
	movq	160(%rsp), %r13
	movq	%r10, 40(%rsp)
	movq	168(%rsp), %r14
	movq	%r11, 32(%rsp)
	movq	176(%rsp), %r15
	call	__cudaPushCallConfiguration@PLT
	movq	32(%rsp), %r11
	movq	40(%rsp), %r10
	testl	%eax, %eax
	jne	.L35
	movq	%r15, 176(%rsp)
	movl	28(%rsp), %r9d
	movl	%ebx, %edi
	movq	%r14, 168(%rsp)
	movl	24(%rsp), %r8d
	movq	%r13, 160(%rsp)
	movl	20(%rsp), %ecx
	movq	%r12, 152(%rsp)
	movl	16(%rsp), %edx
	movq	%rbp, 144(%rsp)
	movl	12(%rsp), %esi
	movq	%r11, 192(%rsp)
	movq	%r10, 184(%rsp)
	addq	$88, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	_Z74__device_stub__Z30fuzzy_depthwise_conv3d_forwardiiiiiiPKiS0_S0_PKfS2_S2_PfiiiiiiPKiS0_S0_PKfS2_S2_Pf
.L35:
	.cfi_restore_state
	addq	$88, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2010:
	.size	_Z28fuzzyDepthwiseConv3dLauncheriiiiiiPKiS0_S0_PKfS2_S2_Pf, .-_Z28fuzzyDepthwiseConv3dLauncheriiiiiiPKiS0_S0_PKfS2_S2_Pf
	.globl	_Z77__device_stub__Z30fuzzy_depthwise_input_backwardiiiiiiPKiS0_S0_PKfS2_S2_S2_PfiiiiiiPKiS0_S0_PKfS2_S2_S2_Pf
	.type	_Z77__device_stub__Z30fuzzy_depthwise_input_backwardiiiiiiPKiS0_S0_PKfS2_S2_S2_PfiiiiiiPKiS0_S0_PKfS2_S2_S2_Pf, @function
_Z77__device_stub__Z30fuzzy_depthwise_input_backwardiiiiiiPKiS0_S0_PKfS2_S2_S2_PfiiiiiiPKiS0_S0_PKfS2_S2_S2_Pf:
.LFB2044:
	.cfi_startproc
	endbr64
	subq	$296, %rsp
	.cfi_def_cfa_offset 304
	movq	304(%rsp), %rax
	movl	%edi, 92(%rsp)
	leaq	120(%rsp), %rdi
	movl	%esi, 88(%rsp)
	leaq	132(%rsp), %rsi
	movq	%rax, 64(%rsp)
	movq	312(%rsp), %rax
	movl	%edx, 84(%rsp)
	leaq	104(%rsp), %rdx
	movq	%rax, 56(%rsp)
	movq	320(%rsp), %rax
	movl	%ecx, 80(%rsp)
	leaq	112(%rsp), %rcx
	movq	%rax, 48(%rsp)
	movq	328(%rsp), %rax
	movl	%r8d, 76(%rsp)
	movq	%rax, 40(%rsp)
	movq	336(%rsp), %rax
	movl	%r9d, 72(%rsp)
	movq	%rax, 32(%rsp)
	movq	344(%rsp), %rax
	movq	%rax, 24(%rsp)
	movq	352(%rsp), %rax
	movq	%rax, 16(%rsp)
	movq	360(%rsp), %rax
	movq	%rax, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 280(%rsp)
	xorl	%eax, %eax
	leaq	92(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	88(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	84(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	80(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	76(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	72(%rsp), %rax
	movq	%rax, 208(%rsp)
	leaq	64(%rsp), %rax
	movq	%rax, 216(%rsp)
	leaq	56(%rsp), %rax
	movq	%rax, 224(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 232(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 240(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 248(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 256(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 264(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 272(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 120(%rsp)
	movl	$1, 128(%rsp)
	movq	%rax, 132(%rsp)
	movl	$1, 140(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L38
	pushq	112(%rsp)
	.cfi_def_cfa_offset 312
	leaq	_Z30fuzzy_depthwise_input_backwardiiiiiiPKiS0_S0_PKfS2_S2_S2_Pf(%rip), %rdi
	pushq	112(%rsp)
	.cfi_def_cfa_offset 320
	movq	148(%rsp), %rcx
	movl	156(%rsp), %r8d
	movq	136(%rsp), %rsi
	movl	144(%rsp), %edx
	leaq	184(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 312
	popq	%rdx
	.cfi_def_cfa_offset 304
.L38:
	movq	280(%rsp), %rax
	subq	%fs:40, %rax
	je	.L40
	call	__stack_chk_fail@PLT
.L40:
	addq	$296, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2044:
	.size	_Z77__device_stub__Z30fuzzy_depthwise_input_backwardiiiiiiPKiS0_S0_PKfS2_S2_S2_PfiiiiiiPKiS0_S0_PKfS2_S2_S2_Pf, .-_Z77__device_stub__Z30fuzzy_depthwise_input_backwardiiiiiiPKiS0_S0_PKfS2_S2_S2_PfiiiiiiPKiS0_S0_PKfS2_S2_S2_Pf
	.globl	_Z30fuzzy_depthwise_input_backwardiiiiiiPKiS0_S0_PKfS2_S2_S2_Pf
	.type	_Z30fuzzy_depthwise_input_backwardiiiiiiPKiS0_S0_PKfS2_S2_S2_Pf, @function
_Z30fuzzy_depthwise_input_backwardiiiiiiPKiS0_S0_PKfS2_S2_S2_Pf:
.LFB2045:
	.cfi_startproc
	endbr64
	jmp	_Z77__device_stub__Z30fuzzy_depthwise_input_backwardiiiiiiPKiS0_S0_PKfS2_S2_S2_PfiiiiiiPKiS0_S0_PKfS2_S2_S2_Pf
	.cfi_endproc
.LFE2045:
	.size	_Z30fuzzy_depthwise_input_backwardiiiiiiPKiS0_S0_PKfS2_S2_S2_Pf, .-_Z30fuzzy_depthwise_input_backwardiiiiiiPKiS0_S0_PKfS2_S2_S2_Pf
	.globl	_Z77__device_stub__Z31fuzzy_depthwise_filter_backwardiiiiiiPKiS0_S0_PKfS2_S2_PfiiiiiiiiPKiS0_S0_PKfS2_S2_Pfii
	.type	_Z77__device_stub__Z31fuzzy_depthwise_filter_backwardiiiiiiPKiS0_S0_PKfS2_S2_PfiiiiiiiiPKiS0_S0_PKfS2_S2_Pfii, @function
_Z77__device_stub__Z31fuzzy_depthwise_filter_backwardiiiiiiPKiS0_S0_PKfS2_S2_PfiiiiiiiiPKiS0_S0_PKfS2_S2_Pfii:
.LFB2046:
	.cfi_startproc
	endbr64
	subq	$280, %rsp
	.cfi_def_cfa_offset 288
	movq	288(%rsp), %rax
	movl	%edi, 76(%rsp)
	leaq	96(%rsp), %rdi
	movl	%esi, 72(%rsp)
	leaq	108(%rsp), %rsi
	movq	%rax, 48(%rsp)
	movq	296(%rsp), %rax
	movl	%edx, 68(%rsp)
	leaq	80(%rsp), %rdx
	movq	%rax, 40(%rsp)
	movq	304(%rsp), %rax
	movl	%ecx, 64(%rsp)
	leaq	88(%rsp), %rcx
	movq	%rax, 32(%rsp)
	movq	312(%rsp), %rax
	movl	%r8d, 60(%rsp)
	movq	%rax, 24(%rsp)
	movq	320(%rsp), %rax
	movl	%r9d, 56(%rsp)
	movq	%rax, 16(%rsp)
	movq	328(%rsp), %rax
	movq	%rax, 8(%rsp)
	movq	336(%rsp), %rax
	movq	%rax, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 264(%rsp)
	xorl	%eax, %eax
	leaq	76(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	72(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	68(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	64(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	60(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	56(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 208(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 216(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 224(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 232(%rsp)
	movq	%rsp, %rax
	movq	%rax, 240(%rsp)
	leaq	344(%rsp), %rax
	movq	%rax, 248(%rsp)
	leaq	352(%rsp), %rax
	movq	%rax, 256(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 96(%rsp)
	movl	$1, 104(%rsp)
	movq	%rax, 108(%rsp)
	movl	$1, 116(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L43
	pushq	88(%rsp)
	.cfi_def_cfa_offset 296
	leaq	_Z31fuzzy_depthwise_filter_backwardiiiiiiPKiS0_S0_PKfS2_S2_Pfii(%rip), %rdi
	pushq	88(%rsp)
	.cfi_def_cfa_offset 304
	movq	124(%rsp), %rcx
	movl	132(%rsp), %r8d
	movq	112(%rsp), %rsi
	movl	120(%rsp), %edx
	leaq	160(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 296
	popq	%rdx
	.cfi_def_cfa_offset 288
.L43:
	movq	264(%rsp), %rax
	subq	%fs:40, %rax
	je	.L45
	call	__stack_chk_fail@PLT
.L45:
	addq	$280, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2046:
	.size	_Z77__device_stub__Z31fuzzy_depthwise_filter_backwardiiiiiiPKiS0_S0_PKfS2_S2_PfiiiiiiiiPKiS0_S0_PKfS2_S2_Pfii, .-_Z77__device_stub__Z31fuzzy_depthwise_filter_backwardiiiiiiPKiS0_S0_PKfS2_S2_PfiiiiiiiiPKiS0_S0_PKfS2_S2_Pfii
	.globl	_Z31fuzzy_depthwise_filter_backwardiiiiiiPKiS0_S0_PKfS2_S2_Pfii
	.type	_Z31fuzzy_depthwise_filter_backwardiiiiiiPKiS0_S0_PKfS2_S2_Pfii, @function
_Z31fuzzy_depthwise_filter_backwardiiiiiiPKiS0_S0_PKfS2_S2_Pfii:
.LFB2047:
	.cfi_startproc
	endbr64
	jmp	_Z77__device_stub__Z31fuzzy_depthwise_filter_backwardiiiiiiPKiS0_S0_PKfS2_S2_PfiiiiiiiiPKiS0_S0_PKfS2_S2_Pfii
	.cfi_endproc
.LFE2047:
	.size	_Z31fuzzy_depthwise_filter_backwardiiiiiiPKiS0_S0_PKfS2_S2_Pfii, .-_Z31fuzzy_depthwise_filter_backwardiiiiiiPKiS0_S0_PKfS2_S2_Pfii
	.globl	_Z32fuzzyDepthwiseConv3dGradLauncheriiiiiiiPKiS0_S0_PKfS2_S2_S2_PfS3_
	.type	_Z32fuzzyDepthwiseConv3dGradLauncheriiiiiiiPKiS0_S0_PKfS2_S2_S2_PfS3_, @function
_Z32fuzzyDepthwiseConv3dGradLauncheriiiiiiiPKiS0_S0_PKfS2_S2_S2_PfS3_:
.LFB2011:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movl	%edi, %r12d
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movl	%ecx, %ebx
	movl	$1, %ecx
	subq	$104, %rsp
	.cfi_def_cfa_offset 160
	movl	160(%rsp), %eax
	movq	208(%rsp), %r10
	movl	%esi, 12(%rsp)
	movq	224(%rsp), %r11
	movl	%edx, 16(%rsp)
	movl	$4194305, %edx
	movl	%eax, 20(%rsp)
	movq	176(%rsp), %rax
	salq	$10, %rdx
	movq	%r10, 56(%rsp)
	movq	168(%rsp), %rbp
	movq	%rax, 24(%rsp)
	movq	184(%rsp), %rax
	movq	%r11, 40(%rsp)
	movq	192(%rsp), %r13
	movl	%r8d, 4(%rsp)
	movq	200(%rsp), %r14
	xorl	%r8d, %r8d
	movl	%r9d, 8(%rsp)
	movq	216(%rsp), %r15
	xorl	%r9d, %r9d
	movq	%rax, 32(%rsp)
	movq	232(%rsp), %rax
	movl	%edi, 72(%rsp)
	movq	%rax, 48(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 76(%rsp)
	movq	72(%rsp), %rdi
	movl	80(%rsp), %esi
	movq	%rdx, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPushCallConfiguration@PLT
	movq	40(%rsp), %r11
	movq	56(%rsp), %r10
	testl	%eax, %eax
	jne	.L49
	pushq	%r11
	.cfi_def_cfa_offset 168
	movl	%r12d, %edi
	pushq	%r15
	.cfi_def_cfa_offset 176
	pushq	%r10
	.cfi_def_cfa_offset 184
	pushq	%r14
	.cfi_def_cfa_offset 192
	pushq	%r13
	.cfi_def_cfa_offset 200
	pushq	72(%rsp)
	.cfi_def_cfa_offset 208
	pushq	72(%rsp)
	.cfi_def_cfa_offset 216
	pushq	%rbp
	.cfi_def_cfa_offset 224
	movl	84(%rsp), %r9d
	movl	72(%rsp), %r8d
	movl	68(%rsp), %ecx
	movl	80(%rsp), %edx
	movl	76(%rsp), %esi
	call	_Z77__device_stub__Z30fuzzy_depthwise_input_backwardiiiiiiPKiS0_S0_PKfS2_S2_S2_PfiiiiiiPKiS0_S0_PKfS2_S2_S2_Pf
	addq	$64, %rsp
	.cfi_def_cfa_offset 160
.L49:
	movl	4(%rsp), %eax
	imull	%ebx, %eax
	movl	8(%rsp), %ebx
	imull	%ebx, %eax
	movl	$12288, %ebx
	cltd
	idivl	%ebx
	xorl	%ebx, %ebx
	movl	%edx, 40(%rsp)
	movl	%eax, 56(%rsp)
.L50:
	movl	56(%rsp), %eax
	cmpl	%eax, %ebx
	jge	.L56
	movl	$4194305, %eax
	movl	%r12d, 72(%rsp)
	movl	$4194305, %edx
	xorl	%r9d, %r9d
	salq	$10, %rax
	salq	$10, %rdx
	movl	$49152, %r8d
	movl	$1, %ecx
	movq	%rax, 84(%rsp)
	subq	$1023, %rax
	movq	%rax, 76(%rsp)
	movq	72(%rsp), %rdi
	movl	80(%rsp), %esi
	movl	$1, 92(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L51
	pushq	%rax
	.cfi_def_cfa_offset 168
	imull	$12288, %ebx, %eax
	movl	%r12d, %edi
	pushq	%rax
	.cfi_def_cfa_offset 176
	pushq	$12288
	.cfi_def_cfa_offset 184
	pushq	72(%rsp)
	.cfi_def_cfa_offset 192
	pushq	%r15
	.cfi_def_cfa_offset 200
	pushq	%r14
	.cfi_def_cfa_offset 208
	pushq	%r13
	.cfi_def_cfa_offset 216
	pushq	88(%rsp)
	.cfi_def_cfa_offset 224
	pushq	88(%rsp)
	.cfi_def_cfa_offset 232
	pushq	%rbp
	.cfi_def_cfa_offset 240
	movl	100(%rsp), %r9d
	movl	88(%rsp), %r8d
	movl	84(%rsp), %ecx
	movl	96(%rsp), %edx
	movl	92(%rsp), %esi
	call	_Z77__device_stub__Z31fuzzy_depthwise_filter_backwardiiiiiiPKiS0_S0_PKfS2_S2_PfiiiiiiiiPKiS0_S0_PKfS2_S2_Pfii
	addq	$80, %rsp
	.cfi_def_cfa_offset 160
.L51:
	incl	%ebx
	jmp	.L50
.L56:
	cmpl	$0, 40(%rsp)
	jle	.L48
	movl	%r12d, 72(%rsp)
	movl	$4194305, %edx
	xorl	%r9d, %r9d
	movl	$1, %ecx
	movabsq	$4294967297, %rax
	salq	$10, %rdx
	movl	$1, 92(%rsp)
	movq	%rax, 76(%rsp)
	movslq	40(%rsp), %rax
	movq	72(%rsp), %rdi
	movl	80(%rsp), %esi
	movq	%rdx, 84(%rsp)
	leaq	0(,%rax,4), %r8
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L48
	movq	%r14, 192(%rsp)
	movl	20(%rsp), %r9d
	movl	%r12d, %edi
	imull	$12288, 56(%rsp), %eax
	movq	%r13, 184(%rsp)
	movl	4(%rsp), %ecx
	movl	16(%rsp), %edx
	movq	%rbp, 160(%rsp)
	movq	%r15, 200(%rsp)
	movl	8(%rsp), %r8d
	movl	%eax, 224(%rsp)
	movl	40(%rsp), %eax
	movl	12(%rsp), %esi
	movl	%eax, 216(%rsp)
	movq	48(%rsp), %rax
	movq	%rax, 208(%rsp)
	movq	32(%rsp), %rax
	movq	%rax, 176(%rsp)
	movq	24(%rsp), %rax
	movq	%rax, 168(%rsp)
	addq	$104, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	_Z77__device_stub__Z31fuzzy_depthwise_filter_backwardiiiiiiPKiS0_S0_PKfS2_S2_PfiiiiiiiiPKiS0_S0_PKfS2_S2_Pfii
.L48:
	.cfi_restore_state
	addq	$104, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2011:
	.size	_Z32fuzzyDepthwiseConv3dGradLauncheriiiiiiiPKiS0_S0_PKfS2_S2_S2_PfS3_, .-_Z32fuzzyDepthwiseConv3dGradLauncheriiiiiiiPKiS0_S0_PKfS2_S2_S2_PfS3_
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z31fuzzy_depthwise_filter_backwardiiiiiiPKiS0_S0_PKfS2_S2_Pfii"
.LC1:
	.string	"_Z30fuzzy_depthwise_input_backwardiiiiiiPKiS0_S0_PKfS2_S2_S2_Pf"
.LC2:
	.string	"_Z30fuzzy_depthwise_conv3d_forwardiiiiiiPKiS0_S0_PKfS2_S2_Pf"
.LC3:
	.string	"_Z25depthwise_filter_backwardiiiiiiPKiS0_S0_PKfS2_Pfii"
.LC4:
	.string	"_Z24depthwise_input_backwardiiiiiiPKiS0_S0_PKfS2_S2_Pf"
.LC5:
	.string	"_Z24depthwise_conv3d_forwardiiiiiiPKiS0_S0_PKfS2_Pf"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2049:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z31fuzzy_depthwise_filter_backwardiiiiiiPKiS0_S0_PKfS2_S2_Pfii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC1(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z30fuzzy_depthwise_input_backwardiiiiiiPKiS0_S0_PKfS2_S2_S2_Pf(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC2(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z30fuzzy_depthwise_conv3d_forwardiiiiiiPKiS0_S0_PKfS2_S2_Pf(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC3(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z25depthwise_filter_backwardiiiiiiPKiS0_S0_PKfS2_Pfii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC4(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z24depthwise_input_backwardiiiiiiPKiS0_S0_PKfS2_S2_Pf(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC5(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z24depthwise_conv3d_forwardiiiiiiPKiS0_S0_PKfS2_Pf(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2049:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
// nnIndex: B*M*K;
// nnCount: B*M;
// input:   B*N*C;
// filter:  filter_size*C*r;
// output:  B*M*(C*r)
__global__ void depthwise_conv3d_forward(int B, int N, int M, int C, int r, int K, const int* nnIndex,
                                         const int* nnCount, const int* binIndex, const float* input,
                                         const float* filter, float* output)
{
    for(int i=blockIdx.x;i<B;i+=gridDim.x)
    {
        for(int j=blockIdx.y*blockDim.x+threadIdx.x;j<M*(C*r);j+=blockDim.x*gridDim.y)
        {
            int cout = j%(C*r); // output channel ID
            int cin = cout/r;   // input channel ID
            int m = j/(C*r);    // output point ID
            int nnSize = nnCount[i*M+m];

            for(int k=0;k<nnSize;k++)
            {
                int n = nnIndex[i*M*K+m*K+k];   // input point ID
                int f = binIndex[i*M*K+m*K+k];

                output[i*M*C*r+j] += input[i*N*C+n*C+cin]*filter[f*C*r+cout]/nnSize;
            }
        }
    }
}


__global__ void depthwise_input_backward(int B, int N, int M, int C, int r, int K, const int* nnIndex,
                                         const int* nnCount, const int* binIndex, const float* input,
                                         const float* filter, const float* gradOutput, float* gradInput)
{
    for(int i=blockIdx.x;i<B;i+=gridDim.x)
    {
        for(int j=blockIdx.y*blockDim.x+threadIdx.x;j<M*(C*r);j+=blockDim.x*gridDim.y)
        {
            int cout = j%(C*r); // output channel ID
            int cin = cout/r;   // input channel ID
            int m = j/(C*r);    // output point ID
            int nnSize = nnCount[i*M+m];

            for(int k=0;k<nnSize;k++)
            {
                int n = nnIndex[i*M*K+m*K+k];   // input point ID
                int f = binIndex[i*M*K+m*K+k];

                float derIn = gradOutput[i*M*C*r+j]*filter[f*C*r+cout]/nnSize;
                atomicAdd(&gradInput[i*N*C+n*C+cin],derIn);
            }
        }
    }
}


__global__ void depthwise_filter_backward(int B, int N, int M, int C, int r, int K, const int* nnIndex,
                                          const int* nnCount, const int* binIndex, const float* input,
                                          const float* gradOutput, float* gradFilter, int sharedMemSize,
                                          int startIdx)
{
    extern __shared__ float gradPerBlock[]; // the gradient on each block
    for (int i=threadIdx.x;i<sharedMemSize;i+=blockDim.x)
    {
        gradPerBlock[i] = 0; // for 1D block
    }
    __syncthreads();

    int endIdx = sharedMemSize+startIdx;
    for(int i=blockIdx.x;i<B;i+=gridDim.x)
    {
        for(int j=blockIdx.y*blockDim.x+threadIdx.x;j<M*(C*r);j+=blockDim.x*gridDim.y)
        {
            int cout = j%(C*r); // output channel ID
            int cin = cout/r;   // input channel ID
            int m = j/(C*r);    // output point ID
            int nnSize = nnCount[i*M+m];

            for(int k=0;k<nnSize;k++)
            {
                int n = nnIndex[i*M*K+m*K+k];   // input point ID
                int f = binIndex[i*M*K+m*K+k];

                float derFilt = gradOutput[i*M*C*r+j]*input[i*N*C+n*C+cin]/nnSize;

                int currIdx = f*C*r+cout;
                if((currIdx>=startIdx) && (currIdx<endIdx)) // within the shared memory
                {
                    atomicAdd(&gradPerBlock[currIdx-startIdx],derFilt);
                }
            }
        }
    }
    __syncthreads();

    for (int i=threadIdx.x;i<sharedMemSize;i+=blockDim.x)
    {
        atomicAdd(&gradFilter[i+startIdx],gradPerBlock[i]); // for 1D block
    }
}


// nnIndex: B*M*K;
// nnCount: B*M;
// input:   B*N*C;
// filter:  filter_size*C*r;
// output:  B*M*(C*r)
__global__ void fuzzy_depthwise_conv3d_forward(int B, int N, int M, int C, int r, int K, const int* nnIndex,
                                               const int* nnCount, const int* binIndex, const float* binCoeff,
                                               const float* input, const float* filter, float* output)
{
    // T is the number of fuzzy bins each neighbor locates in
    const int T = 4;

    for(int i=blockIdx.x;i<B;i+=gridDim.x)
    {
        for(int j=blockIdx.y*blockDim.x+threadIdx.x;j<M*(C*r);j+=blockDim.x*gridDim.y)
        {
            int cout = j%(C*r); // output channel ID
            int cin = cout/r;   // input channel ID
            int m = j/(C*r);    // output point ID
            int nnSize = nnCount[i*M+m];

            for(int k=0;k<nnSize;k++)
            {
                int n = nnIndex[i*M*K+m*K+k];   // input point ID

                float weight = 0;
                for(int idx=0;idx<T;idx++)
                {
                    int f = binIndex[i*M*K*T+m*K*T+k*T+idx];
                    float coeff = binCoeff[i*M*K*T+m*K*T+k*T+idx];

                    if (coeff>0)
                    {
                        weight += coeff*filter[f*C*r+cout];
                    }
                }

                output[i*M*C*r+j] += input[i*N*C+n*C+cin]*weight/nnSize;
            }
        }
    }
}


__global__ void fuzzy_depthwise_input_backward(int B, int N, int M, int C, int r, int K,
                                               const int* nnIndex, const int* nnCount, const int* binIndex,
                                               const float* binCoeff, const float* input, const float* filter,
                                               const float* gradOutput, float* gradInput)
{
    const int T = 4;

    for(int i=blockIdx.x;i<B;i+=gridDim.x)
    {
        for(int j=blockIdx.y*blockDim.x+threadIdx.x;j<M*(C*r);j+=blockDim.x*gridDim.y)
        {
            int cout = j%(C*r); // output channel ID
            int cin = cout/r;   // input channel ID
            int m = j/(C*r);    // output point ID
            int nnSize = nnCount[i*M+m];

            for(int k=0;k<nnSize;k++)
            {
                int n = nnIndex[i*M*K+m*K+k];   // input point ID

                float weight = 0;
                for(int idx=0;idx<T;idx++)
                {
                    int f = binIndex[i*M*K*T+m*K*T+k*T+idx];
                    float coeff = binCoeff[i*M*K*T+m*K*T+k*T+idx];

                    if (coeff>0)
                    {
                        weight += coeff*filter[f*C*r+cout];
                    }
                }

                float derIn = gradOutput[i*M*C*r+j]*weight/nnSize;
                atomicAdd(&gradInput[i*N*C+n*C+cin],derIn);
            }
        }
    }
}


__global__ void fuzzy_depthwise_filter_backward(int B, int N, int M, int C, int r, int K, const int* nnIndex,
                                                const int* nnCount, const int* binIndex, const float* binCoeff,
                                                const float* input, const float* gradOutput, float* gradFilter,
                                                int sharedMemSize, int startIdx)
{
    const int T = 4;

    extern __shared__ float gradPerBlock[]; // the gradient on each block
    for (int i=threadIdx.x;i<sharedMemSize;i+=blockDim.x)
    {
        gradPerBlock[i] = 0; // for 1D block
    }
    __syncthreads();

    int endIdx = sharedMemSize+startIdx;
    for(int i=blockIdx.x;i<B;i+=gridDim.x)
    {
        for(int j=blockIdx.y*blockDim.x+threadIdx.x;j<M*(C*r);j+=blockDim.x*gridDim.y)
        {
            int cout = j%(C*r); // output channel ID
            int cin = cout/r;   // input channel ID
            int m = j/(C*r);    // output point ID
            int nnSize = nnCount[i*M+m];

            for(int k=0;k<nnSize;k++)
            {
                int n = nnIndex[i*M*K+m*K+k];   // input point ID
                float derFilt = gradOutput[i*M*C*r+j]*input[i*N*C+n*C+cin]/nnSize;

                for(int idx=0;idx<T;idx++)
                {
                    int f = binIndex[i*M*K*T+m*K*T+k*T+idx];
                    float coeff = binCoeff[i*M*K*T+m*K*T+k*T+idx];

                    if (coeff>0)
                    {
                        int currIdx = f*C*r+cout;
                        if((currIdx>=startIdx) && (currIdx<endIdx)) // within the shared memory
                        {
                            atomicAdd(&gradPerBlock[currIdx-startIdx],coeff*derFilt);
                        }
                    }
                }
            }
        }
    }
    __syncthreads();

    for (int i=threadIdx.x;i<sharedMemSize;i+=blockDim.x)
    {
        atomicAdd(&gradFilter[i+startIdx],gradPerBlock[i]); // for 1D block
    }
}




void depthwiseConv3dLauncher(int B, int N, int M, int C, int r, int K, const int* nnIndex,
                             const int* nnCount, const int* binIndex, const float* input,
                             const float* filter, float* output)
{
    depthwise_conv3d_forward<<<B,1024>>>(B, N, M, C, r, K, nnIndex, nnCount, binIndex,
                                          input, filter, output);
}

void depthwiseConv3dGradLauncher(int B, int N, int M, int F, int C, int r, int K,
                                 const int* nnIndex, const int* nnCount, const int* binIndex,
                                 const float* input,  const float* filter, const float* gradOutput,
                                 float* gradInput, float* gradFilter)
{
    // titan xp has shared memory of 49152 bytes, each float value takes 4 bytes in the memory
    int maxSharedMemSize = int(49152/sizeof(float));

    depthwise_input_backward<<<B,1024>>>(B, N, M, C, r, K, nnIndex, nnCount, binIndex,
                                          input, filter, gradOutput, gradInput);

    int maxIter = (F*C*r)/maxSharedMemSize;
    int remainder = (F*C*r)%maxSharedMemSize;
    for(int iter=0;iter<maxIter;iter++)
    {
        depthwise_filter_backward<<<B,1024,sizeof(float)*maxSharedMemSize>>>(B, N, M, C, r, K, nnIndex, nnCount,
                                                                             binIndex, input, gradOutput, gradFilter,
                                                                             maxSharedMemSize, maxSharedMemSize*iter);
    }
    if(remainder>0) // fill the remainder
    {
        depthwise_filter_backward<<<B,1024,sizeof(float)*remainder>>>(B, N, M, C, r, K, nnIndex, nnCount,
                                                                      binIndex, input, gradOutput, gradFilter,
                                                                      remainder, maxSharedMemSize*maxIter);
    }
}


void fuzzyDepthwiseConv3dLauncher(int B, int N, int M, int C, int r, int K, const int* nnIndex,
                                  const int* nnCount, const int* binIndex, const float* binCoeff,
                                  const float* input, const float* filter, float* output)
{
    fuzzy_depthwise_conv3d_forward<<<B,1024>>>(B, N, M, C, r, K, nnIndex, nnCount, binIndex,
                                               binCoeff, input, filter, output);
}

void fuzzyDepthwiseConv3dGradLauncher(int B, int N, int M, int F, int C, int r, int K, const int* nnIndex,
                                      const int* nnCount, const int* binIndex, const float* binCoeff,
                                      const float* input,  const float* filter, const float* gradOutput,
                                      float* gradInput, float* gradFilter)
{
    // titan xp has shared memory of 49152 bytes, each float value takes 4 bytes in the memory
    int maxSharedMemSize = int(49152/sizeof(float));

    fuzzy_depthwise_input_backward<<<B,1024>>>(B, N, M, C, r, K, nnIndex, nnCount, binIndex, binCoeff,
                                               input, filter, gradOutput, gradInput);

    int maxIter = (F*C*r)/maxSharedMemSize;
    int remainder = (F*C*r)%maxSharedMemSize;
    for(int iter=0;iter<maxIter;iter++)
    {
        fuzzy_depthwise_filter_backward<<<B,1024,sizeof(float)*maxSharedMemSize>>>(B, N, M, C, r, K, nnIndex, nnCount,
                                                                                   binIndex, binCoeff, input, gradOutput,
                                                                                   gradFilter, maxSharedMemSize,
                                                                                   maxSharedMemSize*iter);
    }
    if(remainder>0) // fill the remainder
    {
        fuzzy_depthwise_filter_backward<<<B,1024,sizeof(float)*remainder>>>(B, N, M, C, r, K, nnIndex, nnCount,
                                                                            binIndex, binCoeff, input, gradOutput,
                                                                            gradFilter, remainder,
                                                                            maxSharedMemSize*maxIter);
    }
}
	.text
	.file	"tf_conv3d_gpu.hip"
	.globl	_Z39__device_stub__depthwise_conv3d_forwardiiiiiiPKiS0_S0_PKfS2_Pf # -- Begin function _Z39__device_stub__depthwise_conv3d_forwardiiiiiiPKiS0_S0_PKfS2_Pf
	.type	_Z39__device_stub__depthwise_conv3d_forwardiiiiiiPKiS0_S0_PKfS2_Pf,@function
_Z39__device_stub__depthwise_conv3d_forwardiiiiiiPKiS0_S0_PKfS2_Pf: # @_Z39__device_stub__depthwise_conv3d_forwardiiiiiiPKiS0_S0_PKfS2_Pf
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$176, %rsp
	.cfi_def_cfa_offset 224
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	28(%rsp), %rax
	movl	%edi, (%rax)
	leaq	24(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	20(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	16(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	12(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	8(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	224(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	232(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	240(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	248(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	256(%rsp), %rax
	movq	%rax, 80(%rbx)
	leaq	264(%rsp), %rax
	movq	%rax, 88(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	40(%rsp), %r12
	leaq	32(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z24depthwise_conv3d_forwardiiiiiiPKiS0_S0_PKfS2_Pf, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$192, %rsp
	.cfi_adjust_cfa_offset -192
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z39__device_stub__depthwise_conv3d_forwardiiiiiiPKiS0_S0_PKfS2_Pf, .Lfunc_end0-_Z39__device_stub__depthwise_conv3d_forwardiiiiiiPKiS0_S0_PKfS2_Pf
	.cfi_endproc
                                        # -- End function
	.globl	_Z39__device_stub__depthwise_input_backwardiiiiiiPKiS0_S0_PKfS2_S2_Pf # -- Begin function _Z39__device_stub__depthwise_input_backwardiiiiiiPKiS0_S0_PKfS2_S2_Pf
	.type	_Z39__device_stub__depthwise_input_backwardiiiiiiPKiS0_S0_PKfS2_S2_Pf,@function
_Z39__device_stub__depthwise_input_backwardiiiiiiPKiS0_S0_PKfS2_S2_Pf: # @_Z39__device_stub__depthwise_input_backwardiiiiiiPKiS0_S0_PKfS2_S2_Pf
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$192, %rsp
	.cfi_def_cfa_offset 240
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	28(%rsp), %rax
	movl	%edi, (%rax)
	leaq	24(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	20(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	16(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	12(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	8(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	240(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	248(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	256(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	264(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	272(%rsp), %rax
	movq	%rax, 80(%rbx)
	leaq	280(%rsp), %rax
	movq	%rax, 88(%rbx)
	leaq	288(%rsp), %rax
	movq	%rax, 96(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	40(%rsp), %r12
	leaq	32(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z24depthwise_input_backwardiiiiiiPKiS0_S0_PKfS2_S2_Pf, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$208, %rsp
	.cfi_adjust_cfa_offset -208
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z39__device_stub__depthwise_input_backwardiiiiiiPKiS0_S0_PKfS2_S2_Pf, .Lfunc_end1-_Z39__device_stub__depthwise_input_backwardiiiiiiPKiS0_S0_PKfS2_S2_Pf
	.cfi_endproc
                                        # -- End function
	.globl	_Z40__device_stub__depthwise_filter_backwardiiiiiiPKiS0_S0_PKfS2_Pfii # -- Begin function _Z40__device_stub__depthwise_filter_backwardiiiiiiPKiS0_S0_PKfS2_Pfii
	.type	_Z40__device_stub__depthwise_filter_backwardiiiiiiPKiS0_S0_PKfS2_Pfii,@function
_Z40__device_stub__depthwise_filter_backwardiiiiiiPKiS0_S0_PKfS2_Pfii: # @_Z40__device_stub__depthwise_filter_backwardiiiiiiPKiS0_S0_PKfS2_Pfii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$192, %rsp
	.cfi_def_cfa_offset 240
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	28(%rsp), %rax
	movl	%edi, (%rax)
	leaq	24(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	20(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	16(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	12(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	8(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	240(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	248(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	256(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	264(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	272(%rsp), %rax
	movq	%rax, 80(%rbx)
	leaq	280(%rsp), %rax
	movq	%rax, 88(%rbx)
	leaq	288(%rsp), %rax
	movq	%rax, 96(%rbx)
	leaq	296(%rsp), %rax
	movq	%rax, 104(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	40(%rsp), %r12
	leaq	32(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z25depthwise_filter_backwardiiiiiiPKiS0_S0_PKfS2_Pfii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$208, %rsp
	.cfi_adjust_cfa_offset -208
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z40__device_stub__depthwise_filter_backwardiiiiiiPKiS0_S0_PKfS2_Pfii, .Lfunc_end2-_Z40__device_stub__depthwise_filter_backwardiiiiiiPKiS0_S0_PKfS2_Pfii
	.cfi_endproc
                                        # -- End function
	.globl	_Z45__device_stub__fuzzy_depthwise_conv3d_forwardiiiiiiPKiS0_S0_PKfS2_S2_Pf # -- Begin function _Z45__device_stub__fuzzy_depthwise_conv3d_forwardiiiiiiPKiS0_S0_PKfS2_S2_Pf
	.type	_Z45__device_stub__fuzzy_depthwise_conv3d_forwardiiiiiiPKiS0_S0_PKfS2_S2_Pf,@function
_Z45__device_stub__fuzzy_depthwise_conv3d_forwardiiiiiiPKiS0_S0_PKfS2_S2_Pf: # @_Z45__device_stub__fuzzy_depthwise_conv3d_forwardiiiiiiPKiS0_S0_PKfS2_S2_Pf
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$192, %rsp
	.cfi_def_cfa_offset 240
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	28(%rsp), %rax
	movl	%edi, (%rax)
	leaq	24(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	20(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	16(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	12(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	8(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	240(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	248(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	256(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	264(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	272(%rsp), %rax
	movq	%rax, 80(%rbx)
	leaq	280(%rsp), %rax
	movq	%rax, 88(%rbx)
	leaq	288(%rsp), %rax
	movq	%rax, 96(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	40(%rsp), %r12
	leaq	32(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z30fuzzy_depthwise_conv3d_forwardiiiiiiPKiS0_S0_PKfS2_S2_Pf, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$208, %rsp
	.cfi_adjust_cfa_offset -208
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	_Z45__device_stub__fuzzy_depthwise_conv3d_forwardiiiiiiPKiS0_S0_PKfS2_S2_Pf, .Lfunc_end3-_Z45__device_stub__fuzzy_depthwise_conv3d_forwardiiiiiiPKiS0_S0_PKfS2_S2_Pf
	.cfi_endproc
                                        # -- End function
	.globl	_Z45__device_stub__fuzzy_depthwise_input_backwardiiiiiiPKiS0_S0_PKfS2_S2_S2_Pf # -- Begin function _Z45__device_stub__fuzzy_depthwise_input_backwardiiiiiiPKiS0_S0_PKfS2_S2_S2_Pf
	.type	_Z45__device_stub__fuzzy_depthwise_input_backwardiiiiiiPKiS0_S0_PKfS2_S2_S2_Pf,@function
_Z45__device_stub__fuzzy_depthwise_input_backwardiiiiiiPKiS0_S0_PKfS2_S2_S2_Pf: # @_Z45__device_stub__fuzzy_depthwise_input_backwardiiiiiiPKiS0_S0_PKfS2_S2_S2_Pf
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$192, %rsp
	.cfi_def_cfa_offset 240
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	28(%rsp), %rax
	movl	%edi, (%rax)
	leaq	24(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	20(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	16(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	12(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	8(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	240(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	248(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	256(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	264(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	272(%rsp), %rax
	movq	%rax, 80(%rbx)
	leaq	280(%rsp), %rax
	movq	%rax, 88(%rbx)
	leaq	288(%rsp), %rax
	movq	%rax, 96(%rbx)
	leaq	296(%rsp), %rax
	movq	%rax, 104(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	40(%rsp), %r12
	leaq	32(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z30fuzzy_depthwise_input_backwardiiiiiiPKiS0_S0_PKfS2_S2_S2_Pf, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$208, %rsp
	.cfi_adjust_cfa_offset -208
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end4:
	.size	_Z45__device_stub__fuzzy_depthwise_input_backwardiiiiiiPKiS0_S0_PKfS2_S2_S2_Pf, .Lfunc_end4-_Z45__device_stub__fuzzy_depthwise_input_backwardiiiiiiPKiS0_S0_PKfS2_S2_S2_Pf
	.cfi_endproc
                                        # -- End function
	.globl	_Z46__device_stub__fuzzy_depthwise_filter_backwardiiiiiiPKiS0_S0_PKfS2_S2_Pfii # -- Begin function _Z46__device_stub__fuzzy_depthwise_filter_backwardiiiiiiPKiS0_S0_PKfS2_S2_Pfii
	.type	_Z46__device_stub__fuzzy_depthwise_filter_backwardiiiiiiPKiS0_S0_PKfS2_S2_Pfii,@function
_Z46__device_stub__fuzzy_depthwise_filter_backwardiiiiiiPKiS0_S0_PKfS2_S2_Pfii: # @_Z46__device_stub__fuzzy_depthwise_filter_backwardiiiiiiPKiS0_S0_PKfS2_S2_Pfii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$208, %rsp
	.cfi_def_cfa_offset 256
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	28(%rsp), %rax
	movl	%edi, (%rax)
	leaq	24(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	20(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	16(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	12(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	8(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	256(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	264(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	272(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	280(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	288(%rsp), %rax
	movq	%rax, 80(%rbx)
	leaq	296(%rsp), %rax
	movq	%rax, 88(%rbx)
	leaq	304(%rsp), %rax
	movq	%rax, 96(%rbx)
	leaq	312(%rsp), %rax
	movq	%rax, 104(%rbx)
	leaq	320(%rsp), %rax
	movq	%rax, 112(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	40(%rsp), %r12
	leaq	32(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z31fuzzy_depthwise_filter_backwardiiiiiiPKiS0_S0_PKfS2_S2_Pfii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$224, %rsp
	.cfi_adjust_cfa_offset -224
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end5:
	.size	_Z46__device_stub__fuzzy_depthwise_filter_backwardiiiiiiPKiS0_S0_PKfS2_S2_Pfii, .Lfunc_end5-_Z46__device_stub__fuzzy_depthwise_filter_backwardiiiiiiPKiS0_S0_PKfS2_S2_Pfii
	.cfi_endproc
                                        # -- End function
	.globl	_Z23depthwiseConv3dLauncheriiiiiiPKiS0_S0_PKfS2_Pf # -- Begin function _Z23depthwiseConv3dLauncheriiiiiiPKiS0_S0_PKfS2_Pf
	.type	_Z23depthwiseConv3dLauncheriiiiiiPKiS0_S0_PKfS2_Pf,@function
_Z23depthwiseConv3dLauncheriiiiiiPKiS0_S0_PKfS2_Pf: # @_Z23depthwiseConv3dLauncheriiiiiiPKiS0_S0_PKfS2_Pf
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	pushq	%rax
	.cfi_def_cfa_offset 64
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%r9d, %ebx
	movl	%r8d, %ebp
	movl	%ecx, %r14d
	movl	%edx, %r15d
	movl	%esi, %r12d
	movl	%edi, %r13d
	movl	%edi, %edi
	btsq	$32, %rdi
	movabsq	$4294967296, %rdx               # imm = 0x100000000
	orq	$1024, %rdx                     # imm = 0x400
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	je	.LBB6_2
# %bb.1:
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB6_2:
	.cfi_def_cfa_offset 64
	movl	%r13d, %edi
	movl	%r12d, %esi
	movl	%r15d, %edx
	movl	%r14d, %ecx
	movl	%ebp, %r8d
	movl	%ebx, %r9d
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z39__device_stub__depthwise_conv3d_forwardiiiiiiPKiS0_S0_PKfS2_Pf # TAILCALL
.Lfunc_end6:
	.size	_Z23depthwiseConv3dLauncheriiiiiiPKiS0_S0_PKfS2_Pf, .Lfunc_end6-_Z23depthwiseConv3dLauncheriiiiiiPKiS0_S0_PKfS2_Pf
	.cfi_endproc
                                        # -- End function
	.globl	_Z27depthwiseConv3dGradLauncheriiiiiiiPKiS0_S0_PKfS2_S2_PfS3_ # -- Begin function _Z27depthwiseConv3dGradLauncheriiiiiiiPKiS0_S0_PKfS2_S2_PfS3_
	.type	_Z27depthwiseConv3dGradLauncheriiiiiiiPKiS0_S0_PKfS2_S2_PfS3_,@function
_Z27depthwiseConv3dGradLauncheriiiiiiiPKiS0_S0_PKfS2_S2_PfS3_: # @_Z27depthwiseConv3dGradLauncheriiiiiiiPKiS0_S0_PKfS2_S2_PfS3_
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$40, %rsp
	.cfi_def_cfa_offset 96
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%r9d, %ebx
	movl	%r8d, %ebp
	movl	%ecx, %r15d
	movl	%edx, 20(%rsp)                  # 4-byte Spill
	movl	%esi, 16(%rsp)                  # 4-byte Spill
	movabsq	$4294968320, %r13               # imm = 0x100000400
	movl	%edi, 12(%rsp)                  # 4-byte Spill
	movl	%edi, %eax
	leaq	-1024(%rax,%r13), %r14
	movq	%r14, %rdi
	movl	$1, %esi
	movq	%r13, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB7_2
# %bb.1:
	subq	$8, %rsp
	.cfi_adjust_cfa_offset 8
	movl	20(%rsp), %edi                  # 4-byte Reload
	movl	24(%rsp), %esi                  # 4-byte Reload
	movl	28(%rsp), %edx                  # 4-byte Reload
	movl	%ebp, %ecx
	movl	%ebx, %r8d
	movl	104(%rsp), %r9d
	pushq	160(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	160(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	160(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	160(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	160(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	160(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	160(%rsp)
	.cfi_adjust_cfa_offset 8
	callq	_Z39__device_stub__depthwise_input_backwardiiiiiiPKiS0_S0_PKfS2_S2_Pf
	addq	$64, %rsp
	.cfi_adjust_cfa_offset -64
.LBB7_2:
	movl	%ebp, %r12d
	imull	%ebp, %r15d
	movl	%ebx, %ebp
	imull	%ebx, %r15d
	movslq	%r15d, %rax
	imulq	$715827883, %rax, %r15          # imm = 0x2AAAAAAB
	movq	%r15, %rcx
	shrq	$63, %rcx
	sarq	$43, %r15
	addl	%ecx, %r15d
	movl	%r15d, %ecx
	shll	$12, %ecx
	movq	%rcx, 24(%rsp)                  # 8-byte Spill
	leal	(%rcx,%rcx,2), %ecx
	movl	%eax, %edx
	subl	%ecx, %edx
	movq	%rdx, 32(%rsp)                  # 8-byte Spill
	cmpl	$12288, %eax                    # imm = 0x3000
	jl	.LBB7_7
# %bb.3:                                # %.lr.ph.preheader
	xorl	%ebx, %ebx
.LBB7_4:                                # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	movl	$49152, %r8d                    # imm = 0xC000
	movq	%r14, %rdi
	movl	$1, %esi
	movq	%r13, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB7_6
# %bb.5:                                #   in Loop: Header=BB7_4 Depth=1
	movl	12(%rsp), %edi                  # 4-byte Reload
	movl	16(%rsp), %esi                  # 4-byte Reload
	movl	20(%rsp), %edx                  # 4-byte Reload
	movl	%r12d, %ecx
	movl	%ebp, %r8d
	movl	96(%rsp), %r9d
	pushq	%rbx
	.cfi_adjust_cfa_offset 8
	pushq	$12288                          # imm = 0x3000
	.cfi_adjust_cfa_offset 8
	pushq	176(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	168(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	160(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	160(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	160(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	160(%rsp)
	.cfi_adjust_cfa_offset 8
	callq	_Z40__device_stub__depthwise_filter_backwardiiiiiiPKiS0_S0_PKfS2_Pfii
	addq	$64, %rsp
	.cfi_adjust_cfa_offset -64
.LBB7_6:                                #   in Loop: Header=BB7_4 Depth=1
	addl	$12288, %ebx                    # imm = 0x3000
	decl	%r15d
	jne	.LBB7_4
.LBB7_7:                                # %._crit_edge
	movq	32(%rsp), %rbx                  # 8-byte Reload
	testl	%ebx, %ebx
	jle	.LBB7_10
# %bb.8:
	movl	%ebx, %r8d
	shlq	$2, %r8
	movq	%r14, %rdi
	movl	$1, %esi
	movq	%r13, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	je	.LBB7_9
.LBB7_10:
	addq	$40, %rsp
	.cfi_def_cfa_offset 56
	jmp	.LBB7_11
.LBB7_9:
	.cfi_def_cfa_offset 96
	movq	24(%rsp), %rax                  # 8-byte Reload
	leal	(%rax,%rax,2), %eax
	movl	12(%rsp), %edi                  # 4-byte Reload
	movl	16(%rsp), %esi                  # 4-byte Reload
	movl	20(%rsp), %edx                  # 4-byte Reload
	movl	%r12d, %ecx
	movl	%ebp, %r8d
	movl	96(%rsp), %r9d
	pushq	%rax
	.cfi_adjust_cfa_offset 8
	pushq	%rbx
	.cfi_adjust_cfa_offset 8
	pushq	176(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	168(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	160(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	160(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	160(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	160(%rsp)
	.cfi_adjust_cfa_offset 8
	callq	_Z40__device_stub__depthwise_filter_backwardiiiiiiPKiS0_S0_PKfS2_Pfii
	addq	$104, %rsp
	.cfi_adjust_cfa_offset -104
.LBB7_11:
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end7:
	.size	_Z27depthwiseConv3dGradLauncheriiiiiiiPKiS0_S0_PKfS2_S2_PfS3_, .Lfunc_end7-_Z27depthwiseConv3dGradLauncheriiiiiiiPKiS0_S0_PKfS2_S2_PfS3_
	.cfi_endproc
                                        # -- End function
	.globl	_Z28fuzzyDepthwiseConv3dLauncheriiiiiiPKiS0_S0_PKfS2_S2_Pf # -- Begin function _Z28fuzzyDepthwiseConv3dLauncheriiiiiiPKiS0_S0_PKfS2_S2_Pf
	.type	_Z28fuzzyDepthwiseConv3dLauncheriiiiiiPKiS0_S0_PKfS2_S2_Pf,@function
_Z28fuzzyDepthwiseConv3dLauncheriiiiiiPKiS0_S0_PKfS2_S2_Pf: # @_Z28fuzzyDepthwiseConv3dLauncheriiiiiiPKiS0_S0_PKfS2_S2_Pf
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	pushq	%rax
	.cfi_def_cfa_offset 64
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%r9d, %ebx
	movl	%r8d, %ebp
	movl	%ecx, %r14d
	movl	%edx, %r15d
	movl	%esi, %r12d
	movl	%edi, %r13d
	movl	%edi, %edi
	btsq	$32, %rdi
	movabsq	$4294967296, %rdx               # imm = 0x100000000
	orq	$1024, %rdx                     # imm = 0x400
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	je	.LBB8_2
# %bb.1:
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB8_2:
	.cfi_def_cfa_offset 64
	movl	%r13d, %edi
	movl	%r12d, %esi
	movl	%r15d, %edx
	movl	%r14d, %ecx
	movl	%ebp, %r8d
	movl	%ebx, %r9d
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z45__device_stub__fuzzy_depthwise_conv3d_forwardiiiiiiPKiS0_S0_PKfS2_S2_Pf # TAILCALL
.Lfunc_end8:
	.size	_Z28fuzzyDepthwiseConv3dLauncheriiiiiiPKiS0_S0_PKfS2_S2_Pf, .Lfunc_end8-_Z28fuzzyDepthwiseConv3dLauncheriiiiiiPKiS0_S0_PKfS2_S2_Pf
	.cfi_endproc
                                        # -- End function
	.globl	_Z32fuzzyDepthwiseConv3dGradLauncheriiiiiiiPKiS0_S0_PKfS2_S2_S2_PfS3_ # -- Begin function _Z32fuzzyDepthwiseConv3dGradLauncheriiiiiiiPKiS0_S0_PKfS2_S2_S2_PfS3_
	.type	_Z32fuzzyDepthwiseConv3dGradLauncheriiiiiiiPKiS0_S0_PKfS2_S2_S2_PfS3_,@function
_Z32fuzzyDepthwiseConv3dGradLauncheriiiiiiiPKiS0_S0_PKfS2_S2_S2_PfS3_: # @_Z32fuzzyDepthwiseConv3dGradLauncheriiiiiiiPKiS0_S0_PKfS2_S2_S2_PfS3_
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$40, %rsp
	.cfi_def_cfa_offset 96
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%r9d, %ebx
	movl	%r8d, %ebp
	movl	%ecx, %r15d
	movl	%edx, 20(%rsp)                  # 4-byte Spill
	movl	%esi, 16(%rsp)                  # 4-byte Spill
	movabsq	$4294968320, %r13               # imm = 0x100000400
	movl	%edi, 12(%rsp)                  # 4-byte Spill
	movl	%edi, %eax
	leaq	-1024(%rax,%r13), %r14
	movq	%r14, %rdi
	movl	$1, %esi
	movq	%r13, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB9_2
# %bb.1:
	movl	12(%rsp), %edi                  # 4-byte Reload
	movl	16(%rsp), %esi                  # 4-byte Reload
	movl	20(%rsp), %edx                  # 4-byte Reload
	movl	%ebp, %ecx
	movl	%ebx, %r8d
	movl	96(%rsp), %r9d
	pushq	160(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	160(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	160(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	160(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	160(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	160(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	160(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	160(%rsp)
	.cfi_adjust_cfa_offset 8
	callq	_Z45__device_stub__fuzzy_depthwise_input_backwardiiiiiiPKiS0_S0_PKfS2_S2_S2_Pf
	addq	$64, %rsp
	.cfi_adjust_cfa_offset -64
.LBB9_2:
	movl	%ebp, %r12d
	imull	%ebp, %r15d
	movl	%ebx, %ebp
	imull	%ebx, %r15d
	movslq	%r15d, %rax
	imulq	$715827883, %rax, %r15          # imm = 0x2AAAAAAB
	movq	%r15, %rcx
	shrq	$63, %rcx
	sarq	$43, %r15
	addl	%ecx, %r15d
	movl	%r15d, %ecx
	shll	$12, %ecx
	movq	%rcx, 24(%rsp)                  # 8-byte Spill
	leal	(%rcx,%rcx,2), %ecx
	movl	%eax, %edx
	subl	%ecx, %edx
	movq	%rdx, 32(%rsp)                  # 8-byte Spill
	cmpl	$12288, %eax                    # imm = 0x3000
	jl	.LBB9_7
# %bb.3:                                # %.lr.ph.preheader
	xorl	%ebx, %ebx
.LBB9_4:                                # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	movl	$49152, %r8d                    # imm = 0xC000
	movq	%r14, %rdi
	movl	$1, %esi
	movq	%r13, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB9_6
# %bb.5:                                #   in Loop: Header=BB9_4 Depth=1
	subq	$8, %rsp
	.cfi_adjust_cfa_offset 8
	movl	20(%rsp), %edi                  # 4-byte Reload
	movl	24(%rsp), %esi                  # 4-byte Reload
	movl	28(%rsp), %edx                  # 4-byte Reload
	movl	%r12d, %ecx
	movl	%ebp, %r8d
	movl	104(%rsp), %r9d
	pushq	%rbx
	.cfi_adjust_cfa_offset 8
	pushq	$12288                          # imm = 0x3000
	.cfi_adjust_cfa_offset 8
	pushq	192(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	184(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	176(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	176(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	176(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	176(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	176(%rsp)
	.cfi_adjust_cfa_offset 8
	callq	_Z46__device_stub__fuzzy_depthwise_filter_backwardiiiiiiPKiS0_S0_PKfS2_S2_Pfii
	addq	$80, %rsp
	.cfi_adjust_cfa_offset -80
.LBB9_6:                                #   in Loop: Header=BB9_4 Depth=1
	addl	$12288, %ebx                    # imm = 0x3000
	decl	%r15d
	jne	.LBB9_4
.LBB9_7:                                # %._crit_edge
	movq	32(%rsp), %rbx                  # 8-byte Reload
	testl	%ebx, %ebx
	jle	.LBB9_10
# %bb.8:
	movl	%ebx, %r8d
	shlq	$2, %r8
	movq	%r14, %rdi
	movl	$1, %esi
	movq	%r13, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	je	.LBB9_9
.LBB9_10:
	addq	$40, %rsp
	.cfi_def_cfa_offset 56
	jmp	.LBB9_11
.LBB9_9:
	.cfi_def_cfa_offset 96
	movq	24(%rsp), %rax                  # 8-byte Reload
	leal	(%rax,%rax,2), %eax
	subq	$8, %rsp
	.cfi_adjust_cfa_offset 8
	movl	20(%rsp), %edi                  # 4-byte Reload
	movl	24(%rsp), %esi                  # 4-byte Reload
	movl	28(%rsp), %edx                  # 4-byte Reload
	movl	%r12d, %ecx
	movl	%ebp, %r8d
	movl	104(%rsp), %r9d
	pushq	%rax
	.cfi_adjust_cfa_offset 8
	pushq	%rbx
	.cfi_adjust_cfa_offset 8
	pushq	192(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	184(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	176(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	176(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	176(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	176(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	176(%rsp)
	.cfi_adjust_cfa_offset 8
	callq	_Z46__device_stub__fuzzy_depthwise_filter_backwardiiiiiiPKiS0_S0_PKfS2_S2_Pfii
	addq	$120, %rsp
	.cfi_adjust_cfa_offset -120
.LBB9_11:
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end9:
	.size	_Z32fuzzyDepthwiseConv3dGradLauncheriiiiiiiPKiS0_S0_PKfS2_S2_S2_PfS3_, .Lfunc_end9-_Z32fuzzyDepthwiseConv3dGradLauncheriiiiiiiPKiS0_S0_PKfS2_S2_S2_PfS3_
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB10_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB10_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z24depthwise_conv3d_forwardiiiiiiPKiS0_S0_PKfS2_Pf, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z24depthwise_input_backwardiiiiiiPKiS0_S0_PKfS2_S2_Pf, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z25depthwise_filter_backwardiiiiiiPKiS0_S0_PKfS2_Pfii, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z30fuzzy_depthwise_conv3d_forwardiiiiiiPKiS0_S0_PKfS2_S2_Pf, %esi
	movl	$.L__unnamed_4, %edx
	movl	$.L__unnamed_4, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z30fuzzy_depthwise_input_backwardiiiiiiPKiS0_S0_PKfS2_S2_S2_Pf, %esi
	movl	$.L__unnamed_5, %edx
	movl	$.L__unnamed_5, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z31fuzzy_depthwise_filter_backwardiiiiiiPKiS0_S0_PKfS2_S2_Pfii, %esi
	movl	$.L__unnamed_6, %edx
	movl	$.L__unnamed_6, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end10:
	.size	__hip_module_ctor, .Lfunc_end10-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB11_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB11_2:
	retq
.Lfunc_end11:
	.size	__hip_module_dtor, .Lfunc_end11-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z24depthwise_conv3d_forwardiiiiiiPKiS0_S0_PKfS2_Pf,@object # @_Z24depthwise_conv3d_forwardiiiiiiPKiS0_S0_PKfS2_Pf
	.section	.rodata,"a",@progbits
	.globl	_Z24depthwise_conv3d_forwardiiiiiiPKiS0_S0_PKfS2_Pf
	.p2align	3, 0x0
_Z24depthwise_conv3d_forwardiiiiiiPKiS0_S0_PKfS2_Pf:
	.quad	_Z39__device_stub__depthwise_conv3d_forwardiiiiiiPKiS0_S0_PKfS2_Pf
	.size	_Z24depthwise_conv3d_forwardiiiiiiPKiS0_S0_PKfS2_Pf, 8

	.type	_Z24depthwise_input_backwardiiiiiiPKiS0_S0_PKfS2_S2_Pf,@object # @_Z24depthwise_input_backwardiiiiiiPKiS0_S0_PKfS2_S2_Pf
	.globl	_Z24depthwise_input_backwardiiiiiiPKiS0_S0_PKfS2_S2_Pf
	.p2align	3, 0x0
_Z24depthwise_input_backwardiiiiiiPKiS0_S0_PKfS2_S2_Pf:
	.quad	_Z39__device_stub__depthwise_input_backwardiiiiiiPKiS0_S0_PKfS2_S2_Pf
	.size	_Z24depthwise_input_backwardiiiiiiPKiS0_S0_PKfS2_S2_Pf, 8

	.type	_Z25depthwise_filter_backwardiiiiiiPKiS0_S0_PKfS2_Pfii,@object # @_Z25depthwise_filter_backwardiiiiiiPKiS0_S0_PKfS2_Pfii
	.globl	_Z25depthwise_filter_backwardiiiiiiPKiS0_S0_PKfS2_Pfii
	.p2align	3, 0x0
_Z25depthwise_filter_backwardiiiiiiPKiS0_S0_PKfS2_Pfii:
	.quad	_Z40__device_stub__depthwise_filter_backwardiiiiiiPKiS0_S0_PKfS2_Pfii
	.size	_Z25depthwise_filter_backwardiiiiiiPKiS0_S0_PKfS2_Pfii, 8

	.type	_Z30fuzzy_depthwise_conv3d_forwardiiiiiiPKiS0_S0_PKfS2_S2_Pf,@object # @_Z30fuzzy_depthwise_conv3d_forwardiiiiiiPKiS0_S0_PKfS2_S2_Pf
	.globl	_Z30fuzzy_depthwise_conv3d_forwardiiiiiiPKiS0_S0_PKfS2_S2_Pf
	.p2align	3, 0x0
_Z30fuzzy_depthwise_conv3d_forwardiiiiiiPKiS0_S0_PKfS2_S2_Pf:
	.quad	_Z45__device_stub__fuzzy_depthwise_conv3d_forwardiiiiiiPKiS0_S0_PKfS2_S2_Pf
	.size	_Z30fuzzy_depthwise_conv3d_forwardiiiiiiPKiS0_S0_PKfS2_S2_Pf, 8

	.type	_Z30fuzzy_depthwise_input_backwardiiiiiiPKiS0_S0_PKfS2_S2_S2_Pf,@object # @_Z30fuzzy_depthwise_input_backwardiiiiiiPKiS0_S0_PKfS2_S2_S2_Pf
	.globl	_Z30fuzzy_depthwise_input_backwardiiiiiiPKiS0_S0_PKfS2_S2_S2_Pf
	.p2align	3, 0x0
_Z30fuzzy_depthwise_input_backwardiiiiiiPKiS0_S0_PKfS2_S2_S2_Pf:
	.quad	_Z45__device_stub__fuzzy_depthwise_input_backwardiiiiiiPKiS0_S0_PKfS2_S2_S2_Pf
	.size	_Z30fuzzy_depthwise_input_backwardiiiiiiPKiS0_S0_PKfS2_S2_S2_Pf, 8

	.type	_Z31fuzzy_depthwise_filter_backwardiiiiiiPKiS0_S0_PKfS2_S2_Pfii,@object # @_Z31fuzzy_depthwise_filter_backwardiiiiiiPKiS0_S0_PKfS2_S2_Pfii
	.globl	_Z31fuzzy_depthwise_filter_backwardiiiiiiPKiS0_S0_PKfS2_S2_Pfii
	.p2align	3, 0x0
_Z31fuzzy_depthwise_filter_backwardiiiiiiPKiS0_S0_PKfS2_S2_Pfii:
	.quad	_Z46__device_stub__fuzzy_depthwise_filter_backwardiiiiiiPKiS0_S0_PKfS2_S2_Pfii
	.size	_Z31fuzzy_depthwise_filter_backwardiiiiiiPKiS0_S0_PKfS2_S2_Pfii, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z24depthwise_conv3d_forwardiiiiiiPKiS0_S0_PKfS2_Pf"
	.size	.L__unnamed_1, 52

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z24depthwise_input_backwardiiiiiiPKiS0_S0_PKfS2_S2_Pf"
	.size	.L__unnamed_2, 55

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z25depthwise_filter_backwardiiiiiiPKiS0_S0_PKfS2_Pfii"
	.size	.L__unnamed_3, 55

	.type	.L__unnamed_4,@object           # @3
.L__unnamed_4:
	.asciz	"_Z30fuzzy_depthwise_conv3d_forwardiiiiiiPKiS0_S0_PKfS2_S2_Pf"
	.size	.L__unnamed_4, 61

	.type	.L__unnamed_5,@object           # @4
.L__unnamed_5:
	.asciz	"_Z30fuzzy_depthwise_input_backwardiiiiiiPKiS0_S0_PKfS2_S2_S2_Pf"
	.size	.L__unnamed_5, 64

	.type	.L__unnamed_6,@object           # @5
.L__unnamed_6:
	.asciz	"_Z31fuzzy_depthwise_filter_backwardiiiiiiPKiS0_S0_PKfS2_S2_Pfii"
	.size	.L__unnamed_6, 64

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z39__device_stub__depthwise_conv3d_forwardiiiiiiPKiS0_S0_PKfS2_Pf
	.addrsig_sym _Z39__device_stub__depthwise_input_backwardiiiiiiPKiS0_S0_PKfS2_S2_Pf
	.addrsig_sym _Z40__device_stub__depthwise_filter_backwardiiiiiiPKiS0_S0_PKfS2_Pfii
	.addrsig_sym _Z45__device_stub__fuzzy_depthwise_conv3d_forwardiiiiiiPKiS0_S0_PKfS2_S2_Pf
	.addrsig_sym _Z45__device_stub__fuzzy_depthwise_input_backwardiiiiiiPKiS0_S0_PKfS2_S2_S2_Pf
	.addrsig_sym _Z46__device_stub__fuzzy_depthwise_filter_backwardiiiiiiPKiS0_S0_PKfS2_S2_Pfii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z24depthwise_conv3d_forwardiiiiiiPKiS0_S0_PKfS2_Pf
	.addrsig_sym _Z24depthwise_input_backwardiiiiiiPKiS0_S0_PKfS2_S2_Pf
	.addrsig_sym _Z25depthwise_filter_backwardiiiiiiPKiS0_S0_PKfS2_Pfii
	.addrsig_sym _Z30fuzzy_depthwise_conv3d_forwardiiiiiiPKiS0_S0_PKfS2_S2_Pf
	.addrsig_sym _Z30fuzzy_depthwise_input_backwardiiiiiiPKiS0_S0_PKfS2_S2_S2_Pf
	.addrsig_sym _Z31fuzzy_depthwise_filter_backwardiiiiiiPKiS0_S0_PKfS2_S2_Pfii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z24depthwise_conv3d_forwardiiiiiiPKiS0_S0_PKfS2_Pf ; -- Begin function _Z24depthwise_conv3d_forwardiiiiiiPKiS0_S0_PKfS2_Pf
	.globl	_Z24depthwise_conv3d_forwardiiiiiiPKiS0_S0_PKfS2_Pf
	.p2align	8
	.type	_Z24depthwise_conv3d_forwardiiiiiiPKiS0_S0_PKfS2_Pf,@function
_Z24depthwise_conv3d_forwardiiiiiiPKiS0_S0_PKfS2_Pf: ; @_Z24depthwise_conv3d_forwardiiiiiiPKiS0_S0_PKfS2_Pf
; %bb.0:
	s_load_b128 s[16:19], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_cmp_ge_i32 s14, s16
	s_cbranch_scc1 .LBB0_9
; %bb.1:                                ; %.lr.ph73
	s_clause 0x1
	s_load_b64 s[2:3], s[0:1], 0x10
	s_load_b32 s29, s[0:1], 0x54
	s_add_u32 s12, s0, 0x48
	s_addc_u32 s13, s1, 0
	s_clause 0x1
	s_load_b128 s[20:23], s[0:1], 0x38
	s_load_b32 s28, s[0:1], 0x48
	s_mul_i32 s30, s14, s18
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s24, s2, s19
	s_ashr_i32 s25, s2, 31
	s_ashr_i32 s26, s24, 31
	s_add_i32 s2, s2, s25
	s_add_i32 s4, s24, s26
	s_xor_b32 s2, s2, s25
	s_xor_b32 s27, s4, s26
	v_cvt_f32_u32_e32 v1, s2
	v_cvt_f32_u32_e32 v2, s27
	s_sub_i32 s4, 0, s27
	s_sub_i32 s5, 0, s2
	s_and_b32 s29, s29, 0xffff
	v_rcp_iflag_f32_e32 v1, v1
	v_rcp_iflag_f32_e32 v2, v2
	s_mul_i32 s31, s28, s18
	s_waitcnt_depctr 0xfff
	v_dual_mul_f32 v1, 0x4f7ffffe, v1 :: v_dual_mul_f32 v2, 0x4f7ffffe, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_u32_f32_e32 v3, v1
	v_cvt_u32_f32_e32 v4, v2
	v_mad_u64_u32 v[1:2], null, s15, s29, v[0:1]
	s_mul_i32 s15, s24, s18
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_lo_u32 v6, s5, v3
	v_mul_lo_u32 v5, s4, v4
	s_load_b256 s[4:11], s[0:1], 0x18
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_gt_i32_e64 s0, s15, v1
	v_mul_hi_u32 v2, v3, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v0, v4, v5
	v_add_nc_u32_e32 v10, v3, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_nc_u32_e32 v9, v4, v0
.LBB0_2:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_4 Depth 2
                                        ;       Child Loop BB0_6 Depth 3
	s_and_saveexec_b32 s33, s0
	s_cbranch_execz .LBB0_8
; %bb.3:                                ; %.lr.ph69
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_load_b32 s37, s[12:13], 0x4
	v_mov_b32_e32 v11, v1
	s_mul_i32 s34, s14, s18
	s_mul_i32 s35, s14, s17
	s_mul_i32 s36, s24, s34
	s_mov_b32 s38, 0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s37, s37, s29
.LBB0_4:                                ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB0_6 Depth 3
	v_ashrrev_i32_e32 v0, 31, v11
	s_mov_b32 s39, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v2, v11, v0
	v_xor_b32_e32 v2, v2, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v3, v2, v9
	v_mul_lo_u32 v4, v3, s27
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v2, v2, v4
	v_add_nc_u32_e32 v4, 1, v3
	v_subrev_nc_u32_e32 v5, s27, v2
	v_cmp_le_u32_e32 vcc_lo, s27, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v3, v3, v4 :: v_dual_cndmask_b32 v2, v2, v5
	v_xor_b32_e32 v4, s26, v0
	v_add_nc_u32_e32 v5, 1, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_le_u32_e32 vcc_lo, s27, v2
	v_cndmask_b32_e32 v0, v3, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v5, v0, v4
	v_sub_nc_u32_e32 v0, v5, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v2, s34, v0
	v_ashrrev_i32_e32 v3, 31, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	v_add_co_u32 v2, vcc_lo, s6, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
	global_load_b32 v12, v[2:3], off
	s_waitcnt vmcnt(0)
	v_cmpx_lt_i32_e32 0, v12
	s_cbranch_execz .LBB0_7
; %bb.5:                                ; %.lr.ph
                                        ;   in Loop: Header=BB0_4 Depth=2
	v_mul_lo_u32 v0, v0, s24
	v_add_nc_u32_e32 v5, s30, v5
	s_mov_b32 s40, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v4, v5, v4
	v_sub_nc_u32_e32 v0, v11, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v4, s3, v4
	v_ashrrev_i32_e32 v6, 31, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v7, v0, v6
	v_xor_b32_e32 v7, v7, v6
	v_xor_b32_e32 v6, s25, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v8, v7, v10
	v_mul_lo_u32 v14, v8, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v7, v7, v14
	v_subrev_nc_u32_e32 v15, s2, v7
	v_add_nc_u32_e32 v14, 1, v8
	v_add_nc_u32_e32 v2, s36, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s22, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s23, v3, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s2, v7
	global_load_b32 v13, v[2:3], off
	v_cndmask_b32_e32 v7, v7, v15, vcc_lo
	v_cndmask_b32_e32 v5, v8, v14, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_le_u32_e32 vcc_lo, s2, v7
	v_add_nc_u32_e32 v8, 1, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v7, v5, v8, vcc_lo
	v_ashrrev_i32_e32 v5, 31, v4
	v_xor_b32_e32 v14, v7, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[7:8], 2, v[4:5]
	v_sub_nc_u32_e32 v4, v14, v6
	v_cvt_f32_i32_e32 v14, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v5, vcc_lo, s4, v7
	v_add_co_ci_u32_e32 v6, vcc_lo, s5, v8, vcc_lo
	v_add_co_u32 v7, vcc_lo, s8, v7
	v_add_co_ci_u32_e32 v8, vcc_lo, s9, v8, vcc_lo
.LBB0_6:                                ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_4 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	global_load_b32 v15, v[5:6], off
	global_load_b32 v17, v[7:8], off
	v_add_nc_u32_e32 v12, -1, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_eq_u32_e64 s1, 0, v12
	s_or_b32 s40, s1, s40
	s_waitcnt vmcnt(1)
	v_add_nc_u32_e32 v19, s35, v15
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[15:16], null, s24, v17, v[0:1]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[17:18], null, v19, s19, v[4:5]
	v_ashrrev_i32_e32 v16, 31, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v18, 31, v17
	v_lshlrev_b64 v[15:16], 2, v[15:16]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[17:18], 2, v[17:18]
	v_add_co_u32 v15, vcc_lo, s20, v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v16, vcc_lo, s21, v16, vcc_lo
	v_add_co_u32 v17, vcc_lo, s10, v17
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v18, vcc_lo, s11, v18, vcc_lo
	global_load_b32 v15, v[15:16], off
	global_load_b32 v16, v[17:18], off
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v15, v16, v15
	v_div_scale_f32 v16, null, v14, v14, v15
	v_div_scale_f32 v19, vcc_lo, v15, v14, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v17, v16
	s_waitcnt_depctr 0xfff
	v_fma_f32 v18, -v16, v17, 1.0
	v_fmac_f32_e32 v17, v18, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v18, v19, v17
	v_fma_f32 v20, -v16, v18, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v18, v20, v17
	v_fma_f32 v16, -v16, v18, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_div_fmas_f32 v16, v16, v17, v18
	v_add_co_u32 v5, vcc_lo, v5, 4
	v_add_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
	v_div_fixup_f32 v15, v16, v14, v15
	v_add_co_u32 v7, vcc_lo, v7, 4
	v_add_co_ci_u32_e32 v8, vcc_lo, 0, v8, vcc_lo
	s_delay_alu instid0(VALU_DEP_3)
	v_add_f32_e32 v13, v13, v15
	global_store_b32 v[2:3], v13, off
	s_and_not1_b32 exec_lo, exec_lo, s40
	s_cbranch_execnz .LBB0_6
.LBB0_7:                                ; %Flow118
                                        ;   in Loop: Header=BB0_4 Depth=2
	s_or_b32 exec_lo, exec_lo, s39
	v_add_nc_u32_e32 v11, s37, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_le_i32_e32 vcc_lo, s15, v11
	s_or_b32 s38, vcc_lo, s38
	s_and_not1_b32 exec_lo, exec_lo, s38
	s_cbranch_execnz .LBB0_4
.LBB0_8:                                ; %Flow120
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s33
	s_add_i32 s14, s28, s14
	s_add_i32 s30, s30, s31
	s_cmp_ge_i32 s14, s16
	s_cbranch_scc0 .LBB0_2
.LBB0_9:                                ; %._crit_edge74
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z24depthwise_conv3d_forwardiiiiiiPKiS0_S0_PKfS2_Pf
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 328
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 21
		.amdhsa_next_free_sgpr 41
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z24depthwise_conv3d_forwardiiiiiiPKiS0_S0_PKfS2_Pf, .Lfunc_end0-_Z24depthwise_conv3d_forwardiiiiiiPKiS0_S0_PKfS2_Pf
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1048
; NumSgprs: 43
; NumVgprs: 21
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 5
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 43
; NumVGPRsForWavesPerEU: 21
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z24depthwise_input_backwardiiiiiiPKiS0_S0_PKfS2_S2_Pf ; -- Begin function _Z24depthwise_input_backwardiiiiiiPKiS0_S0_PKfS2_S2_Pf
	.globl	_Z24depthwise_input_backwardiiiiiiPKiS0_S0_PKfS2_S2_Pf
	.p2align	8
	.type	_Z24depthwise_input_backwardiiiiiiPKiS0_S0_PKfS2_S2_Pf,@function
_Z24depthwise_input_backwardiiiiiiPKiS0_S0_PKfS2_S2_Pf: ; @_Z24depthwise_input_backwardiiiiiiPKiS0_S0_PKfS2_S2_Pf
; %bb.0:
	s_load_b128 s[4:7], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_cmp_ge_i32 s14, s4
	s_cbranch_scc1 .LBB1_11
; %bb.1:                                ; %.lr.ph75
	s_clause 0x1
	s_load_b64 s[2:3], s[0:1], 0x10
	s_load_b128 s[8:11], s[0:1], 0x18
	s_add_u32 s12, s0, 0x50
	s_addc_u32 s13, s1, 0
	s_clause 0x2
	s_load_b32 s29, s[0:1], 0x5c
	s_load_b64 s[20:21], s[0:1], 0x48
	s_load_b32 s28, s[0:1], 0x50
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s24, s2, s7
	s_ashr_i32 s25, s2, 31
	s_ashr_i32 s26, s24, 31
	s_add_i32 s2, s2, s25
	s_add_i32 s16, s24, s26
	s_xor_b32 s2, s2, s25
	s_xor_b32 s27, s16, s26
	v_cvt_f32_u32_e32 v1, s2
	v_cvt_f32_u32_e32 v2, s27
	s_sub_i32 s16, 0, s2
	s_sub_i32 s17, 0, s27
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v1, v1
	v_rcp_iflag_f32_e32 v2, v2
	s_waitcnt_depctr 0xfff
	v_dual_mul_f32 v1, 0x4f7ffffe, v1 :: v_dual_mul_f32 v2, 0x4f7ffffe, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_u32_f32_e32 v3, v1
	v_cvt_u32_f32_e32 v4, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v5, s16, v3
	v_mul_lo_u32 v6, s17, v4
	s_clause 0x1
	s_load_b64 s[22:23], s[0:1], 0x28
	s_load_b128 s[16:19], s[0:1], 0x38
	s_and_b32 s1, s29, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[1:2], null, s15, s1, v[0:1]
	s_mul_i32 s15, s24, s6
	v_mul_hi_u32 v2, v3, v5
	v_mul_hi_u32 v0, v4, v6
	v_cmp_gt_i32_e64 s0, s15, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v10, v3, v2
	v_add_nc_u32_e32 v9, v4, v0
.LBB1_2:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB1_4 Depth 2
                                        ;       Child Loop BB1_6 Depth 3
                                        ;         Child Loop BB1_7 Depth 4
	s_delay_alu instid0(VALU_DEP_3)
	s_and_saveexec_b32 s29, s0
	s_cbranch_execz .LBB1_10
; %bb.3:                                ; %.lr.ph71
                                        ;   in Loop: Header=BB1_2 Depth=1
	s_load_b32 s34, s[12:13], 0x4
	v_mov_b32_e32 v11, v1
	s_mul_i32 s30, s14, s6
	s_mul_i32 s31, s14, s5
	s_mul_i32 s33, s24, s30
	s_mov_b32 s35, 0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s34, s34, s1
.LBB1_4:                                ;   Parent Loop BB1_2 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB1_6 Depth 3
                                        ;         Child Loop BB1_7 Depth 4
	v_ashrrev_i32_e32 v0, 31, v11
	s_mov_b32 s36, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v2, v11, v0
	v_xor_b32_e32 v2, v2, v0
	v_xor_b32_e32 v0, s26, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v3, v2, v9
	v_mul_lo_u32 v4, v3, s27
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v2, v2, v4
	v_add_nc_u32_e32 v4, 1, v3
	v_subrev_nc_u32_e32 v5, s27, v2
	v_cmp_le_u32_e32 vcc_lo, s27, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_cndmask_b32 v3, v3, v4 :: v_dual_cndmask_b32 v2, v2, v5
	v_add_nc_u32_e32 v4, 1, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_le_u32_e32 vcc_lo, s27, v2
	v_cndmask_b32_e32 v2, v3, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v2, v2, v0
	v_sub_nc_u32_e32 v0, v2, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v2, s30, v0
	v_ashrrev_i32_e32 v3, 31, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[2:3]
	v_add_co_u32 v3, vcc_lo, s10, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, s11, v4, vcc_lo
	global_load_b32 v12, v[3:4], off
	s_waitcnt vmcnt(0)
	v_cmpx_lt_i32_e32 0, v12
	s_cbranch_execz .LBB1_9
; %bb.5:                                ; %.lr.ph
                                        ;   in Loop: Header=BB1_4 Depth=2
	v_mul_lo_u32 v0, v0, s24
	v_mul_lo_u32 v13, v2, s3
	v_cvt_f32_i32_e32 v14, v12
	s_mov_b32 s37, 0
	s_mov_b32 s38, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v0, v11, v0
	v_ashrrev_i32_e32 v5, 31, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v3, v0, v5
	v_xor_b32_e32 v3, v3, v5
	v_xor_b32_e32 v5, s25, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v4, v3, v10
	v_mul_lo_u32 v6, v4, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v6, v3, v6
	v_add_nc_u32_e32 v3, 1, v4
	v_subrev_nc_u32_e32 v7, s2, v6
	v_cmp_le_u32_e32 vcc_lo, s2, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v8, v4, v3, vcc_lo
	v_cndmask_b32_e32 v6, v6, v7, vcc_lo
	v_add_nc_u32_e32 v3, s33, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v7, 1, v8
	v_cmp_le_u32_e32 vcc_lo, s2, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_ashrrev_i32_e32 v4, 31, v3
	v_cndmask_b32_e32 v6, v8, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	v_xor_b32_e32 v6, v6, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v2, vcc_lo, s18, v3
	v_add_co_ci_u32_e32 v3, vcc_lo, s19, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_3)
	v_sub_nc_u32_e32 v4, v6, v5
.LBB1_6:                                ;   Parent Loop BB1_2 Depth=1
                                        ;     Parent Loop BB1_4 Depth=2
                                        ; =>    This Loop Header: Depth=3
                                        ;         Child Loop BB1_7 Depth 4
	v_add_nc_u32_e32 v5, s38, v13
	s_mov_b32 s39, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v6, 31, v5
	v_lshlrev_b64 v[5:6], 2, v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v7, vcc_lo, s22, v5
	v_add_co_ci_u32_e32 v8, vcc_lo, s23, v6, vcc_lo
	v_add_co_u32 v5, vcc_lo, s8, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, s9, v6, vcc_lo
	global_load_b32 v7, v[7:8], off
	global_load_b32 v8, v[5:6], off
	s_waitcnt vmcnt(1)
	v_mad_u64_u32 v[5:6], null, s24, v7, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v6, 31, v5
	v_lshlrev_b64 v[5:6], 2, v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v5, vcc_lo, s16, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, s17, v6, vcc_lo
	global_load_b32 v7, v[2:3], off
	global_load_b32 v15, v[5:6], off
	s_waitcnt vmcnt(0)
	v_dual_mul_f32 v7, v7, v15 :: v_dual_add_nc_u32 v8, s31, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[5:6], null, v8, s7, v[4:5]
	v_div_scale_f32 v15, null, v14, v14, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v6, 31, v5
	v_rcp_f32_e32 v16, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[5:6], 2, v[5:6]
	v_add_co_u32 v5, vcc_lo, s20, v5
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v6, vcc_lo, s21, v6, vcc_lo
	s_waitcnt_depctr 0xfff
	v_fma_f32 v17, -v15, v16, 1.0
	global_load_b32 v8, v[5:6], off
	v_fmac_f32_e32 v16, v17, v16
	v_div_scale_f32 v17, vcc_lo, v7, v14, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v18, v17, v16
	v_fma_f32 v19, -v15, v18, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v18, v19, v16
	v_fma_f32 v15, -v15, v18, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v15, v15, v16, v18
	v_div_fixup_f32 v15, v15, v14, v7
.LBB1_7:                                ; %atomicrmw.start
                                        ;   Parent Loop BB1_2 Depth=1
                                        ;     Parent Loop BB1_4 Depth=2
                                        ;       Parent Loop BB1_6 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f32_e32 v7, v8, v15
	global_atomic_cmpswap_b32 v7, v[5:6], v[7:8], off glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u32_e32 vcc_lo, v7, v8
	v_mov_b32_e32 v8, v7
	s_or_b32 s39, vcc_lo, s39
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s39
	s_cbranch_execnz .LBB1_7
; %bb.8:                                ; %atomicrmw.end
                                        ;   in Loop: Header=BB1_6 Depth=3
	s_or_b32 exec_lo, exec_lo, s39
	s_add_i32 s38, s38, 1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_eq_u32_e32 vcc_lo, s38, v12
	s_or_b32 s37, vcc_lo, s37
	s_and_not1_b32 exec_lo, exec_lo, s37
	s_cbranch_execnz .LBB1_6
.LBB1_9:                                ; %Flow113
                                        ;   in Loop: Header=BB1_4 Depth=2
	s_or_b32 exec_lo, exec_lo, s36
	v_add_nc_u32_e32 v11, s34, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_le_i32_e32 vcc_lo, s15, v11
	s_or_b32 s35, vcc_lo, s35
	s_and_not1_b32 exec_lo, exec_lo, s35
	s_cbranch_execnz .LBB1_4
.LBB1_10:                               ; %Flow115
                                        ;   in Loop: Header=BB1_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s29
	s_add_i32 s14, s28, s14
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_ge_i32 s14, s4
	s_cbranch_scc0 .LBB1_2
.LBB1_11:                               ; %._crit_edge76
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z24depthwise_input_backwardiiiiiiPKiS0_S0_PKfS2_S2_Pf
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 336
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 20
		.amdhsa_next_free_sgpr 40
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z24depthwise_input_backwardiiiiiiPKiS0_S0_PKfS2_S2_Pf, .Lfunc_end1-_Z24depthwise_input_backwardiiiiiiPKiS0_S0_PKfS2_S2_Pf
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1068
; NumSgprs: 42
; NumVgprs: 20
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 5
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 42
; NumVGPRsForWavesPerEU: 20
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z25depthwise_filter_backwardiiiiiiPKiS0_S0_PKfS2_Pfii ; -- Begin function _Z25depthwise_filter_backwardiiiiiiPKiS0_S0_PKfS2_Pfii
	.globl	_Z25depthwise_filter_backwardiiiiiiPKiS0_S0_PKfS2_Pfii
	.p2align	8
	.type	_Z25depthwise_filter_backwardiiiiiiPKiS0_S0_PKfS2_Pfii,@function
_Z25depthwise_filter_backwardiiiiiiPKiS0_S0_PKfS2_Pfii: ; @_Z25depthwise_filter_backwardiiiiiiPKiS0_S0_PKfS2_Pfii
; %bb.0:
	s_load_b64 s[6:7], s[0:1], 0x48
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_i32_e64 s2, s6, v0
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB2_3
; %bb.1:                                ; %.lr.ph
	s_load_b32 s4, s[0:1], 0x5c
	v_lshl_add_u32 v1, v0, 2, 0
	v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v3, v0
	s_mov_b32 s5, 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s4, s4, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1)
	s_lshl_b32 s8, s4, 2
.LBB2_2:                                ; =>This Inner Loop Header: Depth=1
	v_add_nc_u32_e32 v3, s4, v3
	ds_store_b32 v1, v2
	v_add_nc_u32_e32 v1, s8, v1
	v_cmp_le_i32_e32 vcc_lo, s6, v3
	s_or_b32 s5, vcc_lo, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s5
	s_cbranch_execnz .LBB2_2
.LBB2_3:                                ; %Flow167
	s_or_b32 exec_lo, exec_lo, s3
	s_clause 0x2
	s_load_b128 s[24:27], s[0:1], 0x0
	s_load_b256 s[16:23], s[0:1], 0x18
	s_load_b128 s[8:11], s[0:1], 0x38
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cmp_ge_i32 s14, s24
	s_cbranch_scc1 .LBB2_14
; %bb.4:                                ; %.lr.ph101
	s_load_b64 s[4:5], s[0:1], 0x10
	s_add_i32 s28, s7, s6
	s_add_u32 s12, s0, 0x50
	s_addc_u32 s13, s1, 0
	s_clause 0x1
	s_load_b32 s29, s[0:1], 0x50
	s_load_b32 s3, s[0:1], 0x5c
	s_mul_i32 s37, s14, s26
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s30, s4, s27
	s_ashr_i32 s33, s4, 31
	s_ashr_i32 s31, s30, 31
	s_add_i32 s4, s4, s33
	s_add_i32 s34, s30, s31
	s_xor_b32 s35, s4, s33
	s_xor_b32 s34, s34, s31
	v_cvt_f32_u32_e32 v2, s35
	v_cvt_f32_u32_e32 v1, s34
	s_sub_i32 s4, 0, s34
	s_sub_i32 s36, 0, s35
	s_mul_i32 s38, s29, s26
	v_rcp_iflag_f32_e32 v2, v2
	v_rcp_iflag_f32_e32 v1, v1
	s_waitcnt_depctr 0xfff
	v_dual_mul_f32 v2, 0x4f7ffffe, v2 :: v_dual_mul_f32 v1, 0x4f7ffffe, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_u32_f32_e32 v4, v2
	v_cvt_u32_f32_e32 v3, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v6, s36, v4
	v_mul_lo_u32 v5, s4, v3
	s_and_b32 s36, s3, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[1:2], null, s15, s36, v[0:1]
	s_mul_i32 s15, s30, s26
	v_mul_hi_u32 v2, v3, v5
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_hi_u32 v5, v4, v6
	v_cmp_gt_i32_e64 s3, s15, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v12, v3, v2
	v_add_nc_u32_e32 v13, v4, v5
.LBB2_5:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB2_7 Depth 2
                                        ;       Child Loop BB2_9 Depth 3
	s_delay_alu instid0(VALU_DEP_3)
	s_and_saveexec_b32 s39, s3
	s_cbranch_execz .LBB2_13
; %bb.6:                                ; %.lr.ph97
                                        ;   in Loop: Header=BB2_5 Depth=1
	s_load_b32 s43, s[12:13], 0x4
	v_mov_b32_e32 v14, v1
	s_mul_i32 s40, s14, s26
	s_mul_i32 s41, s14, s25
	s_mul_i32 s42, s30, s40
	s_mov_b32 s44, 0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s43, s43, s36
.LBB2_7:                                ;   Parent Loop BB2_5 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB2_9 Depth 3
	v_ashrrev_i32_e32 v2, 31, v14
	s_mov_b32 s45, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v3, v14, v2
	v_xor_b32_e32 v3, v3, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v4, v3, v12
	v_mul_lo_u32 v5, v4, s34
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v3, v3, v5
	v_add_nc_u32_e32 v5, 1, v4
	v_subrev_nc_u32_e32 v6, s34, v3
	v_cmp_le_u32_e32 vcc_lo, s34, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v4, v4, v5 :: v_dual_cndmask_b32 v5, v3, v6
	v_xor_b32_e32 v3, s31, v2
	v_add_nc_u32_e32 v6, 1, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_le_u32_e32 vcc_lo, s34, v5
	v_cndmask_b32_e32 v2, v4, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v4, v2, v3
	v_sub_nc_u32_e32 v2, v4, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v5, s40, v2
	v_ashrrev_i32_e32 v6, 31, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[5:6], 2, v[5:6]
	v_add_co_u32 v5, vcc_lo, s18, v5
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v6, vcc_lo, s19, v6, vcc_lo
	global_load_b32 v15, v[5:6], off
	s_waitcnt vmcnt(0)
	v_cmpx_lt_i32_e32 0, v15
	s_cbranch_execz .LBB2_12
; %bb.8:                                ; %.lr.ph93
                                        ;   in Loop: Header=BB2_7 Depth=2
	v_mul_lo_u32 v2, v2, s30
	v_cvt_f32_i32_e32 v16, v15
	s_mov_b32 s46, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v2, v14, v2
	v_ashrrev_i32_e32 v7, 31, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v5, v2, v7
	v_xor_b32_e32 v5, v5, v7
	v_xor_b32_e32 v7, s33, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v6, v5, v13
	v_mul_lo_u32 v8, v6, s35
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v8, v5, v8
	v_subrev_nc_u32_e32 v9, s35, v8
	v_cmp_le_u32_e32 vcc_lo, s35, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_cndmask_b32 v11, v8, v9 :: v_dual_add_nc_u32 v4, s37, v4
	v_sub_nc_u32_e32 v3, v4, v3
	v_add_nc_u32_e32 v4, 1, v6
	v_add_nc_u32_e32 v5, s42, v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_lo_u32 v3, s5, v3
	v_cndmask_b32_e32 v10, v6, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_ashrrev_i32_e32 v6, 31, v5
	v_cmp_le_u32_e32 vcc_lo, s35, v11
	v_add_nc_u32_e32 v17, 1, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[5:6], 2, v[5:6]
	v_ashrrev_i32_e32 v4, 31, v3
	v_cndmask_b32_e32 v10, v10, v17, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_lshlrev_b64 v[8:9], 2, v[3:4]
	v_add_co_u32 v3, vcc_lo, s8, v5
	v_add_co_ci_u32_e32 v4, vcc_lo, s9, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v10, v10, v7
	v_add_co_u32 v5, vcc_lo, s16, v8
	v_add_co_ci_u32_e32 v6, vcc_lo, s17, v9, vcc_lo
	v_add_co_u32 v8, vcc_lo, s20, v8
	s_delay_alu instid0(VALU_DEP_4)
	v_sub_nc_u32_e32 v7, v10, v7
	v_add_co_ci_u32_e32 v9, vcc_lo, s21, v9, vcc_lo
.LBB2_9:                                ;   Parent Loop BB2_5 Depth=1
                                        ;     Parent Loop BB2_7 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	global_load_b32 v17, v[8:9], off
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[10:11], null, s30, v17, v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_le_i32_e32 vcc_lo, s7, v10
	v_cmp_gt_i32_e64 s4, s28, v10
	s_and_b32 s47, vcc_lo, s4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s4, s47
	s_cbranch_execz .LBB2_11
; %bb.10:                               ;   in Loop: Header=BB2_9 Depth=3
	global_load_b32 v11, v[5:6], off
	v_subrev_nc_u32_e32 v10, s7, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_lshl_add_u32 v10, v10, 2, 0
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v11, s41, v11
	v_mad_u64_u32 v[17:18], null, v11, s27, v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v18, 31, v17
	v_lshlrev_b64 v[17:18], 2, v[17:18]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v17, vcc_lo, s22, v17
	v_add_co_ci_u32_e32 v18, vcc_lo, s23, v18, vcc_lo
	global_load_b32 v11, v[3:4], off
	global_load_b32 v17, v[17:18], off
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v11, v11, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_scale_f32 v17, null, v16, v16, v11
	v_rcp_f32_e32 v18, v17
	s_waitcnt_depctr 0xfff
	v_fma_f32 v19, -v17, v18, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v18, v19, v18
	v_div_scale_f32 v19, vcc_lo, v11, v16, v11
	v_mul_f32_e32 v20, v19, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v21, -v17, v20, v19
	v_fmac_f32_e32 v20, v21, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v17, -v17, v20, v19
	v_div_fmas_f32 v17, v17, v18, v20
	s_delay_alu instid0(VALU_DEP_1)
	v_div_fixup_f32 v11, v17, v16, v11
	ds_add_f32 v10, v11
.LBB2_11:                               ;   in Loop: Header=BB2_9 Depth=3
	s_or_b32 exec_lo, exec_lo, s4
	v_add_nc_u32_e32 v15, -1, v15
	v_add_co_u32 v5, vcc_lo, v5, 4
	v_add_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u32_e32 vcc_lo, 0, v15
	v_add_co_u32 v8, s4, v8, 4
	v_add_co_ci_u32_e64 v9, s4, 0, v9, s4
	s_or_b32 s46, vcc_lo, s46
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s46
	s_cbranch_execnz .LBB2_9
.LBB2_12:                               ; %Flow161
                                        ;   in Loop: Header=BB2_7 Depth=2
	s_or_b32 exec_lo, exec_lo, s45
	v_add_nc_u32_e32 v14, s43, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_le_i32_e32 vcc_lo, s15, v14
	s_or_b32 s44, vcc_lo, s44
	s_and_not1_b32 exec_lo, exec_lo, s44
	s_cbranch_execnz .LBB2_7
.LBB2_13:                               ; %Flow163
                                        ;   in Loop: Header=BB2_5 Depth=1
	s_or_b32 exec_lo, exec_lo, s39
	s_add_i32 s14, s29, s14
	s_add_i32 s37, s37, s38
	s_cmp_ge_i32 s14, s24
	s_cbranch_scc0 .LBB2_5
.LBB2_14:                               ; %._crit_edge102
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB2_19
; %bb.15:                               ; %.lr.ph105
	s_load_b32 s0, s[0:1], 0x5c
	s_mov_b32 s1, 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s0, s0, 0xffff
.LBB2_16:                               ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB2_17 Depth 2
	v_add_nc_u32_e32 v1, s7, v0
	v_lshl_add_u32 v3, v0, 2, 0
	s_mov_b32 s2, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v2, 31, v1
	ds_load_b32 v5, v3
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s10, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, s11, v2, vcc_lo
	global_load_b32 v4, v[1:2], off
.LBB2_17:                               ; %atomicrmw.start
                                        ;   Parent Loop BB2_16 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f32_e32 v3, v4, v5
	global_atomic_cmpswap_b32 v3, v[1:2], v[3:4], off glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u32_e32 vcc_lo, v3, v4
	v_mov_b32_e32 v4, v3
	s_or_b32 s2, vcc_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s2
	s_cbranch_execnz .LBB2_17
; %bb.18:                               ; %atomicrmw.end
                                        ;   in Loop: Header=BB2_16 Depth=1
	s_or_b32 exec_lo, exec_lo, s2
	v_add_nc_u32_e32 v0, s0, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_le_i32_e32 vcc_lo, s6, v0
	s_or_b32 s1, vcc_lo, s1
	s_and_not1_b32 exec_lo, exec_lo, s1
	s_cbranch_execnz .LBB2_16
.LBB2_19:                               ; %Flow159
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z25depthwise_filter_backwardiiiiiiPKiS0_S0_PKfS2_Pfii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 336
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 22
		.amdhsa_next_free_sgpr 48
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_Z25depthwise_filter_backwardiiiiiiPKiS0_S0_PKfS2_Pfii, .Lfunc_end2-_Z25depthwise_filter_backwardiiiiiiPKiS0_S0_PKfS2_Pfii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1372
; NumSgprs: 50
; NumVgprs: 22
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 6
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 50
; NumVGPRsForWavesPerEU: 22
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z30fuzzy_depthwise_conv3d_forwardiiiiiiPKiS0_S0_PKfS2_S2_Pf ; -- Begin function _Z30fuzzy_depthwise_conv3d_forwardiiiiiiPKiS0_S0_PKfS2_S2_Pf
	.globl	_Z30fuzzy_depthwise_conv3d_forwardiiiiiiPKiS0_S0_PKfS2_S2_Pf
	.p2align	8
	.type	_Z30fuzzy_depthwise_conv3d_forwardiiiiiiPKiS0_S0_PKfS2_S2_Pf,@function
_Z30fuzzy_depthwise_conv3d_forwardiiiiiiPKiS0_S0_PKfS2_S2_Pf: ; @_Z30fuzzy_depthwise_conv3d_forwardiiiiiiPKiS0_S0_PKfS2_S2_Pf
; %bb.0:
	s_load_b128 s[16:19], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_cmp_ge_i32 s14, s16
	s_cbranch_scc1 .LBB3_13
; %bb.1:                                ; %.lr.ph94
	s_clause 0x2
	s_load_b64 s[2:3], s[0:1], 0x10
	s_load_b32 s33, s[0:1], 0x50
	s_load_b32 s26, s[0:1], 0x5c
	s_add_u32 s12, s0, 0x50
	s_addc_u32 s13, s1, 0
	s_mul_i32 s35, s14, s18
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s28, s2, s19
	s_ashr_i32 s29, s2, 31
	s_ashr_i32 s30, s28, 31
	s_add_i32 s2, s2, s29
	s_add_i32 s4, s28, s30
	s_xor_b32 s2, s2, s29
	s_xor_b32 s31, s4, s30
	v_cvt_f32_u32_e32 v1, s2
	v_cvt_f32_u32_e32 v2, s31
	s_sub_i32 s20, 0, s2
	s_sub_i32 s21, 0, s31
	s_load_b256 s[4:11], s[0:1], 0x18
	v_rcp_iflag_f32_e32 v1, v1
	v_rcp_iflag_f32_e32 v2, v2
	s_lshl_b32 s34, s3, 2
	s_mul_i32 s36, s33, s18
	s_waitcnt_depctr 0xfff
	v_dual_mul_f32 v1, 0x4f7ffffe, v1 :: v_dual_mul_f32 v2, 0x4f7ffffe, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_u32_f32_e32 v3, v1
	v_cvt_u32_f32_e32 v4, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v5, s20, v3
	v_mul_lo_u32 v6, s21, v4
	s_clause 0x1
	s_load_b128 s[20:23], s[0:1], 0x38
	s_load_b64 s[24:25], s[0:1], 0x48
	s_and_b32 s1, s26, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[1:2], null, s15, s1, v[0:1]
	s_mul_i32 s15, s28, s18
	v_mul_hi_u32 v2, v3, v5
	v_mul_hi_u32 v0, v4, v6
	v_cmp_gt_i32_e64 s0, s15, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v8, v3, v2
	v_add_nc_u32_e32 v7, v4, v0
.LBB3_2:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB3_4 Depth 2
                                        ;       Child Loop BB3_6 Depth 3
                                        ;         Child Loop BB3_7 Depth 4
	s_delay_alu instid0(VALU_DEP_3)
	s_and_saveexec_b32 s37, s0
	s_cbranch_execz .LBB3_12
; %bb.3:                                ; %.lr.ph90
                                        ;   in Loop: Header=BB3_2 Depth=1
	s_load_b32 s41, s[12:13], 0x4
	v_mov_b32_e32 v9, v1
	s_mul_i32 s38, s14, s18
	s_mul_i32 s39, s14, s17
	s_mul_i32 s40, s28, s38
	s_mov_b32 s42, 0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s41, s41, s1
.LBB3_4:                                ;   Parent Loop BB3_2 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB3_6 Depth 3
                                        ;         Child Loop BB3_7 Depth 4
	v_ashrrev_i32_e32 v0, 31, v9
	s_mov_b32 s43, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v2, v9, v0
	v_xor_b32_e32 v6, s30, v0
	v_xor_b32_e32 v2, v2, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v3, v2, v7
	v_mul_lo_u32 v4, v3, s31
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v2, v2, v4
	v_add_nc_u32_e32 v4, 1, v3
	v_subrev_nc_u32_e32 v5, s31, v2
	v_cmp_le_u32_e32 vcc_lo, s31, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_cndmask_b32 v3, v3, v4 :: v_dual_cndmask_b32 v2, v2, v5
	v_add_nc_u32_e32 v4, 1, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_le_u32_e32 vcc_lo, s31, v2
	v_cndmask_b32_e32 v0, v3, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v12, v0, v6
	v_sub_nc_u32_e32 v0, v12, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v4, s38, v0
	v_ashrrev_i32_e32 v5, 31, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[4:5]
	v_add_co_u32 v2, vcc_lo, s6, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
	global_load_b32 v10, v[2:3], off
	s_waitcnt vmcnt(0)
	v_cmpx_lt_i32_e32 0, v10
	s_cbranch_execz .LBB3_11
; %bb.5:                                ; %.lr.ph
                                        ;   in Loop: Header=BB3_4 Depth=2
	v_mul_lo_u32 v0, v0, s28
	s_mov_b32 s44, 0
	s_mov_b32 s45, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v0, v9, v0
	v_ashrrev_i32_e32 v5, 31, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v13, v0, v5
	v_xor_b32_e32 v13, v13, v5
	v_xor_b32_e32 v5, s29, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v14, v13, v8
	v_mul_lo_u32 v15, v14, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v13, v13, v15
	v_add_nc_u32_e32 v15, 1, v14
	v_subrev_nc_u32_e32 v16, s2, v13
	v_add_nc_u32_e32 v2, s40, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s24, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s25, v3, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s2, v13
	global_load_b32 v11, v[2:3], off
	v_dual_cndmask_b32 v13, v13, v16 :: v_dual_cndmask_b32 v14, v14, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_le_u32_e32 vcc_lo, s2, v13
	v_add_nc_u32_e32 v15, 1, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_cndmask_b32 v13, v14, v15 :: v_dual_add_nc_u32 v12, s35, v12
	v_sub_nc_u32_e32 v6, v12, v6
	v_mul_lo_u32 v12, v4, s3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v13, v13, v5
	v_mul_lo_u32 v4, s34, v6
	s_delay_alu instid0(VALU_DEP_2)
	v_sub_nc_u32_e32 v6, v13, v5
	v_cvt_f32_i32_e32 v13, v10
.LBB3_6:                                ;   Parent Loop BB3_2 Depth=1
                                        ;     Parent Loop BB3_4 Depth=2
                                        ; =>    This Loop Header: Depth=3
                                        ;         Child Loop BB3_7 Depth 4
	v_add_nc_u32_e32 v14, s45, v12
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v5, 31, v4
	s_mov_b64 s[26:27], 0
	v_lshlrev_b64 v[17:18], 2, v[4:5]
	v_mov_b32_e32 v5, 0
	v_ashrrev_i32_e32 v15, 31, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[14:15], 2, v[14:15]
	v_add_co_u32 v14, vcc_lo, s4, v14
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v15, vcc_lo, s5, v15, vcc_lo
	global_load_b32 v14, v[14:15], off
	v_add_co_u32 v15, vcc_lo, s10, v17
	v_add_co_ci_u32_e32 v16, vcc_lo, s11, v18, vcc_lo
	v_add_co_u32 v17, vcc_lo, s8, v17
	v_add_co_ci_u32_e32 v18, vcc_lo, s9, v18, vcc_lo
.LBB3_7:                                ;   Parent Loop BB3_2 Depth=1
                                        ;     Parent Loop BB3_4 Depth=2
                                        ;       Parent Loop BB3_6 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v19, vcc_lo, v15, s26
	v_add_co_ci_u32_e32 v20, vcc_lo, s27, v16, vcc_lo
	s_mov_b32 s46, exec_lo
	global_load_b32 v19, v[19:20], off
	s_waitcnt vmcnt(0)
	v_cmpx_lt_f32_e32 0, v19
	s_cbranch_execz .LBB3_9
; %bb.8:                                ;   in Loop: Header=BB3_7 Depth=4
	v_add_co_u32 v20, vcc_lo, v17, s26
	v_add_co_ci_u32_e32 v21, vcc_lo, s27, v18, vcc_lo
	global_load_b32 v22, v[20:21], off
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[20:21], null, s28, v22, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v21, 31, v20
	v_lshlrev_b64 v[20:21], 2, v[20:21]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v20, vcc_lo, s22, v20
	v_add_co_ci_u32_e32 v21, vcc_lo, s23, v21, vcc_lo
	global_load_b32 v20, v[20:21], off
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v5, v19, v20
.LBB3_9:                                ;   in Loop: Header=BB3_7 Depth=4
	s_or_b32 exec_lo, exec_lo, s46
	s_add_u32 s26, s26, 4
	s_addc_u32 s27, s27, 0
	s_cmp_eq_u32 s26, 16
	s_cbranch_scc0 .LBB3_7
; %bb.10:                               ;   in Loop: Header=BB3_6 Depth=3
	v_add_nc_u32_e32 v16, s39, v14
	s_add_i32 s45, s45, 1
	v_add_nc_u32_e32 v4, 4, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[14:15], null, v16, s19, v[6:7]
	v_ashrrev_i32_e32 v15, 31, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[14:15], 2, v[14:15]
	v_add_co_u32 v14, vcc_lo, s20, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v15, vcc_lo, s21, v15, vcc_lo
	global_load_b32 v14, v[14:15], off
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v5, v5, v14
	v_div_scale_f32 v14, null, v13, v13, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v15, v14
	s_waitcnt_depctr 0xfff
	v_fma_f32 v16, -v14, v15, 1.0
	v_fmac_f32_e32 v15, v16, v15
	v_div_scale_f32 v16, vcc_lo, v5, v13, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v17, v16, v15
	v_fma_f32 v18, -v14, v17, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v17, v18, v15
	v_fma_f32 v14, -v14, v17, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_fmas_f32 v14, v14, v15, v17
	v_cmp_eq_u32_e32 vcc_lo, s45, v10
	v_div_fixup_f32 v5, v14, v13, v5
	s_or_b32 s44, vcc_lo, s44
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f32_e32 v11, v11, v5
	global_store_b32 v[2:3], v11, off
	s_and_not1_b32 exec_lo, exec_lo, s44
	s_cbranch_execnz .LBB3_6
.LBB3_11:                               ; %Flow143
                                        ;   in Loop: Header=BB3_4 Depth=2
	s_or_b32 exec_lo, exec_lo, s43
	v_add_nc_u32_e32 v9, s41, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_le_i32_e32 vcc_lo, s15, v9
	s_or_b32 s42, vcc_lo, s42
	s_and_not1_b32 exec_lo, exec_lo, s42
	s_cbranch_execnz .LBB3_4
.LBB3_12:                               ; %Flow145
                                        ;   in Loop: Header=BB3_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s37
	s_add_i32 s14, s33, s14
	s_add_i32 s35, s35, s36
	s_cmp_ge_i32 s14, s16
	s_cbranch_scc0 .LBB3_2
.LBB3_13:                               ; %._crit_edge95
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z30fuzzy_depthwise_conv3d_forwardiiiiiiPKiS0_S0_PKfS2_S2_Pf
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 336
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 23
		.amdhsa_next_free_sgpr 47
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end3:
	.size	_Z30fuzzy_depthwise_conv3d_forwardiiiiiiPKiS0_S0_PKfS2_S2_Pf, .Lfunc_end3-_Z30fuzzy_depthwise_conv3d_forwardiiiiiiPKiS0_S0_PKfS2_S2_Pf
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1164
; NumSgprs: 49
; NumVgprs: 23
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 6
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 49
; NumVGPRsForWavesPerEU: 23
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z30fuzzy_depthwise_input_backwardiiiiiiPKiS0_S0_PKfS2_S2_S2_Pf ; -- Begin function _Z30fuzzy_depthwise_input_backwardiiiiiiPKiS0_S0_PKfS2_S2_S2_Pf
	.globl	_Z30fuzzy_depthwise_input_backwardiiiiiiPKiS0_S0_PKfS2_S2_S2_Pf
	.p2align	8
	.type	_Z30fuzzy_depthwise_input_backwardiiiiiiPKiS0_S0_PKfS2_S2_S2_Pf,@function
_Z30fuzzy_depthwise_input_backwardiiiiiiPKiS0_S0_PKfS2_S2_S2_Pf: ; @_Z30fuzzy_depthwise_input_backwardiiiiiiPKiS0_S0_PKfS2_S2_S2_Pf
; %bb.0:
	s_load_b128 s[16:19], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_cmp_ge_i32 s14, s16
	s_cbranch_scc1 .LBB4_15
; %bb.1:                                ; %.lr.ph96
	s_clause 0x2
	s_load_b64 s[2:3], s[0:1], 0x10
	s_load_b32 s33, s[0:1], 0x58
	s_load_b32 s26, s[0:1], 0x64
	s_add_u32 s12, s0, 0x58
	s_addc_u32 s13, s1, 0
	s_mul_i32 s35, s14, s18
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s28, s2, s19
	s_ashr_i32 s29, s2, 31
	s_ashr_i32 s30, s28, 31
	s_add_i32 s2, s2, s29
	s_add_i32 s4, s28, s30
	s_xor_b32 s2, s2, s29
	s_xor_b32 s31, s4, s30
	v_cvt_f32_u32_e32 v1, s2
	v_cvt_f32_u32_e32 v2, s31
	s_sub_i32 s20, 0, s2
	s_sub_i32 s21, 0, s31
	s_load_b256 s[4:11], s[0:1], 0x18
	v_rcp_iflag_f32_e32 v1, v1
	v_rcp_iflag_f32_e32 v2, v2
	s_lshl_b32 s34, s3, 2
	s_mul_i32 s36, s33, s18
	s_waitcnt_depctr 0xfff
	v_dual_mul_f32 v1, 0x4f7ffffe, v1 :: v_dual_mul_f32 v2, 0x4f7ffffe, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_u32_f32_e32 v3, v1
	v_cvt_u32_f32_e32 v4, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v5, s20, v3
	v_mul_lo_u32 v6, s21, v4
	s_clause 0x1
	s_load_b128 s[20:23], s[0:1], 0x40
	s_load_b64 s[24:25], s[0:1], 0x50
	s_and_b32 s1, s26, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[1:2], null, s15, s1, v[0:1]
	s_mul_i32 s15, s28, s18
	v_mul_hi_u32 v2, v3, v5
	v_mul_hi_u32 v0, v4, v6
	v_cmp_gt_i32_e64 s0, s15, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v12, v3, v2
	v_add_nc_u32_e32 v11, v4, v0
.LBB4_2:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB4_4 Depth 2
                                        ;       Child Loop BB4_6 Depth 3
                                        ;         Child Loop BB4_7 Depth 4
                                        ;         Child Loop BB4_11 Depth 4
	s_delay_alu instid0(VALU_DEP_3)
	s_and_saveexec_b32 s37, s0
	s_cbranch_execz .LBB4_14
; %bb.3:                                ; %.lr.ph92
                                        ;   in Loop: Header=BB4_2 Depth=1
	s_load_b32 s41, s[12:13], 0x4
	v_mov_b32_e32 v13, v1
	s_mul_i32 s38, s14, s18
	s_mul_i32 s39, s14, s17
	s_mul_i32 s40, s28, s38
	s_mov_b32 s42, 0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s41, s41, s1
.LBB4_4:                                ;   Parent Loop BB4_2 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB4_6 Depth 3
                                        ;         Child Loop BB4_7 Depth 4
                                        ;         Child Loop BB4_11 Depth 4
	v_ashrrev_i32_e32 v0, 31, v13
	s_mov_b32 s43, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v2, v13, v0
	v_xor_b32_e32 v2, v2, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v3, v2, v11
	v_mul_lo_u32 v4, v3, s31
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v2, v2, v4
	v_add_nc_u32_e32 v4, 1, v3
	v_subrev_nc_u32_e32 v5, s31, v2
	v_cmp_le_u32_e32 vcc_lo, s31, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v3, v3, v4 :: v_dual_cndmask_b32 v2, v2, v5
	v_xor_b32_e32 v4, s30, v0
	v_add_nc_u32_e32 v5, 1, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_le_u32_e32 vcc_lo, s31, v2
	v_cndmask_b32_e32 v0, v3, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v5, v0, v4
	v_sub_nc_u32_e32 v0, v5, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v2, s38, v0
	v_ashrrev_i32_e32 v3, 31, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[6:7], 2, v[2:3]
	v_add_co_u32 v6, vcc_lo, s6, v6
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v7, vcc_lo, s7, v7, vcc_lo
	global_load_b32 v14, v[6:7], off
	s_waitcnt vmcnt(0)
	v_cmpx_lt_i32_e32 0, v14
	s_cbranch_execz .LBB4_13
; %bb.5:                                ; %.lr.ph
                                        ;   in Loop: Header=BB4_4 Depth=2
	v_mul_lo_u32 v0, v0, s28
	v_mul_lo_u32 v15, v2, s3
	s_mov_b32 s44, 0
	s_mov_b32 s45, 0
	v_add_nc_u32_e32 v5, s35, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v0, v13, v0
	v_sub_nc_u32_e32 v16, v5, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v3, 31, v0
	v_mul_lo_u32 v2, s34, v16
	v_cvt_f32_i32_e32 v16, v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v6, v0, v3
	v_xor_b32_e32 v6, v6, v3
	v_xor_b32_e32 v3, s29, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v7, v6, v12
	v_mul_lo_u32 v8, v7, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v8, v6, v8
	v_add_nc_u32_e32 v6, 1, v7
	v_subrev_nc_u32_e32 v9, s2, v8
	v_cmp_le_u32_e32 vcc_lo, s2, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v10, v7, v6, vcc_lo
	v_cndmask_b32_e32 v8, v8, v9, vcc_lo
	v_add_nc_u32_e32 v6, s40, v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v9, 1, v10
	v_cmp_le_u32_e32 vcc_lo, s2, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_ashrrev_i32_e32 v7, 31, v6
	v_cndmask_b32_e32 v8, v10, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[4:5], 2, v[6:7]
	v_xor_b32_e32 v6, v8, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v4, vcc_lo, s22, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s23, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_3)
	v_sub_nc_u32_e32 v6, v6, v3
.LBB4_6:                                ;   Parent Loop BB4_2 Depth=1
                                        ;     Parent Loop BB4_4 Depth=2
                                        ; =>    This Loop Header: Depth=3
                                        ;         Child Loop BB4_7 Depth 4
                                        ;         Child Loop BB4_11 Depth 4
	v_add_nc_u32_e32 v7, s45, v15
	v_ashrrev_i32_e32 v3, 31, v2
	s_mov_b64 s[26:27], 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v8, 31, v7
	v_lshlrev_b64 v[17:18], 2, v[2:3]
	v_mov_b32_e32 v3, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[7:8], 2, v[7:8]
	v_add_co_u32 v7, vcc_lo, s4, v7
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v8, vcc_lo, s5, v8, vcc_lo
	global_load_b32 v7, v[7:8], off
	v_add_co_u32 v8, vcc_lo, s10, v17
	v_add_co_ci_u32_e32 v9, vcc_lo, s11, v18, vcc_lo
	v_add_co_u32 v10, vcc_lo, s8, v17
	v_add_co_ci_u32_e32 v17, vcc_lo, s9, v18, vcc_lo
.LBB4_7:                                ;   Parent Loop BB4_2 Depth=1
                                        ;     Parent Loop BB4_4 Depth=2
                                        ;       Parent Loop BB4_6 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v18, vcc_lo, v8, s26
	v_add_co_ci_u32_e32 v19, vcc_lo, s27, v9, vcc_lo
	s_mov_b32 s46, exec_lo
	global_load_b32 v18, v[18:19], off
	s_waitcnt vmcnt(0)
	v_cmpx_lt_f32_e32 0, v18
	s_cbranch_execz .LBB4_9
; %bb.8:                                ;   in Loop: Header=BB4_7 Depth=4
	v_add_co_u32 v19, vcc_lo, v10, s26
	v_add_co_ci_u32_e32 v20, vcc_lo, s27, v17, vcc_lo
	global_load_b32 v21, v[19:20], off
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[19:20], null, s28, v21, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v20, 31, v19
	v_lshlrev_b64 v[19:20], 2, v[19:20]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v19, vcc_lo, s20, v19
	v_add_co_ci_u32_e32 v20, vcc_lo, s21, v20, vcc_lo
	global_load_b32 v19, v[19:20], off
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v3, v18, v19
.LBB4_9:                                ;   in Loop: Header=BB4_7 Depth=4
	s_or_b32 exec_lo, exec_lo, s46
	s_add_u32 s26, s26, 4
	s_addc_u32 s27, s27, 0
	s_cmp_eq_u32 s26, 16
	s_cbranch_scc0 .LBB4_7
; %bb.10:                               ;   in Loop: Header=BB4_6 Depth=3
	global_load_b32 v9, v[4:5], off
	v_add_nc_u32_e32 v10, s39, v7
	s_mov_b32 s26, 0
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v3, v3, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[7:8], null, v10, s19, v[6:7]
	v_div_scale_f32 v9, null, v16, v16, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v8, 31, v7
	v_rcp_f32_e32 v17, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[7:8], 2, v[7:8]
	v_add_co_u32 v7, vcc_lo, s24, v7
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v8, vcc_lo, s25, v8, vcc_lo
	s_waitcnt_depctr 0xfff
	v_fma_f32 v18, -v9, v17, 1.0
	global_load_b32 v10, v[7:8], off
	v_fmac_f32_e32 v17, v18, v17
	v_div_scale_f32 v18, vcc_lo, v3, v16, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v19, v18, v17
	v_fma_f32 v20, -v9, v19, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v19, v20, v17
	v_fma_f32 v9, -v9, v19, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v9, v9, v17, v19
	v_div_fixup_f32 v3, v9, v16, v3
.LBB4_11:                               ; %atomicrmw.start
                                        ;   Parent Loop BB4_2 Depth=1
                                        ;     Parent Loop BB4_4 Depth=2
                                        ;       Parent Loop BB4_6 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f32_e32 v9, v10, v3
	global_atomic_cmpswap_b32 v9, v[7:8], v[9:10], off glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u32_e32 vcc_lo, v9, v10
	v_mov_b32_e32 v10, v9
	s_or_b32 s26, vcc_lo, s26
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s26
	s_cbranch_execnz .LBB4_11
; %bb.12:                               ; %atomicrmw.end
                                        ;   in Loop: Header=BB4_6 Depth=3
	s_or_b32 exec_lo, exec_lo, s26
	s_add_i32 s45, s45, 1
	v_add_nc_u32_e32 v2, 4, v2
	v_cmp_eq_u32_e32 vcc_lo, s45, v14
	s_or_b32 s44, vcc_lo, s44
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s44
	s_cbranch_execnz .LBB4_6
.LBB4_13:                               ; %Flow145
                                        ;   in Loop: Header=BB4_4 Depth=2
	s_or_b32 exec_lo, exec_lo, s43
	v_add_nc_u32_e32 v13, s41, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_le_i32_e32 vcc_lo, s15, v13
	s_or_b32 s42, vcc_lo, s42
	s_and_not1_b32 exec_lo, exec_lo, s42
	s_cbranch_execnz .LBB4_4
.LBB4_14:                               ; %Flow147
                                        ;   in Loop: Header=BB4_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s37
	s_add_i32 s14, s33, s14
	s_add_i32 s35, s35, s36
	s_cmp_ge_i32 s14, s16
	s_cbranch_scc0 .LBB4_2
.LBB4_15:                               ; %._crit_edge97
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z30fuzzy_depthwise_input_backwardiiiiiiPKiS0_S0_PKfS2_S2_S2_Pf
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 344
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 22
		.amdhsa_next_free_sgpr 47
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end4:
	.size	_Z30fuzzy_depthwise_input_backwardiiiiiiPKiS0_S0_PKfS2_S2_S2_Pf, .Lfunc_end4-_Z30fuzzy_depthwise_input_backwardiiiiiiPKiS0_S0_PKfS2_S2_S2_Pf
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1204
; NumSgprs: 49
; NumVgprs: 22
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 6
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 49
; NumVGPRsForWavesPerEU: 22
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z31fuzzy_depthwise_filter_backwardiiiiiiPKiS0_S0_PKfS2_S2_Pfii ; -- Begin function _Z31fuzzy_depthwise_filter_backwardiiiiiiPKiS0_S0_PKfS2_S2_Pfii
	.globl	_Z31fuzzy_depthwise_filter_backwardiiiiiiPKiS0_S0_PKfS2_S2_Pfii
	.p2align	8
	.type	_Z31fuzzy_depthwise_filter_backwardiiiiiiPKiS0_S0_PKfS2_S2_Pfii,@function
_Z31fuzzy_depthwise_filter_backwardiiiiiiPKiS0_S0_PKfS2_S2_Pfii: ; @_Z31fuzzy_depthwise_filter_backwardiiiiiiPKiS0_S0_PKfS2_S2_Pfii
; %bb.0:
	s_load_b64 s[6:7], s[0:1], 0x50
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_i32_e64 s2, s6, v0
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB5_3
; %bb.1:                                ; %.lr.ph
	s_load_b32 s4, s[0:1], 0x64
	v_lshl_add_u32 v1, v0, 2, 0
	v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v3, v0
	s_mov_b32 s5, 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s4, s4, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1)
	s_lshl_b32 s8, s4, 2
.LBB5_2:                                ; =>This Inner Loop Header: Depth=1
	v_add_nc_u32_e32 v3, s4, v3
	ds_store_b32 v1, v2
	v_add_nc_u32_e32 v1, s8, v1
	v_cmp_le_i32_e32 vcc_lo, s6, v3
	s_or_b32 s5, vcc_lo, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s5
	s_cbranch_execnz .LBB5_2
.LBB5_3:                                ; %Flow189
	s_or_b32 exec_lo, exec_lo, s3
	s_clause 0x3
	s_load_b128 s[8:11], s[0:1], 0x0
	s_load_b256 s[16:23], s[0:1], 0x18
	s_load_b128 s[24:27], s[0:1], 0x38
	s_load_b64 s[12:13], s[0:1], 0x48
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cmp_ge_i32 s14, s8
	s_cbranch_scc1 .LBB5_17
; %bb.4:                                ; %.lr.ph118
	s_load_b64 s[4:5], s[0:1], 0x10
	s_add_i32 s33, s7, s6
	s_add_u32 s28, s0, 0x58
	s_addc_u32 s29, s1, 0
	s_clause 0x1
	s_load_b32 s34, s[0:1], 0x58
	s_load_b32 s3, s[0:1], 0x64
	s_mul_i32 s42, s14, s10
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s35, s4, s11
	s_ashr_i32 s37, s4, 31
	s_ashr_i32 s36, s35, 31
	s_add_i32 s4, s4, s37
	s_add_i32 s30, s35, s36
	s_xor_b32 s39, s4, s37
	s_xor_b32 s38, s30, s36
	v_cvt_f32_u32_e32 v2, s39
	v_cvt_f32_u32_e32 v1, s38
	s_sub_i32 s4, 0, s38
	s_sub_i32 s30, 0, s39
	s_and_b32 s40, s3, 0xffff
	v_rcp_iflag_f32_e32 v2, v2
	v_rcp_iflag_f32_e32 v1, v1
	s_lshl_b32 s41, s5, 2
	s_mul_i32 s43, s34, s10
	s_waitcnt_depctr 0xfff
	v_dual_mul_f32 v2, 0x4f7ffffe, v2 :: v_dual_mul_f32 v1, 0x4f7ffffe, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_u32_f32_e32 v4, v2
	v_cvt_u32_f32_e32 v3, v1
	v_mad_u64_u32 v[1:2], null, s15, s40, v[0:1]
	s_mul_i32 s15, s35, s10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_lo_u32 v6, s30, v4
	v_mul_lo_u32 v5, s4, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_i32_e64 s3, s15, v1
	v_mul_hi_u32 v2, v3, v5
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v5, v4, v6
	v_add_nc_u32_e32 v8, v3, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_nc_u32_e32 v9, v4, v5
.LBB5_5:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB5_7 Depth 2
                                        ;       Child Loop BB5_9 Depth 3
                                        ;         Child Loop BB5_10 Depth 4
	s_and_saveexec_b32 s44, s3
	s_cbranch_execz .LBB5_16
; %bb.6:                                ; %.lr.ph114
                                        ;   in Loop: Header=BB5_5 Depth=1
	s_load_b32 s48, s[28:29], 0x4
	v_mov_b32_e32 v10, v1
	s_mul_i32 s45, s14, s10
	s_mul_i32 s46, s14, s9
	s_mul_i32 s47, s35, s45
	s_mov_b32 s49, 0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s48, s48, s40
.LBB5_7:                                ;   Parent Loop BB5_5 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB5_9 Depth 3
                                        ;         Child Loop BB5_10 Depth 4
	v_ashrrev_i32_e32 v2, 31, v10
	s_mov_b32 s50, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v3, v10, v2
	v_xor_b32_e32 v3, v3, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v4, v3, v8
	v_mul_lo_u32 v5, v4, s38
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v3, v3, v5
	v_add_nc_u32_e32 v5, 1, v4
	v_subrev_nc_u32_e32 v6, s38, v3
	v_cmp_le_u32_e32 vcc_lo, s38, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v4, v4, v5 :: v_dual_cndmask_b32 v3, v3, v6
	v_xor_b32_e32 v5, s36, v2
	v_add_nc_u32_e32 v6, 1, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_le_u32_e32 vcc_lo, s38, v3
	v_cndmask_b32_e32 v2, v4, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v6, v2, v5
	v_sub_nc_u32_e32 v2, v6, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v3, s45, v2
	v_ashrrev_i32_e32 v4, 31, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[11:12], 2, v[3:4]
	v_add_co_u32 v11, vcc_lo, s18, v11
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v12, vcc_lo, s19, v12, vcc_lo
	global_load_b32 v11, v[11:12], off
	s_waitcnt vmcnt(0)
	v_cmpx_lt_i32_e32 0, v11
	s_cbranch_execz .LBB5_15
; %bb.8:                                ; %.lr.ph110
                                        ;   in Loop: Header=BB5_7 Depth=2
	v_add_nc_u32_e32 v12, s47, v10
	v_mul_lo_u32 v2, v2, s35
	v_add_nc_u32_e32 v6, s42, v6
	s_mov_b32 s51, 0
	s_mov_b32 s52, 0
	v_ashrrev_i32_e32 v13, 31, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_sub_nc_u32_e32 v5, v6, v5
	v_sub_nc_u32_e32 v2, v10, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[12:13], 2, v[12:13]
	v_ashrrev_i32_e32 v4, 31, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v12, vcc_lo, s26, v12
	v_add_co_ci_u32_e32 v13, vcc_lo, s27, v13, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v7, v2, v4
	global_load_b32 v12, v[12:13], off
	v_xor_b32_e32 v7, v7, v4
	v_xor_b32_e32 v4, s37, v4
	v_mul_hi_u32 v13, v7, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v14, v13, s39
	v_sub_nc_u32_e32 v7, v7, v14
	v_add_nc_u32_e32 v14, 1, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v15, s39, v7
	v_cmp_le_u32_e32 vcc_lo, s39, v7
	v_cndmask_b32_e32 v7, v7, v15, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v13, v13, v14, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s39, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v14, 1, v13
	v_cndmask_b32_e32 v7, v13, v14, vcc_lo
	v_mul_lo_u32 v13, v3, s5
	v_mul_lo_u32 v3, s41, v5
	v_cvt_f32_i32_e32 v14, v11
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v6, v7, v4
	v_sub_nc_u32_e32 v5, v6, v4
.LBB5_9:                                ;   Parent Loop BB5_5 Depth=1
                                        ;     Parent Loop BB5_7 Depth=2
                                        ; =>    This Loop Header: Depth=3
                                        ;         Child Loop BB5_10 Depth 4
	v_add_nc_u32_e32 v6, s52, v13
	s_mov_b64 s[30:31], 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v7, 31, v6
	v_lshlrev_b64 v[6:7], 2, v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v6, vcc_lo, s16, v6
	v_add_co_ci_u32_e32 v7, vcc_lo, s17, v7, vcc_lo
	global_load_b32 v4, v[6:7], off
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v4, s46, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[6:7], null, v4, s11, v[5:6]
	v_ashrrev_i32_e32 v7, 31, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[6:7], 2, v[6:7]
	v_add_co_u32 v6, vcc_lo, s24, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v7, vcc_lo, s25, v7, vcc_lo
	global_load_b32 v4, v[6:7], off
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v18, v12, v4
	v_div_scale_f32 v15, null, v14, v14, v18
	v_div_scale_f32 v17, vcc_lo, v18, v14, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v16, v15
	s_waitcnt_depctr 0xfff
	v_fma_f32 v4, -v15, v16, 1.0
	v_fmac_f32_e32 v16, v4, v16
	v_ashrrev_i32_e32 v4, 31, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v19, v17, v16
	v_fma_f32 v6, -v15, v19, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v19, v6, v16
	v_lshlrev_b64 v[6:7], 2, v[3:4]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v17, -v15, v19, v17
	v_add_co_u32 v4, s4, s22, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v15, s4, s23, v7, s4
	v_div_fmas_f32 v19, v17, v16, v19
	v_add_co_u32 v16, vcc_lo, s20, v6
	v_add_co_ci_u32_e32 v17, vcc_lo, s21, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_3)
	v_div_fixup_f32 v18, v19, v14, v18
.LBB5_10:                               ;   Parent Loop BB5_5 Depth=1
                                        ;     Parent Loop BB5_7 Depth=2
                                        ;       Parent Loop BB5_9 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	v_add_co_u32 v6, vcc_lo, v4, s30
	v_add_co_ci_u32_e32 v7, vcc_lo, s31, v15, vcc_lo
	s_mov_b32 s53, exec_lo
	global_load_b32 v19, v[6:7], off
	s_waitcnt vmcnt(0)
	v_cmpx_lt_f32_e32 0, v19
	s_cbranch_execz .LBB5_13
; %bb.11:                               ;   in Loop: Header=BB5_10 Depth=4
	v_add_co_u32 v6, vcc_lo, v16, s30
	v_add_co_ci_u32_e32 v7, vcc_lo, s31, v17, vcc_lo
	global_load_b32 v20, v[6:7], off
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[6:7], null, s35, v20, v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_le_i32_e32 vcc_lo, s7, v6
	v_cmp_gt_i32_e64 s4, s33, v6
	s_and_b32 s4, vcc_lo, s4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 exec_lo, exec_lo, s4
	s_cbranch_execz .LBB5_13
; %bb.12:                               ;   in Loop: Header=BB5_10 Depth=4
	v_subrev_nc_u32_e32 v6, s7, v6
	v_mul_f32_e32 v7, v18, v19
	s_delay_alu instid0(VALU_DEP_2)
	v_lshl_add_u32 v6, v6, 2, 0
	ds_add_f32 v6, v7
.LBB5_13:                               ;   in Loop: Header=BB5_10 Depth=4
	s_or_b32 exec_lo, exec_lo, s53
	s_add_u32 s30, s30, 4
	s_addc_u32 s31, s31, 0
	s_cmp_eq_u32 s30, 16
	s_cbranch_scc0 .LBB5_10
; %bb.14:                               ;   in Loop: Header=BB5_9 Depth=3
	s_add_i32 s52, s52, 1
	v_add_nc_u32_e32 v3, 4, v3
	v_cmp_eq_u32_e32 vcc_lo, s52, v11
	s_or_b32 s51, vcc_lo, s51
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s51
	s_cbranch_execnz .LBB5_9
.LBB5_15:                               ; %Flow183
                                        ;   in Loop: Header=BB5_7 Depth=2
	s_or_b32 exec_lo, exec_lo, s50
	v_add_nc_u32_e32 v10, s48, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_le_i32_e32 vcc_lo, s15, v10
	s_or_b32 s49, vcc_lo, s49
	s_and_not1_b32 exec_lo, exec_lo, s49
	s_cbranch_execnz .LBB5_7
.LBB5_16:                               ; %Flow185
                                        ;   in Loop: Header=BB5_5 Depth=1
	s_or_b32 exec_lo, exec_lo, s44
	s_add_i32 s14, s34, s14
	s_add_i32 s42, s42, s43
	s_cmp_ge_i32 s14, s8
	s_cbranch_scc0 .LBB5_5
.LBB5_17:                               ; %._crit_edge119
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB5_22
; %bb.18:                               ; %.lr.ph122
	s_load_b32 s0, s[0:1], 0x64
	s_mov_b32 s1, 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s0, s0, 0xffff
.LBB5_19:                               ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB5_20 Depth 2
	v_add_nc_u32_e32 v1, s7, v0
	v_lshl_add_u32 v3, v0, 2, 0
	s_mov_b32 s2, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v2, 31, v1
	ds_load_b32 v5, v3
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s12, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, s13, v2, vcc_lo
	global_load_b32 v4, v[1:2], off
.LBB5_20:                               ; %atomicrmw.start
                                        ;   Parent Loop BB5_19 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f32_e32 v3, v4, v5
	global_atomic_cmpswap_b32 v3, v[1:2], v[3:4], off glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u32_e32 vcc_lo, v3, v4
	v_mov_b32_e32 v4, v3
	s_or_b32 s2, vcc_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s2
	s_cbranch_execnz .LBB5_20
; %bb.21:                               ; %atomicrmw.end
                                        ;   in Loop: Header=BB5_19 Depth=1
	s_or_b32 exec_lo, exec_lo, s2
	v_add_nc_u32_e32 v0, s0, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_le_i32_e32 vcc_lo, s6, v0
	s_or_b32 s1, vcc_lo, s1
	s_and_not1_b32 exec_lo, exec_lo, s1
	s_cbranch_execnz .LBB5_19
.LBB5_22:                               ; %Flow180
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z31fuzzy_depthwise_filter_backwardiiiiiiPKiS0_S0_PKfS2_S2_Pfii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 344
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 21
		.amdhsa_next_free_sgpr 54
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end5:
	.size	_Z31fuzzy_depthwise_filter_backwardiiiiiiPKiS0_S0_PKfS2_S2_Pfii, .Lfunc_end5-_Z31fuzzy_depthwise_filter_backwardiiiiiiPKiS0_S0_PKfS2_S2_Pfii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1476
; NumSgprs: 56
; NumVgprs: 21
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 6
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 56
; NumVGPRsForWavesPerEU: 21
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym gradPerBlock
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
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        .value_kind:     hidden_grid_dims
      - .offset:         208
        .size:           4
        .value_kind:     hidden_dynamic_lds_size
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 344
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z31fuzzy_depthwise_filter_backwardiiiiiiPKiS0_S0_PKfS2_S2_Pfii
    .private_segment_fixed_size: 0
    .sgpr_count:     56
    .sgpr_spill_count: 0
    .symbol:         _Z31fuzzy_depthwise_filter_backwardiiiiiiPKiS0_S0_PKfS2_S2_Pfii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     21
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
