#include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <math.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <time.h>

// Defined min and max functions 
#define MAX(x, y) (((x) > (y)) ? (x) : (y))
#define MIN(x, y) (((x) < (y)) ? (x) : (y))


__global__ void mergeSort(int* startingArr, int* endingArr, unsigned int N, unsigned int sortedArraySize, unsigned int threads, unsigned int totalSortedArrays) {

	// Assigns thread ID 
	unsigned int id = threadIdx.x + blockIdx.x * blockDim.x;

	// index of the first element of the first sorted array that this thread is responsible for
	unsigned startElementIndex = id * sortedArraySize;

	// loop through each of the sorted arrays that this thread is responsible for merging
	for (unsigned int currentArray = id; currentArray < totalSortedArrays; currentArray += threads) {

		// calculate the middle and end element indices for this merge
		unsigned arrayMiddle = MIN(startElementIndex + (sortedArraySize / 2), N);
		unsigned arrayEnd = MIN(startElementIndex + sortedArraySize, N);

		// create variables to hold the left and right indices of the merge as it proceeds
		unsigned int leftArrayIndex = startElementIndex;
		unsigned int rightArrayIndex = arrayMiddle;

		// perform the merge of two sorted sub-arrays into one sorted array
		for (unsigned int i = startElementIndex; i < arrayEnd; i++) {

			// If middle array is larger, temp start is index in sorted array 
			if (leftArrayIndex < arrayMiddle && (rightArrayIndex >= arrayEnd || startingArr[leftArrayIndex] < startingArr[rightArrayIndex])) {
				endingArr[i] = startingArr[leftArrayIndex];
				leftArrayIndex++;
			}

			// If middle array start is smaller, middle array is index in sorted array 
			else {
				endingArr[i] = startingArr[rightArrayIndex];
				rightArrayIndex++;
			}
		}

		// increment to the start point of the next merge
		startElementIndex += threads * sortedArraySize;
	}
}

int main() {
	printf("Parallelized Merge Sort Has Begun");

	unsigned int N = 1000000;
	unsigned int threads = 32;
	if (threads > 1024) {
		threads = 1024;
	}

	// Define arrays for system
	int* startingArray = new int[N];
	int* endingArray = new int[N];
	int* cudaStartArray;
	int* cudaEndArray;

	// Initialize array to random values 0 and 10000   
	for (int i = 0; i < N; i++) {
		startingArray[i] = rand() % 10000;
	}

	// Copy starting Array values into end Array
	memcpy(endingArray, startingArray, N * sizeof(int));

	// Clock variable
	clock_t startTime = clock();

	// iterate through the levels of the merge tree, using the size of the individual sorted arrays at each level as the loop index
	for (unsigned int sortedArraySize = 2; sortedArraySize < N * 2; sortedArraySize = sortedArraySize * 2) {
		clock_t loopTime = clock();

		cudaSetDevice(0);

		// Allocate memory on device for the original list and the list at the end of this step
		cudaMalloc((void**)& cudaStartArray, N * sizeof(int));
		cudaMalloc((void**)& cudaEndArray, N * sizeof(int));

		// Copy data from host to device
		cudaMemcpy(cudaStartArray, startingArray, N * sizeof(int), cudaMemcpyHostToDevice);
		cudaMemcpy(cudaEndArray, endingArray, N * sizeof(int), cudaMemcpyHostToDevice);

		// calculate how many individual arrays there are at this level of the merge tree
		unsigned int totalSortedArrays = N / sortedArraySize + (N % sortedArraySize != 0);

		// call MergeSort kernel function
		mergeSort <<<1, threads>>> (cudaStartArray, cudaEndArray, N, sortedArraySize, threads, totalSortedArrays);

		// Synchronize threads 
		cudaDeviceSynchronize();

		// Copy resulting list to host
		cudaMemcpy(endingArray, cudaEndArray, N * sizeof(int), cudaMemcpyDeviceToHost);

		// Free cuda memory 
		cudaFree(cudaStartArray);
		cudaFree(cudaEndArray);

		// Copies endingArray to startingArray to prepare for the next step
		memcpy(startingArray, endingArray, N * sizeof(int));

		// printing timing results
		printf("\nMerge Tree Level: %d || Size of Sorted Arrays: %d  || Level Merge Time:  %f", (int)log2(sortedArraySize), sortedArraySize, (float)(clock() - loopTime) / CLOCKS_PER_SEC);
	}

	printf(" \nFINAL ITERATION : ");

	// Checks to see if merge sorted matrix is properly sorted 
	bool isTrue = true;
	for (unsigned int i = 0; i < N; i++) {
		//printf("%d \n", endingArray[j]);
		if (i > 0) {
			if (endingArray[i] < endingArray[i - 1]) {
				isTrue = false;
			}
		}
	}

	// Prints if matrix has or hasn't been sorted 
	if (isTrue) {
		printf("The Input Array Is Sorted From Merge Sort \n");
	}
	else {
		printf("The Input Array Is Not Sorted From Merge Sort \n");
	}

	// Prints total time of system 
	printf("Total Merge Sort Time :  %f", ((float)(clock() - startTime)) / CLOCKS_PER_SEC);

	return 0;
}
	.file	"tmpxft_002ec947_00000000-6_ParallelMergeSort.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2030:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z34__device_stub__Z9mergeSortPiS_jjjjPiS_jjjj
	.type	_Z34__device_stub__Z9mergeSortPiS_jjjjPiS_jjjj, @function
_Z34__device_stub__Z9mergeSortPiS_jjjjPiS_jjjj:
.LFB2052:
	.cfi_startproc
	endbr64
	subq	$168, %rsp
	.cfi_def_cfa_offset 176
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	48(%rsp), %rcx
	movl	%r8d, 4(%rsp)
	movl	%r9d, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 152(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 136(%rsp)
	movq	%rsp, %rax
	movq	%rax, 144(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	48(%rsp)
	.cfi_def_cfa_offset 184
	leaq	_Z9mergeSortPiS_jjjj(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 192
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 184
	popq	%rdx
	.cfi_def_cfa_offset 176
.L2:
	movq	152(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$168, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2052:
	.size	_Z34__device_stub__Z9mergeSortPiS_jjjjPiS_jjjj, .-_Z34__device_stub__Z9mergeSortPiS_jjjjPiS_jjjj
	.globl	_Z9mergeSortPiS_jjjj
	.type	_Z9mergeSortPiS_jjjj, @function
_Z9mergeSortPiS_jjjj:
.LFB2053:
	.cfi_startproc
	endbr64
	jmp	_Z34__device_stub__Z9mergeSortPiS_jjjjPiS_jjjj
	.cfi_endproc
.LFE2053:
	.size	_Z9mergeSortPiS_jjjj, .-_Z9mergeSortPiS_jjjj
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"Parallelized Merge Sort Has Begun"
.LC2:
	.string	"\nMerge Tree Level: %d || Size of Sorted Arrays: %d  || Level Merge Time:  %f"
.LC3:
	.string	" \nFINAL ITERATION : "
.LC4:
	.string	"The Input Array Is Sorted From Merge Sort \n"
.LC5:
	.string	"The Input Array Is Not Sorted From Merge Sort \n"
.LC6:
	.string	"Total Merge Sort Time :  %f"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	leaq	.LC0(%rip), %rsi
	movl	$2, %edi
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movl	$10000, %r13d
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	xorl	%r12d, %r12d
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$72, %rsp
	.cfi_def_cfa_offset 128
	movq	%fs:40, %rax
	movq	%rax, 56(%rsp)
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movl	$4000000, %edi
	call	_Znam@PLT
	movl	$4000000, %edi
	movq	%rax, %rbp
	call	_Znam@PLT
	movq	%rax, %rbx
.L9:
	call	rand@PLT
	cltd
	idivl	%r13d
	movl	%edx, 0(%rbp,%r12,4)
	incq	%r12
	cmpq	$1000000, %r12
	jne	.L9
	movq	%r12, %rcx
	movq	%rbx, %rdi
	movq	%rbp, %rsi
	movl	$20, %r14d
	rep movsl
	movl	$2, %r12d
	call	clock@PLT
	movq	%rax, %r13
.L11:
	call	clock@PLT
	xorl	%edi, %edi
	movq	%rax, %r15
	call	cudaSetDevice@PLT
	leaq	16(%rsp), %rdi
	movl	$4000000, %esi
	call	cudaMalloc@PLT
	leaq	24(%rsp), %rdi
	movl	$4000000, %esi
	call	cudaMalloc@PLT
	movq	16(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbp, %rsi
	movl	$4000000, %edx
	call	cudaMemcpy@PLT
	movq	24(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbx, %rsi
	movl	$4000000, %edx
	call	cudaMemcpy@PLT
	movl	$134217729, %edx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	salq	$5, %rdx
	movl	$1, %ecx
	movl	$1, %esi
	movabsq	$4294967297, %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L10
	xorl	%edx, %edx
	movl	$1000000, %eax
	movq	24(%rsp), %rsi
	movl	%r12d, %ecx
	divl	%r12d
	movq	16(%rsp), %rdi
	movl	$32, %r8d
	cmpl	$1, %edx
	movl	$1000000, %edx
	sbbl	$-1, %eax
	movl	%eax, %r9d
	call	_Z34__device_stub__Z9mergeSortPiS_jjjjPiS_jjjj
.L10:
	call	cudaDeviceSynchronize@PLT
	movq	24(%rsp), %rsi
	movl	$4000000, %edx
	movq	%rbx, %rdi
	movl	$2, %ecx
	call	cudaMemcpy@PLT
	movq	16(%rsp), %rdi
	call	cudaFree@PLT
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	movl	$1000000, %ecx
	movq	%rbp, %rdi
	movq	%rbx, %rsi
	rep movsl
	call	clock@PLT
	cvtsi2sdl	%r12d, %xmm0
	movq	%rax, 8(%rsp)
	call	log2@PLT
	movq	8(%rsp), %rax
	movl	%r12d, %ecx
	leaq	.LC2(%rip), %rsi
	movaps	%xmm0, %xmm1
	movl	$2, %edi
	addl	%r12d, %r12d
	cvttsd2sil	%xmm1, %edx
	subq	%r15, %rax
	cvtsi2ssq	%rax, %xmm0
	movb	$1, %al
	divss	.LC1(%rip), %xmm0
	cvtss2sd	%xmm0, %xmm0
	call	__printf_chk@PLT
	decl	%r14d
	jne	.L11
	leaq	.LC3(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	xorl	%eax, %eax
	movb	$1, %dl
	xorl	%ecx, %ecx
.L13:
	testq	%rax, %rax
	je	.L12
	leal	-1(%rax), %esi
	movl	(%rbx,%rsi,4), %edi
	cmpl	%edi, (%rbx,%rax,4)
	cmovl	%ecx, %edx
.L12:
	incq	%rax
	cmpq	$1000000, %rax
	jne	.L13
	leaq	.LC4(%rip), %rsi
	testb	%dl, %dl
	jne	.L25
	leaq	.LC5(%rip), %rsi
.L25:
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	call	clock@PLT
	leaq	.LC6(%rip), %rsi
	movl	$2, %edi
	subq	%r13, %rax
	cvtsi2ssq	%rax, %xmm0
	movb	$1, %al
	divss	.LC1(%rip), %xmm0
	cvtss2sd	%xmm0, %xmm0
	call	__printf_chk@PLT
	movq	56(%rsp), %rax
	subq	%fs:40, %rax
	je	.L16
	call	__stack_chk_fail@PLT
.L16:
	addq	$72, %rsp
	.cfi_def_cfa_offset 56
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2027:
	.size	main, .-main
	.section	.rodata.str1.1
.LC7:
	.string	"_Z9mergeSortPiS_jjjj"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC7(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z9mergeSortPiS_jjjj(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2055:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst4,"aM",@progbits,4
	.align 4
.LC1:
	.long	1232348160
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include "hip/hip_runtime.h"

#include <math.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <time.h>

// Defined min and max functions 
#define MAX(x, y) (((x) > (y)) ? (x) : (y))
#define MIN(x, y) (((x) < (y)) ? (x) : (y))


__global__ void mergeSort(int* startingArr, int* endingArr, unsigned int N, unsigned int sortedArraySize, unsigned int threads, unsigned int totalSortedArrays) {

	// Assigns thread ID 
	unsigned int id = threadIdx.x + blockIdx.x * blockDim.x;

	// index of the first element of the first sorted array that this thread is responsible for
	unsigned startElementIndex = id * sortedArraySize;

	// loop through each of the sorted arrays that this thread is responsible for merging
	for (unsigned int currentArray = id; currentArray < totalSortedArrays; currentArray += threads) {

		// calculate the middle and end element indices for this merge
		unsigned arrayMiddle = MIN(startElementIndex + (sortedArraySize / 2), N);
		unsigned arrayEnd = MIN(startElementIndex + sortedArraySize, N);

		// create variables to hold the left and right indices of the merge as it proceeds
		unsigned int leftArrayIndex = startElementIndex;
		unsigned int rightArrayIndex = arrayMiddle;

		// perform the merge of two sorted sub-arrays into one sorted array
		for (unsigned int i = startElementIndex; i < arrayEnd; i++) {

			// If middle array is larger, temp start is index in sorted array 
			if (leftArrayIndex < arrayMiddle && (rightArrayIndex >= arrayEnd || startingArr[leftArrayIndex] < startingArr[rightArrayIndex])) {
				endingArr[i] = startingArr[leftArrayIndex];
				leftArrayIndex++;
			}

			// If middle array start is smaller, middle array is index in sorted array 
			else {
				endingArr[i] = startingArr[rightArrayIndex];
				rightArrayIndex++;
			}
		}

		// increment to the start point of the next merge
		startElementIndex += threads * sortedArraySize;
	}
}

int main() {
	printf("Parallelized Merge Sort Has Begun");

	unsigned int N = 1000000;
	unsigned int threads = 32;
	if (threads > 1024) {
		threads = 1024;
	}

	// Define arrays for system
	int* startingArray = new int[N];
	int* endingArray = new int[N];
	int* cudaStartArray;
	int* cudaEndArray;

	// Initialize array to random values 0 and 10000   
	for (int i = 0; i < N; i++) {
		startingArray[i] = rand() % 10000;
	}

	// Copy starting Array values into end Array
	memcpy(endingArray, startingArray, N * sizeof(int));

	// Clock variable
	clock_t startTime = clock();

	// iterate through the levels of the merge tree, using the size of the individual sorted arrays at each level as the loop index
	for (unsigned int sortedArraySize = 2; sortedArraySize < N * 2; sortedArraySize = sortedArraySize * 2) {
		clock_t loopTime = clock();

		hipSetDevice(0);

		// Allocate memory on device for the original list and the list at the end of this step
		hipMalloc((void**)& cudaStartArray, N * sizeof(int));
		hipMalloc((void**)& cudaEndArray, N * sizeof(int));

		// Copy data from host to device
		hipMemcpy(cudaStartArray, startingArray, N * sizeof(int), hipMemcpyHostToDevice);
		hipMemcpy(cudaEndArray, endingArray, N * sizeof(int), hipMemcpyHostToDevice);

		// calculate how many individual arrays there are at this level of the merge tree
		unsigned int totalSortedArrays = N / sortedArraySize + (N % sortedArraySize != 0);

		// call MergeSort kernel function
		mergeSort <<<1, threads>>> (cudaStartArray, cudaEndArray, N, sortedArraySize, threads, totalSortedArrays);

		// Synchronize threads 
		hipDeviceSynchronize();

		// Copy resulting list to host
		hipMemcpy(endingArray, cudaEndArray, N * sizeof(int), hipMemcpyDeviceToHost);

		// Free cuda memory 
		hipFree(cudaStartArray);
		hipFree(cudaEndArray);

		// Copies endingArray to startingArray to prepare for the next step
		memcpy(startingArray, endingArray, N * sizeof(int));

		// printing timing results
		printf("\nMerge Tree Level: %d || Size of Sorted Arrays: %d  || Level Merge Time:  %f", (int)log2(sortedArraySize), sortedArraySize, (float)(clock() - loopTime) / CLOCKS_PER_SEC);
	}

	printf(" \nFINAL ITERATION : ");

	// Checks to see if merge sorted matrix is properly sorted 
	bool isTrue = true;
	for (unsigned int i = 0; i < N; i++) {
		//printf("%d \n", endingArray[j]);
		if (i > 0) {
			if (endingArray[i] < endingArray[i - 1]) {
				isTrue = false;
			}
		}
	}

	// Prints if matrix has or hasn't been sorted 
	if (isTrue) {
		printf("The Input Array Is Sorted From Merge Sort \n");
	}
	else {
		printf("The Input Array Is Not Sorted From Merge Sort \n");
	}

	// Prints total time of system 
	printf("Total Merge Sort Time :  %f", ((float)(clock() - startTime)) / CLOCKS_PER_SEC);

	return 0;
}
	.text
	.file	"ParallelMergeSort.hip"
	.globl	_Z24__device_stub__mergeSortPiS_jjjj # -- Begin function _Z24__device_stub__mergeSortPiS_jjjj
	.type	_Z24__device_stub__mergeSortPiS_jjjj,@function
_Z24__device_stub__mergeSortPiS_jjjj:   # @_Z24__device_stub__mergeSortPiS_jjjj
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	4(%rsp), %rcx
	movl	%r8d, (%rcx)
	movq	%rsp, %r8
	movl	%r9d, (%r8)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z9mergeSortPiS_jjjj, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z24__device_stub__mergeSortPiS_jjjj, .Lfunc_end0-_Z24__device_stub__mergeSortPiS_jjjj
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0                          # -- Begin function main
.LCPI1_0:
	.long	0x49742400                      # float 1.0E+6
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$24, %rsp
	.cfi_def_cfa_offset 80
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	xorl	%r14d, %r14d
	movl	$.L.str, %edi
	xorl	%eax, %eax
	callq	printf
	movl	$4000000, %edi                  # imm = 0x3D0900
	callq	_Znam
	movq	%rax, %r15
	movl	$4000000, %edi                  # imm = 0x3D0900
	callq	_Znam
	movq	%rax, %rbx
.LBB1_1:                                # =>This Inner Loop Header: Depth=1
	callq	rand
	cltq
	imulq	$1759218605, %rax, %rcx         # imm = 0x68DB8BAD
	movq	%rcx, %rdx
	shrq	$63, %rdx
	sarq	$44, %rcx
	addl	%edx, %ecx
	imull	$10000, %ecx, %ecx              # imm = 0x2710
	subl	%ecx, %eax
	movl	%eax, (%r15,%r14,4)
	incq	%r14
	cmpq	$1000000, %r14                  # imm = 0xF4240
	jne	.LBB1_1
# %bb.2:
	movabsq	$4294967297, %r14               # imm = 0x100000001
	movl	$4000000, %edx                  # imm = 0x3D0900
	movq	%rbx, %rdi
	movq	%r15, %rsi
	callq	memcpy@PLT
	movl	$2, %r13d
	callq	clock
	movq	%rax, 16(%rsp)                  # 8-byte Spill
	leaq	31(%r14), %r12
.LBB1_3:                                # =>This Inner Loop Header: Depth=1
	callq	clock
	movq	%rax, %rbp
	xorl	%edi, %edi
	callq	hipSetDevice
	movl	$4000000, %esi                  # imm = 0x3D0900
	leaq	8(%rsp), %rdi
	callq	hipMalloc
	movl	$4000000, %esi                  # imm = 0x3D0900
	movq	%rsp, %rdi
	callq	hipMalloc
	movq	8(%rsp), %rdi
	movl	$4000000, %edx                  # imm = 0x3D0900
	movq	%r15, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%rsp), %rdi
	movl	$4000000, %edx                  # imm = 0x3D0900
	movq	%rbx, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movabsq	$4294967297, %rdi               # imm = 0x100000001
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_5
# %bb.4:                                #   in Loop: Header=BB1_3 Depth=1
	movl	$1000000, %eax                  # imm = 0xF4240
	xorl	%edx, %edx
	divl	%r13d
	leal	-1(%r13), %ecx
	movl	$1000000, %edx                  # imm = 0xF4240
	andl	%edx, %ecx
	cmpl	$1, %ecx
	sbbl	$-1, %eax
	movq	8(%rsp), %rdi
	movq	(%rsp), %rsi
	movl	%r13d, %ecx
	movl	$32, %r8d
	movl	%eax, %r9d
	callq	_Z24__device_stub__mergeSortPiS_jjjj
.LBB1_5:                                #   in Loop: Header=BB1_3 Depth=1
	callq	hipDeviceSynchronize
	movq	(%rsp), %rsi
	movl	$4000000, %edx                  # imm = 0x3D0900
	movq	%rbx, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movq	8(%rsp), %rdi
	callq	hipFree
	movq	(%rsp), %rdi
	callq	hipFree
	movl	$4000000, %edx                  # imm = 0x3D0900
	movq	%r15, %rdi
	movq	%rbx, %rsi
	callq	memcpy@PLT
	movl	%r13d, %eax
	xorps	%xmm0, %xmm0
	cvtsi2sd	%rax, %xmm0
	callq	log2
	cvttsd2si	%xmm0, %r14d
	callq	clock
	subq	%rbp, %rax
	xorps	%xmm0, %xmm0
	cvtsi2ss	%rax, %xmm0
	divss	.LCPI1_0(%rip), %xmm0
	cvtss2sd	%xmm0, %xmm0
	movl	$.L.str.1, %edi
	movl	%r14d, %esi
	movl	%r13d, %edx
	movb	$1, %al
	callq	printf
	leal	(,%r13,2), %eax
	cmpl	$1000000, %r13d                 # imm = 0xF4240
	movl	%eax, %r13d
	jb	.LBB1_3
# %bb.6:
	xorl	%r14d, %r14d
	movl	$.L.str.2, %edi
	xorl	%eax, %eax
	callq	printf
	movb	$1, %al
	xorl	%ecx, %ecx
.LBB1_7:                                # =>This Inner Loop Header: Depth=1
	testq	%rcx, %rcx
	je	.LBB1_9
# %bb.8:                                #   in Loop: Header=BB1_7 Depth=1
	movl	(%rbx,%rcx,4), %edx
	cmpl	-4(%rbx,%rcx,4), %edx
	movzbl	%al, %eax
	cmovll	%r14d, %eax
.LBB1_9:                                #   in Loop: Header=BB1_7 Depth=1
	incq	%rcx
	cmpq	$1000000, %rcx                  # imm = 0xF4240
	jne	.LBB1_7
# %bb.10:
	testb	$1, %al
	movl	$.Lstr, %eax
	movl	$.Lstr.1, %edi
	cmoveq	%rax, %rdi
	callq	puts@PLT
	callq	clock
	subq	16(%rsp), %rax                  # 8-byte Folded Reload
	xorps	%xmm0, %xmm0
	cvtsi2ss	%rax, %xmm0
	divss	.LCPI1_0(%rip), %xmm0
	cvtss2sd	%xmm0, %xmm0
	movl	$.L.str.5, %edi
	movb	$1, %al
	callq	printf
	xorl	%eax, %eax
	addq	$24, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	main, .Lfunc_end1-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z9mergeSortPiS_jjjj, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z9mergeSortPiS_jjjj,@object    # @_Z9mergeSortPiS_jjjj
	.section	.rodata,"a",@progbits
	.globl	_Z9mergeSortPiS_jjjj
	.p2align	3, 0x0
_Z9mergeSortPiS_jjjj:
	.quad	_Z24__device_stub__mergeSortPiS_jjjj
	.size	_Z9mergeSortPiS_jjjj, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"Parallelized Merge Sort Has Begun"
	.size	.L.str, 34

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"\nMerge Tree Level: %d || Size of Sorted Arrays: %d  || Level Merge Time:  %f"
	.size	.L.str.1, 77

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	" \nFINAL ITERATION : "
	.size	.L.str.2, 21

	.type	.L.str.5,@object                # @.str.5
.L.str.5:
	.asciz	"Total Merge Sort Time :  %f"
	.size	.L.str.5, 28

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z9mergeSortPiS_jjjj"
	.size	.L__unnamed_1, 21

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.type	.Lstr,@object                   # @str
	.section	.rodata.str1.1,"aMS",@progbits,1
.Lstr:
	.asciz	"The Input Array Is Not Sorted From Merge Sort "
	.size	.Lstr, 47

	.type	.Lstr.1,@object                 # @str.1
.Lstr.1:
	.asciz	"The Input Array Is Sorted From Merge Sort "
	.size	.Lstr.1, 43

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z24__device_stub__mergeSortPiS_jjjj
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z9mergeSortPiS_jjjj
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z9mergeSortPiS_jjjj    ; -- Begin function _Z9mergeSortPiS_jjjj
	.globl	_Z9mergeSortPiS_jjjj
	.p2align	8
	.type	_Z9mergeSortPiS_jjjj,@function
_Z9mergeSortPiS_jjjj:                   ; @_Z9mergeSortPiS_jjjj
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x2c
	s_load_b128 s[4:7], s[0:1], 0x10
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_u32_e64 s7, v1
	s_cbranch_execz .LBB0_17
; %bb.1:                                ; %.lr.ph62
	s_load_b128 s[8:11], s[0:1], 0x0
	v_mul_lo_u32 v2, v1, s5
	v_mov_b32_e32 v4, 0
	s_lshr_b32 s1, s5, 1
	s_mul_i32 s2, s6, s5
	s_mov_b32 s3, 0
                                        ; implicit-def: $vgpr0
.LBB0_2:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_4 Depth 2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v3, s5, v2
	s_mov_b32 s12, exec_lo
	v_min_u32_e32 v9, s4, v3
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_u32_e64 v2, v9
	s_cbranch_execz .LBB0_16
; %bb.3:                                ; %.lr.ph.preheader
                                        ;   in Loop: Header=BB0_2 Depth=1
	v_add_nc_u32_e32 v5, s1, v2
	v_mov_b32_e32 v3, v4
	v_mov_b32_e32 v11, v2
	s_mov_b32 s13, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_min_u32_e32 v10, s4, v5
	v_lshlrev_b64 v[5:6], 2, v[2:3]
	v_mov_b32_e32 v3, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mov_b32_e32 v7, v10
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v5, vcc_lo, s10, v5
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v6, vcc_lo, s11, v6, vcc_lo
.LBB0_4:                                ; %.lr.ph
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_mov_b32 s14, 0
	s_mov_b32 s0, exec_lo
                                        ; implicit-def: $vgpr8
	v_cmpx_ge_u32_e64 v3, v10
	s_xor_b32 s0, exec_lo, s0
	s_cbranch_execz .LBB0_6
; %bb.5:                                ; %.lr.ph._crit_edge
                                        ;   in Loop: Header=BB0_4 Depth=2
	s_waitcnt vmcnt(0)
	v_mov_b32_e32 v8, v4
	s_mov_b32 s14, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[12:13], 2, v[7:8]
	v_add_co_u32 v12, vcc_lo, s8, v12
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v13, vcc_lo, s9, v13, vcc_lo
	global_load_b32 v8, v[12:13], off
.LBB0_6:                                ; %Flow
                                        ;   in Loop: Header=BB0_4 Depth=2
	s_or_saveexec_b32 s15, s0
	s_mov_b32 s0, 0
	s_xor_b32 exec_lo, exec_lo, s15
	s_cbranch_execz .LBB0_10
; %bb.7:                                ;   in Loop: Header=BB0_4 Depth=2
	v_lshlrev_b64 v[12:13], 2, v[3:4]
	s_mov_b32 s0, -1
	s_mov_b32 s17, s14
	s_mov_b32 s16, exec_lo
                                        ; implicit-def: $vgpr8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v12, vcc_lo, s8, v12
	v_add_co_ci_u32_e32 v13, vcc_lo, s9, v13, vcc_lo
	global_load_b32 v0, v[12:13], off
	v_cmpx_lt_u32_e64 v7, v9
	s_cbranch_execz .LBB0_9
; %bb.8:                                ;   in Loop: Header=BB0_4 Depth=2
	s_waitcnt vmcnt(1)
	v_mov_b32_e32 v8, v4
	s_and_not1_b32 s17, s14, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[12:13], 2, v[7:8]
	v_add_co_u32 v12, vcc_lo, s8, v12
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v13, vcc_lo, s9, v13, vcc_lo
	global_load_b32 v8, v[12:13], off
	s_waitcnt vmcnt(0)
	v_cmp_ge_i32_e32 vcc_lo, v0, v8
	v_cmp_lt_i32_e64 s0, v0, v8
	s_and_b32 s18, vcc_lo, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	s_or_not1_b32 s0, s0, exec_lo
	s_or_b32 s17, s17, s18
.LBB0_9:                                ; %Flow90
                                        ;   in Loop: Header=BB0_4 Depth=2
	s_or_b32 exec_lo, exec_lo, s16
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 s14, s14, exec_lo
	s_and_b32 s16, s17, exec_lo
	s_and_b32 s0, s0, exec_lo
	s_or_b32 s14, s14, s16
.LBB0_10:                               ; %Flow89
                                        ;   in Loop: Header=BB0_4 Depth=2
	s_or_b32 exec_lo, exec_lo, s15
                                        ; implicit-def: $vgpr12
	s_and_saveexec_b32 s15, s14
	s_cbranch_execz .LBB0_12
; %bb.11:                               ;   in Loop: Header=BB0_4 Depth=2
	v_add_nc_u32_e32 v12, 1, v7
	s_waitcnt vmcnt(0)
	global_store_b32 v[5:6], v8, off
.LBB0_12:                               ; %Flow91
                                        ;   in Loop: Header=BB0_4 Depth=2
	s_or_b32 exec_lo, exec_lo, s15
	s_and_saveexec_b32 s14, s0
	s_cbranch_execz .LBB0_14
; %bb.13:                               ; %._crit_edge65
                                        ;   in Loop: Header=BB0_4 Depth=2
	v_dual_mov_b32 v12, v7 :: v_dual_add_nc_u32 v3, 1, v3
	s_waitcnt vmcnt(0)
	global_store_b32 v[5:6], v0, off
.LBB0_14:                               ;   in Loop: Header=BB0_4 Depth=2
	s_or_b32 exec_lo, exec_lo, s14
	v_add_nc_u32_e32 v11, 1, v11
	v_add_co_u32 v5, s0, v5, 4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v6, s0, 0, v6, s0
	v_cmp_ge_u32_e32 vcc_lo, v11, v9
	v_mov_b32_e32 v7, v12
	s_or_b32 s13, vcc_lo, s13
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s13
	s_cbranch_execnz .LBB0_4
; %bb.15:                               ; %Flow92
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s13
.LBB0_16:                               ; %Flow93
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	s_or_b32 exec_lo, exec_lo, s12
	v_add_nc_u32_e32 v1, s6, v1
	v_add_nc_u32_e32 v2, s2, v2
	v_cmp_le_u32_e32 vcc_lo, s7, v1
	s_or_b32 s3, vcc_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s3
	s_cbranch_execnz .LBB0_2
.LBB0_17:                               ; %Flow95
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z9mergeSortPiS_jjjj
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 14
		.amdhsa_next_free_sgpr 19
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z9mergeSortPiS_jjjj, .Lfunc_end0-_Z9mergeSortPiS_jjjj
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 600
; NumSgprs: 21
; NumVgprs: 14
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 21
; NumVGPRsForWavesPerEU: 14
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z9mergeSortPiS_jjjj
    .private_segment_fixed_size: 0
    .sgpr_count:     21
    .sgpr_spill_count: 0
    .symbol:         _Z9mergeSortPiS_jjjj.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     14
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
