/******************************************************************************
 *cr
 *cr         (C) Copyright 2010-2013 The Board of Trustees of the
 *cr                        University of Illinois
 *cr                         All Rights Reserved
 *cr
 ******************************************************************************/

#define TILE_SIZE 30

__global__ void kernel(int *A0, int *Anext, int nx, int ny, int nz) {
	#define A0(i, j, k) A0[((k)*ny + (j))*nx + (i)]
	#define Anext(i, j, k) Anext[((k)*ny + (j))*nx + (i)]
	
	int tx = threadIdx.x, ty = threadIdx.y;
	int dx = blockDim.x, dy = blockDim.y;
	int i = tx + dx * blockIdx.x;  
	int j = ty + dy * blockIdx.y;  

	if ((i < nx) && (j < ny)){//check we are within bounds
		//Load this thread's top, bottom, and center z values
		int bottom = A0(i,j,0);
		int center = A0(i,j,1);
		int top = A0(i,j,2);

		//create shared memory tile
		__shared__ int ds_A[TILE_SIZE][TILE_SIZE];

		//loop through all z slices
		for (int k=1; k<nz-1; ++k){
			//load up current z-axis slice
			ds_A[ty][tx] = center; 
			__syncthreads(); //wait for all other threads to do their thing

			Anext(i,j,k) = bottom + top +
				((tx > 0)?    ds_A[ty][tx-1]: (i==0)?    0: A0(i-1,j,k)) +
				((tx < dx-1)? ds_A[ty][tx+1]: (i==nx-1)? 0: A0(i+1,j,k)) +
				((ty > 0)?    ds_A[ty-1][tx]: 	(j==0)? 0:			A0(i,j-1,k)) +
				((ty < dy-1)? ds_A[ty+1][tx]: (j==ny-1)? 0: A0(i,j+1,k)) -
				6 * center;

			//shift z-values
			bottom = center; center = top;
			__syncthreads();
			//load new top value
			top = A0(i,j,k+2);
		}
	}
	#undef A0
	#undef Anext
}

void launchStencil(int* A0, int* Anext, int nx, int ny, int nz) {
	//set-up space as TILE_SIZE=30 so each block is 30x30 threads
	//we need nx/30 x ny/30 blocks in each grid
    dim3 dimGrid(ceil(nx/double(TILE_SIZE)),ceil(ny/double(TILE_SIZE)),1);
	dim3 dimBlock(TILE_SIZE,TILE_SIZE,1);
	
	kernel<<<dimGrid, dimBlock>>>(A0,Anext,nx,ny,nz);
}


	.file	"tmpxft_00258207_00000000-6_kernel.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2011:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2011:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z30__device_stub__Z6kernelPiS_iiiPiS_iii
	.type	_Z30__device_stub__Z6kernelPiS_iiiPiS_iii, @function
_Z30__device_stub__Z6kernelPiS_iiiPiS_iii:
.LFB2033:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	32(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	40(%rsp), %rcx
	movl	%r8d, 4(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	40(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z6kernelPiS_iii(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 176
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L2:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2033:
	.size	_Z30__device_stub__Z6kernelPiS_iiiPiS_iii, .-_Z30__device_stub__Z6kernelPiS_iiiPiS_iii
	.globl	_Z6kernelPiS_iii
	.type	_Z6kernelPiS_iii, @function
_Z6kernelPiS_iii:
.LFB2034:
	.cfi_startproc
	endbr64
	jmp	_Z30__device_stub__Z6kernelPiS_iiiPiS_iii
	.cfi_endproc
.LFE2034:
	.size	_Z6kernelPiS_iii, .-_Z6kernelPiS_iii
	.globl	_Z13launchStencilPiS_iii
	.type	_Z13launchStencilPiS_iii, @function
_Z13launchStencilPiS_iii:
.LFB2008:
	.cfi_startproc
	endbr64
	pushq	%r14
	.cfi_def_cfa_offset 16
	.cfi_offset 14, -16
	cvtsi2sdl	%ecx, %xmm0
	movl	%r8d, %r14d
	pushq	%r13
	.cfi_def_cfa_offset 24
	.cfi_offset 13, -24
	movq	%rsi, %r13
	pushq	%r12
	.cfi_def_cfa_offset 32
	.cfi_offset 12, -32
	movq	%rdi, %r12
	pushq	%rbp
	.cfi_def_cfa_offset 40
	.cfi_offset 6, -40
	movl	%ecx, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 48
	.cfi_offset 3, -48
	movl	%edx, %ebx
	subq	$48, %rsp
	.cfi_def_cfa_offset 96
	divsd	.LC0(%rip), %xmm0
	call	ceil@PLT
	movsd	%xmm0, 8(%rsp)
	cvtsi2sdl	%ebx, %xmm0
	divsd	.LC0(%rip), %xmm0
	call	ceil@PLT
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$1, %ecx
	cvttsd2siq	%xmm0, %rax
	movsd	8(%rsp), %xmm1
	movl	$1, %esi
	movabsq	$128849018910, %rdx
	movl	%eax, 24(%rsp)
	cvttsd2siq	%xmm1, %rax
	movl	%eax, 28(%rsp)
	movq	24(%rsp), %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L8
	addq	$48, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 48
	movl	%r14d, %r8d
	movl	%ebp, %ecx
	movl	%ebx, %edx
	movq	%r13, %rsi
	popq	%rbx
	.cfi_def_cfa_offset 40
	movq	%r12, %rdi
	popq	%rbp
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r13
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	jmp	_Z30__device_stub__Z6kernelPiS_iiiPiS_iii
.L8:
	.cfi_restore_state
	addq	$48, %rsp
	.cfi_def_cfa_offset 48
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%rbp
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r13
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2008:
	.size	_Z13launchStencilPiS_iii, .-_Z13launchStencilPiS_iii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC1:
	.string	"_Z6kernelPiS_iii"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2036:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC1(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z6kernelPiS_iii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2036:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst8,"aM",@progbits,8
	.align 8
.LC0:
	.long	0
	.long	1077805056
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
/******************************************************************************
 *cr
 *cr         (C) Copyright 2010-2013 The Board of Trustees of the
 *cr                        University of Illinois
 *cr                         All Rights Reserved
 *cr
 ******************************************************************************/

#define TILE_SIZE 30

__global__ void kernel(int *A0, int *Anext, int nx, int ny, int nz) {
	#define A0(i, j, k) A0[((k)*ny + (j))*nx + (i)]
	#define Anext(i, j, k) Anext[((k)*ny + (j))*nx + (i)]
	
	int tx = threadIdx.x, ty = threadIdx.y;
	int dx = blockDim.x, dy = blockDim.y;
	int i = tx + dx * blockIdx.x;  
	int j = ty + dy * blockIdx.y;  

	if ((i < nx) && (j < ny)){//check we are within bounds
		//Load this thread's top, bottom, and center z values
		int bottom = A0(i,j,0);
		int center = A0(i,j,1);
		int top = A0(i,j,2);

		//create shared memory tile
		__shared__ int ds_A[TILE_SIZE][TILE_SIZE];

		//loop through all z slices
		for (int k=1; k<nz-1; ++k){
			//load up current z-axis slice
			ds_A[ty][tx] = center; 
			__syncthreads(); //wait for all other threads to do their thing

			Anext(i,j,k) = bottom + top +
				((tx > 0)?    ds_A[ty][tx-1]: (i==0)?    0: A0(i-1,j,k)) +
				((tx < dx-1)? ds_A[ty][tx+1]: (i==nx-1)? 0: A0(i+1,j,k)) +
				((ty > 0)?    ds_A[ty-1][tx]: 	(j==0)? 0:			A0(i,j-1,k)) +
				((ty < dy-1)? ds_A[ty+1][tx]: (j==ny-1)? 0: A0(i,j+1,k)) -
				6 * center;

			//shift z-values
			bottom = center; center = top;
			__syncthreads();
			//load new top value
			top = A0(i,j,k+2);
		}
	}
	#undef A0
	#undef Anext
}

void launchStencil(int* A0, int* Anext, int nx, int ny, int nz) {
	//set-up space as TILE_SIZE=30 so each block is 30x30 threads
	//we need nx/30 x ny/30 blocks in each grid
    dim3 dimGrid(ceil(nx/double(TILE_SIZE)),ceil(ny/double(TILE_SIZE)),1);
	dim3 dimBlock(TILE_SIZE,TILE_SIZE,1);
	
	kernel<<<dimGrid, dimBlock>>>(A0,Anext,nx,ny,nz);
}


	.text
	.file	"kernel.hip"
	.globl	_Z21__device_stub__kernelPiS_iii # -- Begin function _Z21__device_stub__kernelPiS_iii
	.type	_Z21__device_stub__kernelPiS_iii,@function
_Z21__device_stub__kernelPiS_iii:       # @_Z21__device_stub__kernelPiS_iii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	4(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z6kernelPiS_iii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z21__device_stub__kernelPiS_iii, .Lfunc_end0-_Z21__device_stub__kernelPiS_iii
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0                          # -- Begin function _Z13launchStencilPiS_iii
.LCPI1_0:
	.quad	0x403e000000000000              # double 30
	.text
	.globl	_Z13launchStencilPiS_iii
	.type	_Z13launchStencilPiS_iii,@function
_Z13launchStencilPiS_iii:               # @_Z13launchStencilPiS_iii
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	pushq	%rax
	.cfi_def_cfa_offset 64
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%r8d, %ebx
	movl	%ecx, %ebp
	movl	%edx, %r14d
	movq	%rsi, %r15
	movq	%rdi, %r12
	cvtsi2sd	%edx, %xmm0
	divsd	.LCPI1_0(%rip), %xmm0
	callq	ceil@PLT
	cvttsd2si	%xmm0, %r13
	xorps	%xmm0, %xmm0
	cvtsi2sd	%ebp, %xmm0
	divsd	.LCPI1_0(%rip), %xmm0
	callq	ceil@PLT
	cvttsd2si	%xmm0, %rdi
	movl	%r13d, %eax
	shlq	$32, %rdi
	orq	%rax, %rdi
	movabsq	$128849018910, %rdx             # imm = 0x1E0000001E
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	je	.LBB1_2
# %bb.1:
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB1_2:
	.cfi_def_cfa_offset 64
	movq	%r12, %rdi
	movq	%r15, %rsi
	movl	%r14d, %edx
	movl	%ebp, %ecx
	movl	%ebx, %r8d
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z21__device_stub__kernelPiS_iii # TAILCALL
.Lfunc_end1:
	.size	_Z13launchStencilPiS_iii, .Lfunc_end1-_Z13launchStencilPiS_iii
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z6kernelPiS_iii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z6kernelPiS_iii,@object        # @_Z6kernelPiS_iii
	.section	.rodata,"a",@progbits
	.globl	_Z6kernelPiS_iii
	.p2align	3, 0x0
_Z6kernelPiS_iii:
	.quad	_Z21__device_stub__kernelPiS_iii
	.size	_Z6kernelPiS_iii, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z6kernelPiS_iii"
	.size	.L__unnamed_1, 17

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z21__device_stub__kernelPiS_iii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z6kernelPiS_iii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z6kernelPiS_iii        ; -- Begin function _Z6kernelPiS_iii
	.globl	_Z6kernelPiS_iii
	.p2align	8
	.type	_Z6kernelPiS_iii,@function
_Z6kernelPiS_iii:                       ; @_Z6kernelPiS_iii
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x2c
	s_load_b128 s[16:19], s[0:1], 0x10
	v_and_b32_e32 v2, 0x3ff, v0
	v_bfe_u32 v1, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_and_b32 s3, s2, 0xffff
	s_lshr_b32 s5, s2, 16
	s_mul_i32 s7, s14, s3
	s_mul_i32 s15, s15, s5
	v_add_nc_u32_e32 v0, s7, v2
	v_add_nc_u32_e32 v3, s15, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_i32_e32 vcc_lo, s16, v0
	v_cmp_gt_i32_e64 s2, s17, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, vcc_lo, s2
	s_cmp_gt_i32 s18, 2
	s_cselect_b32 s4, -1, 0
	s_and_b32 s2, s2, s4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s4, s2
	s_cbranch_execz .LBB0_27
; %bb.1:                                ; %.lr.ph
	v_add_nc_u32_e32 v6, s17, v3
	s_load_b128 s[8:11], s[0:1], 0x0
	s_add_i32 s3, s3, -1
	s_add_i32 s5, s5, -1
	v_cmp_le_i32_e64 s1, s3, v2
	v_mad_u64_u32 v[4:5], null, v6, s16, v[0:1]
	v_mad_u64_u32 v[6:7], null, v3, s16, v[0:1]
	v_cmp_ne_u32_e64 s3, 0, v1
	v_cmp_le_i32_e64 s5, s5, v1
	s_add_i32 s2, s16, -1
	s_add_i32 s6, s17, -1
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_ashrrev_i32_e32 v5, 31, v4
	s_add_i32 s12, s18, -2
	v_ashrrev_i32_e32 v7, 31, v6
	v_cmp_ne_u32_e64 s0, 0, v0
	v_cmp_ne_u32_e64 s2, s2, v0
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	v_cmp_ne_u32_e64 s4, 0, v3
	v_lshlrev_b64 v[6:7], 2, v[6:7]
	v_cmp_ne_u32_e64 s6, s6, v3
	v_ashrrev_i32_e32 v13, 31, v0
	s_waitcnt lgkmcnt(0)
	s_add_u32 s13, s8, -4
	v_add_co_u32 v4, vcc_lo, s8, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s9, v5, vcc_lo
	v_add_co_u32 v8, vcc_lo, s8, v6
	v_add_co_ci_u32_e32 v9, vcc_lo, s9, v7, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, 0, v2
	s_clause 0x1
	global_load_b32 v7, v[4:5], off
	global_load_b32 v10, v[8:9], off
	v_lshlrev_b32_e32 v4, 2, v2
	v_lshl_add_u32 v5, s17, 1, v3
	s_addc_u32 s14, s9, -1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mad_u32_u24 v8, 0x78, v1, v4
	v_add3_u32 v4, s15, s17, v1
	v_mul_lo_u32 v1, s16, v5
	s_add_u32 s15, s8, 4
	s_addc_u32 s18, s9, 0
	v_add_nc_u32_e32 v9, -4, v8
	v_add_nc_u32_e32 v6, -1, v4
	v_mul_lo_u32 v12, s16, v4
	v_add_nc_u32_e32 v11, 0xffffff88, v8
	v_add3_u32 v1, v2, v1, s7
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mul_lo_u32 v4, s16, v6
	v_add_nc_u32_e32 v5, s16, v12
	s_mul_i32 s16, s17, s16
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add3_u32 v3, v2, v4, s7
	v_add3_u32 v5, v2, v5, s7
.LBB0_2:                                ; =>This Inner Loop Header: Depth=1
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[14:15], 2, v[1:2]
	s_waitcnt vmcnt(1)
	v_mov_b32_e32 v2, v7
	ds_store_b32 v8, v2
	v_add_co_u32 v14, s7, s8, v14
	v_add_co_ci_u32_e64 v15, s7, s9, v15, s7
	global_load_b32 v7, v[14:15], off
	s_waitcnt vmcnt(0) lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
                                        ; implicit-def: $vgpr14
	s_and_saveexec_b32 s7, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s7, exec_lo, s7
	s_cbranch_execz .LBB0_4
; %bb.3:                                ;   in Loop: Header=BB0_2 Depth=1
	ds_load_b32 v14, v9
.LBB0_4:                                ; %Flow150
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_and_not1_saveexec_b32 s17, s7
	s_cbranch_execz .LBB0_8
; %bb.5:                                ;   in Loop: Header=BB0_2 Depth=1
	s_waitcnt lgkmcnt(0)
	v_mov_b32_e32 v14, 0
	s_and_saveexec_b32 s19, s0
	s_cbranch_execz .LBB0_7
; %bb.6:                                ;   in Loop: Header=BB0_2 Depth=1
	v_ashrrev_i32_e32 v4, 31, v12
	v_add_co_u32 v14, s7, v0, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e64 v15, s7, v13, v4, s7
	v_lshlrev_b64 v[14:15], 2, v[14:15]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v14, s7, s13, v14
	v_add_co_ci_u32_e64 v15, s7, s14, v15, s7
	global_load_b32 v14, v[14:15], off
.LBB0_7:                                ; %Flow149
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s19
.LBB0_8:                                ;   in Loop: Header=BB0_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s17
                                        ; implicit-def: $vgpr15
	s_and_saveexec_b32 s7, s1
	s_xor_b32 s17, exec_lo, s7
	s_cbranch_execz .LBB0_12
; %bb.9:                                ;   in Loop: Header=BB0_2 Depth=1
	v_mov_b32_e32 v15, 0
	s_and_saveexec_b32 s19, s2
	s_cbranch_execz .LBB0_11
; %bb.10:                               ;   in Loop: Header=BB0_2 Depth=1
	v_ashrrev_i32_e32 v4, 31, v12
	v_add_co_u32 v15, s7, v0, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e64 v16, s7, v13, v4, s7
	v_lshlrev_b64 v[15:16], 2, v[15:16]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v15, s7, s15, v15
	v_add_co_ci_u32_e64 v16, s7, s18, v16, s7
	global_load_b32 v15, v[15:16], off
.LBB0_11:                               ; %Flow147
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s19
.LBB0_12:                               ; %Flow148
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_and_not1_saveexec_b32 s7, s17
	s_cbranch_execz .LBB0_14
; %bb.13:                               ;   in Loop: Header=BB0_2 Depth=1
	s_waitcnt vmcnt(0)
	ds_load_b32 v15, v8 offset:4
.LBB0_14:                               ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s7
                                        ; implicit-def: $vgpr4
	s_and_saveexec_b32 s7, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s7, exec_lo, s7
	s_cbranch_execz .LBB0_16
; %bb.15:                               ;   in Loop: Header=BB0_2 Depth=1
	ds_load_b32 v4, v11
.LBB0_16:                               ; %Flow146
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_and_not1_saveexec_b32 s17, s7
	s_cbranch_execz .LBB0_20
; %bb.17:                               ;   in Loop: Header=BB0_2 Depth=1
	s_waitcnt lgkmcnt(0)
	v_mov_b32_e32 v4, 0
	s_and_saveexec_b32 s19, s4
	s_cbranch_execz .LBB0_19
; %bb.18:                               ;   in Loop: Header=BB0_2 Depth=1
	v_ashrrev_i32_e32 v4, 31, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[16:17], 2, v[3:4]
	v_add_co_u32 v16, s7, s8, v16
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v17, s7, s9, v17, s7
	global_load_b32 v4, v[16:17], off
.LBB0_19:                               ; %Flow145
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s19
.LBB0_20:                               ;   in Loop: Header=BB0_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s17
                                        ; implicit-def: $vgpr6
	s_and_saveexec_b32 s7, s5
	s_xor_b32 s17, exec_lo, s7
	s_cbranch_execz .LBB0_24
; %bb.21:                               ;   in Loop: Header=BB0_2 Depth=1
	v_mov_b32_e32 v6, 0
	s_and_saveexec_b32 s19, s6
	s_cbranch_execz .LBB0_23
; %bb.22:                               ;   in Loop: Header=BB0_2 Depth=1
	v_ashrrev_i32_e32 v6, 31, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[16:17], 2, v[5:6]
	v_add_co_u32 v16, s7, s8, v16
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v17, s7, s9, v17, s7
	global_load_b32 v6, v[16:17], off
.LBB0_23:                               ; %Flow
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s19
.LBB0_24:                               ; %Flow144
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_and_not1_saveexec_b32 s7, s17
	s_cbranch_execz .LBB0_26
; %bb.25:                               ;   in Loop: Header=BB0_2 Depth=1
	s_waitcnt vmcnt(0)
	ds_load_b32 v6, v8 offset:120
.LBB0_26:                               ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s7
	v_add_nc_u32_e32 v16, v0, v12
	v_mul_lo_u32 v18, v2, -6
	v_add_nc_u32_e32 v1, s16, v1
	v_add_nc_u32_e32 v12, s16, v12
	v_add_nc_u32_e32 v3, s16, v3
	v_ashrrev_i32_e32 v17, 31, v16
	v_add_nc_u32_e32 v5, s16, v5
	s_add_i32 s12, s12, -1
	v_add3_u32 v10, v18, v10, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[16:17], 2, v[16:17]
	s_cmp_lg_u32 s12, 0
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add3_u32 v10, v10, v14, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v14, s7, s10, v16
	v_add_co_ci_u32_e64 v15, s7, s11, v17, s7
	s_delay_alu instid0(VALU_DEP_3)
	v_add3_u32 v4, v10, v4, v6
	v_mov_b32_e32 v10, v2
	global_store_b32 v[14:15], v4, off
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB0_2
.LBB0_27:                               ; %.loopexit
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z6kernelPiS_iii
		.amdhsa_group_segment_fixed_size 3600
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 19
		.amdhsa_next_free_sgpr 20
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z6kernelPiS_iii, .Lfunc_end0-_Z6kernelPiS_iii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1080
; NumSgprs: 22
; NumVgprs: 19
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 3600 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 22
; NumVGPRsForWavesPerEU: 19
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 3600
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z6kernelPiS_iii
    .private_segment_fixed_size: 0
    .sgpr_count:     22
    .sgpr_spill_count: 0
    .symbol:         _Z6kernelPiS_iii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     19
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
