#include "includes.h"
__global__ void histogram_kernel(float* magnitude, float* phase, float* histograms, int input_width, int input_height, int cell_grid_width, int cell_grid_height, int magnitude_step, int phase_step, int histograms_step, int cell_width, int cell_height, int num_bins)
{
//TODO: make the buffer sizes dependent on an input or template parameter.
// Each thread block needs to store intermediate results for 64 gradients
// and also 8 different histograms, each with 9 bins.
__shared__ int s_lbin_pos[64];
__shared__ float s_lbin[64];
__shared__ int s_rbin_pos[64];
__shared__ float s_rbin[64];
__shared__ float s_hist[9 * 8];

// The columns of the image are mapped to the first dimension of the block
// grid and the first dimension of the thread block.
int pixel_x = blockIdx.x * blockDim.x + threadIdx.x;
// If current position is outside the image, stop here
if(pixel_x >= input_width)
{
return;
}
// The columns of the image are mapped to the second dimension of the block
// grid and the second dimension of the thread block.
int pixel_y = blockIdx.y * blockDim.y + threadIdx.y;
// If current position is outside the image, stop here
if(pixel_y >= input_height)
{
return;
}

// Each row has magnitude_step size
int mag_pixel_idx = pixel_y * magnitude_step + pixel_x;
// Each row has phase_step size
int phase_pixel_idx = pixel_y * phase_step + pixel_x;

// The phase was previously normalized to [0,1]
float bin_size = 1.0f / (float)num_bins;
// By dividing by the bin size and taking the integer part, you find out
// inside which bin the gradient is at. If it's greater than the middle of the bin
// it will be divided between this one and the next, if it's lesser it will
// be divided between this and the previous one. By subtracting 0.5 before
// taking the integer part, the division will always be between this bin and
// the next.
int left_bin = (int)floor((phase[phase_pixel_idx] / bin_size) - 0.5f);
// The result of the previous operation might be negative. If so, the next
// bit fixes that. Otherwise that changes nothing.
left_bin = (left_bin + num_bins) % num_bins;
// Take the next bin as the right bin.
// If the left bin is the last one, this will be outside range. Wait a bit
// before taking the remainder, because this value needs to be used in the
// formula below.
int right_bin = (left_bin + 1);
// Calculate the distance between the gradient phase and the limit between
// the left and right bins. Normalized by the bin size, the limit is equal
// to the right bin identifier.
float delta = (phase[phase_pixel_idx] / bin_size) - right_bin;
if(delta < -0.5)
{
delta += num_bins;
}
//Fix range for right_bin now
right_bin = right_bin % num_bins;

// Store the bin positions and amounts for each bin on shared buffers.
s_lbin_pos[threadIdx.x] = left_bin;
s_lbin[threadIdx.x] = (0.5 - delta) * magnitude[mag_pixel_idx];
s_rbin_pos[threadIdx.x] = right_bin;
s_rbin[threadIdx.x] = (0.5 + delta) * magnitude[mag_pixel_idx];

// Wait for other threads.
__syncthreads();

// Initialize histograms shared buffer.
s_hist[threadIdx.x] = 0.0f;
if(threadIdx.x < 8)
{
s_hist[threadIdx.x + 64] = 0.0f;
}

int cell_y = pixel_y / cell_height;

// Each partial histogram will be calculated by only one thread.
if(threadIdx.x < 8)
{
int s_hist_idx = 9 * threadIdx.x;
for(int i = 1; i < 8; ++i)
{
s_hist[s_hist_idx + s_lbin_pos[8 * threadIdx.x + i]] += s_lbin[8
* threadIdx.x + i];
s_hist[s_hist_idx + s_rbin_pos[8 * threadIdx.x + i]] += s_rbin[8
* threadIdx.x + i];
}
}

// Wait until all threads finish.
__syncthreads();

// Add to the complete histogram sum using atomic operations.
int out_idx = cell_y * histograms_step + threadIdx.x;
atomicAdd(&(histograms[out_idx]), s_hist[threadIdx.x]);

if(threadIdx.x < 8)
{
atomicAdd(&(histograms[out_idx + 64]), s_hist[threadIdx.x + 64]);
}
}
	.file	"tmpxft_00317582_00000000-6_histogram_kernel.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2010:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2010:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z50__device_stub__Z16histogram_kernelPfS_S_iiiiiiiiiiPfS_S_iiiiiiiiii
	.type	_Z50__device_stub__Z16histogram_kernelPfS_S_iiiiiiiiiiPfS_S_iiiiiiiiii, @function
_Z50__device_stub__Z16histogram_kernelPfS_S_iiiiiiiiiiPfS_S_iiiiiiiiii:
.LFB2032:
	.cfi_startproc
	endbr64
	subq	$232, %rsp
	.cfi_def_cfa_offset 240
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	48(%rsp), %rdx
	movl	%ecx, 20(%rsp)
	leaq	56(%rsp), %rcx
	movl	%r8d, 16(%rsp)
	movl	%r9d, 12(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 216(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 112(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	240(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	248(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	256(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	264(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	272(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	280(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	288(%rsp), %rax
	movq	%rax, 208(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	56(%rsp)
	.cfi_def_cfa_offset 248
	leaq	_Z16histogram_kernelPfS_S_iiiiiiiiii(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 256
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 248
	popq	%rdx
	.cfi_def_cfa_offset 240
.L2:
	movq	216(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$232, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2032:
	.size	_Z50__device_stub__Z16histogram_kernelPfS_S_iiiiiiiiiiPfS_S_iiiiiiiiii, .-_Z50__device_stub__Z16histogram_kernelPfS_S_iiiiiiiiiiPfS_S_iiiiiiiiii
	.globl	_Z16histogram_kernelPfS_S_iiiiiiiiii
	.type	_Z16histogram_kernelPfS_S_iiiiiiiiii, @function
_Z16histogram_kernelPfS_S_iiiiiiiiii:
.LFB2033:
	.cfi_startproc
	endbr64
	jmp	_Z50__device_stub__Z16histogram_kernelPfS_S_iiiiiiiiiiPfS_S_iiiiiiiiii
	.cfi_endproc
.LFE2033:
	.size	_Z16histogram_kernelPfS_S_iiiiiiiiii, .-_Z16histogram_kernelPfS_S_iiiiiiiiii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z16histogram_kernelPfS_S_iiiiiiiiii"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2035:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z16histogram_kernelPfS_S_iiiiiiiiii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2035:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void histogram_kernel(float* magnitude, float* phase, float* histograms, int input_width, int input_height, int cell_grid_width, int cell_grid_height, int magnitude_step, int phase_step, int histograms_step, int cell_width, int cell_height, int num_bins)
{
//TODO: make the buffer sizes dependent on an input or template parameter.
// Each thread block needs to store intermediate results for 64 gradients
// and also 8 different histograms, each with 9 bins.
__shared__ int s_lbin_pos[64];
__shared__ float s_lbin[64];
__shared__ int s_rbin_pos[64];
__shared__ float s_rbin[64];
__shared__ float s_hist[9 * 8];

// The columns of the image are mapped to the first dimension of the block
// grid and the first dimension of the thread block.
int pixel_x = blockIdx.x * blockDim.x + threadIdx.x;
// If current position is outside the image, stop here
if(pixel_x >= input_width)
{
return;
}
// The columns of the image are mapped to the second dimension of the block
// grid and the second dimension of the thread block.
int pixel_y = blockIdx.y * blockDim.y + threadIdx.y;
// If current position is outside the image, stop here
if(pixel_y >= input_height)
{
return;
}

// Each row has magnitude_step size
int mag_pixel_idx = pixel_y * magnitude_step + pixel_x;
// Each row has phase_step size
int phase_pixel_idx = pixel_y * phase_step + pixel_x;

// The phase was previously normalized to [0,1]
float bin_size = 1.0f / (float)num_bins;
// By dividing by the bin size and taking the integer part, you find out
// inside which bin the gradient is at. If it's greater than the middle of the bin
// it will be divided between this one and the next, if it's lesser it will
// be divided between this and the previous one. By subtracting 0.5 before
// taking the integer part, the division will always be between this bin and
// the next.
int left_bin = (int)floor((phase[phase_pixel_idx] / bin_size) - 0.5f);
// The result of the previous operation might be negative. If so, the next
// bit fixes that. Otherwise that changes nothing.
left_bin = (left_bin + num_bins) % num_bins;
// Take the next bin as the right bin.
// If the left bin is the last one, this will be outside range. Wait a bit
// before taking the remainder, because this value needs to be used in the
// formula below.
int right_bin = (left_bin + 1);
// Calculate the distance between the gradient phase and the limit between
// the left and right bins. Normalized by the bin size, the limit is equal
// to the right bin identifier.
float delta = (phase[phase_pixel_idx] / bin_size) - right_bin;
if(delta < -0.5)
{
delta += num_bins;
}
//Fix range for right_bin now
right_bin = right_bin % num_bins;

// Store the bin positions and amounts for each bin on shared buffers.
s_lbin_pos[threadIdx.x] = left_bin;
s_lbin[threadIdx.x] = (0.5 - delta) * magnitude[mag_pixel_idx];
s_rbin_pos[threadIdx.x] = right_bin;
s_rbin[threadIdx.x] = (0.5 + delta) * magnitude[mag_pixel_idx];

// Wait for other threads.
__syncthreads();

// Initialize histograms shared buffer.
s_hist[threadIdx.x] = 0.0f;
if(threadIdx.x < 8)
{
s_hist[threadIdx.x + 64] = 0.0f;
}

int cell_y = pixel_y / cell_height;

// Each partial histogram will be calculated by only one thread.
if(threadIdx.x < 8)
{
int s_hist_idx = 9 * threadIdx.x;
for(int i = 1; i < 8; ++i)
{
s_hist[s_hist_idx + s_lbin_pos[8 * threadIdx.x + i]] += s_lbin[8
* threadIdx.x + i];
s_hist[s_hist_idx + s_rbin_pos[8 * threadIdx.x + i]] += s_rbin[8
* threadIdx.x + i];
}
}

// Wait until all threads finish.
__syncthreads();

// Add to the complete histogram sum using atomic operations.
int out_idx = cell_y * histograms_step + threadIdx.x;
atomicAdd(&(histograms[out_idx]), s_hist[threadIdx.x]);

if(threadIdx.x < 8)
{
atomicAdd(&(histograms[out_idx + 64]), s_hist[threadIdx.x + 64]);
}
}
	.text
	.file	"histogram_kernel.hip"
	.globl	_Z31__device_stub__histogram_kernelPfS_S_iiiiiiiiii # -- Begin function _Z31__device_stub__histogram_kernelPfS_S_iiiiiiiiii
	.type	_Z31__device_stub__histogram_kernelPfS_S_iiiiiiiiii,@function
_Z31__device_stub__histogram_kernelPfS_S_iiiiiiiiii: # @_Z31__device_stub__histogram_kernelPfS_S_iiiiiiiiii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$208, %rsp
	.cfi_def_cfa_offset 256
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	20(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	16(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	12(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	256(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	264(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	272(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	280(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	288(%rsp), %rax
	movq	%rax, 80(%rbx)
	leaq	296(%rsp), %rax
	movq	%rax, 88(%rbx)
	leaq	304(%rsp), %rax
	movq	%rax, 96(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z16histogram_kernelPfS_S_iiiiiiiiii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$224, %rsp
	.cfi_adjust_cfa_offset -224
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z31__device_stub__histogram_kernelPfS_S_iiiiiiiiii, .Lfunc_end0-_Z31__device_stub__histogram_kernelPfS_S_iiiiiiiiii
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z16histogram_kernelPfS_S_iiiiiiiiii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z16histogram_kernelPfS_S_iiiiiiiiii,@object # @_Z16histogram_kernelPfS_S_iiiiiiiiii
	.section	.rodata,"a",@progbits
	.globl	_Z16histogram_kernelPfS_S_iiiiiiiiii
	.p2align	3, 0x0
_Z16histogram_kernelPfS_S_iiiiiiiiii:
	.quad	_Z31__device_stub__histogram_kernelPfS_S_iiiiiiiiii
	.size	_Z16histogram_kernelPfS_S_iiiiiiiiii, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z16histogram_kernelPfS_S_iiiiiiiiii"
	.size	.L__unnamed_1, 37

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z31__device_stub__histogram_kernelPfS_S_iiiiiiiiii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z16histogram_kernelPfS_S_iiiiiiiiii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z16histogram_kernelPfS_S_iiiiiiiiii ; -- Begin function _Z16histogram_kernelPfS_S_iiiiiiiiii
	.globl	_Z16histogram_kernelPfS_S_iiiiiiiiii
	.p2align	8
	.type	_Z16histogram_kernelPfS_S_iiiiiiiiii,@function
_Z16histogram_kernelPfS_S_iiiiiiiiii:   ; @_Z16histogram_kernelPfS_S_iiiiiiiiii
; %bb.0:
	s_clause 0x1
	s_load_b32 s6, s[0:1], 0x4c
	s_load_b64 s[2:3], s[0:1], 0x18
	v_and_b32_e32 v1, 0x3ff, v0
	s_add_u32 s4, s0, 64
	s_addc_u32 s5, s1, 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s6, s6, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[4:5], null, s14, s6, v[1:2]
	v_cmp_gt_i32_e32 vcc_lo, s2, v4
	s_and_saveexec_b32 s2, vcc_lo
	s_cbranch_execz .LBB0_12
; %bb.1:
	s_load_b32 s2, s[4:5], 0xc
	v_bfe_u32 v0, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s2, s2, 16
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[2:3], null, s15, s2, v[0:1]
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_i32_e32 vcc_lo, s3, v2
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_12
; %bb.2:
	s_clause 0x3
	s_load_b128 s[4:7], s[0:1], 0x28
	s_load_b64 s[12:13], s[0:1], 0x38
	s_load_b128 s[8:11], s[0:1], 0x0
	s_load_b64 s[2:3], s[0:1], 0x10
	s_waitcnt lgkmcnt(0)
	v_mad_u64_u32 v[5:6], null, v2, s5, v[4:5]
	s_ashr_i32 s0, s13, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s1, s13, s0
	s_xor_b32 s0, s1, s0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_sub_i32 s1, 0, s0
	v_ashrrev_i32_e32 v6, 31, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[5:6], 2, v[5:6]
	v_add_co_u32 v5, vcc_lo, s10, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v6, vcc_lo, s11, v6, vcc_lo
	global_load_b32 v0, v[5:6], off
	v_mad_u64_u32 v[5:6], null, v2, s4, v[4:5]
	v_ashrrev_i32_e32 v6, 31, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[5:6]
	v_add_co_u32 v3, vcc_lo, s8, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v4, vcc_lo, s9, v4, vcc_lo
	global_load_b32 v5, v[3:4], off
	v_cvt_f32_i32_e32 v3, s13
	v_div_scale_f32 v4, null, v3, v3, 1.0
	v_div_scale_f32 v8, vcc_lo, 1.0, v3, 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v6, v4
	s_waitcnt_depctr 0xfff
	v_fma_f32 v7, -v4, v6, 1.0
	v_fmac_f32_e32 v6, v7, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v7, v8, v6
	v_fma_f32 v9, -v4, v7, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v7, v9, v6
	v_fma_f32 v4, -v4, v7, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v4, v4, v6, v7
	v_div_fixup_f32 v4, v4, v3, 1.0
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f32 v6, null, v4, v4, v0
	v_div_scale_f32 v9, vcc_lo, v0, v4, v0
	v_rcp_f32_e32 v7, v6
	s_waitcnt_depctr 0xfff
	v_fma_f32 v8, -v6, v7, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v7, v8, v7
	v_mul_f32_e32 v8, v9, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v10, -v6, v8, v9
	v_fmac_f32_e32 v8, v10, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v6, -v6, v8, v9
	v_cvt_f32_u32_e32 v9, s0
	v_div_fmas_f32 v6, v6, v7, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v7, v9
	v_div_fixup_f32 v0, v6, v4, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_add_f32_e32 v4, -0.5, v0
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v6, 0x4f7ffffe, v7
	v_floor_f32_e32 v4, v4
	v_cvt_u32_f32_e32 v6, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_i32_f32_e32 v4, v4
	v_mul_lo_u32 v7, s1, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v4, s13, v4
	v_mul_hi_u32 v7, v6, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v8, 31, v4
	v_add_nc_u32_e32 v4, v4, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v9, v6, v7
	v_xor_b32_e32 v4, v4, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v6, v4, v9
	v_mul_lo_u32 v6, v6, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v4, v4, v6
	v_subrev_nc_u32_e32 v6, s0, v4
	v_cmp_le_u32_e32 vcc_lo, s0, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v4, v4, v6, vcc_lo
	v_subrev_nc_u32_e32 v6, s0, v4
	v_cmp_le_u32_e32 vcc_lo, s0, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v4, v4, v6, vcc_lo
	s_waitcnt vmcnt(0)
	v_cvt_f64_f32_e32 v[5:6], v5
	v_xor_b32_e32 v4, v4, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v10, v4, v8
	v_add_nc_u32_e32 v11, 1, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f32_i32_e32 v4, v11
	v_sub_f32_e32 v0, v0, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_gt_f32_e32 vcc_lo, -0.5, v0
	v_cndmask_b32_e32 v3, 0x80000000, v3, vcc_lo
	v_add_f32_e32 v0, v0, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cvt_f64_f32_e32 v[3:4], v0
	v_ashrrev_i32_e32 v0, 31, v11
	v_add_f64 v[7:8], -v[3:4], 0.5
	v_add_f64 v[3:4], v[3:4], 0.5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[7:8], v[7:8], v[5:6]
	v_mul_f64 v[3:4], v[3:4], v[5:6]
	v_add_nc_u32_e32 v5, v11, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v5, v5, v0
	v_mul_hi_u32 v6, v5, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_mul_lo_u32 v6, v6, s0
	v_cvt_f32_f64_e32 v7, v[7:8]
	v_cvt_f32_f64_e32 v3, v[3:4]
	v_sub_nc_u32_e32 v4, v5, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v5, s0, v4
	v_cmp_le_u32_e32 vcc_lo, s0, v4
	v_cndmask_b32_e32 v4, v4, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v5, s0, v4
	v_cmp_le_u32_e32 vcc_lo, s0, v4
	v_cndmask_b32_e32 v4, v4, v5, vcc_lo
	v_cmp_gt_u32_e32 vcc_lo, 8, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v5, v4, v0
	v_lshlrev_b32_e32 v4, 2, v1
	v_sub_nc_u32_e32 v5, v5, v0
	v_mov_b32_e32 v0, 0
	s_delay_alu instid0(VALU_DEP_3)
	v_add_nc_u32_e32 v6, 32, v4
	ds_store_2addr_b32 v4, v10, v5 offset0:72 offset1:136
	ds_store_2addr_stride64_b32 v6, v7, v3 offset0:3 offset1:4
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_store_b32 v4, v0
	s_and_saveexec_b32 s0, vcc_lo
	s_cbranch_execz .LBB0_4
; %bb.3:
	ds_store_b32 v4, v0 offset:256
.LBB0_4:
	s_or_b32 exec_lo, exec_lo, s0
	s_and_saveexec_b32 s0, vcc_lo
	s_cbranch_execz .LBB0_7
; %bb.5:
	v_mul_u32_u24_e32 v0, 9, v1
	v_lshl_add_u32 v3, v1, 5, 0x124
	s_mov_b32 s1, 0
.LBB0_6:                                ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_add_nc_u32_e32 v7, s1, v3
	s_add_i32 s1, s1, 4
	ds_load_2addr_stride64_b32 v[5:6], v7 offset1:1
	ds_load_2addr_stride64_b32 v[7:8], v7 offset0:2 offset1:3
	s_cmp_lg_u32 s1, 28
	s_waitcnt lgkmcnt(1)
	v_add_lshl_u32 v5, v5, v0, 2
	v_add_lshl_u32 v6, v6, v0, 2
	ds_load_b32 v9, v5
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v7, v7, v9
	ds_store_b32 v5, v7
	ds_load_b32 v5, v6
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v5, v8, v5
	ds_store_b32 v6, v5
	s_cbranch_scc1 .LBB0_6
.LBB0_7:                                ; %Flow101
	s_or_b32 exec_lo, exec_lo, s0
	s_ashr_i32 s1, s12, 31
	v_ashrrev_i32_e32 v5, 31, v2
	s_add_i32 s0, s12, s1
	s_waitcnt lgkmcnt(0)
	s_xor_b32 s4, s0, s1
	s_barrier
	v_cvt_f32_u32_e32 v0, s4
	s_sub_i32 s0, 0, s4
	v_add_nc_u32_e32 v2, v2, v5
	buffer_gl0_inv
	v_rcp_iflag_f32_e32 v0, v0
	v_xor_b32_e32 v2, v2, v5
	v_xor_b32_e32 v5, s1, v5
	s_mov_b32 s1, 0
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v0, 0x4f7ffffe, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v0, v0
	v_mul_lo_u32 v3, s0, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v3, v0, v3
	v_add_nc_u32_e32 v0, v0, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v0, v2, v0
	v_mul_lo_u32 v3, v0, s4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v2, v2, v3
	v_add_nc_u32_e32 v3, 1, v0
	v_subrev_nc_u32_e32 v6, s4, v2
	v_cmp_le_u32_e64 s0, s4, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v0, v0, v3, s0
	v_cndmask_b32_e64 v2, v2, v6, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v3, 1, v0
	v_cmp_le_u32_e64 s0, s4, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v0, v0, v3, s0
	v_xor_b32_e32 v0, v0, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v0, v0, v5
	ds_load_b32 v5, v4
	v_mad_u64_u32 v[2:3], null, v0, s6, v[1:2]
	v_ashrrev_i32_e32 v3, 31, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[2:3]
	v_add_co_u32 v0, s0, s2, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v1, s0, s3, v1, s0
	global_load_b32 v3, v[0:1], off
.LBB0_8:                                ; %atomicrmw.start
                                        ; =>This Inner Loop Header: Depth=1
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f32_e32 v2, v3, v5
	global_atomic_cmpswap_b32 v2, v[0:1], v[2:3], off glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u32_e64 s0, v2, v3
	v_mov_b32_e32 v3, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s1, s0, s1
	s_and_not1_b32 exec_lo, exec_lo, s1
	s_cbranch_execnz .LBB0_8
; %bb.9:                                ; %atomicrmw.end
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_12
; %bb.10:
	global_load_b32 v3, v[0:1], off offset:256
	ds_load_b32 v4, v4 offset:256
	s_mov_b32 s0, 0
.LBB0_11:                               ; %atomicrmw.start60
                                        ; =>This Inner Loop Header: Depth=1
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f32_e32 v2, v3, v4
	global_atomic_cmpswap_b32 v2, v[0:1], v[2:3], off offset:256 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u32_e32 vcc_lo, v2, v3
	v_mov_b32_e32 v3, v2
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB0_11
.LBB0_12:
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z16histogram_kernelPfS_S_iiiiiiiiii
		.amdhsa_group_segment_fixed_size 1312
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 320
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 12
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z16histogram_kernelPfS_S_iiiiiiiiii, .Lfunc_end0-_Z16histogram_kernelPfS_S_iiiiiiiiii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1440
; NumSgprs: 18
; NumVgprs: 12
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 1312 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 12
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         36
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     by_value
      - .offset:         44
        .size:           4
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     by_value
      - .offset:         52
        .size:           4
        .value_kind:     by_value
      - .offset:         56
        .size:           4
        .value_kind:     by_value
      - .offset:         60
        .size:           4
        .value_kind:     by_value
      - .offset:         64
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         68
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         72
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         76
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         78
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         80
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         82
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         84
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         86
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         112
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         120
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         128
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 1312
    .kernarg_segment_align: 8
    .kernarg_segment_size: 320
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z16histogram_kernelPfS_S_iiiiiiiiii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z16histogram_kernelPfS_S_iiiiiiiiii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     12
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
