#include<stdio.h>
#include<stdlib.h>
#include<string.h>
//#include<cublas.h>
//#include<R.h>

#define NTHREADS 512


//computes u = constant * t(X) %*% v
__device__ void cXtv(float con, int rows, int cols, float * X, int ldX, float * v, 
		     float * u){
  int i,k;
  float sum;

  for(k = 0; k < cols; k++){
    sum = 0;
    for(i = 0; i < rows; i++){
      sum += X[i + k*ldX] * v[i];
    }
    u[k] = con*sum;
  }
}

//computes X = X + v %*% u'
__device__ void Xpvut(int rows, int cols, float * X, int ldX, float *v, float *u){
  int i, j;
  
  for(i=0; i<rows; i++)
    for(j=0; j<cols; j++)
      X[i + j*ldX] += v[i] * u[j];
}


//calculates T = V'V where V is upper triangular
__device__ void uVtV(int rows, int cols, float * V, float * T){
  int i, j, k;
  float sum;
  for(i=0; i<cols; i++){
    for(j=0; j<cols; j++){
      sum = 0;
      for(k=0; k<min(i,j); k++)
	sum += V[k + i*rows] * V[k + j*rows];
      T[i + j*cols] = sum;
    }
  }
}


//Rounds "length" up the the next multiple of block length
__device__ int alignBlock(int length, unsigned blockExp){
  int blockSize = 1 << blockExp;
  int out = (length + blockSize - 1) & ( ( (unsigned) - 1) << blockExp);
  return out;
}

__device__ void colswap(float *X, int n, int p, int i, int j){
  float tmp;
  int k;
  float * Xi = X + i*n;
  float * Xj = X + i*j;
  if(i <= p && j <= p){
    for(k = 0; k < n; k++){
      tmp = Xi[k];
      Xi[k] = Xj[k];
      Xj[k] = tmp;
    }
  }
}

__device__ int getMaxIdx(int p, float * ColNorms, int id){
  int maxIdx = 0, i, bit;
  float max = ColNorms[maxIdx], tmp;

  for(i = 1; i < p; i++){
    bit =  ( id & (1 << i) ) >> 1;
    if( bit == 1){
      tmp = ColNorms[i];
      if(tmp > max){
	max = tmp;
	maxIdx = i;
      }
    }
  }

  return maxIdx;
}

__device__ int idx(int id, int p, int i){
  int j, colcount=0, out;

  for(j=0; j<p; j++){

    if(colcount == i)
      out = j;
    
    if( ( id & ( 1 << j ) ) >> j == 1)
      colcount += 1;
  }

  return out;
}

__global__ void getColNorms(int rows, int cols, float * dX, float * ColNorms){

	int colIndex = threadIdx.x + blockIdx.x * blockDim.x;
	float sum = 0.f, term, * col;

	if(colIndex >= cols)
	  return;

	col = dX + colIndex * rows;

	// debug printing
	// printf("printing column %d\n", colIndex);
	// for(int i = 0; i < rows; i++)
	// printf("%f, ", col[i]);
	// puts("");
	// end debug printing

	for(int i = 0; i < rows; i++) {
		term = col[i];
		term *= term;
		sum += term;
	}

	// debug printing
	// printf("norm %f\n", norm);
	// end debug printing

	ColNorms[colIndex] = sqrtf(sum);
}

__global__ void GetQRDecompBlocked(int n, int p, float * X, float * ColNorms, 
				   unsigned int blockSize, int stride, float * scales, 
				   float * Beta, float * qrAux, int * pivot, 
				   float * WtR, int * rank, float * V, float * W,
				   float * T, float * u){
  
  float tol = 0.0001;  //float tolerance
  int blockCount, blockEnd = 0, bc, i, kp;  //kp is # cols processed

  //unsigned int id = threadIDx.x + blockIDx.x * blockDim.x;
  int varcount = 0, maxIdx, pm = 1; 
  //unsigned int * binid;
  float * Xm; //model id's model matrix; will eventually contain R in QR decomp
  //float * pXcol = X; //pointer to column of X
  float * pXmcol; //pointer to column of Xm
  float maxNorm;
  float * pXmBlock; //pointer to block of Xm 
  size_t fbytes = sizeof(float);
  int rk = 0; // Local value of rank;
  int maxRank;  //maximum possible rank of the model matrix
  float minElt; // Lowest acceptable norm under given tolerance.
  int maxCol; //this will be initialized to pm - 1, highest candidate column, not fixed
  int maxRow = n - 1;
  int rowskp = stride; // # unprocessed rows = stride - kp
  int colskp;   // # unprocessed cols = cols - kp
  float *pVcol;             //pointer to column of V
  float *pVdiag;            //pointer to diagonal element of V
  float *pXmdiag;    //pointer to diagonal element of dQRBlock
  int colIdx;
  int a,b;
  int l;


  //if(id > M)
  //  return;

  //binid = (unsigned int *)calloc(p-1, sizeof(unsigned int));

  /*
  //copies the relevant columns of X into Xm
  do{
    int jump = 0;
    unsigned int bit = 0;

    memcpy(pXmcol, pXcol, n*fbytes);  //copy the current column

    //any time we copy any column but the first, set binid[col] = 1
    if(varcount > 0){ 
      binid[p - varcount] = 1; //actual index is (p - 1) - (varcount - 1)
      pm += 1;
    }

    pXmcol += n;  //update pointer on Xm to the next column

    //bitwise operations on id to find proper columns
    //look for the next used column of X
    do{
      jump += 1;  //increment number of columns of X to move forward
      varcount += 1; //increment number of total vars of X checked
      //note: each column of X but the first represents a variable

      //set bit as the k'th bit of id (1st bit is far right)
      bit = ( id & ( 1 << varcount ) ) >> varcount; 

      //alternative code: declare tmpid above first.
      ////bit = tmpid & 1;  //bit = 1 if last bit of tmpid is 1, 0 otherwise
      ////tmpid = tmpid >> 1;  //bitshift tmpid right - lopping off last bit
    }
    while(bit == 0 && varcount < p);

       
    pXcol += n*jump; //update pointer on X to the next used column
  }
  while(varcount < p );  
  //if varcount = k ( = p - 1 ), we still have to copy this last column, so the
  //loop must iterate again
  */

  pm = p;
  
  //initialize variables that depend on pm and Xm
  //Xm = (float *) calloc(stride*pm,fbytes);  //allocate memory for model matrix
  Xm = X;
  pXmcol = Xm;
  pXmBlock = Xm; 

  maxCol = pm - 1; //maximum possible column

  colskp = pm;
  maxIdx = getMaxIdx(p, ColNorms, (1 << pm) - 1);
		     //id);
  maxNorm = ColNorms[maxIdx];

  if (maxNorm < tol){
    maxRank = 0; // Short-circuits the main pivot loop
  }
  else{
    minElt = (1.0 + maxNorm) * tol;
    maxRank = n > pm ? pm : n; //min(n,pm)
  }

  blockCount = (pm + blockSize - 1) / blockSize;
  
  for(bc = 0; bc < blockCount; bc++){
    // Determines "blockEnd", which counts the number of columns remaining
    // in the upcoming block.  Swaps trivial columns with the rightmost
    // unvisited column until either a nontrivial column is found or all
    // columns have been visited.  Note that 'blockEnd <= blockSize', with
    // inequality possible only in the rightmost processed block.
    //
    // This pivoting scheme does not attempt to order columns by norm, nor
    // does it recompute norms altered by the rank-one update within the
    // upcoming block.  A higher-fidelity scheme is implemented in the non-
    // blocked form of this function.  Sapienti sat.

    blockEnd = 0;
    
    for(i = kp; i < kp + blockSize && i < maxRank && i <= maxCol; i++){
      float colNorm = ColNorms[i];
	//ColNorms[idx(id, p, i)];

      while( (colNorm < minElt) && (maxCol > i) ){
	//while colNorm is smaller than the lowest acceptable norm, given tolerance
	//and while the maximum column possible is larger than the current column

	//keep track of column swap in pivot vector
	int tempIdx = pivot[maxCol];
	
	//exchange columns of Xm: current column and maxCol
	colswap(Xm, stride, pm, i, maxCol);
	
	pivot[maxCol] = pivot[i];
	pivot[i] = tempIdx;
	    
	maxCol--;

	//set new colNorm as norm of max column, now in i'th spot
	colNorm = ColNorms[i];
	  //ColNorms[idx(id, p, i)];
      }

      if (colNorm >= minElt)
	blockEnd++;
       
    }

    rk += blockEnd;

    //set V to 0 everywhere
    for(a=0; a<blockSize; a++)
      for(b=0; b<rowskp; b++)
	*(V + b + a*rowskp) = 0;

    
    pVcol = V;             //pointer to column of V
    pVdiag = V;            //pointer to diagonal element of V
    pXmdiag = pXmBlock;    //pointer to diagonal element of XmBlock
    
    for(colIdx = 0; colIdx < blockEnd; colIdx++){
      float v1;
      float v1Abs;

      memcpy(pVdiag, pXmdiag, (rowskp - colIdx)*fbytes);
      
      // Builds Householder vector from maximal column just copied.
      // For now, uses slow memory transfers to modify leading element:
      //      V_1 += sign(V_1) * normV.

      v1 = *pVdiag;
      v1Abs = fabs(v1);

      if(kp == maxRow)//botom row is not scaled
	qrAux[kp] = v1Abs;
      else{ // zero-valued "normV" should already have been ruled out.
	int d;
	float normV = 0;
	float recipNormV;
	float fac;
		
	for(d=0; d < rowskp - colIdx; d++){
	  float diag = pVdiag[d];
	  normV += diag*diag;
	}

	normV = sqrtf(normV);
	recipNormV = 1.0 / normV;
	qrAux[kp] = 1.0 + v1Abs * recipNormV;
	scales[colIdx] = (v1 >= 0.f ? 1.f : -1.f) * recipNormV;
	
	// Scales leading nonzero element of vector.
	fac = 1.0 + normV / v1Abs;
	*pVdiag *= fac;

	Beta[colIdx] = -2.0 / (normV * normV + v1Abs * (-1.0 + fac * fac));

	// u = Beta[colIdx] * t(pXmBlock) %*% pVcol
	// rows of pXmBlock = rowskp
	// cols of pXmBlock = min(blockSize, colskp)
	// leading dimension of pXmBlock = stride
	// elements of pVcol = rowskp
	// elements of u = min(blockSize, colskp)
	cXtv(Beta[colIdx], rowskp, min(blockSize, colskp), pXmBlock, stride, pVcol, u);
	
	//pXmBlock = pXmBlock + pVcol %*% u'
	//rows of pXmBlock = rowskp
	//cols of pXmBlock = min(blockSize, colsk)
	//elements of pVcol = rowskp
	//elements of u = min(blockSize, colsk)
	//leading dim of pXmBlock = stride
	Xpvut(rowskp, min(blockSize, colskp), pXmBlock, stride, pVcol, u);
	
      }

      pVcol += rowskp; 
      pVdiag += (rowskp + 1); 
      pXmdiag += (stride + 1); 
      kp++;
    }

    
    // If more unseen columns remain, updates the remainder of QR lying to
    // the right of the block just updated.  This must be done unless we
    // happen to have exited the inner loop without having applied any
    // Householder transformations (i.e., blockEnd == 0).
    if (bc < blockCount - 1 && blockEnd > 0) {
      // w_m = Beta (I + W V^t) v_m, where the unsubscripted matrices
      // refer to those built at step 'i-1', having 'i' columns.
      //
      // w_i = Beta v_i
      //

      
      float *pTcol = T;  //pointer to columns of dT
      float *pWcol = W;  //pointer to columns of dW
      int m, a, b, c;
      pVcol = V;  //pointer to columns of dV
      
      //  T = V^t V
      //// T = dT
      //// V = dV
      //rows of V' = blockSize
      //cols of V' = rowsk
      //leading dim of V = rowsk
      //leading dim of T = rowsk
      //rows/cols of T = blockSize
      uVtV(rowskp, blockSize, V, T);

      for (m = 0; m < blockSize; m++, pWcol += rowskp, pVcol += rowskp, 
	     pTcol += blockSize) {
	//for m=0,1,..., blockSize - 1
	//pdWcol += rowsk
	//pdVcol += rowsk
	//pdTcol += blockSize
	int a;

	for(a = 0; a<rowskp; a++)
	  pWcol[a] = Beta[m]*pVcol[a];
	
	// w_m = w_m + Beta W T(.,m)
	//// w_m = pWcol
	//// Beta = Beta[m]
	//// T(.,m) = pTcol
	//// W = dW
	if (m > 0) {
	  int a, b;
	  for(a = 0; a < rowskp; a++){
	    float sum = 0;
	    for(b = 0; b < m; b++){
	      sum += W[b + a*m] * pTcol[b];
	    }
	    pWcol[a] += sum;
	  }
	}
      }

      
      // Updates R, beginning at current diagonal by:
      //   R = (I_m + V W^t) R = R + V (W^t R)
      //
      
      // WtR = W^t R
      //// WtR = dWtR
      //// W = dW
      //W is rowskp by blockSize
      //pXmBlock + blockSize*stride is rowskp by colskp - blockSize
      //WtR is blockSize by colsk - blockSize
      for(a = 0; a < blockSize; a++){
	for(b = 0; b < colskp - blockSize; b++){
	  float sum = 0;
	  for(c = 0; c < rowskp; c++)
	    sum += W[c + rowskp*a] * *(pXmBlock + blockSize*stride + c + b*rowskp);
	  WtR[a + b*blockSize] = sum;
	}
      }

      // R = V WtR + R
      //// V = dV 
      //// WtR = dWtR
      //// R = pdQRBlock + blockSize*stride
      // V is rowskp by blockSize
      //WtR is blockSize by colskp - blockSize
      //pXmBlock + blockSize*stride is rowskp by colskp - blockSize
      for(a = 0; a < rowskp; a++){
	for(b = 0; b < colskp - blockSize; b++){
	  float sum = 0;
	  for(c = 0; c < blockSize; c++){
	    sum += V[a + c*rowskp] * WtR[c + b*blockSize];
	  }
	  *(pXmBlock + blockSize*stride + a + b*rowskp) += sum;
	}
      }

    }
      
    // Flushes scaled Householder vectors to the subdiagonals of dQR,
    // 'blockSize'-many at a time.  The only time a smaller number are
    // sent occurs when a partial block remains at the right end.
    //
    pVdiag = V;  //pointer to diagonal of V
    pXmdiag = pXmBlock;  //pointer to diagonal of pXmBlock / XmBlock

    
    for (l = 0; l < blockEnd; l++, pVdiag += (rowskp + 1),
	   pXmdiag += (stride + 1)) {
      //for l = 0, 1, ..., blockEnd - 1
      //// pVdiag += (rowskp + 1)
      //// pXmdiag += (stride +1)
      
      int a;

      //pVdiag + 1 = scales[l]* (pVdiag + 1)
      //pXmdiag + 1 = pVdiag + 1
      for(a = 0; a < rowskp - l - 1; a++){
	*(pVdiag + 1 + a) *= scales[l];
	*(pXmdiag + 1 + a) = *(pVdiag + 1 + a);
      }

    }
    
    pXmBlock += blockSize * (stride + 1);
    colskp -= blockSize;
    rowskp -= blockSize;
    
    //end main loop

  }

  
  //set rank
  *rank = rk;	
       
  // Xm now contains the upper-triangular portion of the factorization,
  // R.
  // V is lower-triangular, and contains the Householder vectors, from
  // which the Q portion can be derived.  An adjusted form of the
  // diagonal is saved in qrAux, while the sub-diagonal portion is
  // written onto QR.


}

int main(void){
  int n = 10, p = 5;
  //, k = p - 1;
  int i, j;
  size_t fbytes = sizeof(float);
  float * X = (float *)malloc(n*p*fbytes);
  float * dX, * dColNorms;
  int nblocks, nthreads = NTHREADS;
  const unsigned blockExp = 7;
  unsigned int blockSize = 1 << blockExp;
  int stride = (n + blockSize - 1) & (((unsigned) -1) << blockExp);

  float * dscales;
  float * dBeta;
  float * dqrAux;
  int * dpivot;
  float * dWtR;
  int * drank;
  float * dV;
  float * dW; 
  float * dT; 
  float * du; 

  for(i=0; i<n; i++)
    for(j=0; j<p; j++)
      X[i + j*n] = i + j;

  printf("\n X \n");

  for(i=0; i<n; i++){
    for(j=0; j<p; j++){
      printf("%.f ", X[i + j*n]);
    }
    printf("\n");
  }
    
  
  cudaMalloc( (void **)&dX, n*p*fbytes );
  cudaMalloc( (void **)&dColNorms, p*fbytes);
  cudaMalloc( (void **)&dscales, blockSize*fbytes);
  cudaMalloc( (void **)&dBeta, blockSize*fbytes);
  cudaMalloc( (void **)&dqrAux, p*fbytes);
  cudaMalloc( (void **)&dpivot, p*sizeof(int));
  cudaMalloc( (void **)&dWtR, blockSize*(p - blockSize)*fbytes);
  cudaMalloc( (void **)&drank, sizeof(int));
  cudaMalloc( (void **)&dV, blockSize*stride*fbytes);
  cudaMalloc( (void **)&dW, blockSize*stride*fbytes);
  cudaMalloc( (void **)&dT, blockSize*blockSize*fbytes);
  cudaMalloc( (void **)&du, stride*fbytes);


  cudaMemcpy( dX, X, n*p*fbytes, cudaMemcpyHostToDevice);

  nblocks = p / nthreads;
  if(nblocks * nthreads < p)
      nblocks++;

  getColNorms<<<nblocks, nthreads>>>(n, p, dX, dColNorms);

  GetQRDecompBlocked<<<1,1>>>(n, p, dX, dColNorms, blockSize, stride, dscales, dBeta,
			      dqrAux, dpivot, dWtR, drank, dV, dW, dT, du);

  cudaMemcpy( X, dX, n*p*fbytes, cudaMemcpyDeviceToHost);

  printf("\n R \n");

  for(i=0; i<n; i++){
    for(j=0; j<p; j++){
      printf("%.f ", X[i + j*n]);
    }
    printf("\n");
  }

  cudaFree(dX);
  cudaFree(dColNorms);
  free(X);
  cudaFree(dscales);
  cudaFree(dBeta);
  cudaFree(dqrAux);
  cudaFree(dpivot);
  cudaFree(dWtR);
  cudaFree(drank);
  cudaFree(dV);
  cudaFree(dW);
  cudaFree(dT);
  cudaFree(du);

  return 0;

} 

	.file	"tmpxft_0035ff81_00000000-6_qrdecomp.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2037:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2037:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z4cXtvfiiPfiS_S_
	.type	_Z4cXtvfiiPfiS_S_, @function
_Z4cXtvfiiPfiS_S_:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2027:
	.size	_Z4cXtvfiiPfiS_S_, .-_Z4cXtvfiiPfiS_S_
	.globl	_Z5XpvutiiPfiS_S_
	.type	_Z5XpvutiiPfiS_S_, @function
_Z5XpvutiiPfiS_S_:
.LFB2028:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2028:
	.size	_Z5XpvutiiPfiS_S_, .-_Z5XpvutiiPfiS_S_
	.globl	_Z4uVtViiPfS_
	.type	_Z4uVtViiPfS_, @function
_Z4uVtViiPfS_:
.LFB2029:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2029:
	.size	_Z4uVtViiPfS_, .-_Z4uVtViiPfS_
	.globl	_Z10alignBlockij
	.type	_Z10alignBlockij, @function
_Z10alignBlockij:
.LFB2030:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2030:
	.size	_Z10alignBlockij, .-_Z10alignBlockij
	.globl	_Z7colswapPfiiii
	.type	_Z7colswapPfiiii, @function
_Z7colswapPfiiii:
.LFB2031:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2031:
	.size	_Z7colswapPfiiii, .-_Z7colswapPfiiii
	.globl	_Z9getMaxIdxiPfi
	.type	_Z9getMaxIdxiPfi, @function
_Z9getMaxIdxiPfi:
.LFB2032:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2032:
	.size	_Z9getMaxIdxiPfi, .-_Z9getMaxIdxiPfi
	.globl	_Z3idxiii
	.type	_Z3idxiii, @function
_Z3idxiii:
.LFB2033:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2033:
	.size	_Z3idxiii, .-_Z3idxiii
	.globl	_Z35__device_stub__Z11getColNormsiiPfS_iiPfS_
	.type	_Z35__device_stub__Z11getColNormsiiPfS_iiPfS_, @function
_Z35__device_stub__Z11getColNormsiiPfS_iiPfS_:
.LFB2059:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movl	%edi, 28(%rsp)
	leaq	56(%rsp), %rdi
	movl	%esi, 24(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 16(%rsp)
	leaq	40(%rsp), %rdx
	movq	%rcx, 8(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	28(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L16
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z11getColNormsiiPfS_(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L16:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L18
	call	__stack_chk_fail@PLT
.L18:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2059:
	.size	_Z35__device_stub__Z11getColNormsiiPfS_iiPfS_, .-_Z35__device_stub__Z11getColNormsiiPfS_iiPfS_
	.globl	_Z11getColNormsiiPfS_
	.type	_Z11getColNormsiiPfS_, @function
_Z11getColNormsiiPfS_:
.LFB2060:
	.cfi_startproc
	endbr64
	jmp	_Z35__device_stub__Z11getColNormsiiPfS_iiPfS_
	.cfi_endproc
.LFE2060:
	.size	_Z11getColNormsiiPfS_, .-_Z11getColNormsiiPfS_
	.globl	_Z65__device_stub__Z18GetQRDecompBlockediiPfS_jiS_S_S_PiS_S0_S_S_S_S_iiPfS_jiS_S_S_PiS_S0_S_S_S_S_
	.type	_Z65__device_stub__Z18GetQRDecompBlockediiPfS_jiS_S_S_PiS_S0_S_S_S_S_iiPfS_jiS_S_S_PiS_S0_S_S_S_S_, @function
_Z65__device_stub__Z18GetQRDecompBlockediiPfS_jiS_S_S_PiS_S0_S_S_S_S_iiPfS_jiS_S_S_PiS_S0_S_S_S_S_:
.LFB2061:
	.cfi_startproc
	endbr64
	subq	$328, %rsp
	.cfi_def_cfa_offset 336
	movq	336(%rsp), %rax
	movl	%edi, 108(%rsp)
	leaq	136(%rsp), %rdi
	movl	%esi, 104(%rsp)
	leaq	148(%rsp), %rsi
	movq	%rax, 72(%rsp)
	movq	344(%rsp), %rax
	movq	%rdx, 96(%rsp)
	leaq	120(%rsp), %rdx
	movq	%rax, 64(%rsp)
	movq	352(%rsp), %rax
	movq	%rcx, 88(%rsp)
	leaq	128(%rsp), %rcx
	movq	%rax, 56(%rsp)
	movq	360(%rsp), %rax
	movl	%r8d, 84(%rsp)
	movq	%rax, 48(%rsp)
	movq	368(%rsp), %rax
	movl	%r9d, 80(%rsp)
	movq	%rax, 40(%rsp)
	movq	376(%rsp), %rax
	movq	%rax, 32(%rsp)
	movq	384(%rsp), %rax
	movq	%rax, 24(%rsp)
	movq	392(%rsp), %rax
	movq	%rax, 16(%rsp)
	movq	400(%rsp), %rax
	movq	%rax, 8(%rsp)
	movq	408(%rsp), %rax
	movq	%rax, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 312(%rsp)
	xorl	%eax, %eax
	leaq	108(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	104(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	96(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	88(%rsp), %rax
	movq	%rax, 208(%rsp)
	leaq	84(%rsp), %rax
	movq	%rax, 216(%rsp)
	leaq	80(%rsp), %rax
	movq	%rax, 224(%rsp)
	leaq	72(%rsp), %rax
	movq	%rax, 232(%rsp)
	leaq	64(%rsp), %rax
	movq	%rax, 240(%rsp)
	leaq	56(%rsp), %rax
	movq	%rax, 248(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 256(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 264(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 272(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 280(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 288(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 296(%rsp)
	movq	%rsp, %rax
	movq	%rax, 304(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 136(%rsp)
	movl	$1, 144(%rsp)
	movq	%rax, 148(%rsp)
	movl	$1, 156(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L22
	pushq	128(%rsp)
	.cfi_def_cfa_offset 344
	leaq	_Z18GetQRDecompBlockediiPfS_jiS_S_S_PiS_S0_S_S_S_S_(%rip), %rdi
	pushq	128(%rsp)
	.cfi_def_cfa_offset 352
	movq	164(%rsp), %rcx
	movl	172(%rsp), %r8d
	movq	152(%rsp), %rsi
	movl	160(%rsp), %edx
	leaq	200(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 344
	popq	%rdx
	.cfi_def_cfa_offset 336
.L22:
	movq	312(%rsp), %rax
	subq	%fs:40, %rax
	je	.L24
	call	__stack_chk_fail@PLT
.L24:
	addq	$328, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2061:
	.size	_Z65__device_stub__Z18GetQRDecompBlockediiPfS_jiS_S_S_PiS_S0_S_S_S_S_iiPfS_jiS_S_S_PiS_S0_S_S_S_S_, .-_Z65__device_stub__Z18GetQRDecompBlockediiPfS_jiS_S_S_PiS_S0_S_S_S_S_iiPfS_jiS_S_S_PiS_S0_S_S_S_S_
	.globl	_Z18GetQRDecompBlockediiPfS_jiS_S_S_PiS_S0_S_S_S_S_
	.type	_Z18GetQRDecompBlockediiPfS_jiS_S_S_PiS_S0_S_S_S_S_, @function
_Z18GetQRDecompBlockediiPfS_jiS_S_S_PiS_S0_S_S_S_S_:
.LFB2062:
	.cfi_startproc
	endbr64
	jmp	_Z65__device_stub__Z18GetQRDecompBlockediiPfS_jiS_S_S_PiS_S0_S_S_S_S_iiPfS_jiS_S_S_PiS_S0_S_S_S_S_
	.cfi_endproc
.LFE2062:
	.size	_Z18GetQRDecompBlockediiPfS_jiS_S_S_PiS_S0_S_S_S_S_, .-_Z18GetQRDecompBlockediiPfS_jiS_S_S_PiS_S0_S_S_S_S_
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"\n X \n"
.LC1:
	.string	"%.f "
.LC2:
	.string	"\n"
.LC3:
	.string	"\n R \n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2034:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movl	$200, %edi
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$136, %rsp
	.cfi_def_cfa_offset 192
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	call	malloc@PLT
	xorl	%edx, %edx
	movq	%rax, %rbx
	movq	%rax, %rsi
.L28:
	movq	%rsi, %rcx
	xorl	%eax, %eax
.L29:
	leal	(%rax,%rdx), %edi
	incl	%eax
	addq	$40, %rcx
	cvtsi2ssl	%edi, %xmm0
	movss	%xmm0, -40(%rcx)
	cmpl	$5, %eax
	jne	.L29
	incl	%edx
	addq	$4, %rsi
	cmpl	$10, %edx
	jne	.L28
	leaq	.LC0(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	xorl	%ebp, %ebp
	call	__printf_chk@PLT
	leaq	.LC1(%rip), %r12
.L31:
	leaq	(%rbx,%rbp,4), %r14
	xorl	%r13d, %r13d
.L32:
	movq	%r12, %rsi
	movl	$2, %edi
	movb	$1, %al
	incl	%r13d
	cvtss2sd	(%r14), %xmm0
	call	__printf_chk@PLT
	addq	$40, %r14
	cmpl	$5, %r13d
	jne	.L32
	leaq	.LC2(%rip), %r13
	movl	$2, %edi
	xorl	%eax, %eax
	incq	%rbp
	movq	%r13, %rsi
	call	__printf_chk@PLT
	cmpq	$10, %rbp
	jne	.L31
	movq	%rsp, %rdi
	movl	$200, %esi
	call	cudaMalloc@PLT
	leaq	8(%rsp), %rdi
	movl	$20, %esi
	call	cudaMalloc@PLT
	leaq	16(%rsp), %rdi
	movl	$512, %esi
	call	cudaMalloc@PLT
	leaq	24(%rsp), %rdi
	movl	$512, %esi
	call	cudaMalloc@PLT
	leaq	32(%rsp), %rdi
	movl	$20, %esi
	call	cudaMalloc@PLT
	leaq	40(%rsp), %rdi
	movl	$20, %esi
	call	cudaMalloc@PLT
	movl	$33554309, %esi
	leaq	48(%rsp), %rdi
	salq	$9, %rsi
	call	cudaMalloc@PLT
	leaq	56(%rsp), %rdi
	movl	$4, %esi
	call	cudaMalloc@PLT
	leaq	64(%rsp), %rdi
	movl	$65536, %esi
	call	cudaMalloc@PLT
	leaq	72(%rsp), %rdi
	movl	$65536, %esi
	call	cudaMalloc@PLT
	leaq	80(%rsp), %rdi
	movl	$65536, %esi
	call	cudaMalloc@PLT
	leaq	88(%rsp), %rdi
	movl	$512, %esi
	call	cudaMalloc@PLT
	movq	(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbx, %rsi
	movl	$200, %edx
	call	cudaMemcpy@PLT
	movl	$8388609, %edx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	salq	$9, %rdx
	movl	$1, %ecx
	movabsq	$4294967297, %rdi
	movl	$1, %esi
	movq	%rdx, 108(%rsp)
	movl	$1, 116(%rsp)
	movq	%rdi, 96(%rsp)
	movl	$1, 104(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L34
	movq	8(%rsp), %rcx
	movq	(%rsp), %rdx
	movl	$5, %esi
	movl	$10, %edi
	call	_Z35__device_stub__Z11getColNormsiiPfS_iiPfS_
.L34:
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$1, %ecx
	movl	$1, %esi
	movabsq	$4294967297, %rdi
	movl	$1, 116(%rsp)
	movq	%rdi, %rdx
	movq	%rdi, 108(%rsp)
	movq	%rdi, 96(%rsp)
	movl	$1, 104(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L35
	pushq	88(%rsp)
	.cfi_def_cfa_offset 200
	movl	$128, %r9d
	movl	$128, %r8d
	movl	$5, %esi
	pushq	88(%rsp)
	.cfi_def_cfa_offset 208
	movl	$10, %edi
	pushq	88(%rsp)
	.cfi_def_cfa_offset 216
	pushq	88(%rsp)
	.cfi_def_cfa_offset 224
	pushq	88(%rsp)
	.cfi_def_cfa_offset 232
	pushq	88(%rsp)
	.cfi_def_cfa_offset 240
	pushq	88(%rsp)
	.cfi_def_cfa_offset 248
	pushq	88(%rsp)
	.cfi_def_cfa_offset 256
	pushq	88(%rsp)
	.cfi_def_cfa_offset 264
	pushq	88(%rsp)
	.cfi_def_cfa_offset 272
	movq	88(%rsp), %rcx
	movq	80(%rsp), %rdx
	call	_Z65__device_stub__Z18GetQRDecompBlockediiPfS_jiS_S_S_PiS_S0_S_S_S_S_iiPfS_jiS_S_S_PiS_S0_S_S_S_S_
	addq	$80, %rsp
	.cfi_def_cfa_offset 192
.L35:
	movq	(%rsp), %rsi
	movl	$2, %ecx
	movl	$200, %edx
	xorl	%ebp, %ebp
	movq	%rbx, %rdi
	call	cudaMemcpy@PLT
	leaq	.LC3(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
.L36:
	leaq	(%rbx,%rbp,4), %r15
	xorl	%r14d, %r14d
.L37:
	movq	%r12, %rsi
	movl	$2, %edi
	movb	$1, %al
	incl	%r14d
	cvtss2sd	(%r15), %xmm0
	call	__printf_chk@PLT
	addq	$40, %r15
	cmpl	$5, %r14d
	jne	.L37
	movq	%r13, %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	incq	%rbp
	call	__printf_chk@PLT
	cmpq	$10, %rbp
	jne	.L36
	movq	(%rsp), %rdi
	call	cudaFree@PLT
	movq	8(%rsp), %rdi
	call	cudaFree@PLT
	movq	%rbx, %rdi
	call	free@PLT
	movq	16(%rsp), %rdi
	call	cudaFree@PLT
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	movq	32(%rsp), %rdi
	call	cudaFree@PLT
	movq	40(%rsp), %rdi
	call	cudaFree@PLT
	movq	48(%rsp), %rdi
	call	cudaFree@PLT
	movq	56(%rsp), %rdi
	call	cudaFree@PLT
	movq	64(%rsp), %rdi
	call	cudaFree@PLT
	movq	72(%rsp), %rdi
	call	cudaFree@PLT
	movq	80(%rsp), %rdi
	call	cudaFree@PLT
	movq	88(%rsp), %rdi
	call	cudaFree@PLT
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L39
	call	__stack_chk_fail@PLT
.L39:
	addq	$136, %rsp
	.cfi_def_cfa_offset 56
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2034:
	.size	main, .-main
	.section	.rodata.str1.1
.LC4:
	.string	"_Z18GetQRDecompBlockediiPfS_jiS_S_S_PiS_S0_S_S_S_S_"
.LC5:
	.string	"_Z11getColNormsiiPfS_"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2064:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC4(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z18GetQRDecompBlockediiPfS_jiS_S_S_PiS_S0_S_S_S_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC5(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z11getColNormsiiPfS_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2064:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include<stdio.h>
#include<stdlib.h>
#include<string.h>
//#include<cublas.h>
//#include<R.h>

#define NTHREADS 512


//computes u = constant * t(X) %*% v
__device__ void cXtv(float con, int rows, int cols, float * X, int ldX, float * v, 
		     float * u){
  int i,k;
  float sum;

  for(k = 0; k < cols; k++){
    sum = 0;
    for(i = 0; i < rows; i++){
      sum += X[i + k*ldX] * v[i];
    }
    u[k] = con*sum;
  }
}

//computes X = X + v %*% u'
__device__ void Xpvut(int rows, int cols, float * X, int ldX, float *v, float *u){
  int i, j;
  
  for(i=0; i<rows; i++)
    for(j=0; j<cols; j++)
      X[i + j*ldX] += v[i] * u[j];
}


//calculates T = V'V where V is upper triangular
__device__ void uVtV(int rows, int cols, float * V, float * T){
  int i, j, k;
  float sum;
  for(i=0; i<cols; i++){
    for(j=0; j<cols; j++){
      sum = 0;
      for(k=0; k<min(i,j); k++)
	sum += V[k + i*rows] * V[k + j*rows];
      T[i + j*cols] = sum;
    }
  }
}


//Rounds "length" up the the next multiple of block length
__device__ int alignBlock(int length, unsigned blockExp){
  int blockSize = 1 << blockExp;
  int out = (length + blockSize - 1) & ( ( (unsigned) - 1) << blockExp);
  return out;
}

__device__ void colswap(float *X, int n, int p, int i, int j){
  float tmp;
  int k;
  float * Xi = X + i*n;
  float * Xj = X + i*j;
  if(i <= p && j <= p){
    for(k = 0; k < n; k++){
      tmp = Xi[k];
      Xi[k] = Xj[k];
      Xj[k] = tmp;
    }
  }
}

__device__ int getMaxIdx(int p, float * ColNorms, int id){
  int maxIdx = 0, i, bit;
  float max = ColNorms[maxIdx], tmp;

  for(i = 1; i < p; i++){
    bit =  ( id & (1 << i) ) >> 1;
    if( bit == 1){
      tmp = ColNorms[i];
      if(tmp > max){
	max = tmp;
	maxIdx = i;
      }
    }
  }

  return maxIdx;
}

__device__ int idx(int id, int p, int i){
  int j, colcount=0, out;

  for(j=0; j<p; j++){

    if(colcount == i)
      out = j;
    
    if( ( id & ( 1 << j ) ) >> j == 1)
      colcount += 1;
  }

  return out;
}

__global__ void getColNorms(int rows, int cols, float * dX, float * ColNorms){

	int colIndex = threadIdx.x + blockIdx.x * blockDim.x;
	float sum = 0.f, term, * col;

	if(colIndex >= cols)
	  return;

	col = dX + colIndex * rows;

	// debug printing
	// printf("printing column %d\n", colIndex);
	// for(int i = 0; i < rows; i++)
	// printf("%f, ", col[i]);
	// puts("");
	// end debug printing

	for(int i = 0; i < rows; i++) {
		term = col[i];
		term *= term;
		sum += term;
	}

	// debug printing
	// printf("norm %f\n", norm);
	// end debug printing

	ColNorms[colIndex] = sqrtf(sum);
}

__global__ void GetQRDecompBlocked(int n, int p, float * X, float * ColNorms, 
				   unsigned int blockSize, int stride, float * scales, 
				   float * Beta, float * qrAux, int * pivot, 
				   float * WtR, int * rank, float * V, float * W,
				   float * T, float * u){
  
  float tol = 0.0001;  //float tolerance
  int blockCount, blockEnd = 0, bc, i, kp;  //kp is # cols processed

  //unsigned int id = threadIDx.x + blockIDx.x * blockDim.x;
  int varcount = 0, maxIdx, pm = 1; 
  //unsigned int * binid;
  float * Xm; //model id's model matrix; will eventually contain R in QR decomp
  //float * pXcol = X; //pointer to column of X
  float * pXmcol; //pointer to column of Xm
  float maxNorm;
  float * pXmBlock; //pointer to block of Xm 
  size_t fbytes = sizeof(float);
  int rk = 0; // Local value of rank;
  int maxRank;  //maximum possible rank of the model matrix
  float minElt; // Lowest acceptable norm under given tolerance.
  int maxCol; //this will be initialized to pm - 1, highest candidate column, not fixed
  int maxRow = n - 1;
  int rowskp = stride; // # unprocessed rows = stride - kp
  int colskp;   // # unprocessed cols = cols - kp
  float *pVcol;             //pointer to column of V
  float *pVdiag;            //pointer to diagonal element of V
  float *pXmdiag;    //pointer to diagonal element of dQRBlock
  int colIdx;
  int a,b;
  int l;


  //if(id > M)
  //  return;

  //binid = (unsigned int *)calloc(p-1, sizeof(unsigned int));

  /*
  //copies the relevant columns of X into Xm
  do{
    int jump = 0;
    unsigned int bit = 0;

    memcpy(pXmcol, pXcol, n*fbytes);  //copy the current column

    //any time we copy any column but the first, set binid[col] = 1
    if(varcount > 0){ 
      binid[p - varcount] = 1; //actual index is (p - 1) - (varcount - 1)
      pm += 1;
    }

    pXmcol += n;  //update pointer on Xm to the next column

    //bitwise operations on id to find proper columns
    //look for the next used column of X
    do{
      jump += 1;  //increment number of columns of X to move forward
      varcount += 1; //increment number of total vars of X checked
      //note: each column of X but the first represents a variable

      //set bit as the k'th bit of id (1st bit is far right)
      bit = ( id & ( 1 << varcount ) ) >> varcount; 

      //alternative code: declare tmpid above first.
      ////bit = tmpid & 1;  //bit = 1 if last bit of tmpid is 1, 0 otherwise
      ////tmpid = tmpid >> 1;  //bitshift tmpid right - lopping off last bit
    }
    while(bit == 0 && varcount < p);

       
    pXcol += n*jump; //update pointer on X to the next used column
  }
  while(varcount < p );  
  //if varcount = k ( = p - 1 ), we still have to copy this last column, so the
  //loop must iterate again
  */

  pm = p;
  
  //initialize variables that depend on pm and Xm
  //Xm = (float *) calloc(stride*pm,fbytes);  //allocate memory for model matrix
  Xm = X;
  pXmcol = Xm;
  pXmBlock = Xm; 

  maxCol = pm - 1; //maximum possible column

  colskp = pm;
  maxIdx = getMaxIdx(p, ColNorms, (1 << pm) - 1);
		     //id);
  maxNorm = ColNorms[maxIdx];

  if (maxNorm < tol){
    maxRank = 0; // Short-circuits the main pivot loop
  }
  else{
    minElt = (1.0 + maxNorm) * tol;
    maxRank = n > pm ? pm : n; //min(n,pm)
  }

  blockCount = (pm + blockSize - 1) / blockSize;
  
  for(bc = 0; bc < blockCount; bc++){
    // Determines "blockEnd", which counts the number of columns remaining
    // in the upcoming block.  Swaps trivial columns with the rightmost
    // unvisited column until either a nontrivial column is found or all
    // columns have been visited.  Note that 'blockEnd <= blockSize', with
    // inequality possible only in the rightmost processed block.
    //
    // This pivoting scheme does not attempt to order columns by norm, nor
    // does it recompute norms altered by the rank-one update within the
    // upcoming block.  A higher-fidelity scheme is implemented in the non-
    // blocked form of this function.  Sapienti sat.

    blockEnd = 0;
    
    for(i = kp; i < kp + blockSize && i < maxRank && i <= maxCol; i++){
      float colNorm = ColNorms[i];
	//ColNorms[idx(id, p, i)];

      while( (colNorm < minElt) && (maxCol > i) ){
	//while colNorm is smaller than the lowest acceptable norm, given tolerance
	//and while the maximum column possible is larger than the current column

	//keep track of column swap in pivot vector
	int tempIdx = pivot[maxCol];
	
	//exchange columns of Xm: current column and maxCol
	colswap(Xm, stride, pm, i, maxCol);
	
	pivot[maxCol] = pivot[i];
	pivot[i] = tempIdx;
	    
	maxCol--;

	//set new colNorm as norm of max column, now in i'th spot
	colNorm = ColNorms[i];
	  //ColNorms[idx(id, p, i)];
      }

      if (colNorm >= minElt)
	blockEnd++;
       
    }

    rk += blockEnd;

    //set V to 0 everywhere
    for(a=0; a<blockSize; a++)
      for(b=0; b<rowskp; b++)
	*(V + b + a*rowskp) = 0;

    
    pVcol = V;             //pointer to column of V
    pVdiag = V;            //pointer to diagonal element of V
    pXmdiag = pXmBlock;    //pointer to diagonal element of XmBlock
    
    for(colIdx = 0; colIdx < blockEnd; colIdx++){
      float v1;
      float v1Abs;

      memcpy(pVdiag, pXmdiag, (rowskp - colIdx)*fbytes);
      
      // Builds Householder vector from maximal column just copied.
      // For now, uses slow memory transfers to modify leading element:
      //      V_1 += sign(V_1) * normV.

      v1 = *pVdiag;
      v1Abs = fabs(v1);

      if(kp == maxRow)//botom row is not scaled
	qrAux[kp] = v1Abs;
      else{ // zero-valued "normV" should already have been ruled out.
	int d;
	float normV = 0;
	float recipNormV;
	float fac;
		
	for(d=0; d < rowskp - colIdx; d++){
	  float diag = pVdiag[d];
	  normV += diag*diag;
	}

	normV = sqrtf(normV);
	recipNormV = 1.0 / normV;
	qrAux[kp] = 1.0 + v1Abs * recipNormV;
	scales[colIdx] = (v1 >= 0.f ? 1.f : -1.f) * recipNormV;
	
	// Scales leading nonzero element of vector.
	fac = 1.0 + normV / v1Abs;
	*pVdiag *= fac;

	Beta[colIdx] = -2.0 / (normV * normV + v1Abs * (-1.0 + fac * fac));

	// u = Beta[colIdx] * t(pXmBlock) %*% pVcol
	// rows of pXmBlock = rowskp
	// cols of pXmBlock = min(blockSize, colskp)
	// leading dimension of pXmBlock = stride
	// elements of pVcol = rowskp
	// elements of u = min(blockSize, colskp)
	cXtv(Beta[colIdx], rowskp, min(blockSize, colskp), pXmBlock, stride, pVcol, u);
	
	//pXmBlock = pXmBlock + pVcol %*% u'
	//rows of pXmBlock = rowskp
	//cols of pXmBlock = min(blockSize, colsk)
	//elements of pVcol = rowskp
	//elements of u = min(blockSize, colsk)
	//leading dim of pXmBlock = stride
	Xpvut(rowskp, min(blockSize, colskp), pXmBlock, stride, pVcol, u);
	
      }

      pVcol += rowskp; 
      pVdiag += (rowskp + 1); 
      pXmdiag += (stride + 1); 
      kp++;
    }

    
    // If more unseen columns remain, updates the remainder of QR lying to
    // the right of the block just updated.  This must be done unless we
    // happen to have exited the inner loop without having applied any
    // Householder transformations (i.e., blockEnd == 0).
    if (bc < blockCount - 1 && blockEnd > 0) {
      // w_m = Beta (I + W V^t) v_m, where the unsubscripted matrices
      // refer to those built at step 'i-1', having 'i' columns.
      //
      // w_i = Beta v_i
      //

      
      float *pTcol = T;  //pointer to columns of dT
      float *pWcol = W;  //pointer to columns of dW
      int m, a, b, c;
      pVcol = V;  //pointer to columns of dV
      
      //  T = V^t V
      //// T = dT
      //// V = dV
      //rows of V' = blockSize
      //cols of V' = rowsk
      //leading dim of V = rowsk
      //leading dim of T = rowsk
      //rows/cols of T = blockSize
      uVtV(rowskp, blockSize, V, T);

      for (m = 0; m < blockSize; m++, pWcol += rowskp, pVcol += rowskp, 
	     pTcol += blockSize) {
	//for m=0,1,..., blockSize - 1
	//pdWcol += rowsk
	//pdVcol += rowsk
	//pdTcol += blockSize
	int a;

	for(a = 0; a<rowskp; a++)
	  pWcol[a] = Beta[m]*pVcol[a];
	
	// w_m = w_m + Beta W T(.,m)
	//// w_m = pWcol
	//// Beta = Beta[m]
	//// T(.,m) = pTcol
	//// W = dW
	if (m > 0) {
	  int a, b;
	  for(a = 0; a < rowskp; a++){
	    float sum = 0;
	    for(b = 0; b < m; b++){
	      sum += W[b + a*m] * pTcol[b];
	    }
	    pWcol[a] += sum;
	  }
	}
      }

      
      // Updates R, beginning at current diagonal by:
      //   R = (I_m + V W^t) R = R + V (W^t R)
      //
      
      // WtR = W^t R
      //// WtR = dWtR
      //// W = dW
      //W is rowskp by blockSize
      //pXmBlock + blockSize*stride is rowskp by colskp - blockSize
      //WtR is blockSize by colsk - blockSize
      for(a = 0; a < blockSize; a++){
	for(b = 0; b < colskp - blockSize; b++){
	  float sum = 0;
	  for(c = 0; c < rowskp; c++)
	    sum += W[c + rowskp*a] * *(pXmBlock + blockSize*stride + c + b*rowskp);
	  WtR[a + b*blockSize] = sum;
	}
      }

      // R = V WtR + R
      //// V = dV 
      //// WtR = dWtR
      //// R = pdQRBlock + blockSize*stride
      // V is rowskp by blockSize
      //WtR is blockSize by colskp - blockSize
      //pXmBlock + blockSize*stride is rowskp by colskp - blockSize
      for(a = 0; a < rowskp; a++){
	for(b = 0; b < colskp - blockSize; b++){
	  float sum = 0;
	  for(c = 0; c < blockSize; c++){
	    sum += V[a + c*rowskp] * WtR[c + b*blockSize];
	  }
	  *(pXmBlock + blockSize*stride + a + b*rowskp) += sum;
	}
      }

    }
      
    // Flushes scaled Householder vectors to the subdiagonals of dQR,
    // 'blockSize'-many at a time.  The only time a smaller number are
    // sent occurs when a partial block remains at the right end.
    //
    pVdiag = V;  //pointer to diagonal of V
    pXmdiag = pXmBlock;  //pointer to diagonal of pXmBlock / XmBlock

    
    for (l = 0; l < blockEnd; l++, pVdiag += (rowskp + 1),
	   pXmdiag += (stride + 1)) {
      //for l = 0, 1, ..., blockEnd - 1
      //// pVdiag += (rowskp + 1)
      //// pXmdiag += (stride +1)
      
      int a;

      //pVdiag + 1 = scales[l]* (pVdiag + 1)
      //pXmdiag + 1 = pVdiag + 1
      for(a = 0; a < rowskp - l - 1; a++){
	*(pVdiag + 1 + a) *= scales[l];
	*(pXmdiag + 1 + a) = *(pVdiag + 1 + a);
      }

    }
    
    pXmBlock += blockSize * (stride + 1);
    colskp -= blockSize;
    rowskp -= blockSize;
    
    //end main loop

  }

  
  //set rank
  *rank = rk;	
       
  // Xm now contains the upper-triangular portion of the factorization,
  // R.
  // V is lower-triangular, and contains the Householder vectors, from
  // which the Q portion can be derived.  An adjusted form of the
  // diagonal is saved in qrAux, while the sub-diagonal portion is
  // written onto QR.


}

int main(void){
  int n = 10, p = 5;
  //, k = p - 1;
  int i, j;
  size_t fbytes = sizeof(float);
  float * X = (float *)malloc(n*p*fbytes);
  float * dX, * dColNorms;
  int nblocks, nthreads = NTHREADS;
  const unsigned blockExp = 7;
  unsigned int blockSize = 1 << blockExp;
  int stride = (n + blockSize - 1) & (((unsigned) -1) << blockExp);

  float * dscales;
  float * dBeta;
  float * dqrAux;
  int * dpivot;
  float * dWtR;
  int * drank;
  float * dV;
  float * dW; 
  float * dT; 
  float * du; 

  for(i=0; i<n; i++)
    for(j=0; j<p; j++)
      X[i + j*n] = i + j;

  printf("\n X \n");

  for(i=0; i<n; i++){
    for(j=0; j<p; j++){
      printf("%.f ", X[i + j*n]);
    }
    printf("\n");
  }
    
  
  hipMalloc( (void **)&dX, n*p*fbytes );
  hipMalloc( (void **)&dColNorms, p*fbytes);
  hipMalloc( (void **)&dscales, blockSize*fbytes);
  hipMalloc( (void **)&dBeta, blockSize*fbytes);
  hipMalloc( (void **)&dqrAux, p*fbytes);
  hipMalloc( (void **)&dpivot, p*sizeof(int));
  hipMalloc( (void **)&dWtR, blockSize*(p - blockSize)*fbytes);
  hipMalloc( (void **)&drank, sizeof(int));
  hipMalloc( (void **)&dV, blockSize*stride*fbytes);
  hipMalloc( (void **)&dW, blockSize*stride*fbytes);
  hipMalloc( (void **)&dT, blockSize*blockSize*fbytes);
  hipMalloc( (void **)&du, stride*fbytes);


  hipMemcpy( dX, X, n*p*fbytes, hipMemcpyHostToDevice);

  nblocks = p / nthreads;
  if(nblocks * nthreads < p)
      nblocks++;

  getColNorms<<<nblocks, nthreads>>>(n, p, dX, dColNorms);

  GetQRDecompBlocked<<<1,1>>>(n, p, dX, dColNorms, blockSize, stride, dscales, dBeta,
			      dqrAux, dpivot, dWtR, drank, dV, dW, dT, du);

  hipMemcpy( X, dX, n*p*fbytes, hipMemcpyDeviceToHost);

  printf("\n R \n");

  for(i=0; i<n; i++){
    for(j=0; j<p; j++){
      printf("%.f ", X[i + j*n]);
    }
    printf("\n");
  }

  hipFree(dX);
  hipFree(dColNorms);
  free(X);
  hipFree(dscales);
  hipFree(dBeta);
  hipFree(dqrAux);
  hipFree(dpivot);
  hipFree(dWtR);
  hipFree(drank);
  hipFree(dV);
  hipFree(dW);
  hipFree(dT);
  hipFree(du);

  return 0;

} 

	.text
	.file	"qrdecomp.hip"
	.globl	_Z26__device_stub__getColNormsiiPfS_ # -- Begin function _Z26__device_stub__getColNormsiiPfS_
	.type	_Z26__device_stub__getColNormsiiPfS_,@function
_Z26__device_stub__getColNormsiiPfS_:   # @_Z26__device_stub__getColNormsiiPfS_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	12(%rsp), %rax
	movl	%edi, (%rax)
	leaq	8(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z11getColNormsiiPfS_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z26__device_stub__getColNormsiiPfS_, .Lfunc_end0-_Z26__device_stub__getColNormsiiPfS_
	.cfi_endproc
                                        # -- End function
	.globl	_Z33__device_stub__GetQRDecompBlockediiPfS_jiS_S_S_PiS_S0_S_S_S_S_ # -- Begin function _Z33__device_stub__GetQRDecompBlockediiPfS_jiS_S_S_PiS_S0_S_S_S_S_
	.type	_Z33__device_stub__GetQRDecompBlockediiPfS_jiS_S_S_PiS_S0_S_S_S_S_,@function
_Z33__device_stub__GetQRDecompBlockediiPfS_jiS_S_S_PiS_S0_S_S_S_S_: # @_Z33__device_stub__GetQRDecompBlockediiPfS_jiS_S_S_PiS_S0_S_S_S_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$208, %rsp
	.cfi_def_cfa_offset 256
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	12(%rsp), %rax
	movl	%edi, (%rax)
	leaq	8(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	4(%rsp), %rcx
	movl	%r8d, (%rcx)
	movq	%rsp, %r8
	movl	%r9d, (%r8)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	256(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	264(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	272(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	280(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	288(%rsp), %rax
	movq	%rax, 80(%rbx)
	leaq	296(%rsp), %rax
	movq	%rax, 88(%rbx)
	leaq	304(%rsp), %rax
	movq	%rax, 96(%rbx)
	leaq	312(%rsp), %rax
	movq	%rax, 104(%rbx)
	leaq	320(%rsp), %rax
	movq	%rax, 112(%rbx)
	leaq	328(%rsp), %rax
	movq	%rax, 120(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z18GetQRDecompBlockediiPfS_jiS_S_S_PiS_S0_S_S_S_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$224, %rsp
	.cfi_adjust_cfa_offset -224
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z33__device_stub__GetQRDecompBlockediiPfS_jiS_S_S_PiS_S0_S_S_S_S_, .Lfunc_end1-_Z33__device_stub__GetQRDecompBlockediiPfS_jiS_S_S_PiS_S0_S_S_S_S_
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r12
	.cfi_def_cfa_offset 32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	subq	$104, %rsp
	.cfi_def_cfa_offset 144
	.cfi_offset %rbx, -40
	.cfi_offset %r12, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movl	$200, %edi
	callq	malloc
	movq	%rax, %rbx
	xorl	%eax, %eax
	movq	%rbx, %rcx
.LBB2_1:                                # %.preheader109
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB2_2 Depth 2
	movq	$-200, %rdx
	movl	%eax, %esi
.LBB2_2:                                #   Parent Loop BB2_1 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	xorps	%xmm0, %xmm0
	cvtsi2ss	%esi, %xmm0
	movss	%xmm0, 200(%rcx,%rdx)
	incl	%esi
	addq	$40, %rdx
	jne	.LBB2_2
# %bb.3:                                #   in Loop: Header=BB2_1 Depth=1
	incq	%rax
	addq	$4, %rcx
	cmpq	$10, %rax
	jne	.LBB2_1
# %bb.4:
	movl	$.Lstr, %edi
	callq	puts@PLT
	xorl	%r14d, %r14d
	movq	%rbx, %r15
.LBB2_5:                                # %.preheader108
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB2_6 Depth 2
	movq	$-200, %r12
.LBB2_6:                                #   Parent Loop BB2_5 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	xorps	%xmm0, %xmm0
	cvtss2sd	200(%r15,%r12), %xmm0
	movl	$.L.str.1, %edi
	movb	$1, %al
	callq	printf
	addq	$40, %r12
	jne	.LBB2_6
# %bb.7:                                #   in Loop: Header=BB2_5 Depth=1
	movl	$10, %edi
	callq	putchar@PLT
	incq	%r14
	addq	$4, %r15
	cmpq	$10, %r14
	jne	.LBB2_5
# %bb.8:
	movabsq	$4294967297, %r14               # imm = 0x100000001
	leaq	8(%rsp), %r15
	movl	$200, %esi
	movq	%r15, %rdi
	callq	hipMalloc
	leaq	16(%rsp), %rdi
	movl	$20, %esi
	callq	hipMalloc
	leaq	96(%rsp), %rdi
	movl	$512, %esi                      # imm = 0x200
	callq	hipMalloc
	leaq	88(%rsp), %rdi
	movl	$512, %esi                      # imm = 0x200
	callq	hipMalloc
	leaq	80(%rsp), %rdi
	movl	$20, %esi
	callq	hipMalloc
	leaq	72(%rsp), %rdi
	movl	$20, %esi
	callq	hipMalloc
	leaq	64(%rsp), %rdi
	movabsq	$17179806208, %rsi              # imm = 0x3FFFF0A00
	callq	hipMalloc
	leaq	56(%rsp), %rdi
	movl	$4, %esi
	callq	hipMalloc
	leaq	48(%rsp), %rdi
	movl	$65536, %esi                    # imm = 0x10000
	callq	hipMalloc
	leaq	40(%rsp), %rdi
	movl	$65536, %esi                    # imm = 0x10000
	callq	hipMalloc
	leaq	32(%rsp), %rdi
	movl	$65536, %esi                    # imm = 0x10000
	callq	hipMalloc
	leaq	24(%rsp), %rdi
	movl	$512, %esi                      # imm = 0x200
	callq	hipMalloc
	movq	(%r15), %rdi
	movl	$200, %edx
	movq	%rbx, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	511(%r14), %rdx
	movq	%r14, %rdi
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_10
# %bb.9:
	movq	8(%rsp), %rdx
	movq	16(%rsp), %rcx
	movl	$10, %edi
	movl	$5, %esi
	callq	_Z26__device_stub__getColNormsiiPfS_
.LBB2_10:
	movq	%r14, %rdi
	movl	$1, %esi
	movq	%r14, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_12
# %bb.11:
	movq	8(%rsp), %rdx
	movq	16(%rsp), %rcx
	movl	$10, %edi
	movl	$5, %esi
	movl	$128, %r8d
	movl	$128, %r9d
	pushq	24(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	40(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	56(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	72(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	88(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	104(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	120(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	136(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	152(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	168(%rsp)
	.cfi_adjust_cfa_offset 8
	callq	_Z33__device_stub__GetQRDecompBlockediiPfS_jiS_S_S_PiS_S0_S_S_S_S_
	addq	$80, %rsp
	.cfi_adjust_cfa_offset -80
.LBB2_12:
	movq	8(%rsp), %rsi
	movl	$200, %edx
	movq	%rbx, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movl	$.Lstr.1, %edi
	callq	puts@PLT
	xorl	%r14d, %r14d
	movq	%rbx, %r15
.LBB2_13:                               # %.preheader
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB2_14 Depth 2
	movq	$-200, %r12
.LBB2_14:                               #   Parent Loop BB2_13 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	xorps	%xmm0, %xmm0
	cvtss2sd	200(%r15,%r12), %xmm0
	movl	$.L.str.1, %edi
	movb	$1, %al
	callq	printf
	addq	$40, %r12
	jne	.LBB2_14
# %bb.15:                               #   in Loop: Header=BB2_13 Depth=1
	movl	$10, %edi
	callq	putchar@PLT
	incq	%r14
	addq	$4, %r15
	cmpq	$10, %r14
	jne	.LBB2_13
# %bb.16:
	movq	8(%rsp), %rdi
	callq	hipFree
	movq	16(%rsp), %rdi
	callq	hipFree
	movq	%rbx, %rdi
	callq	free
	movq	96(%rsp), %rdi
	callq	hipFree
	movq	88(%rsp), %rdi
	callq	hipFree
	movq	80(%rsp), %rdi
	callq	hipFree
	movq	72(%rsp), %rdi
	callq	hipFree
	movq	64(%rsp), %rdi
	callq	hipFree
	movq	56(%rsp), %rdi
	callq	hipFree
	movq	48(%rsp), %rdi
	callq	hipFree
	movq	40(%rsp), %rdi
	callq	hipFree
	movq	32(%rsp), %rdi
	callq	hipFree
	movq	24(%rsp), %rdi
	callq	hipFree
	xorl	%eax, %eax
	addq	$104, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	main, .Lfunc_end2-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB3_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB3_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z11getColNormsiiPfS_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z18GetQRDecompBlockediiPfS_jiS_S_S_PiS_S0_S_S_S_S_, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end3:
	.size	__hip_module_ctor, .Lfunc_end3-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB4_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB4_2:
	retq
.Lfunc_end4:
	.size	__hip_module_dtor, .Lfunc_end4-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z11getColNormsiiPfS_,@object   # @_Z11getColNormsiiPfS_
	.section	.rodata,"a",@progbits
	.globl	_Z11getColNormsiiPfS_
	.p2align	3, 0x0
_Z11getColNormsiiPfS_:
	.quad	_Z26__device_stub__getColNormsiiPfS_
	.size	_Z11getColNormsiiPfS_, 8

	.type	_Z18GetQRDecompBlockediiPfS_jiS_S_S_PiS_S0_S_S_S_S_,@object # @_Z18GetQRDecompBlockediiPfS_jiS_S_S_PiS_S0_S_S_S_S_
	.globl	_Z18GetQRDecompBlockediiPfS_jiS_S_S_PiS_S0_S_S_S_S_
	.p2align	3, 0x0
_Z18GetQRDecompBlockediiPfS_jiS_S_S_PiS_S0_S_S_S_S_:
	.quad	_Z33__device_stub__GetQRDecompBlockediiPfS_jiS_S_S_PiS_S0_S_S_S_S_
	.size	_Z18GetQRDecompBlockediiPfS_jiS_S_S_PiS_S0_S_S_S_S_, 8

	.type	.L.str.1,@object                # @.str.1
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str.1:
	.asciz	"%.f "
	.size	.L.str.1, 5

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z11getColNormsiiPfS_"
	.size	.L__unnamed_1, 22

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z18GetQRDecompBlockediiPfS_jiS_S_S_PiS_S0_S_S_S_S_"
	.size	.L__unnamed_2, 52

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.type	.Lstr,@object                   # @str
	.section	.rodata.str1.1,"aMS",@progbits,1
.Lstr:
	.asciz	"\n X "
	.size	.Lstr, 5

	.type	.Lstr.1,@object                 # @str.1
.Lstr.1:
	.asciz	"\n R "
	.size	.Lstr.1, 5

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z26__device_stub__getColNormsiiPfS_
	.addrsig_sym _Z33__device_stub__GetQRDecompBlockediiPfS_jiS_S_S_PiS_S0_S_S_S_S_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z11getColNormsiiPfS_
	.addrsig_sym _Z18GetQRDecompBlockediiPfS_jiS_S_S_PiS_S0_S_S_S_S_
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z11getColNormsiiPfS_   ; -- Begin function _Z11getColNormsiiPfS_
	.globl	_Z11getColNormsiiPfS_
	.p2align	8
	.type	_Z11getColNormsiiPfS_,@function
_Z11getColNormsiiPfS_:                  ; @_Z11getColNormsiiPfS_
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x24
	s_load_b64 s[4:5], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_i32_e64 s5, v1
	s_cbranch_execz .LBB0_6
; %bb.1:
	s_load_b128 s[0:3], s[0:1], 0x8
	s_cmp_lt_i32 s4, 1
	s_cbranch_scc1 .LBB0_4
; %bb.2:                                ; %.lr.ph.preheader
	v_mul_lo_u32 v2, v1, s4
	v_mov_b32_e32 v0, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s0, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
.LBB0_3:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	global_load_b32 v4, v[2:3], off
	v_add_co_u32 v2, vcc_lo, v2, 4
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
	s_add_i32 s4, s4, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s4, 0
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v0, v4, v4
	s_cbranch_scc0 .LBB0_3
	s_branch .LBB0_5
.LBB0_4:
	v_mov_b32_e32 v0, 0
.LBB0_5:                                ; %Flow34
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v2, 0x4f800000, v0
	v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v0
	v_cndmask_b32_e32 v3, v0, v2, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_sqrt_f32_e32 v0, v3
	s_waitcnt_depctr 0xfff
	v_add_nc_u32_e32 v2, -1, v0
	v_add_nc_u32_e32 v4, 1, v0
	v_fma_f32 v5, -v2, v0, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v6, -v4, v0, v3
	s_waitcnt lgkmcnt(0)
	v_cmp_ge_f32_e64 s0, 0, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v0, v0, v2, s0
	v_cmp_lt_f32_e64 s0, 0, v6
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v0, v0, v4, s0
	v_mul_f32_e32 v4, 0x37800000, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e32 v4, v0, v4, vcc_lo
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	v_cmp_class_f32_e64 vcc_lo, v3, 0x260
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v2, v4, v3, vcc_lo
	v_add_co_u32 v0, vcc_lo, s2, v0
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
	global_store_b32 v[0:1], v2, off
.LBB0_6:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z11getColNormsiiPfS_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 7
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z11getColNormsiiPfS_, .Lfunc_end0-_Z11getColNormsiiPfS_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 368
; NumSgprs: 18
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z18GetQRDecompBlockediiPfS_jiS_S_S_PiS_S0_S_S_S_S_ ; -- Begin function _Z18GetQRDecompBlockediiPfS_jiS_S_S_PiS_S0_S_S_S_S_
	.globl	_Z18GetQRDecompBlockediiPfS_jiS_S_S_PiS_S0_S_S_S_S_
	.p2align	8
	.type	_Z18GetQRDecompBlockediiPfS_jiS_S_S_PiS_S0_S_S_S_S_,@function
_Z18GetQRDecompBlockediiPfS_jiS_S_S_PiS_S0_S_S_S_S_: ; @_Z18GetQRDecompBlockediiPfS_jiS_S_S_PiS_S0_S_S_S_S_
; %bb.0:
	s_clause 0x1
	s_load_b64 s[2:3], s[0:1], 0x0
	s_load_b128 s[20:23], s[0:1], 0x8
	s_mov_b64 s[4:5], 0
	s_waitcnt lgkmcnt(0)
	s_cmp_lt_i32 s3, 2
	s_cbranch_scc1 .LBB1_7
; %bb.1:                                ; %.lr.ph.i
	s_load_b32 s8, s[22:23], 0x0
	s_lshl_b32 s4, -1, s3
	s_mov_b32 s9, 1
	s_and_not1_b32 s5, 0x7ffffffe, s4
	s_add_u32 s6, s22, 4
	s_addc_u32 s7, s23, 0
	s_mov_b32 s4, 0
.LBB1_2:                                ; =>This Inner Loop Header: Depth=1
	s_lshl_b32 s10, 1, s9
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s10, s10, s5
	s_cmp_lg_u32 s10, 2
	s_cbranch_scc1 .LBB1_5
; %bb.3:                                ;   in Loop: Header=BB1_2 Depth=1
	s_load_b32 s10, s[6:7], 0x0
	s_waitcnt lgkmcnt(0)
	v_cmp_ngt_f32_e64 s11, s10, s8
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 vcc_lo, exec_lo, s11
	s_cbranch_vccnz .LBB1_5
; %bb.4:                                ;   in Loop: Header=BB1_2 Depth=1
	s_mov_b32 s4, s9
	s_mov_b32 s8, s10
.LBB1_5:                                ;   in Loop: Header=BB1_2 Depth=1
	s_add_i32 s9, s9, 1
	s_add_u32 s6, s6, 4
	s_addc_u32 s7, s7, 0
	s_cmp_lg_u32 s3, s9
	s_cbranch_scc1 .LBB1_2
; %bb.6:                                ; %_Z9getMaxIdxiPfi.exit.loopexit
	s_ashr_i32 s5, s4, 31
.LBB1_7:                                ; %_Z9getMaxIdxiPfi.exit
	s_delay_alu instid0(SALU_CYCLE_1)
	s_lshl_b64 s[4:5], s[4:5], 2
	s_mov_b32 s74, 0
	s_add_u32 s4, s22, s4
	s_addc_u32 s5, s23, s5
	s_load_b32 s4, s[4:5], 0x0
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_f32_e64 s5, 0x38d1b717, s4
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 vcc_lo, exec_lo, s5
	s_cbranch_vccnz .LBB1_9
; %bb.8:
	v_cvt_f64_f32_e32 v[0:1], s4
	s_brev_b32 s4, 7
	s_mov_b32 s5, 0x3f1a36e2
	s_min_i32 s33, s2, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[0:1], v[0:1], 1.0
	v_mul_f64 v[0:1], v[0:1], s[4:5]
	s_delay_alu instid0(VALU_DEP_1)
	v_cvt_f32_f64_e32 v2, v[0:1]
	s_branch .LBB1_10
.LBB1_9:
	s_mov_b32 s33, 0
                                        ; implicit-def: $vgpr2
.LBB1_10:
	s_load_b64 s[28:29], s[0:1], 0x18
	s_add_i32 s30, s3, -1
	s_waitcnt lgkmcnt(0)
	v_cvt_f32_u32_e32 v0, s28
	s_sub_i32 s5, 0, s28
	s_add_i32 s24, s30, s28
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v0, v0
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v0, 0x4f7ffffe, v0
	v_cvt_u32_f32_e32 v0, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s4, v0
	s_mul_i32 s5, s5, s4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_hi_u32 s5, s4, s5
	s_add_i32 s25, s4, s5
	s_load_b512 s[4:19], s[0:1], 0x20
	s_mul_hi_u32 s25, s24, s25
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s26, s25, s28
	s_sub_i32 s24, s24, s26
	s_add_i32 s26, s25, 1
	s_sub_i32 s27, s24, s28
	s_cmp_ge_u32 s24, s28
	s_cselect_b32 s25, s26, s25
	s_cselect_b32 s24, s27, s24
	s_add_i32 s26, s25, 1
	s_cmp_ge_u32 s24, s28
	s_cselect_b32 s72, s26, s25
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lt_i32 s72, 1
	s_cbranch_scc1 .LBB1_102
; %bb.11:                               ; %.preheader365.lr.ph
	v_cvt_f64_u32_e32 v[0:1], s28
	s_add_i32 s73, s2, -1
	s_cmp_gt_i32 s29, 0
	s_load_b128 s[24:27], s[0:1], 0x60
	s_cselect_b32 s31, -1, 0
	s_cmp_lg_u32 s28, 0
	s_mov_b32 s36, s2
	s_cselect_b32 s75, -1, 0
	s_add_i32 s76, s72, -1
	s_cmp_gt_i32 s28, 0
	s_mul_i32 s0, s29, s28
	s_cselect_b32 s77, -1, 0
	s_ashr_i32 s37, s2, 31
	s_add_i32 s40, s0, s28
	s_lshl_b64 s[36:37], s[36:37], 2
	s_mov_b32 s35, 0
	s_waitcnt lgkmcnt(0)
	s_add_u32 s36, s8, s36
	s_addc_u32 s37, s9, s37
	s_ashr_i32 s39, s29, 31
	s_mov_b32 s38, s29
	s_mov_b32 s41, s35
	s_lshl_b64 s[38:39], s[38:39], 2
	s_mov_b32 s1, s35
	s_lshl_b64 s[40:41], s[40:41], 2
	s_mov_b32 s34, s28
	s_add_u32 s78, s38, 4
	s_addc_u32 s79, s39, 0
	s_lshl_b64 s[42:43], s[0:1], 2
	v_mov_b32_e32 v3, 0
	v_cndmask_b32_e64 v4, 0, 1, s75
	s_lshl_b64 s[44:45], s[34:35], 2
	s_add_u32 s80, s20, s42
	s_addc_u32 s81, s21, s43
	s_xor_b32 s82, s31, -1
	s_mov_b64 s[46:47], s[20:21]
	s_mov_b32 s85, s3
	s_mov_b32 s83, 0
	s_mov_b32 s48, s29
	v_max_f64 v[0:1], v[0:1], v[0:1]
                                        ; implicit-def: $sgpr50
.LBB1_12:                               ; %.preheader365
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB1_14 Depth 2
                                        ;       Child Loop BB1_16 Depth 3
                                        ;         Child Loop BB1_18 Depth 4
                                        ;     Child Loop BB1_25 Depth 2
                                        ;       Child Loop BB1_27 Depth 3
                                        ;     Child Loop BB1_31 Depth 2
                                        ;       Child Loop BB1_33 Depth 3
                                        ;       Child Loop BB1_37 Depth 3
                                        ;       Child Loop BB1_40 Depth 3
                                        ;         Child Loop BB1_42 Depth 4
                                        ;       Child Loop BB1_47 Depth 3
                                        ;         Child Loop BB1_49 Depth 4
                                        ;     Child Loop BB1_58 Depth 2
                                        ;       Child Loop BB1_59 Depth 3
                                        ;         Child Loop BB1_61 Depth 4
                                        ;     Child Loop BB1_67 Depth 2
                                        ;       Child Loop BB1_69 Depth 3
                                        ;       Child Loop BB1_72 Depth 3
                                        ;         Child Loop BB1_73 Depth 4
                                        ;     Child Loop BB1_77 Depth 2
                                        ;       Child Loop BB1_79 Depth 3
                                        ;         Child Loop BB1_81 Depth 4
                                        ;     Child Loop BB1_87 Depth 2
                                        ;       Child Loop BB1_89 Depth 3
                                        ;         Child Loop BB1_91 Depth 4
                                        ;     Child Loop BB1_96 Depth 2
                                        ;       Child Loop BB1_98 Depth 3
	s_add_i32 s2, s50, s28
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
	s_cmp_ge_u32 s50, s2
	s_cselect_b32 s0, -1, 0
	s_cmp_ge_i32 s50, s33
	s_cselect_b32 s1, -1, 0
	s_or_b32 s0, s0, s1
	s_cmp_gt_i32 s50, s30
	s_cselect_b32 s1, -1, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s0, s0, s1
	s_and_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccnz .LBB1_22
; %bb.13:                               ; %.lr.ph376.preheader
                                        ;   in Loop: Header=BB1_12 Depth=1
	s_mul_i32 s0, s29, s50
	s_mov_b32 s84, 0
	s_sub_i32 s34, 0, s50
	s_mov_b32 s1, s50
.LBB1_14:                               ; %.lr.ph376
                                        ;   Parent Loop BB1_12 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB1_16 Depth 3
                                        ;         Child Loop BB1_18 Depth 4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_ashr_i32 s53, s1, 31
	s_mov_b32 s52, s1
	s_lshl_b64 s[58:59], s[52:53], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s54, s22, s58
	s_addc_u32 s55, s23, s59
	s_cmp_gt_i32 s30, s1
	global_load_b32 v5, v3, s[54:55]
	s_cselect_b32 s1, -1, 0
	s_waitcnt vmcnt(0)
	v_cmp_lt_f32_e32 vcc_lo, v5, v2
	s_and_b32 s1, vcc_lo, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB1_21
; %bb.15:                               ; %.lr.ph
                                        ;   in Loop: Header=BB1_14 Depth=2
	s_ashr_i32 s1, s0, 31
	s_mul_i32 s60, s30, s52
	s_lshl_b64 s[56:57], s[0:1], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s56, s20, s56
	s_addc_u32 s57, s21, s57
	s_add_u32 s58, s10, s58
	s_addc_u32 s59, s11, s59
.LBB1_16:                               ;   Parent Loop BB1_12 Depth=1
                                        ;     Parent Loop BB1_14 Depth=2
                                        ; =>    This Loop Header: Depth=3
                                        ;         Child Loop BB1_18 Depth 4
	s_ashr_i32 s31, s30, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[62:63], s[30:31], 2
	s_add_u32 s62, s10, s62
	s_addc_u32 s63, s11, s63
	s_cmp_gt_i32 s30, s3
	global_load_b32 v6, v3, s[62:63]
	s_cselect_b32 s1, -1, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s1, s82, s1
	s_and_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB1_20
; %bb.17:                               ; %.lr.ph.i331.preheader
                                        ;   in Loop: Header=BB1_16 Depth=3
	s_ashr_i32 s61, s60, 31
	s_mov_b64 s[64:65], s[56:57]
	s_lshl_b64 s[66:67], s[60:61], 2
	s_mov_b32 s1, s29
	s_add_u32 s66, s20, s66
	s_addc_u32 s67, s21, s67
.LBB1_18:                               ; %.lr.ph.i331
                                        ;   Parent Loop BB1_12 Depth=1
                                        ;     Parent Loop BB1_14 Depth=2
                                        ;       Parent Loop BB1_16 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	s_clause 0x1
	global_load_b32 v5, v3, s[66:67]
	global_load_b32 v7, v3, s[64:65]
	s_add_i32 s1, s1, -1
	s_waitcnt vmcnt(1)
	global_store_b32 v3, v5, s[64:65]
	s_waitcnt vmcnt(0)
	global_store_b32 v3, v7, s[66:67]
	s_add_u32 s64, s64, 4
	s_addc_u32 s65, s65, 0
	s_add_u32 s66, s66, 4
	s_addc_u32 s67, s67, 0
	s_cmp_lg_u32 s1, 0
	s_cbranch_scc1 .LBB1_18
; %bb.19:                               ; %_Z7colswapPfiiii.exit.loopexit
                                        ;   in Loop: Header=BB1_16 Depth=3
	global_load_b32 v5, v3, s[54:55]
.LBB1_20:                               ; %_Z7colswapPfiiii.exit
                                        ;   in Loop: Header=BB1_16 Depth=3
	global_load_b32 v7, v3, s[58:59]
	s_add_i32 s30, s30, -1
	s_waitcnt vmcnt(1)
	v_cmp_lt_f32_e32 vcc_lo, v5, v2
	s_cmp_gt_i32 s30, s52
	s_waitcnt vmcnt(0)
	s_clause 0x1
	global_store_b32 v3, v7, s[62:63]
	global_store_b32 v3, v6, s[58:59]
	s_cselect_b32 s1, -1, 0
	s_add_i32 s60, s60, s34
	s_and_b32 s1, vcc_lo, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB1_16
.LBB1_21:                               ; %._crit_edge
                                        ;   in Loop: Header=BB1_14 Depth=2
	v_cmp_ge_f32_e32 vcc_lo, v5, v2
	s_cmp_lg_u32 vcc_lo, 0
	s_addc_u32 s84, s84, 0
	s_add_i32 s1, s52, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_ge_u32 s1, s2
	s_cselect_b32 s31, -1, 0
	s_cmp_ge_i32 s1, s33
	s_cselect_b32 s49, -1, 0
	s_cmp_ge_i32 s52, s30
	s_cselect_b32 s51, -1, 0
	s_add_i32 s0, s0, s29
	s_or_b32 s49, s49, s51
	s_add_i32 s34, s34, -1
	s_or_b32 s31, s49, s31
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s31
	s_cbranch_vccnz .LBB1_14
	s_branch .LBB1_23
.LBB1_22:                               ;   in Loop: Header=BB1_12 Depth=1
	s_mov_b32 s84, s35
.LBB1_23:                               ; %.critedge
                                        ;   in Loop: Header=BB1_12 Depth=1
	s_cmp_gt_i32 s48, 0
	v_cmp_ne_u32_e64 s0, 1, v4
	s_cselect_b32 s1, -1, 0
	s_and_not1_b32 vcc_lo, exec_lo, s75
	v_cndmask_b32_e64 v5, 0, 1, s1
	s_cbranch_vccnz .LBB1_29
; %bb.24:                               ; %.preheader360.preheader
                                        ;   in Loop: Header=BB1_12 Depth=1
	s_mov_b32 s34, 0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s2, s34
.LBB1_25:                               ; %.preheader360
                                        ;   Parent Loop BB1_12 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB1_27 Depth 3
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB1_28
; %bb.26:                               ; %.lr.ph380
                                        ;   in Loop: Header=BB1_25 Depth=2
	s_lshl_b64 s[52:53], s[34:35], 2
	s_mov_b32 s31, 0
	s_add_u32 s52, s16, s52
	s_addc_u32 s53, s17, s53
.LBB1_27:                               ;   Parent Loop BB1_12 Depth=1
                                        ;     Parent Loop BB1_25 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_add_i32 s31, s31, 1
	global_store_b32 v3, v3, s[52:53]
	s_add_u32 s52, s52, 4
	s_addc_u32 s53, s53, 0
	s_cmp_lt_i32 s31, s48
	s_cbranch_scc1 .LBB1_27
.LBB1_28:                               ; %._crit_edge381
                                        ;   in Loop: Header=BB1_25 Depth=2
	s_add_i32 s2, s2, 1
	s_add_i32 s34, s34, s48
	s_cmp_eq_u32 s2, s28
	s_cbranch_scc0 .LBB1_25
.LBB1_29:                               ; %.preheader364
                                        ;   in Loop: Header=BB1_12 Depth=1
	s_ashr_i32 s49, s48, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[52:53], s[48:49], 2
	s_add_u32 s31, s52, 4
	s_addc_u32 s49, s53, 0
	s_cmp_lg_u32 s84, 0
	s_cselect_b32 s86, -1, 0
	s_cmp_eq_u32 s84, 0
	s_cbranch_scc1 .LBB1_55
; %bb.30:                               ; %.lr.ph393
                                        ;   in Loop: Header=BB1_12 Depth=1
	v_cvt_f64_i32_e32 v[6:7], s85
	s_mov_b32 s54, 0
	s_mov_b64 s[56:57], s[16:17]
	s_mov_b64 s[58:59], s[52:53]
	s_mov_b64 s[60:61], s[16:17]
	s_mov_b64 s[62:63], s[46:47]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_min_f64 v[6:7], v[0:1], v[6:7]
	v_cvt_i32_f64_e32 v6, v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cmp_lt_i32_e64 s1, 0, v6
	v_readfirstlane_b32 s87, v6
	v_cndmask_b32_e64 v6, 0, 1, s1
.LBB1_31:                               ;   Parent Loop BB1_12 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB1_33 Depth 3
                                        ;       Child Loop BB1_37 Depth 3
                                        ;       Child Loop BB1_40 Depth 3
                                        ;         Child Loop BB1_42 Depth 4
                                        ;       Child Loop BB1_47 Depth 3
                                        ;         Child Loop BB1_49 Depth 4
	s_cmp_eq_u32 s48, s54
	s_cbranch_scc1 .LBB1_34
; %bb.32:                               ; %.lr.ph.i.i.preheader
                                        ;   in Loop: Header=BB1_31 Depth=2
	s_mov_b64 s[64:65], 0
.LBB1_33:                               ; %.lr.ph.i.i
                                        ;   Parent Loop BB1_12 Depth=1
                                        ;     Parent Loop BB1_31 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s66, s62, s64
	s_addc_u32 s67, s63, s65
	s_add_u32 s68, s60, s64
	global_load_u8 v7, v3, s[66:67]
	s_addc_u32 s69, s61, s65
	s_add_u32 s64, s64, 4
	s_addc_u32 s65, s65, 0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u64 s[58:59], s[64:65]
	s_waitcnt vmcnt(0)
	global_store_b8 v3, v7, s[68:69]
	global_load_u8 v7, v3, s[66:67] offset:1
	s_waitcnt vmcnt(0)
	global_store_b8 v3, v7, s[68:69] offset:1
	global_load_u8 v7, v3, s[66:67] offset:2
	s_waitcnt vmcnt(0)
	global_store_b8 v3, v7, s[68:69] offset:2
	global_load_u8 v7, v3, s[66:67] offset:3
	s_waitcnt vmcnt(0)
	global_store_b8 v3, v7, s[68:69] offset:3
	s_cbranch_scc1 .LBB1_33
.LBB1_34:                               ; %._crit_edge.i.i
                                        ;   in Loop: Header=BB1_31 Depth=2
	global_load_b32 v8, v3, s[60:61]
	s_cmp_eq_u32 s50, s73
	s_mov_b32 s2, -1
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v7, 0x7fffffff, v8
	s_cbranch_scc1 .LBB1_52
; %bb.35:                               ; %.preheader359
                                        ;   in Loop: Header=BB1_31 Depth=2
	v_mov_b32_e32 v9, 0
	s_sub_i32 s2, s48, s54
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lt_i32 s2, 1
	s_cbranch_scc1 .LBB1_38
; %bb.36:                               ; %.lr.ph385.preheader
                                        ;   in Loop: Header=BB1_31 Depth=2
	s_mov_b32 s34, 0
	s_mov_b64 s[64:65], s[60:61]
.LBB1_37:                               ; %.lr.ph385
                                        ;   Parent Loop BB1_12 Depth=1
                                        ;     Parent Loop BB1_31 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	global_load_b32 v10, v3, s[64:65]
	s_add_i32 s34, s34, 1
	s_add_u32 s64, s64, 4
	s_addc_u32 s65, s65, 0
	s_cmp_lt_i32 s34, s2
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v9, v10, v10
	s_cbranch_scc1 .LBB1_37
.LBB1_38:                               ; %._crit_edge386
                                        ;   in Loop: Header=BB1_31 Depth=2
	s_delay_alu instid0(VALU_DEP_1)
	v_mul_f32_e32 v10, 0x4f800000, v9
	v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v9
	s_ashr_i32 s51, s50, 31
	s_mov_b32 s55, s35
	s_lshl_b64 s[64:65], s[50:51], 2
	v_cndmask_b32_e32 v9, v9, v10, vcc_lo
	s_add_u32 s64, s8, s64
	s_addc_u32 s65, s9, s65
	s_lshl_b64 s[66:67], s[54:55], 2
	s_delay_alu instid0(VALU_DEP_1)
	v_sqrt_f32_e32 v10, v9
	s_add_u32 s68, s4, s66
	s_addc_u32 s69, s5, s67
	s_waitcnt_depctr 0xfff
	v_add_nc_u32_e32 v11, -1, v10
	v_add_nc_u32_e32 v12, 1, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v13, -v11, v10, v9
	v_fma_f32 v14, -v12, v10, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_ge_f32_e64 s2, 0, v13
	v_cndmask_b32_e64 v10, v10, v11, s2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_f32_e64 s2, 0, v14
	v_cndmask_b32_e64 v10, v10, v12, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v11, 0x37800000, v10
	v_cndmask_b32_e32 v10, v10, v11, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v9, 0x260
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v17, v10, v9, vcc_lo
	v_div_scale_f32 v9, null, v17, v17, 1.0
	v_div_scale_f32 v10, null, v7, v7, v17
	v_div_scale_f32 v15, vcc_lo, 1.0, v17, 1.0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rcp_f32_e32 v11, v9
	v_rcp_f32_e32 v12, v10
	s_waitcnt_depctr 0xfff
	v_fma_f32 v13, -v9, v11, 1.0
	v_fma_f32 v14, -v10, v12, 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v11, v13, v11
	v_div_scale_f32 v13, s2, v17, v7, v17
	v_fmac_f32_e32 v12, v14, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v14, v15, v11
	v_mul_f32_e32 v16, v13, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v18, -v9, v14, v15
	v_fma_f32 v19, -v10, v16, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v14, v18, v11
	v_fmac_f32_e32 v16, v19, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_fma_f32 v10, -v10, v16, v13
	v_mul_f32_e32 v13, v17, v17
	v_fma_f32 v9, -v9, v14, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_div_fmas_f32 v18, v9, v11, v14
	s_mov_b32 vcc_lo, s2
	v_cvt_f64_f32_e32 v[13:14], v13
	v_div_fmas_f32 v9, v10, v12, v16
	v_cvt_f64_f32_e32 v[11:12], v7
	v_cmp_le_f32_e32 vcc_lo, 0, v8
	v_cmp_ne_u32_e64 s2, 1, v6
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_fixup_f32 v9, v9, |v8|, v17
	v_div_fixup_f32 v17, v18, v17, 1.0
	v_add_f32_e32 v19, 1.0, v9
	s_delay_alu instid0(VALU_DEP_2)
	v_fma_f32 v18, |v8|, v17, 1.0
	v_cndmask_b32_e64 v8, -v17, v17, vcc_lo
	s_clause 0x1
	global_store_b32 v3, v18, s[64:65]
	global_store_b32 v3, v8, s[68:69]
	v_mul_f32_e32 v9, v19, v19
	global_load_b32 v20, v3, s[60:61]
	s_add_u32 s64, s6, s66
	s_addc_u32 s65, s7, s67
	v_cvt_f64_f32_e32 v[9:10], v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[9:10], v[9:10], -1.0
	v_fma_f64 v[9:10], v[9:10], v[11:12], v[13:14]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_scale_f64 v[11:12], null, v[9:10], v[9:10], -2.0
	v_rcp_f64_e32 v[13:14], v[11:12]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[15:16], -v[11:12], v[13:14], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[13:14], v[13:14], v[15:16], v[13:14]
	v_fma_f64 v[15:16], -v[11:12], v[13:14], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f64 v[13:14], v[13:14], v[15:16], v[13:14]
	v_div_scale_f64 v[15:16], vcc_lo, -2.0, v[9:10], -2.0
	v_mul_f64 v[17:18], v[15:16], v[13:14]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[11:12], -v[11:12], v[17:18], v[15:16]
	v_div_fmas_f64 v[11:12], v[11:12], v[13:14], v[17:18]
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f64 v[8:9], v[11:12], v[9:10], -2.0
	v_cvt_f32_f64_e32 v8, v[8:9]
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v9, v19, v20
	s_clause 0x1
	global_store_b32 v3, v9, s[60:61]
	global_store_b32 v3, v8, s[64:65]
	s_cbranch_vccnz .LBB1_45
; %bb.39:                               ; %.preheader.i.preheader
                                        ;   in Loop: Header=BB1_31 Depth=2
	s_mov_b32 s64, 0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s34, s64
.LBB1_40:                               ; %.preheader.i
                                        ;   Parent Loop BB1_12 Depth=1
                                        ;     Parent Loop BB1_31 Depth=2
                                        ; =>    This Loop Header: Depth=3
                                        ;         Child Loop BB1_42 Depth 4
	v_cmp_ne_u32_e32 vcc_lo, 1, v5
	s_cbranch_vccnz .LBB1_43
; %bb.41:                               ; %.lr.ph.i334
                                        ;   in Loop: Header=BB1_40 Depth=3
	s_ashr_i32 s65, s64, 31
	v_mov_b32_e32 v9, 0
	s_lshl_b64 s[68:69], s[64:65], 2
	s_mov_b64 s[66:67], 0
	s_add_u32 s51, s46, s68
	s_addc_u32 s55, s47, s69
	s_mov_b32 s65, s48
.LBB1_42:                               ;   Parent Loop BB1_12 Depth=1
                                        ;     Parent Loop BB1_31 Depth=2
                                        ;       Parent Loop BB1_40 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	s_add_u32 s68, s51, s66
	s_addc_u32 s69, s55, s67
	s_add_u32 s70, s56, s66
	s_addc_u32 s71, s57, s67
	s_clause 0x1
	global_load_b32 v10, v3, s[68:69]
	global_load_b32 v11, v3, s[70:71]
	s_add_i32 s65, s65, -1
	s_add_u32 s66, s66, 4
	s_addc_u32 s67, s67, 0
	s_cmp_lg_u32 s65, 0
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v9, v10, v11
	s_cbranch_scc1 .LBB1_42
	s_branch .LBB1_44
.LBB1_43:                               ;   in Loop: Header=BB1_40 Depth=3
	v_mov_b32_e32 v9, 0
.LBB1_44:                               ; %._crit_edge.i
                                        ;   in Loop: Header=BB1_40 Depth=3
	s_lshl_b64 s[66:67], s[34:35], 2
	s_delay_alu instid0(VALU_DEP_1)
	v_mul_f32_e32 v9, v9, v8
	s_add_u32 s66, s26, s66
	s_addc_u32 s67, s27, s67
	s_add_i32 s34, s34, 1
	s_add_i32 s64, s64, s29
	s_cmp_lg_u32 s34, s87
	global_store_b32 v3, v9, s[66:67]
	s_cbranch_scc1 .LBB1_40
.LBB1_45:                               ; %_Z4cXtvfiiPfiS_S_.exit
                                        ;   in Loop: Header=BB1_31 Depth=2
	v_cmp_ne_u32_e32 vcc_lo, 1, v5
	s_cbranch_vccnz .LBB1_51
; %bb.46:                               ; %.preheader.i337.preheader
                                        ;   in Loop: Header=BB1_31 Depth=2
	s_mov_b32 s34, 0
	s_mov_b64 s[64:65], s[46:47]
.LBB1_47:                               ; %.preheader.i337
                                        ;   Parent Loop BB1_12 Depth=1
                                        ;     Parent Loop BB1_31 Depth=2
                                        ; =>    This Loop Header: Depth=3
                                        ;         Child Loop BB1_49 Depth 4
	s_and_b32 vcc_lo, exec_lo, s2
	s_cbranch_vccnz .LBB1_50
; %bb.48:                               ; %.lr.ph.i339
                                        ;   in Loop: Header=BB1_47 Depth=3
	s_lshl_b64 s[68:69], s[34:35], 2
	s_mov_b64 s[66:67], s[26:27]
	s_add_u32 s68, s56, s68
	s_addc_u32 s69, s57, s69
	s_mov_b64 s[70:71], s[64:65]
	s_mov_b32 s51, s87
.LBB1_49:                               ;   Parent Loop BB1_12 Depth=1
                                        ;     Parent Loop BB1_31 Depth=2
                                        ;       Parent Loop BB1_47 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	s_clause 0x2
	global_load_b32 v8, v3, s[68:69]
	global_load_b32 v9, v3, s[66:67]
	global_load_b32 v10, v3, s[70:71]
	s_add_i32 s51, s51, -1
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v10, v8, v9
	global_store_b32 v3, v10, s[70:71]
	s_add_u32 s70, s70, s38
	s_addc_u32 s71, s71, s39
	s_add_u32 s66, s66, 4
	s_addc_u32 s67, s67, 0
	s_cmp_lg_u32 s51, 0
	s_cbranch_scc1 .LBB1_49
.LBB1_50:                               ; %._crit_edge.i338
                                        ;   in Loop: Header=BB1_47 Depth=3
	s_add_i32 s34, s34, 1
	s_add_u32 s64, s64, 4
	s_addc_u32 s65, s65, 0
	s_cmp_lg_u32 s34, s48
	s_cbranch_scc1 .LBB1_47
.LBB1_51:                               ; %Flow711
                                        ;   in Loop: Header=BB1_31 Depth=2
	s_mov_b32 s2, 0
.LBB1_52:                               ; %Flow718
                                        ;   in Loop: Header=BB1_31 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s2
	s_cbranch_vccz .LBB1_54
; %bb.53:                               ;   in Loop: Header=BB1_31 Depth=2
	global_store_b32 v3, v7, s[36:37] offset:-4
.LBB1_54:                               ; %_Z5XpvutiiPfiS_S_.exit
                                        ;   in Loop: Header=BB1_31 Depth=2
	s_add_u32 s56, s56, s52
	s_addc_u32 s57, s57, s53
	s_add_u32 s60, s60, s31
	s_addc_u32 s61, s61, s49
	s_add_i32 s50, s50, 1
	s_add_i32 s54, s54, 1
	s_add_u32 s62, s62, s78
	s_addc_u32 s63, s63, s79
	s_add_u32 s58, s58, -4
	s_addc_u32 s59, s59, -1
	s_cmp_lg_u32 s54, s84
	s_cbranch_scc1 .LBB1_31
.LBB1_55:                               ; %._crit_edge394
                                        ;   in Loop: Header=BB1_12 Depth=1
	s_sub_i32 s2, s85, s28
	s_cmp_lt_i32 s83, s76
	s_cselect_b32 s1, -1, 0
	s_cmp_lg_u32 s84, 0
	s_cselect_b32 s34, -1, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s1, s1, s34
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB1_94
; %bb.56:                               ;   in Loop: Header=BB1_12 Depth=1
	s_and_not1_b32 vcc_lo, exec_lo, s77
	s_cbranch_vccnz .LBB1_65
; %bb.57:                               ; %.preheader27.i.preheader
                                        ;   in Loop: Header=BB1_12 Depth=1
	s_mov_b32 s54, 0
	s_mov_b32 s1, 0
.LBB1_58:                               ; %.preheader27.i
                                        ;   Parent Loop BB1_12 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB1_59 Depth 3
                                        ;         Child Loop BB1_61 Depth 4
	s_ashr_i32 s55, s54, 31
	s_mov_b32 s56, 0
	s_lshl_b64 s[58:59], s[54:55], 2
	s_mov_b32 s51, 0
	s_add_u32 s58, s16, s58
	s_addc_u32 s59, s17, s59
.LBB1_59:                               ; %.preheader.i341
                                        ;   Parent Loop BB1_12 Depth=1
                                        ;     Parent Loop BB1_58 Depth=2
                                        ; =>    This Loop Header: Depth=3
                                        ;         Child Loop BB1_61 Depth 4
	s_min_i32 s34, s1, s51
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s34, 0
	s_cbranch_scc1 .LBB1_62
; %bb.60:                               ; %.lr.ph.i343
                                        ;   in Loop: Header=BB1_59 Depth=3
	s_ashr_i32 s57, s56, 31
	v_mov_b32_e32 v6, 0
	s_lshl_b64 s[60:61], s[56:57], 2
	s_mov_b64 s[62:63], s[58:59]
	s_add_u32 s60, s16, s60
	s_addc_u32 s61, s17, s61
.LBB1_61:                               ;   Parent Loop BB1_12 Depth=1
                                        ;     Parent Loop BB1_58 Depth=2
                                        ;       Parent Loop BB1_59 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	s_clause 0x1
	global_load_b32 v7, v3, s[62:63]
	global_load_b32 v8, v3, s[60:61]
	s_add_i32 s34, s34, -1
	s_add_u32 s60, s60, 4
	s_addc_u32 s61, s61, 0
	s_add_u32 s62, s62, 4
	s_addc_u32 s63, s63, 0
	s_cmp_lg_u32 s34, 0
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v6, v7, v8
	s_cbranch_scc1 .LBB1_61
	s_branch .LBB1_63
.LBB1_62:                               ;   in Loop: Header=BB1_59 Depth=3
	v_mov_b32_e32 v6, 0
.LBB1_63:                               ; %._crit_edge.i345
                                        ;   in Loop: Header=BB1_59 Depth=3
	s_mul_i32 s34, s51, s28
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s34, s34, s1
	s_lshl_b64 s[60:61], s[34:35], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s60, s24, s60
	s_addc_u32 s61, s25, s61
	s_add_i32 s51, s51, 1
	s_add_i32 s56, s56, s48
	s_cmp_lg_u32 s51, s28
	global_store_b32 v3, v6, s[60:61]
	s_cbranch_scc1 .LBB1_59
; %bb.64:                               ; %._crit_edge31.i
                                        ;   in Loop: Header=BB1_58 Depth=2
	s_add_i32 s1, s1, 1
	s_add_i32 s54, s54, s48
	s_cmp_lg_u32 s1, s28
	s_cbranch_scc1 .LBB1_58
.LBB1_65:                               ; %_Z4uVtViiPfS_.exit
                                        ;   in Loop: Header=BB1_12 Depth=1
	s_and_b32 vcc_lo, exec_lo, s0
	s_max_u32 s51, s2, 1
	s_cbranch_vccnz .LBB1_85
; %bb.66:                               ; %.preheader358.lr.ph
                                        ;   in Loop: Header=BB1_12 Depth=1
	s_cmp_lt_i32 s48, 1
	s_mov_b32 s54, 0
	s_mov_b64 s[56:57], 0
	s_cselect_b32 s68, -1, 0
	s_mov_b64 s[58:59], s[24:25]
	s_mov_b64 s[60:61], s[18:19]
	s_mov_b64 s[62:63], s[16:17]
.LBB1_67:                               ; %.preheader358
                                        ;   Parent Loop BB1_12 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB1_69 Depth 3
                                        ;       Child Loop BB1_72 Depth 3
                                        ;         Child Loop BB1_73 Depth 4
	v_cmp_ne_u32_e64 s1, 1, v5
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB1_70
; %bb.68:                               ; %.lr.ph397
                                        ;   in Loop: Header=BB1_67 Depth=2
	s_mov_b32 s55, s35
	s_mov_b32 s34, 0
	s_lshl_b64 s[64:65], s[54:55], 2
	s_mov_b64 s[66:67], 0
	s_add_u32 s64, s6, s64
	s_addc_u32 s65, s7, s65
.LBB1_69:                               ;   Parent Loop BB1_12 Depth=1
                                        ;     Parent Loop BB1_67 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_add_u32 s70, s62, s66
	s_addc_u32 s71, s63, s67
	s_clause 0x1
	global_load_b32 v6, v3, s[64:65]
	global_load_b32 v7, v3, s[70:71]
	s_add_u32 s70, s60, s66
	s_addc_u32 s71, s61, s67
	s_add_i32 s34, s34, 1
	s_add_u32 s66, s66, 4
	s_addc_u32 s67, s67, 0
	s_cmp_lt_i32 s34, s48
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v6, v6, v7
	global_store_b32 v3, v6, s[70:71]
	s_cbranch_scc1 .LBB1_69
.LBB1_70:                               ; %._crit_edge398
                                        ;   in Loop: Header=BB1_67 Depth=2
	s_cmp_eq_u32 s54, 0
	s_cselect_b32 s34, -1, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s34, s34, s68
	s_and_b32 vcc_lo, exec_lo, s34
	s_cbranch_vccnz .LBB1_75
; %bb.71:                               ; %.preheader353.preheader
                                        ;   in Loop: Header=BB1_67 Depth=2
	s_mov_b32 s34, 0
	s_mov_b64 s[64:65], s[18:19]
.LBB1_72:                               ; %.preheader353
                                        ;   Parent Loop BB1_12 Depth=1
                                        ;     Parent Loop BB1_67 Depth=2
                                        ; =>    This Loop Header: Depth=3
                                        ;         Child Loop BB1_73 Depth 4
	v_mov_b32_e32 v6, 0
	s_mov_b64 s[66:67], 0
	s_mov_b32 s55, 0
.LBB1_73:                               ;   Parent Loop BB1_12 Depth=1
                                        ;     Parent Loop BB1_67 Depth=2
                                        ;       Parent Loop BB1_72 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	s_add_u32 s70, s64, s66
	s_addc_u32 s71, s65, s67
	s_add_u32 s88, s58, s66
	s_addc_u32 s89, s59, s67
	s_clause 0x1
	global_load_b32 v7, v3, s[70:71]
	global_load_b32 v8, v3, s[88:89]
	s_add_i32 s55, s55, 1
	s_add_u32 s66, s66, 4
	s_addc_u32 s67, s67, 0
	s_cmp_lt_u32 s55, s54
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v6, v7, v8
	s_cbranch_scc1 .LBB1_73
; %bb.74:                               ;   in Loop: Header=BB1_72 Depth=3
	s_lshl_b64 s[66:67], s[34:35], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s66, s60, s66
	s_addc_u32 s67, s61, s67
	s_add_i32 s34, s34, 1
	global_load_b32 v7, v3, s[66:67]
	s_add_u32 s64, s64, s56
	s_addc_u32 s65, s65, s57
	s_cmp_lt_i32 s34, s48
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v6, v6, v7
	global_store_b32 v3, v6, s[66:67]
	s_cbranch_scc1 .LBB1_72
.LBB1_75:                               ; %.loopexit
                                        ;   in Loop: Header=BB1_67 Depth=2
	s_add_i32 s54, s54, 1
	s_add_u32 s60, s60, s52
	s_addc_u32 s61, s61, s53
	s_add_u32 s62, s62, s52
	s_addc_u32 s63, s63, s53
	s_add_u32 s56, s56, 4
	s_addc_u32 s57, s57, 0
	s_add_u32 s58, s58, s44
	s_addc_u32 s59, s59, s45
	s_cmp_eq_u32 s54, s28
	s_cbranch_scc0 .LBB1_67
; %bb.76:                               ; %.preheader363
                                        ;   in Loop: Header=BB1_12 Depth=1
	s_cmp_lg_u32 s85, s28
	s_mov_b32 s52, 0
	s_cselect_b32 s62, -1, 0
	s_mov_b32 s63, 0
.LBB1_77:                               ; %.preheader356
                                        ;   Parent Loop BB1_12 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB1_79 Depth 3
                                        ;         Child Loop BB1_81 Depth 4
	s_and_not1_b32 vcc_lo, exec_lo, s62
	s_cbranch_vccnz .LBB1_84
; %bb.78:                               ; %.preheader352.lr.ph
                                        ;   in Loop: Header=BB1_77 Depth=2
	s_mov_b32 s53, s35
	s_mov_b32 s54, 0
	s_lshl_b64 s[56:57], s[52:53], 2
	s_mov_b32 s53, 0
	s_add_u32 s56, s18, s56
	s_addc_u32 s57, s19, s57
.LBB1_79:                               ; %.preheader352
                                        ;   Parent Loop BB1_12 Depth=1
                                        ;     Parent Loop BB1_77 Depth=2
                                        ; =>    This Loop Header: Depth=3
                                        ;         Child Loop BB1_81 Depth 4
	s_and_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB1_82
; %bb.80:                               ; %.lr.ph409
                                        ;   in Loop: Header=BB1_79 Depth=3
	s_mov_b32 s55, s35
	v_mov_b32_e32 v6, 0
	s_lshl_b64 s[58:59], s[54:55], 2
	s_mov_b32 s34, 0
	s_add_u32 s58, s80, s58
	s_addc_u32 s59, s81, s59
	s_mov_b64 s[60:61], s[56:57]
.LBB1_81:                               ;   Parent Loop BB1_12 Depth=1
                                        ;     Parent Loop BB1_77 Depth=2
                                        ;       Parent Loop BB1_79 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	s_clause 0x1
	global_load_b32 v7, v3, s[60:61]
	global_load_b32 v8, v3, s[58:59]
	s_add_i32 s34, s34, 1
	s_add_u32 s60, s60, 4
	s_addc_u32 s61, s61, 0
	s_add_u32 s58, s58, 4
	s_addc_u32 s59, s59, 0
	s_cmp_lt_i32 s34, s48
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v6, v7, v8
	s_cbranch_scc1 .LBB1_81
	s_branch .LBB1_83
.LBB1_82:                               ;   in Loop: Header=BB1_79 Depth=3
	v_mov_b32_e32 v6, 0
.LBB1_83:                               ; %._crit_edge410
                                        ;   in Loop: Header=BB1_79 Depth=3
	s_mul_i32 s34, s53, s28
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s34, s34, s63
	s_lshl_b64 s[58:59], s[34:35], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s58, s12, s58
	s_addc_u32 s59, s13, s59
	s_add_i32 s53, s53, 1
	s_add_i32 s54, s54, s48
	s_cmp_lg_u32 s53, s51
	global_store_b32 v3, v6, s[58:59]
	s_cbranch_scc1 .LBB1_79
.LBB1_84:                               ; %._crit_edge415
                                        ;   in Loop: Header=BB1_77 Depth=2
	s_add_i32 s63, s63, 1
	s_add_i32 s52, s52, s48
	s_cmp_eq_u32 s63, s28
	s_cbranch_scc0 .LBB1_77
.LBB1_85:                               ; %.preheader361
                                        ;   in Loop: Header=BB1_12 Depth=1
	v_cmp_ne_u32_e32 vcc_lo, 1, v5
	s_cbranch_vccnz .LBB1_94
; %bb.86:                               ; %.preheader355.lr.ph
                                        ;   in Loop: Header=BB1_12 Depth=1
	s_cmp_lg_u32 s85, s28
	s_mov_b32 s52, 0
	s_cselect_b32 s1, -1, 0
	s_add_u32 s56, s46, s42
	s_addc_u32 s57, s47, s43
.LBB1_87:                               ; %.preheader355
                                        ;   Parent Loop BB1_12 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB1_89 Depth 3
                                        ;         Child Loop BB1_91 Depth 4
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB1_93
; %bb.88:                               ; %.preheader.lr.ph
                                        ;   in Loop: Header=BB1_87 Depth=2
	s_mov_b32 s53, s35
	s_mov_b32 s60, 0
	s_lshl_b64 s[54:55], s[52:53], 2
	s_mov_b32 s53, 0
	s_add_u32 s58, s56, s54
	s_addc_u32 s59, s57, s55
.LBB1_89:                               ; %.preheader
                                        ;   Parent Loop BB1_12 Depth=1
                                        ;     Parent Loop BB1_87 Depth=2
                                        ; =>    This Loop Header: Depth=3
                                        ;         Child Loop BB1_91 Depth 4
	v_mov_b32_e32 v5, 0
	s_and_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccnz .LBB1_92
; %bb.90:                               ; %.lr.ph419
                                        ;   in Loop: Header=BB1_89 Depth=3
	s_mov_b32 s34, s52
	s_mov_b32 s54, s53
	s_mov_b32 s61, s28
.LBB1_91:                               ;   Parent Loop BB1_12 Depth=1
                                        ;     Parent Loop BB1_87 Depth=2
                                        ;       Parent Loop BB1_89 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	s_lshl_b64 s[62:63], s[34:35], 2
	s_mov_b32 s55, s35
	s_add_u32 s62, s16, s62
	s_addc_u32 s63, s17, s63
	s_lshl_b64 s[64:65], s[54:55], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s64, s12, s64
	s_addc_u32 s65, s13, s65
	s_clause 0x1
	global_load_b32 v6, v3, s[62:63]
	global_load_b32 v7, v3, s[64:65]
	s_add_i32 s61, s61, -1
	s_add_i32 s54, s54, 1
	s_add_i32 s34, s34, s48
	s_cmp_lg_u32 s61, 0
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v5, v6, v7
	s_cbranch_scc1 .LBB1_91
.LBB1_92:                               ; %._crit_edge420
                                        ;   in Loop: Header=BB1_89 Depth=3
	s_mul_i32 s34, s60, s48
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[54:55], s[34:35], 2
	s_add_u32 s54, s58, s54
	s_addc_u32 s55, s59, s55
	s_add_i32 s60, s60, 1
	global_load_b32 v6, v3, s[54:55]
	s_add_i32 s53, s53, s28
	s_cmp_lg_u32 s60, s51
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v5, v5, v6
	global_store_b32 v3, v5, s[54:55]
	s_cbranch_scc1 .LBB1_89
.LBB1_93:                               ; %._crit_edge423
                                        ;   in Loop: Header=BB1_87 Depth=2
	s_add_i32 s52, s52, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lt_i32 s52, s48
	s_cbranch_scc1 .LBB1_87
.LBB1_94:                               ; %.loopexit362
                                        ;   in Loop: Header=BB1_12 Depth=1
	s_and_not1_b32 vcc_lo, exec_lo, s86
	s_cbranch_vccnz .LBB1_100
; %bb.95:                               ; %.preheader354.lr.ph
                                        ;   in Loop: Header=BB1_12 Depth=1
	s_mov_b32 s34, 0
	s_mov_b64 s[0:1], s[16:17]
	s_mov_b64 s[52:53], s[46:47]
.LBB1_96:                               ; %.preheader354
                                        ;   Parent Loop BB1_12 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB1_98 Depth 3
	s_not_b32 s51, s34
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s51, s48, s51
	s_cmp_lt_i32 s51, 1
	s_cbranch_scc1 .LBB1_99
; %bb.97:                               ; %.lr.ph426
                                        ;   in Loop: Header=BB1_96 Depth=2
	s_lshl_b64 s[54:55], s[34:35], 2
	s_mov_b32 s58, 0
	s_add_u32 s54, s4, s54
	s_addc_u32 s55, s5, s55
	s_mov_b64 s[56:57], 4
.LBB1_98:                               ;   Parent Loop BB1_12 Depth=1
                                        ;     Parent Loop BB1_96 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s60, s0, s56
	s_addc_u32 s61, s1, s57
	s_clause 0x1
	global_load_b32 v5, v3, s[54:55]
	global_load_b32 v6, v3, s[60:61]
	s_add_u32 s62, s52, s56
	s_addc_u32 s63, s53, s57
	s_add_i32 s58, s58, 1
	s_add_u32 s56, s56, 4
	s_addc_u32 s57, s57, 0
	s_cmp_lt_i32 s58, s51
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v5, v5, v6
	s_clause 0x1
	global_store_b32 v3, v5, s[60:61]
	global_store_b32 v3, v5, s[62:63]
	s_cbranch_scc1 .LBB1_98
.LBB1_99:                               ; %._crit_edge427
                                        ;   in Loop: Header=BB1_96 Depth=2
	s_add_i32 s34, s34, 1
	s_add_u32 s52, s52, s78
	s_addc_u32 s53, s53, s79
	s_add_u32 s0, s0, s31
	s_addc_u32 s1, s1, s49
	s_cmp_lg_u32 s34, s84
	s_cbranch_scc1 .LBB1_96
.LBB1_100:                              ; %._crit_edge431
                                        ;   in Loop: Header=BB1_12 Depth=1
	s_add_i32 s74, s84, s74
	s_add_u32 s46, s46, s40
	s_addc_u32 s47, s47, s41
	s_sub_i32 s48, s48, s28
	s_add_i32 s83, s83, 1
	s_add_u32 s80, s80, s40
	s_addc_u32 s81, s81, s41
	s_cmp_lt_i32 s83, s72
	s_cbranch_scc0 .LBB1_102
; %bb.101:                              ;   in Loop: Header=BB1_12 Depth=1
	s_mov_b32 s85, s2
	s_branch .LBB1_12
.LBB1_102:                              ; %._crit_edge439
	v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s74
	s_waitcnt lgkmcnt(0)
	global_store_b32 v0, v1, s[14:15]
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z18GetQRDecompBlockediiPfS_jiS_S_S_PiS_S0_S_S_S_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 112
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 21
		.amdhsa_next_free_sgpr 90
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z18GetQRDecompBlockediiPfS_jiS_S_S_PiS_S0_S_S_S_S_, .Lfunc_end1-_Z18GetQRDecompBlockediiPfS_jiS_S_S_PiS_S0_S_S_S_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 3816
; NumSgprs: 92
; NumVgprs: 21
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 11
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 92
; NumVGPRsForWavesPerEU: 21
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     by_value
      - .offset:         4
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z11getColNormsiiPfS_
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z11getColNormsiiPfS_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     7
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     by_value
      - .offset:         4
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         48
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         56
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         64
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         72
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         80
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         88
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         96
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         104
        .size:           8
        .value_kind:     global_buffer
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 112
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z18GetQRDecompBlockediiPfS_jiS_S_S_PiS_S0_S_S_S_S_
    .private_segment_fixed_size: 0
    .sgpr_count:     92
    .sgpr_spill_count: 0
    .symbol:         _Z18GetQRDecompBlockediiPfS_jiS_S_S_PiS_S0_S_S_S_S_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     21
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
