#include <stdio.h>
#include <cuda.h>
#include <time.h>

#define m(y,x) mapa[(y * cols) + x]

/*Definición de constantes*/
#define currentGPU 0		//El número más alto suele indicar la salida de vídeo
#define MAX 50

typedef struct {
	int y;
	int x;
} Antena;

__global__ void gpu_init(int *mapad, int max, int size)
{
	/*Identificaciones necesarios*/
	int IDX_Thread = threadIdx.x; 
	int IDY_Thread = threadIdx.y;
	int IDX_block =	blockIdx.x;
	int IDY_block =	blockIdx.y;
	int shapeGrid_X = gridDim.x;
	int threads_per_block =	blockDim.x * blockDim.y;
	int position = threads_per_block * ((IDY_block * shapeGrid_X)+IDX_block)+((IDY_Thread*blockDim.x)+IDX_Thread);

	if (position<size) mapad[position] = max;
}

__global__ void gpu_actualizar(int *mapad, int rows, int cols, Antena antena, int size)
{
	int IDX_Thread = threadIdx.x; 
	int IDY_Thread = threadIdx.y;
	int IDX_block =	blockIdx.x;
	int IDY_block =	blockIdx.y;
	int shapeGrid_X = gridDim.x;
	int threads_per_block =	blockDim.x * blockDim.y;
	int position = threads_per_block * ((IDY_block * shapeGrid_X)+IDX_block)+((IDY_Thread*blockDim.x)+IDX_Thread);

	if(position<size)
	{
		int x,y;
		y=(int)position/cols;
		x=position-y*rows;
		int dist = abs(antena.x -x) + abs(antena.y - y);
		int nuevadist = dist*dist;
		if(nuevadist<mapad[position])
		{
			mapad[position] = nuevadist;
		}
	}

}
int manhattan(Antena a, int y, int x){

	int dist = abs(a.x -x) + abs(a.y - y);
	return dist * dist;
}


int main()
{
	int rows, cols,nAntenas, i,j;
	rows = 5;
	cols = 5;
	nAntenas = 1;
	Antena *antenas;

	 if ((antenas = (Antena *) calloc(rows * cols, sizeof(Antena)))==NULL){		//mapa
		printf("error\n");
		exit (-1);
	}

	/*Declaración e inicialización de variables CPU (HOST)*/
	int *mapa;

	/*Indicamos la GPU (DEVICE) que vamos a utilizar*/
	int *mapad;

	/*Reserva de memoria para de variables CPU*/
	if ((mapa=(int *) calloc(rows * cols, sizeof(int)))==NULL){		//mapa
		printf("error\n");
		exit (-1);
	}
	


	/*Reserva de memoria para variables del DEVICE (en memoria GPU)*/
	
	cudaMalloc( (void**) &mapad, sizeof(int) * (int) rows * cols);
	

	/*Inicialización del mapa*/
	int size = rows * cols;
	int tam = (int) ceil( ((float)(rows * cols))/size);
	dim3 bloqdiminit(128,1);
	dim3 griddiminit(tam,1);

	gpu_init<<<griddiminit,bloqdiminit>>>(mapad,MAX,size);

	/*Copia de datos del HOST al DEVICE*/
	cudaMemcpy(mapa,mapad,sizeof(int) * rows*cols,cudaMemcpyDeviceToHost);

	/*Lanzamos la función del DEVICE*/
	cudaDeviceSynchronize();
	printf("matriz:\n");
	for (i = 0; i<5;i++){
		for (j=0;j<5;j++){
			printf(" %d ",mapa[j*5+i]);
		}
		printf("\n");

	}
	printf("fin de la matriz\n");

	Antena ant = {2,2};

	gpu_actualizar<<<griddiminit,bloqdiminit>>>(mapad, rows,  cols,  ant,  size);
	
	cudaMemcpy(mapa,mapad,sizeof(int) * rows*cols,cudaMemcpyDeviceToHost);

	/*Lanzamos la función del DEVICE*/
	cudaDeviceSynchronize();
	printf("matriz2:\n");
	for (i = 0; i<5;i++){
		for (j=0;j<5;j++){
			printf(" %d ",mapa[j*5+i]);
		}
		printf("\n");

	}
	printf("fin de la matriz2\n");

	/*Liberamos memoria del DEVICE*/
	cudaFree(mapad);

	/*Liberamos memoria del HOST*/
	free(mapa);

	/*Liberamos los hilos del DEVICE*/
	cudaDeviceReset();
} //main





	.file	"tmpxft_002d7523_00000000-6_prueba4.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2031:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z9manhattan6Antenaii
	.type	_Z9manhattan6Antenaii, @function
_Z9manhattan6Antenaii:
.LFB2027:
	.cfi_startproc
	endbr64
	movl	%edx, %eax
	movq	%rdi, %rdx
	sarq	$32, %rdx
	subl	%eax, %edx
	movl	%edx, %eax
	negl	%eax
	cmovs	%edx, %eax
	subl	%esi, %edi
	movl	%edi, %edx
	negl	%edx
	cmovs	%edi, %edx
	addl	%edx, %eax
	imull	%eax, %eax
	ret
	.cfi_endproc
.LFE2027:
	.size	_Z9manhattan6Antenaii, .-_Z9manhattan6Antenaii
	.globl	_Z29__device_stub__Z8gpu_initPiiiPiii
	.type	_Z29__device_stub__Z8gpu_initPiiiPiii, @function
_Z29__device_stub__Z8gpu_initPiiiPiii:
.LFB2053:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 8(%rsp)
	leaq	24(%rsp), %rcx
	leaq	32(%rsp), %rdi
	movl	%esi, 4(%rsp)
	leaq	44(%rsp), %rsi
	movl	%edx, (%rsp)
	leaq	16(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 40(%rsp)
	movq	%rax, 80(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 88(%rsp)
	movq	%rsp, %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 32(%rsp)
	movq	%rax, 44(%rsp)
	movl	$1, 52(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L3
	pushq	24(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z8gpu_initPiii(%rip), %rdi
	pushq	24(%rsp)
	.cfi_def_cfa_offset 144
	movq	60(%rsp), %rcx
	movl	68(%rsp), %r8d
	movq	48(%rsp), %rsi
	movl	56(%rsp), %edx
	leaq	96(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L3:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L5
	call	__stack_chk_fail@PLT
.L5:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2053:
	.size	_Z29__device_stub__Z8gpu_initPiiiPiii, .-_Z29__device_stub__Z8gpu_initPiiiPiii
	.globl	_Z8gpu_initPiii
	.type	_Z8gpu_initPiii, @function
_Z8gpu_initPiii:
.LFB2054:
	.cfi_startproc
	endbr64
	jmp	_Z29__device_stub__Z8gpu_initPiiiPiii
	.cfi_endproc
.LFE2054:
	.size	_Z8gpu_initPiii, .-_Z8gpu_initPiii
	.globl	_Z44__device_stub__Z14gpu_actualizarPiii6AntenaiPiiiR6Antenai
	.type	_Z44__device_stub__Z14gpu_actualizarPiii6AntenaiPiiiR6Antenai, @function
_Z44__device_stub__Z14gpu_actualizarPiii6AntenaiPiiiR6Antenai:
.LFB2055:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rdi
	movl	%esi, 20(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 16(%rsp)
	leaq	32(%rsp), %rdx
	movl	%r8d, 12(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movq	%rcx, 120(%rsp)
	leaq	40(%rsp), %rcx
	movq	%rax, 96(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movl	$1, 56(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L9
	pushq	40(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z14gpu_actualizarPiii6Antenai(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 176
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L9:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L11
	call	__stack_chk_fail@PLT
.L11:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2055:
	.size	_Z44__device_stub__Z14gpu_actualizarPiii6AntenaiPiiiR6Antenai, .-_Z44__device_stub__Z14gpu_actualizarPiii6AntenaiPiiiR6Antenai
	.globl	_Z14gpu_actualizarPiii6Antenai
	.type	_Z14gpu_actualizarPiii6Antenai, @function
_Z14gpu_actualizarPiii6Antenai:
.LFB2056:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rcx, 8(%rsp)
	leaq	8(%rsp), %rcx
	call	_Z44__device_stub__Z14gpu_actualizarPiii6AntenaiPiiiR6Antenai
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2056:
	.size	_Z14gpu_actualizarPiii6Antenai, .-_Z14gpu_actualizarPiii6Antenai
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"error\n"
.LC1:
	.string	"matriz:\n"
.LC2:
	.string	" %d "
.LC3:
	.string	"\n"
.LC4:
	.string	"fin de la matriz\n"
.LC5:
	.string	"matriz2:\n"
.LC6:
	.string	"fin de la matriz2\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2028:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movl	$8, %esi
	movl	$25, %edi
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$56, %rsp
	.cfi_def_cfa_offset 112
	movq	%fs:40, %rax
	movq	%rax, 40(%rsp)
	xorl	%eax, %eax
	call	calloc@PLT
	testq	%rax, %rax
	jne	.L16
.L17:
	movl	$2, %edi
	leaq	.LC0(%rip), %rsi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	orl	$-1, %edi
	call	exit@PLT
.L16:
	movl	$4, %esi
	movl	$25, %edi
	call	calloc@PLT
	movq	%rax, %rbx
	testq	%rax, %rax
	je	.L17
	movq	%rsp, %rdi
	movl	$100, %esi
	call	cudaMalloc@PLT
	movl	$33554433, %edx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	salq	$7, %rdx
	movl	$1, %ecx
	movabsq	$4294967297, %rdi
	movl	$1, %esi
	movq	%rdx, 16(%rsp)
	movl	$1, 24(%rsp)
	movq	%rdi, 28(%rsp)
	movl	$1, 36(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L18
	movq	(%rsp), %rdi
	movl	$25, %edx
	movl	$50, %esi
	call	_Z29__device_stub__Z8gpu_initPiiiPiii
.L18:
	movq	(%rsp), %rsi
	movl	$2, %ecx
	movl	$100, %edx
	xorl	%ebp, %ebp
	movq	%rbx, %rdi
	leaq	.LC2(%rip), %r13
	call	cudaMemcpy@PLT
	call	cudaDeviceSynchronize@PLT
	leaq	.LC1(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
.L19:
	leaq	(%rbx,%rbp,4), %r14
	movl	$5, %r12d
.L20:
	movl	(%r14), %edx
	movq	%r13, %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	addq	$20, %r14
	call	__printf_chk@PLT
	decl	%r12d
	jne	.L20
	leaq	.LC3(%rip), %r14
	movl	$2, %edi
	xorl	%eax, %eax
	incq	%rbp
	movq	%r14, %rsi
	call	__printf_chk@PLT
	cmpq	$5, %rbp
	jne	.L19
	leaq	.LC4(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movl	24(%rsp), %ecx
	movl	36(%rsp), %esi
	xorl	%r9d, %r9d
	movq	16(%rsp), %rdx
	movq	28(%rsp), %rdi
	xorl	%r8d, %r8d
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L22
	movq	(%rsp), %rdi
	leaq	8(%rsp), %rcx
	movl	$5, %edx
	movabsq	$8589934594, %rax
	movl	$25, %r8d
	movl	$5, %esi
	movq	%rax, 8(%rsp)
	call	_Z44__device_stub__Z14gpu_actualizarPiii6AntenaiPiiiR6Antenai
.L22:
	movq	(%rsp), %rsi
	movl	$2, %ecx
	movl	$100, %edx
	xorl	%ebp, %ebp
	movq	%rbx, %rdi
	call	cudaMemcpy@PLT
	call	cudaDeviceSynchronize@PLT
	leaq	.LC5(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
.L23:
	leaq	(%rbx,%rbp,4), %r15
	xorl	%r12d, %r12d
.L24:
	movl	(%r15), %edx
	movq	%r13, %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	incl	%r12d
	addq	$20, %r15
	call	__printf_chk@PLT
	cmpl	$5, %r12d
	jne	.L24
	movq	%r14, %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	incq	%rbp
	call	__printf_chk@PLT
	cmpq	$5, %rbp
	jne	.L23
	leaq	.LC6(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movq	(%rsp), %rdi
	call	cudaFree@PLT
	movq	%rbx, %rdi
	call	free@PLT
	call	cudaDeviceReset@PLT
	movq	40(%rsp), %rax
	subq	%fs:40, %rax
	je	.L26
	call	__stack_chk_fail@PLT
.L26:
	addq	$56, %rsp
	.cfi_def_cfa_offset 56
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2028:
	.size	main, .-main
	.section	.rodata.str1.1
.LC7:
	.string	"_Z14gpu_actualizarPiii6Antenai"
.LC8:
	.string	"_Z8gpu_initPiii"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2058:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC7(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z14gpu_actualizarPiii6Antenai(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC8(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z8gpu_initPiii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2058:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <stdio.h>
#include <hip/hip_runtime.h>
#include <time.h>

#define m(y,x) mapa[(y * cols) + x]

/*Definición de constantes*/
#define currentGPU 0		//El número más alto suele indicar la salida de vídeo
#define MAX 50

typedef struct {
	int y;
	int x;
} Antena;

__global__ void gpu_init(int *mapad, int max, int size)
{
	/*Identificaciones necesarios*/
	int IDX_Thread = threadIdx.x; 
	int IDY_Thread = threadIdx.y;
	int IDX_block =	blockIdx.x;
	int IDY_block =	blockIdx.y;
	int shapeGrid_X = gridDim.x;
	int threads_per_block =	blockDim.x * blockDim.y;
	int position = threads_per_block * ((IDY_block * shapeGrid_X)+IDX_block)+((IDY_Thread*blockDim.x)+IDX_Thread);

	if (position<size) mapad[position] = max;
}

__global__ void gpu_actualizar(int *mapad, int rows, int cols, Antena antena, int size)
{
	int IDX_Thread = threadIdx.x; 
	int IDY_Thread = threadIdx.y;
	int IDX_block =	blockIdx.x;
	int IDY_block =	blockIdx.y;
	int shapeGrid_X = gridDim.x;
	int threads_per_block =	blockDim.x * blockDim.y;
	int position = threads_per_block * ((IDY_block * shapeGrid_X)+IDX_block)+((IDY_Thread*blockDim.x)+IDX_Thread);

	if(position<size)
	{
		int x,y;
		y=(int)position/cols;
		x=position-y*rows;
		int dist = abs(antena.x -x) + abs(antena.y - y);
		int nuevadist = dist*dist;
		if(nuevadist<mapad[position])
		{
			mapad[position] = nuevadist;
		}
	}

}
int manhattan(Antena a, int y, int x){

	int dist = abs(a.x -x) + abs(a.y - y);
	return dist * dist;
}


int main()
{
	int rows, cols,nAntenas, i,j;
	rows = 5;
	cols = 5;
	nAntenas = 1;
	Antena *antenas;

	 if ((antenas = (Antena *) calloc(rows * cols, sizeof(Antena)))==NULL){		//mapa
		printf("error\n");
		exit (-1);
	}

	/*Declaración e inicialización de variables CPU (HOST)*/
	int *mapa;

	/*Indicamos la GPU (DEVICE) que vamos a utilizar*/
	int *mapad;

	/*Reserva de memoria para de variables CPU*/
	if ((mapa=(int *) calloc(rows * cols, sizeof(int)))==NULL){		//mapa
		printf("error\n");
		exit (-1);
	}
	


	/*Reserva de memoria para variables del DEVICE (en memoria GPU)*/
	
	hipMalloc( (void**) &mapad, sizeof(int) * (int) rows * cols);
	

	/*Inicialización del mapa*/
	int size = rows * cols;
	int tam = (int) ceil( ((float)(rows * cols))/size);
	dim3 bloqdiminit(128,1);
	dim3 griddiminit(tam,1);

	gpu_init<<<griddiminit,bloqdiminit>>>(mapad,MAX,size);

	/*Copia de datos del HOST al DEVICE*/
	hipMemcpy(mapa,mapad,sizeof(int) * rows*cols,hipMemcpyDeviceToHost);

	/*Lanzamos la función del DEVICE*/
	hipDeviceSynchronize();
	printf("matriz:\n");
	for (i = 0; i<5;i++){
		for (j=0;j<5;j++){
			printf(" %d ",mapa[j*5+i]);
		}
		printf("\n");

	}
	printf("fin de la matriz\n");

	Antena ant = {2,2};

	gpu_actualizar<<<griddiminit,bloqdiminit>>>(mapad, rows,  cols,  ant,  size);
	
	hipMemcpy(mapa,mapad,sizeof(int) * rows*cols,hipMemcpyDeviceToHost);

	/*Lanzamos la función del DEVICE*/
	hipDeviceSynchronize();
	printf("matriz2:\n");
	for (i = 0; i<5;i++){
		for (j=0;j<5;j++){
			printf(" %d ",mapa[j*5+i]);
		}
		printf("\n");

	}
	printf("fin de la matriz2\n");

	/*Liberamos memoria del DEVICE*/
	hipFree(mapad);

	/*Liberamos memoria del HOST*/
	free(mapa);

	/*Liberamos los hilos del DEVICE*/
	hipDeviceReset();
} //main





	.text
	.file	"prueba4.hip"
	.globl	_Z23__device_stub__gpu_initPiii # -- Begin function _Z23__device_stub__gpu_initPiii
	.type	_Z23__device_stub__gpu_initPiii,@function
_Z23__device_stub__gpu_initPiii:        # @_Z23__device_stub__gpu_initPiii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$96, %rsp
	.cfi_def_cfa_offset 144
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	4(%rsp), %rcx
	movl	%esi, (%rcx)
	movq	%rsp, %rsi
	movl	%edx, (%rsi)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z8gpu_initPiii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$112, %rsp
	.cfi_adjust_cfa_offset -112
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z23__device_stub__gpu_initPiii, .Lfunc_end0-_Z23__device_stub__gpu_initPiii
	.cfi_endproc
                                        # -- End function
	.globl	_Z29__device_stub__gpu_actualizarPiii6Antenai # -- Begin function _Z29__device_stub__gpu_actualizarPiii6Antenai
	.type	_Z29__device_stub__gpu_actualizarPiii6Antenai,@function
_Z29__device_stub__gpu_actualizarPiii6Antenai: # @_Z29__device_stub__gpu_actualizarPiii6Antenai
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rcx, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rdi, (%rcx)
	leaq	12(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	8(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	4(%rsp), %rdx
	movl	%r8d, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rcx, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rax, 24(%rbx)
	movq	%rdx, 32(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z14gpu_actualizarPiii6Antenai, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z29__device_stub__gpu_actualizarPiii6Antenai, .Lfunc_end1-_Z29__device_stub__gpu_actualizarPiii6Antenai
	.cfi_endproc
                                        # -- End function
	.globl	_Z9manhattan6Antenaii           # -- Begin function _Z9manhattan6Antenaii
	.type	_Z9manhattan6Antenaii,@function
_Z9manhattan6Antenaii:                  # @_Z9manhattan6Antenaii
	.cfi_startproc
# %bb.0:
	movq	%rdi, %rax
	shrq	$32, %rax
	subl	%edx, %eax
	movl	%eax, %ecx
	negl	%ecx
	cmovsl	%eax, %ecx
	subl	%esi, %edi
	movl	%edi, %eax
	negl	%eax
	cmovsl	%edi, %eax
	addl	%ecx, %eax
	imull	%eax, %eax
	retq
.Lfunc_end2:
	.size	_Z9manhattan6Antenaii, .Lfunc_end2-_Z9manhattan6Antenaii
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	pushq	%rax
	.cfi_def_cfa_offset 64
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	$25, %edi
	movl	$4, %esi
	callq	calloc
	testq	%rax, %rax
	je	.LBB3_14
# %bb.1:
	movq	%rax, %rbx
	movabsq	$4294967297, %r14               # imm = 0x100000001
	movq	%rsp, %rdi
	movl	$100, %esi
	callq	hipMalloc
	leaq	127(%r14), %r15
	movq	%r14, %rdi
	movl	$1, %esi
	movq	%r15, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB3_3
# %bb.2:
	movq	(%rsp), %rdi
	movl	$50, %esi
	movl	$25, %edx
	callq	_Z23__device_stub__gpu_initPiii
.LBB3_3:
	movq	(%rsp), %rsi
	movl	$100, %edx
	movq	%rbx, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	callq	hipDeviceSynchronize
	movl	$.Lstr, %edi
	callq	puts@PLT
	movq	%rbx, %r12
	xorl	%r13d, %r13d
.LBB3_4:                                # %.preheader68
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB3_5 Depth 2
	movq	$-100, %rbp
.LBB3_5:                                #   Parent Loop BB3_4 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movl	100(%r12,%rbp), %esi
	movl	$.L.str.2, %edi
	xorl	%eax, %eax
	callq	printf
	addq	$20, %rbp
	jne	.LBB3_5
# %bb.6:                                #   in Loop: Header=BB3_4 Depth=1
	movl	$10, %edi
	callq	putchar@PLT
	incq	%r13
	addq	$4, %r12
	cmpq	$5, %r13
	jne	.LBB3_4
# %bb.7:
	movl	$.Lstr.1, %edi
	callq	puts@PLT
	movq	%r14, %rdi
	movl	$1, %esi
	movq	%r15, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB3_9
# %bb.8:
	movq	(%rsp), %rdi
	movabsq	$8589934594, %rcx               # imm = 0x200000002
	movl	$5, %esi
	movl	$5, %edx
	movl	$25, %r8d
	callq	_Z29__device_stub__gpu_actualizarPiii6Antenai
.LBB3_9:
	movq	(%rsp), %rsi
	movl	$100, %edx
	movq	%rbx, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	callq	hipDeviceSynchronize
	movl	$.Lstr.2, %edi
	callq	puts@PLT
	movq	%rbx, %r14
	xorl	%r15d, %r15d
.LBB3_10:                               # %.preheader
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB3_11 Depth 2
	movq	$-100, %r12
.LBB3_11:                               #   Parent Loop BB3_10 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movl	100(%r14,%r12), %esi
	movl	$.L.str.2, %edi
	xorl	%eax, %eax
	callq	printf
	addq	$20, %r12
	jne	.LBB3_11
# %bb.12:                               #   in Loop: Header=BB3_10 Depth=1
	movl	$10, %edi
	callq	putchar@PLT
	incq	%r15
	addq	$4, %r14
	cmpq	$5, %r15
	jne	.LBB3_10
# %bb.13:
	movl	$.Lstr.3, %edi
	callq	puts@PLT
	movq	(%rsp), %rdi
	callq	hipFree
	movq	%rbx, %rdi
	callq	free
	callq	hipDeviceReset
	xorl	%eax, %eax
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB3_14:
	.cfi_def_cfa_offset 64
	movl	$.Lstr.4, %edi
	callq	puts@PLT
	movl	$-1, %edi
	callq	exit
.Lfunc_end3:
	.size	main, .Lfunc_end3-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB4_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB4_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z8gpu_initPiii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z14gpu_actualizarPiii6Antenai, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end4:
	.size	__hip_module_ctor, .Lfunc_end4-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB5_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB5_2:
	retq
.Lfunc_end5:
	.size	__hip_module_dtor, .Lfunc_end5-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z8gpu_initPiii,@object         # @_Z8gpu_initPiii
	.section	.rodata,"a",@progbits
	.globl	_Z8gpu_initPiii
	.p2align	3, 0x0
_Z8gpu_initPiii:
	.quad	_Z23__device_stub__gpu_initPiii
	.size	_Z8gpu_initPiii, 8

	.type	_Z14gpu_actualizarPiii6Antenai,@object # @_Z14gpu_actualizarPiii6Antenai
	.globl	_Z14gpu_actualizarPiii6Antenai
	.p2align	3, 0x0
_Z14gpu_actualizarPiii6Antenai:
	.quad	_Z29__device_stub__gpu_actualizarPiii6Antenai
	.size	_Z14gpu_actualizarPiii6Antenai, 8

	.type	.L.str.2,@object                # @.str.2
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str.2:
	.asciz	" %d "
	.size	.L.str.2, 5

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z8gpu_initPiii"
	.size	.L__unnamed_1, 16

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z14gpu_actualizarPiii6Antenai"
	.size	.L__unnamed_2, 31

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.type	.Lstr,@object                   # @str
	.section	.rodata.str1.1,"aMS",@progbits,1
.Lstr:
	.asciz	"matriz:"
	.size	.Lstr, 8

	.type	.Lstr.1,@object                 # @str.1
.Lstr.1:
	.asciz	"fin de la matriz"
	.size	.Lstr.1, 17

	.type	.Lstr.2,@object                 # @str.2
.Lstr.2:
	.asciz	"matriz2:"
	.size	.Lstr.2, 9

	.type	.Lstr.3,@object                 # @str.3
.Lstr.3:
	.asciz	"fin de la matriz2"
	.size	.Lstr.3, 18

	.type	.Lstr.4,@object                 # @str.4
.Lstr.4:
	.asciz	"error"
	.size	.Lstr.4, 6

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z23__device_stub__gpu_initPiii
	.addrsig_sym _Z29__device_stub__gpu_actualizarPiii6Antenai
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z8gpu_initPiii
	.addrsig_sym _Z14gpu_actualizarPiii6Antenai
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z8gpu_initPiii         ; -- Begin function _Z8gpu_initPiii
	.globl	_Z8gpu_initPiii
	.p2align	8
	.type	_Z8gpu_initPiii,@function
_Z8gpu_initPiii:                        ; @_Z8gpu_initPiii
; %bb.0:
	s_clause 0x2
	s_load_b32 s4, s[0:1], 0x10
	s_load_b32 s5, s[0:1], 0x1c
	s_load_b64 s[2:3], s[0:1], 0x8
	v_bfe_u32 v1, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s4, s4, s15
	s_lshr_b32 s6, s5, 16
	s_add_i32 s4, s4, s14
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mad_u64_u32 v[2:3], null, s4, s6, v[1:2]
	v_and_b32_e32 v3, 0x3ff, v0
	s_and_b32 s4, s5, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[0:1], null, v2, s4, v[3:4]
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_i32_e32 vcc_lo, s3, v0
	s_and_saveexec_b32 s3, vcc_lo
	s_cbranch_execz .LBB0_2
; %bb.1:
	s_load_b64 s[0:1], s[0:1], 0x0
	v_ashrrev_i32_e32 v1, 31, v0
	v_mov_b32_e32 v2, s2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v0, vcc_lo, s0, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	global_store_b32 v[0:1], v2, off
.LBB0_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z8gpu_initPiii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 5
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z8gpu_initPiii, .Lfunc_end0-_Z8gpu_initPiii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 176
; NumSgprs: 18
; NumVgprs: 5
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 5
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z14gpu_actualizarPiii6Antenai ; -- Begin function _Z14gpu_actualizarPiii6Antenai
	.globl	_Z14gpu_actualizarPiii6Antenai
	.p2align	8
	.type	_Z14gpu_actualizarPiii6Antenai,@function
_Z14gpu_actualizarPiii6Antenai:         ; @_Z14gpu_actualizarPiii6Antenai
; %bb.0:
	s_clause 0x2
	s_load_b32 s2, s[0:1], 0x20
	s_load_b32 s3, s[0:1], 0x2c
	s_load_b32 s4, s[0:1], 0x18
	v_bfe_u32 v1, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s2, s2, s15
	s_lshr_b32 s5, s3, 16
	s_add_i32 s2, s2, s14
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mad_u64_u32 v[2:3], null, s2, s5, v[1:2]
	v_and_b32_e32 v3, 0x3ff, v0
	s_and_b32 s2, s3, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[0:1], null, v2, s2, v[3:4]
	s_mov_b32 s2, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e64 s4, v0
	s_cbranch_execz .LBB1_3
; %bb.1:
	s_load_b128 s[4:7], s[0:1], 0x0
	v_ashrrev_i32_e32 v1, 31, v0
	s_load_b64 s[0:1], s[0:1], 0x10
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[0:1]
	v_add_nc_u32_e32 v7, v0, v1
	v_xor_b32_e32 v7, v7, v1
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v2, vcc_lo, s4, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
	s_ashr_i32 s2, s7, 31
	v_sub_nc_u32_e32 v0, s1, v0
	s_add_i32 s3, s7, s2
	global_load_b32 v6, v[2:3], off
	s_xor_b32 s3, s3, s2
	v_xor_b32_e32 v1, s2, v1
	v_cvt_f32_u32_e32 v4, s3
	s_sub_i32 s4, 0, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v4, v4
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v4, 0x4f7ffffe, v4
	v_cvt_u32_f32_e32 v4, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v5, s4, v4
	v_mul_hi_u32 v5, v4, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v4, v4, v5
	v_mul_hi_u32 v4, v7, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v5, v4, s3
	v_sub_nc_u32_e32 v5, v7, v5
	v_add_nc_u32_e32 v7, 1, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v8, s3, v5
	v_cmp_le_u32_e32 vcc_lo, s3, v5
	v_dual_cndmask_b32 v5, v5, v8 :: v_dual_cndmask_b32 v4, v4, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_le_u32_e32 vcc_lo, s3, v5
	v_add_nc_u32_e32 v7, 1, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v4, v4, v7, vcc_lo
	v_xor_b32_e32 v4, v4, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v1, v4, v1
	v_mad_u64_u32 v[4:5], null, v1, s6, v[0:1]
	v_sub_nc_u32_e32 v0, s0, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v5, 0, v0
	v_sub_nc_u32_e32 v1, 0, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_max_i32_e32 v0, v0, v5
	v_max_i32_e32 v1, v4, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v0, v1, v0
	v_mul_lo_u32 v0, v0, v0
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_lt_i32_e32 vcc_lo, v0, v6
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB1_3
; %bb.2:
	global_store_b32 v[2:3], v0, off
.LBB1_3:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z14gpu_actualizarPiii6Antenai
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 9
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z14gpu_actualizarPiii6Antenai, .Lfunc_end1-_Z14gpu_actualizarPiii6Antenai
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 432
; NumSgprs: 18
; NumVgprs: 9
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 9
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .offset:         12
        .size:           4
        .value_kind:     by_value
      - .offset:         16
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         20
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         28
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         30
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         32
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         34
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         36
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         38
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         56
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         80
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 272
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z8gpu_initPiii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z8gpu_initPiii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     5
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .offset:         12
        .size:           4
        .value_kind:     by_value
      - .offset:         16
        .size:           8
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z14gpu_actualizarPiii6Antenai
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z14gpu_actualizarPiii6Antenai.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     9
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
