
#include <cuda_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <sys/time.h>
#define blockSize 128
__global__ void reduce0(int *g_idata,int *g_odata){
extern __shared__ int sdata[];

//each thread loads one element from global to shared mem
unsigned int tid = threadIdx.x;
unsigned int i = blockIdx.x*blockDim.x+threadIdx.x;
sdata[tid]=g_idata[i];
//printf("%d- ",sdata[tid]);
__syncthreads();
//if(threadIdx.x==0){
//printf("\n");}

//do reduction in shared mem 
for(unsigned int s=1 ;s<blockDim.x; s*=2){
	if(tid%(2*s)==0){
		//if(tid==0){
		//printf("Level %d Thread %d Data %d + Data %d \n",s,tid,sdata[tid],sdata[tid+s]);}
		sdata[tid]+=sdata[tid+s];
	}
	__syncthreads();
}
// write the result for this block to global mem
if(tid ==0){ 
	g_odata[blockIdx.x]=sdata[0];
}

}

__global__ void reduce1(int *g_idata,int *g_odata){
extern __shared__ int sdata[];

//each thread loads one element from global to shared mem
unsigned int tid = threadIdx.x;
unsigned int i = blockIdx.x*blockDim.x+threadIdx.x;
sdata[tid]=g_idata[i];
//printf("%d- ",sdata[tid]);
__syncthreads();
//if(threadIdx.x==0){
//printf("\n");}

//do reduction in shared mem 
for(unsigned int s=1 ;s<blockDim.x; s*=2){
	int index=2*s*tid;
	if(index<blockDim.x){
		sdata[index]+=sdata[index+s];
	}
	__syncthreads();
}
// write the result for this block to global mem
if(tid ==0){ 
	g_odata[blockIdx.x]=sdata[0];
}

}

__global__ void reduce2(int *g_idata,int *g_odata){
extern __shared__ int sdata[];

//each thread loads one element from global to shared mem
unsigned int tid = threadIdx.x;
unsigned int i = blockIdx.x*blockDim.x+threadIdx.x;
sdata[tid]=g_idata[i];
//printf("%d- ",sdata[tid]);
__syncthreads();
//if(threadIdx.x==0){
//printf("\n");}

//do reduction in shared mem 
for(unsigned int s=blockDim.x/2; s>0;s>>=1){
	if(tid<s){
		sdata[tid]+=sdata[tid+s];
	}
	__syncthreads();
}
// write the result for this block to global mem
if(tid ==0){ 
	g_odata[blockIdx.x]=sdata[0];
}

}


__global__ void reduce3(int *g_idata,int *g_odata){
extern __shared__ int sdata[];

//each thread loads one element from global to shared mem
unsigned int tid = threadIdx.x;
unsigned int i = blockIdx.x*(blockDim.x*2)+threadIdx.x;
sdata[tid]=g_idata[i]+g_idata[i+blockDim.x];
//printf("%d- ",sdata[tid]);
__syncthreads();
//if(threadIdx.x==0){
//printf("\n");}

//do reduction in shared mem 
for(unsigned int s=blockDim.x/2; s>0;s>>=1){
	if(tid<s){
		sdata[tid]+=sdata[tid+s];
	}
	__syncthreads();
}
// write the result for this block to global mem
if(tid ==0){ 
	g_odata[blockIdx.x]=sdata[0];
}

}

__device__ void warpReduce(volatile int* sdata,int tid ){
	sdata[tid]+=sdata[tid +32];
	sdata[tid]+=sdata[tid +16];
	sdata[tid]+=sdata[tid +8];
	sdata[tid]+=sdata[tid +4];
	sdata[tid]+=sdata[tid +2];
	sdata[tid]+=sdata[tid +1];
}

__global__ void reduce4(int *g_idata,int *g_odata){
extern __shared__ int sdata[];

//each thread loads one element from global to shared mem
unsigned int tid = threadIdx.x;
unsigned int i = blockIdx.x*(blockDim.x*2)+threadIdx.x;
sdata[tid]=g_idata[i]+g_idata[i+blockDim.x];
//printf("%d- ",sdata[tid]);
__syncthreads();
//if(threadIdx.x==0){
//printf("\n");}

//do reduction in shared mem 
for(unsigned int s=blockDim.x/2; s>32;s>>=1){
	if(tid<s){
		sdata[tid]+=sdata[tid+s];
	}
	__syncthreads();
}
if(tid<32){ warpReduce(sdata,tid);}
// write the result for this block to global mem
if(tid ==0){ 
	g_odata[blockIdx.x]=sdata[0];
}

}
/*
template <unsigned int blockSize> 
__device__ void warpReducenew(volatile int* sdata,int tid ){
	if(blockSize>=64) sdata[tid]+=sdata[tid +32];
	if(blockSize>=32) sdata[tid]+=sdata[tid +16];
	if(blockSize>=16) sdata[tid]+=sdata[tid +8];
	if(blockSize>=8) sdata[tid]+=sdata[tid +4];
	if(blockSize>=4) sdata[tid]+=sdata[tid +2];
	if(blockSize>=2) sdata[tid]+=sdata[tid +1];
}


template <unsigned int blockSize>
__global__ void reduce5(int *g_idata,int * g_odata){

extern __shared__ int sdata[];
unsigned int tid = threadIdx.x;
unsigned int i = blockIdx.x*(blockDim.x*2)+threadIdx.x;
sdata[tid]=g_idata[i]+g_idata[i+blockDim.x];
__syncthreads();

if(blockSize>=512){
	if(tid<256 ){sdata[tid]+=sdata[tid+256];}
	__syncthreads();
}
if(blockSize>=256){
	if(tid<128 ){sdata[tid]+=sdata[tid+128];}
	__syncthreads();
}
if(blockSize>=128){
	if(tid<64 ){sdata[tid]+=sdata[tid+64];}
	__syncthreads();
}

if(tid<32){ warpReducenew<blockSize>(sdata,tid);}
// write the result for this block to global mem
if(tid ==0){ 
	g_odata[blockIdx.x]=sdata[0];
}



}

template <unsigned int blockSize>
__device__ void warpReduce(volatile int *sdata, unsigned int tid) 
{
	if (blockSize >=  64) sdata[tid] += sdata[tid + 32];
	if (blockSize >=  32) sdata[tid] += sdata[tid + 16];
	if (blockSize >=  16) sdata[tid] += sdata[tid +  8];
	if(blockSize >=   8) sdata[tid] += sdata[tid +  4];
	if (blockSize >=   4) sdata[tid] += sdata[tid +  2];
	if (blockSize >=   2) sdata[tid] += sdata[tid +  1];}
template <unsigned int blockSize>
__global__ voidreduce6(int *g_idata, int *g_odata, unsigned int n)
 {extern __shared__ int sdata[];

 unsigned int tid = threadIdx.x;
 unsigned int i = blockIdx.x*(blockSize*2) + tid;
 unsigned int gridSize = blockSize*2*gridDim.x;

 sdata[tid] = 0;

 while (i < n)
 	{
 		sdata[tid] += g_idata[i] + g_idata[i+blockSize];  i += gridSize;
 		  }
 __syncthreads();

 if (blockSize >= 512) { if (tid < 256) { sdata[tid] += sdata[tid + 256]; } __syncthreads(); }
 if (blockSize >= 256) { if (tid < 128) { sdata[tid] += sdata[tid + 128]; } __syncthreads(); }
 if (blockSize >= 128) { if (tid <  64) { sdata[tid] += sdata[tid +  64]; } __syncthreads(); }
 if (tid < 32)warpReduce(sdata, tid);
 if (tid == 0) g_odata[blockIdx.x] = sdata[0];
}
*/




int main(int argc, char **argv) {
int N= 1<<atoi(argv[1]);
int Blocks= atoi(argv[2]);
int Threads= atoi(argv[3]);


printf("Doing a parallel reduction for  N= %d NumberOfBlocks=%d Threads=%d \n",N,Blocks,Threads );

// Define input output 
int *h_idata;
int *g_idata,*g_odata;
int d_output;
h_idata=(int *)malloc( sizeof(int)*N);
for(unsigned int i=0 ;i<N;i++){
	h_idata[i]=i%2;
	//printf("-%d",h_idata[i]);
}
//printf("\n");
cudaMalloc(&g_idata, N*sizeof(int));
cudaMalloc(&g_odata, Blocks*sizeof(int));
cudaMemcpy(g_idata, h_idata, N*sizeof(int), cudaMemcpyHostToDevice);

//reduce0<<<ceil(N/(Blocks*Threads)),Threads>>>(g_idata,g_odata);
Blocks=N/Threads;

int Level=Threads;
while(N/Level>0){
	
	//printf(" Level=%d ,N/Level=%d \n",Level,N/Level );
	if(Level==Threads){
	reduce0<<<N/Level,Threads,Threads*sizeof(int)>>>(g_idata,g_odata);
	}else{
	reduce0<<<N/Level,Threads,Threads*sizeof(int)>>>(g_odata,g_odata);
		
	}
	cudaDeviceSynchronize();
	if(N/Level<Threads){
			reduce0<<<1,N/Level,N/Level*sizeof(int)>>>(g_odata,g_odata);

	}
	Level=Level*Threads;
}

	

cudaMemcpy(&d_output, g_odata, sizeof(int), cudaMemcpyDeviceToHost);

int s=0;
for(unsigned int i=0;i<N;i++){
	s=s+h_idata[i];
}
printf("reduce0 Device %d Host %d\n",d_output,s ); 


 Level=Threads;
while(N/Level>0){
	
	if(Level==Threads){
	reduce1<<<N/Level,Threads,Threads*sizeof(int)>>>(g_idata,g_odata);
	}else{
	reduce1<<<N/Level,Threads,Threads*sizeof(int)>>>(g_odata,g_odata);
		
	}
	cudaDeviceSynchronize();
	if(N/Level<Threads){
			reduce1<<<1,N/Level,N/Level*sizeof(int)>>>(g_odata,g_odata);

	}
	Level=Level*Threads;
}

	

cudaMemcpy(&d_output, g_odata, sizeof(int), cudaMemcpyDeviceToHost);
printf("reduce1 Device %d Host %d\n",d_output,s ); 


 Level=Threads;
while(N/Level>0){
	
	if(Level==Threads){
	reduce2<<<N/Level,Threads,Threads*sizeof(int)>>>(g_idata,g_odata);
	}else{
	reduce2<<<N/Level,Threads,Threads*sizeof(int)>>>(g_odata,g_odata);
		
	}
	cudaDeviceSynchronize();
	if(N/Level<Threads){
			reduce2<<<1,N/Level,N/Level*sizeof(int)>>>(g_odata,g_odata);

	}
	Level=Level*Threads;
}

	

cudaMemcpy(&d_output, g_odata, sizeof(int), cudaMemcpyDeviceToHost);
printf("reduce2 Device %d Host %d\n",d_output,s ); 



 Level=Threads;

while(N/Level>0){
	
	if(Level==Threads){
	reduce3<<<N/(Level*2),Threads,Threads*sizeof(int)>>>(g_idata,g_odata);
	}else {
	reduce3<<<N/(Level*2),Threads,Threads*sizeof(int)>>>(g_odata,g_odata);
		
	}
	cudaDeviceSynchronize();
	Level=Level*2;
	if(N/Level<=Threads){
			reduce3<<<1,N/(Level*2),N/(Level*2)*sizeof(int)>>>(g_odata,g_odata);

	}
	Level=Level*Threads;
}

	

cudaMemcpy(&d_output, g_odata, sizeof(int), cudaMemcpyDeviceToHost);
printf("reduce3 Device %d Host %d\n",d_output,s ); 


 Level=Threads;

while(N/Level>0){
	
	if(Level==Threads){
	reduce4<<<N/(Level*2),Threads,Threads*sizeof(int)>>>(g_idata,g_odata);
	}else {
	reduce4<<<N/(Level*2),Threads,Threads*sizeof(int)>>>(g_odata,g_odata);
		
	}
	cudaDeviceSynchronize();
	Level=Level*2;
	if(N/Level<=Threads){
			reduce4<<<1,N/(Level*2),N/(Level*2)*sizeof(int)>>>(g_odata,g_odata);

	}
	Level=Level*Threads;
}

	

cudaMemcpy(&d_output, g_odata, sizeof(int), cudaMemcpyDeviceToHost);
printf("reduce4 Device %d Host %d\n",d_output,s ); 


/*
 Level=Threads;

while(N/Level>0){
	
	if(Level==Threads){
	switch (Threads)
	{
		case 512:
			reduce5<512><<< N/(Level*2), Threads,Threads*sizeof(int) >>>(g_idata, g_odata);
			break;
		case 256:
			reduce5<256><<< N/(Level*2), Threads,Threads*sizeof(int) >>>(g_idata, g_odata); 
			break;
		case 128:
			reduce5<128><<< N/(Level*2), Threads,Threads*sizeof(int) >>>(g_idata, g_odata);
			break;
		case 64:
			reduce5< 64><<<  N/(Level*2), Threads,Threads*sizeof(int) >>>(g_idata, g_odata);
			break;
		case 32:
			reduce5< 32><<<N/(Level*2), Threads,Threads*sizeof(int) >>>(g_idata, g_odata);
			break;
		case 16:
			reduce5< 16><<<N/(Level*2), Threads,Threads*sizeof(int) >>>(g_idata, g_odata);
			break;
		case  8:
			reduce5<  8><<<N/(Level*2), Threads,Threads*sizeof(int) >>>(g_idata, g_odata);
			break;
		case  4:
			reduce5<  4><<<N/(Level*2), Threads,Threads*sizeof(int) >>>(g_idata, g_odata);
			break;
		case  2:
			reduce5< 2><<<N/(Level*2), Threads,Threads*sizeof(int) >>>(g_idata, g_odata);
			break;
		case  1:
			reduce5<  1><<<N/(Level*2), Threads,Threads*sizeof(int) >>>(g_idata, g_odata);
			 break;
			}
	}else {
		switch (Threads)
	{
		case 512:
			reduce5<512><<<N/(Level*2), Threads,Threads*sizeof(int) >>>(g_odata, g_odata);
			break;
		case 256:
			reduce5<256><<<N/(Level*2), Threads,Threads*sizeof(int) >>>(g_odata, g_odata); 
			break;
		case 128:
			reduce5<128><<<N/(Level*2), Threads,Threads*sizeof(int) >>>(g_odata, g_odata);
			break;
		case 64:
			reduce5< 64><<<N/(Level*2), Threads,Threads*sizeof(int) >>>(g_odata, g_odata);
			break;
		case 32:
			reduce5< 32><<<N/(Level*2), Threads,Threads*sizeof(int) >>>(g_odata, g_odata);
			break;
		case 16:
			reduce5< 16><<<N/(Level*2), Threads,Threads*sizeof(int) >>>(g_odata, g_odata);
			break;
		case  8:
			reduce5<  8><<<N/(Level*2), Threads,Threads*sizeof(int) >>>(g_odata, g_odata);
			break;
		case  4:
			reduce5<  4><<<N/(Level*2), Threads,Threads*sizeof(int) >>>(g_odata, g_odata);
			break;
		case  2:
			reduce5< 2><<<N/(Level*2), Threads,Threads*sizeof(int) >>>(g_odata, g_odata);
			break;
		case  1:
			reduce5<  1><<<N/(Level*2), Threads,Threads*sizeof(int) >>>(g_odata, g_odata);
			 break;
			}
		
	}
	cudaDeviceSynchronize();
	Level=Level*2;
	if(N/Level<=Threads){
		switch (N/(Level*2))
	{
		case 512:
			reduce5<512><<<1, N/(Level*2),N/(Level*2)*sizeof(int) >>>(g_odata, g_odata);
			break;
		case 256:
			reduce5<256><<<1, N/(Level*2),N/(Level*2)*sizeof(int) >>>(g_odata, g_odata); 
			break;
		case 128:
			reduce5<128><<<1, N/(Level*2),N/(Level*2)*sizeof(int) >>>(g_odata, g_odata);
			break;
		case 64:
			reduce5< 64><<<1, N/(Level*2),N/(Level*2)*sizeof(int) >>>(g_odata, g_odata);
			break;
		case 32:
			reduce5< 32><<<1, N/(Level*2),N/(Level*2)*sizeof(int) >>>(g_odata, g_odata);
			break;
		case 16:
			reduce5< 16><<<1, N/(Level*2),N/(Level*2)*sizeof(int) >>>(g_odata, g_odata);
			break;
		case  8:
			reduce5<  8><<<1, N/(Level*2),N/(Level*2)*sizeof(int) >>>(g_odata, g_odata);
			break;
		case  4:
			reduce5<  4><<<1, N/(Level*2),N/(Level*2)*sizeof(int) >>>(g_odata, g_odata);
			break;
		case  2:
			reduce5< 2><<<1, N/(Level*2),N/(Level*2)*sizeof(int) >>>(g_odata, g_odata);
			break;
		case  1:
			reduce5<  1><<<1, N/(Level*2),N/(Level*2)*sizeof(int) >>>(g_odata, g_odata);
			 break;
			}
			reduce4<<<1,N/(Level*2),N/(Level*2)*sizeof(int)>>>(g_odata,g_odata);

	}
	Level=Level*Threads;
}

	

cudaMemcpy(&d_output, g_odata, sizeof(int), cudaMemcpyDeviceToHost);
printf("reduce5 Device %d Host %d\n",d_output,s ); 
*/





return 0;
}
	.file	"tmpxft_002cb4b5_00000000-6_sum_reduce.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2031:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z10warpReducePVii
	.type	_Z10warpReducePVii, @function
_Z10warpReducePVii:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2027:
	.size	_Z10warpReducePVii, .-_Z10warpReducePVii
	.globl	_Z28__device_stub__Z7reduce0PiS_PiS_
	.type	_Z28__device_stub__Z7reduce0PiS_PiS_, @function
_Z28__device_stub__Z7reduce0PiS_PiS_:
.LFB2053:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 8(%rsp)
	leaq	32(%rsp), %rcx
	leaq	24(%rsp), %rdx
	movq	%rsi, (%rsp)
	leaq	40(%rsp), %rdi
	leaq	52(%rsp), %rsi
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 48(%rsp)
	movq	%rax, 88(%rsp)
	movq	%rsp, %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L4
	pushq	32(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7reduce0PiS_(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 144
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	104(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L4:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L6
	call	__stack_chk_fail@PLT
.L6:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2053:
	.size	_Z28__device_stub__Z7reduce0PiS_PiS_, .-_Z28__device_stub__Z7reduce0PiS_PiS_
	.globl	_Z7reduce0PiS_
	.type	_Z7reduce0PiS_, @function
_Z7reduce0PiS_:
.LFB2054:
	.cfi_startproc
	endbr64
	jmp	_Z28__device_stub__Z7reduce0PiS_PiS_
	.cfi_endproc
.LFE2054:
	.size	_Z7reduce0PiS_, .-_Z7reduce0PiS_
	.globl	_Z28__device_stub__Z7reduce1PiS_PiS_
	.type	_Z28__device_stub__Z7reduce1PiS_PiS_, @function
_Z28__device_stub__Z7reduce1PiS_PiS_:
.LFB2055:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 8(%rsp)
	leaq	32(%rsp), %rcx
	leaq	24(%rsp), %rdx
	movq	%rsi, (%rsp)
	leaq	40(%rsp), %rdi
	leaq	52(%rsp), %rsi
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 48(%rsp)
	movq	%rax, 88(%rsp)
	movq	%rsp, %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L10
	pushq	32(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7reduce1PiS_(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 144
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	104(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L10:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L12
	call	__stack_chk_fail@PLT
.L12:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2055:
	.size	_Z28__device_stub__Z7reduce1PiS_PiS_, .-_Z28__device_stub__Z7reduce1PiS_PiS_
	.globl	_Z7reduce1PiS_
	.type	_Z7reduce1PiS_, @function
_Z7reduce1PiS_:
.LFB2056:
	.cfi_startproc
	endbr64
	jmp	_Z28__device_stub__Z7reduce1PiS_PiS_
	.cfi_endproc
.LFE2056:
	.size	_Z7reduce1PiS_, .-_Z7reduce1PiS_
	.globl	_Z28__device_stub__Z7reduce2PiS_PiS_
	.type	_Z28__device_stub__Z7reduce2PiS_PiS_, @function
_Z28__device_stub__Z7reduce2PiS_PiS_:
.LFB2057:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 8(%rsp)
	leaq	32(%rsp), %rcx
	leaq	24(%rsp), %rdx
	movq	%rsi, (%rsp)
	leaq	40(%rsp), %rdi
	leaq	52(%rsp), %rsi
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 48(%rsp)
	movq	%rax, 88(%rsp)
	movq	%rsp, %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L15
	pushq	32(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7reduce2PiS_(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 144
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	104(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L15:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L17
	call	__stack_chk_fail@PLT
.L17:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2057:
	.size	_Z28__device_stub__Z7reduce2PiS_PiS_, .-_Z28__device_stub__Z7reduce2PiS_PiS_
	.globl	_Z7reduce2PiS_
	.type	_Z7reduce2PiS_, @function
_Z7reduce2PiS_:
.LFB2058:
	.cfi_startproc
	endbr64
	jmp	_Z28__device_stub__Z7reduce2PiS_PiS_
	.cfi_endproc
.LFE2058:
	.size	_Z7reduce2PiS_, .-_Z7reduce2PiS_
	.globl	_Z28__device_stub__Z7reduce3PiS_PiS_
	.type	_Z28__device_stub__Z7reduce3PiS_PiS_, @function
_Z28__device_stub__Z7reduce3PiS_PiS_:
.LFB2059:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 8(%rsp)
	leaq	32(%rsp), %rcx
	leaq	24(%rsp), %rdx
	movq	%rsi, (%rsp)
	leaq	40(%rsp), %rdi
	leaq	52(%rsp), %rsi
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 48(%rsp)
	movq	%rax, 88(%rsp)
	movq	%rsp, %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L20
	pushq	32(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7reduce3PiS_(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 144
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	104(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L20:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L22
	call	__stack_chk_fail@PLT
.L22:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2059:
	.size	_Z28__device_stub__Z7reduce3PiS_PiS_, .-_Z28__device_stub__Z7reduce3PiS_PiS_
	.globl	_Z7reduce3PiS_
	.type	_Z7reduce3PiS_, @function
_Z7reduce3PiS_:
.LFB2060:
	.cfi_startproc
	endbr64
	jmp	_Z28__device_stub__Z7reduce3PiS_PiS_
	.cfi_endproc
.LFE2060:
	.size	_Z7reduce3PiS_, .-_Z7reduce3PiS_
	.globl	_Z28__device_stub__Z7reduce4PiS_PiS_
	.type	_Z28__device_stub__Z7reduce4PiS_PiS_, @function
_Z28__device_stub__Z7reduce4PiS_PiS_:
.LFB2061:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 8(%rsp)
	leaq	32(%rsp), %rcx
	leaq	24(%rsp), %rdx
	movq	%rsi, (%rsp)
	leaq	40(%rsp), %rdi
	leaq	52(%rsp), %rsi
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 48(%rsp)
	movq	%rax, 88(%rsp)
	movq	%rsp, %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L25
	pushq	32(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7reduce4PiS_(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 144
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	104(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L25:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L27
	call	__stack_chk_fail@PLT
.L27:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2061:
	.size	_Z28__device_stub__Z7reduce4PiS_PiS_, .-_Z28__device_stub__Z7reduce4PiS_PiS_
	.globl	_Z7reduce4PiS_
	.type	_Z7reduce4PiS_, @function
_Z7reduce4PiS_:
.LFB2062:
	.cfi_startproc
	endbr64
	jmp	_Z28__device_stub__Z7reduce4PiS_PiS_
	.cfi_endproc
.LFE2062:
	.size	_Z7reduce4PiS_, .-_Z7reduce4PiS_
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"Doing a parallel reduction for  N= %d NumberOfBlocks=%d Threads=%d \n"
.LC1:
	.string	"reduce0 Device %d Host %d\n"
.LC2:
	.string	"reduce1 Device %d Host %d\n"
.LC3:
	.string	"reduce2 Device %d Host %d\n"
.LC4:
	.string	"reduce3 Device %d Host %d\n"
.LC5:
	.string	"reduce4 Device %d Host %d\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2028:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movq	%rsi, %rbp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movl	$1, %ebx
	subq	$88, %rsp
	.cfi_def_cfa_offset 144
	movq	8(%rsi), %rdi
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	xorl	%eax, %eax
	call	atoi@PLT
	movq	16(%rbp), %rdi
	movl	%eax, %ecx
	sall	%cl, %ebx
	call	atoi@PLT
	movq	24(%rbp), %rdi
	movslq	%ebx, %r13
	movl	%eax, %r12d
	salq	$2, %r13
	call	atoi@PLT
	movl	%r12d, %ecx
	movl	%ebx, %edx
	movl	$2, %edi
	movl	%eax, %r8d
	leaq	.LC0(%rip), %rsi
	movl	%eax, %ebp
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movq	%r13, %rdi
	call	malloc@PLT
	movq	%rax, %r14
	xorl	%eax, %eax
.L31:
	cmpl	%ebx, %eax
	jnb	.L82
	movl	%eax, %edx
	andl	$1, %edx
	movl	%edx, (%r14,%rax,4)
	incq	%rax
	jmp	.L31
.L82:
	movq	%r13, %rsi
	leaq	32(%rsp), %rdi
	movl	%ebp, %r15d
	call	cudaMalloc@PLT
	movslq	%r12d, %rsi
	leaq	40(%rsp), %rdi
	salq	$2, %rsi
	call	cudaMalloc@PLT
	movq	32(%rsp), %rdi
	movq	%r13, %rdx
	movq	%r14, %rsi
	movabsq	$4294967297, %r13
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	movslq	%ebp, %rax
	salq	$2, %rax
	movq	%rax, (%rsp)
.L33:
	movl	%ebx, %eax
	cltd
	idivl	%r15d
	movslq	%eax, %r12
	testl	%r12d, %r12d
	jle	.L83
	cmpl	%ebp, %r15d
	jne	.L34
	movq	%r13, 64(%rsp)
	movq	(%rsp), %r8
	xorl	%r9d, %r9d
	movq	%r13, 52(%rsp)
	movl	68(%rsp), %ecx
	movl	%r15d, 60(%rsp)
	movl	56(%rsp), %esi
	movl	%r12d, 48(%rsp)
	movq	60(%rsp), %rdx
	movq	48(%rsp), %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L36
	movq	40(%rsp), %rsi
	movq	32(%rsp), %rdi
	jmp	.L77
.L34:
	movq	%r13, 64(%rsp)
	movq	(%rsp), %r8
	xorl	%r9d, %r9d
	movq	%r13, 52(%rsp)
	movl	68(%rsp), %ecx
	movl	%ebp, 60(%rsp)
	movl	56(%rsp), %esi
	movl	%r12d, 48(%rsp)
	movq	60(%rsp), %rdx
	movq	48(%rsp), %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L36
	movq	40(%rsp), %rdi
	movq	%rdi, %rsi
.L77:
	call	_Z28__device_stub__Z7reduce0PiS_PiS_
.L36:
	call	cudaDeviceSynchronize@PLT
	cmpl	%ebp, %r12d
	jge	.L38
	movq	%r13, 64(%rsp)
	movl	68(%rsp), %ecx
	xorl	%r9d, %r9d
	movq	%r13, %rdi
	movl	%r12d, 60(%rsp)
	movq	60(%rsp), %rdx
	movl	$1, %esi
	leaq	0(,%r12,4), %r8
	movq	%r13, 48(%rsp)
	movl	$1, 56(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L38
	movq	40(%rsp), %rdi
	movq	%rdi, %rsi
	call	_Z28__device_stub__Z7reduce0PiS_PiS_
.L38:
	imull	%ebp, %r15d
	jmp	.L33
.L83:
	leaq	28(%rsp), %rax
	movq	40(%rsp), %rsi
	movl	$2, %ecx
	xorl	%r13d, %r13d
	movl	$4, %edx
	movq	%rax, %rdi
	movq	%rax, 8(%rsp)
	call	cudaMemcpy@PLT
	xorl	%eax, %eax
.L41:
	cmpl	%ebx, %eax
	jnb	.L84
	addl	(%r14,%rax,4), %r13d
	incq	%rax
	jmp	.L41
.L84:
	movl	28(%rsp), %edx
	movl	%r13d, %ecx
	leaq	.LC1(%rip), %rsi
	xorl	%eax, %eax
	movl	$2, %edi
	movl	%ebp, %r15d
	movabsq	$4294967297, %r14
	call	__printf_chk@PLT
.L43:
	movl	%ebx, %eax
	cltd
	idivl	%r15d
	movslq	%eax, %r12
	testl	%r12d, %r12d
	jle	.L85
	cmpl	%ebp, %r15d
	jne	.L44
	movq	%r14, 64(%rsp)
	movq	(%rsp), %r8
	xorl	%r9d, %r9d
	movq	%r14, 52(%rsp)
	movl	68(%rsp), %ecx
	movl	%r15d, 60(%rsp)
	movl	56(%rsp), %esi
	movl	%r12d, 48(%rsp)
	movq	60(%rsp), %rdx
	movq	48(%rsp), %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L46
	movq	40(%rsp), %rsi
	movq	32(%rsp), %rdi
	jmp	.L78
.L44:
	movq	%r14, 64(%rsp)
	movq	(%rsp), %r8
	xorl	%r9d, %r9d
	movq	%r14, 52(%rsp)
	movl	68(%rsp), %ecx
	movl	%ebp, 60(%rsp)
	movl	56(%rsp), %esi
	movl	%r12d, 48(%rsp)
	movq	60(%rsp), %rdx
	movq	48(%rsp), %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L46
	movq	40(%rsp), %rdi
	movq	%rdi, %rsi
.L78:
	call	_Z28__device_stub__Z7reduce1PiS_PiS_
.L46:
	call	cudaDeviceSynchronize@PLT
	cmpl	%ebp, %r12d
	jge	.L48
	movq	%r14, 64(%rsp)
	movl	68(%rsp), %ecx
	xorl	%r9d, %r9d
	movq	%r14, %rdi
	movl	%r12d, 60(%rsp)
	movq	60(%rsp), %rdx
	movl	$1, %esi
	leaq	0(,%r12,4), %r8
	movq	%r14, 48(%rsp)
	movl	$1, 56(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L48
	movq	40(%rsp), %rdi
	movq	%rdi, %rsi
	call	_Z28__device_stub__Z7reduce1PiS_PiS_
.L48:
	imull	%ebp, %r15d
	jmp	.L43
.L85:
	movq	40(%rsp), %rsi
	movq	8(%rsp), %rdi
	movl	$2, %ecx
	movl	%ebp, %r15d
	movabsq	$4294967297, %r14
	movl	$4, %edx
	call	cudaMemcpy@PLT
	movl	28(%rsp), %edx
	movl	%r13d, %ecx
	xorl	%eax, %eax
	leaq	.LC2(%rip), %rsi
	movl	$2, %edi
	call	__printf_chk@PLT
.L51:
	movl	%ebx, %eax
	cltd
	idivl	%r15d
	movslq	%eax, %r12
	testl	%r12d, %r12d
	jle	.L86
	cmpl	%ebp, %r15d
	jne	.L52
	movq	%r14, 64(%rsp)
	movq	(%rsp), %r8
	xorl	%r9d, %r9d
	movq	%r14, 52(%rsp)
	movl	68(%rsp), %ecx
	movl	%r15d, 60(%rsp)
	movl	56(%rsp), %esi
	movl	%r12d, 48(%rsp)
	movq	60(%rsp), %rdx
	movq	48(%rsp), %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L54
	movq	40(%rsp), %rsi
	movq	32(%rsp), %rdi
	jmp	.L79
.L52:
	movq	%r14, 64(%rsp)
	movq	(%rsp), %r8
	xorl	%r9d, %r9d
	movq	%r14, 52(%rsp)
	movl	68(%rsp), %ecx
	movl	%ebp, 60(%rsp)
	movl	56(%rsp), %esi
	movl	%r12d, 48(%rsp)
	movq	60(%rsp), %rdx
	movq	48(%rsp), %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L54
	movq	40(%rsp), %rdi
	movq	%rdi, %rsi
.L79:
	call	_Z28__device_stub__Z7reduce2PiS_PiS_
.L54:
	call	cudaDeviceSynchronize@PLT
	cmpl	%ebp, %r12d
	jge	.L56
	movq	%r14, 64(%rsp)
	movl	68(%rsp), %ecx
	xorl	%r9d, %r9d
	movq	%r14, %rdi
	movl	%r12d, 60(%rsp)
	movq	60(%rsp), %rdx
	movl	$1, %esi
	leaq	0(,%r12,4), %r8
	movq	%r14, 48(%rsp)
	movl	$1, 56(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L56
	movq	40(%rsp), %rdi
	movq	%rdi, %rsi
	call	_Z28__device_stub__Z7reduce2PiS_PiS_
.L56:
	imull	%ebp, %r15d
	jmp	.L51
.L86:
	movq	40(%rsp), %rsi
	movq	8(%rsp), %rdi
	movl	$2, %ecx
	movl	%ebp, %r12d
	movabsq	$4294967297, %r14
	movl	$4, %edx
	call	cudaMemcpy@PLT
	movl	28(%rsp), %edx
	movl	%r13d, %ecx
	xorl	%eax, %eax
	leaq	.LC3(%rip), %rsi
	movl	$2, %edi
	call	__printf_chk@PLT
.L59:
	movl	%ebx, %eax
	cltd
	idivl	%r12d
	testl	%eax, %eax
	jle	.L87
	leal	(%r12,%r12), %r15d
	cmpl	%ebp, %r12d
	jne	.L60
	movl	%ebx, %eax
	movq	%r14, 64(%rsp)
	movq	(%rsp), %r8
	xorl	%r9d, %r9d
	cltd
	movq	%r14, 52(%rsp)
	movl	68(%rsp), %ecx
	idivl	%r15d
	movl	%r12d, 60(%rsp)
	movl	56(%rsp), %esi
	movq	60(%rsp), %rdx
	movl	%eax, 48(%rsp)
	movq	48(%rsp), %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L62
	movq	40(%rsp), %rsi
	movq	32(%rsp), %rdi
	jmp	.L80
.L60:
	movl	%ebx, %eax
	movq	%r14, 64(%rsp)
	movq	(%rsp), %r8
	xorl	%r9d, %r9d
	cltd
	movq	%r14, 52(%rsp)
	movl	68(%rsp), %ecx
	idivl	%r15d
	movl	%ebp, 60(%rsp)
	movl	56(%rsp), %esi
	movq	60(%rsp), %rdx
	movl	%eax, 48(%rsp)
	movq	48(%rsp), %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L62
	movq	40(%rsp), %rdi
	movq	%rdi, %rsi
.L80:
	call	_Z28__device_stub__Z7reduce3PiS_PiS_
.L62:
	call	cudaDeviceSynchronize@PLT
	movl	%ebx, %eax
	cltd
	idivl	%r15d
	cmpl	%ebp, %eax
	jg	.L64
	movl	%ebx, %eax
	sall	$2, %r12d
	movq	%r14, 64(%rsp)
	movl	68(%rsp), %ecx
	cltd
	xorl	%r9d, %r9d
	movq	%r14, %rdi
	movl	$1, %esi
	idivl	%r12d
	movq	%r14, 48(%rsp)
	movl	$1, 56(%rsp)
	movl	%eax, 60(%rsp)
	cltq
	movq	60(%rsp), %rdx
	leaq	0(,%rax,4), %r8
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L64
	movq	40(%rsp), %rdi
	movq	%rdi, %rsi
	call	_Z28__device_stub__Z7reduce3PiS_PiS_
.L64:
	imull	%ebp, %r15d
	movl	%r15d, %r12d
	jmp	.L59
.L87:
	movq	40(%rsp), %rsi
	movq	8(%rsp), %rdi
	movl	$2, %ecx
	movl	%ebp, %r12d
	movabsq	$4294967297, %r14
	movl	$4, %edx
	call	cudaMemcpy@PLT
	movl	28(%rsp), %edx
	movl	%r13d, %ecx
	xorl	%eax, %eax
	leaq	.LC4(%rip), %rsi
	movl	$2, %edi
	call	__printf_chk@PLT
.L67:
	movl	%ebx, %eax
	cltd
	idivl	%r12d
	testl	%eax, %eax
	jle	.L88
	leal	(%r12,%r12), %r15d
	cmpl	%ebp, %r12d
	jne	.L68
	movl	%ebx, %eax
	movq	%r14, 64(%rsp)
	movq	(%rsp), %r8
	xorl	%r9d, %r9d
	cltd
	movq	%r14, 52(%rsp)
	movl	68(%rsp), %ecx
	idivl	%r15d
	movl	%r12d, 60(%rsp)
	movl	56(%rsp), %esi
	movq	60(%rsp), %rdx
	movl	%eax, 48(%rsp)
	movq	48(%rsp), %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L70
	movq	40(%rsp), %rsi
	movq	32(%rsp), %rdi
	jmp	.L81
.L68:
	movl	%ebx, %eax
	movq	%r14, 64(%rsp)
	movq	(%rsp), %r8
	xorl	%r9d, %r9d
	cltd
	movq	%r14, 52(%rsp)
	movl	68(%rsp), %ecx
	idivl	%r15d
	movl	%ebp, 60(%rsp)
	movl	56(%rsp), %esi
	movq	60(%rsp), %rdx
	movl	%eax, 48(%rsp)
	movq	48(%rsp), %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L70
	movq	40(%rsp), %rdi
	movq	%rdi, %rsi
.L81:
	call	_Z28__device_stub__Z7reduce4PiS_PiS_
.L70:
	call	cudaDeviceSynchronize@PLT
	movl	%ebx, %eax
	cltd
	idivl	%r15d
	cmpl	%ebp, %eax
	jg	.L72
	movl	%ebx, %eax
	sall	$2, %r12d
	movq	%r14, 64(%rsp)
	movl	68(%rsp), %ecx
	cltd
	xorl	%r9d, %r9d
	movq	%r14, %rdi
	movl	$1, %esi
	idivl	%r12d
	movq	%r14, 48(%rsp)
	movl	$1, 56(%rsp)
	movl	%eax, 60(%rsp)
	cltq
	movq	60(%rsp), %rdx
	leaq	0(,%rax,4), %r8
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L72
	movq	40(%rsp), %rdi
	movq	%rdi, %rsi
	call	_Z28__device_stub__Z7reduce4PiS_PiS_
.L72:
	imull	%ebp, %r15d
	movl	%r15d, %r12d
	jmp	.L67
.L88:
	movq	40(%rsp), %rsi
	movq	8(%rsp), %rdi
	movl	$2, %ecx
	movl	$4, %edx
	call	cudaMemcpy@PLT
	movl	28(%rsp), %edx
	xorl	%eax, %eax
	movl	%r13d, %ecx
	leaq	.LC5(%rip), %rsi
	movl	$2, %edi
	call	__printf_chk@PLT
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L75
	call	__stack_chk_fail@PLT
.L75:
	addq	$88, %rsp
	.cfi_def_cfa_offset 56
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2028:
	.size	main, .-main
	.section	.rodata.str1.1
.LC6:
	.string	"_Z7reduce4PiS_"
.LC7:
	.string	"_Z7reduce3PiS_"
.LC8:
	.string	"_Z7reduce2PiS_"
.LC9:
	.string	"_Z7reduce1PiS_"
.LC10:
	.string	"_Z7reduce0PiS_"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2064:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC6(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z7reduce4PiS_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC7(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z7reduce3PiS_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC8(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z7reduce2PiS_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC9(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z7reduce1PiS_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC10(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z7reduce0PiS_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2064:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <sys/time.h>
#define blockSize 128
__global__ void reduce0(int *g_idata,int *g_odata){
extern __shared__ int sdata[];

//each thread loads one element from global to shared mem
unsigned int tid = threadIdx.x;
unsigned int i = blockIdx.x*blockDim.x+threadIdx.x;
sdata[tid]=g_idata[i];
//printf("%d- ",sdata[tid]);
__syncthreads();
//if(threadIdx.x==0){
//printf("\n");}

//do reduction in shared mem 
for(unsigned int s=1 ;s<blockDim.x; s*=2){
	if(tid%(2*s)==0){
		//if(tid==0){
		//printf("Level %d Thread %d Data %d + Data %d \n",s,tid,sdata[tid],sdata[tid+s]);}
		sdata[tid]+=sdata[tid+s];
	}
	__syncthreads();
}
// write the result for this block to global mem
if(tid ==0){ 
	g_odata[blockIdx.x]=sdata[0];
}

}

__global__ void reduce1(int *g_idata,int *g_odata){
extern __shared__ int sdata[];

//each thread loads one element from global to shared mem
unsigned int tid = threadIdx.x;
unsigned int i = blockIdx.x*blockDim.x+threadIdx.x;
sdata[tid]=g_idata[i];
//printf("%d- ",sdata[tid]);
__syncthreads();
//if(threadIdx.x==0){
//printf("\n");}

//do reduction in shared mem 
for(unsigned int s=1 ;s<blockDim.x; s*=2){
	int index=2*s*tid;
	if(index<blockDim.x){
		sdata[index]+=sdata[index+s];
	}
	__syncthreads();
}
// write the result for this block to global mem
if(tid ==0){ 
	g_odata[blockIdx.x]=sdata[0];
}

}

__global__ void reduce2(int *g_idata,int *g_odata){
extern __shared__ int sdata[];

//each thread loads one element from global to shared mem
unsigned int tid = threadIdx.x;
unsigned int i = blockIdx.x*blockDim.x+threadIdx.x;
sdata[tid]=g_idata[i];
//printf("%d- ",sdata[tid]);
__syncthreads();
//if(threadIdx.x==0){
//printf("\n");}

//do reduction in shared mem 
for(unsigned int s=blockDim.x/2; s>0;s>>=1){
	if(tid<s){
		sdata[tid]+=sdata[tid+s];
	}
	__syncthreads();
}
// write the result for this block to global mem
if(tid ==0){ 
	g_odata[blockIdx.x]=sdata[0];
}

}


__global__ void reduce3(int *g_idata,int *g_odata){
extern __shared__ int sdata[];

//each thread loads one element from global to shared mem
unsigned int tid = threadIdx.x;
unsigned int i = blockIdx.x*(blockDim.x*2)+threadIdx.x;
sdata[tid]=g_idata[i]+g_idata[i+blockDim.x];
//printf("%d- ",sdata[tid]);
__syncthreads();
//if(threadIdx.x==0){
//printf("\n");}

//do reduction in shared mem 
for(unsigned int s=blockDim.x/2; s>0;s>>=1){
	if(tid<s){
		sdata[tid]+=sdata[tid+s];
	}
	__syncthreads();
}
// write the result for this block to global mem
if(tid ==0){ 
	g_odata[blockIdx.x]=sdata[0];
}

}

__device__ void warpReduce(volatile int* sdata,int tid ){
	sdata[tid]+=sdata[tid +32];
	sdata[tid]+=sdata[tid +16];
	sdata[tid]+=sdata[tid +8];
	sdata[tid]+=sdata[tid +4];
	sdata[tid]+=sdata[tid +2];
	sdata[tid]+=sdata[tid +1];
}

__global__ void reduce4(int *g_idata,int *g_odata){
extern __shared__ int sdata[];

//each thread loads one element from global to shared mem
unsigned int tid = threadIdx.x;
unsigned int i = blockIdx.x*(blockDim.x*2)+threadIdx.x;
sdata[tid]=g_idata[i]+g_idata[i+blockDim.x];
//printf("%d- ",sdata[tid]);
__syncthreads();
//if(threadIdx.x==0){
//printf("\n");}

//do reduction in shared mem 
for(unsigned int s=blockDim.x/2; s>32;s>>=1){
	if(tid<s){
		sdata[tid]+=sdata[tid+s];
	}
	__syncthreads();
}
if(tid<32){ warpReduce(sdata,tid);}
// write the result for this block to global mem
if(tid ==0){ 
	g_odata[blockIdx.x]=sdata[0];
}

}
/*
template <unsigned int blockSize> 
__device__ void warpReducenew(volatile int* sdata,int tid ){
	if(blockSize>=64) sdata[tid]+=sdata[tid +32];
	if(blockSize>=32) sdata[tid]+=sdata[tid +16];
	if(blockSize>=16) sdata[tid]+=sdata[tid +8];
	if(blockSize>=8) sdata[tid]+=sdata[tid +4];
	if(blockSize>=4) sdata[tid]+=sdata[tid +2];
	if(blockSize>=2) sdata[tid]+=sdata[tid +1];
}


template <unsigned int blockSize>
__global__ void reduce5(int *g_idata,int * g_odata){

extern __shared__ int sdata[];
unsigned int tid = threadIdx.x;
unsigned int i = blockIdx.x*(blockDim.x*2)+threadIdx.x;
sdata[tid]=g_idata[i]+g_idata[i+blockDim.x];
__syncthreads();

if(blockSize>=512){
	if(tid<256 ){sdata[tid]+=sdata[tid+256];}
	__syncthreads();
}
if(blockSize>=256){
	if(tid<128 ){sdata[tid]+=sdata[tid+128];}
	__syncthreads();
}
if(blockSize>=128){
	if(tid<64 ){sdata[tid]+=sdata[tid+64];}
	__syncthreads();
}

if(tid<32){ warpReducenew<blockSize>(sdata,tid);}
// write the result for this block to global mem
if(tid ==0){ 
	g_odata[blockIdx.x]=sdata[0];
}



}

template <unsigned int blockSize>
__device__ void warpReduce(volatile int *sdata, unsigned int tid) 
{
	if (blockSize >=  64) sdata[tid] += sdata[tid + 32];
	if (blockSize >=  32) sdata[tid] += sdata[tid + 16];
	if (blockSize >=  16) sdata[tid] += sdata[tid +  8];
	if(blockSize >=   8) sdata[tid] += sdata[tid +  4];
	if (blockSize >=   4) sdata[tid] += sdata[tid +  2];
	if (blockSize >=   2) sdata[tid] += sdata[tid +  1];}
template <unsigned int blockSize>
__global__ voidreduce6(int *g_idata, int *g_odata, unsigned int n)
 {extern __shared__ int sdata[];

 unsigned int tid = threadIdx.x;
 unsigned int i = blockIdx.x*(blockSize*2) + tid;
 unsigned int gridSize = blockSize*2*gridDim.x;

 sdata[tid] = 0;

 while (i < n)
 	{
 		sdata[tid] += g_idata[i] + g_idata[i+blockSize];  i += gridSize;
 		  }
 __syncthreads();

 if (blockSize >= 512) { if (tid < 256) { sdata[tid] += sdata[tid + 256]; } __syncthreads(); }
 if (blockSize >= 256) { if (tid < 128) { sdata[tid] += sdata[tid + 128]; } __syncthreads(); }
 if (blockSize >= 128) { if (tid <  64) { sdata[tid] += sdata[tid +  64]; } __syncthreads(); }
 if (tid < 32)warpReduce(sdata, tid);
 if (tid == 0) g_odata[blockIdx.x] = sdata[0];
}
*/




int main(int argc, char **argv) {
int N= 1<<atoi(argv[1]);
int Blocks= atoi(argv[2]);
int Threads= atoi(argv[3]);


printf("Doing a parallel reduction for  N= %d NumberOfBlocks=%d Threads=%d \n",N,Blocks,Threads );

// Define input output 
int *h_idata;
int *g_idata,*g_odata;
int d_output;
h_idata=(int *)malloc( sizeof(int)*N);
for(unsigned int i=0 ;i<N;i++){
	h_idata[i]=i%2;
	//printf("-%d",h_idata[i]);
}
//printf("\n");
hipMalloc(&g_idata, N*sizeof(int));
hipMalloc(&g_odata, Blocks*sizeof(int));
hipMemcpy(g_idata, h_idata, N*sizeof(int), hipMemcpyHostToDevice);

//reduce0<<<ceil(N/(Blocks*Threads)),Threads>>>(g_idata,g_odata);
Blocks=N/Threads;

int Level=Threads;
while(N/Level>0){
	
	//printf(" Level=%d ,N/Level=%d \n",Level,N/Level );
	if(Level==Threads){
	reduce0<<<N/Level,Threads,Threads*sizeof(int)>>>(g_idata,g_odata);
	}else{
	reduce0<<<N/Level,Threads,Threads*sizeof(int)>>>(g_odata,g_odata);
		
	}
	hipDeviceSynchronize();
	if(N/Level<Threads){
			reduce0<<<1,N/Level,N/Level*sizeof(int)>>>(g_odata,g_odata);

	}
	Level=Level*Threads;
}

	

hipMemcpy(&d_output, g_odata, sizeof(int), hipMemcpyDeviceToHost);

int s=0;
for(unsigned int i=0;i<N;i++){
	s=s+h_idata[i];
}
printf("reduce0 Device %d Host %d\n",d_output,s ); 


 Level=Threads;
while(N/Level>0){
	
	if(Level==Threads){
	reduce1<<<N/Level,Threads,Threads*sizeof(int)>>>(g_idata,g_odata);
	}else{
	reduce1<<<N/Level,Threads,Threads*sizeof(int)>>>(g_odata,g_odata);
		
	}
	hipDeviceSynchronize();
	if(N/Level<Threads){
			reduce1<<<1,N/Level,N/Level*sizeof(int)>>>(g_odata,g_odata);

	}
	Level=Level*Threads;
}

	

hipMemcpy(&d_output, g_odata, sizeof(int), hipMemcpyDeviceToHost);
printf("reduce1 Device %d Host %d\n",d_output,s ); 


 Level=Threads;
while(N/Level>0){
	
	if(Level==Threads){
	reduce2<<<N/Level,Threads,Threads*sizeof(int)>>>(g_idata,g_odata);
	}else{
	reduce2<<<N/Level,Threads,Threads*sizeof(int)>>>(g_odata,g_odata);
		
	}
	hipDeviceSynchronize();
	if(N/Level<Threads){
			reduce2<<<1,N/Level,N/Level*sizeof(int)>>>(g_odata,g_odata);

	}
	Level=Level*Threads;
}

	

hipMemcpy(&d_output, g_odata, sizeof(int), hipMemcpyDeviceToHost);
printf("reduce2 Device %d Host %d\n",d_output,s ); 



 Level=Threads;

while(N/Level>0){
	
	if(Level==Threads){
	reduce3<<<N/(Level*2),Threads,Threads*sizeof(int)>>>(g_idata,g_odata);
	}else {
	reduce3<<<N/(Level*2),Threads,Threads*sizeof(int)>>>(g_odata,g_odata);
		
	}
	hipDeviceSynchronize();
	Level=Level*2;
	if(N/Level<=Threads){
			reduce3<<<1,N/(Level*2),N/(Level*2)*sizeof(int)>>>(g_odata,g_odata);

	}
	Level=Level*Threads;
}

	

hipMemcpy(&d_output, g_odata, sizeof(int), hipMemcpyDeviceToHost);
printf("reduce3 Device %d Host %d\n",d_output,s ); 


 Level=Threads;

while(N/Level>0){
	
	if(Level==Threads){
	reduce4<<<N/(Level*2),Threads,Threads*sizeof(int)>>>(g_idata,g_odata);
	}else {
	reduce4<<<N/(Level*2),Threads,Threads*sizeof(int)>>>(g_odata,g_odata);
		
	}
	hipDeviceSynchronize();
	Level=Level*2;
	if(N/Level<=Threads){
			reduce4<<<1,N/(Level*2),N/(Level*2)*sizeof(int)>>>(g_odata,g_odata);

	}
	Level=Level*Threads;
}

	

hipMemcpy(&d_output, g_odata, sizeof(int), hipMemcpyDeviceToHost);
printf("reduce4 Device %d Host %d\n",d_output,s ); 


/*
 Level=Threads;

while(N/Level>0){
	
	if(Level==Threads){
	switch (Threads)
	{
		case 512:
			reduce5<512><<< N/(Level*2), Threads,Threads*sizeof(int) >>>(g_idata, g_odata);
			break;
		case 256:
			reduce5<256><<< N/(Level*2), Threads,Threads*sizeof(int) >>>(g_idata, g_odata); 
			break;
		case 128:
			reduce5<128><<< N/(Level*2), Threads,Threads*sizeof(int) >>>(g_idata, g_odata);
			break;
		case 64:
			reduce5< 64><<<  N/(Level*2), Threads,Threads*sizeof(int) >>>(g_idata, g_odata);
			break;
		case 32:
			reduce5< 32><<<N/(Level*2), Threads,Threads*sizeof(int) >>>(g_idata, g_odata);
			break;
		case 16:
			reduce5< 16><<<N/(Level*2), Threads,Threads*sizeof(int) >>>(g_idata, g_odata);
			break;
		case  8:
			reduce5<  8><<<N/(Level*2), Threads,Threads*sizeof(int) >>>(g_idata, g_odata);
			break;
		case  4:
			reduce5<  4><<<N/(Level*2), Threads,Threads*sizeof(int) >>>(g_idata, g_odata);
			break;
		case  2:
			reduce5< 2><<<N/(Level*2), Threads,Threads*sizeof(int) >>>(g_idata, g_odata);
			break;
		case  1:
			reduce5<  1><<<N/(Level*2), Threads,Threads*sizeof(int) >>>(g_idata, g_odata);
			 break;
			}
	}else {
		switch (Threads)
	{
		case 512:
			reduce5<512><<<N/(Level*2), Threads,Threads*sizeof(int) >>>(g_odata, g_odata);
			break;
		case 256:
			reduce5<256><<<N/(Level*2), Threads,Threads*sizeof(int) >>>(g_odata, g_odata); 
			break;
		case 128:
			reduce5<128><<<N/(Level*2), Threads,Threads*sizeof(int) >>>(g_odata, g_odata);
			break;
		case 64:
			reduce5< 64><<<N/(Level*2), Threads,Threads*sizeof(int) >>>(g_odata, g_odata);
			break;
		case 32:
			reduce5< 32><<<N/(Level*2), Threads,Threads*sizeof(int) >>>(g_odata, g_odata);
			break;
		case 16:
			reduce5< 16><<<N/(Level*2), Threads,Threads*sizeof(int) >>>(g_odata, g_odata);
			break;
		case  8:
			reduce5<  8><<<N/(Level*2), Threads,Threads*sizeof(int) >>>(g_odata, g_odata);
			break;
		case  4:
			reduce5<  4><<<N/(Level*2), Threads,Threads*sizeof(int) >>>(g_odata, g_odata);
			break;
		case  2:
			reduce5< 2><<<N/(Level*2), Threads,Threads*sizeof(int) >>>(g_odata, g_odata);
			break;
		case  1:
			reduce5<  1><<<N/(Level*2), Threads,Threads*sizeof(int) >>>(g_odata, g_odata);
			 break;
			}
		
	}
	cudaDeviceSynchronize();
	Level=Level*2;
	if(N/Level<=Threads){
		switch (N/(Level*2))
	{
		case 512:
			reduce5<512><<<1, N/(Level*2),N/(Level*2)*sizeof(int) >>>(g_odata, g_odata);
			break;
		case 256:
			reduce5<256><<<1, N/(Level*2),N/(Level*2)*sizeof(int) >>>(g_odata, g_odata); 
			break;
		case 128:
			reduce5<128><<<1, N/(Level*2),N/(Level*2)*sizeof(int) >>>(g_odata, g_odata);
			break;
		case 64:
			reduce5< 64><<<1, N/(Level*2),N/(Level*2)*sizeof(int) >>>(g_odata, g_odata);
			break;
		case 32:
			reduce5< 32><<<1, N/(Level*2),N/(Level*2)*sizeof(int) >>>(g_odata, g_odata);
			break;
		case 16:
			reduce5< 16><<<1, N/(Level*2),N/(Level*2)*sizeof(int) >>>(g_odata, g_odata);
			break;
		case  8:
			reduce5<  8><<<1, N/(Level*2),N/(Level*2)*sizeof(int) >>>(g_odata, g_odata);
			break;
		case  4:
			reduce5<  4><<<1, N/(Level*2),N/(Level*2)*sizeof(int) >>>(g_odata, g_odata);
			break;
		case  2:
			reduce5< 2><<<1, N/(Level*2),N/(Level*2)*sizeof(int) >>>(g_odata, g_odata);
			break;
		case  1:
			reduce5<  1><<<1, N/(Level*2),N/(Level*2)*sizeof(int) >>>(g_odata, g_odata);
			 break;
			}
			reduce4<<<1,N/(Level*2),N/(Level*2)*sizeof(int)>>>(g_odata,g_odata);

	}
	Level=Level*Threads;
}

	

cudaMemcpy(&d_output, g_odata, sizeof(int), cudaMemcpyDeviceToHost);
printf("reduce5 Device %d Host %d\n",d_output,s ); 
*/





return 0;
}
	.text
	.file	"sum_reduce.hip"
	.globl	_Z22__device_stub__reduce0PiS_  # -- Begin function _Z22__device_stub__reduce0PiS_
	.type	_Z22__device_stub__reduce0PiS_,@function
_Z22__device_stub__reduce0PiS_:         # @_Z22__device_stub__reduce0PiS_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	16(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7reduce0PiS_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z22__device_stub__reduce0PiS_, .Lfunc_end0-_Z22__device_stub__reduce0PiS_
	.cfi_endproc
                                        # -- End function
	.globl	_Z22__device_stub__reduce1PiS_  # -- Begin function _Z22__device_stub__reduce1PiS_
	.type	_Z22__device_stub__reduce1PiS_,@function
_Z22__device_stub__reduce1PiS_:         # @_Z22__device_stub__reduce1PiS_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	16(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7reduce1PiS_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z22__device_stub__reduce1PiS_, .Lfunc_end1-_Z22__device_stub__reduce1PiS_
	.cfi_endproc
                                        # -- End function
	.globl	_Z22__device_stub__reduce2PiS_  # -- Begin function _Z22__device_stub__reduce2PiS_
	.type	_Z22__device_stub__reduce2PiS_,@function
_Z22__device_stub__reduce2PiS_:         # @_Z22__device_stub__reduce2PiS_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	16(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7reduce2PiS_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z22__device_stub__reduce2PiS_, .Lfunc_end2-_Z22__device_stub__reduce2PiS_
	.cfi_endproc
                                        # -- End function
	.globl	_Z22__device_stub__reduce3PiS_  # -- Begin function _Z22__device_stub__reduce3PiS_
	.type	_Z22__device_stub__reduce3PiS_,@function
_Z22__device_stub__reduce3PiS_:         # @_Z22__device_stub__reduce3PiS_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	16(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7reduce3PiS_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	_Z22__device_stub__reduce3PiS_, .Lfunc_end3-_Z22__device_stub__reduce3PiS_
	.cfi_endproc
                                        # -- End function
	.globl	_Z22__device_stub__reduce4PiS_  # -- Begin function _Z22__device_stub__reduce4PiS_
	.type	_Z22__device_stub__reduce4PiS_,@function
_Z22__device_stub__reduce4PiS_:         # @_Z22__device_stub__reduce4PiS_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	16(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7reduce4PiS_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end4:
	.size	_Z22__device_stub__reduce4PiS_, .Lfunc_end4-_Z22__device_stub__reduce4PiS_
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$72, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%rsi, %r14
	movq	8(%rsi), %rdi
	callq	atoi
	movl	$1, %ebx
	movl	%eax, %ecx
	shll	%cl, %ebx
	movq	16(%r14), %rdi
	callq	atoi
	movl	%eax, %ebp
	movq	24(%r14), %rdi
	callq	atoi
	movl	%eax, %r14d
	movq	%rax, 40(%rsp)                  # 8-byte Spill
	xorl	%r13d, %r13d
	movl	$.L.str, %edi
	movl	%ebx, %esi
	movl	%ebp, %edx
	movl	%eax, %ecx
	xorl	%eax, %eax
	callq	printf
	movslq	%ebx, %r12
	shlq	$2, %r12
	movq	%r12, %rdi
	callq	malloc
	movq	%rax, %r15
.LBB5_1:                                # =>This Inner Loop Header: Depth=1
	movl	%r13d, %eax
	andl	$1, %eax
	movl	%eax, (%r15,%r13,4)
	incq	%r13
	cmpq	%r13, %rbx
	jne	.LBB5_1
# %bb.2:
	leaq	64(%rsp), %r13
	movq	%r13, %rdi
	movq	%r12, %rsi
	callq	hipMalloc
	movslq	%ebp, %rsi
	shlq	$2, %rsi
	movq	%rsp, %rdi
	callq	hipMalloc
	movq	(%r13), %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	movl	%ebx, %eax
	cltd
	idivl	40(%rsp)                        # 4-byte Folded Reload
	movl	%eax, %ecx
	movslq	%r14d, %rax
	movq	%rax, 56(%rsp)                  # 8-byte Spill
	movl	%r14d, %eax
	movq	%rax, 16(%rsp)                  # 8-byte Spill
	movl	%ecx, 12(%rsp)                  # 4-byte Spill
	testl	%ecx, %ecx
	jle	.LBB5_14
# %bb.3:                                # %.lr.ph
	movq	56(%rsp), %rax                  # 8-byte Reload
	leaq	(,%rax,4), %rax
	movq	%rax, 32(%rsp)                  # 8-byte Spill
	movq	16(%rsp), %rcx                  # 8-byte Reload
	movabsq	$4294967296, %rax               # imm = 0x100000000
	orq	%rax, %rcx
	movq	%rcx, 24(%rsp)                  # 8-byte Spill
	incq	%rax
	movq	%rax, 48(%rsp)                  # 8-byte Spill
	movl	12(%rsp), %ebp                  # 4-byte Reload
	movq	40(%rsp), %rax                  # 8-byte Reload
	movl	%eax, %r13d
.LBB5_4:                                # =>This Inner Loop Header: Depth=1
	movl	%ebp, %r12d
	movq	%r12, %rdi
	movabsq	$4294967296, %rax               # imm = 0x100000000
	orq	%rax, %rdi
	movl	$1, %esi
	movq	24(%rsp), %rdx                  # 8-byte Reload
	movl	$1, %ecx
	movq	32(%rsp), %r8                   # 8-byte Reload
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	cmpl	%r14d, %r13d
	jne	.LBB5_7
# %bb.5:                                #   in Loop: Header=BB5_4 Depth=1
	testl	%eax, %eax
	jne	.LBB5_10
# %bb.6:                                #   in Loop: Header=BB5_4 Depth=1
	movq	64(%rsp), %rdi
	movq	(%rsp), %rsi
	jmp	.LBB5_9
.LBB5_7:                                #   in Loop: Header=BB5_4 Depth=1
	testl	%eax, %eax
	jne	.LBB5_10
# %bb.8:                                #   in Loop: Header=BB5_4 Depth=1
	movq	(%rsp), %rdi
	movq	%rdi, %rsi
.LBB5_9:                                #   in Loop: Header=BB5_4 Depth=1
	callq	_Z22__device_stub__reduce0PiS_
.LBB5_10:                               #   in Loop: Header=BB5_4 Depth=1
	callq	hipDeviceSynchronize
	cmpl	%r14d, %ebp
	jge	.LBB5_13
# %bb.11:                               #   in Loop: Header=BB5_4 Depth=1
	leaq	(,%r12,4), %r8
	movabsq	$4294967296, %rax               # imm = 0x100000000
	orq	%rax, %r12
	movq	48(%rsp), %rdi                  # 8-byte Reload
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB5_13
# %bb.12:                               #   in Loop: Header=BB5_4 Depth=1
	movq	(%rsp), %rdi
	movq	%rdi, %rsi
	callq	_Z22__device_stub__reduce0PiS_
.LBB5_13:                               #   in Loop: Header=BB5_4 Depth=1
	imull	%r14d, %r13d
	movl	%ebx, %eax
	cltd
	idivl	%r13d
	movl	%eax, %ebp
	testl	%eax, %eax
	jg	.LBB5_4
.LBB5_14:                               # %._crit_edge
	movq	(%rsp), %rsi
	leaq	8(%rsp), %rdi
	movl	$4, %edx
	movl	$2, %ecx
	callq	hipMemcpy
	xorl	%eax, %eax
	xorl	%ebp, %ebp
.LBB5_15:                               # =>This Inner Loop Header: Depth=1
	addl	(%r15,%rax,4), %ebp
	incq	%rax
	cmpq	%rax, %rbx
	jne	.LBB5_15
# %bb.16:
	movl	8(%rsp), %esi
	movl	$.L.str.1, %edi
	movl	%ebp, %edx
	xorl	%eax, %eax
	callq	printf
	movl	12(%rsp), %r15d                 # 4-byte Reload
	testl	%r15d, %r15d
	movq	40(%rsp), %rcx                  # 8-byte Reload
	jle	.LBB5_40
# %bb.17:                               # %.lr.ph320
	movq	56(%rsp), %rax                  # 8-byte Reload
	leaq	(,%rax,4), %rax
	movq	%rax, 32(%rsp)                  # 8-byte Spill
	movq	16(%rsp), %rdx                  # 8-byte Reload
	movabsq	$4294967296, %rax               # imm = 0x100000000
	orq	%rax, %rdx
	movq	%rdx, 24(%rsp)                  # 8-byte Spill
	incq	%rax
	movq	%rax, 48(%rsp)                  # 8-byte Spill
	movl	%ecx, %r12d
.LBB5_18:                               # =>This Inner Loop Header: Depth=1
	movl	%r15d, %r13d
	movq	%r13, %rdi
	movabsq	$4294967296, %rax               # imm = 0x100000000
	orq	%rax, %rdi
	movl	$1, %esi
	movq	24(%rsp), %rdx                  # 8-byte Reload
	movl	$1, %ecx
	movq	32(%rsp), %r8                   # 8-byte Reload
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	cmpl	%r14d, %r12d
	jne	.LBB5_21
# %bb.19:                               #   in Loop: Header=BB5_18 Depth=1
	testl	%eax, %eax
	jne	.LBB5_24
# %bb.20:                               #   in Loop: Header=BB5_18 Depth=1
	movq	64(%rsp), %rdi
	movq	(%rsp), %rsi
	jmp	.LBB5_23
.LBB5_21:                               #   in Loop: Header=BB5_18 Depth=1
	testl	%eax, %eax
	jne	.LBB5_24
# %bb.22:                               #   in Loop: Header=BB5_18 Depth=1
	movq	(%rsp), %rdi
	movq	%rdi, %rsi
.LBB5_23:                               #   in Loop: Header=BB5_18 Depth=1
	callq	_Z22__device_stub__reduce1PiS_
.LBB5_24:                               #   in Loop: Header=BB5_18 Depth=1
	callq	hipDeviceSynchronize
	cmpl	%r14d, %r15d
	jge	.LBB5_27
# %bb.25:                               #   in Loop: Header=BB5_18 Depth=1
	leaq	(,%r13,4), %r8
	movabsq	$4294967296, %rax               # imm = 0x100000000
	orq	%rax, %r13
	movq	48(%rsp), %rdi                  # 8-byte Reload
	movl	$1, %esi
	movq	%r13, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB5_27
# %bb.26:                               #   in Loop: Header=BB5_18 Depth=1
	movq	(%rsp), %rdi
	movq	%rdi, %rsi
	callq	_Z22__device_stub__reduce1PiS_
.LBB5_27:                               #   in Loop: Header=BB5_18 Depth=1
	imull	%r14d, %r12d
	movl	%ebx, %eax
	cltd
	idivl	%r12d
	movl	%eax, %r15d
	testl	%eax, %eax
	jg	.LBB5_18
# %bb.28:                               # %._crit_edge321
	movq	(%rsp), %rsi
	leaq	8(%rsp), %r15
	movl	$4, %edx
	movq	%r15, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movl	(%r15), %esi
	movl	$.L.str.2, %edi
	movl	%ebp, %edx
	xorl	%eax, %eax
	callq	printf
	movl	12(%rsp), %r15d                 # 4-byte Reload
	testl	%r15d, %r15d
	jle	.LBB5_53
# %bb.29:                               # %.lr.ph324
	movq	16(%rsp), %rcx                  # 8-byte Reload
	movabsq	$4294967296, %rax               # imm = 0x100000000
	orq	%rax, %rcx
	movq	%rcx, 24(%rsp)                  # 8-byte Spill
	movq	40(%rsp), %rax                  # 8-byte Reload
	movl	%eax, %r12d
.LBB5_30:                               # =>This Inner Loop Header: Depth=1
	movl	%r15d, %r13d
	movq	%r13, %rdi
	movabsq	$4294967296, %rax               # imm = 0x100000000
	orq	%rax, %rdi
	movl	$1, %esi
	movq	24(%rsp), %rdx                  # 8-byte Reload
	movl	$1, %ecx
	movq	32(%rsp), %r8                   # 8-byte Reload
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	cmpl	%r14d, %r12d
	jne	.LBB5_33
# %bb.31:                               #   in Loop: Header=BB5_30 Depth=1
	testl	%eax, %eax
	jne	.LBB5_36
# %bb.32:                               #   in Loop: Header=BB5_30 Depth=1
	movq	64(%rsp), %rdi
	movq	(%rsp), %rsi
	jmp	.LBB5_35
.LBB5_33:                               #   in Loop: Header=BB5_30 Depth=1
	testl	%eax, %eax
	jne	.LBB5_36
# %bb.34:                               #   in Loop: Header=BB5_30 Depth=1
	movq	(%rsp), %rdi
	movq	%rdi, %rsi
.LBB5_35:                               #   in Loop: Header=BB5_30 Depth=1
	callq	_Z22__device_stub__reduce2PiS_
.LBB5_36:                               #   in Loop: Header=BB5_30 Depth=1
	callq	hipDeviceSynchronize
	cmpl	%r14d, %r15d
	jge	.LBB5_39
# %bb.37:                               #   in Loop: Header=BB5_30 Depth=1
	leaq	(,%r13,4), %r8
	movabsq	$4294967296, %rax               # imm = 0x100000000
	orq	%rax, %r13
	movq	48(%rsp), %rdi                  # 8-byte Reload
	movl	$1, %esi
	movq	%r13, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB5_39
# %bb.38:                               #   in Loop: Header=BB5_30 Depth=1
	movq	(%rsp), %rdi
	movq	%rdi, %rsi
	callq	_Z22__device_stub__reduce2PiS_
.LBB5_39:                               #   in Loop: Header=BB5_30 Depth=1
	imull	%r14d, %r12d
	movl	%ebx, %eax
	cltd
	idivl	%r12d
	movl	%eax, %r15d
	testl	%eax, %eax
	jg	.LBB5_30
	jmp	.LBB5_41
.LBB5_40:                               # %._crit_edge325.critedge
	movq	(%rsp), %rsi
	leaq	8(%rsp), %r15
	movl	$4, %edx
	movq	%r15, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movl	(%r15), %esi
	movl	$.L.str.2, %edi
	movl	%ebp, %edx
	xorl	%eax, %eax
	callq	printf
.LBB5_41:                               # %._crit_edge325
	movq	(%rsp), %rsi
	leaq	8(%rsp), %r15
	movl	$4, %edx
	movq	%r15, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movl	(%r15), %esi
	movl	$.L.str.3, %edi
	movl	%ebp, %edx
	xorl	%eax, %eax
	callq	printf
	cmpl	$0, 12(%rsp)                    # 4-byte Folded Reload
	jle	.LBB5_66
# %bb.42:                               # %.lr.ph328
	movq	56(%rsp), %rax                  # 8-byte Reload
	leaq	(,%rax,4), %rax
	movq	%rax, 32(%rsp)                  # 8-byte Spill
	movq	16(%rsp), %r13                  # 8-byte Reload
	movabsq	$4294967296, %rax               # imm = 0x100000000
	orq	%rax, %r13
	leal	(%r14,%r14), %ecx
	movl	%ecx, 24(%rsp)                  # 4-byte Spill
	incq	%rax
	movq	%rax, 48(%rsp)                  # 8-byte Spill
	movq	40(%rsp), %r12                  # 8-byte Reload
                                        # kill: def $r12d killed $r12d killed $r12 def $r12
.LBB5_43:                               # =>This Inner Loop Header: Depth=1
	cmpl	%r14d, %r12d
	jne	.LBB5_46
# %bb.44:                               #   in Loop: Header=BB5_43 Depth=1
	movl	%ebx, %eax
	cltd
	idivl	24(%rsp)                        # 4-byte Folded Reload
                                        # kill: def $eax killed $eax def $rax
	movabsq	$4294967296, %rcx               # imm = 0x100000000
	orq	%rcx, %rax
	movq	%rax, %rdi
	movl	$1, %esi
	movq	%r13, %rdx
	movl	$1, %ecx
	movq	32(%rsp), %r8                   # 8-byte Reload
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB5_49
# %bb.45:                               #   in Loop: Header=BB5_43 Depth=1
	movq	64(%rsp), %rdi
	movq	(%rsp), %rsi
	jmp	.LBB5_48
.LBB5_46:                               #   in Loop: Header=BB5_43 Depth=1
	leal	(%r12,%r12), %ecx
	movl	%ebx, %eax
	cltd
	idivl	%ecx
                                        # kill: def $eax killed $eax def $rax
	movabsq	$4294967296, %rcx               # imm = 0x100000000
	orq	%rcx, %rax
	movq	%rax, %rdi
	movl	$1, %esi
	movq	%r13, %rdx
	movl	$1, %ecx
	movq	32(%rsp), %r8                   # 8-byte Reload
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB5_49
# %bb.47:                               #   in Loop: Header=BB5_43 Depth=1
	movq	(%rsp), %rdi
	movq	%rdi, %rsi
.LBB5_48:                               #   in Loop: Header=BB5_43 Depth=1
	callq	_Z22__device_stub__reduce3PiS_
.LBB5_49:                               #   in Loop: Header=BB5_43 Depth=1
	callq	hipDeviceSynchronize
	leal	(%r12,%r12), %r15d
	movl	%ebx, %eax
	cltd
	idivl	%r15d
	cmpl	%r14d, %eax
	jg	.LBB5_52
# %bb.50:                               #   in Loop: Header=BB5_43 Depth=1
	shll	$2, %r12d
	movl	%ebx, %eax
	cltd
	idivl	%r12d
                                        # kill: def $eax killed $eax def $rax
	movslq	%eax, %r8
	shlq	$2, %r8
	movabsq	$4294967296, %rcx               # imm = 0x100000000
	orq	%rcx, %rax
	movq	48(%rsp), %rdi                  # 8-byte Reload
	movl	$1, %esi
	movq	%rax, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB5_52
# %bb.51:                               #   in Loop: Header=BB5_43 Depth=1
	movq	(%rsp), %rdi
	movq	%rdi, %rsi
	callq	_Z22__device_stub__reduce3PiS_
.LBB5_52:                               #   in Loop: Header=BB5_43 Depth=1
	imull	%r14d, %r15d
	movl	%ebx, %eax
	cltd
	idivl	%r15d
	movl	%r15d, %r12d
	testl	%eax, %eax
	jg	.LBB5_43
	jmp	.LBB5_54
.LBB5_66:                               # %._crit_edge333.critedge
	movq	(%rsp), %rsi
	leaq	8(%rsp), %rbx
	movl	$4, %edx
	movq	%rbx, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movl	(%rbx), %esi
	movl	$.L.str.4, %edi
	movl	%ebp, %edx
	xorl	%eax, %eax
	callq	printf
	jmp	.LBB5_67
.LBB5_53:                               # %._crit_edge329.critedge
	movq	(%rsp), %rsi
	leaq	8(%rsp), %r15
	movl	$4, %edx
	movq	%r15, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movl	(%r15), %esi
	movl	$.L.str.3, %edi
	movl	%ebp, %edx
	xorl	%eax, %eax
	callq	printf
.LBB5_54:                               # %._crit_edge329
	movq	(%rsp), %rsi
	leaq	8(%rsp), %r15
	movl	$4, %edx
	movq	%r15, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movl	(%r15), %esi
	movl	$.L.str.4, %edi
	movl	%ebp, %edx
	xorl	%eax, %eax
	callq	printf
	cmpl	$0, 12(%rsp)                    # 4-byte Folded Reload
	movq	40(%rsp), %r13                  # 8-byte Reload
	jle	.LBB5_67
# %bb.55:                               # %.lr.ph332
	shlq	$2, 56(%rsp)                    # 8-byte Folded Spill
	movabsq	$4294967296, %rax               # imm = 0x100000000
	orq	%rax, 16(%rsp)                  # 8-byte Folded Spill
	leal	(%r14,%r14), %r12d
	leaq	1(%rax), %r15
.LBB5_56:                               # =>This Inner Loop Header: Depth=1
	cmpl	%r14d, %r13d
	jne	.LBB5_59
# %bb.57:                               #   in Loop: Header=BB5_56 Depth=1
	movl	%ebx, %eax
	cltd
	idivl	%r12d
                                        # kill: def $eax killed $eax def $rax
	movabsq	$4294967296, %rcx               # imm = 0x100000000
	orq	%rcx, %rax
	movq	%rax, %rdi
	movl	$1, %esi
	movq	16(%rsp), %rdx                  # 8-byte Reload
	movl	$1, %ecx
	movq	56(%rsp), %r8                   # 8-byte Reload
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB5_62
# %bb.58:                               #   in Loop: Header=BB5_56 Depth=1
	movq	64(%rsp), %rdi
	movq	(%rsp), %rsi
	jmp	.LBB5_61
.LBB5_59:                               #   in Loop: Header=BB5_56 Depth=1
	leal	(,%r13,2), %ecx
	movl	%ebx, %eax
	cltd
	idivl	%ecx
                                        # kill: def $eax killed $eax def $rax
	movabsq	$4294967296, %rcx               # imm = 0x100000000
	orq	%rcx, %rax
	movq	%rax, %rdi
	movl	$1, %esi
	movq	16(%rsp), %rdx                  # 8-byte Reload
	movl	$1, %ecx
	movq	56(%rsp), %r8                   # 8-byte Reload
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB5_62
# %bb.60:                               #   in Loop: Header=BB5_56 Depth=1
	movq	(%rsp), %rdi
	movq	%rdi, %rsi
.LBB5_61:                               #   in Loop: Header=BB5_56 Depth=1
	callq	_Z22__device_stub__reduce4PiS_
.LBB5_62:                               #   in Loop: Header=BB5_56 Depth=1
	callq	hipDeviceSynchronize
	movq	%r13, %rcx
	addl	%r13d, %r13d
	movl	%ebx, %eax
	cltd
	idivl	%r13d
	cmpl	%r14d, %eax
	jg	.LBB5_65
# %bb.63:                               #   in Loop: Header=BB5_56 Depth=1
	shll	$2, %ecx
	movl	%ebx, %eax
	cltd
	idivl	%ecx
                                        # kill: def $eax killed $eax def $rax
	movslq	%eax, %r8
	shlq	$2, %r8
	movabsq	$4294967296, %rcx               # imm = 0x100000000
	orq	%rcx, %rax
	movq	%r15, %rdi
	movl	$1, %esi
	movq	%rax, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB5_65
# %bb.64:                               #   in Loop: Header=BB5_56 Depth=1
	movq	(%rsp), %rdi
	movq	%rdi, %rsi
	callq	_Z22__device_stub__reduce4PiS_
.LBB5_65:                               #   in Loop: Header=BB5_56 Depth=1
	imull	%r14d, %r13d
	movl	%ebx, %eax
	cltd
	idivl	%r13d
                                        # kill: def $r13d killed $r13d def $r13
	testl	%eax, %eax
	jg	.LBB5_56
.LBB5_67:                               # %._crit_edge333
	movq	(%rsp), %rsi
	leaq	8(%rsp), %rbx
	movl	$4, %edx
	movq	%rbx, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movl	(%rbx), %esi
	movl	$.L.str.5, %edi
	movl	%ebp, %edx
	xorl	%eax, %eax
	callq	printf
	xorl	%eax, %eax
	addq	$72, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end5:
	.size	main, .Lfunc_end5-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB6_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB6_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z7reduce0PiS_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z7reduce1PiS_, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z7reduce2PiS_, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z7reduce3PiS_, %esi
	movl	$.L__unnamed_4, %edx
	movl	$.L__unnamed_4, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z7reduce4PiS_, %esi
	movl	$.L__unnamed_5, %edx
	movl	$.L__unnamed_5, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end6:
	.size	__hip_module_ctor, .Lfunc_end6-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB7_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB7_2:
	retq
.Lfunc_end7:
	.size	__hip_module_dtor, .Lfunc_end7-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z7reduce0PiS_,@object          # @_Z7reduce0PiS_
	.section	.rodata,"a",@progbits
	.globl	_Z7reduce0PiS_
	.p2align	3, 0x0
_Z7reduce0PiS_:
	.quad	_Z22__device_stub__reduce0PiS_
	.size	_Z7reduce0PiS_, 8

	.type	_Z7reduce1PiS_,@object          # @_Z7reduce1PiS_
	.globl	_Z7reduce1PiS_
	.p2align	3, 0x0
_Z7reduce1PiS_:
	.quad	_Z22__device_stub__reduce1PiS_
	.size	_Z7reduce1PiS_, 8

	.type	_Z7reduce2PiS_,@object          # @_Z7reduce2PiS_
	.globl	_Z7reduce2PiS_
	.p2align	3, 0x0
_Z7reduce2PiS_:
	.quad	_Z22__device_stub__reduce2PiS_
	.size	_Z7reduce2PiS_, 8

	.type	_Z7reduce3PiS_,@object          # @_Z7reduce3PiS_
	.globl	_Z7reduce3PiS_
	.p2align	3, 0x0
_Z7reduce3PiS_:
	.quad	_Z22__device_stub__reduce3PiS_
	.size	_Z7reduce3PiS_, 8

	.type	_Z7reduce4PiS_,@object          # @_Z7reduce4PiS_
	.globl	_Z7reduce4PiS_
	.p2align	3, 0x0
_Z7reduce4PiS_:
	.quad	_Z22__device_stub__reduce4PiS_
	.size	_Z7reduce4PiS_, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"Doing a parallel reduction for  N= %d NumberOfBlocks=%d Threads=%d \n"
	.size	.L.str, 69

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"reduce0 Device %d Host %d\n"
	.size	.L.str.1, 27

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"reduce1 Device %d Host %d\n"
	.size	.L.str.2, 27

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"reduce2 Device %d Host %d\n"
	.size	.L.str.3, 27

	.type	.L.str.4,@object                # @.str.4
.L.str.4:
	.asciz	"reduce3 Device %d Host %d\n"
	.size	.L.str.4, 27

	.type	.L.str.5,@object                # @.str.5
.L.str.5:
	.asciz	"reduce4 Device %d Host %d\n"
	.size	.L.str.5, 27

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z7reduce0PiS_"
	.size	.L__unnamed_1, 15

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z7reduce1PiS_"
	.size	.L__unnamed_2, 15

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z7reduce2PiS_"
	.size	.L__unnamed_3, 15

	.type	.L__unnamed_4,@object           # @3
.L__unnamed_4:
	.asciz	"_Z7reduce3PiS_"
	.size	.L__unnamed_4, 15

	.type	.L__unnamed_5,@object           # @4
.L__unnamed_5:
	.asciz	"_Z7reduce4PiS_"
	.size	.L__unnamed_5, 15

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z22__device_stub__reduce0PiS_
	.addrsig_sym _Z22__device_stub__reduce1PiS_
	.addrsig_sym _Z22__device_stub__reduce2PiS_
	.addrsig_sym _Z22__device_stub__reduce3PiS_
	.addrsig_sym _Z22__device_stub__reduce4PiS_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z7reduce0PiS_
	.addrsig_sym _Z7reduce1PiS_
	.addrsig_sym _Z7reduce2PiS_
	.addrsig_sym _Z7reduce3PiS_
	.addrsig_sym _Z7reduce4PiS_
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z7reduce0PiS_          ; -- Begin function _Z7reduce0PiS_
	.globl	_Z7reduce0PiS_
	.p2align	8
	.type	_Z7reduce0PiS_,@function
_Z7reduce0PiS_:                         ; @_Z7reduce0PiS_
; %bb.0:
	s_clause 0x1
	s_load_b32 s5, s[0:1], 0x1c
	s_load_b128 s[0:3], s[0:1], 0x0
	s_mov_b32 s4, s15
	s_waitcnt lgkmcnt(0)
	s_and_b32 s5, s5, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s4, s5, v[0:1]
	v_mov_b32_e32 v2, 0
	s_cmp_lt_u32 s5, 2
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v2, v[1:2], off
	v_lshl_add_u32 v1, v0, 2, 0
	s_waitcnt vmcnt(0)
	ds_store_b32 v1, v2
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB0_5
; %bb.1:                                ; %.lr.ph.preheader
	s_mov_b32 s1, 1
.LBB0_2:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b32 s0, s1, 1
	s_add_i32 s6, s0, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v2, s6, v0
	s_mov_b32 s6, exec_lo
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB0_4
; %bb.3:                                ;   in Loop: Header=BB0_2 Depth=1
	v_lshl_add_u32 v2, s1, 2, v1
	ds_load_b32 v2, v2
	ds_load_b32 v3, v1
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v2, v3, v2
	ds_store_b32 v1, v2
.LBB0_4:                                ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s6
	s_cmp_ge_u32 s0, s5
	s_mov_b32 s1, s0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc0 .LBB0_2
.LBB0_5:                                ; %._crit_edge
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB0_7
; %bb.6:
	v_mov_b32_e32 v0, 0
	s_mov_b32 s5, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[0:1], s[4:5], 2
	s_add_u32 s0, s2, s0
	ds_load_b32 v1, v0
	s_addc_u32 s1, s3, s1
	s_waitcnt lgkmcnt(0)
	global_store_b32 v0, v1, s[0:1]
.LBB0_7:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7reduce0PiS_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 4
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z7reduce0PiS_, .Lfunc_end0-_Z7reduce0PiS_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 304
; NumSgprs: 18
; NumVgprs: 4
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 4
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z7reduce1PiS_          ; -- Begin function _Z7reduce1PiS_
	.globl	_Z7reduce1PiS_
	.p2align	8
	.type	_Z7reduce1PiS_,@function
_Z7reduce1PiS_:                         ; @_Z7reduce1PiS_
; %bb.0:
	s_clause 0x1
	s_load_b32 s5, s[0:1], 0x1c
	s_load_b128 s[0:3], s[0:1], 0x0
	s_mov_b32 s4, s15
	s_waitcnt lgkmcnt(0)
	s_and_b32 s5, s5, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s4, s5, v[0:1]
	v_mov_b32_e32 v2, 0
	s_cmp_lt_u32 s5, 2
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v1, v[1:2], off
	v_lshl_add_u32 v2, v0, 2, 0
	s_waitcnt vmcnt(0)
	ds_store_b32 v2, v1
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB1_5
; %bb.1:                                ; %.lr.ph.preheader
	s_mov_b32 s1, 1
.LBB1_2:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	s_lshl_b32 s0, s1, 1
	s_mov_b32 s6, exec_lo
	v_mul_lo_u32 v1, s0, v0
	v_cmpx_gt_u32_e64 s5, v1
	s_cbranch_execz .LBB1_4
; %bb.3:                                ;   in Loop: Header=BB1_2 Depth=1
	v_lshl_add_u32 v1, v1, 2, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_lshl_add_u32 v2, s1, 2, v1
	ds_load_b32 v2, v2
	ds_load_b32 v3, v1
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v2, v3, v2
	ds_store_b32 v1, v2
.LBB1_4:                                ;   in Loop: Header=BB1_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s6
	s_cmp_ge_u32 s0, s5
	s_mov_b32 s1, s0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc0 .LBB1_2
.LBB1_5:                                ; %._crit_edge
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB1_7
; %bb.6:
	v_mov_b32_e32 v0, 0
	s_mov_b32 s5, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[0:1], s[4:5], 2
	s_add_u32 s0, s2, s0
	ds_load_b32 v1, v0
	s_addc_u32 s1, s3, s1
	s_waitcnt lgkmcnt(0)
	global_store_b32 v0, v1, s[0:1]
.LBB1_7:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7reduce1PiS_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 4
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z7reduce1PiS_, .Lfunc_end1-_Z7reduce1PiS_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 316
; NumSgprs: 18
; NumVgprs: 4
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 4
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z7reduce2PiS_          ; -- Begin function _Z7reduce2PiS_
	.globl	_Z7reduce2PiS_
	.p2align	8
	.type	_Z7reduce2PiS_,@function
_Z7reduce2PiS_:                         ; @_Z7reduce2PiS_
; %bb.0:
	s_clause 0x1
	s_load_b32 s5, s[0:1], 0x1c
	s_load_b128 s[0:3], s[0:1], 0x0
	s_mov_b32 s4, s15
	s_waitcnt lgkmcnt(0)
	s_and_b32 s5, s5, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s4, s5, v[0:1]
	v_mov_b32_e32 v2, 0
	s_cmp_lt_u32 s5, 2
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v2, v[1:2], off
	v_lshl_add_u32 v1, v0, 2, 0
	s_waitcnt vmcnt(0)
	ds_store_b32 v1, v2
	s_waitcnt lgkmcnt(0)
	s_barrier
.LBB2_1:                                ; =>This Inner Loop Header: Depth=1
	buffer_gl0_inv
	s_cbranch_scc1 .LBB2_5
; %bb.2:                                ; %.lr.ph
                                        ;   in Loop: Header=BB2_1 Depth=1
	s_lshr_b32 s0, s5, 1
	s_mov_b32 s1, exec_lo
	v_cmpx_gt_u32_e64 s0, v0
	s_cbranch_execz .LBB2_4
; %bb.3:                                ;   in Loop: Header=BB2_1 Depth=1
	v_lshl_add_u32 v2, s0, 2, v1
	ds_load_b32 v2, v2
	ds_load_b32 v3, v1
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v2, v3, v2
	ds_store_b32 v1, v2
.LBB2_4:                                ;   in Loop: Header=BB2_1 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_waitcnt lgkmcnt(0)
	s_barrier
	s_cmp_lt_u32 s5, 4
	s_mov_b32 s5, s0
	s_branch .LBB2_1
.LBB2_5:                                ; %._crit_edge
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB2_7
; %bb.6:
	v_mov_b32_e32 v0, 0
	s_mov_b32 s5, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[0:1], s[4:5], 2
	s_add_u32 s0, s2, s0
	ds_load_b32 v1, v0
	s_addc_u32 s1, s3, s1
	s_waitcnt lgkmcnt(0)
	global_store_b32 v0, v1, s[0:1]
.LBB2_7:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7reduce2PiS_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 4
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_Z7reduce2PiS_, .Lfunc_end2-_Z7reduce2PiS_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 280
; NumSgprs: 18
; NumVgprs: 4
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 4
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z7reduce3PiS_          ; -- Begin function _Z7reduce3PiS_
	.globl	_Z7reduce3PiS_
	.p2align	8
	.type	_Z7reduce3PiS_,@function
_Z7reduce3PiS_:                         ; @_Z7reduce3PiS_
; %bb.0:
	s_clause 0x1
	s_load_b32 s5, s[0:1], 0x1c
	s_load_b128 s[0:3], s[0:1], 0x0
	s_mov_b32 s4, s15
	s_waitcnt lgkmcnt(0)
	s_and_b32 s5, s5, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	s_mul_i32 s6, s15, s5
	s_cmp_lt_u32 s5, 2
	v_lshl_add_u32 v1, s6, 1, v0
	v_mov_b32_e32 v2, 0
	v_lshlrev_b64 v[3:4], 2, v[1:2]
	v_add_nc_u32_e32 v1, s5, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v3, vcc_lo, s0, v3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	s_clause 0x1
	global_load_b32 v3, v[3:4], off
	global_load_b32 v2, v[1:2], off
	v_lshl_add_u32 v1, v0, 2, 0
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v2, v2, v3
	ds_store_b32 v1, v2
	s_waitcnt lgkmcnt(0)
	s_barrier
.LBB3_1:                                ; =>This Inner Loop Header: Depth=1
	buffer_gl0_inv
	s_cbranch_scc1 .LBB3_5
; %bb.2:                                ; %.lr.ph
                                        ;   in Loop: Header=BB3_1 Depth=1
	s_lshr_b32 s0, s5, 1
	s_mov_b32 s1, exec_lo
	v_cmpx_gt_u32_e64 s0, v0
	s_cbranch_execz .LBB3_4
; %bb.3:                                ;   in Loop: Header=BB3_1 Depth=1
	v_lshl_add_u32 v2, s0, 2, v1
	ds_load_b32 v2, v2
	ds_load_b32 v3, v1
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v2, v3, v2
	ds_store_b32 v1, v2
.LBB3_4:                                ;   in Loop: Header=BB3_1 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_waitcnt lgkmcnt(0)
	s_barrier
	s_cmp_lt_u32 s5, 4
	s_mov_b32 s5, s0
	s_branch .LBB3_1
.LBB3_5:                                ; %._crit_edge
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB3_7
; %bb.6:
	v_mov_b32_e32 v0, 0
	s_mov_b32 s5, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[0:1], s[4:5], 2
	s_add_u32 s0, s2, s0
	ds_load_b32 v1, v0
	s_addc_u32 s1, s3, s1
	s_waitcnt lgkmcnt(0)
	global_store_b32 v0, v1, s[0:1]
.LBB3_7:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7reduce3PiS_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 5
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end3:
	.size	_Z7reduce3PiS_, .Lfunc_end3-_Z7reduce3PiS_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 332
; NumSgprs: 18
; NumVgprs: 5
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 5
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z7reduce4PiS_          ; -- Begin function _Z7reduce4PiS_
	.globl	_Z7reduce4PiS_
	.p2align	8
	.type	_Z7reduce4PiS_,@function
_Z7reduce4PiS_:                         ; @_Z7reduce4PiS_
; %bb.0:
	s_clause 0x1
	s_load_b32 s5, s[0:1], 0x1c
	s_load_b128 s[0:3], s[0:1], 0x0
	s_mov_b32 s4, s15
	s_waitcnt lgkmcnt(0)
	s_and_b32 s5, s5, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	s_mul_i32 s6, s15, s5
	s_cmpk_lt_u32 s5, 0x42
	v_lshl_add_u32 v1, s6, 1, v0
	v_mov_b32_e32 v2, 0
	v_lshlrev_b64 v[3:4], 2, v[1:2]
	v_add_nc_u32_e32 v1, s5, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v3, vcc_lo, s0, v3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	s_clause 0x1
	global_load_b32 v3, v[3:4], off
	global_load_b32 v2, v[1:2], off
	v_lshl_add_u32 v1, v0, 2, 0
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v2, v2, v3
	ds_store_b32 v1, v2
	s_waitcnt lgkmcnt(0)
	s_barrier
.LBB4_1:                                ; =>This Inner Loop Header: Depth=1
	buffer_gl0_inv
	s_cbranch_scc1 .LBB4_5
; %bb.2:                                ; %.lr.ph
                                        ;   in Loop: Header=BB4_1 Depth=1
	s_lshr_b32 s0, s5, 1
	s_mov_b32 s1, exec_lo
	v_cmpx_gt_u32_e64 s0, v0
	s_cbranch_execz .LBB4_4
; %bb.3:                                ;   in Loop: Header=BB4_1 Depth=1
	v_lshl_add_u32 v2, s0, 2, v1
	ds_load_b32 v2, v2
	ds_load_b32 v3, v1
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v2, v3, v2
	ds_store_b32 v1, v2
.LBB4_4:                                ;   in Loop: Header=BB4_1 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_waitcnt lgkmcnt(0)
	s_barrier
	s_cmpk_lt_u32 s5, 0x84
	s_mov_b32 s5, s0
	s_branch .LBB4_1
.LBB4_5:                                ; %._crit_edge
	s_mov_b32 s1, exec_lo
	v_cmpx_gt_u32_e32 32, v0
	s_cbranch_execz .LBB4_7
; %bb.6:
	v_add_nc_u32_e32 v2, 0x80, v1
	v_cmp_ne_u32_e64 s0, -1, v1
	s_mov_b64 s[6:7], src_shared_base
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_ne_u32_e32 vcc_lo, -1, v2
	v_cndmask_b32_e64 v3, 0, s7, s0
	v_cndmask_b32_e32 v4, 0, v2, vcc_lo
	v_cndmask_b32_e64 v5, 0, s7, vcc_lo
	v_cndmask_b32_e64 v2, 0, v1, s0
	flat_load_b32 v5, v[4:5] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v6, v[2:3] glc dlc
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v4, 64, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v4
	v_cndmask_b32_e32 v4, 0, v4, vcc_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v6, v6, v5
	v_cndmask_b32_e64 v5, 0, s7, vcc_lo
	flat_store_b32 v[2:3], v6 dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b32 v5, v[4:5] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v6, v[2:3] glc dlc
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v4, 32, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v4
	v_cndmask_b32_e32 v4, 0, v4, vcc_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v6, v6, v5
	v_cndmask_b32_e64 v5, 0, s7, vcc_lo
	flat_store_b32 v[2:3], v6 dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b32 v5, v[4:5] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v6, v[2:3] glc dlc
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v4, 16, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v4
	v_cndmask_b32_e32 v4, 0, v4, vcc_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v6, v6, v5
	v_cndmask_b32_e64 v5, 0, s7, vcc_lo
	flat_store_b32 v[2:3], v6 dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b32 v5, v[4:5] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v6, v[2:3] glc dlc
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v4, 8, v1
	v_add_nc_u32_e32 v1, 4, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_cmp_ne_u32_e32 vcc_lo, -1, v4
	v_cndmask_b32_e32 v4, 0, v4, vcc_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v6, v6, v5
	v_cndmask_b32_e64 v5, 0, s7, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, -1, v1
	flat_store_b32 v[2:3], v6 dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b32 v5, v[4:5] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v6, v[2:3] glc dlc
	s_waitcnt vmcnt(0)
	v_cndmask_b32_e32 v4, 0, v1, vcc_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v1, v6, v5
	v_cndmask_b32_e64 v5, 0, s7, vcc_lo
	flat_store_b32 v[2:3], v1 dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b32 v1, v[4:5] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v4, v[2:3] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_nc_u32_e32 v1, v4, v1
	flat_store_b32 v[2:3], v1 dlc
	s_waitcnt_vscnt null, 0x0
.LBB4_7:
	s_or_b32 exec_lo, exec_lo, s1
	s_mov_b32 s5, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB4_9
; %bb.8:
	v_mov_b32_e32 v0, 0
	s_lshl_b64 s[0:1], s[4:5], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s0, s2, s0
	s_addc_u32 s1, s3, s1
	ds_load_b32 v1, v0
	s_waitcnt lgkmcnt(0)
	global_store_b32 v0, v1, s[0:1]
.LBB4_9:
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7reduce4PiS_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 7
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end4:
	.size	_Z7reduce4PiS_, .Lfunc_end4-_Z7reduce4PiS_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 772
; NumSgprs: 18
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym sdata
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         20
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         28
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         30
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         32
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         34
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         36
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         38
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         56
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         80
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         136
        .size:           4
        .value_kind:     hidden_dynamic_lds_size
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 272
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z7reduce0PiS_
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z7reduce0PiS_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     4
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         20
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         28
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         30
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         32
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         34
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         36
        .size:           2
        .value_kind:     hidden_remainder_y
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amdhsa.version:
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...

	.end_amdgpu_metadata
