//3x3 mask
__constant__
double mask0[3][3] = {  {0.1036,0.1464,0.1036},
						{0.1464,0,0.1464},
						{0.1036,0.1464,0.1036}};	
						
//horizontal 5x5 mask
__constant__
double mask1[5][5] = {  {0,0,0,0,0},
						{0.0465,0.0735,0.1040,0.0735,0.0465},
						{0.0520,0.1040,0,0.1040,0.0520},
						{0.0465,0.0735,0.1040,0.0735,0.0465},
						{0,0,0,0,0}};

//vertical 5x5 mask						
__constant__
double mask2[5][5] = {  {0,0.0465,0.0520,0.0465,0},
						{0,0.0735,0.1040,0.0735,0},
						{0,0.1040,0,0.1040,0},
						{0,0.0735,0.1040,0.0735,0},
						{0,0.0465,0.0520,0.0465,0}};

//45 degree 7x7 mask					
__constant__
double mask3[7][7] = {	{0,0,0,0,0.0251,0,0},
						{0,0,0,0.0397,0.0355,0.0281,0},
						{0,0,0.0562,0.0794,0.0562,0.0355,0.0251},
						{0,0.0397,0.0794,0,0.0794,0.0397,0},
						{0.0251,0.0355,0.0562,0.0794,0.0562,0,0},
						{0,0.0281,0.0355,0.0397,0,0,0},
						{0,0,0.0251,0,0,0,0}};
						
//135 degree 7x7 mask							
__constant__						
double mask4[7][7] = {  {0,0,0.0251,0,0,0,0},
						{0,0.0281,0.0355,0.0397,0,0,0},
						{0.0251,0.0355,0.0562,0.0794,0.0562,0,0},
						{0,0.0397,0.0794,0,0.0794,0.0397,0},
						{0,0,0.0562,0.0794,0.0562,0.0355,0.0251},
						{0,0,0,0.0397,0.0355,0.0281,0},
						{0,0,0,0,0.0251,0,0}};
	.file	"tmpxft_00259a7a_00000000-6_masks.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2010:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2010:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"mask0"
.LC1:
	.string	"mask1"
.LC2:
	.string	"mask2"
.LC3:
	.string	"mask3"
.LC4:
	.string	"mask4"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2033:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	movl	$72, %r9d
	xorl	%r8d, %r8d
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	movq	%rdx, %rcx
	leaq	_ZL5mask0(%rip), %rsi
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC1(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$200, %r9d
	leaq	_ZL5mask1(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC2(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$200, %r9d
	leaq	_ZL5mask2(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	popq	%r8
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC3(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$392, %r9d
	leaq	_ZL5mask3(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r9
	.cfi_def_cfa_offset 24
	popq	%r10
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC4(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movl	$392, %r9d
	movq	%rdx, %rcx
	leaq	_ZL5mask4(%rip), %rsi
	call	__cudaRegisterVar@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	popq	%r11
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2033:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.local	_ZL5mask4
	.comm	_ZL5mask4,392,32
	.local	_ZL5mask3
	.comm	_ZL5mask3,392,32
	.local	_ZL5mask2
	.comm	_ZL5mask2,200,32
	.local	_ZL5mask1
	.comm	_ZL5mask1,200,32
	.local	_ZL5mask0
	.comm	_ZL5mask0,72,32
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
//3x3 mask
__constant__
double mask0[3][3] = {  {0.1036,0.1464,0.1036},
						{0.1464,0,0.1464},
						{0.1036,0.1464,0.1036}};	
						
//horizontal 5x5 mask
__constant__
double mask1[5][5] = {  {0,0,0,0,0},
						{0.0465,0.0735,0.1040,0.0735,0.0465},
						{0.0520,0.1040,0,0.1040,0.0520},
						{0.0465,0.0735,0.1040,0.0735,0.0465},
						{0,0,0,0,0}};

//vertical 5x5 mask						
__constant__
double mask2[5][5] = {  {0,0.0465,0.0520,0.0465,0},
						{0,0.0735,0.1040,0.0735,0},
						{0,0.1040,0,0.1040,0},
						{0,0.0735,0.1040,0.0735,0},
						{0,0.0465,0.0520,0.0465,0}};

//45 degree 7x7 mask					
__constant__
double mask3[7][7] = {	{0,0,0,0,0.0251,0,0},
						{0,0,0,0.0397,0.0355,0.0281,0},
						{0,0,0.0562,0.0794,0.0562,0.0355,0.0251},
						{0,0.0397,0.0794,0,0.0794,0.0397,0},
						{0.0251,0.0355,0.0562,0.0794,0.0562,0,0},
						{0,0.0281,0.0355,0.0397,0,0,0},
						{0,0,0.0251,0,0,0,0}};
						
//135 degree 7x7 mask							
__constant__						
double mask4[7][7] = {  {0,0,0.0251,0,0,0,0},
						{0,0.0281,0.0355,0.0397,0,0,0},
						{0.0251,0.0355,0.0562,0.0794,0.0562,0,0},
						{0,0.0397,0.0794,0,0.0794,0.0397,0},
						{0,0,0.0562,0.0794,0.0562,0.0355,0.0251},
						{0,0,0,0.0397,0.0355,0.0281,0},
						{0,0,0,0,0.0251,0,0}};
	.text
	.file	"masks.hip"
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB0_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB0_2:
	movl	$mask0, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$72, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$mask1, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movl	$200, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$mask2, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movl	$200, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$mask3, %esi
	movl	$.L__unnamed_4, %edx
	movl	$.L__unnamed_4, %ecx
	movl	$392, %r9d                      # imm = 0x188
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$mask4, %esi
	movl	$.L__unnamed_5, %edx
	movl	$.L__unnamed_5, %ecx
	movl	$392, %r9d                      # imm = 0x188
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$__hip_module_dtor, %edi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end0:
	.size	__hip_module_ctor, .Lfunc_end0-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB1_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB1_2:
	retq
.Lfunc_end1:
	.size	__hip_module_dtor, .Lfunc_end1-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	mask0,@object                   # @mask0
	.local	mask0
	.comm	mask0,72,16
	.type	mask1,@object                   # @mask1
	.local	mask1
	.comm	mask1,200,16
	.type	mask2,@object                   # @mask2
	.local	mask2
	.comm	mask2,200,16
	.type	mask3,@object                   # @mask3
	.local	mask3
	.comm	mask3,392,16
	.type	mask4,@object                   # @mask4
	.local	mask4
	.comm	mask4,392,16
	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"mask0"
	.size	.L__unnamed_1, 6

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"mask1"
	.size	.L__unnamed_2, 6

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"mask2"
	.size	.L__unnamed_3, 6

	.type	.L__unnamed_4,@object           # @3
.L__unnamed_4:
	.asciz	"mask3"
	.size	.L__unnamed_4, 6

	.type	.L__unnamed_5,@object           # @4
.L__unnamed_5:
	.asciz	"mask4"
	.size	.L__unnamed_5, 6

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym mask0
	.addrsig_sym mask1
	.addrsig_sym mask2
	.addrsig_sym mask3
	.addrsig_sym mask4
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.protected	mask0                   ; @mask0
	.type	mask0,@object
	.data
	.globl	mask0
	.p2align	4, 0x0
mask0:
	.quad	0x3fba858793dd97f6              ; double 0.1036
	.quad	0x3fc2bd3c36113405              ; double 0.1464
	.quad	0x3fba858793dd97f6              ; double 0.1036
	.quad	0x3fc2bd3c36113405              ; double 0.1464
	.quad	0x0000000000000000              ; double 0
	.quad	0x3fc2bd3c36113405              ; double 0.1464
	.quad	0x3fba858793dd97f6              ; double 0.1036
	.quad	0x3fc2bd3c36113405              ; double 0.1464
	.quad	0x3fba858793dd97f6              ; double 0.1036
	.size	mask0, 72

	.protected	mask1                   ; @mask1
	.type	mask1,@object
	.globl	mask1
	.p2align	4, 0x0
mask1:
	.zero	40
	.quad	0x3fa7ced916872b02              ; double 0.0465
	.quad	0x3fb2d0e560418937              ; double 0.073499999999999996
	.quad	0x3fba9fbe76c8b439              ; double 0.104
	.quad	0x3fb2d0e560418937              ; double 0.073499999999999996
	.quad	0x3fa7ced916872b02              ; double 0.0465
	.quad	0x3faa9fbe76c8b439              ; double 0.051999999999999998
	.quad	0x3fba9fbe76c8b439              ; double 0.104
	.quad	0x0000000000000000              ; double 0
	.quad	0x3fba9fbe76c8b439              ; double 0.104
	.quad	0x3faa9fbe76c8b439              ; double 0.051999999999999998
	.quad	0x3fa7ced916872b02              ; double 0.0465
	.quad	0x3fb2d0e560418937              ; double 0.073499999999999996
	.quad	0x3fba9fbe76c8b439              ; double 0.104
	.quad	0x3fb2d0e560418937              ; double 0.073499999999999996
	.quad	0x3fa7ced916872b02              ; double 0.0465
	.zero	40
	.size	mask1, 200

	.protected	mask2                   ; @mask2
	.type	mask2,@object
	.globl	mask2
	.p2align	4, 0x0
mask2:
	.quad	0x0000000000000000              ; double 0
	.quad	0x3fa7ced916872b02              ; double 0.0465
	.quad	0x3faa9fbe76c8b439              ; double 0.051999999999999998
	.quad	0x3fa7ced916872b02              ; double 0.0465
	.quad	0x0000000000000000              ; double 0
	.quad	0x0000000000000000              ; double 0
	.quad	0x3fb2d0e560418937              ; double 0.073499999999999996
	.quad	0x3fba9fbe76c8b439              ; double 0.104
	.quad	0x3fb2d0e560418937              ; double 0.073499999999999996
	.quad	0x0000000000000000              ; double 0
	.quad	0x0000000000000000              ; double 0
	.quad	0x3fba9fbe76c8b439              ; double 0.104
	.quad	0x0000000000000000              ; double 0
	.quad	0x3fba9fbe76c8b439              ; double 0.104
	.quad	0x0000000000000000              ; double 0
	.quad	0x0000000000000000              ; double 0
	.quad	0x3fb2d0e560418937              ; double 0.073499999999999996
	.quad	0x3fba9fbe76c8b439              ; double 0.104
	.quad	0x3fb2d0e560418937              ; double 0.073499999999999996
	.quad	0x0000000000000000              ; double 0
	.quad	0x0000000000000000              ; double 0
	.quad	0x3fa7ced916872b02              ; double 0.0465
	.quad	0x3faa9fbe76c8b439              ; double 0.051999999999999998
	.quad	0x3fa7ced916872b02              ; double 0.0465
	.quad	0x0000000000000000              ; double 0
	.size	mask2, 200

	.protected	mask3                   ; @mask3
	.type	mask3,@object
	.globl	mask3
	.p2align	4, 0x0
mask3:
	.quad	0x0000000000000000              ; double 0
	.quad	0x0000000000000000              ; double 0
	.quad	0x0000000000000000              ; double 0
	.quad	0x0000000000000000              ; double 0
	.quad	0x3f99b3d07c84b5dd              ; double 0.025100000000000001
	.quad	0x0000000000000000              ; double 0
	.quad	0x0000000000000000              ; double 0
	.quad	0x0000000000000000              ; double 0
	.quad	0x0000000000000000              ; double 0
	.quad	0x0000000000000000              ; double 0
	.quad	0x3fa4538ef34d6a16              ; double 0.039699999999999999
	.quad	0x3fa22d0e56041893              ; double 0.035499999999999997
	.quad	0x3f9cc63f141205bc              ; double 0.0281
	.quad	0x0000000000000000              ; double 0
	.quad	0x0000000000000000              ; double 0
	.quad	0x0000000000000000              ; double 0
	.quad	0x3facc63f141205bc              ; double 0.0562
	.quad	0x3fb4538ef34d6a16              ; double 0.079399999999999998
	.quad	0x3facc63f141205bc              ; double 0.0562
	.quad	0x3fa22d0e56041893              ; double 0.035499999999999997
	.quad	0x3f99b3d07c84b5dd              ; double 0.025100000000000001
	.quad	0x0000000000000000              ; double 0
	.quad	0x3fa4538ef34d6a16              ; double 0.039699999999999999
	.quad	0x3fb4538ef34d6a16              ; double 0.079399999999999998
	.quad	0x0000000000000000              ; double 0
	.quad	0x3fb4538ef34d6a16              ; double 0.079399999999999998
	.quad	0x3fa4538ef34d6a16              ; double 0.039699999999999999
	.quad	0x0000000000000000              ; double 0
	.quad	0x3f99b3d07c84b5dd              ; double 0.025100000000000001
	.quad	0x3fa22d0e56041893              ; double 0.035499999999999997
	.quad	0x3facc63f141205bc              ; double 0.0562
	.quad	0x3fb4538ef34d6a16              ; double 0.079399999999999998
	.quad	0x3facc63f141205bc              ; double 0.0562
	.quad	0x0000000000000000              ; double 0
	.quad	0x0000000000000000              ; double 0
	.quad	0x0000000000000000              ; double 0
	.quad	0x3f9cc63f141205bc              ; double 0.0281
	.quad	0x3fa22d0e56041893              ; double 0.035499999999999997
	.quad	0x3fa4538ef34d6a16              ; double 0.039699999999999999
	.quad	0x0000000000000000              ; double 0
	.quad	0x0000000000000000              ; double 0
	.quad	0x0000000000000000              ; double 0
	.quad	0x0000000000000000              ; double 0
	.quad	0x0000000000000000              ; double 0
	.quad	0x3f99b3d07c84b5dd              ; double 0.025100000000000001
	.quad	0x0000000000000000              ; double 0
	.quad	0x0000000000000000              ; double 0
	.quad	0x0000000000000000              ; double 0
	.quad	0x0000000000000000              ; double 0
	.size	mask3, 392

	.protected	mask4                   ; @mask4
	.type	mask4,@object
	.globl	mask4
	.p2align	4, 0x0
mask4:
	.quad	0x0000000000000000              ; double 0
	.quad	0x0000000000000000              ; double 0
	.quad	0x3f99b3d07c84b5dd              ; double 0.025100000000000001
	.quad	0x0000000000000000              ; double 0
	.quad	0x0000000000000000              ; double 0
	.quad	0x0000000000000000              ; double 0
	.quad	0x0000000000000000              ; double 0
	.quad	0x0000000000000000              ; double 0
	.quad	0x3f9cc63f141205bc              ; double 0.0281
	.quad	0x3fa22d0e56041893              ; double 0.035499999999999997
	.quad	0x3fa4538ef34d6a16              ; double 0.039699999999999999
	.quad	0x0000000000000000              ; double 0
	.quad	0x0000000000000000              ; double 0
	.quad	0x0000000000000000              ; double 0
	.quad	0x3f99b3d07c84b5dd              ; double 0.025100000000000001
	.quad	0x3fa22d0e56041893              ; double 0.035499999999999997
	.quad	0x3facc63f141205bc              ; double 0.0562
	.quad	0x3fb4538ef34d6a16              ; double 0.079399999999999998
	.quad	0x3facc63f141205bc              ; double 0.0562
	.quad	0x0000000000000000              ; double 0
	.quad	0x0000000000000000              ; double 0
	.quad	0x0000000000000000              ; double 0
	.quad	0x3fa4538ef34d6a16              ; double 0.039699999999999999
	.quad	0x3fb4538ef34d6a16              ; double 0.079399999999999998
	.quad	0x0000000000000000              ; double 0
	.quad	0x3fb4538ef34d6a16              ; double 0.079399999999999998
	.quad	0x3fa4538ef34d6a16              ; double 0.039699999999999999
	.quad	0x0000000000000000              ; double 0
	.quad	0x0000000000000000              ; double 0
	.quad	0x0000000000000000              ; double 0
	.quad	0x3facc63f141205bc              ; double 0.0562
	.quad	0x3fb4538ef34d6a16              ; double 0.079399999999999998
	.quad	0x3facc63f141205bc              ; double 0.0562
	.quad	0x3fa22d0e56041893              ; double 0.035499999999999997
	.quad	0x3f99b3d07c84b5dd              ; double 0.025100000000000001
	.quad	0x0000000000000000              ; double 0
	.quad	0x0000000000000000              ; double 0
	.quad	0x0000000000000000              ; double 0
	.quad	0x3fa4538ef34d6a16              ; double 0.039699999999999999
	.quad	0x3fa22d0e56041893              ; double 0.035499999999999997
	.quad	0x3f9cc63f141205bc              ; double 0.0281
	.quad	0x0000000000000000              ; double 0
	.quad	0x0000000000000000              ; double 0
	.quad	0x0000000000000000              ; double 0
	.quad	0x0000000000000000              ; double 0
	.quad	0x0000000000000000              ; double 0
	.quad	0x3f99b3d07c84b5dd              ; double 0.025100000000000001
	.quad	0x0000000000000000              ; double 0
	.quad	0x0000000000000000              ; double 0
	.size	mask4, 392

	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.amdgpu_metadata
---
amdhsa.kernels:  []
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
