/*
 *  file name: matrix.cu
 *
 *  matrix.cu contains the code that realize some common used matrix operations in CUDA
 *  
 *  this is a toy program for learning CUDA, some functions are reusable in other project
 *  
 */
#include <stdio.h>
#include <stdlib.h>
#include <assert.h>
#include <unistd.h>

#define BLOCK_SIZE 16

/*
*********************************************************************
function name: gpu_square_matrix_mult

description: dot product of two matrix (not only square) in GPU

parameters: 
            &a GPU device pointer to a n X n matrix (A)
            &b GPU device pointer to a n X n matrix (B)
            &c GPU device output purpose pointer to a n X n matrix (C) 
            to store the result
Note:
    grid and block should be configured as:

        dim3 dim_grid((n - 1) / BLOCK_SIZE + 1, (n - 1) / BLOCK_SIZE + 1, 1);
        dim3 dim_block(BLOCK_SIZE, BLOCK_SIZE, 1);

return: none
*********************************************************************
*/
__global__ void gpu_square_matrix_mult(int *d_M, int *d_N, int *d_result, int width) 
{
    __shared__ int Mds[BLOCK_SIZE][BLOCK_SIZE];
    __shared__ int Nds[BLOCK_SIZE][BLOCK_SIZE];

    int bx = blockIdx.x;
    int by = blockIdx.y;

    int tx = threadIdx.x;
    int ty = threadIdx.y;
    
    int row = by * BLOCK_SIZE + ty;
    int col = bx * BLOCK_SIZE + tx;
    
    int p_val = 0;

    //ph -> phrase
    for (int ph = 0; ph < ceil(width/(float)BLOCK_SIZE); ++ph) {

    	if ((row < width) && (ph*BLOCK_SIZE + tx) < width) {
	   Mds[ty][tx] = d_M[row*width + ph*BLOCK_SIZE + tx];
	} else {
	   Mds[ty][tx] = 0; // assign 0 is position is not within input dim
	}

	if ((col < width) && (ph*BLOCK_SIZE + ty) < width) {
	   Nds[ty][tx] = d_N[(ph*BLOCK_SIZE + ty) * width + col];
	} else {
	  Nds[ty][tx] = 0;
	}
	__syncthreads();

	for (int k = 0; k < BLOCK_SIZE; ++k) {
	    p_val += Mds[ty][k] * Nds[k][tx];
	}
	__syncthreads();
    }

    if ((row < width) && (col < width)) {
       d_result[row * width + col] = p_val;
    }
}

/*
*********************************************************************
function name: cpu_matrix_mult

description: dot product of two matrix (not only square) in CPU, 
             for validating GPU results

parameters: 
            &a CPU host pointer to a m X n matrix (A)
            &b CPU host pointer to a n X k matrix (B)
            &c CPU host output purpose pointer to a m X k matrix (C) 
            to store the result
return: none
*********************************************************************
*/
void cpu_matrix_mult(int *h_a, int *h_b, int *h_result, int m, int n, int k) {
    for (int i = 0; i < m; ++i) 
    {
        for (int j = 0; j < k; ++j) 
        {
            int tmp = 0.0;
            for (int h = 0; h < n; ++h) 
            {
                tmp += h_a[i * n + h] * h_b[h * k + j];
            }
            h_result[i * k + j] = tmp;
        }
    }
}

int main(int argc, char const *argv[])
{
    int m, n, k;
    /* Fixed seed for illustration */
    srand(3333);
    printf("please type in m n and k\n");
    scanf("%d %d %d", &m, &n, &k);


    // allocate memory in host RAM, h_cc is used to store CPU result
    int *h_a = NULL, *h_b, *h_c, *h_cc;
    cudaError_t err = cudaMallocHost((void **) &h_a, sizeof(int)*m*n);
    printf("Error status is %s\n",cudaGetErrorString(err));
    printf("%p\n", h_a);
    cudaMallocHost((void **) &h_b, sizeof(int)*n*k);
    cudaMallocHost((void **) &h_c, sizeof(int)*m*k);
    cudaMallocHost((void **) &h_cc, sizeof(int)*m*k);

    // random initialize matrix A
    for (int i = 0; i < m; ++i) {
        for (int j = 0; j < n; ++j) {
            h_a[i * n + j] = rand() % 1024;
        }
    }

    // random initialize matrix B
    for (int i = 0; i < n; ++i) {
        for (int j = 0; j < k; ++j) {
            h_b[i * k + j] = rand() % 1024;
        }
    }
    float gpu_elapsed_time_ms, cpu_elapsed_time_ms;

    // some events to count the execution time
    cudaEvent_t start, stop;
    cudaEventCreate(&start);
    cudaEventCreate(&stop);

    // start to count execution time of GPU version
    cudaEventRecord(start, 0);
    // Allocate memory space on the device 
    int *d_a, *d_b, *d_c;
    cudaMalloc((void **) &d_a, sizeof(int)*m*n);
    cudaMalloc((void **) &d_b, sizeof(int)*n*k);
    cudaMalloc((void **) &d_c, sizeof(int)*m*k);

    // copy matrix A and B from host to device memory
    cudaMemcpy(d_a, h_a, sizeof(int)*m*n, cudaMemcpyHostToDevice);
    cudaMemcpy(d_b, h_b, sizeof(int)*n*k, cudaMemcpyHostToDevice);

    unsigned int grid_rows = (m + BLOCK_SIZE - 1) / BLOCK_SIZE;
    unsigned int grid_cols = (k + BLOCK_SIZE - 1) / BLOCK_SIZE;
    
    dim3 dimGrid(grid_cols, grid_rows);
    dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE);
   
    // Launch kernel 
    gpu_square_matrix_mult<<<dimGrid, dimBlock>>>(d_a, d_b, d_c, n);    
    // Transefr results from device to host 
    cudaMemcpy(h_c, d_c, sizeof(int)*m*k, cudaMemcpyDeviceToHost);
    cudaDeviceSynchronize();
    // time counting terminate
    cudaEventRecord(stop, 0);
    cudaEventSynchronize(stop);

    // compute time elapse on GPU computing
    cudaEventElapsedTime(&gpu_elapsed_time_ms, start, stop);
    printf("Time elapsed on matrix multiplication of %dx%d . %dx%d on GPU: %f ms.\n\n", m, n, n, k, gpu_elapsed_time_ms);

    // start the CPU version
    cudaEventRecord(start, 0);

    cpu_matrix_mult(h_a, h_b, h_cc, m, n, k);

    cudaEventRecord(stop, 0);
    cudaEventSynchronize(stop);
    cudaEventElapsedTime(&cpu_elapsed_time_ms, start, stop);
    printf("Time elapsed on matrix multiplication of %dx%d . %dx%d on CPU: %f ms.\n\n", m, n, n, k, cpu_elapsed_time_ms);

    // validate results computed by GPU
    int all_ok = 1;
    for (int i = 0; i < m; ++i)
    {
        for (int j = 0; j < k; ++j)
        {

            if(h_cc[i*k + j] != h_c[i*k + j])
            {
                printf("[%d][%d]:%d == [%d][%d]:%d, ", i, j, h_cc[i*k + j], i, j, h_c[i*k + j]);
                all_ok = 0;
            }
        }
        printf("\n");
    }

    // roughly compute speedup
    if(all_ok)
    {
        printf("all results are correct!!!, speedup = %f\n", cpu_elapsed_time_ms / gpu_elapsed_time_ms);
    }
    else
    {
        printf("incorrect results\n");
    }

    // free memory
    cudaFree(d_a);
    cudaFree(d_b);
    cudaFree(d_c);
    cudaFreeHost(h_a);
    cudaFreeHost(h_b);
    cudaFreeHost(h_c);
    cudaFreeHost(h_cc);
    return 0;
}

	.file	"tmpxft_0034e310_00000000-6_matrix_cuda_v2.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2044:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2044:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z15cpu_matrix_multPiS_S_iii
	.type	_Z15cpu_matrix_multPiS_S_iii, @function
_Z15cpu_matrix_multPiS_S_iii:
.LFB2040:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movslq	%r9d, %rax
	movq	%rsi, %r11
	xorl	%r10d, %r10d
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	salq	$2, %rax
	xorl	%esi, %esi
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movl	%ecx, %ebx
	xorl	%ecx, %ecx
	movq	%rdx, -8(%rsp)
	movq	%rax, -16(%rsp)
.L3:
	cmpl	%ebx, %r10d
	jge	.L2
	movq	-8(%rsp), %rdx
	movslq	%esi, %rax
	leaq	(%rdx,%rax,4), %r15
	movslq	%ecx, %rax
	leaq	(%rdi,%rax,4), %r14
	xorl	%eax, %eax
.L8:
	cmpl	%eax, %r9d
	jle	.L5
	leaq	(%r11,%rax,4), %r12
	xorl	%edx, %edx
	xorl	%ebp, %ebp
.L6:
	cmpl	%edx, %r8d
	jle	.L11
	movl	(%r14,%rdx,4), %r13d
	imull	(%r12), %r13d
	incq	%rdx
	addl	%r13d, %ebp
	movq	-16(%rsp), %r13
	addq	%r13, %r12
	jmp	.L6
.L11:
	movl	%ebp, (%r15,%rax,4)
	incq	%rax
	jmp	.L8
.L5:
	incl	%r10d
	addl	%r9d, %esi
	addl	%r8d, %ecx
	jmp	.L3
.L2:
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2040:
	.size	_Z15cpu_matrix_multPiS_S_iii, .-_Z15cpu_matrix_multPiS_S_iii
	.globl	_Z47__device_stub__Z22gpu_square_matrix_multPiS_S_iPiS_S_i
	.type	_Z47__device_stub__Z22gpu_square_matrix_multPiS_S_iPiS_S_i, @function
_Z47__device_stub__Z22gpu_square_matrix_multPiS_S_iPiS_S_i:
.LFB2066:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 4(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L12
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z22gpu_square_matrix_multPiS_S_i(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L12:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L14
	call	__stack_chk_fail@PLT
.L14:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2066:
	.size	_Z47__device_stub__Z22gpu_square_matrix_multPiS_S_iPiS_S_i, .-_Z47__device_stub__Z22gpu_square_matrix_multPiS_S_iPiS_S_i
	.globl	_Z22gpu_square_matrix_multPiS_S_i
	.type	_Z22gpu_square_matrix_multPiS_S_i, @function
_Z22gpu_square_matrix_multPiS_S_i:
.LFB2067:
	.cfi_startproc
	endbr64
	jmp	_Z47__device_stub__Z22gpu_square_matrix_multPiS_S_iPiS_S_i
	.cfi_endproc
.LFE2067:
	.size	_Z22gpu_square_matrix_multPiS_S_i, .-_Z22gpu_square_matrix_multPiS_S_i
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"please type in m n and k\n"
.LC1:
	.string	"%d %d %d"
.LC2:
	.string	"Error status is %s\n"
.LC3:
	.string	"%p\n"
.LC4:
	.string	"Time elapsed on matrix multiplication of %dx%d . %dx%d on GPU: %f ms.\n\n"
.LC5:
	.string	"Time elapsed on matrix multiplication of %dx%d . %dx%d on CPU: %f ms.\n\n"
.LC6:
	.string	"[%d][%d]:%d == [%d][%d]:%d, "
.LC7:
	.string	"\n"
.LC8:
	.string	"all results are correct!!!, speedup = %f\n"
.LC9:
	.string	"incorrect results\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2041:
	.cfi_startproc
	endbr64
	pushq	%r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	movl	$3333, %edi
	pushq	%r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	movl	$1024, %r12d
	pushq	%rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	xorl	%ebx, %ebx
	subq	$136, %rsp
	.cfi_def_cfa_offset 176
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	call	srand@PLT
	leaq	.LC0(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	leaq	8(%rsp), %rdx
	xorl	%eax, %eax
	leaq	12(%rsp), %rcx
	leaq	4(%rsp), %rsi
	leaq	.LC1(%rip), %rdi
	call	__isoc23_scanf@PLT
	movslq	4(%rsp), %rsi
	movslq	8(%rsp), %rax
	xorl	%ecx, %ecx
	leaq	24(%rsp), %rdi
	movq	%rcx, 24(%rsp)
	imulq	%rax, %rsi
	salq	$2, %rsi
	call	cudaMallocHost@PLT
	movl	%eax, %edi
	call	cudaGetErrorString@PLT
	leaq	.LC2(%rip), %rsi
	movl	$2, %edi
	movq	%rax, %rdx
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movq	24(%rsp), %rdx
	leaq	.LC3(%rip), %rsi
	xorl	%eax, %eax
	movl	$2, %edi
	call	__printf_chk@PLT
	movslq	8(%rsp), %rsi
	movslq	12(%rsp), %rax
	leaq	32(%rsp), %rdi
	imulq	%rax, %rsi
	salq	$2, %rsi
	call	cudaMallocHost@PLT
	movslq	4(%rsp), %rsi
	movslq	12(%rsp), %rax
	leaq	40(%rsp), %rdi
	imulq	%rax, %rsi
	salq	$2, %rsi
	call	cudaMallocHost@PLT
	movslq	4(%rsp), %rsi
	movslq	12(%rsp), %rax
	leaq	48(%rsp), %rdi
	imulq	%rax, %rsi
	salq	$2, %rsi
	call	cudaMallocHost@PLT
.L18:
	cmpl	%ebx, 4(%rsp)
	jle	.L36
	xorl	%ebp, %ebp
.L20:
	cmpl	%ebp, 8(%rsp)
	jle	.L37
	call	rand@PLT
	movl	8(%rsp), %ecx
	cltd
	idivl	%r12d
	movq	24(%rsp), %rax
	imull	%ebx, %ecx
	addl	%ebp, %ecx
	incl	%ebp
	movslq	%ecx, %rcx
	movl	%edx, (%rax,%rcx,4)
	jmp	.L20
.L37:
	incl	%ebx
	jmp	.L18
.L36:
	xorl	%ebx, %ebx
	movl	$1024, %r12d
.L21:
	cmpl	%ebx, 8(%rsp)
	jle	.L38
	xorl	%ebp, %ebp
.L23:
	cmpl	%ebp, 12(%rsp)
	jle	.L39
	call	rand@PLT
	movl	12(%rsp), %ecx
	cltd
	idivl	%r12d
	movq	32(%rsp), %rax
	imull	%ebx, %ecx
	addl	%ebp, %ecx
	incl	%ebp
	movslq	%ecx, %rcx
	movl	%edx, (%rax,%rcx,4)
	jmp	.L23
.L39:
	incl	%ebx
	jmp	.L21
.L38:
	leaq	56(%rsp), %rdi
	call	cudaEventCreate@PLT
	leaq	64(%rsp), %rdi
	call	cudaEventCreate@PLT
	movq	56(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movslq	4(%rsp), %rsi
	movslq	8(%rsp), %rax
	leaq	72(%rsp), %rdi
	imulq	%rax, %rsi
	salq	$2, %rsi
	call	cudaMalloc@PLT
	movslq	8(%rsp), %rsi
	movslq	12(%rsp), %rax
	leaq	80(%rsp), %rdi
	imulq	%rax, %rsi
	salq	$2, %rsi
	call	cudaMalloc@PLT
	movslq	4(%rsp), %rsi
	movslq	12(%rsp), %rax
	leaq	88(%rsp), %rdi
	imulq	%rax, %rsi
	salq	$2, %rsi
	call	cudaMalloc@PLT
	movslq	4(%rsp), %rdx
	movslq	8(%rsp), %rax
	movl	$1, %ecx
	movq	24(%rsp), %rsi
	movq	72(%rsp), %rdi
	imulq	%rax, %rdx
	salq	$2, %rdx
	call	cudaMemcpy@PLT
	movslq	8(%rsp), %rdx
	movslq	12(%rsp), %rax
	movl	$1, %ecx
	movq	32(%rsp), %rsi
	movq	80(%rsp), %rdi
	imulq	%rax, %rdx
	salq	$2, %rdx
	call	cudaMemcpy@PLT
	movl	4(%rsp), %eax
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$16, %esi
	movl	$1, 104(%rsp)
	addl	$15, %eax
	movl	$1, 116(%rsp)
	cltd
	idivl	%esi
	movl	%eax, %ecx
	movl	12(%rsp), %eax
	movl	%ecx, 100(%rsp)
	movl	$1, %ecx
	addl	$15, %eax
	cltd
	idivl	%esi
	movabsq	$68719476752, %rdx
	movl	$1, %esi
	movq	%rdx, 108(%rsp)
	movl	%eax, 96(%rsp)
	movq	96(%rsp), %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L24
	movl	8(%rsp), %ecx
	movq	88(%rsp), %rdx
	movq	80(%rsp), %rsi
	movq	72(%rsp), %rdi
	call	_Z47__device_stub__Z22gpu_square_matrix_multPiS_S_iPiS_S_i
.L24:
	movslq	4(%rsp), %rdx
	movslq	12(%rsp), %rax
	movl	$2, %ecx
	xorl	%ebx, %ebx
	movq	88(%rsp), %rsi
	movq	40(%rsp), %rdi
	movl	$1, %r13d
	leaq	.LC6(%rip), %rbp
	imulq	%rax, %rdx
	salq	$2, %rdx
	call	cudaMemcpy@PLT
	call	cudaDeviceSynchronize@PLT
	movq	64(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movq	64(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movq	64(%rsp), %rdx
	movq	56(%rsp), %rsi
	leaq	16(%rsp), %rdi
	call	cudaEventElapsedTime@PLT
	movl	8(%rsp), %ecx
	movl	12(%rsp), %r9d
	movb	$1, %al
	movl	4(%rsp), %edx
	leaq	.LC4(%rip), %rsi
	movl	$2, %edi
	cvtss2sd	16(%rsp), %xmm0
	movl	%ecx, %r8d
	call	__printf_chk@PLT
	movq	56(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movl	12(%rsp), %r9d
	movl	8(%rsp), %r8d
	movl	4(%rsp), %ecx
	movq	48(%rsp), %rdx
	movq	32(%rsp), %rsi
	movq	24(%rsp), %rdi
	call	_Z15cpu_matrix_multPiS_S_iii
	movq	64(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movq	64(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movq	64(%rsp), %rdx
	movq	56(%rsp), %rsi
	leaq	20(%rsp), %rdi
	call	cudaEventElapsedTime@PLT
	movl	8(%rsp), %ecx
	movl	12(%rsp), %r9d
	movb	$1, %al
	movl	4(%rsp), %edx
	leaq	.LC5(%rip), %rsi
	movl	$2, %edi
	cvtss2sd	20(%rsp), %xmm0
	movl	%ecx, %r8d
	call	__printf_chk@PLT
.L25:
	cmpl	%ebx, 4(%rsp)
	jle	.L40
	xorl	%r12d, %r12d
.L28:
	movl	12(%rsp), %eax
	cmpl	%r12d, %eax
	jle	.L41
	imull	%ebx, %eax
	movq	48(%rsp), %rdx
	addl	%r12d, %eax
	cltq
	movl	(%rdx,%rax,4), %r8d
	movq	40(%rsp), %rdx
	movl	(%rdx,%rax,4), %eax
	cmpl	%eax, %r8d
	je	.L26
	pushq	%rax
	.cfi_def_cfa_offset 184
	movl	%ebx, %edx
	movl	%ebx, %r9d
	movl	%r12d, %ecx
	pushq	%r12
	.cfi_def_cfa_offset 192
	movq	%rbp, %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	xorl	%r13d, %r13d
	call	__printf_chk@PLT
	popq	%rax
	.cfi_def_cfa_offset 184
	popq	%rdx
	.cfi_def_cfa_offset 176
.L26:
	incl	%r12d
	jmp	.L28
.L41:
	leaq	.LC7(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	incl	%ebx
	call	__printf_chk@PLT
	jmp	.L25
.L40:
	testl	%r13d, %r13d
	je	.L29
	leaq	.LC8(%rip), %rsi
	movl	$2, %edi
	movb	$1, %al
	movss	20(%rsp), %xmm0
	divss	16(%rsp), %xmm0
	cvtss2sd	%xmm0, %xmm0
	call	__printf_chk@PLT
	jmp	.L30
.L29:
	leaq	.LC9(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
.L30:
	movq	72(%rsp), %rdi
	call	cudaFree@PLT
	movq	80(%rsp), %rdi
	call	cudaFree@PLT
	movq	88(%rsp), %rdi
	call	cudaFree@PLT
	movq	24(%rsp), %rdi
	call	cudaFreeHost@PLT
	movq	32(%rsp), %rdi
	call	cudaFreeHost@PLT
	movq	40(%rsp), %rdi
	call	cudaFreeHost@PLT
	movq	48(%rsp), %rdi
	call	cudaFreeHost@PLT
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L31
	call	__stack_chk_fail@PLT
.L31:
	addq	$136, %rsp
	.cfi_def_cfa_offset 40
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2041:
	.size	main, .-main
	.section	.rodata.str1.1
.LC10:
	.string	"_Z22gpu_square_matrix_multPiS_S_i"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2069:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC10(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z22gpu_square_matrix_multPiS_S_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2069:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

/*
 *  file name: matrix.cu
 *
 *  matrix.cu contains the code that realize some common used matrix operations in CUDA
 *  
 *  this is a toy program for learning CUDA, some functions are reusable in other project
 *  
 */

#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <assert.h>
#include <unistd.h>

#define BLOCK_SIZE 16

/*
*********************************************************************
function name: gpu_square_matrix_mult

description: dot product of two matrix (not only square) in GPU

parameters: 
            &a GPU device pointer to a n X n matrix (A)
            &b GPU device pointer to a n X n matrix (B)
            &c GPU device output purpose pointer to a n X n matrix (C) 
            to store the result
Note:
    grid and block should be configured as:

        dim3 dim_grid((n - 1) / BLOCK_SIZE + 1, (n - 1) / BLOCK_SIZE + 1, 1);
        dim3 dim_block(BLOCK_SIZE, BLOCK_SIZE, 1);

return: none
*********************************************************************
*/
__global__ void gpu_square_matrix_mult(int *d_M, int *d_N, int *d_result, int width) 
{
    __shared__ int Mds[BLOCK_SIZE][BLOCK_SIZE];
    __shared__ int Nds[BLOCK_SIZE][BLOCK_SIZE];

    int bx = blockIdx.x;
    int by = blockIdx.y;

    int tx = threadIdx.x;
    int ty = threadIdx.y;
    
    int row = by * BLOCK_SIZE + ty;
    int col = bx * BLOCK_SIZE + tx;
    
    int p_val = 0;

    //ph -> phrase
    for (int ph = 0; ph < ceil(width/(float)BLOCK_SIZE); ++ph) {

    	if ((row < width) && (ph*BLOCK_SIZE + tx) < width) {
	   Mds[ty][tx] = d_M[row*width + ph*BLOCK_SIZE + tx];
	} else {
	   Mds[ty][tx] = 0; // assign 0 is position is not within input dim
	}

	if ((col < width) && (ph*BLOCK_SIZE + ty) < width) {
	   Nds[ty][tx] = d_N[(ph*BLOCK_SIZE + ty) * width + col];
	} else {
	  Nds[ty][tx] = 0;
	}
	__syncthreads();

	for (int k = 0; k < BLOCK_SIZE; ++k) {
	    p_val += Mds[ty][k] * Nds[k][tx];
	}
	__syncthreads();
    }

    if ((row < width) && (col < width)) {
       d_result[row * width + col] = p_val;
    }
}

/*
*********************************************************************
function name: cpu_matrix_mult

description: dot product of two matrix (not only square) in CPU, 
             for validating GPU results

parameters: 
            &a CPU host pointer to a m X n matrix (A)
            &b CPU host pointer to a n X k matrix (B)
            &c CPU host output purpose pointer to a m X k matrix (C) 
            to store the result
return: none
*********************************************************************
*/
void cpu_matrix_mult(int *h_a, int *h_b, int *h_result, int m, int n, int k) {
    for (int i = 0; i < m; ++i) 
    {
        for (int j = 0; j < k; ++j) 
        {
            int tmp = 0.0;
            for (int h = 0; h < n; ++h) 
            {
                tmp += h_a[i * n + h] * h_b[h * k + j];
            }
            h_result[i * k + j] = tmp;
        }
    }
}

int main(int argc, char const *argv[])
{
    int m, n, k;
    /* Fixed seed for illustration */
    srand(3333);
    printf("please type in m n and k\n");
    scanf("%d %d %d", &m, &n, &k);


    // allocate memory in host RAM, h_cc is used to store CPU result
    int *h_a = NULL, *h_b, *h_c, *h_cc;
    hipError_t err = hipHostMalloc((void **) &h_a, sizeof(int)*m*n, hipHostMallocDefault);
    printf("Error status is %s\n",hipGetErrorString(err));
    printf("%p\n", h_a);
    hipHostMalloc((void **) &h_b, sizeof(int)*n*k, hipHostMallocDefault);
    hipHostMalloc((void **) &h_c, sizeof(int)*m*k, hipHostMallocDefault);
    hipHostMalloc((void **) &h_cc, sizeof(int)*m*k, hipHostMallocDefault);

    // random initialize matrix A
    for (int i = 0; i < m; ++i) {
        for (int j = 0; j < n; ++j) {
            h_a[i * n + j] = rand() % 1024;
        }
    }

    // random initialize matrix B
    for (int i = 0; i < n; ++i) {
        for (int j = 0; j < k; ++j) {
            h_b[i * k + j] = rand() % 1024;
        }
    }
    float gpu_elapsed_time_ms, cpu_elapsed_time_ms;

    // some events to count the execution time
    hipEvent_t start, stop;
    hipEventCreate(&start);
    hipEventCreate(&stop);

    // start to count execution time of GPU version
    hipEventRecord(start, 0);
    // Allocate memory space on the device 
    int *d_a, *d_b, *d_c;
    hipMalloc((void **) &d_a, sizeof(int)*m*n);
    hipMalloc((void **) &d_b, sizeof(int)*n*k);
    hipMalloc((void **) &d_c, sizeof(int)*m*k);

    // copy matrix A and B from host to device memory
    hipMemcpy(d_a, h_a, sizeof(int)*m*n, hipMemcpyHostToDevice);
    hipMemcpy(d_b, h_b, sizeof(int)*n*k, hipMemcpyHostToDevice);

    unsigned int grid_rows = (m + BLOCK_SIZE - 1) / BLOCK_SIZE;
    unsigned int grid_cols = (k + BLOCK_SIZE - 1) / BLOCK_SIZE;
    
    dim3 dimGrid(grid_cols, grid_rows);
    dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE);
   
    // Launch kernel 
    gpu_square_matrix_mult<<<dimGrid, dimBlock>>>(d_a, d_b, d_c, n);    
    // Transefr results from device to host 
    hipMemcpy(h_c, d_c, sizeof(int)*m*k, hipMemcpyDeviceToHost);
    hipDeviceSynchronize();
    // time counting terminate
    hipEventRecord(stop, 0);
    hipEventSynchronize(stop);

    // compute time elapse on GPU computing
    hipEventElapsedTime(&gpu_elapsed_time_ms, start, stop);
    printf("Time elapsed on matrix multiplication of %dx%d . %dx%d on GPU: %f ms.\n\n", m, n, n, k, gpu_elapsed_time_ms);

    // start the CPU version
    hipEventRecord(start, 0);

    cpu_matrix_mult(h_a, h_b, h_cc, m, n, k);

    hipEventRecord(stop, 0);
    hipEventSynchronize(stop);
    hipEventElapsedTime(&cpu_elapsed_time_ms, start, stop);
    printf("Time elapsed on matrix multiplication of %dx%d . %dx%d on CPU: %f ms.\n\n", m, n, n, k, cpu_elapsed_time_ms);

    // validate results computed by GPU
    int all_ok = 1;
    for (int i = 0; i < m; ++i)
    {
        for (int j = 0; j < k; ++j)
        {

            if(h_cc[i*k + j] != h_c[i*k + j])
            {
                printf("[%d][%d]:%d == [%d][%d]:%d, ", i, j, h_cc[i*k + j], i, j, h_c[i*k + j]);
                all_ok = 0;
            }
        }
        printf("\n");
    }

    // roughly compute speedup
    if(all_ok)
    {
        printf("all results are correct!!!, speedup = %f\n", cpu_elapsed_time_ms / gpu_elapsed_time_ms);
    }
    else
    {
        printf("incorrect results\n");
    }

    // free memory
    hipFree(d_a);
    hipFree(d_b);
    hipFree(d_c);
    hipHostFree(h_a);
    hipHostFree(h_b);
    hipHostFree(h_c);
    hipHostFree(h_cc);
    return 0;
}

	.text
	.file	"matrix_cuda_v2.hip"
	.globl	_Z37__device_stub__gpu_square_matrix_multPiS_S_i # -- Begin function _Z37__device_stub__gpu_square_matrix_multPiS_S_i
	.type	_Z37__device_stub__gpu_square_matrix_multPiS_S_i,@function
_Z37__device_stub__gpu_square_matrix_multPiS_S_i: # @_Z37__device_stub__gpu_square_matrix_multPiS_S_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	4(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z22gpu_square_matrix_multPiS_S_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z37__device_stub__gpu_square_matrix_multPiS_S_i, .Lfunc_end0-_Z37__device_stub__gpu_square_matrix_multPiS_S_i
	.cfi_endproc
                                        # -- End function
	.globl	_Z15cpu_matrix_multPiS_S_iii    # -- Begin function _Z15cpu_matrix_multPiS_S_iii
	.type	_Z15cpu_matrix_multPiS_S_iii,@function
_Z15cpu_matrix_multPiS_S_iii:           # @_Z15cpu_matrix_multPiS_S_iii
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%r9d, -36(%rsp)                 # 4-byte Spill
	movq	%rdx, -8(%rsp)                  # 8-byte Spill
	movq	%rsi, -16(%rsp)                 # 8-byte Spill
	movq	%rdi, -24(%rsp)                 # 8-byte Spill
	testl	%ecx, %ecx
	jle	.LBB1_7
# %bb.1:                                # %.preheader27.lr.ph
	movslq	-36(%rsp), %rax                 # 4-byte Folded Reload
	movl	%ecx, %r9d
	movl	%eax, %r10d
	movl	%r8d, %r11d
	movq	%rax, -32(%rsp)                 # 8-byte Spill
	leaq	(,%rax,4), %rbx
	xorl	%r14d, %r14d
	xorl	%r15d, %r15d
.LBB1_2:                                # %.preheader27
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB1_4 Depth 2
                                        #       Child Loop BB1_9 Depth 3
	cmpl	$0, -36(%rsp)                   # 4-byte Folded Reload
	jle	.LBB1_6
# %bb.3:                                # %.preheader.lr.ph
                                        #   in Loop: Header=BB1_2 Depth=1
	movl	%r14d, %eax
	movq	-24(%rsp), %rcx                 # 8-byte Reload
	leaq	(%rcx,%rax,4), %r12
	movq	%r15, %rax
	imulq	-32(%rsp), %rax                 # 8-byte Folded Reload
	movq	-8(%rsp), %rcx                  # 8-byte Reload
	leaq	(%rcx,%rax,4), %r13
	movq	-16(%rsp), %rdi                 # 8-byte Reload
	xorl	%eax, %eax
.LBB1_4:                                # %.preheader
                                        #   Parent Loop BB1_2 Depth=1
                                        # =>  This Loop Header: Depth=2
                                        #       Child Loop BB1_9 Depth 3
	testl	%r8d, %r8d
	jle	.LBB1_5
# %bb.8:                                # %.lr.ph.preheader
                                        #   in Loop: Header=BB1_4 Depth=2
	xorl	%esi, %esi
	movq	%rdi, %rbp
	xorl	%edx, %edx
.LBB1_9:                                # %.lr.ph
                                        #   Parent Loop BB1_2 Depth=1
                                        #     Parent Loop BB1_4 Depth=2
                                        # =>    This Inner Loop Header: Depth=3
	movl	(%rbp), %ecx
	imull	(%r12,%rsi,4), %ecx
	addl	%ecx, %edx
	incq	%rsi
	addq	%rbx, %rbp
	cmpq	%rsi, %r11
	jne	.LBB1_9
	jmp	.LBB1_10
.LBB1_5:                                #   in Loop: Header=BB1_4 Depth=2
	xorl	%edx, %edx
.LBB1_10:                               # %._crit_edge
                                        #   in Loop: Header=BB1_4 Depth=2
	movl	%edx, (%r13,%rax,4)
	incq	%rax
	addq	$4, %rdi
	cmpq	%r10, %rax
	jne	.LBB1_4
.LBB1_6:                                # %._crit_edge31
                                        #   in Loop: Header=BB1_2 Depth=1
	incq	%r15
	addl	%r8d, %r14d
	cmpq	%r9, %r15
	jne	.LBB1_2
.LBB1_7:                                # %._crit_edge33
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z15cpu_matrix_multPiS_S_iii, .Lfunc_end1-_Z15cpu_matrix_multPiS_S_iii
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$104, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	$3333, %edi                     # imm = 0xD05
	callq	srand
	movl	$.Lstr, %edi
	callq	puts@PLT
	xorl	%r13d, %r13d
	leaq	20(%rsp), %r14
	leaq	16(%rsp), %rbx
	leaq	12(%rsp), %r15
	movl	$.L.str.1, %edi
	movq	%r14, %rsi
	movq	%rbx, %rdx
	movq	%r15, %rcx
	xorl	%eax, %eax
	callq	__isoc23_scanf
	leaq	40(%rsp), %r12
	movq	$0, (%r12)
	movslq	(%r14), %rax
	movslq	(%rbx), %rsi
	imulq	%rax, %rsi
	shlq	$2, %rsi
	movq	%r12, %rdi
	xorl	%edx, %edx
	callq	hipHostMalloc
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.2, %edi
	movq	%rax, %rsi
	xorl	%eax, %eax
	callq	printf
	movq	(%r12), %rsi
	movl	$.L.str.3, %edi
	xorl	%eax, %eax
	callq	printf
	movslq	(%rbx), %rax
	movslq	(%r15), %rsi
	imulq	%rax, %rsi
	shlq	$2, %rsi
	leaq	32(%rsp), %rdi
	xorl	%edx, %edx
	callq	hipHostMalloc
	movslq	(%r14), %rax
	movslq	(%r15), %rsi
	imulq	%rax, %rsi
	shlq	$2, %rsi
	leaq	72(%rsp), %rdi
	xorl	%edx, %edx
	callq	hipHostMalloc
	movslq	(%r14), %rax
	movslq	(%r15), %rsi
	imulq	%rax, %rsi
	shlq	$2, %rsi
	leaq	64(%rsp), %rdi
	xorl	%edx, %edx
	callq	hipHostMalloc
	movl	(%r14), %ecx
	movl	(%rbx), %eax
	testl	%ecx, %ecx
	jle	.LBB2_6
.LBB2_1:                                # %.preheader55
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB2_3 Depth 2
	testl	%eax, %eax
	jle	.LBB2_5
# %bb.2:                                # %.lr.ph.preheader
                                        #   in Loop: Header=BB2_1 Depth=1
	movslq	%r13d, %rbx
	xorl	%r14d, %r14d
.LBB2_3:                                # %.lr.ph
                                        #   Parent Loop BB2_1 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	callq	rand
                                        # kill: def $eax killed $eax def $rax
	leal	1023(%rax), %ecx
	testl	%eax, %eax
	cmovnsl	%eax, %ecx
	andl	$-1024, %ecx                    # imm = 0xFC00
	subl	%ecx, %eax
	movq	40(%rsp), %rcx
	movslq	16(%rsp), %rdx
	imulq	%rbx, %rdx
	addq	%r14, %rdx
	movl	%eax, (%rcx,%rdx,4)
	movl	16(%rsp), %eax
	incq	%r14
	cmpl	%eax, %r14d
	jl	.LBB2_3
# %bb.4:                                # %._crit_edge.loopexit
                                        #   in Loop: Header=BB2_1 Depth=1
	movl	20(%rsp), %ecx
.LBB2_5:                                # %._crit_edge
                                        #   in Loop: Header=BB2_1 Depth=1
	incl	%r13d
	cmpl	%ecx, %r13d
	jl	.LBB2_1
.LBB2_6:                                # %.preheader54
	testl	%eax, %eax
	jle	.LBB2_13
# %bb.7:                                # %.preheader53.preheader
	xorl	%ebx, %ebx
	movl	12(%rsp), %ecx
.LBB2_8:                                # %.preheader53
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB2_10 Depth 2
	testl	%ecx, %ecx
	jle	.LBB2_12
# %bb.9:                                # %.lr.ph59.preheader
                                        #   in Loop: Header=BB2_8 Depth=1
	movslq	%ebx, %r14
	xorl	%r15d, %r15d
.LBB2_10:                               # %.lr.ph59
                                        #   Parent Loop BB2_8 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	callq	rand
                                        # kill: def $eax killed $eax def $rax
	leal	1023(%rax), %ecx
	testl	%eax, %eax
	cmovnsl	%eax, %ecx
	andl	$-1024, %ecx                    # imm = 0xFC00
	subl	%ecx, %eax
	movq	32(%rsp), %rcx
	movslq	12(%rsp), %rdx
	imulq	%r14, %rdx
	addq	%r15, %rdx
	movl	%eax, (%rcx,%rdx,4)
	movl	12(%rsp), %ecx
	incq	%r15
	cmpl	%ecx, %r15d
	jl	.LBB2_10
# %bb.11:                               # %._crit_edge60.loopexit
                                        #   in Loop: Header=BB2_8 Depth=1
	movl	16(%rsp), %eax
.LBB2_12:                               # %._crit_edge60
                                        #   in Loop: Header=BB2_8 Depth=1
	incl	%ebx
	cmpl	%eax, %ebx
	jl	.LBB2_8
.LBB2_13:                               # %._crit_edge62
	leaq	56(%rsp), %rbx
	movq	%rbx, %rdi
	callq	hipEventCreate
	leaq	24(%rsp), %rdi
	callq	hipEventCreate
	movq	(%rbx), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movslq	20(%rsp), %rax
	movslq	16(%rsp), %rsi
	imulq	%rax, %rsi
	shlq	$2, %rsi
	leaq	96(%rsp), %r14
	movq	%r14, %rdi
	callq	hipMalloc
	movslq	16(%rsp), %rax
	movslq	12(%rsp), %rsi
	imulq	%rax, %rsi
	shlq	$2, %rsi
	leaq	88(%rsp), %rbx
	movq	%rbx, %rdi
	callq	hipMalloc
	movslq	20(%rsp), %rax
	movslq	12(%rsp), %rsi
	imulq	%rax, %rsi
	shlq	$2, %rsi
	leaq	48(%rsp), %rdi
	callq	hipMalloc
	movq	(%r14), %rdi
	movq	40(%rsp), %rsi
	movslq	20(%rsp), %rax
	movslq	16(%rsp), %rdx
	imulq	%rax, %rdx
	shlq	$2, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%rbx), %rdi
	movq	32(%rsp), %rsi
	movslq	16(%rsp), %rax
	movslq	12(%rsp), %rdx
	imulq	%rax, %rdx
	shlq	$2, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	movl	20(%rsp), %edi
	leal	15(%rdi), %eax
	addl	$30, %edi
	testl	%eax, %eax
	cmovnsl	%eax, %edi
	sarl	$4, %edi
	movl	12(%rsp), %eax
	leal	15(%rax), %ecx
	addl	$30, %eax
	testl	%ecx, %ecx
	cmovnsl	%ecx, %eax
	sarl	$4, %eax
	shlq	$32, %rdi
	orq	%rax, %rdi
	movabsq	$68719476752, %rdx              # imm = 0x1000000010
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_15
# %bb.14:
	movq	96(%rsp), %rdi
	movq	88(%rsp), %rsi
	movq	48(%rsp), %rdx
	movl	16(%rsp), %ecx
	callq	_Z37__device_stub__gpu_square_matrix_multPiS_S_i
.LBB2_15:
	movq	72(%rsp), %rdi
	movq	48(%rsp), %rsi
	movslq	20(%rsp), %rax
	movslq	12(%rsp), %rdx
	imulq	%rax, %rdx
	shlq	$2, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	callq	hipDeviceSynchronize
	movq	24(%rsp), %rdi
	xorl	%ebx, %ebx
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	24(%rsp), %rdi
	callq	hipEventSynchronize
	movq	56(%rsp), %rsi
	movq	24(%rsp), %rdx
	leaq	84(%rsp), %r14
	movq	%r14, %rdi
	callq	hipEventElapsedTime
	movl	20(%rsp), %esi
	movl	16(%rsp), %ecx
	movl	12(%rsp), %r8d
	cvtss2sd	(%r14), %xmm0
	movl	$.L.str.4, %edi
	movl	%ecx, %edx
	movb	$1, %al
	callq	printf
	movq	56(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	40(%rsp), %rdi
	movq	32(%rsp), %rsi
	movq	64(%rsp), %rdx
	movl	20(%rsp), %ecx
	movl	16(%rsp), %r8d
	movl	12(%rsp), %r9d
	callq	_Z15cpu_matrix_multPiS_S_iii
	movq	24(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	24(%rsp), %rdi
	callq	hipEventSynchronize
	movq	56(%rsp), %rsi
	movq	24(%rsp), %rdx
	leaq	80(%rsp), %r14
	movq	%r14, %rdi
	callq	hipEventElapsedTime
	movl	20(%rsp), %esi
	movl	16(%rsp), %ecx
	movl	12(%rsp), %r8d
	xorps	%xmm0, %xmm0
	cvtss2sd	(%r14), %xmm0
	movl	$.L.str.5, %edi
	movl	%ecx, %edx
	movb	$1, %al
	callq	printf
	cmpl	$0, 20(%rsp)
	jle	.LBB2_24
# %bb.16:                               # %.preheader.preheader
	movl	$1, %ebp
.LBB2_17:                               # %.preheader
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB2_19 Depth 2
	movl	12(%rsp), %eax
	testl	%eax, %eax
	jle	.LBB2_22
# %bb.18:                               # %.lr.ph65.preheader
                                        #   in Loop: Header=BB2_17 Depth=1
	xorl	%r14d, %r14d
.LBB2_19:                               # %.lr.ph65
                                        #   Parent Loop BB2_17 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movq	64(%rsp), %rcx
	movl	%ebx, %edx
	imull	%eax, %edx
	movslq	%edx, %rdx
	addq	%r14, %rdx
	movl	(%rcx,%rdx,4), %ecx
	movq	72(%rsp), %rsi
	movl	(%rsi,%rdx,4), %edx
	cmpl	%edx, %ecx
	je	.LBB2_21
# %bb.20:                               #   in Loop: Header=BB2_19 Depth=2
	movl	%edx, (%rsp)
	xorl	%ebp, %ebp
	movl	$.L.str.6, %edi
	movl	%ebx, %esi
	movl	%r14d, %edx
	movl	%ebx, %r8d
	movl	%r14d, %r9d
	xorl	%eax, %eax
	callq	printf
	movl	12(%rsp), %eax
.LBB2_21:                               #   in Loop: Header=BB2_19 Depth=2
	incq	%r14
	cmpl	%eax, %r14d
	jl	.LBB2_19
.LBB2_22:                               # %._crit_edge66
                                        #   in Loop: Header=BB2_17 Depth=1
	movl	$10, %edi
	callq	putchar@PLT
	incl	%ebx
	cmpl	20(%rsp), %ebx
	jl	.LBB2_17
# %bb.23:                               # %._crit_edge69
	testl	%ebp, %ebp
	je	.LBB2_25
.LBB2_24:                               # %._crit_edge69.thread
	movss	80(%rsp), %xmm0                 # xmm0 = mem[0],zero,zero,zero
	divss	84(%rsp), %xmm0
	cvtss2sd	%xmm0, %xmm0
	movl	$.L.str.8, %edi
	movb	$1, %al
	callq	printf
	jmp	.LBB2_26
.LBB2_25:
	movl	$.Lstr.1, %edi
	callq	puts@PLT
.LBB2_26:
	movq	96(%rsp), %rdi
	callq	hipFree
	movq	88(%rsp), %rdi
	callq	hipFree
	movq	48(%rsp), %rdi
	callq	hipFree
	movq	40(%rsp), %rdi
	callq	hipHostFree
	movq	32(%rsp), %rdi
	callq	hipHostFree
	movq	72(%rsp), %rdi
	callq	hipHostFree
	movq	64(%rsp), %rdi
	callq	hipHostFree
	xorl	%eax, %eax
	addq	$104, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	main, .Lfunc_end2-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB3_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB3_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z22gpu_square_matrix_multPiS_S_i, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end3:
	.size	__hip_module_ctor, .Lfunc_end3-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB4_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB4_2:
	retq
.Lfunc_end4:
	.size	__hip_module_dtor, .Lfunc_end4-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z22gpu_square_matrix_multPiS_S_i,@object # @_Z22gpu_square_matrix_multPiS_S_i
	.section	.rodata,"a",@progbits
	.globl	_Z22gpu_square_matrix_multPiS_S_i
	.p2align	3, 0x0
_Z22gpu_square_matrix_multPiS_S_i:
	.quad	_Z37__device_stub__gpu_square_matrix_multPiS_S_i
	.size	_Z22gpu_square_matrix_multPiS_S_i, 8

	.type	.L.str.1,@object                # @.str.1
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str.1:
	.asciz	"%d %d %d"
	.size	.L.str.1, 9

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"Error status is %s\n"
	.size	.L.str.2, 20

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"%p\n"
	.size	.L.str.3, 4

	.type	.L.str.4,@object                # @.str.4
.L.str.4:
	.asciz	"Time elapsed on matrix multiplication of %dx%d . %dx%d on GPU: %f ms.\n\n"
	.size	.L.str.4, 72

	.type	.L.str.5,@object                # @.str.5
.L.str.5:
	.asciz	"Time elapsed on matrix multiplication of %dx%d . %dx%d on CPU: %f ms.\n\n"
	.size	.L.str.5, 72

	.type	.L.str.6,@object                # @.str.6
.L.str.6:
	.asciz	"[%d][%d]:%d == [%d][%d]:%d, "
	.size	.L.str.6, 29

	.type	.L.str.8,@object                # @.str.8
.L.str.8:
	.asciz	"all results are correct!!!, speedup = %f\n"
	.size	.L.str.8, 42

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z22gpu_square_matrix_multPiS_S_i"
	.size	.L__unnamed_1, 34

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.type	.Lstr,@object                   # @str
	.section	.rodata.str1.1,"aMS",@progbits,1
.Lstr:
	.asciz	"please type in m n and k"
	.size	.Lstr, 25

	.type	.Lstr.1,@object                 # @str.1
.Lstr.1:
	.asciz	"incorrect results"
	.size	.Lstr.1, 18

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z37__device_stub__gpu_square_matrix_multPiS_S_i
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z22gpu_square_matrix_multPiS_S_i
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z22gpu_square_matrix_multPiS_S_i ; -- Begin function _Z22gpu_square_matrix_multPiS_S_i
	.globl	_Z22gpu_square_matrix_multPiS_S_i
	.p2align	8
	.type	_Z22gpu_square_matrix_multPiS_S_i,@function
_Z22gpu_square_matrix_multPiS_S_i:      ; @_Z22gpu_square_matrix_multPiS_S_i
; %bb.0:
	s_clause 0x2
	s_load_b32 s8, s[0:1], 0x18
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b64 s[2:3], s[0:1], 0x10
	v_bfe_u32 v4, v0, 10, 10
	v_and_b32_e32 v5, 0x3ff, v0
	s_mov_b32 s9, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshl_add_u32 v2, s15, 4, v4
	v_lshl_add_u32 v0, s14, 4, v5
	s_waitcnt lgkmcnt(0)
	v_cvt_f32_i32_e32 v1, s8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v1, 0x3d800000, v1
	v_ceil_f32_e32 v3, v1
	v_mov_b32_e32 v1, 0
	s_delay_alu instid0(VALU_DEP_2)
	v_cmp_nlt_f32_e32 vcc_lo, 0, v3
	s_cbranch_vccnz .LBB0_13
; %bb.1:                                ; %.lr.ph
	v_lshlrev_b32_e32 v1, 2, v5
	v_lshlrev_b32_e32 v6, 6, v4
	v_mul_lo_u32 v8, v2, s8
	v_cmp_gt_i32_e64 s0, s8, v2
	v_cmp_gt_i32_e64 s1, s8, v0
	v_add_nc_u32_e32 v7, 0x400, v1
	v_add_nc_u32_e32 v9, v6, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_dual_mov_b32 v1, 0 :: v_dual_add_nc_u32 v10, v7, v6
.LBB0_2:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_11 Depth 2
	v_mov_b32_e32 v11, 0
	s_and_saveexec_b32 s10, s0
	s_cbranch_execz .LBB0_6
; %bb.3:                                ;   in Loop: Header=BB0_2 Depth=1
	v_lshl_add_u32 v12, s9, 4, v5
	v_mov_b32_e32 v11, 0
	s_mov_b32 s11, exec_lo
	s_delay_alu instid0(VALU_DEP_2)
	v_cmpx_gt_i32_e64 s8, v12
	s_cbranch_execz .LBB0_5
; %bb.4:                                ;   in Loop: Header=BB0_2 Depth=1
	v_add_nc_u32_e32 v11, v12, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v12, 31, v11
	v_lshlrev_b64 v[11:12], 2, v[11:12]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v11, vcc_lo, s4, v11
	v_add_co_ci_u32_e32 v12, vcc_lo, s5, v12, vcc_lo
	global_load_b32 v11, v[11:12], off
.LBB0_5:                                ; %Flow81
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s11
.LBB0_6:                                ;   in Loop: Header=BB0_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s10
	v_mov_b32_e32 v12, 0
	s_waitcnt vmcnt(0)
	ds_store_b32 v9, v11
	s_and_saveexec_b32 s10, s1
	s_cbranch_execz .LBB0_10
; %bb.7:                                ;   in Loop: Header=BB0_2 Depth=1
	v_lshl_add_u32 v11, s9, 4, v4
	v_mov_b32_e32 v12, 0
	s_mov_b32 s11, exec_lo
	s_delay_alu instid0(VALU_DEP_2)
	v_cmpx_gt_i32_e64 s8, v11
	s_cbranch_execz .LBB0_9
; %bb.8:                                ;   in Loop: Header=BB0_2 Depth=1
	v_mad_u64_u32 v[12:13], null, v11, s8, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v13, 31, v12
	v_lshlrev_b64 v[11:12], 2, v[12:13]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v11, vcc_lo, s6, v11
	v_add_co_ci_u32_e32 v12, vcc_lo, s7, v12, vcc_lo
	global_load_b32 v12, v[11:12], off
.LBB0_9:                                ; %Flow
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s11
.LBB0_10:                               ;   in Loop: Header=BB0_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s10
	v_mov_b32_e32 v11, v7
	s_mov_b32 s10, 0
	s_waitcnt vmcnt(0)
	ds_store_b32 v10, v12
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
.LBB0_11:                               ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_add_nc_u32_e32 v12, s10, v6
	s_add_i32 s10, s10, 4
	ds_load_b32 v14, v11
	ds_load_b32 v15, v12
	v_add_nc_u32_e32 v11, 64, v11
	s_cmp_eq_u32 s10, 64
	s_waitcnt lgkmcnt(0)
	v_mad_u64_u32 v[12:13], null, v14, v15, v[1:2]
	s_delay_alu instid0(VALU_DEP_1)
	v_mov_b32_e32 v1, v12
	s_cbranch_scc0 .LBB0_11
; %bb.12:                               ;   in Loop: Header=BB0_2 Depth=1
	s_add_i32 s9, s9, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	v_cvt_f32_i32_e32 v11, s9
	s_barrier
	buffer_gl0_inv
	v_cmp_ngt_f32_e32 vcc_lo, v3, v11
	s_cbranch_vccz .LBB0_2
.LBB0_13:                               ; %Flow83
	v_max_i32_e32 v3, v2, v0
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e64 s8, v3
	s_cbranch_execz .LBB0_15
; %bb.14:
	v_mad_u64_u32 v[3:4], null, v2, s8, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v4, 31, v3
	v_lshlrev_b64 v[2:3], 2, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s2, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
	global_store_b32 v[2:3], v1, off
.LBB0_15:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z22gpu_square_matrix_multPiS_S_i
		.amdhsa_group_segment_fixed_size 2048
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 28
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 16
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z22gpu_square_matrix_multPiS_S_i, .Lfunc_end0-_Z22gpu_square_matrix_multPiS_S_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 588
; NumSgprs: 18
; NumVgprs: 16
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 2048 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 16
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
    .group_segment_fixed_size: 2048
    .kernarg_segment_align: 8
    .kernarg_segment_size: 28
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z22gpu_square_matrix_multPiS_S_i
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z22gpu_square_matrix_multPiS_S_i.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     16
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
