/*
	Name: Daniyal Manair
	Student Number: 20064993
*/
#include "cuda_runtime.h"
#include "device_launch_parameters.h"

#include <vector>
#include <stdio.h>
#include <random>
#include <algorithm>
#include <chrono>
#include <map>

__global__ void TiledMatrixMulGPU2(float* A, float* B, float* C, const int N) {
	__shared__ float t_A [2][2];
	__shared__ float t_B [2][2];

	unsigned int tileWidth = 2;
	unsigned int bx = blockIdx.x;
	unsigned int by = blockIdx.y;
	unsigned int tx = threadIdx.x;
	unsigned int ty = threadIdx.y;
	unsigned int row = by * tileWidth + ty;
	unsigned int col = bx * tileWidth + tx;

	float cValue = 0.0;
	for (int i = 0; i < (N / tileWidth); i++) {
		t_A[ty][tx] = A[row*N + i*tileWidth + tx];
		t_B[ty][tx] = B[(i*tileWidth + ty)*N + col];
		__syncthreads();
		for (int j = 0; j < tileWidth; j++)
			cValue += t_A[ty][j] * t_B[j][tx];
		__syncthreads();
	}
	C[row*N + col] = cValue;
}

__global__ void TiledMatrixMulGPU4(float* A, float* B, float* C, const int N) {
	__shared__ float t_A [4][4];
	__shared__ float t_B [4][4];

	unsigned int tileWidth = 4;
	unsigned int bx = blockIdx.x;
	unsigned int by = blockIdx.y;
	unsigned int tx = threadIdx.x;
	unsigned int ty = threadIdx.y;
	unsigned int row = by * tileWidth + ty;
	unsigned int col = bx * tileWidth + tx;

	float cValue = 0.0;
	for (int i = 0; i < (N / tileWidth); i++) {
		t_A[ty][tx] = A[row*N + i*tileWidth + tx];
		t_B[ty][tx] = B[(i*tileWidth + ty)*N + col];
		__syncthreads();
		for (int j = 0; j < tileWidth; j++)
			cValue += t_A[ty][j] * t_B[j][tx];
		__syncthreads();
	}
	C[row*N + col] = cValue;
}	


__global__ void TiledMatrixMulGPU10(float* A, float* B, float* C, const int N) {
	__shared__ float t_A [10][10];
	__shared__ float t_B [10][10];

	unsigned int tileWidth = 10;
	unsigned int bx = blockIdx.x;
	unsigned int by = blockIdx.y;
	unsigned int tx = threadIdx.x;
	unsigned int ty = threadIdx.y;
	unsigned int row = by * tileWidth + ty;
	unsigned int col = bx * tileWidth + tx;

	float cValue = 0.0;
	for (int i = 0; i < (N / tileWidth); i++) {
		t_A[ty][tx] = A[row*N + i*tileWidth + tx];
		t_B[ty][tx] = B[(i*tileWidth + ty)*N + col];
		__syncthreads();
		for (int j = 0; j < tileWidth; j++)
			cValue += t_A[ty][j] * t_B[j][tx];
		__syncthreads();
	}
	C[row*N + col] = cValue;
}

__global__ void TiledMatrixMulGPU20(float* A, float* B, float* C, const int N) {
	__shared__ float t_A [20][20];
	__shared__ float t_B [20][20];

	unsigned int tileWidth = 20;
	unsigned int bx = blockIdx.x;
	unsigned int by = blockIdx.y;
	unsigned int tx = threadIdx.x;
	unsigned int ty = threadIdx.y;
	unsigned int row = by * tileWidth + ty;
	unsigned int col = bx * tileWidth + tx;

	float cValue = 0.0;
	for (int i = 0; i < (N / tileWidth); i++) {
		t_A[ty][tx] = A[row*N + i*tileWidth + tx];
		t_B[ty][tx] = B[(i*tileWidth + ty)*N + col];
		__syncthreads();
		for (int j = 0; j < tileWidth; j++)
			cValue += t_A[ty][j] * t_B[j][tx];
		__syncthreads();
	}
	C[row*N + col] = cValue;
}

__global__ void TiledMatrixMulGPU25(float* A, float* B, float* C, int N) {
	__shared__ float t_A[25][25];
	__shared__ float t_B[25][25];

	unsigned int tileWidth = 25;
	unsigned int bx = blockIdx.x;
	unsigned int by = blockIdx.y;
	unsigned int tx = threadIdx.x;
	unsigned int ty = threadIdx.y;
	unsigned int row = by * tileWidth + ty;
	unsigned int col = bx * tileWidth + tx;

	float cValue = 0.0;
	for (int i = 0; i < (N / tileWidth); i++) {
		t_A[ty][tx] = A[row*N + i*tileWidth + tx];
		t_B[ty][tx] = B[(i*tileWidth + ty)*N + col];
		__syncthreads();
		for (int j = 0; j < tileWidth; j++)
			cValue += t_A[ty][j] * t_B[j][tx];
		__syncthreads();
	}
	C[row*N + col] = cValue;
}

void initialData(float* matrix, const int size){
	for (int i = 0; i < size; i++)
		matrix[i] = (float)(rand() & 0xFF) / 10.0f;
}

void MatrixMulCPU(float* A, float* B, float* C, const int N){
	for (int i = 0; i < N; i++) {
		for (int j = 0; j < N; j++) {
			for (int k = 0; k < N; k++) 
				C[i * N + j] += A[i * N + k] * B[k * N + j];
		}
	}
}

void checkResult(float* CPU, float* GPU, const int size) {
	double epsilon = 1.0E-8;
	
	for (int i = 0; i < size; i++){
		if (abs(CPU[i] - GPU[i]) > epsilon){
			printf("CPU %f GPU %f ", CPU[i], GPU[i]);
			printf("Arrays do not match.\n\n");
			return;
		}
	}
	printf("Test PASSED\n\n");
}

void printArr(float* matrix, const int size) {
	printf("[");
	for (int i = 0; i < size; i++)
		printf("%f,", matrix[i]);
	printf("\b]\n");

}

void GPUtest(float* C_A, float* C_B, float* CPUResult, const int tileSize, const int N){
	// Initialize variables
	cudaEvent_t gStart, gEnd;
	float timeDuration;
	float *G_A, *G_B, *G_C, *GPUResult;
	size_t size = N * N * sizeof(float);
	
	// Initialize GPU variables
	cudaMalloc((void**)&G_A, size);
	cudaMalloc((void**)&G_B, size);
	cudaMalloc((void**)&G_C, size);
	GPUResult = (float*)malloc(size);
	memset(GPUResult, 0.0, size);
	cudaEventCreate(&gStart);
    cudaEventCreate(&gEnd);
	
	// Copy over the data
	cudaMemcpy(G_A, C_A, size, cudaMemcpyHostToDevice);
	cudaMemcpy(G_B, C_B, size, cudaMemcpyHostToDevice);
	
	// Perform GPU comparison

	// Create block
	dim3 block(tileSize, tileSize, 1);
	dim3 grid((int)ceil((N + block.x - 1) / block.x),(int)ceil((N + block.y - 1) / block.y), 1);

	cudaEventRecord(gStart);
	if (tileSize == 2)
		TiledMatrixMulGPU2 <<<grid, block>>> (G_A, G_B, G_C, N);
	else if (tileSize == 4)
		TiledMatrixMulGPU4 <<<grid, block>>> (G_A, G_B, G_C, N);
	else if (tileSize == 10)
		TiledMatrixMulGPU10 <<<grid, block>>> (G_A, G_B, G_C, N);
	else if (tileSize == 20)
		TiledMatrixMulGPU20 <<<grid, block>>> (G_A, G_B, G_C, N);
	else if (tileSize == 25) 	
		TiledMatrixMulGPU25 <<<grid, block >>> (G_A, G_B, G_C, N);
	cudaEventRecord(gEnd);
	
	cudaEventSynchronize(gEnd);
	cudaEventElapsedTime(&timeDuration, gStart, gEnd);
	cudaMemcpy(GPUResult, G_C, size, cudaMemcpyDeviceToHost);
	printf("The GPU took %f to perform the computation with tile size %d.\n", timeDuration, tileSize);
	checkResult(CPUResult, GPUResult, N*N);
	
	cudaFree(G_A);
	cudaFree(G_B);
	cudaFree(G_C);
	free(GPUResult);

	FILE *fp;
	fp=fopen("machineProblem4.csv","a");
	fprintf(fp,"%d,%d,%f\n",N,tileSize,timeDuration);
	fclose(fp);
}

void computeMatrix(const int N) {
	// Initial prints
	printf("------------------------------------------------------------------------\n\n");
	printf("%dx%d matrix multiplication.\n\n", N, N);

	// Initialize Host variables
	float *C_A, *C_B, *C_C;
	size_t size = N * N * sizeof(float);
	
	// Initialize space
	C_A = (float*)malloc(size);
	C_B = (float*)malloc(size);
	C_C = (float*)malloc(size);
	
	// Set with random data
	initialData(C_A, N*N);
	initialData(C_B, N*N);
	memset(C_C, 0.0, size);

	// Serial Test CPU
	MatrixMulCPU(C_A, C_B, C_C, N);
	
	// Test Complete parallel Computation
	int tileSizes [] = {2, 4, 10, 20, 25};
	
	for (int i = 0; i < 5; i++)
		GPUtest(C_A, C_B, C_C, tileSizes[i], N);
	
	// Free all the memory
	free(C_A);
	free(C_B);
	free(C_C);
	cudaDeviceReset();
}

// --------------------BONUS-----------------------------

#define BONUSTILE_C 8
#define BONUSTILE_R 14

__global__ void TiledMatrixMulGPUBonus1(float* A, float* B, float* C, int M, int N, int K) {
	int Brows = N;
	int Crows = M;
	int Ccols = K;
	float cValue = 0;
	unsigned int bx = blockIdx.x;
	unsigned int by = blockIdx.y;
	unsigned int tx = threadIdx.x;
	unsigned int ty = threadIdx.y;
	int row = by*BONUSTILE_R + ty;
	int col = bx*BONUSTILE_C + tx;

	__shared__ float t_A[BONUSTILE_R][BONUSTILE_C];
	__shared__ float t_B[BONUSTILE_R][BONUSTILE_C];

	for (int i = 0; i < (BONUSTILE_C + N - 1) / 2; i++) {

		if (i*BONUSTILE_C + tx < N && row < M)
			t_A[ty][tx] = A[row*N + i*BONUSTILE_C + tx];
		else
			t_A[ty][tx] = 0.0;

		if (i*BONUSTILE_C + ty < Brows && col < K)
			t_B[ty][tx] = B[(i*BONUSTILE_C + ty)*K + col];
		else
			t_B[ty][tx] = 0.0;

		__syncthreads();

		for (int j = 0; j < BONUSTILE_C; j++)
			cValue += t_A[ty][j] * t_B[j][tx];

		__syncthreads();
	}

	if (row < Crows && col < Ccols)
		C[((by * blockDim.y + ty)*Ccols) + (bx * blockDim.x) + tx] = cValue;
}

__global__ void TiledMatrixMulGPUBonus(float* A, float* B, float* C, int M, int N, int K) {
	float cValue = 0;
	unsigned int bx = blockIdx.x;
	unsigned int by = blockIdx.y;
	unsigned int tx = threadIdx.x;
	unsigned int ty = threadIdx.y;
	int row = by*BONUSTILE_R + ty;
	int col = bx*BONUSTILE_C + tx;

	__shared__ float t_A[BONUSTILE_R][BONUSTILE_C];
	__shared__ float t_B[BONUSTILE_R][BONUSTILE_C];

	for (int i = 0; i < (BONUSTILE_C + N - 1) / 2; i++) {

		if (i*BONUSTILE_C + tx < N && row < M)
			t_A[ty][tx] = A[row*N + i*BONUSTILE_C + tx];
		else
			t_A[ty][tx] = 0.0;

		if (i*BONUSTILE_C + ty < N && col < K)
			t_B[ty][tx] = B[(i*BONUSTILE_C + ty)*K + col];
		else
			t_B[ty][tx] = 0.0;

		__syncthreads();

		for (int j = 0; j < BONUSTILE_C; j++)
			cValue += t_A[ty][j] * t_B[j][tx];

		__syncthreads();
	}

	if (row < M && col < K)
		C[((by * blockDim.y + ty)*K) + (bx * blockDim.x) + tx] = cValue;
}

void MatrixMulCPUBonus(float* A, float* B, float* C, const int M, const int N, const int K) {
	float cValue = 0.0;
	for (int i = 0; i < M; i++) {
		for (int j = 0; j < K; j++) {
			cValue = 0.0;
			for (int k = 0; k < N; k++) 
				cValue += A[i * N + k] * B[k * K + j];
			C[i * K + j] = cValue;
		}
	}
}

void computeMatrixBonus(const int M, const int N, const int K) {
	// Initial prints
	printf("------------------------------------------------------------------------\n\n");
	printf("%dx%d and %dx%d matrix multiplication with %dx%d tile size.\n\n", M, N, N, K, BONUSTILE_R, BONUSTILE_C);

	float *C_A, *C_B, *C_C, *GPUResult;
	size_t sizeA = M * N * sizeof(float);
	size_t sizeB = N * K * sizeof(float);
	size_t sizeC = M * K * sizeof(float);
	
	// Initialize space
	C_A = (float*)malloc(sizeA);
	C_B = (float*)malloc(sizeB);
	C_C = (float*)malloc(sizeC);
	GPUResult = (float*)malloc(sizeC);
	
	// Set with random data
	initialData(C_A, M * N);
	initialData(C_B, N * K);
	memset(C_C, 0.0, sizeC);
	memset(GPUResult, 0.0, sizeC);

	// Serial Test CPU
	MatrixMulCPUBonus(C_A, C_B, C_C, M, N, K);
	
	// GPU calculations
	float *G_A, *G_B, *G_C;
	
	// Initialize GPU variables
	cudaMalloc((void**)&G_A, sizeA);
	cudaMalloc((void**)&G_B, sizeB);
	cudaMalloc((void**)&G_C, sizeC);
	// Copy over values
	cudaMemcpy(G_A, C_A, sizeA, cudaMemcpyHostToDevice);
	cudaMemcpy(G_B, C_B, sizeB, cudaMemcpyHostToDevice);
	
	// Case 1 8x14
	dim3 block(BONUSTILE_C, BONUSTILE_R, 1);
	dim3 grid((K + block.x - 1) / block.x, (M + block.y - 1) / block.y, 1);
	
	TiledMatrixMulGPUBonus <<<grid, block>>> (G_A, G_B, G_C, M, N, K);
	cudaMemcpy(GPUResult, G_C, sizeC, cudaMemcpyDeviceToHost);
	checkResult(C_C, GPUResult, N*N);

	// Free all the memory
	free(C_A);
	free(C_B);
	free(C_C);
	free(GPUResult);
	cudaFree(G_A);
	cudaFree(G_B);
	cudaFree(G_C);
	cudaDeviceReset();
}

// ------------------------------------------------------


int main(){
	FILE *fp;
	fp=fopen("machineProblem4.csv","w");
	fprintf(fp,"matrixSize,tileSize,time\n");
	fclose(fp);
	int matrixWidths [] = {100, 200, 500, 1000, 1500, 5000};
	
	for (int i = 0; i < 6; i++)
		computeMatrix(matrixWidths[i]);

	printf("------------------------------------------------------------------------\n");
    
	printf("BONUS\n");
	
	computeMatrixBonus(2, 3, 4);
	computeMatrixBonus(250, 300, 450);
	printf("------------------------------------------------------------------------\n\n");
	return 0;
}

	.file	"tmpxft_002800e4_00000000-6_kernel.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4839:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE4839:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z11initialDataPfi
	.type	_Z11initialDataPfi, @function
_Z11initialDataPfi:
.LFB4828:
	.cfi_startproc
	endbr64
	pushq	%r12
	.cfi_def_cfa_offset 16
	.cfi_offset 12, -16
	movq	%rdi, %r12
	pushq	%rbp
	.cfi_def_cfa_offset 24
	.cfi_offset 6, -24
	movl	%esi, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset 3, -32
	xorl	%ebx, %ebx
.L3:
	cmpl	%ebx, %ebp
	jle	.L7
	call	rand@PLT
	movzbl	%al, %eax
	cvtsi2ssl	%eax, %xmm0
	divss	.LC0(%rip), %xmm0
	movss	%xmm0, (%r12,%rbx,4)
	incq	%rbx
	jmp	.L3
.L7:
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4828:
	.size	_Z11initialDataPfi, .-_Z11initialDataPfi
	.globl	_Z12MatrixMulCPUPfS_S_i
	.type	_Z12MatrixMulCPUPfS_S_i, @function
_Z12MatrixMulCPUPfS_S_i:
.LFB4829:
	.cfi_startproc
	endbr64
	pushq	%r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	movq	%rdx, %r10
	movq	%rdi, %r8
	xorl	%edx, %edx
	pushq	%r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	pushq	%rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	xorl	%ebp, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	movq	%rsi, %rbx
	movslq	%ecx, %rsi
	movq	%rsi, %rax
	salq	$2, %rsi
.L9:
	cmpl	%eax, %ebp
	jge	.L8
	movq	%rbx, %r11
	leaq	(%r10,%rdx), %rcx
	leaq	(%r8,%rdx), %r13
	xorl	%r9d, %r9d
.L13:
	movq	%r11, %r12
	xorl	%edi, %edi
.L10:
	movss	0(%r13,%rdi,4), %xmm0
	mulss	(%r12), %xmm0
	incq	%rdi
	addq	%rsi, %r12
	addss	(%rcx), %xmm0
	movss	%xmm0, (%rcx)
	cmpl	%edi, %eax
	jg	.L10
	incl	%r9d
	addq	$4, %r11
	addq	$4, %rcx
	cmpl	%r9d, %eax
	jne	.L13
	incl	%ebp
	addq	%rsi, %rdx
	jmp	.L9
.L8:
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4829:
	.size	_Z12MatrixMulCPUPfS_S_i, .-_Z12MatrixMulCPUPfS_S_i
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC3:
	.string	"CPU %f GPU %f "
.LC4:
	.string	"Arrays do not match.\n\n"
.LC5:
	.string	"Test PASSED\n\n"
	.text
	.globl	_Z11checkResultPfS_i
	.type	_Z11checkResultPfS_i, @function
_Z11checkResultPfS_i:
.LFB4830:
	.cfi_startproc
	endbr64
	movsd	.LC2(%rip), %xmm4
	xorl	%eax, %eax
	movss	.LC1(%rip), %xmm3
.L17:
	cmpl	%eax, %edx
	jle	.L25
	movss	(%rdi,%rax,4), %xmm0
	movss	(%rsi,%rax,4), %xmm1
	incq	%rax
	movaps	%xmm0, %xmm2
	subss	%xmm1, %xmm2
	andps	%xmm3, %xmm2
	cvtss2sd	%xmm2, %xmm2
	comisd	%xmm4, %xmm2
	jbe	.L17
	pushq	%rax
	.cfi_def_cfa_offset 16
	movl	$2, %edi
	movb	$2, %al
	cvtss2sd	%xmm0, %xmm0
	leaq	.LC3(%rip), %rsi
	cvtss2sd	%xmm1, %xmm1
	call	__printf_chk@PLT
	leaq	.LC4(%rip), %rsi
	xorl	%eax, %eax
	popq	%rdx
	.cfi_def_cfa_offset 8
	movl	$2, %edi
	jmp	.L24
.L25:
	leaq	.LC5(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
.L24:
	jmp	__printf_chk@PLT
	.cfi_endproc
.LFE4830:
	.size	_Z11checkResultPfS_i, .-_Z11checkResultPfS_i
	.section	.rodata.str1.1
.LC6:
	.string	"["
.LC7:
	.string	"%f,"
.LC8:
	.string	"\b]\n"
	.text
	.globl	_Z8printArrPfi
	.type	_Z8printArrPfi, @function
_Z8printArrPfi:
.LFB4831:
	.cfi_startproc
	endbr64
	pushq	%r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	xorl	%eax, %eax
	leaq	.LC7(%rip), %r13
	pushq	%r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	movq	%rdi, %r12
	movl	$2, %edi
	pushq	%rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	movl	%esi, %ebp
	leaq	.LC6(%rip), %rsi
	pushq	%rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	xorl	%ebx, %ebx
	pushq	%rcx
	.cfi_def_cfa_offset 48
	call	__printf_chk@PLT
.L27:
	cmpl	%ebx, %ebp
	jle	.L30
	movq	%r13, %rsi
	movl	$2, %edi
	movb	$1, %al
	cvtss2sd	(%r12,%rbx,4), %xmm0
	call	__printf_chk@PLT
	incq	%rbx
	jmp	.L27
.L30:
	popq	%rdx
	.cfi_def_cfa_offset 40
	leaq	.LC8(%rip), %rsi
	popq	%rbx
	.cfi_def_cfa_offset 32
	movl	$2, %edi
	popq	%rbp
	.cfi_def_cfa_offset 24
	xorl	%eax, %eax
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	__printf_chk@PLT
	.cfi_endproc
.LFE4831:
	.size	_Z8printArrPfi, .-_Z8printArrPfi
	.globl	_Z17MatrixMulCPUBonusPfS_S_iii
	.type	_Z17MatrixMulCPUBonusPfS_S_iii, @function
_Z17MatrixMulCPUBonusPfS_S_iii:
.LFB4834:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	xorl	%r10d, %r10d
	xorl	%r11d, %r11d
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movl	%ecx, %r12d
	xorl	%ecx, %ecx
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movq	%rsi, %rbp
	movq	%rdx, %rsi
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movslq	%r9d, %rbx
	salq	$2, %rbx
.L32:
	cmpl	%r12d, %r11d
	jge	.L31
	movslq	%r10d, %rax
	leaq	(%rsi,%rax,4), %r15
	movslq	%ecx, %rax
	leaq	(%rdi,%rax,4), %r14
	xorl	%eax, %eax
.L37:
	cmpl	%eax, %r9d
	jle	.L34
	leaq	0(%rbp,%rax,4), %r13
	xorl	%edx, %edx
	xorps	%xmm0, %xmm0
.L35:
	cmpl	%edx, %r8d
	jle	.L39
	movss	(%r14,%rdx,4), %xmm1
	mulss	0(%r13), %xmm1
	incq	%rdx
	addq	%rbx, %r13
	addss	%xmm1, %xmm0
	jmp	.L35
.L39:
	movss	%xmm0, (%r15,%rax,4)
	incq	%rax
	jmp	.L37
.L34:
	incl	%r11d
	addl	%r9d, %r10d
	addl	%r8d, %ecx
	jmp	.L32
.L31:
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4834:
	.size	_Z17MatrixMulCPUBonusPfS_S_iii, .-_Z17MatrixMulCPUBonusPfS_S_iii
	.globl	_Z43__device_stub__Z18TiledMatrixMulGPU2PfS_S_iPfS_S_i
	.type	_Z43__device_stub__Z18TiledMatrixMulGPU2PfS_S_iPfS_S_i, @function
_Z43__device_stub__Z18TiledMatrixMulGPU2PfS_S_iPfS_S_i:
.LFB4861:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 4(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L40
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z18TiledMatrixMulGPU2PfS_S_i(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L40:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L42
	call	__stack_chk_fail@PLT
.L42:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4861:
	.size	_Z43__device_stub__Z18TiledMatrixMulGPU2PfS_S_iPfS_S_i, .-_Z43__device_stub__Z18TiledMatrixMulGPU2PfS_S_iPfS_S_i
	.globl	_Z18TiledMatrixMulGPU2PfS_S_i
	.type	_Z18TiledMatrixMulGPU2PfS_S_i, @function
_Z18TiledMatrixMulGPU2PfS_S_i:
.LFB4862:
	.cfi_startproc
	endbr64
	jmp	_Z43__device_stub__Z18TiledMatrixMulGPU2PfS_S_iPfS_S_i
	.cfi_endproc
.LFE4862:
	.size	_Z18TiledMatrixMulGPU2PfS_S_i, .-_Z18TiledMatrixMulGPU2PfS_S_i
	.globl	_Z43__device_stub__Z18TiledMatrixMulGPU4PfS_S_iPfS_S_i
	.type	_Z43__device_stub__Z18TiledMatrixMulGPU4PfS_S_iPfS_S_i, @function
_Z43__device_stub__Z18TiledMatrixMulGPU4PfS_S_iPfS_S_i:
.LFB4863:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 4(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L45
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z18TiledMatrixMulGPU4PfS_S_i(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L45:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L47
	call	__stack_chk_fail@PLT
.L47:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4863:
	.size	_Z43__device_stub__Z18TiledMatrixMulGPU4PfS_S_iPfS_S_i, .-_Z43__device_stub__Z18TiledMatrixMulGPU4PfS_S_iPfS_S_i
	.globl	_Z18TiledMatrixMulGPU4PfS_S_i
	.type	_Z18TiledMatrixMulGPU4PfS_S_i, @function
_Z18TiledMatrixMulGPU4PfS_S_i:
.LFB4864:
	.cfi_startproc
	endbr64
	jmp	_Z43__device_stub__Z18TiledMatrixMulGPU4PfS_S_iPfS_S_i
	.cfi_endproc
.LFE4864:
	.size	_Z18TiledMatrixMulGPU4PfS_S_i, .-_Z18TiledMatrixMulGPU4PfS_S_i
	.globl	_Z44__device_stub__Z19TiledMatrixMulGPU10PfS_S_iPfS_S_i
	.type	_Z44__device_stub__Z19TiledMatrixMulGPU10PfS_S_iPfS_S_i, @function
_Z44__device_stub__Z19TiledMatrixMulGPU10PfS_S_iPfS_S_i:
.LFB4865:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 4(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L50
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z19TiledMatrixMulGPU10PfS_S_i(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L50:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L52
	call	__stack_chk_fail@PLT
.L52:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4865:
	.size	_Z44__device_stub__Z19TiledMatrixMulGPU10PfS_S_iPfS_S_i, .-_Z44__device_stub__Z19TiledMatrixMulGPU10PfS_S_iPfS_S_i
	.globl	_Z19TiledMatrixMulGPU10PfS_S_i
	.type	_Z19TiledMatrixMulGPU10PfS_S_i, @function
_Z19TiledMatrixMulGPU10PfS_S_i:
.LFB4866:
	.cfi_startproc
	endbr64
	jmp	_Z44__device_stub__Z19TiledMatrixMulGPU10PfS_S_iPfS_S_i
	.cfi_endproc
.LFE4866:
	.size	_Z19TiledMatrixMulGPU10PfS_S_i, .-_Z19TiledMatrixMulGPU10PfS_S_i
	.globl	_Z44__device_stub__Z19TiledMatrixMulGPU20PfS_S_iPfS_S_i
	.type	_Z44__device_stub__Z19TiledMatrixMulGPU20PfS_S_iPfS_S_i, @function
_Z44__device_stub__Z19TiledMatrixMulGPU20PfS_S_iPfS_S_i:
.LFB4867:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 4(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L55
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z19TiledMatrixMulGPU20PfS_S_i(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L55:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L57
	call	__stack_chk_fail@PLT
.L57:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4867:
	.size	_Z44__device_stub__Z19TiledMatrixMulGPU20PfS_S_iPfS_S_i, .-_Z44__device_stub__Z19TiledMatrixMulGPU20PfS_S_iPfS_S_i
	.globl	_Z19TiledMatrixMulGPU20PfS_S_i
	.type	_Z19TiledMatrixMulGPU20PfS_S_i, @function
_Z19TiledMatrixMulGPU20PfS_S_i:
.LFB4868:
	.cfi_startproc
	endbr64
	jmp	_Z44__device_stub__Z19TiledMatrixMulGPU20PfS_S_iPfS_S_i
	.cfi_endproc
.LFE4868:
	.size	_Z19TiledMatrixMulGPU20PfS_S_i, .-_Z19TiledMatrixMulGPU20PfS_S_i
	.globl	_Z44__device_stub__Z19TiledMatrixMulGPU25PfS_S_iPfS_S_i
	.type	_Z44__device_stub__Z19TiledMatrixMulGPU25PfS_S_iPfS_S_i, @function
_Z44__device_stub__Z19TiledMatrixMulGPU25PfS_S_iPfS_S_i:
.LFB4869:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 4(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L60
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z19TiledMatrixMulGPU25PfS_S_i(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L60:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L62
	call	__stack_chk_fail@PLT
.L62:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4869:
	.size	_Z44__device_stub__Z19TiledMatrixMulGPU25PfS_S_iPfS_S_i, .-_Z44__device_stub__Z19TiledMatrixMulGPU25PfS_S_iPfS_S_i
	.globl	_Z19TiledMatrixMulGPU25PfS_S_i
	.type	_Z19TiledMatrixMulGPU25PfS_S_i, @function
_Z19TiledMatrixMulGPU25PfS_S_i:
.LFB4870:
	.cfi_startproc
	endbr64
	jmp	_Z44__device_stub__Z19TiledMatrixMulGPU25PfS_S_iPfS_S_i
	.cfi_endproc
.LFE4870:
	.size	_Z19TiledMatrixMulGPU25PfS_S_i, .-_Z19TiledMatrixMulGPU25PfS_S_i
	.section	.rodata.str1.1
.LC10:
	.string	"The GPU took %f to perform the computation with tile size %d.\n"
.LC11:
	.string	"a"
.LC12:
	.string	"machineProblem4.csv"
.LC13:
	.string	"%d,%d,%f\n"
	.text
	.globl	_Z7GPUtestPfS_S_ii
	.type	_Z7GPUtestPfS_S_ii, @function
_Z7GPUtestPfS_S_ii:
.LFB4832:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movl	%r8d, %r15d
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	imull	%r8d, %r15d
	movq	%rdi, %r14
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movq	%rsi, %r13
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movq	%rdx, %r12
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movl	%r8d, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movl	%ecx, %ebx
	subq	$104, %rsp
	.cfi_def_cfa_offset 160
	movq	%fs:40, %rax
	movq	%rax, 88(%rsp)
	xorl	%eax, %eax
	movslq	%r15d, %rax
	leaq	40(%rsp), %rdi
	salq	$2, %rax
	movq	%rax, %rsi
	movq	%rax, (%rsp)
	call	cudaMalloc@PLT
	movq	(%rsp), %rsi
	leaq	48(%rsp), %rdi
	call	cudaMalloc@PLT
	movq	(%rsp), %rsi
	leaq	56(%rsp), %rdi
	call	cudaMalloc@PLT
	movq	(%rsp), %rdi
	call	malloc@PLT
	movq	(%rsp), %rcx
	xorl	%esi, %esi
	movq	%rax, %rdi
	movq	%rax, 8(%rsp)
	movq	%rcx, %rdx
	call	__memset_chk@PLT
	leaq	24(%rsp), %rdi
	call	cudaEventCreate@PLT
	leaq	32(%rsp), %rdi
	call	cudaEventCreate@PLT
	movq	(%rsp), %rdx
	movq	40(%rsp), %rdi
	movq	%r14, %rsi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	movq	(%rsp), %rdx
	movq	48(%rsp), %rdi
	movq	%r13, %rsi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	xorl	%edx, %edx
	leal	-1(%rbx,%rbp), %eax
	movq	24(%rsp), %rdi
	divl	%ebx
	movl	$1, 72(%rsp)
	movl	$1, 84(%rsp)
	xorl	%esi, %esi
	movl	%eax, 76(%rsp)
	movl	%eax, 80(%rsp)
	call	cudaEventRecord@PLT
	cmpl	$10, %ebx
	je	.L66
	jg	.L67
	cmpl	$2, %ebx
	je	.L68
	cmpl	$4, %ebx
	je	.L69
	jmp	.L70
.L67:
	cmpl	$20, %ebx
	je	.L71
	cmpl	$25, %ebx
	je	.L72
	jmp	.L70
.L68:
	movl	72(%rsp), %ecx
	movq	76(%rsp), %rdi
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movabsq	$8589934594, %rdx
	movl	84(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L70
	movq	56(%rsp), %rdx
	movq	48(%rsp), %rsi
	movl	%ebp, %ecx
	movq	40(%rsp), %rdi
	call	_Z43__device_stub__Z18TiledMatrixMulGPU2PfS_S_iPfS_S_i
	jmp	.L70
.L69:
	movl	72(%rsp), %ecx
	movq	76(%rsp), %rdi
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movabsq	$17179869188, %rdx
	movl	84(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L70
	movq	56(%rsp), %rdx
	movq	48(%rsp), %rsi
	movl	%ebp, %ecx
	movq	40(%rsp), %rdi
	call	_Z43__device_stub__Z18TiledMatrixMulGPU4PfS_S_iPfS_S_i
	jmp	.L70
.L66:
	movl	72(%rsp), %ecx
	movq	76(%rsp), %rdi
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movabsq	$42949672970, %rdx
	movl	84(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L70
	movq	56(%rsp), %rdx
	movq	48(%rsp), %rsi
	movl	%ebp, %ecx
	movq	40(%rsp), %rdi
	call	_Z44__device_stub__Z19TiledMatrixMulGPU10PfS_S_iPfS_S_i
	jmp	.L70
.L71:
	movl	72(%rsp), %ecx
	movq	76(%rsp), %rdi
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movabsq	$85899345940, %rdx
	movl	84(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L70
	movq	56(%rsp), %rdx
	movq	48(%rsp), %rsi
	movl	%ebp, %ecx
	movq	40(%rsp), %rdi
	call	_Z44__device_stub__Z19TiledMatrixMulGPU20PfS_S_iPfS_S_i
	jmp	.L70
.L72:
	movl	72(%rsp), %ecx
	movq	76(%rsp), %rdi
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movabsq	$107374182425, %rdx
	movl	84(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L70
	movq	56(%rsp), %rdx
	movq	48(%rsp), %rsi
	movl	%ebp, %ecx
	movq	40(%rsp), %rdi
	call	_Z44__device_stub__Z19TiledMatrixMulGPU25PfS_S_iPfS_S_i
.L70:
	movq	32(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movq	32(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movq	32(%rsp), %rdx
	movq	24(%rsp), %rsi
	leaq	20(%rsp), %rdi
	call	cudaEventElapsedTime@PLT
	movq	(%rsp), %rdx
	movq	56(%rsp), %rsi
	movl	$2, %ecx
	movq	8(%rsp), %rdi
	call	cudaMemcpy@PLT
	movl	%ebx, %edx
	leaq	.LC10(%rip), %rsi
	movb	$1, %al
	movl	$2, %edi
	cvtss2sd	20(%rsp), %xmm0
	call	__printf_chk@PLT
	movq	8(%rsp), %rsi
	movl	%r15d, %edx
	movq	%r12, %rdi
	call	_Z11checkResultPfS_i
	movq	40(%rsp), %rdi
	call	cudaFree@PLT
	movq	48(%rsp), %rdi
	call	cudaFree@PLT
	movq	56(%rsp), %rdi
	call	cudaFree@PLT
	movq	8(%rsp), %rdi
	call	free@PLT
	leaq	.LC11(%rip), %rsi
	leaq	.LC12(%rip), %rdi
	call	fopen@PLT
	movl	%ebx, %r8d
	movl	%ebp, %ecx
	movl	$2, %esi
	movq	%rax, %rdi
	movq	%rax, %r12
	movb	$1, %al
	cvtss2sd	20(%rsp), %xmm0
	leaq	.LC13(%rip), %rdx
	call	__fprintf_chk@PLT
	movq	%r12, %rdi
	call	fclose@PLT
	movq	88(%rsp), %rax
	subq	%fs:40, %rax
	je	.L75
	call	__stack_chk_fail@PLT
.L75:
	addq	$104, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4832:
	.size	_Z7GPUtestPfS_S_ii, .-_Z7GPUtestPfS_S_ii
	.section	.rodata.str1.1
.LC14:
	.string	"------------------------------------------------------------------------\n\n"
.LC15:
	.string	"%dx%d matrix multiplication.\n\n"
	.text
	.globl	_Z13computeMatrixi
	.type	_Z13computeMatrixi, @function
_Z13computeMatrixi:
.LFB4833:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	leaq	.LC14(%rip), %rsi
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movl	%edi, %ebx
	movl	$2, %edi
	movl	%ebx, %r15d
	imull	%ebx, %r15d
	subq	$40, %rsp
	.cfi_def_cfa_offset 96
	movq	%fs:40, %rax
	movq	%rax, 24(%rsp)
	xorl	%eax, %eax
	movslq	%r15d, %rbp
	salq	$2, %rbp
	call	__printf_chk@PLT
	movl	%ebx, %ecx
	movl	%ebx, %edx
	leaq	.LC15(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movq	%rbp, %rdi
	call	malloc@PLT
	movq	%rbp, %rdi
	movq	%rax, %r14
	call	malloc@PLT
	movq	%rbp, %rdi
	movq	%rax, %r13
	call	malloc@PLT
	movl	%r15d, %esi
	movq	%r14, %rdi
	movq	%rax, %r12
	call	_Z11initialDataPfi
	movl	%r15d, %esi
	movq	%r13, %rdi
	call	_Z11initialDataPfi
	movq	%rbp, %rcx
	movq	%rbp, %rdx
	xorl	%esi, %esi
	movq	%r12, %rdi
	xorl	%ebp, %ebp
	call	__memset_chk@PLT
	movl	%ebx, %ecx
	movq	%r12, %rdx
	movq	%r13, %rsi
	movq	%r14, %rdi
	call	_Z12MatrixMulCPUPfS_S_i
	movl	$25, 20(%rsp)
	movabsq	$17179869186, %rax
	movq	%rax, 4(%rsp)
	movabsq	$85899345930, %rax
	movq	%rax, 12(%rsp)
.L78:
	movl	4(%rsp,%rbp,4), %ecx
	movl	%ebx, %r8d
	movq	%r12, %rdx
	movq	%r13, %rsi
	movq	%r14, %rdi
	incq	%rbp
	call	_Z7GPUtestPfS_S_ii
	cmpq	$5, %rbp
	jne	.L78
	movq	%r14, %rdi
	call	free@PLT
	movq	%r13, %rdi
	call	free@PLT
	movq	%r12, %rdi
	call	free@PLT
	movq	24(%rsp), %rax
	subq	%fs:40, %rax
	je	.L79
	call	__stack_chk_fail@PLT
.L79:
	addq	$40, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	cudaDeviceReset@PLT
	.cfi_endproc
.LFE4833:
	.size	_Z13computeMatrixi, .-_Z13computeMatrixi
	.globl	_Z50__device_stub__Z23TiledMatrixMulGPUBonus1PfS_S_iiiPfS_S_iii
	.type	_Z50__device_stub__Z23TiledMatrixMulGPUBonus1PfS_S_iiiPfS_S_iii, @function
_Z50__device_stub__Z23TiledMatrixMulGPUBonus1PfS_S_iiiPfS_S_iii:
.LFB4871:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	56(%rsp), %rdx
	movl	%ecx, 20(%rsp)
	leaq	64(%rsp), %rcx
	movl	%r8d, 16(%rsp)
	movl	%r9d, 12(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L83
	pushq	64(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z23TiledMatrixMulGPUBonus1PfS_S_iii(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 208
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L83:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L85
	call	__stack_chk_fail@PLT
.L85:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4871:
	.size	_Z50__device_stub__Z23TiledMatrixMulGPUBonus1PfS_S_iiiPfS_S_iii, .-_Z50__device_stub__Z23TiledMatrixMulGPUBonus1PfS_S_iiiPfS_S_iii
	.globl	_Z23TiledMatrixMulGPUBonus1PfS_S_iii
	.type	_Z23TiledMatrixMulGPUBonus1PfS_S_iii, @function
_Z23TiledMatrixMulGPUBonus1PfS_S_iii:
.LFB4872:
	.cfi_startproc
	endbr64
	jmp	_Z50__device_stub__Z23TiledMatrixMulGPUBonus1PfS_S_iiiPfS_S_iii
	.cfi_endproc
.LFE4872:
	.size	_Z23TiledMatrixMulGPUBonus1PfS_S_iii, .-_Z23TiledMatrixMulGPUBonus1PfS_S_iii
	.globl	_Z49__device_stub__Z22TiledMatrixMulGPUBonusPfS_S_iiiPfS_S_iii
	.type	_Z49__device_stub__Z22TiledMatrixMulGPUBonusPfS_S_iiiPfS_S_iii, @function
_Z49__device_stub__Z22TiledMatrixMulGPUBonusPfS_S_iiiPfS_S_iii:
.LFB4873:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	56(%rsp), %rdx
	movl	%ecx, 20(%rsp)
	leaq	64(%rsp), %rcx
	movl	%r8d, 16(%rsp)
	movl	%r9d, 12(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L88
	pushq	64(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z22TiledMatrixMulGPUBonusPfS_S_iii(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 208
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L88:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L90
	call	__stack_chk_fail@PLT
.L90:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4873:
	.size	_Z49__device_stub__Z22TiledMatrixMulGPUBonusPfS_S_iiiPfS_S_iii, .-_Z49__device_stub__Z22TiledMatrixMulGPUBonusPfS_S_iiiPfS_S_iii
	.globl	_Z22TiledMatrixMulGPUBonusPfS_S_iii
	.type	_Z22TiledMatrixMulGPUBonusPfS_S_iii, @function
_Z22TiledMatrixMulGPUBonusPfS_S_iii:
.LFB4874:
	.cfi_startproc
	endbr64
	jmp	_Z49__device_stub__Z22TiledMatrixMulGPUBonusPfS_S_iiiPfS_S_iii
	.cfi_endproc
.LFE4874:
	.size	_Z22TiledMatrixMulGPUBonusPfS_S_iii, .-_Z22TiledMatrixMulGPUBonusPfS_S_iii
	.section	.rodata.str1.1
.LC16:
	.string	"%dx%d and %dx%d matrix multiplication with %dx%d tile size.\n\n"
	.text
	.globl	_Z18computeMatrixBonusiii
	.type	_Z18computeMatrixBonusiii, @function
_Z18computeMatrixBonusiii:
.LFB4835:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movl	%edx, %r12d
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movl	%edi, %ebp
	movl	$2, %edi
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movl	%esi, %ebx
	leaq	.LC14(%rip), %rsi
	movl	%ebx, %r15d
	imull	%r12d, %r15d
	subq	$120, %rsp
	.cfi_def_cfa_offset 176
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	call	__printf_chk@PLT
	pushq	$8
	.cfi_def_cfa_offset 184
	movl	%r12d, %r9d
	movl	%ebx, %r8d
	pushq	$14
	.cfi_def_cfa_offset 192
	movl	%ebx, %ecx
	movl	%ebp, %edx
	leaq	.LC16(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movl	%ebp, %esi
	imull	%ebx, %esi
	movslq	%esi, %rax
	movl	%esi, 60(%rsp)
	salq	$2, %rax
	movq	%rax, 40(%rsp)
	movslq	%r15d, %rax
	movq	40(%rsp), %rdi
	salq	$2, %rax
	movq	%rax, 48(%rsp)
	movl	%ebp, %eax
	imull	%r12d, %eax
	cltq
	salq	$2, %rax
	movq	%rax, 16(%rsp)
	call	malloc@PLT
	movq	48(%rsp), %rdi
	movq	%rax, %r14
	call	malloc@PLT
	movq	16(%rsp), %rdi
	movq	%rax, %r13
	call	malloc@PLT
	movq	16(%rsp), %rdi
	movq	%rax, 24(%rsp)
	call	malloc@PLT
	movl	60(%rsp), %esi
	movq	%r14, %rdi
	movq	%rax, 32(%rsp)
	call	_Z11initialDataPfi
	movl	%r15d, %esi
	movq	%r13, %rdi
	call	_Z11initialDataPfi
	movq	16(%rsp), %rcx
	movq	24(%rsp), %rdi
	xorl	%esi, %esi
	movq	%rcx, %rdx
	call	__memset_chk@PLT
	movq	16(%rsp), %rcx
	movq	32(%rsp), %rdi
	xorl	%esi, %esi
	movq	%rcx, %rdx
	call	__memset_chk@PLT
	movq	24(%rsp), %rdx
	movl	%r12d, %r9d
	movl	%ebx, %r8d
	movl	%ebp, %ecx
	movq	%r13, %rsi
	movq	%r14, %rdi
	call	_Z17MatrixMulCPUBonusPfS_S_iii
	popq	%rax
	.cfi_def_cfa_offset 184
	popq	%rdx
	.cfi_def_cfa_offset 176
	movq	24(%rsp), %rsi
	leaq	56(%rsp), %rdi
	call	cudaMalloc@PLT
	movq	32(%rsp), %rsi
	leaq	64(%rsp), %rdi
	call	cudaMalloc@PLT
	movq	(%rsp), %rsi
	leaq	72(%rsp), %rdi
	call	cudaMalloc@PLT
	movq	24(%rsp), %rdx
	movq	56(%rsp), %rdi
	movq	%r14, %rsi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	movq	32(%rsp), %rdx
	movq	64(%rsp), %rdi
	movq	%r13, %rsi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	leal	7(%r12), %eax
	xorl	%edx, %edx
	xorl	%r9d, %r9d
	shrl	$3, %eax
	movl	$14, %ecx
	xorl	%r8d, %r8d
	movl	$1, %esi
	movl	%eax, 92(%rsp)
	leal	13(%rbp), %eax
	divl	%ecx
	movabsq	$60129542152, %rdx
	movl	$1, %ecx
	movl	%eax, 96(%rsp)
	movq	92(%rsp), %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L94
	movq	72(%rsp), %rdx
	movq	64(%rsp), %rsi
	movl	%r12d, %r9d
	movl	%ebx, %r8d
	movq	56(%rsp), %rdi
	movl	%ebp, %ecx
	call	_Z49__device_stub__Z22TiledMatrixMulGPUBonusPfS_S_iiiPfS_S_iii
.L94:
	imull	%ebx, %ebx
	movq	(%rsp), %rdx
	movq	72(%rsp), %rsi
	movl	$2, %ecx
	movq	16(%rsp), %rdi
	call	cudaMemcpy@PLT
	movq	16(%rsp), %rsi
	movq	8(%rsp), %rdi
	movl	%ebx, %edx
	call	_Z11checkResultPfS_i
	movq	%r14, %rdi
	call	free@PLT
	movq	%r13, %rdi
	call	free@PLT
	movq	8(%rsp), %rdi
	call	free@PLT
	movq	16(%rsp), %rdi
	call	free@PLT
	movq	56(%rsp), %rdi
	call	cudaFree@PLT
	movq	64(%rsp), %rdi
	call	cudaFree@PLT
	movq	72(%rsp), %rdi
	call	cudaFree@PLT
	call	cudaDeviceReset@PLT
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L95
	call	__stack_chk_fail@PLT
.L95:
	addq	$120, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4835:
	.size	_Z18computeMatrixBonusiii, .-_Z18computeMatrixBonusiii
	.section	.rodata.str1.1
.LC17:
	.string	"w"
.LC18:
	.string	"matrixSize,tileSize,time\n"
.LC19:
	.string	"------------------------------------------------------------------------\n"
.LC20:
	.string	"BONUS\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB4836:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	.LC17(%rip), %rsi
	leaq	.LC12(%rip), %rdi
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	movq	%fs:40, %rax
	movq	%rax, 24(%rsp)
	xorl	%eax, %eax
	call	fopen@PLT
	leaq	.LC18(%rip), %rdx
	movl	$2, %esi
	movq	%rax, %rbx
	movq	%rax, %rdi
	xorl	%eax, %eax
	call	__fprintf_chk@PLT
	movq	%rbx, %rdi
	xorl	%ebx, %ebx
	call	fclose@PLT
	movabsq	$858993459300, %rax
	movq	%rax, (%rsp)
	movabsq	$4294967296500, %rax
	movq	%rax, 8(%rsp)
	movabsq	$21474836481500, %rax
	movq	%rax, 16(%rsp)
.L98:
	movl	(%rsp,%rbx,4), %edi
	incq	%rbx
	call	_Z13computeMatrixi
	cmpq	$6, %rbx
	jne	.L98
	leaq	.LC19(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	leaq	.LC20(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movl	$4, %edx
	movl	$3, %esi
	movl	$2, %edi
	call	_Z18computeMatrixBonusiii
	movl	$300, %esi
	movl	$250, %edi
	movl	$450, %edx
	call	_Z18computeMatrixBonusiii
	xorl	%eax, %eax
	movl	$2, %edi
	leaq	.LC14(%rip), %rsi
	call	__printf_chk@PLT
	movq	24(%rsp), %rax
	subq	%fs:40, %rax
	je	.L99
	call	__stack_chk_fail@PLT
.L99:
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4836:
	.size	main, .-main
	.section	.rodata.str1.1
.LC21:
	.string	"_Z22TiledMatrixMulGPUBonusPfS_S_iii"
.LC22:
	.string	"_Z23TiledMatrixMulGPUBonus1PfS_S_iii"
.LC23:
	.string	"_Z19TiledMatrixMulGPU25PfS_S_i"
.LC24:
	.string	"_Z19TiledMatrixMulGPU20PfS_S_i"
.LC25:
	.string	"_Z19TiledMatrixMulGPU10PfS_S_i"
.LC26:
	.string	"_Z18TiledMatrixMulGPU4PfS_S_i"
.LC27:
	.string	"_Z18TiledMatrixMulGPU2PfS_S_i"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4876:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC21(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z22TiledMatrixMulGPUBonusPfS_S_iii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC22(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z23TiledMatrixMulGPUBonus1PfS_S_iii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC23(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z19TiledMatrixMulGPU25PfS_S_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC24(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z19TiledMatrixMulGPU20PfS_S_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC25(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z19TiledMatrixMulGPU10PfS_S_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC26(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z18TiledMatrixMulGPU4PfS_S_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC27(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z18TiledMatrixMulGPU2PfS_S_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE4876:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst4,"aM",@progbits,4
	.align 4
.LC0:
	.long	1092616192
	.section	.rodata.cst16,"aM",@progbits,16
	.align 16
.LC1:
	.long	2147483647
	.long	0
	.long	0
	.long	0
	.section	.rodata.cst8,"aM",@progbits,8
	.align 8
.LC2:
	.long	-500134854
	.long	1044740494
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

/*
	Name: Daniyal Manair
	Student Number: 20064993
*/
#include "hip/hip_runtime.h"


#include <vector>
#include <stdio.h>
#include <random>
#include <algorithm>
#include <chrono>
#include <map>

__global__ void TiledMatrixMulGPU2(float* A, float* B, float* C, const int N) {
	__shared__ float t_A [2][2];
	__shared__ float t_B [2][2];

	unsigned int tileWidth = 2;
	unsigned int bx = blockIdx.x;
	unsigned int by = blockIdx.y;
	unsigned int tx = threadIdx.x;
	unsigned int ty = threadIdx.y;
	unsigned int row = by * tileWidth + ty;
	unsigned int col = bx * tileWidth + tx;

	float cValue = 0.0;
	for (int i = 0; i < (N / tileWidth); i++) {
		t_A[ty][tx] = A[row*N + i*tileWidth + tx];
		t_B[ty][tx] = B[(i*tileWidth + ty)*N + col];
		__syncthreads();
		for (int j = 0; j < tileWidth; j++)
			cValue += t_A[ty][j] * t_B[j][tx];
		__syncthreads();
	}
	C[row*N + col] = cValue;
}

__global__ void TiledMatrixMulGPU4(float* A, float* B, float* C, const int N) {
	__shared__ float t_A [4][4];
	__shared__ float t_B [4][4];

	unsigned int tileWidth = 4;
	unsigned int bx = blockIdx.x;
	unsigned int by = blockIdx.y;
	unsigned int tx = threadIdx.x;
	unsigned int ty = threadIdx.y;
	unsigned int row = by * tileWidth + ty;
	unsigned int col = bx * tileWidth + tx;

	float cValue = 0.0;
	for (int i = 0; i < (N / tileWidth); i++) {
		t_A[ty][tx] = A[row*N + i*tileWidth + tx];
		t_B[ty][tx] = B[(i*tileWidth + ty)*N + col];
		__syncthreads();
		for (int j = 0; j < tileWidth; j++)
			cValue += t_A[ty][j] * t_B[j][tx];
		__syncthreads();
	}
	C[row*N + col] = cValue;
}	


__global__ void TiledMatrixMulGPU10(float* A, float* B, float* C, const int N) {
	__shared__ float t_A [10][10];
	__shared__ float t_B [10][10];

	unsigned int tileWidth = 10;
	unsigned int bx = blockIdx.x;
	unsigned int by = blockIdx.y;
	unsigned int tx = threadIdx.x;
	unsigned int ty = threadIdx.y;
	unsigned int row = by * tileWidth + ty;
	unsigned int col = bx * tileWidth + tx;

	float cValue = 0.0;
	for (int i = 0; i < (N / tileWidth); i++) {
		t_A[ty][tx] = A[row*N + i*tileWidth + tx];
		t_B[ty][tx] = B[(i*tileWidth + ty)*N + col];
		__syncthreads();
		for (int j = 0; j < tileWidth; j++)
			cValue += t_A[ty][j] * t_B[j][tx];
		__syncthreads();
	}
	C[row*N + col] = cValue;
}

__global__ void TiledMatrixMulGPU20(float* A, float* B, float* C, const int N) {
	__shared__ float t_A [20][20];
	__shared__ float t_B [20][20];

	unsigned int tileWidth = 20;
	unsigned int bx = blockIdx.x;
	unsigned int by = blockIdx.y;
	unsigned int tx = threadIdx.x;
	unsigned int ty = threadIdx.y;
	unsigned int row = by * tileWidth + ty;
	unsigned int col = bx * tileWidth + tx;

	float cValue = 0.0;
	for (int i = 0; i < (N / tileWidth); i++) {
		t_A[ty][tx] = A[row*N + i*tileWidth + tx];
		t_B[ty][tx] = B[(i*tileWidth + ty)*N + col];
		__syncthreads();
		for (int j = 0; j < tileWidth; j++)
			cValue += t_A[ty][j] * t_B[j][tx];
		__syncthreads();
	}
	C[row*N + col] = cValue;
}

__global__ void TiledMatrixMulGPU25(float* A, float* B, float* C, int N) {
	__shared__ float t_A[25][25];
	__shared__ float t_B[25][25];

	unsigned int tileWidth = 25;
	unsigned int bx = blockIdx.x;
	unsigned int by = blockIdx.y;
	unsigned int tx = threadIdx.x;
	unsigned int ty = threadIdx.y;
	unsigned int row = by * tileWidth + ty;
	unsigned int col = bx * tileWidth + tx;

	float cValue = 0.0;
	for (int i = 0; i < (N / tileWidth); i++) {
		t_A[ty][tx] = A[row*N + i*tileWidth + tx];
		t_B[ty][tx] = B[(i*tileWidth + ty)*N + col];
		__syncthreads();
		for (int j = 0; j < tileWidth; j++)
			cValue += t_A[ty][j] * t_B[j][tx];
		__syncthreads();
	}
	C[row*N + col] = cValue;
}

void initialData(float* matrix, const int size){
	for (int i = 0; i < size; i++)
		matrix[i] = (float)(rand() & 0xFF) / 10.0f;
}

void MatrixMulCPU(float* A, float* B, float* C, const int N){
	for (int i = 0; i < N; i++) {
		for (int j = 0; j < N; j++) {
			for (int k = 0; k < N; k++) 
				C[i * N + j] += A[i * N + k] * B[k * N + j];
		}
	}
}

void checkResult(float* CPU, float* GPU, const int size) {
	double epsilon = 1.0E-8;
	
	for (int i = 0; i < size; i++){
		if (abs(CPU[i] - GPU[i]) > epsilon){
			printf("CPU %f GPU %f ", CPU[i], GPU[i]);
			printf("Arrays do not match.\n\n");
			return;
		}
	}
	printf("Test PASSED\n\n");
}

void printArr(float* matrix, const int size) {
	printf("[");
	for (int i = 0; i < size; i++)
		printf("%f,", matrix[i]);
	printf("\b]\n");

}

void GPUtest(float* C_A, float* C_B, float* CPUResult, const int tileSize, const int N){
	// Initialize variables
	hipEvent_t gStart, gEnd;
	float timeDuration;
	float *G_A, *G_B, *G_C, *GPUResult;
	size_t size = N * N * sizeof(float);
	
	// Initialize GPU variables
	hipMalloc((void**)&G_A, size);
	hipMalloc((void**)&G_B, size);
	hipMalloc((void**)&G_C, size);
	GPUResult = (float*)malloc(size);
	memset(GPUResult, 0.0, size);
	hipEventCreate(&gStart);
    hipEventCreate(&gEnd);
	
	// Copy over the data
	hipMemcpy(G_A, C_A, size, hipMemcpyHostToDevice);
	hipMemcpy(G_B, C_B, size, hipMemcpyHostToDevice);
	
	// Perform GPU comparison

	// Create block
	dim3 block(tileSize, tileSize, 1);
	dim3 grid((int)ceil((N + block.x - 1) / block.x),(int)ceil((N + block.y - 1) / block.y), 1);

	hipEventRecord(gStart);
	if (tileSize == 2)
		TiledMatrixMulGPU2 <<<grid, block>>> (G_A, G_B, G_C, N);
	else if (tileSize == 4)
		TiledMatrixMulGPU4 <<<grid, block>>> (G_A, G_B, G_C, N);
	else if (tileSize == 10)
		TiledMatrixMulGPU10 <<<grid, block>>> (G_A, G_B, G_C, N);
	else if (tileSize == 20)
		TiledMatrixMulGPU20 <<<grid, block>>> (G_A, G_B, G_C, N);
	else if (tileSize == 25) 	
		TiledMatrixMulGPU25 <<<grid, block >>> (G_A, G_B, G_C, N);
	hipEventRecord(gEnd);
	
	hipEventSynchronize(gEnd);
	hipEventElapsedTime(&timeDuration, gStart, gEnd);
	hipMemcpy(GPUResult, G_C, size, hipMemcpyDeviceToHost);
	printf("The GPU took %f to perform the computation with tile size %d.\n", timeDuration, tileSize);
	checkResult(CPUResult, GPUResult, N*N);
	
	hipFree(G_A);
	hipFree(G_B);
	hipFree(G_C);
	free(GPUResult);

	FILE *fp;
	fp=fopen("machineProblem4.csv","a");
	fprintf(fp,"%d,%d,%f\n",N,tileSize,timeDuration);
	fclose(fp);
}

void computeMatrix(const int N) {
	// Initial prints
	printf("------------------------------------------------------------------------\n\n");
	printf("%dx%d matrix multiplication.\n\n", N, N);

	// Initialize Host variables
	float *C_A, *C_B, *C_C;
	size_t size = N * N * sizeof(float);
	
	// Initialize space
	C_A = (float*)malloc(size);
	C_B = (float*)malloc(size);
	C_C = (float*)malloc(size);
	
	// Set with random data
	initialData(C_A, N*N);
	initialData(C_B, N*N);
	memset(C_C, 0.0, size);

	// Serial Test CPU
	MatrixMulCPU(C_A, C_B, C_C, N);
	
	// Test Complete parallel Computation
	int tileSizes [] = {2, 4, 10, 20, 25};
	
	for (int i = 0; i < 5; i++)
		GPUtest(C_A, C_B, C_C, tileSizes[i], N);
	
	// Free all the memory
	free(C_A);
	free(C_B);
	free(C_C);
	hipDeviceReset();
}

// --------------------BONUS-----------------------------

#define BONUSTILE_C 8
#define BONUSTILE_R 14

__global__ void TiledMatrixMulGPUBonus1(float* A, float* B, float* C, int M, int N, int K) {
	int Brows = N;
	int Crows = M;
	int Ccols = K;
	float cValue = 0;
	unsigned int bx = blockIdx.x;
	unsigned int by = blockIdx.y;
	unsigned int tx = threadIdx.x;
	unsigned int ty = threadIdx.y;
	int row = by*BONUSTILE_R + ty;
	int col = bx*BONUSTILE_C + tx;

	__shared__ float t_A[BONUSTILE_R][BONUSTILE_C];
	__shared__ float t_B[BONUSTILE_R][BONUSTILE_C];

	for (int i = 0; i < (BONUSTILE_C + N - 1) / 2; i++) {

		if (i*BONUSTILE_C + tx < N && row < M)
			t_A[ty][tx] = A[row*N + i*BONUSTILE_C + tx];
		else
			t_A[ty][tx] = 0.0;

		if (i*BONUSTILE_C + ty < Brows && col < K)
			t_B[ty][tx] = B[(i*BONUSTILE_C + ty)*K + col];
		else
			t_B[ty][tx] = 0.0;

		__syncthreads();

		for (int j = 0; j < BONUSTILE_C; j++)
			cValue += t_A[ty][j] * t_B[j][tx];

		__syncthreads();
	}

	if (row < Crows && col < Ccols)
		C[((by * blockDim.y + ty)*Ccols) + (bx * blockDim.x) + tx] = cValue;
}

__global__ void TiledMatrixMulGPUBonus(float* A, float* B, float* C, int M, int N, int K) {
	float cValue = 0;
	unsigned int bx = blockIdx.x;
	unsigned int by = blockIdx.y;
	unsigned int tx = threadIdx.x;
	unsigned int ty = threadIdx.y;
	int row = by*BONUSTILE_R + ty;
	int col = bx*BONUSTILE_C + tx;

	__shared__ float t_A[BONUSTILE_R][BONUSTILE_C];
	__shared__ float t_B[BONUSTILE_R][BONUSTILE_C];

	for (int i = 0; i < (BONUSTILE_C + N - 1) / 2; i++) {

		if (i*BONUSTILE_C + tx < N && row < M)
			t_A[ty][tx] = A[row*N + i*BONUSTILE_C + tx];
		else
			t_A[ty][tx] = 0.0;

		if (i*BONUSTILE_C + ty < N && col < K)
			t_B[ty][tx] = B[(i*BONUSTILE_C + ty)*K + col];
		else
			t_B[ty][tx] = 0.0;

		__syncthreads();

		for (int j = 0; j < BONUSTILE_C; j++)
			cValue += t_A[ty][j] * t_B[j][tx];

		__syncthreads();
	}

	if (row < M && col < K)
		C[((by * blockDim.y + ty)*K) + (bx * blockDim.x) + tx] = cValue;
}

void MatrixMulCPUBonus(float* A, float* B, float* C, const int M, const int N, const int K) {
	float cValue = 0.0;
	for (int i = 0; i < M; i++) {
		for (int j = 0; j < K; j++) {
			cValue = 0.0;
			for (int k = 0; k < N; k++) 
				cValue += A[i * N + k] * B[k * K + j];
			C[i * K + j] = cValue;
		}
	}
}

void computeMatrixBonus(const int M, const int N, const int K) {
	// Initial prints
	printf("------------------------------------------------------------------------\n\n");
	printf("%dx%d and %dx%d matrix multiplication with %dx%d tile size.\n\n", M, N, N, K, BONUSTILE_R, BONUSTILE_C);

	float *C_A, *C_B, *C_C, *GPUResult;
	size_t sizeA = M * N * sizeof(float);
	size_t sizeB = N * K * sizeof(float);
	size_t sizeC = M * K * sizeof(float);
	
	// Initialize space
	C_A = (float*)malloc(sizeA);
	C_B = (float*)malloc(sizeB);
	C_C = (float*)malloc(sizeC);
	GPUResult = (float*)malloc(sizeC);
	
	// Set with random data
	initialData(C_A, M * N);
	initialData(C_B, N * K);
	memset(C_C, 0.0, sizeC);
	memset(GPUResult, 0.0, sizeC);

	// Serial Test CPU
	MatrixMulCPUBonus(C_A, C_B, C_C, M, N, K);
	
	// GPU calculations
	float *G_A, *G_B, *G_C;
	
	// Initialize GPU variables
	hipMalloc((void**)&G_A, sizeA);
	hipMalloc((void**)&G_B, sizeB);
	hipMalloc((void**)&G_C, sizeC);
	// Copy over values
	hipMemcpy(G_A, C_A, sizeA, hipMemcpyHostToDevice);
	hipMemcpy(G_B, C_B, sizeB, hipMemcpyHostToDevice);
	
	// Case 1 8x14
	dim3 block(BONUSTILE_C, BONUSTILE_R, 1);
	dim3 grid((K + block.x - 1) / block.x, (M + block.y - 1) / block.y, 1);
	
	TiledMatrixMulGPUBonus <<<grid, block>>> (G_A, G_B, G_C, M, N, K);
	hipMemcpy(GPUResult, G_C, sizeC, hipMemcpyDeviceToHost);
	checkResult(C_C, GPUResult, N*N);

	// Free all the memory
	free(C_A);
	free(C_B);
	free(C_C);
	free(GPUResult);
	hipFree(G_A);
	hipFree(G_B);
	hipFree(G_C);
	hipDeviceReset();
}

// ------------------------------------------------------


int main(){
	FILE *fp;
	fp=fopen("machineProblem4.csv","w");
	fprintf(fp,"matrixSize,tileSize,time\n");
	fclose(fp);
	int matrixWidths [] = {100, 200, 500, 1000, 1500, 5000};
	
	for (int i = 0; i < 6; i++)
		computeMatrix(matrixWidths[i]);

	printf("------------------------------------------------------------------------\n");
    
	printf("BONUS\n");
	
	computeMatrixBonus(2, 3, 4);
	computeMatrixBonus(250, 300, 450);
	printf("------------------------------------------------------------------------\n\n");
	return 0;
}

	.text
	.file	"kernel.hip"
	.globl	_Z33__device_stub__TiledMatrixMulGPU2PfS_S_i # -- Begin function _Z33__device_stub__TiledMatrixMulGPU2PfS_S_i
	.type	_Z33__device_stub__TiledMatrixMulGPU2PfS_S_i,@function
_Z33__device_stub__TiledMatrixMulGPU2PfS_S_i: # @_Z33__device_stub__TiledMatrixMulGPU2PfS_S_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	4(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z18TiledMatrixMulGPU2PfS_S_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z33__device_stub__TiledMatrixMulGPU2PfS_S_i, .Lfunc_end0-_Z33__device_stub__TiledMatrixMulGPU2PfS_S_i
	.cfi_endproc
                                        # -- End function
	.globl	_Z33__device_stub__TiledMatrixMulGPU4PfS_S_i # -- Begin function _Z33__device_stub__TiledMatrixMulGPU4PfS_S_i
	.type	_Z33__device_stub__TiledMatrixMulGPU4PfS_S_i,@function
_Z33__device_stub__TiledMatrixMulGPU4PfS_S_i: # @_Z33__device_stub__TiledMatrixMulGPU4PfS_S_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	4(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z18TiledMatrixMulGPU4PfS_S_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z33__device_stub__TiledMatrixMulGPU4PfS_S_i, .Lfunc_end1-_Z33__device_stub__TiledMatrixMulGPU4PfS_S_i
	.cfi_endproc
                                        # -- End function
	.globl	_Z34__device_stub__TiledMatrixMulGPU10PfS_S_i # -- Begin function _Z34__device_stub__TiledMatrixMulGPU10PfS_S_i
	.type	_Z34__device_stub__TiledMatrixMulGPU10PfS_S_i,@function
_Z34__device_stub__TiledMatrixMulGPU10PfS_S_i: # @_Z34__device_stub__TiledMatrixMulGPU10PfS_S_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	4(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z19TiledMatrixMulGPU10PfS_S_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z34__device_stub__TiledMatrixMulGPU10PfS_S_i, .Lfunc_end2-_Z34__device_stub__TiledMatrixMulGPU10PfS_S_i
	.cfi_endproc
                                        # -- End function
	.globl	_Z34__device_stub__TiledMatrixMulGPU20PfS_S_i # -- Begin function _Z34__device_stub__TiledMatrixMulGPU20PfS_S_i
	.type	_Z34__device_stub__TiledMatrixMulGPU20PfS_S_i,@function
_Z34__device_stub__TiledMatrixMulGPU20PfS_S_i: # @_Z34__device_stub__TiledMatrixMulGPU20PfS_S_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	4(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z19TiledMatrixMulGPU20PfS_S_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	_Z34__device_stub__TiledMatrixMulGPU20PfS_S_i, .Lfunc_end3-_Z34__device_stub__TiledMatrixMulGPU20PfS_S_i
	.cfi_endproc
                                        # -- End function
	.globl	_Z34__device_stub__TiledMatrixMulGPU25PfS_S_i # -- Begin function _Z34__device_stub__TiledMatrixMulGPU25PfS_S_i
	.type	_Z34__device_stub__TiledMatrixMulGPU25PfS_S_i,@function
_Z34__device_stub__TiledMatrixMulGPU25PfS_S_i: # @_Z34__device_stub__TiledMatrixMulGPU25PfS_S_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	4(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z19TiledMatrixMulGPU25PfS_S_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end4:
	.size	_Z34__device_stub__TiledMatrixMulGPU25PfS_S_i, .Lfunc_end4-_Z34__device_stub__TiledMatrixMulGPU25PfS_S_i
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0                          # -- Begin function _Z11initialDataPfi
.LCPI5_0:
	.long	0x41200000                      # float 10
	.text
	.globl	_Z11initialDataPfi
	.type	_Z11initialDataPfi,@function
_Z11initialDataPfi:                     # @_Z11initialDataPfi
	.cfi_startproc
# %bb.0:
	testl	%esi, %esi
	jle	.LBB5_4
# %bb.1:                                # %.lr.ph.preheader
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movq	%rdi, %rbx
	movl	%esi, %r14d
	xorl	%r15d, %r15d
.LBB5_2:                                # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	callq	rand
	movzbl	%al, %eax
	xorps	%xmm0, %xmm0
	cvtsi2ss	%eax, %xmm0
	divss	.LCPI5_0(%rip), %xmm0
	movss	%xmm0, (%rbx,%r15,4)
	incq	%r15
	cmpq	%r15, %r14
	jne	.LBB5_2
# %bb.3:
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	.cfi_restore %rbx
	.cfi_restore %r14
	.cfi_restore %r15
.LBB5_4:                                # %._crit_edge
	retq
.Lfunc_end5:
	.size	_Z11initialDataPfi, .Lfunc_end5-_Z11initialDataPfi
	.cfi_endproc
                                        # -- End function
	.globl	_Z12MatrixMulCPUPfS_S_i         # -- Begin function _Z12MatrixMulCPUPfS_S_i
	.type	_Z12MatrixMulCPUPfS_S_i,@function
_Z12MatrixMulCPUPfS_S_i:                # @_Z12MatrixMulCPUPfS_S_i
	.cfi_startproc
# %bb.0:
	testl	%ecx, %ecx
	jle	.LBB6_8
# %bb.1:                                # %.preheader23.lr.ph
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movl	%ecx, %eax
	leaq	(,%rax,4), %r8
	xorl	%r9d, %r9d
	xorl	%r10d, %r10d
.LBB6_2:                                # %.preheader.lr.ph
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB6_3 Depth 2
                                        #       Child Loop BB6_4 Depth 3
	movl	%r9d, %r11d
	leaq	(%rdi,%r11,4), %r11
	movq	%r10, %rbx
	imulq	%rax, %rbx
	leaq	(%rdx,%rbx,4), %rbx
	movq	%rsi, %r14
	xorl	%r15d, %r15d
.LBB6_3:                                # %.preheader
                                        #   Parent Loop BB6_2 Depth=1
                                        # =>  This Loop Header: Depth=2
                                        #       Child Loop BB6_4 Depth 3
	movss	(%rbx,%r15,4), %xmm0            # xmm0 = mem[0],zero,zero,zero
	movq	%r14, %r12
	xorl	%r13d, %r13d
.LBB6_4:                                #   Parent Loop BB6_2 Depth=1
                                        #     Parent Loop BB6_3 Depth=2
                                        # =>    This Inner Loop Header: Depth=3
	movss	(%r11,%r13,4), %xmm1            # xmm1 = mem[0],zero,zero,zero
	mulss	(%r12), %xmm1
	addss	%xmm1, %xmm0
	movss	%xmm0, (%rbx,%r15,4)
	incq	%r13
	addq	%r8, %r12
	cmpq	%r13, %rax
	jne	.LBB6_4
# %bb.5:                                # %._crit_edge
                                        #   in Loop: Header=BB6_3 Depth=2
	incq	%r15
	addq	$4, %r14
	cmpq	%rax, %r15
	jne	.LBB6_3
# %bb.6:                                # %._crit_edge26
                                        #   in Loop: Header=BB6_2 Depth=1
	incq	%r10
	addl	%ecx, %r9d
	cmpq	%rax, %r10
	jne	.LBB6_2
# %bb.7:
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	.cfi_restore %rbx
	.cfi_restore %r12
	.cfi_restore %r13
	.cfi_restore %r14
	.cfi_restore %r15
.LBB6_8:                                # %._crit_edge28
	retq
.Lfunc_end6:
	.size	_Z12MatrixMulCPUPfS_S_i, .Lfunc_end6-_Z12MatrixMulCPUPfS_S_i
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst16,"aM",@progbits,16
	.p2align	4, 0x0                          # -- Begin function _Z11checkResultPfS_i
.LCPI7_0:
	.long	0x7fffffff                      # float NaN
	.long	0x7fffffff                      # float NaN
	.long	0x7fffffff                      # float NaN
	.long	0x7fffffff                      # float NaN
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0
.LCPI7_1:
	.quad	0x3e45798ee2308c3a              # double 1.0E-8
	.text
	.globl	_Z11checkResultPfS_i
	.type	_Z11checkResultPfS_i,@function
_Z11checkResultPfS_i:                   # @_Z11checkResultPfS_i
	.cfi_startproc
# %bb.0:
	movq	%rdi, %rax
	movl	$.Lstr.1, %edi
	testl	%edx, %edx
	jle	puts@PLT                        # TAILCALL
# %bb.1:                                # %.lr.ph.preheader
	movl	%edx, %ecx
	xorl	%edx, %edx
	movaps	.LCPI7_0(%rip), %xmm0           # xmm0 = [NaN,NaN,NaN,NaN]
	movsd	.LCPI7_1(%rip), %xmm1           # xmm1 = mem[0],zero
	jmp	.LBB7_3
.LBB7_2:                                #   in Loop: Header=BB7_3 Depth=1
	incq	%rdx
	cmpq	%rdx, %rcx
	je	puts@PLT                        # TAILCALL
.LBB7_3:                                # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	movss	(%rax,%rdx,4), %xmm2            # xmm2 = mem[0],zero,zero,zero
	movss	(%rsi,%rdx,4), %xmm3            # xmm3 = mem[0],zero,zero,zero
	movaps	%xmm2, %xmm4
	subss	%xmm3, %xmm4
	andps	%xmm0, %xmm4
	cvtss2sd	%xmm4, %xmm4
	ucomisd	%xmm1, %xmm4
	jbe	.LBB7_2
# %bb.4:
	pushq	%rax
	.cfi_def_cfa_offset 16
	xorps	%xmm0, %xmm0
	cvtss2sd	%xmm2, %xmm0
	xorps	%xmm1, %xmm1
	cvtss2sd	%xmm3, %xmm1
	movl	$.L.str, %edi
	movb	$2, %al
	callq	printf
	movl	$.Lstr, %edi
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
	jmp	puts@PLT                        # TAILCALL
.Lfunc_end7:
	.size	_Z11checkResultPfS_i, .Lfunc_end7-_Z11checkResultPfS_i
	.cfi_endproc
                                        # -- End function
	.globl	_Z8printArrPfi                  # -- Begin function _Z8printArrPfi
	.type	_Z8printArrPfi,@function
_Z8printArrPfi:                         # @_Z8printArrPfi
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	pushq	%rax
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%esi, %ebp
	movq	%rdi, %rbx
	movl	$91, %edi
	callq	putchar@PLT
	testl	%ebp, %ebp
	jle	.LBB8_3
# %bb.1:                                # %.lr.ph.preheader
	movl	%ebp, %r14d
	xorl	%r15d, %r15d
.LBB8_2:                                # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	xorps	%xmm0, %xmm0
	cvtss2sd	(%rbx,%r15,4), %xmm0
	movl	$.L.str.4, %edi
	movb	$1, %al
	callq	printf
	incq	%r15
	cmpq	%r15, %r14
	jne	.LBB8_2
.LBB8_3:                                # %._crit_edge
	movl	$.Lstr.2, %edi
	addq	$8, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	puts@PLT                        # TAILCALL
.Lfunc_end8:
	.size	_Z8printArrPfi, .Lfunc_end8-_Z8printArrPfi
	.cfi_endproc
                                        # -- End function
	.globl	_Z7GPUtestPfS_S_ii              # -- Begin function _Z7GPUtestPfS_S_ii
	.type	_Z7GPUtestPfS_S_ii,@function
_Z7GPUtestPfS_S_ii:                     # @_Z7GPUtestPfS_S_ii
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$72, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%r8d, %r12d
	movl	%ecx, %r14d
	movq	%rdx, 24(%rsp)                  # 8-byte Spill
	movq	%rsi, %rbx
	movq	%rdi, %r15
	movl	%r8d, %eax
	imull	%eax, %eax
	movq	%rax, 56(%rsp)                  # 8-byte Spill
	leaq	(,%rax,4), %rbp
	leaq	16(%rsp), %r13
	movq	%r13, %rdi
	movq	%rbp, %rsi
	callq	hipMalloc
	leaq	8(%rsp), %rdi
	movq	%rbp, %rsi
	callq	hipMalloc
	movq	%rsp, %rdi
	movq	%rbp, %rsi
	callq	hipMalloc
	movl	$1, %edi
	movq	%rbp, %rsi
	callq	calloc@PLT
	movq	%rax, 48(%rsp)                  # 8-byte Spill
	leaq	40(%rsp), %rdi
	callq	hipEventCreate
	leaq	32(%rsp), %rdi
	callq	hipEventCreate
	movq	(%r13), %rdi
	movq	%r15, %rsi
	movq	%rbp, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	8(%rsp), %rax
	movq	(%rax), %rdi
	movq	%rbx, %rsi
	movq	%rbp, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	movl	%r14d, %eax
	movq	%rax, %r15
	shlq	$32, %r15
	orq	%rax, %r15
	leal	(%r14,%r12), %eax
	decl	%eax
	xorl	%edx, %edx
	divl	%r14d
                                        # kill: def $eax killed $eax def $rax
	movq	%rax, %rbx
	shlq	$32, %rbx
	orq	%rax, %rbx
	leaq	40(%rsp), %rax
	movq	(%rax), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	cmpl	$9, %r14d
	jle	.LBB9_1
# %bb.5:
	cmpl	$10, %r14d
	je	.LBB9_12
# %bb.6:
	cmpl	$20, %r14d
	movq	24(%rsp), %r13                  # 8-byte Reload
	je	.LBB9_14
# %bb.7:
	cmpl	$25, %r14d
	jne	.LBB9_16
# %bb.8:
	movq	%rbx, %rdi
	movl	$1, %esi
	movq	%r15, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB9_16
# %bb.9:
	movq	16(%rsp), %rdi
	movq	8(%rsp), %rsi
	movq	(%rsp), %rdx
	movl	%r12d, %ecx
	callq	_Z34__device_stub__TiledMatrixMulGPU25PfS_S_i
	jmp	.LBB9_16
.LBB9_1:
	cmpl	$2, %r14d
	je	.LBB9_10
# %bb.2:
	cmpl	$4, %r14d
	movq	24(%rsp), %r13                  # 8-byte Reload
	jne	.LBB9_16
# %bb.3:
	movq	%rbx, %rdi
	movl	$1, %esi
	movq	%r15, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB9_16
# %bb.4:
	movq	16(%rsp), %rdi
	movq	8(%rsp), %rsi
	movq	(%rsp), %rdx
	movl	%r12d, %ecx
	callq	_Z33__device_stub__TiledMatrixMulGPU4PfS_S_i
	jmp	.LBB9_16
.LBB9_12:
	movq	%rbx, %rdi
	movl	$1, %esi
	movq	%r15, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	movq	24(%rsp), %r13                  # 8-byte Reload
	jne	.LBB9_16
# %bb.13:
	movq	16(%rsp), %rdi
	movq	8(%rsp), %rsi
	movq	(%rsp), %rdx
	movl	%r12d, %ecx
	callq	_Z34__device_stub__TiledMatrixMulGPU10PfS_S_i
	jmp	.LBB9_16
.LBB9_14:
	movq	%rbx, %rdi
	movl	$1, %esi
	movq	%r15, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB9_16
# %bb.15:
	movq	16(%rsp), %rdi
	movq	8(%rsp), %rsi
	movq	(%rsp), %rdx
	movl	%r12d, %ecx
	callq	_Z34__device_stub__TiledMatrixMulGPU20PfS_S_i
	jmp	.LBB9_16
.LBB9_10:
	movq	%rbx, %rdi
	movl	$1, %esi
	movq	%r15, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	movq	24(%rsp), %r13                  # 8-byte Reload
	jne	.LBB9_16
# %bb.11:
	movq	16(%rsp), %rdi
	movq	8(%rsp), %rsi
	movq	(%rsp), %rdx
	movl	%r12d, %ecx
	callq	_Z33__device_stub__TiledMatrixMulGPU2PfS_S_i
.LBB9_16:
	movq	32(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	32(%rsp), %rdi
	callq	hipEventSynchronize
	movq	40(%rsp), %rsi
	movq	32(%rsp), %rdx
	leaq	68(%rsp), %rbx
	movq	%rbx, %rdi
	callq	hipEventElapsedTime
	movq	(%rsp), %rsi
	movq	48(%rsp), %r15                  # 8-byte Reload
	movq	%r15, %rdi
	movq	%rbp, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	cvtss2sd	(%rbx), %xmm0
	movl	$.L.str.6, %edi
	movl	%r14d, %esi
	movb	$1, %al
	callq	printf
	movq	%r13, %rdi
	movq	%r15, %rsi
	movq	56(%rsp), %rdx                  # 8-byte Reload
                                        # kill: def $edx killed $edx killed $rdx
	callq	_Z11checkResultPfS_i
	movq	16(%rsp), %rdi
	callq	hipFree
	movq	8(%rsp), %rdi
	callq	hipFree
	movq	(%rsp), %rdi
	callq	hipFree
	movq	%r15, %rdi
	callq	free
	movl	$.L.str.7, %edi
	movl	$.L.str.8, %esi
	callq	fopen
	movq	%rax, %r15
	xorps	%xmm0, %xmm0
	cvtss2sd	(%rbx), %xmm0
	movl	$.L.str.9, %esi
	movq	%rax, %rdi
	movl	%r12d, %edx
	movl	%r14d, %ecx
	movb	$1, %al
	callq	fprintf
	movq	%r15, %rdi
	callq	fclose
	addq	$72, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end9:
	.size	_Z7GPUtestPfS_S_ii, .Lfunc_end9-_Z7GPUtestPfS_S_ii
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0                          # -- Begin function _Z13computeMatrixi
.LCPI10_0:
	.long	0x41200000                      # float 10
	.section	.rodata.cst16,"aM",@progbits,16
	.p2align	4, 0x0
.LCPI10_1:
	.long	2                               # 0x2
	.long	4                               # 0x4
	.long	10                              # 0xa
	.long	20                              # 0x14
	.text
	.globl	_Z13computeMatrixi
	.type	_Z13computeMatrixi,@function
_Z13computeMatrixi:                     # @_Z13computeMatrixi
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$40, %rsp
	.cfi_def_cfa_offset 96
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%edi, %ebx
	movl	$.Lstr.7, %edi
	callq	puts@PLT
	movl	$.L.str.11, %edi
	movl	%ebx, %esi
	movl	%ebx, %edx
	xorl	%eax, %eax
	callq	printf
	movl	%ebx, %ebp
	imull	%ebp, %ebp
	leaq	(,%rbp,4), %r12
	movq	%r12, %rdi
	callq	malloc
	movq	%rax, %r14
	movq	%r12, %rdi
	callq	malloc
	movq	%rax, %r15
	movq	%r12, 8(%rsp)                   # 8-byte Spill
	movq	%r12, %rdi
	callq	malloc
	movq	%rax, %r12
	testl	%ebx, %ebx
	je	.LBB10_5
# %bb.1:                                # %.lr.ph.i.preheader
	xorl	%r13d, %r13d
.LBB10_2:                               # %.lr.ph.i
                                        # =>This Inner Loop Header: Depth=1
	callq	rand
	movss	.LCPI10_0(%rip), %xmm1          # xmm1 = mem[0],zero,zero,zero
	movzbl	%al, %eax
	xorps	%xmm0, %xmm0
	cvtsi2ss	%eax, %xmm0
	divss	%xmm1, %xmm0
	movss	%xmm0, (%r14,%r13,4)
	incq	%r13
	cmpq	%r13, %rbp
	jne	.LBB10_2
# %bb.3:                                # %.lr.ph.i30.preheader
	xorl	%r13d, %r13d
.LBB10_4:                               # %.lr.ph.i30
                                        # =>This Inner Loop Header: Depth=1
	callq	rand
	movzbl	%al, %eax
	xorps	%xmm0, %xmm0
	cvtsi2ss	%eax, %xmm0
	divss	.LCPI10_0(%rip), %xmm0
	movss	%xmm0, (%r15,%r13,4)
	incq	%r13
	cmpq	%r13, %rbp
	jne	.LBB10_4
.LBB10_5:                               # %_Z11initialDataPfi.exit34
	xorl	%ebp, %ebp
	movq	%r12, %rdi
	xorl	%esi, %esi
	movq	8(%rsp), %rdx                   # 8-byte Reload
	callq	memset@PLT
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movl	%ebx, %ecx
	callq	_Z12MatrixMulCPUPfS_S_i
	movaps	.LCPI10_1(%rip), %xmm0          # xmm0 = [2,4,10,20]
	movaps	%xmm0, 16(%rsp)
	movl	$25, 32(%rsp)
.LBB10_6:                               # =>This Inner Loop Header: Depth=1
	movl	16(%rsp,%rbp,4), %ecx
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movl	%ebx, %r8d
	callq	_Z7GPUtestPfS_S_ii
	incq	%rbp
	cmpq	$5, %rbp
	jne	.LBB10_6
# %bb.7:
	movq	%r14, %rdi
	callq	free
	movq	%r15, %rdi
	callq	free
	movq	%r12, %rdi
	callq	free
	addq	$40, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	hipDeviceReset                  # TAILCALL
.Lfunc_end10:
	.size	_Z13computeMatrixi, .Lfunc_end10-_Z13computeMatrixi
	.cfi_endproc
                                        # -- End function
	.globl	_Z38__device_stub__TiledMatrixMulGPUBonus1PfS_S_iii # -- Begin function _Z38__device_stub__TiledMatrixMulGPUBonus1PfS_S_iii
	.type	_Z38__device_stub__TiledMatrixMulGPUBonus1PfS_S_iii,@function
_Z38__device_stub__TiledMatrixMulGPUBonus1PfS_S_iii: # @_Z38__device_stub__TiledMatrixMulGPUBonus1PfS_S_iii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	20(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	16(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	12(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z23TiledMatrixMulGPUBonus1PfS_S_iii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end11:
	.size	_Z38__device_stub__TiledMatrixMulGPUBonus1PfS_S_iii, .Lfunc_end11-_Z38__device_stub__TiledMatrixMulGPUBonus1PfS_S_iii
	.cfi_endproc
                                        # -- End function
	.globl	_Z37__device_stub__TiledMatrixMulGPUBonusPfS_S_iii # -- Begin function _Z37__device_stub__TiledMatrixMulGPUBonusPfS_S_iii
	.type	_Z37__device_stub__TiledMatrixMulGPUBonusPfS_S_iii,@function
_Z37__device_stub__TiledMatrixMulGPUBonusPfS_S_iii: # @_Z37__device_stub__TiledMatrixMulGPUBonusPfS_S_iii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	20(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	16(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	12(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z22TiledMatrixMulGPUBonusPfS_S_iii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end12:
	.size	_Z37__device_stub__TiledMatrixMulGPUBonusPfS_S_iii, .Lfunc_end12-_Z37__device_stub__TiledMatrixMulGPUBonusPfS_S_iii
	.cfi_endproc
                                        # -- End function
	.globl	_Z17MatrixMulCPUBonusPfS_S_iii  # -- Begin function _Z17MatrixMulCPUBonusPfS_S_iii
	.type	_Z17MatrixMulCPUBonusPfS_S_iii,@function
_Z17MatrixMulCPUBonusPfS_S_iii:         # @_Z17MatrixMulCPUBonusPfS_S_iii
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%rdx, -8(%rsp)                  # 8-byte Spill
	movq	%rsi, -16(%rsp)                 # 8-byte Spill
	movq	%rdi, -24(%rsp)                 # 8-byte Spill
	testl	%ecx, %ecx
	jle	.LBB13_9
# %bb.1:                                # %.preheader27.lr.ph
	movslq	%r9d, %rdi
	movl	%ecx, %ecx
	movl	%edi, %r10d
	movl	%r8d, %r11d
	leaq	(,%rdi,4), %rbx
	xorl	%r14d, %r14d
	xorl	%r15d, %r15d
.LBB13_2:                               # %.preheader27
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB13_4 Depth 2
                                        #       Child Loop BB13_6 Depth 3
	testl	%r9d, %r9d
	jle	.LBB13_8
# %bb.3:                                # %.preheader.lr.ph
                                        #   in Loop: Header=BB13_2 Depth=1
	movl	%r14d, %eax
	movq	-24(%rsp), %rdx                 # 8-byte Reload
	leaq	(%rdx,%rax,4), %r12
	movq	%r15, %rax
	imulq	%rdi, %rax
	movq	-8(%rsp), %rdx                  # 8-byte Reload
	leaq	(%rdx,%rax,4), %r13
	movq	-16(%rsp), %rsi                 # 8-byte Reload
	xorl	%eax, %eax
.LBB13_4:                               # %.preheader
                                        #   Parent Loop BB13_2 Depth=1
                                        # =>  This Loop Header: Depth=2
                                        #       Child Loop BB13_6 Depth 3
	xorps	%xmm0, %xmm0
	testl	%r8d, %r8d
	jle	.LBB13_7
# %bb.5:                                # %.lr.ph.preheader
                                        #   in Loop: Header=BB13_4 Depth=2
	movq	%rsi, %rbp
	xorl	%edx, %edx
.LBB13_6:                               # %.lr.ph
                                        #   Parent Loop BB13_2 Depth=1
                                        #     Parent Loop BB13_4 Depth=2
                                        # =>    This Inner Loop Header: Depth=3
	movss	(%r12,%rdx,4), %xmm1            # xmm1 = mem[0],zero,zero,zero
	mulss	(%rbp), %xmm1
	addss	%xmm1, %xmm0
	incq	%rdx
	addq	%rbx, %rbp
	cmpq	%rdx, %r11
	jne	.LBB13_6
.LBB13_7:                               # %._crit_edge
                                        #   in Loop: Header=BB13_4 Depth=2
	movss	%xmm0, (%r13,%rax,4)
	incq	%rax
	addq	$4, %rsi
	cmpq	%r10, %rax
	jne	.LBB13_4
.LBB13_8:                               # %._crit_edge31
                                        #   in Loop: Header=BB13_2 Depth=1
	incq	%r15
	addl	%r8d, %r14d
	cmpq	%rcx, %r15
	jne	.LBB13_2
.LBB13_9:                               # %._crit_edge33
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end13:
	.size	_Z17MatrixMulCPUBonusPfS_S_iii, .Lfunc_end13-_Z17MatrixMulCPUBonusPfS_S_iii
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0                          # -- Begin function _Z18computeMatrixBonusiii
.LCPI14_0:
	.long	0x41200000                      # float 10
	.text
	.globl	_Z18computeMatrixBonusiii
	.type	_Z18computeMatrixBonusiii,@function
_Z18computeMatrixBonusiii:              # @_Z18computeMatrixBonusiii
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$104, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%edx, %r12d
	movl	%esi, %ebp
	movl	%edi, %r13d
	movl	$.Lstr.7, %edi
	callq	puts@PLT
	movl	$8, (%rsp)
	movl	$.L.str.12, %edi
	movl	%r13d, %esi
	movl	%ebp, %edx
	movl	%ebp, %ecx
	movl	%r12d, %r8d
	movl	$14, %r9d
	xorl	%eax, %eax
	callq	printf
	movl	%ebp, %ebx
	imull	%r13d, %ebx
	movslq	%ebx, %r14
	leaq	(,%r14,4), %rdi
	movl	%r12d, %r15d
	movl	%ebp, 20(%rsp)                  # 4-byte Spill
	imull	%ebp, %r15d
	movslq	%r15d, %rbp
	shlq	$2, %rbp
	movq	%r12, 64(%rsp)                  # 8-byte Spill
	movl	%r12d, %eax
	movq	%r13, 96(%rsp)                  # 8-byte Spill
	imull	%r13d, %eax
	movslq	%eax, %r13
	shlq	$2, %r13
	movq	%rdi, 80(%rsp)                  # 8-byte Spill
	callq	malloc
	movq	%rax, %r12
	movq	%rbp, 88(%rsp)                  # 8-byte Spill
	movq	%rbp, %rdi
	movq	%r13, %rbp
	callq	malloc
	movq	%rax, %r13
	movq	%rbp, %rdi
	callq	malloc
	movq	%rax, 56(%rsp)                  # 8-byte Spill
	movq	%rbp, %rdi
	callq	malloc
	movq	%rax, 48(%rsp)                  # 8-byte Spill
	testl	%r14d, %r14d
	jle	.LBB14_3
# %bb.1:                                # %.lr.ph.preheader.i
	movl	%ebx, %ebx
	xorl	%r14d, %r14d
.LBB14_2:                               # %.lr.ph.i
                                        # =>This Inner Loop Header: Depth=1
	callq	rand
	movzbl	%al, %eax
	xorps	%xmm0, %xmm0
	cvtsi2ss	%eax, %xmm0
	divss	.LCPI14_0(%rip), %xmm0
	movss	%xmm0, (%r12,%r14,4)
	incq	%r14
	cmpq	%r14, %rbx
	jne	.LBB14_2
.LBB14_3:                               # %_Z11initialDataPfi.exit
	testl	%r15d, %r15d
	jle	.LBB14_6
# %bb.4:                                # %.lr.ph.preheader.i57
	movl	%r15d, %ebx
	xorl	%r14d, %r14d
.LBB14_5:                               # %.lr.ph.i59
                                        # =>This Inner Loop Header: Depth=1
	callq	rand
	movzbl	%al, %eax
	xorps	%xmm0, %xmm0
	cvtsi2ss	%eax, %xmm0
	divss	.LCPI14_0(%rip), %xmm0
	movss	%xmm0, (%r13,%r14,4)
	incq	%r14
	cmpq	%r14, %rbx
	jne	.LBB14_5
.LBB14_6:                               # %_Z11initialDataPfi.exit63
	movq	56(%rsp), %rbx                  # 8-byte Reload
	movq	%rbx, %rdi
	xorl	%esi, %esi
	movq	%rbp, %rdx
	callq	memset@PLT
	movq	48(%rsp), %rdi                  # 8-byte Reload
	xorl	%esi, %esi
	movq	%rbp, %rdx
	callq	memset@PLT
	movq	%r12, %rdi
	movq	%r13, %rsi
	movq	%rbx, %rdx
	movq	96(%rsp), %r15                  # 8-byte Reload
	movl	%r15d, %ecx
	movl	20(%rsp), %r8d                  # 4-byte Reload
	movq	64(%rsp), %r9                   # 8-byte Reload
                                        # kill: def $r9d killed $r9d killed $r9
	callq	_Z17MatrixMulCPUBonusPfS_S_iii
	leaq	40(%rsp), %rdi
	movq	80(%rsp), %r14                  # 8-byte Reload
	movq	%r14, %rsi
	callq	hipMalloc
	leaq	32(%rsp), %rdi
	movq	88(%rsp), %rbx                  # 8-byte Reload
	movq	%rbx, %rsi
	callq	hipMalloc
	leaq	24(%rsp), %rdi
	movq	%rbp, 72(%rsp)                  # 8-byte Spill
	movq	%rbp, %rsi
	callq	hipMalloc
	leaq	40(%rsp), %rax
	movq	(%rax), %rdi
	movq	%r12, %rsi
	movq	%r14, %rdx
	movq	64(%rsp), %r14                  # 8-byte Reload
	movl	20(%rsp), %ebp                  # 4-byte Reload
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	32(%rsp), %rax
	movq	(%rax), %rdi
	movq	%r13, %rsi
	movq	%rbx, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	leal	7(%r14), %eax
	shrl	$3, %eax
	leal	13(%r15), %ecx
	shrl	%ecx
	movl	$2454267027, %edx               # imm = 0x92492493
	imulq	%rcx, %rdx
	shrq	$2, %rdx
	movabsq	$2305843004918726656, %rdi      # imm = 0x1FFFFFFF00000000
	andq	%rdx, %rdi
	orq	%rax, %rdi
	movabsq	$60129542152, %rdx              # imm = 0xE00000008
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB14_8
# %bb.7:
	movq	40(%rsp), %rdi
	movq	32(%rsp), %rsi
	movq	24(%rsp), %rdx
	movl	%r15d, %ecx
	movl	%ebp, %r8d
	movl	%r14d, %r9d
	callq	_Z37__device_stub__TiledMatrixMulGPUBonusPfS_S_iii
.LBB14_8:
	movq	24(%rsp), %rsi
	movq	48(%rsp), %r15                  # 8-byte Reload
	movq	%r15, %rdi
	movq	72(%rsp), %rdx                  # 8-byte Reload
	movl	$2, %ecx
	callq	hipMemcpy
	imull	%ebp, %ebp
	movq	56(%rsp), %r14                  # 8-byte Reload
	movq	%r14, %rdi
	movq	%r15, %rsi
	movl	%ebp, %edx
	callq	_Z11checkResultPfS_i
	movq	%r12, %rdi
	callq	free
	movq	%r13, %rdi
	callq	free
	movq	%r14, %rdi
	callq	free
	movq	%r15, %rdi
	callq	free
	movq	40(%rsp), %rdi
	callq	hipFree
	movq	32(%rsp), %rdi
	callq	hipFree
	movq	24(%rsp), %rdi
	callq	hipFree
	callq	hipDeviceReset
	addq	$104, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end14:
	.size	_Z18computeMatrixBonusiii, .Lfunc_end14-_Z18computeMatrixBonusiii
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst16,"aM",@progbits,16
	.p2align	4, 0x0                          # -- Begin function main
.LCPI15_0:
	.long	100                             # 0x64
	.long	200                             # 0xc8
	.long	500                             # 0x1f4
	.long	1000                            # 0x3e8
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movl	$.L.str.7, %edi
	movl	$.L.str.13, %esi
	callq	fopen
	movq	%rax, %rbx
	movl	$.L.str.14, %edi
	movl	$25, %esi
	movl	$1, %edx
	movq	%rax, %rcx
	callq	fwrite@PLT
	movq	%rbx, %rdi
	callq	fclose
	movaps	.LCPI15_0(%rip), %xmm0          # xmm0 = [100,200,500,1000]
	movaps	%xmm0, (%rsp)
	movabsq	$21474836481500, %rax           # imm = 0x1388000005DC
	movq	%rax, 16(%rsp)
	xorl	%ebx, %ebx
.LBB15_1:                               # =>This Inner Loop Header: Depth=1
	movl	(%rsp,%rbx,4), %edi
	callq	_Z13computeMatrixi
	incq	%rbx
	cmpq	$6, %rbx
	jne	.LBB15_1
# %bb.2:
	movl	$.Lstr.5, %edi
	callq	puts@PLT
	movl	$.Lstr.6, %edi
	callq	puts@PLT
	movl	$2, %edi
	movl	$3, %esi
	movl	$4, %edx
	callq	_Z18computeMatrixBonusiii
	movl	$250, %edi
	movl	$300, %esi                      # imm = 0x12C
	movl	$450, %edx                      # imm = 0x1C2
	callq	_Z18computeMatrixBonusiii
	movl	$.Lstr.7, %edi
	callq	puts@PLT
	xorl	%eax, %eax
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end15:
	.size	main, .Lfunc_end15-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB16_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB16_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z18TiledMatrixMulGPU2PfS_S_i, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z18TiledMatrixMulGPU4PfS_S_i, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z19TiledMatrixMulGPU10PfS_S_i, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z19TiledMatrixMulGPU20PfS_S_i, %esi
	movl	$.L__unnamed_4, %edx
	movl	$.L__unnamed_4, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z19TiledMatrixMulGPU25PfS_S_i, %esi
	movl	$.L__unnamed_5, %edx
	movl	$.L__unnamed_5, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z23TiledMatrixMulGPUBonus1PfS_S_iii, %esi
	movl	$.L__unnamed_6, %edx
	movl	$.L__unnamed_6, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z22TiledMatrixMulGPUBonusPfS_S_iii, %esi
	movl	$.L__unnamed_7, %edx
	movl	$.L__unnamed_7, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end16:
	.size	__hip_module_ctor, .Lfunc_end16-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB17_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB17_2:
	retq
.Lfunc_end17:
	.size	__hip_module_dtor, .Lfunc_end17-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z18TiledMatrixMulGPU2PfS_S_i,@object # @_Z18TiledMatrixMulGPU2PfS_S_i
	.section	.rodata,"a",@progbits
	.globl	_Z18TiledMatrixMulGPU2PfS_S_i
	.p2align	3, 0x0
_Z18TiledMatrixMulGPU2PfS_S_i:
	.quad	_Z33__device_stub__TiledMatrixMulGPU2PfS_S_i
	.size	_Z18TiledMatrixMulGPU2PfS_S_i, 8

	.type	_Z18TiledMatrixMulGPU4PfS_S_i,@object # @_Z18TiledMatrixMulGPU4PfS_S_i
	.globl	_Z18TiledMatrixMulGPU4PfS_S_i
	.p2align	3, 0x0
_Z18TiledMatrixMulGPU4PfS_S_i:
	.quad	_Z33__device_stub__TiledMatrixMulGPU4PfS_S_i
	.size	_Z18TiledMatrixMulGPU4PfS_S_i, 8

	.type	_Z19TiledMatrixMulGPU10PfS_S_i,@object # @_Z19TiledMatrixMulGPU10PfS_S_i
	.globl	_Z19TiledMatrixMulGPU10PfS_S_i
	.p2align	3, 0x0
_Z19TiledMatrixMulGPU10PfS_S_i:
	.quad	_Z34__device_stub__TiledMatrixMulGPU10PfS_S_i
	.size	_Z19TiledMatrixMulGPU10PfS_S_i, 8

	.type	_Z19TiledMatrixMulGPU20PfS_S_i,@object # @_Z19TiledMatrixMulGPU20PfS_S_i
	.globl	_Z19TiledMatrixMulGPU20PfS_S_i
	.p2align	3, 0x0
_Z19TiledMatrixMulGPU20PfS_S_i:
	.quad	_Z34__device_stub__TiledMatrixMulGPU20PfS_S_i
	.size	_Z19TiledMatrixMulGPU20PfS_S_i, 8

	.type	_Z19TiledMatrixMulGPU25PfS_S_i,@object # @_Z19TiledMatrixMulGPU25PfS_S_i
	.globl	_Z19TiledMatrixMulGPU25PfS_S_i
	.p2align	3, 0x0
_Z19TiledMatrixMulGPU25PfS_S_i:
	.quad	_Z34__device_stub__TiledMatrixMulGPU25PfS_S_i
	.size	_Z19TiledMatrixMulGPU25PfS_S_i, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"CPU %f GPU %f "
	.size	.L.str, 15

	.type	.L.str.4,@object                # @.str.4
.L.str.4:
	.asciz	"%f,"
	.size	.L.str.4, 4

	.type	.L.str.6,@object                # @.str.6
.L.str.6:
	.asciz	"The GPU took %f to perform the computation with tile size %d.\n"
	.size	.L.str.6, 63

	.type	.L.str.7,@object                # @.str.7
.L.str.7:
	.asciz	"machineProblem4.csv"
	.size	.L.str.7, 20

	.type	.L.str.8,@object                # @.str.8
.L.str.8:
	.asciz	"a"
	.size	.L.str.8, 2

	.type	.L.str.9,@object                # @.str.9
.L.str.9:
	.asciz	"%d,%d,%f\n"
	.size	.L.str.9, 10

	.type	.L.str.11,@object               # @.str.11
.L.str.11:
	.asciz	"%dx%d matrix multiplication.\n\n"
	.size	.L.str.11, 31

	.type	_Z23TiledMatrixMulGPUBonus1PfS_S_iii,@object # @_Z23TiledMatrixMulGPUBonus1PfS_S_iii
	.section	.rodata,"a",@progbits
	.globl	_Z23TiledMatrixMulGPUBonus1PfS_S_iii
	.p2align	3, 0x0
_Z23TiledMatrixMulGPUBonus1PfS_S_iii:
	.quad	_Z38__device_stub__TiledMatrixMulGPUBonus1PfS_S_iii
	.size	_Z23TiledMatrixMulGPUBonus1PfS_S_iii, 8

	.type	_Z22TiledMatrixMulGPUBonusPfS_S_iii,@object # @_Z22TiledMatrixMulGPUBonusPfS_S_iii
	.globl	_Z22TiledMatrixMulGPUBonusPfS_S_iii
	.p2align	3, 0x0
_Z22TiledMatrixMulGPUBonusPfS_S_iii:
	.quad	_Z37__device_stub__TiledMatrixMulGPUBonusPfS_S_iii
	.size	_Z22TiledMatrixMulGPUBonusPfS_S_iii, 8

	.type	.L.str.12,@object               # @.str.12
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str.12:
	.asciz	"%dx%d and %dx%d matrix multiplication with %dx%d tile size.\n\n"
	.size	.L.str.12, 62

	.type	.L.str.13,@object               # @.str.13
.L.str.13:
	.asciz	"w"
	.size	.L.str.13, 2

	.type	.L.str.14,@object               # @.str.14
.L.str.14:
	.asciz	"matrixSize,tileSize,time\n"
	.size	.L.str.14, 26

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z18TiledMatrixMulGPU2PfS_S_i"
	.size	.L__unnamed_1, 30

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z18TiledMatrixMulGPU4PfS_S_i"
	.size	.L__unnamed_2, 30

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z19TiledMatrixMulGPU10PfS_S_i"
	.size	.L__unnamed_3, 31

	.type	.L__unnamed_4,@object           # @3
.L__unnamed_4:
	.asciz	"_Z19TiledMatrixMulGPU20PfS_S_i"
	.size	.L__unnamed_4, 31

	.type	.L__unnamed_5,@object           # @4
.L__unnamed_5:
	.asciz	"_Z19TiledMatrixMulGPU25PfS_S_i"
	.size	.L__unnamed_5, 31

	.type	.L__unnamed_6,@object           # @5
.L__unnamed_6:
	.asciz	"_Z23TiledMatrixMulGPUBonus1PfS_S_iii"
	.size	.L__unnamed_6, 37

	.type	.L__unnamed_7,@object           # @6
.L__unnamed_7:
	.asciz	"_Z22TiledMatrixMulGPUBonusPfS_S_iii"
	.size	.L__unnamed_7, 36

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.type	.Lstr,@object                   # @str
	.section	.rodata.str1.1,"aMS",@progbits,1
.Lstr:
	.asciz	"Arrays do not match.\n"
	.size	.Lstr, 22

	.type	.Lstr.1,@object                 # @str.1
.Lstr.1:
	.asciz	"Test PASSED\n"
	.size	.Lstr.1, 13

	.type	.Lstr.2,@object                 # @str.2
.Lstr.2:
	.asciz	"\b]"
	.size	.Lstr.2, 3

	.type	.Lstr.5,@object                 # @str.5
.Lstr.5:
	.asciz	"------------------------------------------------------------------------"
	.size	.Lstr.5, 73

	.type	.Lstr.6,@object                 # @str.6
.Lstr.6:
	.asciz	"BONUS"
	.size	.Lstr.6, 6

	.type	.Lstr.7,@object                 # @str.7
.Lstr.7:
	.asciz	"------------------------------------------------------------------------\n"
	.size	.Lstr.7, 74

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z33__device_stub__TiledMatrixMulGPU2PfS_S_i
	.addrsig_sym _Z33__device_stub__TiledMatrixMulGPU4PfS_S_i
	.addrsig_sym _Z34__device_stub__TiledMatrixMulGPU10PfS_S_i
	.addrsig_sym _Z34__device_stub__TiledMatrixMulGPU20PfS_S_i
	.addrsig_sym _Z34__device_stub__TiledMatrixMulGPU25PfS_S_i
	.addrsig_sym _Z38__device_stub__TiledMatrixMulGPUBonus1PfS_S_iii
	.addrsig_sym _Z37__device_stub__TiledMatrixMulGPUBonusPfS_S_iii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z18TiledMatrixMulGPU2PfS_S_i
	.addrsig_sym _Z18TiledMatrixMulGPU4PfS_S_i
	.addrsig_sym _Z19TiledMatrixMulGPU10PfS_S_i
	.addrsig_sym _Z19TiledMatrixMulGPU20PfS_S_i
	.addrsig_sym _Z19TiledMatrixMulGPU25PfS_S_i
	.addrsig_sym _Z23TiledMatrixMulGPUBonus1PfS_S_iii
	.addrsig_sym _Z22TiledMatrixMulGPUBonusPfS_S_iii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z18TiledMatrixMulGPU2PfS_S_i ; -- Begin function _Z18TiledMatrixMulGPU2PfS_S_i
	.globl	_Z18TiledMatrixMulGPU2PfS_S_i
	.p2align	8
	.type	_Z18TiledMatrixMulGPU2PfS_S_i,@function
_Z18TiledMatrixMulGPU2PfS_S_i:          ; @_Z18TiledMatrixMulGPU2PfS_S_i
; %bb.0:
	s_clause 0x2
	s_load_b32 s8, s[0:1], 0x18
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b64 s[0:1], s[0:1], 0x10
	v_bfe_u32 v1, v0, 10, 10
	v_dual_mov_b32 v6, 0 :: v_dual_and_b32 v5, 0x3ff, v0
	s_lshl_b32 s2, s14, 1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshl_add_u32 v2, s15, 1, v1
	s_waitcnt lgkmcnt(0)
	v_mul_lo_u32 v4, v2, s8
	s_cmp_lt_u32 s8, 2
	s_cbranch_scc1 .LBB0_3
; %bb.1:                                ; %.lr.ph
	v_lshlrev_b32_e32 v2, 2, v5
	v_mul_lo_u32 v3, v1, s8
	v_dual_mov_b32 v6, 0 :: v_dual_lshlrev_b32 v7, 3, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_mov_b32 v1, 0 :: v_dual_add_nc_u32 v8, 16, v2
	v_add_nc_u32_e32 v0, v5, v4
	v_add_nc_u32_e32 v9, v7, v2
	s_lshr_b32 s3, s8, 1
	v_add3_u32 v2, v5, v3, s2
	v_add_nc_u32_e32 v10, v8, v7
	s_lshl_b32 s8, s8, 1
.LBB0_2:                                ; =>This Inner Loop Header: Depth=1
	v_mov_b32_e32 v3, v1
	v_lshlrev_b64 v[11:12], 2, v[0:1]
	v_add_nc_u32_e32 v0, 2, v0
	s_add_i32 s3, s3, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	s_cmp_eq_u32 s3, 0
	v_lshlrev_b64 v[13:14], 2, v[2:3]
	v_add_co_u32 v11, vcc_lo, s4, v11
	v_add_co_ci_u32_e32 v12, vcc_lo, s5, v12, vcc_lo
	v_add_nc_u32_e32 v2, s8, v2
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_u32 v13, vcc_lo, s6, v13
	v_add_co_ci_u32_e32 v14, vcc_lo, s7, v14, vcc_lo
	global_load_b32 v3, v[11:12], off
	global_load_b32 v11, v[13:14], off
	s_waitcnt vmcnt(1)
	ds_store_b32 v9, v3
	s_waitcnt vmcnt(0)
	ds_store_b32 v10, v11
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_b64 v[11:12], v7
	ds_load_2addr_b32 v[13:14], v8 offset1:2
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_fmac_f32_e32 v6, v11, v13
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v6, v12, v14
	s_cbranch_scc0 .LBB0_2
.LBB0_3:                                ; %Flow62
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add3_u32 v0, s2, v5, v4
	v_mov_b32_e32 v1, 0
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	global_store_b32 v[0:1], v6, off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z18TiledMatrixMulGPU2PfS_S_i
		.amdhsa_group_segment_fixed_size 32
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 28
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 15
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z18TiledMatrixMulGPU2PfS_S_i, .Lfunc_end0-_Z18TiledMatrixMulGPU2PfS_S_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 376
; NumSgprs: 18
; NumVgprs: 15
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 32 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 15
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z18TiledMatrixMulGPU4PfS_S_i ; -- Begin function _Z18TiledMatrixMulGPU4PfS_S_i
	.globl	_Z18TiledMatrixMulGPU4PfS_S_i
	.p2align	8
	.type	_Z18TiledMatrixMulGPU4PfS_S_i,@function
_Z18TiledMatrixMulGPU4PfS_S_i:          ; @_Z18TiledMatrixMulGPU4PfS_S_i
; %bb.0:
	s_clause 0x2
	s_load_b32 s2, s[0:1], 0x18
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b64 s[0:1], s[0:1], 0x10
	v_bfe_u32 v4, v0, 10, 10
	v_and_b32_e32 v1, 0x3ff, v0
	v_mov_b32_e32 v5, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshl_add_u32 v2, s15, 2, v4
	v_lshl_add_u32 v0, s14, 2, v1
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2)
	v_mul_lo_u32 v3, v2, s2
	s_cmp_lt_u32 s2, 4
	s_cbranch_scc1 .LBB1_5
; %bb.1:                                ; %.lr.ph
	v_dual_mov_b32 v5, 0 :: v_dual_lshlrev_b32 v2, 2, v1
	v_lshlrev_b32_e32 v6, 4, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v8, v3, v1
	s_lshr_b32 s3, s2, 2
	v_add_nc_u32_e32 v7, 64, v2
	s_mov_b32 s8, 0
	v_dual_mov_b32 v2, 0 :: v_dual_add_nc_u32 v9, v6, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_nc_u32_e32 v10, v7, v6
.LBB1_2:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB1_3 Depth 2
	s_lshl_b32 s9, s8, 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v13, s9, v4
	v_add_nc_u32_e32 v1, s9, v8
	s_mov_b32 s9, 0
	v_mad_u64_u32 v[11:12], null, v13, s2, v[0:1]
	v_mov_b32_e32 v12, v2
	v_lshlrev_b64 v[13:14], 2, v[1:2]
	v_mov_b32_e32 v1, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[11:12], 2, v[11:12]
	v_add_co_u32 v13, vcc_lo, s4, v13
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v14, vcc_lo, s5, v14, vcc_lo
	v_add_co_u32 v11, vcc_lo, s6, v11
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v12, vcc_lo, s7, v12, vcc_lo
	global_load_b32 v13, v[13:14], off
	global_load_b32 v11, v[11:12], off
	s_waitcnt vmcnt(1)
	ds_store_b32 v9, v13
	s_waitcnt vmcnt(0)
	ds_store_b32 v10, v11
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
.LBB1_3:                                ;   Parent Loop BB1_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_add_nc_u32_e32 v11, s9, v6
	s_add_i32 s9, s9, 4
	ds_load_b32 v12, v1
	ds_load_b32 v11, v11
	v_add_nc_u32_e32 v1, 16, v1
	s_cmp_eq_u32 s9, 16
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v5, v11, v12
	s_cbranch_scc0 .LBB1_3
; %bb.4:                                ;   in Loop: Header=BB1_2 Depth=1
	s_add_i32 s8, s8, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s8, s3
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc0 .LBB1_2
.LBB1_5:                                ; %Flow62
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v1, 0 :: v_dual_add_nc_u32 v0, v3, v0
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	global_store_b32 v[0:1], v5, off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z18TiledMatrixMulGPU4PfS_S_i
		.amdhsa_group_segment_fixed_size 128
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 28
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 15
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z18TiledMatrixMulGPU4PfS_S_i, .Lfunc_end1-_Z18TiledMatrixMulGPU4PfS_S_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 412
; NumSgprs: 18
; NumVgprs: 15
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 128 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 15
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z19TiledMatrixMulGPU10PfS_S_i ; -- Begin function _Z19TiledMatrixMulGPU10PfS_S_i
	.globl	_Z19TiledMatrixMulGPU10PfS_S_i
	.p2align	8
	.type	_Z19TiledMatrixMulGPU10PfS_S_i,@function
_Z19TiledMatrixMulGPU10PfS_S_i:         ; @_Z19TiledMatrixMulGPU10PfS_S_i
; %bb.0:
	s_load_b32 s2, s[0:1], 0x18
	v_bfe_u32 v2, v0, 10, 10
	s_clause 0x1
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b64 s[0:1], s[0:1], 0x10
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[4:5], null, s15, 10, v[2:3]
	v_and_b32_e32 v3, 0x3ff, v0
	v_mov_b32_e32 v5, 0
	v_mad_u64_u32 v[0:1], null, s14, 10, v[3:4]
	s_waitcnt lgkmcnt(0)
	v_mul_lo_u32 v1, v4, s2
	s_cmp_lt_u32 s2, 10
	s_cbranch_scc1 .LBB2_5
; %bb.1:                                ; %.lr.ph
	v_dual_mov_b32 v5, 0 :: v_dual_lshlrev_b32 v4, 2, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v7, v1, v3
	v_mul_u32_u24_e32 v8, 40, v2
	s_mul_hi_u32 s3, s2, 0xcccccccd
	v_add_nc_u32_e32 v6, 0x190, v4
	v_mad_u32_u24 v9, v2, 40, v4
	v_mov_b32_e32 v4, 0
	s_lshr_b32 s3, s3, 3
	s_mov_b32 s8, 0
	v_mad_u32_u24 v10, v2, 40, v6
.LBB2_2:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB2_3 Depth 2
	s_mul_i32 s9, s8, 10
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v13, s9, v2
	v_add_nc_u32_e32 v3, s9, v7
	s_mov_b32 s9, 0
	v_mad_u64_u32 v[11:12], null, v13, s2, v[0:1]
	v_mov_b32_e32 v12, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[13:14], 2, v[3:4]
	v_mov_b32_e32 v3, v6
	v_lshlrev_b64 v[11:12], 2, v[11:12]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v13, vcc_lo, s4, v13
	v_add_co_ci_u32_e32 v14, vcc_lo, s5, v14, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v11, vcc_lo, s6, v11
	v_add_co_ci_u32_e32 v12, vcc_lo, s7, v12, vcc_lo
	global_load_b32 v13, v[13:14], off
	global_load_b32 v11, v[11:12], off
	s_waitcnt vmcnt(1)
	ds_store_b32 v9, v13
	s_waitcnt vmcnt(0)
	ds_store_b32 v10, v11
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
.LBB2_3:                                ;   Parent Loop BB2_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_add_nc_u32_e32 v11, s9, v8
	s_add_i32 s9, s9, 4
	ds_load_b32 v12, v3
	ds_load_b32 v11, v11
	v_add_nc_u32_e32 v3, 40, v3
	s_cmp_eq_u32 s9, 40
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v5, v11, v12
	s_cbranch_scc0 .LBB2_3
; %bb.4:                                ;   in Loop: Header=BB2_2 Depth=1
	s_add_i32 s8, s8, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s8, s3
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc0 .LBB2_2
.LBB2_5:                                ; %Flow62
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v1, 0 :: v_dual_add_nc_u32 v0, v1, v0
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	global_store_b32 v[0:1], v5, off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z19TiledMatrixMulGPU10PfS_S_i
		.amdhsa_group_segment_fixed_size 800
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 28
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 15
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_Z19TiledMatrixMulGPU10PfS_S_i, .Lfunc_end2-_Z19TiledMatrixMulGPU10PfS_S_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 424
; NumSgprs: 18
; NumVgprs: 15
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 800 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 15
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z19TiledMatrixMulGPU20PfS_S_i ; -- Begin function _Z19TiledMatrixMulGPU20PfS_S_i
	.globl	_Z19TiledMatrixMulGPU20PfS_S_i
	.p2align	8
	.type	_Z19TiledMatrixMulGPU20PfS_S_i,@function
_Z19TiledMatrixMulGPU20PfS_S_i:         ; @_Z19TiledMatrixMulGPU20PfS_S_i
; %bb.0:
	s_load_b32 s2, s[0:1], 0x18
	v_bfe_u32 v2, v0, 10, 10
	s_clause 0x1
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b64 s[0:1], s[0:1], 0x10
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[4:5], null, s15, 20, v[2:3]
	v_and_b32_e32 v3, 0x3ff, v0
	v_mov_b32_e32 v5, 0
	v_mad_u64_u32 v[0:1], null, s14, 20, v[3:4]
	s_waitcnt lgkmcnt(0)
	v_mul_lo_u32 v1, v4, s2
	s_cmp_lt_u32 s2, 20
	s_cbranch_scc1 .LBB3_5
; %bb.1:                                ; %.lr.ph
	v_dual_mov_b32 v5, 0 :: v_dual_lshlrev_b32 v4, 2, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v7, v1, v3
	v_mul_u32_u24_e32 v8, 0x50, v2
	s_mul_hi_u32 s3, s2, 0xcccccccd
	v_add_nc_u32_e32 v6, 0x640, v4
	v_mad_u32_u24 v9, 0x50, v2, v4
	v_mov_b32_e32 v4, 0
	s_lshr_b32 s3, s3, 4
	s_mov_b32 s8, 0
	v_mad_u32_u24 v10, 0x50, v2, v6
.LBB3_2:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB3_3 Depth 2
	s_mul_i32 s9, s8, 20
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v13, s9, v2
	v_add_nc_u32_e32 v3, s9, v7
	s_mov_b32 s9, 0
	v_mad_u64_u32 v[11:12], null, v13, s2, v[0:1]
	v_mov_b32_e32 v12, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[13:14], 2, v[3:4]
	v_mov_b32_e32 v3, v6
	v_lshlrev_b64 v[11:12], 2, v[11:12]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v13, vcc_lo, s4, v13
	v_add_co_ci_u32_e32 v14, vcc_lo, s5, v14, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v11, vcc_lo, s6, v11
	v_add_co_ci_u32_e32 v12, vcc_lo, s7, v12, vcc_lo
	global_load_b32 v13, v[13:14], off
	global_load_b32 v11, v[11:12], off
	s_waitcnt vmcnt(1)
	ds_store_b32 v9, v13
	s_waitcnt vmcnt(0)
	ds_store_b32 v10, v11
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
.LBB3_3:                                ;   Parent Loop BB3_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_add_nc_u32_e32 v11, s9, v8
	s_add_i32 s9, s9, 4
	ds_load_b32 v12, v3
	ds_load_b32 v11, v11
	v_add_nc_u32_e32 v3, 0x50, v3
	s_cmpk_eq_i32 s9, 0x50
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v5, v11, v12
	s_cbranch_scc0 .LBB3_3
; %bb.4:                                ;   in Loop: Header=BB3_2 Depth=1
	s_add_i32 s8, s8, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s8, s3
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc0 .LBB3_2
.LBB3_5:                                ; %Flow62
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v1, 0 :: v_dual_add_nc_u32 v0, v1, v0
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	global_store_b32 v[0:1], v5, off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z19TiledMatrixMulGPU20PfS_S_i
		.amdhsa_group_segment_fixed_size 3200
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 28
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 15
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end3:
	.size	_Z19TiledMatrixMulGPU20PfS_S_i, .Lfunc_end3-_Z19TiledMatrixMulGPU20PfS_S_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 440
; NumSgprs: 18
; NumVgprs: 15
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 3200 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 15
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z19TiledMatrixMulGPU25PfS_S_i ; -- Begin function _Z19TiledMatrixMulGPU25PfS_S_i
	.globl	_Z19TiledMatrixMulGPU25PfS_S_i
	.p2align	8
	.type	_Z19TiledMatrixMulGPU25PfS_S_i,@function
_Z19TiledMatrixMulGPU25PfS_S_i:         ; @_Z19TiledMatrixMulGPU25PfS_S_i
; %bb.0:
	s_load_b32 s2, s[0:1], 0x18
	v_bfe_u32 v2, v0, 10, 10
	s_clause 0x1
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b64 s[0:1], s[0:1], 0x10
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[4:5], null, s15, 25, v[2:3]
	v_and_b32_e32 v3, 0x3ff, v0
	v_mov_b32_e32 v5, 0
	v_mad_u64_u32 v[0:1], null, s14, 25, v[3:4]
	s_waitcnt lgkmcnt(0)
	v_mul_lo_u32 v1, v4, s2
	s_cmp_lt_u32 s2, 25
	s_cbranch_scc1 .LBB4_5
; %bb.1:                                ; %.lr.ph
	v_dual_mov_b32 v5, 0 :: v_dual_lshlrev_b32 v4, 2, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v7, v1, v3
	v_mul_u32_u24_e32 v8, 0x64, v2
	s_mul_hi_u32 s3, s2, 0x51eb851f
	v_add_nc_u32_e32 v6, 0x9d0, v4
	v_mad_u32_u24 v9, 0x64, v2, v4
	v_mov_b32_e32 v4, 0
	s_lshr_b32 s3, s3, 3
	s_mov_b32 s8, 0
	v_mad_u32_u24 v10, 0x64, v2, v6
.LBB4_2:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB4_3 Depth 2
	s_mul_i32 s9, s8, 25
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v13, s9, v2
	v_add_nc_u32_e32 v3, s9, v7
	s_mov_b32 s9, 0
	v_mad_u64_u32 v[11:12], null, v13, s2, v[0:1]
	v_mov_b32_e32 v12, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[13:14], 2, v[3:4]
	v_mov_b32_e32 v3, v6
	v_lshlrev_b64 v[11:12], 2, v[11:12]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v13, vcc_lo, s4, v13
	v_add_co_ci_u32_e32 v14, vcc_lo, s5, v14, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v11, vcc_lo, s6, v11
	v_add_co_ci_u32_e32 v12, vcc_lo, s7, v12, vcc_lo
	global_load_b32 v13, v[13:14], off
	global_load_b32 v11, v[11:12], off
	s_waitcnt vmcnt(1)
	ds_store_b32 v9, v13
	s_waitcnt vmcnt(0)
	ds_store_b32 v10, v11
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
.LBB4_3:                                ;   Parent Loop BB4_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_add_nc_u32_e32 v11, s9, v8
	s_add_i32 s9, s9, 4
	ds_load_b32 v12, v3
	ds_load_b32 v11, v11
	v_add_nc_u32_e32 v3, 0x64, v3
	s_cmpk_eq_i32 s9, 0x64
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v5, v11, v12
	s_cbranch_scc0 .LBB4_3
; %bb.4:                                ;   in Loop: Header=BB4_2 Depth=1
	s_add_i32 s8, s8, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s8, s3
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc0 .LBB4_2
.LBB4_5:                                ; %Flow62
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v1, 0 :: v_dual_add_nc_u32 v0, v1, v0
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	global_store_b32 v[0:1], v5, off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z19TiledMatrixMulGPU25PfS_S_i
		.amdhsa_group_segment_fixed_size 5012
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 28
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 15
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end4:
	.size	_Z19TiledMatrixMulGPU25PfS_S_i, .Lfunc_end4-_Z19TiledMatrixMulGPU25PfS_S_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 440
; NumSgprs: 18
; NumVgprs: 15
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 5012 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 15
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z23TiledMatrixMulGPUBonus1PfS_S_iii ; -- Begin function _Z23TiledMatrixMulGPUBonus1PfS_S_iii
	.globl	_Z23TiledMatrixMulGPUBonus1PfS_S_iii
	.p2align	8
	.type	_Z23TiledMatrixMulGPUBonus1PfS_S_iii,@function
_Z23TiledMatrixMulGPUBonus1PfS_S_iii:   ; @_Z23TiledMatrixMulGPUBonus1PfS_S_iii
; %bb.0:
	s_clause 0x2
	s_load_b128 s[4:7], s[0:1], 0x18
	s_load_b128 s[8:11], s[0:1], 0x0
	s_load_b64 s[12:13], s[0:1], 0x10
	v_bfe_u32 v1, v0, 10, 10
	v_dual_mov_b32 v6, 0 :: v_dual_and_b32 v5, 0x3ff, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[2:3], null, s15, 14, v[1:2]
	v_lshl_add_u32 v0, s14, 3, v5
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_i32_e32 vcc_lo, s4, v2
	v_cmp_gt_i32_e64 s2, s6, v0
	s_cmp_lt_i32 s5, -5
	s_cbranch_scc1 .LBB5_9
; %bb.1:                                ; %.lr.ph
	v_dual_mov_b32 v4, 0 :: v_dual_lshlrev_b32 v3, 2, v5
	v_dual_mov_b32 v6, 0 :: v_dual_lshlrev_b32 v7, 5, v1
	v_mul_lo_u32 v9, v2, s5
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v8, 0x1c0, v3
	s_add_i32 s3, s5, 7
	v_add_nc_u32_e32 v10, v7, v3
	s_lshr_b32 s7, s3, 1
	s_mov_b32 s16, 0
	v_add_nc_u32_e32 v11, v8, v7
.LBB5_2:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB5_7 Depth 2
	s_lshl_b32 s17, s16, 3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v3, 0 :: v_dual_add_nc_u32 v12, s17, v5
	v_cmp_gt_u32_e64 s3, s5, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s3, vcc_lo, s3
	s_and_saveexec_b32 s18, s3
	s_cbranch_execz .LBB5_4
; %bb.3:                                ;   in Loop: Header=BB5_2 Depth=1
	v_add_nc_u32_e32 v3, v12, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[12:13], 2, v[3:4]
	v_add_co_u32 v12, s3, s8, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v13, s3, s9, v13, s3
	global_load_b32 v3, v[12:13], off
.LBB5_4:                                ;   in Loop: Header=BB5_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s18
	v_dual_mov_b32 v13, 0 :: v_dual_add_nc_u32 v12, s17, v1
	s_waitcnt vmcnt(0)
	ds_store_b32 v10, v3
	v_cmp_gt_u32_e64 s3, s5, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s3, s2, s3
	s_and_saveexec_b32 s17, s3
	s_cbranch_execz .LBB5_6
; %bb.5:                                ;   in Loop: Header=BB5_2 Depth=1
	v_mad_u64_u32 v[13:14], null, v12, s6, v[0:1]
	v_mov_b32_e32 v14, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[12:13], 2, v[13:14]
	v_add_co_u32 v12, s3, s10, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v13, s3, s11, v13, s3
	global_load_b32 v13, v[12:13], off
.LBB5_6:                                ;   in Loop: Header=BB5_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s17
	v_mov_b32_e32 v3, v8
	s_mov_b32 s3, 0
	s_waitcnt vmcnt(0)
	ds_store_b32 v11, v13
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
.LBB5_7:                                ;   Parent Loop BB5_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_add_nc_u32_e32 v12, s3, v7
	s_add_i32 s3, s3, 4
	ds_load_b32 v13, v3
	ds_load_b32 v12, v12
	v_add_nc_u32_e32 v3, 32, v3
	s_cmp_eq_u32 s3, 32
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v6, v12, v13
	s_cbranch_scc0 .LBB5_7
; %bb.8:                                ;   in Loop: Header=BB5_2 Depth=1
	s_add_i32 s16, s16, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s16, s7
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc0 .LBB5_2
.LBB5_9:                                ; %Flow98
	v_cmp_gt_i32_e32 vcc_lo, s4, v2
	v_cmp_gt_i32_e64 s2, s6, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, vcc_lo, s2
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB5_11
; %bb.10:
	s_load_b32 s0, s[0:1], 0x34
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s1, s0, 16
	s_and_b32 s0, s0, 0xffff
	v_mad_u64_u32 v[2:3], null, s15, s1, v[1:2]
	s_mul_i32 s14, s14, s0
	v_mov_b32_e32 v1, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v0, v2, s6
	v_add3_u32 v0, s14, v5, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	v_add_co_u32 v0, vcc_lo, s12, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s13, v1, vcc_lo
	global_store_b32 v[0:1], v6, off
.LBB5_11:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z23TiledMatrixMulGPUBonus1PfS_S_iii
		.amdhsa_group_segment_fixed_size 896
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 15
		.amdhsa_next_free_sgpr 19
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end5:
	.size	_Z23TiledMatrixMulGPUBonus1PfS_S_iii, .Lfunc_end5-_Z23TiledMatrixMulGPUBonus1PfS_S_iii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 584
; NumSgprs: 21
; NumVgprs: 15
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 896 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 21
; NumVGPRsForWavesPerEU: 15
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z22TiledMatrixMulGPUBonusPfS_S_iii ; -- Begin function _Z22TiledMatrixMulGPUBonusPfS_S_iii
	.globl	_Z22TiledMatrixMulGPUBonusPfS_S_iii
	.p2align	8
	.type	_Z22TiledMatrixMulGPUBonusPfS_S_iii,@function
_Z22TiledMatrixMulGPUBonusPfS_S_iii:    ; @_Z22TiledMatrixMulGPUBonusPfS_S_iii
; %bb.0:
	s_clause 0x2
	s_load_b128 s[4:7], s[0:1], 0x18
	s_load_b128 s[8:11], s[0:1], 0x0
	s_load_b64 s[12:13], s[0:1], 0x10
	v_bfe_u32 v1, v0, 10, 10
	v_dual_mov_b32 v6, 0 :: v_dual_and_b32 v5, 0x3ff, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[2:3], null, s15, 14, v[1:2]
	v_lshl_add_u32 v0, s14, 3, v5
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_i32_e32 vcc_lo, s4, v2
	v_cmp_gt_i32_e64 s2, s6, v0
	s_cmp_lt_i32 s5, -5
	s_cbranch_scc1 .LBB6_9
; %bb.1:                                ; %.lr.ph
	v_dual_mov_b32 v4, 0 :: v_dual_lshlrev_b32 v3, 2, v5
	v_dual_mov_b32 v6, 0 :: v_dual_lshlrev_b32 v7, 5, v1
	v_mul_lo_u32 v9, v2, s5
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v8, 0x1c0, v3
	s_add_i32 s3, s5, 7
	v_add_nc_u32_e32 v10, v7, v3
	s_lshr_b32 s7, s3, 1
	s_mov_b32 s16, 0
	v_add_nc_u32_e32 v11, v8, v7
.LBB6_2:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB6_7 Depth 2
	s_lshl_b32 s17, s16, 3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v3, 0 :: v_dual_add_nc_u32 v12, s17, v5
	v_cmp_gt_u32_e64 s3, s5, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s3, vcc_lo, s3
	s_and_saveexec_b32 s18, s3
	s_cbranch_execz .LBB6_4
; %bb.3:                                ;   in Loop: Header=BB6_2 Depth=1
	v_add_nc_u32_e32 v3, v12, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[12:13], 2, v[3:4]
	v_add_co_u32 v12, s3, s8, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v13, s3, s9, v13, s3
	global_load_b32 v3, v[12:13], off
.LBB6_4:                                ;   in Loop: Header=BB6_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s18
	v_dual_mov_b32 v13, 0 :: v_dual_add_nc_u32 v12, s17, v1
	s_waitcnt vmcnt(0)
	ds_store_b32 v10, v3
	v_cmp_gt_u32_e64 s3, s5, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s3, s2, s3
	s_and_saveexec_b32 s17, s3
	s_cbranch_execz .LBB6_6
; %bb.5:                                ;   in Loop: Header=BB6_2 Depth=1
	v_mad_u64_u32 v[13:14], null, v12, s6, v[0:1]
	v_mov_b32_e32 v14, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[12:13], 2, v[13:14]
	v_add_co_u32 v12, s3, s10, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v13, s3, s11, v13, s3
	global_load_b32 v13, v[12:13], off
.LBB6_6:                                ;   in Loop: Header=BB6_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s17
	v_mov_b32_e32 v3, v8
	s_mov_b32 s3, 0
	s_waitcnt vmcnt(0)
	ds_store_b32 v11, v13
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
.LBB6_7:                                ;   Parent Loop BB6_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_add_nc_u32_e32 v12, s3, v7
	s_add_i32 s3, s3, 4
	ds_load_b32 v13, v3
	ds_load_b32 v12, v12
	v_add_nc_u32_e32 v3, 32, v3
	s_cmp_eq_u32 s3, 32
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v6, v12, v13
	s_cbranch_scc0 .LBB6_7
; %bb.8:                                ;   in Loop: Header=BB6_2 Depth=1
	s_add_i32 s16, s16, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s16, s7
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc0 .LBB6_2
.LBB6_9:                                ; %Flow95
	v_cmp_gt_i32_e32 vcc_lo, s4, v2
	v_cmp_gt_i32_e64 s2, s6, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, vcc_lo, s2
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB6_11
; %bb.10:
	s_load_b32 s0, s[0:1], 0x34
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s1, s0, 16
	s_and_b32 s0, s0, 0xffff
	v_mad_u64_u32 v[2:3], null, s15, s1, v[1:2]
	s_mul_i32 s14, s14, s0
	v_mov_b32_e32 v1, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v0, v2, s6
	v_add3_u32 v0, s14, v5, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	v_add_co_u32 v0, vcc_lo, s12, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s13, v1, vcc_lo
	global_store_b32 v[0:1], v6, off
.LBB6_11:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z22TiledMatrixMulGPUBonusPfS_S_iii
		.amdhsa_group_segment_fixed_size 896
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 15
		.amdhsa_next_free_sgpr 19
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end6:
	.size	_Z22TiledMatrixMulGPUBonusPfS_S_iii, .Lfunc_end6-_Z22TiledMatrixMulGPUBonusPfS_S_iii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 584
; NumSgprs: 21
; NumVgprs: 15
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 896 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 21
; NumVGPRsForWavesPerEU: 15
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
    .group_segment_fixed_size: 32
    .kernarg_segment_align: 8
    .kernarg_segment_size: 28
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z18TiledMatrixMulGPU2PfS_S_i
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z18TiledMatrixMulGPU2PfS_S_i.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     15
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
    .group_segment_fixed_size: 128
    .kernarg_segment_align: 8
    .kernarg_segment_size: 28
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z18TiledMatrixMulGPU4PfS_S_i
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z18TiledMatrixMulGPU4PfS_S_i.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     15
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
    .group_segment_fixed_size: 800
    .kernarg_segment_align: 8
    .kernarg_segment_size: 28
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z19TiledMatrixMulGPU10PfS_S_i
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z19TiledMatrixMulGPU10PfS_S_i.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     15
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
    .group_segment_fixed_size: 3200
    .kernarg_segment_align: 8
    .kernarg_segment_size: 28
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z19TiledMatrixMulGPU20PfS_S_i
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z19TiledMatrixMulGPU20PfS_S_i.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     15
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
    .group_segment_fixed_size: 5012
    .kernarg_segment_align: 8
    .kernarg_segment_size: 28
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z19TiledMatrixMulGPU25PfS_S_i
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z19TiledMatrixMulGPU25PfS_S_i.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     15
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         44
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         52
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         54
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         56
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         58
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         60
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         62
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         104
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 896
    .kernarg_segment_align: 8
    .kernarg_segment_size: 296
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z23TiledMatrixMulGPUBonus1PfS_S_iii
    .private_segment_fixed_size: 0
    .sgpr_count:     21
    .sgpr_spill_count: 0
    .symbol:         _Z23TiledMatrixMulGPUBonus1PfS_S_iii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     15
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         44
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         52
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         54
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         56
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         58
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         60
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         62
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         104
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 896
    .kernarg_segment_align: 8
    .kernarg_segment_size: 296
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z22TiledMatrixMulGPUBonusPfS_S_iii
    .private_segment_fixed_size: 0
    .sgpr_count:     21
    .sgpr_spill_count: 0
    .symbol:         _Z22TiledMatrixMulGPUBonusPfS_S_iii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     15
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
