#include <stdio.h>
#include <cuda.h>
#include <math.h>

__global__ void TwoDimPoisson(float *d_A, float *d_B, float *d_F, double dx, float* diff)
{
	int threadId = threadIdx.x + (blockIdx.x * blockDim.x);
	int threadAbove = threadId - blockDim.x;
	int threadBelow = threadId + blockDim.x;
	int N = gridDim.x * blockDim.x;

	// Punt if this thread is a boundary point
	if ((threadAbove <= 0) || (threadBelow >= N-1) ||
			(threadId % (blockDim.x) == 0) || 
			((threadId+1) % (blockDim.x) == 0))
		return;
	else
	{ 
		d_B[threadId] = (.25*(d_A[threadId+1] + d_A[threadId-1]
					+ d_A[threadAbove] + d_A[threadBelow])
				+ d_F[threadId]*pow(dx,2.0));
	}
	atomicAdd(diff,abs(d_B[threadId]-d_A[threadId])/(blockDim.x*gridDim.x));
}

int main(int argc, char** argv)
{
	const int n = atoi(argv[1]);
	int steps = 0;
	const int BYTES = n*n * sizeof(float);
	float* h_A = new float[n*n];
	float* h_B = new float[n*n];
	float* h_F = new float[n*n];
	double dx = 0.1;

	for (int i = 0; i < n; i++)
	{
		for (int j = 0; j < n; j++)
		{
			h_A[n*i + j] = 0;
			h_B[n*i + j] = 0;
			h_F[n*i + j] = 0;

			if (j==0) h_A[n*i + j] = 1000;

			if (j==n-1) h_F[n*i + j] = 5*i+20;

			h_A[n*i + j]+=h_F[n*i + j];
		}
	}

	//declare GPU memory pointers
	float *d_A;
	float *d_B;
	float *d_F;
	float *diff;

	//allocate memory on the device
	cudaMalloc((void **) &d_A, BYTES);  
	cudaMalloc((void **) &d_B, BYTES);
	cudaMalloc((void **) &d_F, BYTES);
	cudaMallocManaged(&diff, sizeof(float));
	*diff = 0.0;

	//transfer the array to the GPU
	//destination, source, size, method
	cudaMemcpy(d_B, h_B, BYTES, cudaMemcpyHostToDevice);
	cudaMemcpy(d_A, h_A, BYTES, cudaMemcpyHostToDevice);
	cudaMemcpy(d_B, d_A, BYTES, cudaMemcpyDeviceToDevice);
	cudaMemcpy(d_F, h_F, BYTES, cudaMemcpyHostToDevice);

	//launch the kernel
	while (true)
	{
		steps++;
		*diff = 0.0;
		TwoDimPoisson<<<n,n>>>(d_A, d_B, d_F, dx, diff);
		cudaDeviceSynchronize();
		cudaMemcpy(h_A, d_A, BYTES, cudaMemcpyDeviceToHost);
		cudaMemcpy(h_B, d_B, BYTES, cudaMemcpyDeviceToHost);
		cudaMemcpy(d_A, d_B, BYTES, cudaMemcpyDeviceToDevice);
		if (*diff < 0.0001) break;
	}

	//copy the results back onto the device
	//destination, source, size, method
	cudaMemcpy(h_B, d_B, BYTES, cudaMemcpyDeviceToHost);

	for (int i = 0; i < n; i++)
	{
		for (int j = 0; j < n; j++)
		{
			printf("%-10.3f  ", h_B[i*n + j]);
		}
		printf("\n");
	}
	printf("\nSteps: %d \nn: %d\n",steps,n);

	//free memory previously allocated on the device 
	cudaFree(d_A);
	cudaFree(d_B);
	cudaFree(d_F);
}

	.file	"tmpxft_0033fea5_00000000-6_PoissonTwoDim.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2030:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z40__device_stub__Z13TwoDimPoissonPfS_S_dS_PfS_S_dS_
	.type	_Z40__device_stub__Z13TwoDimPoissonPfS_S_dS_PfS_S_dS_, @function
_Z40__device_stub__Z13TwoDimPoissonPfS_S_dS_PfS_S_dS_:
.LFB2052:
	.cfi_startproc
	endbr64
	subq	$168, %rsp
	.cfi_def_cfa_offset 176
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	48(%rsp), %rdx
	movq	%rcx, 8(%rsp)
	leaq	56(%rsp), %rcx
	movsd	%xmm0, 16(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 152(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 112(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 144(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	56(%rsp)
	.cfi_def_cfa_offset 184
	leaq	_Z13TwoDimPoissonPfS_S_dS_(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 192
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 184
	popq	%rdx
	.cfi_def_cfa_offset 176
.L2:
	movq	152(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$168, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2052:
	.size	_Z40__device_stub__Z13TwoDimPoissonPfS_S_dS_PfS_S_dS_, .-_Z40__device_stub__Z13TwoDimPoissonPfS_S_dS_PfS_S_dS_
	.globl	_Z13TwoDimPoissonPfS_S_dS_
	.type	_Z13TwoDimPoissonPfS_S_dS_, @function
_Z13TwoDimPoissonPfS_S_dS_:
.LFB2053:
	.cfi_startproc
	endbr64
	jmp	_Z40__device_stub__Z13TwoDimPoissonPfS_S_dS_PfS_S_dS_
	.cfi_endproc
.LFE2053:
	.size	_Z13TwoDimPoissonPfS_S_dS_, .-_Z13TwoDimPoissonPfS_S_dS_
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC4:
	.string	"%-10.3f  "
.LC5:
	.string	"\n"
.LC6:
	.string	"\nSteps: %d \nn: %d\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$88, %rsp
	.cfi_def_cfa_offset 144
	movq	8(%rsi), %rdi
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	xorl	%eax, %eax
	call	atoi@PLT
	movl	%eax, %r13d
	movl	%eax, %r12d
	imull	%eax, %r13d
	leal	0(,%r13,4), %ebp
	movslq	%r13d, %r13
	salq	$2, %r13
	movq	%r13, %rdi
	call	_Znam@PLT
	movq	%r13, %rdi
	movq	%rax, 8(%rsp)
	call	_Znam@PLT
	movq	%r13, %rdi
	movslq	%r12d, %r13
	movq	%rax, %rbx
	salq	$2, %r13
	call	_Znam@PLT
	xorl	%esi, %esi
	xorl	%edx, %edx
	movq	%rax, %r14
	leal	-1(%r12), %eax
	movq	%rax, %r10
	leaq	4(,%rax,4), %r9
	xorl	%eax, %eax
.L9:
	cmpl	%r12d, %edx
	jge	.L27
	leaq	(%rbx,%rsi), %r11
	leal	(%rdx,%rdx,4), %r8d
	movq	%r9, %rcx
	movq	%r11, %rdi
	addl	$20, %r8d
	rep stosb
	movq	%rsi, %rcx
	xorl	%edi, %edi
.L13:
	xorps	%xmm0, %xmm0
	testl	%edi, %edi
	jne	.L10
	movss	.LC1(%rip), %xmm0
.L10:
	cmpl	%edi, %r10d
	je	.L11
	movl	$0x00000000, (%r14,%rcx)
	jmp	.L12
.L11:
	cvtsi2ssl	%r8d, %xmm1
	movss	%xmm1, (%r14,%rcx)
.L12:
	addss	(%r14,%rcx), %xmm0
	movq	8(%rsp), %r11
	incl	%edi
	movss	%xmm0, (%r11,%rcx)
	addq	$4, %rcx
	cmpl	%edi, %r12d
	jne	.L13
	incl	%edx
	addq	%r13, %rsi
	jmp	.L9
.L27:
	movslq	%ebp, %rbp
	leaq	16(%rsp), %rdi
	movabsq	$4294967297, %r15
	movq	%rbp, %rsi
	call	cudaMalloc@PLT
	leaq	24(%rsp), %rdi
	movq	%rbp, %rsi
	call	cudaMalloc@PLT
	leaq	32(%rsp), %rdi
	movq	%rbp, %rsi
	call	cudaMalloc@PLT
	leaq	40(%rsp), %rdi
	movl	$1, %edx
	movl	$4, %esi
	call	cudaMallocManaged@PLT
	movq	40(%rsp), %rax
	movq	%rbp, %rdx
	movq	%rbx, %rsi
	movq	24(%rsp), %rdi
	movl	$1, %ecx
	movl	$0x00000000, (%rax)
	call	cudaMemcpy@PLT
	movq	8(%rsp), %rsi
	movq	16(%rsp), %rdi
	movq	%rbp, %rdx
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	movq	16(%rsp), %rsi
	movq	24(%rsp), %rdi
	movq	%rbp, %rdx
	movl	$3, %ecx
	call	cudaMemcpy@PLT
	movq	32(%rsp), %rdi
	movq	%r14, %rsi
	movq	%rbp, %rdx
	movl	$1, %ecx
	xorl	%r14d, %r14d
	call	cudaMemcpy@PLT
.L16:
	movq	40(%rsp), %rax
	movq	%r15, 64(%rsp)
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	%r15, 52(%rsp)
	movl	68(%rsp), %ecx
	incl	%r14d
	movl	$0x00000000, (%rax)
	movl	56(%rsp), %esi
	movl	%r12d, 60(%rsp)
	movq	60(%rsp), %rdx
	movl	%r12d, 48(%rsp)
	movq	48(%rsp), %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L15
	movq	40(%rsp), %rcx
	movsd	.LC2(%rip), %xmm0
	movq	32(%rsp), %rdx
	movq	24(%rsp), %rsi
	movq	16(%rsp), %rdi
	call	_Z40__device_stub__Z13TwoDimPoissonPfS_S_dS_PfS_S_dS_
.L15:
	call	cudaDeviceSynchronize@PLT
	movq	16(%rsp), %rsi
	movq	8(%rsp), %rdi
	movq	%rbp, %rdx
	movl	$2, %ecx
	call	cudaMemcpy@PLT
	movq	24(%rsp), %rsi
	movq	%rbp, %rdx
	movq	%rbx, %rdi
	movl	$2, %ecx
	call	cudaMemcpy@PLT
	movq	24(%rsp), %rsi
	movq	16(%rsp), %rdi
	movq	%rbp, %rdx
	movl	$3, %ecx
	call	cudaMemcpy@PLT
	movq	40(%rsp), %rax
	movsd	.LC3(%rip), %xmm1
	cvtss2sd	(%rax), %xmm0
	comisd	%xmm0, %xmm1
	jbe	.L16
	movq	24(%rsp), %rsi
	movq	%rbp, %rdx
	movl	$2, %ecx
	movq	%rbx, %rdi
	xorl	%ebp, %ebp
	call	cudaMemcpy@PLT
.L18:
	cmpl	%r12d, %ebp
	jge	.L28
	leaq	(%rbx,%r13), %r15
.L19:
	cvtss2sd	(%rbx), %xmm0
	leaq	.LC4(%rip), %rsi
	movl	$2, %edi
	movb	$1, %al
	call	__printf_chk@PLT
	addq	$4, %rbx
	cmpq	%r15, %rbx
	jne	.L19
	leaq	.LC5(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	incl	%ebp
	call	__printf_chk@PLT
	jmp	.L18
.L28:
	movl	%r12d, %ecx
	movl	%r14d, %edx
	leaq	.LC6(%rip), %rsi
	xorl	%eax, %eax
	movl	$2, %edi
	call	__printf_chk@PLT
	movq	16(%rsp), %rdi
	call	cudaFree@PLT
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	movq	32(%rsp), %rdi
	call	cudaFree@PLT
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L21
	call	__stack_chk_fail@PLT
.L21:
	addq	$88, %rsp
	.cfi_def_cfa_offset 56
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2027:
	.size	main, .-main
	.section	.rodata.str1.1
.LC7:
	.string	"_Z13TwoDimPoissonPfS_S_dS_"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC7(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z13TwoDimPoissonPfS_S_dS_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2055:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst4,"aM",@progbits,4
	.align 4
.LC1:
	.long	1148846080
	.section	.rodata.cst8,"aM",@progbits,8
	.align 8
.LC2:
	.long	-1717986918
	.long	1069128089
	.align 8
.LC3:
	.long	-350469331
	.long	1058682594
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <stdio.h>
#include <hip/hip_runtime.h>
#include <math.h>

__global__ void TwoDimPoisson(float *d_A, float *d_B, float *d_F, double dx, float* diff)
{
	int threadId = threadIdx.x + (blockIdx.x * blockDim.x);
	int threadAbove = threadId - blockDim.x;
	int threadBelow = threadId + blockDim.x;
	int N = gridDim.x * blockDim.x;

	// Punt if this thread is a boundary point
	if ((threadAbove <= 0) || (threadBelow >= N-1) ||
			(threadId % (blockDim.x) == 0) || 
			((threadId+1) % (blockDim.x) == 0))
		return;
	else
	{ 
		d_B[threadId] = (.25*(d_A[threadId+1] + d_A[threadId-1]
					+ d_A[threadAbove] + d_A[threadBelow])
				+ d_F[threadId]*pow(dx,2.0));
	}
	atomicAdd(diff,abs(d_B[threadId]-d_A[threadId])/(blockDim.x*gridDim.x));
}

int main(int argc, char** argv)
{
	const int n = atoi(argv[1]);
	int steps = 0;
	const int BYTES = n*n * sizeof(float);
	float* h_A = new float[n*n];
	float* h_B = new float[n*n];
	float* h_F = new float[n*n];
	double dx = 0.1;

	for (int i = 0; i < n; i++)
	{
		for (int j = 0; j < n; j++)
		{
			h_A[n*i + j] = 0;
			h_B[n*i + j] = 0;
			h_F[n*i + j] = 0;

			if (j==0) h_A[n*i + j] = 1000;

			if (j==n-1) h_F[n*i + j] = 5*i+20;

			h_A[n*i + j]+=h_F[n*i + j];
		}
	}

	//declare GPU memory pointers
	float *d_A;
	float *d_B;
	float *d_F;
	float *diff;

	//allocate memory on the device
	hipMalloc((void **) &d_A, BYTES);  
	hipMalloc((void **) &d_B, BYTES);
	hipMalloc((void **) &d_F, BYTES);
	hipMallocManaged(&diff, sizeof(float));
	*diff = 0.0;

	//transfer the array to the GPU
	//destination, source, size, method
	hipMemcpy(d_B, h_B, BYTES, hipMemcpyHostToDevice);
	hipMemcpy(d_A, h_A, BYTES, hipMemcpyHostToDevice);
	hipMemcpy(d_B, d_A, BYTES, hipMemcpyDeviceToDevice);
	hipMemcpy(d_F, h_F, BYTES, hipMemcpyHostToDevice);

	//launch the kernel
	while (true)
	{
		steps++;
		*diff = 0.0;
		TwoDimPoisson<<<n,n>>>(d_A, d_B, d_F, dx, diff);
		hipDeviceSynchronize();
		hipMemcpy(h_A, d_A, BYTES, hipMemcpyDeviceToHost);
		hipMemcpy(h_B, d_B, BYTES, hipMemcpyDeviceToHost);
		hipMemcpy(d_A, d_B, BYTES, hipMemcpyDeviceToDevice);
		if (*diff < 0.0001) break;
	}

	//copy the results back onto the device
	//destination, source, size, method
	hipMemcpy(h_B, d_B, BYTES, hipMemcpyDeviceToHost);

	for (int i = 0; i < n; i++)
	{
		for (int j = 0; j < n; j++)
		{
			printf("%-10.3f  ", h_B[i*n + j]);
		}
		printf("\n");
	}
	printf("\nSteps: %d \nn: %d\n",steps,n);

	//free memory previously allocated on the device 
	hipFree(d_A);
	hipFree(d_B);
	hipFree(d_F);
}

	.text
	.file	"PoissonTwoDim.hip"
	.globl	_Z28__device_stub__TwoDimPoissonPfS_S_dS_ # -- Begin function _Z28__device_stub__TwoDimPoissonPfS_S_dS_
	.type	_Z28__device_stub__TwoDimPoissonPfS_S_dS_,@function
_Z28__device_stub__TwoDimPoissonPfS_S_dS_: # @_Z28__device_stub__TwoDimPoissonPfS_S_dS_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movsd	%xmm0, (%rdx)
	leaq	24(%rsp), %r8
	movq	%rcx, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%r8, 32(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z13TwoDimPoissonPfS_S_dS_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z28__device_stub__TwoDimPoissonPfS_S_dS_, .Lfunc_end0-_Z28__device_stub__TwoDimPoissonPfS_S_dS_
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0                          # -- Begin function main
.LCPI1_0:
	.long	0x447a0000                      # float 1000
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0
.LCPI1_1:
	.quad	0x3fb999999999999a              # double 0.10000000000000001
.LCPI1_2:
	.quad	0x3f1a36e2eb1c432d              # double 1.0E-4
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$88, %rsp
	.cfi_def_cfa_offset 144
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	8(%rsi), %rdi
	callq	atoi
	movl	%eax, %ebx
	imull	%eax, %eax
	leaq	(,%rax,4), %r12
	movl	%eax, %r15d
	shll	$2, %r15d
	movq	%r12, %rdi
	callq	_Znam
	movq	%rax, %r14
	movq	%r12, %rdi
	callq	_Znam
	movq	%rax, 8(%rsp)                   # 8-byte Spill
	movq	%r12, %rdi
	callq	_Znam
	movq	%rbx, %rcx
	movq	%rax, 56(%rsp)                  # 8-byte Spill
	testl	%ecx, %ecx
	movq	%rbx, 32(%rsp)                  # 8-byte Spill
	jle	.LBB1_1
# %bb.12:                               # %.preheader90.lr.ph
	movl	%r15d, 48(%rsp)                 # 4-byte Spill
	leal	-1(%rcx), %ebx
	movl	%ecx, %ebp
	leaq	(,%rbp,4), %rax
	movq	%rax, 72(%rsp)                  # 8-byte Spill
	xorl	%r12d, %r12d
	xorl	%r15d, %r15d
	movq	%r14, 80(%rsp)                  # 8-byte Spill
.LBB1_13:                               # %.lr.ph
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB1_14 Depth 2
	movl	%r12d, %eax
	movq	56(%rsp), %rdx                  # 8-byte Reload
	leaq	(%rdx,%rax,4), %r13
	leaq	(%r14,%rax,4), %r14
	movl	%ecx, %eax
	imull	%r15d, %eax
	movq	8(%rsp), %rcx                   # 8-byte Reload
	leaq	(%rcx,%rax,4), %rdi
	leal	(%r15,%r15,4), %eax
	addl	$20, %eax
	xorps	%xmm0, %xmm0
	cvtsi2ss	%eax, %xmm0
	movss	%xmm0, 52(%rsp)                 # 4-byte Spill
	xorl	%esi, %esi
	movq	72(%rsp), %rdx                  # 8-byte Reload
	callq	memset@PLT
	movss	.LCPI1_0(%rip), %xmm2           # xmm2 = mem[0],zero,zero,zero
	xorl	%eax, %eax
.LBB1_14:                               #   Parent Loop BB1_13 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movaps	%xmm2, %xmm0
	testq	%rax, %rax
	je	.LBB1_16
# %bb.15:                               #   in Loop: Header=BB1_14 Depth=2
	xorps	%xmm0, %xmm0
.LBB1_16:                               #   in Loop: Header=BB1_14 Depth=2
	movss	52(%rsp), %xmm1                 # 4-byte Reload
                                        # xmm1 = mem[0],zero,zero,zero
	cmpq	%rax, %rbx
	je	.LBB1_18
# %bb.17:                               #   in Loop: Header=BB1_14 Depth=2
	xorps	%xmm1, %xmm1
.LBB1_18:                               #   in Loop: Header=BB1_14 Depth=2
	movss	%xmm1, (%r13,%rax,4)
	addss	%xmm1, %xmm0
	movss	%xmm0, (%r14,%rax,4)
	incq	%rax
	cmpq	%rax, %rbp
	jne	.LBB1_14
# %bb.19:                               # %._crit_edge
                                        #   in Loop: Header=BB1_13 Depth=1
	incq	%r15
	movq	32(%rsp), %rcx                  # 8-byte Reload
	addl	%ecx, %r12d
	cmpq	%rbp, %r15
	movq	80(%rsp), %r14                  # 8-byte Reload
	jne	.LBB1_13
# %bb.20:
	movl	48(%rsp), %r15d                 # 4-byte Reload
	jmp	.LBB1_2
.LBB1_1:                                # %.._crit_edge93_crit_edge
	movl	%ecx, %ebp
.LBB1_2:                                # %._crit_edge93
	movslq	%r15d, %r13
	leaq	24(%rsp), %r12
	movq	%r12, %rdi
	movq	%r13, %rsi
	callq	hipMalloc
	leaq	16(%rsp), %rbx
	movq	%rbx, %rdi
	movq	%r13, %rsi
	callq	hipMalloc
	leaq	40(%rsp), %rdi
	movq	%r13, %rsi
	callq	hipMalloc
	leaq	64(%rsp), %r15
	movl	$4, %esi
	movq	%r15, %rdi
	movl	$1, %edx
	callq	hipMallocManaged
	movq	(%r15), %rax
	movl	$0, (%rax)
	movq	(%rbx), %rdi
	movq	8(%rsp), %rsi                   # 8-byte Reload
	movq	%r13, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%r12), %rdi
	movq	%r14, %rsi
	movq	%r13, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%rbx), %rdi
	movq	(%r12), %rsi
	movq	%r13, %rdx
	movl	$3, %ecx
	callq	hipMemcpy
	leaq	40(%rsp), %rax
	movq	(%rax), %rdi
	movq	56(%rsp), %rsi                  # 8-byte Reload
	movq	%r13, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	movq	%rbp, %rbx
	btsq	$32, %rbx
	xorl	%r12d, %r12d
	movq	(%r15), %rax
.LBB1_3:                                # =>This Inner Loop Header: Depth=1
	movl	$0, (%rax)
	movq	%rbx, %rdi
	movl	$1, %esi
	movq	%rbx, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_5
# %bb.4:                                #   in Loop: Header=BB1_3 Depth=1
	movq	24(%rsp), %rdi
	movq	16(%rsp), %rsi
	movq	40(%rsp), %rdx
	movq	64(%rsp), %rcx
	movsd	.LCPI1_1(%rip), %xmm0           # xmm0 = mem[0],zero
	callq	_Z28__device_stub__TwoDimPoissonPfS_S_dS_
.LBB1_5:                                #   in Loop: Header=BB1_3 Depth=1
	callq	hipDeviceSynchronize
	movq	24(%rsp), %rsi
	movq	%r14, %rdi
	movq	%r13, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	movq	16(%rsp), %rsi
	movq	8(%rsp), %rdi                   # 8-byte Reload
	movq	%r13, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	movq	24(%rsp), %rdi
	movq	16(%rsp), %rsi
	movq	%r13, %rdx
	movl	$3, %ecx
	callq	hipMemcpy
	movq	64(%rsp), %rax
	xorps	%xmm0, %xmm0
	cvtss2sd	(%rax), %xmm0
	incl	%r12d
	movsd	.LCPI1_2(%rip), %xmm1           # xmm1 = mem[0],zero
	ucomisd	%xmm0, %xmm1
	jbe	.LBB1_3
# %bb.6:
	movq	16(%rsp), %rsi
	movq	8(%rsp), %rdi                   # 8-byte Reload
	movq	%r13, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	movq	32(%rsp), %rdx                  # 8-byte Reload
	testl	%edx, %edx
	jle	.LBB1_11
# %bb.7:                                # %.lr.ph95.preheader
	xorl	%ebx, %ebx
	xorl	%r14d, %r14d
.LBB1_8:                                # %.lr.ph95
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB1_9 Depth 2
	movl	%ebx, %eax
	movq	8(%rsp), %rcx                   # 8-byte Reload
	leaq	(%rcx,%rax,4), %r15
	xorl	%r13d, %r13d
.LBB1_9:                                #   Parent Loop BB1_8 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	xorps	%xmm0, %xmm0
	cvtss2sd	(%r15,%r13,4), %xmm0
	movl	$.L.str, %edi
	movb	$1, %al
	callq	printf
	incq	%r13
	cmpq	%r13, %rbp
	jne	.LBB1_9
# %bb.10:                               # %._crit_edge96
                                        #   in Loop: Header=BB1_8 Depth=1
	movl	$10, %edi
	callq	putchar@PLT
	incq	%r14
	movq	32(%rsp), %rdx                  # 8-byte Reload
	addl	%edx, %ebx
	cmpq	%rbp, %r14
	jne	.LBB1_8
.LBB1_11:                               # %._crit_edge98
	movl	$.L.str.2, %edi
	movl	%r12d, %esi
                                        # kill: def $edx killed $edx killed $rdx
	xorl	%eax, %eax
	callq	printf
	movq	24(%rsp), %rdi
	callq	hipFree
	movq	16(%rsp), %rdi
	callq	hipFree
	movq	40(%rsp), %rdi
	callq	hipFree
	xorl	%eax, %eax
	addq	$88, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	main, .Lfunc_end1-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z13TwoDimPoissonPfS_S_dS_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z13TwoDimPoissonPfS_S_dS_,@object # @_Z13TwoDimPoissonPfS_S_dS_
	.section	.rodata,"a",@progbits
	.globl	_Z13TwoDimPoissonPfS_S_dS_
	.p2align	3, 0x0
_Z13TwoDimPoissonPfS_S_dS_:
	.quad	_Z28__device_stub__TwoDimPoissonPfS_S_dS_
	.size	_Z13TwoDimPoissonPfS_S_dS_, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"%-10.3f  "
	.size	.L.str, 10

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"\nSteps: %d \nn: %d\n"
	.size	.L.str.2, 19

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z13TwoDimPoissonPfS_S_dS_"
	.size	.L__unnamed_1, 27

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z28__device_stub__TwoDimPoissonPfS_S_dS_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z13TwoDimPoissonPfS_S_dS_
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z13TwoDimPoissonPfS_S_dS_ ; -- Begin function _Z13TwoDimPoissonPfS_S_dS_
	.globl	_Z13TwoDimPoissonPfS_S_dS_
	.p2align	8
	.type	_Z13TwoDimPoissonPfS_S_dS_,@function
_Z13TwoDimPoissonPfS_S_dS_:             ; @_Z13TwoDimPoissonPfS_S_dS_
; %bb.0:
	s_load_b32 s4, s[0:1], 0x34
	s_add_u32 s2, s0, 40
	s_addc_u32 s3, s1, 0
	s_mov_b32 s5, exec_lo
	s_waitcnt lgkmcnt(0)
	s_and_b32 s4, s4, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
	v_subrev_nc_u32_e32 v0, s4, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e32 0, v0
	s_cbranch_execz .LBB0_9
; %bb.1:
	s_load_b32 s14, s[2:3], 0x0
	v_add_nc_u32_e32 v3, s4, v1
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s14, s14, s4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_i32 s2, s14, -1
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_cmp_gt_i32_e32 vcc_lo, s2, v3
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_9
; %bb.2:
	v_cvt_f32_u32_e32 v2, s4
	s_sub_i32 s2, 0, s4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v2, v2
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v2, 0x4f7ffffe, v2
	v_cvt_u32_f32_e32 v2, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v4, s2, v2
	v_mul_hi_u32 v4, v2, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v2, v2, v4
	v_mul_hi_u32 v4, v1, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v4, v4, s4
	v_sub_nc_u32_e32 v4, v1, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v5, s4, v4
	v_cmp_le_u32_e32 vcc_lo, s4, v4
	v_cndmask_b32_e32 v4, v4, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v5, s4, v4
	v_cmp_le_u32_e32 vcc_lo, s4, v4
	v_cndmask_b32_e32 v4, v4, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, 0, v4
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_9
; %bb.3:
	v_add_nc_u32_e32 v4, 1, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v2, v4, v2
	v_mul_lo_u32 v2, v2, s4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v2, v4, v2
	v_subrev_nc_u32_e32 v4, s4, v2
	v_cmp_le_u32_e32 vcc_lo, s4, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v2, v2, v4, vcc_lo
	v_subrev_nc_u32_e32 v4, s4, v2
	v_cmp_le_u32_e32 vcc_lo, s4, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v2, v2, v4, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, 0, v2
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_9
; %bb.4:
	s_load_b256 s[4:11], s[0:1], 0x0
	s_mov_b32 s3, 0x3fe55555
	s_mov_b32 s2, 0x55555555
	s_mov_b32 s12, 0x968915a9
	s_mov_b32 s16, 0x4222de17
	s_mov_b32 s13, 0x3fba6564
	s_mov_b32 s17, 0x3fbdee67
	s_mov_b32 s18, 0x652b82fe
	s_mov_b32 s19, 0x3ff71547
	s_load_b64 s[0:1], s[0:1], 0x20
	s_mov_b32 s15, exec_lo
	s_waitcnt lgkmcnt(0)
	v_frexp_mant_f64_e64 v[4:5], |s[10:11]|
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_gt_f64_e32 vcc_lo, s[2:3], v[4:5]
	v_cndmask_b32_e64 v2, 0, 1, vcc_lo
	v_ldexp_f64 v[4:5], v[4:5], v2
	v_frexp_exp_i32_f64_e32 v2, s[10:11]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[6:7], v[4:5], 1.0
	v_add_f64 v[12:13], v[4:5], -1.0
	v_subrev_co_ci_u32_e32 v2, vcc_lo, 0, v2, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[8:9], v[6:7]
	v_add_f64 v[14:15], v[6:7], -1.0
	v_add_f64 v[4:5], v[4:5], -v[14:15]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[10:11], -v[6:7], v[8:9], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[8:9], v[10:11], v[8:9], v[8:9]
	v_fma_f64 v[10:11], -v[6:7], v[8:9], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[8:9], v[10:11], v[8:9], v[8:9]
	v_mul_f64 v[10:11], v[12:13], v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[16:17], v[6:7], v[10:11]
	v_fma_f64 v[6:7], v[10:11], v[6:7], -v[16:17]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[4:5], v[10:11], v[4:5], v[6:7]
	v_add_f64 v[6:7], v[16:17], v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[14:15], v[12:13], -v[6:7]
	v_add_f64 v[16:17], v[6:7], -v[16:17]
	v_add_f64 v[12:13], v[12:13], -v[14:15]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[4:5], v[16:17], -v[4:5]
	v_add_f64 v[6:7], v[12:13], -v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[4:5], v[4:5], v[6:7]
	v_add_f64 v[4:5], v[14:15], v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[4:5], v[8:9], v[4:5]
	v_add_f64 v[6:7], v[10:11], v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[8:9], v[6:7], -v[10:11]
	v_mul_f64 v[10:11], v[6:7], v[6:7]
	v_add_f64 v[4:5], v[4:5], -v[8:9]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[8:9], v[6:7], v[6:7], -v[10:11]
	v_add_f64 v[12:13], v[4:5], v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[8:9], v[6:7], v[12:13], v[8:9]
	v_add_f64 v[12:13], v[10:11], v[8:9]
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[14:15], v[12:13], s[16:17], s[12:13]
	s_mov_b32 s12, 0x3abe935a
	s_mov_b32 s13, 0x3fbe25e4
	v_add_f64 v[10:11], v[12:13], -v[10:11]
	v_mul_f64 v[20:21], v[6:7], v[12:13]
	s_mov_b32 s17, 0x3c7abc9e
	s_mov_b32 s16, 0x3b39803f
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_fma_f64 v[14:15], v[12:13], v[14:15], s[12:13]
	s_mov_b32 s12, 0x47e6c9c2
	s_mov_b32 s13, 0x3fc110ef
	v_add_f64 v[8:9], v[8:9], -v[10:11]
	s_delay_alu instid0(VALU_DEP_2)
	v_fma_f64 v[14:15], v[12:13], v[14:15], s[12:13]
	s_mov_b32 s12, 0xcfa74449
	s_mov_b32 s13, 0x3fc3b13b
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[14:15], v[12:13], v[14:15], s[12:13]
	s_mov_b32 s12, 0x71bf3c30
	s_mov_b32 s13, 0x3fc745d1
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[14:15], v[12:13], v[14:15], s[12:13]
	s_mov_b32 s12, 0x1c7792ce
	s_mov_b32 s13, 0x3fcc71c7
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[14:15], v[12:13], v[14:15], s[12:13]
	s_mov_b32 s12, 0x924920da
	s_mov_b32 s13, 0x3fd24924
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[14:15], v[12:13], v[14:15], s[12:13]
	s_mov_b32 s12, 0x9999999c
	s_mov_b32 s13, 0x3fd99999
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[14:15], v[12:13], v[14:15], s[12:13]
	s_mov_b32 s12, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[16:17], v[12:13], v[14:15]
	v_fma_f64 v[10:11], v[12:13], v[14:15], -v[16:17]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[10:11], v[8:9], v[14:15], v[10:11]
	v_add_f64 v[14:15], v[16:17], v[10:11]
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[18:19], v[14:15], s[2:3]
	v_add_f64 v[16:17], v[14:15], -v[16:17]
	s_mov_b32 s3, 0xbfe55555
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	v_add_f64 v[22:23], v[18:19], s[2:3]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_add_f64 v[10:11], v[10:11], -v[16:17]
	v_fma_f64 v[16:17], v[12:13], v[6:7], -v[20:21]
	s_mov_b32 s2, 0xd5df274d
	s_mov_b32 s3, 0x3c8543b0
	v_add_f64 v[14:15], v[14:15], -v[22:23]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[10:11], v[10:11], s[2:3]
	v_fma_f64 v[12:13], v[12:13], v[4:5], v[16:17]
	s_mov_b32 s3, 0x3fe62e42
	s_mov_b32 s2, 0xfefa39ef
	v_ldexp_f64 v[4:5], v[4:5], 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[10:11], v[10:11], v[14:15]
	v_fma_f64 v[8:9], v[8:9], v[6:7], v[12:13]
	v_ldexp_f64 v[6:7], v[6:7], 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[12:13], v[18:19], v[10:11]
	v_add_f64 v[14:15], v[20:21], v[8:9]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[16:17], v[18:19], -v[12:13]
	v_mul_f64 v[18:19], v[14:15], v[12:13]
	v_add_f64 v[20:21], v[14:15], -v[20:21]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[10:11], v[10:11], v[16:17]
	v_fma_f64 v[16:17], v[14:15], v[12:13], -v[18:19]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[8:9], v[8:9], -v[20:21]
	v_fma_f64 v[10:11], v[14:15], v[10:11], v[16:17]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_fma_f64 v[8:9], v[8:9], v[12:13], v[10:11]
	v_cvt_f64_i32_e32 v[12:13], v2
	v_ashrrev_i32_e32 v2, 31, v1
	v_add_f64 v[10:11], v[18:19], v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_add_f64 v[14:15], v[6:7], v[10:11]
	v_add_f64 v[16:17], v[10:11], -v[18:19]
	v_mul_f64 v[18:19], v[12:13], s[2:3]
	v_add_f64 v[6:7], v[14:15], -v[6:7]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[8:9], v[8:9], -v[16:17]
	v_fma_f64 v[16:17], v[12:13], s[2:3], -v[18:19]
	v_cmp_eq_f64_e64 s3, s[10:11], 1.0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[6:7], v[10:11], -v[6:7]
	v_add_f64 v[4:5], v[4:5], v[8:9]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[8:9], v[12:13], s[16:17], v[16:17]
	s_and_b32 s3, s3, exec_lo
	s_cselect_b32 s13, 0x3ff00000, 2.0
	s_mov_b32 s3, 0xbfe62e42
	s_mov_b32 s17, 0xbc7abc9e
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[4:5], v[4:5], v[6:7]
	v_add_f64 v[6:7], v[18:19], v[8:9]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[10:11], v[14:15], v[4:5]
	v_add_f64 v[18:19], v[6:7], -v[18:19]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[12:13], v[6:7], v[10:11]
	v_add_f64 v[14:15], v[10:11], -v[14:15]
	v_add_f64 v[8:9], v[8:9], -v[18:19]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[16:17], v[12:13], -v[6:7]
	v_add_f64 v[4:5], v[4:5], -v[14:15]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[20:21], v[12:13], -v[16:17]
	v_add_f64 v[10:11], v[10:11], -v[16:17]
	v_add_f64 v[14:15], v[8:9], v[4:5]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_f64 v[6:7], v[6:7], -v[20:21]
	v_lshlrev_b64 v[20:21], 2, v[1:2]
	v_mov_b32_e32 v1, 0
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[6:7], v[10:11], v[6:7]
	v_add_f64 v[10:11], v[14:15], -v[8:9]
	v_add_f64 v[6:7], v[14:15], v[6:7]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[14:15], v[14:15], -v[10:11]
	v_add_f64 v[4:5], v[4:5], -v[10:11]
	v_add_f64 v[16:17], v[12:13], v[6:7]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[8:9], v[8:9], -v[14:15]
	v_add_f64 v[10:11], v[16:17], -v[12:13]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[4:5], v[4:5], v[8:9]
	v_add_f64 v[6:7], v[6:7], -v[10:11]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[4:5], v[4:5], v[6:7]
	v_add_f64 v[6:7], v[16:17], v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[8:9], v[6:7], -v[16:17]
	v_mul_f64 v[10:11], s[12:13], v[6:7]
	v_add_f64 v[4:5], v[4:5], -v[8:9]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f64 v[6:7], s[12:13], v[6:7], -v[10:11]
	v_cmp_class_f64_e64 vcc_lo, v[10:11], 0x204
	v_fma_f64 v[5:6], s[12:13], v[4:5], v[6:7]
	v_ashrrev_i32_e32 v4, 31, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[2:3], 2, v[3:4]
	v_add_f64 v[7:8], v[10:11], v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v13, v8, v11 :: v_dual_cndmask_b32 v12, v7, v10
	v_add_co_u32 v22, vcc_lo, s8, v20
	v_add_co_ci_u32_e32 v23, vcc_lo, s9, v21, vcc_lo
	v_mul_f64 v[14:15], v[12:13], s[18:19]
	v_add_co_u32 v0, vcc_lo, s4, v0
	global_load_b32 v24, v[22:23], off
	v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
	v_add_co_u32 v2, vcc_lo, s4, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
	v_add_co_u32 v22, vcc_lo, s4, v20
	v_add_co_ci_u32_e32 v23, vcc_lo, s5, v21, vcc_lo
	s_clause 0x3
	global_load_b32 v25, v[0:1], off
	global_load_b32 v26, v[2:3], off
	global_load_b32 v27, v[22:23], off offset:4
	global_load_b32 v28, v[22:23], off offset:-4
	v_cmp_nlt_f64_e32 vcc_lo, 0x40900000, v[12:13]
	v_rndne_f64_e32 v[14:15], v[14:15]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_fma_f64 v[16:17], v[14:15], s[2:3], v[12:13]
	s_mov_b32 s2, 0xfca7ab0c
	s_mov_b32 s3, 0x3e928af3
	v_cvt_i32_f64_e32 v2, v[14:15]
	v_fma_f64 v[16:17], v[14:15], s[16:17], v[16:17]
	s_mov_b32 s16, 0x6a5dcb37
	s_mov_b32 s17, 0x3e5ade15
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[18:19], v[16:17], s[16:17], s[2:3]
	s_mov_b32 s2, 0x623fde64
	s_mov_b32 s3, 0x3ec71dee
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[18:19], v[16:17], v[18:19], s[2:3]
	s_mov_b32 s2, 0x7c89e6b0
	s_mov_b32 s3, 0x3efa0199
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[18:19], v[16:17], v[18:19], s[2:3]
	s_mov_b32 s2, 0x14761f6e
	s_mov_b32 s3, 0x3f2a01a0
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[18:19], v[16:17], v[18:19], s[2:3]
	s_mov_b32 s2, 0x1852b7b0
	s_mov_b32 s3, 0x3f56c16c
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[18:19], v[16:17], v[18:19], s[2:3]
	s_mov_b32 s2, 0x11122322
	s_mov_b32 s3, 0x3f811111
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[18:19], v[16:17], v[18:19], s[2:3]
	s_mov_b32 s2, 0x555502a1
	s_mov_b32 s3, 0x3fa55555
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[18:19], v[16:17], v[18:19], s[2:3]
	s_mov_b32 s2, 0x55555511
	s_mov_b32 s3, 0x3fc55555
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[18:19], v[16:17], v[18:19], s[2:3]
	s_mov_b32 s2, 11
	s_mov_b32 s3, 0x3fe00000
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[18:19], v[16:17], v[18:19], s[2:3]
	v_cmp_ngt_f64_e64 s2, 0xc090cc00, v[12:13]
	v_cmp_neq_f64_e64 s3, 0x7ff00000, |v[12:13]|
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[0:1], v[16:17], v[18:19], 1.0
	v_fma_f64 v[0:1], v[16:17], v[0:1], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_ldexp_f64 v[0:1], v[0:1], v2
	v_add_f64 v[2:3], v[7:8], -v[10:11]
	v_mul_f64 v[7:8], s[12:13], 0.5
	v_cndmask_b32_e32 v9, 0x7ff00000, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f64 v[1:2], v[5:6], -v[2:3]
	v_trunc_f64_e32 v[3:4], s[12:13]
	v_trunc_f64_e32 v[5:6], v[7:8]
	v_readfirstlane_b32 s4, v0
	v_cndmask_b32_e64 v10, 0, v9, s2
	s_and_b32 s2, s2, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	s_and_b32 s2, s2, exec_lo
	s_cselect_b32 s4, s4, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v9, s4
	v_cmp_class_f64_e64 vcc_lo, v[9:10], 0x204
	v_cndmask_b32_e64 v2, 0, v2, s3
	v_cndmask_b32_e64 v1, 0, v1, s3
	v_cmp_eq_f64_e64 s2, s[12:13], v[3:4]
	v_cmp_neq_f64_e64 s3, v[5:6], v[7:8]
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v3, v27, v28
	v_fma_f64 v[0:1], v[9:10], v[1:2], v[9:10]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v4, v3, v25
	v_add_f32_e32 v4, v4, v26
	s_and_b32 s8, vcc_lo, exec_lo
	v_cmp_eq_f64_e64 s8, s[10:11], 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_cvt_f64_f32_e32 v[4:5], v4
	v_readfirstlane_b32 s5, v0
	v_cndmask_b32_e32 v0, v1, v10, vcc_lo
	v_cmp_lt_f64_e64 vcc_lo, s[10:11], 0
	s_cselect_b32 s4, s4, s5
	s_and_b32 s3, s2, s3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_and_b32 s5, s3, exec_lo
	s_cselect_b32 s5, s11, 0x3ff00000
	v_bfi_b32 v0, 0x7fffffff, v0, s5
	v_cmp_class_f64_e64 s5, s[10:11], 0x204
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v1, 0x7ff80000, v0, s2
	s_and_b32 s2, s2, exec_lo
	s_cselect_b32 s2, s4, 0
	s_and_b32 s9, vcc_lo, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v0, v0, v1, vcc_lo
	s_cselect_b32 s4, s2, s4
	s_or_b32 vcc_lo, s8, s5
	s_and_b32 s2, s8, exec_lo
	s_cselect_b32 s2, 0, 0x7ff00000
	s_and_b32 s3, s3, exec_lo
	s_cselect_b32 s3, s11, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v1, s3
	s_and_b32 s3, vcc_lo, exec_lo
	s_cselect_b32 s3, 0, s4
	v_bfi_b32 v1, 0x7fffffff, s2, v1
	v_cmp_o_f64_e64 s2, s[10:11], s[10:11]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v2, v0, v1, vcc_lo
	v_cvt_f64_f32_e32 v[0:1], v24
	v_cndmask_b32_e64 v3, 0x7ff80000, v2, s2
	s_and_b32 s2, s2, exec_lo
	s_cselect_b32 s2, s3, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v2, s2
	v_mul_f64 v[0:1], v[2:3], v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[0:1], 0x3fd00000, v[4:5], v[0:1]
	v_cvt_f32_f64_e32 v2, v[0:1]
	v_add_co_u32 v0, vcc_lo, s6, v20
	v_add_co_ci_u32_e32 v1, vcc_lo, s7, v21, vcc_lo
	global_store_b32 v[0:1], v2, off
	global_load_b32 v0, v[22:23], off
	v_cvt_f32_u32_e32 v1, s14
	s_waitcnt vmcnt(0)
	v_sub_f32_e32 v0, v2, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v2, 0x7fffffff, v0
	v_div_scale_f32 v3, null, v1, v1, v2
	v_div_scale_f32 v2, vcc_lo, v2, v1, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v4, v3
	s_waitcnt_depctr 0xfff
	v_fma_f32 v5, -v3, v4, 1.0
	v_fmac_f32_e32 v4, v5, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v5, v2, v4
	v_fma_f32 v6, -v3, v5, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v5, v6, v4
	v_fma_f32 v2, -v3, v5, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v2, v2, v4, v5
	v_div_fixup_f32 v0, v2, v1, |v0|
	v_bfrev_b32_e32 v2, 1
.LBB0_5:                                ; %ComputeLoop
                                        ; =>This Inner Loop Header: Depth=1
	s_ctz_i32_b32 s2, s15
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	v_readlane_b32 s3, v0, s2
	s_lshl_b32 s2, 1, s2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_not1_b32 s15, s15, s2
	s_cmp_lg_u32 s15, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f32_e32 v2, s3, v2
	s_cbranch_scc1 .LBB0_5
; %bb.6:                                ; %ComputeEnd
	v_mbcnt_lo_u32_b32 v0, exec_lo, 0
	s_mov_b32 s2, 0
	s_mov_b32 s3, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v0
	s_xor_b32 s3, exec_lo, s3
	s_cbranch_execz .LBB0_9
; %bb.7:
	v_mov_b32_e32 v3, 0
	global_load_b32 v1, v3, s[0:1]
.LBB0_8:                                ; %atomicrmw.start
                                        ; =>This Inner Loop Header: Depth=1
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v0, v1, v2
	global_atomic_cmpswap_b32 v0, v3, v[0:1], s[0:1] glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u32_e32 vcc_lo, v0, v1
	v_mov_b32_e32 v1, v0
	s_or_b32 s2, vcc_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s2
	s_cbranch_execnz .LBB0_8
.LBB0_9:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z13TwoDimPoissonPfS_S_dS_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 29
		.amdhsa_next_free_sgpr 20
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z13TwoDimPoissonPfS_S_dS_, .Lfunc_end0-_Z13TwoDimPoissonPfS_S_dS_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 2932
; NumSgprs: 22
; NumVgprs: 29
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 3
; NumSGPRsForWavesPerEU: 22
; NumVGPRsForWavesPerEU: 29
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           8
        .value_kind:     by_value
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         44
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         52
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         54
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         56
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         58
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         60
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         62
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         104
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 296
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z13TwoDimPoissonPfS_S_dS_
    .private_segment_fixed_size: 0
    .sgpr_count:     22
    .sgpr_spill_count: 0
    .symbol:         _Z13TwoDimPoissonPfS_S_dS_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     29
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
