
/*
    Kernel to do temperature update in explicit finite difference
    solution to 3-D heat equation. Works for a block size of 16 x 16.
    Make copies for other block sizes. Can be easily extended to 
    arbitrary sized stencils.
*/


# include <stdio.h>
# include <cuda.h>

__global__ void temperature_update16x16(float* temp1_d, float* temp2_d, float alpha, 
                    float dt, 
                    const int N_x, const int N_y, const int N_z,
                    const float dx, const float dy, const float dz){


#define BDIMX 16
#define BDIMY 16

__shared__ float slice[BDIMX+2][BDIMY+2];

int ix = blockIdx.x*blockDim.x + threadIdx.x;
int iy = blockIdx.y*blockDim.y + threadIdx.y;

int tx = threadIdx.x + 1;
int ty = threadIdx.y + 1;

int stride = N_x*N_y;
int i2d = iy*N_x + ix;
int o2d = 0;
bool compute_if = ix > 0 && ix < (N_x-1) && iy > 0 && iy < (N_y-1);


float behind;
float current = temp1_d[i2d]; o2d = i2d; i2d += stride;
float infront = temp1_d[i2d]; i2d += stride;

for(int i=1; i<N_z-1; i++){

    // These go in registers:
    behind = current;
    current= infront;
    infront= temp1_d[i2d];

    i2d += stride;
    o2d += stride;
    __syncthreads();

    // Shared memory

    if (compute_if){
        if(threadIdx.x == 0){ // Halo left
            slice[ty][tx-1]     =   temp1_d[o2d - 1];
        }

        if(threadIdx.x == BDIMX-1){ // Halo right
            slice[ty][tx+1]     =   temp1_d[o2d + 1];
        }

        if(threadIdx.y == 0){ // Halo bottom
            slice[ty-1][tx]     =   temp1_d[o2d - N_x];
        }

        if(threadIdx.y == BDIMY-1){ // Halo top
            slice[ty+1][tx]     =   temp1_d[o2d + N_x];
        }
    }

    __syncthreads();

    slice[ty][tx] = current;

    __syncthreads();

    if (compute_if){
        
        temp2_d[o2d]  = current + (alpha*dt)*(
                        (slice[ty][tx-1] - 2*slice[ty][tx]
                        +slice[ty][tx+1])/(dx*dx) +
                        (slice[ty-1][tx] - 2*slice[ty][tx]
                        +slice[ty+1][tx])/(dy*dy) +
                        (behind - 2*current + infront)/(dz*dz));

    }

    __syncthreads();

}

}


	.file	"tmpxft_002cf2f2_00000000-6_3D_heat_kernel.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2029:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z53__device_stub__Z23temperature_update16x16PfS_ffiiifffPfS_ffiiifff
	.type	_Z53__device_stub__Z23temperature_update16x16PfS_ffiiifffPfS_ffiiifff, @function
_Z53__device_stub__Z23temperature_update16x16PfS_ffiiifffPfS_ffiiifff:
.LFB2051:
	.cfi_startproc
	endbr64
	subq	$216, %rsp
	.cfi_def_cfa_offset 224
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movl	%edx, 20(%rsp)
	leaq	56(%rsp), %rdx
	movl	%ecx, 16(%rsp)
	leaq	64(%rsp), %rcx
	movl	%r8d, 12(%rsp)
	movss	%xmm0, 28(%rsp)
	movss	%xmm1, 24(%rsp)
	movss	%xmm2, 8(%rsp)
	movss	%xmm3, 4(%rsp)
	movss	%xmm4, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 200(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	28(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 184(%rsp)
	movq	%rsp, %rax
	movq	%rax, 192(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	64(%rsp)
	.cfi_def_cfa_offset 232
	leaq	_Z23temperature_update16x16PfS_ffiiifff(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 240
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 232
	popq	%rdx
	.cfi_def_cfa_offset 224
.L2:
	movq	200(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$216, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2051:
	.size	_Z53__device_stub__Z23temperature_update16x16PfS_ffiiifffPfS_ffiiifff, .-_Z53__device_stub__Z23temperature_update16x16PfS_ffiiifffPfS_ffiiifff
	.globl	_Z23temperature_update16x16PfS_ffiiifff
	.type	_Z23temperature_update16x16PfS_ffiiifff, @function
_Z23temperature_update16x16PfS_ffiiifff:
.LFB2052:
	.cfi_startproc
	endbr64
	jmp	_Z53__device_stub__Z23temperature_update16x16PfS_ffiiifffPfS_ffiiifff
	.cfi_endproc
.LFE2052:
	.size	_Z23temperature_update16x16PfS_ffiiifff, .-_Z23temperature_update16x16PfS_ffiiifff
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z23temperature_update16x16PfS_ffiiifff"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z23temperature_update16x16PfS_ffiiifff(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2054:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


/*
    Kernel to do temperature update in explicit finite difference
    solution to 3-D heat equation. Works for a block size of 16 x 16.
    Make copies for other block sizes. Can be easily extended to 
    arbitrary sized stencils.
*/


# include <stdio.h>
# include <hip/hip_runtime.h>

__global__ void temperature_update16x16(float* temp1_d, float* temp2_d, float alpha, 
                    float dt, 
                    const int N_x, const int N_y, const int N_z,
                    const float dx, const float dy, const float dz){


#define BDIMX 16
#define BDIMY 16

__shared__ float slice[BDIMX+2][BDIMY+2];

int ix = blockIdx.x*blockDim.x + threadIdx.x;
int iy = blockIdx.y*blockDim.y + threadIdx.y;

int tx = threadIdx.x + 1;
int ty = threadIdx.y + 1;

int stride = N_x*N_y;
int i2d = iy*N_x + ix;
int o2d = 0;
bool compute_if = ix > 0 && ix < (N_x-1) && iy > 0 && iy < (N_y-1);


float behind;
float current = temp1_d[i2d]; o2d = i2d; i2d += stride;
float infront = temp1_d[i2d]; i2d += stride;

for(int i=1; i<N_z-1; i++){

    // These go in registers:
    behind = current;
    current= infront;
    infront= temp1_d[i2d];

    i2d += stride;
    o2d += stride;
    __syncthreads();

    // Shared memory

    if (compute_if){
        if(threadIdx.x == 0){ // Halo left
            slice[ty][tx-1]     =   temp1_d[o2d - 1];
        }

        if(threadIdx.x == BDIMX-1){ // Halo right
            slice[ty][tx+1]     =   temp1_d[o2d + 1];
        }

        if(threadIdx.y == 0){ // Halo bottom
            slice[ty-1][tx]     =   temp1_d[o2d - N_x];
        }

        if(threadIdx.y == BDIMY-1){ // Halo top
            slice[ty+1][tx]     =   temp1_d[o2d + N_x];
        }
    }

    __syncthreads();

    slice[ty][tx] = current;

    __syncthreads();

    if (compute_if){
        
        temp2_d[o2d]  = current + (alpha*dt)*(
                        (slice[ty][tx-1] - 2*slice[ty][tx]
                        +slice[ty][tx+1])/(dx*dx) +
                        (slice[ty-1][tx] - 2*slice[ty][tx]
                        +slice[ty+1][tx])/(dy*dy) +
                        (behind - 2*current + infront)/(dz*dz));

    }

    __syncthreads();

}

}


	.text
	.file	"3D_heat_kernel.hip"
	.globl	_Z38__device_stub__temperature_update16x16PfS_ffiiifff # -- Begin function _Z38__device_stub__temperature_update16x16PfS_ffiiifff
	.type	_Z38__device_stub__temperature_update16x16PfS_ffiiifff,@function
_Z38__device_stub__temperature_update16x16PfS_ffiiifff: # @_Z38__device_stub__temperature_update16x16PfS_ffiiifff
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$176, %rsp
	.cfi_def_cfa_offset 224
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	28(%rsp), %rsi
	movss	%xmm0, (%rsi)
	leaq	24(%rsp), %r9
	movss	%xmm1, (%r9)
	leaq	20(%rsp), %r10
	movl	%edx, (%r10)
	leaq	16(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	12(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	8(%rsp), %r8
	movss	%xmm2, (%r8)
	leaq	4(%rsp), %r11
	movss	%xmm3, (%r11)
	movq	%rsp, %r14
	movss	%xmm4, (%r14)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%r9, 24(%rbx)
	movq	%r10, 32(%rbx)
	movq	%rdx, 40(%rbx)
	movq	%rcx, 48(%rbx)
	movq	%r8, 56(%rbx)
	movq	%r11, 64(%rbx)
	movq	%r14, 72(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	40(%rsp), %r12
	leaq	32(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z23temperature_update16x16PfS_ffiiifff, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$192, %rsp
	.cfi_adjust_cfa_offset -192
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z38__device_stub__temperature_update16x16PfS_ffiiifff, .Lfunc_end0-_Z38__device_stub__temperature_update16x16PfS_ffiiifff
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z23temperature_update16x16PfS_ffiiifff, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z23temperature_update16x16PfS_ffiiifff,@object # @_Z23temperature_update16x16PfS_ffiiifff
	.section	.rodata,"a",@progbits
	.globl	_Z23temperature_update16x16PfS_ffiiifff
	.p2align	3, 0x0
_Z23temperature_update16x16PfS_ffiiifff:
	.quad	_Z38__device_stub__temperature_update16x16PfS_ffiiifff
	.size	_Z23temperature_update16x16PfS_ffiiifff, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z23temperature_update16x16PfS_ffiiifff"
	.size	.L__unnamed_1, 40

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z38__device_stub__temperature_update16x16PfS_ffiiifff
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z23temperature_update16x16PfS_ffiiifff
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z23temperature_update16x16PfS_ffiiifff ; -- Begin function _Z23temperature_update16x16PfS_ffiiifff
	.globl	_Z23temperature_update16x16PfS_ffiiifff
	.p2align	8
	.type	_Z23temperature_update16x16PfS_ffiiifff,@function
_Z23temperature_update16x16PfS_ffiiifff: ; @_Z23temperature_update16x16PfS_ffiiifff
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x3c
	s_load_b256 s[4:11], s[0:1], 0x10
	v_and_b32_e32 v5, 0x3ff, v0
	v_bfe_u32 v6, v0, 10, 10
	s_mov_b32 s16, 0
	s_mov_b32 s12, exec_lo
	s_waitcnt lgkmcnt(0)
	s_and_b32 s3, s2, 0xffff
	s_lshr_b32 s2, s2, 16
	s_mul_i32 s17, s14, s3
	s_mul_i32 s18, s15, s2
	v_add_nc_u32_e32 v2, s17, v5
	v_add_nc_u32_e32 v3, s18, v6
	s_delay_alu instid0(VALU_DEP_2)
	v_cmpx_lt_i32_e32 0, v2
; %bb.1:
	s_add_i32 s2, s6, -1
	s_add_i32 s3, s7, -1
	v_cmp_gt_i32_e32 vcc_lo, s2, v2
	v_cmp_gt_i32_e64 s2, s3, v3
	v_cmp_lt_i32_e64 s3, 0, v3
	s_delay_alu instid0(VALU_DEP_2)
	s_and_b32 s2, vcc_lo, s2
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, s2, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s16, s2, exec_lo
; %bb.2:
	s_or_b32 exec_lo, exec_lo, s12
	s_cmp_lt_i32 s8, 3
	s_cbranch_scc1 .LBB0_26
; %bb.3:                                ; %.lr.ph
	v_mad_u64_u32 v[0:1], null, v3, s6, v[2:3]
	s_load_b128 s[12:15], s[0:1], 0x0
	s_mul_i32 s2, s7, s6
	v_lshl_add_u32 v3, s7, 1, v3
	v_lshlrev_b32_e32 v4, 2, v5
	v_add3_u32 v17, s18, s7, v6
	v_mul_f32_e64 v13, s4, s5
	v_add_nc_u32_e32 v7, s2, v0
	v_ashrrev_i32_e32 v1, 31, v0
	v_mul_lo_u32 v3, s6, v3
	v_mad_u64_u32 v[23:24], null, s6, v17, s[6:7]
	s_delay_alu instid0(VALU_DEP_4)
	v_ashrrev_i32_e32 v8, 31, v7
	v_mul_f32_e64 v14, s9, s9
	v_mul_f32_e64 v15, s10, s10
	v_mul_f32_e64 v16, s11, s11
	s_ashr_i32 s3, s2, 31
	v_lshlrev_b64 v[19:20], 2, v[7:8]
	v_lshlrev_b64 v[7:8], 2, v[0:1]
	v_add3_u32 v3, v5, v3, s17
	v_add3_u32 v21, v5, v23, s17
	s_add_i32 s7, s8, -2
	s_lshl_b64 s[4:5], s[2:3], 2
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v1, vcc_lo, s12, v19
	v_add_co_ci_u32_e32 v2, vcc_lo, s13, v20, vcc_lo
	v_add_co_u32 v9, vcc_lo, s12, v7
	v_add_co_ci_u32_e32 v10, vcc_lo, s13, v8, vcc_lo
	v_mad_u32_u24 v8, 0x48, v6, v4
	s_clause 0x1
	global_load_b32 v7, v[1:2], off
	global_load_b32 v22, v[9:10], off
	v_ashrrev_i32_e32 v4, 31, v3
	s_mov_b64 s[8:9], 0
	v_add_nc_u32_e32 v9, 0x50, v8
	v_add_nc_u32_e32 v10, 0x48, v8
	v_add_nc_u32_e32 v11, 0x94, v8
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	v_add_nc_u32_e32 v12, 4, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v17, vcc_lo, s12, v3
	v_add_co_ci_u32_e32 v18, vcc_lo, s13, v4, vcc_lo
	v_add_co_u32 v19, vcc_lo, s14, v19
	v_add_co_ci_u32_e32 v20, vcc_lo, s15, v20, vcc_lo
.LBB0_4:                                ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v3, vcc_lo, v17, s8
	v_add_co_ci_u32_e32 v4, vcc_lo, s9, v18, vcc_lo
	s_waitcnt vmcnt(1)
	v_dual_mov_b32 v23, v7 :: v_dual_add_nc_u32 v0, s2, v0
	global_load_b32 v7, v[3:4], off
	s_waitcnt vmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s3, s16
	s_cbranch_execz .LBB0_23
; %bb.5:                                ; %NodeBlock
                                        ;   in Loop: Header=BB0_4 Depth=1
	s_mov_b32 s10, 0
	s_mov_b32 s11, exec_lo
                                        ; implicit-def: $vgpr24
                                        ; implicit-def: $sgpr0_sgpr1
	v_cmpx_lt_i32_e32 14, v5
	s_xor_b32 s11, exec_lo, s11
	s_cbranch_execz .LBB0_9
; %bb.6:                                ; %LeafBlock147
                                        ;   in Loop: Header=BB0_4 Depth=1
	s_mov_b32 s14, exec_lo
                                        ; implicit-def: $sgpr0_sgpr1
	v_cmpx_eq_u32_e32 15, v5
; %bb.7:                                ;   in Loop: Header=BB0_4 Depth=1
	s_mov_b32 s10, exec_lo
	s_mov_b64 s[0:1], 1
; %bb.8:                                ; %Flow160
                                        ;   in Loop: Header=BB0_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s14
	v_mov_b32_e32 v24, v9
	s_and_b32 s10, s10, exec_lo
.LBB0_9:                                ; %Flow159
                                        ;   in Loop: Header=BB0_4 Depth=1
	s_or_saveexec_b32 s11, s11
	v_dual_mov_b32 v4, s1 :: v_dual_mov_b32 v3, s0
	s_xor_b32 exec_lo, exec_lo, s11
; %bb.10:                               ; %LeafBlock
                                        ;   in Loop: Header=BB0_4 Depth=1
	v_cmp_eq_u32_e32 vcc_lo, 0, v5
	v_dual_mov_b32 v3, -1 :: v_dual_mov_b32 v24, v10
	v_mov_b32_e32 v4, -1
	s_and_not1_b32 s0, s10, exec_lo
	s_and_b32 s1, vcc_lo, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s10, s0, s1
; %bb.11:                               ; %Flow161
                                        ;   in Loop: Header=BB0_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s11
	s_and_saveexec_b32 s0, s10
	s_cbranch_execz .LBB0_13
; %bb.12:                               ; %.sink.split
                                        ;   in Loop: Header=BB0_4 Depth=1
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, s8, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s9, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, v1, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, v2, v4, vcc_lo
	global_load_b32 v3, v[3:4], off
	s_waitcnt vmcnt(0)
	ds_store_b32 v24, v3
.LBB0_13:                               ;   in Loop: Header=BB0_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	s_mov_b32 s0, 0
	s_mov_b32 s1, exec_lo
                                        ; implicit-def: $vgpr24
                                        ; implicit-def: $vgpr3
	v_cmpx_lt_i32_e32 14, v6
	s_xor_b32 s1, exec_lo, s1
	s_cbranch_execz .LBB0_17
; %bb.14:                               ; %LeafBlock151
                                        ;   in Loop: Header=BB0_4 Depth=1
	s_mov_b32 s10, exec_lo
	v_cmpx_eq_u32_e32 15, v6
; %bb.15:                               ;   in Loop: Header=BB0_4 Depth=1
	s_mov_b32 s0, exec_lo
; %bb.16:                               ; %Flow155
                                        ;   in Loop: Header=BB0_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
	v_dual_mov_b32 v24, v11 :: v_dual_mov_b32 v3, v21
	s_and_b32 s0, s0, exec_lo
.LBB0_17:                               ; %Flow
                                        ;   in Loop: Header=BB0_4 Depth=1
	s_and_not1_saveexec_b32 s1, s1
	s_cbranch_execz .LBB0_21
; %bb.18:                               ; %LeafBlock149
                                        ;   in Loop: Header=BB0_4 Depth=1
	s_mov_b32 s10, s0
	s_mov_b32 s11, exec_lo
                                        ; implicit-def: $vgpr3
	v_cmpx_eq_u32_e32 0, v6
; %bb.19:                               ;   in Loop: Header=BB0_4 Depth=1
	v_subrev_nc_u32_e32 v3, s6, v0
	s_or_b32 s10, s0, exec_lo
; %bb.20:                               ; %Flow157
                                        ;   in Loop: Header=BB0_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s11
	v_mov_b32_e32 v24, v12
	s_and_not1_b32 s0, s0, exec_lo
	s_and_b32 s10, s10, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s0, s0, s10
.LBB0_21:                               ; %Flow156
                                        ;   in Loop: Header=BB0_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB0_23
; %bb.22:                               ; %.sink.split98
                                        ;   in Loop: Header=BB0_4 Depth=1
	v_ashrrev_i32_e32 v4, 31, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	v_add_co_u32 v3, vcc_lo, s12, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, s13, v4, vcc_lo
	global_load_b32 v3, v[3:4], off
	s_waitcnt vmcnt(0)
	ds_store_b32 v24, v3
.LBB0_23:                               ; %Flow162
                                        ;   in Loop: Header=BB0_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s3
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_store_b32 v8, v23 offset:76
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s3, s16
	s_cbranch_execz .LBB0_25
; %bb.24:                               ;   in Loop: Header=BB0_4 Depth=1
	ds_load_2addr_b32 v[3:4], v8 offset0:18 offset1:19
	ds_load_2addr_b32 v[24:25], v8 offset0:1 offset1:20
	ds_load_b32 v26, v8 offset:148
	s_waitcnt lgkmcnt(2)
	v_fma_f32 v3, -2.0, v4, v3
	s_waitcnt lgkmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v24, -2.0, v4 :: v_dual_add_f32 v3, v25, v3
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v24, v24, v26
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_scale_f32 v25, null, v14, v14, v3
	v_div_scale_f32 v26, null, v15, v15, v24
	v_div_scale_f32 v33, vcc_lo, v3, v14, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rcp_f32_e32 v28, v25
	v_rcp_f32_e32 v29, v26
	s_waitcnt_depctr 0xfff
	v_fma_f32 v32, -v25, v28, 1.0
	v_fma_f32 v34, -v26, v29, 1.0
	v_fmac_f32_e32 v22, -2.0, v23
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_fmac_f32 v28, v32, v28 :: v_dual_fmac_f32 v29, v34, v29
	v_add_f32_e32 v22, v22, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_scale_f32 v4, null, v16, v16, v22
	v_rcp_f32_e32 v27, v4
	s_waitcnt_depctr 0xfff
	v_fma_f32 v31, -v4, v27, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v27, v31, v27
	v_mul_f32_e32 v31, v33, v28
	v_div_scale_f32 v35, s1, v24, v15, v24
	v_div_scale_f32 v30, s0, v22, v16, v22
	v_fma_f32 v36, -v25, v31, v33
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v34, v35, v29
	v_dual_mul_f32 v32, v30, v27 :: v_dual_fmac_f32 v31, v36, v28
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v38, -v26, v34, v35
	v_fma_f32 v37, -v4, v32, v30
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v25, -v25, v31, v33
	v_fmac_f32_e32 v34, v38, v29
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fmas_f32 v25, v25, v28, v31
	v_fma_f32 v26, -v26, v34, v35
	s_mov_b32 vcc_lo, s1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fixup_f32 v3, v25, v14, v3
	v_div_fmas_f32 v26, v26, v29, v34
	s_mov_b32 vcc_lo, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f32 v24, v26, v15, v24
	v_dual_fmac_f32 v32, v37, v27 :: v_dual_add_f32 v3, v3, v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v4, -v4, v32, v30
	v_div_fmas_f32 v4, v4, v27, v32
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f32 v4, v4, v16, v22
	v_add_f32_e32 v3, v4, v3
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f32 v22, v13, v3, v23
	v_add_co_u32 v3, vcc_lo, v19, s8
	v_add_co_ci_u32_e32 v4, vcc_lo, s9, v20, vcc_lo
	global_store_b32 v[3:4], v22, off
.LBB0_25:                               ;   in Loop: Header=BB0_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s3
	s_add_u32 s8, s8, s4
	v_dual_mov_b32 v22, v23 :: v_dual_add_nc_u32 v21, s2, v21
	s_addc_u32 s9, s9, s5
	s_add_i32 s7, s7, -1
	s_waitcnt_vscnt null, 0x0
	s_cmp_eq_u32 s7, 0
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc0 .LBB0_4
.LBB0_26:                               ; %._crit_edge
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z23temperature_update16x16PfS_ffiiifff
		.amdhsa_group_segment_fixed_size 1296
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 304
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 39
		.amdhsa_next_free_sgpr 19
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z23temperature_update16x16PfS_ffiiifff, .Lfunc_end0-_Z23temperature_update16x16PfS_ffiiifff
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1324
; NumSgprs: 21
; NumVgprs: 39
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 1296 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 4
; NumSGPRsForWavesPerEU: 21
; NumVGPRsForWavesPerEU: 39
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         36
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     by_value
      - .offset:         44
        .size:           4
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         52
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         60
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         62
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         64
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         66
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         68
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         70
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         112
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 1296
    .kernarg_segment_align: 8
    .kernarg_segment_size: 304
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z23temperature_update16x16PfS_ffiiifff
    .private_segment_fixed_size: 0
    .sgpr_count:     21
    .sgpr_spill_count: 0
    .symbol:         _Z23temperature_update16x16PfS_ffiiifff.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     39
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
