// dijkstra 算法的并行自全源加未更新快速退出 
__global__ void dijkstra(int* V, int* E, int* W, int* n, int* vis, int* dist, int* predist){
	const int u0 = threadIdx.z * blockDim.x * blockDim.y + threadIdx.y * blockDim.x + threadIdx.x; 
	const int offset = blockDim.x * blockDim.y * blockDim.z; // the number of threads in a block
	const int blockNum = (const int) gridDim.x * gridDim.y; // the number of block

	int u = -1;
	int sn = -1;
	int s = blockIdx.z * (gridDim.x *  gridDim.y) + blockIdx.y * gridDim.x + blockIdx.x;

	__shared__ int quickBreak[1];

	while(s < (*n)){ // source must valid

		sn = (s * (*n));

		for(int i = 0; i < (*n); i++){

			quickBreak[0] = 0; 
			
			u = u0;
			while(u < *n){ 
				if(vis[u + sn] == 0){ 
					vis[u + sn] = 1;
					for(int j = V[u]; j < V[u + 1]; j++){ // the end of j, j is the index of E and W, E[j] is the end of this edge, W[j] is the weight of this edge.	
						atomicMin(&predist[E[j] + sn], dist[u + sn] + W[j]); // s is source.
					}
				}
				u += offset;
			}
			
			__syncthreads(); 

			u = u0;
			while(u < (*n)){
				if(predist[u + sn] < dist[u + sn]){ 
					dist[u + sn] = predist[u + sn];
					vis[u + sn] = 0; 

					quickBreak[0] = 1;
				}
				u += offset;
			}

			__syncthreads();

			if(quickBreak[0] == 0){
				break;
			}
			__syncthreads(); 
		}
		s += blockNum; // next vertex
	}	
}


// base is the start index of E  
__global__ void divide(int* V, int* E, int* W, int* n, int* flag, int* base, int* part, int* vis, int* dist, int* predist){
	
	const int u0 = threadIdx.z * blockDim.x * blockDim.y + threadIdx.y * blockDim.x + threadIdx.x;  
	const int offset = blockDim.x * blockDim.y * blockDim.z; // the number of threads in a  block
	
	int u = -1;
	int l = -1;
	int r = -1;
	int localBase = base[0];
	int localPart = part[0];
	
	u = u0; // this turn, u is not the number of vertex, it's just a offset to tell out of range(part), and u+l is the true number of vertex.
	while(u < (*n)){ // the vertex represented by the current thread  is in video memory.

		if(V[u + 1] <= localBase){ // self right
			u += offset;
			continue; // the range of vertex's edge is illegal. 
		}
		else if(V[u] >= localBase + localPart){ // self left
			u += offset;
			continue; // the range of vertex's edge is illegal. 
		}

		// dist is updated
		if(vis[u]){ 
			// different part is not ordered, so can not use vis to tell.
			//vis[u] -= 1; // 
			atomicSub(&vis[u], 1); // set the ability of running sub one.

			// Shrink the range
			l = localBase>V[u]?localBase:V[u];
			r = (localBase + localPart)<V[u + 1]?(localBase + localPart):V[u + 1];
			
			for(int j = l; j < r; j++){ // get the end of u, j is the index of E and W, E[j] is the end of this edge, W[j] is the weight of this edge.	
				atomicMin(&predist[E[j - localBase]], dist[u] + W[j - localBase]); // the index is not true, need to add offset.
			}
		}
		
		u += offset;
	}
	__syncthreads(); 

	u = u0;
	while(u < (*n)){
		if(predist[u] < dist[u]){ 
			dist[u] = predist[u];
			vis[u] = (V[u + 1] + localPart - 1) / localPart - V[u] / localPart; // recalc the ability of running.
			flag[0] = 1;
		}
		u += offset;
	}
}

	.file	"tmpxft_00211bc0_00000000-6_dijkstra.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2010:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2010:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z39__device_stub__Z8dijkstraPiS_S_S_S_S_S_PiS_S_S_S_S_S_
	.type	_Z39__device_stub__Z8dijkstraPiS_S_S_S_S_S_PiS_S_S_S_S_S_, @function
_Z39__device_stub__Z8dijkstraPiS_S_S_S_S_S_PiS_S_S_S_S_S_:
.LFB2032:
	.cfi_startproc
	endbr64
	subq	$200, %rsp
	.cfi_def_cfa_offset 208
	movq	208(%rsp), %rax
	movq	%rdi, 56(%rsp)
	leaq	80(%rsp), %rdi
	movq	%rsi, 48(%rsp)
	leaq	92(%rsp), %rsi
	movq	%rdx, 40(%rsp)
	leaq	64(%rsp), %rdx
	movq	%rcx, 32(%rsp)
	leaq	72(%rsp), %rcx
	movq	%r8, 24(%rsp)
	movq	%r9, 16(%rsp)
	movq	%rax, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 184(%rsp)
	xorl	%eax, %eax
	leaq	56(%rsp), %rax
	movl	$1, 88(%rsp)
	movq	%rax, 128(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 176(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 80(%rsp)
	movq	%rax, 92(%rsp)
	movl	$1, 100(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	72(%rsp)
	.cfi_def_cfa_offset 216
	leaq	_Z8dijkstraPiS_S_S_S_S_S_(%rip), %rdi
	pushq	72(%rsp)
	.cfi_def_cfa_offset 224
	movq	108(%rsp), %rcx
	movl	116(%rsp), %r8d
	movq	96(%rsp), %rsi
	movl	104(%rsp), %edx
	leaq	144(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 216
	popq	%rdx
	.cfi_def_cfa_offset 208
.L2:
	movq	184(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$200, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2032:
	.size	_Z39__device_stub__Z8dijkstraPiS_S_S_S_S_S_PiS_S_S_S_S_S_, .-_Z39__device_stub__Z8dijkstraPiS_S_S_S_S_S_PiS_S_S_S_S_S_
	.globl	_Z8dijkstraPiS_S_S_S_S_S_
	.type	_Z8dijkstraPiS_S_S_S_S_S_, @function
_Z8dijkstraPiS_S_S_S_S_S_:
.LFB2033:
	.cfi_startproc
	endbr64
	jmp	_Z39__device_stub__Z8dijkstraPiS_S_S_S_S_S_PiS_S_S_S_S_S_
	.cfi_endproc
.LFE2033:
	.size	_Z8dijkstraPiS_S_S_S_S_S_, .-_Z8dijkstraPiS_S_S_S_S_S_
	.globl	_Z43__device_stub__Z6dividePiS_S_S_S_S_S_S_S_S_PiS_S_S_S_S_S_S_S_S_
	.type	_Z43__device_stub__Z6dividePiS_S_S_S_S_S_S_S_S_PiS_S_S_S_S_S_S_S_S_, @function
_Z43__device_stub__Z6dividePiS_S_S_S_S_S_S_S_S_PiS_S_S_S_S_S_S_S_S_:
.LFB2034:
	.cfi_startproc
	endbr64
	subq	$248, %rsp
	.cfi_def_cfa_offset 256
	movq	256(%rsp), %rax
	movq	%rdi, 72(%rsp)
	leaq	104(%rsp), %rdi
	movq	%rsi, 64(%rsp)
	leaq	116(%rsp), %rsi
	movq	%rax, 24(%rsp)
	movq	264(%rsp), %rax
	movq	%rdx, 56(%rsp)
	leaq	88(%rsp), %rdx
	movq	%rax, 16(%rsp)
	movq	272(%rsp), %rax
	movq	%rcx, 48(%rsp)
	leaq	96(%rsp), %rcx
	movq	%rax, 8(%rsp)
	movq	280(%rsp), %rax
	movq	%r8, 40(%rsp)
	movq	%r9, 32(%rsp)
	movq	%rax, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 232(%rsp)
	xorl	%eax, %eax
	leaq	72(%rsp), %rax
	movl	$1, 112(%rsp)
	movq	%rax, 152(%rsp)
	leaq	64(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	56(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 208(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 216(%rsp)
	movq	%rsp, %rax
	movq	%rax, 224(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 104(%rsp)
	movq	%rax, 116(%rsp)
	movl	$1, 124(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L8
	pushq	96(%rsp)
	.cfi_def_cfa_offset 264
	leaq	_Z6dividePiS_S_S_S_S_S_S_S_S_(%rip), %rdi
	pushq	96(%rsp)
	.cfi_def_cfa_offset 272
	movq	132(%rsp), %rcx
	movl	140(%rsp), %r8d
	movq	120(%rsp), %rsi
	movl	128(%rsp), %edx
	leaq	168(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 264
	popq	%rdx
	.cfi_def_cfa_offset 256
.L8:
	movq	232(%rsp), %rax
	subq	%fs:40, %rax
	je	.L10
	call	__stack_chk_fail@PLT
.L10:
	addq	$248, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2034:
	.size	_Z43__device_stub__Z6dividePiS_S_S_S_S_S_S_S_S_PiS_S_S_S_S_S_S_S_S_, .-_Z43__device_stub__Z6dividePiS_S_S_S_S_S_S_S_S_PiS_S_S_S_S_S_S_S_S_
	.globl	_Z6dividePiS_S_S_S_S_S_S_S_S_
	.type	_Z6dividePiS_S_S_S_S_S_S_S_S_, @function
_Z6dividePiS_S_S_S_S_S_S_S_S_:
.LFB2035:
	.cfi_startproc
	endbr64
	jmp	_Z43__device_stub__Z6dividePiS_S_S_S_S_S_S_S_S_PiS_S_S_S_S_S_S_S_S_
	.cfi_endproc
.LFE2035:
	.size	_Z6dividePiS_S_S_S_S_S_S_S_S_, .-_Z6dividePiS_S_S_S_S_S_S_S_S_
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z6dividePiS_S_S_S_S_S_S_S_S_"
.LC1:
	.string	"_Z8dijkstraPiS_S_S_S_S_S_"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2037:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z6dividePiS_S_S_S_S_S_S_S_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC1(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z8dijkstraPiS_S_S_S_S_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2037:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
// dijkstra 算法的并行自全源加未更新快速退出 
__global__ void dijkstra(int* V, int* E, int* W, int* n, int* vis, int* dist, int* predist){
	const int u0 = threadIdx.z * blockDim.x * blockDim.y + threadIdx.y * blockDim.x + threadIdx.x; 
	const int offset = blockDim.x * blockDim.y * blockDim.z; // the number of threads in a block
	const int blockNum = (const int) gridDim.x * gridDim.y; // the number of block

	int u = -1;
	int sn = -1;
	int s = blockIdx.z * (gridDim.x *  gridDim.y) + blockIdx.y * gridDim.x + blockIdx.x;

	__shared__ int quickBreak[1];

	while(s < (*n)){ // source must valid

		sn = (s * (*n));

		for(int i = 0; i < (*n); i++){

			quickBreak[0] = 0; 
			
			u = u0;
			while(u < *n){ 
				if(vis[u + sn] == 0){ 
					vis[u + sn] = 1;
					for(int j = V[u]; j < V[u + 1]; j++){ // the end of j, j is the index of E and W, E[j] is the end of this edge, W[j] is the weight of this edge.	
						atomicMin(&predist[E[j] + sn], dist[u + sn] + W[j]); // s is source.
					}
				}
				u += offset;
			}
			
			__syncthreads(); 

			u = u0;
			while(u < (*n)){
				if(predist[u + sn] < dist[u + sn]){ 
					dist[u + sn] = predist[u + sn];
					vis[u + sn] = 0; 

					quickBreak[0] = 1;
				}
				u += offset;
			}

			__syncthreads();

			if(quickBreak[0] == 0){
				break;
			}
			__syncthreads(); 
		}
		s += blockNum; // next vertex
	}	
}


// base is the start index of E  
__global__ void divide(int* V, int* E, int* W, int* n, int* flag, int* base, int* part, int* vis, int* dist, int* predist){
	
	const int u0 = threadIdx.z * blockDim.x * blockDim.y + threadIdx.y * blockDim.x + threadIdx.x;  
	const int offset = blockDim.x * blockDim.y * blockDim.z; // the number of threads in a  block
	
	int u = -1;
	int l = -1;
	int r = -1;
	int localBase = base[0];
	int localPart = part[0];
	
	u = u0; // this turn, u is not the number of vertex, it's just a offset to tell out of range(part), and u+l is the true number of vertex.
	while(u < (*n)){ // the vertex represented by the current thread  is in video memory.

		if(V[u + 1] <= localBase){ // self right
			u += offset;
			continue; // the range of vertex's edge is illegal. 
		}
		else if(V[u] >= localBase + localPart){ // self left
			u += offset;
			continue; // the range of vertex's edge is illegal. 
		}

		// dist is updated
		if(vis[u]){ 
			// different part is not ordered, so can not use vis to tell.
			//vis[u] -= 1; // 
			atomicSub(&vis[u], 1); // set the ability of running sub one.

			// Shrink the range
			l = localBase>V[u]?localBase:V[u];
			r = (localBase + localPart)<V[u + 1]?(localBase + localPart):V[u + 1];
			
			for(int j = l; j < r; j++){ // get the end of u, j is the index of E and W, E[j] is the end of this edge, W[j] is the weight of this edge.	
				atomicMin(&predist[E[j - localBase]], dist[u] + W[j - localBase]); // the index is not true, need to add offset.
			}
		}
		
		u += offset;
	}
	__syncthreads(); 

	u = u0;
	while(u < (*n)){
		if(predist[u] < dist[u]){ 
			dist[u] = predist[u];
			vis[u] = (V[u + 1] + localPart - 1) / localPart - V[u] / localPart; // recalc the ability of running.
			flag[0] = 1;
		}
		u += offset;
	}
}

	.text
	.file	"dijkstra.hip"
	.globl	_Z23__device_stub__dijkstraPiS_S_S_S_S_S_ # -- Begin function _Z23__device_stub__dijkstraPiS_S_S_S_S_S_
	.type	_Z23__device_stub__dijkstraPiS_S_S_S_S_S_,@function
_Z23__device_stub__dijkstraPiS_S_S_S_S_S_: # @_Z23__device_stub__dijkstraPiS_S_S_S_S_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z8dijkstraPiS_S_S_S_S_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z23__device_stub__dijkstraPiS_S_S_S_S_S_, .Lfunc_end0-_Z23__device_stub__dijkstraPiS_S_S_S_S_S_
	.cfi_endproc
                                        # -- End function
	.globl	_Z21__device_stub__dividePiS_S_S_S_S_S_S_S_S_ # -- Begin function _Z21__device_stub__dividePiS_S_S_S_S_S_S_S_S_
	.type	_Z21__device_stub__dividePiS_S_S_S_S_S_S_S_S_,@function
_Z21__device_stub__dividePiS_S_S_S_S_S_S_S_S_: # @_Z21__device_stub__dividePiS_S_S_S_S_S_S_S_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$176, %rsp
	.cfi_def_cfa_offset 224
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	224(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	232(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	240(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	248(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z6dividePiS_S_S_S_S_S_S_S_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$192, %rsp
	.cfi_adjust_cfa_offset -192
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z21__device_stub__dividePiS_S_S_S_S_S_S_S_S_, .Lfunc_end1-_Z21__device_stub__dividePiS_S_S_S_S_S_S_S_S_
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z8dijkstraPiS_S_S_S_S_S_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z6dividePiS_S_S_S_S_S_S_S_S_, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z8dijkstraPiS_S_S_S_S_S_,@object # @_Z8dijkstraPiS_S_S_S_S_S_
	.section	.rodata,"a",@progbits
	.globl	_Z8dijkstraPiS_S_S_S_S_S_
	.p2align	3, 0x0
_Z8dijkstraPiS_S_S_S_S_S_:
	.quad	_Z23__device_stub__dijkstraPiS_S_S_S_S_S_
	.size	_Z8dijkstraPiS_S_S_S_S_S_, 8

	.type	_Z6dividePiS_S_S_S_S_S_S_S_S_,@object # @_Z6dividePiS_S_S_S_S_S_S_S_S_
	.globl	_Z6dividePiS_S_S_S_S_S_S_S_S_
	.p2align	3, 0x0
_Z6dividePiS_S_S_S_S_S_S_S_S_:
	.quad	_Z21__device_stub__dividePiS_S_S_S_S_S_S_S_S_
	.size	_Z6dividePiS_S_S_S_S_S_S_S_S_, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z8dijkstraPiS_S_S_S_S_S_"
	.size	.L__unnamed_1, 26

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z6dividePiS_S_S_S_S_S_S_S_S_"
	.size	.L__unnamed_2, 30

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z23__device_stub__dijkstraPiS_S_S_S_S_S_
	.addrsig_sym _Z21__device_stub__dividePiS_S_S_S_S_S_S_S_S_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z8dijkstraPiS_S_S_S_S_S_
	.addrsig_sym _Z6dividePiS_S_S_S_S_S_S_S_S_
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z8dijkstraPiS_S_S_S_S_S_ ; -- Begin function _Z8dijkstraPiS_S_S_S_S_S_
	.globl	_Z8dijkstraPiS_S_S_S_S_S_
	.p2align	8
	.type	_Z8dijkstraPiS_S_S_S_S_S_,@function
_Z8dijkstraPiS_S_S_S_S_S_:              ; @_Z8dijkstraPiS_S_S_S_S_S_
; %bb.0:
	s_clause 0x1
	s_load_b256 s[4:11], s[0:1], 0x0
	s_load_b64 s[16:17], s[0:1], 0x38
	s_add_u32 s2, s0, 56
	s_addc_u32 s3, s1, 0
	s_waitcnt lgkmcnt(0)
	s_load_b32 s22, s[10:11], 0x0
	s_mul_i32 s20, s17, s16
	s_mul_i32 s12, s16, s14
	s_mul_i32 s14, s20, s15
	s_add_i32 s12, s12, s13
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_i32 s21, s12, s14
	s_waitcnt lgkmcnt(0)
	s_cmp_ge_i32 s21, s22
	s_cbranch_scc1 .LBB0_23
; %bb.1:                                ; %.lr.ph93.preheader
	s_load_b64 s[2:3], s[2:3], 0xc
	s_load_b256 s[12:19], s[0:1], 0x20
	v_bfe_u32 v1, v0, 10, 10
	v_bfe_u32 v2, v0, 20, 10
	v_dual_mov_b32 v14, 1 :: v_dual_mov_b32 v13, 0
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s0, s2, 16
	s_and_b32 s1, s2, 0xffff
	v_mad_u32_u24 v3, v2, s0, v1
	v_and_b32_e32 v2, 0x3ff, v0
	s_and_b32 s2, s3, 0xffff
	s_mul_i32 s0, s0, s1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_mul_i32 s2, s0, s2
	v_mad_u64_u32 v[0:1], null, v3, s1, v[2:3]
	s_ashr_i32 s3, s2, 31
	s_delay_alu instid0(SALU_CYCLE_1)
	s_lshl_b64 s[18:19], s[2:3], 2
.LBB0_2:                                ; %.lr.ph93
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_4 Depth 2
                                        ;       Child Loop BB0_6 Depth 3
                                        ;         Child Loop BB0_9 Depth 4
                                        ;       Child Loop BB0_13 Depth 3
	s_cmp_lt_i32 s22, 1
	s_cbranch_scc1 .LBB0_22
; %bb.3:                                ; %.lr.ph88.preheader
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_mul_i32 s1, s22, s21
	s_mov_b32 s3, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v1, s1, v0
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
.LBB0_4:                                ; %.lr.ph88
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB0_6 Depth 3
                                        ;         Child Loop BB0_9 Depth 4
                                        ;       Child Loop BB0_13 Depth 3
	v_cmp_gt_i32_e32 vcc_lo, s22, v0
	ds_store_b32 v13, v13
	s_and_saveexec_b32 s22, vcc_lo
	s_cbranch_execz .LBB0_11
; %bb.5:                                ; %.lr.ph81.preheader
                                        ;   in Loop: Header=BB0_4 Depth=2
	v_mov_b32_e32 v3, v0
	s_mov_b32 s23, 0
.LBB0_6:                                ; %.lr.ph81
                                        ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_4 Depth=2
                                        ; =>    This Loop Header: Depth=3
                                        ;         Child Loop BB0_9 Depth 4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v4, s1, v3
	s_mov_b32 s24, exec_lo
	v_ashrrev_i32_e32 v5, 31, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[8:9], 2, v[4:5]
	v_add_co_u32 v6, vcc_lo, s12, v8
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v7, vcc_lo, s13, v9, vcc_lo
	global_load_b32 v4, v[6:7], off
	s_waitcnt vmcnt(0)
	v_cmpx_eq_u32_e32 0, v4
	s_cbranch_execz .LBB0_10
; %bb.7:                                ;   in Loop: Header=BB0_6 Depth=3
	v_ashrrev_i32_e32 v4, 31, v3
	global_store_b32 v[6:7], v14, off
	v_lshlrev_b64 v[4:5], 2, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, s4, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
	global_load_b64 v[6:7], v[4:5], off
	s_waitcnt vmcnt(0)
	v_cmp_lt_i32_e32 vcc_lo, v6, v7
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_10
; %bb.8:                                ; %.lr.ph
                                        ;   in Loop: Header=BB0_6 Depth=3
	v_ashrrev_i32_e32 v7, 31, v6
	s_mov_b32 s25, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[11:12], 2, v[6:7]
	v_add_co_u32 v7, vcc_lo, s14, v8
	v_add_co_ci_u32_e32 v8, vcc_lo, s15, v9, vcc_lo
	v_add_co_u32 v9, vcc_lo, s6, v11
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v10, vcc_lo, s7, v12, vcc_lo
	v_add_co_u32 v11, vcc_lo, s8, v11
	v_add_co_ci_u32_e32 v12, vcc_lo, s9, v12, vcc_lo
.LBB0_9:                                ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_4 Depth=2
                                        ;       Parent Loop BB0_6 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	global_load_b32 v15, v[9:10], off
	global_load_b32 v17, v[7:8], off
	global_load_b32 v18, v[11:12], off
	v_add_nc_u32_e32 v6, 1, v6
	v_add_co_u32 v11, s0, v11, 4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e64 v12, s0, 0, v12, s0
	s_waitcnt vmcnt(2)
	v_add_nc_u32_e32 v15, s1, v15
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v17, v18, v17
	v_ashrrev_i32_e32 v16, 31, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[15:16], 2, v[15:16]
	v_add_co_u32 v15, vcc_lo, s16, v15
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v16, vcc_lo, s17, v16, vcc_lo
	v_add_co_u32 v9, vcc_lo, v9, 4
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v10, vcc_lo
	global_atomic_min_i32 v[15:16], v17, off
	global_load_b32 v15, v[4:5], off offset:4
	s_waitcnt vmcnt(0)
	v_cmp_ge_i32_e32 vcc_lo, v6, v15
	s_or_b32 s25, vcc_lo, s25
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s25
	s_cbranch_execnz .LBB0_9
.LBB0_10:                               ; %.loopexit
                                        ;   in Loop: Header=BB0_6 Depth=3
	s_or_b32 exec_lo, exec_lo, s24
	global_load_b32 v4, v13, s[10:11]
	v_add_nc_u32_e32 v3, s2, v3
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_ge_i32_e32 vcc_lo, v3, v4
	s_or_b32 s23, vcc_lo, s23
	s_and_not1_b32 exec_lo, exec_lo, s23
	s_cbranch_execnz .LBB0_6
.LBB0_11:                               ; %Flow133
                                        ;   in Loop: Header=BB0_4 Depth=2
	s_or_b32 exec_lo, exec_lo, s22
	s_waitcnt lgkmcnt(0)
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	global_load_b32 v7, v13, s[10:11]
	s_mov_b32 s22, exec_lo
	s_waitcnt vmcnt(0)
	v_cmpx_lt_i32_e64 v0, v7
	s_cbranch_execz .LBB0_16
; %bb.12:                               ; %.lr.ph84.preheader
                                        ;   in Loop: Header=BB0_4 Depth=2
	v_dual_mov_b32 v4, v2 :: v_dual_mov_b32 v3, v1
	v_mov_b32_e32 v8, v0
	s_mov_b32 s23, 0
.LBB0_13:                               ; %.lr.ph84
                                        ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_4 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v9, vcc_lo, s16, v3
	v_add_co_ci_u32_e32 v10, vcc_lo, s17, v4, vcc_lo
	v_add_co_u32 v5, vcc_lo, s14, v3
	v_add_co_ci_u32_e32 v6, vcc_lo, s15, v4, vcc_lo
	s_mov_b32 s0, exec_lo
	global_load_b32 v9, v[9:10], off
	global_load_b32 v10, v[5:6], off
	s_waitcnt vmcnt(0)
	v_cmpx_lt_i32_e64 v9, v10
	s_cbranch_execz .LBB0_15
; %bb.14:                               ;   in Loop: Header=BB0_13 Depth=3
	v_add_co_u32 v10, vcc_lo, s12, v3
	v_add_co_ci_u32_e32 v11, vcc_lo, s13, v4, vcc_lo
	global_store_b32 v[5:6], v9, off
	global_store_b32 v[10:11], v13, off
	global_load_b32 v7, v13, s[10:11]
	ds_store_b32 v13, v14
.LBB0_15:                               ;   in Loop: Header=BB0_13 Depth=3
	s_or_b32 exec_lo, exec_lo, s0
	v_add_nc_u32_e32 v8, s2, v8
	v_add_co_u32 v3, s0, v3, s18
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v4, s0, s19, v4, s0
	s_waitcnt vmcnt(0)
	v_cmp_ge_i32_e32 vcc_lo, v8, v7
	s_or_b32 s23, vcc_lo, s23
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s23
	s_cbranch_execnz .LBB0_13
.LBB0_16:                               ; %Flow129
                                        ;   in Loop: Header=BB0_4 Depth=2
	s_or_b32 exec_lo, exec_lo, s22
	s_waitcnt lgkmcnt(0)
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	ds_load_b32 v3, v13
	s_waitcnt lgkmcnt(0)
	v_cmp_ne_u32_e32 vcc_lo, 0, v3
	s_cbranch_vccz .LBB0_18
; %bb.17:                               ;   in Loop: Header=BB0_4 Depth=2
	s_barrier
	buffer_gl0_inv
	global_load_b32 v3, v13, s[10:11]
	s_add_i32 s3, s3, 1
	s_mov_b32 s0, 0
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s22, v3
	v_cmp_ge_i32_e64 s23, s3, v3
	s_branch .LBB0_19
.LBB0_18:                               ;   in Loop: Header=BB0_4 Depth=2
	s_mov_b32 s0, -1
	s_mov_b32 s23, -1
                                        ; implicit-def: $sgpr3
                                        ; implicit-def: $sgpr22
.LBB0_19:                               ; %Flow135
                                        ;   in Loop: Header=BB0_4 Depth=2
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s23
	s_cbranch_vccnz .LBB0_4
; %bb.20:                               ; %loop.exit.guard
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_and_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccz .LBB0_22
; %bb.21:                               ; %._crit_edge85.._crit_edge89.loopexit_crit_edge
                                        ;   in Loop: Header=BB0_2 Depth=1
	global_load_b32 v1, v13, s[10:11]
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s22, v1
.LBB0_22:                               ; %._crit_edge89
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_add_i32 s21, s21, s20
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	s_cmp_lt_i32 s21, s22
	s_cbranch_scc1 .LBB0_2
.LBB0_23:                               ; %._crit_edge94
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z8dijkstraPiS_S_S_S_S_S_
		.amdhsa_group_segment_fixed_size 4
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 312
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 19
		.amdhsa_next_free_sgpr 26
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z8dijkstraPiS_S_S_S_S_S_, .Lfunc_end0-_Z8dijkstraPiS_S_S_S_S_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1012
; NumSgprs: 28
; NumVgprs: 19
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 4 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 28
; NumVGPRsForWavesPerEU: 19
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.text
	.protected	_Z6dividePiS_S_S_S_S_S_S_S_S_ ; -- Begin function _Z6dividePiS_S_S_S_S_S_S_S_S_
	.globl	_Z6dividePiS_S_S_S_S_S_S_S_S_
	.p2align	8
	.type	_Z6dividePiS_S_S_S_S_S_S_S_S_,@function
_Z6dividePiS_S_S_S_S_S_S_S_S_:          ; @_Z6dividePiS_S_S_S_S_S_S_S_S_
; %bb.0:
	s_clause 0x2
	s_load_b512 s[4:19], s[0:1], 0x0
	s_load_b64 s[2:3], s[0:1], 0x5c
	s_load_b128 s[20:23], s[0:1], 0x40
	v_bfe_u32 v1, v0, 10, 10
	v_bfe_u32 v2, v0, 20, 10
	s_waitcnt lgkmcnt(0)
	s_load_b32 s24, s[10:11], 0x0
	s_load_b32 s1, s[16:17], 0x0
	s_lshr_b32 s0, s2, 16
	s_and_b32 s2, s2, 0xffff
	v_mad_u32_u24 v3, v2, s0, v1
	v_and_b32_e32 v2, 0x3ff, v0
	s_and_b32 s3, s3, 0xffff
	s_mul_i32 s0, s0, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[0:1], null, v3, s2, v[2:3]
	s_mul_i32 s2, s0, s3
	s_mov_b32 s3, exec_lo
	s_waitcnt lgkmcnt(0)
	v_cmpx_gt_i32_e64 s24, v0
	s_cbranch_execz .LBB1_11
; %bb.1:                                ; %.lr.ph96
	s_load_b32 s14, s[14:15], 0x0
	v_dual_mov_b32 v6, s24 :: v_dual_mov_b32 v9, 0
	v_dual_mov_b32 v8, -1 :: v_dual_mov_b32 v1, v0
	s_mov_b32 s17, 0
	s_waitcnt lgkmcnt(0)
	s_ashr_i32 s15, s14, 31
	s_add_i32 s16, s1, s14
	s_lshl_b64 s[24:25], s[14:15], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_sub_u32 s6, s6, s24
	s_subb_u32 s7, s7, s25
	s_sub_u32 s8, s8, s24
	s_subb_u32 s9, s9, s25
.LBB1_2:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB1_7 Depth 2
	v_ashrrev_i32_e32 v2, 31, v1
	s_mov_b32 s24, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[1:2]
	v_add_co_u32 v4, vcc_lo, s4, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
	global_load_b32 v7, v[4:5], off offset:4
	s_waitcnt vmcnt(0)
	v_cmpx_lt_i32_e64 s14, v7
	s_cbranch_execz .LBB1_10
; %bb.3:                                ;   in Loop: Header=BB1_2 Depth=1
	global_load_b32 v7, v[4:5], off
	s_mov_b32 s25, exec_lo
	s_waitcnt vmcnt(0)
	v_cmpx_gt_i32_e64 s16, v7
	s_cbranch_execz .LBB1_9
; %bb.4:                                ;   in Loop: Header=BB1_2 Depth=1
	v_add_co_u32 v6, vcc_lo, s18, v2
	v_add_co_ci_u32_e32 v7, vcc_lo, s19, v3, vcc_lo
	s_mov_b32 s26, exec_lo
	global_load_b32 v10, v[6:7], off
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u32_e32 0, v10
	s_cbranch_execz .LBB1_8
; %bb.5:                                ;   in Loop: Header=BB1_2 Depth=1
	global_atomic_add_u32 v[6:7], v8, off
	global_load_b64 v[4:5], v[4:5], off
	s_waitcnt vmcnt(0)
	v_max_i32_e32 v10, s14, v4
	v_min_i32_e32 v11, s16, v5
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_lt_i32_e32 vcc_lo, v10, v11
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB1_8
; %bb.6:                                ; %.lr.ph
                                        ;   in Loop: Header=BB1_2 Depth=1
	v_ashrrev_i32_e32 v5, 31, v4
	s_mov_b32 s27, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_3)
	v_cmp_lt_i64_e32 vcc_lo, s[14:15], v[4:5]
	v_cndmask_b32_e32 v5, s15, v5, vcc_lo
	v_cndmask_b32_e32 v4, s14, v4, vcc_lo
	v_add_co_u32 v2, vcc_lo, s20, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s21, v3, vcc_lo
	v_lshlrev_b64 v[6:7], 2, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, s6, v6
	v_add_co_ci_u32_e32 v5, vcc_lo, s7, v7, vcc_lo
	v_add_co_u32 v6, vcc_lo, s8, v6
	v_add_co_ci_u32_e32 v7, vcc_lo, s9, v7, vcc_lo
.LBB1_7:                                ;   Parent Loop BB1_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	global_load_b32 v12, v[4:5], off
	global_load_b32 v14, v[2:3], off
	global_load_b32 v15, v[6:7], off
	v_add_nc_u32_e32 v10, 1, v10
	v_add_co_u32 v6, s0, v6, 4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e64 v7, s0, 0, v7, s0
	s_waitcnt vmcnt(2)
	v_ashrrev_i32_e32 v13, 31, v12
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v14, v15, v14
	v_lshlrev_b64 v[12:13], 2, v[12:13]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v12, vcc_lo, s22, v12
	v_add_co_ci_u32_e32 v13, vcc_lo, s23, v13, vcc_lo
	v_add_co_u32 v4, vcc_lo, v4, 4
	v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
	global_atomic_min_i32 v[12:13], v14, off
	v_cmp_ge_i32_e32 vcc_lo, v10, v11
	s_or_b32 s27, vcc_lo, s27
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s27
	s_cbranch_execnz .LBB1_7
.LBB1_8:                                ; %.loopexit
                                        ;   in Loop: Header=BB1_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s26
	global_load_b32 v6, v9, s[10:11]
.LBB1_9:                                ; %Flow149
                                        ;   in Loop: Header=BB1_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s25
.LBB1_10:                               ; %.backedge
                                        ;   in Loop: Header=BB1_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	s_or_b32 exec_lo, exec_lo, s24
	v_add_nc_u32_e32 v1, s2, v1
	s_waitcnt vmcnt(0)
	v_cmp_ge_i32_e32 vcc_lo, v1, v6
	s_or_b32 s17, vcc_lo, s17
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s17
	s_cbranch_execnz .LBB1_2
.LBB1_11:                               ; %Flow151
	s_or_b32 exec_lo, exec_lo, s3
	v_mov_b32_e32 v5, 0
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_mov_b32 s0, exec_lo
	global_load_b32 v8, v5, s[10:11]
	s_waitcnt vmcnt(0)
	v_cmpx_lt_i32_e64 v0, v8
	s_cbranch_execz .LBB1_16
; %bb.12:                               ; %.lr.ph99
	s_ashr_i32 s8, s1, 31
	v_mov_b32_e32 v7, 1
	s_add_i32 s0, s1, s8
	s_ashr_i32 s3, s2, 31
	s_xor_b32 s9, s0, s8
	s_add_i32 s1, s1, -1
	v_cvt_f32_u32_e32 v1, s9
	s_sub_i32 s0, 0, s9
	s_mov_b32 s14, 0
	s_lshl_b64 s[6:7], s[2:3], 2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v1, v1
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v1, 0x4f7ffffe, v1
	v_cvt_u32_f32_e32 v3, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v1, s0, v3
	v_mul_hi_u32 v4, v3, v1
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[1:2], 2, v[0:1]
	v_add_nc_u32_e32 v6, v3, v4
.LBB1_13:                               ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v9, vcc_lo, s22, v1
	v_add_co_ci_u32_e32 v10, vcc_lo, s23, v2, vcc_lo
	v_add_co_u32 v3, vcc_lo, s20, v1
	v_add_co_ci_u32_e32 v4, vcc_lo, s21, v2, vcc_lo
	s_mov_b32 s3, exec_lo
	global_load_b32 v9, v[9:10], off
	global_load_b32 v10, v[3:4], off
	s_waitcnt vmcnt(0)
	v_cmpx_lt_i32_e64 v9, v10
	s_cbranch_execz .LBB1_15
; %bb.14:                               ;   in Loop: Header=BB1_13 Depth=1
	v_add_co_u32 v10, vcc_lo, s4, v1
	v_add_co_ci_u32_e32 v11, vcc_lo, s5, v2, vcc_lo
	global_store_b32 v[3:4], v9, off
	global_load_b64 v[3:4], v[10:11], off
	s_waitcnt vmcnt(0)
	v_ashrrev_i32_e32 v8, 31, v3
	v_add_nc_u32_e32 v4, s1, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v3, v3, v8
	v_ashrrev_i32_e32 v9, 31, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v3, v3, v8
	v_xor_b32_e32 v8, s8, v8
	v_mul_hi_u32 v10, v3, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v12, v10, s9
	v_sub_nc_u32_e32 v3, v3, v12
	v_add_nc_u32_e32 v12, 1, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_le_u32_e32 vcc_lo, s9, v3
	v_cndmask_b32_e32 v10, v10, v12, vcc_lo
	v_subrev_nc_u32_e32 v12, s9, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_cndmask_b32 v3, v3, v12 :: v_dual_add_nc_u32 v4, v4, v9
	v_xor_b32_e32 v4, v4, v9
	v_xor_b32_e32 v9, s8, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_le_u32_e32 vcc_lo, s9, v3
	v_mul_hi_u32 v11, v4, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v13, v11, s9
	v_sub_nc_u32_e32 v4, v4, v13
	v_add_nc_u32_e32 v13, 1, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cmp_le_u32_e64 s0, s9, v4
	v_subrev_nc_u32_e32 v14, s9, v4
	v_cndmask_b32_e64 v11, v11, v13, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v4, v4, v14, s0
	v_add_nc_u32_e32 v13, 1, v11
	v_add_nc_u32_e32 v12, 1, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e32 v3, v10, v12, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s9, v4
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v4, v11, v13, vcc_lo
	v_xor_b32_e32 v3, v3, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v4, v4, v9
	v_sub_nc_u32_e32 v8, v8, v3
	v_add_co_u32 v3, vcc_lo, s18, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v9, v4, v9
	v_add_co_ci_u32_e32 v4, vcc_lo, s19, v2, vcc_lo
	v_add_nc_u32_e32 v8, v9, v8
	global_store_b32 v[3:4], v8, off
	global_store_b32 v5, v7, s[12:13]
	global_load_b32 v8, v5, s[10:11]
.LBB1_15:                               ;   in Loop: Header=BB1_13 Depth=1
	s_or_b32 exec_lo, exec_lo, s3
	v_add_nc_u32_e32 v0, s2, v0
	v_add_co_u32 v1, s0, v1, s6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v2, s0, s7, v2, s0
	s_waitcnt vmcnt(0)
	v_cmp_ge_i32_e32 vcc_lo, v0, v8
	s_or_b32 s14, vcc_lo, s14
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s14
	s_cbranch_execnz .LBB1_13
.LBB1_16:                               ; %._crit_edge100
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z6dividePiS_S_S_S_S_S_S_S_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 336
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 16
		.amdhsa_next_free_sgpr 28
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z6dividePiS_S_S_S_S_S_S_S_S_, .Lfunc_end1-_Z6dividePiS_S_S_S_S_S_S_S_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1200
; NumSgprs: 30
; NumVgprs: 16
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 30
; NumVGPRsForWavesPerEU: 16
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         48
        .size:           8
        .value_kind:     global_buffer
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         60
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         64
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         68
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         70
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         72
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         74
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         76
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         78
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         112
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         120
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 4
    .kernarg_segment_align: 8
    .kernarg_segment_size: 312
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z8dijkstraPiS_S_S_S_S_S_
    .private_segment_fixed_size: 0
    .sgpr_count:     28
    .sgpr_spill_count: 0
    .symbol:         _Z8dijkstraPiS_S_S_S_S_S_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     19
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         48
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         56
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         64
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         72
        .size:           8
        .value_kind:     global_buffer
      - .offset:         80
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         84
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         88
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         92
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         94
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         96
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         98
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         100
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         102
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         120
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         128
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         136
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         144
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 336
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z6dividePiS_S_S_S_S_S_S_S_S_
    .private_segment_fixed_size: 0
    .sgpr_count:     30
    .sgpr_spill_count: 0
    .symbol:         _Z6dividePiS_S_S_S_S_S_S_S_S_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     16
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
