// ****
// Implement the phasor method using complex data rather than two times reconstruction
// ****
#define NPOINT 1
#define STRIDE 1
/*__global__ void ThreeD_NLOS_Phasor_General( float* p_xyz,  float* p_xyt_real,  float* p_xyt_imag,   
    float* sensor_pos, float* origin, float* laser_pos,  float dx,  float dz,  int NX,  int NY, int NZ, 
    float c_dt,  int N_pos, int Nt,  float ReceiveDelay)
{
        int nz = blockIdx.z * blockDim.z + threadIdx.z; // the nz-column, which is the time direction
        int ny = blockIdx.y * blockDim.y + threadIdx.y; // the ny-col
        int nx = blockIdx.x * blockDim.x + threadIdx.x; // the nx-row
        float CF_real = 0.0, CF_imag = 0.0, CF = 0.0;
        float tao = 0.0;
        float voxel_int_real = 0.0, voxel_int_imag =0.0;
        float voxel_real = 0.0, voxel_imag =0.0;
        int Index = 0, counter = 1;
        float GPS_x = origin[0] - (nx-NX/2)*dx;    // x-coordiante for the voxel
        float GPS_y = origin[1] + (ny-NY/2)*dx;    // y-coordiante for the voxel
        float GPS_z = origin[2] + (nz)*dz;         // z-coordiante for the voxel
        // time delay from the laser spot to the voxel
        float tao_trans = sqrtf( (laser_pos[0]-GPS_x)*(laser_pos[0]-GPS_x) + (laser_pos[1]-GPS_y)*(laser_pos[1]-GPS_y) + (laser_pos[2]-GPS_z)*(laser_pos[2]-GPS_z) );
        float x_pos,y_pos,z_pos, cos_theta;
        float voxel_int_real_tp[NPOINT], voxel_int_imag_tp[NPOINT],  voxel_sq_real_tp[NPOINT], voxel_sq_imag_tp[NPOINT];
        
        for(int K = 0; K<NPOINT; K++)
        {
            voxel_int_real_tp[K] = 0.0;
            voxel_int_imag_tp[K] = 0.0;
            voxel_sq_real_tp[K] = 0.0;
            voxel_sq_imag_tp[K] = 0.0;
        }
        
        for(int K_x = 0;K_x<N_pos; K_x++)
        {
              x_pos = sensor_pos[K_x];
              y_pos = sensor_pos[K_x+N_pos];
              z_pos = sensor_pos[K_x+2*N_pos];
              tao = sqrtf( (x_pos-GPS_x) * (x_pos-GPS_x) + (y_pos-GPS_y)*(y_pos-GPS_y) + (z_pos-GPS_z)*(z_pos-GPS_z) );
              cos_theta = GPS_z/(tao + 1e-6);
              Index = int( floorf((tao + tao_trans)/c_dt-ReceiveDelay) );
              if((Index<Nt-NPOINT*STRIDE) && (Index>0))
              {
                  for(int P = 0; P<NPOINT; P++)
                    {
                        voxel_real = p_xyt_real[Index+K_x*(Nt)+P*STRIDE] * cos_theta;
                        voxel_imag = p_xyt_imag[Index+K_x*(Nt)+P*STRIDE] * cos_theta;                         
                        voxel_int_real_tp[P] = voxel_int_real_tp[P] + voxel_real;    //* sqrt(Index*1.0);
                        voxel_int_imag_tp[P] = voxel_int_imag_tp[P] + voxel_imag;    //* sqrt(Index*1.0);
                        voxel_sq_real_tp[P] = voxel_sq_real_tp[P] + voxel_real * voxel_real;
                        voxel_sq_imag_tp[P] = voxel_sq_imag_tp[P] + voxel_imag * voxel_imag;
                    }
                    counter = counter+1;
              }
        }
        
        voxel_int_real = voxel_int_real_tp[0]; 
        voxel_int_imag = voxel_int_imag_tp[0];
        
        
        for (int J=0;J<NPOINT;J++)
        {
    
            if((voxel_sq_real_tp[J]>1e-6) && (voxel_sq_imag_tp[J]>1e-6))
            {
              CF_real = CF_real + powf(voxel_int_real_tp[J],2)/voxel_sq_real_tp[J]/counter;
              CF_imag = CF_imag + powf(voxel_int_imag_tp[J],2)/voxel_sq_imag_tp[J]/counter;
              
            }
        }
        CF = sqrtf( CF_real*CF_real + CF_imag*CF_imag );
        p_xyz[nx+NX*ny+nz*(NX*NY)] = sqrtf( voxel_int_real * voxel_int_real  + voxel_int_imag * voxel_int_imag ) * (CF);
}*/

// ****
// Implement the phasor method using complex data rather than two times reconstruction
// ****
#define NPOINT 1
#define STRIDE 1
__global__ void ThreeD_NLOS_Phasor_General( float* p_xyz,  float* p_xyt_real,  float* p_xyt_imag,   
    float* sensor_pos, float* origin, float* laser_pos,  float dx,  float dz,  int NX,  int NY, int NZ, 
    float c_dt,  int N_pos, int Nt,  float ReceiveDelay)
{
        int nz = blockIdx.z * blockDim.z + threadIdx.z; // the nz-column, which is the time direction
        int ny = blockIdx.y * blockDim.y + threadIdx.y; // the ny-col
        int nx = blockIdx.x * blockDim.x + threadIdx.x; // the nx-row
        float CF_real = 0.0, CF_imag = 0.0, CF = 0.0;
        float tao = 0.0;
        float voxel_int_real = 0.0, voxel_int_imag =0.0;
        float voxel_real = 0.0, voxel_imag =0.0;
        int Index = 0, counter = 1;
        float GPS_x = origin[0] - (nx-NX/2)*dx;    // x-coordiante for the voxel
        float GPS_y = origin[1] + (ny-NY/2)*dx;    // y-coordiante for the voxel
        float GPS_z = origin[2] + (nz)*dz;         // z-coordiante for the voxel
        // time delay from the laser spot to the voxel
        float tao_trans = sqrtf( (laser_pos[0]-GPS_x)*(laser_pos[0]-GPS_x) + (laser_pos[1]-GPS_y)*(laser_pos[1]-GPS_y) + (laser_pos[2]-GPS_z)*(laser_pos[2]-GPS_z) );
        float x_pos,y_pos,z_pos, cos_theta;
        float  voxel_sq_real, voxel_sq_imag;
         
        for(int K_x = 0;K_x<N_pos; K_x++)
        {
              x_pos = sensor_pos[K_x];
              y_pos = sensor_pos[K_x+N_pos];
              z_pos = sensor_pos[K_x+2*N_pos];
              tao = sqrtf( (x_pos-GPS_x) * (x_pos-GPS_x) + (y_pos-GPS_y)*(y_pos-GPS_y) + (z_pos-GPS_z)*(z_pos-GPS_z) );
              cos_theta = GPS_z/(tao + 1e-6);
              Index = int( floorf((tao + tao_trans)/c_dt-ReceiveDelay) );
              if((Index<Nt) && (Index>0))
              {

                    voxel_real = p_xyt_real[Index+K_x*(Nt)] * cos_theta;
                    voxel_imag = p_xyt_imag[Index+K_x*(Nt)] * cos_theta;                         
                    voxel_int_real = voxel_int_real + voxel_real;    //* sqrt(Index*1.0);
                    voxel_int_imag = voxel_int_imag + voxel_imag;    //* sqrt(Index*1.0);
                    voxel_sq_real = voxel_sq_real + voxel_real * voxel_real;
                    voxel_sq_imag = voxel_sq_imag + voxel_imag * voxel_imag;
                    counter = counter+1;
              }
        }
              
        if((voxel_sq_real>1e-6) && (voxel_sq_imag>1e-6))
        {
          CF_real = CF_real + powf(voxel_int_real,2)/voxel_sq_real/counter;
          CF_imag = CF_imag + powf(voxel_int_imag,2)/voxel_sq_imag/counter;
          
        }
 
        CF = sqrtf( CF_real*CF_real + CF_imag*CF_imag );
        p_xyz[nx+NX*ny+nz*(NX*NY)] = sqrtf( voxel_int_real * voxel_int_real  + voxel_int_imag * voxel_int_imag ) * (CF);
}
	.file	"tmpxft_0038a682_00000000-6_PhasorField.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2010:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2010:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z65__device_stub__Z26ThreeD_NLOS_Phasor_GeneralPfS_S_S_S_S_ffiiifiifPfS_S_S_S_S_ffiiifiif
	.type	_Z65__device_stub__Z26ThreeD_NLOS_Phasor_GeneralPfS_S_S_S_S_ffiiifiifPfS_S_S_S_S_ffiiifiif, @function
_Z65__device_stub__Z26ThreeD_NLOS_Phasor_GeneralPfS_S_S_S_S_ffiiifiifPfS_S_S_S_S_ffiiifiif:
.LFB2032:
	.cfi_startproc
	endbr64
	subq	$264, %rsp
	.cfi_def_cfa_offset 272
	movq	%rdi, 56(%rsp)
	leaq	80(%rsp), %rdi
	movq	%rsi, 48(%rsp)
	leaq	92(%rsp), %rsi
	movq	%rdx, 40(%rsp)
	leaq	64(%rsp), %rdx
	movq	%rcx, 32(%rsp)
	leaq	72(%rsp), %rcx
	movq	%r8, 24(%rsp)
	movq	%r9, 16(%rsp)
	movss	%xmm0, 12(%rsp)
	movss	%xmm1, 8(%rsp)
	movss	%xmm2, 4(%rsp)
	movss	%xmm3, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 248(%rsp)
	xorl	%eax, %eax
	leaq	56(%rsp), %rax
	movl	$1, 88(%rsp)
	movq	%rax, 128(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	272(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	280(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	288(%rsp), %rax
	movq	%rax, 208(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 216(%rsp)
	leaq	296(%rsp), %rax
	movq	%rax, 224(%rsp)
	leaq	304(%rsp), %rax
	movq	%rax, 232(%rsp)
	movq	%rsp, %rax
	movq	%rax, 240(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 80(%rsp)
	movq	%rax, 92(%rsp)
	movl	$1, 100(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	72(%rsp)
	.cfi_def_cfa_offset 280
	leaq	_Z26ThreeD_NLOS_Phasor_GeneralPfS_S_S_S_S_ffiiifiif(%rip), %rdi
	pushq	72(%rsp)
	.cfi_def_cfa_offset 288
	movq	108(%rsp), %rcx
	movl	116(%rsp), %r8d
	movq	96(%rsp), %rsi
	movl	104(%rsp), %edx
	leaq	144(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 280
	popq	%rdx
	.cfi_def_cfa_offset 272
.L2:
	movq	248(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$264, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2032:
	.size	_Z65__device_stub__Z26ThreeD_NLOS_Phasor_GeneralPfS_S_S_S_S_ffiiifiifPfS_S_S_S_S_ffiiifiif, .-_Z65__device_stub__Z26ThreeD_NLOS_Phasor_GeneralPfS_S_S_S_S_ffiiifiifPfS_S_S_S_S_ffiiifiif
	.globl	_Z26ThreeD_NLOS_Phasor_GeneralPfS_S_S_S_S_ffiiifiif
	.type	_Z26ThreeD_NLOS_Phasor_GeneralPfS_S_S_S_S_ffiiifiif, @function
_Z26ThreeD_NLOS_Phasor_GeneralPfS_S_S_S_S_ffiiifiif:
.LFB2033:
	.cfi_startproc
	endbr64
	jmp	_Z65__device_stub__Z26ThreeD_NLOS_Phasor_GeneralPfS_S_S_S_S_ffiiifiifPfS_S_S_S_S_ffiiifiif
	.cfi_endproc
.LFE2033:
	.size	_Z26ThreeD_NLOS_Phasor_GeneralPfS_S_S_S_S_ffiiifiif, .-_Z26ThreeD_NLOS_Phasor_GeneralPfS_S_S_S_S_ffiiifiif
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z26ThreeD_NLOS_Phasor_GeneralPfS_S_S_S_S_ffiiifiif"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2035:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z26ThreeD_NLOS_Phasor_GeneralPfS_S_S_S_S_ffiiifiif(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2035:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
// ****
// Implement the phasor method using complex data rather than two times reconstruction
// ****
#define NPOINT 1
#define STRIDE 1
/*__global__ void ThreeD_NLOS_Phasor_General( float* p_xyz,  float* p_xyt_real,  float* p_xyt_imag,   
    float* sensor_pos, float* origin, float* laser_pos,  float dx,  float dz,  int NX,  int NY, int NZ, 
    float c_dt,  int N_pos, int Nt,  float ReceiveDelay)
{
        int nz = blockIdx.z * blockDim.z + threadIdx.z; // the nz-column, which is the time direction
        int ny = blockIdx.y * blockDim.y + threadIdx.y; // the ny-col
        int nx = blockIdx.x * blockDim.x + threadIdx.x; // the nx-row
        float CF_real = 0.0, CF_imag = 0.0, CF = 0.0;
        float tao = 0.0;
        float voxel_int_real = 0.0, voxel_int_imag =0.0;
        float voxel_real = 0.0, voxel_imag =0.0;
        int Index = 0, counter = 1;
        float GPS_x = origin[0] - (nx-NX/2)*dx;    // x-coordiante for the voxel
        float GPS_y = origin[1] + (ny-NY/2)*dx;    // y-coordiante for the voxel
        float GPS_z = origin[2] + (nz)*dz;         // z-coordiante for the voxel
        // time delay from the laser spot to the voxel
        float tao_trans = sqrtf( (laser_pos[0]-GPS_x)*(laser_pos[0]-GPS_x) + (laser_pos[1]-GPS_y)*(laser_pos[1]-GPS_y) + (laser_pos[2]-GPS_z)*(laser_pos[2]-GPS_z) );
        float x_pos,y_pos,z_pos, cos_theta;
        float voxel_int_real_tp[NPOINT], voxel_int_imag_tp[NPOINT],  voxel_sq_real_tp[NPOINT], voxel_sq_imag_tp[NPOINT];
        
        for(int K = 0; K<NPOINT; K++)
        {
            voxel_int_real_tp[K] = 0.0;
            voxel_int_imag_tp[K] = 0.0;
            voxel_sq_real_tp[K] = 0.0;
            voxel_sq_imag_tp[K] = 0.0;
        }
        
        for(int K_x = 0;K_x<N_pos; K_x++)
        {
              x_pos = sensor_pos[K_x];
              y_pos = sensor_pos[K_x+N_pos];
              z_pos = sensor_pos[K_x+2*N_pos];
              tao = sqrtf( (x_pos-GPS_x) * (x_pos-GPS_x) + (y_pos-GPS_y)*(y_pos-GPS_y) + (z_pos-GPS_z)*(z_pos-GPS_z) );
              cos_theta = GPS_z/(tao + 1e-6);
              Index = int( floorf((tao + tao_trans)/c_dt-ReceiveDelay) );
              if((Index<Nt-NPOINT*STRIDE) && (Index>0))
              {
                  for(int P = 0; P<NPOINT; P++)
                    {
                        voxel_real = p_xyt_real[Index+K_x*(Nt)+P*STRIDE] * cos_theta;
                        voxel_imag = p_xyt_imag[Index+K_x*(Nt)+P*STRIDE] * cos_theta;                         
                        voxel_int_real_tp[P] = voxel_int_real_tp[P] + voxel_real;    //* sqrt(Index*1.0);
                        voxel_int_imag_tp[P] = voxel_int_imag_tp[P] + voxel_imag;    //* sqrt(Index*1.0);
                        voxel_sq_real_tp[P] = voxel_sq_real_tp[P] + voxel_real * voxel_real;
                        voxel_sq_imag_tp[P] = voxel_sq_imag_tp[P] + voxel_imag * voxel_imag;
                    }
                    counter = counter+1;
              }
        }
        
        voxel_int_real = voxel_int_real_tp[0]; 
        voxel_int_imag = voxel_int_imag_tp[0];
        
        
        for (int J=0;J<NPOINT;J++)
        {
    
            if((voxel_sq_real_tp[J]>1e-6) && (voxel_sq_imag_tp[J]>1e-6))
            {
              CF_real = CF_real + powf(voxel_int_real_tp[J],2)/voxel_sq_real_tp[J]/counter;
              CF_imag = CF_imag + powf(voxel_int_imag_tp[J],2)/voxel_sq_imag_tp[J]/counter;
              
            }
        }
        CF = sqrtf( CF_real*CF_real + CF_imag*CF_imag );
        p_xyz[nx+NX*ny+nz*(NX*NY)] = sqrtf( voxel_int_real * voxel_int_real  + voxel_int_imag * voxel_int_imag ) * (CF);
}*/

// ****
// Implement the phasor method using complex data rather than two times reconstruction
// ****
#define NPOINT 1
#define STRIDE 1
__global__ void ThreeD_NLOS_Phasor_General( float* p_xyz,  float* p_xyt_real,  float* p_xyt_imag,   
    float* sensor_pos, float* origin, float* laser_pos,  float dx,  float dz,  int NX,  int NY, int NZ, 
    float c_dt,  int N_pos, int Nt,  float ReceiveDelay)
{
        int nz = blockIdx.z * blockDim.z + threadIdx.z; // the nz-column, which is the time direction
        int ny = blockIdx.y * blockDim.y + threadIdx.y; // the ny-col
        int nx = blockIdx.x * blockDim.x + threadIdx.x; // the nx-row
        float CF_real = 0.0, CF_imag = 0.0, CF = 0.0;
        float tao = 0.0;
        float voxel_int_real = 0.0, voxel_int_imag =0.0;
        float voxel_real = 0.0, voxel_imag =0.0;
        int Index = 0, counter = 1;
        float GPS_x = origin[0] - (nx-NX/2)*dx;    // x-coordiante for the voxel
        float GPS_y = origin[1] + (ny-NY/2)*dx;    // y-coordiante for the voxel
        float GPS_z = origin[2] + (nz)*dz;         // z-coordiante for the voxel
        // time delay from the laser spot to the voxel
        float tao_trans = sqrtf( (laser_pos[0]-GPS_x)*(laser_pos[0]-GPS_x) + (laser_pos[1]-GPS_y)*(laser_pos[1]-GPS_y) + (laser_pos[2]-GPS_z)*(laser_pos[2]-GPS_z) );
        float x_pos,y_pos,z_pos, cos_theta;
        float  voxel_sq_real, voxel_sq_imag;
         
        for(int K_x = 0;K_x<N_pos; K_x++)
        {
              x_pos = sensor_pos[K_x];
              y_pos = sensor_pos[K_x+N_pos];
              z_pos = sensor_pos[K_x+2*N_pos];
              tao = sqrtf( (x_pos-GPS_x) * (x_pos-GPS_x) + (y_pos-GPS_y)*(y_pos-GPS_y) + (z_pos-GPS_z)*(z_pos-GPS_z) );
              cos_theta = GPS_z/(tao + 1e-6);
              Index = int( floorf((tao + tao_trans)/c_dt-ReceiveDelay) );
              if((Index<Nt) && (Index>0))
              {

                    voxel_real = p_xyt_real[Index+K_x*(Nt)] * cos_theta;
                    voxel_imag = p_xyt_imag[Index+K_x*(Nt)] * cos_theta;                         
                    voxel_int_real = voxel_int_real + voxel_real;    //* sqrt(Index*1.0);
                    voxel_int_imag = voxel_int_imag + voxel_imag;    //* sqrt(Index*1.0);
                    voxel_sq_real = voxel_sq_real + voxel_real * voxel_real;
                    voxel_sq_imag = voxel_sq_imag + voxel_imag * voxel_imag;
                    counter = counter+1;
              }
        }
              
        if((voxel_sq_real>1e-6) && (voxel_sq_imag>1e-6))
        {
          CF_real = CF_real + powf(voxel_int_real,2)/voxel_sq_real/counter;
          CF_imag = CF_imag + powf(voxel_int_imag,2)/voxel_sq_imag/counter;
          
        }
 
        CF = sqrtf( CF_real*CF_real + CF_imag*CF_imag );
        p_xyz[nx+NX*ny+nz*(NX*NY)] = sqrtf( voxel_int_real * voxel_int_real  + voxel_int_imag * voxel_int_imag ) * (CF);
}
	.text
	.file	"PhasorField.hip"
	.globl	_Z41__device_stub__ThreeD_NLOS_Phasor_GeneralPfS_S_S_S_S_ffiiifiif # -- Begin function _Z41__device_stub__ThreeD_NLOS_Phasor_GeneralPfS_S_S_S_S_ffiiifiif
	.type	_Z41__device_stub__ThreeD_NLOS_Phasor_GeneralPfS_S_S_S_S_ffiiifiif,@function
_Z41__device_stub__ThreeD_NLOS_Phasor_GeneralPfS_S_S_S_S_ffiiifiif: # @_Z41__device_stub__ThreeD_NLOS_Phasor_GeneralPfS_S_S_S_S_ffiiifiif
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$240, %rsp
	.cfi_def_cfa_offset 288
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	72(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	64(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	56(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	48(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	40(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	32(%rsp), %r8
	movq	%r9, (%r8)
	leaq	12(%rsp), %r9
	movss	%xmm0, (%r9)
	leaq	8(%rsp), %r10
	movss	%xmm1, (%r10)
	leaq	4(%rsp), %r11
	movss	%xmm2, (%r11)
	movq	%rsp, %r14
	movss	%xmm3, (%r14)
	leaq	112(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	movq	%r9, 48(%rbx)
	movq	%r10, 56(%rbx)
	leaq	288(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	296(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	304(%rsp), %rax
	movq	%rax, 80(%rbx)
	movq	%r11, 88(%rbx)
	leaq	312(%rsp), %rax
	movq	%rax, 96(%rbx)
	leaq	320(%rsp), %rax
	movq	%rax, 104(%rbx)
	movq	%r14, 112(%rbx)
	leaq	96(%rsp), %r14
	leaq	80(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z26ThreeD_NLOS_Phasor_GeneralPfS_S_S_S_S_ffiiifiif, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$256, %rsp                      # imm = 0x100
	.cfi_adjust_cfa_offset -256
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z41__device_stub__ThreeD_NLOS_Phasor_GeneralPfS_S_S_S_S_ffiiifiif, .Lfunc_end0-_Z41__device_stub__ThreeD_NLOS_Phasor_GeneralPfS_S_S_S_S_ffiiifiif
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z26ThreeD_NLOS_Phasor_GeneralPfS_S_S_S_S_ffiiifiif, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z26ThreeD_NLOS_Phasor_GeneralPfS_S_S_S_S_ffiiifiif,@object # @_Z26ThreeD_NLOS_Phasor_GeneralPfS_S_S_S_S_ffiiifiif
	.section	.rodata,"a",@progbits
	.globl	_Z26ThreeD_NLOS_Phasor_GeneralPfS_S_S_S_S_ffiiifiif
	.p2align	3, 0x0
_Z26ThreeD_NLOS_Phasor_GeneralPfS_S_S_S_S_ffiiifiif:
	.quad	_Z41__device_stub__ThreeD_NLOS_Phasor_GeneralPfS_S_S_S_S_ffiiifiif
	.size	_Z26ThreeD_NLOS_Phasor_GeneralPfS_S_S_S_S_ffiiifiif, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z26ThreeD_NLOS_Phasor_GeneralPfS_S_S_S_S_ffiiifiif"
	.size	.L__unnamed_1, 52

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z41__device_stub__ThreeD_NLOS_Phasor_GeneralPfS_S_S_S_S_ffiiifiif
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z26ThreeD_NLOS_Phasor_GeneralPfS_S_S_S_S_ffiiifiif
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z26ThreeD_NLOS_Phasor_GeneralPfS_S_S_S_S_ffiiifiif ; -- Begin function _Z26ThreeD_NLOS_Phasor_GeneralPfS_S_S_S_S_ffiiifiif
	.globl	_Z26ThreeD_NLOS_Phasor_GeneralPfS_S_S_S_S_ffiiifiif
	.p2align	8
	.type	_Z26ThreeD_NLOS_Phasor_GeneralPfS_S_S_S_S_ffiiifiif,@function
_Z26ThreeD_NLOS_Phasor_GeneralPfS_S_S_S_S_ffiiifiif: ; @_Z26ThreeD_NLOS_Phasor_GeneralPfS_S_S_S_S_ffiiifiif
; %bb.0:
	s_clause 0x3
	s_load_b64 s[2:3], s[0:1], 0x64
	s_load_b128 s[24:27], s[0:1], 0x44
	s_load_b256 s[4:11], s[0:1], 0x0
	s_load_b256 s[16:23], s[0:1], 0x20
	v_bfe_u32 v1, v0, 20, 10
	v_and_b32_e32 v6, 0x3ff, v0
	v_bfe_u32 v5, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_and_b32 s0, s3, 0xffff
	s_lshr_b32 s1, s2, 16
	s_and_b32 s2, s2, 0xffff
	v_mad_u64_u32 v[2:3], null, s15, s0, v[1:2]
	v_mad_u64_u32 v[0:1], null, s13, s2, v[6:7]
	v_mov_b32_e32 v1, 0
	v_mad_u64_u32 v[3:4], null, s14, s1, v[5:6]
	s_cmp_lt_i32 s25, 1
	s_mov_b32 s3, 0
	s_cbranch_scc1 .LBB0_6
; %bb.1:                                ; %.lr.ph
	s_clause 0x1
	s_load_b64 s[0:1], s[16:17], 0x0
	s_load_b32 s2, s[16:17], 0x8
	s_lshr_b32 s14, s22, 31
	s_load_b64 s[12:13], s[18:19], 0x0
	s_add_i32 s14, s22, s14
	s_lshr_b32 s15, s23, 31
	s_ashr_i32 s14, s14, 1
	s_add_i32 s15, s23, s15
	v_subrev_nc_u32_e32 v1, s14, v0
	s_ashr_i32 s14, s15, 1
	s_load_b32 s15, s[18:19], 0x8
	v_subrev_nc_u32_e32 v4, s14, v3
	s_mov_b64 s[16:17], s[10:11]
	v_cvt_f32_i32_e32 v1, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cvt_f32_i32_e32 v4, v4
	s_waitcnt lgkmcnt(0)
	v_fma_f32 v9, -v1, s20, s0
	v_cvt_f32_i32_e32 v1, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fma_f32 v10, v4, s20, s1
	s_mov_b32 s1, s3
	v_sub_f32_e32 v4, s12, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v11, v1, s21, s2
	v_sub_f32_e32 v1, s13, v10
	s_mov_b32 s2, s25
	s_mov_b32 s12, 0xa0b5ed8d
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v4, v4, v4 :: v_dual_sub_f32 v5, s15, v11
	s_mov_b32 s13, 0x3eb0c6f7
	s_lshl_b64 s[14:15], s[2:3], 2
	v_fmac_f32_e32 v4, v1, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v4, v5, v5
	v_mul_f32_e32 v1, 0x4f800000, v4
	v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v6, v4, v1, vcc_lo
	v_cvt_f64_f32_e32 v[4:5], v11
	v_sqrt_f32_e32 v1, v6
	s_waitcnt_depctr 0xfff
	v_add_nc_u32_e32 v7, -1, v1
	v_add_nc_u32_e32 v8, 1, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v12, -v7, v1, v6
	v_fma_f32 v13, -v8, v1, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cmp_ge_f32_e64 s0, 0, v12
	v_mov_b32_e32 v12, 1
	v_cndmask_b32_e64 v1, v1, v7, s0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_f32_e64 s0, 0, v13
	v_cndmask_b32_e64 v7, v1, v8, s0
	v_mov_b32_e32 v1, 0
	s_lshl_b32 s0, s25, 1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	s_mov_b32 s2, s0
	v_mul_f32_e32 v8, 0x37800000, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v7, v7, v8, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v6, 0x260
                                        ; implicit-def: $vgpr8
	v_dual_cndmask_b32 v13, v7, v6 :: v_dual_mov_b32 v6, 0
                                        ; implicit-def: $vgpr7
.LBB0_2:                                ; =>This Inner Loop Header: Depth=1
	s_add_u32 s18, s16, s14
	s_addc_u32 s19, s17, s15
	s_clause 0x1
	s_load_b32 s0, s[18:19], 0x0
	s_load_b32 s20, s[16:17], 0x0
	s_lshl_b64 s[18:19], s[2:3], 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	s_add_u32 s18, s10, s18
	s_addc_u32 s19, s11, s19
	s_load_b32 s18, s[18:19], 0x0
	s_waitcnt lgkmcnt(0)
	v_dual_sub_f32 v14, s0, v10 :: v_dual_sub_f32 v15, s20, v9
	v_mul_f32_e32 v14, v14, v14
	v_sub_f32_e32 v16, s18, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v14, v15, v15
	v_fmac_f32_e32 v14, v16, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v15, 0x4f800000, v14
	v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v14
	v_cndmask_b32_e32 v14, v14, v15, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_sqrt_f32_e32 v15, v14
	s_waitcnt_depctr 0xfff
	v_add_nc_u32_e32 v16, -1, v15
	v_add_nc_u32_e32 v17, 1, v15
	v_fma_f32 v18, -v16, v15, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v19, -v17, v15, v14
	v_cmp_ge_f32_e64 s0, 0, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v15, v15, v16, s0
	v_cmp_lt_f32_e64 s0, 0, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v15, v15, v17, s0
	v_mul_f32_e32 v16, 0x37800000, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v15, v15, v16, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v14, 0x260
	v_cndmask_b32_e32 v14, v15, v14, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v15, v13, v14
	v_div_scale_f32 v16, null, s24, s24, v15
	v_div_scale_f32 v19, vcc_lo, v15, s24, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v17, v16
	s_waitcnt_depctr 0xfff
	v_fma_f32 v18, -v16, v17, 1.0
	v_fmac_f32_e32 v17, v18, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v18, v19, v17
	v_fma_f32 v20, -v16, v18, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v18, v20, v17
	v_fma_f32 v16, -v16, v18, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v16, v16, v17, v18
	v_div_fixup_f32 v15, v16, s24, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_subrev_f32_e32 v15, s27, v15
	v_floor_f32_e32 v15, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_i32_f32_e32 v15, v15
	v_cmp_gt_i32_e32 vcc_lo, s26, v15
	v_cmp_lt_i32_e64 s0, 0, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s18, vcc_lo, s0
	s_and_saveexec_b32 s0, s18
	s_cbranch_execz .LBB0_4
; %bb.3:                                ;   in Loop: Header=BB0_2 Depth=1
	v_cvt_f64_f32_e32 v[16:17], v14
	v_add_nc_u32_e32 v14, s1, v15
	v_add_nc_u32_e32 v12, 1, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v15, 31, v14
	v_lshlrev_b64 v[14:15], 2, v[14:15]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v24, vcc_lo, s6, v14
	v_add_co_ci_u32_e32 v25, vcc_lo, s7, v15, vcc_lo
	v_add_co_u32 v14, vcc_lo, s8, v14
	v_add_co_ci_u32_e32 v15, vcc_lo, s9, v15, vcc_lo
	global_load_b32 v24, v[24:25], off
	global_load_b32 v25, v[14:15], off
	v_add_f64 v[16:17], v[16:17], s[12:13]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_scale_f64 v[18:19], null, v[16:17], v[16:17], v[4:5]
	v_rcp_f64_e32 v[20:21], v[18:19]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[22:23], -v[18:19], v[20:21], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f64 v[14:15], v[20:21], v[22:23], v[20:21]
	v_div_scale_f64 v[22:23], vcc_lo, v[4:5], v[16:17], v[4:5]
	v_fma_f64 v[20:21], -v[18:19], v[14:15], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[14:15], v[14:15], v[20:21], v[14:15]
	v_mul_f64 v[20:21], v[22:23], v[14:15]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[18:19], -v[18:19], v[20:21], v[22:23]
	v_div_fmas_f64 v[14:15], v[18:19], v[14:15], v[20:21]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f64 v[14:15], v[14:15], v[16:17], v[4:5]
	v_cvt_f32_f64_e32 v14, v[14:15]
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v15, v24, v14
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v16, v25, v14
	v_fmac_f32_e32 v1, v24, v14
	v_fmac_f32_e32 v6, v25, v14
	v_dual_fmac_f32 v8, v15, v15 :: v_dual_fmac_f32 v7, v16, v16
.LBB0_4:                                ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	s_add_i32 s25, s25, -1
	s_add_i32 s1, s1, s26
	s_add_i32 s2, s2, 1
	s_add_u32 s16, s16, 4
	s_addc_u32 s17, s17, 0
	s_cmp_eq_u32 s25, 0
	s_cbranch_scc0 .LBB0_2
; %bb.5:                                ; %._crit_edge.loopexit
	v_cvt_f32_i32_e32 v4, v12
	s_branch .LBB0_7
.LBB0_6:
	v_mov_b32_e32 v4, 1.0
	v_mov_b32_e32 v6, 0
                                        ; implicit-def: $vgpr7
                                        ; implicit-def: $vgpr8
.LBB0_7:                                ; %Flow
	v_cvt_f64_f32_e32 v[9:10], v8
	v_cvt_f64_f32_e32 v[11:12], v7
	s_mov_b32 s0, 0xa0b5ed8d
	s_mov_b32 s1, 0x3eb0c6f7
	v_mov_b32_e32 v5, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_lt_f64_e32 vcc_lo, s[0:1], v[9:10]
	v_cmp_lt_f64_e64 s0, s[0:1], v[11:12]
	v_mov_b32_e32 v9, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, vcc_lo, s0
	s_and_saveexec_b32 s3, s0
	s_cbranch_execz .LBB0_9
; %bb.8:
	v_frexp_mant_f32_e64 v5, |v1|
	s_mov_b32 s1, 0x3e76c4e1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_gt_f32_e32 vcc_lo, 0x3f2aaaab, v5
	v_cndmask_b32_e64 v9, 0, 1, vcc_lo
	v_ldexp_f32 v5, v5, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f32_e32 v11, -1.0, v5
	v_add_f32_e32 v9, 1.0, v5
	v_rcp_f32_e32 v10, v9
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v12, v11, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v14, v9, v12 :: v_dual_add_f32 v13, -1.0, v9
	v_fma_f32 v9, v12, v9, -v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v5, v5, v13
	v_frexp_mant_f32_e64 v13, |v6|
	v_fmac_f32_e32 v9, v12, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_f32_e64 s0, 0x3f2aaaab, v13
	v_add_f32_e32 v15, v14, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v5, 0, 1, s0
	v_sub_f32_e32 v14, v15, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_ldexp_f32 v5, v13, v5
	v_sub_f32_e32 v13, v11, v15
	v_sub_f32_e32 v9, v14, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v16, 1.0, v5
	v_sub_f32_e32 v11, v11, v13
	v_add_f32_e32 v14, -1.0, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rcp_f32_e32 v17, v16
	v_sub_f32_e32 v11, v11, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
	v_add_f32_e32 v9, v9, v11
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v11, v14, v17
	v_add_f32_e32 v9, v13, v9
	v_add_f32_e32 v13, -1.0, v16
	v_mul_f32_e32 v9, v10, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v5, v5, v13
	v_add_f32_e32 v13, v12, v9
	v_mul_f32_e32 v15, v16, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v10, v11, v16, -v15
	v_mul_f32_e32 v16, v13, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_fmac_f32 v10, v11, v5 :: v_dual_sub_f32 v5, v13, v12
	v_fma_f32 v18, v13, v13, -v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v12, v15, v10 :: v_dual_sub_f32 v5, v9, v5
	v_sub_f32_e32 v9, v14, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v19, v5, v5
	v_dual_sub_f32 v15, v12, v15 :: v_dual_sub_f32 v14, v14, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v18, v13, v19
	v_sub_f32_e32 v10, v15, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v12, v14, v12
	v_add_f32_e32 v14, v16, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v10, v10, v12
	v_fmaak_f32 v12, s1, v14, 0x3e91f4c4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_add_f32 v9, v9, v10 :: v_dual_fmaak_f32 v10, v14, v12, 0x3ecccdef
	v_dual_sub_f32 v12, v14, v16 :: v_dual_mul_f32 v21, v13, v14
	v_mul_f32_e32 v9, v17, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v15, v14, v10
	v_sub_f32_e32 v12, v18, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v16, v11, v9
	v_fma_f32 v17, v14, v10, -v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v17, v12, v10
	v_mul_f32_e32 v10, v16, v16
	v_sub_f32_e32 v11, v16, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v18, v16, v16, -v10
	v_sub_f32_e32 v9, v9, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v19, v9, v9
	v_fmac_f32_e32 v18, v16, v19
	v_fma_f32 v19, v14, v13, -v21
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v22, v10, v18
	v_fmac_f32_e32 v19, v14, v5
	v_ldexp_f32 v5, v5, 1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_fmaak_f32 v14, s1, v22, 0x3e91f4c4 :: v_dual_fmac_f32 v19, v12, v13
	v_sub_f32_e32 v10, v22, v10
	v_fmaak_f32 v12, v22, v14, 0x3ecccdef
	v_frexp_exp_i32_f32_e32 v14, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v10, v18, v10
	v_mul_f32_e32 v23, v22, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_subrev_co_ci_u32_e32 v14, vcc_lo, 0, v14, vcc_lo
	v_fma_f32 v18, v22, v12, -v23
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_f32_i32_e32 v14, v14
	v_dual_fmac_f32 v18, v10, v12 :: v_dual_add_f32 v11, v15, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v15, v11, v15
	v_add_f32_e32 v20, 0x3f2aaaaa, v11
	v_sub_f32_e32 v15, v17, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v17, 0xbf2aaaaa, v20
	v_add_f32_e32 v15, 0x31739010, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v11, v11, v17
	v_add_f32_e32 v17, v21, v19
	v_add_f32_e32 v11, v15, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v21, v17, v21
	v_dual_add_f32 v15, v20, v11 :: v_dual_sub_f32 v12, v19, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v20, v20, v15
	v_dual_mul_f32 v24, v17, v15 :: v_dual_add_f32 v11, v11, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v20, v17, v15, -v24
	v_dual_fmac_f32 v20, v17, v11 :: v_dual_add_f32 v11, v23, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v20, v12, v15
	v_ldexp_f32 v12, v13, 1
	v_mul_f32_e32 v13, v16, v22
	v_sub_f32_e32 v15, v11, v23
	v_add_f32_e32 v19, 0x3f2aaaaa, v11
	v_add_f32_e32 v21, v24, v20
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f32 v23, v22, v16, -v13
	v_sub_f32_e32 v15, v18, v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_add_f32 v18, 0xbf2aaaaa, v19 :: v_dual_add_f32 v25, v12, v21
	v_dual_sub_f32 v24, v21, v24 :: v_dual_fmac_f32 v23, v22, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v15, 0x31739010, v15
	v_dual_sub_f32 v11, v11, v18 :: v_dual_sub_f32 v12, v25, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v18, v20, v24
	v_fmac_f32_e32 v23, v10, v16
	v_ldexp_f32 v9, v9, 1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_add_f32 v10, v15, v11 :: v_dual_sub_f32 v11, v21, v12
	v_add_f32_e32 v5, v5, v18
	v_frexp_exp_i32_f32_e32 v21, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_add_f32 v12, v19, v10 :: v_dual_add_f32 v5, v5, v11
	v_subrev_co_ci_u32_e64 v21, vcc_lo, 0, v21, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v15, v19, v12
	v_cmp_eq_f32_e32 vcc_lo, 1.0, v1
	v_add_f32_e32 v19, v25, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v17, 0x3f317218, v14 :: v_dual_add_f32 v10, v10, v15
	v_fma_f32 v20, 0x3f317218, v14, -v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v20, 0xb102e308, v14
	v_add_f32_e32 v14, v13, v23
	v_mul_f32_e32 v18, v14, v12
	v_sub_f32_e32 v13, v14, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v15, v14, v12, -v18
	v_sub_f32_e32 v13, v23, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_dual_fmac_f32 v15, v14, v10 :: v_dual_sub_f32 v14, v19, v25
	v_add_f32_e32 v11, v17, v20
	v_cvt_f32_i32_e32 v10, v21
	v_fmac_f32_e32 v15, v13, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_dual_sub_f32 v5, v5, v14 :: v_dual_add_f32 v22, v11, v19
	v_sub_f32_e32 v17, v11, v17
	v_ldexp_f32 v12, v16, 1
	v_add_f32_e32 v14, v18, v15
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_mul_f32 v16, 0x3f317218, v10 :: v_dual_sub_f32 v23, v22, v11
	v_dual_sub_f32 v17, v20, v17 :: v_dual_sub_f32 v18, v14, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v20, v22, v23
	v_sub_f32_e32 v13, v19, v23
	v_add_f32_e32 v19, v17, v5
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v15, v15, v18
	v_fma_f32 v18, 0x3f317218, v10, -v16
	v_sub_f32_e32 v11, v11, v20
	v_dual_sub_f32 v20, v19, v17 :: v_dual_add_f32 v9, v9, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_fmac_f32 v18, 0xb102e308, v10 :: v_dual_add_f32 v11, v13, v11
	v_add_f32_e32 v13, v12, v14
	v_sub_f32_e32 v5, v5, v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_add_f32 v11, v19, v11 :: v_dual_sub_f32 v12, v13, v12
	v_sub_f32_e32 v19, v19, v20
	v_add_f32_e32 v21, v22, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v12, v14, v12
	v_sub_f32_e32 v14, v17, v19
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v15, v21, v22
	v_add_f32_e32 v9, v9, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_add_f32 v5, v5, v14 :: v_dual_sub_f32 v10, v11, v15
	v_dual_add_f32 v11, v16, v18 :: v_dual_add_f32 v12, v13, v9
	v_cndmask_b32_e64 v15, 2.0, 1.0, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_add_f32 v5, v5, v10 :: v_dual_sub_f32 v16, v11, v16
	v_dual_add_f32 v10, v11, v12 :: v_dual_sub_f32 v13, v12, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v14, v21, v5
	v_sub_f32_e32 v16, v18, v16
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v17, v10, v11
	v_sub_f32_e32 v9, v9, v13
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_sub_f32 v19, v14, v21 :: v_dual_mul_f32 v20, v15, v14
	v_sub_f32_e32 v18, v10, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_sub_f32 v12, v12, v17 :: v_dual_sub_f32 v5, v5, v19
	v_fma_f32 v14, v15, v14, -v20
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v11, v11, v18
	v_cmp_class_f32_e64 vcc_lo, v20, 0x204
	v_dual_fmac_f32 v14, v15, v5 :: v_dual_add_f32 v11, v12, v11
	v_add_f32_e32 v5, v16, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_add_f32 v12, v20, v14 :: v_dual_sub_f32 v13, v5, v16
	v_add_f32_e32 v11, v5, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v17, v12, v20, vcc_lo
	v_dual_sub_f32 v12, v12, v20 :: v_dual_sub_f32 v5, v5, v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_add_f32 v18, v10, v11 :: v_dual_sub_f32 v9, v9, v13
	v_cmp_eq_f32_e32 vcc_lo, 0x42b17218, v17
	v_cmp_neq_f32_e64 s0, 0x7f800000, |v17|
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_dual_sub_f32 v5, v16, v5 :: v_dual_sub_f32 v10, v18, v10
	v_mul_f32_e32 v20, 0.5, v15
	v_cndmask_b32_e64 v19, 0, 0x37000000, vcc_lo
	v_cmp_eq_f32_e32 vcc_lo, 1.0, v6
	v_add_f32_e32 v5, v9, v5
	v_sub_f32_e32 v9, v11, v10
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v13, v17, v19
	v_cndmask_b32_e64 v21, 2.0, 1.0, vcc_lo
	v_add_f32_e32 v5, v5, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v10, 0x3fb8aa3b, v13
	v_add_f32_e32 v16, v18, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v9, 0x3fb8aa3b, v13, -v10
	v_rndne_f32_e32 v11, v10
	v_dual_sub_f32 v18, v16, v18 :: v_dual_fmac_f32 v9, 0x32a5705f, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v10, v10, v11
	v_cvt_i32_f32_e32 v11, v11
	v_sub_f32_e32 v5, v5, v18
	v_trunc_f32_e32 v18, v15
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_add_f32 v9, v10, v9 :: v_dual_mul_f32 v10, v21, v16
	v_cmp_eq_f32_e32 vcc_lo, v18, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_exp_f32_e32 v9, v9
	v_fma_f32 v16, v21, v16, -v10
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_fmac_f32 v16, v21, v5 :: v_dual_sub_f32 v5, v14, v12
	v_trunc_f32_e32 v12, v20
	s_waitcnt_depctr 0xfff
	v_ldexp_f32 v9, v9, v11
	v_add_f32_e32 v11, v10, v16
	v_cndmask_b32_e64 v5, 0, v5, s0
	v_cmp_ngt_f32_e64 s0, 0xc2ce8ed0, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v5, v19, v5
	v_cndmask_b32_e64 v9, 0, v9, s0
	v_cmp_class_f32_e64 s0, v10, 0x204
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v14, v11, v10, s0
	v_cmp_nlt_f32_e64 s0, 0x42b17218, v13
	v_sub_f32_e32 v10, v11, v10
	v_cmp_eq_f32_e64 s1, 0x42b17218, v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v9, 0x7f800000, v9, s0
	v_cmp_neq_f32_e64 s0, v12, v20
	v_sub_f32_e32 v10, v16, v10
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v12, 0, 0x37000000, s1
	v_fma_f32 v5, v9, v5, v9
	v_cmp_eq_f32_e64 s1, 0x7f800000, v9
	s_and_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v13, 1.0, v1, s0
	v_sub_f32_e32 v15, v14, v12
	v_cndmask_b32_e64 v5, v5, v9, s1
	v_cmp_eq_f32_e64 s1, 0, v1
	v_cndmask_b32_e64 v17, 0, v1, s0
	v_cmp_class_f32_e64 s0, v1, 0x204
	v_mul_f32_e32 v9, 0x3fb8aa3b, v15
	v_bfi_b32 v5, 0x7fffffff, v5, v13
	v_cndmask_b32_e64 v13, 0x7f800000, 0, s1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v19, 0x3fb8aa3b, v15, -v9
	v_cndmask_b32_e32 v18, 0x7fc00000, v5, vcc_lo
	v_cmp_gt_f32_e32 vcc_lo, 0, v1
	v_rndne_f32_e32 v20, v9
	v_bfi_b32 v13, 0x7fffffff, v13, v17
	v_fmac_f32_e32 v19, 0x32a5705f, v15
	v_cndmask_b32_e32 v5, v5, v18, vcc_lo
	s_delay_alu instid0(VALU_DEP_4)
	v_sub_f32_e32 v9, v9, v20
	s_or_b32 vcc_lo, s1, s0
	v_cvt_i32_f32_e32 v17, v20
	v_cmp_ngt_f32_e64 s0, 0xc2ce8ed0, v15
	v_cndmask_b32_e32 v5, v5, v13, vcc_lo
	v_cmp_o_f32_e32 vcc_lo, v1, v1
	v_add_f32_e32 v9, v9, v19
	v_mul_f32_e32 v13, 0.5, v21
	v_cmp_nlt_f32_e64 s1, 0x42b17218, v15
	v_trunc_f32_e32 v18, v21
	v_cndmask_b32_e32 v5, 0x7fc00000, v5, vcc_lo
	v_exp_f32_e32 v9, v9
	v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v14|
	v_trunc_f32_e32 v19, v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_div_scale_f32 v11, null, v8, v8, v5
	v_cndmask_b32_e32 v10, 0, v10, vcc_lo
	v_cmp_eq_f32_e32 vcc_lo, v18, v21
	v_rcp_f32_e32 v16, v11
	s_delay_alu instid0(TRANS32_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_ldexp_f32 v9, v9, v17
	v_add_f32_e32 v10, v12, v10
	s_delay_alu instid0(VALU_DEP_2)
	v_cndmask_b32_e64 v9, 0, v9, s0
	v_cmp_neq_f32_e64 s0, v19, v13
	s_waitcnt_depctr 0xfff
	v_fma_f32 v12, -v11, v16, 1.0
	v_cndmask_b32_e64 v9, 0x7f800000, v9, s1
	v_div_scale_f32 v13, s1, v5, v8, v5
	s_and_b32 s0, vcc_lo, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v16, v12, v16
	v_fma_f32 v10, v9, v10, v9
	v_cmp_eq_f32_e64 s2, 0x7f800000, v9
	v_cndmask_b32_e64 v12, 1.0, v6, s0
	v_cndmask_b32_e64 v15, 0, v6, s0
	v_mul_f32_e32 v14, v13, v16
	v_cmp_class_f32_e64 s0, v6, 0x204
	v_cndmask_b32_e64 v9, v10, v9, s2
	v_cmp_eq_f32_e64 s2, 0, v6
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v10, -v11, v14, v13
	v_bfi_b32 v9, 0x7fffffff, v9, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v12, 0x7f800000, 0, s2
	v_fmac_f32_e32 v14, v10, v16
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cndmask_b32_e32 v10, 0x7fc00000, v9, vcc_lo
	v_cmp_gt_f32_e32 vcc_lo, 0, v6
	v_bfi_b32 v12, 0x7fffffff, v12, v15
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f32 v11, -v11, v14, v13
	v_cndmask_b32_e32 v9, v9, v10, vcc_lo
	s_mov_b32 vcc_lo, s1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_fmas_f32 v10, v11, v16, v14
	s_or_b32 vcc_lo, s2, s0
	v_cndmask_b32_e32 v9, v9, v12, vcc_lo
	v_cmp_o_f32_e32 vcc_lo, v6, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_div_fixup_f32 v5, v10, v8, v5
	v_cndmask_b32_e32 v8, 0x7fc00000, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_div_scale_f32 v9, null, v4, v4, v5
	v_div_scale_f32 v15, vcc_lo, v5, v4, v5
	v_div_scale_f32 v10, null, v7, v7, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v11, v9
	v_rcp_f32_e32 v12, v10
	s_waitcnt_depctr 0xfff
	v_fma_f32 v13, -v9, v11, 1.0
	v_fma_f32 v14, -v10, v12, 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v11, v13, v11
	v_div_scale_f32 v13, s0, v8, v7, v8
	v_fmac_f32_e32 v12, v14, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v14, v15, v11
	v_mul_f32_e32 v16, v13, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v17, -v9, v14, v15
	v_fma_f32 v18, -v10, v16, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v14, v17, v11
	v_fmac_f32_e32 v16, v18, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v9, -v9, v14, v15
	v_fma_f32 v10, -v10, v16, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_fmas_f32 v9, v9, v11, v14
	s_mov_b32 vcc_lo, s0
	v_div_fmas_f32 v10, v10, v12, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fixup_f32 v5, v9, v4, v5
	v_div_fixup_f32 v7, v10, v7, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v9, 0, v5
	v_div_scale_f32 v8, null, v4, v4, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v10, v8
	s_waitcnt_depctr 0xfff
	v_fma_f32 v11, -v8, v10, 1.0
	v_fmac_f32_e32 v10, v11, v10
	v_div_scale_f32 v11, vcc_lo, v7, v4, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v12, v11, v10
	v_fma_f32 v13, -v8, v12, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v12, v13, v10
	v_fma_f32 v8, -v8, v12, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v8, v8, v10, v12
	v_div_fixup_f32 v4, v8, v4, v7
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f32_e32 v5, 0, v4
.LBB0_9:
	s_or_b32 exec_lo, exec_lo, s3
	v_mul_f32_e32 v1, v1, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v4, v9, v9 :: v_dual_fmac_f32 v1, v6, v6
	v_mul_f32_e32 v6, 0x4f800000, v1
	v_cmp_gt_f32_e64 s0, 0xf800000, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v6, v1, v6, s0
	v_sqrt_f32_e32 v8, v6
	s_waitcnt_depctr 0xfff
	v_dual_fmac_f32 v4, v5, v5 :: v_dual_add_nc_u32 v11, -1, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v5, 0x4f800000, v4
	v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v4
	v_dual_cndmask_b32 v7, v4, v5 :: v_dual_add_nc_u32 v12, 1, v8
	v_mad_u64_u32 v[4:5], null, v2, s23, v[3:4]
	v_fma_f32 v2, -v11, v8, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f32 v5, -v12, v8, v6
	v_sqrt_f32_e32 v1, v7
	s_waitcnt_depctr 0xfff
	v_add_nc_u32_e32 v9, -1, v1
	v_add_nc_u32_e32 v10, 1, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v13, -v9, v1, v7
	v_fma_f32 v3, -v10, v1, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_ge_f32_e64 s1, 0, v13
	v_cndmask_b32_e64 v1, v1, v9, s1
	v_cmp_ge_f32_e64 s1, 0, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v2, v8, v11, s1
	v_cmp_lt_f32_e64 s1, 0, v3
	v_cndmask_b32_e64 v3, v1, v10, s1
	v_cmp_lt_f32_e64 s1, 0, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v5, v2, v12, s1
	v_mad_u64_u32 v[1:2], null, v4, s22, v[0:1]
	v_mul_f32_e32 v0, 0x37800000, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v0, v3, v0, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v7, 0x260
	v_cndmask_b32_e32 v4, v0, v7, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v6, 0x260
	v_mul_f32_e32 v2, 0x37800000, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v3, v5, v2, s0
	v_ashrrev_i32_e32 v2, 31, v1
	v_cndmask_b32_e32 v3, v3, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	v_mul_f32_e32 v2, v3, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v0, vcc_lo, s4, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
	global_store_b32 v[0:1], v2, off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z26ThreeD_NLOS_Phasor_GeneralPfS_S_S_S_S_ffiiifiif
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 344
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 26
		.amdhsa_next_free_sgpr 28
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z26ThreeD_NLOS_Phasor_GeneralPfS_S_S_S_S_ffiiifiif, .Lfunc_end0-_Z26ThreeD_NLOS_Phasor_GeneralPfS_S_S_S_S_ffiiifiif
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 4016
; NumSgprs: 30
; NumVgprs: 26
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 3
; NumSGPRsForWavesPerEU: 30
; NumVGPRsForWavesPerEU: 26
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .offset:         48
        .size:           4
        .value_kind:     by_value
      - .offset:         52
        .size:           4
        .value_kind:     by_value
      - .offset:         56
        .size:           4
        .value_kind:     by_value
      - .offset:         60
        .size:           4
        .value_kind:     by_value
      - .offset:         64
        .size:           4
        .value_kind:     by_value
      - .offset:         68
        .size:           4
        .value_kind:     by_value
      - .offset:         72
        .size:           4
        .value_kind:     by_value
      - .offset:         76
        .size:           4
        .value_kind:     by_value
      - .offset:         80
        .size:           4
        .value_kind:     by_value
      - .offset:         88
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         92
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         96
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         100
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         102
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         104
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         106
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         108
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         110
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         128
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         136
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         144
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         152
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 344
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z26ThreeD_NLOS_Phasor_GeneralPfS_S_S_S_S_ffiiifiif
    .private_segment_fixed_size: 0
    .sgpr_count:     30
    .sgpr_spill_count: 0
    .symbol:         _Z26ThreeD_NLOS_Phasor_GeneralPfS_S_S_S_S_ffiiifiif.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     26
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
