#include "includes.h"
__global__ void update_mixed_derivatives(double *temppsix, double *temppsiy, double *temppsixy, unsigned int nx, unsigned int ny, double dx, double dy, unsigned int TileSize)
{
unsigned int bx = blockIdx.x;
unsigned int by = blockIdx.y;

unsigned int tx = threadIdx.x;
unsigned int ty = threadIdx.y;

unsigned int index_x = bx * TileSize + tx;
unsigned int index_y = by * TileSize + ty;

unsigned int indexToWrite = index_y * nx + index_x;

if ((index_y == 0 || index_y == ny - 1) && (index_x != 0 && index_x != nx - 1))
temppsixy[indexToWrite] = (temppsiy[indexToWrite+1] - temppsiy[indexToWrite-1])/(2 * dx);
else
if ((index_y != 0 && index_y != ny - 1) && (index_x == 0 || index_x == nx - 1))
temppsixy[indexToWrite] = (temppsix[indexToWrite + nx] - temppsix[indexToWrite - nx])/(2 * dy);
else
if((index_y == 0 || index_y == ny - 1) && (index_x == 0 || index_x == nx - 1)){
if(index_y == 0 && index_x == 0){
double d1 = (temppsiy[1] - temppsiy[0])/dx;
double d2 = (temppsix[nx] - temppsix[0])/dy;
double d3 = (temppsix[nx+1] - temppsix[1])/dy;
double d4 = (temppsiy[nx+1] - temppsiy[nx])/dx;
temppsixy[indexToWrite] = 0.75 * (d1 + d2) - 0.25 * (d3 + d4);
}
else if(index_y == 0 && index_x == nx-1){
double d1 = (temppsiy[nx-1] - temppsiy[nx-2])/dx;
double d2 = (temppsix[nx+nx-2] - temppsix[nx-2])/dy;
double d3 = (temppsix[nx+nx-1] - temppsix[nx-1])/dy;
double d4 = (temppsiy[nx+nx-1] - temppsiy[nx+nx-2])/dx;
temppsixy[indexToWrite] = 0.75 * (d1 + d3) - 0.25 * (d2 + d4);

}
else if(index_y == ny-1 && index_x == 0){
double d1 = (temppsiy[nx *(ny-2) + 1] - temppsiy[nx *(ny-2)])/dx;
double d2 = (temppsix[nx *(ny-1)] - temppsix[nx *(ny-2)])/dy;
double d3 = (temppsix[nx *(ny-1)] - temppsix[nx *(ny-2) + 1])/dy;
double d4 = (temppsiy[nx *(ny-1) + 1] - temppsiy[nx *(ny-1)])/dx;
temppsixy[indexToWrite] = 0.75 * (d2 + d4) - 0.25 * (d3 + d1);

}
else if(index_y == ny-1 && index_x == nx-1){
double d1 = (temppsiy[nx *(ny-2) + nx - 1] - temppsiy[nx *(ny-2) + nx - 2])/dx;
double d2 = (temppsix[nx *(ny-1) + nx - 2] - temppsix[nx *(ny-2) + nx - 2])/dy;
double d3 = (temppsix[nx *(ny-1) + nx - 1] - temppsix[nx *(ny-2) + nx - 1])/dy;
double d4 = (temppsiy[nx *(ny-1) + nx - 1] - temppsiy[nx *(ny-1) + nx - 2])/dx;
temppsixy[indexToWrite] = 0.75 * (d3 + d4) - 0.25 * (d1 + d2);
}
}
else{
double dxy1 = (temppsiy[indexToWrite+1] - temppsiy[indexToWrite-1])/(2 * dx);
double dxy2 = (temppsix[indexToWrite + nx] - temppsix[indexToWrite - nx])/(2 * dy);
temppsixy[indexToWrite] = (dxy1 + dxy2)/2.0;
}

}
	.file	"tmpxft_00334806_00000000-6_update_mixed_derivatives.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2010:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2010:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z53__device_stub__Z24update_mixed_derivativesPdS_S_jjddjPdS_S_jjddj
	.type	_Z53__device_stub__Z24update_mixed_derivativesPdS_S_jjddjPdS_S_jjddj, @function
_Z53__device_stub__Z24update_mixed_derivativesPdS_S_jjddjPdS_S_jjddj:
.LFB2032:
	.cfi_startproc
	endbr64
	subq	$216, %rsp
	.cfi_def_cfa_offset 224
	movq	%rdi, 56(%rsp)
	leaq	88(%rsp), %rdi
	movq	%rsi, 48(%rsp)
	leaq	100(%rsp), %rsi
	movq	%rdx, 40(%rsp)
	leaq	72(%rsp), %rdx
	movl	%ecx, 36(%rsp)
	leaq	80(%rsp), %rcx
	movl	%r8d, 32(%rsp)
	movl	%r9d, 12(%rsp)
	movsd	%xmm0, 24(%rsp)
	movsd	%xmm1, 16(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 200(%rsp)
	xorl	%eax, %eax
	leaq	56(%rsp), %rax
	movl	$1, 96(%rsp)
	movq	%rax, 136(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	36(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 192(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 88(%rsp)
	movq	%rax, 100(%rsp)
	movl	$1, 108(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	80(%rsp)
	.cfi_def_cfa_offset 232
	leaq	_Z24update_mixed_derivativesPdS_S_jjddj(%rip), %rdi
	pushq	80(%rsp)
	.cfi_def_cfa_offset 240
	movq	116(%rsp), %rcx
	movl	124(%rsp), %r8d
	movq	104(%rsp), %rsi
	movl	112(%rsp), %edx
	leaq	152(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 232
	popq	%rdx
	.cfi_def_cfa_offset 224
.L2:
	movq	200(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$216, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2032:
	.size	_Z53__device_stub__Z24update_mixed_derivativesPdS_S_jjddjPdS_S_jjddj, .-_Z53__device_stub__Z24update_mixed_derivativesPdS_S_jjddjPdS_S_jjddj
	.globl	_Z24update_mixed_derivativesPdS_S_jjddj
	.type	_Z24update_mixed_derivativesPdS_S_jjddj, @function
_Z24update_mixed_derivativesPdS_S_jjddj:
.LFB2033:
	.cfi_startproc
	endbr64
	jmp	_Z53__device_stub__Z24update_mixed_derivativesPdS_S_jjddjPdS_S_jjddj
	.cfi_endproc
.LFE2033:
	.size	_Z24update_mixed_derivativesPdS_S_jjddj, .-_Z24update_mixed_derivativesPdS_S_jjddj
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z24update_mixed_derivativesPdS_S_jjddj"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2035:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z24update_mixed_derivativesPdS_S_jjddj(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2035:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void update_mixed_derivatives(double *temppsix, double *temppsiy, double *temppsixy, unsigned int nx, unsigned int ny, double dx, double dy, unsigned int TileSize)
{
unsigned int bx = blockIdx.x;
unsigned int by = blockIdx.y;

unsigned int tx = threadIdx.x;
unsigned int ty = threadIdx.y;

unsigned int index_x = bx * TileSize + tx;
unsigned int index_y = by * TileSize + ty;

unsigned int indexToWrite = index_y * nx + index_x;

if ((index_y == 0 || index_y == ny - 1) && (index_x != 0 && index_x != nx - 1))
temppsixy[indexToWrite] = (temppsiy[indexToWrite+1] - temppsiy[indexToWrite-1])/(2 * dx);
else
if ((index_y != 0 && index_y != ny - 1) && (index_x == 0 || index_x == nx - 1))
temppsixy[indexToWrite] = (temppsix[indexToWrite + nx] - temppsix[indexToWrite - nx])/(2 * dy);
else
if((index_y == 0 || index_y == ny - 1) && (index_x == 0 || index_x == nx - 1)){
if(index_y == 0 && index_x == 0){
double d1 = (temppsiy[1] - temppsiy[0])/dx;
double d2 = (temppsix[nx] - temppsix[0])/dy;
double d3 = (temppsix[nx+1] - temppsix[1])/dy;
double d4 = (temppsiy[nx+1] - temppsiy[nx])/dx;
temppsixy[indexToWrite] = 0.75 * (d1 + d2) - 0.25 * (d3 + d4);
}
else if(index_y == 0 && index_x == nx-1){
double d1 = (temppsiy[nx-1] - temppsiy[nx-2])/dx;
double d2 = (temppsix[nx+nx-2] - temppsix[nx-2])/dy;
double d3 = (temppsix[nx+nx-1] - temppsix[nx-1])/dy;
double d4 = (temppsiy[nx+nx-1] - temppsiy[nx+nx-2])/dx;
temppsixy[indexToWrite] = 0.75 * (d1 + d3) - 0.25 * (d2 + d4);

}
else if(index_y == ny-1 && index_x == 0){
double d1 = (temppsiy[nx *(ny-2) + 1] - temppsiy[nx *(ny-2)])/dx;
double d2 = (temppsix[nx *(ny-1)] - temppsix[nx *(ny-2)])/dy;
double d3 = (temppsix[nx *(ny-1)] - temppsix[nx *(ny-2) + 1])/dy;
double d4 = (temppsiy[nx *(ny-1) + 1] - temppsiy[nx *(ny-1)])/dx;
temppsixy[indexToWrite] = 0.75 * (d2 + d4) - 0.25 * (d3 + d1);

}
else if(index_y == ny-1 && index_x == nx-1){
double d1 = (temppsiy[nx *(ny-2) + nx - 1] - temppsiy[nx *(ny-2) + nx - 2])/dx;
double d2 = (temppsix[nx *(ny-1) + nx - 2] - temppsix[nx *(ny-2) + nx - 2])/dy;
double d3 = (temppsix[nx *(ny-1) + nx - 1] - temppsix[nx *(ny-2) + nx - 1])/dy;
double d4 = (temppsiy[nx *(ny-1) + nx - 1] - temppsiy[nx *(ny-1) + nx - 2])/dx;
temppsixy[indexToWrite] = 0.75 * (d3 + d4) - 0.25 * (d1 + d2);
}
}
else{
double dxy1 = (temppsiy[indexToWrite+1] - temppsiy[indexToWrite-1])/(2 * dx);
double dxy2 = (temppsix[indexToWrite + nx] - temppsix[indexToWrite - nx])/(2 * dy);
temppsixy[indexToWrite] = (dxy1 + dxy2)/2.0;
}

}
	.text
	.file	"update_mixed_derivatives.hip"
	.globl	_Z39__device_stub__update_mixed_derivativesPdS_S_jjddj # -- Begin function _Z39__device_stub__update_mixed_derivativesPdS_S_jjddj
	.type	_Z39__device_stub__update_mixed_derivativesPdS_S_jjddj,@function
_Z39__device_stub__update_mixed_derivativesPdS_S_jjddj: # @_Z39__device_stub__update_mixed_derivativesPdS_S_jjddj
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$176, %rsp
	.cfi_def_cfa_offset 224
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	72(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	64(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	56(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	20(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	16(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	48(%rsp), %r8
	movsd	%xmm0, (%r8)
	leaq	40(%rsp), %r10
	movsd	%xmm1, (%r10)
	leaq	12(%rsp), %r11
	movl	%r9d, (%r11)
	leaq	112(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	movq	%r10, 48(%rbx)
	movq	%r11, 56(%rbx)
	leaq	96(%rsp), %r14
	leaq	80(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z24update_mixed_derivativesPdS_S_jjddj, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$192, %rsp
	.cfi_adjust_cfa_offset -192
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z39__device_stub__update_mixed_derivativesPdS_S_jjddj, .Lfunc_end0-_Z39__device_stub__update_mixed_derivativesPdS_S_jjddj
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z24update_mixed_derivativesPdS_S_jjddj, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z24update_mixed_derivativesPdS_S_jjddj,@object # @_Z24update_mixed_derivativesPdS_S_jjddj
	.section	.rodata,"a",@progbits
	.globl	_Z24update_mixed_derivativesPdS_S_jjddj
	.p2align	3, 0x0
_Z24update_mixed_derivativesPdS_S_jjddj:
	.quad	_Z39__device_stub__update_mixed_derivativesPdS_S_jjddj
	.size	_Z24update_mixed_derivativesPdS_S_jjddj, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z24update_mixed_derivativesPdS_S_jjddj"
	.size	.L__unnamed_1, 40

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z39__device_stub__update_mixed_derivativesPdS_S_jjddj
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z24update_mixed_derivativesPdS_S_jjddj
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z24update_mixed_derivativesPdS_S_jjddj ; -- Begin function _Z24update_mixed_derivativesPdS_S_jjddj
	.globl	_Z24update_mixed_derivativesPdS_S_jjddj
	.p2align	8
	.type	_Z24update_mixed_derivativesPdS_S_jjddj,@function
_Z24update_mixed_derivativesPdS_S_jjddj: ; @_Z24update_mixed_derivativesPdS_S_jjddj
; %bb.0:
	s_clause 0x3
	s_load_b32 s2, s[0:1], 0x30
	s_load_b128 s[4:7], s[0:1], 0x20
	s_load_b128 s[8:11], s[0:1], 0x0
	s_load_b64 s[16:17], s[0:1], 0x18
	v_bfe_u32 v1, v0, 10, 10
	v_and_b32_e32 v0, 0x3ff, v0
	s_mov_b32 s3, exec_lo
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[4:5], null, s15, s2, v[1:2]
	v_mad_u64_u32 v[2:3], null, s14, s2, v[0:1]
	s_mov_b32 s14, 0
	s_mov_b32 s15, 0
	s_delay_alu instid0(VALU_DEP_2)
	v_cmp_eq_u32_e64 s2, 0, v4
	v_cmpx_ne_u32_e32 0, v4
	s_xor_b32 s12, exec_lo, s3
; %bb.1:
	s_add_i32 s3, s17, -1
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, 0, v2
	v_cmp_eq_u32_e64 s3, s3, v4
	s_and_b32 s3, s3, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s13, s3, -1
	s_and_b32 s14, s3, exec_lo
	s_and_b32 s15, s13, exec_lo
; %bb.2:                                ; %Flow
	s_or_saveexec_b32 s3, s12
	s_load_b64 s[12:13], s[0:1], 0x10
	v_mul_lo_u32 v1, v4, s16
	s_xor_b32 exec_lo, exec_lo, s3
; %bb.3:
	v_cmp_eq_u32_e32 vcc_lo, 0, v2
	v_cmp_ne_u32_e64 s0, 0, v2
	s_and_not1_b32 s1, s15, exec_lo
	s_and_not1_b32 s14, s14, exec_lo
	s_and_b32 s15, vcc_lo, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 s0, s0, exec_lo
	s_or_b32 s15, s1, s15
	s_or_b32 s14, s14, s0
; %bb.4:                                ; %Flow252
	s_or_b32 exec_lo, exec_lo, s3
	v_add_nc_u32_e32 v0, v1, v2
	s_mov_b32 s3, 0
                                        ; implicit-def: $vgpr5_vgpr6
	s_and_saveexec_b32 s0, s14
	s_cbranch_execz .LBB0_8
; %bb.5:
	s_add_i32 s1, s16, -1
	s_mov_b32 s14, -1
	v_cmp_ne_u32_e32 vcc_lo, s1, v2
	s_mov_b32 s1, 0
                                        ; implicit-def: $vgpr5_vgpr6
	s_and_saveexec_b32 s3, vcc_lo
	s_cbranch_execz .LBB0_7
; %bb.6:
	v_dual_mov_b32 v6, 0 :: v_dual_add_nc_u32 v5, 1, v0
	v_add_f64 v[9:10], s[4:5], s[4:5]
	s_mov_b32 s1, exec_lo
	s_xor_b32 s14, exec_lo, -1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[7:8], 3, v[5:6]
	v_add_nc_u32_e32 v5, -1, v0
	v_lshlrev_b64 v[5:6], 3, v[5:6]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v7, vcc_lo, s10, v7
	v_add_co_ci_u32_e32 v8, vcc_lo, s11, v8, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v5, vcc_lo, s10, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, s11, v6, vcc_lo
	s_clause 0x1
	global_load_b64 v[7:8], v[7:8], off
	global_load_b64 v[5:6], v[5:6], off
	s_waitcnt vmcnt(0)
	v_add_f64 v[5:6], v[7:8], -v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_scale_f64 v[7:8], null, v[9:10], v[9:10], v[5:6]
	v_rcp_f64_e32 v[11:12], v[7:8]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[13:14], -v[7:8], v[11:12], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[11:12], v[11:12], v[13:14], v[11:12]
	v_fma_f64 v[13:14], -v[7:8], v[11:12], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f64 v[11:12], v[11:12], v[13:14], v[11:12]
	v_div_scale_f64 v[13:14], vcc_lo, v[5:6], v[9:10], v[5:6]
	v_mul_f64 v[15:16], v[13:14], v[11:12]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[7:8], -v[7:8], v[15:16], v[13:14]
	v_div_fmas_f64 v[7:8], v[7:8], v[11:12], v[15:16]
	s_delay_alu instid0(VALU_DEP_1)
	v_div_fixup_f64 v[5:6], v[7:8], v[9:10], v[5:6]
.LBB0_7:                                ; %Flow254
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 s15, s15, exec_lo
	s_and_b32 s14, s14, exec_lo
	s_and_b32 s3, s1, exec_lo
	s_or_b32 s15, s15, s14
.LBB0_8:                                ; %Flow253
	s_or_b32 exec_lo, exec_lo, s0
	s_and_saveexec_b32 s14, s15
	s_cbranch_execz .LBB0_34
; %bb.9:
	s_add_i32 s0, s17, -1
	s_mov_b32 s21, -1
	v_cmp_eq_u32_e64 s0, s0, v4
	s_mov_b32 s19, 0
	s_mov_b32 s20, 0
	s_mov_b32 s15, s3
                                        ; implicit-def: $vgpr5_vgpr6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s1, s2, s0
	s_xor_b32 s1, s1, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_saveexec_b32 s18, s1
	s_xor_b32 s18, exec_lo, s18
	s_cbranch_execz .LBB0_13
; %bb.10:
	s_add_i32 s1, s16, -1
	v_cmp_eq_u32_e32 vcc_lo, 0, v2
	v_cmp_eq_u32_e64 s1, s1, v2
	s_mov_b32 s15, s3
                                        ; implicit-def: $vgpr5_vgpr6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s20, vcc_lo, s1
	s_and_saveexec_b32 s1, s20
	s_cbranch_execz .LBB0_12
; %bb.11:
	v_dual_mov_b32 v6, 0 :: v_dual_add_nc_u32 v5, s16, v0
	v_add_f64 v[9:10], s[6:7], s[6:7]
	s_or_b32 s15, s3, exec_lo
	s_xor_b32 s21, exec_lo, -1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[7:8], 3, v[5:6]
	v_subrev_nc_u32_e32 v5, s16, v0
	v_lshlrev_b64 v[5:6], 3, v[5:6]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v7, vcc_lo, s8, v7
	v_add_co_ci_u32_e32 v8, vcc_lo, s9, v8, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v5, vcc_lo, s8, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, s9, v6, vcc_lo
	s_clause 0x1
	global_load_b64 v[7:8], v[7:8], off
	global_load_b64 v[5:6], v[5:6], off
	s_waitcnt vmcnt(0)
	v_add_f64 v[5:6], v[7:8], -v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_scale_f64 v[7:8], null, v[9:10], v[9:10], v[5:6]
	v_rcp_f64_e32 v[11:12], v[7:8]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[13:14], -v[7:8], v[11:12], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[11:12], v[11:12], v[13:14], v[11:12]
	v_fma_f64 v[13:14], -v[7:8], v[11:12], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f64 v[11:12], v[11:12], v[13:14], v[11:12]
	v_div_scale_f64 v[13:14], vcc_lo, v[5:6], v[9:10], v[5:6]
	v_mul_f64 v[15:16], v[13:14], v[11:12]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[7:8], -v[7:8], v[15:16], v[13:14]
	v_div_fmas_f64 v[7:8], v[7:8], v[11:12], v[15:16]
	s_delay_alu instid0(VALU_DEP_1)
	v_div_fixup_f64 v[5:6], v[7:8], v[9:10], v[5:6]
.LBB0_12:                               ; %Flow257
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 s1, s3, exec_lo
	s_and_b32 s15, s15, exec_lo
	s_and_b32 s20, s21, exec_lo
	s_or_b32 s15, s1, s15
.LBB0_13:                               ; %Flow256
	s_or_saveexec_b32 s18, s18
                                        ; implicit-def: $sgpr22
                                        ; implicit-def: $sgpr23
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 exec_lo, exec_lo, s18
; %bb.14:                               ; %.critedge
	s_add_i32 s1, s16, -1
	v_cmp_eq_u32_e32 vcc_lo, 0, v2
	v_cmp_eq_u32_e64 s1, s1, v2
	s_mov_b32 s19, exec_lo
                                        ; implicit-def: $vgpr5_vgpr6
	s_and_b32 s22, vcc_lo, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
	s_or_b32 s21, vcc_lo, s1
	s_and_b32 s23, s1, exec_lo
	s_xor_b32 s21, s21, -1
	s_and_not1_b32 s1, s20, exec_lo
	s_and_b32 s20, s21, exec_lo
	s_or_b32 s20, s1, s20
; %bb.15:                               ; %Flow258
	s_or_b32 exec_lo, exec_lo, s18
	s_and_saveexec_b32 s1, s20
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s18, exec_lo, s1
	s_cbranch_execz .LBB0_17
; %bb.16:
	v_dual_mov_b32 v6, 0 :: v_dual_add_nc_u32 v5, 1, v0
	v_add_f64 v[13:14], s[4:5], s[4:5]
	s_or_b32 s15, s15, exec_lo
	s_and_not1_b32 s19, s19, exec_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[7:8], 3, v[5:6]
	v_add_nc_u32_e32 v5, -1, v0
	v_lshlrev_b64 v[9:10], 3, v[5:6]
	v_add_nc_u32_e32 v5, s16, v0
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v7, vcc_lo, s10, v7
	v_add_co_ci_u32_e32 v8, vcc_lo, s11, v8, vcc_lo
	v_lshlrev_b64 v[11:12], 3, v[5:6]
	v_subrev_nc_u32_e32 v5, s16, v0
	v_add_co_u32 v9, vcc_lo, s10, v9
	v_add_co_ci_u32_e32 v10, vcc_lo, s11, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[5:6], 3, v[5:6]
	v_add_co_u32 v11, vcc_lo, s8, v11
	v_add_co_ci_u32_e32 v12, vcc_lo, s9, v12, vcc_lo
	v_add_co_u32 v5, vcc_lo, s8, v5
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v6, vcc_lo, s9, v6, vcc_lo
	s_clause 0x1
	global_load_b64 v[7:8], v[7:8], off
	global_load_b64 v[9:10], v[9:10], off
	s_clause 0x1
	global_load_b64 v[11:12], v[11:12], off
	global_load_b64 v[5:6], v[5:6], off
	s_waitcnt vmcnt(2)
	v_add_f64 v[7:8], v[7:8], -v[9:10]
	v_add_f64 v[9:10], s[6:7], s[6:7]
	s_waitcnt vmcnt(0)
	v_add_f64 v[5:6], v[11:12], -v[5:6]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_scale_f64 v[11:12], null, v[13:14], v[13:14], v[7:8]
	v_div_scale_f64 v[15:16], null, v[9:10], v[9:10], v[5:6]
	v_div_scale_f64 v[25:26], vcc_lo, v[7:8], v[13:14], v[7:8]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rcp_f64_e32 v[17:18], v[11:12]
	v_rcp_f64_e32 v[19:20], v[15:16]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[21:22], -v[11:12], v[17:18], 1.0
	v_fma_f64 v[23:24], -v[15:16], v[19:20], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[17:18], v[17:18], v[21:22], v[17:18]
	v_fma_f64 v[19:20], v[19:20], v[23:24], v[19:20]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[21:22], -v[11:12], v[17:18], 1.0
	v_fma_f64 v[23:24], -v[15:16], v[19:20], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fma_f64 v[17:18], v[17:18], v[21:22], v[17:18]
	v_div_scale_f64 v[21:22], s1, v[5:6], v[9:10], v[5:6]
	v_fma_f64 v[19:20], v[19:20], v[23:24], v[19:20]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[23:24], v[25:26], v[17:18]
	v_mul_f64 v[27:28], v[21:22], v[19:20]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[11:12], -v[11:12], v[23:24], v[25:26]
	v_fma_f64 v[15:16], -v[15:16], v[27:28], v[21:22]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_fmas_f64 v[11:12], v[11:12], v[17:18], v[23:24]
	s_mov_b32 vcc_lo, s1
	v_div_fmas_f64 v[15:16], v[15:16], v[19:20], v[27:28]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fixup_f64 v[7:8], v[11:12], v[13:14], v[7:8]
	v_div_fixup_f64 v[5:6], v[15:16], v[9:10], v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[5:6], v[7:8], v[5:6]
	v_mul_f64 v[5:6], v[5:6], 0.5
.LBB0_17:                               ; %Flow259
	s_or_b32 exec_lo, exec_lo, s18
	s_and_saveexec_b32 s18, s19
	s_cbranch_execz .LBB0_33
; %bb.18:
	v_or_b32_e32 v3, v4, v2
	s_mov_b32 s20, s15
                                        ; implicit-def: $vgpr5_vgpr6
	s_mov_b32 s1, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_ne_u32_e32 0, v3
	s_xor_b32 s19, exec_lo, s1
	s_cbranch_execz .LBB0_30
; %bb.19:
	s_and_b32 s1, s2, s23
	s_mov_b32 s21, s15
	s_xor_b32 s1, s1, -1
                                        ; implicit-def: $vgpr5_vgpr6
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_saveexec_b32 s2, s1
	s_xor_b32 s20, exec_lo, s2
	s_cbranch_execz .LBB0_27
; %bb.20:
	s_and_b32 s1, s0, s22
	s_mov_b32 s21, s15
	s_xor_b32 s1, s1, -1
                                        ; implicit-def: $vgpr5_vgpr6
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_saveexec_b32 s2, s1
	s_xor_b32 s22, exec_lo, s2
	s_cbranch_execz .LBB0_24
; %bb.21:
	s_and_b32 s1, s0, s23
	s_mov_b32 s0, s15
                                        ; implicit-def: $vgpr5_vgpr6
	s_and_saveexec_b32 s2, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s21, exec_lo, s2
	s_cbranch_execz .LBB0_23
; %bb.22:
	v_dual_mov_b32 v3, 0 :: v_dual_add_nc_u32 v2, -1, v1
	s_mul_i32 s2, s17, s16
	s_mov_b32 s1, 0
	s_add_i32 s0, s2, -2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_lshlrev_b64 v[4:5], 3, v[2:3]
	v_add_nc_u32_e32 v2, -2, v1
	s_lshl_b64 s[24:25], s[0:1], 3
	s_add_u32 s26, s8, s24
	s_addc_u32 s27, s9, s25
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[1:2], 3, v[2:3]
	v_add_co_u32 v6, vcc_lo, s10, v4
	v_add_co_ci_u32_e32 v7, vcc_lo, s11, v5, vcc_lo
	s_add_i32 s0, s2, -1
	v_add_co_u32 v8, vcc_lo, s10, v1
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v9, vcc_lo, s11, v2, vcc_lo
	v_add_co_u32 v1, vcc_lo, s8, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s9, v2, vcc_lo
	s_clause 0x1
	global_load_b64 v[6:7], v[6:7], off
	global_load_b64 v[8:9], v[8:9], off
	global_load_b64 v[1:2], v[1:2], off
	v_add_co_u32 v3, vcc_lo, s8, v4
	v_add_co_ci_u32_e32 v4, vcc_lo, s9, v5, vcc_lo
	s_load_b64 s[26:27], s[26:27], 0x0
	s_lshl_b64 s[0:1], s[0:1], 3
	global_load_b64 v[3:4], v[3:4], off
	s_add_u32 s28, s8, s0
	s_addc_u32 s29, s9, s1
	s_add_u32 s0, s10, s0
	s_load_b64 s[28:29], s[28:29], 0x0
	s_addc_u32 s1, s11, s1
	s_add_u32 s24, s10, s24
	s_addc_u32 s25, s11, s25
	s_clause 0x1
	s_load_b64 s[0:1], s[0:1], 0x0
	s_load_b64 s[24:25], s[24:25], 0x0
	s_waitcnt vmcnt(2)
	v_add_f64 v[5:6], v[6:7], -v[8:9]
	s_waitcnt vmcnt(1) lgkmcnt(0)
	v_add_f64 v[1:2], s[26:27], -v[1:2]
	v_add_f64 v[9:10], s[0:1], -s[24:25]
	s_waitcnt vmcnt(0)
	v_add_f64 v[3:4], s[28:29], -v[3:4]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_div_scale_f64 v[7:8], null, s[4:5], s[4:5], v[5:6]
	v_div_scale_f64 v[11:12], null, s[6:7], s[6:7], v[1:2]
	s_delay_alu instid0(VALU_DEP_4)
	v_div_scale_f64 v[17:18], null, s[4:5], s[4:5], v[9:10]
	v_div_scale_f64 v[31:32], vcc_lo, v[5:6], s[4:5], v[5:6]
	v_div_scale_f64 v[33:34], s0, v[1:2], s[6:7], v[1:2]
	v_div_scale_f64 v[13:14], null, s[6:7], s[6:7], v[3:4]
	v_rcp_f64_e32 v[15:16], v[7:8]
	v_rcp_f64_e32 v[19:20], v[11:12]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[23:24], v[17:18]
	v_rcp_f64_e32 v[21:22], v[13:14]
	v_fma_f64 v[25:26], -v[7:8], v[15:16], 1.0
	s_delay_alu instid0(TRANS32_DEP_3)
	v_fma_f64 v[27:28], -v[11:12], v[19:20], 1.0
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[29:30], -v[13:14], v[21:22], 1.0
	v_fma_f64 v[15:16], v[15:16], v[25:26], v[15:16]
	v_fma_f64 v[25:26], -v[17:18], v[23:24], 1.0
	v_fma_f64 v[19:20], v[19:20], v[27:28], v[19:20]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[21:22], v[21:22], v[29:30], v[21:22]
	v_fma_f64 v[27:28], -v[7:8], v[15:16], 1.0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[23:24], v[23:24], v[25:26], v[23:24]
	v_fma_f64 v[25:26], -v[11:12], v[19:20], 1.0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[29:30], -v[13:14], v[21:22], 1.0
	v_fma_f64 v[15:16], v[15:16], v[27:28], v[15:16]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[27:28], -v[17:18], v[23:24], 1.0
	v_fma_f64 v[19:20], v[19:20], v[25:26], v[19:20]
	v_div_scale_f64 v[25:26], s1, v[3:4], s[6:7], v[3:4]
	v_fma_f64 v[21:22], v[21:22], v[29:30], v[21:22]
	v_div_scale_f64 v[29:30], s2, v[9:10], s[4:5], v[9:10]
	v_mul_f64 v[35:36], v[31:32], v[15:16]
	v_fma_f64 v[23:24], v[23:24], v[27:28], v[23:24]
	v_mul_f64 v[27:28], v[33:34], v[19:20]
	v_mul_f64 v[37:38], v[25:26], v[21:22]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[7:8], -v[7:8], v[35:36], v[31:32]
	v_mul_f64 v[31:32], v[29:30], v[23:24]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[11:12], -v[11:12], v[27:28], v[33:34]
	v_fma_f64 v[13:14], -v[13:14], v[37:38], v[25:26]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_div_fmas_f64 v[7:8], v[7:8], v[15:16], v[35:36]
	s_mov_b32 vcc_lo, s0
	v_fma_f64 v[15:16], -v[17:18], v[31:32], v[29:30]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_div_fmas_f64 v[11:12], v[11:12], v[19:20], v[27:28]
	s_mov_b32 vcc_lo, s1
	s_or_b32 s0, s15, exec_lo
	v_div_fmas_f64 v[13:14], v[13:14], v[21:22], v[37:38]
	s_mov_b32 vcc_lo, s2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_div_fixup_f64 v[5:6], v[7:8], s[4:5], v[5:6]
	v_div_fmas_f64 v[7:8], v[15:16], v[23:24], v[31:32]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_div_fixup_f64 v[1:2], v[11:12], s[6:7], v[1:2]
	v_div_fixup_f64 v[3:4], v[13:14], s[6:7], v[3:4]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_div_fixup_f64 v[7:8], v[7:8], s[4:5], v[9:10]
	v_add_f64 v[1:2], v[5:6], v[1:2]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[3:4], v[3:4], v[7:8]
	v_ldexp_f64 v[1:2], -v[1:2], -2
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[5:6], 0x3fe80000, v[3:4], v[1:2]
.LBB0_23:                               ; %Flow264
	s_or_b32 exec_lo, exec_lo, s21
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_and_not1_b32 s1, s15, exec_lo
	s_and_b32 s0, s0, exec_lo
                                        ; implicit-def: $vgpr1
	s_or_b32 s21, s1, s0
.LBB0_24:                               ; %Flow263
	s_and_not1_saveexec_b32 s22, s22
	s_cbranch_execz .LBB0_26
; %bb.25:
	v_mov_b32_e32 v2, 0
	s_add_i32 s0, s17, -2
	s_mov_b32 s25, 0
	s_mul_i32 s0, s0, s16
	s_mov_b32 s1, s25
	v_lshlrev_b64 v[3:4], 3, v[1:2]
	v_add_nc_u32_e32 v1, 1, v1
	s_add_i32 s24, s0, 1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_lshl_b64 s[26:27], s[24:25], 3
	v_lshlrev_b64 v[1:2], 3, v[1:2]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_add_co_u32 v5, vcc_lo, s8, v3
	v_add_co_ci_u32_e32 v6, vcc_lo, s9, v4, vcc_lo
	s_add_u32 s24, s10, s26
	v_add_co_u32 v1, vcc_lo, s10, v1
	global_load_b64 v[5:6], v[5:6], off
	v_add_co_ci_u32_e32 v2, vcc_lo, s11, v2, vcc_lo
	v_add_co_u32 v3, vcc_lo, s10, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s11, v4, vcc_lo
	s_clause 0x1
	global_load_b64 v[1:2], v[1:2], off
	global_load_b64 v[3:4], v[3:4], off
	s_addc_u32 s25, s11, s27
	s_lshl_b64 s[0:1], s[0:1], 3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s28, s10, s0
	s_addc_u32 s29, s11, s1
	s_add_u32 s0, s8, s0
	s_clause 0x1
	s_load_b64 s[24:25], s[24:25], 0x0
	s_load_b64 s[28:29], s[28:29], 0x0
	s_addc_u32 s1, s9, s1
	s_add_u32 s26, s8, s26
	s_load_b64 s[0:1], s[0:1], 0x0
	s_addc_u32 s27, s9, s27
	s_or_b32 s21, s21, exec_lo
	s_load_b64 s[26:27], s[26:27], 0x0
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[7:8], s[24:25], -s[28:29]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f64 v[11:12], null, s[4:5], s[4:5], v[7:8]
	v_div_scale_f64 v[31:32], vcc_lo, v[7:8], s[4:5], v[7:8]
	v_rcp_f64_e32 v[15:16], v[11:12]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[23:24], -v[11:12], v[15:16], 1.0
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[15:16], v[15:16], v[23:24], v[15:16]
	s_waitcnt vmcnt(2)
	v_add_f64 v[9:10], v[5:6], -s[0:1]
	v_add_f64 v[5:6], v[5:6], -s[26:27]
	s_waitcnt vmcnt(0)
	v_add_f64 v[1:2], v[1:2], -v[3:4]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_div_scale_f64 v[3:4], null, s[6:7], s[6:7], v[9:10]
	v_div_scale_f64 v[13:14], null, s[6:7], s[6:7], v[5:6]
	v_div_scale_f64 v[33:34], s0, v[9:10], s[6:7], v[9:10]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_div_scale_f64 v[17:18], null, s[4:5], s[4:5], v[1:2]
	v_div_scale_f64 v[35:36], s2, v[1:2], s[4:5], v[1:2]
	v_rcp_f64_e32 v[19:20], v[3:4]
	v_rcp_f64_e32 v[21:22], v[13:14]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(TRANS32_DEP_3)
	v_rcp_f64_e32 v[25:26], v[17:18]
	v_fma_f64 v[27:28], -v[3:4], v[19:20], 1.0
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[29:30], -v[13:14], v[21:22], 1.0
	v_fma_f64 v[23:24], -v[17:18], v[25:26], 1.0
	v_fma_f64 v[19:20], v[19:20], v[27:28], v[19:20]
	v_fma_f64 v[27:28], -v[11:12], v[15:16], 1.0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[21:22], v[21:22], v[29:30], v[21:22]
	v_fma_f64 v[23:24], v[25:26], v[23:24], v[25:26]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[25:26], -v[3:4], v[19:20], 1.0
	v_fma_f64 v[15:16], v[15:16], v[27:28], v[15:16]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[29:30], -v[13:14], v[21:22], 1.0
	v_fma_f64 v[27:28], -v[17:18], v[23:24], 1.0
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_fma_f64 v[19:20], v[19:20], v[25:26], v[19:20]
	v_div_scale_f64 v[25:26], s1, v[5:6], s[6:7], v[5:6]
	v_fma_f64 v[21:22], v[21:22], v[29:30], v[21:22]
	v_mul_f64 v[29:30], v[31:32], v[15:16]
	v_fma_f64 v[23:24], v[23:24], v[27:28], v[23:24]
	v_mul_f64 v[27:28], v[33:34], v[19:20]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mul_f64 v[37:38], v[25:26], v[21:22]
	v_fma_f64 v[11:12], -v[11:12], v[29:30], v[31:32]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mul_f64 v[31:32], v[35:36], v[23:24]
	v_fma_f64 v[3:4], -v[3:4], v[27:28], v[33:34]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[13:14], -v[13:14], v[37:38], v[25:26]
	v_div_fmas_f64 v[11:12], v[11:12], v[15:16], v[29:30]
	s_mov_b32 vcc_lo, s0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[15:16], -v[17:18], v[31:32], v[35:36]
	v_div_fmas_f64 v[3:4], v[3:4], v[19:20], v[27:28]
	s_mov_b32 vcc_lo, s1
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_div_fmas_f64 v[13:14], v[13:14], v[21:22], v[37:38]
	s_mov_b32 vcc_lo, s2
	v_div_fixup_f64 v[7:8], v[11:12], s[4:5], v[7:8]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_div_fmas_f64 v[11:12], v[15:16], v[23:24], v[31:32]
	v_div_fixup_f64 v[3:4], v[3:4], s[6:7], v[9:10]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_div_fixup_f64 v[5:6], v[13:14], s[6:7], v[5:6]
	v_div_fixup_f64 v[1:2], v[11:12], s[4:5], v[1:2]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[5:6], v[7:8], v[5:6]
	v_add_f64 v[1:2], v[3:4], v[1:2]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ldexp_f64 v[3:4], -v[5:6], -2
	v_fma_f64 v[5:6], 0x3fe80000, v[1:2], v[3:4]
.LBB0_26:                               ; %Flow265
	s_or_b32 exec_lo, exec_lo, s22
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_and_not1_b32 s0, s15, exec_lo
	s_and_b32 s1, s21, exec_lo
                                        ; implicit-def: $vgpr2_vgpr3
	s_or_b32 s21, s0, s1
.LBB0_27:                               ; %Flow262
	s_and_not1_saveexec_b32 s17, s20
	s_cbranch_execz .LBB0_29
; %bb.28:
	v_mov_b32_e32 v3, 0
	s_mov_b32 s1, 0
	s_add_i32 s0, s16, -2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_lshl_b64 s[22:23], s[0:1], 3
	v_lshlrev_b64 v[1:2], 3, v[2:3]
	s_add_u32 s24, s10, s22
	s_addc_u32 s25, s11, s23
	s_add_i32 s0, s0, s16
	s_load_b64 s[34:35], s[24:25], 0x0
	s_lshl_b64 s[0:1], s[0:1], 3
	v_add_co_u32 v3, vcc_lo, s10, v1
	v_add_co_ci_u32_e32 v4, vcc_lo, s11, v2, vcc_lo
	v_add_co_u32 v1, vcc_lo, s8, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s9, v2, vcc_lo
	global_load_b64 v[3:4], v[3:4], off
	s_add_u32 s26, s8, s0
	s_addc_u32 s27, s9, s1
	global_load_b64 v[1:2], v[1:2], off
	s_add_u32 s22, s8, s22
	s_addc_u32 s23, s9, s23
	s_clause 0x1
	s_load_b128 s[24:27], s[26:27], 0x0
	s_load_b64 s[22:23], s[22:23], 0x0
	s_add_u32 s0, s10, s0
	s_addc_u32 s1, s11, s1
	s_or_b32 s21, s21, exec_lo
	s_load_b128 s[28:31], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[5:6], s[24:25], -s[22:23]
	v_add_f64 v[7:8], s[30:31], -s[28:29]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_scale_f64 v[11:12], null, s[6:7], s[6:7], v[5:6]
	v_div_scale_f64 v[15:16], null, s[4:5], s[4:5], v[7:8]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[19:20], v[11:12]
	v_rcp_f64_e32 v[23:24], v[15:16]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[27:28], -v[11:12], v[19:20], 1.0
	v_fma_f64 v[31:32], -v[15:16], v[23:24], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[19:20], v[19:20], v[27:28], v[19:20]
	v_fma_f64 v[23:24], v[23:24], v[31:32], v[23:24]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[27:28], -v[11:12], v[19:20], 1.0
	v_fma_f64 v[31:32], -v[15:16], v[23:24], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[19:20], v[19:20], v[27:28], v[19:20]
	v_fma_f64 v[23:24], v[23:24], v[31:32], v[23:24]
	s_waitcnt vmcnt(1)
	v_add_f64 v[3:4], v[3:4], -s[34:35]
	s_waitcnt vmcnt(0)
	v_add_f64 v[1:2], s[26:27], -v[1:2]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_div_scale_f64 v[9:10], null, s[4:5], s[4:5], v[3:4]
	v_div_scale_f64 v[33:34], vcc_lo, v[3:4], s[4:5], v[3:4]
	v_div_scale_f64 v[13:14], null, s[6:7], s[6:7], v[1:2]
	v_div_scale_f64 v[27:28], s1, v[1:2], s[6:7], v[1:2]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rcp_f64_e32 v[17:18], v[9:10]
	v_rcp_f64_e32 v[21:22], v[13:14]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[25:26], -v[9:10], v[17:18], 1.0
	v_fma_f64 v[29:30], -v[13:14], v[21:22], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[17:18], v[17:18], v[25:26], v[17:18]
	v_fma_f64 v[21:22], v[21:22], v[29:30], v[21:22]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[25:26], -v[9:10], v[17:18], 1.0
	v_fma_f64 v[29:30], -v[13:14], v[21:22], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fma_f64 v[17:18], v[17:18], v[25:26], v[17:18]
	v_div_scale_f64 v[25:26], s0, v[5:6], s[6:7], v[5:6]
	v_fma_f64 v[21:22], v[21:22], v[29:30], v[21:22]
	v_div_scale_f64 v[29:30], s2, v[7:8], s[4:5], v[7:8]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mul_f64 v[31:32], v[33:34], v[17:18]
	v_mul_f64 v[35:36], v[25:26], v[19:20]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mul_f64 v[37:38], v[27:28], v[21:22]
	v_mul_f64 v[39:40], v[29:30], v[23:24]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[9:10], -v[9:10], v[31:32], v[33:34]
	v_fma_f64 v[11:12], -v[11:12], v[35:36], v[25:26]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[13:14], -v[13:14], v[37:38], v[27:28]
	v_fma_f64 v[15:16], -v[15:16], v[39:40], v[29:30]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_div_fmas_f64 v[9:10], v[9:10], v[17:18], v[31:32]
	s_mov_b32 vcc_lo, s0
	v_div_fmas_f64 v[11:12], v[11:12], v[19:20], v[35:36]
	s_mov_b32 vcc_lo, s1
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_div_fmas_f64 v[13:14], v[13:14], v[21:22], v[37:38]
	s_mov_b32 vcc_lo, s2
	v_div_fmas_f64 v[15:16], v[15:16], v[23:24], v[39:40]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_div_fixup_f64 v[3:4], v[9:10], s[4:5], v[3:4]
	v_div_fixup_f64 v[5:6], v[11:12], s[6:7], v[5:6]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_div_fixup_f64 v[1:2], v[13:14], s[6:7], v[1:2]
	v_div_fixup_f64 v[7:8], v[15:16], s[4:5], v[7:8]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[1:2], v[3:4], v[1:2]
	v_add_f64 v[5:6], v[5:6], v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ldexp_f64 v[3:4], -v[5:6], -2
	v_fma_f64 v[5:6], 0x3fe80000, v[1:2], v[3:4]
.LBB0_29:                               ; %Flow266
	s_or_b32 exec_lo, exec_lo, s17
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_and_not1_b32 s0, s15, exec_lo
	s_and_b32 s1, s21, exec_lo
	s_or_b32 s20, s0, s1
.LBB0_30:                               ; %Flow261
	s_and_not1_saveexec_b32 s19, s19
	s_cbranch_execz .LBB0_32
; %bb.31:
	s_mov_b32 s17, 0
	s_load_b128 s[24:27], s[10:11], 0x0
	s_lshl_b64 s[0:1], s[16:17], 3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s22, s8, s0
	s_addc_u32 s23, s9, s1
	s_add_i32 s16, s16, 1
	s_clause 0x1
	s_load_b64 s[22:23], s[22:23], 0x0
	s_load_b128 s[28:31], s[8:9], 0x0
	s_lshl_b64 s[16:17], s[16:17], 3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s8, s8, s16
	s_addc_u32 s9, s9, s17
	s_add_u32 s16, s10, s16
	s_addc_u32 s17, s11, s17
	s_load_b64 s[8:9], s[8:9], 0x0
	s_add_u32 s0, s10, s0
	s_addc_u32 s1, s11, s1
	s_clause 0x1
	s_load_b64 s[10:11], s[16:17], 0x0
	s_load_b64 s[0:1], s[0:1], 0x0
	s_or_b32 s20, s20, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[1:2], s[26:27], -s[24:25]
	v_add_f64 v[3:4], s[22:23], -s[28:29]
	v_add_f64 v[5:6], s[8:9], -s[30:31]
	v_add_f64 v[7:8], s[10:11], -s[0:1]
	s_delay_alu instid0(VALU_DEP_4)
	v_div_scale_f64 v[9:10], null, s[4:5], s[4:5], v[1:2]
	v_div_scale_f64 v[33:34], vcc_lo, v[1:2], s[4:5], v[1:2]
	v_div_scale_f64 v[11:12], null, s[6:7], s[6:7], v[3:4]
	v_div_scale_f64 v[13:14], null, s[6:7], s[6:7], v[5:6]
	v_div_scale_f64 v[15:16], null, s[4:5], s[4:5], v[7:8]
	v_rcp_f64_e32 v[17:18], v[9:10]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rcp_f64_e32 v[19:20], v[11:12]
	v_rcp_f64_e32 v[21:22], v[13:14]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(TRANS32_DEP_3)
	v_rcp_f64_e32 v[23:24], v[15:16]
	v_fma_f64 v[25:26], -v[9:10], v[17:18], 1.0
	v_fma_f64 v[27:28], -v[11:12], v[19:20], 1.0
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[29:30], -v[13:14], v[21:22], 1.0
	v_fma_f64 v[31:32], -v[15:16], v[23:24], 1.0
	v_fma_f64 v[17:18], v[17:18], v[25:26], v[17:18]
	v_fma_f64 v[19:20], v[19:20], v[27:28], v[19:20]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[21:22], v[21:22], v[29:30], v[21:22]
	v_fma_f64 v[23:24], v[23:24], v[31:32], v[23:24]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[25:26], -v[9:10], v[17:18], 1.0
	v_fma_f64 v[27:28], -v[11:12], v[19:20], 1.0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[29:30], -v[13:14], v[21:22], 1.0
	v_fma_f64 v[31:32], -v[15:16], v[23:24], 1.0
	s_delay_alu instid0(VALU_DEP_4)
	v_fma_f64 v[17:18], v[17:18], v[25:26], v[17:18]
	v_div_scale_f64 v[25:26], s0, v[3:4], s[6:7], v[3:4]
	v_fma_f64 v[19:20], v[19:20], v[27:28], v[19:20]
	v_div_scale_f64 v[27:28], s1, v[5:6], s[6:7], v[5:6]
	v_fma_f64 v[21:22], v[21:22], v[29:30], v[21:22]
	v_div_scale_f64 v[29:30], s2, v[7:8], s[4:5], v[7:8]
	v_fma_f64 v[23:24], v[23:24], v[31:32], v[23:24]
	v_mul_f64 v[31:32], v[33:34], v[17:18]
	v_mul_f64 v[35:36], v[25:26], v[19:20]
	v_mul_f64 v[37:38], v[27:28], v[21:22]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mul_f64 v[39:40], v[29:30], v[23:24]
	v_fma_f64 v[9:10], -v[9:10], v[31:32], v[33:34]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[11:12], -v[11:12], v[35:36], v[25:26]
	v_fma_f64 v[13:14], -v[13:14], v[37:38], v[27:28]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[15:16], -v[15:16], v[39:40], v[29:30]
	v_div_fmas_f64 v[9:10], v[9:10], v[17:18], v[31:32]
	s_mov_b32 vcc_lo, s0
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_div_fmas_f64 v[11:12], v[11:12], v[19:20], v[35:36]
	s_mov_b32 vcc_lo, s1
	v_div_fmas_f64 v[13:14], v[13:14], v[21:22], v[37:38]
	s_mov_b32 vcc_lo, s2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_div_fmas_f64 v[15:16], v[15:16], v[23:24], v[39:40]
	v_div_fixup_f64 v[1:2], v[9:10], s[4:5], v[1:2]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_div_fixup_f64 v[3:4], v[11:12], s[6:7], v[3:4]
	v_div_fixup_f64 v[5:6], v[13:14], s[6:7], v[5:6]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_div_fixup_f64 v[7:8], v[15:16], s[4:5], v[7:8]
	v_add_f64 v[1:2], v[1:2], v[3:4]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[5:6], v[5:6], v[7:8]
	v_ldexp_f64 v[3:4], -v[5:6], -2
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[5:6], 0x3fe80000, v[1:2], v[3:4]
.LBB0_32:                               ; %Flow267
	s_or_b32 exec_lo, exec_lo, s19
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_and_not1_b32 s0, s15, exec_lo
	s_and_b32 s1, s20, exec_lo
	s_or_b32 s15, s0, s1
.LBB0_33:                               ; %Flow260
	s_or_b32 exec_lo, exec_lo, s18
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_and_not1_b32 s0, s3, exec_lo
	s_and_b32 s1, s15, exec_lo
	s_or_b32 s3, s0, s1
.LBB0_34:                               ; %Flow255
	s_or_b32 exec_lo, exec_lo, s14
	s_and_saveexec_b32 s0, s3
	s_cbranch_execz .LBB0_36
; %bb.35:                               ; %.sink.split
	v_mov_b32_e32 v1, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 3, v[0:1]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v0, vcc_lo, s12, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s13, v1, vcc_lo
	global_store_b64 v[0:1], v[5:6], off
.LBB0_36:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z24update_mixed_derivativesPdS_S_jjddj
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 52
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 41
		.amdhsa_next_free_sgpr 36
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z24update_mixed_derivativesPdS_S_jjddj, .Lfunc_end0-_Z24update_mixed_derivativesPdS_S_jjddj
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 4376
; NumSgprs: 38
; NumVgprs: 41
; ScratchSize: 0
; MemoryBound: 1
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 4
; VGPRBlocks: 5
; NumSGPRsForWavesPerEU: 38
; NumVGPRsForWavesPerEU: 41
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           8
        .value_kind:     by_value
      - .offset:         40
        .size:           8
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     by_value
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 52
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z24update_mixed_derivativesPdS_S_jjddj
    .private_segment_fixed_size: 0
    .sgpr_count:     38
    .sgpr_spill_count: 0
    .symbol:         _Z24update_mixed_derivativesPdS_S_jjddj.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     41
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
