#include "cuda_runtime.h"
#include "device_launch_parameters.h"

#include <stdio.h>
#include <cmath>
#include <iostream>
#include <forward_list>
#include <chrono>

cudaError_t findSimpleDividersWithCUDA(std::forward_list<long long> *result, long long value, int cudaCores);

__device__ bool isPrime(long long value)
{
	for (int i = 2; i <= sqrt((double) value); i++)
	{
		if (value%i == 0)
			return false;
	}
	return true;
}

__global__ void getSimpleDividersKernel(char *output, long long from, long long value, int step)
{
	const long long current = threadIdx.x + from + step * blockIdx.x;

	long long outPos = current - from;

	output[outPos] = 0;

	if (value%current == 0 && isPrime(current))
	{
		while (value%current == 0)
		{
			output[outPos]++;
			value /= current;
		}
	}
	
}


int main()
{
	using namespace std;

	char *outputArray = nullptr;
	long long value;
	std::forward_list<long long> result;

	std::cout << "Write value:" << std::endl;
	std::cin >> value;

	auto begin = chrono::high_resolution_clock::now();

    // Add vectors in parallel.
	cudaError_t cudaStatus = findSimpleDividersWithCUDA(&result, value, 1000);
    if (cudaStatus != cudaSuccess) {
        fprintf(stderr, "findSimpleDividersWithCUDA failed!");
        return 1;
    }

	auto end = chrono::high_resolution_clock::now();

	auto run_time = chrono::duration_cast<chrono::milliseconds>(end - begin).count();

	cout << "It's done in " << run_time << "ms" << endl;

    // cudaDeviceReset must be called before exiting in order for profiling and
    // tracing tools such as Nsight and Visual Profiler to show complete traces.
    cudaStatus = cudaDeviceReset();
    if (cudaStatus != cudaSuccess) {
        fprintf(stderr, "cudaDeviceReset failed!");
        return 1;
    }

	for (auto item : result)
	{
		std::cout << item << ' ';
	}

    return 0;
}

cudaError_t findSimpleDividersWithCUDA(std::forward_list<long long> *result, long long value, int cudaCores)
{
	const long long from = 2;
	const long long buferSize = value - from;
	const long long blockCount = (buferSize / cudaCores) + (buferSize%cudaCores == 0 ? 0 : 1);

	if (buferSize < cudaCores)
	{
		cudaCores = buferSize;
	}

	char *buffer_output = new char[buferSize];
	char *dev_output;

	cudaError_t cudaStatus;

	// Choose which GPU to run on, change this on a multi-GPU system.
	cudaStatus = cudaSetDevice(0);
	if (cudaStatus != cudaSuccess) {
		fprintf(stderr, "cudaSetDevice failed!  Do you have a CUDA-capable GPU installed?");
		goto Error;
	}

	// Allocate GPU buffers for three vectors (two input, one output).

	cudaStatus = cudaMalloc(&dev_output, buferSize);
	if (cudaStatus != cudaSuccess) {
		fprintf(stderr, "cudaMalloc failed!");
		goto Error;
	}


	getSimpleDividersKernel <<<blockCount, cudaCores >>> (dev_output, from, value, cudaCores);

	cudaStatus = cudaGetLastError();
	if (cudaStatus != cudaSuccess) {
		fprintf(stderr, "addKernel launch failed: %s\n", cudaGetErrorString(cudaStatus));
		goto Error;
	}

	// cudaDeviceSynchronize waits for the kernel to finish, and returns
	// any errors encountered during the launch.
	cudaStatus = cudaDeviceSynchronize();
	if (cudaStatus != cudaSuccess) {
		fprintf(stderr, "cudaDeviceSynchronize returned error code %d after launching addKernel!\n", cudaStatus);
		goto Error;
	}

	cudaStatus = cudaMemcpy(buffer_output, dev_output, buferSize, cudaMemcpyDeviceToHost);
	if (cudaStatus != cudaSuccess) {
		fprintf(stderr, "cudaMemcpy 260 failed!");
		goto Error;
	}

	for (long long j = 0; j < buferSize; j++)
	{
		int itCount = (int)buffer_output[j];
		for (int k = 0; k < itCount; k++)
		{
			long long tempValue = from + j;
			result->push_front(tempValue);
		}
	}

Error:
	delete[] buffer_output;
	cudaFree(dev_output);

	return cudaStatus;
}

	.file	"tmpxft_0034960b_00000000-6_kernel.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3885:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3885:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z7isPrimex
	.type	_Z7isPrimex, @function
_Z7isPrimex:
.LFB3868:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE3868:
	.size	_Z7isPrimex, .-_Z7isPrimex
	.globl	_Z46__device_stub__Z23getSimpleDividersKernelPcxxiPcxxi
	.type	_Z46__device_stub__Z23getSimpleDividersKernelPcxxiPcxxi, @function
_Z46__device_stub__Z23getSimpleDividersKernelPcxxiPcxxi:
.LFB3907:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 4(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L4
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z23getSimpleDividersKernelPcxxi(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L4:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L6
	call	__stack_chk_fail@PLT
.L6:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3907:
	.size	_Z46__device_stub__Z23getSimpleDividersKernelPcxxiPcxxi, .-_Z46__device_stub__Z23getSimpleDividersKernelPcxxiPcxxi
	.globl	_Z23getSimpleDividersKernelPcxxi
	.type	_Z23getSimpleDividersKernelPcxxi, @function
_Z23getSimpleDividersKernelPcxxi:
.LFB3908:
	.cfi_startproc
	endbr64
	jmp	_Z46__device_stub__Z23getSimpleDividersKernelPcxxiPcxxi
	.cfi_endproc
.LFE3908:
	.size	_Z23getSimpleDividersKernelPcxxi, .-_Z23getSimpleDividersKernelPcxxi
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"cudaSetDevice failed!  Do you have a CUDA-capable GPU installed?"
.LC1:
	.string	"cudaMalloc failed!"
.LC2:
	.string	"addKernel launch failed: %s\n"
.LC3:
	.string	"cudaDeviceSynchronize returned error code %d after launching addKernel!\n"
.LC4:
	.string	"cudaMemcpy 260 failed!"
	.text
	.globl	_Z26findSimpleDividersWithCUDAPSt12forward_listIxSaIxEExi
	.type	_Z26findSimpleDividersWithCUDAPSt12forward_listIxSaIxEExi, @function
_Z26findSimpleDividersWithCUDAPSt12forward_listIxSaIxEExi:
.LFB3882:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movslq	%edx, %r15
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	movq	%rsi, %r14
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movq	%rdi, %r13
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movq	%r15, %r12
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	leaq	-2(%rsi), %rbp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movq	%rbp, %rdi
	subq	$72, %rsp
	.cfi_def_cfa_offset 128
	movq	%fs:40, %rax
	movq	%rax, 56(%rsp)
	xorl	%eax, %eax
	cmpq	%rbp, %r15
	cmovg	%ebp, %r12d
	call	_Znam@PLT
	xorl	%edi, %edi
	movq	%rax, (%rsp)
	call	cudaSetDevice@PLT
	leaq	.LC0(%rip), %rdx
	movl	%eax, %ebx
	testl	%eax, %eax
	jne	.L27
	leaq	24(%rsp), %rdi
	movq	%rbp, %rsi
	call	cudaMalloc@PLT
	movl	%eax, %ebx
	testl	%eax, %eax
	je	.L14
	leaq	.LC1(%rip), %rdx
.L27:
	movq	stderr(%rip), %rdi
	movl	$2, %esi
	xorl	%eax, %eax
	call	__fprintf_chk@PLT
	jmp	.L13
.L14:
	movq	%rbp, %rax
	movl	%r12d, 44(%rsp)
	movabsq	$4294967297, %rcx
	cqto
	movq	%rcx, 36(%rsp)
	movl	40(%rsp), %esi
	idivq	%r15
	movq	%rcx, 48(%rsp)
	movl	52(%rsp), %ecx
	cmpq	$1, %rdx
	movq	44(%rsp), %rdx
	sbbq	$-1, %rax
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	%eax, 32(%rsp)
	movq	32(%rsp), %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L15
	movq	24(%rsp), %rdi
	movl	%r12d, %ecx
	movq	%r14, %rdx
	movl	$2, %esi
	call	_Z46__device_stub__Z23getSimpleDividersKernelPcxxiPcxxi
.L15:
	call	cudaGetLastError@PLT
	movl	%eax, %ebx
	testl	%eax, %eax
	je	.L16
	movl	%eax, %edi
	call	cudaGetErrorString@PLT
	movq	stderr(%rip), %rdi
	movl	$2, %esi
	leaq	.LC2(%rip), %rdx
	movq	%rax, %rcx
	xorl	%eax, %eax
	call	__fprintf_chk@PLT
	jmp	.L13
.L16:
	call	cudaDeviceSynchronize@PLT
	movl	%eax, %ebx
	testl	%eax, %eax
	je	.L17
	movq	stderr(%rip), %rdi
	movl	%eax, %ecx
	movl	$2, %esi
	xorl	%eax, %eax
	leaq	.LC3(%rip), %rdx
	call	__fprintf_chk@PLT
	jmp	.L13
.L17:
	movq	24(%rsp), %rsi
	movq	(%rsp), %rdi
	movq	%rbp, %rdx
	xorl	%r12d, %r12d
	movl	$2, %ecx
	call	cudaMemcpy@PLT
	leaq	.LC4(%rip), %rdx
	movl	%eax, %ebx
	testl	%eax, %eax
	jne	.L27
.L18:
	cmpq	%rbp, %r12
	jge	.L13
	movq	(%rsp), %rax
	xorl	%r14d, %r14d
	leaq	2(%r12), %rdx
	movsbl	(%rax,%r12), %r15d
.L19:
	cmpl	%r15d, %r14d
	jge	.L28
	movl	$16, %edi
	movq	%rdx, 8(%rsp)
	incl	%r14d
	call	_Znwm@PLT
	movq	0(%r13), %rcx
	movq	8(%rsp), %rdx
	movq	%rax, 0(%r13)
	movq	%rdx, 8(%rax)
	movq	%rcx, (%rax)
	jmp	.L19
.L28:
	incq	%r12
	jmp	.L18
.L13:
	movq	(%rsp), %rdi
	call	_ZdaPv@PLT
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	movq	56(%rsp), %rax
	subq	%fs:40, %rax
	je	.L22
	call	__stack_chk_fail@PLT
.L22:
	addq	$72, %rsp
	.cfi_def_cfa_offset 56
	movl	%ebx, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3882:
	.size	_Z26findSimpleDividersWithCUDAPSt12forward_listIxSaIxEExi, .-_Z26findSimpleDividersWithCUDAPSt12forward_listIxSaIxEExi
	.section	.rodata.str1.1
.LC5:
	.string	"Write value:"
.LC6:
	.string	"findSimpleDividersWithCUDA failed!"
.LC7:
	.string	"It's done in "
.LC8:
	.string	"ms"
.LC9:
	.string	"cudaDeviceReset failed!"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB3869:
	.cfi_startproc
	.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
	.cfi_lsda 0x1b,.LLSDA3869
	endbr64
	pushq	%r12
	.cfi_def_cfa_offset 16
	.cfi_offset 12, -16
	leaq	.LC5(%rip), %rsi
	pushq	%rbp
	.cfi_def_cfa_offset 24
	.cfi_offset 6, -24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset 3, -32
	leaq	_ZSt4cout(%rip), %rbx
	movq	%rbx, %rdi
	subq	$32, %rsp
	.cfi_def_cfa_offset 64
	movq	%fs:40, %rax
	movq	%rax, 24(%rsp)
	xorl	%eax, %eax
	xorl	%eax, %eax
	movq	%rax, 16(%rsp)
.LEHB0:
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%rax, %rdi
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
	leaq	8(%rsp), %rsi
	leaq	_ZSt3cin(%rip), %rdi
	call	_ZNSi10_M_extractIxEERSiRT_@PLT
	call	_ZNSt6chrono3_V212system_clock3nowEv@PLT
	movq	8(%rsp), %rsi
	leaq	16(%rsp), %rdi
	movl	$1000, %edx
	movq	%rax, %rbp
	call	_Z26findSimpleDividersWithCUDAPSt12forward_listIxSaIxEExi
	testl	%eax, %eax
	je	.L30
	leaq	.LC6(%rip), %rdx
.L50:
	movq	stderr(%rip), %rdi
	movl	$2, %esi
	xorl	%eax, %eax
	call	__fprintf_chk@PLT
	movl	$1, %ebx
	jmp	.L31
.L30:
	call	_ZNSt6chrono3_V212system_clock3nowEv@PLT
	movl	$1000000, %ecx
	leaq	.LC7(%rip), %rsi
	movq	%rbx, %rdi
	subq	%rbp, %rax
	cqto
	idivq	%rcx
	movq	%rax, %rbp
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%rax, %rdi
	movq	%rbp, %rsi
	call	_ZNSo9_M_insertIlEERSoT_@PLT
	movq	%rax, %rdi
	leaq	.LC8(%rip), %rsi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%rax, %rdi
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
	call	cudaDeviceReset@PLT
	movq	16(%rsp), %rbp
	leaq	7(%rsp), %r12
	leaq	.LC9(%rip), %rdx
	testl	%eax, %eax
	jne	.L50
.L32:
	testq	%rbp, %rbp
	je	.L52
	movq	8(%rbp), %rsi
	movq	%rbx, %rdi
	call	_ZNSo9_M_insertIxEERSoT_@PLT
	movq	%rax, %rdi
	movq	(%rax), %rax
	movb	$32, 7(%rsp)
	movq	-24(%rax), %rax
	cmpq	$0, 16(%rdi,%rax)
	je	.L34
	movl	$1, %edx
	movq	%r12, %rsi
	call	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
	jmp	.L35
.L34:
	movl	$32, %esi
	call	_ZNSo3putEc@PLT
.LEHE0:
.L35:
	movq	0(%rbp), %rbp
	jmp	.L32
.L52:
	xorl	%ebx, %ebx
.L31:
	movq	16(%rsp), %rdi
.L37:
	testq	%rdi, %rdi
	je	.L53
	movq	(%rdi), %rbp
	movl	$16, %esi
	call	_ZdlPvm@PLT
	movq	%rbp, %rdi
	jmp	.L37
.L44:
	endbr64
	movq	%rax, %rbx
.L39:
	movq	16(%rsp), %rdi
.L40:
	testq	%rdi, %rdi
	je	.L54
	movq	(%rdi), %rbp
	movl	$16, %esi
	call	_ZdlPvm@PLT
	movq	%rbp, %rdi
	jmp	.L40
.L54:
	movq	24(%rsp), %rax
	subq	%fs:40, %rax
	jne	.L51
	movq	%rbx, %rdi
.LEHB1:
	call	_Unwind_Resume@PLT
.LEHE1:
.L53:
	movq	24(%rsp), %rax
	subq	%fs:40, %rax
	je	.L43
.L51:
	call	__stack_chk_fail@PLT
.L43:
	addq	$32, %rsp
	.cfi_def_cfa_offset 32
	movl	%ebx, %eax
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3869:
	.globl	__gxx_personality_v0
	.section	.gcc_except_table,"a",@progbits
.LLSDA3869:
	.byte	0xff
	.byte	0xff
	.byte	0x1
	.uleb128 .LLSDACSE3869-.LLSDACSB3869
.LLSDACSB3869:
	.uleb128 .LEHB0-.LFB3869
	.uleb128 .LEHE0-.LEHB0
	.uleb128 .L44-.LFB3869
	.uleb128 0
	.uleb128 .LEHB1-.LFB3869
	.uleb128 .LEHE1-.LEHB1
	.uleb128 0
	.uleb128 0
.LLSDACSE3869:
	.section	.text.startup
	.size	main, .-main
	.section	.rodata.str1.1
.LC10:
	.string	"_Z23getSimpleDividersKernelPcxxi"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3910:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC10(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z23getSimpleDividersKernelPcxxi(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3910:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.hidden	DW.ref.__gxx_personality_v0
	.weak	DW.ref.__gxx_personality_v0
	.section	.data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
	.align 8
	.type	DW.ref.__gxx_personality_v0, @object
	.size	DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
	.quad	__gxx_personality_v0
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include "hip/hip_runtime.h"


#include <stdio.h>
#include <cmath>
#include <iostream>
#include <forward_list>
#include <chrono>

hipError_t findSimpleDividersWithCUDA(std::forward_list<long long> *result, long long value, int cudaCores);

__device__ bool isPrime(long long value)
{
	for (int i = 2; i <= sqrt((double) value); i++)
	{
		if (value%i == 0)
			return false;
	}
	return true;
}

__global__ void getSimpleDividersKernel(char *output, long long from, long long value, int step)
{
	const long long current = threadIdx.x + from + step * blockIdx.x;

	long long outPos = current - from;

	output[outPos] = 0;

	if (value%current == 0 && isPrime(current))
	{
		while (value%current == 0)
		{
			output[outPos]++;
			value /= current;
		}
	}
	
}


int main()
{
	using namespace std;

	char *outputArray = nullptr;
	long long value;
	std::forward_list<long long> result;

	std::cout << "Write value:" << std::endl;
	std::cin >> value;

	auto begin = chrono::high_resolution_clock::now();

    // Add vectors in parallel.
	hipError_t cudaStatus = findSimpleDividersWithCUDA(&result, value, 1000);
    if (cudaStatus != hipSuccess) {
        fprintf(stderr, "findSimpleDividersWithCUDA failed!");
        return 1;
    }

	auto end = chrono::high_resolution_clock::now();

	auto run_time = chrono::duration_cast<chrono::milliseconds>(end - begin).count();

	cout << "It's done in " << run_time << "ms" << endl;

    // cudaDeviceReset must be called before exiting in order for profiling and
    // tracing tools such as Nsight and Visual Profiler to show complete traces.
    cudaStatus = hipDeviceReset();
    if (cudaStatus != hipSuccess) {
        fprintf(stderr, "hipDeviceReset failed!");
        return 1;
    }

	for (auto item : result)
	{
		std::cout << item << ' ';
	}

    return 0;
}

hipError_t findSimpleDividersWithCUDA(std::forward_list<long long> *result, long long value, int cudaCores)
{
	const long long from = 2;
	const long long buferSize = value - from;
	const long long blockCount = (buferSize / cudaCores) + (buferSize%cudaCores == 0 ? 0 : 1);

	if (buferSize < cudaCores)
	{
		cudaCores = buferSize;
	}

	char *buffer_output = new char[buferSize];
	char *dev_output;

	hipError_t cudaStatus;

	// Choose which GPU to run on, change this on a multi-GPU system.
	cudaStatus = hipSetDevice(0);
	if (cudaStatus != hipSuccess) {
		fprintf(stderr, "hipSetDevice failed!  Do you have a CUDA-capable GPU installed?");
		goto Error;
	}

	// Allocate GPU buffers for three vectors (two input, one output).

	cudaStatus = hipMalloc(&dev_output, buferSize);
	if (cudaStatus != hipSuccess) {
		fprintf(stderr, "hipMalloc failed!");
		goto Error;
	}


	getSimpleDividersKernel <<<blockCount, cudaCores >>> (dev_output, from, value, cudaCores);

	cudaStatus = hipGetLastError();
	if (cudaStatus != hipSuccess) {
		fprintf(stderr, "addKernel launch failed: %s\n", hipGetErrorString(cudaStatus));
		goto Error;
	}

	// cudaDeviceSynchronize waits for the kernel to finish, and returns
	// any errors encountered during the launch.
	cudaStatus = hipDeviceSynchronize();
	if (cudaStatus != hipSuccess) {
		fprintf(stderr, "hipDeviceSynchronize returned error code %d after launching addKernel!\n", cudaStatus);
		goto Error;
	}

	cudaStatus = hipMemcpy(buffer_output, dev_output, buferSize, hipMemcpyDeviceToHost);
	if (cudaStatus != hipSuccess) {
		fprintf(stderr, "hipMemcpy 260 failed!");
		goto Error;
	}

	for (long long j = 0; j < buferSize; j++)
	{
		int itCount = (int)buffer_output[j];
		for (int k = 0; k < itCount; k++)
		{
			long long tempValue = from + j;
			result->push_front(tempValue);
		}
	}

Error:
	delete[] buffer_output;
	hipFree(dev_output);

	return cudaStatus;
}

	.text
	.file	"kernel.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z38__device_stub__getSimpleDividersKernelPcxxi # -- Begin function _Z38__device_stub__getSimpleDividersKernelPcxxi
	.type	_Z38__device_stub__getSimpleDividersKernelPcxxi,@function
_Z38__device_stub__getSimpleDividersKernelPcxxi: # @_Z38__device_stub__getSimpleDividersKernelPcxxi
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	4(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z23getSimpleDividersKernelPcxxi, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z38__device_stub__getSimpleDividersKernelPcxxi, .Lfunc_end0-_Z38__device_stub__getSimpleDividersKernelPcxxi
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
.Lfunc_begin0:
	.cfi_startproc
	.cfi_personality 3, __gxx_personality_v0
	.cfi_lsda 3, .Lexception0
# %bb.0:
	pushq	%r14
	.cfi_def_cfa_offset 16
	pushq	%rbx
	.cfi_def_cfa_offset 24
	subq	$24, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -24
	.cfi_offset %r14, -16
	movq	$0, 8(%rsp)
.Ltmp0:
	movl	$_ZSt4cout, %ebx
	movl	$_ZSt4cout, %edi
	movl	$.L.str, %esi
	movl	$12, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp1:
# %bb.1:                                # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
	movq	_ZSt4cout(%rip), %rax
	addq	-24(%rax), %rbx
.Ltmp2:
	movq	%rbx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
.Ltmp3:
# %bb.2:                                # %.noexc26
.Ltmp4:
	movsbl	%al, %esi
	movl	$_ZSt4cout, %edi
	callq	_ZNSo3putEc
.Ltmp5:
# %bb.3:                                # %.noexc27
.Ltmp6:
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
.Ltmp7:
# %bb.4:                                # %_ZNSolsEPFRSoS_E.exit
.Ltmp8:
	leaq	16(%rsp), %rsi
	movl	$_ZSt3cin, %edi
	callq	_ZNSi10_M_extractIxEERSiRT_
.Ltmp9:
# %bb.5:                                # %_ZNSirsERx.exit
	callq	_ZNSt6chrono3_V212system_clock3nowEv
	movq	%rax, %rbx
	movq	16(%rsp), %rsi
.Ltmp11:
	leaq	8(%rsp), %rdi
	movl	$1000, %edx                     # imm = 0x3E8
	callq	_Z26findSimpleDividersWithCUDAPSt12forward_listIxSaIxEExi
.Ltmp12:
# %bb.6:
	testl	%eax, %eax
	jne	.LBB1_7
# %bb.10:
	callq	_ZNSt6chrono3_V212system_clock3nowEv
	movq	%rax, %r14
.Ltmp14:
	movl	$_ZSt4cout, %edi
	movl	$.L.str.2, %esi
	movl	$13, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp15:
# %bb.11:                               # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit17
	subq	%rbx, %r14
	movabsq	$4835703278458516699, %rcx      # imm = 0x431BDE82D7B634DB
	movq	%r14, %rax
	imulq	%rcx
	movq	%rdx, %rsi
	shrq	$63, %rsi
	sarq	$18, %rdx
	addq	%rdx, %rsi
.Ltmp16:
	movl	$_ZSt4cout, %edi
	callq	_ZNSo9_M_insertIlEERSoT_
.Ltmp17:
# %bb.12:                               # %_ZNSolsEl.exit
.Ltmp18:
	movq	%rax, %rbx
	movl	$.L.str.3, %esi
	movl	$2, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp19:
# %bb.13:                               # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit18
	movq	(%rbx), %rax
	movq	-24(%rax), %rdi
	addq	%rbx, %rdi
.Ltmp20:
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
.Ltmp21:
# %bb.14:                               # %.noexc29
.Ltmp22:
	movsbl	%al, %esi
	movq	%rbx, %rdi
	callq	_ZNSo3putEc
.Ltmp23:
# %bb.15:                               # %.noexc30
.Ltmp24:
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
.Ltmp25:
# %bb.16:                               # %_ZNSolsEPFRSoS_E.exit19
.Ltmp26:
	callq	hipDeviceReset
.Ltmp27:
# %bb.17:
	testl	%eax, %eax
	jne	.LBB1_20
# %bb.18:                               # %.preheader
	movq	8(%rsp), %r14
	testq	%r14, %r14
	je	.LBB1_19
# %bb.22:
	leaq	7(%rsp), %rbx
.LBB1_23:                               # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	movq	8(%r14), %rsi
.Ltmp29:
	movl	$_ZSt4cout, %edi
	callq	_ZNSo9_M_insertIxEERSoT_
.Ltmp30:
# %bb.24:                               # %_ZNSolsEx.exit
                                        #   in Loop: Header=BB1_23 Depth=1
	movb	$32, 7(%rsp)
	movq	(%rax), %rcx
	movq	-24(%rcx), %rcx
	cmpq	$0, 16(%rax,%rcx)
	je	.LBB1_26
# %bb.25:                               #   in Loop: Header=BB1_23 Depth=1
.Ltmp31:
	movl	$1, %edx
	movq	%rax, %rdi
	movq	%rbx, %rsi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp32:
	jmp	.LBB1_27
.LBB1_26:                               #   in Loop: Header=BB1_23 Depth=1
.Ltmp33:
	movq	%rax, %rdi
	movl	$32, %esi
	callq	_ZNSo3putEc
.Ltmp34:
.LBB1_27:                               #   in Loop: Header=BB1_23 Depth=1
	movq	(%r14), %r14
	testq	%r14, %r14
	jne	.LBB1_23
# %bb.28:
	xorl	%ebx, %ebx
.LBB1_29:                               # %.loopexit
	movq	8(%rsp), %rdi
	testq	%rdi, %rdi
	je	.LBB1_31
.LBB1_30:                               # %.lr.ph.i.i
                                        # =>This Inner Loop Header: Depth=1
	movq	(%rdi), %r14
	callq	_ZdlPv
	movq	%r14, %rdi
	testq	%r14, %r14
	jne	.LBB1_30
	jmp	.LBB1_31
.LBB1_19:
	xorl	%ebx, %ebx
.LBB1_31:                               # %_ZNSt14_Fwd_list_baseIxSaIxEED2Ev.exit
	movl	%ebx, %eax
	addq	$24, %rsp
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	retq
.LBB1_7:
	.cfi_def_cfa_offset 48
	movq	stderr(%rip), %rcx
	movl	$.L.str.1, %edi
	movl	$34, %esi
	jmp	.LBB1_8
.LBB1_20:
	movq	stderr(%rip), %rcx
	movl	$.L.str.4, %edi
	movl	$22, %esi
.LBB1_8:                                # %.loopexit
	movl	$1, %edx
	callq	fwrite@PLT
	movl	$1, %ebx
	jmp	.LBB1_29
.LBB1_9:
.Ltmp13:
	jmp	.LBB1_33
.LBB1_32:
.Ltmp10:
	jmp	.LBB1_33
.LBB1_21:
.Ltmp28:
	jmp	.LBB1_33
.LBB1_36:
.Ltmp35:
.LBB1_33:
	movq	%rax, %rbx
	movq	8(%rsp), %rdi
	testq	%rdi, %rdi
	je	.LBB1_35
.LBB1_34:                               # %.lr.ph.i.i22
                                        # =>This Inner Loop Header: Depth=1
	movq	(%rdi), %r14
	callq	_ZdlPv
	movq	%r14, %rdi
	testq	%r14, %r14
	jne	.LBB1_34
.LBB1_35:                               # %_ZNSt14_Fwd_list_baseIxSaIxEED2Ev.exit25
	movq	%rbx, %rdi
	callq	_Unwind_Resume@PLT
.Lfunc_end1:
	.size	main, .Lfunc_end1-main
	.cfi_endproc
	.section	.gcc_except_table,"a",@progbits
	.p2align	2, 0x0
GCC_except_table1:
.Lexception0:
	.byte	255                             # @LPStart Encoding = omit
	.byte	255                             # @TType Encoding = omit
	.byte	1                               # Call site Encoding = uleb128
	.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
	.uleb128 .Ltmp0-.Lfunc_begin0           # >> Call Site 1 <<
	.uleb128 .Ltmp9-.Ltmp0                  #   Call between .Ltmp0 and .Ltmp9
	.uleb128 .Ltmp10-.Lfunc_begin0          #     jumps to .Ltmp10
	.byte	0                               #   On action: cleanup
	.uleb128 .Ltmp11-.Lfunc_begin0          # >> Call Site 2 <<
	.uleb128 .Ltmp12-.Ltmp11                #   Call between .Ltmp11 and .Ltmp12
	.uleb128 .Ltmp13-.Lfunc_begin0          #     jumps to .Ltmp13
	.byte	0                               #   On action: cleanup
	.uleb128 .Ltmp14-.Lfunc_begin0          # >> Call Site 3 <<
	.uleb128 .Ltmp27-.Ltmp14                #   Call between .Ltmp14 and .Ltmp27
	.uleb128 .Ltmp28-.Lfunc_begin0          #     jumps to .Ltmp28
	.byte	0                               #   On action: cleanup
	.uleb128 .Ltmp29-.Lfunc_begin0          # >> Call Site 4 <<
	.uleb128 .Ltmp34-.Ltmp29                #   Call between .Ltmp29 and .Ltmp34
	.uleb128 .Ltmp35-.Lfunc_begin0          #     jumps to .Ltmp35
	.byte	0                               #   On action: cleanup
	.uleb128 .Ltmp34-.Lfunc_begin0          # >> Call Site 5 <<
	.uleb128 .Lfunc_end1-.Ltmp34            #   Call between .Ltmp34 and .Lfunc_end1
	.byte	0                               #     has no landing pad
	.byte	0                               #   On action: cleanup
.Lcst_end0:
	.p2align	2, 0x0
                                        # -- End function
	.text
	.globl	_Z26findSimpleDividersWithCUDAPSt12forward_listIxSaIxEExi # -- Begin function _Z26findSimpleDividersWithCUDAPSt12forward_listIxSaIxEExi
	.type	_Z26findSimpleDividersWithCUDAPSt12forward_listIxSaIxEExi,@function
_Z26findSimpleDividersWithCUDAPSt12forward_listIxSaIxEExi: # @_Z26findSimpleDividersWithCUDAPSt12forward_listIxSaIxEExi
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$24, %rsp
	.cfi_def_cfa_offset 80
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%rsi, 16(%rsp)                  # 8-byte Spill
	leaq	-2(%rsi), %r14
	movslq	%edx, %r13
	movq	%r14, %rax
	cqto
	idivq	%r13
	movq	%rax, %r12
	cmpq	$1, %rdx
	sbbq	$-1, %r12
	movq	%rdi, %r15
	cmpq	%r13, %r14
	cmovll	%r14d, %r13d
	movq	%r14, %rdi
	callq	_Znam
	movq	%rax, %rbx
	xorl	%edi, %edi
	callq	hipSetDevice
	testl	%eax, %eax
	jne	.LBB2_1
# %bb.3:
	leaq	8(%rsp), %rdi
	movq	%r14, %rsi
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB2_4
# %bb.5:
	movl	%r12d, %edi
	btsq	$32, %rdi
	movl	%r13d, %edx
	btsq	$32, %rdx
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	movq	16(%rsp), %r12                  # 8-byte Reload
	jne	.LBB2_7
# %bb.6:
	movq	8(%rsp), %rdi
	movl	$2, %esi
	movq	%r12, %rdx
	movl	%r13d, %ecx
	callq	_Z38__device_stub__getSimpleDividersKernelPcxxi
.LBB2_7:
	callq	hipGetLastError
	testl	%eax, %eax
	jne	.LBB2_8
# %bb.9:
	callq	hipDeviceSynchronize
	testl	%eax, %eax
	jne	.LBB2_10
# %bb.11:
	movq	8(%rsp), %rsi
	movq	%rbx, %rdi
	movq	%r14, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	testl	%eax, %eax
	jne	.LBB2_20
# %bb.12:                               # %.preheader
	xorl	%ebp, %ebp
	cmpq	$3, %r12
	jl	.LBB2_19
# %bb.13:                               # %.lr.ph55.preheader
	xorl	%r12d, %r12d
.LBB2_14:                               # %.lr.ph55
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB2_16 Depth 2
	movsbl	(%rbx,%r12), %ebp
	testl	%ebp, %ebp
	jle	.LBB2_17
# %bb.15:                               # %.lr.ph
                                        #   in Loop: Header=BB2_14 Depth=1
	leaq	2(%r12), %r13
.LBB2_16:                               #   Parent Loop BB2_14 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movl	$16, %edi
	callq	_Znwm
	movq	%r13, 8(%rax)
	movq	(%r15), %rcx
	movq	%rcx, (%rax)
	movq	%rax, (%r15)
	decl	%ebp
	jne	.LBB2_16
.LBB2_17:                               # %._crit_edge
                                        #   in Loop: Header=BB2_14 Depth=1
	incq	%r12
	cmpq	%r14, %r12
	jne	.LBB2_14
# %bb.18:
	xorl	%ebp, %ebp
	jmp	.LBB2_19
.LBB2_1:
	movl	%eax, %ebp
	movq	stderr(%rip), %rcx
	movl	$.L.str.5, %edi
	movl	$63, %esi
	jmp	.LBB2_2
.LBB2_4:
	movl	%eax, %ebp
	movq	stderr(%rip), %rcx
	movl	$.L.str.6, %edi
	movl	$17, %esi
	jmp	.LBB2_2
.LBB2_8:
	movl	%eax, %ebp
	movq	stderr(%rip), %r14
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.7, %esi
	movq	%r14, %rdi
	movq	%rax, %rdx
	xorl	%eax, %eax
	callq	fprintf
	jmp	.LBB2_19
.LBB2_10:
	movl	%eax, %ebp
	movq	stderr(%rip), %rdi
	movl	$.L.str.8, %esi
	movl	%eax, %edx
	xorl	%eax, %eax
	callq	fprintf
	jmp	.LBB2_19
.LBB2_20:
	movl	%eax, %ebp
	movq	stderr(%rip), %rcx
	movl	$.L.str.9, %edi
	movl	$21, %esi
.LBB2_2:                                # %.loopexit
	movl	$1, %edx
	callq	fwrite@PLT
.LBB2_19:                               # %.loopexit
	movq	%rbx, %rdi
	callq	_ZdaPv
	movq	8(%rsp), %rdi
	callq	hipFree
	movl	%ebp, %eax
	addq	$24, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z26findSimpleDividersWithCUDAPSt12forward_listIxSaIxEExi, .Lfunc_end2-_Z26findSimpleDividersWithCUDAPSt12forward_listIxSaIxEExi
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB3_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB3_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z23getSimpleDividersKernelPcxxi, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end3:
	.size	__hip_module_ctor, .Lfunc_end3-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB4_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB4_2:
	retq
.Lfunc_end4:
	.size	__hip_module_dtor, .Lfunc_end4-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z23getSimpleDividersKernelPcxxi,@object # @_Z23getSimpleDividersKernelPcxxi
	.section	.rodata,"a",@progbits
	.globl	_Z23getSimpleDividersKernelPcxxi
	.p2align	3, 0x0
_Z23getSimpleDividersKernelPcxxi:
	.quad	_Z38__device_stub__getSimpleDividersKernelPcxxi
	.size	_Z23getSimpleDividersKernelPcxxi, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"Write value:"
	.size	.L.str, 13

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"findSimpleDividersWithCUDA failed!"
	.size	.L.str.1, 35

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"It's done in "
	.size	.L.str.2, 14

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"ms"
	.size	.L.str.3, 3

	.type	.L.str.4,@object                # @.str.4
.L.str.4:
	.asciz	"hipDeviceReset failed!"
	.size	.L.str.4, 23

	.type	.L.str.5,@object                # @.str.5
.L.str.5:
	.asciz	"hipSetDevice failed!  Do you have a CUDA-capable GPU installed?"
	.size	.L.str.5, 64

	.type	.L.str.6,@object                # @.str.6
.L.str.6:
	.asciz	"hipMalloc failed!"
	.size	.L.str.6, 18

	.type	.L.str.7,@object                # @.str.7
.L.str.7:
	.asciz	"addKernel launch failed: %s\n"
	.size	.L.str.7, 29

	.type	.L.str.8,@object                # @.str.8
.L.str.8:
	.asciz	"hipDeviceSynchronize returned error code %d after launching addKernel!\n"
	.size	.L.str.8, 72

	.type	.L.str.9,@object                # @.str.9
.L.str.9:
	.asciz	"hipMemcpy 260 failed!"
	.size	.L.str.9, 22

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z23getSimpleDividersKernelPcxxi"
	.size	.L__unnamed_1, 33

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z38__device_stub__getSimpleDividersKernelPcxxi
	.addrsig_sym __gxx_personality_v0
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Unwind_Resume
	.addrsig_sym _Z23getSimpleDividersKernelPcxxi
	.addrsig_sym _ZSt4cout
	.addrsig_sym _ZSt3cin
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z23getSimpleDividersKernelPcxxi ; -- Begin function _Z23getSimpleDividersKernelPcxxi
	.globl	_Z23getSimpleDividersKernelPcxxi
	.p2align	8
	.type	_Z23getSimpleDividersKernelPcxxi,@function
_Z23getSimpleDividersKernelPcxxi:       ; @_Z23getSimpleDividersKernelPcxxi
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x18
	s_load_b128 s[4:7], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s15, s15, s2
	s_load_b64 s[2:3], s[0:1], 0x10
	s_add_u32 s0, s15, s6
	s_addc_u32 s1, 0, s7
	v_add_co_u32 v2, s0, s0, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e64 v3, null, s1, 0, s0
	v_ashrrev_i32_e32 v10, 31, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v2, v10
	v_add_co_ci_u32_e32 v1, vcc_lo, v3, v10, vcc_lo
	s_waitcnt lgkmcnt(0)
	s_ashr_i32 s8, s3, 31
	v_xor_b32_e32 v11, v0, v10
	s_delay_alu instid0(VALU_DEP_2)
	v_xor_b32_e32 v12, v1, v10
	s_add_u32 s0, s2, s8
	s_mov_b32 s9, s8
	s_addc_u32 s1, s3, s8
	v_cvt_f32_u32_e32 v4, v11
	v_cvt_f32_u32_e32 v5, v12
	v_sub_co_u32 v13, vcc_lo, 0, v11
	v_sub_co_ci_u32_e32 v14, vcc_lo, 0, v12, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmamk_f32 v0, v5, 0x4f800000, v4
	s_xor_b64 s[0:1], s[0:1], s[8:9]
	v_rcp_f32_e32 v0, v0
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v0, 0x5f7ffffc, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v1, 0x2f800000, v0
	v_trunc_f32_e32 v1, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmamk_f32 v0, v1, 0xcf800000, v0
	v_cvt_u32_f32_e32 v15, v1
	v_cvt_u32_f32_e32 v16, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v6, v13, v15
	v_mul_lo_u32 v7, v14, v16
	v_mad_u64_u32 v[0:1], null, v13, v16, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add3_u32 v17, v1, v6, v7
	v_mul_hi_u32 v18, v16, v0
	v_mad_u64_u32 v[8:9], null, v15, v0, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[6:7], null, v16, v17, 0
	v_mad_u64_u32 v[0:1], null, v15, v17, 0
	v_add_co_u32 v6, vcc_lo, v18, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v7, vcc_lo, 0, v7, vcc_lo
	v_add_co_u32 v6, vcc_lo, v6, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v6, vcc_lo, v7, v9, vcc_lo
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
	v_add_co_u32 v0, vcc_lo, v6, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
	v_add_co_u32 v16, vcc_lo, v16, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v15, vcc_lo, v15, v1, vcc_lo
	v_mul_lo_u32 v6, v14, v16
	v_mad_u64_u32 v[0:1], null, v13, v16, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v7, v13, v15
	v_mul_hi_u32 v18, v16, v0
	v_mad_u64_u32 v[8:9], null, v15, v0, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v17, v1, v7, v6
	v_mad_u64_u32 v[6:7], null, v16, v17, 0
	v_mad_u64_u32 v[0:1], null, v15, v17, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v6, vcc_lo, v18, v6
	v_add_co_ci_u32_e32 v7, vcc_lo, 0, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v6, vcc_lo, v6, v8
	v_add_co_ci_u32_e32 v6, vcc_lo, v7, v9, vcc_lo
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v6, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v8, vcc_lo, v16, v0
	v_add_co_ci_u32_e32 v15, vcc_lo, v15, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_hi_u32 v16, s0, v8
	v_mad_u64_u32 v[6:7], null, s1, v8, 0
	v_mad_u64_u32 v[0:1], null, s0, v15, 0
	v_mad_u64_u32 v[8:9], null, s1, v15, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v0, vcc_lo, v16, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, v6
	v_add_co_ci_u32_e32 v0, vcc_lo, v1, v7, vcc_lo
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v6, vcc_lo, v0, v8
	v_add_co_ci_u32_e32 v7, vcc_lo, 0, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_lo_u32 v8, v12, v6
	v_mad_u64_u32 v[0:1], null, v11, v6, 0
	v_mul_lo_u32 v6, v11, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_co_u32 v0, vcc_lo, s0, v0
	v_add3_u32 v1, v1, v6, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v6, s1, v1
	v_sub_co_ci_u32_e64 v6, s0, v6, v12, vcc_lo
	v_sub_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	v_sub_co_u32 v7, vcc_lo, v0, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_3)
	v_subrev_co_ci_u32_e64 v8, s0, 0, v6, vcc_lo
	v_cmp_ge_u32_e64 s0, v0, v11
	v_sub_co_ci_u32_e32 v6, vcc_lo, v6, v12, vcc_lo
	v_cmp_ge_u32_e32 vcc_lo, v1, v12
	s_mov_b32 s1, exec_lo
	v_cndmask_b32_e64 v9, 0, -1, s0
	v_cmp_ge_u32_e64 s0, v7, v11
	v_cndmask_b32_e64 v17, 0, -1, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, v8, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v15, 0, -1, s0
	v_cmp_ge_u32_e64 s0, v8, v12
	v_cndmask_b32_e64 v16, 0, -1, s0
	v_cmp_eq_u32_e64 s0, v1, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v15, v16, v15, vcc_lo
	v_sub_co_u32 v16, vcc_lo, v7, v11
	v_subrev_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, 0, v15
	v_cndmask_b32_e64 v9, v17, v9, s0
	s_mov_b32 s0, -1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v7, v7, v16 :: v_dual_cndmask_b32 v6, v8, v6
	v_cmp_ne_u32_e32 vcc_lo, 0, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v0, v0, v7 :: v_dual_cndmask_b32 v1, v1, v6
	v_sub_co_u32 v8, vcc_lo, v2, s6
	v_subrev_co_ci_u32_e32 v9, vcc_lo, s7, v3, vcc_lo
	v_xor_b32_e32 v0, s8, v0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v1, s8, v1
	v_sub_co_u32 v6, vcc_lo, v0, s8
	s_delay_alu instid0(VALU_DEP_2)
	v_subrev_co_ci_u32_e32 v7, vcc_lo, s8, v1, vcc_lo
	v_add_co_u32 v0, vcc_lo, s4, v8
	v_add_co_ci_u32_e32 v1, vcc_lo, s5, v9, vcc_lo
	v_mov_b32_e32 v8, 0
	global_store_b8 v[0:1], v8, off
	v_cmpx_eq_u64_e32 0, v[6:7]
	s_cbranch_execz .LBB0_11
; %bb.1:
	v_cvt_f64_i32_e32 v[6:7], v3
	v_cvt_f64_u32_e32 v[2:3], v2
	s_mov_b32 s1, exec_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ldexp_f64 v[6:7], v[6:7], 32
	v_add_f64 v[2:3], v[6:7], v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_gt_f64_e32 vcc_lo, 0x10000000, v[2:3]
	v_cndmask_b32_e64 v6, 0, 1, vcc_lo
	v_lshlrev_b32_e32 v6, 8, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ldexp_f64 v[2:3], v[2:3], v6
	v_rsq_f64_e32 v[6:7], v[2:3]
	s_waitcnt_depctr 0xfff
	v_mul_f64 v[8:9], v[2:3], v[6:7]
	v_mul_f64 v[6:7], v[6:7], 0.5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[15:16], -v[6:7], v[8:9], 0.5
	v_fma_f64 v[8:9], v[8:9], v[15:16], v[8:9]
	v_fma_f64 v[6:7], v[6:7], v[15:16], v[6:7]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[15:16], -v[8:9], v[8:9], v[2:3]
	v_fma_f64 v[8:9], v[15:16], v[6:7], v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[15:16], -v[8:9], v[8:9], v[2:3]
	v_fma_f64 v[6:7], v[15:16], v[6:7], v[8:9]
	v_cndmask_b32_e64 v8, 0, 0xffffff80, vcc_lo
	v_cmp_class_f64_e64 vcc_lo, v[2:3], 0x260
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ldexp_f64 v[6:7], v[6:7], v8
	v_dual_cndmask_b32 v3, v7, v3 :: v_dual_cndmask_b32 v2, v6, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_le_f64_e32 2.0, v[2:3]
	s_cbranch_execz .LBB0_7
; %bb.2:                                ; %.lr.ph.i.preheader
	s_mov_b64 s[4:5], 2
	s_mov_b32 s8, 0
                                        ; implicit-def: $sgpr9
                                        ; implicit-def: $sgpr11
                                        ; implicit-def: $sgpr10
.LBB0_3:                                ; %.lr.ph.i
                                        ; =>This Inner Loop Header: Depth=1
	s_ashr_i32 s6, s5, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_add_u32 s12, s4, s6
	s_mov_b32 s7, s6
	s_addc_u32 s13, s5, s6
	s_xor_b64 s[6:7], s[12:13], s[6:7]
	s_delay_alu instid0(SALU_CYCLE_1)
	v_cvt_f32_u32_e32 v6, s6
	v_cvt_f32_u32_e32 v7, s7
	s_sub_u32 s0, 0, s6
	s_subb_u32 s12, 0, s7
	s_or_b32 s10, s10, exec_lo
	s_or_b32 s11, s11, exec_lo
	v_fmac_f32_e32 v6, 0x4f800000, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v6, v6
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v6, 0x5f7ffffc, v6
	v_mul_f32_e32 v7, 0x2f800000, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_trunc_f32_e32 v7, v7
	v_fmac_f32_e32 v6, 0xcf800000, v7
	v_cvt_u32_f32_e32 v7, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_u32_f32_e32 v6, v6
	v_mul_lo_u32 v8, s0, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v9, s0, v6
	v_mul_lo_u32 v15, s12, v6
	v_add_nc_u32_e32 v8, v9, v8
	v_mul_lo_u32 v9, s0, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v8, v8, v15
	v_mul_hi_u32 v15, v6, v9
	s_delay_alu instid0(VALU_DEP_2)
	v_mul_lo_u32 v16, v6, v8
	v_mul_hi_u32 v17, v6, v8
	v_mul_hi_u32 v18, v7, v9
	v_mul_lo_u32 v9, v7, v9
	v_mul_hi_u32 v19, v7, v8
	v_mul_lo_u32 v8, v7, v8
	v_add_co_u32 v15, vcc_lo, v15, v16
	v_add_co_ci_u32_e32 v16, vcc_lo, 0, v17, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v9, vcc_lo, v15, v9
	v_add_co_ci_u32_e32 v9, vcc_lo, v16, v18, vcc_lo
	v_add_co_ci_u32_e32 v15, vcc_lo, 0, v19, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v8, vcc_lo, v9, v8
	v_add_co_ci_u32_e32 v9, vcc_lo, 0, v15, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v6, vcc_lo, v6, v8
	v_add_co_ci_u32_e32 v7, vcc_lo, v7, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_hi_u32 v8, s0, v6
	v_mul_lo_u32 v15, s12, v6
	v_mul_lo_u32 v9, s0, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v8, v8, v9
	v_mul_lo_u32 v9, s0, v6
	v_add_nc_u32_e32 v8, v8, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v15, v6, v9
	v_mul_lo_u32 v16, v6, v8
	v_mul_hi_u32 v17, v6, v8
	v_mul_hi_u32 v18, v7, v9
	v_mul_lo_u32 v9, v7, v9
	v_mul_hi_u32 v19, v7, v8
	v_mul_lo_u32 v8, v7, v8
	v_add_co_u32 v15, vcc_lo, v15, v16
	v_add_co_ci_u32_e32 v16, vcc_lo, 0, v17, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v9, vcc_lo, v15, v9
	v_add_co_ci_u32_e32 v9, vcc_lo, v16, v18, vcc_lo
	v_add_co_ci_u32_e32 v15, vcc_lo, 0, v19, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v8, vcc_lo, v9, v8
	v_add_co_ci_u32_e32 v9, vcc_lo, 0, v15, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v15, vcc_lo, v6, v8
	v_add_co_ci_u32_e32 v17, vcc_lo, v7, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_hi_u32 v18, v11, v15
	v_mad_u64_u32 v[8:9], null, v12, v15, 0
	v_mad_u64_u32 v[6:7], null, v11, v17, 0
	v_mad_u64_u32 v[15:16], null, v12, v17, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v6, vcc_lo, v18, v6
	v_add_co_ci_u32_e32 v7, vcc_lo, 0, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v6, vcc_lo, v6, v8
	v_add_co_ci_u32_e32 v6, vcc_lo, v7, v9, vcc_lo
	v_add_co_ci_u32_e32 v7, vcc_lo, 0, v16, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v8, vcc_lo, v6, v15
	v_add_co_ci_u32_e32 v9, vcc_lo, 0, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_lo_u32 v15, s7, v8
	v_mad_u64_u32 v[6:7], null, s6, v8, 0
	v_mul_lo_u32 v8, s6, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_co_u32 v6, vcc_lo, v11, v6
	v_add3_u32 v7, v7, v8, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v8, v12, v7
	v_subrev_co_ci_u32_e64 v8, s0, s7, v8, vcc_lo
	v_sub_co_ci_u32_e32 v7, vcc_lo, v12, v7, vcc_lo
	v_sub_co_u32 v9, vcc_lo, v6, s6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_subrev_co_ci_u32_e64 v15, s0, 0, v8, vcc_lo
	v_cmp_le_u32_e64 s0, s6, v6
	v_subrev_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s7, v7
	v_cndmask_b32_e64 v16, 0, -1, s0
	v_cmp_le_u32_e64 s0, s6, v9
	v_cndmask_b32_e64 v19, 0, -1, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, s7, v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v17, 0, -1, s0
	v_cmp_le_u32_e64 s0, s7, v15
	v_cndmask_b32_e64 v18, 0, -1, s0
	v_cmp_eq_u32_e64 s0, s7, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v17, v18, v17, vcc_lo
	v_sub_co_u32 v18, vcc_lo, v9, s6
	v_subrev_co_ci_u32_e32 v8, vcc_lo, 0, v8, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, 0, v17
	v_cndmask_b32_e64 v16, v19, v16, s0
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v9, v9, v18 :: v_dual_cndmask_b32 v8, v15, v8
	v_cmp_ne_u32_e32 vcc_lo, 0, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_cndmask_b32 v6, v6, v9 :: v_dual_cndmask_b32 v7, v7, v8
	v_xor_b32_e32 v6, v6, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v7, v7, v10
	v_sub_co_u32 v6, vcc_lo, v6, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_co_ci_u32_e32 v7, vcc_lo, v7, v10, vcc_lo
	v_cmpx_ne_u64_e32 0, v[6:7]
; %bb.4:                                ;   in Loop: Header=BB0_3 Depth=1
	s_add_u32 s4, s4, 1
	s_addc_u32 s5, s5, 0
	v_cvt_f64_i32_e32 v[6:7], s4
	s_and_not1_b32 s6, s11, exec_lo
	s_and_not1_b32 s10, s10, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_nge_f64_e32 vcc_lo, v[2:3], v[6:7]
	s_and_b32 s7, vcc_lo, exec_lo
	s_or_b32 s11, s6, s7
; %bb.5:                                ; %Flow
                                        ;   in Loop: Header=BB0_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	s_xor_b32 s0, s10, -1
	s_and_b32 s6, exec_lo, s11
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_or_b32 s8, s6, s8
	s_and_not1_b32 s6, s9, exec_lo
	s_and_b32 s0, s0, exec_lo
	s_or_b32 s9, s6, s0
	s_and_not1_b32 exec_lo, exec_lo, s8
	s_cbranch_execnz .LBB0_3
; %bb.6:                                ; %loop.exit.guard
	s_or_b32 exec_lo, exec_lo, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_not1_b32 s0, s9, exec_lo
.LBB0_7:                                ; %Flow28
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB0_11
; %bb.8:                                ; %.lr.ph.preheader
	v_fmac_f32_e32 v4, 0x4f800000, v5
	v_mov_b32_e32 v18, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v2, v4
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v2, 0x5f7ffffc, v2
	v_mul_f32_e32 v3, 0x2f800000, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_trunc_f32_e32 v3, v3
	v_fmac_f32_e32 v2, 0xcf800000, v3
	v_cvt_u32_f32_e32 v15, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_u32_f32_e32 v16, v2
	v_mul_lo_u32 v2, v13, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v3, v14, v16
	v_mad_u64_u32 v[8:9], null, v13, v16, 0
	v_add3_u32 v6, v9, v2, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v17, v16, v8
	v_mad_u64_u32 v[2:3], null, v16, v6, 0
	v_mad_u64_u32 v[4:5], null, v15, v6, 0
	v_mad_u64_u32 v[6:7], null, v15, v8, 0
	v_dual_mov_b32 v9, s3 :: v_dual_mov_b32 v8, s2
	s_mov_b32 s2, 0
.LBB0_9:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_ashrrev_i32_e32 v19, 31, v9
	v_add_co_u32 v20, vcc_lo, v17, v2
	v_add_co_ci_u32_e32 v21, vcc_lo, 0, v3, vcc_lo
	v_add_co_u32 v8, vcc_lo, v8, v19
	v_add_co_ci_u32_e32 v9, vcc_lo, v9, v19, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v20, vcc_lo, v20, v6
	v_add_co_ci_u32_e32 v20, vcc_lo, v21, v7, vcc_lo
	v_add_co_ci_u32_e32 v21, vcc_lo, 0, v5, vcc_lo
	v_xor_b32_e32 v25, v8, v19
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_co_u32 v8, vcc_lo, v20, v4
	v_xor_b32_e32 v24, v9, v19
	v_add_co_ci_u32_e32 v9, vcc_lo, 0, v21, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v26, vcc_lo, v16, v8
	v_xor_b32_e32 v23, v19, v10
	v_add_co_ci_u32_e32 v27, vcc_lo, v15, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[8:9], null, v13, v26, 0
	v_mul_lo_u32 v21, v14, v26
	v_mul_lo_u32 v22, v13, v27
	v_and_b32_e32 v18, 0xff, v18
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_mad_u64_u32 v[19:20], null, v27, v8, 0
	v_mul_hi_u32 v28, v26, v8
	v_add3_u32 v29, v9, v22, v21
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u16 v18, v18, 1
	v_mad_u64_u32 v[8:9], null, v26, v29, 0
	v_mad_u64_u32 v[21:22], null, v27, v29, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v8, vcc_lo, v28, v8
	v_add_co_ci_u32_e32 v9, vcc_lo, 0, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v8, vcc_lo, v8, v19
	v_add_co_ci_u32_e32 v8, vcc_lo, v9, v20, vcc_lo
	v_add_co_ci_u32_e32 v9, vcc_lo, 0, v22, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v8, vcc_lo, v8, v21
	v_add_co_ci_u32_e32 v9, vcc_lo, 0, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v26, vcc_lo, v26, v8
	v_add_co_ci_u32_e32 v27, vcc_lo, v27, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_hi_u32 v28, v25, v26
	v_mad_u64_u32 v[8:9], null, v24, v26, 0
	v_mad_u64_u32 v[19:20], null, v25, v27, 0
	v_mad_u64_u32 v[21:22], null, v24, v27, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v19, vcc_lo, v28, v19
	v_add_co_ci_u32_e32 v20, vcc_lo, 0, v20, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v8, vcc_lo, v19, v8
	v_add_co_ci_u32_e32 v8, vcc_lo, v20, v9, vcc_lo
	v_add_co_ci_u32_e32 v9, vcc_lo, 0, v22, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v19, vcc_lo, v8, v21
	v_add_co_ci_u32_e32 v20, vcc_lo, 0, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_lo_u32 v21, v12, v19
	v_mad_u64_u32 v[8:9], null, v11, v19, 0
	v_mul_lo_u32 v29, v11, v20
	v_add_co_u32 v22, vcc_lo, v19, 1
	v_add_co_ci_u32_e32 v31, vcc_lo, 0, v20, vcc_lo
	v_add_co_u32 v28, s0, v19, 2
	v_sub_co_u32 v8, vcc_lo, v25, v8
	v_add3_u32 v9, v9, v29, v21
	v_add_co_ci_u32_e64 v30, s0, 0, v20, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v21, v24, v9
	v_sub_co_ci_u32_e64 v21, s0, v21, v12, vcc_lo
	v_sub_co_ci_u32_e32 v9, vcc_lo, v24, v9, vcc_lo
	v_cmp_ge_u32_e32 vcc_lo, v8, v11
	v_sub_co_u32 v25, s0, v8, v11
	v_cndmask_b32_e64 v8, 0, -1, vcc_lo
	v_subrev_co_ci_u32_e64 v21, vcc_lo, 0, v21, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_ge_u32_e32 vcc_lo, v25, v11
	v_cmp_ge_u32_e64 s0, v21, v12
	v_cndmask_b32_e64 v24, 0, -1, vcc_lo
	v_cmp_ge_u32_e32 vcc_lo, v9, v12
	v_cndmask_b32_e64 v25, 0, -1, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, v9, v12
	v_cndmask_b32_e64 v9, 0, -1, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v8, v25, v8, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, v21, v12
	v_cndmask_b32_e32 v9, v9, v24, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_cmp_ne_u32_e32 vcc_lo, 0, v9
	v_cndmask_b32_e32 v9, v31, v30, vcc_lo
	v_cmp_ne_u32_e64 s0, 0, v8
	v_cndmask_b32_e32 v8, v22, v28, vcc_lo
	v_cndmask_b32_e64 v9, v20, v9, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v8, v19, v8, s0
	v_xor_b32_e32 v9, v9, v23
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v8, v8, v23
	v_sub_co_u32 v8, vcc_lo, v8, v23
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_co_ci_u32_e32 v9, vcc_lo, v9, v23, vcc_lo
	v_ashrrev_i32_e32 v25, 31, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_co_u32 v19, vcc_lo, v8, v25
	v_add_co_ci_u32_e32 v20, vcc_lo, v9, v25, vcc_lo
	v_xor_b32_e32 v28, v19, v25
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v29, v20, v25
	v_mad_u64_u32 v[19:20], null, v28, v27, 0
	v_mul_hi_u32 v30, v28, v26
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[21:22], null, v29, v26, 0
	v_mad_u64_u32 v[23:24], null, v29, v27, 0
	v_add_co_u32 v19, vcc_lo, v30, v19
	v_add_co_ci_u32_e32 v20, vcc_lo, 0, v20, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v19, vcc_lo, v19, v21
	v_add_co_ci_u32_e32 v19, vcc_lo, v20, v22, vcc_lo
	v_add_co_ci_u32_e32 v20, vcc_lo, 0, v24, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v21, vcc_lo, v19, v23
	v_add_co_ci_u32_e32 v22, vcc_lo, 0, v20, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_lo_u32 v23, v12, v21
	v_mad_u64_u32 v[19:20], null, v11, v21, 0
	v_mul_lo_u32 v21, v11, v22
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_co_u32 v19, vcc_lo, v28, v19
	v_add3_u32 v20, v20, v21, v23
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v21, v29, v20
	v_sub_co_ci_u32_e64 v21, s0, v21, v12, vcc_lo
	v_sub_co_ci_u32_e32 v20, vcc_lo, v29, v20, vcc_lo
	v_cmp_ge_u32_e32 vcc_lo, v19, v11
	v_sub_co_u32 v22, s0, v19, v11
	v_cndmask_b32_e64 v23, 0, -1, vcc_lo
	v_subrev_co_ci_u32_e64 v24, vcc_lo, 0, v21, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_ge_u32_e32 vcc_lo, v22, v11
	v_cmp_eq_u32_e64 s1, v24, v12
	v_cndmask_b32_e64 v26, 0, -1, vcc_lo
	v_sub_co_ci_u32_e64 v21, vcc_lo, v21, v12, s0
	v_cmp_ge_u32_e64 s0, v20, v12
	v_sub_co_u32 v27, vcc_lo, v22, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_subrev_co_ci_u32_e32 v21, vcc_lo, 0, v21, vcc_lo
	v_cndmask_b32_e64 v28, 0, -1, s0
	v_cmp_ge_u32_e64 s0, v24, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v29, 0, -1, s0
	v_cmp_eq_u32_e64 s0, v20, v12
	v_cndmask_b32_e64 v26, v29, v26, s1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v23, v28, v23, s0
	v_cmp_ne_u32_e32 vcc_lo, 0, v26
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_ne_u32_e64 s0, 0, v23
	v_dual_cndmask_b32 v21, v24, v21 :: v_dual_cndmask_b32 v22, v22, v27
	v_cndmask_b32_e64 v20, v20, v21, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v19, v19, v22, s0
	v_xor_b32_e32 v20, v20, v25
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v19, v19, v25
	v_sub_co_u32 v19, vcc_lo, v19, v25
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_co_ci_u32_e32 v20, vcc_lo, v20, v25, vcc_lo
	v_cmp_ne_u64_e32 vcc_lo, 0, v[19:20]
	s_or_b32 s2, vcc_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s2
	s_cbranch_execnz .LBB0_9
; %bb.10:                               ; %._Z7isPrimex.exit.loopexit_crit_edge
	s_or_b32 exec_lo, exec_lo, s2
	global_store_b8 v[0:1], v18, off
.LBB0_11:                               ; %_Z7isPrimex.exit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z23getSimpleDividersKernelPcxxi
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 28
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 32
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z23getSimpleDividersKernelPcxxi, .Lfunc_end0-_Z23getSimpleDividersKernelPcxxi
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 3216
; NumSgprs: 18
; NumVgprs: 32
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 3
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 32
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           8
        .value_kind:     by_value
      - .offset:         16
        .size:           8
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     by_value
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 28
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z23getSimpleDividersKernelPcxxi
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z23getSimpleDividersKernelPcxxi.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     32
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
