/*=========================================================================
 *
 *  Copyright Insight Software Consortium
 *
 *  Licensed under the Apache License, Version 2.0 (the "License");
 *  you may not use this file except in compliance with the License.
 *  You may obtain a copy of the License at
 *
 *         http://www.apache.org/licenses/LICENSE-2.0.txt
 *
 *  Unless required by applicable law or agreed to in writing, software
 *  distributed under the License is distributed on an "AS IS" BASIS,
 *  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 *  See the License for the specific language governing permissions and
 *  limitations under the License.
 *
 *=========================================================================*/

#include <stdio.h>

/** This is for parallel reduction and is modified from NVIDIA's example code */

// Utility class used to avoid linker errors with extern
// unsized shared memory arrays with templated type
template<class T>
struct SharedMemory
{
    __device__ inline operator T *()
    {
        extern __shared__ int __smem[];
        return (T *)__smem;
    }

    __device__ inline operator const T *() const
    {
        extern __shared__ int __smem[];
        return (T *)__smem;
    }
};

// specialize for double to avoid unaligned memory
// access compile errors
template<>
struct SharedMemory<double>
{
    __device__ inline operator double *()
    {
        extern __shared__ double __smem_d[];
        return (double *)__smem_d;
    }

    __device__ inline operator const double *() const
    {
        extern __shared__ double __smem_d[];
        return (double *)__smem_d;
    }
};

// The following defines are set during runtime compilation, see reduction.cpp
// #define T float
// #define blockSize 128
// #define nIsPow2 1
/*
    This version is completely unrolled.  It uses a template parameter to achieve
    optimal code for any (power of 2) number of threads.  This requires a switch
    statement in the host code to handle all the different thread block sizes at
    compile time.

    Note, this kernel needs a minimum of 64*sizeof(T) bytes of shared memory.
    In other words if blockSize <= 32, allocate 64*sizeof(T) bytes.
    If blockSize > 32, allocate blockSize*sizeof(T) bytes.
*/
template <class T>
__device__ void reduce5(T *g_idata, T *g_odata, unsigned int n, unsigned int blockSize)
{
    T *sdata = SharedMemory<T>();

    // perform first level of reduction,
    // reading from global memory, writing to shared memory
    unsigned int tid = threadIdx.x;
    unsigned int i = blockIdx.x * (blockSize * 2) + threadIdx.x;

    T mySum = (i < n) ? g_idata[i] : 0;

    if (i + blockSize < n)
        mySum += g_idata[i+blockSize];

    sdata[tid] = mySum;
    __syncthreads();

    // do reduction in shared mem
    if (blockSize >= 512) { if (tid < 256) { sdata[tid] = mySum = mySum + sdata[tid + 256]; } __syncthreads(); }
    if (blockSize >= 256) { if (tid < 128) { sdata[tid] = mySum = mySum + sdata[tid + 128]; } __syncthreads(); }
    if (blockSize >= 128) { if (tid <  64) { sdata[tid] = mySum = mySum + sdata[tid +  64]; } __syncthreads(); }

    if (tid < 32)
    {
        // now that we are using warp-synchronous programming (below)
        // we need to declare our shared memory volatile so that the compiler
        // doesn't reorder stores to it and induce incorrect behavior.
        volatile T *smem = sdata;
        if (blockSize >=  64) { smem[tid] = mySum = mySum + smem[tid + 32]; }
        if (blockSize >=  32) { smem[tid] = mySum = mySum + smem[tid + 16]; }
        if (blockSize >=  16) { smem[tid] = mySum = mySum + smem[tid +  8]; }
        if (blockSize >=   8) { smem[tid] = mySum = mySum + smem[tid +  4]; }
        if (blockSize >=   4) { smem[tid] = mySum = mySum + smem[tid +  2]; }
        if (blockSize >=   2) { smem[tid] = mySum = mySum + smem[tid +  1]; }
    }

    // write result for this block to global mem
    if (tid == 0) g_odata[blockIdx.x] = sdata[0];
}

/*
    This version adds multiple elements per thread sequentially.  This reduces the overall
    cost of the algorithm while keeping the work complexity O(n) and the step complexity O(log n).
    (Brent's Theorem optimization)

    Note, this kernel needs a minimum of 64*sizeof(T) bytes of shared memory.
    In other words if blockSize <= 32, allocate 64*sizeof(T) bytes.
    If blockSize > 32, allocate blockSize*sizeof(T) bytes.
*/
template <class T>
__device__ void reduce6(T *g_idata, T *g_odata, unsigned int n, unsigned int blockSize, bool nIsPow2)
{
    T *sdata = SharedMemory<T>();

    // perform first level of reduction,
    // reading from global memory, writing to shared memory
    unsigned int tid = threadIdx.x;
    unsigned int i = blockIdx.x * (blockSize * 2) + threadIdx.x;
    unsigned int gridSize = blockSize*2*gridDim.x;

    T mySum = 0;

    // we reduce multiple elements per thread.  The number is determined by the
    // number of active thread blocks (via gridDim).  More blocks will result
    // in a larger gridSize and therefore fewer elements per thread
    while (i < n)
    {
        mySum += g_idata[i];

        // ensure we don't read out of bounds -- this is optimized away for powerOf2 sized arrays
        if (nIsPow2 || i + blockSize < n)
            mySum += g_idata[i+blockSize];

        i += gridSize;
    }

    // each thread puts its local sum into shared memory
    sdata[tid] = mySum;
    __syncthreads();

    // do reduction in shared mem
    if (blockSize >= 512) { if (tid < 256) { sdata[tid] = mySum = mySum + sdata[tid + 256]; } __syncthreads(); }
    if (blockSize >= 256) { if (tid < 128) { sdata[tid] = mySum = mySum + sdata[tid + 128]; } __syncthreads(); }
    if (blockSize >= 128) { if (tid <  64) { sdata[tid] = mySum = mySum + sdata[tid +  64]; } __syncthreads(); }

    if (tid < 32)
    {
        // now that we are using warp-synchronous programming (below)
        // we need to declare our shared memory volatile so that the compiler
        // doesn't reorder stores to it and induce incorrect behavior.
        volatile T *smem = sdata;

        if (blockSize >=  64) { smem[tid] = mySum = mySum + smem[tid + 32]; }
        if (blockSize >=  32) { smem[tid] = mySum = mySum + smem[tid + 16]; }
        if (blockSize >=  16) { smem[tid] = mySum = mySum + smem[tid +  8]; }
        if (blockSize >=   8) { smem[tid] = mySum = mySum + smem[tid +  4]; }
        if (blockSize >=   4) { smem[tid] = mySum = mySum + smem[tid +  2]; }
        if (blockSize >=   2) { smem[tid] = mySum = mySum + smem[tid +  1]; }
    }
    
    // write result for this block to global mem
    if (tid == 0)        
        g_odata[blockIdx.x] = sdata[0];
}

#define MAKE_reduce5_TEMPLATE_IMPL(_exportname_, T) \
  extern "C" __global__ void _exportname_(T* g_idata, T *g_odata, unsigned int n, unsigned int blockSize)\
  {\
    reduce5<T>(g_idata, g_odata, n, blockSize);\
  }

#define MAKE_reduce6_TEMPLATE_IMPL(_exportname_, T) \
  extern "C" __global__ void _exportname_(T* g_idata, T *g_odata, unsigned int n, unsigned int blockSize, bool nIsPow2)\
  {\
    reduce6<T>(g_idata, g_odata, n, blockSize, nIsPow2);\
  }

#define MAKE_IMPL(_func_)\
  MAKE_##_func_##_TEMPLATE_IMPL(_func_##_c, char);\
  MAKE_##_func_##_TEMPLATE_IMPL(_func_##_uc, unsigned char);\
  MAKE_##_func_##_TEMPLATE_IMPL(_func_##_s, short);\
  MAKE_##_func_##_TEMPLATE_IMPL(_func_##_i, int);\
  MAKE_##_func_##_TEMPLATE_IMPL(_func_##_ui, unsigned int);\
  MAKE_##_func_##_TEMPLATE_IMPL(_func_##_f, float);\
  MAKE_##_func_##_TEMPLATE_IMPL(_func_##_d, double);

// Export the template implementations
MAKE_IMPL(reduce5);
MAKE_IMPL(reduce6);

	.file	"tmpxft_0022c199_00000000-6_CudaReduction.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2035:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2035:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.type	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0, @function
_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0:
.LFB2202:
	.cfi_startproc
	jmp	cudaLaunchKernel@PLT
	.cfi_endproc
.LFE2202:
	.size	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0, .-_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	.globl	_Z32__device_stub__Z9reduce5_cPcS_jjPcS_jj
	.type	_Z32__device_stub__Z9reduce5_cPcS_jjPcS_jj, @function
_Z32__device_stub__Z9reduce5_cPcS_jjPcS_jj:
.LFB2057:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	32(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	40(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 72(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 80(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L3
	pushq	40(%rsp)
	.cfi_def_cfa_offset 136
	leaq	reduce5_c(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 144
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	88(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L3:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L5
	call	__stack_chk_fail@PLT
.L5:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2057:
	.size	_Z32__device_stub__Z9reduce5_cPcS_jjPcS_jj, .-_Z32__device_stub__Z9reduce5_cPcS_jjPcS_jj
	.globl	reduce5_c
	.type	reduce5_c, @function
reduce5_c:
.LFB2058:
	.cfi_startproc
	endbr64
	jmp	_Z32__device_stub__Z9reduce5_cPcS_jjPcS_jj
	.cfi_endproc
.LFE2058:
	.size	reduce5_c, .-reduce5_c
	.globl	_Z34__device_stub__Z10reduce5_ucPhS_jjPhS_jj
	.type	_Z34__device_stub__Z10reduce5_ucPhS_jjPhS_jj, @function
_Z34__device_stub__Z10reduce5_ucPhS_jjPhS_jj:
.LFB2059:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	32(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	40(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 72(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 80(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L9
	pushq	40(%rsp)
	.cfi_def_cfa_offset 136
	leaq	reduce5_uc(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 144
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	88(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L9:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L11
	call	__stack_chk_fail@PLT
.L11:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2059:
	.size	_Z34__device_stub__Z10reduce5_ucPhS_jjPhS_jj, .-_Z34__device_stub__Z10reduce5_ucPhS_jjPhS_jj
	.globl	reduce5_uc
	.type	reduce5_uc, @function
reduce5_uc:
.LFB2060:
	.cfi_startproc
	endbr64
	jmp	_Z34__device_stub__Z10reduce5_ucPhS_jjPhS_jj
	.cfi_endproc
.LFE2060:
	.size	reduce5_uc, .-reduce5_uc
	.globl	_Z32__device_stub__Z9reduce5_sPsS_jjPsS_jj
	.type	_Z32__device_stub__Z9reduce5_sPsS_jjPsS_jj, @function
_Z32__device_stub__Z9reduce5_sPsS_jjPsS_jj:
.LFB2061:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	32(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	40(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 72(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 80(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L14
	pushq	40(%rsp)
	.cfi_def_cfa_offset 136
	leaq	reduce5_s(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 144
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	88(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L14:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L16
	call	__stack_chk_fail@PLT
.L16:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2061:
	.size	_Z32__device_stub__Z9reduce5_sPsS_jjPsS_jj, .-_Z32__device_stub__Z9reduce5_sPsS_jjPsS_jj
	.globl	reduce5_s
	.type	reduce5_s, @function
reduce5_s:
.LFB2062:
	.cfi_startproc
	endbr64
	jmp	_Z32__device_stub__Z9reduce5_sPsS_jjPsS_jj
	.cfi_endproc
.LFE2062:
	.size	reduce5_s, .-reduce5_s
	.globl	_Z32__device_stub__Z9reduce5_iPiS_jjPiS_jj
	.type	_Z32__device_stub__Z9reduce5_iPiS_jjPiS_jj, @function
_Z32__device_stub__Z9reduce5_iPiS_jjPiS_jj:
.LFB2063:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	32(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	40(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 72(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 80(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L19
	pushq	40(%rsp)
	.cfi_def_cfa_offset 136
	leaq	reduce5_i(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 144
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	88(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L19:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L21
	call	__stack_chk_fail@PLT
.L21:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2063:
	.size	_Z32__device_stub__Z9reduce5_iPiS_jjPiS_jj, .-_Z32__device_stub__Z9reduce5_iPiS_jjPiS_jj
	.globl	reduce5_i
	.type	reduce5_i, @function
reduce5_i:
.LFB2064:
	.cfi_startproc
	endbr64
	jmp	_Z32__device_stub__Z9reduce5_iPiS_jjPiS_jj
	.cfi_endproc
.LFE2064:
	.size	reduce5_i, .-reduce5_i
	.globl	_Z34__device_stub__Z10reduce5_uiPjS_jjPjS_jj
	.type	_Z34__device_stub__Z10reduce5_uiPjS_jjPjS_jj, @function
_Z34__device_stub__Z10reduce5_uiPjS_jjPjS_jj:
.LFB2065:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	32(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	40(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 72(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 80(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L24
	pushq	40(%rsp)
	.cfi_def_cfa_offset 136
	leaq	reduce5_ui(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 144
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	88(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L24:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L26
	call	__stack_chk_fail@PLT
.L26:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2065:
	.size	_Z34__device_stub__Z10reduce5_uiPjS_jjPjS_jj, .-_Z34__device_stub__Z10reduce5_uiPjS_jjPjS_jj
	.globl	reduce5_ui
	.type	reduce5_ui, @function
reduce5_ui:
.LFB2066:
	.cfi_startproc
	endbr64
	jmp	_Z34__device_stub__Z10reduce5_uiPjS_jjPjS_jj
	.cfi_endproc
.LFE2066:
	.size	reduce5_ui, .-reduce5_ui
	.globl	_Z32__device_stub__Z9reduce5_fPfS_jjPfS_jj
	.type	_Z32__device_stub__Z9reduce5_fPfS_jjPfS_jj, @function
_Z32__device_stub__Z9reduce5_fPfS_jjPfS_jj:
.LFB2067:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	32(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	40(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 72(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 80(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L29
	pushq	40(%rsp)
	.cfi_def_cfa_offset 136
	leaq	reduce5_f(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 144
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	88(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L29:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L31
	call	__stack_chk_fail@PLT
.L31:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2067:
	.size	_Z32__device_stub__Z9reduce5_fPfS_jjPfS_jj, .-_Z32__device_stub__Z9reduce5_fPfS_jjPfS_jj
	.globl	reduce5_f
	.type	reduce5_f, @function
reduce5_f:
.LFB2068:
	.cfi_startproc
	endbr64
	jmp	_Z32__device_stub__Z9reduce5_fPfS_jjPfS_jj
	.cfi_endproc
.LFE2068:
	.size	reduce5_f, .-reduce5_f
	.globl	_Z32__device_stub__Z9reduce5_dPdS_jjPdS_jj
	.type	_Z32__device_stub__Z9reduce5_dPdS_jjPdS_jj, @function
_Z32__device_stub__Z9reduce5_dPdS_jjPdS_jj:
.LFB2069:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	32(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	40(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 72(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 80(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L34
	pushq	40(%rsp)
	.cfi_def_cfa_offset 136
	leaq	reduce5_d(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 144
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	88(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L34:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L36
	call	__stack_chk_fail@PLT
.L36:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2069:
	.size	_Z32__device_stub__Z9reduce5_dPdS_jjPdS_jj, .-_Z32__device_stub__Z9reduce5_dPdS_jjPdS_jj
	.globl	reduce5_d
	.type	reduce5_d, @function
reduce5_d:
.LFB2070:
	.cfi_startproc
	endbr64
	jmp	_Z32__device_stub__Z9reduce5_dPdS_jjPdS_jj
	.cfi_endproc
.LFE2070:
	.size	reduce5_d, .-reduce5_d
	.globl	_Z33__device_stub__Z9reduce6_cPcS_jjbPcS_jjb
	.type	_Z33__device_stub__Z9reduce6_cPcS_jjbPcS_jjb, @function
_Z33__device_stub__Z9reduce6_cPcS_jjbPcS_jjb:
.LFB2071:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	48(%rsp), %rcx
	movb	%r8b, 4(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L39
	pushq	48(%rsp)
	.cfi_def_cfa_offset 152
	leaq	reduce6_c(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 160
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L39:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L41
	call	__stack_chk_fail@PLT
.L41:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2071:
	.size	_Z33__device_stub__Z9reduce6_cPcS_jjbPcS_jjb, .-_Z33__device_stub__Z9reduce6_cPcS_jjbPcS_jjb
	.globl	reduce6_c
	.type	reduce6_c, @function
reduce6_c:
.LFB2072:
	.cfi_startproc
	endbr64
	movzbl	%r8b, %r8d
	jmp	_Z33__device_stub__Z9reduce6_cPcS_jjbPcS_jjb
	.cfi_endproc
.LFE2072:
	.size	reduce6_c, .-reduce6_c
	.globl	_Z35__device_stub__Z10reduce6_ucPhS_jjbPhS_jjb
	.type	_Z35__device_stub__Z10reduce6_ucPhS_jjbPhS_jjb, @function
_Z35__device_stub__Z10reduce6_ucPhS_jjbPhS_jjb:
.LFB2073:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	48(%rsp), %rcx
	movb	%r8b, 4(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L44
	pushq	48(%rsp)
	.cfi_def_cfa_offset 152
	leaq	reduce6_uc(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 160
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L44:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L46
	call	__stack_chk_fail@PLT
.L46:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2073:
	.size	_Z35__device_stub__Z10reduce6_ucPhS_jjbPhS_jjb, .-_Z35__device_stub__Z10reduce6_ucPhS_jjbPhS_jjb
	.globl	reduce6_uc
	.type	reduce6_uc, @function
reduce6_uc:
.LFB2074:
	.cfi_startproc
	endbr64
	movzbl	%r8b, %r8d
	jmp	_Z35__device_stub__Z10reduce6_ucPhS_jjbPhS_jjb
	.cfi_endproc
.LFE2074:
	.size	reduce6_uc, .-reduce6_uc
	.globl	_Z33__device_stub__Z9reduce6_sPsS_jjbPsS_jjb
	.type	_Z33__device_stub__Z9reduce6_sPsS_jjbPsS_jjb, @function
_Z33__device_stub__Z9reduce6_sPsS_jjbPsS_jjb:
.LFB2075:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	48(%rsp), %rcx
	movb	%r8b, 4(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L49
	pushq	48(%rsp)
	.cfi_def_cfa_offset 152
	leaq	reduce6_s(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 160
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L49:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L51
	call	__stack_chk_fail@PLT
.L51:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2075:
	.size	_Z33__device_stub__Z9reduce6_sPsS_jjbPsS_jjb, .-_Z33__device_stub__Z9reduce6_sPsS_jjbPsS_jjb
	.globl	reduce6_s
	.type	reduce6_s, @function
reduce6_s:
.LFB2076:
	.cfi_startproc
	endbr64
	movzbl	%r8b, %r8d
	jmp	_Z33__device_stub__Z9reduce6_sPsS_jjbPsS_jjb
	.cfi_endproc
.LFE2076:
	.size	reduce6_s, .-reduce6_s
	.globl	_Z33__device_stub__Z9reduce6_iPiS_jjbPiS_jjb
	.type	_Z33__device_stub__Z9reduce6_iPiS_jjbPiS_jjb, @function
_Z33__device_stub__Z9reduce6_iPiS_jjbPiS_jjb:
.LFB2077:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	48(%rsp), %rcx
	movb	%r8b, 4(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L54
	pushq	48(%rsp)
	.cfi_def_cfa_offset 152
	leaq	reduce6_i(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 160
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L54:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L56
	call	__stack_chk_fail@PLT
.L56:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2077:
	.size	_Z33__device_stub__Z9reduce6_iPiS_jjbPiS_jjb, .-_Z33__device_stub__Z9reduce6_iPiS_jjbPiS_jjb
	.globl	reduce6_i
	.type	reduce6_i, @function
reduce6_i:
.LFB2078:
	.cfi_startproc
	endbr64
	movzbl	%r8b, %r8d
	jmp	_Z33__device_stub__Z9reduce6_iPiS_jjbPiS_jjb
	.cfi_endproc
.LFE2078:
	.size	reduce6_i, .-reduce6_i
	.globl	_Z35__device_stub__Z10reduce6_uiPjS_jjbPjS_jjb
	.type	_Z35__device_stub__Z10reduce6_uiPjS_jjbPjS_jjb, @function
_Z35__device_stub__Z10reduce6_uiPjS_jjbPjS_jjb:
.LFB2079:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	48(%rsp), %rcx
	movb	%r8b, 4(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L59
	pushq	48(%rsp)
	.cfi_def_cfa_offset 152
	leaq	reduce6_ui(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 160
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L59:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L61
	call	__stack_chk_fail@PLT
.L61:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2079:
	.size	_Z35__device_stub__Z10reduce6_uiPjS_jjbPjS_jjb, .-_Z35__device_stub__Z10reduce6_uiPjS_jjbPjS_jjb
	.globl	reduce6_ui
	.type	reduce6_ui, @function
reduce6_ui:
.LFB2080:
	.cfi_startproc
	endbr64
	movzbl	%r8b, %r8d
	jmp	_Z35__device_stub__Z10reduce6_uiPjS_jjbPjS_jjb
	.cfi_endproc
.LFE2080:
	.size	reduce6_ui, .-reduce6_ui
	.globl	_Z33__device_stub__Z9reduce6_fPfS_jjbPfS_jjb
	.type	_Z33__device_stub__Z9reduce6_fPfS_jjbPfS_jjb, @function
_Z33__device_stub__Z9reduce6_fPfS_jjbPfS_jjb:
.LFB2081:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	48(%rsp), %rcx
	movb	%r8b, 4(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L64
	pushq	48(%rsp)
	.cfi_def_cfa_offset 152
	leaq	reduce6_f(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 160
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L64:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L66
	call	__stack_chk_fail@PLT
.L66:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2081:
	.size	_Z33__device_stub__Z9reduce6_fPfS_jjbPfS_jjb, .-_Z33__device_stub__Z9reduce6_fPfS_jjbPfS_jjb
	.globl	reduce6_f
	.type	reduce6_f, @function
reduce6_f:
.LFB2082:
	.cfi_startproc
	endbr64
	movzbl	%r8b, %r8d
	jmp	_Z33__device_stub__Z9reduce6_fPfS_jjbPfS_jjb
	.cfi_endproc
.LFE2082:
	.size	reduce6_f, .-reduce6_f
	.globl	_Z33__device_stub__Z9reduce6_dPdS_jjbPdS_jjb
	.type	_Z33__device_stub__Z9reduce6_dPdS_jjbPdS_jjb, @function
_Z33__device_stub__Z9reduce6_dPdS_jjbPdS_jjb:
.LFB2083:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	48(%rsp), %rcx
	movb	%r8b, 4(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L69
	pushq	48(%rsp)
	.cfi_def_cfa_offset 152
	leaq	reduce6_d(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 160
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L69:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L71
	call	__stack_chk_fail@PLT
.L71:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2083:
	.size	_Z33__device_stub__Z9reduce6_dPdS_jjbPdS_jjb, .-_Z33__device_stub__Z9reduce6_dPdS_jjbPdS_jjb
	.globl	reduce6_d
	.type	reduce6_d, @function
reduce6_d:
.LFB2084:
	.cfi_startproc
	endbr64
	movzbl	%r8b, %r8d
	jmp	_Z33__device_stub__Z9reduce6_dPdS_jjbPdS_jjb
	.cfi_endproc
.LFE2084:
	.size	reduce6_d, .-reduce6_d
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"reduce6_d"
.LC1:
	.string	"reduce6_f"
.LC2:
	.string	"reduce6_ui"
.LC3:
	.string	"reduce6_i"
.LC4:
	.string	"reduce6_s"
.LC5:
	.string	"reduce6_uc"
.LC6:
	.string	"reduce6_c"
.LC7:
	.string	"reduce5_d"
.LC8:
	.string	"reduce5_f"
.LC9:
	.string	"reduce5_ui"
.LC10:
	.string	"reduce5_i"
.LC11:
	.string	"reduce5_s"
.LC12:
	.string	"reduce5_uc"
.LC13:
	.string	"reduce5_c"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	reduce6_d(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC1(%rip), %rdx
	movq	%rbx, %rdi
	leaq	reduce6_f(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC2(%rip), %rdx
	movq	%rbx, %rdi
	leaq	reduce6_ui(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC3(%rip), %rdx
	movq	%rbx, %rdi
	leaq	reduce6_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC4(%rip), %rdx
	movq	%rbx, %rdi
	leaq	reduce6_s(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC5(%rip), %rdx
	movq	%rbx, %rdi
	leaq	reduce6_uc(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC6(%rip), %rdx
	movq	%rbx, %rdi
	leaq	reduce6_c(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC7(%rip), %rdx
	movq	%rbx, %rdi
	leaq	reduce5_d(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	leaq	.LC8(%rip), %rdx
	pushq	$0
	.cfi_def_cfa_offset 24
	movq	%rdx, %rcx
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	reduce5_f(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC9(%rip), %rdx
	orl	$-1, %r8d
	leaq	reduce5_ui(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC10(%rip), %rdx
	orl	$-1, %r8d
	leaq	reduce5_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC11(%rip), %rdx
	orl	$-1, %r8d
	leaq	reduce5_s(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC12(%rip), %rdx
	orl	$-1, %r8d
	leaq	reduce5_uc(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC13(%rip), %rdx
	orl	$-1, %r8d
	leaq	reduce5_c(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2086:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

/*=========================================================================
 *
 *  Copyright Insight Software Consortium
 *
 *  Licensed under the Apache License, Version 2.0 (the "License");
 *  you may not use this file except in compliance with the License.
 *  You may obtain a copy of the License at
 *
 *         http://www.apache.org/licenses/LICENSE-2.0.txt
 *
 *  Unless required by applicable law or agreed to in writing, software
 *  distributed under the License is distributed on an "AS IS" BASIS,
 *  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 *  See the License for the specific language governing permissions and
 *  limitations under the License.
 *
 *=========================================================================*/


#include <hip/hip_runtime.h>
#include <stdio.h>

/** This is for parallel reduction and is modified from NVIDIA's example code */

// Utility class used to avoid linker errors with extern
// unsized shared memory arrays with templated type
template<class T>
struct SharedMemory
{
    __device__ inline operator T *()
    {
        extern __shared__ int __smem[];
        return (T *)__smem;
    }

    __device__ inline operator const T *() const
    {
        extern __shared__ int __smem[];
        return (T *)__smem;
    }
};

// specialize for double to avoid unaligned memory
// access compile errors
template<>
struct SharedMemory<double>
{
    __device__ inline operator double *()
    {
        extern __shared__ double __smem_d[];
        return (double *)__smem_d;
    }

    __device__ inline operator const double *() const
    {
        extern __shared__ double __smem_d[];
        return (double *)__smem_d;
    }
};

// The following defines are set during runtime compilation, see reduction.cpp
// #define T float
// #define blockSize 128
// #define nIsPow2 1
/*
    This version is completely unrolled.  It uses a template parameter to achieve
    optimal code for any (power of 2) number of threads.  This requires a switch
    statement in the host code to handle all the different thread block sizes at
    compile time.

    Note, this kernel needs a minimum of 64*sizeof(T) bytes of shared memory.
    In other words if blockSize <= 32, allocate 64*sizeof(T) bytes.
    If blockSize > 32, allocate blockSize*sizeof(T) bytes.
*/
template <class T>
__device__ void reduce5(T *g_idata, T *g_odata, unsigned int n, unsigned int blockSize)
{
    T *sdata = SharedMemory<T>();

    // perform first level of reduction,
    // reading from global memory, writing to shared memory
    unsigned int tid = threadIdx.x;
    unsigned int i = blockIdx.x * (blockSize * 2) + threadIdx.x;

    T mySum = (i < n) ? g_idata[i] : 0;

    if (i + blockSize < n)
        mySum += g_idata[i+blockSize];

    sdata[tid] = mySum;
    __syncthreads();

    // do reduction in shared mem
    if (blockSize >= 512) { if (tid < 256) { sdata[tid] = mySum = mySum + sdata[tid + 256]; } __syncthreads(); }
    if (blockSize >= 256) { if (tid < 128) { sdata[tid] = mySum = mySum + sdata[tid + 128]; } __syncthreads(); }
    if (blockSize >= 128) { if (tid <  64) { sdata[tid] = mySum = mySum + sdata[tid +  64]; } __syncthreads(); }

    if (tid < 32)
    {
        // now that we are using warp-synchronous programming (below)
        // we need to declare our shared memory volatile so that the compiler
        // doesn't reorder stores to it and induce incorrect behavior.
        volatile T *smem = sdata;
        if (blockSize >=  64) { smem[tid] = mySum = mySum + smem[tid + 32]; }
        if (blockSize >=  32) { smem[tid] = mySum = mySum + smem[tid + 16]; }
        if (blockSize >=  16) { smem[tid] = mySum = mySum + smem[tid +  8]; }
        if (blockSize >=   8) { smem[tid] = mySum = mySum + smem[tid +  4]; }
        if (blockSize >=   4) { smem[tid] = mySum = mySum + smem[tid +  2]; }
        if (blockSize >=   2) { smem[tid] = mySum = mySum + smem[tid +  1]; }
    }

    // write result for this block to global mem
    if (tid == 0) g_odata[blockIdx.x] = sdata[0];
}

/*
    This version adds multiple elements per thread sequentially.  This reduces the overall
    cost of the algorithm while keeping the work complexity O(n) and the step complexity O(log n).
    (Brent's Theorem optimization)

    Note, this kernel needs a minimum of 64*sizeof(T) bytes of shared memory.
    In other words if blockSize <= 32, allocate 64*sizeof(T) bytes.
    If blockSize > 32, allocate blockSize*sizeof(T) bytes.
*/
template <class T>
__device__ void reduce6(T *g_idata, T *g_odata, unsigned int n, unsigned int blockSize, bool nIsPow2)
{
    T *sdata = SharedMemory<T>();

    // perform first level of reduction,
    // reading from global memory, writing to shared memory
    unsigned int tid = threadIdx.x;
    unsigned int i = blockIdx.x * (blockSize * 2) + threadIdx.x;
    unsigned int gridSize = blockSize*2*gridDim.x;

    T mySum = 0;

    // we reduce multiple elements per thread.  The number is determined by the
    // number of active thread blocks (via gridDim).  More blocks will result
    // in a larger gridSize and therefore fewer elements per thread
    while (i < n)
    {
        mySum += g_idata[i];

        // ensure we don't read out of bounds -- this is optimized away for powerOf2 sized arrays
        if (nIsPow2 || i + blockSize < n)
            mySum += g_idata[i+blockSize];

        i += gridSize;
    }

    // each thread puts its local sum into shared memory
    sdata[tid] = mySum;
    __syncthreads();

    // do reduction in shared mem
    if (blockSize >= 512) { if (tid < 256) { sdata[tid] = mySum = mySum + sdata[tid + 256]; } __syncthreads(); }
    if (blockSize >= 256) { if (tid < 128) { sdata[tid] = mySum = mySum + sdata[tid + 128]; } __syncthreads(); }
    if (blockSize >= 128) { if (tid <  64) { sdata[tid] = mySum = mySum + sdata[tid +  64]; } __syncthreads(); }

    if (tid < 32)
    {
        // now that we are using warp-synchronous programming (below)
        // we need to declare our shared memory volatile so that the compiler
        // doesn't reorder stores to it and induce incorrect behavior.
        volatile T *smem = sdata;

        if (blockSize >=  64) { smem[tid] = mySum = mySum + smem[tid + 32]; }
        if (blockSize >=  32) { smem[tid] = mySum = mySum + smem[tid + 16]; }
        if (blockSize >=  16) { smem[tid] = mySum = mySum + smem[tid +  8]; }
        if (blockSize >=   8) { smem[tid] = mySum = mySum + smem[tid +  4]; }
        if (blockSize >=   4) { smem[tid] = mySum = mySum + smem[tid +  2]; }
        if (blockSize >=   2) { smem[tid] = mySum = mySum + smem[tid +  1]; }
    }
    
    // write result for this block to global mem
    if (tid == 0)        
        g_odata[blockIdx.x] = sdata[0];
}

#define MAKE_reduce5_TEMPLATE_IMPL(_exportname_, T) \
  extern "C" __global__ void _exportname_(T* g_idata, T *g_odata, unsigned int n, unsigned int blockSize)\
  {\
    reduce5<T>(g_idata, g_odata, n, blockSize);\
  }

#define MAKE_reduce6_TEMPLATE_IMPL(_exportname_, T) \
  extern "C" __global__ void _exportname_(T* g_idata, T *g_odata, unsigned int n, unsigned int blockSize, bool nIsPow2)\
  {\
    reduce6<T>(g_idata, g_odata, n, blockSize, nIsPow2);\
  }

#define MAKE_IMPL(_func_)\
  MAKE_##_func_##_TEMPLATE_IMPL(_func_##_c, char);\
  MAKE_##_func_##_TEMPLATE_IMPL(_func_##_uc, unsigned char);\
  MAKE_##_func_##_TEMPLATE_IMPL(_func_##_s, short);\
  MAKE_##_func_##_TEMPLATE_IMPL(_func_##_i, int);\
  MAKE_##_func_##_TEMPLATE_IMPL(_func_##_ui, unsigned int);\
  MAKE_##_func_##_TEMPLATE_IMPL(_func_##_f, float);\
  MAKE_##_func_##_TEMPLATE_IMPL(_func_##_d, double);

// Export the template implementations
MAKE_IMPL(reduce5);
MAKE_IMPL(reduce6);

	.text
	.file	"CudaReduction.hip"
	.globl	__device_stub__reduce5_c        # -- Begin function __device_stub__reduce5_c
	.type	__device_stub__reduce5_c,@function
__device_stub__reduce5_c:               # @__device_stub__reduce5_c
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$reduce5_c, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	__device_stub__reduce5_c, .Lfunc_end0-__device_stub__reduce5_c
	.cfi_endproc
                                        # -- End function
	.globl	__device_stub__reduce5_uc       # -- Begin function __device_stub__reduce5_uc
	.type	__device_stub__reduce5_uc,@function
__device_stub__reduce5_uc:              # @__device_stub__reduce5_uc
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$reduce5_uc, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	__device_stub__reduce5_uc, .Lfunc_end1-__device_stub__reduce5_uc
	.cfi_endproc
                                        # -- End function
	.globl	__device_stub__reduce5_s        # -- Begin function __device_stub__reduce5_s
	.type	__device_stub__reduce5_s,@function
__device_stub__reduce5_s:               # @__device_stub__reduce5_s
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$reduce5_s, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	__device_stub__reduce5_s, .Lfunc_end2-__device_stub__reduce5_s
	.cfi_endproc
                                        # -- End function
	.globl	__device_stub__reduce5_i        # -- Begin function __device_stub__reduce5_i
	.type	__device_stub__reduce5_i,@function
__device_stub__reduce5_i:               # @__device_stub__reduce5_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$reduce5_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	__device_stub__reduce5_i, .Lfunc_end3-__device_stub__reduce5_i
	.cfi_endproc
                                        # -- End function
	.globl	__device_stub__reduce5_ui       # -- Begin function __device_stub__reduce5_ui
	.type	__device_stub__reduce5_ui,@function
__device_stub__reduce5_ui:              # @__device_stub__reduce5_ui
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$reduce5_ui, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end4:
	.size	__device_stub__reduce5_ui, .Lfunc_end4-__device_stub__reduce5_ui
	.cfi_endproc
                                        # -- End function
	.globl	__device_stub__reduce5_f        # -- Begin function __device_stub__reduce5_f
	.type	__device_stub__reduce5_f,@function
__device_stub__reduce5_f:               # @__device_stub__reduce5_f
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$reduce5_f, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end5:
	.size	__device_stub__reduce5_f, .Lfunc_end5-__device_stub__reduce5_f
	.cfi_endproc
                                        # -- End function
	.globl	__device_stub__reduce5_d        # -- Begin function __device_stub__reduce5_d
	.type	__device_stub__reduce5_d,@function
__device_stub__reduce5_d:               # @__device_stub__reduce5_d
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$reduce5_d, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end6:
	.size	__device_stub__reduce5_d, .Lfunc_end6-__device_stub__reduce5_d
	.cfi_endproc
                                        # -- End function
	.globl	__device_stub__reduce6_c        # -- Begin function __device_stub__reduce6_c
	.type	__device_stub__reduce6_c,@function
__device_stub__reduce6_c:               # @__device_stub__reduce6_c
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	7(%rsp), %rcx
	movb	%r8b, (%rcx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$reduce6_c, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end7:
	.size	__device_stub__reduce6_c, .Lfunc_end7-__device_stub__reduce6_c
	.cfi_endproc
                                        # -- End function
	.globl	__device_stub__reduce6_uc       # -- Begin function __device_stub__reduce6_uc
	.type	__device_stub__reduce6_uc,@function
__device_stub__reduce6_uc:              # @__device_stub__reduce6_uc
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	7(%rsp), %rcx
	movb	%r8b, (%rcx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$reduce6_uc, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end8:
	.size	__device_stub__reduce6_uc, .Lfunc_end8-__device_stub__reduce6_uc
	.cfi_endproc
                                        # -- End function
	.globl	__device_stub__reduce6_s        # -- Begin function __device_stub__reduce6_s
	.type	__device_stub__reduce6_s,@function
__device_stub__reduce6_s:               # @__device_stub__reduce6_s
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	7(%rsp), %rcx
	movb	%r8b, (%rcx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$reduce6_s, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end9:
	.size	__device_stub__reduce6_s, .Lfunc_end9-__device_stub__reduce6_s
	.cfi_endproc
                                        # -- End function
	.globl	__device_stub__reduce6_i        # -- Begin function __device_stub__reduce6_i
	.type	__device_stub__reduce6_i,@function
__device_stub__reduce6_i:               # @__device_stub__reduce6_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	7(%rsp), %rcx
	movb	%r8b, (%rcx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$reduce6_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end10:
	.size	__device_stub__reduce6_i, .Lfunc_end10-__device_stub__reduce6_i
	.cfi_endproc
                                        # -- End function
	.globl	__device_stub__reduce6_ui       # -- Begin function __device_stub__reduce6_ui
	.type	__device_stub__reduce6_ui,@function
__device_stub__reduce6_ui:              # @__device_stub__reduce6_ui
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	7(%rsp), %rcx
	movb	%r8b, (%rcx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$reduce6_ui, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end11:
	.size	__device_stub__reduce6_ui, .Lfunc_end11-__device_stub__reduce6_ui
	.cfi_endproc
                                        # -- End function
	.globl	__device_stub__reduce6_f        # -- Begin function __device_stub__reduce6_f
	.type	__device_stub__reduce6_f,@function
__device_stub__reduce6_f:               # @__device_stub__reduce6_f
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	7(%rsp), %rcx
	movb	%r8b, (%rcx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$reduce6_f, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end12:
	.size	__device_stub__reduce6_f, .Lfunc_end12-__device_stub__reduce6_f
	.cfi_endproc
                                        # -- End function
	.globl	__device_stub__reduce6_d        # -- Begin function __device_stub__reduce6_d
	.type	__device_stub__reduce6_d,@function
__device_stub__reduce6_d:               # @__device_stub__reduce6_d
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	7(%rsp), %rcx
	movb	%r8b, (%rcx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$reduce6_d, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end13:
	.size	__device_stub__reduce6_d, .Lfunc_end13-__device_stub__reduce6_d
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB14_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB14_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$reduce5_c, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$reduce5_uc, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$reduce5_s, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$reduce5_i, %esi
	movl	$.L__unnamed_4, %edx
	movl	$.L__unnamed_4, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$reduce5_ui, %esi
	movl	$.L__unnamed_5, %edx
	movl	$.L__unnamed_5, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$reduce5_f, %esi
	movl	$.L__unnamed_6, %edx
	movl	$.L__unnamed_6, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$reduce5_d, %esi
	movl	$.L__unnamed_7, %edx
	movl	$.L__unnamed_7, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$reduce6_c, %esi
	movl	$.L__unnamed_8, %edx
	movl	$.L__unnamed_8, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$reduce6_uc, %esi
	movl	$.L__unnamed_9, %edx
	movl	$.L__unnamed_9, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$reduce6_s, %esi
	movl	$.L__unnamed_10, %edx
	movl	$.L__unnamed_10, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$reduce6_i, %esi
	movl	$.L__unnamed_11, %edx
	movl	$.L__unnamed_11, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$reduce6_ui, %esi
	movl	$.L__unnamed_12, %edx
	movl	$.L__unnamed_12, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$reduce6_f, %esi
	movl	$.L__unnamed_13, %edx
	movl	$.L__unnamed_13, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$reduce6_d, %esi
	movl	$.L__unnamed_14, %edx
	movl	$.L__unnamed_14, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end14:
	.size	__hip_module_ctor, .Lfunc_end14-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB15_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB15_2:
	retq
.Lfunc_end15:
	.size	__hip_module_dtor, .Lfunc_end15-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	reduce5_c,@object               # @reduce5_c
	.section	.rodata,"a",@progbits
	.globl	reduce5_c
	.p2align	3, 0x0
reduce5_c:
	.quad	__device_stub__reduce5_c
	.size	reduce5_c, 8

	.type	reduce5_uc,@object              # @reduce5_uc
	.globl	reduce5_uc
	.p2align	3, 0x0
reduce5_uc:
	.quad	__device_stub__reduce5_uc
	.size	reduce5_uc, 8

	.type	reduce5_s,@object               # @reduce5_s
	.globl	reduce5_s
	.p2align	3, 0x0
reduce5_s:
	.quad	__device_stub__reduce5_s
	.size	reduce5_s, 8

	.type	reduce5_i,@object               # @reduce5_i
	.globl	reduce5_i
	.p2align	3, 0x0
reduce5_i:
	.quad	__device_stub__reduce5_i
	.size	reduce5_i, 8

	.type	reduce5_ui,@object              # @reduce5_ui
	.globl	reduce5_ui
	.p2align	3, 0x0
reduce5_ui:
	.quad	__device_stub__reduce5_ui
	.size	reduce5_ui, 8

	.type	reduce5_f,@object               # @reduce5_f
	.globl	reduce5_f
	.p2align	3, 0x0
reduce5_f:
	.quad	__device_stub__reduce5_f
	.size	reduce5_f, 8

	.type	reduce5_d,@object               # @reduce5_d
	.globl	reduce5_d
	.p2align	3, 0x0
reduce5_d:
	.quad	__device_stub__reduce5_d
	.size	reduce5_d, 8

	.type	reduce6_c,@object               # @reduce6_c
	.globl	reduce6_c
	.p2align	3, 0x0
reduce6_c:
	.quad	__device_stub__reduce6_c
	.size	reduce6_c, 8

	.type	reduce6_uc,@object              # @reduce6_uc
	.globl	reduce6_uc
	.p2align	3, 0x0
reduce6_uc:
	.quad	__device_stub__reduce6_uc
	.size	reduce6_uc, 8

	.type	reduce6_s,@object               # @reduce6_s
	.globl	reduce6_s
	.p2align	3, 0x0
reduce6_s:
	.quad	__device_stub__reduce6_s
	.size	reduce6_s, 8

	.type	reduce6_i,@object               # @reduce6_i
	.globl	reduce6_i
	.p2align	3, 0x0
reduce6_i:
	.quad	__device_stub__reduce6_i
	.size	reduce6_i, 8

	.type	reduce6_ui,@object              # @reduce6_ui
	.globl	reduce6_ui
	.p2align	3, 0x0
reduce6_ui:
	.quad	__device_stub__reduce6_ui
	.size	reduce6_ui, 8

	.type	reduce6_f,@object               # @reduce6_f
	.globl	reduce6_f
	.p2align	3, 0x0
reduce6_f:
	.quad	__device_stub__reduce6_f
	.size	reduce6_f, 8

	.type	reduce6_d,@object               # @reduce6_d
	.globl	reduce6_d
	.p2align	3, 0x0
reduce6_d:
	.quad	__device_stub__reduce6_d
	.size	reduce6_d, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"reduce5_c"
	.size	.L__unnamed_1, 10

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"reduce5_uc"
	.size	.L__unnamed_2, 11

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"reduce5_s"
	.size	.L__unnamed_3, 10

	.type	.L__unnamed_4,@object           # @3
.L__unnamed_4:
	.asciz	"reduce5_i"
	.size	.L__unnamed_4, 10

	.type	.L__unnamed_5,@object           # @4
.L__unnamed_5:
	.asciz	"reduce5_ui"
	.size	.L__unnamed_5, 11

	.type	.L__unnamed_6,@object           # @5
.L__unnamed_6:
	.asciz	"reduce5_f"
	.size	.L__unnamed_6, 10

	.type	.L__unnamed_7,@object           # @6
.L__unnamed_7:
	.asciz	"reduce5_d"
	.size	.L__unnamed_7, 10

	.type	.L__unnamed_8,@object           # @7
.L__unnamed_8:
	.asciz	"reduce6_c"
	.size	.L__unnamed_8, 10

	.type	.L__unnamed_9,@object           # @8
.L__unnamed_9:
	.asciz	"reduce6_uc"
	.size	.L__unnamed_9, 11

	.type	.L__unnamed_10,@object          # @9
.L__unnamed_10:
	.asciz	"reduce6_s"
	.size	.L__unnamed_10, 10

	.type	.L__unnamed_11,@object          # @10
.L__unnamed_11:
	.asciz	"reduce6_i"
	.size	.L__unnamed_11, 10

	.type	.L__unnamed_12,@object          # @11
.L__unnamed_12:
	.asciz	"reduce6_ui"
	.size	.L__unnamed_12, 11

	.type	.L__unnamed_13,@object          # @12
.L__unnamed_13:
	.asciz	"reduce6_f"
	.size	.L__unnamed_13, 10

	.type	.L__unnamed_14,@object          # @13
.L__unnamed_14:
	.asciz	"reduce6_d"
	.size	.L__unnamed_14, 10

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __device_stub__reduce5_c
	.addrsig_sym __device_stub__reduce5_uc
	.addrsig_sym __device_stub__reduce5_s
	.addrsig_sym __device_stub__reduce5_i
	.addrsig_sym __device_stub__reduce5_ui
	.addrsig_sym __device_stub__reduce5_f
	.addrsig_sym __device_stub__reduce5_d
	.addrsig_sym __device_stub__reduce6_c
	.addrsig_sym __device_stub__reduce6_uc
	.addrsig_sym __device_stub__reduce6_s
	.addrsig_sym __device_stub__reduce6_i
	.addrsig_sym __device_stub__reduce6_ui
	.addrsig_sym __device_stub__reduce6_f
	.addrsig_sym __device_stub__reduce6_d
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym reduce5_c
	.addrsig_sym reduce5_uc
	.addrsig_sym reduce5_s
	.addrsig_sym reduce5_i
	.addrsig_sym reduce5_ui
	.addrsig_sym reduce5_f
	.addrsig_sym reduce5_d
	.addrsig_sym reduce6_c
	.addrsig_sym reduce6_uc
	.addrsig_sym reduce6_s
	.addrsig_sym reduce6_i
	.addrsig_sym reduce6_ui
	.addrsig_sym reduce6_f
	.addrsig_sym reduce6_d
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	reduce5_c               ; -- Begin function reduce5_c
	.globl	reduce5_c
	.p2align	8
	.type	reduce5_c,@function
reduce5_c:                              ; @reduce5_c
; %bb.0:
	s_clause 0x1
	s_load_b64 s[4:5], s[0:1], 0x10
	s_load_b128 s[0:3], s[0:1], 0x0
	v_mov_b32_e32 v3, 0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s6, s15, s5
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshl_add_u32 v1, s6, 1, v0
	s_mov_b32 s6, exec_lo
	v_cmpx_gt_u32_e64 s4, v1
	s_cbranch_execz .LBB0_2
; %bb.1:
	global_load_u8 v3, v1, s[0:1]
.LBB0_2:
	s_or_b32 exec_lo, exec_lo, s6
	v_add_nc_u32_e32 v1, s5, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u32_e32 vcc_lo, s4, v1
	s_and_saveexec_b32 s4, vcc_lo
	s_cbranch_execz .LBB0_4
; %bb.3:
	global_load_u8 v1, v1, s[0:1]
	s_waitcnt vmcnt(0)
	v_add_nc_u16 v3, v1, v3
.LBB0_4:
	s_or_b32 exec_lo, exec_lo, s4
	v_add_nc_u32_e32 v4, 0, v0
	s_cmpk_lt_u32 s5, 0x200
	s_waitcnt vmcnt(0)
	ds_store_b8 v4, v3
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB0_8
; %bb.5:
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 0x100, v0
	s_cbranch_execz .LBB0_7
; %bb.6:
	ds_load_u8 v1, v4 offset:256
	s_waitcnt lgkmcnt(0)
	v_add_nc_u16 v3, v1, v3
	ds_store_b8 v4, v3
.LBB0_7:
	s_or_b32 exec_lo, exec_lo, s0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
.LBB0_8:
	s_cmpk_lt_u32 s5, 0x100
	s_cbranch_scc1 .LBB0_12
; %bb.9:
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 0x80, v0
	s_cbranch_execz .LBB0_11
; %bb.10:
	ds_load_u8 v1, v4 offset:128
	s_waitcnt lgkmcnt(0)
	v_add_nc_u16 v3, v1, v3
	ds_store_b8 v4, v3
.LBB0_11:
	s_or_b32 exec_lo, exec_lo, s0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
.LBB0_12:
	s_cmpk_lt_u32 s5, 0x80
	s_cbranch_scc1 .LBB0_16
; %bb.13:
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 64, v0
	s_cbranch_execz .LBB0_15
; %bb.14:
	ds_load_u8 v1, v4 offset:64
	s_waitcnt lgkmcnt(0)
	v_add_nc_u16 v3, v1, v3
	ds_store_b8 v4, v3
.LBB0_15:
	s_or_b32 exec_lo, exec_lo, s0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
.LBB0_16:
	s_mov_b32 s4, exec_lo
	v_cmpx_gt_u32_e32 32, v0
	s_cbranch_execz .LBB0_29
; %bb.17:
	v_cmp_ne_u32_e32 vcc_lo, -1, v4
	s_mov_b64 s[0:1], src_shared_base
	s_cmp_lt_u32 s5, 64
	v_cndmask_b32_e64 v2, 0, s1, vcc_lo
	v_cndmask_b32_e32 v1, 0, v4, vcc_lo
	s_cbranch_scc1 .LBB0_19
; %bb.18:
	v_add3_u32 v5, 0, v0, 32
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v5
	v_cndmask_b32_e32 v5, 0, v5, vcc_lo
	v_cndmask_b32_e64 v6, 0, s1, vcc_lo
	flat_load_u8 v5, v[5:6] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_nc_u16 v3, v5, v3
	flat_store_b8 v[1:2], v3 dlc
	s_waitcnt_vscnt null, 0x0
.LBB0_19:
	s_cmp_lt_u32 s5, 32
	s_cbranch_scc1 .LBB0_21
; %bb.20:
	v_add_nc_u32_e32 v5, 16, v4
	s_mov_b64 s[0:1], src_shared_base
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v5
	v_cndmask_b32_e32 v5, 0, v5, vcc_lo
	v_cndmask_b32_e64 v6, 0, s1, vcc_lo
	flat_load_u8 v5, v[5:6] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_nc_u16 v3, v5, v3
	flat_store_b8 v[1:2], v3 dlc
	s_waitcnt_vscnt null, 0x0
.LBB0_21:
	s_cmp_lt_u32 s5, 16
	s_cbranch_scc1 .LBB0_23
; %bb.22:
	v_add_nc_u32_e32 v5, 8, v4
	s_mov_b64 s[0:1], src_shared_base
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v5
	v_cndmask_b32_e32 v5, 0, v5, vcc_lo
	v_cndmask_b32_e64 v6, 0, s1, vcc_lo
	flat_load_u8 v5, v[5:6] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_nc_u16 v3, v5, v3
	flat_store_b8 v[1:2], v3 dlc
	s_waitcnt_vscnt null, 0x0
.LBB0_23:
	s_cmp_lt_u32 s5, 8
	s_cbranch_scc1 .LBB0_25
; %bb.24:
	v_add_nc_u32_e32 v5, 4, v4
	s_mov_b64 s[0:1], src_shared_base
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v5
	v_cndmask_b32_e32 v5, 0, v5, vcc_lo
	v_cndmask_b32_e64 v6, 0, s1, vcc_lo
	flat_load_u8 v5, v[5:6] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_nc_u16 v3, v5, v3
	flat_store_b8 v[1:2], v3 dlc
	s_waitcnt_vscnt null, 0x0
.LBB0_25:
	s_cmp_lt_u32 s5, 4
	s_cbranch_scc1 .LBB0_27
; %bb.26:
	v_add_nc_u32_e32 v5, 2, v4
	s_mov_b64 s[0:1], src_shared_base
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v5
	v_cndmask_b32_e32 v5, 0, v5, vcc_lo
	v_cndmask_b32_e64 v6, 0, s1, vcc_lo
	flat_load_u8 v5, v[5:6] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_nc_u16 v3, v5, v3
	flat_store_b8 v[1:2], v3 dlc
	s_waitcnt_vscnt null, 0x0
.LBB0_27:
	s_cmp_lt_u32 s5, 2
	s_cbranch_scc1 .LBB0_29
; %bb.28:
	v_add_nc_u32_e32 v4, 1, v4
	s_mov_b64 s[0:1], src_shared_base
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v4
	v_cndmask_b32_e32 v4, 0, v4, vcc_lo
	v_cndmask_b32_e64 v5, 0, s1, vcc_lo
	flat_load_u8 v4, v[4:5] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_nc_u16 v3, v4, v3
	flat_store_b8 v[1:2], v3 dlc
	s_waitcnt_vscnt null, 0x0
.LBB0_29:                               ; %Flow18
	s_or_b32 exec_lo, exec_lo, s4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB0_31
; %bb.30:
	v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s15
	ds_load_u8 v0, v0
	s_waitcnt lgkmcnt(0)
	global_store_b8 v1, v0, s[2:3]
.LBB0_31:                               ; %_Z7reduce5IcEvPT_S1_jj.exit
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel reduce5_c
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 24
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 7
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	reduce5_c, .Lfunc_end0-reduce5_c
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 852
; NumSgprs: 18
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	reduce5_uc              ; -- Begin function reduce5_uc
	.globl	reduce5_uc
	.p2align	8
	.type	reduce5_uc,@function
reduce5_uc:                             ; @reduce5_uc
; %bb.0:
	s_clause 0x1
	s_load_b64 s[4:5], s[0:1], 0x10
	s_load_b128 s[0:3], s[0:1], 0x0
	v_mov_b32_e32 v3, 0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s6, s15, s5
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshl_add_u32 v1, s6, 1, v0
	s_mov_b32 s6, exec_lo
	v_cmpx_gt_u32_e64 s4, v1
	s_cbranch_execz .LBB1_2
; %bb.1:
	global_load_u8 v3, v1, s[0:1]
.LBB1_2:
	s_or_b32 exec_lo, exec_lo, s6
	v_add_nc_u32_e32 v1, s5, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u32_e32 vcc_lo, s4, v1
	s_and_saveexec_b32 s4, vcc_lo
	s_cbranch_execz .LBB1_4
; %bb.3:
	global_load_u8 v1, v1, s[0:1]
	s_waitcnt vmcnt(0)
	v_add_nc_u16 v3, v1, v3
.LBB1_4:
	s_or_b32 exec_lo, exec_lo, s4
	v_add_nc_u32_e32 v4, 0, v0
	s_cmpk_lt_u32 s5, 0x200
	s_waitcnt vmcnt(0)
	ds_store_b8 v4, v3
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB1_8
; %bb.5:
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 0x100, v0
	s_cbranch_execz .LBB1_7
; %bb.6:
	ds_load_u8 v1, v4 offset:256
	s_waitcnt lgkmcnt(0)
	v_add_nc_u16 v3, v1, v3
	ds_store_b8 v4, v3
.LBB1_7:
	s_or_b32 exec_lo, exec_lo, s0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
.LBB1_8:
	s_cmpk_lt_u32 s5, 0x100
	s_cbranch_scc1 .LBB1_12
; %bb.9:
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 0x80, v0
	s_cbranch_execz .LBB1_11
; %bb.10:
	ds_load_u8 v1, v4 offset:128
	s_waitcnt lgkmcnt(0)
	v_add_nc_u16 v3, v1, v3
	ds_store_b8 v4, v3
.LBB1_11:
	s_or_b32 exec_lo, exec_lo, s0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
.LBB1_12:
	s_cmpk_lt_u32 s5, 0x80
	s_cbranch_scc1 .LBB1_16
; %bb.13:
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 64, v0
	s_cbranch_execz .LBB1_15
; %bb.14:
	ds_load_u8 v1, v4 offset:64
	s_waitcnt lgkmcnt(0)
	v_add_nc_u16 v3, v1, v3
	ds_store_b8 v4, v3
.LBB1_15:
	s_or_b32 exec_lo, exec_lo, s0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
.LBB1_16:
	s_mov_b32 s4, exec_lo
	v_cmpx_gt_u32_e32 32, v0
	s_cbranch_execz .LBB1_29
; %bb.17:
	v_cmp_ne_u32_e32 vcc_lo, -1, v4
	s_mov_b64 s[0:1], src_shared_base
	s_cmp_lt_u32 s5, 64
	v_cndmask_b32_e64 v2, 0, s1, vcc_lo
	v_cndmask_b32_e32 v1, 0, v4, vcc_lo
	s_cbranch_scc1 .LBB1_19
; %bb.18:
	v_add3_u32 v5, 0, v0, 32
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v5
	v_cndmask_b32_e32 v5, 0, v5, vcc_lo
	v_cndmask_b32_e64 v6, 0, s1, vcc_lo
	flat_load_u8 v5, v[5:6] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_nc_u16 v3, v5, v3
	flat_store_b8 v[1:2], v3 dlc
	s_waitcnt_vscnt null, 0x0
.LBB1_19:
	s_cmp_lt_u32 s5, 32
	s_cbranch_scc1 .LBB1_21
; %bb.20:
	v_add_nc_u32_e32 v5, 16, v4
	s_mov_b64 s[0:1], src_shared_base
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v5
	v_cndmask_b32_e32 v5, 0, v5, vcc_lo
	v_cndmask_b32_e64 v6, 0, s1, vcc_lo
	flat_load_u8 v5, v[5:6] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_nc_u16 v3, v5, v3
	flat_store_b8 v[1:2], v3 dlc
	s_waitcnt_vscnt null, 0x0
.LBB1_21:
	s_cmp_lt_u32 s5, 16
	s_cbranch_scc1 .LBB1_23
; %bb.22:
	v_add_nc_u32_e32 v5, 8, v4
	s_mov_b64 s[0:1], src_shared_base
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v5
	v_cndmask_b32_e32 v5, 0, v5, vcc_lo
	v_cndmask_b32_e64 v6, 0, s1, vcc_lo
	flat_load_u8 v5, v[5:6] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_nc_u16 v3, v5, v3
	flat_store_b8 v[1:2], v3 dlc
	s_waitcnt_vscnt null, 0x0
.LBB1_23:
	s_cmp_lt_u32 s5, 8
	s_cbranch_scc1 .LBB1_25
; %bb.24:
	v_add_nc_u32_e32 v5, 4, v4
	s_mov_b64 s[0:1], src_shared_base
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v5
	v_cndmask_b32_e32 v5, 0, v5, vcc_lo
	v_cndmask_b32_e64 v6, 0, s1, vcc_lo
	flat_load_u8 v5, v[5:6] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_nc_u16 v3, v5, v3
	flat_store_b8 v[1:2], v3 dlc
	s_waitcnt_vscnt null, 0x0
.LBB1_25:
	s_cmp_lt_u32 s5, 4
	s_cbranch_scc1 .LBB1_27
; %bb.26:
	v_add_nc_u32_e32 v5, 2, v4
	s_mov_b64 s[0:1], src_shared_base
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v5
	v_cndmask_b32_e32 v5, 0, v5, vcc_lo
	v_cndmask_b32_e64 v6, 0, s1, vcc_lo
	flat_load_u8 v5, v[5:6] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_nc_u16 v3, v5, v3
	flat_store_b8 v[1:2], v3 dlc
	s_waitcnt_vscnt null, 0x0
.LBB1_27:
	s_cmp_lt_u32 s5, 2
	s_cbranch_scc1 .LBB1_29
; %bb.28:
	v_add_nc_u32_e32 v4, 1, v4
	s_mov_b64 s[0:1], src_shared_base
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v4
	v_cndmask_b32_e32 v4, 0, v4, vcc_lo
	v_cndmask_b32_e64 v5, 0, s1, vcc_lo
	flat_load_u8 v4, v[4:5] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_nc_u16 v3, v4, v3
	flat_store_b8 v[1:2], v3 dlc
	s_waitcnt_vscnt null, 0x0
.LBB1_29:                               ; %Flow18
	s_or_b32 exec_lo, exec_lo, s4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB1_31
; %bb.30:
	v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s15
	ds_load_u8 v0, v0
	s_waitcnt lgkmcnt(0)
	global_store_b8 v1, v0, s[2:3]
.LBB1_31:                               ; %_Z7reduce5IhEvPT_S1_jj.exit
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel reduce5_uc
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 24
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 7
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	reduce5_uc, .Lfunc_end1-reduce5_uc
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 852
; NumSgprs: 18
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	reduce5_s               ; -- Begin function reduce5_s
	.globl	reduce5_s
	.p2align	8
	.type	reduce5_s,@function
reduce5_s:                              ; @reduce5_s
; %bb.0:
	s_clause 0x1
	s_load_b64 s[6:7], s[0:1], 0x10
	s_load_b128 s[0:3], s[0:1], 0x0
	v_mov_b32_e32 v3, 0
	s_mov_b32 s4, s15
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s5, s15, s7
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshl_add_u32 v1, s5, 1, v0
	s_mov_b32 s5, exec_lo
	v_cmpx_gt_u32_e64 s6, v1
	s_cbranch_execz .LBB2_2
; %bb.1:
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 1, v[1:2]
	v_add_co_u32 v2, vcc_lo, s0, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
	global_load_u16 v3, v[2:3], off
.LBB2_2:
	s_or_b32 exec_lo, exec_lo, s5
	v_add_nc_u32_e32 v1, s7, v1
	s_mov_b32 s5, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e64 s6, v1
	s_cbranch_execz .LBB2_4
; %bb.3:
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 1, v[1:2]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_u16 v1, v[1:2], off
	s_waitcnt vmcnt(0)
	v_add_nc_u16 v3, v1, v3
.LBB2_4:
	s_or_b32 exec_lo, exec_lo, s5
	v_lshl_add_u32 v4, v0, 1, 0
	s_cmpk_lt_u32 s7, 0x200
	s_waitcnt vmcnt(0)
	ds_store_b16 v4, v3
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB2_8
; %bb.5:
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 0x100, v0
	s_cbranch_execz .LBB2_7
; %bb.6:
	ds_load_u16 v1, v4 offset:512
	s_waitcnt lgkmcnt(0)
	v_add_nc_u16 v3, v1, v3
	ds_store_b16 v4, v3
.LBB2_7:
	s_or_b32 exec_lo, exec_lo, s0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
.LBB2_8:
	s_cmpk_lt_u32 s7, 0x100
	s_cbranch_scc1 .LBB2_12
; %bb.9:
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 0x80, v0
	s_cbranch_execz .LBB2_11
; %bb.10:
	ds_load_u16 v1, v4 offset:256
	s_waitcnt lgkmcnt(0)
	v_add_nc_u16 v3, v1, v3
	ds_store_b16 v4, v3
.LBB2_11:
	s_or_b32 exec_lo, exec_lo, s0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
.LBB2_12:
	s_cmpk_lt_u32 s7, 0x80
	s_cbranch_scc1 .LBB2_16
; %bb.13:
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 64, v0
	s_cbranch_execz .LBB2_15
; %bb.14:
	ds_load_u16 v1, v4 offset:128
	s_waitcnt lgkmcnt(0)
	v_add_nc_u16 v3, v1, v3
	ds_store_b16 v4, v3
.LBB2_15:
	s_or_b32 exec_lo, exec_lo, s0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
.LBB2_16:
	s_mov_b32 s5, exec_lo
	v_cmpx_gt_u32_e32 32, v0
	s_cbranch_execz .LBB2_29
; %bb.17:
	v_cmp_ne_u32_e32 vcc_lo, -1, v4
	s_mov_b64 s[0:1], src_shared_base
	s_cmp_lt_u32 s7, 64
	v_cndmask_b32_e64 v2, 0, s1, vcc_lo
	v_cndmask_b32_e32 v1, 0, v4, vcc_lo
	s_cbranch_scc1 .LBB2_19
; %bb.18:
	v_lshlrev_b32_e32 v5, 1, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v5, 0, v5, 64
	v_cmp_ne_u32_e32 vcc_lo, -1, v5
	v_cndmask_b32_e32 v5, 0, v5, vcc_lo
	v_cndmask_b32_e64 v6, 0, s1, vcc_lo
	flat_load_u16 v5, v[5:6] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_nc_u16 v3, v5, v3
	flat_store_b16 v[1:2], v3 dlc
	s_waitcnt_vscnt null, 0x0
.LBB2_19:
	s_cmp_lt_u32 s7, 32
	s_cbranch_scc1 .LBB2_21
; %bb.20:
	v_add_nc_u32_e32 v5, 32, v4
	s_mov_b64 s[0:1], src_shared_base
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v5
	v_cndmask_b32_e32 v5, 0, v5, vcc_lo
	v_cndmask_b32_e64 v6, 0, s1, vcc_lo
	flat_load_u16 v5, v[5:6] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_nc_u16 v3, v5, v3
	flat_store_b16 v[1:2], v3 dlc
	s_waitcnt_vscnt null, 0x0
.LBB2_21:
	s_cmp_lt_u32 s7, 16
	s_cbranch_scc1 .LBB2_23
; %bb.22:
	v_add_nc_u32_e32 v5, 16, v4
	s_mov_b64 s[0:1], src_shared_base
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v5
	v_cndmask_b32_e32 v5, 0, v5, vcc_lo
	v_cndmask_b32_e64 v6, 0, s1, vcc_lo
	flat_load_u16 v5, v[5:6] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_nc_u16 v3, v5, v3
	flat_store_b16 v[1:2], v3 dlc
	s_waitcnt_vscnt null, 0x0
.LBB2_23:
	s_cmp_lt_u32 s7, 8
	s_cbranch_scc1 .LBB2_25
; %bb.24:
	v_add_nc_u32_e32 v5, 8, v4
	s_mov_b64 s[0:1], src_shared_base
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v5
	v_cndmask_b32_e32 v5, 0, v5, vcc_lo
	v_cndmask_b32_e64 v6, 0, s1, vcc_lo
	flat_load_u16 v5, v[5:6] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_nc_u16 v3, v5, v3
	flat_store_b16 v[1:2], v3 dlc
	s_waitcnt_vscnt null, 0x0
.LBB2_25:
	s_cmp_lt_u32 s7, 4
	s_cbranch_scc1 .LBB2_27
; %bb.26:
	v_add_nc_u32_e32 v5, 4, v4
	s_mov_b64 s[0:1], src_shared_base
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v5
	v_cndmask_b32_e32 v5, 0, v5, vcc_lo
	v_cndmask_b32_e64 v6, 0, s1, vcc_lo
	flat_load_u16 v5, v[5:6] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_nc_u16 v3, v5, v3
	flat_store_b16 v[1:2], v3 dlc
	s_waitcnt_vscnt null, 0x0
.LBB2_27:
	s_cmp_lt_u32 s7, 2
	s_cbranch_scc1 .LBB2_29
; %bb.28:
	v_add_nc_u32_e32 v4, 2, v4
	s_mov_b64 s[0:1], src_shared_base
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v4
	v_cndmask_b32_e32 v4, 0, v4, vcc_lo
	v_cndmask_b32_e64 v5, 0, s1, vcc_lo
	flat_load_u16 v4, v[4:5] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_nc_u16 v3, v4, v3
	flat_store_b16 v[1:2], v3 dlc
	s_waitcnt_vscnt null, 0x0
.LBB2_29:                               ; %Flow16
	s_or_b32 exec_lo, exec_lo, s5
	s_mov_b32 s5, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB2_31
; %bb.30:
	v_mov_b32_e32 v0, 0
	s_lshl_b64 s[0:1], s[4:5], 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s0, s2, s0
	s_addc_u32 s1, s3, s1
	ds_load_u16 v1, v0
	s_waitcnt lgkmcnt(0)
	global_store_b16 v0, v1, s[0:1]
.LBB2_31:                               ; %_Z7reduce5IsEvPT_S1_jj.exit
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel reduce5_s
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 24
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 7
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	reduce5_s, .Lfunc_end2-reduce5_s
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 944
; NumSgprs: 18
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	reduce5_i               ; -- Begin function reduce5_i
	.globl	reduce5_i
	.p2align	8
	.type	reduce5_i,@function
reduce5_i:                              ; @reduce5_i
; %bb.0:
	s_clause 0x1
	s_load_b64 s[6:7], s[0:1], 0x10
	s_load_b128 s[0:3], s[0:1], 0x0
	v_mov_b32_e32 v3, 0
	s_mov_b32 s4, s15
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s5, s15, s7
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshl_add_u32 v1, s5, 1, v0
	s_mov_b32 s5, exec_lo
	v_cmpx_gt_u32_e64 s6, v1
	s_cbranch_execz .LBB3_2
; %bb.1:
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[1:2]
	v_add_co_u32 v2, vcc_lo, s0, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
	global_load_b32 v3, v[2:3], off
.LBB3_2:
	s_or_b32 exec_lo, exec_lo, s5
	v_add_nc_u32_e32 v1, s7, v1
	s_mov_b32 s5, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e64 s6, v1
	s_cbranch_execz .LBB3_4
; %bb.3:
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v1, v[1:2], off
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v3, v1, v3
.LBB3_4:
	s_or_b32 exec_lo, exec_lo, s5
	v_lshl_add_u32 v4, v0, 2, 0
	s_cmpk_lt_u32 s7, 0x200
	s_waitcnt vmcnt(0)
	ds_store_b32 v4, v3
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB3_8
; %bb.5:
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 0x100, v0
	s_cbranch_execz .LBB3_7
; %bb.6:
	ds_load_b32 v1, v4 offset:1024
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v3, v1, v3
	ds_store_b32 v4, v3
.LBB3_7:
	s_or_b32 exec_lo, exec_lo, s0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
.LBB3_8:
	s_cmpk_lt_u32 s7, 0x100
	s_cbranch_scc1 .LBB3_12
; %bb.9:
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 0x80, v0
	s_cbranch_execz .LBB3_11
; %bb.10:
	ds_load_b32 v1, v4 offset:512
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v3, v1, v3
	ds_store_b32 v4, v3
.LBB3_11:
	s_or_b32 exec_lo, exec_lo, s0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
.LBB3_12:
	s_cmpk_lt_u32 s7, 0x80
	s_cbranch_scc1 .LBB3_16
; %bb.13:
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 64, v0
	s_cbranch_execz .LBB3_15
; %bb.14:
	ds_load_b32 v1, v4 offset:256
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v3, v1, v3
	ds_store_b32 v4, v3
.LBB3_15:
	s_or_b32 exec_lo, exec_lo, s0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
.LBB3_16:
	s_mov_b32 s5, exec_lo
	v_cmpx_gt_u32_e32 32, v0
	s_cbranch_execz .LBB3_29
; %bb.17:
	v_cmp_ne_u32_e32 vcc_lo, -1, v4
	s_mov_b64 s[0:1], src_shared_base
	s_cmp_lt_u32 s7, 64
	v_cndmask_b32_e64 v2, 0, s1, vcc_lo
	v_cndmask_b32_e32 v1, 0, v4, vcc_lo
	s_cbranch_scc1 .LBB3_19
; %bb.18:
	v_lshlrev_b32_e32 v5, 2, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v5, 0, v5, 0x80
	v_cmp_ne_u32_e32 vcc_lo, -1, v5
	v_cndmask_b32_e32 v5, 0, v5, vcc_lo
	v_cndmask_b32_e64 v6, 0, s1, vcc_lo
	flat_load_b32 v5, v[5:6] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_nc_u32_e32 v3, v5, v3
	flat_store_b32 v[1:2], v3 dlc
	s_waitcnt_vscnt null, 0x0
.LBB3_19:
	s_cmp_lt_u32 s7, 32
	s_cbranch_scc1 .LBB3_21
; %bb.20:
	v_add_nc_u32_e32 v5, 64, v4
	s_mov_b64 s[0:1], src_shared_base
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v5
	v_cndmask_b32_e32 v5, 0, v5, vcc_lo
	v_cndmask_b32_e64 v6, 0, s1, vcc_lo
	flat_load_b32 v5, v[5:6] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_nc_u32_e32 v3, v5, v3
	flat_store_b32 v[1:2], v3 dlc
	s_waitcnt_vscnt null, 0x0
.LBB3_21:
	s_cmp_lt_u32 s7, 16
	s_cbranch_scc1 .LBB3_23
; %bb.22:
	v_add_nc_u32_e32 v5, 32, v4
	s_mov_b64 s[0:1], src_shared_base
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v5
	v_cndmask_b32_e32 v5, 0, v5, vcc_lo
	v_cndmask_b32_e64 v6, 0, s1, vcc_lo
	flat_load_b32 v5, v[5:6] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_nc_u32_e32 v3, v5, v3
	flat_store_b32 v[1:2], v3 dlc
	s_waitcnt_vscnt null, 0x0
.LBB3_23:
	s_cmp_lt_u32 s7, 8
	s_cbranch_scc1 .LBB3_25
; %bb.24:
	v_add_nc_u32_e32 v5, 16, v4
	s_mov_b64 s[0:1], src_shared_base
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v5
	v_cndmask_b32_e32 v5, 0, v5, vcc_lo
	v_cndmask_b32_e64 v6, 0, s1, vcc_lo
	flat_load_b32 v5, v[5:6] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_nc_u32_e32 v3, v5, v3
	flat_store_b32 v[1:2], v3 dlc
	s_waitcnt_vscnt null, 0x0
.LBB3_25:
	s_cmp_lt_u32 s7, 4
	s_cbranch_scc1 .LBB3_27
; %bb.26:
	v_add_nc_u32_e32 v5, 8, v4
	s_mov_b64 s[0:1], src_shared_base
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v5
	v_cndmask_b32_e32 v5, 0, v5, vcc_lo
	v_cndmask_b32_e64 v6, 0, s1, vcc_lo
	flat_load_b32 v5, v[5:6] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_nc_u32_e32 v3, v5, v3
	flat_store_b32 v[1:2], v3 dlc
	s_waitcnt_vscnt null, 0x0
.LBB3_27:
	s_cmp_lt_u32 s7, 2
	s_cbranch_scc1 .LBB3_29
; %bb.28:
	v_add_nc_u32_e32 v4, 4, v4
	s_mov_b64 s[0:1], src_shared_base
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v4
	v_cndmask_b32_e32 v4, 0, v4, vcc_lo
	v_cndmask_b32_e64 v5, 0, s1, vcc_lo
	flat_load_b32 v4, v[4:5] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_nc_u32_e32 v3, v4, v3
	flat_store_b32 v[1:2], v3 dlc
	s_waitcnt_vscnt null, 0x0
.LBB3_29:                               ; %Flow16
	s_or_b32 exec_lo, exec_lo, s5
	s_mov_b32 s5, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB3_31
; %bb.30:
	v_mov_b32_e32 v0, 0
	s_lshl_b64 s[0:1], s[4:5], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s0, s2, s0
	s_addc_u32 s1, s3, s1
	ds_load_b32 v1, v0
	s_waitcnt lgkmcnt(0)
	global_store_b32 v0, v1, s[0:1]
.LBB3_31:                               ; %_Z7reduce5IiEvPT_S1_jj.exit
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel reduce5_i
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 24
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 7
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end3:
	.size	reduce5_i, .Lfunc_end3-reduce5_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 908
; NumSgprs: 18
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	reduce5_ui              ; -- Begin function reduce5_ui
	.globl	reduce5_ui
	.p2align	8
	.type	reduce5_ui,@function
reduce5_ui:                             ; @reduce5_ui
; %bb.0:
	s_clause 0x1
	s_load_b64 s[6:7], s[0:1], 0x10
	s_load_b128 s[0:3], s[0:1], 0x0
	v_mov_b32_e32 v3, 0
	s_mov_b32 s4, s15
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s5, s15, s7
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshl_add_u32 v1, s5, 1, v0
	s_mov_b32 s5, exec_lo
	v_cmpx_gt_u32_e64 s6, v1
	s_cbranch_execz .LBB4_2
; %bb.1:
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[1:2]
	v_add_co_u32 v2, vcc_lo, s0, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
	global_load_b32 v3, v[2:3], off
.LBB4_2:
	s_or_b32 exec_lo, exec_lo, s5
	v_add_nc_u32_e32 v1, s7, v1
	s_mov_b32 s5, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e64 s6, v1
	s_cbranch_execz .LBB4_4
; %bb.3:
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v1, v[1:2], off
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v3, v1, v3
.LBB4_4:
	s_or_b32 exec_lo, exec_lo, s5
	v_lshl_add_u32 v4, v0, 2, 0
	s_cmpk_lt_u32 s7, 0x200
	s_waitcnt vmcnt(0)
	ds_store_b32 v4, v3
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB4_8
; %bb.5:
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 0x100, v0
	s_cbranch_execz .LBB4_7
; %bb.6:
	ds_load_b32 v1, v4 offset:1024
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v3, v1, v3
	ds_store_b32 v4, v3
.LBB4_7:
	s_or_b32 exec_lo, exec_lo, s0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
.LBB4_8:
	s_cmpk_lt_u32 s7, 0x100
	s_cbranch_scc1 .LBB4_12
; %bb.9:
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 0x80, v0
	s_cbranch_execz .LBB4_11
; %bb.10:
	ds_load_b32 v1, v4 offset:512
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v3, v1, v3
	ds_store_b32 v4, v3
.LBB4_11:
	s_or_b32 exec_lo, exec_lo, s0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
.LBB4_12:
	s_cmpk_lt_u32 s7, 0x80
	s_cbranch_scc1 .LBB4_16
; %bb.13:
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 64, v0
	s_cbranch_execz .LBB4_15
; %bb.14:
	ds_load_b32 v1, v4 offset:256
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v3, v1, v3
	ds_store_b32 v4, v3
.LBB4_15:
	s_or_b32 exec_lo, exec_lo, s0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
.LBB4_16:
	s_mov_b32 s5, exec_lo
	v_cmpx_gt_u32_e32 32, v0
	s_cbranch_execz .LBB4_29
; %bb.17:
	v_cmp_ne_u32_e32 vcc_lo, -1, v4
	s_mov_b64 s[0:1], src_shared_base
	s_cmp_lt_u32 s7, 64
	v_cndmask_b32_e64 v2, 0, s1, vcc_lo
	v_cndmask_b32_e32 v1, 0, v4, vcc_lo
	s_cbranch_scc1 .LBB4_19
; %bb.18:
	v_lshlrev_b32_e32 v5, 2, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v5, 0, v5, 0x80
	v_cmp_ne_u32_e32 vcc_lo, -1, v5
	v_cndmask_b32_e32 v5, 0, v5, vcc_lo
	v_cndmask_b32_e64 v6, 0, s1, vcc_lo
	flat_load_b32 v5, v[5:6] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_nc_u32_e32 v3, v5, v3
	flat_store_b32 v[1:2], v3 dlc
	s_waitcnt_vscnt null, 0x0
.LBB4_19:
	s_cmp_lt_u32 s7, 32
	s_cbranch_scc1 .LBB4_21
; %bb.20:
	v_add_nc_u32_e32 v5, 64, v4
	s_mov_b64 s[0:1], src_shared_base
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v5
	v_cndmask_b32_e32 v5, 0, v5, vcc_lo
	v_cndmask_b32_e64 v6, 0, s1, vcc_lo
	flat_load_b32 v5, v[5:6] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_nc_u32_e32 v3, v5, v3
	flat_store_b32 v[1:2], v3 dlc
	s_waitcnt_vscnt null, 0x0
.LBB4_21:
	s_cmp_lt_u32 s7, 16
	s_cbranch_scc1 .LBB4_23
; %bb.22:
	v_add_nc_u32_e32 v5, 32, v4
	s_mov_b64 s[0:1], src_shared_base
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v5
	v_cndmask_b32_e32 v5, 0, v5, vcc_lo
	v_cndmask_b32_e64 v6, 0, s1, vcc_lo
	flat_load_b32 v5, v[5:6] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_nc_u32_e32 v3, v5, v3
	flat_store_b32 v[1:2], v3 dlc
	s_waitcnt_vscnt null, 0x0
.LBB4_23:
	s_cmp_lt_u32 s7, 8
	s_cbranch_scc1 .LBB4_25
; %bb.24:
	v_add_nc_u32_e32 v5, 16, v4
	s_mov_b64 s[0:1], src_shared_base
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v5
	v_cndmask_b32_e32 v5, 0, v5, vcc_lo
	v_cndmask_b32_e64 v6, 0, s1, vcc_lo
	flat_load_b32 v5, v[5:6] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_nc_u32_e32 v3, v5, v3
	flat_store_b32 v[1:2], v3 dlc
	s_waitcnt_vscnt null, 0x0
.LBB4_25:
	s_cmp_lt_u32 s7, 4
	s_cbranch_scc1 .LBB4_27
; %bb.26:
	v_add_nc_u32_e32 v5, 8, v4
	s_mov_b64 s[0:1], src_shared_base
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v5
	v_cndmask_b32_e32 v5, 0, v5, vcc_lo
	v_cndmask_b32_e64 v6, 0, s1, vcc_lo
	flat_load_b32 v5, v[5:6] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_nc_u32_e32 v3, v5, v3
	flat_store_b32 v[1:2], v3 dlc
	s_waitcnt_vscnt null, 0x0
.LBB4_27:
	s_cmp_lt_u32 s7, 2
	s_cbranch_scc1 .LBB4_29
; %bb.28:
	v_add_nc_u32_e32 v4, 4, v4
	s_mov_b64 s[0:1], src_shared_base
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v4
	v_cndmask_b32_e32 v4, 0, v4, vcc_lo
	v_cndmask_b32_e64 v5, 0, s1, vcc_lo
	flat_load_b32 v4, v[4:5] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_nc_u32_e32 v3, v4, v3
	flat_store_b32 v[1:2], v3 dlc
	s_waitcnt_vscnt null, 0x0
.LBB4_29:                               ; %Flow16
	s_or_b32 exec_lo, exec_lo, s5
	s_mov_b32 s5, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB4_31
; %bb.30:
	v_mov_b32_e32 v0, 0
	s_lshl_b64 s[0:1], s[4:5], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s0, s2, s0
	s_addc_u32 s1, s3, s1
	ds_load_b32 v1, v0
	s_waitcnt lgkmcnt(0)
	global_store_b32 v0, v1, s[0:1]
.LBB4_31:                               ; %_Z7reduce5IjEvPT_S1_jj.exit
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel reduce5_ui
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 24
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 7
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end4:
	.size	reduce5_ui, .Lfunc_end4-reduce5_ui
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 908
; NumSgprs: 18
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	reduce5_f               ; -- Begin function reduce5_f
	.globl	reduce5_f
	.p2align	8
	.type	reduce5_f,@function
reduce5_f:                              ; @reduce5_f
; %bb.0:
	s_clause 0x1
	s_load_b64 s[6:7], s[0:1], 0x10
	s_load_b128 s[0:3], s[0:1], 0x0
	v_mov_b32_e32 v3, 0
	s_mov_b32 s4, s15
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s5, s15, s7
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshl_add_u32 v1, s5, 1, v0
	s_mov_b32 s5, exec_lo
	v_cmpx_gt_u32_e64 s6, v1
	s_cbranch_execz .LBB5_2
; %bb.1:
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[1:2]
	v_add_co_u32 v2, vcc_lo, s0, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
	global_load_b32 v3, v[2:3], off
.LBB5_2:
	s_or_b32 exec_lo, exec_lo, s5
	v_add_nc_u32_e32 v1, s7, v1
	s_mov_b32 s5, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e64 s6, v1
	s_cbranch_execz .LBB5_4
; %bb.3:
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v1, v[1:2], off
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v3, v3, v1
.LBB5_4:
	s_or_b32 exec_lo, exec_lo, s5
	v_lshl_add_u32 v4, v0, 2, 0
	s_cmpk_lt_u32 s7, 0x200
	s_waitcnt vmcnt(0)
	ds_store_b32 v4, v3
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB5_8
; %bb.5:
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 0x100, v0
	s_cbranch_execz .LBB5_7
; %bb.6:
	ds_load_b32 v1, v4 offset:1024
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v3, v3, v1
	ds_store_b32 v4, v3
.LBB5_7:
	s_or_b32 exec_lo, exec_lo, s0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
.LBB5_8:
	s_cmpk_lt_u32 s7, 0x100
	s_cbranch_scc1 .LBB5_12
; %bb.9:
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 0x80, v0
	s_cbranch_execz .LBB5_11
; %bb.10:
	ds_load_b32 v1, v4 offset:512
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v3, v3, v1
	ds_store_b32 v4, v3
.LBB5_11:
	s_or_b32 exec_lo, exec_lo, s0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
.LBB5_12:
	s_cmpk_lt_u32 s7, 0x80
	s_cbranch_scc1 .LBB5_16
; %bb.13:
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 64, v0
	s_cbranch_execz .LBB5_15
; %bb.14:
	ds_load_b32 v1, v4 offset:256
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v3, v3, v1
	ds_store_b32 v4, v3
.LBB5_15:
	s_or_b32 exec_lo, exec_lo, s0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
.LBB5_16:
	s_mov_b32 s5, exec_lo
	v_cmpx_gt_u32_e32 32, v0
	s_cbranch_execz .LBB5_29
; %bb.17:
	v_cmp_ne_u32_e32 vcc_lo, -1, v4
	s_mov_b64 s[0:1], src_shared_base
	s_cmp_lt_u32 s7, 64
	v_cndmask_b32_e64 v2, 0, s1, vcc_lo
	v_cndmask_b32_e32 v1, 0, v4, vcc_lo
	s_cbranch_scc1 .LBB5_19
; %bb.18:
	v_lshlrev_b32_e32 v5, 2, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v5, 0, v5, 0x80
	v_cmp_ne_u32_e32 vcc_lo, -1, v5
	v_cndmask_b32_e32 v5, 0, v5, vcc_lo
	v_cndmask_b32_e64 v6, 0, s1, vcc_lo
	flat_load_b32 v5, v[5:6] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f32_e32 v3, v3, v5
	flat_store_b32 v[1:2], v3 dlc
	s_waitcnt_vscnt null, 0x0
.LBB5_19:
	s_cmp_lt_u32 s7, 32
	s_cbranch_scc1 .LBB5_21
; %bb.20:
	v_add_nc_u32_e32 v5, 64, v4
	s_mov_b64 s[0:1], src_shared_base
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v5
	v_cndmask_b32_e32 v5, 0, v5, vcc_lo
	v_cndmask_b32_e64 v6, 0, s1, vcc_lo
	flat_load_b32 v5, v[5:6] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f32_e32 v3, v3, v5
	flat_store_b32 v[1:2], v3 dlc
	s_waitcnt_vscnt null, 0x0
.LBB5_21:
	s_cmp_lt_u32 s7, 16
	s_cbranch_scc1 .LBB5_23
; %bb.22:
	v_add_nc_u32_e32 v5, 32, v4
	s_mov_b64 s[0:1], src_shared_base
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v5
	v_cndmask_b32_e32 v5, 0, v5, vcc_lo
	v_cndmask_b32_e64 v6, 0, s1, vcc_lo
	flat_load_b32 v5, v[5:6] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f32_e32 v3, v3, v5
	flat_store_b32 v[1:2], v3 dlc
	s_waitcnt_vscnt null, 0x0
.LBB5_23:
	s_cmp_lt_u32 s7, 8
	s_cbranch_scc1 .LBB5_25
; %bb.24:
	v_add_nc_u32_e32 v5, 16, v4
	s_mov_b64 s[0:1], src_shared_base
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v5
	v_cndmask_b32_e32 v5, 0, v5, vcc_lo
	v_cndmask_b32_e64 v6, 0, s1, vcc_lo
	flat_load_b32 v5, v[5:6] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f32_e32 v3, v3, v5
	flat_store_b32 v[1:2], v3 dlc
	s_waitcnt_vscnt null, 0x0
.LBB5_25:
	s_cmp_lt_u32 s7, 4
	s_cbranch_scc1 .LBB5_27
; %bb.26:
	v_add_nc_u32_e32 v5, 8, v4
	s_mov_b64 s[0:1], src_shared_base
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v5
	v_cndmask_b32_e32 v5, 0, v5, vcc_lo
	v_cndmask_b32_e64 v6, 0, s1, vcc_lo
	flat_load_b32 v5, v[5:6] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f32_e32 v3, v3, v5
	flat_store_b32 v[1:2], v3 dlc
	s_waitcnt_vscnt null, 0x0
.LBB5_27:
	s_cmp_lt_u32 s7, 2
	s_cbranch_scc1 .LBB5_29
; %bb.28:
	v_add_nc_u32_e32 v4, 4, v4
	s_mov_b64 s[0:1], src_shared_base
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v4
	v_cndmask_b32_e32 v4, 0, v4, vcc_lo
	v_cndmask_b32_e64 v5, 0, s1, vcc_lo
	flat_load_b32 v4, v[4:5] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f32_e32 v3, v3, v4
	flat_store_b32 v[1:2], v3 dlc
	s_waitcnt_vscnt null, 0x0
.LBB5_29:                               ; %Flow16
	s_or_b32 exec_lo, exec_lo, s5
	s_mov_b32 s5, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB5_31
; %bb.30:
	v_mov_b32_e32 v0, 0
	s_lshl_b64 s[0:1], s[4:5], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s0, s2, s0
	s_addc_u32 s1, s3, s1
	ds_load_b32 v1, v0
	s_waitcnt lgkmcnt(0)
	global_store_b32 v0, v1, s[0:1]
.LBB5_31:                               ; %_Z7reduce5IfEvPT_S1_jj.exit
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel reduce5_f
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 24
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 7
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end5:
	.size	reduce5_f, .Lfunc_end5-reduce5_f
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 908
; NumSgprs: 18
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	reduce5_d               ; -- Begin function reduce5_d
	.globl	reduce5_d
	.p2align	8
	.type	reduce5_d,@function
reduce5_d:                              ; @reduce5_d
; %bb.0:
	s_clause 0x1
	s_load_b64 s[6:7], s[0:1], 0x10
	s_load_b128 s[0:3], s[0:1], 0x0
	v_mov_b32_e32 v1, 0
	v_mov_b32_e32 v2, 0
	s_mov_b32 s4, s15
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s5, s15, s7
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshl_add_u32 v3, s5, 1, v0
	s_mov_b32 s5, exec_lo
	v_cmpx_gt_u32_e64 s6, v3
	s_cbranch_execz .LBB6_2
; %bb.1:
	v_mov_b32_e32 v4, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 3, v[3:4]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b64 v[1:2], v[1:2], off
.LBB6_2:
	s_or_b32 exec_lo, exec_lo, s5
	v_add_nc_u32_e32 v3, s7, v3
	s_mov_b32 s5, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e64 s6, v3
	s_cbranch_execz .LBB6_4
; %bb.3:
	v_mov_b32_e32 v4, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 3, v[3:4]
	v_add_co_u32 v3, vcc_lo, s0, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
	global_load_b64 v[3:4], v[3:4], off
	s_waitcnt vmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[3:4]
.LBB6_4:
	s_or_b32 exec_lo, exec_lo, s5
	v_lshl_add_u32 v5, v0, 3, 0
	s_cmpk_lt_u32 s7, 0x200
	s_waitcnt vmcnt(0)
	ds_store_b64 v5, v[1:2]
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB6_8
; %bb.5:
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 0x100, v0
	s_cbranch_execz .LBB6_7
; %bb.6:
	ds_load_b64 v[3:4], v5 offset:2048
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[3:4]
	ds_store_b64 v5, v[1:2]
.LBB6_7:
	s_or_b32 exec_lo, exec_lo, s0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
.LBB6_8:
	s_cmpk_lt_u32 s7, 0x100
	s_cbranch_scc1 .LBB6_12
; %bb.9:
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 0x80, v0
	s_cbranch_execz .LBB6_11
; %bb.10:
	ds_load_b64 v[3:4], v5 offset:1024
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[3:4]
	ds_store_b64 v5, v[1:2]
.LBB6_11:
	s_or_b32 exec_lo, exec_lo, s0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
.LBB6_12:
	s_cmpk_lt_u32 s7, 0x80
	s_cbranch_scc1 .LBB6_16
; %bb.13:
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 64, v0
	s_cbranch_execz .LBB6_15
; %bb.14:
	ds_load_b64 v[3:4], v5 offset:512
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[3:4]
	ds_store_b64 v5, v[1:2]
.LBB6_15:
	s_or_b32 exec_lo, exec_lo, s0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
.LBB6_16:
	s_mov_b32 s5, exec_lo
	v_cmpx_gt_u32_e32 32, v0
	s_cbranch_execz .LBB6_29
; %bb.17:
	v_cmp_ne_u32_e32 vcc_lo, -1, v5
	s_mov_b64 s[0:1], src_shared_base
	s_cmp_lt_u32 s7, 64
	v_cndmask_b32_e64 v4, 0, s1, vcc_lo
	v_cndmask_b32_e32 v3, 0, v5, vcc_lo
	s_cbranch_scc1 .LBB6_19
; %bb.18:
	v_lshlrev_b32_e32 v6, 3, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v6, 0, v6, 0x100
	v_cmp_ne_u32_e32 vcc_lo, -1, v6
	v_cndmask_b32_e32 v6, 0, v6, vcc_lo
	v_cndmask_b32_e64 v7, 0, s1, vcc_lo
	flat_load_b64 v[6:7], v[6:7] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[6:7]
	flat_store_b64 v[3:4], v[1:2] dlc
	s_waitcnt_vscnt null, 0x0
.LBB6_19:
	s_cmp_lt_u32 s7, 32
	s_cbranch_scc1 .LBB6_21
; %bb.20:
	v_add_nc_u32_e32 v6, 0x80, v5
	s_mov_b64 s[0:1], src_shared_base
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v6
	v_cndmask_b32_e32 v6, 0, v6, vcc_lo
	v_cndmask_b32_e64 v7, 0, s1, vcc_lo
	flat_load_b64 v[6:7], v[6:7] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[6:7]
	flat_store_b64 v[3:4], v[1:2] dlc
	s_waitcnt_vscnt null, 0x0
.LBB6_21:
	s_cmp_lt_u32 s7, 16
	s_cbranch_scc1 .LBB6_23
; %bb.22:
	v_add_nc_u32_e32 v6, 64, v5
	s_mov_b64 s[0:1], src_shared_base
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v6
	v_cndmask_b32_e32 v6, 0, v6, vcc_lo
	v_cndmask_b32_e64 v7, 0, s1, vcc_lo
	flat_load_b64 v[6:7], v[6:7] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[6:7]
	flat_store_b64 v[3:4], v[1:2] dlc
	s_waitcnt_vscnt null, 0x0
.LBB6_23:
	s_cmp_lt_u32 s7, 8
	s_cbranch_scc1 .LBB6_25
; %bb.24:
	v_add_nc_u32_e32 v6, 32, v5
	s_mov_b64 s[0:1], src_shared_base
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v6
	v_cndmask_b32_e32 v6, 0, v6, vcc_lo
	v_cndmask_b32_e64 v7, 0, s1, vcc_lo
	flat_load_b64 v[6:7], v[6:7] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[6:7]
	flat_store_b64 v[3:4], v[1:2] dlc
	s_waitcnt_vscnt null, 0x0
.LBB6_25:
	s_cmp_lt_u32 s7, 4
	s_cbranch_scc1 .LBB6_27
; %bb.26:
	v_add_nc_u32_e32 v6, 16, v5
	s_mov_b64 s[0:1], src_shared_base
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v6
	v_cndmask_b32_e32 v6, 0, v6, vcc_lo
	v_cndmask_b32_e64 v7, 0, s1, vcc_lo
	flat_load_b64 v[6:7], v[6:7] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[6:7]
	flat_store_b64 v[3:4], v[1:2] dlc
	s_waitcnt_vscnt null, 0x0
.LBB6_27:
	s_cmp_lt_u32 s7, 2
	s_cbranch_scc1 .LBB6_29
; %bb.28:
	v_add_nc_u32_e32 v5, 8, v5
	s_mov_b64 s[0:1], src_shared_base
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v5
	v_cndmask_b32_e32 v5, 0, v5, vcc_lo
	v_cndmask_b32_e64 v6, 0, s1, vcc_lo
	flat_load_b64 v[5:6], v[5:6] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[5:6]
	flat_store_b64 v[3:4], v[1:2] dlc
	s_waitcnt_vscnt null, 0x0
.LBB6_29:                               ; %Flow16
	s_or_b32 exec_lo, exec_lo, s5
	s_mov_b32 s5, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB6_31
; %bb.30:
	v_mov_b32_e32 v2, 0
	s_lshl_b64 s[0:1], s[4:5], 3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s0, s2, s0
	s_addc_u32 s1, s3, s1
	ds_load_b64 v[0:1], v2
	s_waitcnt lgkmcnt(0)
	global_store_b64 v2, v[0:1], s[0:1]
.LBB6_31:                               ; %_Z7reduce5IdEvPT_S1_jj.exit
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel reduce5_d
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 24
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 8
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end6:
	.size	reduce5_d, .Lfunc_end6-reduce5_d
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 956
; NumSgprs: 18
; NumVgprs: 8
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 8
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	reduce6_c               ; -- Begin function reduce6_c
	.globl	reduce6_c
	.p2align	8
	.type	reduce6_c,@function
reduce6_c:                              ; @reduce6_c
; %bb.0:
	s_load_b256 s[4:11], s[0:1], 0x0
	v_mov_b32_e32 v3, 0
	s_mov_b32 s2, exec_lo
	s_waitcnt lgkmcnt(0)
	s_lshl_b32 s11, s9, 1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s3, s11, s15
	v_add_nc_u32_e32 v1, s3, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e64 s8, v1
	s_cbranch_execz .LBB7_6
; %bb.1:                                ; %.lr.ph.i.preheader
	s_load_b32 s12, s[0:1], 0x20
	s_bitcmp1_b32 s10, 0
	v_mov_b32_e32 v3, 0
	s_cselect_b32 s0, -1, 0
	s_lshl_b32 s1, s15, 1
	v_mov_b32_e32 v1, v0
	s_or_b32 s1, s1, 1
	s_mov_b32 s10, 0
	s_mul_i32 s1, s9, s1
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s11, s12, s11
.LBB7_2:                                ; %.lr.ph.i
                                        ; =>This Inner Loop Header: Depth=1
	v_add_nc_u32_e32 v2, s3, v1
	global_load_u8 v4, v2, s[4:5]
	v_add_nc_u32_e32 v2, s1, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u32_e32 vcc_lo, s8, v2
	s_or_b32 s13, vcc_lo, s0
	s_waitcnt vmcnt(0)
	v_add_nc_u16 v3, v4, v3
	s_and_saveexec_b32 s12, s13
	s_cbranch_execz .LBB7_4
; %bb.3:                                ;   in Loop: Header=BB7_2 Depth=1
	global_load_u8 v2, v2, s[4:5]
	s_waitcnt vmcnt(0)
	v_add_nc_u16 v3, v2, v3
.LBB7_4:                                ;   in Loop: Header=BB7_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s12
	v_add_nc_u32_e32 v1, s11, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v2, s3, v1
	v_cmp_le_u32_e32 vcc_lo, s8, v2
	s_or_b32 s10, vcc_lo, s10
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s10
	s_cbranch_execnz .LBB7_2
; %bb.5:                                ; %Flow23
	s_or_b32 exec_lo, exec_lo, s10
.LBB7_6:                                ; %Flow24
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s2
	v_add_nc_u32_e32 v4, 0, v0
	s_cmpk_lt_u32 s9, 0x200
	ds_store_b8 v4, v3
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB7_10
; %bb.7:
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 0x100, v0
	s_cbranch_execz .LBB7_9
; %bb.8:
	ds_load_u8 v1, v4 offset:256
	s_waitcnt lgkmcnt(0)
	v_add_nc_u16 v3, v1, v3
	ds_store_b8 v4, v3
.LBB7_9:
	s_or_b32 exec_lo, exec_lo, s0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
.LBB7_10:
	s_cmpk_lt_u32 s9, 0x100
	s_cbranch_scc1 .LBB7_14
; %bb.11:
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 0x80, v0
	s_cbranch_execz .LBB7_13
; %bb.12:
	ds_load_u8 v1, v4 offset:128
	s_waitcnt lgkmcnt(0)
	v_add_nc_u16 v3, v1, v3
	ds_store_b8 v4, v3
.LBB7_13:
	s_or_b32 exec_lo, exec_lo, s0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
.LBB7_14:
	s_cmpk_lt_u32 s9, 0x80
	s_cbranch_scc1 .LBB7_18
; %bb.15:
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 64, v0
	s_cbranch_execz .LBB7_17
; %bb.16:
	ds_load_u8 v1, v4 offset:64
	s_waitcnt lgkmcnt(0)
	v_add_nc_u16 v3, v1, v3
	ds_store_b8 v4, v3
.LBB7_17:
	s_or_b32 exec_lo, exec_lo, s0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
.LBB7_18:
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_u32_e32 32, v0
	s_cbranch_execz .LBB7_31
; %bb.19:
	v_cmp_ne_u32_e32 vcc_lo, -1, v4
	s_mov_b64 s[0:1], src_shared_base
	s_cmp_lt_u32 s9, 64
	v_cndmask_b32_e64 v2, 0, s1, vcc_lo
	v_cndmask_b32_e32 v1, 0, v4, vcc_lo
	s_cbranch_scc1 .LBB7_21
; %bb.20:
	v_add3_u32 v5, 0, v0, 32
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v5
	v_cndmask_b32_e32 v5, 0, v5, vcc_lo
	v_cndmask_b32_e64 v6, 0, s1, vcc_lo
	flat_load_u8 v5, v[5:6] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_nc_u16 v3, v5, v3
	flat_store_b8 v[1:2], v3 dlc
	s_waitcnt_vscnt null, 0x0
.LBB7_21:
	s_cmp_lt_u32 s9, 32
	s_cbranch_scc1 .LBB7_23
; %bb.22:
	v_add_nc_u32_e32 v5, 16, v4
	s_mov_b64 s[0:1], src_shared_base
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v5
	v_cndmask_b32_e32 v5, 0, v5, vcc_lo
	v_cndmask_b32_e64 v6, 0, s1, vcc_lo
	flat_load_u8 v5, v[5:6] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_nc_u16 v3, v5, v3
	flat_store_b8 v[1:2], v3 dlc
	s_waitcnt_vscnt null, 0x0
.LBB7_23:
	s_cmp_lt_u32 s9, 16
	s_cbranch_scc1 .LBB7_25
; %bb.24:
	v_add_nc_u32_e32 v5, 8, v4
	s_mov_b64 s[0:1], src_shared_base
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v5
	v_cndmask_b32_e32 v5, 0, v5, vcc_lo
	v_cndmask_b32_e64 v6, 0, s1, vcc_lo
	flat_load_u8 v5, v[5:6] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_nc_u16 v3, v5, v3
	flat_store_b8 v[1:2], v3 dlc
	s_waitcnt_vscnt null, 0x0
.LBB7_25:
	s_cmp_lt_u32 s9, 8
	s_cbranch_scc1 .LBB7_27
; %bb.26:
	v_add_nc_u32_e32 v5, 4, v4
	s_mov_b64 s[0:1], src_shared_base
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v5
	v_cndmask_b32_e32 v5, 0, v5, vcc_lo
	v_cndmask_b32_e64 v6, 0, s1, vcc_lo
	flat_load_u8 v5, v[5:6] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_nc_u16 v3, v5, v3
	flat_store_b8 v[1:2], v3 dlc
	s_waitcnt_vscnt null, 0x0
.LBB7_27:
	s_cmp_lt_u32 s9, 4
	s_cbranch_scc1 .LBB7_29
; %bb.28:
	v_add_nc_u32_e32 v5, 2, v4
	s_mov_b64 s[0:1], src_shared_base
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v5
	v_cndmask_b32_e32 v5, 0, v5, vcc_lo
	v_cndmask_b32_e64 v6, 0, s1, vcc_lo
	flat_load_u8 v5, v[5:6] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_nc_u16 v3, v5, v3
	flat_store_b8 v[1:2], v3 dlc
	s_waitcnt_vscnt null, 0x0
.LBB7_29:
	s_cmp_lt_u32 s9, 2
	s_cbranch_scc1 .LBB7_31
; %bb.30:
	v_add_nc_u32_e32 v4, 1, v4
	s_mov_b64 s[0:1], src_shared_base
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v4
	v_cndmask_b32_e32 v4, 0, v4, vcc_lo
	v_cndmask_b32_e64 v5, 0, s1, vcc_lo
	flat_load_u8 v4, v[4:5] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_nc_u16 v3, v4, v3
	flat_store_b8 v[1:2], v3 dlc
	s_waitcnt_vscnt null, 0x0
.LBB7_31:                               ; %Flow19
	s_or_b32 exec_lo, exec_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB7_33
; %bb.32:
	v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s15
	ds_load_u8 v0, v0
	s_waitcnt lgkmcnt(0)
	global_store_b8 v1, v0, s[6:7]
.LBB7_33:                               ; %_Z7reduce6IcEvPT_S1_jjb.exit
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel reduce6_c
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 7
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end7:
	.size	reduce6_c, .Lfunc_end7-reduce6_c
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 948
; NumSgprs: 18
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	reduce6_uc              ; -- Begin function reduce6_uc
	.globl	reduce6_uc
	.p2align	8
	.type	reduce6_uc,@function
reduce6_uc:                             ; @reduce6_uc
; %bb.0:
	s_load_b256 s[4:11], s[0:1], 0x0
	v_mov_b32_e32 v3, 0
	s_mov_b32 s2, exec_lo
	s_waitcnt lgkmcnt(0)
	s_lshl_b32 s11, s9, 1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s3, s11, s15
	v_add_nc_u32_e32 v1, s3, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e64 s8, v1
	s_cbranch_execz .LBB8_6
; %bb.1:                                ; %.lr.ph.i.preheader
	s_load_b32 s12, s[0:1], 0x20
	s_bitcmp1_b32 s10, 0
	v_mov_b32_e32 v3, 0
	s_cselect_b32 s0, -1, 0
	s_lshl_b32 s1, s15, 1
	v_mov_b32_e32 v1, v0
	s_or_b32 s1, s1, 1
	s_mov_b32 s10, 0
	s_mul_i32 s1, s9, s1
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s11, s12, s11
.LBB8_2:                                ; %.lr.ph.i
                                        ; =>This Inner Loop Header: Depth=1
	v_add_nc_u32_e32 v2, s3, v1
	global_load_u8 v4, v2, s[4:5]
	v_add_nc_u32_e32 v2, s1, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u32_e32 vcc_lo, s8, v2
	s_or_b32 s13, vcc_lo, s0
	s_waitcnt vmcnt(0)
	v_add_nc_u16 v3, v4, v3
	s_and_saveexec_b32 s12, s13
	s_cbranch_execz .LBB8_4
; %bb.3:                                ;   in Loop: Header=BB8_2 Depth=1
	global_load_u8 v2, v2, s[4:5]
	s_waitcnt vmcnt(0)
	v_add_nc_u16 v3, v2, v3
.LBB8_4:                                ;   in Loop: Header=BB8_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s12
	v_add_nc_u32_e32 v1, s11, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v2, s3, v1
	v_cmp_le_u32_e32 vcc_lo, s8, v2
	s_or_b32 s10, vcc_lo, s10
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s10
	s_cbranch_execnz .LBB8_2
; %bb.5:                                ; %Flow23
	s_or_b32 exec_lo, exec_lo, s10
.LBB8_6:                                ; %Flow24
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s2
	v_add_nc_u32_e32 v4, 0, v0
	s_cmpk_lt_u32 s9, 0x200
	ds_store_b8 v4, v3
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB8_10
; %bb.7:
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 0x100, v0
	s_cbranch_execz .LBB8_9
; %bb.8:
	ds_load_u8 v1, v4 offset:256
	s_waitcnt lgkmcnt(0)
	v_add_nc_u16 v3, v1, v3
	ds_store_b8 v4, v3
.LBB8_9:
	s_or_b32 exec_lo, exec_lo, s0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
.LBB8_10:
	s_cmpk_lt_u32 s9, 0x100
	s_cbranch_scc1 .LBB8_14
; %bb.11:
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 0x80, v0
	s_cbranch_execz .LBB8_13
; %bb.12:
	ds_load_u8 v1, v4 offset:128
	s_waitcnt lgkmcnt(0)
	v_add_nc_u16 v3, v1, v3
	ds_store_b8 v4, v3
.LBB8_13:
	s_or_b32 exec_lo, exec_lo, s0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
.LBB8_14:
	s_cmpk_lt_u32 s9, 0x80
	s_cbranch_scc1 .LBB8_18
; %bb.15:
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 64, v0
	s_cbranch_execz .LBB8_17
; %bb.16:
	ds_load_u8 v1, v4 offset:64
	s_waitcnt lgkmcnt(0)
	v_add_nc_u16 v3, v1, v3
	ds_store_b8 v4, v3
.LBB8_17:
	s_or_b32 exec_lo, exec_lo, s0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
.LBB8_18:
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_u32_e32 32, v0
	s_cbranch_execz .LBB8_31
; %bb.19:
	v_cmp_ne_u32_e32 vcc_lo, -1, v4
	s_mov_b64 s[0:1], src_shared_base
	s_cmp_lt_u32 s9, 64
	v_cndmask_b32_e64 v2, 0, s1, vcc_lo
	v_cndmask_b32_e32 v1, 0, v4, vcc_lo
	s_cbranch_scc1 .LBB8_21
; %bb.20:
	v_add3_u32 v5, 0, v0, 32
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v5
	v_cndmask_b32_e32 v5, 0, v5, vcc_lo
	v_cndmask_b32_e64 v6, 0, s1, vcc_lo
	flat_load_u8 v5, v[5:6] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_nc_u16 v3, v5, v3
	flat_store_b8 v[1:2], v3 dlc
	s_waitcnt_vscnt null, 0x0
.LBB8_21:
	s_cmp_lt_u32 s9, 32
	s_cbranch_scc1 .LBB8_23
; %bb.22:
	v_add_nc_u32_e32 v5, 16, v4
	s_mov_b64 s[0:1], src_shared_base
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v5
	v_cndmask_b32_e32 v5, 0, v5, vcc_lo
	v_cndmask_b32_e64 v6, 0, s1, vcc_lo
	flat_load_u8 v5, v[5:6] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_nc_u16 v3, v5, v3
	flat_store_b8 v[1:2], v3 dlc
	s_waitcnt_vscnt null, 0x0
.LBB8_23:
	s_cmp_lt_u32 s9, 16
	s_cbranch_scc1 .LBB8_25
; %bb.24:
	v_add_nc_u32_e32 v5, 8, v4
	s_mov_b64 s[0:1], src_shared_base
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v5
	v_cndmask_b32_e32 v5, 0, v5, vcc_lo
	v_cndmask_b32_e64 v6, 0, s1, vcc_lo
	flat_load_u8 v5, v[5:6] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_nc_u16 v3, v5, v3
	flat_store_b8 v[1:2], v3 dlc
	s_waitcnt_vscnt null, 0x0
.LBB8_25:
	s_cmp_lt_u32 s9, 8
	s_cbranch_scc1 .LBB8_27
; %bb.26:
	v_add_nc_u32_e32 v5, 4, v4
	s_mov_b64 s[0:1], src_shared_base
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v5
	v_cndmask_b32_e32 v5, 0, v5, vcc_lo
	v_cndmask_b32_e64 v6, 0, s1, vcc_lo
	flat_load_u8 v5, v[5:6] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_nc_u16 v3, v5, v3
	flat_store_b8 v[1:2], v3 dlc
	s_waitcnt_vscnt null, 0x0
.LBB8_27:
	s_cmp_lt_u32 s9, 4
	s_cbranch_scc1 .LBB8_29
; %bb.28:
	v_add_nc_u32_e32 v5, 2, v4
	s_mov_b64 s[0:1], src_shared_base
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v5
	v_cndmask_b32_e32 v5, 0, v5, vcc_lo
	v_cndmask_b32_e64 v6, 0, s1, vcc_lo
	flat_load_u8 v5, v[5:6] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_nc_u16 v3, v5, v3
	flat_store_b8 v[1:2], v3 dlc
	s_waitcnt_vscnt null, 0x0
.LBB8_29:
	s_cmp_lt_u32 s9, 2
	s_cbranch_scc1 .LBB8_31
; %bb.30:
	v_add_nc_u32_e32 v4, 1, v4
	s_mov_b64 s[0:1], src_shared_base
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v4
	v_cndmask_b32_e32 v4, 0, v4, vcc_lo
	v_cndmask_b32_e64 v5, 0, s1, vcc_lo
	flat_load_u8 v4, v[4:5] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_nc_u16 v3, v4, v3
	flat_store_b8 v[1:2], v3 dlc
	s_waitcnt_vscnt null, 0x0
.LBB8_31:                               ; %Flow19
	s_or_b32 exec_lo, exec_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB8_33
; %bb.32:
	v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s15
	ds_load_u8 v0, v0
	s_waitcnt lgkmcnt(0)
	global_store_b8 v1, v0, s[6:7]
.LBB8_33:                               ; %_Z7reduce6IhEvPT_S1_jjb.exit
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel reduce6_uc
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 7
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end8:
	.size	reduce6_uc, .Lfunc_end8-reduce6_uc
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 948
; NumSgprs: 18
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	reduce6_s               ; -- Begin function reduce6_s
	.globl	reduce6_s
	.p2align	8
	.type	reduce6_s,@function
reduce6_s:                              ; @reduce6_s
; %bb.0:
	s_load_b256 s[4:11], s[0:1], 0x0
	v_mov_b32_e32 v3, 0
	s_mov_b32 s2, s15
	s_mov_b32 s3, exec_lo
	s_waitcnt lgkmcnt(0)
	s_lshl_b32 s12, s9, 1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s11, s12, s15
	v_add_nc_u32_e32 v1, s11, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e64 s8, v1
	s_cbranch_execz .LBB9_6
; %bb.1:                                ; %.lr.ph.i.preheader
	s_load_b32 s13, s[0:1], 0x20
	s_bitcmp1_b32 s10, 0
	v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v3, 0
	s_cselect_b32 s0, -1, 0
	s_lshl_b32 s1, s2, 1
	v_mov_b32_e32 v4, v0
	s_or_b32 s1, s1, 1
	s_mov_b32 s10, 0
	s_mul_i32 s1, s9, s1
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s12, s13, s12
.LBB9_2:                                ; %.lr.ph.i
                                        ; =>This Inner Loop Header: Depth=1
	v_add_nc_u32_e32 v1, s11, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[5:6], 1, v[1:2]
	v_add_nc_u32_e32 v1, s1, v4
	v_add_co_u32 v5, vcc_lo, s4, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
	v_cmp_gt_u32_e32 vcc_lo, s8, v1
	global_load_u16 v5, v[5:6], off
	s_or_b32 s14, vcc_lo, s0
	s_waitcnt vmcnt(0)
	v_add_nc_u16 v3, v5, v3
	s_and_saveexec_b32 s13, s14
	s_cbranch_execz .LBB9_4
; %bb.3:                                ;   in Loop: Header=BB9_2 Depth=1
	v_lshlrev_b64 v[5:6], 1, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v5, vcc_lo, s4, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
	global_load_u16 v1, v[5:6], off
	s_waitcnt vmcnt(0)
	v_add_nc_u16 v3, v1, v3
.LBB9_4:                                ;   in Loop: Header=BB9_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s13
	v_add_nc_u32_e32 v4, s12, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v1, s11, v4
	v_cmp_le_u32_e32 vcc_lo, s8, v1
	s_or_b32 s10, vcc_lo, s10
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s10
	s_cbranch_execnz .LBB9_2
; %bb.5:                                ; %Flow21
	s_or_b32 exec_lo, exec_lo, s10
.LBB9_6:                                ; %Flow22
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s3
	v_lshl_add_u32 v4, v0, 1, 0
	s_cmpk_lt_u32 s9, 0x200
	ds_store_b16 v4, v3
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB9_10
; %bb.7:
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 0x100, v0
	s_cbranch_execz .LBB9_9
; %bb.8:
	ds_load_u16 v1, v4 offset:512
	s_waitcnt lgkmcnt(0)
	v_add_nc_u16 v3, v1, v3
	ds_store_b16 v4, v3
.LBB9_9:
	s_or_b32 exec_lo, exec_lo, s0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
.LBB9_10:
	s_cmpk_lt_u32 s9, 0x100
	s_cbranch_scc1 .LBB9_14
; %bb.11:
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 0x80, v0
	s_cbranch_execz .LBB9_13
; %bb.12:
	ds_load_u16 v1, v4 offset:256
	s_waitcnt lgkmcnt(0)
	v_add_nc_u16 v3, v1, v3
	ds_store_b16 v4, v3
.LBB9_13:
	s_or_b32 exec_lo, exec_lo, s0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
.LBB9_14:
	s_cmpk_lt_u32 s9, 0x80
	s_cbranch_scc1 .LBB9_18
; %bb.15:
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 64, v0
	s_cbranch_execz .LBB9_17
; %bb.16:
	ds_load_u16 v1, v4 offset:128
	s_waitcnt lgkmcnt(0)
	v_add_nc_u16 v3, v1, v3
	ds_store_b16 v4, v3
.LBB9_17:
	s_or_b32 exec_lo, exec_lo, s0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
.LBB9_18:
	s_mov_b32 s3, exec_lo
	v_cmpx_gt_u32_e32 32, v0
	s_cbranch_execz .LBB9_31
; %bb.19:
	v_cmp_ne_u32_e32 vcc_lo, -1, v4
	s_mov_b64 s[0:1], src_shared_base
	s_cmp_lt_u32 s9, 64
	v_cndmask_b32_e64 v2, 0, s1, vcc_lo
	v_cndmask_b32_e32 v1, 0, v4, vcc_lo
	s_cbranch_scc1 .LBB9_21
; %bb.20:
	v_lshlrev_b32_e32 v5, 1, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v5, 0, v5, 64
	v_cmp_ne_u32_e32 vcc_lo, -1, v5
	v_cndmask_b32_e32 v5, 0, v5, vcc_lo
	v_cndmask_b32_e64 v6, 0, s1, vcc_lo
	flat_load_u16 v5, v[5:6] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_nc_u16 v3, v5, v3
	flat_store_b16 v[1:2], v3 dlc
	s_waitcnt_vscnt null, 0x0
.LBB9_21:
	s_cmp_lt_u32 s9, 32
	s_cbranch_scc1 .LBB9_23
; %bb.22:
	v_add_nc_u32_e32 v5, 32, v4
	s_mov_b64 s[0:1], src_shared_base
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v5
	v_cndmask_b32_e32 v5, 0, v5, vcc_lo
	v_cndmask_b32_e64 v6, 0, s1, vcc_lo
	flat_load_u16 v5, v[5:6] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_nc_u16 v3, v5, v3
	flat_store_b16 v[1:2], v3 dlc
	s_waitcnt_vscnt null, 0x0
.LBB9_23:
	s_cmp_lt_u32 s9, 16
	s_cbranch_scc1 .LBB9_25
; %bb.24:
	v_add_nc_u32_e32 v5, 16, v4
	s_mov_b64 s[0:1], src_shared_base
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v5
	v_cndmask_b32_e32 v5, 0, v5, vcc_lo
	v_cndmask_b32_e64 v6, 0, s1, vcc_lo
	flat_load_u16 v5, v[5:6] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_nc_u16 v3, v5, v3
	flat_store_b16 v[1:2], v3 dlc
	s_waitcnt_vscnt null, 0x0
.LBB9_25:
	s_cmp_lt_u32 s9, 8
	s_cbranch_scc1 .LBB9_27
; %bb.26:
	v_add_nc_u32_e32 v5, 8, v4
	s_mov_b64 s[0:1], src_shared_base
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v5
	v_cndmask_b32_e32 v5, 0, v5, vcc_lo
	v_cndmask_b32_e64 v6, 0, s1, vcc_lo
	flat_load_u16 v5, v[5:6] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_nc_u16 v3, v5, v3
	flat_store_b16 v[1:2], v3 dlc
	s_waitcnt_vscnt null, 0x0
.LBB9_27:
	s_cmp_lt_u32 s9, 4
	s_cbranch_scc1 .LBB9_29
; %bb.28:
	v_add_nc_u32_e32 v5, 4, v4
	s_mov_b64 s[0:1], src_shared_base
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v5
	v_cndmask_b32_e32 v5, 0, v5, vcc_lo
	v_cndmask_b32_e64 v6, 0, s1, vcc_lo
	flat_load_u16 v5, v[5:6] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_nc_u16 v3, v5, v3
	flat_store_b16 v[1:2], v3 dlc
	s_waitcnt_vscnt null, 0x0
.LBB9_29:
	s_cmp_lt_u32 s9, 2
	s_cbranch_scc1 .LBB9_31
; %bb.30:
	v_add_nc_u32_e32 v4, 2, v4
	s_mov_b64 s[0:1], src_shared_base
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v4
	v_cndmask_b32_e32 v4, 0, v4, vcc_lo
	v_cndmask_b32_e64 v5, 0, s1, vcc_lo
	flat_load_u16 v4, v[4:5] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_nc_u16 v3, v4, v3
	flat_store_b16 v[1:2], v3 dlc
	s_waitcnt_vscnt null, 0x0
.LBB9_31:                               ; %Flow17
	s_or_b32 exec_lo, exec_lo, s3
	s_mov_b32 s3, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB9_33
; %bb.32:
	v_mov_b32_e32 v0, 0
	s_lshl_b64 s[0:1], s[2:3], 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s0, s6, s0
	s_addc_u32 s1, s7, s1
	ds_load_u16 v1, v0
	s_waitcnt lgkmcnt(0)
	global_store_b16 v0, v1, s[0:1]
.LBB9_33:                               ; %_Z7reduce6IsEvPT_S1_jjb.exit
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel reduce6_s
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 7
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end9:
	.size	reduce6_s, .Lfunc_end9-reduce6_s
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1024
; NumSgprs: 18
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	reduce6_i               ; -- Begin function reduce6_i
	.globl	reduce6_i
	.p2align	8
	.type	reduce6_i,@function
reduce6_i:                              ; @reduce6_i
; %bb.0:
	s_load_b256 s[4:11], s[0:1], 0x0
	v_mov_b32_e32 v3, 0
	s_mov_b32 s2, s15
	s_mov_b32 s3, exec_lo
	s_waitcnt lgkmcnt(0)
	s_lshl_b32 s12, s9, 1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s11, s12, s15
	v_add_nc_u32_e32 v1, s11, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e64 s8, v1
	s_cbranch_execz .LBB10_6
; %bb.1:                                ; %.lr.ph.i.preheader
	s_load_b32 s13, s[0:1], 0x20
	s_bitcmp1_b32 s10, 0
	v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v2, 0
	s_cselect_b32 s0, -1, 0
	s_lshl_b32 s1, s2, 1
	v_mov_b32_e32 v4, v0
	s_or_b32 s1, s1, 1
	s_mov_b32 s10, 0
	s_mul_i32 s1, s9, s1
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s12, s13, s12
.LBB10_2:                               ; %.lr.ph.i
                                        ; =>This Inner Loop Header: Depth=1
	v_add_nc_u32_e32 v1, s11, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[5:6], 2, v[1:2]
	v_add_nc_u32_e32 v1, s1, v4
	v_add_co_u32 v5, vcc_lo, s4, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
	v_cmp_gt_u32_e32 vcc_lo, s8, v1
	global_load_b32 v5, v[5:6], off
	s_or_b32 s14, vcc_lo, s0
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v3, v5, v3
	s_and_saveexec_b32 s13, s14
	s_cbranch_execz .LBB10_4
; %bb.3:                                ;   in Loop: Header=BB10_2 Depth=1
	v_lshlrev_b64 v[5:6], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v5, vcc_lo, s4, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
	global_load_b32 v1, v[5:6], off
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v3, v1, v3
.LBB10_4:                               ;   in Loop: Header=BB10_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s13
	v_add_nc_u32_e32 v4, s12, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v1, s11, v4
	v_cmp_le_u32_e32 vcc_lo, s8, v1
	s_or_b32 s10, vcc_lo, s10
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s10
	s_cbranch_execnz .LBB10_2
; %bb.5:                                ; %Flow21
	s_or_b32 exec_lo, exec_lo, s10
.LBB10_6:                               ; %Flow22
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s3
	v_lshl_add_u32 v4, v0, 2, 0
	s_cmpk_lt_u32 s9, 0x200
	ds_store_b32 v4, v3
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB10_10
; %bb.7:
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 0x100, v0
	s_cbranch_execz .LBB10_9
; %bb.8:
	ds_load_b32 v1, v4 offset:1024
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v3, v1, v3
	ds_store_b32 v4, v3
.LBB10_9:
	s_or_b32 exec_lo, exec_lo, s0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
.LBB10_10:
	s_cmpk_lt_u32 s9, 0x100
	s_cbranch_scc1 .LBB10_14
; %bb.11:
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 0x80, v0
	s_cbranch_execz .LBB10_13
; %bb.12:
	ds_load_b32 v1, v4 offset:512
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v3, v1, v3
	ds_store_b32 v4, v3
.LBB10_13:
	s_or_b32 exec_lo, exec_lo, s0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
.LBB10_14:
	s_cmpk_lt_u32 s9, 0x80
	s_cbranch_scc1 .LBB10_18
; %bb.15:
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 64, v0
	s_cbranch_execz .LBB10_17
; %bb.16:
	ds_load_b32 v1, v4 offset:256
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v3, v1, v3
	ds_store_b32 v4, v3
.LBB10_17:
	s_or_b32 exec_lo, exec_lo, s0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
.LBB10_18:
	s_mov_b32 s3, exec_lo
	v_cmpx_gt_u32_e32 32, v0
	s_cbranch_execz .LBB10_31
; %bb.19:
	v_cmp_ne_u32_e32 vcc_lo, -1, v4
	s_mov_b64 s[0:1], src_shared_base
	s_cmp_lt_u32 s9, 64
	v_cndmask_b32_e64 v2, 0, s1, vcc_lo
	v_cndmask_b32_e32 v1, 0, v4, vcc_lo
	s_cbranch_scc1 .LBB10_21
; %bb.20:
	v_lshlrev_b32_e32 v5, 2, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v5, 0, v5, 0x80
	v_cmp_ne_u32_e32 vcc_lo, -1, v5
	v_cndmask_b32_e32 v5, 0, v5, vcc_lo
	v_cndmask_b32_e64 v6, 0, s1, vcc_lo
	flat_load_b32 v5, v[5:6] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_nc_u32_e32 v3, v5, v3
	flat_store_b32 v[1:2], v3 dlc
	s_waitcnt_vscnt null, 0x0
.LBB10_21:
	s_cmp_lt_u32 s9, 32
	s_cbranch_scc1 .LBB10_23
; %bb.22:
	v_add_nc_u32_e32 v5, 64, v4
	s_mov_b64 s[0:1], src_shared_base
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v5
	v_cndmask_b32_e32 v5, 0, v5, vcc_lo
	v_cndmask_b32_e64 v6, 0, s1, vcc_lo
	flat_load_b32 v5, v[5:6] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_nc_u32_e32 v3, v5, v3
	flat_store_b32 v[1:2], v3 dlc
	s_waitcnt_vscnt null, 0x0
.LBB10_23:
	s_cmp_lt_u32 s9, 16
	s_cbranch_scc1 .LBB10_25
; %bb.24:
	v_add_nc_u32_e32 v5, 32, v4
	s_mov_b64 s[0:1], src_shared_base
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v5
	v_cndmask_b32_e32 v5, 0, v5, vcc_lo
	v_cndmask_b32_e64 v6, 0, s1, vcc_lo
	flat_load_b32 v5, v[5:6] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_nc_u32_e32 v3, v5, v3
	flat_store_b32 v[1:2], v3 dlc
	s_waitcnt_vscnt null, 0x0
.LBB10_25:
	s_cmp_lt_u32 s9, 8
	s_cbranch_scc1 .LBB10_27
; %bb.26:
	v_add_nc_u32_e32 v5, 16, v4
	s_mov_b64 s[0:1], src_shared_base
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v5
	v_cndmask_b32_e32 v5, 0, v5, vcc_lo
	v_cndmask_b32_e64 v6, 0, s1, vcc_lo
	flat_load_b32 v5, v[5:6] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_nc_u32_e32 v3, v5, v3
	flat_store_b32 v[1:2], v3 dlc
	s_waitcnt_vscnt null, 0x0
.LBB10_27:
	s_cmp_lt_u32 s9, 4
	s_cbranch_scc1 .LBB10_29
; %bb.28:
	v_add_nc_u32_e32 v5, 8, v4
	s_mov_b64 s[0:1], src_shared_base
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v5
	v_cndmask_b32_e32 v5, 0, v5, vcc_lo
	v_cndmask_b32_e64 v6, 0, s1, vcc_lo
	flat_load_b32 v5, v[5:6] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_nc_u32_e32 v3, v5, v3
	flat_store_b32 v[1:2], v3 dlc
	s_waitcnt_vscnt null, 0x0
.LBB10_29:
	s_cmp_lt_u32 s9, 2
	s_cbranch_scc1 .LBB10_31
; %bb.30:
	v_add_nc_u32_e32 v4, 4, v4
	s_mov_b64 s[0:1], src_shared_base
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v4
	v_cndmask_b32_e32 v4, 0, v4, vcc_lo
	v_cndmask_b32_e64 v5, 0, s1, vcc_lo
	flat_load_b32 v4, v[4:5] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_nc_u32_e32 v3, v4, v3
	flat_store_b32 v[1:2], v3 dlc
	s_waitcnt_vscnt null, 0x0
.LBB10_31:                              ; %Flow17
	s_or_b32 exec_lo, exec_lo, s3
	s_mov_b32 s3, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB10_33
; %bb.32:
	v_mov_b32_e32 v0, 0
	s_lshl_b64 s[0:1], s[2:3], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s0, s6, s0
	s_addc_u32 s1, s7, s1
	ds_load_b32 v1, v0
	s_waitcnt lgkmcnt(0)
	global_store_b32 v0, v1, s[0:1]
.LBB10_33:                              ; %_Z7reduce6IiEvPT_S1_jjb.exit
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel reduce6_i
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 7
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end10:
	.size	reduce6_i, .Lfunc_end10-reduce6_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 984
; NumSgprs: 18
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	reduce6_ui              ; -- Begin function reduce6_ui
	.globl	reduce6_ui
	.p2align	8
	.type	reduce6_ui,@function
reduce6_ui:                             ; @reduce6_ui
; %bb.0:
	s_load_b256 s[4:11], s[0:1], 0x0
	v_mov_b32_e32 v3, 0
	s_mov_b32 s2, s15
	s_mov_b32 s3, exec_lo
	s_waitcnt lgkmcnt(0)
	s_lshl_b32 s12, s9, 1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s11, s12, s15
	v_add_nc_u32_e32 v1, s11, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e64 s8, v1
	s_cbranch_execz .LBB11_6
; %bb.1:                                ; %.lr.ph.i.preheader
	s_load_b32 s13, s[0:1], 0x20
	s_bitcmp1_b32 s10, 0
	v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v2, 0
	s_cselect_b32 s0, -1, 0
	s_lshl_b32 s1, s2, 1
	v_mov_b32_e32 v4, v0
	s_or_b32 s1, s1, 1
	s_mov_b32 s10, 0
	s_mul_i32 s1, s9, s1
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s12, s13, s12
.LBB11_2:                               ; %.lr.ph.i
                                        ; =>This Inner Loop Header: Depth=1
	v_add_nc_u32_e32 v1, s11, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[5:6], 2, v[1:2]
	v_add_nc_u32_e32 v1, s1, v4
	v_add_co_u32 v5, vcc_lo, s4, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
	v_cmp_gt_u32_e32 vcc_lo, s8, v1
	global_load_b32 v5, v[5:6], off
	s_or_b32 s14, vcc_lo, s0
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v3, v5, v3
	s_and_saveexec_b32 s13, s14
	s_cbranch_execz .LBB11_4
; %bb.3:                                ;   in Loop: Header=BB11_2 Depth=1
	v_lshlrev_b64 v[5:6], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v5, vcc_lo, s4, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
	global_load_b32 v1, v[5:6], off
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v3, v1, v3
.LBB11_4:                               ;   in Loop: Header=BB11_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s13
	v_add_nc_u32_e32 v4, s12, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v1, s11, v4
	v_cmp_le_u32_e32 vcc_lo, s8, v1
	s_or_b32 s10, vcc_lo, s10
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s10
	s_cbranch_execnz .LBB11_2
; %bb.5:                                ; %Flow21
	s_or_b32 exec_lo, exec_lo, s10
.LBB11_6:                               ; %Flow22
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s3
	v_lshl_add_u32 v4, v0, 2, 0
	s_cmpk_lt_u32 s9, 0x200
	ds_store_b32 v4, v3
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB11_10
; %bb.7:
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 0x100, v0
	s_cbranch_execz .LBB11_9
; %bb.8:
	ds_load_b32 v1, v4 offset:1024
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v3, v1, v3
	ds_store_b32 v4, v3
.LBB11_9:
	s_or_b32 exec_lo, exec_lo, s0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
.LBB11_10:
	s_cmpk_lt_u32 s9, 0x100
	s_cbranch_scc1 .LBB11_14
; %bb.11:
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 0x80, v0
	s_cbranch_execz .LBB11_13
; %bb.12:
	ds_load_b32 v1, v4 offset:512
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v3, v1, v3
	ds_store_b32 v4, v3
.LBB11_13:
	s_or_b32 exec_lo, exec_lo, s0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
.LBB11_14:
	s_cmpk_lt_u32 s9, 0x80
	s_cbranch_scc1 .LBB11_18
; %bb.15:
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 64, v0
	s_cbranch_execz .LBB11_17
; %bb.16:
	ds_load_b32 v1, v4 offset:256
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v3, v1, v3
	ds_store_b32 v4, v3
.LBB11_17:
	s_or_b32 exec_lo, exec_lo, s0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
.LBB11_18:
	s_mov_b32 s3, exec_lo
	v_cmpx_gt_u32_e32 32, v0
	s_cbranch_execz .LBB11_31
; %bb.19:
	v_cmp_ne_u32_e32 vcc_lo, -1, v4
	s_mov_b64 s[0:1], src_shared_base
	s_cmp_lt_u32 s9, 64
	v_cndmask_b32_e64 v2, 0, s1, vcc_lo
	v_cndmask_b32_e32 v1, 0, v4, vcc_lo
	s_cbranch_scc1 .LBB11_21
; %bb.20:
	v_lshlrev_b32_e32 v5, 2, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v5, 0, v5, 0x80
	v_cmp_ne_u32_e32 vcc_lo, -1, v5
	v_cndmask_b32_e32 v5, 0, v5, vcc_lo
	v_cndmask_b32_e64 v6, 0, s1, vcc_lo
	flat_load_b32 v5, v[5:6] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_nc_u32_e32 v3, v5, v3
	flat_store_b32 v[1:2], v3 dlc
	s_waitcnt_vscnt null, 0x0
.LBB11_21:
	s_cmp_lt_u32 s9, 32
	s_cbranch_scc1 .LBB11_23
; %bb.22:
	v_add_nc_u32_e32 v5, 64, v4
	s_mov_b64 s[0:1], src_shared_base
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v5
	v_cndmask_b32_e32 v5, 0, v5, vcc_lo
	v_cndmask_b32_e64 v6, 0, s1, vcc_lo
	flat_load_b32 v5, v[5:6] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_nc_u32_e32 v3, v5, v3
	flat_store_b32 v[1:2], v3 dlc
	s_waitcnt_vscnt null, 0x0
.LBB11_23:
	s_cmp_lt_u32 s9, 16
	s_cbranch_scc1 .LBB11_25
; %bb.24:
	v_add_nc_u32_e32 v5, 32, v4
	s_mov_b64 s[0:1], src_shared_base
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v5
	v_cndmask_b32_e32 v5, 0, v5, vcc_lo
	v_cndmask_b32_e64 v6, 0, s1, vcc_lo
	flat_load_b32 v5, v[5:6] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_nc_u32_e32 v3, v5, v3
	flat_store_b32 v[1:2], v3 dlc
	s_waitcnt_vscnt null, 0x0
.LBB11_25:
	s_cmp_lt_u32 s9, 8
	s_cbranch_scc1 .LBB11_27
; %bb.26:
	v_add_nc_u32_e32 v5, 16, v4
	s_mov_b64 s[0:1], src_shared_base
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v5
	v_cndmask_b32_e32 v5, 0, v5, vcc_lo
	v_cndmask_b32_e64 v6, 0, s1, vcc_lo
	flat_load_b32 v5, v[5:6] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_nc_u32_e32 v3, v5, v3
	flat_store_b32 v[1:2], v3 dlc
	s_waitcnt_vscnt null, 0x0
.LBB11_27:
	s_cmp_lt_u32 s9, 4
	s_cbranch_scc1 .LBB11_29
; %bb.28:
	v_add_nc_u32_e32 v5, 8, v4
	s_mov_b64 s[0:1], src_shared_base
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v5
	v_cndmask_b32_e32 v5, 0, v5, vcc_lo
	v_cndmask_b32_e64 v6, 0, s1, vcc_lo
	flat_load_b32 v5, v[5:6] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_nc_u32_e32 v3, v5, v3
	flat_store_b32 v[1:2], v3 dlc
	s_waitcnt_vscnt null, 0x0
.LBB11_29:
	s_cmp_lt_u32 s9, 2
	s_cbranch_scc1 .LBB11_31
; %bb.30:
	v_add_nc_u32_e32 v4, 4, v4
	s_mov_b64 s[0:1], src_shared_base
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v4
	v_cndmask_b32_e32 v4, 0, v4, vcc_lo
	v_cndmask_b32_e64 v5, 0, s1, vcc_lo
	flat_load_b32 v4, v[4:5] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_nc_u32_e32 v3, v4, v3
	flat_store_b32 v[1:2], v3 dlc
	s_waitcnt_vscnt null, 0x0
.LBB11_31:                              ; %Flow17
	s_or_b32 exec_lo, exec_lo, s3
	s_mov_b32 s3, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB11_33
; %bb.32:
	v_mov_b32_e32 v0, 0
	s_lshl_b64 s[0:1], s[2:3], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s0, s6, s0
	s_addc_u32 s1, s7, s1
	ds_load_b32 v1, v0
	s_waitcnt lgkmcnt(0)
	global_store_b32 v0, v1, s[0:1]
.LBB11_33:                              ; %_Z7reduce6IjEvPT_S1_jjb.exit
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel reduce6_ui
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 7
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end11:
	.size	reduce6_ui, .Lfunc_end11-reduce6_ui
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 984
; NumSgprs: 18
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	reduce6_f               ; -- Begin function reduce6_f
	.globl	reduce6_f
	.p2align	8
	.type	reduce6_f,@function
reduce6_f:                              ; @reduce6_f
; %bb.0:
	s_load_b256 s[4:11], s[0:1], 0x0
	v_mov_b32_e32 v3, 0
	s_mov_b32 s2, s15
	s_mov_b32 s3, exec_lo
	s_waitcnt lgkmcnt(0)
	s_lshl_b32 s12, s9, 1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s11, s12, s15
	v_add_nc_u32_e32 v1, s11, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e64 s8, v1
	s_cbranch_execz .LBB12_6
; %bb.1:                                ; %.lr.ph.i.preheader
	s_load_b32 s13, s[0:1], 0x20
	s_bitcmp1_b32 s10, 0
	v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v3, 0
	s_cselect_b32 s0, -1, 0
	s_lshl_b32 s1, s2, 1
	v_mov_b32_e32 v4, v0
	s_or_b32 s1, s1, 1
	s_mov_b32 s10, 0
	s_mul_i32 s1, s9, s1
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s12, s13, s12
.LBB12_2:                               ; %.lr.ph.i
                                        ; =>This Inner Loop Header: Depth=1
	v_add_nc_u32_e32 v1, s11, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[5:6], 2, v[1:2]
	v_add_nc_u32_e32 v1, s1, v4
	v_add_co_u32 v5, vcc_lo, s4, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
	v_cmp_gt_u32_e32 vcc_lo, s8, v1
	global_load_b32 v5, v[5:6], off
	s_or_b32 s14, vcc_lo, s0
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v3, v3, v5
	s_and_saveexec_b32 s13, s14
	s_cbranch_execz .LBB12_4
; %bb.3:                                ;   in Loop: Header=BB12_2 Depth=1
	v_lshlrev_b64 v[5:6], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v5, vcc_lo, s4, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
	global_load_b32 v1, v[5:6], off
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v3, v3, v1
.LBB12_4:                               ;   in Loop: Header=BB12_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s13
	v_add_nc_u32_e32 v4, s12, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v1, s11, v4
	v_cmp_le_u32_e32 vcc_lo, s8, v1
	s_or_b32 s10, vcc_lo, s10
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s10
	s_cbranch_execnz .LBB12_2
; %bb.5:                                ; %Flow21
	s_or_b32 exec_lo, exec_lo, s10
.LBB12_6:                               ; %Flow22
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s3
	v_lshl_add_u32 v4, v0, 2, 0
	s_cmpk_lt_u32 s9, 0x200
	ds_store_b32 v4, v3
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB12_10
; %bb.7:
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 0x100, v0
	s_cbranch_execz .LBB12_9
; %bb.8:
	ds_load_b32 v1, v4 offset:1024
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v3, v3, v1
	ds_store_b32 v4, v3
.LBB12_9:
	s_or_b32 exec_lo, exec_lo, s0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
.LBB12_10:
	s_cmpk_lt_u32 s9, 0x100
	s_cbranch_scc1 .LBB12_14
; %bb.11:
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 0x80, v0
	s_cbranch_execz .LBB12_13
; %bb.12:
	ds_load_b32 v1, v4 offset:512
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v3, v3, v1
	ds_store_b32 v4, v3
.LBB12_13:
	s_or_b32 exec_lo, exec_lo, s0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
.LBB12_14:
	s_cmpk_lt_u32 s9, 0x80
	s_cbranch_scc1 .LBB12_18
; %bb.15:
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 64, v0
	s_cbranch_execz .LBB12_17
; %bb.16:
	ds_load_b32 v1, v4 offset:256
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v3, v3, v1
	ds_store_b32 v4, v3
.LBB12_17:
	s_or_b32 exec_lo, exec_lo, s0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
.LBB12_18:
	s_mov_b32 s3, exec_lo
	v_cmpx_gt_u32_e32 32, v0
	s_cbranch_execz .LBB12_31
; %bb.19:
	v_cmp_ne_u32_e32 vcc_lo, -1, v4
	s_mov_b64 s[0:1], src_shared_base
	s_cmp_lt_u32 s9, 64
	v_cndmask_b32_e64 v2, 0, s1, vcc_lo
	v_cndmask_b32_e32 v1, 0, v4, vcc_lo
	s_cbranch_scc1 .LBB12_21
; %bb.20:
	v_lshlrev_b32_e32 v5, 2, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v5, 0, v5, 0x80
	v_cmp_ne_u32_e32 vcc_lo, -1, v5
	v_cndmask_b32_e32 v5, 0, v5, vcc_lo
	v_cndmask_b32_e64 v6, 0, s1, vcc_lo
	flat_load_b32 v5, v[5:6] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f32_e32 v3, v3, v5
	flat_store_b32 v[1:2], v3 dlc
	s_waitcnt_vscnt null, 0x0
.LBB12_21:
	s_cmp_lt_u32 s9, 32
	s_cbranch_scc1 .LBB12_23
; %bb.22:
	v_add_nc_u32_e32 v5, 64, v4
	s_mov_b64 s[0:1], src_shared_base
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v5
	v_cndmask_b32_e32 v5, 0, v5, vcc_lo
	v_cndmask_b32_e64 v6, 0, s1, vcc_lo
	flat_load_b32 v5, v[5:6] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f32_e32 v3, v3, v5
	flat_store_b32 v[1:2], v3 dlc
	s_waitcnt_vscnt null, 0x0
.LBB12_23:
	s_cmp_lt_u32 s9, 16
	s_cbranch_scc1 .LBB12_25
; %bb.24:
	v_add_nc_u32_e32 v5, 32, v4
	s_mov_b64 s[0:1], src_shared_base
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v5
	v_cndmask_b32_e32 v5, 0, v5, vcc_lo
	v_cndmask_b32_e64 v6, 0, s1, vcc_lo
	flat_load_b32 v5, v[5:6] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f32_e32 v3, v3, v5
	flat_store_b32 v[1:2], v3 dlc
	s_waitcnt_vscnt null, 0x0
.LBB12_25:
	s_cmp_lt_u32 s9, 8
	s_cbranch_scc1 .LBB12_27
; %bb.26:
	v_add_nc_u32_e32 v5, 16, v4
	s_mov_b64 s[0:1], src_shared_base
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v5
	v_cndmask_b32_e32 v5, 0, v5, vcc_lo
	v_cndmask_b32_e64 v6, 0, s1, vcc_lo
	flat_load_b32 v5, v[5:6] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f32_e32 v3, v3, v5
	flat_store_b32 v[1:2], v3 dlc
	s_waitcnt_vscnt null, 0x0
.LBB12_27:
	s_cmp_lt_u32 s9, 4
	s_cbranch_scc1 .LBB12_29
; %bb.28:
	v_add_nc_u32_e32 v5, 8, v4
	s_mov_b64 s[0:1], src_shared_base
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v5
	v_cndmask_b32_e32 v5, 0, v5, vcc_lo
	v_cndmask_b32_e64 v6, 0, s1, vcc_lo
	flat_load_b32 v5, v[5:6] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f32_e32 v3, v3, v5
	flat_store_b32 v[1:2], v3 dlc
	s_waitcnt_vscnt null, 0x0
.LBB12_29:
	s_cmp_lt_u32 s9, 2
	s_cbranch_scc1 .LBB12_31
; %bb.30:
	v_add_nc_u32_e32 v4, 4, v4
	s_mov_b64 s[0:1], src_shared_base
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v4
	v_cndmask_b32_e32 v4, 0, v4, vcc_lo
	v_cndmask_b32_e64 v5, 0, s1, vcc_lo
	flat_load_b32 v4, v[4:5] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f32_e32 v3, v3, v4
	flat_store_b32 v[1:2], v3 dlc
	s_waitcnt_vscnt null, 0x0
.LBB12_31:                              ; %Flow17
	s_or_b32 exec_lo, exec_lo, s3
	s_mov_b32 s3, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB12_33
; %bb.32:
	v_mov_b32_e32 v0, 0
	s_lshl_b64 s[0:1], s[2:3], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s0, s6, s0
	s_addc_u32 s1, s7, s1
	ds_load_b32 v1, v0
	s_waitcnt lgkmcnt(0)
	global_store_b32 v0, v1, s[0:1]
.LBB12_33:                              ; %_Z7reduce6IfEvPT_S1_jjb.exit
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel reduce6_f
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 7
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end12:
	.size	reduce6_f, .Lfunc_end12-reduce6_f
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 984
; NumSgprs: 18
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	reduce6_d               ; -- Begin function reduce6_d
	.globl	reduce6_d
	.p2align	8
	.type	reduce6_d,@function
reduce6_d:                              ; @reduce6_d
; %bb.0:
	s_load_b256 s[4:11], s[0:1], 0x0
	v_mov_b32_e32 v1, 0
	s_mov_b32 s2, s15
	s_waitcnt lgkmcnt(0)
	s_mov_b32 s11, exec_lo
	v_mov_b32_e32 v2, 0
	s_lshl_b32 s12, s9, 1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s3, s12, s15
	v_add_nc_u32_e32 v3, s3, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e64 s8, v3
	s_cbranch_execz .LBB13_6
; %bb.1:                                ; %.lr.ph.i.preheader
	s_load_b32 s13, s[0:1], 0x20
	s_bitcmp1_b32 s10, 0
	v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v4, 0
	s_cselect_b32 s0, -1, 0
	s_lshl_b32 s1, s2, 1
	v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v5, v0
	s_or_b32 s1, s1, 1
	s_mov_b32 s10, 0
	s_mul_i32 s1, s9, s1
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s12, s13, s12
.LBB13_2:                               ; %.lr.ph.i
                                        ; =>This Inner Loop Header: Depth=1
	v_add_nc_u32_e32 v3, s3, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[6:7], 3, v[3:4]
	v_add_nc_u32_e32 v3, s1, v5
	v_add_co_u32 v6, vcc_lo, s4, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
	v_cmp_gt_u32_e32 vcc_lo, s8, v3
	global_load_b64 v[6:7], v[6:7], off
	s_or_b32 s14, vcc_lo, s0
	s_waitcnt vmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[6:7]
	s_and_saveexec_b32 s13, s14
	s_cbranch_execz .LBB13_4
; %bb.3:                                ;   in Loop: Header=BB13_2 Depth=1
	v_lshlrev_b64 v[6:7], 3, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v6, vcc_lo, s4, v6
	v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
	global_load_b64 v[6:7], v[6:7], off
	s_waitcnt vmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[6:7]
.LBB13_4:                               ;   in Loop: Header=BB13_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s13
	v_add_nc_u32_e32 v5, s12, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v3, s3, v5
	v_cmp_le_u32_e32 vcc_lo, s8, v3
	s_or_b32 s10, vcc_lo, s10
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s10
	s_cbranch_execnz .LBB13_2
; %bb.5:                                ; %Flow21
	s_or_b32 exec_lo, exec_lo, s10
.LBB13_6:                               ; %Flow22
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s11
	v_lshl_add_u32 v5, v0, 3, 0
	s_cmpk_lt_u32 s9, 0x200
	ds_store_b64 v5, v[1:2]
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB13_10
; %bb.7:
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 0x100, v0
	s_cbranch_execz .LBB13_9
; %bb.8:
	ds_load_b64 v[3:4], v5 offset:2048
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[3:4]
	ds_store_b64 v5, v[1:2]
.LBB13_9:
	s_or_b32 exec_lo, exec_lo, s0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
.LBB13_10:
	s_cmpk_lt_u32 s9, 0x100
	s_cbranch_scc1 .LBB13_14
; %bb.11:
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 0x80, v0
	s_cbranch_execz .LBB13_13
; %bb.12:
	ds_load_b64 v[3:4], v5 offset:1024
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[3:4]
	ds_store_b64 v5, v[1:2]
.LBB13_13:
	s_or_b32 exec_lo, exec_lo, s0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
.LBB13_14:
	s_cmpk_lt_u32 s9, 0x80
	s_cbranch_scc1 .LBB13_18
; %bb.15:
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 64, v0
	s_cbranch_execz .LBB13_17
; %bb.16:
	ds_load_b64 v[3:4], v5 offset:512
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[3:4]
	ds_store_b64 v5, v[1:2]
.LBB13_17:
	s_or_b32 exec_lo, exec_lo, s0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
.LBB13_18:
	s_mov_b32 s3, exec_lo
	v_cmpx_gt_u32_e32 32, v0
	s_cbranch_execz .LBB13_31
; %bb.19:
	v_cmp_ne_u32_e32 vcc_lo, -1, v5
	s_mov_b64 s[0:1], src_shared_base
	s_cmp_lt_u32 s9, 64
	v_cndmask_b32_e64 v4, 0, s1, vcc_lo
	v_cndmask_b32_e32 v3, 0, v5, vcc_lo
	s_cbranch_scc1 .LBB13_21
; %bb.20:
	v_lshlrev_b32_e32 v6, 3, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v6, 0, v6, 0x100
	v_cmp_ne_u32_e32 vcc_lo, -1, v6
	v_cndmask_b32_e32 v6, 0, v6, vcc_lo
	v_cndmask_b32_e64 v7, 0, s1, vcc_lo
	flat_load_b64 v[6:7], v[6:7] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[6:7]
	flat_store_b64 v[3:4], v[1:2] dlc
	s_waitcnt_vscnt null, 0x0
.LBB13_21:
	s_cmp_lt_u32 s9, 32
	s_cbranch_scc1 .LBB13_23
; %bb.22:
	v_add_nc_u32_e32 v6, 0x80, v5
	s_mov_b64 s[0:1], src_shared_base
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v6
	v_cndmask_b32_e32 v6, 0, v6, vcc_lo
	v_cndmask_b32_e64 v7, 0, s1, vcc_lo
	flat_load_b64 v[6:7], v[6:7] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[6:7]
	flat_store_b64 v[3:4], v[1:2] dlc
	s_waitcnt_vscnt null, 0x0
.LBB13_23:
	s_cmp_lt_u32 s9, 16
	s_cbranch_scc1 .LBB13_25
; %bb.24:
	v_add_nc_u32_e32 v6, 64, v5
	s_mov_b64 s[0:1], src_shared_base
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v6
	v_cndmask_b32_e32 v6, 0, v6, vcc_lo
	v_cndmask_b32_e64 v7, 0, s1, vcc_lo
	flat_load_b64 v[6:7], v[6:7] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[6:7]
	flat_store_b64 v[3:4], v[1:2] dlc
	s_waitcnt_vscnt null, 0x0
.LBB13_25:
	s_cmp_lt_u32 s9, 8
	s_cbranch_scc1 .LBB13_27
; %bb.26:
	v_add_nc_u32_e32 v6, 32, v5
	s_mov_b64 s[0:1], src_shared_base
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v6
	v_cndmask_b32_e32 v6, 0, v6, vcc_lo
	v_cndmask_b32_e64 v7, 0, s1, vcc_lo
	flat_load_b64 v[6:7], v[6:7] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[6:7]
	flat_store_b64 v[3:4], v[1:2] dlc
	s_waitcnt_vscnt null, 0x0
.LBB13_27:
	s_cmp_lt_u32 s9, 4
	s_cbranch_scc1 .LBB13_29
; %bb.28:
	v_add_nc_u32_e32 v6, 16, v5
	s_mov_b64 s[0:1], src_shared_base
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v6
	v_cndmask_b32_e32 v6, 0, v6, vcc_lo
	v_cndmask_b32_e64 v7, 0, s1, vcc_lo
	flat_load_b64 v[6:7], v[6:7] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[6:7]
	flat_store_b64 v[3:4], v[1:2] dlc
	s_waitcnt_vscnt null, 0x0
.LBB13_29:
	s_cmp_lt_u32 s9, 2
	s_cbranch_scc1 .LBB13_31
; %bb.30:
	v_add_nc_u32_e32 v5, 8, v5
	s_mov_b64 s[0:1], src_shared_base
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v5
	v_cndmask_b32_e32 v5, 0, v5, vcc_lo
	v_cndmask_b32_e64 v6, 0, s1, vcc_lo
	flat_load_b64 v[5:6], v[5:6] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[5:6]
	flat_store_b64 v[3:4], v[1:2] dlc
	s_waitcnt_vscnt null, 0x0
.LBB13_31:                              ; %Flow17
	s_or_b32 exec_lo, exec_lo, s3
	s_mov_b32 s3, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB13_33
; %bb.32:
	v_mov_b32_e32 v2, 0
	s_lshl_b64 s[0:1], s[2:3], 3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s0, s6, s0
	s_addc_u32 s1, s7, s1
	ds_load_b64 v[0:1], v2
	s_waitcnt lgkmcnt(0)
	global_store_b64 v2, v[0:1], s[0:1]
.LBB13_33:                              ; %_Z7reduce6IdEvPT_S1_jjb.exit
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel reduce6_d
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 8
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end13:
	.size	reduce6_d, .Lfunc_end13-reduce6_d
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1040
; NumSgprs: 18
; NumVgprs: 8
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 8
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __smem
	.addrsig_sym __smem_d
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	.amdgpu_metadata
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        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         152
        .size:           4
        .value_kind:     hidden_dynamic_lds_size
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           reduce6_d
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         reduce6_d.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     8
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
