#include "includes.h"
__global__ static void gaussdensity_direct_tex(int natoms, const float4 *xyzr, const float4 *colors, float gridspacing, unsigned int z, float *densitygrid, float3 *voltexmap, float invisovalue) {
unsigned int xindex  = (blockIdx.x * blockDim.x) * DUNROLLX + threadIdx.x;
unsigned int yindex  = (blockIdx.y * blockDim.y) + threadIdx.y;
unsigned int zindex  = (blockIdx.z * blockDim.z) + threadIdx.z;
unsigned int outaddr =
((gridDim.x * blockDim.x) * DUNROLLX) * (gridDim.y * blockDim.y) * zindex +
((gridDim.x * blockDim.x) * DUNROLLX) * yindex + xindex;
zindex += z;

float coorx = gridspacing * xindex;
float coory = gridspacing * yindex;
float coorz = gridspacing * zindex;

float densityvalx1=0.0f;
float densityvalx2=0.0f;
float3 densitycolx1;
densitycolx1=make_float3(0.0f, 0.0f, 0.0f);
float3 densitycolx2=densitycolx1;

#if DUNROLLX >= 4
float densityvalx3=0.0f;
float densityvalx4=0.0f;
float3 densitycolx3=densitycolx1;
float3 densitycolx4=densitycolx1;
#endif
#if DUNROLLX >= 8
float densityvalx5=0.0f;
float densityvalx6=0.0f;
float densityvalx7=0.0f;
float densityvalx8=0.0f;

float3 densitycolx5=densitycolx1;
float3 densitycolx6=densitycolx1;
float3 densitycolx7=densitycolx1;
float3 densitycolx8=densitycolx1;
#endif

float gridspacing_coalesce = gridspacing * DBLOCKSZX;

int atomid;
for (atomid=0; atomid<natoms; atomid++) {
float4 atom = xyzr[atomid];
float4 color = colors[atomid];

float dy = coory - atom.y;
float dz = coorz - atom.z;
float dyz2 = dy*dy + dz*dz;

float dx1 = coorx - atom.x;
float r21 = (dx1*dx1 + dyz2) * atom.w;
float tmp1 = exp2f(-r21);
densityvalx1 += tmp1;
tmp1 *= invisovalue;
densitycolx1.x += tmp1 * color.x;
densitycolx1.y += tmp1 * color.y;
densitycolx1.z += tmp1 * color.z;

float dx2 = dx1 + gridspacing_coalesce;
float r22 = (dx2*dx2 + dyz2) * atom.w;
float tmp2 = exp2f(-r22);
densityvalx2 += tmp2;
tmp2 *= invisovalue;
densitycolx2.x += tmp2 * color.x;
densitycolx2.y += tmp2 * color.y;
densitycolx2.z += tmp2 * color.z;

#if DUNROLLX >= 4
float dx3 = dx2 + gridspacing_coalesce;
float r23 = (dx3*dx3 + dyz2) * atom.w;
float tmp3 = exp2f(-r23);
densityvalx3 += tmp3;
tmp3 *= invisovalue;
densitycolx3.x += tmp3 * color.x;
densitycolx3.y += tmp3 * color.y;
densitycolx3.z += tmp3 * color.z;

float dx4 = dx3 + gridspacing_coalesce;
float r24 = (dx4*dx4 + dyz2) * atom.w;
float tmp4 = exp2f(-r24);
densityvalx4 += tmp4;
tmp4 *= invisovalue;
densitycolx4.x += tmp4 * color.x;
densitycolx4.y += tmp4 * color.y;
densitycolx4.z += tmp4 * color.z;
#endif
#if DUNROLLX >= 8
float dx5 = dx4 + gridspacing_coalesce;
float r25 = (dx5*dx5 + dyz2) * atom.w;
float tmp5 = exp2f(-r25);
densityvalx5 += tmp5;
tmp5 *= invisovalue;
densitycolx5.x += tmp5 * color.x;
densitycolx5.y += tmp5 * color.y;
densitycolx5.z += tmp5 * color.z;

float dx6 = dx5 + gridspacing_coalesce;
float r26 = (dx6*dx6 + dyz2) * atom.w;
float tmp6 = exp2f(-r26);
densityvalx6 += tmp6;
tmp6 *= invisovalue;
densitycolx6.x += tmp6 * color.x;
densitycolx6.y += tmp6 * color.y;
densitycolx6.z += tmp6 * color.z;

float dx7 = dx6 + gridspacing_coalesce;
float r27 = (dx7*dx7 + dyz2) * atom.w;
float tmp7 = exp2f(-r27);
densityvalx7 += tmp7;
tmp7 *= invisovalue;
densitycolx7.x += tmp7 * color.x;
densitycolx7.y += tmp7 * color.y;
densitycolx7.z += tmp7 * color.z;

float dx8 = dx7 + gridspacing_coalesce;
float r28 = (dx8*dx8 + dyz2) * atom.w;
float tmp8 = exp2f(-r28);
densityvalx8 += tmp8;
tmp8 *= invisovalue;
densitycolx8.x += tmp8 * color.x;
densitycolx8.y += tmp8 * color.y;
densitycolx8.z += tmp8 * color.z;
#endif
}

densitygrid[outaddr             ] += densityvalx1;
voltexmap[outaddr             ].x += densitycolx1.x;
voltexmap[outaddr             ].y += densitycolx1.y;
voltexmap[outaddr             ].z += densitycolx1.z;

densitygrid[outaddr+1*DBLOCKSZX] += densityvalx2;
voltexmap[outaddr+1*DBLOCKSZX].x += densitycolx2.x;
voltexmap[outaddr+1*DBLOCKSZX].y += densitycolx2.y;
voltexmap[outaddr+1*DBLOCKSZX].z += densitycolx2.z;

#if DUNROLLX >= 4
densitygrid[outaddr+2*DBLOCKSZX] += densityvalx3;
voltexmap[outaddr+2*DBLOCKSZX].x += densitycolx3.x;
voltexmap[outaddr+2*DBLOCKSZX].y += densitycolx3.y;
voltexmap[outaddr+2*DBLOCKSZX].z += densitycolx3.z;

densitygrid[outaddr+3*DBLOCKSZX] += densityvalx4;
voltexmap[outaddr+3*DBLOCKSZX].x += densitycolx4.x;
voltexmap[outaddr+3*DBLOCKSZX].y += densitycolx4.y;
voltexmap[outaddr+3*DBLOCKSZX].z += densitycolx4.z;
#endif
#if DUNROLLX >= 8
densitygrid[outaddr+4*DBLOCKSZX] += densityvalx5;
voltexmap[outaddr+4*DBLOCKSZX].x += densitycolx5.x;
voltexmap[outaddr+4*DBLOCKSZX].y += densitycolx5.y;
voltexmap[outaddr+4*DBLOCKSZX].z += densitycolx5.z;

densitygrid[outaddr+5*DBLOCKSZX] += densityvalx6;
voltexmap[outaddr+5*DBLOCKSZX].x += densitycolx6.x;
voltexmap[outaddr+5*DBLOCKSZX].y += densitycolx6.y;
voltexmap[outaddr+5*DBLOCKSZX].z += densitycolx6.z;

densitygrid[outaddr+6*DBLOCKSZX] += densityvalx7;
voltexmap[outaddr+6*DBLOCKSZX].x += densitycolx7.x;
voltexmap[outaddr+6*DBLOCKSZX].y += densitycolx7.y;
voltexmap[outaddr+6*DBLOCKSZX].z += densitycolx7.z;

densitygrid[outaddr+7*DBLOCKSZX] += densityvalx8;
voltexmap[outaddr+7*DBLOCKSZX].x += densitycolx8.x;
voltexmap[outaddr+7*DBLOCKSZX].y += densitycolx8.y;
voltexmap[outaddr+7*DBLOCKSZX].z += densitycolx8.z;
#endif
}
	.file	"tmpxft_002d8da0_00000000-6_gaussdensity_direct_tex.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2010:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2010:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.type	_ZL23gaussdensity_direct_texiPK6float4S1_fjPfP6float3f, @function
_ZL23gaussdensity_direct_texiPK6float4S1_fjPfP6float3f:
.LFB2033:
	.cfi_startproc
	endbr64
	subq	$200, %rsp
	.cfi_def_cfa_offset 208
	movq	%fs:40, %rax
	movq	%rax, 184(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	%edi, 8(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rax, 120(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	20(%rsp), %rax
	movq	%rsi, 24(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 32(%rsp)
	leaq	56(%rsp), %rdx
	movl	%ecx, 16(%rsp)
	leaq	64(%rsp), %rcx
	movq	%rax, 176(%rsp)
	movabsq	$4294967297, %rax
	movq	%r8, 40(%rsp)
	movq	%r9, 48(%rsp)
	movq	%rax, 72(%rsp)
	movl	$1, 80(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	movss	%xmm0, 12(%rsp)
	movss	%xmm1, 20(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	64(%rsp)
	.cfi_def_cfa_offset 216
	leaq	_ZL23gaussdensity_direct_texiPK6float4S1_fjPfP6float3f(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 224
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 216
	popq	%rdx
	.cfi_def_cfa_offset 208
.L2:
	movq	184(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$200, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2033:
	.size	_ZL23gaussdensity_direct_texiPK6float4S1_fjPfP6float3f, .-_ZL23gaussdensity_direct_texiPK6float4S1_fjPfP6float3f
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z23gaussdensity_direct_texiPK6float4S1_fjPfP6float3f"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2035:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_ZL23gaussdensity_direct_texiPK6float4S1_fjPfP6float3f(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2035:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include "includes.h"
__global__ static void gaussdensity_direct_tex(int natoms, const float4 *xyzr, const float4 *colors, float gridspacing, unsigned int z, float *densitygrid, float3 *voltexmap, float invisovalue) {
unsigned int xindex  = (blockIdx.x * blockDim.x) * DUNROLLX + threadIdx.x;
unsigned int yindex  = (blockIdx.y * blockDim.y) + threadIdx.y;
unsigned int zindex  = (blockIdx.z * blockDim.z) + threadIdx.z;
unsigned int outaddr =
((gridDim.x * blockDim.x) * DUNROLLX) * (gridDim.y * blockDim.y) * zindex +
((gridDim.x * blockDim.x) * DUNROLLX) * yindex + xindex;
zindex += z;

float coorx = gridspacing * xindex;
float coory = gridspacing * yindex;
float coorz = gridspacing * zindex;

float densityvalx1=0.0f;
float densityvalx2=0.0f;
float3 densitycolx1;
densitycolx1=make_float3(0.0f, 0.0f, 0.0f);
float3 densitycolx2=densitycolx1;

#if DUNROLLX >= 4
float densityvalx3=0.0f;
float densityvalx4=0.0f;
float3 densitycolx3=densitycolx1;
float3 densitycolx4=densitycolx1;
#endif
#if DUNROLLX >= 8
float densityvalx5=0.0f;
float densityvalx6=0.0f;
float densityvalx7=0.0f;
float densityvalx8=0.0f;

float3 densitycolx5=densitycolx1;
float3 densitycolx6=densitycolx1;
float3 densitycolx7=densitycolx1;
float3 densitycolx8=densitycolx1;
#endif

float gridspacing_coalesce = gridspacing * DBLOCKSZX;

int atomid;
for (atomid=0; atomid<natoms; atomid++) {
float4 atom = xyzr[atomid];
float4 color = colors[atomid];

float dy = coory - atom.y;
float dz = coorz - atom.z;
float dyz2 = dy*dy + dz*dz;

float dx1 = coorx - atom.x;
float r21 = (dx1*dx1 + dyz2) * atom.w;
float tmp1 = exp2f(-r21);
densityvalx1 += tmp1;
tmp1 *= invisovalue;
densitycolx1.x += tmp1 * color.x;
densitycolx1.y += tmp1 * color.y;
densitycolx1.z += tmp1 * color.z;

float dx2 = dx1 + gridspacing_coalesce;
float r22 = (dx2*dx2 + dyz2) * atom.w;
float tmp2 = exp2f(-r22);
densityvalx2 += tmp2;
tmp2 *= invisovalue;
densitycolx2.x += tmp2 * color.x;
densitycolx2.y += tmp2 * color.y;
densitycolx2.z += tmp2 * color.z;

#if DUNROLLX >= 4
float dx3 = dx2 + gridspacing_coalesce;
float r23 = (dx3*dx3 + dyz2) * atom.w;
float tmp3 = exp2f(-r23);
densityvalx3 += tmp3;
tmp3 *= invisovalue;
densitycolx3.x += tmp3 * color.x;
densitycolx3.y += tmp3 * color.y;
densitycolx3.z += tmp3 * color.z;

float dx4 = dx3 + gridspacing_coalesce;
float r24 = (dx4*dx4 + dyz2) * atom.w;
float tmp4 = exp2f(-r24);
densityvalx4 += tmp4;
tmp4 *= invisovalue;
densitycolx4.x += tmp4 * color.x;
densitycolx4.y += tmp4 * color.y;
densitycolx4.z += tmp4 * color.z;
#endif
#if DUNROLLX >= 8
float dx5 = dx4 + gridspacing_coalesce;
float r25 = (dx5*dx5 + dyz2) * atom.w;
float tmp5 = exp2f(-r25);
densityvalx5 += tmp5;
tmp5 *= invisovalue;
densitycolx5.x += tmp5 * color.x;
densitycolx5.y += tmp5 * color.y;
densitycolx5.z += tmp5 * color.z;

float dx6 = dx5 + gridspacing_coalesce;
float r26 = (dx6*dx6 + dyz2) * atom.w;
float tmp6 = exp2f(-r26);
densityvalx6 += tmp6;
tmp6 *= invisovalue;
densitycolx6.x += tmp6 * color.x;
densitycolx6.y += tmp6 * color.y;
densitycolx6.z += tmp6 * color.z;

float dx7 = dx6 + gridspacing_coalesce;
float r27 = (dx7*dx7 + dyz2) * atom.w;
float tmp7 = exp2f(-r27);
densityvalx7 += tmp7;
tmp7 *= invisovalue;
densitycolx7.x += tmp7 * color.x;
densitycolx7.y += tmp7 * color.y;
densitycolx7.z += tmp7 * color.z;

float dx8 = dx7 + gridspacing_coalesce;
float r28 = (dx8*dx8 + dyz2) * atom.w;
float tmp8 = exp2f(-r28);
densityvalx8 += tmp8;
tmp8 *= invisovalue;
densitycolx8.x += tmp8 * color.x;
densitycolx8.y += tmp8 * color.y;
densitycolx8.z += tmp8 * color.z;
#endif
}

densitygrid[outaddr             ] += densityvalx1;
voltexmap[outaddr             ].x += densitycolx1.x;
voltexmap[outaddr             ].y += densitycolx1.y;
voltexmap[outaddr             ].z += densitycolx1.z;

densitygrid[outaddr+1*DBLOCKSZX] += densityvalx2;
voltexmap[outaddr+1*DBLOCKSZX].x += densitycolx2.x;
voltexmap[outaddr+1*DBLOCKSZX].y += densitycolx2.y;
voltexmap[outaddr+1*DBLOCKSZX].z += densitycolx2.z;

#if DUNROLLX >= 4
densitygrid[outaddr+2*DBLOCKSZX] += densityvalx3;
voltexmap[outaddr+2*DBLOCKSZX].x += densitycolx3.x;
voltexmap[outaddr+2*DBLOCKSZX].y += densitycolx3.y;
voltexmap[outaddr+2*DBLOCKSZX].z += densitycolx3.z;

densitygrid[outaddr+3*DBLOCKSZX] += densityvalx4;
voltexmap[outaddr+3*DBLOCKSZX].x += densitycolx4.x;
voltexmap[outaddr+3*DBLOCKSZX].y += densitycolx4.y;
voltexmap[outaddr+3*DBLOCKSZX].z += densitycolx4.z;
#endif
#if DUNROLLX >= 8
densitygrid[outaddr+4*DBLOCKSZX] += densityvalx5;
voltexmap[outaddr+4*DBLOCKSZX].x += densitycolx5.x;
voltexmap[outaddr+4*DBLOCKSZX].y += densitycolx5.y;
voltexmap[outaddr+4*DBLOCKSZX].z += densitycolx5.z;

densitygrid[outaddr+5*DBLOCKSZX] += densityvalx6;
voltexmap[outaddr+5*DBLOCKSZX].x += densitycolx6.x;
voltexmap[outaddr+5*DBLOCKSZX].y += densitycolx6.y;
voltexmap[outaddr+5*DBLOCKSZX].z += densitycolx6.z;

densitygrid[outaddr+6*DBLOCKSZX] += densityvalx7;
voltexmap[outaddr+6*DBLOCKSZX].x += densitycolx7.x;
voltexmap[outaddr+6*DBLOCKSZX].y += densitycolx7.y;
voltexmap[outaddr+6*DBLOCKSZX].z += densitycolx7.z;

densitygrid[outaddr+7*DBLOCKSZX] += densityvalx8;
voltexmap[outaddr+7*DBLOCKSZX].x += densitycolx8.x;
voltexmap[outaddr+7*DBLOCKSZX].y += densitycolx8.y;
voltexmap[outaddr+7*DBLOCKSZX].z += densitycolx8.z;
#endif
}
	.text
	.file	"gaussdensity_direct_tex.hip"
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.section	.text._ZL23gaussdensity_direct_texiPK15HIP_vector_typeIfLj4EES2_fjPfPS_IfLj3EEf,"axG",@progbits,_ZL23gaussdensity_direct_texiPK15HIP_vector_typeIfLj4EES2_fjPfPS_IfLj3EEf,comdat
	.globl	_ZL23gaussdensity_direct_texiPK15HIP_vector_typeIfLj4EES2_fjPfPS_IfLj3EEf ; -- Begin function _ZL23gaussdensity_direct_texiPK15HIP_vector_typeIfLj4EES2_fjPfPS_IfLj3EEf
	.p2align	8
	.type	_ZL23gaussdensity_direct_texiPK15HIP_vector_typeIfLj4EES2_fjPfPS_IfLj3EEf,@function
_ZL23gaussdensity_direct_texiPK15HIP_vector_typeIfLj4EES2_fjPfPS_IfLj3EEf: ; @_ZL23gaussdensity_direct_texiPK15HIP_vector_typeIfLj4EES2_fjPfPS_IfLj3EEf
; %bb.0:
	s_clause 0x2
	s_load_b64 s[2:3], s[0:1], 0x44
	s_load_b32 s19, s[0:1], 0x0
	s_load_b64 s[16:17], s[0:1], 0x38
	v_bfe_u32 v2, v0, 10, 10
	v_bfe_u32 v3, v0, 20, 10
	v_and_b32_e32 v4, 0x3ff, v0
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s18, s2, 16
	s_and_b32 s3, s3, 0xffff
	s_and_b32 s12, s2, 0xffff
	v_mad_u64_u32 v[0:1], null, s14, s18, v[2:3]
	v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
	s_mul_i32 s13, s13, s12
	s_cmp_lt_i32 s19, 1
	v_lshl_add_u32 v30, s13, 3, v4
	s_cbranch_scc1 .LBB0_3
; %bb.1:                                ; %.lr.ph.preheader
	s_clause 0x2
	s_load_b64 s[2:3], s[0:1], 0x18
	s_load_b128 s[4:7], s[0:1], 0x8
	s_load_b32 s13, s[0:1], 0x30
	v_cvt_f32_u32_e32 v3, v0
	v_cvt_f32_u32_e32 v2, v30
	v_dual_mov_b32 v34, 0 :: v_dual_mov_b32 v29, 0
	v_dual_mov_b32 v31, 0 :: v_dual_mov_b32 v32, 0
	v_dual_mov_b32 v33, 0 :: v_dual_mov_b32 v26, 0
	v_dual_mov_b32 v27, 0 :: v_dual_mov_b32 v28, 0
	v_dual_mov_b32 v25, 0 :: v_dual_mov_b32 v22, 0
	v_dual_mov_b32 v21, 0 :: v_dual_mov_b32 v24, 0
	v_dual_mov_b32 v23, 0 :: v_dual_mov_b32 v20, 0
	v_dual_mov_b32 v17, 0 :: v_dual_mov_b32 v10, 0
	s_waitcnt lgkmcnt(0)
	v_dual_mul_f32 v36, s2, v3 :: v_dual_add_nc_u32 v5, s3, v1
	v_dual_mov_b32 v19, 0 :: v_dual_mov_b32 v4, 0
	v_dual_mul_f32 v35, s2, v2 :: v_dual_mov_b32 v2, 0
	s_delay_alu instid0(VALU_DEP_3)
	v_cvt_f32_u32_e32 v5, v5
	v_mov_b32_e32 v15, 0
	v_mul_f32_e64 v37, 0x41000000, s2
	s_add_u32 s14, s6, 8
	v_dual_mov_b32 v14, 0 :: v_dual_mov_b32 v11, 0
	v_mul_f32_e32 v38, s2, v5
	v_dual_mov_b32 v16, 0 :: v_dual_mov_b32 v13, 0
	v_dual_mov_b32 v18, 0 :: v_dual_mov_b32 v7, 0
	v_dual_mov_b32 v12, 0 :: v_dual_mov_b32 v9, 0
	v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v3, 0
	v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v6, 0
	s_addc_u32 s15, s7, 0
	s_add_u32 s20, s4, 8
	s_addc_u32 s21, s5, 0
.LBB0_2:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_add_u32 s4, s20, -8
	s_addc_u32 s5, s21, -1
	s_add_u32 s2, s14, -8
	s_load_b128 s[4:7], s[4:5], 0x0
	s_addc_u32 s3, s15, -1
	s_add_i32 s19, s19, -1
	s_load_b128 s[8:11], s[2:3], 0x0
	s_add_u32 s14, s14, 16
	s_addc_u32 s15, s15, 0
	s_add_u32 s20, s20, 16
	s_addc_u32 s21, s21, 0
	s_cmp_lg_u32 s19, 0
	s_waitcnt lgkmcnt(0)
	v_dual_subrev_f32 v39, s6, v38 :: v_dual_subrev_f32 v40, s4, v35
	v_subrev_f32_e32 v41, s5, v36
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v39, v39, v39 :: v_dual_add_f32 v42, v37, v40
	v_fmac_f32_e32 v39, v41, v41
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v41, v37, v42
	v_fma_f32 v40, v40, v40, v39
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e64 v44, s7, -v40
	v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v44
	v_cndmask_b32_e64 v44, 0, 0x42800000, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v40, s7, -v40, v44
	v_cndmask_b32_e64 v44, 1.0, 0x1f800000, vcc_lo
	v_exp_f32_e32 v40, v40
	s_waitcnt_depctr 0xfff
	v_fmac_f32_e32 v34, v40, v44
	v_fma_f32 v43, v41, v41, v39
	v_fma_f32 v42, v42, v42, v39
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e64 v46, s7, -v43
	v_mul_f32_e64 v45, s7, -v42
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_f32_e64 s3, 0xc2fc0000, v46
	v_cmp_gt_f32_e64 s2, 0xc2fc0000, v45
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v46, 0, 0x42800000, s3
	v_cndmask_b32_e64 v45, 0, 0x42800000, s2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fma_f32 v43, s7, -v43, v46
	v_cndmask_b32_e64 v46, 1.0, 0x1f800000, s3
	v_fma_f32 v42, s7, -v42, v45
	v_cndmask_b32_e64 v45, 1.0, 0x1f800000, s2
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_exp_f32_e32 v43, v43
	v_add_f32_e32 v41, v37, v41
	v_exp_f32_e32 v42, v42
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v47, v41, v41, v39
	v_add_f32_e32 v41, v37, v41
	v_mul_f32_e64 v48, s7, -v47
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fma_f32 v49, v41, v41, v39
	v_add_f32_e32 v41, v37, v41
	v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v48
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f32_e64 v50, s7, -v49
	v_fma_f32 v51, v41, v41, v39
	v_add_f32_e32 v41, v37, v41
	v_cndmask_b32_e64 v48, 0, 0x42800000, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f32_e64 v52, s7, -v51
	v_fma_f32 v53, v41, v41, v39
	v_add_f32_e32 v41, v37, v41
	s_delay_alu instid0(VALU_DEP_4)
	v_fma_f32 v47, s7, -v47, v48
	v_cndmask_b32_e64 v48, 1.0, 0x1f800000, vcc_lo
	v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v50
	v_mul_f32_e64 v54, s7, -v53
	v_fmac_f32_e32 v39, v41, v41
	v_exp_f32_e32 v47, v47
	v_mul_f32_e32 v41, v40, v44
	v_cndmask_b32_e64 v50, 0, 0x42800000, vcc_lo
	v_mul_f32_e32 v40, v42, v45
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_fma_f32 v49, s7, -v49, v50
	v_cndmask_b32_e64 v50, 1.0, 0x1f800000, vcc_lo
	v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v52
	v_mul_f32_e32 v40, s13, v40
	v_cndmask_b32_e64 v52, 0, 0x42800000, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v28, s8, v40
	v_fmac_f32_e32 v27, s9, v40
	v_fmac_f32_e32 v26, s10, v40
	v_fma_f32 v44, s7, -v51, v52
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_exp_f32_e32 v44, v44
	v_mul_f32_e32 v51, v47, v48
	v_dual_mul_f32 v40, s13, v51 :: v_dual_fmac_f32 v29, v42, v45
	v_mul_f32_e32 v42, v43, v46
	v_cndmask_b32_e64 v45, 1.0, 0x1f800000, vcc_lo
	v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v54
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_fmac_f32 v20, s8, v40 :: v_dual_mul_f32 v41, s13, v41
	v_mul_f32_e32 v42, s13, v42
	v_fmac_f32_e32 v25, v43, v46
	v_exp_f32_e32 v43, v49
	v_cndmask_b32_e64 v46, 0, 0x42800000, vcc_lo
	v_dual_fmac_f32 v21, v47, v48 :: v_dual_fmac_f32 v10, v44, v45
	v_fmac_f32_e32 v22, s10, v42
	v_mul_f32_e64 v49, s7, -v39
	v_cndmask_b32_e64 v47, 1.0, 0x1f800000, vcc_lo
	v_fma_f32 v46, s7, -v53, v46
	v_fmac_f32_e32 v24, s8, v42
	v_fmac_f32_e32 v23, s9, v42
	v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v49
	v_fmac_f32_e32 v17, s10, v40
	v_exp_f32_e32 v42, v46
	v_mul_f32_e32 v46, v44, v45
	v_cndmask_b32_e64 v48, 0, 0x42800000, vcc_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f32 v39, s7, -v39, v48
	s_waitcnt_depctr 0xfff
	v_fmac_f32_e32 v4, v42, v47
	v_exp_f32_e32 v39, v39
	v_dual_fmac_f32 v19, s9, v40 :: v_dual_mul_f32 v40, s13, v46
	v_fmac_f32_e32 v33, s8, v41
	v_fmac_f32_e32 v32, s9, v41
	v_fmac_f32_e32 v31, s10, v41
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_dual_mul_f32 v41, v43, v50 :: v_dual_fmac_f32 v12, s9, v40
	v_fmac_f32_e32 v13, s8, v40
	v_fmac_f32_e32 v11, s10, v40
	v_mul_f32_e32 v41, s13, v41
	v_fmac_f32_e32 v15, v43, v50
	v_cndmask_b32_e64 v43, 1.0, 0x1f800000, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v14, s10, v41
	v_fmac_f32_e32 v18, s8, v41
	v_dual_fmac_f32 v16, s9, v41 :: v_dual_mul_f32 v41, v42, v47
	v_mul_f32_e32 v42, v39, v43
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_fmac_f32 v2, v39, v43 :: v_dual_mul_f32 v41, s13, v41
	v_mul_f32_e32 v39, s13, v42
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v9, s8, v41
	v_fmac_f32_e32 v8, s9, v41
	v_dual_fmac_f32 v7, s10, v41 :: v_dual_fmac_f32 v6, s8, v39
	v_fmac_f32_e32 v5, s9, v39
	v_fmac_f32_e32 v3, s10, v39
	s_cbranch_scc1 .LBB0_2
	s_branch .LBB0_4
.LBB0_3:
	v_dual_mov_b32 v34, 0 :: v_dual_mov_b32 v29, 0
	v_dual_mov_b32 v31, 0 :: v_dual_mov_b32 v32, 0
	v_dual_mov_b32 v33, 0 :: v_dual_mov_b32 v26, 0
	v_dual_mov_b32 v27, 0 :: v_dual_mov_b32 v28, 0
	v_dual_mov_b32 v25, 0 :: v_dual_mov_b32 v22, 0
	v_dual_mov_b32 v21, 0 :: v_dual_mov_b32 v24, 0
	v_dual_mov_b32 v23, 0 :: v_dual_mov_b32 v20, 0
	v_dual_mov_b32 v17, 0 :: v_dual_mov_b32 v10, 0
	v_dual_mov_b32 v19, 0 :: v_dual_mov_b32 v4, 0
	v_dual_mov_b32 v15, 0 :: v_dual_mov_b32 v2, 0
	v_dual_mov_b32 v14, 0 :: v_dual_mov_b32 v11, 0
	v_dual_mov_b32 v16, 0 :: v_dual_mov_b32 v13, 0
	v_dual_mov_b32 v18, 0 :: v_dual_mov_b32 v7, 0
	v_dual_mov_b32 v12, 0 :: v_dual_mov_b32 v9, 0
	v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v3, 0
	v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v6, 0
.LBB0_4:                                ; %._crit_edge
	s_mul_i32 s2, s17, s18
	s_mul_i32 s4, s16, s12
	v_mad_u64_u32 v[35:36], null, s2, v1, v[0:1]
	s_load_b128 s[0:3], s[0:1], 0x20
	v_mov_b32_e32 v1, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v0, s4, v35
	v_lshl_add_u32 v0, v0, 3, v30
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[35:36], 2, v[0:1]
	s_waitcnt lgkmcnt(0)
	v_mad_u64_u32 v[37:38], null, v0, 12, s[2:3]
	v_add_nc_u32_e32 v39, 8, v0
	v_add_co_u32 v35, vcc_lo, s0, v35
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v36, vcc_lo, s1, v36, vcc_lo
	global_load_b32 v30, v[35:36], off
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v30, v34, v30
	v_mov_b32_e32 v40, v1
	global_store_b32 v[35:36], v30, off
	global_load_b96 v[34:36], v[37:38], off
	v_lshlrev_b64 v[40:41], 2, v[39:40]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_add_co_u32 v30, vcc_lo, s0, v40
	s_waitcnt vmcnt(0)
	v_dual_add_f32 v33, v33, v34 :: v_dual_add_f32 v34, v32, v35
	v_add_f32_e32 v35, v31, v36
	v_add_co_ci_u32_e32 v31, vcc_lo, s1, v41, vcc_lo
	global_store_b96 v[37:38], v[33:35], off
	global_load_b32 v34, v[30:31], off
	v_mad_u64_u32 v[32:33], null, v39, 12, s[2:3]
	s_waitcnt vmcnt(0)
	v_dual_add_f32 v29, v29, v34 :: v_dual_add_nc_u32 v34, 16, v0
	global_store_b32 v[30:31], v29, off
	global_load_b96 v[29:31], v[32:33], off
	s_waitcnt vmcnt(0)
	v_dual_mov_b32 v35, v1 :: v_dual_add_f32 v28, v28, v29
	v_dual_add_f32 v29, v27, v30 :: v_dual_add_f32 v30, v26, v31
	s_delay_alu instid0(VALU_DEP_2)
	v_lshlrev_b64 v[35:36], 2, v[34:35]
	global_store_b96 v[32:33], v[28:30], off
	v_mad_u64_u32 v[28:29], null, v34, 12, s[2:3]
	v_add_co_u32 v26, vcc_lo, s0, v35
	v_add_co_ci_u32_e32 v27, vcc_lo, s1, v36, vcc_lo
	global_load_b32 v30, v[26:27], off
	s_waitcnt vmcnt(0)
	v_dual_add_f32 v25, v25, v30 :: v_dual_add_nc_u32 v30, 24, v0
	global_store_b32 v[26:27], v25, off
	global_load_b96 v[25:27], v[28:29], off
	s_waitcnt vmcnt(0)
	v_dual_mov_b32 v31, v1 :: v_dual_add_f32 v24, v24, v25
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[31:32], 2, v[30:31]
	v_dual_add_f32 v25, v23, v26 :: v_dual_add_f32 v26, v22, v27
	v_add_co_u32 v22, vcc_lo, s0, v31
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v23, vcc_lo, s1, v32, vcc_lo
	global_store_b96 v[28:29], v[24:26], off
	v_mad_u64_u32 v[24:25], null, v30, 12, s[2:3]
	global_load_b32 v26, v[22:23], off
	s_waitcnt vmcnt(0)
	v_dual_add_f32 v21, v21, v26 :: v_dual_add_nc_u32 v26, 32, v0
	global_store_b32 v[22:23], v21, off
	global_load_b96 v[21:23], v[24:25], off
	s_waitcnt vmcnt(0)
	v_dual_mov_b32 v27, v1 :: v_dual_add_f32 v20, v20, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[27:28], 2, v[26:27]
	v_dual_add_f32 v21, v19, v22 :: v_dual_add_f32 v22, v17, v23
	v_add_co_u32 v27, vcc_lo, s0, v27
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v28, vcc_lo, s1, v28, vcc_lo
	global_store_b96 v[24:25], v[20:22], off
	v_mad_u64_u32 v[22:23], null, v26, 12, s[2:3]
	global_load_b32 v17, v[27:28], off
	v_dual_mov_b32 v25, v1 :: v_dual_add_nc_u32 v24, 40, v0
	v_lshlrev_b64 v[25:26], 2, v[24:25]
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v15, v15, v17
	global_store_b32 v[27:28], v15, off
	global_load_b96 v[19:21], v[22:23], off
	s_waitcnt vmcnt(0)
	v_dual_add_f32 v16, v16, v20 :: v_dual_add_f32 v15, v18, v19
	v_add_co_u32 v18, vcc_lo, s0, v25
	v_add_f32_e32 v17, v14, v21
	v_add_co_ci_u32_e32 v19, vcc_lo, s1, v26, vcc_lo
	v_mad_u64_u32 v[20:21], null, v24, 12, s[2:3]
	global_store_b96 v[22:23], v[15:17], off
	global_load_b32 v14, v[18:19], off
	s_waitcnt vmcnt(0)
	v_dual_add_f32 v10, v10, v14 :: v_dual_add_nc_u32 v17, 48, v0
	global_store_b32 v[18:19], v10, off
	global_load_b96 v[14:16], v[20:21], off
	v_mov_b32_e32 v18, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[18:19], 2, v[17:18]
	v_add_co_u32 v10, vcc_lo, s0, v18
	s_waitcnt vmcnt(0)
	v_dual_add_f32 v13, v13, v14 :: v_dual_add_f32 v14, v12, v15
	v_add_f32_e32 v15, v11, v16
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v11, vcc_lo, s1, v19, vcc_lo
	global_store_b96 v[20:21], v[13:15], off
	global_load_b32 v12, v[10:11], off
	v_mad_u64_u32 v[13:14], null, v17, 12, s[2:3]
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v4, v4, v12
	global_store_b32 v[10:11], v4, off
	global_load_b96 v[10:12], v[13:14], off
	s_waitcnt vmcnt(0)
	v_dual_add_f32 v9, v9, v10 :: v_dual_add_nc_u32 v0, 56, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[15:16], 2, v[0:1]
	v_dual_add_f32 v10, v8, v11 :: v_dual_add_f32 v11, v7, v12
	v_add_co_u32 v7, vcc_lo, s0, v15
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v8, vcc_lo, s1, v16, vcc_lo
	global_store_b96 v[13:14], v[9:11], off
	v_mad_u64_u32 v[9:10], null, v0, 12, s[2:3]
	global_load_b32 v1, v[7:8], off
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v0, v2, v1
	global_store_b32 v[7:8], v0, off
	global_load_b96 v[0:2], v[9:10], off
	s_waitcnt vmcnt(0)
	v_dual_add_f32 v0, v6, v0 :: v_dual_add_f32 v1, v5, v1
	v_add_f32_e32 v2, v3, v2
	global_store_b96 v[9:10], v[0:2], off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _ZL23gaussdensity_direct_texiPK15HIP_vector_typeIfLj4EES2_fjPfPS_IfLj3EEf
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 312
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 55
		.amdhsa_next_free_sgpr 22
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._ZL23gaussdensity_direct_texiPK15HIP_vector_typeIfLj4EES2_fjPfPS_IfLj3EEf,"axG",@progbits,_ZL23gaussdensity_direct_texiPK15HIP_vector_typeIfLj4EES2_fjPfPS_IfLj3EEf,comdat
.Lfunc_end0:
	.size	_ZL23gaussdensity_direct_texiPK15HIP_vector_typeIfLj4EES2_fjPfPS_IfLj3EEf, .Lfunc_end0-_ZL23gaussdensity_direct_texiPK15HIP_vector_typeIfLj4EES2_fjPfPS_IfLj3EEf
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 2188
; NumSgprs: 24
; NumVgprs: 55
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 6
; NumSGPRsForWavesPerEU: 24
; NumVGPRsForWavesPerEU: 55
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .offset:         48
        .size:           4
        .value_kind:     by_value
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         60
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         64
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         68
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         70
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         72
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         74
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         76
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         78
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         112
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         120
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 312
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _ZL23gaussdensity_direct_texiPK15HIP_vector_typeIfLj4EES2_fjPfPS_IfLj3EEf
    .private_segment_fixed_size: 0
    .sgpr_count:     24
    .sgpr_spill_count: 0
    .symbol:         _ZL23gaussdensity_direct_texiPK15HIP_vector_typeIfLj4EES2_fjPfPS_IfLj3EEf.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     55
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
