#include "stdio.h"
#include "cuda_runtime.h"
#include <cuda_runtime_api.h>
#include "device_launch_parameters.h"

#define THREADS 1024

#define gpu_error_check(ans) { gpu_assert((ans), __FILE__, __LINE__); }
inline void gpu_assert(cudaError_t code, const char *file, int line, bool abort=true)
{
   if (code != cudaSuccess) 
   {
      fprintf(stderr,"GPUassert: %s %s %d\n", cudaGetErrorString(code), file, line);
      if (abort) exit(code);
   }
}

void swap(int* array, int first, int second)
{   
    int tmp = array[first];
    array[first] = array[second];
    array[second] = tmp;
}

__device__
void swap_gpu(int* array, int first, int second)
{   
    int tmp = array[first];
    array[first] = array[second];
    array[second] = tmp;
}

__global__
void bitonic_exchange_gpu(int* dev_values, int depth, unsigned long step)
{
    /* Sorting partners: i and pair_for_i */
    unsigned int i, pair_for_i; 
    
    /* Orient tells in which part of bitonic (sub-)sequence elements are (descending or ascending) */
    unsigned int orient_i, orient_pair_for_i; 

    i = threadIdx.x + blockDim.x * blockIdx.x;
    pair_for_i = i + depth;

    orient_pair_for_i = pair_for_i & step;
    orient_i = i & step;

    /* 
        If current array[i] is the second for other array[j] (i<j) so we just do nothing
        It can be seen if for some a[i], a[pair_for_i] located in other bitonic (sub-)sequence
        For example, a[i] in ascending part, a[pair_for_i] in descending
    */
    if (orient_i != 0 && orient_pair_for_i == 0 
        || orient_i == 0 && orient_pair_for_i != 0)
    {
        return;
    }

    if (orient_i == 0) 
    {
        /* Sort ascending */
        if (dev_values[i]>dev_values[pair_for_i])
        {
            swap_gpu(dev_values, i, pair_for_i);
        }
	}
    else 
    {
		/* Sort descending */
        if (dev_values[i]<dev_values[pair_for_i])
        {
        	swap_gpu(dev_values, i, pair_for_i);
        }
	}
}

void bitonic_sort_gpu(int* array, unsigned long size)
{
    size_t size_mem_array = size * sizeof(int);
    int* array_gpu;

    gpu_error_check(cudaMalloc(&array_gpu, size_mem_array));
    gpu_error_check(cudaMemcpy(array_gpu, array, size_mem_array, cudaMemcpyHostToDevice));

    dim3 blocks = (size < THREADS) ? size : size / THREADS;
    dim3 threadsPerBlock = (size < THREADS) ? 1 : THREADS;

    for (int step = 2; step <= size; step <<= 1)
    {
        for (int depth = step >> 1; depth >= 1; depth >>= 1)
        {
            bitonic_exchange_gpu<<<blocks, threadsPerBlock>>>(array_gpu, depth , step);
        }
	}
	
	gpu_error_check(cudaMemcpy(array, array_gpu, size_mem_array, cudaMemcpyDeviceToHost));
	cudaFree(&array_gpu);
}


void bitonic_exchange(int* array, int depth, int step, unsigned long size)
{
    for (int i = 0; i < size; i++)
    {
        unsigned int pair_for_i;
        unsigned int orient_i, orient_pair_for_i;

        pair_for_i = i + depth;

        orient_pair_for_i = pair_for_i & step;
        orient_i = i & step;

        if (orient_i != 0 && orient_pair_for_i == 0 
            || orient_i == 0 && orient_pair_for_i != 0)
        {
            continue;
        }
        
        if (orient_i == 0)
        {
            if (array[i] > array[pair_for_i])
            {
                swap(array, i, pair_for_i);
            }
        } 
        else 
        {
            if (array[i] < array[pair_for_i])
            {
                swap(array, i, pair_for_i);
            }
        }
    }
}

void bitonic_sort(int* array, unsigned long size)
{   
    for (int step = 2; step <= size; step <<= 1)
    {
        for (int j = step >> 1 ; j >= 1; j >>= 1)
        {
            bitonic_exchange(array, j, step, size);
        }
    }
}
	.file	"tmpxft_002277ef_00000000-6_bitonic_sorts.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2035:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2035:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.section	.rodata._Z10gpu_assert9cudaErrorPKcib.str1.1,"aMS",@progbits,1
.LC0:
	.string	"GPUassert: %s %s %d\n"
	.section	.text._Z10gpu_assert9cudaErrorPKcib,"axG",@progbits,_Z10gpu_assert9cudaErrorPKcib,comdat
	.weak	_Z10gpu_assert9cudaErrorPKcib
	.type	_Z10gpu_assert9cudaErrorPKcib, @function
_Z10gpu_assert9cudaErrorPKcib:
.LFB2027:
	.cfi_startproc
	endbr64
	testl	%edi, %edi
	je	.L8
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	movl	%ecx, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 24
	.cfi_offset 3, -24
	movl	%edi, %ebx
	subq	$24, %rsp
	.cfi_def_cfa_offset 48
	movl	%edx, 12(%rsp)
	movq	%rsi, (%rsp)
	call	cudaGetErrorString@PLT
	movl	12(%rsp), %r9d
	movq	(%rsp), %r8
	leaq	.LC0(%rip), %rdx
	movq	stderr(%rip), %rdi
	movq	%rax, %rcx
	movl	$2, %esi
	xorl	%eax, %eax
	call	__fprintf_chk@PLT
	testb	%bpl, %bpl
	je	.L2
	movl	%ebx, %edi
	call	exit@PLT
.L2:
	addq	$24, %rsp
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	ret
.L8:
	.cfi_restore 3
	.cfi_restore 6
	ret
	.cfi_endproc
.LFE2027:
	.size	_Z10gpu_assert9cudaErrorPKcib, .-_Z10gpu_assert9cudaErrorPKcib
	.text
	.globl	_Z4swapPiii
	.type	_Z4swapPiii, @function
_Z4swapPiii:
.LFB2028:
	.cfi_startproc
	endbr64
	movslq	%esi, %rsi
	movslq	%edx, %rdx
	leaq	(%rdi,%rsi,4), %rcx
	leaq	(%rdi,%rdx,4), %rax
	movl	(%rcx), %esi
	movl	(%rax), %edx
	movl	%edx, (%rcx)
	movl	%esi, (%rax)
	ret
	.cfi_endproc
.LFE2028:
	.size	_Z4swapPiii, .-_Z4swapPiii
	.globl	_Z8swap_gpuPiii
	.type	_Z8swap_gpuPiii, @function
_Z8swap_gpuPiii:
.LFB2029:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2029:
	.size	_Z8swap_gpuPiii, .-_Z8swap_gpuPiii
	.globl	_Z16bitonic_exchangePiiim
	.type	_Z16bitonic_exchangePiiim, @function
_Z16bitonic_exchangePiiim:
.LFB2031:
	.cfi_startproc
	endbr64
	xorl	%r8d, %r8d
	movl	%esi, %r11d
	movl	%edx, %r9d
	movq	%rcx, %r10
	movl	%r8d, %esi
	cmpq	%rcx, %r8
	jne	.L22
	ret
.L22:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
.L19:
	movl	%r9d, %ecx
	leal	(%r11,%r8), %edx
	andl	%r8d, %ecx
	setne	%bl
	testl	%r9d, %edx
	setne	%al
	cmpb	%al, %bl
	jne	.L17
	testl	%ecx, %ecx
	movl	(%rdi,%r8,4), %eax
	movl	%edx, %ecx
	jne	.L18
	cmpl	%eax, (%rdi,%rcx,4)
	jge	.L17
	jmp	.L23
.L18:
	cmpl	%eax, (%rdi,%rcx,4)
	jle	.L17
.L23:
	call	_Z4swapPiii
.L17:
	incq	%r8
	movl	%r8d, %esi
	cmpq	%r10, %r8
	jne	.L19
	popq	%rbx
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2031:
	.size	_Z16bitonic_exchangePiiim, .-_Z16bitonic_exchangePiiim
	.globl	_Z12bitonic_sortPim
	.type	_Z12bitonic_sortPim, @function
_Z12bitonic_sortPim:
.LFB2032:
	.cfi_startproc
	endbr64
	pushq	%r12
	.cfi_def_cfa_offset 16
	.cfi_offset 12, -16
	pushq	%rbp
	.cfi_def_cfa_offset 24
	.cfi_offset 6, -24
	movq	%rsi, %rbp
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset 3, -32
	movl	$2, %ebx
.L25:
	movslq	%ebx, %rax
	cmpq	%rax, %rbp
	jb	.L31
	movl	%ebx, %r12d
.L30:
	sarl	%r12d
	testl	%r12d, %r12d
	jle	.L32
	movq	%rbp, %rcx
	movl	%ebx, %edx
	movl	%r12d, %esi
	call	_Z16bitonic_exchangePiiim
	jmp	.L30
.L32:
	addl	%ebx, %ebx
	jmp	.L25
.L31:
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2032:
	.size	_Z12bitonic_sortPim, .-_Z12bitonic_sortPim
	.globl	_Z42__device_stub__Z20bitonic_exchange_gpuPiimPiim
	.type	_Z42__device_stub__Z20bitonic_exchange_gpuPiimPiim, @function
_Z42__device_stub__Z20bitonic_exchange_gpuPiimPiim:
.LFB2057:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movl	%esi, 20(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L33
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z20bitonic_exchange_gpuPiim(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L33:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L35
	call	__stack_chk_fail@PLT
.L35:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2057:
	.size	_Z42__device_stub__Z20bitonic_exchange_gpuPiimPiim, .-_Z42__device_stub__Z20bitonic_exchange_gpuPiimPiim
	.globl	_Z20bitonic_exchange_gpuPiim
	.type	_Z20bitonic_exchange_gpuPiim, @function
_Z20bitonic_exchange_gpuPiim:
.LFB2058:
	.cfi_startproc
	endbr64
	jmp	_Z42__device_stub__Z20bitonic_exchange_gpuPiimPiim
	.cfi_endproc
.LFE2058:
	.size	_Z20bitonic_exchange_gpuPiim, .-_Z20bitonic_exchange_gpuPiim
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC1:
	.string	"/home/ubuntu/Datasets/stackv2/train-structured/KanashinDmitry/spbu-se2019-autumn/master/Task06/bitonic_sorts.cu"
	.text
	.globl	_Z16bitonic_sort_gpuPim
	.type	_Z16bitonic_sort_gpuPim, @function
_Z16bitonic_sort_gpuPim:
.LFB2030:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	leaq	0(,%rsi,4), %r14
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movl	$2, %r12d
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movq	%rdi, %rbp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movq	%rsi, %rbx
	movq	%r14, %rsi
	subq	$72, %rsp
	.cfi_def_cfa_offset 128
	movq	%fs:40, %rax
	movq	%rax, 56(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movq	%rax, %rdi
	movq	%rax, 8(%rsp)
	call	cudaMalloc@PLT
	movl	$1, %ecx
	movl	$82, %edx
	leaq	.LC1(%rip), %rsi
	movl	%eax, %edi
	call	_Z10gpu_assert9cudaErrorPKcib
	movq	24(%rsp), %rdi
	movq	%r14, %rdx
	movq	%rbp, %rsi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	movl	$83, %edx
	movl	$1, %ecx
	leaq	.LC1(%rip), %rsi
	movl	%eax, %edi
	call	_Z10gpu_assert9cudaErrorPKcib
	movq	%rbx, %rax
	movabsq	$4294967297, %rdx
	shrq	$10, %rax
	cmpq	$1023, %rbx
	movq	%rdx, 36(%rsp)
	cmovbe	%ebx, %eax
	cmpq	$1024, %rbx
	movq	%rdx, 48(%rsp)
	movl	%eax, 32(%rsp)
	sbbl	%eax, %eax
	andl	$-1023, %eax
	addl	$1024, %eax
	movl	%eax, 44(%rsp)
.L42:
	movslq	%r12d, %r15
	cmpq	%r15, %rbx
	jb	.L50
	movl	%r12d, %r13d
.L44:
	sarl	%r13d
	testl	%r13d, %r13d
	jle	.L51
	movl	52(%rsp), %ecx
	movq	44(%rsp), %rdx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	32(%rsp), %rdi
	movl	40(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L44
	movq	24(%rsp), %rdi
	movq	%r15, %rdx
	movl	%r13d, %esi
	call	_Z42__device_stub__Z20bitonic_exchange_gpuPiimPiim
	jmp	.L44
.L51:
	addl	%r12d, %r12d
	jmp	.L42
.L50:
	movq	24(%rsp), %rsi
	movl	$2, %ecx
	movq	%r14, %rdx
	movq	%rbp, %rdi
	call	cudaMemcpy@PLT
	movl	$1, %ecx
	movl	$96, %edx
	leaq	.LC1(%rip), %rsi
	movl	%eax, %edi
	call	_Z10gpu_assert9cudaErrorPKcib
	movq	8(%rsp), %rdi
	call	cudaFree@PLT
	movq	56(%rsp), %rax
	subq	%fs:40, %rax
	je	.L47
	call	__stack_chk_fail@PLT
.L47:
	addq	$72, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2030:
	.size	_Z16bitonic_sort_gpuPim, .-_Z16bitonic_sort_gpuPim
	.section	.rodata.str1.1
.LC2:
	.string	"_Z20bitonic_exchange_gpuPiim"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2060:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC2(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z20bitonic_exchange_gpuPiim(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2060:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include "stdio.h"
#include "hip/hip_runtime.h"
#include <hip/hip_runtime_api.h>


#define THREADS 1024

#define gpu_error_check(ans) { gpu_assert((ans), __FILE__, __LINE__); }
inline void gpu_assert(hipError_t code, const char *file, int line, bool abort=true)
{
   if (code != hipSuccess) 
   {
      fprintf(stderr,"GPUassert: %s %s %d\n", hipGetErrorString(code), file, line);
      if (abort) exit(code);
   }
}

void swap(int* array, int first, int second)
{   
    int tmp = array[first];
    array[first] = array[second];
    array[second] = tmp;
}

__device__
void swap_gpu(int* array, int first, int second)
{   
    int tmp = array[first];
    array[first] = array[second];
    array[second] = tmp;
}

__global__
void bitonic_exchange_gpu(int* dev_values, int depth, unsigned long step)
{
    /* Sorting partners: i and pair_for_i */
    unsigned int i, pair_for_i; 
    
    /* Orient tells in which part of bitonic (sub-)sequence elements are (descending or ascending) */
    unsigned int orient_i, orient_pair_for_i; 

    i = threadIdx.x + blockDim.x * blockIdx.x;
    pair_for_i = i + depth;

    orient_pair_for_i = pair_for_i & step;
    orient_i = i & step;

    /* 
        If current array[i] is the second for other array[j] (i<j) so we just do nothing
        It can be seen if for some a[i], a[pair_for_i] located in other bitonic (sub-)sequence
        For example, a[i] in ascending part, a[pair_for_i] in descending
    */
    if (orient_i != 0 && orient_pair_for_i == 0 
        || orient_i == 0 && orient_pair_for_i != 0)
    {
        return;
    }

    if (orient_i == 0) 
    {
        /* Sort ascending */
        if (dev_values[i]>dev_values[pair_for_i])
        {
            swap_gpu(dev_values, i, pair_for_i);
        }
	}
    else 
    {
		/* Sort descending */
        if (dev_values[i]<dev_values[pair_for_i])
        {
        	swap_gpu(dev_values, i, pair_for_i);
        }
	}
}

void bitonic_sort_gpu(int* array, unsigned long size)
{
    size_t size_mem_array = size * sizeof(int);
    int* array_gpu;

    gpu_error_check(hipMalloc(&array_gpu, size_mem_array));
    gpu_error_check(hipMemcpy(array_gpu, array, size_mem_array, hipMemcpyHostToDevice));

    dim3 blocks = (size < THREADS) ? size : size / THREADS;
    dim3 threadsPerBlock = (size < THREADS) ? 1 : THREADS;

    for (int step = 2; step <= size; step <<= 1)
    {
        for (int depth = step >> 1; depth >= 1; depth >>= 1)
        {
            bitonic_exchange_gpu<<<blocks, threadsPerBlock>>>(array_gpu, depth , step);
        }
	}
	
	gpu_error_check(hipMemcpy(array, array_gpu, size_mem_array, hipMemcpyDeviceToHost));
	hipFree(&array_gpu);
}


void bitonic_exchange(int* array, int depth, int step, unsigned long size)
{
    for (int i = 0; i < size; i++)
    {
        unsigned int pair_for_i;
        unsigned int orient_i, orient_pair_for_i;

        pair_for_i = i + depth;

        orient_pair_for_i = pair_for_i & step;
        orient_i = i & step;

        if (orient_i != 0 && orient_pair_for_i == 0 
            || orient_i == 0 && orient_pair_for_i != 0)
        {
            continue;
        }
        
        if (orient_i == 0)
        {
            if (array[i] > array[pair_for_i])
            {
                swap(array, i, pair_for_i);
            }
        } 
        else 
        {
            if (array[i] < array[pair_for_i])
            {
                swap(array, i, pair_for_i);
            }
        }
    }
}

void bitonic_sort(int* array, unsigned long size)
{   
    for (int step = 2; step <= size; step <<= 1)
    {
        for (int j = step >> 1 ; j >= 1; j >>= 1)
        {
            bitonic_exchange(array, j, step, size);
        }
    }
}
	.text
	.file	"bitonic_sorts.hip"
	.globl	_Z4swapPiii                     # -- Begin function _Z4swapPiii
	.type	_Z4swapPiii,@function
_Z4swapPiii:                            # @_Z4swapPiii
	.cfi_startproc
# %bb.0:
	movslq	%esi, %rax
	movl	(%rdi,%rax,4), %ecx
	movslq	%edx, %rdx
	movl	(%rdi,%rdx,4), %esi
	movl	%esi, (%rdi,%rax,4)
	movl	%ecx, (%rdi,%rdx,4)
	retq
.Lfunc_end0:
	.size	_Z4swapPiii, .Lfunc_end0-_Z4swapPiii
	.cfi_endproc
                                        # -- End function
	.globl	_Z35__device_stub__bitonic_exchange_gpuPiim # -- Begin function _Z35__device_stub__bitonic_exchange_gpuPiim
	.type	_Z35__device_stub__bitonic_exchange_gpuPiim,@function
_Z35__device_stub__bitonic_exchange_gpuPiim: # @_Z35__device_stub__bitonic_exchange_gpuPiim
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	12(%rsp), %rcx
	movl	%esi, (%rcx)
	leaq	32(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z20bitonic_exchange_gpuPiim, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z35__device_stub__bitonic_exchange_gpuPiim, .Lfunc_end1-_Z35__device_stub__bitonic_exchange_gpuPiim
	.cfi_endproc
                                        # -- End function
	.globl	_Z16bitonic_sort_gpuPim         # -- Begin function _Z16bitonic_sort_gpuPim
	.type	_Z16bitonic_sort_gpuPim,@function
_Z16bitonic_sort_gpuPim:                # @_Z16bitonic_sort_gpuPim
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$24, %rsp
	.cfi_def_cfa_offset 80
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%rsi, %r15
	movq	%rdi, %r14
	leaq	(,%rsi,4), %rbx
	movq	%rsp, %rdi
	movq	%rbx, %rsi
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB2_1
# %bb.3:                                # %_Z10gpu_assert10hipError_tPKcib.exit
	movq	(%rsp), %rdi
	movq	%r14, 8(%rsp)                   # 8-byte Spill
	movq	%r14, %rsi
	movq	%rbx, 16(%rsp)                  # 8-byte Spill
	movq	%rbx, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	testl	%eax, %eax
	jne	.LBB2_4
# %bb.5:                                # %_Z10gpu_assert10hipError_tPKcib.exit27
	movq	%r15, %rax
	shrq	$10, %rax
	movabsq	$4294967296, %r12               # imm = 0x100000000
	leaq	1(%r12), %rcx
	movl	$1024, %edx                     # imm = 0x400
	orq	%rdx, %r12
	cmpq	%rdx, %r15
	cmovbq	%r15, %rax
	cmovbq	%rcx, %r12
	cmpq	$2, %r15
	jb	.LBB2_9
# %bb.6:                                # %.lr.ph35.preheader
	movl	%eax, %r13d
	btsq	$32, %r13
	movl	$2, %ebx
	movl	$2, %ebp
.LBB2_7:                                # %.lr.ph35
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB2_11 Depth 2
	movl	%ebx, %r14d
	sarl	%r14d
	testl	%r14d, %r14d
	jle	.LBB2_8
.LBB2_11:                               # %.lr.ph
                                        #   Parent Loop BB2_7 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_13
# %bb.12:                               #   in Loop: Header=BB2_11 Depth=2
	movq	(%rsp), %rdi
	movl	%r14d, %esi
	movq	%rbp, %rdx
	callq	_Z35__device_stub__bitonic_exchange_gpuPiim
.LBB2_13:                               #   in Loop: Header=BB2_11 Depth=2
	movl	%r14d, %eax
	shrl	%eax
	cmpl	$2, %r14d
	movl	%eax, %r14d
	jae	.LBB2_11
.LBB2_8:                                # %._crit_edge
                                        #   in Loop: Header=BB2_7 Depth=1
	addl	%ebx, %ebx
	movslq	%ebx, %rbp
	cmpq	%r15, %rbp
	jbe	.LBB2_7
.LBB2_9:                                # %._crit_edge36
	movq	(%rsp), %rsi
	movq	8(%rsp), %rdi                   # 8-byte Reload
	movq	16(%rsp), %rdx                  # 8-byte Reload
	movl	$2, %ecx
	callq	hipMemcpy
	testl	%eax, %eax
	jne	.LBB2_14
# %bb.10:                               # %_Z10gpu_assert10hipError_tPKcib.exit29
	movq	%rsp, %rdi
	callq	hipFree
	addq	$24, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB2_1:
	.cfi_def_cfa_offset 80
	movl	%eax, %ebp
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.1, %esi
	movl	$.L.str, %ecx
	movq	%rbx, %rdi
	movq	%rax, %rdx
	movl	$82, %r8d
	jmp	.LBB2_2
.LBB2_4:
	movl	%eax, %ebp
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.1, %esi
	movl	$.L.str, %ecx
	movq	%rbx, %rdi
	movq	%rax, %rdx
	movl	$83, %r8d
.LBB2_2:
	xorl	%eax, %eax
	callq	fprintf
	movl	%ebp, %edi
	callq	exit
.LBB2_14:
	movl	%eax, %ebx
	movq	stderr(%rip), %r14
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.1, %esi
	movl	$.L.str, %ecx
	movq	%r14, %rdi
	movq	%rax, %rdx
	movl	$96, %r8d
	xorl	%eax, %eax
	callq	fprintf
	movl	%ebx, %edi
	callq	exit
.Lfunc_end2:
	.size	_Z16bitonic_sort_gpuPim, .Lfunc_end2-_Z16bitonic_sort_gpuPim
	.cfi_endproc
                                        # -- End function
	.globl	_Z16bitonic_exchangePiiim       # -- Begin function _Z16bitonic_exchangePiiim
	.type	_Z16bitonic_exchangePiiim,@function
_Z16bitonic_exchangePiiim:              # @_Z16bitonic_exchangePiiim
	.cfi_startproc
# %bb.0:
	testq	%rcx, %rcx
	je	.LBB3_11
# %bb.1:                                # %.lr.ph.preheader
	movslq	%esi, %rax
	leaq	(%rdi,%rax,4), %rsi
	movl	%eax, %r8d
	xorl	%r9d, %r9d
.LBB3_2:                                # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	leal	(%r8,%r9), %r10d
	andl	%edx, %r10d
	testl	%edx, %r9d
	je	.LBB3_4
# %bb.3:                                # %.lr.ph
                                        #   in Loop: Header=BB3_2 Depth=1
	testl	%r10d, %r10d
	je	.LBB3_10
.LBB3_4:                                #   in Loop: Header=BB3_2 Depth=1
	testl	%edx, %r9d
	jne	.LBB3_6
# %bb.5:                                #   in Loop: Header=BB3_2 Depth=1
	testl	%r10d, %r10d
	jne	.LBB3_10
.LBB3_6:                                #   in Loop: Header=BB3_2 Depth=1
	leaq	(%rax,%r9), %r11
	movl	(%rdi,%r9,4), %r10d
	movl	%r11d, %r11d
	movl	(%rdi,%r11,4), %r11d
	testl	%edx, %r9d
	je	.LBB3_7
# %bb.8:                                #   in Loop: Header=BB3_2 Depth=1
	cmpl	%r11d, %r10d
	jge	.LBB3_10
.LBB3_9:                                # %.sink.split
                                        #   in Loop: Header=BB3_2 Depth=1
	movl	(%rsi,%r9,4), %r11d
	movl	%r11d, (%rdi,%r9,4)
	movl	%r10d, (%rsi,%r9,4)
.LBB3_10:                               #   in Loop: Header=BB3_2 Depth=1
	incq	%r9
	cmpq	%r9, %rcx
	jne	.LBB3_2
	jmp	.LBB3_11
.LBB3_7:                                #   in Loop: Header=BB3_2 Depth=1
	cmpl	%r11d, %r10d
	jg	.LBB3_9
	jmp	.LBB3_10
.LBB3_11:                               # %._crit_edge
	retq
.Lfunc_end3:
	.size	_Z16bitonic_exchangePiiim, .Lfunc_end3-_Z16bitonic_exchangePiiim
	.cfi_endproc
                                        # -- End function
	.globl	_Z12bitonic_sortPim             # -- Begin function _Z12bitonic_sortPim
	.type	_Z12bitonic_sortPim,@function
_Z12bitonic_sortPim:                    # @_Z12bitonic_sortPim
	.cfi_startproc
# %bb.0:
	cmpq	$2, %rsi
	jb	.LBB4_5
# %bb.1:                                # %.lr.ph15.preheader
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	pushq	%rax
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%rsi, %rbx
	movq	%rdi, %r14
	movl	$2, %ebp
.LBB4_2:                                # %.lr.ph15
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB4_6 Depth 2
	movl	%ebp, %r15d
	sarl	%r15d
	testl	%r15d, %r15d
	jle	.LBB4_3
.LBB4_6:                                # %.lr.ph
                                        #   Parent Loop BB4_2 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movq	%r14, %rdi
	movl	%r15d, %esi
	movl	%ebp, %edx
	movq	%rbx, %rcx
	callq	_Z16bitonic_exchangePiiim
	movl	%r15d, %eax
	shrl	%eax
	cmpl	$2, %r15d
	movl	%eax, %r15d
	jae	.LBB4_6
.LBB4_3:                                # %._crit_edge
                                        #   in Loop: Header=BB4_2 Depth=1
	addl	%ebp, %ebp
	movslq	%ebp, %rax
	cmpq	%rbx, %rax
	jbe	.LBB4_2
# %bb.4:
	addq	$8, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	.cfi_restore %rbx
	.cfi_restore %r14
	.cfi_restore %r15
	.cfi_restore %rbp
.LBB4_5:                                # %._crit_edge16
	retq
.Lfunc_end4:
	.size	_Z12bitonic_sortPim, .Lfunc_end4-_Z12bitonic_sortPim
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB5_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB5_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z20bitonic_exchange_gpuPiim, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end5:
	.size	__hip_module_ctor, .Lfunc_end5-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB6_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB6_2:
	retq
.Lfunc_end6:
	.size	__hip_module_dtor, .Lfunc_end6-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z20bitonic_exchange_gpuPiim,@object # @_Z20bitonic_exchange_gpuPiim
	.section	.rodata,"a",@progbits
	.globl	_Z20bitonic_exchange_gpuPiim
	.p2align	3, 0x0
_Z20bitonic_exchange_gpuPiim:
	.quad	_Z35__device_stub__bitonic_exchange_gpuPiim
	.size	_Z20bitonic_exchange_gpuPiim, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"/home/ubuntu/Datasets/stackv2/train-structured-repos-hip-sm89/KanashinDmitry/spbu-se2019-autumn/master/Task06/bitonic_sorts.hip"
	.size	.L.str, 128

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"GPUassert: %s %s %d\n"
	.size	.L.str.1, 21

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z20bitonic_exchange_gpuPiim"
	.size	.L__unnamed_1, 29

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z35__device_stub__bitonic_exchange_gpuPiim
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z20bitonic_exchange_gpuPiim
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z20bitonic_exchange_gpuPiim ; -- Begin function _Z20bitonic_exchange_gpuPiim
	.globl	_Z20bitonic_exchange_gpuPiim
	.p2align	8
	.type	_Z20bitonic_exchange_gpuPiim,@function
_Z20bitonic_exchange_gpuPiim:           ; @_Z20bitonic_exchange_gpuPiim
; %bb.0:
	s_clause 0x2
	s_load_b32 s2, s[0:1], 0x24
	s_load_b32 s3, s[0:1], 0x8
	s_load_b32 s4, s[0:1], 0x10
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	v_add_nc_u32_e32 v3, s3, v1
	v_and_b32_e32 v2, s4, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v0, s4, v3
	v_cmp_eq_u32_e32 vcc_lo, 0, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_ne_u32_e64 s2, 0, v0
	s_or_b32 s2, vcc_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_8
; %bb.1:
	v_cmp_ne_u32_e32 vcc_lo, 0, v2
	v_cmp_eq_u32_e64 s2, 0, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s2, vcc_lo, s2
	s_and_b32 exec_lo, exec_lo, s2
	s_cbranch_execz .LBB0_8
; %bb.2:
	s_load_b64 s[2:3], s[0:1], 0x0
	v_mov_b32_e32 v4, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v2, v4
	v_lshlrev_b64 v[7:8], 2, v[3:4]
	v_lshlrev_b64 v[5:6], 2, v[1:2]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v4, s0, s2, v5
	v_add_co_ci_u32_e64 v5, s0, s3, v6, s0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v6, s0, s2, v7
	v_add_co_ci_u32_e64 v7, s0, s3, v8, s0
	s_mov_b32 s0, 0
	s_clause 0x1
	global_load_b32 v0, v[4:5], off
	global_load_b32 v2, v[6:7], off
	s_and_saveexec_b32 s1, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s1, exec_lo, s1
	s_cbranch_execz .LBB0_4
; %bb.3:
	s_waitcnt vmcnt(0)
	v_cmp_lt_i32_e32 vcc_lo, v0, v2
                                        ; implicit-def: $vgpr0
                                        ; implicit-def: $vgpr2
	s_and_b32 s0, vcc_lo, exec_lo
.LBB0_4:                                ; %Flow
	s_and_not1_saveexec_b32 s1, s1
	s_cbranch_execz .LBB0_6
; %bb.5:
	s_waitcnt vmcnt(0)
	v_cmp_gt_i32_e32 vcc_lo, v0, v2
	s_and_not1_b32 s0, s0, exec_lo
	s_and_b32 s4, vcc_lo, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s0, s0, s4
.LBB0_6:                                ; %Flow38
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB0_8
; %bb.7:                                ; %.sink.split
	v_ashrrev_i32_e32 v4, 31, v3
	s_waitcnt vmcnt(0)
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v2, vcc_lo, s2, v3
	v_add_co_ci_u32_e32 v3, vcc_lo, s3, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v0, vcc_lo, s2, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
	s_clause 0x1
	global_load_b32 v4, v[2:3], off
	global_load_b32 v5, v[0:1], off
	s_waitcnt vmcnt(1)
	global_store_b32 v[0:1], v4, off
	s_waitcnt vmcnt(0)
	global_store_b32 v[2:3], v5, off
.LBB0_8:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z20bitonic_exchange_gpuPiim
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 9
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z20bitonic_exchange_gpuPiim, .Lfunc_end0-_Z20bitonic_exchange_gpuPiim
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 428
; NumSgprs: 18
; NumVgprs: 9
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 9
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .offset:         16
        .size:           8
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z20bitonic_exchange_gpuPiim
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z20bitonic_exchange_gpuPiim.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     9
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
