#include <stdio.h>
#include <algorithm>
#include <cstdlib>
#include <curand.h>
#include <curand_kernel.h>

// In the following section, define the model Parameters
#define N_AR 3
#define START_X 0.800, 0.900, 1.100
#define PHI -0.315415, 0.427606, 0.189134
#define C 1.500
// End model parameters

unsigned int N_SIMS, N_BLK, N_THRD, N_BYTES, T_MAX;
const unsigned int MAX_THREADS = 512; // max threads per block 
__constant__ float c_phi[N_AR]; // autoregressive parameters as constant
unsigned int N_BYTES_PARM = N_AR * sizeof(float); // size of parameter constant

// Calculate and return mean of an array of floats
float calcMean(float *arr, unsigned int const n) {
	float sum = 0.0;
	for (int i=0; i<n; i++) {
		sum += arr[i];
	}
	return sum / n; 
}

__host__ cudaEvent_t get_time(void) {
	cudaEvent_t time;
	cudaEventCreate(&time);
	cudaEventRecord(time);
	return time;
}

// Simulate a AR(n) process saving temp results to registers
__global__ void sim_register(float *x0, float *x1, float *x2, float *x_out, 
							const unsigned int N, const unsigned int T) {
	unsigned int const tid = (blockIdx.x * blockDim.x) + threadIdx.x;
	
	if (tid < N) {
		curandState_t state; // initialize rand state
		curand_init(tid, 0, 0, &state); // set seed to thread index

		float r_x0 = x0[tid]; // Copy values of X to register
		float r_x1 = x1[tid];
		float r_x2 = x2[tid];
		float r_x; // initialize r_x
		
		float w; // white noise for AR process
		for (int t=0; t < T; t++) { // Simulate for T_MAX periods
			w = curand_normal(&state) / 2; // w ~ Normal(0, 0.5)
			r_x = C + c_phi[2]*r_x2 + c_phi[1]*r_x1 + c_phi[0]*r_x0 + w;
			r_x2 = r_x1;
			r_x1 = r_x0;
			r_x0 = r_x;
		}

		x_out[tid] = r_x; // save x as output
	}
}

// Simulate a AR(n) process saving work to global mem directly
__global__ void sim_gmem(float *x0, float *x1, float *x2, float *x_out, 
						const unsigned int N, const unsigned int T) {
	unsigned int const i = (blockIdx.x * blockDim.x) + threadIdx.x;
	
	if (i < N) {
		curandState_t state; // initialize rand state
		curand_init(i, 0, 0, &state); // set seed to thread index

		float w; // white noise for AR process
		for (int t=0; t < T; t++) { // Simulate for T_MAX periods
			w = curand_normal(&state) / 2; // w ~ Normal(0, 0.5)
			x_out[i] = C + c_phi[2]*x2[i] + c_phi[1]*x1[i] + c_phi[0]*x0[i] + w;
			x2[i] = x1[i];
			x1[i] = x0[i];
			x0[i] = x_out[i];
		}
	}
}

void simulate(const unsigned int type) {
	float *h_x0, *h_x1, *h_x2, *h_x; 
	h_x0 = (float*) malloc(N_BYTES); // allocate input
	h_x1 = (float*) malloc(N_BYTES); // allocate input
	h_x2 = (float*) malloc(N_BYTES); // allocate input
	h_x = (float*) malloc(N_BYTES); // allocate output 
		
	float start_x [N_AR] = {START_X};
	for (int i = 0; i < N_SIMS; i++) { // set all host Xs to the same number
		h_x0[i] = start_x[0];
		h_x1[i] = start_x[1];
		h_x2[i] = start_x[2];
	}
	
	float *d_x0, *d_x1, *d_x2, *d_out; // device memory for storing X
	cudaMalloc((void **)&d_x0, N_BYTES); // allocate device input
	cudaMalloc((void **)&d_x1, N_BYTES); // allocate device input
	cudaMalloc((void **)&d_x2, N_BYTES); // allocate device input
	cudaMalloc((void **)&d_out, N_BYTES); // allocate device output

	float h_phi [N_AR] = {PHI}; // constant for AR parms
	cudaMemcpyToSymbol(c_phi, h_phi, N_BYTES_PARM); // copy params to constant
	
	/**** Simulation *****/
	char *typeName;
	cudaEvent_t start = get_time(); // start time 
	cudaMemcpy(d_x0, h_x0, N_BYTES, cudaMemcpyHostToDevice); //copy to device
	cudaMemcpy(d_x1, h_x1, N_BYTES, cudaMemcpyHostToDevice); //copy to device
	cudaMemcpy(d_x2, h_x2, N_BYTES, cudaMemcpyHostToDevice); //copy to device
	
	if (type == 1){ // if simulating with registers
		typeName = "registers";
		sim_register<<<N_BLK, N_THRD>>>(d_x0, d_x1, d_x2, d_out, N_SIMS, T_MAX); 
		
	} else { // if simulating with global memory 
		typeName = "global mem";
		sim_gmem<<<N_BLK, N_THRD>>>(d_x0, d_x1, d_x2, d_out, N_SIMS, T_MAX); 
	}	
	cudaMemcpy(h_x, d_out, N_BYTES, cudaMemcpyDeviceToHost ); // copy back
	cudaEvent_t stop = get_time(); // stop time
	cudaEventSynchronize(stop);
	
	// Calculate and print simulation results and timing
	float x_mu = calcMean(h_x, N_SIMS);
	float dur = 0;
	cudaEventElapsedTime(&dur, start, stop);
	printf("\twith %s, result=%f, %.3f ms taken, \n", typeName, x_mu, dur);
	
	// Free up memory
	cudaFree(d_x2); cudaFree(d_x1); cudaFree(d_x0); 
	cudaFree(d_out); cudaFree(c_phi);
	free(h_x0); free(h_x1); free(h_x2); free(h_x);
}

int main(int argc, char* argv[]) {
	if (argc == 3) { // get number of simulations based on CMDLINE input
		N_SIMS = atoi(argv[1]);
		T_MAX = atoi(argv[2]);
	} else {
		printf("Usage: %s [nSimulations] [maxTimePeriods].\n", argv[0]);
		return EXIT_FAILURE;
	}
	N_BLK = N_SIMS / MAX_THREADS + 1; // min of one block
	N_THRD = std::min(N_SIMS, MAX_THREADS); // num of threads per block
	N_BYTES = N_SIMS * sizeof(float); // size of array 
	printf("Running %u simulations over %u time periods...\n", N_SIMS, T_MAX);
	
	simulate(1); // simulating with registers
	simulate(2); // simulating with global memory
	return EXIT_SUCCESS;
}

	.file	"tmpxft_002d1a06_00000000-6_test_register.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2528:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2528:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z8calcMeanPfj
	.type	_Z8calcMeanPfj, @function
_Z8calcMeanPfj:
.LFB2521:
	.cfi_startproc
	endbr64
	xorl	%eax, %eax
	xorps	%xmm0, %xmm0
.L3:
	cmpl	%esi, %eax
	jnb	.L6
	addss	(%rdi,%rax,4), %xmm0
	incq	%rax
	jmp	.L3
.L6:
	cvtsi2ssl	%esi, %xmm1
	divss	%xmm1, %xmm0
	ret
	.cfi_endproc
.LFE2521:
	.size	_Z8calcMeanPfj, .-_Z8calcMeanPfj
	.globl	_Z8get_timev
	.type	_Z8get_timev, @function
_Z8get_timev:
.LFB2522:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%fs:40, %rax
	movq	%rax, 8(%rsp)
	xorl	%eax, %eax
	movq	%rsp, %rdi
	call	cudaEventCreate@PLT
	movq	(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movq	(%rsp), %rax
	movq	8(%rsp), %rdx
	subq	%fs:40, %rdx
	je	.L8
	call	__stack_chk_fail@PLT
.L8:
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2522:
	.size	_Z8get_timev, .-_Z8get_timev
	.globl	_Z40__device_stub__Z12sim_registerPfS_S_S_jjPfS_S_S_jj
	.type	_Z40__device_stub__Z12sim_registerPfS_S_S_jjPfS_S_S_jj, @function
_Z40__device_stub__Z12sim_registerPfS_S_S_jjPfS_S_S_jj:
.LFB2550:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	56(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	64(%rsp), %rcx
	movl	%r8d, 12(%rsp)
	movl	%r9d, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L10
	pushq	64(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z12sim_registerPfS_S_S_jj(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 208
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L10:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L12
	call	__stack_chk_fail@PLT
.L12:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2550:
	.size	_Z40__device_stub__Z12sim_registerPfS_S_S_jjPfS_S_S_jj, .-_Z40__device_stub__Z12sim_registerPfS_S_S_jjPfS_S_S_jj
	.globl	_Z12sim_registerPfS_S_S_jj
	.type	_Z12sim_registerPfS_S_S_jj, @function
_Z12sim_registerPfS_S_S_jj:
.LFB2551:
	.cfi_startproc
	endbr64
	jmp	_Z40__device_stub__Z12sim_registerPfS_S_S_jjPfS_S_S_jj
	.cfi_endproc
.LFE2551:
	.size	_Z12sim_registerPfS_S_S_jj, .-_Z12sim_registerPfS_S_S_jj
	.globl	_Z35__device_stub__Z8sim_gmemPfS_S_S_jjPfS_S_S_jj
	.type	_Z35__device_stub__Z8sim_gmemPfS_S_S_jjPfS_S_S_jj, @function
_Z35__device_stub__Z8sim_gmemPfS_S_S_jjPfS_S_S_jj:
.LFB2552:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	56(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	64(%rsp), %rcx
	movl	%r8d, 12(%rsp)
	movl	%r9d, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L15
	pushq	64(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z8sim_gmemPfS_S_S_jj(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 208
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L15:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L17
	call	__stack_chk_fail@PLT
.L17:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2552:
	.size	_Z35__device_stub__Z8sim_gmemPfS_S_S_jjPfS_S_S_jj, .-_Z35__device_stub__Z8sim_gmemPfS_S_S_jjPfS_S_S_jj
	.globl	_Z8sim_gmemPfS_S_S_jj
	.type	_Z8sim_gmemPfS_S_S_jj, @function
_Z8sim_gmemPfS_S_S_jj:
.LFB2553:
	.cfi_startproc
	endbr64
	jmp	_Z35__device_stub__Z8sim_gmemPfS_S_S_jjPfS_S_S_jj
	.cfi_endproc
.LFE2553:
	.size	_Z8sim_gmemPfS_S_S_jj, .-_Z8sim_gmemPfS_S_S_jj
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC1:
	.string	"registers"
.LC2:
	.string	"global mem"
.LC7:
	.string	"\twith %s, result=%f, %.3f ms taken, \n"
	.text
	.globl	_Z8simulatej
	.type	_Z8simulatej, @function
_Z8simulatej:
.LFB2523:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	movl	%edi, %r14d
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$120, %rsp
	.cfi_def_cfa_offset 176
	movl	N_BYTES(%rip), %r13d
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	movq	%r13, %rdi
	call	malloc@PLT
	movq	%r13, %rdi
	movq	%rax, %r12
	call	malloc@PLT
	movq	%r13, %rdi
	movq	%rax, %rbp
	call	malloc@PLT
	movq	%r13, %rdi
	movq	%rax, %rbx
	call	malloc@PLT
	movl	N_SIMS(%rip), %edx
	movss	.LC3(%rip), %xmm0
	movss	.LC4(%rip), %xmm1
	movss	.LC5(%rip), %xmm2
	movq	%rax, 8(%rsp)
	xorl	%eax, %eax
.L21:
	cmpl	%edx, %eax
	jnb	.L30
	movss	%xmm0, (%r12,%rax,4)
	movss	%xmm1, 0(%rbp,%rax,4)
	movss	%xmm2, (%rbx,%rax,4)
	incq	%rax
	jmp	.L21
.L30:
	leaq	32(%rsp), %rdi
	movq	%r13, %rsi
	leaq	_ZL5c_phi(%rip), %r15
	call	cudaMalloc@PLT
	movl	N_BYTES(%rip), %esi
	leaq	40(%rsp), %rdi
	call	cudaMalloc@PLT
	movl	N_BYTES(%rip), %esi
	leaq	48(%rsp), %rdi
	call	cudaMalloc@PLT
	movl	N_BYTES(%rip), %esi
	leaq	56(%rsp), %rdi
	call	cudaMalloc@PLT
	movl	N_BYTES_PARM(%rip), %edx
	xorl	%ecx, %ecx
	movq	%r15, %rdi
	movl	$1, %r8d
	leaq	92(%rsp), %rsi
	movabsq	$4529195350730309139, %rax
	movl	$0x3e41ac58, 100(%rsp)
	movq	%rax, 92(%rsp)
	call	cudaMemcpyToSymbol@PLT
	call	_Z8get_timev
	movl	N_BYTES(%rip), %edx
	movq	32(%rsp), %rdi
	movq	%r12, %rsi
	movl	$1, %ecx
	movq	%rax, 16(%rsp)
	call	cudaMemcpy@PLT
	movl	N_BYTES(%rip), %edx
	movq	40(%rsp), %rdi
	movq	%rbp, %rsi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	movl	N_BYTES(%rip), %edx
	movq	48(%rsp), %rdi
	movq	%rbx, %rsi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	movl	N_THRD(%rip), %eax
	decl	%r14d
	movl	N_BLK(%rip), %edx
	movl	$0, %r9d
	movl	$0, %r8d
	movl	%eax, 80(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 84(%rsp)
	movl	88(%rsp), %ecx
	movl	%edx, 68(%rsp)
	movq	80(%rsp), %rdx
	movq	%rax, 72(%rsp)
	movq	68(%rsp), %rdi
	movl	76(%rsp), %esi
	jne	.L23
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L24
	movl	T_MAX(%rip), %r9d
	movl	N_SIMS(%rip), %r8d
	movq	56(%rsp), %rcx
	movq	48(%rsp), %rdx
	movq	40(%rsp), %rsi
	movq	32(%rsp), %rdi
	call	_Z40__device_stub__Z12sim_registerPfS_S_S_jjPfS_S_S_jj
.L24:
	leaq	.LC1(%rip), %r13
	jmp	.L25
.L23:
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L26
	movl	T_MAX(%rip), %r9d
	movl	N_SIMS(%rip), %r8d
	movq	56(%rsp), %rcx
	movq	48(%rsp), %rdx
	movq	40(%rsp), %rsi
	movq	32(%rsp), %rdi
	call	_Z35__device_stub__Z8sim_gmemPfS_S_S_jjPfS_S_S_jj
.L26:
	leaq	.LC2(%rip), %r13
.L25:
	movl	N_BYTES(%rip), %edx
	movq	56(%rsp), %rsi
	movl	$2, %ecx
	movq	8(%rsp), %rdi
	call	cudaMemcpy@PLT
	call	_Z8get_timev
	movq	%rax, %rdi
	movq	%rax, %r14
	call	cudaEventSynchronize@PLT
	movl	N_SIMS(%rip), %esi
	movq	8(%rsp), %rdi
	movq	%r14, %rdx
	call	_Z8calcMeanPfj
	movq	16(%rsp), %rsi
	leaq	80(%rsp), %rdi
	movl	$0x00000000, 80(%rsp)
	movss	%xmm0, 28(%rsp)
	call	cudaEventElapsedTime@PLT
	movss	28(%rsp), %xmm0
	movq	%r13, %rdx
	movb	$2, %al
	leaq	.LC7(%rip), %rsi
	movl	$2, %edi
	cvtss2sd	80(%rsp), %xmm1
	cvtss2sd	%xmm0, %xmm0
	call	__printf_chk@PLT
	movq	48(%rsp), %rdi
	call	cudaFree@PLT
	movq	40(%rsp), %rdi
	call	cudaFree@PLT
	movq	32(%rsp), %rdi
	call	cudaFree@PLT
	movq	56(%rsp), %rdi
	call	cudaFree@PLT
	movq	%r15, %rdi
	call	cudaFree@PLT
	movq	%r12, %rdi
	call	free@PLT
	movq	%rbp, %rdi
	call	free@PLT
	movq	%rbx, %rdi
	call	free@PLT
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L27
	call	__stack_chk_fail@PLT
.L27:
	movq	8(%rsp), %rdi
	addq	$120, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	free@PLT
	.cfi_endproc
.LFE2523:
	.size	_Z8simulatej, .-_Z8simulatej
	.section	.rodata.str1.1
.LC8:
	.string	"Running %u simulations over %u time periods...\n"
.LC9:
	.string	"Usage: %s [nSimulations] [maxTimePeriods].\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2524:
	.cfi_startproc
	endbr64
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	movq	%rsi, %rbp
	pushq	%rbx
	.cfi_def_cfa_offset 24
	.cfi_offset 3, -24
	pushq	%rcx
	.cfi_def_cfa_offset 32
	cmpl	$3, %edi
	jne	.L32
	movq	8(%rsi), %rdi
	call	atoi@PLT
	movq	16(%rbp), %rdi
	movl	%eax, %ebx
	movl	%eax, N_SIMS(%rip)
	call	atoi@PLT
	movl	%ebx, %edx
	movl	$2, %edi
	leaq	.LC8(%rip), %rsi
	movl	%eax, %ecx
	movl	%eax, T_MAX(%rip)
	movl	%ebx, %eax
	shrl	$9, %eax
	incl	%eax
	movl	%eax, N_BLK(%rip)
	movl	$512, %eax
	cmpl	%eax, %ebx
	cmovbe	%ebx, %eax
	movl	%eax, N_THRD(%rip)
	leal	0(,%rbx,4), %eax
	movl	%eax, N_BYTES(%rip)
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movl	$1, %edi
	call	_Z8simulatej
	movl	$2, %edi
	call	_Z8simulatej
	xorl	%eax, %eax
	jmp	.L31
.L32:
	movq	(%rsi), %rdx
	movl	$2, %edi
	xorl	%eax, %eax
	leaq	.LC9(%rip), %rsi
	call	__printf_chk@PLT
	movl	$1, %eax
.L31:
	popq	%rdx
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2524:
	.size	main, .-main
	.section	.rodata.str1.1
.LC10:
	.string	"_Z8sim_gmemPfS_S_S_jj"
.LC11:
	.string	"_Z12sim_registerPfS_S_S_jj"
.LC12:
	.string	"precalc_xorwow_matrix"
.LC13:
	.string	"precalc_xorwow_offset_matrix"
.LC14:
	.string	"mrg32k3aM1"
.LC15:
	.string	"mrg32k3aM2"
.LC16:
	.string	"mrg32k3aM1SubSeq"
.LC17:
	.string	"mrg32k3aM2SubSeq"
.LC18:
	.string	"mrg32k3aM1Seq"
.LC19:
	.string	"mrg32k3aM2Seq"
.LC20:
	.string	"__cr_lgamma_table"
.LC21:
	.string	"c_phi"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2555:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC10(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z8sim_gmemPfS_S_S_jj(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC11(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z12sim_registerPfS_S_S_jj(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC12(%rip), %rdx
	movl	$102400, %r9d
	leaq	_ZL21precalc_xorwow_matrix(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC13(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$102400, %r9d
	leaq	_ZL28precalc_xorwow_offset_matrix(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC14(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$2304, %r9d
	leaq	_ZL10mrg32k3aM1(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	popq	%r8
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC15(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$2304, %r9d
	leaq	_ZL10mrg32k3aM2(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r9
	.cfi_def_cfa_offset 24
	popq	%r10
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC16(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$2016, %r9d
	leaq	_ZL16mrg32k3aM1SubSeq(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r11
	.cfi_def_cfa_offset 24
	popq	%rax
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC17(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$2016, %r9d
	leaq	_ZL16mrg32k3aM2SubSeq(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC18(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$2304, %r9d
	leaq	_ZL13mrg32k3aM1Seq(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC19(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$2304, %r9d
	leaq	_ZL13mrg32k3aM2Seq(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	popq	%r8
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC20(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$72, %r9d
	leaq	_ZL17__cr_lgamma_table(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r9
	.cfi_def_cfa_offset 24
	popq	%r10
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC21(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movl	$12, %r9d
	movq	%rdx, %rcx
	leaq	_ZL5c_phi(%rip), %rsi
	call	__cudaRegisterVar@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	popq	%r11
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2555:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.globl	N_BYTES_PARM
	.data
	.align 4
	.type	N_BYTES_PARM, @object
	.size	N_BYTES_PARM, 4
N_BYTES_PARM:
	.long	12
	.local	_ZL5c_phi
	.comm	_ZL5c_phi,12,8
	.globl	T_MAX
	.bss
	.align 4
	.type	T_MAX, @object
	.size	T_MAX, 4
T_MAX:
	.zero	4
	.globl	N_BYTES
	.align 4
	.type	N_BYTES, @object
	.size	N_BYTES, 4
N_BYTES:
	.zero	4
	.globl	N_THRD
	.align 4
	.type	N_THRD, @object
	.size	N_THRD, 4
N_THRD:
	.zero	4
	.globl	N_BLK
	.align 4
	.type	N_BLK, @object
	.size	N_BLK, 4
N_BLK:
	.zero	4
	.globl	N_SIMS
	.align 4
	.type	N_SIMS, @object
	.size	N_SIMS, 4
N_SIMS:
	.zero	4
	.local	_ZL17__cr_lgamma_table
	.comm	_ZL17__cr_lgamma_table,72,32
	.local	_ZL13mrg32k3aM2Seq
	.comm	_ZL13mrg32k3aM2Seq,2304,32
	.local	_ZL13mrg32k3aM1Seq
	.comm	_ZL13mrg32k3aM1Seq,2304,32
	.local	_ZL16mrg32k3aM2SubSeq
	.comm	_ZL16mrg32k3aM2SubSeq,2016,32
	.local	_ZL16mrg32k3aM1SubSeq
	.comm	_ZL16mrg32k3aM1SubSeq,2016,32
	.local	_ZL10mrg32k3aM2
	.comm	_ZL10mrg32k3aM2,2304,32
	.local	_ZL10mrg32k3aM1
	.comm	_ZL10mrg32k3aM1,2304,32
	.local	_ZL28precalc_xorwow_offset_matrix
	.comm	_ZL28precalc_xorwow_offset_matrix,102400,32
	.local	_ZL21precalc_xorwow_matrix
	.comm	_ZL21precalc_xorwow_matrix,102400,32
	.section	.rodata.cst4,"aM",@progbits,4
	.align 4
.LC3:
	.long	1061997773
	.align 4
.LC4:
	.long	1063675494
	.align 4
.LC5:
	.long	1066192077
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include <stdio.h>
#include <algorithm>
#include <cstdlib>
#include <hiprand/hiprand.h>
#include <hiprand/hiprand_kernel.h>

// In the following section, define the model Parameters
#define N_AR 3
#define START_X 0.800, 0.900, 1.100
#define PHI -0.315415, 0.427606, 0.189134
#define C 1.500
// End model parameters

unsigned int N_SIMS, N_BLK, N_THRD, N_BYTES, T_MAX;
const unsigned int MAX_THREADS = 512; // max threads per block 
__constant__ float c_phi[N_AR]; // autoregressive parameters as constant
unsigned int N_BYTES_PARM = N_AR * sizeof(float); // size of parameter constant

// Calculate and return mean of an array of floats
float calcMean(float *arr, unsigned int const n) {
	float sum = 0.0;
	for (int i=0; i<n; i++) {
		sum += arr[i];
	}
	return sum / n; 
}

__host__ hipEvent_t get_time(void) {
	hipEvent_t time;
	hipEventCreate(&time);
	hipEventRecord(time);
	return time;
}

// Simulate a AR(n) process saving temp results to registers
__global__ void sim_register(float *x0, float *x1, float *x2, float *x_out, 
							const unsigned int N, const unsigned int T) {
	unsigned int const tid = (blockIdx.x * blockDim.x) + threadIdx.x;
	
	if (tid < N) {
		hiprandState_t state; // initialize rand state
		hiprand_init(tid, 0, 0, &state); // set seed to thread index

		float r_x0 = x0[tid]; // Copy values of X to register
		float r_x1 = x1[tid];
		float r_x2 = x2[tid];
		float r_x; // initialize r_x
		
		float w; // white noise for AR process
		for (int t=0; t < T; t++) { // Simulate for T_MAX periods
			w = hiprand_normal(&state) / 2; // w ~ Normal(0, 0.5)
			r_x = C + c_phi[2]*r_x2 + c_phi[1]*r_x1 + c_phi[0]*r_x0 + w;
			r_x2 = r_x1;
			r_x1 = r_x0;
			r_x0 = r_x;
		}

		x_out[tid] = r_x; // save x as output
	}
}

// Simulate a AR(n) process saving work to global mem directly
__global__ void sim_gmem(float *x0, float *x1, float *x2, float *x_out, 
						const unsigned int N, const unsigned int T) {
	unsigned int const i = (blockIdx.x * blockDim.x) + threadIdx.x;
	
	if (i < N) {
		hiprandState_t state; // initialize rand state
		hiprand_init(i, 0, 0, &state); // set seed to thread index

		float w; // white noise for AR process
		for (int t=0; t < T; t++) { // Simulate for T_MAX periods
			w = hiprand_normal(&state) / 2; // w ~ Normal(0, 0.5)
			x_out[i] = C + c_phi[2]*x2[i] + c_phi[1]*x1[i] + c_phi[0]*x0[i] + w;
			x2[i] = x1[i];
			x1[i] = x0[i];
			x0[i] = x_out[i];
		}
	}
}

void simulate(const unsigned int type) {
	float *h_x0, *h_x1, *h_x2, *h_x; 
	h_x0 = (float*) malloc(N_BYTES); // allocate input
	h_x1 = (float*) malloc(N_BYTES); // allocate input
	h_x2 = (float*) malloc(N_BYTES); // allocate input
	h_x = (float*) malloc(N_BYTES); // allocate output 
		
	float start_x [N_AR] = {START_X};
	for (int i = 0; i < N_SIMS; i++) { // set all host Xs to the same number
		h_x0[i] = start_x[0];
		h_x1[i] = start_x[1];
		h_x2[i] = start_x[2];
	}
	
	float *d_x0, *d_x1, *d_x2, *d_out; // device memory for storing X
	hipMalloc((void **)&d_x0, N_BYTES); // allocate device input
	hipMalloc((void **)&d_x1, N_BYTES); // allocate device input
	hipMalloc((void **)&d_x2, N_BYTES); // allocate device input
	hipMalloc((void **)&d_out, N_BYTES); // allocate device output

	float h_phi [N_AR] = {PHI}; // constant for AR parms
	hipMemcpyToSymbol(HIP_SYMBOL(c_phi), h_phi, N_BYTES_PARM); // copy params to constant
	
	/**** Simulation *****/
	char *typeName;
	hipEvent_t start = get_time(); // start time 
	hipMemcpy(d_x0, h_x0, N_BYTES, hipMemcpyHostToDevice); //copy to device
	hipMemcpy(d_x1, h_x1, N_BYTES, hipMemcpyHostToDevice); //copy to device
	hipMemcpy(d_x2, h_x2, N_BYTES, hipMemcpyHostToDevice); //copy to device
	
	if (type == 1){ // if simulating with registers
		typeName = "registers";
		sim_register<<<N_BLK, N_THRD>>>(d_x0, d_x1, d_x2, d_out, N_SIMS, T_MAX); 
		
	} else { // if simulating with global memory 
		typeName = "global mem";
		sim_gmem<<<N_BLK, N_THRD>>>(d_x0, d_x1, d_x2, d_out, N_SIMS, T_MAX); 
	}	
	hipMemcpy(h_x, d_out, N_BYTES, hipMemcpyDeviceToHost ); // copy back
	hipEvent_t stop = get_time(); // stop time
	hipEventSynchronize(stop);
	
	// Calculate and print simulation results and timing
	float x_mu = calcMean(h_x, N_SIMS);
	float dur = 0;
	hipEventElapsedTime(&dur, start, stop);
	printf("\twith %s, result=%f, %.3f ms taken, \n", typeName, x_mu, dur);
	
	// Free up memory
	hipFree(d_x2); hipFree(d_x1); hipFree(d_x0); 
	hipFree(d_out); hipFree(c_phi);
	free(h_x0); free(h_x1); free(h_x2); free(h_x);
}

int main(int argc, char* argv[]) {
	if (argc == 3) { // get number of simulations based on CMDLINE input
		N_SIMS = atoi(argv[1]);
		T_MAX = atoi(argv[2]);
	} else {
		printf("Usage: %s [nSimulations] [maxTimePeriods].\n", argv[0]);
		return EXIT_FAILURE;
	}
	N_BLK = N_SIMS / MAX_THREADS + 1; // min of one block
	N_THRD = std::min(N_SIMS, MAX_THREADS); // num of threads per block
	N_BYTES = N_SIMS * sizeof(float); // size of array 
	printf("Running %u simulations over %u time periods...\n", N_SIMS, T_MAX);
	
	simulate(1); // simulating with registers
	simulate(2); // simulating with global memory
	return EXIT_SUCCESS;
}

	.text
	.file	"test_register.hip"
	.globl	_Z8calcMeanPfj                  # -- Begin function _Z8calcMeanPfj
	.type	_Z8calcMeanPfj,@function
_Z8calcMeanPfj:                         # @_Z8calcMeanPfj
	.cfi_startproc
# %bb.0:
	movl	%esi, %eax
	xorps	%xmm0, %xmm0
	testl	%esi, %esi
	je	.LBB0_3
# %bb.1:                                # %.lr.ph.preheader
	xorl	%ecx, %ecx
.LBB0_2:                                # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	addss	(%rdi,%rcx,4), %xmm0
	incq	%rcx
	cmpq	%rcx, %rax
	jne	.LBB0_2
.LBB0_3:                                # %._crit_edge
	cvtsi2ss	%rax, %xmm1
	divss	%xmm1, %xmm0
	retq
.Lfunc_end0:
	.size	_Z8calcMeanPfj, .Lfunc_end0-_Z8calcMeanPfj
	.cfi_endproc
                                        # -- End function
	.globl	_Z8get_timev                    # -- Begin function _Z8get_timev
	.type	_Z8get_timev,@function
_Z8get_timev:                           # @_Z8get_timev
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$16, %rsp
	.cfi_def_cfa_offset 32
	.cfi_offset %rbx, -16
	leaq	8(%rsp), %rbx
	movq	%rbx, %rdi
	callq	hipEventCreate
	movq	(%rbx), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	(%rbx), %rax
	addq	$16, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z8get_timev, .Lfunc_end1-_Z8get_timev
	.cfi_endproc
                                        # -- End function
	.globl	_Z27__device_stub__sim_registerPfS_S_S_jj # -- Begin function _Z27__device_stub__sim_registerPfS_S_S_jj
	.type	_Z27__device_stub__sim_registerPfS_S_S_jj,@function
_Z27__device_stub__sim_registerPfS_S_S_jj: # @_Z27__device_stub__sim_registerPfS_S_S_jj
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	12(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	8(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z12sim_registerPfS_S_S_jj, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z27__device_stub__sim_registerPfS_S_S_jj, .Lfunc_end2-_Z27__device_stub__sim_registerPfS_S_S_jj
	.cfi_endproc
                                        # -- End function
	.globl	_Z23__device_stub__sim_gmemPfS_S_S_jj # -- Begin function _Z23__device_stub__sim_gmemPfS_S_S_jj
	.type	_Z23__device_stub__sim_gmemPfS_S_S_jj,@function
_Z23__device_stub__sim_gmemPfS_S_S_jj:  # @_Z23__device_stub__sim_gmemPfS_S_S_jj
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	12(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	8(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z8sim_gmemPfS_S_S_jj, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	_Z23__device_stub__sim_gmemPfS_S_S_jj, .Lfunc_end3-_Z23__device_stub__sim_gmemPfS_S_S_jj
	.cfi_endproc
                                        # -- End function
	.globl	_Z8simulatej                    # -- Begin function _Z8simulatej
	.type	_Z8simulatej,@function
_Z8simulatej:                           # @_Z8simulatej
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$88, %rsp
	.cfi_def_cfa_offset 144
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%edi, 8(%rsp)                   # 4-byte Spill
	movl	N_BYTES(%rip), %ebp
	movq	%rbp, %rdi
	callq	malloc
	movq	%rax, %rbx
	movq	%rbp, %rdi
	callq	malloc
	movq	%rax, %r14
	movq	%rbp, %rdi
	callq	malloc
	movq	%rax, %r15
	movq	%rbp, %rdi
	callq	malloc
	movq	%rax, %r12
	movl	N_SIMS(%rip), %eax
	testq	%rax, %rax
	je	.LBB4_3
# %bb.1:                                # %.lr.ph.preheader
	xorl	%ecx, %ecx
.LBB4_2:                                # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	movl	$1061997773, (%rbx,%rcx,4)      # imm = 0x3F4CCCCD
	movl	$1063675494, (%r14,%rcx,4)      # imm = 0x3F666666
	movl	$1066192077, (%r15,%rcx,4)      # imm = 0x3F8CCCCD
	incq	%rcx
	cmpq	%rcx, %rax
	jne	.LBB4_2
.LBB4_3:                                # %._crit_edge
	leaq	40(%rsp), %r13
	movq	%r13, %rdi
	movq	%rbp, %rsi
	callq	hipMalloc
	movl	N_BYTES(%rip), %esi
	leaq	32(%rsp), %rdi
	callq	hipMalloc
	movl	N_BYTES(%rip), %esi
	leaq	24(%rsp), %rdi
	callq	hipMalloc
	movl	N_BYTES(%rip), %esi
	leaq	16(%rsp), %rdi
	callq	hipMalloc
	movabsq	$4529195350730309139, %rax      # imm = 0x3EDAEF2CBEA17E13
	leaq	76(%rsp), %rsi
	movq	%rax, (%rsi)
	movl	$1044491352, 8(%rsi)            # imm = 0x3E41AC58
	movl	N_BYTES_PARM(%rip), %edx
	movl	$c_phi, %edi
	xorl	%ecx, %ecx
	movl	$1, %r8d
	callq	hipMemcpyToSymbol
	leaq	56(%rsp), %rbp
	movq	%rbp, %rdi
	callq	hipEventCreate
	movq	(%rbp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	(%rbp), %rax
	movq	%rax, 64(%rsp)                  # 8-byte Spill
	movq	(%r13), %rdi
	movl	N_BYTES(%rip), %edx
	movq	%rbx, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	32(%rsp), %rax
	movq	(%rax), %rdi
	movl	N_BYTES(%rip), %edx
	movq	%r14, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	24(%rsp), %rax
	movq	(%rax), %rdi
	movl	N_BYTES(%rip), %edx
	movq	%r15, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movl	N_BLK(%rip), %edi
	movl	N_THRD(%rip), %edx
	btsq	$32, %rdi
	btsq	$32, %rdx
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	cmpl	$1, 8(%rsp)                     # 4-byte Folded Reload
	jne	.LBB4_6
# %bb.4:
	movl	$.L.str, %ecx
	movq	%rcx, 8(%rsp)                   # 8-byte Spill
	testl	%eax, %eax
	jne	.LBB4_8
# %bb.5:
	movq	40(%rsp), %rdi
	movq	32(%rsp), %rsi
	movq	24(%rsp), %rdx
	movq	16(%rsp), %rcx
	movl	N_SIMS(%rip), %r8d
	movl	T_MAX(%rip), %r9d
	callq	_Z27__device_stub__sim_registerPfS_S_S_jj
	jmp	.LBB4_8
.LBB4_6:
	movl	$.L.str.1, %ecx
	movq	%rcx, 8(%rsp)                   # 8-byte Spill
	testl	%eax, %eax
	jne	.LBB4_8
# %bb.7:
	movq	40(%rsp), %rdi
	movq	32(%rsp), %rsi
	movq	24(%rsp), %rdx
	movq	16(%rsp), %rcx
	movl	N_SIMS(%rip), %r8d
	movl	T_MAX(%rip), %r9d
	callq	_Z23__device_stub__sim_gmemPfS_S_S_jj
.LBB4_8:
	movq	16(%rsp), %rsi
	movl	N_BYTES(%rip), %edx
	movq	%r12, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	leaq	56(%rsp), %r13
	movq	%r13, %rdi
	callq	hipEventCreate
	movq	(%r13), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	(%r13), %r13
	movq	%r13, %rdi
	callq	hipEventSynchronize
	movl	N_SIMS(%rip), %eax
	xorps	%xmm1, %xmm1
	testq	%rax, %rax
	je	.LBB4_11
# %bb.9:                                # %.lr.ph.preheader.i
	xorl	%ecx, %ecx
.LBB4_10:                               # %.lr.ph.i
                                        # =>This Inner Loop Header: Depth=1
	addss	(%r12,%rcx,4), %xmm1
	incq	%rcx
	cmpq	%rcx, %rax
	jne	.LBB4_10
.LBB4_11:                               # %_Z8calcMeanPfj.exit
	cvtsi2ss	%rax, %xmm0
	divss	%xmm0, %xmm1
	movss	%xmm1, 52(%rsp)                 # 4-byte Spill
	leaq	56(%rsp), %rbp
	movl	$0, (%rbp)
	movq	%rbp, %rdi
	movq	64(%rsp), %rsi                  # 8-byte Reload
	movq	%r13, %rdx
	callq	hipEventElapsedTime
	xorps	%xmm0, %xmm0
	cvtss2sd	52(%rsp), %xmm0                 # 4-byte Folded Reload
	xorps	%xmm1, %xmm1
	cvtss2sd	(%rbp), %xmm1
	movl	$.L.str.2, %edi
	movq	8(%rsp), %rsi                   # 8-byte Reload
	movb	$2, %al
	callq	printf
	movq	24(%rsp), %rdi
	callq	hipFree
	movq	32(%rsp), %rdi
	callq	hipFree
	movq	40(%rsp), %rdi
	callq	hipFree
	movq	16(%rsp), %rdi
	callq	hipFree
	movl	$c_phi, %edi
	callq	hipFree
	movq	%rbx, %rdi
	callq	free
	movq	%r14, %rdi
	callq	free
	movq	%r15, %rdi
	callq	free
	movq	%r12, %rdi
	callq	free
	addq	$88, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end4:
	.size	_Z8simulatej, .Lfunc_end4-_Z8simulatej
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%r14
	.cfi_def_cfa_offset 16
	pushq	%rbx
	.cfi_def_cfa_offset 24
	pushq	%rax
	.cfi_def_cfa_offset 32
	.cfi_offset %rbx, -24
	.cfi_offset %r14, -16
	movq	%rsi, %rbx
	cmpl	$3, %edi
	jne	.LBB5_2
# %bb.1:
	movq	8(%rbx), %rdi
	callq	atoi
	movl	%eax, %r14d
	movl	%eax, N_SIMS(%rip)
	movq	16(%rbx), %rdi
	callq	atoi
	movl	%r14d, %ecx
	shrl	$9, %ecx
	incl	%ecx
	movl	%ecx, N_BLK(%rip)
	movl	$512, %ecx                      # imm = 0x200
	cmpl	%ecx, %r14d
	cmovbl	%r14d, %ecx
	movl	%eax, T_MAX(%rip)
	movl	%ecx, N_THRD(%rip)
	leal	(,%r14,4), %ecx
	movl	%ecx, N_BYTES(%rip)
	xorl	%ebx, %ebx
	movl	$.L.str.4, %edi
	movl	%r14d, %esi
	movl	%eax, %edx
	xorl	%eax, %eax
	callq	printf
	movl	$1, %edi
	callq	_Z8simulatej
	movl	$2, %edi
	callq	_Z8simulatej
	jmp	.LBB5_3
.LBB5_2:
	movq	(%rbx), %rsi
	movl	$.L.str.3, %edi
	xorl	%eax, %eax
	callq	printf
	movl	$1, %ebx
.LBB5_3:
	movl	%ebx, %eax
	addq	$8, %rsp
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end5:
	.size	main, .Lfunc_end5-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB6_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB6_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z12sim_registerPfS_S_S_jj, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z8sim_gmemPfS_S_S_jj, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$0, 8(%rsp)
	movl	$1, (%rsp)
	movl	$c_phi, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movl	$12, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	callq	__hipRegisterVar
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end6:
	.size	__hip_module_ctor, .Lfunc_end6-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB7_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB7_2:
	retq
.Lfunc_end7:
	.size	__hip_module_dtor, .Lfunc_end7-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	N_SIMS,@object                  # @N_SIMS
	.bss
	.globl	N_SIMS
	.p2align	2, 0x0
N_SIMS:
	.long	0                               # 0x0
	.size	N_SIMS, 4

	.type	N_BLK,@object                   # @N_BLK
	.globl	N_BLK
	.p2align	2, 0x0
N_BLK:
	.long	0                               # 0x0
	.size	N_BLK, 4

	.type	N_THRD,@object                  # @N_THRD
	.globl	N_THRD
	.p2align	2, 0x0
N_THRD:
	.long	0                               # 0x0
	.size	N_THRD, 4

	.type	N_BYTES,@object                 # @N_BYTES
	.globl	N_BYTES
	.p2align	2, 0x0
N_BYTES:
	.long	0                               # 0x0
	.size	N_BYTES, 4

	.type	T_MAX,@object                   # @T_MAX
	.globl	T_MAX
	.p2align	2, 0x0
T_MAX:
	.long	0                               # 0x0
	.size	T_MAX, 4

	.type	c_phi,@object                   # @c_phi
	.local	c_phi
	.comm	c_phi,12,4
	.type	N_BYTES_PARM,@object            # @N_BYTES_PARM
	.data
	.globl	N_BYTES_PARM
	.p2align	2, 0x0
N_BYTES_PARM:
	.long	12                              # 0xc
	.size	N_BYTES_PARM, 4

	.type	_Z12sim_registerPfS_S_S_jj,@object # @_Z12sim_registerPfS_S_S_jj
	.section	.rodata,"a",@progbits
	.globl	_Z12sim_registerPfS_S_S_jj
	.p2align	3, 0x0
_Z12sim_registerPfS_S_S_jj:
	.quad	_Z27__device_stub__sim_registerPfS_S_S_jj
	.size	_Z12sim_registerPfS_S_S_jj, 8

	.type	_Z8sim_gmemPfS_S_S_jj,@object   # @_Z8sim_gmemPfS_S_S_jj
	.globl	_Z8sim_gmemPfS_S_S_jj
	.p2align	3, 0x0
_Z8sim_gmemPfS_S_S_jj:
	.quad	_Z23__device_stub__sim_gmemPfS_S_S_jj
	.size	_Z8sim_gmemPfS_S_S_jj, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"registers"
	.size	.L.str, 10

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"global mem"
	.size	.L.str.1, 11

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"\twith %s, result=%f, %.3f ms taken, \n"
	.size	.L.str.2, 38

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"Usage: %s [nSimulations] [maxTimePeriods].\n"
	.size	.L.str.3, 44

	.type	.L.str.4,@object                # @.str.4
.L.str.4:
	.asciz	"Running %u simulations over %u time periods...\n"
	.size	.L.str.4, 48

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z12sim_registerPfS_S_S_jj"
	.size	.L__unnamed_1, 27

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z8sim_gmemPfS_S_S_jj"
	.size	.L__unnamed_2, 22

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"c_phi"
	.size	.L__unnamed_3, 6

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z27__device_stub__sim_registerPfS_S_S_jj
	.addrsig_sym _Z23__device_stub__sim_gmemPfS_S_S_jj
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym c_phi
	.addrsig_sym _Z12sim_registerPfS_S_S_jj
	.addrsig_sym _Z8sim_gmemPfS_S_S_jj
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z12sim_registerPfS_S_S_jj ; -- Begin function _Z12sim_registerPfS_S_S_jj
	.globl	_Z12sim_registerPfS_S_S_jj
	.p2align	8
	.type	_Z12sim_registerPfS_S_S_jj,@function
_Z12sim_registerPfS_S_S_jj:             ; @_Z12sim_registerPfS_S_S_jj
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x34
	s_load_b64 s[8:9], s[0:1], 0x20
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[2:3], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_u32_e64 s8, v2
	s_cbranch_execz .LBB0_10
; %bb.1:
	s_load_b256 s[0:7], s[0:1], 0x0
	v_mov_b32_e32 v3, 0
	s_cmp_eq_u32 s9, 0
	s_mov_b32 s8, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[2:3]
	s_cbranch_scc1 .LBB0_8
; %bb.2:                                ; %.lr.ph
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, s4, v0
	v_add_co_ci_u32_e32 v4, vcc_lo, s5, v1, vcc_lo
	v_add_co_u32 v5, vcc_lo, s2, v0
	v_add_co_ci_u32_e32 v6, vcc_lo, s3, v1, vcc_lo
	v_add_co_u32 v7, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v8, vcc_lo, s1, v1, vcc_lo
	global_load_b32 v4, v[3:4], off
	global_load_b32 v3, v[5:6], off
	global_load_b32 v11, v[7:8], off
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, c_phi@rel32@lo+4
	s_addc_u32 s1, s1, c_phi@rel32@hi+12
	s_clause 0x1
	s_load_b64 s[2:3], s[0:1], 0x0
	s_load_b32 s1, s[0:1], 0x8
	v_xor_b32_e32 v2, 0x2c7f967f, v2
	v_mov_b32_e32 v7, 0xa96f9d04
                                        ; implicit-def: $vgpr10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v5, 0x493c4aa1, v2
	v_add_nc_u32_e32 v2, 0x8ac25218, v5
	v_add_nc_u32_e32 v6, 0x583f19, v5
	v_xor_b32_e32 v8, 0x159a55e5, v5
	v_add_nc_u32_e32 v13, 0x75bcd15, v5
	v_mov_b32_e32 v5, 0x8f14727c
.LBB0_3:                                ; =>This Inner Loop Header: Depth=1
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_4)
	v_mov_b32_e32 v9, v11
	s_cmp_lg_u32 s8, 0
	s_mov_b32 s8, 0
	s_cbranch_scc0 .LBB0_5
; %bb.4:                                ;   in Loop: Header=BB0_3 Depth=1
	v_dual_mov_b32 v12, v7 :: v_dual_mov_b32 v7, v13
	v_mov_b32_e32 v11, v10
	s_branch .LBB0_6
.LBB0_5:                                ;   in Loop: Header=BB0_3 Depth=1
	v_lshrrev_b32_e32 v10, 2, v13
	v_lshlrev_b32_e32 v11, 4, v6
	s_mov_b32 s8, 1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v10, v10, v13
	v_lshlrev_b32_e32 v12, 1, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v11, v12, v11
	v_xor3_b32 v10, v11, v10, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add3_u32 v11, v2, v10, 0x587c5
	v_add_nc_u32_e32 v2, 0xb0f8a, v2
	v_cvt_f32_u32_e32 v11, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmaak_f32 v11, 0x2f800000, v11, 0x2f800000
	v_cmp_gt_f32_e32 vcc_lo, 0x800000, v11
	v_cndmask_b32_e64 v12, 1.0, 0x4f800000, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v11, v11, v12
	v_log_f32_e32 v11, v11
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v12, 0x3f317217, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v13, 0x3f317217, v11, -v12
	v_fmac_f32_e32 v13, 0x3377d1cf, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_add_f32_e32 v12, v12, v13
	v_cndmask_b32_e64 v13, 0, 0x41b17218, vcc_lo
	v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v11|
	v_cndmask_b32_e32 v11, v11, v12, vcc_lo
	v_lshrrev_b32_e32 v12, 2, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v11, v11, v13
	v_xor_b32_e32 v8, v12, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v11, -2.0, v11 :: v_dual_lshlrev_b32 v12, 1, v8
	v_mul_f32_e32 v13, 0x4f800000, v11
	v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v11, v11, v13, vcc_lo
	v_lshlrev_b32_e32 v13, 4, v10
	v_xor_b32_e32 v12, v12, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor3_b32 v13, v12, v8, v10
	v_add_nc_u32_e32 v12, v13, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f32_u32_e32 v12, v12
	v_fmaak_f32 v12, 0x30c90fdb, v12, 0x30c90fdb
	v_sqrt_f32_e32 v14, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v12, 0.15915494, v12
	s_waitcnt_depctr 0xfff
	v_add_nc_u32_e32 v8, -1, v14
	v_add_nc_u32_e32 v15, 1, v14
	v_fma_f32 v16, -v8, v14, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v17, -v15, v14, v11
	v_cmp_ge_f32_e64 s0, 0, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v8, v14, v8, s0
	v_cmp_lt_f32_e64 s0, 0, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v8, v8, v15, s0
	v_sin_f32_e32 v15, v12
	v_mul_f32_e32 v14, 0x37800000, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v8, v8, v14, vcc_lo
	v_cos_f32_e32 v14, v12
	v_cmp_class_f32_e64 vcc_lo, v11, 0x260
	v_cndmask_b32_e32 v16, v8, v11, vcc_lo
	v_mov_b32_e32 v12, v6
	v_dual_mov_b32 v8, v5 :: v_dual_mov_b32 v5, v10
	s_delay_alu instid0(TRANS32_DEP_2) | instid1(VALU_DEP_3)
	v_dual_mov_b32 v6, v13 :: v_dual_mul_f32 v11, v16, v15
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v10, v16, v14
.LBB0_6:                                ; %_Z14hiprand_normalI12hiprandStateEfPT_.exit
                                        ;   in Loop: Header=BB0_3 Depth=1
	s_waitcnt lgkmcnt(0)
	v_mul_f32_e32 v4, s1, v4
	s_add_i32 s9, s9, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_cmp_eq_u32 s9, 0
	v_cvt_f64_f32_e32 v[13:14], v4
	v_mul_f32_e32 v4, s3, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cvt_f64_f32_e32 v[15:16], v4
	v_mul_f32_e32 v4, s2, v9
	v_cvt_f64_f32_e32 v[17:18], v4
	v_mul_f32_e32 v4, 0.5, v11
	v_add_f64 v[13:14], 0x3ff80000, v[13:14]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[13:14], v[13:14], v[15:16]
	v_cvt_f64_f32_e32 v[15:16], v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[13:14], v[13:14], v[17:18]
	v_add_f64 v[13:14], v[13:14], v[15:16]
	s_delay_alu instid0(VALU_DEP_1)
	v_cvt_f32_f64_e32 v11, v[13:14]
	s_cbranch_scc1 .LBB0_9
; %bb.7:                                ;   in Loop: Header=BB0_3 Depth=1
	v_dual_mov_b32 v4, v3 :: v_dual_mov_b32 v3, v9
	v_mov_b32_e32 v13, v7
	v_mov_b32_e32 v7, v12
	s_branch .LBB0_3
.LBB0_8:
                                        ; implicit-def: $vgpr11
.LBB0_9:                                ; %Flow60
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s6, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
	global_store_b32 v[0:1], v11, off
.LBB0_10:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z12sim_registerPfS_S_S_jj
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 19
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z12sim_registerPfS_S_S_jj, .Lfunc_end0-_Z12sim_registerPfS_S_S_jj
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 916
; NumSgprs: 18
; NumVgprs: 19
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 19
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z8sim_gmemPfS_S_S_jj   ; -- Begin function _Z8sim_gmemPfS_S_S_jj
	.globl	_Z8sim_gmemPfS_S_S_jj
	.p2align	8
	.type	_Z8sim_gmemPfS_S_S_jj,@function
_Z8sim_gmemPfS_S_S_jj:                  ; @_Z8sim_gmemPfS_S_S_jj
; %bb.0:
	s_clause 0x1
	s_load_b32 s4, s[0:1], 0x34
	s_load_b64 s[2:3], s[0:1], 0x20
	s_waitcnt lgkmcnt(0)
	s_and_b32 s4, s4, 0xffff
	s_cmp_lg_u32 s3, 0
	v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
	s_cselect_b32 s4, -1, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_cmp_gt_u32_e32 vcc_lo, s2, v1
	s_mov_b32 s2, 0
	s_and_b32 s4, vcc_lo, s4
	s_and_saveexec_b32 s5, s4
	s_cbranch_execz .LBB1_6
; %bb.1:                                ; %.lr.ph
	s_load_b256 s[8:15], s[0:1], 0x0
	v_xor_b32_e32 v0, 0x2c7f967f, v1
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, c_phi@rel32@lo+4
	s_addc_u32 s1, s1, c_phi@rel32@hi+12
	s_clause 0x1
	s_load_b64 s[4:5], s[0:1], 0x0
	s_load_b32 s1, s[0:1], 0x8
	v_mov_b32_e32 v11, 0x8f14727c
	v_mul_lo_u32 v0, 0x493c4aa1, v0
	v_mov_b32_e32 v2, 0
	v_mov_b32_e32 v10, 0xa96f9d04
                                        ; implicit-def: $vgpr14
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v9, 0x583f19, v0
	v_lshlrev_b64 v[6:7], 2, v[1:2]
	v_add_nc_u32_e32 v8, 0x8ac25218, v0
	v_xor_b32_e32 v12, 0x159a55e5, v0
	v_add_nc_u32_e32 v13, 0x75bcd15, v0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_u32 v0, vcc_lo, s12, v6
	v_add_co_ci_u32_e32 v1, vcc_lo, s13, v7, vcc_lo
	v_add_co_u32 v2, vcc_lo, s10, v6
	v_add_co_ci_u32_e32 v3, vcc_lo, s11, v7, vcc_lo
	v_add_co_u32 v4, vcc_lo, s8, v6
	v_add_co_ci_u32_e32 v5, vcc_lo, s9, v7, vcc_lo
	v_add_co_u32 v6, vcc_lo, s14, v6
	v_add_co_ci_u32_e32 v7, vcc_lo, s15, v7, vcc_lo
.LBB1_2:                                ; =>This Inner Loop Header: Depth=1
	s_cmp_lg_u32 s2, 0
	s_mov_b32 s2, 0
	s_cbranch_scc0 .LBB1_4
; %bb.3:                                ;   in Loop: Header=BB1_2 Depth=1
	v_mov_b32_e32 v15, v14
	s_branch .LBB1_5
.LBB1_4:                                ;   in Loop: Header=BB1_2 Depth=1
	v_lshrrev_b32_e32 v14, 2, v13
	s_mov_b32 s2, 1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v13, v14, v13
	v_lshlrev_b32_e32 v14, 4, v9
	v_lshlrev_b32_e32 v15, 1, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v14, v15, v14
	v_xor3_b32 v14, v14, v13, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add3_u32 v13, v8, v14, 0x587c5
	v_add_nc_u32_e32 v8, 0xb0f8a, v8
	v_cvt_f32_u32_e32 v13, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmaak_f32 v13, 0x2f800000, v13, 0x2f800000
	v_cmp_gt_f32_e32 vcc_lo, 0x800000, v13
	v_cndmask_b32_e64 v15, 1.0, 0x4f800000, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v13, v13, v15
	v_log_f32_e32 v13, v13
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v15, 0x3f317217, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v16, 0x3f317217, v13, -v15
	v_fmac_f32_e32 v16, 0x3377d1cf, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_add_f32_e32 v15, v15, v16
	v_cndmask_b32_e64 v16, 0, 0x41b17218, vcc_lo
	v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v13|
	v_cndmask_b32_e32 v13, v13, v15, vcc_lo
	v_lshrrev_b32_e32 v15, 2, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v13, v13, v16
	v_xor_b32_e32 v12, v15, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v13, -2.0, v13
	v_mul_f32_e32 v16, 0x4f800000, v13
	v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v13
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b32_e32 v15, 1, v12
	v_dual_cndmask_b32 v13, v13, v16 :: v_dual_lshlrev_b32 v16, 4, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sqrt_f32_e32 v17, v13
	v_xor_b32_e32 v15, v15, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_3)
	v_xor3_b32 v15, v15, v12, v14
	s_waitcnt_depctr 0xfff
	v_add_nc_u32_e32 v18, 1, v17
	v_add_nc_u32_e32 v12, -1, v17
	v_add_nc_u32_e32 v16, v15, v8
	v_fma_f32 v20, -v18, v17, v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v19, -v12, v17, v13
	v_cmp_ge_f32_e64 s0, 0, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v12, v17, v12, s0
	v_cmp_lt_f32_e64 s0, 0, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v12, v12, v18, s0
	v_mul_f32_e32 v17, 0x37800000, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v12, v12, v17 :: v_dual_mov_b32 v17, v9
	v_cvt_f32_u32_e32 v16, v16
	v_cmp_class_f32_e64 vcc_lo, v13, 0x260
	v_dual_mov_b32 v9, v15 :: v_dual_fmaak_f32 v16, 0x30c90fdb, v16, 0x30c90fdb
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v19, v12, v13 :: v_dual_mov_b32 v12, v11
	v_dual_mov_b32 v11, v14 :: v_dual_mul_f32 v16, 0.15915494, v16
	s_delay_alu instid0(VALU_DEP_1)
	v_sin_f32_e32 v18, v16
	v_cos_f32_e32 v16, v16
	v_dual_mov_b32 v13, v10 :: v_dual_mov_b32 v10, v17
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v15, v19, v18
	v_mul_f32_e32 v14, v19, v16
.LBB1_5:                                ; %_Z14hiprand_normalI12hiprandStateEfPT_.exit
                                        ;   in Loop: Header=BB1_2 Depth=1
	global_load_b32 v16, v[0:1], off
	global_load_b32 v18, v[2:3], off
	global_load_b32 v20, v[4:5], off
	s_add_i32 s3, s3, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u32 s3, 0
	s_waitcnt vmcnt(2)
	v_mul_f32_e32 v16, s1, v16
	s_waitcnt vmcnt(1)
	v_mul_f32_e32 v18, s5, v18
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v20, s4, v20
	v_cvt_f64_f32_e32 v[16:17], v16
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cvt_f64_f32_e32 v[18:19], v18
	v_cvt_f64_f32_e32 v[20:21], v20
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[16:17], 0x3ff80000, v[16:17]
	v_add_f64 v[16:17], v[16:17], v[18:19]
	v_mul_f32_e32 v18, 0.5, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[15:16], v[16:17], v[20:21]
	v_cvt_f64_f32_e32 v[17:18], v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[15:16], v[15:16], v[17:18]
	v_cvt_f32_f64_e32 v15, v[15:16]
	global_store_b32 v[6:7], v15, off
	global_load_b32 v15, v[2:3], off
	s_waitcnt vmcnt(0)
	global_store_b32 v[0:1], v15, off
	global_load_b32 v15, v[4:5], off
	s_waitcnt vmcnt(0)
	global_store_b32 v[2:3], v15, off
	global_load_b32 v15, v[6:7], off
	s_waitcnt vmcnt(0)
	global_store_b32 v[4:5], v15, off
	s_cbranch_scc1 .LBB1_2
.LBB1_6:                                ; %.loopexit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z8sim_gmemPfS_S_S_jj
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 22
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z8sim_gmemPfS_S_S_jj, .Lfunc_end1-_Z8sim_gmemPfS_S_S_jj
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 940
; NumSgprs: 18
; NumVgprs: 22
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 22
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.protected	c_phi                   ; @c_phi
	.type	c_phi,@object
	.section	.bss,"aw",@nobits
	.globl	c_phi
	.p2align	2, 0x0
c_phi:
	.zero	12
	.size	c_phi, 12

	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym c_phi
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         36
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         44
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         52
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         54
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         56
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         58
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         60
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         62
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         104
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 296
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z12sim_registerPfS_S_S_jj
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z12sim_registerPfS_S_S_jj.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     19
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         36
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         44
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         52
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         54
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         56
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         58
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         60
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         62
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         104
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 296
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z8sim_gmemPfS_S_S_jj
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z8sim_gmemPfS_S_S_jj.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     22
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
