/**********************************************************
* This code is intended for for computing multiplication  *
* for sub-product tree.                                   *
*             2*poly_length  <= T           *
* According to this constraint subproduct tree level      *
* where poly_length is not more than 129 is possible by   *
*  this code.
*ceil((poly_on_layer*0.5)/(floor(T/2*poly_length)) < 2^16 *
***********************************************************/

#include<iostream>
#include <ctime>
#include<cmath>

#define BASE_1 31

using namespace std;

const int Tmul = 512;
/***************************************************************
* one thread is responsible for computing one coefficient of c *
****************************************************************/

typedef int            sfixn;
typedef unsigned int   usfixn;


__device__ __host__ __inline__ 
sfixn add_mod(sfixn a, sfixn b, sfixn P) {
    sfixn r = a + b;
    r -= P;
    r += (r >> BASE_1) & P;
    return r;
}

__device__ __host__ __inline__ 
sfixn mul_mod(sfixn a, sfixn b, int P) {
    double ninv = 1 / (double)P;
    sfixn q  = (sfixn) ((((double) a) * ((double) b)) * ninv);
    sfixn res = a * b - q * P;
    res += (res >> BASE_1) & P;
    res -= 	P;
    res += (res >> BASE_1) & P;
    return res;
}




__global__ void listPlainMulGpu( sfixn *Mgpu, int start_offset, int length_poly, int poly_on_layer, int threadsForAmul, int mulInThreadBlock, int p)
{
	__shared__ sfixn sM[2*Tmul];	
	int mulID= ((threadIdx.x/threadsForAmul) + blockIdx.x*mulInThreadBlock);
	
	if( mulID < (poly_on_layer/2) && threadIdx.x < threadsForAmul*mulInThreadBlock)
	{

		int j = start_offset + ( mulID* length_poly*2);		
		int q = start_offset + ( poly_on_layer*length_poly) + ( mulID*(2*length_poly-1));

		int t = (threadIdx.x/threadsForAmul);
		int u = threadIdx.x % threadsForAmul;

		int s = t*(4*length_poly-1);
		int k = s + length_poly;
		int l = k + length_poly;
		int c = l+u;
		int a, b, i;

		sM[s+u] = Mgpu[j + u];
		__syncthreads();
		
		if(u != (2*length_poly-1) )
		{
			if(u < length_poly)
			{
				a = s;
				b = k + u;			
				sM[c] =  mul_mod(sM[a],sM[b],p);
				++a; --b;
				for(i = 0; i < u; ++i, ++a, --b)
					sM[c] =  add_mod(mul_mod(sM[a],sM[b],p),sM[c] ,p);
				/*
				Mgpu[j + u] = i;
				*/

				Mgpu[q+u] = sM[c];				
			}
			else
			{
				b = l - 1;
				a = (u - length_poly) + 1 + s;
				sM[c] =  mul_mod(sM[a],sM[b],p);
				++a; --b;
				
				int tempU = u;
				u = (2*length_poly-2) - u;
				for(i = 0; i < u; ++i, ++a, --b)
					sM[c] =  add_mod(mul_mod(sM[a],sM[b],p),sM[c] ,p);
				/*
				Mgpu[j + u] = i;
				*/

				Mgpu[q+tempU] = sM[c];			
			}	
			
	
		}/*
		else			
		{		
			Mgpu[j + u] = -1;				
		}*/
	}		
}



sfixn add_modCPU(sfixn a, sfixn b, sfixn P) {
    sfixn r = a + b;
    r -= P;
    r += (r >> BASE_1) & P;
    return r;
}


sfixn mul_modCPU(sfixn a, sfixn b, int P) {
    double ninv = 1 / (double)P;
    sfixn q  = (sfixn) ((((double) a) * ((double) b)) * ninv);
    sfixn res = a * b - q * P;
    res += (res >> BASE_1) & P;
    res -= 	P;
    res += (res >> BASE_1) & P;
    return res;
}

void list_mul(sfixn *M , int n, int start_offset, int length_poly, int poly_on_layer, int result_offset, int p)
{
	/********************************************************
	* Number of threads responsible for one multiplication  *
	*********************************************************/	
	int threadsForAmul = 2*length_poly;

	/************************************************
	* Number of multiplications in one thread block *
	*************************************************/
	int mulInThreadBlock = (int)floor((double)Tmul/(double)threadsForAmul);

	/****************************
	* Number of blocks required *
	****************************/
	int blockNo = (int)ceil( ((double)poly_on_layer/(double) mulInThreadBlock)*0.5  );	

	sfixn *Mgpu;
	cudaMalloc((void **)&Mgpu, sizeof(sfixn)*n);
	cudaThreadSynchronize();
	cudaMemcpy(Mgpu, M, sizeof(sfixn)*n, cudaMemcpyHostToDevice);
	cudaThreadSynchronize();



	cudaEvent_t start, stop;
	cudaEventCreate(&start);
        cudaEventCreate(&stop);
	cudaEventRecord(start, 0);

	
	listPlainMulGpu<<<blockNo, Tmul>>>(Mgpu, start_offset, length_poly, poly_on_layer, threadsForAmul, mulInThreadBlock, p);
	
	cudaThreadSynchronize();

	cudaEventRecord(stop, 0);
        cudaEventSynchronize(stop);
        float outerTime;
        cudaEventElapsedTime(&outerTime, start, stop);
	cout<<outerTime<<" miliseconds"<<endl;


	cudaFree(Mgpu);  
	/*
	cout<<"threadsForAmul: "<<threadsForAmul<<" mulInThreadBlock: "<<mulInThreadBlock<<" blockNo: " <<blockNo<<endl;
	int i, j, k, l, q, a, b, c;
	for(i = 0; i < poly_on_layer/2; ++i )
	{
		j = start_offset + 2*i*length_poly;
		k = j + length_poly;
		l = k + length_poly;		
		q = result_offset + i*(2*length_poly -1);
		for(c = q; c < q+(2*length_poly -1); ++c)		
			M[c] = 0;
		for(a = j; a < k; ++a)
		{
			c = q;
			for(b = k; b < l; ++b, ++c)
			{
				M[c] = add_modCPU(mul_modCPU(M[a], M[b], p), M[c], p);				 
			}
			++q;		
		}
	}

	//
	sfixn *temp = new sfixn[n];
	cudaMemcpy(temp, Mgpu, sizeof(sfixn)*n, cudaMemcpyDeviceToHost);
	//
	cudaFree(Mgpu);        
	//	


	for(i = 0; i < n; ++i)
	{	
		if(M[i] != temp[i])
		{	
			cout<<i<<" "<<M[i]<<" "<<temp[i]<<endl;
			break;
		}
	}
	cout<<endl;
	
	delete [] temp;
	//	
	*/
}



int main(int argc, char *argv[])
{	
	int p= 7, start_offset = 0, length_poly = 4, poly_on_layer = 4, result_offset ;	

	if (argc > 1) start_offset = atoi(argv[1]);
	if (argc > 2) length_poly = atoi(argv[2]);
        if (argc > 3) poly_on_layer = atoi(argv[3]);
	if (argc > 4) p = atoi(argv[4]);
	
	result_offset = start_offset + length_poly*poly_on_layer;
	

	/**************************************
	* poly_on_layer MUST BE DIVISIBLE BY 2 *
	***************************************/
	int n, i;
	n = result_offset + (2*length_poly-1)*(poly_on_layer/2);	
	sfixn *M = new int[n];
	
	
	cout<<endl;
	for(i = start_offset; i < result_offset; ++i)
		M[i] = rand()% p;
		
			
	
	
	
	cout<<endl;
	
	cout<<p<<" "<<start_offset<<" "<<length_poly<<" "<<poly_on_layer<<" "<<result_offset<<" "<<n<<endl;
	/*
	for(i = 0; i < n; ++i)	
		cout<<M[i]<<" ";
	cout<<endl;	
	*/
		
	list_mul(M , n, start_offset, length_poly, poly_on_layer, result_offset, p );
	
		

	delete [] M;
	
	return 0;
}
	
	

	.file	"tmpxft_0025631b_00000000-6_list_plain_mul.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3643:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3643:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z10add_modCPUiii
	.type	_Z10add_modCPUiii, @function
_Z10add_modCPUiii:
.LFB3637:
	.cfi_startproc
	endbr64
	addl	%esi, %edi
	subl	%edx, %edi
	movl	%edi, %eax
	sarl	$31, %eax
	andl	%edx, %eax
	addl	%edi, %eax
	ret
	.cfi_endproc
.LFE3637:
	.size	_Z10add_modCPUiii, .-_Z10add_modCPUiii
	.globl	_Z10mul_modCPUiii
	.type	_Z10mul_modCPUiii, @function
_Z10mul_modCPUiii:
.LFB3638:
	.cfi_startproc
	endbr64
	cvtsi2sdl	%esi, %xmm1
	movl	%edi, %eax
	cvtsi2sdl	%edi, %xmm0
	cvtsi2sdl	%edx, %xmm2
	imull	%esi, %eax
	mulsd	%xmm1, %xmm0
	movsd	.LC0(%rip), %xmm1
	divsd	%xmm2, %xmm1
	mulsd	%xmm1, %xmm0
	cvttsd2sil	%xmm0, %ecx
	imull	%edx, %ecx
	subl	%ecx, %eax
	movl	%eax, %ecx
	sarl	$31, %ecx
	andl	%edx, %ecx
	addl	%eax, %ecx
	subl	%edx, %ecx
	movl	%ecx, %eax
	sarl	$31, %eax
	andl	%edx, %eax
	addl	%ecx, %eax
	ret
	.cfi_endproc
.LFE3638:
	.size	_Z10mul_modCPUiii, .-_Z10mul_modCPUiii
	.globl	_Z41__device_stub__Z15listPlainMulGpuPiiiiiiiPiiiiiii
	.type	_Z41__device_stub__Z15listPlainMulGpuPiiiiiiiPiiiiiii, @function
_Z41__device_stub__Z15listPlainMulGpuPiiiiiiiPiiiiiii:
.LFB3665:
	.cfi_startproc
	endbr64
	subq	$168, %rsp
	.cfi_def_cfa_offset 176
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rdi
	movl	%esi, 20(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 16(%rsp)
	leaq	32(%rsp), %rdx
	movl	%ecx, 12(%rsp)
	leaq	40(%rsp), %rcx
	movl	%r8d, 8(%rsp)
	movl	%r9d, 4(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 152(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	176(%rsp), %rax
	movq	%rax, 144(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L4
	pushq	40(%rsp)
	.cfi_def_cfa_offset 184
	leaq	_Z15listPlainMulGpuPiiiiiii(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 192
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 184
	popq	%rdx
	.cfi_def_cfa_offset 176
.L4:
	movq	152(%rsp), %rax
	subq	%fs:40, %rax
	je	.L6
	call	__stack_chk_fail@PLT
.L6:
	addq	$168, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3665:
	.size	_Z41__device_stub__Z15listPlainMulGpuPiiiiiiiPiiiiiii, .-_Z41__device_stub__Z15listPlainMulGpuPiiiiiiiPiiiiiii
	.globl	_Z15listPlainMulGpuPiiiiiii
	.type	_Z15listPlainMulGpuPiiiiiii, @function
_Z15listPlainMulGpuPiiiiiii:
.LFB3666:
	.cfi_startproc
	endbr64
	jmp	_Z41__device_stub__Z15listPlainMulGpuPiiiiiiiPiiiiiii
	.cfi_endproc
.LFE3666:
	.size	_Z15listPlainMulGpuPiiiiiii, .-_Z15listPlainMulGpuPiiiiiii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC3:
	.string	" miliseconds"
	.text
	.globl	_Z8list_mulPiiiiiii
	.type	_Z8list_mulPiiiiiii, @function
_Z8list_mulPiiiiiii:
.LFB3639:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	leal	(%rcx,%rcx), %r15d
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	cvtsi2sdl	%r15d, %xmm1
	movq	%rdi, %r14
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movl	%r8d, %r12d
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movl	%ecx, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movslq	%esi, %rbx
	salq	$2, %rbx
	subq	$88, %rsp
	.cfi_def_cfa_offset 144
	movsd	.LC1(%rip), %xmm0
	movl	%edx, 4(%rsp)
	divsd	%xmm1, %xmm0
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	xorl	%eax, %eax
	call	floor@PLT
	cvttsd2sil	%xmm0, %r13d
	cvtsi2sdl	%r12d, %xmm0
	cvtsi2sdl	%r13d, %xmm1
	divsd	%xmm1, %xmm0
	mulsd	.LC2(%rip), %xmm0
	call	ceil@PLT
	leaq	24(%rsp), %rdi
	movq	%rbx, %rsi
	movsd	%xmm0, 8(%rsp)
	call	cudaMalloc@PLT
	call	cudaThreadSynchronize@PLT
	movq	24(%rsp), %rdi
	movq	%rbx, %rdx
	movq	%r14, %rsi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	call	cudaThreadSynchronize@PLT
	leaq	32(%rsp), %rdi
	call	cudaEventCreate@PLT
	leaq	40(%rsp), %rdi
	call	cudaEventCreate@PLT
	movq	32(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movl	$8388609, %edx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movsd	8(%rsp), %xmm0
	salq	$9, %rdx
	movl	$1, %ecx
	movl	$1, 68(%rsp)
	movq	%rdx, 60(%rsp)
	cvttsd2sil	%xmm0, %eax
	movl	%eax, 48(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 52(%rsp)
	movq	48(%rsp), %rdi
	movl	56(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L11
	pushq	%rax
	.cfi_def_cfa_offset 152
	movl	152(%rsp), %eax
	movl	%r12d, %ecx
	movl	%ebp, %edx
	movl	%r13d, %r9d
	movl	%r15d, %r8d
	pushq	%rax
	.cfi_def_cfa_offset 160
	movl	20(%rsp), %esi
	movq	40(%rsp), %rdi
	call	_Z41__device_stub__Z15listPlainMulGpuPiiiiiiiPiiiiiii
	popq	%rdx
	.cfi_def_cfa_offset 152
	popq	%rcx
	.cfi_def_cfa_offset 144
.L11:
	call	cudaThreadSynchronize@PLT
	movq	40(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movq	40(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movq	40(%rsp), %rdx
	movq	32(%rsp), %rsi
	leaq	60(%rsp), %rdi
	call	cudaEventElapsedTime@PLT
	leaq	_ZSt4cout(%rip), %rdi
	cvtss2sd	60(%rsp), %xmm0
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	leaq	.LC3(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%rax, %rdi
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L12
	call	__stack_chk_fail@PLT
.L12:
	addq	$88, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3639:
	.size	_Z8list_mulPiiiiiii, .-_Z8list_mulPiiiiiii
	.section	.rodata.str1.1
.LC4:
	.string	" "
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB3640:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$24, %rsp
	.cfi_def_cfa_offset 80
	cmpl	$1, %edi
	jle	.L19
	movl	%edi, %r15d
	movq	8(%rsi), %rdi
	movq	%rsi, %r14
	call	atoi@PLT
	movl	%eax, %r13d
	cmpl	$2, %r15d
	je	.L20
	movq	16(%r14), %rdi
	call	atoi@PLT
	movl	%eax, %r12d
	cmpl	$3, %r15d
	je	.L21
	movq	24(%r14), %rdi
	movl	$7, %ebp
	call	atoi@PLT
	movl	%eax, %ebx
	cmpl	$4, %r15d
	je	.L15
	movq	32(%r14), %rdi
	call	atoi@PLT
	movl	%eax, %ebp
	jmp	.L15
.L19:
	movl	$4, %ebx
	movl	$4, %r12d
	xorl	%r13d, %r13d
	jmp	.L24
.L20:
	movl	$4, %ebx
	movl	$4, %r12d
	jmp	.L24
.L21:
	movl	$4, %ebx
.L24:
	movl	$7, %ebp
.L15:
	movl	%ebx, %eax
	movl	$2, %esi
	leal	-1(%r12,%r12), %ecx
	movl	%r12d, %r14d
	cltd
	imull	%ebx, %r14d
	idivl	%esi
	addl	%r13d, %r14d
	imull	%eax, %ecx
	leal	(%rcx,%r14), %eax
	movl	%eax, 4(%rsp)
	movslq	%eax, %rdi
	movabsq	$2305843009213693950, %rax
	cmpq	%rdi, %rax
	jb	.L16
	salq	$2, %rdi
	call	_Znam@PLT
	leaq	_ZSt4cout(%rip), %rdi
	movq	%rax, %r15
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
	movslq	%r13d, %rcx
	jmp	.L17
.L16:
	call	__cxa_throw_bad_array_new_length@PLT
.L17:
	cmpl	%ecx, %r14d
	jle	.L25
	movq	%rcx, 8(%rsp)
	call	rand@PLT
	movq	8(%rsp), %rcx
	cltd
	idivl	%ebp
	movl	%edx, (%r15,%rcx,4)
	incq	%rcx
	jmp	.L17
.L25:
	leaq	_ZSt4cout(%rip), %rdi
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
	movl	%ebp, %esi
	leaq	_ZSt4cout(%rip), %rdi
	call	_ZNSolsEi@PLT
	leaq	.LC4(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	%r13d, %esi
	movq	%rax, %rdi
	call	_ZNSolsEi@PLT
	leaq	.LC4(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	%r12d, %esi
	movq	%rax, %rdi
	call	_ZNSolsEi@PLT
	leaq	.LC4(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	%ebx, %esi
	movq	%rax, %rdi
	call	_ZNSolsEi@PLT
	leaq	.LC4(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	%r14d, %esi
	movq	%rax, %rdi
	call	_ZNSolsEi@PLT
	leaq	.LC4(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	4(%rsp), %esi
	movq	%rax, %rdi
	call	_ZNSolsEi@PLT
	movq	%rax, %rdi
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
	movl	%r14d, %r9d
	movl	%ebx, %r8d
	movl	%r12d, %ecx
	pushq	%rax
	.cfi_def_cfa_offset 88
	movl	%r13d, %edx
	movq	%r15, %rdi
	pushq	%rbp
	.cfi_def_cfa_offset 96
	movl	20(%rsp), %esi
	call	_Z8list_mulPiiiiiii
	movq	%r15, %rdi
	call	_ZdaPv@PLT
	addq	$40, %rsp
	.cfi_def_cfa_offset 56
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3640:
	.size	main, .-main
	.section	.rodata.str1.1
.LC5:
	.string	"_Z15listPlainMulGpuPiiiiiii"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3668:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC5(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z15listPlainMulGpuPiiiiiii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3668:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst8,"aM",@progbits,8
	.align 8
.LC0:
	.long	0
	.long	1072693248
	.align 8
.LC1:
	.long	0
	.long	1082130432
	.align 8
.LC2:
	.long	0
	.long	1071644672
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

/**********************************************************
* This code is intended for for computing multiplication  *
* for sub-product tree.                                   *
*             2*poly_length  <= T           *
* According to this constraint subproduct tree level      *
* where poly_length is not more than 129 is possible by   *
*  this code.
*ceil((poly_on_layer*0.5)/(floor(T/2*poly_length)) < 2^16 *
***********************************************************/


#include <hip/hip_runtime.h>
#include<iostream>
#include <ctime>
#include<cmath>

#define BASE_1 31

using namespace std;

const int Tmul = 512;
/***************************************************************
* one thread is responsible for computing one coefficient of c *
****************************************************************/

typedef int            sfixn;
typedef unsigned int   usfixn;


__device__ __host__ __inline__ 
sfixn add_mod(sfixn a, sfixn b, sfixn P) {
    sfixn r = a + b;
    r -= P;
    r += (r >> BASE_1) & P;
    return r;
}

__device__ __host__ __inline__ 
sfixn mul_mod(sfixn a, sfixn b, int P) {
    double ninv = 1 / (double)P;
    sfixn q  = (sfixn) ((((double) a) * ((double) b)) * ninv);
    sfixn res = a * b - q * P;
    res += (res >> BASE_1) & P;
    res -= 	P;
    res += (res >> BASE_1) & P;
    return res;
}




__global__ void listPlainMulGpu( sfixn *Mgpu, int start_offset, int length_poly, int poly_on_layer, int threadsForAmul, int mulInThreadBlock, int p)
{
	__shared__ sfixn sM[2*Tmul];	
	int mulID= ((threadIdx.x/threadsForAmul) + blockIdx.x*mulInThreadBlock);
	
	if( mulID < (poly_on_layer/2) && threadIdx.x < threadsForAmul*mulInThreadBlock)
	{

		int j = start_offset + ( mulID* length_poly*2);		
		int q = start_offset + ( poly_on_layer*length_poly) + ( mulID*(2*length_poly-1));

		int t = (threadIdx.x/threadsForAmul);
		int u = threadIdx.x % threadsForAmul;

		int s = t*(4*length_poly-1);
		int k = s + length_poly;
		int l = k + length_poly;
		int c = l+u;
		int a, b, i;

		sM[s+u] = Mgpu[j + u];
		__syncthreads();
		
		if(u != (2*length_poly-1) )
		{
			if(u < length_poly)
			{
				a = s;
				b = k + u;			
				sM[c] =  mul_mod(sM[a],sM[b],p);
				++a; --b;
				for(i = 0; i < u; ++i, ++a, --b)
					sM[c] =  add_mod(mul_mod(sM[a],sM[b],p),sM[c] ,p);
				/*
				Mgpu[j + u] = i;
				*/

				Mgpu[q+u] = sM[c];				
			}
			else
			{
				b = l - 1;
				a = (u - length_poly) + 1 + s;
				sM[c] =  mul_mod(sM[a],sM[b],p);
				++a; --b;
				
				int tempU = u;
				u = (2*length_poly-2) - u;
				for(i = 0; i < u; ++i, ++a, --b)
					sM[c] =  add_mod(mul_mod(sM[a],sM[b],p),sM[c] ,p);
				/*
				Mgpu[j + u] = i;
				*/

				Mgpu[q+tempU] = sM[c];			
			}	
			
	
		}/*
		else			
		{		
			Mgpu[j + u] = -1;				
		}*/
	}		
}



sfixn add_modCPU(sfixn a, sfixn b, sfixn P) {
    sfixn r = a + b;
    r -= P;
    r += (r >> BASE_1) & P;
    return r;
}


sfixn mul_modCPU(sfixn a, sfixn b, int P) {
    double ninv = 1 / (double)P;
    sfixn q  = (sfixn) ((((double) a) * ((double) b)) * ninv);
    sfixn res = a * b - q * P;
    res += (res >> BASE_1) & P;
    res -= 	P;
    res += (res >> BASE_1) & P;
    return res;
}

void list_mul(sfixn *M , int n, int start_offset, int length_poly, int poly_on_layer, int result_offset, int p)
{
	/********************************************************
	* Number of threads responsible for one multiplication  *
	*********************************************************/	
	int threadsForAmul = 2*length_poly;

	/************************************************
	* Number of multiplications in one thread block *
	*************************************************/
	int mulInThreadBlock = (int)floor((double)Tmul/(double)threadsForAmul);

	/****************************
	* Number of blocks required *
	****************************/
	int blockNo = (int)ceil( ((double)poly_on_layer/(double) mulInThreadBlock)*0.5  );	

	sfixn *Mgpu;
	hipMalloc((void **)&Mgpu, sizeof(sfixn)*n);
	hipDeviceSynchronize();
	hipMemcpy(Mgpu, M, sizeof(sfixn)*n, hipMemcpyHostToDevice);
	hipDeviceSynchronize();



	hipEvent_t start, stop;
	hipEventCreate(&start);
        hipEventCreate(&stop);
	hipEventRecord(start, 0);

	
	listPlainMulGpu<<<blockNo, Tmul>>>(Mgpu, start_offset, length_poly, poly_on_layer, threadsForAmul, mulInThreadBlock, p);
	
	hipDeviceSynchronize();

	hipEventRecord(stop, 0);
        hipEventSynchronize(stop);
        float outerTime;
        hipEventElapsedTime(&outerTime, start, stop);
	cout<<outerTime<<" miliseconds"<<endl;


	hipFree(Mgpu);  
	/*
	cout<<"threadsForAmul: "<<threadsForAmul<<" mulInThreadBlock: "<<mulInThreadBlock<<" blockNo: " <<blockNo<<endl;
	int i, j, k, l, q, a, b, c;
	for(i = 0; i < poly_on_layer/2; ++i )
	{
		j = start_offset + 2*i*length_poly;
		k = j + length_poly;
		l = k + length_poly;		
		q = result_offset + i*(2*length_poly -1);
		for(c = q; c < q+(2*length_poly -1); ++c)		
			M[c] = 0;
		for(a = j; a < k; ++a)
		{
			c = q;
			for(b = k; b < l; ++b, ++c)
			{
				M[c] = add_modCPU(mul_modCPU(M[a], M[b], p), M[c], p);				 
			}
			++q;		
		}
	}

	//
	sfixn *temp = new sfixn[n];
	cudaMemcpy(temp, Mgpu, sizeof(sfixn)*n, cudaMemcpyDeviceToHost);
	//
	cudaFree(Mgpu);        
	//	


	for(i = 0; i < n; ++i)
	{	
		if(M[i] != temp[i])
		{	
			cout<<i<<" "<<M[i]<<" "<<temp[i]<<endl;
			break;
		}
	}
	cout<<endl;
	
	delete [] temp;
	//	
	*/
}



int main(int argc, char *argv[])
{	
	int p= 7, start_offset = 0, length_poly = 4, poly_on_layer = 4, result_offset ;	

	if (argc > 1) start_offset = atoi(argv[1]);
	if (argc > 2) length_poly = atoi(argv[2]);
        if (argc > 3) poly_on_layer = atoi(argv[3]);
	if (argc > 4) p = atoi(argv[4]);
	
	result_offset = start_offset + length_poly*poly_on_layer;
	

	/**************************************
	* poly_on_layer MUST BE DIVISIBLE BY 2 *
	***************************************/
	int n, i;
	n = result_offset + (2*length_poly-1)*(poly_on_layer/2);	
	sfixn *M = new int[n];
	
	
	cout<<endl;
	for(i = start_offset; i < result_offset; ++i)
		M[i] = rand()% p;
		
			
	
	
	
	cout<<endl;
	
	cout<<p<<" "<<start_offset<<" "<<length_poly<<" "<<poly_on_layer<<" "<<result_offset<<" "<<n<<endl;
	/*
	for(i = 0; i < n; ++i)	
		cout<<M[i]<<" ";
	cout<<endl;	
	*/
		
	list_mul(M , n, start_offset, length_poly, poly_on_layer, result_offset, p );
	
		

	delete [] M;
	
	return 0;
}
	
	

	.text
	.file	"list_plain_mul.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z30__device_stub__listPlainMulGpuPiiiiiii # -- Begin function _Z30__device_stub__listPlainMulGpuPiiiiiii
	.type	_Z30__device_stub__listPlainMulGpuPiiiiiii,@function
_Z30__device_stub__listPlainMulGpuPiiiiiii: # @_Z30__device_stub__listPlainMulGpuPiiiiiii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	20(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	16(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	12(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	8(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	4(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	192(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z15listPlainMulGpuPiiiiiii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z30__device_stub__listPlainMulGpuPiiiiiii, .Lfunc_end0-_Z30__device_stub__listPlainMulGpuPiiiiiii
	.cfi_endproc
                                        # -- End function
	.globl	_Z10add_modCPUiii               # -- Begin function _Z10add_modCPUiii
	.type	_Z10add_modCPUiii,@function
_Z10add_modCPUiii:                      # @_Z10add_modCPUiii
	.cfi_startproc
# %bb.0:
                                        # kill: def $esi killed $esi def $rsi
                                        # kill: def $edi killed $edi def $rdi
	leal	(%rdi,%rsi), %ecx
	movl	%ecx, %eax
	subl	%edx, %eax
	cmovsl	%ecx, %eax
	retq
.Lfunc_end1:
	.size	_Z10add_modCPUiii, .Lfunc_end1-_Z10add_modCPUiii
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0                          # -- Begin function _Z10mul_modCPUiii
.LCPI2_0:
	.quad	0x3ff0000000000000              # double 1
	.text
	.globl	_Z10mul_modCPUiii
	.type	_Z10mul_modCPUiii,@function
_Z10mul_modCPUiii:                      # @_Z10mul_modCPUiii
	.cfi_startproc
# %bb.0:
	cvtsi2sd	%edx, %xmm0
	movsd	.LCPI2_0(%rip), %xmm1           # xmm1 = mem[0],zero
	divsd	%xmm0, %xmm1
	xorps	%xmm0, %xmm0
	cvtsi2sd	%edi, %xmm0
	cvtsi2sd	%esi, %xmm2
	mulsd	%xmm0, %xmm2
	mulsd	%xmm1, %xmm2
	cvttsd2si	%xmm2, %eax
	imull	%edi, %esi
	imull	%edx, %eax
	subl	%eax, %esi
	movl	%esi, %ecx
	sarl	$31, %ecx
	andl	%edx, %ecx
	addl	%esi, %ecx
	movl	%ecx, %eax
	subl	%edx, %eax
	cmovsl	%ecx, %eax
	retq
.Lfunc_end2:
	.size	_Z10mul_modCPUiii, .Lfunc_end2-_Z10mul_modCPUiii
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0                          # -- Begin function _Z8list_mulPiiiiiii
.LCPI3_0:
	.quad	0x4080000000000000              # double 512
.LCPI3_1:
	.quad	0x3fe0000000000000              # double 0.5
	.text
	.globl	_Z8list_mulPiiiiiii
	.type	_Z8list_mulPiiiiiii,@function
_Z8list_mulPiiiiiii:                    # @_Z8list_mulPiiiiiii
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$72, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%r8d, %ebx
	movl	%ecx, %r14d
	movl	%edx, 16(%rsp)                  # 4-byte Spill
	movl	%esi, %ebp
	movq	%rdi, %r13
	leal	(%r14,%r14), %r15d
	cvtsi2sd	%r15d, %xmm1
	movsd	.LCPI3_0(%rip), %xmm0           # xmm0 = mem[0],zero
	divsd	%xmm1, %xmm0
	callq	floor@PLT
	movapd	%xmm0, %xmm1
	movl	%ebx, 20(%rsp)                  # 4-byte Spill
	xorps	%xmm0, %xmm0
	cvtsi2sd	%ebx, %xmm0
	movapd	%xmm1, 48(%rsp)                 # 16-byte Spill
	cvttpd2dq	%xmm1, %xmm1
	cvtdq2pd	%xmm1, %xmm1
	divsd	%xmm1, %xmm0
	mulsd	.LCPI3_1(%rip), %xmm0
	callq	ceil@PLT
	cvttsd2si	%xmm0, %r12d
	movslq	%ebp, %rbp
	shlq	$2, %rbp
	leaq	24(%rsp), %rbx
	movq	%rbx, %rdi
	movq	%rbp, %rsi
	callq	hipMalloc
	callq	hipDeviceSynchronize
	movq	(%rbx), %rdi
	movq	%r13, %rsi
	movq	%rbp, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	callq	hipDeviceSynchronize
	leaq	32(%rsp), %rbx
	movq	%rbx, %rdi
	callq	hipEventCreate
	leaq	8(%rsp), %rdi
	callq	hipEventCreate
	movq	(%rbx), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	btsq	$32, %r12
	movabsq	$4294967296, %rdx               # imm = 0x100000000
	orq	$512, %rdx                      # imm = 0x200
	movq	%r12, %rdi
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB3_2
# %bb.1:
	movl	128(%rsp), %eax
	cvttsd2si	48(%rsp), %r9d          # 16-byte Folded Reload
	movq	24(%rsp), %rdi
	movl	%eax, (%rsp)
	movl	16(%rsp), %esi                  # 4-byte Reload
	movl	%r14d, %edx
	movl	20(%rsp), %ecx                  # 4-byte Reload
	movl	%r15d, %r8d
	callq	_Z30__device_stub__listPlainMulGpuPiiiiiii
.LBB3_2:
	callq	hipDeviceSynchronize
	movq	8(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	8(%rsp), %rdi
	callq	hipEventSynchronize
	movq	32(%rsp), %rsi
	movq	8(%rsp), %rdx
	leaq	44(%rsp), %rbx
	movq	%rbx, %rdi
	callq	hipEventElapsedTime
	xorps	%xmm0, %xmm0
	cvtss2sd	(%rbx), %xmm0
	movl	$_ZSt4cout, %edi
	callq	_ZNSo9_M_insertIdEERSoT_
	movq	%rax, %rbx
	movl	$.L.str, %esi
	movl	$12, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	(%rbx), %rax
	movq	-24(%rax), %rdi
	addq	%rbx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%rbx, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movq	24(%rsp), %rdi
	callq	hipFree
	addq	$72, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	_Z8list_mulPiiiiiii, .Lfunc_end3-_Z8list_mulPiiiiiii
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$40, %rsp
	.cfi_def_cfa_offset 96
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	$7, %ebp
	xorl	%ebx, %ebx
	movl	$4, %r13d
	cmpl	$2, %edi
	jl	.LBB4_1
# %bb.2:
	movq	%rsi, %r14
	movl	%edi, %r12d
	movq	8(%rsi), %rdi
	callq	atoi
	movl	%eax, %ebx
	cmpl	$2, %r12d
	jne	.LBB4_3
.LBB4_1:
	movl	$4, %eax
.LBB4_7:                                # %.thread48
	movl	%eax, %r15d
	imull	%r13d, %r15d
	movq	%rbx, 16(%rsp)                  # 8-byte Spill
	addl	%r15d, %ebx
	movq	%rax, 32(%rsp)                  # 8-byte Spill
	leal	-1(,%rax,2), %eax
	movl	%r13d, %r12d
	shrl	$31, %r12d
	movl	%r13d, 28(%rsp)                 # 4-byte Spill
	addl	%r13d, %r12d
	sarl	%r12d
	imull	%eax, %r12d
	addl	%ebx, %r12d
	movslq	%r12d, %rax
	leaq	(,%rax,4), %rcx
	testl	%eax, %eax
	movq	$-1, %rdi
	cmovnsq	%rcx, %rdi
	callq	_Znam
	movq	%rax, %r13
	movl	$_ZSt4cout, %ecx
	movq	_ZSt4cout(%rip), %rax
	movq	-24(%rax), %rdi
	addq	%rcx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movl	$_ZSt4cout, %edi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	testl	%r15d, %r15d
	jle	.LBB4_10
# %bb.8:                                # %.lr.ph.preheader
	movslq	16(%rsp), %r15                  # 4-byte Folded Reload
	movslq	%ebx, %r14
.LBB4_9:                                # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	callq	rand
	cltd
	idivl	%ebp
	movl	%edx, (%r13,%r15,4)
	incq	%r15
	cmpq	%r14, %r15
	jl	.LBB4_9
.LBB4_10:                               # %._crit_edge
	movq	_ZSt4cout(%rip), %rax
	movq	-24(%rax), %rdi
	movl	$_ZSt4cout, %eax
	addq	%rax, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movl	$_ZSt4cout, %edi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movl	$_ZSt4cout, %edi
	movl	%ebp, %esi
	callq	_ZNSolsEi
	movq	%rax, %r15
	movl	$.L.str.1, %esi
	movl	$1, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	%r15, %rdi
	movl	%ebx, %r14d
	movq	16(%rsp), %rsi                  # 8-byte Reload
                                        # kill: def $esi killed $esi killed $rsi
	callq	_ZNSolsEi
	movq	%rax, %r15
	movl	$.L.str.1, %esi
	movl	$1, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	%r15, %rdi
	movq	32(%rsp), %rsi                  # 8-byte Reload
                                        # kill: def $esi killed $esi killed $rsi
	callq	_ZNSolsEi
	movq	%rax, %r15
	movl	$.L.str.1, %esi
	movl	$1, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	%r15, %rdi
	movl	28(%rsp), %ebx                  # 4-byte Reload
	movl	%ebx, %esi
	callq	_ZNSolsEi
	movq	%rax, %r15
	movl	$.L.str.1, %esi
	movl	$1, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	%r15, %rdi
	movl	%r14d, %esi
	callq	_ZNSolsEi
	movq	%rax, %r14
	movl	$.L.str.1, %esi
	movl	$1, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	%r14, %rdi
	movl	%r12d, %esi
	callq	_ZNSolsEi
	movq	%rax, %r14
	movq	(%rax), %rax
	movq	-24(%rax), %rdi
	addq	%r14, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%r14, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movl	%ebp, (%rsp)
	movq	%r13, %rdi
	movl	%r12d, %esi
	movq	16(%rsp), %rdx                  # 8-byte Reload
                                        # kill: def $edx killed $edx killed $rdx
	movq	32(%rsp), %rcx                  # 8-byte Reload
                                        # kill: def $ecx killed $ecx killed $rcx
	movl	%ebx, %r8d
	callq	_Z8list_mulPiiiiiii
	movq	%r13, %rdi
	callq	_ZdaPv
	xorl	%eax, %eax
	addq	$40, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB4_3:
	.cfi_def_cfa_offset 96
	movq	16(%r14), %rdi
	callq	atoi
                                        # kill: def $eax killed $eax def $rax
	cmpl	$4, %r12d
	jb	.LBB4_7
# %bb.4:
	movq	%rax, %r15
	movq	24(%r14), %rdi
	callq	atoi
	movl	%eax, %r13d
	cmpl	$4, %r12d
	je	.LBB4_6
# %bb.5:
	movq	32(%r14), %rdi
	callq	atoi
	movl	%eax, %ebp
.LBB4_6:                                # %.thread48
	movq	%r15, %rax
	jmp	.LBB4_7
.Lfunc_end4:
	.size	main, .Lfunc_end4-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB5_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB5_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z15listPlainMulGpuPiiiiiii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end5:
	.size	__hip_module_ctor, .Lfunc_end5-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB6_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB6_2:
	retq
.Lfunc_end6:
	.size	__hip_module_dtor, .Lfunc_end6-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z15listPlainMulGpuPiiiiiii,@object # @_Z15listPlainMulGpuPiiiiiii
	.section	.rodata,"a",@progbits
	.globl	_Z15listPlainMulGpuPiiiiiii
	.p2align	3, 0x0
_Z15listPlainMulGpuPiiiiiii:
	.quad	_Z30__device_stub__listPlainMulGpuPiiiiiii
	.size	_Z15listPlainMulGpuPiiiiiii, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	" miliseconds"
	.size	.L.str, 13

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	" "
	.size	.L.str.1, 2

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z15listPlainMulGpuPiiiiiii"
	.size	.L__unnamed_1, 28

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z30__device_stub__listPlainMulGpuPiiiiiii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z15listPlainMulGpuPiiiiiii
	.addrsig_sym _ZSt4cout
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z15listPlainMulGpuPiiiiiii ; -- Begin function _Z15listPlainMulGpuPiiiiiii
	.globl	_Z15listPlainMulGpuPiiiiiii
	.p2align	8
	.type	_Z15listPlainMulGpuPiiiiiii,@function
_Z15listPlainMulGpuPiiiiiii:            ; @_Z15listPlainMulGpuPiiiiiii
; %bb.0:
	s_clause 0x1
	s_load_b128 s[4:7], s[0:1], 0x8
	s_load_b64 s[2:3], s[0:1], 0x18
	s_waitcnt lgkmcnt(0)
	v_cvt_f32_u32_e32 v1, s7
	s_sub_i32 s8, 0, s7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v1, v1
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v1, 0x4f7ffffe, v1
	v_cvt_u32_f32_e32 v1, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_mul_lo_u32 v2, s8, v1
	s_lshr_b32 s8, s6, 31
	s_add_i32 s8, s6, s8
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_ashr_i32 s8, s8, 1
	v_mul_hi_u32 v2, v1, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v1, v1, v2
	v_mul_hi_u32 v1, v0, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v2, v1, s7
	v_add_nc_u32_e32 v3, 1, v1
	v_sub_nc_u32_e32 v2, v0, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v4, s7, v2
	v_cmp_le_u32_e32 vcc_lo, s7, v2
	v_dual_cndmask_b32 v2, v2, v4 :: v_dual_cndmask_b32 v1, v1, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_le_u32_e32 vcc_lo, s7, v2
	v_add_nc_u32_e32 v3, 1, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v3, v1, v3, vcc_lo
	v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
	s_mul_i32 s2, s2, s7
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_u32_e64 s2, s2, v0
	v_cmp_gt_i32_e32 vcc_lo, s8, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, vcc_lo, s2
	s_and_saveexec_b32 s8, s2
	s_cbranch_execz .LBB0_15
; %bb.1:
	v_mul_lo_u32 v2, v3, s7
	s_lshl_b32 s2, s5, 1
	s_load_b64 s[8:9], s[0:1], 0x0
	v_mul_lo_u32 v7, s2, v1
	s_add_i32 s0, s2, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s1, s0, s2
	v_mul_lo_u32 v10, v3, s1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v6, v0, v2
	v_add3_u32 v4, v7, s4, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v5, 31, v4
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, s8, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s9, v5, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, s0, v6
	global_load_b32 v2, v[4:5], off
	v_add_lshl_u32 v4, v6, v10, 2
	s_waitcnt vmcnt(0)
	ds_store_b32 v4, v2
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_15
; %bb.2:
	v_cvt_f64_i32_e32 v[4:5], s3
	v_add_nc_u32_e32 v2, s5, v10
                                        ; implicit-def: $vgpr9
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v11, s5, v2
	v_add_nc_u32_e32 v8, v6, v11
	s_delay_alu instid0(VALU_DEP_1)
	v_lshlrev_b32_e32 v8, 2, v8
	v_cmpx_le_i32_e64 s5, v6
	s_xor_b32 s1, exec_lo, s0
	s_cbranch_execz .LBB0_8
; %bb.3:
	v_div_scale_f64 v[12:13], null, v[4:5], v[4:5], 1.0
	v_div_scale_f64 v[18:19], vcc_lo, 1.0, v[4:5], 1.0
	v_subrev_nc_u32_e32 v2, s5, v10
	v_lshl_add_u32 v9, v11, 2, -4
	s_mov_b32 s10, 0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_lshl_u32 v2, v2, v6, 2
	ds_load_b32 v2, v2 offset:4
	ds_load_b32 v9, v9
	s_waitcnt lgkmcnt(0)
	v_cvt_f64_i32_e32 v[20:21], v9
	v_rcp_f64_e32 v[14:15], v[12:13]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[16:17], -v[12:13], v[14:15], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[14:15], v[14:15], v[16:17], v[14:15]
	v_fma_f64 v[16:17], -v[12:13], v[14:15], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[14:15], v[14:15], v[16:17], v[14:15]
	v_mul_f64 v[16:17], v[18:19], v[14:15]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_fma_f64 v[12:13], -v[12:13], v[16:17], v[18:19]
	v_cvt_f64_i32_e32 v[18:19], v2
	v_mul_lo_u32 v2, v9, v2
	v_div_fmas_f64 v[11:12], v[12:13], v[14:15], v[16:17]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[13:14], v[18:19], v[20:21]
	v_div_fixup_f64 v[4:5], v[11:12], v[4:5], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[11:12], v[4:5], v[13:14]
	v_cvt_i32_f64_e32 v11, v[11:12]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v9, v11, s3
	v_sub_nc_u32_e32 v2, v2, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v9, 31, v2
	v_and_b32_e32 v9, s3, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v9, v9, v2
	v_sub_nc_u32_e32 v2, s2, v6
	s_mov_b32 s2, exec_lo
	v_subrev_nc_u32_e32 v11, s3, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_gt_i32_e32 vcc_lo, 0, v11
	v_dual_cndmask_b32 v9, v11, v9 :: v_dual_add_nc_u32 v2, -2, v2
	ds_store_b32 v8, v9
	v_cmpx_lt_i32_e32 0, v2
	s_cbranch_execz .LBB0_7
; %bb.4:                                ; %.lr.ph
	s_lshl_b32 s0, s5, 2
	s_not_b32 s7, s7
	v_lshlrev_b32_e32 v0, 2, v0
	s_add_i32 s7, s7, s0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v3, v3, s7
	s_mov_b32 s7, 0
	v_lshl_add_u32 v0, v3, 2, v0
	v_lshlrev_b32_e32 v3, 2, v10
	s_delay_alu instid0(VALU_DEP_2)
	v_subrev_nc_u32_e32 v10, s0, v0
	s_lshl_b32 s0, s5, 3
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	v_add3_u32 v0, s0, v3, -8
	s_delay_alu instid0(VALU_DEP_2)
	v_add_nc_u32_e32 v3, 8, v10
.LBB0_5:                                ; =>This Inner Loop Header: Depth=1
	ds_load_b32 v14, v3
	ds_load_b32 v15, v0
	s_add_i32 s7, s7, 1
	v_add_nc_u32_e32 v0, -4, v0
	v_add_nc_u32_e32 v3, 4, v3
	s_waitcnt lgkmcnt(1)
	v_cvt_f64_i32_e32 v[10:11], v14
	s_waitcnt lgkmcnt(0)
	v_cvt_f64_i32_e32 v[12:13], v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[10:11], v[10:11], v[12:13]
	v_mul_f64 v[10:11], v[4:5], v[10:11]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cvt_i32_f64_e32 v10, v[10:11]
	v_mul_lo_u32 v11, v15, v14
	v_mul_lo_u32 v10, v10, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v10, v11, v10
	v_ashrrev_i32_e32 v11, 31, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v11, s3, v11
	v_add_nc_u32_e32 v10, v11, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_subrev_nc_u32_e32 v11, s3, v10
	v_cmp_gt_i32_e32 vcc_lo, 0, v11
	v_cndmask_b32_e32 v10, v11, v10, vcc_lo
	v_cmp_ge_i32_e32 vcc_lo, s7, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v9, v10, v9
	s_or_b32 s10, vcc_lo, s10
	v_subrev_nc_u32_e32 v10, s3, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_gt_i32_e64 s0, 0, v10
	v_cndmask_b32_e64 v9, v10, v9, s0
	ds_store_b32 v8, v9
	s_and_not1_b32 exec_lo, exec_lo, s10
	s_cbranch_execnz .LBB0_5
; %bb.6:                                ; %Flow
	s_or_b32 exec_lo, exec_lo, s10
.LBB0_7:                                ; %Flow156
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s2
                                        ; implicit-def: $vgpr2
                                        ; implicit-def: $vgpr10
                                        ; implicit-def: $vgpr4_vgpr5
                                        ; implicit-def: $vgpr8
.LBB0_8:                                ; %Flow159
	s_and_not1_saveexec_b32 s1, s1
	s_cbranch_execz .LBB0_14
; %bb.9:
	v_div_scale_f64 v[11:12], null, v[4:5], v[4:5], 1.0
	v_div_scale_f64 v[17:18], vcc_lo, 1.0, v[4:5], 1.0
	v_add_nc_u32_e32 v0, v6, v2
	v_lshlrev_b32_e32 v2, 2, v10
	s_mov_b32 s7, 0
	s_mov_b32 s2, exec_lo
	s_delay_alu instid0(VALU_DEP_2)
	v_lshlrev_b32_e32 v3, 2, v0
	ds_load_b32 v9, v2
	ds_load_b32 v19, v3
	s_waitcnt lgkmcnt(1)
	v_cvt_f64_i32_e32 v[2:3], v9
	v_rcp_f64_e32 v[13:14], v[11:12]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[15:16], -v[11:12], v[13:14], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[13:14], v[13:14], v[15:16], v[13:14]
	v_fma_f64 v[15:16], -v[11:12], v[13:14], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[13:14], v[13:14], v[15:16], v[13:14]
	v_mul_f64 v[15:16], v[17:18], v[13:14]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_fma_f64 v[11:12], -v[11:12], v[15:16], v[17:18]
	s_waitcnt lgkmcnt(0)
	v_cvt_f64_i32_e32 v[17:18], v19
	v_div_fmas_f64 v[11:12], v[11:12], v[13:14], v[15:16]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[13:14], v[2:3], v[17:18]
	v_div_fixup_f64 v[2:3], v[11:12], v[4:5], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[4:5], v[2:3], v[13:14]
	v_cvt_i32_f64_e32 v4, v[4:5]
	v_mul_lo_u32 v5, v19, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v4, v4, s3
	v_sub_nc_u32_e32 v4, v5, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v5, 31, v4
	v_and_b32_e32 v5, s3, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v4, v5, v4
	v_subrev_nc_u32_e32 v5, s3, v4
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_i32_e32 vcc_lo, 0, v5
	v_cndmask_b32_e32 v9, v5, v4, vcc_lo
	ds_store_b32 v8, v9
	v_cmpx_ne_u32_e32 0, v6
	s_cbranch_execz .LBB0_13
; %bb.10:                               ; %.lr.ph109.preheader
	v_lshl_add_u32 v0, v0, 2, -4
	v_lshl_add_u32 v4, v10, 2, 4
	s_mov_b32 s10, 0
.LBB0_11:                               ; %.lr.ph109
                                        ; =>This Inner Loop Header: Depth=1
	ds_load_b32 v5, v4
	ds_load_b32 v14, v0
	s_add_i32 s10, s10, 1
	v_add_nc_u32_e32 v4, 4, v4
	v_add_nc_u32_e32 v0, -4, v0
	s_waitcnt lgkmcnt(1)
	v_cvt_f64_i32_e32 v[10:11], v5
	s_waitcnt lgkmcnt(0)
	v_cvt_f64_i32_e32 v[12:13], v14
	v_mul_lo_u32 v5, v14, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[10:11], v[10:11], v[12:13]
	v_mul_f64 v[10:11], v[2:3], v[10:11]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_i32_f64_e32 v10, v[10:11]
	v_mul_lo_u32 v10, v10, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v5, v5, v10
	v_ashrrev_i32_e32 v10, 31, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v10, s3, v10
	v_add_nc_u32_e32 v5, v10, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_subrev_nc_u32_e32 v10, s3, v5
	v_cmp_gt_i32_e32 vcc_lo, 0, v10
	v_cndmask_b32_e32 v5, v10, v5, vcc_lo
	v_cmp_ge_u32_e32 vcc_lo, s10, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v5, v5, v9
	s_or_b32 s7, vcc_lo, s7
	v_subrev_nc_u32_e32 v9, s3, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_gt_i32_e64 s0, 0, v9
	v_cndmask_b32_e64 v9, v9, v5, s0
	ds_store_b32 v8, v9
	s_and_not1_b32 exec_lo, exec_lo, s7
	s_cbranch_execnz .LBB0_11
; %bb.12:                               ; %Flow157
	s_or_b32 exec_lo, exec_lo, s7
.LBB0_13:                               ; %Flow158
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s2
.LBB0_14:                               ; %.sink.split
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	v_sub_nc_u32_e32 v0, v7, v1
	s_mul_i32 s0, s6, s5
	s_add_i32 s0, s0, s4
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_add3_u32 v0, s0, v0, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v1, 31, v0
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s8, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s9, v1, vcc_lo
	global_store_b32 v[0:1], v9, off
.LBB0_15:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z15listPlainMulGpuPiiiiiii
		.amdhsa_group_segment_fixed_size 4096
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 32
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 22
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z15listPlainMulGpuPiiiiiii, .Lfunc_end0-_Z15listPlainMulGpuPiiiiiii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1528
; NumSgprs: 18
; NumVgprs: 22
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 4096 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 22
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .offset:         12
        .size:           4
        .value_kind:     by_value
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
    .group_segment_fixed_size: 4096
    .kernarg_segment_align: 8
    .kernarg_segment_size: 32
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z15listPlainMulGpuPiiiiiii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z15listPlainMulGpuPiiiiiii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     22
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
