#include "includes.h"
__global__ void back(double *h_out_d, double *weights_out_d, double *weights_h_d, double *weights_in_d, double *outputs_d, double *deltas_h_d, double *deltas_h_new_d, double *deltas_o_d, double *weights_in_delta_d, double *weights_out_delta_d, double *weights_h_delta_d, int height, int inputs, int outputs, int layers, double *training_in_d, double *training_out_d, int sample){

int i, j;

int tix = threadIdx.x;
int tiy = threadIdx.y + sample;

int h_offset = tiy * layers * height;
int w_o_d_offset = tiy * outputs * height;
int w_h_d_offset = tiy * (layers-1) * height * height;
int w_i_d_offset = tiy * inputs * height;
int d_h_offset = tiy * height;

double delta_sum, temp;

/*__shared__ double h_out_ds[H_LAYERS*H_HEIGHT];
__shared__ double weights_h_ds[(H_LAYERS-1)*H_HEIGHT*H_HEIGHT];
__shared__ double deltas_h_ds[H_HEIGHT];
__shared__ double deltas_h_new_ds[H_HEIGHT];

for(i=0;i<layers;i++)
h_out_ds[tix*height+i] = h_out_d[tix*height+i];
for(i=0;i<layers-1;i++){
for(j=0;j<height;j++)
weights_h_ds[i*height*height + tix*height + j] = weights_h_d[i*height*height + tix*height + j];
}
deltas_h_ds[tix] = deltas_h_d[tix];
deltas_h_new_ds[tix] = deltas_h_new_d[tix];

__syncthreads();
*/
//output layer
if(tix < outputs){
deltas_o_d[tiy * outputs + tix] = (outputs_d[tiy * outputs + tix] - training_out_d[tiy]);
for(i = 0; i < height; i++){
weights_out_delta_d[w_o_d_offset + (tix * height) + i] = deltas_o_d[tiy * outputs + tix] * h_out_d[h_offset + (layers-1)*height+i];
}
}

__syncthreads();

//hidden layer

//layer connected to output
delta_sum = 0;
for(i = 0; i < outputs; i++){
delta_sum += weights_out_d[tix + (i * height)] * deltas_o_d[tiy * outputs + i];
}
temp = h_out_d[h_offset + (layers-1)*height + tix];
deltas_h_d[d_h_offset + tix] = temp * (1 - temp) * delta_sum;

for(i = 0; i < height; i++){
weights_h_delta_d[w_h_d_offset + (layers-2)*height*height + (tix * height) + i] = deltas_h_d[d_h_offset + tix] * h_out_d[h_offset + (layers-2)*height+i];
}

__syncthreads();

//each hidden layer not connected to input/hidden output layer
for(i = layers - 2; i > 0; i--){
delta_sum = 0;
for(j = 0; j < height; j++){
delta_sum += weights_h_d[i*height*height + j*height + tix] * deltas_h_d[d_h_offset + j];
}
temp = h_out_d[h_offset + i*height + tix];
deltas_h_new_d[d_h_offset + tix] = temp * (1 - temp) * delta_sum;

for(j = 0; j < height; j++){
weights_h_delta_d[w_h_d_offset + (i-1)*height*height + (tix * height) + j] = (deltas_h_new_d[d_h_offset + tix] * h_out_d[h_offset + (i-1)*height+j]);
}

__syncthreads();
//change pointers to simulate copying memory
deltas_h_d[d_h_offset + tix] = deltas_h_new_d[d_h_offset + tix];

__syncthreads();

}

//Layer connected to inputs
delta_sum = 0;
for(i=0; i<height; i++){
delta_sum += weights_h_d[i*height + tix] * deltas_h_d[d_h_offset + i];
}
temp = h_out_d[h_offset + tix];
deltas_h_new_d[d_h_offset + tix] = temp * (1 - temp) * delta_sum;

for(i=0; i<inputs; i++){
weights_in_delta_d[w_i_d_offset + tix*inputs+i] = (deltas_h_new_d[d_h_offset + tix] * training_in_d[tiy * inputs + i]);
}

__syncthreads();

}
	.file	"tmpxft_002aa35b_00000000-6_back.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2010:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2010:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z52__device_stub__Z4backPdS_S_S_S_S_S_S_S_S_S_iiiiS_S_iPdS_S_S_S_S_S_S_S_S_S_iiiiS_S_i
	.type	_Z52__device_stub__Z4backPdS_S_S_S_S_S_S_S_S_S_iiiiS_S_iPdS_S_S_S_S_S_S_S_S_S_iiiiS_S_i, @function
_Z52__device_stub__Z4backPdS_S_S_S_S_S_S_S_S_S_iiiiS_S_iPdS_S_S_S_S_S_S_S_S_S_iiiiS_S_i:
.LFB2032:
	.cfi_startproc
	endbr64
	subq	$344, %rsp
	.cfi_def_cfa_offset 352
	movq	352(%rsp), %rax
	movq	%rdi, 104(%rsp)
	leaq	136(%rsp), %rdi
	movq	%rsi, 96(%rsp)
	leaq	148(%rsp), %rsi
	movq	%rax, 56(%rsp)
	movq	360(%rsp), %rax
	movq	%rdx, 88(%rsp)
	leaq	120(%rsp), %rdx
	movq	%rax, 48(%rsp)
	movq	368(%rsp), %rax
	movq	%rcx, 80(%rsp)
	leaq	128(%rsp), %rcx
	movq	%rax, 40(%rsp)
	movq	376(%rsp), %rax
	movq	%r8, 72(%rsp)
	movq	%rax, 32(%rsp)
	movq	384(%rsp), %rax
	movq	%r9, 64(%rsp)
	movq	%rax, 24(%rsp)
	movq	424(%rsp), %rax
	movq	%rax, 16(%rsp)
	movq	432(%rsp), %rax
	movq	%rax, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 328(%rsp)
	xorl	%eax, %eax
	leaq	104(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	96(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	88(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	80(%rsp), %rax
	movq	%rax, 208(%rsp)
	leaq	72(%rsp), %rax
	movq	%rax, 216(%rsp)
	leaq	64(%rsp), %rax
	movq	%rax, 224(%rsp)
	leaq	56(%rsp), %rax
	movq	%rax, 232(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 240(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 248(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 256(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 264(%rsp)
	leaq	392(%rsp), %rax
	movq	%rax, 272(%rsp)
	leaq	400(%rsp), %rax
	movq	%rax, 280(%rsp)
	leaq	408(%rsp), %rax
	movq	%rax, 288(%rsp)
	leaq	416(%rsp), %rax
	movq	%rax, 296(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 304(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 312(%rsp)
	leaq	440(%rsp), %rax
	movq	%rax, 320(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 136(%rsp)
	movl	$1, 144(%rsp)
	movq	%rax, 148(%rsp)
	movl	$1, 156(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	128(%rsp)
	.cfi_def_cfa_offset 360
	leaq	_Z4backPdS_S_S_S_S_S_S_S_S_S_iiiiS_S_i(%rip), %rdi
	pushq	128(%rsp)
	.cfi_def_cfa_offset 368
	movq	164(%rsp), %rcx
	movl	172(%rsp), %r8d
	movq	152(%rsp), %rsi
	movl	160(%rsp), %edx
	leaq	200(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 360
	popq	%rdx
	.cfi_def_cfa_offset 352
.L2:
	movq	328(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$344, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2032:
	.size	_Z52__device_stub__Z4backPdS_S_S_S_S_S_S_S_S_S_iiiiS_S_iPdS_S_S_S_S_S_S_S_S_S_iiiiS_S_i, .-_Z52__device_stub__Z4backPdS_S_S_S_S_S_S_S_S_S_iiiiS_S_iPdS_S_S_S_S_S_S_S_S_S_iiiiS_S_i
	.globl	_Z4backPdS_S_S_S_S_S_S_S_S_S_iiiiS_S_i
	.type	_Z4backPdS_S_S_S_S_S_S_S_S_S_iiiiS_S_i, @function
_Z4backPdS_S_S_S_S_S_S_S_S_S_iiiiS_S_i:
.LFB2033:
	.cfi_startproc
	endbr64
	jmp	_Z52__device_stub__Z4backPdS_S_S_S_S_S_S_S_S_S_iiiiS_S_iPdS_S_S_S_S_S_S_S_S_S_iiiiS_S_i
	.cfi_endproc
.LFE2033:
	.size	_Z4backPdS_S_S_S_S_S_S_S_S_S_iiiiS_S_i, .-_Z4backPdS_S_S_S_S_S_S_S_S_S_iiiiS_S_i
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z4backPdS_S_S_S_S_S_S_S_S_S_iiiiS_S_i"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2035:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z4backPdS_S_S_S_S_S_S_S_S_S_iiiiS_S_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2035:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void back(double *h_out_d, double *weights_out_d, double *weights_h_d, double *weights_in_d, double *outputs_d, double *deltas_h_d, double *deltas_h_new_d, double *deltas_o_d, double *weights_in_delta_d, double *weights_out_delta_d, double *weights_h_delta_d, int height, int inputs, int outputs, int layers, double *training_in_d, double *training_out_d, int sample){

int i, j;

int tix = threadIdx.x;
int tiy = threadIdx.y + sample;

int h_offset = tiy * layers * height;
int w_o_d_offset = tiy * outputs * height;
int w_h_d_offset = tiy * (layers-1) * height * height;
int w_i_d_offset = tiy * inputs * height;
int d_h_offset = tiy * height;

double delta_sum, temp;

/*__shared__ double h_out_ds[H_LAYERS*H_HEIGHT];
__shared__ double weights_h_ds[(H_LAYERS-1)*H_HEIGHT*H_HEIGHT];
__shared__ double deltas_h_ds[H_HEIGHT];
__shared__ double deltas_h_new_ds[H_HEIGHT];

for(i=0;i<layers;i++)
h_out_ds[tix*height+i] = h_out_d[tix*height+i];
for(i=0;i<layers-1;i++){
for(j=0;j<height;j++)
weights_h_ds[i*height*height + tix*height + j] = weights_h_d[i*height*height + tix*height + j];
}
deltas_h_ds[tix] = deltas_h_d[tix];
deltas_h_new_ds[tix] = deltas_h_new_d[tix];

__syncthreads();
*/
//output layer
if(tix < outputs){
deltas_o_d[tiy * outputs + tix] = (outputs_d[tiy * outputs + tix] - training_out_d[tiy]);
for(i = 0; i < height; i++){
weights_out_delta_d[w_o_d_offset + (tix * height) + i] = deltas_o_d[tiy * outputs + tix] * h_out_d[h_offset + (layers-1)*height+i];
}
}

__syncthreads();

//hidden layer

//layer connected to output
delta_sum = 0;
for(i = 0; i < outputs; i++){
delta_sum += weights_out_d[tix + (i * height)] * deltas_o_d[tiy * outputs + i];
}
temp = h_out_d[h_offset + (layers-1)*height + tix];
deltas_h_d[d_h_offset + tix] = temp * (1 - temp) * delta_sum;

for(i = 0; i < height; i++){
weights_h_delta_d[w_h_d_offset + (layers-2)*height*height + (tix * height) + i] = deltas_h_d[d_h_offset + tix] * h_out_d[h_offset + (layers-2)*height+i];
}

__syncthreads();

//each hidden layer not connected to input/hidden output layer
for(i = layers - 2; i > 0; i--){
delta_sum = 0;
for(j = 0; j < height; j++){
delta_sum += weights_h_d[i*height*height + j*height + tix] * deltas_h_d[d_h_offset + j];
}
temp = h_out_d[h_offset + i*height + tix];
deltas_h_new_d[d_h_offset + tix] = temp * (1 - temp) * delta_sum;

for(j = 0; j < height; j++){
weights_h_delta_d[w_h_d_offset + (i-1)*height*height + (tix * height) + j] = (deltas_h_new_d[d_h_offset + tix] * h_out_d[h_offset + (i-1)*height+j]);
}

__syncthreads();
//change pointers to simulate copying memory
deltas_h_d[d_h_offset + tix] = deltas_h_new_d[d_h_offset + tix];

__syncthreads();

}

//Layer connected to inputs
delta_sum = 0;
for(i=0; i<height; i++){
delta_sum += weights_h_d[i*height + tix] * deltas_h_d[d_h_offset + i];
}
temp = h_out_d[h_offset + tix];
deltas_h_new_d[d_h_offset + tix] = temp * (1 - temp) * delta_sum;

for(i=0; i<inputs; i++){
weights_in_delta_d[w_i_d_offset + tix*inputs+i] = (deltas_h_new_d[d_h_offset + tix] * training_in_d[tiy * inputs + i]);
}

__syncthreads();

}
	.text
	.file	"back.hip"
	.globl	_Z19__device_stub__backPdS_S_S_S_S_S_S_S_S_S_iiiiS_S_i # -- Begin function _Z19__device_stub__backPdS_S_S_S_S_S_S_S_S_S_iiiiS_S_i
	.type	_Z19__device_stub__backPdS_S_S_S_S_S_S_S_S_S_iiiiS_S_i,@function
_Z19__device_stub__backPdS_S_S_S_S_S_S_S_S_S_iiiiS_S_i: # @_Z19__device_stub__backPdS_S_S_S_S_S_S_S_S_S_iiiiS_S_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$240, %rsp
	.cfi_def_cfa_offset 288
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	288(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	296(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	304(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	312(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	320(%rsp), %rax
	movq	%rax, 80(%rbx)
	leaq	328(%rsp), %rax
	movq	%rax, 88(%rbx)
	leaq	336(%rsp), %rax
	movq	%rax, 96(%rbx)
	leaq	344(%rsp), %rax
	movq	%rax, 104(%rbx)
	leaq	352(%rsp), %rax
	movq	%rax, 112(%rbx)
	leaq	360(%rsp), %rax
	movq	%rax, 120(%rbx)
	leaq	368(%rsp), %rax
	movq	%rax, 128(%rbx)
	leaq	376(%rsp), %rax
	movq	%rax, 136(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z4backPdS_S_S_S_S_S_S_S_S_S_iiiiS_S_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$256, %rsp                      # imm = 0x100
	.cfi_adjust_cfa_offset -256
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z19__device_stub__backPdS_S_S_S_S_S_S_S_S_S_iiiiS_S_i, .Lfunc_end0-_Z19__device_stub__backPdS_S_S_S_S_S_S_S_S_S_iiiiS_S_i
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z4backPdS_S_S_S_S_S_S_S_S_S_iiiiS_S_i, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z4backPdS_S_S_S_S_S_S_S_S_S_iiiiS_S_i,@object # @_Z4backPdS_S_S_S_S_S_S_S_S_S_iiiiS_S_i
	.section	.rodata,"a",@progbits
	.globl	_Z4backPdS_S_S_S_S_S_S_S_S_S_iiiiS_S_i
	.p2align	3, 0x0
_Z4backPdS_S_S_S_S_S_S_S_S_S_iiiiS_S_i:
	.quad	_Z19__device_stub__backPdS_S_S_S_S_S_S_S_S_S_iiiiS_S_i
	.size	_Z4backPdS_S_S_S_S_S_S_S_S_S_iiiiS_S_i, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z4backPdS_S_S_S_S_S_S_S_S_S_iiiiS_S_i"
	.size	.L__unnamed_1, 39

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z19__device_stub__backPdS_S_S_S_S_S_S_S_S_S_iiiiS_S_i
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z4backPdS_S_S_S_S_S_S_S_S_S_iiiiS_S_i
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z4backPdS_S_S_S_S_S_S_S_S_S_iiiiS_S_i ; -- Begin function _Z4backPdS_S_S_S_S_S_S_S_S_S_iiiiS_S_i
	.globl	_Z4backPdS_S_S_S_S_S_S_S_S_S_iiiiS_S_i
	.p2align	8
	.type	_Z4backPdS_S_S_S_S_S_S_S_S_S_iiiiS_S_i,@function
_Z4backPdS_S_S_S_S_S_S_S_S_S_iiiiS_S_i: ; @_Z4backPdS_S_S_S_S_S_S_S_S_S_iiiiS_S_i
; %bb.0:
	s_clause 0x5
	s_load_b32 s33, s[0:1], 0x78
	s_load_b256 s[4:11], s[0:1], 0x58
	s_load_b128 s[28:31], s[0:1], 0x0
	s_load_b64 s[2:3], s[0:1], 0x10
	s_load_b256 s[20:27], s[0:1], 0x20
	s_load_b256 s[12:19], s[0:1], 0x40
	v_bfe_u32 v1, v0, 10, 10
	v_and_b32_e32 v0, 0x3ff, v0
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v1, s33, v1
	s_add_i32 s18, s7, -1
	v_mul_lo_u32 v23, v1, s7
	v_mul_lo_u32 v3, v1, s6
	v_cmpx_gt_i32_e64 s6, v0
	s_cbranch_execz .LBB0_4
; %bb.1:
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v6, v3, v0
	v_ashrrev_i32_e32 v2, 31, v1
	s_cmp_lt_i32 s4, 1
	v_ashrrev_i32_e32 v7, 31, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[4:5], 3, v[6:7]
	v_lshlrev_b64 v[7:8], 3, v[1:2]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v9, vcc_lo, s20, v4
	v_add_co_ci_u32_e32 v10, vcc_lo, s21, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v7, vcc_lo, s10, v7
	v_add_co_ci_u32_e32 v8, vcc_lo, s11, v8, vcc_lo
	v_add_co_u32 v4, vcc_lo, s26, v4
	global_load_b64 v[9:10], v[9:10], off
	global_load_b64 v[7:8], v[7:8], off
	v_add_co_ci_u32_e32 v5, vcc_lo, s27, v5, vcc_lo
	s_waitcnt vmcnt(0)
	v_add_f64 v[7:8], v[9:10], -v[7:8]
	global_store_b64 v[4:5], v[7:8], off
	s_cbranch_scc1 .LBB0_4
; %bb.2:                                ; %.lr.ph
	v_add_nc_u32_e32 v2, s18, v23
	v_mul_lo_u32 v6, v6, s4
	s_mov_b32 s1, s4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v8, v2, s4
	v_ashrrev_i32_e32 v7, 31, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v9, 31, v8
	v_lshlrev_b64 v[6:7], 3, v[6:7]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[8:9], 3, v[8:9]
	v_add_co_u32 v6, vcc_lo, s14, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v7, vcc_lo, s15, v7, vcc_lo
	v_add_co_u32 v8, vcc_lo, s28, v8
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v9, vcc_lo, s29, v9, vcc_lo
.LBB0_3:                                ; =>This Inner Loop Header: Depth=1
	global_load_b64 v[10:11], v[4:5], off
	global_load_b64 v[12:13], v[8:9], off
	v_add_co_u32 v8, vcc_lo, v8, 8
	v_add_co_ci_u32_e32 v9, vcc_lo, 0, v9, vcc_lo
	s_add_i32 s1, s1, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u32 s1, 0
	s_waitcnt vmcnt(0)
	v_mul_f64 v[10:11], v[10:11], v[12:13]
	global_store_b64 v[6:7], v[10:11], off
	v_add_co_u32 v6, vcc_lo, v6, 8
	v_add_co_ci_u32_e32 v7, vcc_lo, 0, v7, vcc_lo
	s_cbranch_scc1 .LBB0_3
.LBB0_4:                                ; %.loopexit
	s_or_b32 exec_lo, exec_lo, s0
	s_cmp_lt_i32 s6, 1
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB0_7
; %bb.5:                                ; %.lr.ph201.preheader
	v_ashrrev_i32_e32 v4, 31, v3
	v_dual_mov_b32 v5, 0 :: v_dual_lshlrev_b32 v2, 3, v0
	v_mov_b32_e32 v6, 0
	s_ashr_i32 s1, s4, 31
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[7:8], 3, v[3:4]
	v_add_co_u32 v2, s0, s30, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v3, null, s31, 0, s0
	s_mov_b32 s0, s4
	v_add_co_u32 v7, vcc_lo, s26, v7
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v8, vcc_lo, s27, v8, vcc_lo
	s_lshl_b64 s[0:1], s[0:1], 3
.LBB0_6:                                ; %.lr.ph201
                                        ; =>This Inner Loop Header: Depth=1
	global_load_b64 v[9:10], v[2:3], off
	global_load_b64 v[11:12], v[7:8], off
	v_add_co_u32 v7, vcc_lo, v7, 8
	v_add_co_ci_u32_e32 v8, vcc_lo, 0, v8, vcc_lo
	v_add_co_u32 v2, vcc_lo, v2, s0
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
	s_add_i32 s6, s6, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u32 s6, 0
	s_waitcnt vmcnt(0)
	v_fma_f64 v[5:6], v[9:10], v[11:12], v[5:6]
	s_cbranch_scc1 .LBB0_6
	s_branch .LBB0_8
.LBB0_7:
	v_mov_b32_e32 v5, 0
	v_mov_b32_e32 v6, 0
.LBB0_8:                                ; %._crit_edge
	v_add_nc_u32_e32 v4, s18, v23
	v_mul_lo_u32 v24, v23, s4
	s_cmp_gt_i32 s4, 0
	s_cselect_b32 s0, -1, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[2:3], null, v4, s4, v[0:1]
	v_mul_lo_u32 v4, v1, s4
	s_cmp_lt_i32 s4, 1
	v_ashrrev_i32_e32 v3, 31, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 3, v[2:3]
	v_add_co_u32 v2, vcc_lo, s28, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v3, vcc_lo, s29, v3, vcc_lo
	global_load_b64 v[2:3], v[2:3], off
	s_waitcnt vmcnt(0)
	v_add_f64 v[7:8], -v[2:3], 1.0
	v_mul_f64 v[2:3], v[2:3], v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_f64 v[8:9], v[5:6], v[2:3]
	v_add_nc_u32_e32 v2, v4, v0
	v_ashrrev_i32_e32 v3, 31, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 3, v[2:3]
	v_add_co_u32 v6, vcc_lo, s22, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v7, vcc_lo, s23, v3, vcc_lo
	global_store_b64 v[6:7], v[8:9], off
	s_cbranch_scc1 .LBB0_11
; %bb.9:                                ; %.lr.ph204
	v_mul_lo_u32 v5, v4, s18
	s_add_i32 s1, s7, -2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s1, s1, s4
	v_add_nc_u32_e32 v10, s1, v24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add3_u32 v5, s1, v0, v5
	s_mov_b32 s1, s4
	v_ashrrev_i32_e32 v11, 31, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v8, v5, s4
	v_lshlrev_b64 v[10:11], 3, v[10:11]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v9, 31, v8
	v_lshlrev_b64 v[8:9], 3, v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v8, vcc_lo, s16, v8
	v_add_co_ci_u32_e32 v9, vcc_lo, s17, v9, vcc_lo
	v_add_co_u32 v10, vcc_lo, s28, v10
	v_add_co_ci_u32_e32 v11, vcc_lo, s29, v11, vcc_lo
.LBB0_10:                               ; =>This Inner Loop Header: Depth=1
	global_load_b64 v[12:13], v[6:7], off
	global_load_b64 v[14:15], v[10:11], off
	v_add_co_u32 v10, vcc_lo, v10, 8
	v_add_co_ci_u32_e32 v11, vcc_lo, 0, v11, vcc_lo
	s_add_i32 s1, s1, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u32 s1, 0
	s_waitcnt vmcnt(0)
	v_mul_f64 v[12:13], v[12:13], v[14:15]
	global_store_b64 v[8:9], v[12:13], off
	v_add_co_u32 v8, vcc_lo, v8, 8
	v_add_co_ci_u32_e32 v9, vcc_lo, 0, v9, vcc_lo
	s_cbranch_scc1 .LBB0_10
.LBB0_11:                               ; %._crit_edge205
	v_ashrrev_i32_e32 v5, 31, v4
	v_cndmask_b32_e64 v25, 0, 1, s0
	s_cmp_lt_i32 s7, 3
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB0_20
; %bb.12:                               ; %.preheader197.lr.ph
	v_mul_lo_u32 v8, v1, s18
	v_lshlrev_b64 v[15:16], 3, v[4:5]
	s_add_i32 s1, s7, -2
	s_mul_i32 s6, s4, s4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[10:11], null, s6, s1, v[0:1]
	v_add3_u32 v8, s7, v8, -3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[12:13], null, s4, v8, v[0:1]
	v_add3_u32 v13, v23, s7, -3
	v_add_co_u32 v8, vcc_lo, s24, v2
	v_add_co_ci_u32_e32 v9, vcc_lo, s25, v3, vcc_lo
	v_mul_lo_u32 v11, s4, v13
	v_mul_lo_u32 v13, s4, v12
	v_add_co_u32 v15, vcc_lo, s22, v15
	v_add_co_ci_u32_e32 v16, vcc_lo, s23, v16, vcc_lo
.LBB0_13:                               ; %.preheader197
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_15 Depth 2
                                        ;     Child Loop BB0_18 Depth 2
	v_mov_b32_e32 v17, 0
	v_mov_b32_e32 v18, 0
	s_and_not1_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccnz .LBB0_16
; %bb.14:                               ; %.lr.ph208
                                        ;   in Loop: Header=BB0_13 Depth=1
	v_dual_mov_b32 v19, v10 :: v_dual_mov_b32 v22, v16
	v_mov_b32_e32 v21, v15
	s_mov_b32 s7, s4
.LBB0_15:                               ;   Parent Loop BB0_13 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_ashrrev_i32_e32 v20, 31, v19
	s_add_i32 s7, s7, -1
	s_cmp_lg_u32 s7, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[26:27], 3, v[19:20]
	v_add_nc_u32_e32 v19, s4, v19
	v_add_co_u32 v26, vcc_lo, s2, v26
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v27, vcc_lo, s3, v27, vcc_lo
	global_load_b64 v[28:29], v[21:22], off
	global_load_b64 v[26:27], v[26:27], off
	v_add_co_u32 v21, vcc_lo, v21, 8
	v_add_co_ci_u32_e32 v22, vcc_lo, 0, v22, vcc_lo
	s_waitcnt vmcnt(0)
	v_fma_f64 v[17:18], v[26:27], v[28:29], v[17:18]
	s_cbranch_scc1 .LBB0_15
.LBB0_16:                               ; %._crit_edge209
                                        ;   in Loop: Header=BB0_13 Depth=1
	v_add_nc_u32_e32 v12, s1, v23
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[19:20], null, v12, s4, v[0:1]
	v_ashrrev_i32_e32 v20, 31, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[19:20], 3, v[19:20]
	v_add_co_u32 v19, vcc_lo, s28, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v20, vcc_lo, s29, v20, vcc_lo
	s_and_not1_b32 vcc_lo, exec_lo, s0
	global_load_b64 v[19:20], v[19:20], off
	s_waitcnt vmcnt(0)
	v_add_f64 v[21:22], -v[19:20], 1.0
	v_mul_f64 v[19:20], v[19:20], v[21:22]
	s_delay_alu instid0(VALU_DEP_1)
	v_mul_f64 v[17:18], v[17:18], v[19:20]
	global_store_b64 v[8:9], v[17:18], off
	s_cbranch_vccnz .LBB0_19
; %bb.17:                               ; %.lr.ph213
                                        ;   in Loop: Header=BB0_13 Depth=1
	v_ashrrev_i32_e32 v14, 31, v13
	v_ashrrev_i32_e32 v12, 31, v11
	s_mov_b32 s7, s4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[17:18], 3, v[13:14]
	v_lshlrev_b64 v[19:20], 3, v[11:12]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v17, vcc_lo, s16, v17
	v_add_co_ci_u32_e32 v18, vcc_lo, s17, v18, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v19, vcc_lo, s28, v19
	v_add_co_ci_u32_e32 v20, vcc_lo, s29, v20, vcc_lo
.LBB0_18:                               ;   Parent Loop BB0_13 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	global_load_b64 v[21:22], v[8:9], off
	global_load_b64 v[26:27], v[19:20], off
	v_add_co_u32 v19, vcc_lo, v19, 8
	v_add_co_ci_u32_e32 v20, vcc_lo, 0, v20, vcc_lo
	s_add_i32 s7, s7, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u32 s7, 0
	s_waitcnt vmcnt(0)
	v_mul_f64 v[21:22], v[21:22], v[26:27]
	global_store_b64 v[17:18], v[21:22], off
	v_add_co_u32 v17, vcc_lo, v17, 8
	v_add_co_ci_u32_e32 v18, vcc_lo, 0, v18, vcc_lo
	s_cbranch_scc1 .LBB0_18
.LBB0_19:                               ; %._crit_edge214
                                        ;   in Loop: Header=BB0_13 Depth=1
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	global_load_b64 v[17:18], v[8:9], off
	v_subrev_nc_u32_e32 v10, s6, v10
	v_subrev_nc_u32_e32 v13, s6, v13
	v_subrev_nc_u32_e32 v11, s4, v11
	s_add_i32 s7, s1, -1
	s_cmp_lt_i32 s1, 2
	s_mov_b32 s1, s7
	s_waitcnt vmcnt(0)
	global_store_b64 v[6:7], v[17:18], off
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc0 .LBB0_13
.LBB0_20:                               ; %.preheader
	v_cmp_ne_u32_e32 vcc_lo, 1, v25
	s_cbranch_vccnz .LBB0_23
; %bb.21:                               ; %.lr.ph218.preheader
	v_lshlrev_b64 v[8:9], 3, v[4:5]
	v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v7, 0
	v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v6, v0
	s_mov_b32 s0, s4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v8, vcc_lo, s22, v8
	v_add_co_ci_u32_e32 v9, vcc_lo, s23, v9, vcc_lo
.LBB0_22:                               ; %.lr.ph218
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_lshlrev_b64 v[10:11], 3, v[6:7]
	v_add_nc_u32_e32 v6, s4, v6
	s_add_i32 s0, s0, -1
	s_cmp_lg_u32 s0, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v10, vcc_lo, s2, v10
	v_add_co_ci_u32_e32 v11, vcc_lo, s3, v11, vcc_lo
	global_load_b64 v[12:13], v[8:9], off
	global_load_b64 v[10:11], v[10:11], off
	v_add_co_u32 v8, vcc_lo, v8, 8
	v_add_co_ci_u32_e32 v9, vcc_lo, 0, v9, vcc_lo
	s_waitcnt vmcnt(0)
	v_fma_f64 v[4:5], v[10:11], v[12:13], v[4:5]
	s_cbranch_scc1 .LBB0_22
	s_branch .LBB0_24
.LBB0_23:
	v_mov_b32_e32 v4, 0
	v_mov_b32_e32 v5, 0
.LBB0_24:                               ; %._crit_edge219
	v_add_nc_u32_e32 v6, v24, v0
	s_cmp_lt_i32 s5, 1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v7, 31, v6
	v_lshlrev_b64 v[6:7], 3, v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v6, vcc_lo, s28, v6
	v_add_co_ci_u32_e32 v7, vcc_lo, s29, v7, vcc_lo
	v_add_co_u32 v2, vcc_lo, s24, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s25, v3, vcc_lo
	global_load_b64 v[6:7], v[6:7], off
	s_waitcnt vmcnt(0)
	v_add_f64 v[8:9], -v[6:7], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[6:7], v[6:7], v[8:9]
	v_mul_f64 v[4:5], v[4:5], v[6:7]
	global_store_b64 v[2:3], v[4:5], off
	s_cbranch_scc1 .LBB0_27
; %bb.25:                               ; %.lr.ph223
	v_mul_lo_u32 v4, v1, s5
	v_mul_lo_u32 v0, v0, s5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v5, 31, v4
	v_mad_u64_u32 v[6:7], null, v4, s4, v[0:1]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[4:5], 3, v[4:5]
	v_ashrrev_i32_e32 v7, 31, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 3, v[6:7]
	v_add_co_u32 v0, vcc_lo, s12, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s13, v1, vcc_lo
	v_add_co_u32 v4, vcc_lo, s8, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s9, v5, vcc_lo
.LBB0_26:                               ; =>This Inner Loop Header: Depth=1
	global_load_b64 v[6:7], v[2:3], off
	global_load_b64 v[8:9], v[4:5], off
	v_add_co_u32 v4, vcc_lo, v4, 8
	v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
	s_add_i32 s5, s5, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u32 s5, 0
	s_waitcnt vmcnt(0)
	v_mul_f64 v[6:7], v[6:7], v[8:9]
	global_store_b64 v[0:1], v[6:7], off
	v_add_co_u32 v0, vcc_lo, v0, 8
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
	s_cbranch_scc1 .LBB0_26
.LBB0_27:                               ; %._crit_edge224
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z4backPdS_S_S_S_S_S_S_S_S_S_iiiiS_S_i
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 124
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 30
		.amdhsa_next_free_sgpr 34
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z4backPdS_S_S_S_S_S_S_S_S_S_iiiiS_S_i, .Lfunc_end0-_Z4backPdS_S_S_S_S_S_S_S_S_S_iiiiS_S_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1964
; NumSgprs: 36
; NumVgprs: 30
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 4
; VGPRBlocks: 3
; NumSGPRsForWavesPerEU: 36
; NumVGPRsForWavesPerEU: 30
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         48
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         56
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         64
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         72
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         80
        .size:           8
        .value_kind:     global_buffer
      - .offset:         88
        .size:           4
        .value_kind:     by_value
      - .offset:         92
        .size:           4
        .value_kind:     by_value
      - .offset:         96
        .size:           4
        .value_kind:     by_value
      - .offset:         100
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         104
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         112
        .size:           8
        .value_kind:     global_buffer
      - .offset:         120
        .size:           4
        .value_kind:     by_value
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 124
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z4backPdS_S_S_S_S_S_S_S_S_S_iiiiS_S_i
    .private_segment_fixed_size: 0
    .sgpr_count:     36
    .sgpr_spill_count: 0
    .symbol:         _Z4backPdS_S_S_S_S_S_S_S_S_S_iiiiS_S_i.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     30
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
