#include <stdio.h>
#include <stdlib.h>
#include <time.h>

/*
配列の形

node 0:state
     1:height
     2:out_root_id
     3:in_root_id
     4:source,sinkにつながっているかのflg

edge 0:flow
     1:reverse_id
     2:in_node_id
     3:out_node_id
     4:in_link_id
     5:out_link_id
     6:id
*/

#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(cudaError_t code, const char *file, int line, bool abort=true)
{
  if (code != cudaSuccess) {
    fprintf(stderr,"GPUassert: %s %s %d\n", cudaGetErrorString(code), file, line);
    if (abort) exit(code);
  }
}
  
#define NODE 7
#define EDGE 7

#define NADR(NUM, ID, EL) (NUM * EL + ID)
#define EADR(NUM, ID, EL) ((NUM * 2) * EL + ID)

//node
#define STATE 0
#define HEIGHT 1
#define OUT_ROOT 2
#define IN_ROOT 3
#define ST_FLG 4
#define ACTIVE 5
#define N_ROUTE 6

//edge
#define FLOW 0
#define ROUTE 1
#define REVERSE 2
#define IN_NODE 3
#define IN_LINK 4
#define OUT_NODE 5
#define OUT_LINK 6

int *N_NUM;
int *E_NUM;
int *n_table;
int *e_table;
int *source;
int *sink;

void link(int e_table, int from, int to, int r_edge, int flow);
int load(FILE *fp);

__global__ void first_reset(int *n_table, int *e_table, int *source, int *sink, int *N_NUM, int *E_NUM) {
  int total_id = blockDim.x * blockIdx.x + threadIdx.x;
  if (total_id >= N_NUM[0]) return;
  if (total_id == source[0]) {
    n_table[NADR(N_NUM[0], total_id, STATE)] = 1;
    n_table[NADR(N_NUM[0], total_id, HEIGHT)] = 0;
    n_table[NADR(N_NUM[0], total_id, ACTIVE)] = 0;
    n_table[NADR(N_NUM[0], total_id, N_ROUTE)] = 0;
    return;
  }
  else if (total_id == sink[0]) {
    n_table[NADR(N_NUM[0], total_id, STATE)] = 2;
    n_table[NADR(N_NUM[0], total_id, HEIGHT)] = 0;
    n_table[NADR(N_NUM[0], total_id, ACTIVE)] = 0;
    n_table[NADR(N_NUM[0], total_id, N_ROUTE)] = 0;
    return;
  }
  else if (n_table[NADR(N_NUM[0], total_id, ST_FLG)] != -1) {
    int f_flg = n_table[NADR(N_NUM[0], total_id, ST_FLG)];
    int in_node = e_table[EADR(E_NUM[0], f_flg, IN_NODE)];
    n_table[NADR(N_NUM[0], total_id, HEIGHT)] = 1;
    n_table[NADR(N_NUM[0], total_id, ACTIVE)] = 1;
    n_table[NADR(N_NUM[0], total_id, N_ROUTE)] = 1;
    if (in_node == source[0]) n_table[NADR(N_NUM[0], total_id, STATE)] = 1;
    else n_table[NADR(N_NUM[0], total_id, STATE)] = 2;
  }
}

__global__ void node_reset(int *n_table, int *e_table, int *source, int *sink, int *N_NUM, int *E_NUM, int *e_flg) {
  int total_id = blockDim.x * blockIdx.x + threadIdx.x;
  if (total_id >= N_NUM[0]) return;
  if (total_id == source[0] || total_id == sink[0]) return;
  if (n_table[NADR(N_NUM[0], total_id, ST_FLG)] == -1) {
    n_table[NADR(N_NUM[0], total_id, HEIGHT)] = N_NUM[0];
    n_table[NADR(N_NUM[0], total_id, STATE)] = 0;
    n_table[NADR(N_NUM[0], total_id, ACTIVE)] = 0;
    n_table[NADR(N_NUM[0], total_id, N_ROUTE)] = 0;
    return;
  }
  else {
    n_table[NADR(N_NUM[0], total_id, ACTIVE)] = 1;
    int f_flg = n_table[NADR(N_NUM[0], total_id, ST_FLG)];
    if (e_table[EADR(E_NUM[0], f_flg, FLOW)] == 0) {
      n_table[NADR(N_NUM[0], total_id, HEIGHT)] = N_NUM[0];
      n_table[NADR(N_NUM[0], total_id, STATE)] = 0;
      n_table[NADR(N_NUM[0], total_id, ACTIVE)] = 0;
      n_table[NADR(N_NUM[0], total_id, N_ROUTE)] = 0;
      n_table[NADR(N_NUM[0], total_id, ST_FLG)] = -1;
    }
  }
}

__global__ void trace_cu(int *n_table, int *e_table, int *flg3, int *que3, int *N_NUM, int *E_NUM, int *flg1, int *e_flg) {
  flg1[0] = 0;
  int node_id = blockDim.x * blockIdx.x + threadIdx.x;
  if (node_id >= N_NUM[0]) return;

  __shared__ int n_num[1];
  n_num[0] = N_NUM[0];
  __shared__ int e_num[1];
  e_num[0] = E_NUM[0];

  if (n_table[NADR(n_num[0], node_id, ACTIVE)] != 1) return;
  int state, look_n, root, link;
  if (n_table[NADR(n_num[0], node_id, STATE)] == 1) {
    state = 1;
    look_n = OUT_NODE;
    root = OUT_ROOT;
    link = OUT_LINK;
  }
  else {
    state = 2;
    look_n = IN_NODE;
    root = IN_ROOT;
    link = IN_LINK;
  }
  int old;
  int lok_node;
  int edge_id = n_table[NADR(n_num[0], node_id, root)];
  for (;;) {
    for (;;) {
      if (edge_id == -1) {
	n_table[NADR(n_num[0], node_id, ACTIVE)] = 0;
	return;
      }
      if (e_table[EADR(e_num[0], edge_id, FLOW)] > 0) break;
      edge_id = e_table[EADR(e_num[0], edge_id, link)];
    }
    lok_node = e_table[EADR(e_num[0], edge_id, look_n)];
    if (n_table[NADR(n_num[0], lok_node, STATE)] == 0) {
      //old = atomicExch(&e_flg[lok_node], 1);
      old = atomicAdd(&n_table[NADR(n_num[0], lok_node, N_ROUTE)], 1);
      if (old == 0) {
	n_table[NADR(n_num[0], lok_node, STATE)] = state;
	n_table[NADR(n_num[0], lok_node, HEIGHT)] = n_table[NADR(n_num[0], node_id, HEIGHT)] + 1;
	n_table[NADR(n_num[0], lok_node, ACTIVE)] = 1;
	flg1[0] = 1;
      }
    }
    else if (n_table[NADR(n_num[0], lok_node, STATE)] != state) {
      old = atomicAdd(&(flg3[0]), 1);
      que3[old] = edge_id;
    }
    edge_id = e_table[EADR(e_num[0], edge_id, link)];
  }
}

__device__ void flow_t(int *n_table, int *e_table, int flow, int pre_edge, int edge, int N_NUM, int E_NUM, int tag, int *flg1) {
  int link = IN_NODE;

  int old = atomicSub(&e_table[EADR(E_NUM, edge, FLOW)], flow);
  int reverse = e_table[EADR(E_NUM, edge, REVERSE)];
  atomicAdd(&e_table[EADR(E_NUM, reverse, FLOW)], flow);
  int l_node = e_table[EADR(E_NUM, edge, link)];
  if (old == flow) {
    old = atomicSub(&n_table[NADR(N_NUM, l_node, N_ROUTE)], 1);
    if (old == 1) atomicAdd(&flg1[0], 1);
  }

  for (;;) {
    old = atomicSub(&e_table[EADR(E_NUM, pre_edge, FLOW)], flow);
    reverse = e_table[EADR(E_NUM, pre_edge, REVERSE)];
    atomicAdd(&e_table[EADR(E_NUM, reverse, FLOW)], flow);
    if (pre_edge == tag) {
      if (old == flow) atomicAdd(&flg1[0], 1);
      break;
    }
    l_node = e_table[EADR(E_NUM, edge, link)];
    if (l_node == e_table[EADR(E_NUM, tag, link)]) link = OUT_NODE;
    if (old == flow) {
      old = atomicSub(&n_table[NADR(N_NUM, l_node, N_ROUTE)], 1);
      if (old == 1) atomicAdd(&flg1[0], 1);
    }
    pre_edge = e_table[EADR(E_NUM, pre_edge, ROUTE)];
  }
}

__global__ void aug_cu(int *n_table, int *e_table, int *flg3, int *que3, int *source, int *sink, int *e_flg, int *flow_sum, int *N_NUM, int *E_NUM, int *flg1) {
  int total_id = blockDim.x * blockIdx.x + threadIdx.x;
  if (total_id >= flg3[0]) return;
  int tag = que3[total_id];
  int old = atomicExch(&e_flg[tag], 1);
  if (old != 0) return;
  int pre_edge = tag;

  __shared__ int n_num[1];
  n_num[0] = N_NUM[0];
  __shared__ int e_num[1];

  e_num[0] = E_NUM[0];
  int flow = e_table[EADR(e_num[0], tag, FLOW)];
  if (flow == 0) return;
  int node = e_table[EADR(e_num[0], tag, IN_NODE)];
  int state = 1;
  int height = n_table[NADR(N_NUM[0], node, HEIGHT)] - 1;

  int root = IN_ROOT;
  int look_n = IN_NODE;
  int link = IN_LINK;
  for (;;) {
    int edge_id = n_table[NADR(n_num[0], node, root)];
    int flow1;
    int lok_node;
    for (;;) {
      if (edge_id == -1) return;
      flow1 = e_table[EADR(e_num[0], edge_id, FLOW)];
      lok_node = e_table[EADR(e_num[0], edge_id, look_n)];
      if (flow1 > 0) {
	if (n_table[NADR(n_num[0], lok_node, HEIGHT)] == height) {
	  if (n_table[NADR(n_num[0], lok_node, STATE)] == state) {
	    old = atomicExch(&e_flg[edge_id], 1);
	    if (old == 0) {
	      flow = ((flow > flow1) ? flow1 : flow);
	      break;
	    }
	  }
	}
      }
      edge_id = e_table[EADR(e_num[0], edge_id, link)];
    }
    if (lok_node == sink[0]) {
      flow_t(n_table, e_table, flow, pre_edge, edge_id, n_num[0], e_num[0], tag, flg1);
      atomicAdd(&flow_sum[0], flow);
      return;
    }
    else if (lok_node == source[0]) {
      node = e_table[EADR(e_num[0], tag, OUT_NODE)];
      height = n_table[NADR(n_num[0], node, HEIGHT)] - 1;
      state = 2;

      root = OUT_ROOT;
      look_n = OUT_NODE;
      link = OUT_LINK;
    }
    else {
      node = lok_node;
      height--;
    }
    e_table[EADR(e_num[0], edge_id, ROUTE)] = pre_edge;
    pre_edge = edge_id;
  }
}

__global__ void flg_reset(int *flg) {
  flg[0] = 0;
}

int main(int argc, char **argv) {
  if (argc != 2) {
    printf("Usage: ./bk.exe file.inp\n");
    return 1;
  }
  FILE *fp = fopen(argv[1], "r");
  if (fp == NULL) {
    printf("Can't open file [%s]\n", argv[1]);
    return 1;
  }
  int max = load(fp);
  fclose(fp);

  if (max == -1) return 0;//ファイルの形式がおかしい時return

  clock_t start, end;//時間計測用

  //hostの変数確保
  int *flg1, *flg3;
  gpuErrchk ( cudaMallocHost(&flg1, sizeof(int)) );
  gpuErrchk ( cudaMallocHost(&flg3, sizeof(int)) );
  int *flow_sum;
  gpuErrchk ( cudaMallocHost(&flow_sum, sizeof(int)) );

  size_t C_SIZE = sizeof(int);
  size_t N_SIZE = sizeof(int) * N_NUM[0] * NODE;
  size_t E_SIZE = sizeof(int) * E_NUM[0] * EDGE * 2;

  //deviceの変数確保
  int *DN_NUM;
  int *DE_NUM;
  int *nd_table;
  int *ed_table;
  int *d_flg1, *d_flg3;
  int *d_que3;
  int *d_source, *d_sink;
  int *dflow_sum;
  int *de_flg;
  int *d_cnt;

  gpuErrchk( cudaMalloc((void**)&DN_NUM, C_SIZE) );
  gpuErrchk( cudaMalloc((void**)&DE_NUM, C_SIZE) );
  gpuErrchk( cudaMalloc((void**)&d_flg1, C_SIZE) );
  gpuErrchk( cudaMalloc((void**)&d_flg3, C_SIZE) );
  gpuErrchk( cudaMalloc((void**)&d_que3, sizeof(int) * E_NUM[0]) );
  gpuErrchk( cudaMalloc((void**)&nd_table, N_SIZE) );
  gpuErrchk( cudaMalloc((void**)&ed_table, E_SIZE) );
  gpuErrchk( cudaMalloc((void**)&d_source, C_SIZE) );
  gpuErrchk( cudaMalloc((void**)&d_sink, C_SIZE) );
  gpuErrchk( cudaMalloc((void**)&dflow_sum, C_SIZE) );
  gpuErrchk( cudaMalloc((void**)&de_flg, sizeof(int) * E_NUM[0] * 2) );
  gpuErrchk (cudaMalloc((void**)&d_cnt, sizeof(int)) );

  //deviceへのコピー
  gpuErrchk( cudaMemcpy(nd_table, n_table, N_SIZE, cudaMemcpyHostToDevice) );
  gpuErrchk( cudaMemcpy(ed_table, e_table, E_SIZE, cudaMemcpyHostToDevice) );
  gpuErrchk( cudaMemcpy(d_source, source, C_SIZE, cudaMemcpyHostToDevice) );
  gpuErrchk( cudaMemcpy(d_sink, sink, C_SIZE, cudaMemcpyHostToDevice) );
  gpuErrchk( cudaMemcpy(DN_NUM, N_NUM, C_SIZE, cudaMemcpyHostToDevice) );
  gpuErrchk( cudaMemcpy(DE_NUM, E_NUM, C_SIZE, cudaMemcpyHostToDevice) );

  //計測開始
  start = clock();

  flg_reset<<<1, 1>>>(dflow_sum);//flow_sumを初期化
  first_reset<<<(N_NUM[0] / 32) + 1, 32>>>(nd_table, ed_table, d_source, d_sink, DN_NUM, DE_NUM);
  for (;;) {
    flg_reset<<<1, 1>>>(d_flg3);
    node_reset<<<(N_NUM[0] / 32) + 1, 32>>>(nd_table, ed_table, d_source, d_sink, DN_NUM, DE_NUM, de_flg);
    gpuErrchk( cudaThreadSynchronize() );
    //growth stage
    for (;;) {
      trace_cu<<<(N_NUM[0] / 56) + 1, 56>>>(nd_table, ed_table, d_flg3, d_que3, DN_NUM, DE_NUM, d_flg1, de_flg);
      gpuErrchk( cudaThreadSynchronize() );
      gpuErrchk( cudaMemcpy(flg1, d_flg1, C_SIZE, cudaMemcpyDeviceToHost) );
      if (flg1[0] == 0) break;
    }

    //ぶつかったエッジがあったかを確認
    gpuErrchk( cudaMemcpy(flg3, d_flg3, C_SIZE, cudaMemcpyDeviceToHost) );
    if (flg3[0] == 0) break;

    //augmentation stage
    for (int i = 0; i < 3; i++) {
      gpuErrchk( cudaMemset((void**)de_flg, 0, sizeof(int) * E_NUM[0] * 2) );
      aug_cu<<<(flg3[0] / 32) + 1, 32>>>(nd_table, ed_table, d_flg3, d_que3, d_source, d_sink, de_flg, dflow_sum, DN_NUM, DE_NUM, d_flg1);
      gpuErrchk( cudaThreadSynchronize() );
    }

    gpuErrchk( cudaMemcpy(flg1, d_flg1, C_SIZE, cudaMemcpyDeviceToHost) );

    gpuErrchk( cudaMemcpy(flow_sum, dflow_sum, C_SIZE, cudaMemcpyDeviceToHost) );
    printf("current_flow : %d\n", flow_sum[0]);
  }

  printf("flow_sum : %d\n", flow_sum[0]);
  end = clock();
  //計測終了
  printf("time:%.2f[s]\n", (double)(end - start) / CLOCKS_PER_SEC);

  cudaFree(DN_NUM);
  cudaFree(DE_NUM);
  cudaFree(nd_table);
  cudaFree(ed_table);
  cudaFree(d_flg1);
  cudaFree(d_flg3);
  cudaFree(d_que3);
  cudaFree(d_source);
  cudaFree(d_sink);
  cudaFree(dflow_sum);
  cudaFree(d_cnt);
  cudaFree(de_flg);

  cudaFreeHost(flg1);
  cudaFreeHost(flg3);
  cudaFreeHost(n_table);
  cudaFreeHost(e_table);
  cudaFreeHost(source);
  cudaFreeHost(sink);
  cudaFreeHost(flow_sum);
  cudaFreeHost(N_NUM);
  cudaFreeHost(E_NUM);

  return 0;
}

void link(int *n_table, int *e_table, int from, int to, int flow, int edge_id, int *count) {
  int edge = n_table[NADR(N_NUM[0], from, OUT_ROOT)];
  for (;;) {
    if (edge == -1) break;
    if (e_table[EADR(E_NUM[0], edge, OUT_NODE)] == to) {
      e_table[EADR(E_NUM[0], edge, FLOW)] += flow;
      count[0]++;
      return;
    }
    edge = e_table[EADR(E_NUM[0], edge, OUT_LINK)];
  }
  //正のエッジ
  e_table[EADR(E_NUM[0], edge_id, REVERSE)] = edge_id + 1;
  e_table[EADR(E_NUM[0], edge_id, FLOW)] = flow;
  e_table[EADR(E_NUM[0], edge_id, IN_NODE)] = from;
  e_table[EADR(E_NUM[0], edge_id, OUT_NODE)] = to;
  e_table[EADR(E_NUM[0], edge_id, OUT_LINK)] = n_table[NADR(N_NUM[0], from, OUT_ROOT)];
  n_table[NADR(N_NUM[0], from, OUT_ROOT)] = edge_id;
  e_table[EADR(E_NUM[0], edge_id, IN_LINK)] = n_table[NADR(N_NUM[0], to, IN_ROOT)];
  n_table[NADR(N_NUM[0], to, IN_ROOT)] = edge_id;
  if (from == source[0]) {
    n_table[NADR(N_NUM[0], to, ST_FLG)] = edge_id;
  }
  if (to == sink[0]) {
    n_table[NADR(N_NUM[0], from, ST_FLG)] = edge_id;
  }

  //逆(reverse)のエッジ
  e_table[EADR(E_NUM[0], (edge_id + 1), REVERSE)] = edge_id;
  e_table[EADR(E_NUM[0], (edge_id + 1), FLOW)] = 0;
  e_table[EADR(E_NUM[0], (edge_id + 1), IN_NODE)] = to;
  e_table[EADR(E_NUM[0], (edge_id + 1), OUT_NODE)] = from;
  e_table[EADR(E_NUM[0], (edge_id + 1), OUT_LINK)] = n_table[NADR(N_NUM[0], to, OUT_ROOT)];
  n_table[NADR(N_NUM[0], to, OUT_ROOT)] = edge_id + 1;
  e_table[EADR(E_NUM[0], (edge_id + 1), IN_LINK)] = n_table[NADR(N_NUM[0], from, IN_ROOT)];
  n_table[NADR(N_NUM[0], from, IN_ROOT)] = edge_id + 1;
}

int load(FILE *fp) {
  int max = 0;
  char s1[10], s2[10];
  gpuErrchk( cudaMallocHost(&N_NUM, sizeof(int)) );
  gpuErrchk( cudaMallocHost(&E_NUM, sizeof(int)) );
  int result = fscanf(fp, "%s %s %d %d\n", s1, s2, &N_NUM[0], &E_NUM[0]);
  if (result == EOF) return -1;
  gpuErrchk( cudaMallocHost(&n_table, sizeof(int) * N_NUM[0] * NODE) );
  gpuErrchk( cudaMallocHost(&e_table, sizeof(int) * E_NUM[0] * EDGE * 2) );

  for (int i = 0; i < N_NUM[0]; i++) {
    n_table[NADR(N_NUM[0], i, OUT_ROOT)] = -1;
    n_table[NADR(N_NUM[0], i, IN_ROOT)] = -1;
    n_table[NADR(N_NUM[0], i, ST_FLG)] = -1;
  }
  for (int i = 0; i < E_NUM[0] * 2; i++) {
    e_table[EADR(E_NUM[0], i, REVERSE)] = -1;
    e_table[EADR(E_NUM[0], i, IN_NODE)] = -1;
    e_table[EADR(E_NUM[0], i, OUT_NODE)] = -1;
    e_table[EADR(E_NUM[0], i, IN_LINK)] = -1;
    e_table[EADR(E_NUM[0], i, OUT_LINK)] = -1;
  }
  int t;
  result = fscanf(fp, "%s %d %s\n", s1, &t, s2);
  if (result == EOF) return -1;
  cudaMallocHost(&source, sizeof(int));
  source[0] = t;
  result = fscanf(fp, "%s %d %s\n", s1, &t, s2);
  if (result == EOF) return -1;
  cudaMallocHost(&sink, sizeof(int));
  sink[0] = t;

  int *count;
  count = new int[1]();
  for (int i = 0; i < E_NUM[0]; i++) {
    int from, to, flow;
    result = fscanf(fp, "%s %d %d %d\n", s1, &from, &to, &flow);
    if (result == EOF) break;
    if (flow > max) max = flow;
    link(n_table, e_table, from, to, flow, (i - count[0]) * 2, count);
  }
  delete[] count;

  return max;
}

	.file	"tmpxft_00309fd4_00000000-6_sub.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2034:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2034:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.section	.rodata._Z9gpuAssert9cudaErrorPKcib.str1.1,"aMS",@progbits,1
.LC0:
	.string	"GPUassert: %s %s %d\n"
	.section	.text._Z9gpuAssert9cudaErrorPKcib,"axG",@progbits,_Z9gpuAssert9cudaErrorPKcib,comdat
	.weak	_Z9gpuAssert9cudaErrorPKcib
	.type	_Z9gpuAssert9cudaErrorPKcib, @function
_Z9gpuAssert9cudaErrorPKcib:
.LFB2027:
	.cfi_startproc
	endbr64
	testl	%edi, %edi
	je	.L8
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	movl	%ecx, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 24
	.cfi_offset 3, -24
	movl	%edi, %ebx
	subq	$24, %rsp
	.cfi_def_cfa_offset 48
	movl	%edx, 12(%rsp)
	movq	%rsi, (%rsp)
	call	cudaGetErrorString@PLT
	movl	12(%rsp), %r9d
	movq	(%rsp), %r8
	leaq	.LC0(%rip), %rdx
	movq	stderr(%rip), %rdi
	movq	%rax, %rcx
	movl	$2, %esi
	xorl	%eax, %eax
	call	__fprintf_chk@PLT
	testb	%bpl, %bpl
	je	.L2
	movl	%ebx, %edi
	call	exit@PLT
.L2:
	addq	$24, %rsp
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	ret
.L8:
	.cfi_restore 3
	.cfi_restore 6
	ret
	.cfi_endproc
.LFE2027:
	.size	_Z9gpuAssert9cudaErrorPKcib, .-_Z9gpuAssert9cudaErrorPKcib
	.text
	.globl	_Z6flow_tPiS_iiiiiiS_
	.type	_Z6flow_tPiS_iiiiiiS_, @function
_Z6flow_tPiS_iiiiiiS_:
.LFB2028:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2028:
	.size	_Z6flow_tPiS_iiiiiiS_, .-_Z6flow_tPiS_iiiiiiS_
	.globl	_Z4linkPiS_iiiiS_
	.type	_Z4linkPiS_iiiiS_, @function
_Z4linkPiS_iiiiS_:
.LFB2030:
	.cfi_startproc
	endbr64
	movl	%ecx, %r10d
	movq	N_NUM(%rip), %rcx
	pushq	%r14
	.cfi_def_cfa_offset 16
	.cfi_offset 14, -16
	movq	%rsi, %rax
	movq	E_NUM(%rip), %r11
	pushq	%r13
	.cfi_def_cfa_offset 24
	.cfi_offset 13, -24
	movl	%edx, %esi
	pushq	%r12
	.cfi_def_cfa_offset 32
	.cfi_offset 12, -32
	pushq	%rbp
	.cfi_def_cfa_offset 40
	.cfi_offset 6, -40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	.cfi_offset 3, -48
	movl	(%rcx), %edx
	movl	(%r11), %ebx
	movq	48(%rsp), %rbp
	leal	(%rsi,%rdx,2), %edx
	movslq	%edx, %rdx
	imull	$10, %ebx, %r13d
	imull	$12, %ebx, %r12d
	movslq	(%rdi,%rdx,4), %rdx
.L18:
	cmpl	$-1, %edx
	je	.L15
	leal	0(%r13,%rdx), %r14d
	movslq	%r14d, %r14
	cmpl	%r10d, (%rax,%r14,4)
	jne	.L16
	addl	%r8d, (%rax,%rdx,4)
	incl	0(%rbp)
	jmp	.L14
.L16:
	addl	%r12d, %edx
	movslq	%edx, %rdx
	movslq	(%rax,%rdx,4), %rdx
	jmp	.L18
.L15:
	leal	(%r9,%rbx,4), %ebx
	movslq	%r9d, %rbp
	leal	1(%r9), %edx
	movslq	%ebx, %rbx
	movl	%edx, (%rax,%rbx,4)
	leaq	0(,%rbp,4), %rbx
	movl	%r8d, (%rax,%rbp,4)
	imull	$6, (%r11), %r8d
	addl	%r9d, %r8d
	movslq	%r8d, %r8
	movl	%esi, (%rax,%r8,4)
	imull	$10, (%r11), %r8d
	addl	%r9d, %r8d
	movslq	%r8d, %r8
	movl	%r10d, (%rax,%r8,4)
	movl	(%rcx), %r8d
	leal	(%rsi,%r8,2), %r8d
	movslq	%r8d, %r8
	movl	(%rdi,%r8,4), %ebp
	imull	$12, (%r11), %r8d
	addl	%r9d, %r8d
	movslq	%r8d, %r8
	movl	%ebp, (%rax,%r8,4)
	movl	(%rcx), %r8d
	leal	(%rsi,%r8,2), %r8d
	movslq	%r8d, %r8
	movl	%r9d, (%rdi,%r8,4)
	imull	$3, (%rcx), %r8d
	addl	%r10d, %r8d
	movslq	%r8d, %r8
	movl	(%rdi,%r8,4), %ebp
	movl	(%r11), %r8d
	leal	(%r9,%r8,8), %r8d
	movslq	%r8d, %r8
	movl	%ebp, (%rax,%r8,4)
	imull	$3, (%rcx), %r8d
	addl	%r10d, %r8d
	movslq	%r8d, %r8
	movl	%r9d, (%rdi,%r8,4)
	movq	source(%rip), %r8
	cmpl	%esi, (%r8)
	jne	.L19
	movl	(%rcx), %r8d
	leal	(%r10,%r8,4), %r8d
	movslq	%r8d, %r8
	movl	%r9d, (%rdi,%r8,4)
.L19:
	movq	sink(%rip), %r8
	cmpl	%r10d, (%r8)
	jne	.L20
	movl	(%rcx), %r8d
	leal	(%rsi,%r8,4), %r8d
	movslq	%r8d, %r8
	movl	%r9d, (%rdi,%r8,4)
.L20:
	movl	(%r11), %r8d
	leal	(%rdx,%r8,4), %r8d
	movslq	%r8d, %r8
	movl	%r9d, (%rax,%r8,4)
	xorl	%r8d, %r8d
	movl	%r8d, 4(%rax,%rbx)
	imull	$6, (%r11), %r8d
	addl	%edx, %r8d
	movslq	%r8d, %r8
	movl	%r10d, (%rax,%r8,4)
	imull	$10, (%r11), %r8d
	addl	%edx, %r8d
	movslq	%r8d, %r8
	movl	%esi, (%rax,%r8,4)
	movl	(%rcx), %r8d
	leal	(%r10,%r8,2), %r8d
	movslq	%r8d, %r8
	movl	(%rdi,%r8,4), %r9d
	imull	$12, (%r11), %r8d
	addl	%edx, %r8d
	movslq	%r8d, %r8
	movl	%r9d, (%rax,%r8,4)
	movl	(%rcx), %r8d
	leal	(%r10,%r8,2), %r8d
	movslq	%r8d, %r8
	movl	%edx, (%rdi,%r8,4)
	imull	$3, (%rcx), %r8d
	addl	%esi, %r8d
	movslq	%r8d, %r8
	movl	(%rdi,%r8,4), %r9d
	movl	(%r11), %r8d
	leal	(%rdx,%r8,8), %r8d
	movslq	%r8d, %r8
	movl	%r9d, (%rax,%r8,4)
	imull	$3, (%rcx), %eax
	addl	%esi, %eax
	cltq
	movl	%edx, (%rdi,%rax,4)
.L14:
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%rbp
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r13
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2030:
	.size	_Z4linkPiS_iiiiS_, .-_Z4linkPiS_iiiiS_
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC1:
	.string	"/home/ubuntu/Datasets/stackv2/train-structured/greensprin/BK/master/sub.cu"
.LC2:
	.string	"%s %s %d %d\n"
.LC3:
	.string	"%s %d %s\n"
.LC4:
	.string	"%s %d %d %d\n"
	.text
	.globl	_Z4loadP8_IO_FILE
	.type	_Z4loadP8_IO_FILE, @function
_Z4loadP8_IO_FILE:
.LFB2031:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	xorl	%edx, %edx
	movl	$4, %esi
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	leaq	.LC1(%rip), %r12
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movq	%rdi, %rbp
	leaq	N_NUM(%rip), %rdi
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$56, %rsp
	.cfi_def_cfa_offset 112
	movq	%fs:40, %rax
	movq	%rax, 40(%rsp)
	xorl	%eax, %eax
	leaq	30(%rsp), %rbx
	leaq	20(%rsp), %r13
	call	cudaHostAlloc@PLT
	movl	$1, %ecx
	movl	$440, %edx
	movq	%r12, %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKcib
	xorl	%edx, %edx
	movl	$4, %esi
	leaq	E_NUM(%rip), %rdi
	call	cudaHostAlloc@PLT
	movl	$1, %ecx
	movl	$441, %edx
	movq	%r12, %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKcib
	xorl	%eax, %eax
	movq	%rbx, %rcx
	movq	%r13, %rdx
	movq	E_NUM(%rip), %r9
	movq	N_NUM(%rip), %r8
	leaq	.LC2(%rip), %rsi
	movq	%rbp, %rdi
	call	__isoc23_fscanf@PLT
	incl	%eax
	jne	.L23
.L29:
	orl	$-1, %r12d
	jmp	.L22
.L23:
	movq	N_NUM(%rip), %rax
	xorl	%edx, %edx
	leaq	n_table(%rip), %rdi
	movslq	(%rax), %rsi
	imulq	$28, %rsi, %rsi
	call	cudaHostAlloc@PLT
	movl	$1, %ecx
	movl	$444, %edx
	movq	%r12, %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKcib
	movq	E_NUM(%rip), %rax
	xorl	%edx, %edx
	leaq	e_table(%rip), %rdi
	movslq	(%rax), %rsi
	imulq	$56, %rsi, %rsi
	call	cudaHostAlloc@PLT
	movl	$1, %ecx
	movq	%r12, %rsi
	movl	$445, %edx
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKcib
	movq	N_NUM(%rip), %rcx
	movq	n_table(%rip), %rsi
	xorl	%eax, %eax
.L25:
	movl	(%rcx), %edx
	cmpl	%eax, %edx
	jle	.L45
	leal	(%rax,%rdx,2), %edx
	movslq	%edx, %rdx
	movl	$-1, (%rsi,%rdx,4)
	imull	$3, (%rcx), %edx
	addl	%eax, %edx
	movslq	%edx, %rdx
	movl	$-1, (%rsi,%rdx,4)
	movl	(%rcx), %edx
	leal	(%rax,%rdx,4), %edx
	incl	%eax
	movslq	%edx, %rdx
	movl	$-1, (%rsi,%rdx,4)
	jmp	.L25
.L45:
	movq	E_NUM(%rip), %rdx
	movq	e_table(%rip), %rcx
	xorl	%eax, %eax
.L27:
	movl	(%rdx), %esi
	leal	(%rsi,%rsi), %edi
	cmpl	%eax, %edi
	jle	.L46
	leal	(%rax,%rsi,4), %esi
	movslq	%esi, %rsi
	movl	$-1, (%rcx,%rsi,4)
	imull	$6, (%rdx), %esi
	addl	%eax, %esi
	movslq	%esi, %rsi
	movl	$-1, (%rcx,%rsi,4)
	imull	$10, (%rdx), %esi
	addl	%eax, %esi
	movslq	%esi, %rsi
	movl	$-1, (%rcx,%rsi,4)
	movl	(%rdx), %esi
	leal	(%rax,%rsi,8), %esi
	movslq	%esi, %rsi
	movl	$-1, (%rcx,%rsi,4)
	imull	$12, (%rdx), %esi
	addl	%eax, %esi
	incl	%eax
	movslq	%esi, %rsi
	movl	$-1, (%rcx,%rsi,4)
	jmp	.L27
.L46:
	leaq	4(%rsp), %r14
	xorl	%eax, %eax
	movq	%rbx, %r8
	movq	%r13, %rdx
	leaq	.LC3(%rip), %r12
	movq	%r14, %rcx
	movq	%rbp, %rdi
	movq	%r12, %rsi
	call	__isoc23_fscanf@PLT
	incl	%eax
	je	.L29
	xorl	%edx, %edx
	movl	$4, %esi
	leaq	source(%rip), %rdi
	call	cudaHostAlloc@PLT
	movl	4(%rsp), %edx
	movq	%rbx, %r8
	movq	%r14, %rcx
	movq	source(%rip), %rax
	movq	%r12, %rsi
	movq	%rbp, %rdi
	movl	%edx, (%rax)
	xorl	%eax, %eax
	movq	%r13, %rdx
	call	__isoc23_fscanf@PLT
	incl	%eax
	je	.L29
	xorl	%edx, %edx
	movl	$4, %esi
	xorl	%r14d, %r14d
	xorl	%r12d, %r12d
	leaq	sink(%rip), %rdi
	leaq	.LC4(%rip), %r15
	call	cudaHostAlloc@PLT
	movl	4(%rsp), %edx
	movl	$4, %edi
	movq	sink(%rip), %rax
	movl	%edx, (%rax)
	call	_Znam@PLT
	xorl	%edi, %edi
	movl	%edi, (%rax)
	movq	%rax, %rbx
.L30:
	movq	E_NUM(%rip), %rax
	cmpl	%r14d, (%rax)
	jle	.L32
	xorl	%eax, %eax
	leaq	8(%rsp), %rcx
	leaq	16(%rsp), %r9
	movq	%r13, %rdx
	leaq	12(%rsp), %r8
	movq	%r15, %rsi
	movq	%rbp, %rdi
	call	__isoc23_fscanf@PLT
	incl	%eax
	je	.L32
	movl	16(%rsp), %r8d
	movl	%r14d, %eax
	movq	e_table(%rip), %rsi
	movq	n_table(%rip), %rdi
	cmpl	%r8d, %r12d
	cmovl	%r8d, %r12d
	subl	(%rbx), %eax
	pushq	%rdx
	.cfi_def_cfa_offset 120
	incl	%r14d
	pushq	%rbx
	.cfi_def_cfa_offset 128
	movl	28(%rsp), %ecx
	leal	(%rax,%rax), %r9d
	movl	24(%rsp), %edx
	call	_Z4linkPiS_iiiiS_
	popq	%rcx
	.cfi_def_cfa_offset 120
	popq	%rsi
	.cfi_def_cfa_offset 112
	jmp	.L30
.L32:
	movq	%rbx, %rdi
	call	_ZdaPv@PLT
.L22:
	movq	40(%rsp), %rax
	subq	%fs:40, %rax
	je	.L34
	call	__stack_chk_fail@PLT
.L34:
	addq	$56, %rsp
	.cfi_def_cfa_offset 56
	movl	%r12d, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2031:
	.size	_Z4loadP8_IO_FILE, .-_Z4loadP8_IO_FILE
	.globl	_Z41__device_stub__Z11first_resetPiS_S_S_S_S_PiS_S_S_S_S_
	.type	_Z41__device_stub__Z11first_resetPiS_S_S_S_S_PiS_S_S_S_S_, @function
_Z41__device_stub__Z11first_resetPiS_S_S_S_S_PiS_S_S_S_S_:
.LFB2056:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	56(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	64(%rsp), %rcx
	movq	%r8, 8(%rsp)
	movq	%r9, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 152(%rsp)
	movq	%rsp, %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L47
	pushq	64(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z11first_resetPiS_S_S_S_S_(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 208
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L47:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L49
	call	__stack_chk_fail@PLT
.L49:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2056:
	.size	_Z41__device_stub__Z11first_resetPiS_S_S_S_S_PiS_S_S_S_S_, .-_Z41__device_stub__Z11first_resetPiS_S_S_S_S_PiS_S_S_S_S_
	.globl	_Z11first_resetPiS_S_S_S_S_
	.type	_Z11first_resetPiS_S_S_S_S_, @function
_Z11first_resetPiS_S_S_S_S_:
.LFB2057:
	.cfi_startproc
	endbr64
	jmp	_Z41__device_stub__Z11first_resetPiS_S_S_S_S_PiS_S_S_S_S_
	.cfi_endproc
.LFE2057:
	.size	_Z11first_resetPiS_S_S_S_S_, .-_Z11first_resetPiS_S_S_S_S_
	.globl	_Z42__device_stub__Z10node_resetPiS_S_S_S_S_S_PiS_S_S_S_S_S_
	.type	_Z42__device_stub__Z10node_resetPiS_S_S_S_S_S_PiS_S_S_S_S_S_, @function
_Z42__device_stub__Z10node_resetPiS_S_S_S_S_S_PiS_S_S_S_S_S_:
.LFB2058:
	.cfi_startproc
	endbr64
	subq	$200, %rsp
	.cfi_def_cfa_offset 208
	movq	208(%rsp), %rax
	movq	%rdi, 56(%rsp)
	leaq	80(%rsp), %rdi
	movq	%rsi, 48(%rsp)
	leaq	92(%rsp), %rsi
	movq	%rdx, 40(%rsp)
	leaq	64(%rsp), %rdx
	movq	%rcx, 32(%rsp)
	leaq	72(%rsp), %rcx
	movq	%r8, 24(%rsp)
	movq	%r9, 16(%rsp)
	movq	%rax, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 184(%rsp)
	xorl	%eax, %eax
	leaq	56(%rsp), %rax
	movl	$1, 88(%rsp)
	movq	%rax, 128(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 176(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 80(%rsp)
	movq	%rax, 92(%rsp)
	movl	$1, 100(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L52
	pushq	72(%rsp)
	.cfi_def_cfa_offset 216
	leaq	_Z10node_resetPiS_S_S_S_S_S_(%rip), %rdi
	pushq	72(%rsp)
	.cfi_def_cfa_offset 224
	movq	108(%rsp), %rcx
	movl	116(%rsp), %r8d
	movq	96(%rsp), %rsi
	movl	104(%rsp), %edx
	leaq	144(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 216
	popq	%rdx
	.cfi_def_cfa_offset 208
.L52:
	movq	184(%rsp), %rax
	subq	%fs:40, %rax
	je	.L54
	call	__stack_chk_fail@PLT
.L54:
	addq	$200, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2058:
	.size	_Z42__device_stub__Z10node_resetPiS_S_S_S_S_S_PiS_S_S_S_S_S_, .-_Z42__device_stub__Z10node_resetPiS_S_S_S_S_S_PiS_S_S_S_S_S_
	.globl	_Z10node_resetPiS_S_S_S_S_S_
	.type	_Z10node_resetPiS_S_S_S_S_S_, @function
_Z10node_resetPiS_S_S_S_S_S_:
.LFB2059:
	.cfi_startproc
	endbr64
	jmp	_Z42__device_stub__Z10node_resetPiS_S_S_S_S_S_PiS_S_S_S_S_S_
	.cfi_endproc
.LFE2059:
	.size	_Z10node_resetPiS_S_S_S_S_S_, .-_Z10node_resetPiS_S_S_S_S_S_
	.globl	_Z41__device_stub__Z8trace_cuPiS_S_S_S_S_S_S_PiS_S_S_S_S_S_S_
	.type	_Z41__device_stub__Z8trace_cuPiS_S_S_S_S_S_S_PiS_S_S_S_S_S_S_, @function
_Z41__device_stub__Z8trace_cuPiS_S_S_S_S_S_S_PiS_S_S_S_S_S_S_:
.LFB2060:
	.cfi_startproc
	endbr64
	subq	$216, %rsp
	.cfi_def_cfa_offset 224
	movq	224(%rsp), %rax
	movq	%rdi, 56(%rsp)
	leaq	88(%rsp), %rdi
	movq	%rsi, 48(%rsp)
	leaq	100(%rsp), %rsi
	movq	%rax, 8(%rsp)
	movq	232(%rsp), %rax
	movq	%rdx, 40(%rsp)
	leaq	72(%rsp), %rdx
	movq	%rcx, 32(%rsp)
	leaq	80(%rsp), %rcx
	movq	%r8, 24(%rsp)
	movq	%r9, 16(%rsp)
	movq	%rax, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 200(%rsp)
	xorl	%eax, %eax
	leaq	56(%rsp), %rax
	movl	$1, 96(%rsp)
	movq	%rax, 136(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 184(%rsp)
	movq	%rsp, %rax
	movq	%rax, 192(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 88(%rsp)
	movq	%rax, 100(%rsp)
	movl	$1, 108(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L57
	pushq	80(%rsp)
	.cfi_def_cfa_offset 232
	leaq	_Z8trace_cuPiS_S_S_S_S_S_S_(%rip), %rdi
	pushq	80(%rsp)
	.cfi_def_cfa_offset 240
	movq	116(%rsp), %rcx
	movl	124(%rsp), %r8d
	movq	104(%rsp), %rsi
	movl	112(%rsp), %edx
	leaq	152(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 232
	popq	%rdx
	.cfi_def_cfa_offset 224
.L57:
	movq	200(%rsp), %rax
	subq	%fs:40, %rax
	je	.L59
	call	__stack_chk_fail@PLT
.L59:
	addq	$216, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2060:
	.size	_Z41__device_stub__Z8trace_cuPiS_S_S_S_S_S_S_PiS_S_S_S_S_S_S_, .-_Z41__device_stub__Z8trace_cuPiS_S_S_S_S_S_S_PiS_S_S_S_S_S_S_
	.globl	_Z8trace_cuPiS_S_S_S_S_S_S_
	.type	_Z8trace_cuPiS_S_S_S_S_S_S_, @function
_Z8trace_cuPiS_S_S_S_S_S_S_:
.LFB2061:
	.cfi_startproc
	endbr64
	jmp	_Z41__device_stub__Z8trace_cuPiS_S_S_S_S_S_S_PiS_S_S_S_S_S_S_
	.cfi_endproc
.LFE2061:
	.size	_Z8trace_cuPiS_S_S_S_S_S_S_, .-_Z8trace_cuPiS_S_S_S_S_S_S_
	.globl	_Z45__device_stub__Z6aug_cuPiS_S_S_S_S_S_S_S_S_S_PiS_S_S_S_S_S_S_S_S_S_
	.type	_Z45__device_stub__Z6aug_cuPiS_S_S_S_S_S_S_S_S_S_PiS_S_S_S_S_S_S_S_S_S_, @function
_Z45__device_stub__Z6aug_cuPiS_S_S_S_S_S_S_S_S_S_PiS_S_S_S_S_S_S_S_S_S_:
.LFB2062:
	.cfi_startproc
	endbr64
	subq	$264, %rsp
	.cfi_def_cfa_offset 272
	movq	272(%rsp), %rax
	movq	%rdi, 88(%rsp)
	leaq	112(%rsp), %rdi
	movq	%rsi, 80(%rsp)
	leaq	124(%rsp), %rsi
	movq	%rax, 40(%rsp)
	movq	280(%rsp), %rax
	movq	%rdx, 72(%rsp)
	leaq	96(%rsp), %rdx
	movq	%rax, 32(%rsp)
	movq	288(%rsp), %rax
	movq	%rcx, 64(%rsp)
	leaq	104(%rsp), %rcx
	movq	%rax, 24(%rsp)
	movq	296(%rsp), %rax
	movq	%r8, 56(%rsp)
	movq	%rax, 16(%rsp)
	movq	304(%rsp), %rax
	movq	%r9, 48(%rsp)
	movq	%rax, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 248(%rsp)
	xorl	%eax, %eax
	leaq	88(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	80(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	72(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	64(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	56(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 208(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 216(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 224(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 232(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 240(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 112(%rsp)
	movl	$1, 120(%rsp)
	movq	%rax, 124(%rsp)
	movl	$1, 132(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L62
	pushq	104(%rsp)
	.cfi_def_cfa_offset 280
	leaq	_Z6aug_cuPiS_S_S_S_S_S_S_S_S_S_(%rip), %rdi
	pushq	104(%rsp)
	.cfi_def_cfa_offset 288
	movq	140(%rsp), %rcx
	movl	148(%rsp), %r8d
	movq	128(%rsp), %rsi
	movl	136(%rsp), %edx
	leaq	176(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 280
	popq	%rdx
	.cfi_def_cfa_offset 272
.L62:
	movq	248(%rsp), %rax
	subq	%fs:40, %rax
	je	.L64
	call	__stack_chk_fail@PLT
.L64:
	addq	$264, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2062:
	.size	_Z45__device_stub__Z6aug_cuPiS_S_S_S_S_S_S_S_S_S_PiS_S_S_S_S_S_S_S_S_S_, .-_Z45__device_stub__Z6aug_cuPiS_S_S_S_S_S_S_S_S_S_PiS_S_S_S_S_S_S_S_S_S_
	.globl	_Z6aug_cuPiS_S_S_S_S_S_S_S_S_S_
	.type	_Z6aug_cuPiS_S_S_S_S_S_S_S_S_S_, @function
_Z6aug_cuPiS_S_S_S_S_S_S_S_S_S_:
.LFB2063:
	.cfi_startproc
	endbr64
	jmp	_Z45__device_stub__Z6aug_cuPiS_S_S_S_S_S_S_S_S_S_PiS_S_S_S_S_S_S_S_S_S_
	.cfi_endproc
.LFE2063:
	.size	_Z6aug_cuPiS_S_S_S_S_S_S_S_S_S_, .-_Z6aug_cuPiS_S_S_S_S_S_S_S_S_S_
	.globl	_Z28__device_stub__Z9flg_resetPiPi
	.type	_Z28__device_stub__Z9flg_resetPiPi, @function
_Z28__device_stub__Z9flg_resetPiPi:
.LFB2064:
	.cfi_startproc
	endbr64
	subq	$104, %rsp
	.cfi_def_cfa_offset 112
	movq	%rdi, 8(%rsp)
	leaq	24(%rsp), %rcx
	leaq	16(%rsp), %rdx
	leaq	44(%rsp), %rsi
	leaq	32(%rsp), %rdi
	movq	%fs:40, %rax
	movq	%rax, 88(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 40(%rsp)
	movq	%rax, 80(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 32(%rsp)
	movq	%rax, 44(%rsp)
	movl	$1, 52(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L67
	pushq	24(%rsp)
	.cfi_def_cfa_offset 120
	leaq	_Z9flg_resetPi(%rip), %rdi
	pushq	24(%rsp)
	.cfi_def_cfa_offset 128
	movq	60(%rsp), %rcx
	movl	68(%rsp), %r8d
	movq	48(%rsp), %rsi
	movl	56(%rsp), %edx
	leaq	96(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 120
	popq	%rdx
	.cfi_def_cfa_offset 112
.L67:
	movq	88(%rsp), %rax
	subq	%fs:40, %rax
	je	.L69
	call	__stack_chk_fail@PLT
.L69:
	addq	$104, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2064:
	.size	_Z28__device_stub__Z9flg_resetPiPi, .-_Z28__device_stub__Z9flg_resetPiPi
	.globl	_Z9flg_resetPi
	.type	_Z9flg_resetPi, @function
_Z9flg_resetPi:
.LFB2065:
	.cfi_startproc
	endbr64
	jmp	_Z28__device_stub__Z9flg_resetPiPi
	.cfi_endproc
.LFE2065:
	.size	_Z9flg_resetPi, .-_Z9flg_resetPi
	.section	.rodata.str1.1
.LC5:
	.string	"Usage: ./bk.exe file.inp\n"
.LC6:
	.string	"r"
.LC7:
	.string	"Can't open file [%s]\n"
.LC8:
	.string	"current_flow : %d\n"
.LC9:
	.string	"flow_sum : %d\n"
.LC11:
	.string	"time:%.2f[s]\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2029:
	.cfi_startproc
	endbr64
	pushq	%r14
	.cfi_def_cfa_offset 16
	.cfi_offset 14, -16
	pushq	%r13
	.cfi_def_cfa_offset 24
	.cfi_offset 13, -24
	pushq	%r12
	.cfi_def_cfa_offset 32
	.cfi_offset 12, -32
	pushq	%rbp
	.cfi_def_cfa_offset 40
	.cfi_offset 6, -40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	.cfi_offset 3, -48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	movq	%fs:40, %rax
	movq	%rax, 152(%rsp)
	xorl	%eax, %eax
	cmpl	$2, %edi
	je	.L73
	leaq	.LC5(%rip), %rsi
	movl	$2, %edi
	call	__printf_chk@PLT
	jmp	.L74
.L73:
	movq	8(%rsi), %rdi
	movq	%rsi, %rbp
	leaq	.LC6(%rip), %rsi
	call	fopen@PLT
	movq	%rax, %rbx
	testq	%rax, %rax
	jne	.L75
	movq	8(%rbp), %rdx
	leaq	.LC7(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
.L74:
	movl	$1, %eax
	jmp	.L72
.L75:
	movq	%rax, %rdi
	call	_Z4loadP8_IO_FILE
	movq	%rbx, %rdi
	movl	%eax, %ebp
	call	fclose@PLT
	incl	%ebp
	je	.L77
	xorl	%edx, %edx
	leaq	8(%rsp), %rdi
	movl	$4, %esi
	call	cudaHostAlloc@PLT
	movl	$1, %ecx
	movl	$292, %edx
	leaq	.LC1(%rip), %rbx
	movl	%eax, %edi
	movq	%rbx, %rsi
	call	_Z9gpuAssert9cudaErrorPKcib
	xorl	%edx, %edx
	leaq	16(%rsp), %rdi
	movl	$4, %esi
	call	cudaHostAlloc@PLT
	movl	$1, %ecx
	movl	$293, %edx
	movq	%rbx, %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKcib
	xorl	%edx, %edx
	leaq	24(%rsp), %rdi
	movl	$4, %esi
	call	cudaHostAlloc@PLT
	movl	$1, %ecx
	movl	$295, %edx
	movq	%rbx, %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKcib
	leaq	32(%rsp), %rdi
	movl	$4, %esi
	movq	N_NUM(%rip), %rax
	movslq	(%rax), %r12
	movq	E_NUM(%rip), %rax
	movslq	(%rax), %rbp
	imulq	$28, %r12, %r12
	call	cudaMalloc@PLT
	movl	$1, %ecx
	movl	$313, %edx
	movq	%rbx, %rsi
	movl	%eax, %edi
	imulq	$56, %rbp, %rbp
	call	_Z9gpuAssert9cudaErrorPKcib
	leaq	40(%rsp), %rdi
	movl	$4, %esi
	call	cudaMalloc@PLT
	movl	$1, %ecx
	movl	$314, %edx
	movq	%rbx, %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKcib
	leaq	64(%rsp), %rdi
	movl	$4, %esi
	call	cudaMalloc@PLT
	movl	$1, %ecx
	movl	$315, %edx
	movq	%rbx, %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKcib
	leaq	72(%rsp), %rdi
	movl	$4, %esi
	call	cudaMalloc@PLT
	movl	$1, %ecx
	movl	$316, %edx
	movq	%rbx, %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKcib
	movq	E_NUM(%rip), %rax
	leaq	80(%rsp), %rdi
	movslq	(%rax), %rsi
	salq	$2, %rsi
	call	cudaMalloc@PLT
	movl	$1, %ecx
	movl	$317, %edx
	movq	%rbx, %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKcib
	movq	%r12, %rsi
	leaq	48(%rsp), %rdi
	call	cudaMalloc@PLT
	movl	$1, %ecx
	movl	$318, %edx
	movq	%rbx, %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKcib
	leaq	56(%rsp), %rdi
	movq	%rbp, %rsi
	call	cudaMalloc@PLT
	movl	$1, %ecx
	movl	$319, %edx
	movq	%rbx, %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKcib
	leaq	88(%rsp), %rdi
	movl	$4, %esi
	call	cudaMalloc@PLT
	movl	$1, %ecx
	movl	$320, %edx
	movq	%rbx, %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKcib
	leaq	96(%rsp), %rdi
	movl	$4, %esi
	call	cudaMalloc@PLT
	movl	$1, %ecx
	movl	$321, %edx
	movq	%rbx, %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKcib
	leaq	104(%rsp), %rdi
	movl	$4, %esi
	call	cudaMalloc@PLT
	movl	$1, %ecx
	movl	$322, %edx
	movq	%rbx, %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKcib
	movq	E_NUM(%rip), %rax
	leaq	112(%rsp), %rdi
	movslq	(%rax), %rsi
	salq	$3, %rsi
	call	cudaMalloc@PLT
	movl	$1, %ecx
	movl	$323, %edx
	movq	%rbx, %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKcib
	leaq	120(%rsp), %rdi
	movl	$4, %esi
	call	cudaMalloc@PLT
	movl	$1, %ecx
	movl	$324, %edx
	movq	%rbx, %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKcib
	movq	n_table(%rip), %rsi
	movq	48(%rsp), %rdi
	movq	%r12, %rdx
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	movl	$1, %ecx
	movl	$327, %edx
	movq	%rbx, %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKcib
	movq	e_table(%rip), %rsi
	movq	56(%rsp), %rdi
	movq	%rbp, %rdx
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	movl	$1, %ecx
	movl	$328, %edx
	movq	%rbx, %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKcib
	movq	88(%rsp), %rdi
	movl	$1, %ecx
	movq	source(%rip), %rsi
	movl	$4, %edx
	call	cudaMemcpy@PLT
	movl	$1, %ecx
	movl	$329, %edx
	movq	%rbx, %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKcib
	movq	96(%rsp), %rdi
	movl	$1, %ecx
	movq	sink(%rip), %rsi
	movl	$4, %edx
	call	cudaMemcpy@PLT
	movl	$1, %ecx
	movl	$330, %edx
	movq	%rbx, %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKcib
	movq	32(%rsp), %rdi
	movl	$1, %ecx
	movq	N_NUM(%rip), %rsi
	movl	$4, %edx
	call	cudaMemcpy@PLT
	movl	$1, %ecx
	movl	$331, %edx
	movq	%rbx, %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKcib
	movq	40(%rsp), %rdi
	movl	$1, %ecx
	movq	E_NUM(%rip), %rsi
	movl	$4, %edx
	call	cudaMemcpy@PLT
	movl	$1, %ecx
	movl	$332, %edx
	movq	%rbx, %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKcib
	call	clock@PLT
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$1, %ecx
	movabsq	$4294967297, %rdi
	movl	$1, %esi
	movl	$1, 148(%rsp)
	movq	%rax, %r12
	movq	%rdi, %rdx
	movq	%rdi, 140(%rsp)
	movq	%rdi, 128(%rsp)
	movl	$1, 136(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L78
	movq	104(%rsp), %rdi
	call	_Z28__device_stub__Z9flg_resetPiPi
.L78:
	movl	$32, %esi
	movl	$134217729, %ecx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	N_NUM(%rip), %rax
	salq	$5, %rcx
	movl	$1, 148(%rsp)
	movq	%rcx, 140(%rsp)
	movl	(%rax), %eax
	cltd
	idivl	%esi
	movq	%rcx, %rdx
	movl	$1, %ecx
	incl	%eax
	movl	%eax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 132(%rsp)
	movq	128(%rsp), %rdi
	movl	136(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L79
	movq	40(%rsp), %r9
	movq	32(%rsp), %r8
	movq	96(%rsp), %rcx
	movq	88(%rsp), %rdx
	movq	56(%rsp), %rsi
	movq	48(%rsp), %rdi
	call	_Z41__device_stub__Z11first_resetPiS_S_S_S_S_PiS_S_S_S_S_
.L79:
	movabsq	$4294967297, %rbp
.L87:
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	%rbp, %rdx
	movl	$1, %ecx
	movq	%rbp, %rdi
	movl	$1, %esi
	movq	%rbp, 140(%rsp)
	movl	$1, 148(%rsp)
	movq	%rbp, 128(%rsp)
	movl	$1, 136(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L80
	movq	72(%rsp), %rdi
	call	_Z28__device_stub__Z9flg_resetPiPi
.L80:
	movl	$32, %esi
	movl	$134217729, %ecx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	N_NUM(%rip), %rax
	salq	$5, %rcx
	movq	%rbp, 132(%rsp)
	movq	%rcx, 140(%rsp)
	movl	$1, 148(%rsp)
	movl	(%rax), %eax
	cltd
	idivl	%esi
	movl	136(%rsp), %esi
	movq	%rcx, %rdx
	movl	$1, %ecx
	incl	%eax
	movl	%eax, 128(%rsp)
	movq	128(%rsp), %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L81
	pushq	%rsi
	.cfi_def_cfa_offset 216
	pushq	120(%rsp)
	.cfi_def_cfa_offset 224
	movq	56(%rsp), %r9
	movq	48(%rsp), %r8
	movq	112(%rsp), %rcx
	movq	104(%rsp), %rdx
	movq	72(%rsp), %rsi
	movq	64(%rsp), %rdi
	call	_Z42__device_stub__Z10node_resetPiS_S_S_S_S_S_PiS_S_S_S_S_S_
	popq	%rdi
	.cfi_def_cfa_offset 216
	popq	%r8
	.cfi_def_cfa_offset 208
.L81:
	call	cudaThreadSynchronize@PLT
	movl	$1, %ecx
	movq	%rbx, %rsi
	movl	$342, %edx
	movabsq	$4294967352, %r13
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKcib
.L83:
	movq	N_NUM(%rip), %rax
	movl	$56, %ecx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	%rbp, 132(%rsp)
	movl	136(%rsp), %esi
	movl	(%rax), %eax
	movq	%r13, 140(%rsp)
	movl	$1, 148(%rsp)
	cltd
	idivl	%ecx
	movq	%r13, %rdx
	movl	$1, %ecx
	incl	%eax
	movl	%eax, 128(%rsp)
	movq	128(%rsp), %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L82
	pushq	112(%rsp)
	.cfi_def_cfa_offset 216
	pushq	72(%rsp)
	.cfi_def_cfa_offset 224
	movq	56(%rsp), %r9
	movq	48(%rsp), %r8
	movq	96(%rsp), %rcx
	movq	88(%rsp), %rdx
	movq	72(%rsp), %rsi
	movq	64(%rsp), %rdi
	call	_Z41__device_stub__Z8trace_cuPiS_S_S_S_S_S_S_PiS_S_S_S_S_S_S_
	popq	%rdx
	.cfi_def_cfa_offset 216
	popq	%rcx
	.cfi_def_cfa_offset 208
.L82:
	call	cudaThreadSynchronize@PLT
	movl	$1, %ecx
	movl	$346, %edx
	movq	%rbx, %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKcib
	movq	64(%rsp), %rsi
	movq	8(%rsp), %rdi
	movl	$2, %ecx
	movl	$4, %edx
	call	cudaMemcpy@PLT
	movl	$1, %ecx
	movl	$347, %edx
	movq	%rbx, %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKcib
	movq	8(%rsp), %rax
	cmpl	$0, (%rax)
	jne	.L83
	movq	72(%rsp), %rsi
	movq	16(%rsp), %rdi
	movl	$2, %ecx
	movl	$4, %edx
	call	cudaMemcpy@PLT
	movl	$1, %ecx
	movl	$352, %edx
	movq	%rbx, %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKcib
	movq	16(%rsp), %rax
	cmpl	$0, (%rax)
	je	.L84
	movabsq	$4294967328, %r14
	movl	$3, %r13d
.L86:
	movq	E_NUM(%rip), %rax
	movq	112(%rsp), %rdi
	xorl	%esi, %esi
	movslq	(%rax), %rdx
	salq	$3, %rdx
	call	cudaMemset@PLT
	movl	$1, %ecx
	movl	$357, %edx
	movq	%rbx, %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKcib
	movq	16(%rsp), %rax
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$32, %ecx
	movq	%rbp, 132(%rsp)
	movl	136(%rsp), %esi
	movl	(%rax), %eax
	movq	%r14, 140(%rsp)
	movl	$1, 148(%rsp)
	cltd
	idivl	%ecx
	movq	%r14, %rdx
	movl	$1, %ecx
	incl	%eax
	movl	%eax, 128(%rsp)
	movq	128(%rsp), %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L85
	pushq	%rax
	.cfi_def_cfa_offset 216
	pushq	72(%rsp)
	.cfi_def_cfa_offset 224
	pushq	56(%rsp)
	.cfi_def_cfa_offset 232
	pushq	56(%rsp)
	.cfi_def_cfa_offset 240
	pushq	136(%rsp)
	.cfi_def_cfa_offset 248
	pushq	152(%rsp)
	.cfi_def_cfa_offset 256
	movq	144(%rsp), %r9
	movq	136(%rsp), %r8
	movq	128(%rsp), %rcx
	movq	120(%rsp), %rdx
	movq	104(%rsp), %rsi
	movq	96(%rsp), %rdi
	call	_Z45__device_stub__Z6aug_cuPiS_S_S_S_S_S_S_S_S_S_PiS_S_S_S_S_S_S_S_S_S_
	addq	$48, %rsp
	.cfi_def_cfa_offset 208
.L85:
	call	cudaThreadSynchronize@PLT
	movl	$1, %ecx
	movl	$359, %edx
	movq	%rbx, %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKcib
	decl	%r13d
	jne	.L86
	movq	64(%rsp), %rsi
	movq	8(%rsp), %rdi
	movl	$2, %ecx
	movl	$4, %edx
	call	cudaMemcpy@PLT
	movq	%rbx, %rsi
	movl	$1, %ecx
	movl	$362, %edx
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKcib
	movq	104(%rsp), %rsi
	movq	24(%rsp), %rdi
	movl	$2, %ecx
	movl	$4, %edx
	call	cudaMemcpy@PLT
	movq	%rbx, %rsi
	movl	$1, %ecx
	movl	$364, %edx
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKcib
	movq	24(%rsp), %rax
	movl	$2, %edi
	leaq	.LC8(%rip), %rsi
	movl	(%rax), %edx
	xorl	%eax, %eax
	call	__printf_chk@PLT
	jmp	.L87
.L84:
	movq	24(%rsp), %rax
	leaq	.LC9(%rip), %rsi
	movl	$2, %edi
	movl	(%rax), %edx
	xorl	%eax, %eax
	call	__printf_chk@PLT
	call	clock@PLT
	leaq	.LC11(%rip), %rsi
	movl	$2, %edi
	subq	%r12, %rax
	cvtsi2sdq	%rax, %xmm0
	movb	$1, %al
	divsd	.LC10(%rip), %xmm0
	call	__printf_chk@PLT
	movq	32(%rsp), %rdi
	call	cudaFree@PLT
	movq	40(%rsp), %rdi
	call	cudaFree@PLT
	movq	48(%rsp), %rdi
	call	cudaFree@PLT
	movq	56(%rsp), %rdi
	call	cudaFree@PLT
	movq	64(%rsp), %rdi
	call	cudaFree@PLT
	movq	72(%rsp), %rdi
	call	cudaFree@PLT
	movq	80(%rsp), %rdi
	call	cudaFree@PLT
	movq	88(%rsp), %rdi
	call	cudaFree@PLT
	movq	96(%rsp), %rdi
	call	cudaFree@PLT
	movq	104(%rsp), %rdi
	call	cudaFree@PLT
	movq	120(%rsp), %rdi
	call	cudaFree@PLT
	movq	112(%rsp), %rdi
	call	cudaFree@PLT
	movq	8(%rsp), %rdi
	call	cudaFreeHost@PLT
	movq	16(%rsp), %rdi
	call	cudaFreeHost@PLT
	movq	n_table(%rip), %rdi
	call	cudaFreeHost@PLT
	movq	e_table(%rip), %rdi
	call	cudaFreeHost@PLT
	movq	source(%rip), %rdi
	call	cudaFreeHost@PLT
	movq	sink(%rip), %rdi
	call	cudaFreeHost@PLT
	movq	24(%rsp), %rdi
	call	cudaFreeHost@PLT
	movq	N_NUM(%rip), %rdi
	call	cudaFreeHost@PLT
	movq	E_NUM(%rip), %rdi
	call	cudaFreeHost@PLT
.L77:
	xorl	%eax, %eax
.L72:
	movq	152(%rsp), %rdx
	subq	%fs:40, %rdx
	je	.L88
	call	__stack_chk_fail@PLT
.L88:
	addq	$160, %rsp
	.cfi_def_cfa_offset 48
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%rbp
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r13
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2029:
	.size	main, .-main
	.section	.rodata.str1.1
.LC12:
	.string	"_Z9flg_resetPi"
.LC13:
	.string	"_Z6aug_cuPiS_S_S_S_S_S_S_S_S_S_"
.LC14:
	.string	"_Z8trace_cuPiS_S_S_S_S_S_S_"
.LC15:
	.string	"_Z10node_resetPiS_S_S_S_S_S_"
.LC16:
	.string	"_Z11first_resetPiS_S_S_S_S_"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2067:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC12(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z9flg_resetPi(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC13(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z6aug_cuPiS_S_S_S_S_S_S_S_S_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC14(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z8trace_cuPiS_S_S_S_S_S_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC15(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z10node_resetPiS_S_S_S_S_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC16(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z11first_resetPiS_S_S_S_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2067:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.globl	sink
	.bss
	.align 8
	.type	sink, @object
	.size	sink, 8
sink:
	.zero	8
	.globl	source
	.align 8
	.type	source, @object
	.size	source, 8
source:
	.zero	8
	.globl	e_table
	.align 8
	.type	e_table, @object
	.size	e_table, 8
e_table:
	.zero	8
	.globl	n_table
	.align 8
	.type	n_table, @object
	.size	n_table, 8
n_table:
	.zero	8
	.globl	E_NUM
	.align 8
	.type	E_NUM, @object
	.size	E_NUM, 8
E_NUM:
	.zero	8
	.globl	N_NUM
	.align 8
	.type	N_NUM, @object
	.size	N_NUM, 8
N_NUM:
	.zero	8
	.section	.rodata.cst8,"aM",@progbits,8
	.align 8
.LC10:
	.long	0
	.long	1093567616
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>

/*
配列の形

node 0:state
     1:height
     2:out_root_id
     3:in_root_id
     4:source,sinkにつながっているかのflg

edge 0:flow
     1:reverse_id
     2:in_node_id
     3:out_node_id
     4:in_link_id
     5:out_link_id
     6:id
*/

#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(hipError_t code, const char *file, int line, bool abort=true)
{
  if (code != hipSuccess) {
    fprintf(stderr,"GPUassert: %s %s %d\n", hipGetErrorString(code), file, line);
    if (abort) exit(code);
  }
}
  
#define NODE 7
#define EDGE 7

#define NADR(NUM, ID, EL) (NUM * EL + ID)
#define EADR(NUM, ID, EL) ((NUM * 2) * EL + ID)

//node
#define STATE 0
#define HEIGHT 1
#define OUT_ROOT 2
#define IN_ROOT 3
#define ST_FLG 4
#define ACTIVE 5
#define N_ROUTE 6

//edge
#define FLOW 0
#define ROUTE 1
#define REVERSE 2
#define IN_NODE 3
#define IN_LINK 4
#define OUT_NODE 5
#define OUT_LINK 6

int *N_NUM;
int *E_NUM;
int *n_table;
int *e_table;
int *source;
int *sink;

void link(int e_table, int from, int to, int r_edge, int flow);
int load(FILE *fp);

__global__ void first_reset(int *n_table, int *e_table, int *source, int *sink, int *N_NUM, int *E_NUM) {
  int total_id = blockDim.x * blockIdx.x + threadIdx.x;
  if (total_id >= N_NUM[0]) return;
  if (total_id == source[0]) {
    n_table[NADR(N_NUM[0], total_id, STATE)] = 1;
    n_table[NADR(N_NUM[0], total_id, HEIGHT)] = 0;
    n_table[NADR(N_NUM[0], total_id, ACTIVE)] = 0;
    n_table[NADR(N_NUM[0], total_id, N_ROUTE)] = 0;
    return;
  }
  else if (total_id == sink[0]) {
    n_table[NADR(N_NUM[0], total_id, STATE)] = 2;
    n_table[NADR(N_NUM[0], total_id, HEIGHT)] = 0;
    n_table[NADR(N_NUM[0], total_id, ACTIVE)] = 0;
    n_table[NADR(N_NUM[0], total_id, N_ROUTE)] = 0;
    return;
  }
  else if (n_table[NADR(N_NUM[0], total_id, ST_FLG)] != -1) {
    int f_flg = n_table[NADR(N_NUM[0], total_id, ST_FLG)];
    int in_node = e_table[EADR(E_NUM[0], f_flg, IN_NODE)];
    n_table[NADR(N_NUM[0], total_id, HEIGHT)] = 1;
    n_table[NADR(N_NUM[0], total_id, ACTIVE)] = 1;
    n_table[NADR(N_NUM[0], total_id, N_ROUTE)] = 1;
    if (in_node == source[0]) n_table[NADR(N_NUM[0], total_id, STATE)] = 1;
    else n_table[NADR(N_NUM[0], total_id, STATE)] = 2;
  }
}

__global__ void node_reset(int *n_table, int *e_table, int *source, int *sink, int *N_NUM, int *E_NUM, int *e_flg) {
  int total_id = blockDim.x * blockIdx.x + threadIdx.x;
  if (total_id >= N_NUM[0]) return;
  if (total_id == source[0] || total_id == sink[0]) return;
  if (n_table[NADR(N_NUM[0], total_id, ST_FLG)] == -1) {
    n_table[NADR(N_NUM[0], total_id, HEIGHT)] = N_NUM[0];
    n_table[NADR(N_NUM[0], total_id, STATE)] = 0;
    n_table[NADR(N_NUM[0], total_id, ACTIVE)] = 0;
    n_table[NADR(N_NUM[0], total_id, N_ROUTE)] = 0;
    return;
  }
  else {
    n_table[NADR(N_NUM[0], total_id, ACTIVE)] = 1;
    int f_flg = n_table[NADR(N_NUM[0], total_id, ST_FLG)];
    if (e_table[EADR(E_NUM[0], f_flg, FLOW)] == 0) {
      n_table[NADR(N_NUM[0], total_id, HEIGHT)] = N_NUM[0];
      n_table[NADR(N_NUM[0], total_id, STATE)] = 0;
      n_table[NADR(N_NUM[0], total_id, ACTIVE)] = 0;
      n_table[NADR(N_NUM[0], total_id, N_ROUTE)] = 0;
      n_table[NADR(N_NUM[0], total_id, ST_FLG)] = -1;
    }
  }
}

__global__ void trace_cu(int *n_table, int *e_table, int *flg3, int *que3, int *N_NUM, int *E_NUM, int *flg1, int *e_flg) {
  flg1[0] = 0;
  int node_id = blockDim.x * blockIdx.x + threadIdx.x;
  if (node_id >= N_NUM[0]) return;

  __shared__ int n_num[1];
  n_num[0] = N_NUM[0];
  __shared__ int e_num[1];
  e_num[0] = E_NUM[0];

  if (n_table[NADR(n_num[0], node_id, ACTIVE)] != 1) return;
  int state, look_n, root, link;
  if (n_table[NADR(n_num[0], node_id, STATE)] == 1) {
    state = 1;
    look_n = OUT_NODE;
    root = OUT_ROOT;
    link = OUT_LINK;
  }
  else {
    state = 2;
    look_n = IN_NODE;
    root = IN_ROOT;
    link = IN_LINK;
  }
  int old;
  int lok_node;
  int edge_id = n_table[NADR(n_num[0], node_id, root)];
  for (;;) {
    for (;;) {
      if (edge_id == -1) {
	n_table[NADR(n_num[0], node_id, ACTIVE)] = 0;
	return;
      }
      if (e_table[EADR(e_num[0], edge_id, FLOW)] > 0) break;
      edge_id = e_table[EADR(e_num[0], edge_id, link)];
    }
    lok_node = e_table[EADR(e_num[0], edge_id, look_n)];
    if (n_table[NADR(n_num[0], lok_node, STATE)] == 0) {
      //old = atomicExch(&e_flg[lok_node], 1);
      old = atomicAdd(&n_table[NADR(n_num[0], lok_node, N_ROUTE)], 1);
      if (old == 0) {
	n_table[NADR(n_num[0], lok_node, STATE)] = state;
	n_table[NADR(n_num[0], lok_node, HEIGHT)] = n_table[NADR(n_num[0], node_id, HEIGHT)] + 1;
	n_table[NADR(n_num[0], lok_node, ACTIVE)] = 1;
	flg1[0] = 1;
      }
    }
    else if (n_table[NADR(n_num[0], lok_node, STATE)] != state) {
      old = atomicAdd(&(flg3[0]), 1);
      que3[old] = edge_id;
    }
    edge_id = e_table[EADR(e_num[0], edge_id, link)];
  }
}

__device__ void flow_t(int *n_table, int *e_table, int flow, int pre_edge, int edge, int N_NUM, int E_NUM, int tag, int *flg1) {
  int link = IN_NODE;

  int old = atomicSub(&e_table[EADR(E_NUM, edge, FLOW)], flow);
  int reverse = e_table[EADR(E_NUM, edge, REVERSE)];
  atomicAdd(&e_table[EADR(E_NUM, reverse, FLOW)], flow);
  int l_node = e_table[EADR(E_NUM, edge, link)];
  if (old == flow) {
    old = atomicSub(&n_table[NADR(N_NUM, l_node, N_ROUTE)], 1);
    if (old == 1) atomicAdd(&flg1[0], 1);
  }

  for (;;) {
    old = atomicSub(&e_table[EADR(E_NUM, pre_edge, FLOW)], flow);
    reverse = e_table[EADR(E_NUM, pre_edge, REVERSE)];
    atomicAdd(&e_table[EADR(E_NUM, reverse, FLOW)], flow);
    if (pre_edge == tag) {
      if (old == flow) atomicAdd(&flg1[0], 1);
      break;
    }
    l_node = e_table[EADR(E_NUM, edge, link)];
    if (l_node == e_table[EADR(E_NUM, tag, link)]) link = OUT_NODE;
    if (old == flow) {
      old = atomicSub(&n_table[NADR(N_NUM, l_node, N_ROUTE)], 1);
      if (old == 1) atomicAdd(&flg1[0], 1);
    }
    pre_edge = e_table[EADR(E_NUM, pre_edge, ROUTE)];
  }
}

__global__ void aug_cu(int *n_table, int *e_table, int *flg3, int *que3, int *source, int *sink, int *e_flg, int *flow_sum, int *N_NUM, int *E_NUM, int *flg1) {
  int total_id = blockDim.x * blockIdx.x + threadIdx.x;
  if (total_id >= flg3[0]) return;
  int tag = que3[total_id];
  int old = atomicExch(&e_flg[tag], 1);
  if (old != 0) return;
  int pre_edge = tag;

  __shared__ int n_num[1];
  n_num[0] = N_NUM[0];
  __shared__ int e_num[1];

  e_num[0] = E_NUM[0];
  int flow = e_table[EADR(e_num[0], tag, FLOW)];
  if (flow == 0) return;
  int node = e_table[EADR(e_num[0], tag, IN_NODE)];
  int state = 1;
  int height = n_table[NADR(N_NUM[0], node, HEIGHT)] - 1;

  int root = IN_ROOT;
  int look_n = IN_NODE;
  int link = IN_LINK;
  for (;;) {
    int edge_id = n_table[NADR(n_num[0], node, root)];
    int flow1;
    int lok_node;
    for (;;) {
      if (edge_id == -1) return;
      flow1 = e_table[EADR(e_num[0], edge_id, FLOW)];
      lok_node = e_table[EADR(e_num[0], edge_id, look_n)];
      if (flow1 > 0) {
	if (n_table[NADR(n_num[0], lok_node, HEIGHT)] == height) {
	  if (n_table[NADR(n_num[0], lok_node, STATE)] == state) {
	    old = atomicExch(&e_flg[edge_id], 1);
	    if (old == 0) {
	      flow = ((flow > flow1) ? flow1 : flow);
	      break;
	    }
	  }
	}
      }
      edge_id = e_table[EADR(e_num[0], edge_id, link)];
    }
    if (lok_node == sink[0]) {
      flow_t(n_table, e_table, flow, pre_edge, edge_id, n_num[0], e_num[0], tag, flg1);
      atomicAdd(&flow_sum[0], flow);
      return;
    }
    else if (lok_node == source[0]) {
      node = e_table[EADR(e_num[0], tag, OUT_NODE)];
      height = n_table[NADR(n_num[0], node, HEIGHT)] - 1;
      state = 2;

      root = OUT_ROOT;
      look_n = OUT_NODE;
      link = OUT_LINK;
    }
    else {
      node = lok_node;
      height--;
    }
    e_table[EADR(e_num[0], edge_id, ROUTE)] = pre_edge;
    pre_edge = edge_id;
  }
}

__global__ void flg_reset(int *flg) {
  flg[0] = 0;
}

int main(int argc, char **argv) {
  if (argc != 2) {
    printf("Usage: ./bk.exe file.inp\n");
    return 1;
  }
  FILE *fp = fopen(argv[1], "r");
  if (fp == NULL) {
    printf("Can't open file [%s]\n", argv[1]);
    return 1;
  }
  int max = load(fp);
  fclose(fp);

  if (max == -1) return 0;//ファイルの形式がおかしい時return

  clock_t start, end;//時間計測用

  //hostの変数確保
  int *flg1, *flg3;
  gpuErrchk ( hipHostMalloc(&flg1, sizeof(int), hipHostMallocDefault) );
  gpuErrchk ( hipHostMalloc(&flg3, sizeof(int), hipHostMallocDefault) );
  int *flow_sum;
  gpuErrchk ( hipHostMalloc(&flow_sum, sizeof(int), hipHostMallocDefault) );

  size_t C_SIZE = sizeof(int);
  size_t N_SIZE = sizeof(int) * N_NUM[0] * NODE;
  size_t E_SIZE = sizeof(int) * E_NUM[0] * EDGE * 2;

  //deviceの変数確保
  int *DN_NUM;
  int *DE_NUM;
  int *nd_table;
  int *ed_table;
  int *d_flg1, *d_flg3;
  int *d_que3;
  int *d_source, *d_sink;
  int *dflow_sum;
  int *de_flg;
  int *d_cnt;

  gpuErrchk( hipMalloc((void**)&DN_NUM, C_SIZE) );
  gpuErrchk( hipMalloc((void**)&DE_NUM, C_SIZE) );
  gpuErrchk( hipMalloc((void**)&d_flg1, C_SIZE) );
  gpuErrchk( hipMalloc((void**)&d_flg3, C_SIZE) );
  gpuErrchk( hipMalloc((void**)&d_que3, sizeof(int) * E_NUM[0]) );
  gpuErrchk( hipMalloc((void**)&nd_table, N_SIZE) );
  gpuErrchk( hipMalloc((void**)&ed_table, E_SIZE) );
  gpuErrchk( hipMalloc((void**)&d_source, C_SIZE) );
  gpuErrchk( hipMalloc((void**)&d_sink, C_SIZE) );
  gpuErrchk( hipMalloc((void**)&dflow_sum, C_SIZE) );
  gpuErrchk( hipMalloc((void**)&de_flg, sizeof(int) * E_NUM[0] * 2) );
  gpuErrchk (hipMalloc((void**)&d_cnt, sizeof(int)) );

  //deviceへのコピー
  gpuErrchk( hipMemcpy(nd_table, n_table, N_SIZE, hipMemcpyHostToDevice) );
  gpuErrchk( hipMemcpy(ed_table, e_table, E_SIZE, hipMemcpyHostToDevice) );
  gpuErrchk( hipMemcpy(d_source, source, C_SIZE, hipMemcpyHostToDevice) );
  gpuErrchk( hipMemcpy(d_sink, sink, C_SIZE, hipMemcpyHostToDevice) );
  gpuErrchk( hipMemcpy(DN_NUM, N_NUM, C_SIZE, hipMemcpyHostToDevice) );
  gpuErrchk( hipMemcpy(DE_NUM, E_NUM, C_SIZE, hipMemcpyHostToDevice) );

  //計測開始
  start = clock();

  flg_reset<<<1, 1>>>(dflow_sum);//flow_sumを初期化
  first_reset<<<(N_NUM[0] / 32) + 1, 32>>>(nd_table, ed_table, d_source, d_sink, DN_NUM, DE_NUM);
  for (;;) {
    flg_reset<<<1, 1>>>(d_flg3);
    node_reset<<<(N_NUM[0] / 32) + 1, 32>>>(nd_table, ed_table, d_source, d_sink, DN_NUM, DE_NUM, de_flg);
    gpuErrchk( hipDeviceSynchronize() );
    //growth stage
    for (;;) {
      trace_cu<<<(N_NUM[0] / 56) + 1, 56>>>(nd_table, ed_table, d_flg3, d_que3, DN_NUM, DE_NUM, d_flg1, de_flg);
      gpuErrchk( hipDeviceSynchronize() );
      gpuErrchk( hipMemcpy(flg1, d_flg1, C_SIZE, hipMemcpyDeviceToHost) );
      if (flg1[0] == 0) break;
    }

    //ぶつかったエッジがあったかを確認
    gpuErrchk( hipMemcpy(flg3, d_flg3, C_SIZE, hipMemcpyDeviceToHost) );
    if (flg3[0] == 0) break;

    //augmentation stage
    for (int i = 0; i < 3; i++) {
      gpuErrchk( hipMemset((void**)de_flg, 0, sizeof(int) * E_NUM[0] * 2) );
      aug_cu<<<(flg3[0] / 32) + 1, 32>>>(nd_table, ed_table, d_flg3, d_que3, d_source, d_sink, de_flg, dflow_sum, DN_NUM, DE_NUM, d_flg1);
      gpuErrchk( hipDeviceSynchronize() );
    }

    gpuErrchk( hipMemcpy(flg1, d_flg1, C_SIZE, hipMemcpyDeviceToHost) );

    gpuErrchk( hipMemcpy(flow_sum, dflow_sum, C_SIZE, hipMemcpyDeviceToHost) );
    printf("current_flow : %d\n", flow_sum[0]);
  }

  printf("flow_sum : %d\n", flow_sum[0]);
  end = clock();
  //計測終了
  printf("time:%.2f[s]\n", (double)(end - start) / CLOCKS_PER_SEC);

  hipFree(DN_NUM);
  hipFree(DE_NUM);
  hipFree(nd_table);
  hipFree(ed_table);
  hipFree(d_flg1);
  hipFree(d_flg3);
  hipFree(d_que3);
  hipFree(d_source);
  hipFree(d_sink);
  hipFree(dflow_sum);
  hipFree(d_cnt);
  hipFree(de_flg);

  hipHostFree(flg1);
  hipHostFree(flg3);
  hipHostFree(n_table);
  hipHostFree(e_table);
  hipHostFree(source);
  hipHostFree(sink);
  hipHostFree(flow_sum);
  hipHostFree(N_NUM);
  hipHostFree(E_NUM);

  return 0;
}

void link(int *n_table, int *e_table, int from, int to, int flow, int edge_id, int *count) {
  int edge = n_table[NADR(N_NUM[0], from, OUT_ROOT)];
  for (;;) {
    if (edge == -1) break;
    if (e_table[EADR(E_NUM[0], edge, OUT_NODE)] == to) {
      e_table[EADR(E_NUM[0], edge, FLOW)] += flow;
      count[0]++;
      return;
    }
    edge = e_table[EADR(E_NUM[0], edge, OUT_LINK)];
  }
  //正のエッジ
  e_table[EADR(E_NUM[0], edge_id, REVERSE)] = edge_id + 1;
  e_table[EADR(E_NUM[0], edge_id, FLOW)] = flow;
  e_table[EADR(E_NUM[0], edge_id, IN_NODE)] = from;
  e_table[EADR(E_NUM[0], edge_id, OUT_NODE)] = to;
  e_table[EADR(E_NUM[0], edge_id, OUT_LINK)] = n_table[NADR(N_NUM[0], from, OUT_ROOT)];
  n_table[NADR(N_NUM[0], from, OUT_ROOT)] = edge_id;
  e_table[EADR(E_NUM[0], edge_id, IN_LINK)] = n_table[NADR(N_NUM[0], to, IN_ROOT)];
  n_table[NADR(N_NUM[0], to, IN_ROOT)] = edge_id;
  if (from == source[0]) {
    n_table[NADR(N_NUM[0], to, ST_FLG)] = edge_id;
  }
  if (to == sink[0]) {
    n_table[NADR(N_NUM[0], from, ST_FLG)] = edge_id;
  }

  //逆(reverse)のエッジ
  e_table[EADR(E_NUM[0], (edge_id + 1), REVERSE)] = edge_id;
  e_table[EADR(E_NUM[0], (edge_id + 1), FLOW)] = 0;
  e_table[EADR(E_NUM[0], (edge_id + 1), IN_NODE)] = to;
  e_table[EADR(E_NUM[0], (edge_id + 1), OUT_NODE)] = from;
  e_table[EADR(E_NUM[0], (edge_id + 1), OUT_LINK)] = n_table[NADR(N_NUM[0], to, OUT_ROOT)];
  n_table[NADR(N_NUM[0], to, OUT_ROOT)] = edge_id + 1;
  e_table[EADR(E_NUM[0], (edge_id + 1), IN_LINK)] = n_table[NADR(N_NUM[0], from, IN_ROOT)];
  n_table[NADR(N_NUM[0], from, IN_ROOT)] = edge_id + 1;
}

int load(FILE *fp) {
  int max = 0;
  char s1[10], s2[10];
  gpuErrchk( hipHostMalloc(&N_NUM, sizeof(int), hipHostMallocDefault) );
  gpuErrchk( hipHostMalloc(&E_NUM, sizeof(int), hipHostMallocDefault) );
  int result = fscanf(fp, "%s %s %d %d\n", s1, s2, &N_NUM[0], &E_NUM[0]);
  if (result == EOF) return -1;
  gpuErrchk( hipHostMalloc(&n_table, sizeof(int) * N_NUM[0] * NODE, hipHostMallocDefault) );
  gpuErrchk( hipHostMalloc(&e_table, sizeof(int) * E_NUM[0] * EDGE * 2, hipHostMallocDefault) );

  for (int i = 0; i < N_NUM[0]; i++) {
    n_table[NADR(N_NUM[0], i, OUT_ROOT)] = -1;
    n_table[NADR(N_NUM[0], i, IN_ROOT)] = -1;
    n_table[NADR(N_NUM[0], i, ST_FLG)] = -1;
  }
  for (int i = 0; i < E_NUM[0] * 2; i++) {
    e_table[EADR(E_NUM[0], i, REVERSE)] = -1;
    e_table[EADR(E_NUM[0], i, IN_NODE)] = -1;
    e_table[EADR(E_NUM[0], i, OUT_NODE)] = -1;
    e_table[EADR(E_NUM[0], i, IN_LINK)] = -1;
    e_table[EADR(E_NUM[0], i, OUT_LINK)] = -1;
  }
  int t;
  result = fscanf(fp, "%s %d %s\n", s1, &t, s2);
  if (result == EOF) return -1;
  hipHostMalloc(&source, sizeof(int), hipHostMallocDefault);
  source[0] = t;
  result = fscanf(fp, "%s %d %s\n", s1, &t, s2);
  if (result == EOF) return -1;
  hipHostMalloc(&sink, sizeof(int), hipHostMallocDefault);
  sink[0] = t;

  int *count;
  count = new int[1]();
  for (int i = 0; i < E_NUM[0]; i++) {
    int from, to, flow;
    result = fscanf(fp, "%s %d %d %d\n", s1, &from, &to, &flow);
    if (result == EOF) break;
    if (flow > max) max = flow;
    link(n_table, e_table, from, to, flow, (i - count[0]) * 2, count);
  }
  delete[] count;

  return max;
}

	.text
	.file	"sub.hip"
	.globl	_Z26__device_stub__first_resetPiS_S_S_S_S_ # -- Begin function _Z26__device_stub__first_resetPiS_S_S_S_S_
	.type	_Z26__device_stub__first_resetPiS_S_S_S_S_,@function
_Z26__device_stub__first_resetPiS_S_S_S_S_: # @_Z26__device_stub__first_resetPiS_S_S_S_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z11first_resetPiS_S_S_S_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z26__device_stub__first_resetPiS_S_S_S_S_, .Lfunc_end0-_Z26__device_stub__first_resetPiS_S_S_S_S_
	.cfi_endproc
                                        # -- End function
	.globl	_Z25__device_stub__node_resetPiS_S_S_S_S_S_ # -- Begin function _Z25__device_stub__node_resetPiS_S_S_S_S_S_
	.type	_Z25__device_stub__node_resetPiS_S_S_S_S_S_,@function
_Z25__device_stub__node_resetPiS_S_S_S_S_S_: # @_Z25__device_stub__node_resetPiS_S_S_S_S_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z10node_resetPiS_S_S_S_S_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z25__device_stub__node_resetPiS_S_S_S_S_S_, .Lfunc_end1-_Z25__device_stub__node_resetPiS_S_S_S_S_S_
	.cfi_endproc
                                        # -- End function
	.globl	_Z23__device_stub__trace_cuPiS_S_S_S_S_S_S_ # -- Begin function _Z23__device_stub__trace_cuPiS_S_S_S_S_S_S_
	.type	_Z23__device_stub__trace_cuPiS_S_S_S_S_S_S_,@function
_Z23__device_stub__trace_cuPiS_S_S_S_S_S_S_: # @_Z23__device_stub__trace_cuPiS_S_S_S_S_S_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	216(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z8trace_cuPiS_S_S_S_S_S_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z23__device_stub__trace_cuPiS_S_S_S_S_S_S_, .Lfunc_end2-_Z23__device_stub__trace_cuPiS_S_S_S_S_S_S_
	.cfi_endproc
                                        # -- End function
	.globl	_Z21__device_stub__aug_cuPiS_S_S_S_S_S_S_S_S_S_ # -- Begin function _Z21__device_stub__aug_cuPiS_S_S_S_S_S_S_S_S_S_
	.type	_Z21__device_stub__aug_cuPiS_S_S_S_S_S_S_S_S_S_,@function
_Z21__device_stub__aug_cuPiS_S_S_S_S_S_S_S_S_S_: # @_Z21__device_stub__aug_cuPiS_S_S_S_S_S_S_S_S_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$192, %rsp
	.cfi_def_cfa_offset 240
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	240(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	248(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	256(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	264(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	272(%rsp), %rax
	movq	%rax, 80(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z6aug_cuPiS_S_S_S_S_S_S_S_S_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$208, %rsp
	.cfi_adjust_cfa_offset -208
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	_Z21__device_stub__aug_cuPiS_S_S_S_S_S_S_S_S_S_, .Lfunc_end3-_Z21__device_stub__aug_cuPiS_S_S_S_S_S_S_S_S_S_
	.cfi_endproc
                                        # -- End function
	.globl	_Z24__device_stub__flg_resetPi  # -- Begin function _Z24__device_stub__flg_resetPi
	.type	_Z24__device_stub__flg_resetPi,@function
_Z24__device_stub__flg_resetPi:         # @_Z24__device_stub__flg_resetPi
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$64, %rsp
	.cfi_def_cfa_offset 112
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	movq	%rsp, %rbx
	movq	%rax, (%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z9flg_resetPi, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$80, %rsp
	.cfi_adjust_cfa_offset -80
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end4:
	.size	_Z24__device_stub__flg_resetPi, .Lfunc_end4-_Z24__device_stub__flg_resetPi
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0                          # -- Begin function main
.LCPI5_0:
	.quad	0x412e848000000000              # double 1.0E+6
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$136, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	cmpl	$2, %edi
	jne	.LBB5_50
# %bb.1:
	movq	%rsi, %rbx
	movq	8(%rsi), %rdi
	movl	$.L.str.1, %esi
	callq	fopen
	testq	%rax, %rax
	je	.LBB5_53
# %bb.2:
	movq	%rax, %r14
	movq	%rax, %rdi
	callq	_Z4loadP8_IO_FILE
	movl	%eax, %ebx
	movq	%r14, %rdi
	callq	fclose
	cmpl	$-1, %ebx
	je	.LBB5_54
# %bb.3:
	leaq	104(%rsp), %rdi
	movl	$4, %esi
	xorl	%edx, %edx
	callq	hipHostMalloc
	testl	%eax, %eax
	jne	.LBB5_65
# %bb.4:                                # %_Z9gpuAssert10hipError_tPKcib.exit
	leaq	96(%rsp), %rdi
	movl	$4, %esi
	xorl	%edx, %edx
	callq	hipHostMalloc
	testl	%eax, %eax
	jne	.LBB5_66
# %bb.5:                                # %_Z9gpuAssert10hipError_tPKcib.exit60
	leaq	88(%rsp), %rdi
	movl	$4, %esi
	xorl	%edx, %edx
	callq	hipHostMalloc
	testl	%eax, %eax
	jne	.LBB5_67
# %bb.6:                                # %_Z9gpuAssert10hipError_tPKcib.exit62
	movq	N_NUM(%rip), %rax
	movslq	(%rax), %r15
	movq	E_NUM(%rip), %rax
	movslq	(%rax), %r14
	leaq	32(%rsp), %rdi
	movl	$4, %esi
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB5_68
# %bb.7:                                # %_Z9gpuAssert10hipError_tPKcib.exit64
	leaq	24(%rsp), %rdi
	movl	$4, %esi
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB5_69
# %bb.8:                                # %_Z9gpuAssert10hipError_tPKcib.exit66
	leaq	72(%rsp), %rdi
	movl	$4, %esi
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB5_70
# %bb.9:                                # %_Z9gpuAssert10hipError_tPKcib.exit68
	leaq	64(%rsp), %rdi
	movl	$4, %esi
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB5_71
# %bb.10:                               # %_Z9gpuAssert10hipError_tPKcib.exit70
	movq	E_NUM(%rip), %rax
	movslq	(%rax), %rsi
	shlq	$2, %rsi
	leaq	112(%rsp), %rdi
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB5_72
# %bb.11:                               # %_Z9gpuAssert10hipError_tPKcib.exit72
	leaq	(%r15,%r15,8), %rax
	leaq	(%rax,%rax,2), %rbx
	addq	%r15, %rbx
	leaq	16(%rsp), %rdi
	movq	%rbx, %rsi
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB5_73
# %bb.12:                               # %_Z9gpuAssert10hipError_tPKcib.exit74
	imulq	$56, %r14, %r14
	leaq	8(%rsp), %rdi
	movq	%r14, %rsi
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB5_74
# %bb.13:                               # %_Z9gpuAssert10hipError_tPKcib.exit76
	leaq	56(%rsp), %rdi
	movl	$4, %esi
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB5_75
# %bb.14:                               # %_Z9gpuAssert10hipError_tPKcib.exit78
	leaq	48(%rsp), %rdi
	movl	$4, %esi
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB5_76
# %bb.15:                               # %_Z9gpuAssert10hipError_tPKcib.exit80
	leaq	80(%rsp), %rdi
	movl	$4, %esi
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB5_77
# %bb.16:                               # %_Z9gpuAssert10hipError_tPKcib.exit82
	movq	E_NUM(%rip), %rax
	movslq	(%rax), %rsi
	shlq	$3, %rsi
	leaq	40(%rsp), %rdi
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB5_78
# %bb.17:                               # %_Z9gpuAssert10hipError_tPKcib.exit84
	leaq	128(%rsp), %rdi
	movl	$4, %esi
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB5_79
# %bb.18:                               # %_Z9gpuAssert10hipError_tPKcib.exit86
	movq	16(%rsp), %rdi
	movq	n_table(%rip), %rsi
	movq	%rbx, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	testl	%eax, %eax
	jne	.LBB5_80
# %bb.19:                               # %_Z9gpuAssert10hipError_tPKcib.exit88
	movq	8(%rsp), %rdi
	movq	e_table(%rip), %rsi
	movq	%r14, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	testl	%eax, %eax
	jne	.LBB5_81
# %bb.20:                               # %_Z9gpuAssert10hipError_tPKcib.exit90
	movq	56(%rsp), %rdi
	movq	source(%rip), %rsi
	movl	$4, %edx
	movl	$1, %ecx
	callq	hipMemcpy
	testl	%eax, %eax
	jne	.LBB5_82
# %bb.21:                               # %_Z9gpuAssert10hipError_tPKcib.exit92
	movq	48(%rsp), %rdi
	movq	sink(%rip), %rsi
	movl	$4, %edx
	movl	$1, %ecx
	callq	hipMemcpy
	testl	%eax, %eax
	jne	.LBB5_83
# %bb.22:                               # %_Z9gpuAssert10hipError_tPKcib.exit94
	movq	32(%rsp), %rdi
	movq	N_NUM(%rip), %rsi
	movl	$4, %edx
	movl	$1, %ecx
	callq	hipMemcpy
	testl	%eax, %eax
	jne	.LBB5_84
# %bb.23:                               # %_Z9gpuAssert10hipError_tPKcib.exit96
	movq	24(%rsp), %rdi
	movq	E_NUM(%rip), %rsi
	movl	$4, %edx
	movl	$1, %ecx
	callq	hipMemcpy
	testl	%eax, %eax
	jne	.LBB5_85
# %bb.24:                               # %_Z9gpuAssert10hipError_tPKcib.exit98
	movabsq	$4294967296, %r13               # imm = 0x100000000
	callq	clock
	movq	%rax, 120(%rsp)                 # 8-byte Spill
	leaq	1(%r13), %rdi
	movl	$1, %esi
	movq	%rdi, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB5_26
# %bb.25:
	movq	80(%rsp), %rdi
	callq	_Z24__device_stub__flg_resetPi
.LBB5_26:
	movq	N_NUM(%rip), %rax
	movl	(%rax), %eax
	leal	31(%rax), %edi
	testl	%eax, %eax
	cmovnsl	%eax, %edi
	sarl	$5, %edi
	incl	%edi
	orq	%r13, %rdi
	leaq	32(%r13), %r14
	movl	$1, %esi
	movq	%r14, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB5_28
# %bb.27:
	movq	16(%rsp), %rdi
	movq	8(%rsp), %rsi
	movq	56(%rsp), %rdx
	movq	48(%rsp), %rcx
	movq	32(%rsp), %r8
	movq	24(%rsp), %r9
	callq	_Z26__device_stub__first_resetPiS_S_S_S_S_
.LBB5_28:                               # %.preheader255
	leaq	1(%r13), %r15
	leaq	56(%r13), %r12
.LBB5_29:                               # =>This Loop Header: Depth=1
                                        #     Child Loop BB5_34 Depth 2
                                        #     Child Loop BB5_42 Depth 2
	movq	%r15, %rdi
	movl	$1, %esi
	movq	%r15, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB5_31
# %bb.30:                               #   in Loop: Header=BB5_29 Depth=1
	movq	64(%rsp), %rdi
	callq	_Z24__device_stub__flg_resetPi
.LBB5_31:                               #   in Loop: Header=BB5_29 Depth=1
	movq	N_NUM(%rip), %rax
	movl	(%rax), %eax
	leal	31(%rax), %edi
	testl	%eax, %eax
	cmovnsl	%eax, %edi
	sarl	$5, %edi
	incl	%edi
	orq	%r13, %rdi
	movl	$1, %esi
	movq	%r14, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB5_33
# %bb.32:                               #   in Loop: Header=BB5_29 Depth=1
	movq	16(%rsp), %rdi
	movq	8(%rsp), %rsi
	movq	56(%rsp), %rdx
	movq	48(%rsp), %rcx
	movq	32(%rsp), %r8
	movq	24(%rsp), %r9
	subq	$8, %rsp
	.cfi_adjust_cfa_offset 8
	pushq	48(%rsp)
	.cfi_adjust_cfa_offset 8
	callq	_Z25__device_stub__node_resetPiS_S_S_S_S_S_
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
.LBB5_33:                               #   in Loop: Header=BB5_29 Depth=1
	callq	hipDeviceSynchronize
	testl	%eax, %eax
	jne	.LBB5_61
.LBB5_34:                               # %_Z9gpuAssert10hipError_tPKcib.exit100
                                        #   Parent Loop BB5_29 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movq	N_NUM(%rip), %rax
	movslq	(%rax), %rax
	imulq	$-1840700269, %rax, %rcx        # imm = 0x92492493
	shrq	$32, %rcx
	addl	%eax, %ecx
	movl	%ecx, %eax
	sarl	$5, %eax
	shrl	$31, %ecx
	leal	(%rax,%rcx), %edi
	incl	%edi
	orq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB5_36
# %bb.35:                               #   in Loop: Header=BB5_34 Depth=2
	movq	16(%rsp), %rdi
	movq	8(%rsp), %rsi
	movq	64(%rsp), %rdx
	movq	112(%rsp), %rcx
	movq	32(%rsp), %r8
	movq	24(%rsp), %r9
	pushq	40(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	80(%rsp)
	.cfi_adjust_cfa_offset 8
	callq	_Z23__device_stub__trace_cuPiS_S_S_S_S_S_S_
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
.LBB5_36:                               #   in Loop: Header=BB5_34 Depth=2
	callq	hipDeviceSynchronize
	testl	%eax, %eax
	jne	.LBB5_57
# %bb.37:                               # %_Z9gpuAssert10hipError_tPKcib.exit102
                                        #   in Loop: Header=BB5_34 Depth=2
	movq	104(%rsp), %rdi
	movq	72(%rsp), %rsi
	movl	$4, %edx
	movl	$2, %ecx
	callq	hipMemcpy
	testl	%eax, %eax
	jne	.LBB5_56
# %bb.38:                               # %_Z9gpuAssert10hipError_tPKcib.exit104
                                        #   in Loop: Header=BB5_34 Depth=2
	movq	104(%rsp), %rax
	cmpl	$0, (%rax)
	jne	.LBB5_34
# %bb.39:                               #   in Loop: Header=BB5_29 Depth=1
	movq	96(%rsp), %rdi
	movq	64(%rsp), %rsi
	movl	$4, %edx
	movl	$2, %ecx
	callq	hipMemcpy
	testl	%eax, %eax
	jne	.LBB5_62
# %bb.40:                               # %_Z9gpuAssert10hipError_tPKcib.exit106
                                        #   in Loop: Header=BB5_29 Depth=1
	movq	96(%rsp), %rax
	cmpl	$0, (%rax)
	je	.LBB5_52
# %bb.41:                               # %.preheader.preheader
                                        #   in Loop: Header=BB5_29 Depth=1
	movl	$3, %ebx
.LBB5_42:                               # %.preheader
                                        #   Parent Loop BB5_29 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movq	40(%rsp), %rdi
	movq	E_NUM(%rip), %rax
	movslq	(%rax), %rdx
	shlq	$3, %rdx
	xorl	%esi, %esi
	callq	hipMemset
	testl	%eax, %eax
	jne	.LBB5_58
# %bb.43:                               # %_Z9gpuAssert10hipError_tPKcib.exit112
                                        #   in Loop: Header=BB5_42 Depth=2
	movq	96(%rsp), %rax
	movl	(%rax), %eax
	leal	31(%rax), %edi
	testl	%eax, %eax
	cmovnsl	%eax, %edi
	sarl	$5, %edi
	incl	%edi
	orq	%r13, %rdi
	movl	$1, %esi
	movq	%r14, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB5_45
# %bb.44:                               #   in Loop: Header=BB5_42 Depth=2
	movq	16(%rsp), %rdi
	movq	8(%rsp), %rsi
	movq	64(%rsp), %rdx
	movq	112(%rsp), %rcx
	movq	56(%rsp), %r8
	movq	48(%rsp), %r9
	subq	$8, %rsp
	.cfi_adjust_cfa_offset 8
	pushq	80(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	40(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	56(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	112(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	80(%rsp)
	.cfi_adjust_cfa_offset 8
	callq	_Z21__device_stub__aug_cuPiS_S_S_S_S_S_S_S_S_S_
	addq	$48, %rsp
	.cfi_adjust_cfa_offset -48
.LBB5_45:                               # %_Z9gpuAssert10hipError_tPKcib.exit114
                                        #   in Loop: Header=BB5_42 Depth=2
	callq	hipDeviceSynchronize
	testl	%eax, %eax
	jne	.LBB5_59
# %bb.46:                               #   in Loop: Header=BB5_42 Depth=2
	decl	%ebx
	jne	.LBB5_42
# %bb.47:                               #   in Loop: Header=BB5_29 Depth=1
	movq	104(%rsp), %rdi
	movq	72(%rsp), %rsi
	movl	$4, %edx
	movl	$2, %ecx
	callq	hipMemcpy
	testl	%eax, %eax
	jne	.LBB5_64
# %bb.48:                               # %_Z9gpuAssert10hipError_tPKcib.exit108
                                        #   in Loop: Header=BB5_29 Depth=1
	movq	88(%rsp), %rdi
	movq	80(%rsp), %rsi
	movl	$4, %edx
	movl	$2, %ecx
	callq	hipMemcpy
	testl	%eax, %eax
	jne	.LBB5_63
# %bb.49:                               # %_Z9gpuAssert10hipError_tPKcib.exit110
                                        #   in Loop: Header=BB5_29 Depth=1
	movq	88(%rsp), %rax
	movl	(%rax), %esi
	movl	$.L.str.4, %edi
	xorl	%eax, %eax
	callq	printf
	jmp	.LBB5_29
.LBB5_50:
	movl	$.Lstr, %edi
	callq	puts@PLT
	jmp	.LBB5_51
.LBB5_52:
	movq	88(%rsp), %rax
	movl	(%rax), %esi
	xorl	%ebp, %ebp
	movl	$.L.str.5, %edi
	xorl	%eax, %eax
	callq	printf
	callq	clock
	subq	120(%rsp), %rax                 # 8-byte Folded Reload
	cvtsi2sd	%rax, %xmm0
	divsd	.LCPI5_0(%rip), %xmm0
	movl	$.L.str.6, %edi
	movb	$1, %al
	callq	printf
	movq	32(%rsp), %rdi
	callq	hipFree
	movq	24(%rsp), %rdi
	callq	hipFree
	movq	16(%rsp), %rdi
	callq	hipFree
	movq	8(%rsp), %rdi
	callq	hipFree
	movq	72(%rsp), %rdi
	callq	hipFree
	movq	64(%rsp), %rdi
	callq	hipFree
	movq	112(%rsp), %rdi
	callq	hipFree
	movq	56(%rsp), %rdi
	callq	hipFree
	movq	48(%rsp), %rdi
	callq	hipFree
	movq	80(%rsp), %rdi
	callq	hipFree
	movq	128(%rsp), %rdi
	callq	hipFree
	movq	40(%rsp), %rdi
	callq	hipFree
	movq	104(%rsp), %rdi
	callq	hipHostFree
	movq	96(%rsp), %rdi
	callq	hipHostFree
	movq	n_table(%rip), %rdi
	callq	hipHostFree
	movq	e_table(%rip), %rdi
	callq	hipHostFree
	movq	source(%rip), %rdi
	callq	hipHostFree
	movq	sink(%rip), %rdi
	callq	hipHostFree
	movq	88(%rsp), %rdi
	callq	hipHostFree
	movq	N_NUM(%rip), %rdi
	callq	hipHostFree
	movq	E_NUM(%rip), %rdi
	callq	hipHostFree
	jmp	.LBB5_55
.LBB5_53:
	movq	8(%rbx), %rsi
	movl	$.L.str.2, %edi
	xorl	%eax, %eax
	callq	printf
.LBB5_51:
	movl	$1, %ebp
.LBB5_55:
	movl	%ebp, %eax
	addq	$136, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB5_54:
	.cfi_def_cfa_offset 192
	xorl	%ebp, %ebp
	jmp	.LBB5_55
.LBB5_56:
	movl	%eax, %ebp
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.10, %esi
	movl	$.L.str.3, %ecx
	movq	%rbx, %rdi
	movq	%rax, %rdx
	movl	$349, %r8d                      # imm = 0x15D
	jmp	.LBB5_60
.LBB5_57:
	movl	%eax, %ebp
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.10, %esi
	movl	$.L.str.3, %ecx
	movq	%rbx, %rdi
	movq	%rax, %rdx
	movl	$348, %r8d                      # imm = 0x15C
	jmp	.LBB5_60
.LBB5_58:
	movl	%eax, %ebp
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.10, %esi
	movl	$.L.str.3, %ecx
	movq	%rbx, %rdi
	movq	%rax, %rdx
	movl	$359, %r8d                      # imm = 0x167
	jmp	.LBB5_60
.LBB5_59:
	movl	%eax, %ebp
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.10, %esi
	movl	$.L.str.3, %ecx
	movq	%rbx, %rdi
	movq	%rax, %rdx
	movl	$361, %r8d                      # imm = 0x169
.LBB5_60:
	xorl	%eax, %eax
	callq	fprintf
	movl	%ebp, %edi
	callq	exit
.LBB5_61:
	movl	%eax, %ebp
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.10, %esi
	movl	$.L.str.3, %ecx
	movq	%rbx, %rdi
	movq	%rax, %rdx
	movl	$344, %r8d                      # imm = 0x158
	jmp	.LBB5_60
.LBB5_62:
	movl	%eax, %ebp
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.10, %esi
	movl	$.L.str.3, %ecx
	movq	%rbx, %rdi
	movq	%rax, %rdx
	movl	$354, %r8d                      # imm = 0x162
	jmp	.LBB5_60
.LBB5_63:
	movl	%eax, %ebp
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.10, %esi
	movl	$.L.str.3, %ecx
	movq	%rbx, %rdi
	movq	%rax, %rdx
	movl	$366, %r8d                      # imm = 0x16E
	jmp	.LBB5_60
.LBB5_64:
	movl	%eax, %ebp
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.10, %esi
	movl	$.L.str.3, %ecx
	movq	%rbx, %rdi
	movq	%rax, %rdx
	movl	$364, %r8d                      # imm = 0x16C
	jmp	.LBB5_60
.LBB5_65:
	movl	%eax, %ebx
	movq	stderr(%rip), %r14
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.10, %esi
	movl	$.L.str.3, %ecx
	movq	%r14, %rdi
	movq	%rax, %rdx
	movl	$294, %r8d                      # imm = 0x126
	jmp	.LBB5_86
.LBB5_66:
	movl	%eax, %ebx
	movq	stderr(%rip), %r14
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.10, %esi
	movl	$.L.str.3, %ecx
	movq	%r14, %rdi
	movq	%rax, %rdx
	movl	$295, %r8d                      # imm = 0x127
	jmp	.LBB5_86
.LBB5_67:
	movl	%eax, %ebx
	movq	stderr(%rip), %r14
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.10, %esi
	movl	$.L.str.3, %ecx
	movq	%r14, %rdi
	movq	%rax, %rdx
	movl	$297, %r8d                      # imm = 0x129
	jmp	.LBB5_86
.LBB5_68:
	movl	%eax, %ebx
	movq	stderr(%rip), %r14
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.10, %esi
	movl	$.L.str.3, %ecx
	movq	%r14, %rdi
	movq	%rax, %rdx
	movl	$315, %r8d                      # imm = 0x13B
	jmp	.LBB5_86
.LBB5_69:
	movl	%eax, %ebx
	movq	stderr(%rip), %r14
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.10, %esi
	movl	$.L.str.3, %ecx
	movq	%r14, %rdi
	movq	%rax, %rdx
	movl	$316, %r8d                      # imm = 0x13C
	jmp	.LBB5_86
.LBB5_70:
	movl	%eax, %ebx
	movq	stderr(%rip), %r14
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.10, %esi
	movl	$.L.str.3, %ecx
	movq	%r14, %rdi
	movq	%rax, %rdx
	movl	$317, %r8d                      # imm = 0x13D
	jmp	.LBB5_86
.LBB5_71:
	movl	%eax, %ebx
	movq	stderr(%rip), %r14
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.10, %esi
	movl	$.L.str.3, %ecx
	movq	%r14, %rdi
	movq	%rax, %rdx
	movl	$318, %r8d                      # imm = 0x13E
	jmp	.LBB5_86
.LBB5_72:
	movl	%eax, %ebx
	movq	stderr(%rip), %r14
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.10, %esi
	movl	$.L.str.3, %ecx
	movq	%r14, %rdi
	movq	%rax, %rdx
	movl	$319, %r8d                      # imm = 0x13F
	jmp	.LBB5_86
.LBB5_73:
	movl	%eax, %ebp
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.10, %esi
	movl	$.L.str.3, %ecx
	movq	%rbx, %rdi
	movq	%rax, %rdx
	movl	$320, %r8d                      # imm = 0x140
	jmp	.LBB5_60
.LBB5_74:
	movl	%eax, %ebp
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.10, %esi
	movl	$.L.str.3, %ecx
	movq	%rbx, %rdi
	movq	%rax, %rdx
	movl	$321, %r8d                      # imm = 0x141
	jmp	.LBB5_60
.LBB5_75:
	movl	%eax, %ebp
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.10, %esi
	movl	$.L.str.3, %ecx
	movq	%rbx, %rdi
	movq	%rax, %rdx
	movl	$322, %r8d                      # imm = 0x142
	jmp	.LBB5_60
.LBB5_76:
	movl	%eax, %ebp
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.10, %esi
	movl	$.L.str.3, %ecx
	movq	%rbx, %rdi
	movq	%rax, %rdx
	movl	$323, %r8d                      # imm = 0x143
	jmp	.LBB5_60
.LBB5_77:
	movl	%eax, %ebp
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.10, %esi
	movl	$.L.str.3, %ecx
	movq	%rbx, %rdi
	movq	%rax, %rdx
	movl	$324, %r8d                      # imm = 0x144
	jmp	.LBB5_60
.LBB5_78:
	movl	%eax, %ebp
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.10, %esi
	movl	$.L.str.3, %ecx
	movq	%rbx, %rdi
	movq	%rax, %rdx
	movl	$325, %r8d                      # imm = 0x145
	jmp	.LBB5_60
.LBB5_79:
	movl	%eax, %ebp
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.10, %esi
	movl	$.L.str.3, %ecx
	movq	%rbx, %rdi
	movq	%rax, %rdx
	movl	$326, %r8d                      # imm = 0x146
	jmp	.LBB5_60
.LBB5_80:
	movl	%eax, %ebx
	movq	stderr(%rip), %r14
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.10, %esi
	movl	$.L.str.3, %ecx
	movq	%r14, %rdi
	movq	%rax, %rdx
	movl	$329, %r8d                      # imm = 0x149
	jmp	.LBB5_86
.LBB5_81:
	movl	%eax, %ebx
	movq	stderr(%rip), %r14
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.10, %esi
	movl	$.L.str.3, %ecx
	movq	%r14, %rdi
	movq	%rax, %rdx
	movl	$330, %r8d                      # imm = 0x14A
	jmp	.LBB5_86
.LBB5_82:
	movl	%eax, %ebx
	movq	stderr(%rip), %r14
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.10, %esi
	movl	$.L.str.3, %ecx
	movq	%r14, %rdi
	movq	%rax, %rdx
	movl	$331, %r8d                      # imm = 0x14B
	jmp	.LBB5_86
.LBB5_83:
	movl	%eax, %ebx
	movq	stderr(%rip), %r14
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.10, %esi
	movl	$.L.str.3, %ecx
	movq	%r14, %rdi
	movq	%rax, %rdx
	movl	$332, %r8d                      # imm = 0x14C
	jmp	.LBB5_86
.LBB5_84:
	movl	%eax, %ebx
	movq	stderr(%rip), %r14
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.10, %esi
	movl	$.L.str.3, %ecx
	movq	%r14, %rdi
	movq	%rax, %rdx
	movl	$333, %r8d                      # imm = 0x14D
	jmp	.LBB5_86
.LBB5_85:
	movl	%eax, %ebx
	movq	stderr(%rip), %r14
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.10, %esi
	movl	$.L.str.3, %ecx
	movq	%r14, %rdi
	movq	%rax, %rdx
	movl	$334, %r8d                      # imm = 0x14E
.LBB5_86:
	xorl	%eax, %eax
	callq	fprintf
	movl	%ebx, %edi
	callq	exit
.Lfunc_end5:
	.size	main, .Lfunc_end5-main
	.cfi_endproc
                                        # -- End function
	.globl	_Z4loadP8_IO_FILE               # -- Begin function _Z4loadP8_IO_FILE
	.type	_Z4loadP8_IO_FILE,@function
_Z4loadP8_IO_FILE:                      # @_Z4loadP8_IO_FILE
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$56, %rsp
	.cfi_def_cfa_offset 112
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%rdi, %rbx
	movl	$N_NUM, %edi
	movl	$4, %esi
	xorl	%edx, %edx
	callq	hipHostMalloc
	testl	%eax, %eax
	jne	.LBB6_1
# %bb.3:                                # %_Z9gpuAssert10hipError_tPKcib.exit
	movl	$E_NUM, %edi
	movl	$4, %esi
	xorl	%edx, %edx
	callq	hipHostMalloc
	testl	%eax, %eax
	jne	.LBB6_4
# %bb.5:                                # %_Z9gpuAssert10hipError_tPKcib.exit39
	movq	N_NUM(%rip), %r8
	movq	E_NUM(%rip), %r9
	leaq	36(%rsp), %rdx
	leaq	46(%rsp), %rcx
	movl	$.L.str.7, %esi
	movq	%rbx, %rdi
	xorl	%eax, %eax
	callq	__isoc23_fscanf
	cmpl	$-1, %eax
	je	.LBB6_6
# %bb.7:
	movq	N_NUM(%rip), %rax
	movslq	(%rax), %rax
	leaq	(%rax,%rax,8), %rcx
	leaq	(%rcx,%rcx,2), %rsi
	addq	%rax, %rsi
	movl	$n_table, %edi
	xorl	%edx, %edx
	callq	hipHostMalloc
	testl	%eax, %eax
	jne	.LBB6_8
# %bb.9:                                # %_Z9gpuAssert10hipError_tPKcib.exit41
	movq	E_NUM(%rip), %rax
	movslq	(%rax), %rax
	imulq	$56, %rax, %rsi
	movl	$e_table, %edi
	xorl	%edx, %edx
	callq	hipHostMalloc
	testl	%eax, %eax
	jne	.LBB6_24
# %bb.10:                               # %_Z9gpuAssert10hipError_tPKcib.exit43.preheader
	movq	N_NUM(%rip), %rax
	movl	(%rax), %edi
	testl	%edi, %edi
	jle	.LBB6_13
# %bb.11:                               # %.lr.ph
	movq	n_table(%rip), %rcx
	xorl	%edx, %edx
	movl	$-1, %esi
.LBB6_12:                               # %_Z9gpuAssert10hipError_tPKcib.exit43
                                        # =>This Inner Loop Header: Depth=1
	addl	%edi, %edi
	movslq	%edi, %rdi
	addq	%rdx, %rdi
	movl	%esi, (%rcx,%rdi,4)
	movslq	(%rax), %rdi
	leaq	(%rdi,%rdi,2), %rdi
	addq	%rdx, %rdi
	movl	%esi, (%rcx,%rdi,4)
	movslq	(%rax), %rdi
	leaq	(%rdx,%rdi,4), %rdi
	movl	%esi, (%rcx,%rdi,4)
	movl	(%rax), %edi
	incq	%rdx
	cmpl	%edi, %edx
	jl	.LBB6_12
.LBB6_13:                               # %.preheader
	movq	E_NUM(%rip), %rax
	movl	(%rax), %edi
	testl	%edi, %edi
	jle	.LBB6_16
# %bb.14:                               # %.lr.ph49
	movq	e_table(%rip), %rcx
	xorl	%edx, %edx
	movl	$-1, %esi
.LBB6_15:                               # =>This Inner Loop Header: Depth=1
	shll	$2, %edi
	movslq	%edi, %rdi
	addq	%rdx, %rdi
	movl	%esi, (%rcx,%rdi,4)
	movslq	(%rax), %rdi
	leaq	(%rdi,%rdi,2), %rdi
	leaq	(%rdx,%rdi,2), %rdi
	movl	%esi, (%rcx,%rdi,4)
	movslq	(%rax), %rdi
	leaq	(%rdi,%rdi,4), %rdi
	leaq	(%rdx,%rdi,2), %rdi
	movl	%esi, (%rcx,%rdi,4)
	movslq	(%rax), %rdi
	leaq	(%rdx,%rdi,8), %rdi
	movl	%esi, (%rcx,%rdi,4)
	movslq	(%rax), %rdi
	leaq	(%rdi,%rdi,2), %rdi
	leaq	(%rdx,%rdi,4), %rdi
	movl	%esi, (%rcx,%rdi,4)
	movl	(%rax), %edi
	leal	(%rdi,%rdi), %r8d
	incq	%rdx
	cmpl	%r8d, %edx
	jl	.LBB6_15
.LBB6_16:                               # %._crit_edge
	leaq	36(%rsp), %rdx
	leaq	20(%rsp), %rcx
	leaq	46(%rsp), %r8
	movl	$.L.str.8, %esi
	movq	%rbx, %rdi
	xorl	%eax, %eax
	callq	__isoc23_fscanf
	movl	$-1, %r14d
	cmpl	$-1, %eax
	je	.LBB6_23
# %bb.17:
	xorl	%ebp, %ebp
	movl	$source, %edi
	movl	$4, %esi
	xorl	%edx, %edx
	callq	hipHostMalloc
	leaq	20(%rsp), %rcx
	movl	(%rcx), %eax
	movq	source(%rip), %rdx
	movl	%eax, (%rdx)
	leaq	36(%rsp), %rdx
	leaq	46(%rsp), %r8
	movl	$.L.str.8, %esi
	movq	%rbx, %rdi
	xorl	%eax, %eax
	callq	__isoc23_fscanf
	cmpl	$-1, %eax
	je	.LBB6_23
# %bb.18:
	movl	$sink, %edi
	movl	$4, %esi
	xorl	%edx, %edx
	callq	hipHostMalloc
	movl	20(%rsp), %eax
	movq	sink(%rip), %rcx
	movl	%eax, (%rcx)
	movl	$4, %edi
	callq	_Znam
	movq	%rax, %r14
	movl	$0, (%rax)
	movq	E_NUM(%rip), %rax
	cmpl	$0, (%rax)
	jle	.LBB6_22
# %bb.19:                               # %.lr.ph53.preheader
	leaq	24(%rsp), %r15
	xorl	%r12d, %r12d
	xorl	%r13d, %r13d
	xorl	%ebp, %ebp
.LBB6_20:                               # %.lr.ph53
                                        # =>This Inner Loop Header: Depth=1
	movl	$.L.str.9, %esi
	movq	%rbx, %rdi
	leaq	36(%rsp), %rdx
	leaq	32(%rsp), %rcx
	leaq	28(%rsp), %r8
	movq	%r15, %r9
	xorl	%eax, %eax
	callq	__isoc23_fscanf
	cmpl	$-1, %eax
	je	.LBB6_22
# %bb.21:                               #   in Loop: Header=BB6_20 Depth=1
	movl	24(%rsp), %r8d
	cmpl	%ebp, %r8d
	cmovgl	%r8d, %ebp
	movq	n_table(%rip), %rdi
	movq	e_table(%rip), %rsi
	movl	32(%rsp), %edx
	movl	28(%rsp), %ecx
	movl	(%r14), %eax
	addl	%eax, %eax
	movl	%r12d, %r9d
	subl	%eax, %r9d
	movq	%r14, (%rsp)
	callq	_Z4linkPiS_iiiiS_
	incl	%r13d
	movq	E_NUM(%rip), %rax
	addl	$2, %r12d
	cmpl	(%rax), %r13d
	jl	.LBB6_20
.LBB6_22:                               # %.loopexit
	movq	%r14, %rdi
	callq	_ZdaPv
	movl	%ebp, %r14d
	jmp	.LBB6_23
.LBB6_6:
	movl	$-1, %r14d
.LBB6_23:
	movl	%r14d, %eax
	addq	$56, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB6_1:
	.cfi_def_cfa_offset 112
	movl	%eax, %ebp
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.10, %esi
	movl	$.L.str.3, %ecx
	movq	%rbx, %rdi
	movq	%rax, %rdx
	movl	$442, %r8d                      # imm = 0x1BA
	jmp	.LBB6_2
.LBB6_4:
	movl	%eax, %ebp
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.10, %esi
	movl	$.L.str.3, %ecx
	movq	%rbx, %rdi
	movq	%rax, %rdx
	movl	$443, %r8d                      # imm = 0x1BB
	jmp	.LBB6_2
.LBB6_8:
	movl	%eax, %ebp
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.10, %esi
	movl	$.L.str.3, %ecx
	movq	%rbx, %rdi
	movq	%rax, %rdx
	movl	$446, %r8d                      # imm = 0x1BE
	jmp	.LBB6_2
.LBB6_24:
	movl	%eax, %ebp
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.10, %esi
	movl	$.L.str.3, %ecx
	movq	%rbx, %rdi
	movq	%rax, %rdx
	movl	$447, %r8d                      # imm = 0x1BF
.LBB6_2:
	xorl	%eax, %eax
	callq	fprintf
	movl	%ebp, %edi
	callq	exit
.Lfunc_end6:
	.size	_Z4loadP8_IO_FILE, .Lfunc_end6-_Z4loadP8_IO_FILE
	.cfi_endproc
                                        # -- End function
	.globl	_Z4linkPiS_iiiiS_               # -- Begin function _Z4linkPiS_iiiiS_
	.type	_Z4linkPiS_iiiiS_,@function
_Z4linkPiS_iiiiS_:                      # @_Z4linkPiS_iiiiS_
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	N_NUM(%rip), %r10
	movslq	(%r10), %r11
	movslq	%edx, %rax
	leaq	(%rax,%r11,2), %rdx
	movl	(%rdi,%rdx,4), %r11d
	movq	E_NUM(%rip), %rdx
	movl	(%rdx), %r14d
	cmpl	$-1, %r11d
	je	.LBB7_5
# %bb.1:                                # %.lr.ph
	movq	48(%rsp), %rbx
	leal	(%r14,%r14), %r15d
	leal	(%r15,%r15,4), %r15d
	leal	(,%r14,4), %r12d
	leal	(%r12,%r12,2), %ebp
.LBB7_2:                                # =>This Inner Loop Header: Depth=1
	leal	(%r15,%r11), %r12d
	movslq	%r12d, %r12
	cmpl	%ecx, (%rsi,%r12,4)
	je	.LBB7_3
# %bb.4:                                #   in Loop: Header=BB7_2 Depth=1
	addl	%ebp, %r11d
	movslq	%r11d, %r11
	movl	(%rsi,%r11,4), %r11d
	cmpl	$-1, %r11d
	jne	.LBB7_2
.LBB7_5:                                # %._crit_edge
	movslq	%r9d, %rbx
	leaq	1(%rbx), %r11
	leal	(%rbx,%r14,4), %ebp
	movslq	%ebp, %r14
	movl	%r11d, (%rsi,%r14,4)
	movl	%r8d, (%rsi,%rbx,4)
	movslq	(%rdx), %r8
	leaq	(%r8,%r8,2), %r8
	leaq	(%rbx,%r8,2), %r8
	movl	%eax, (%rsi,%r8,4)
	movslq	(%rdx), %r8
	leaq	(%r8,%r8,4), %r8
	leaq	(%rbx,%r8,2), %r8
	movl	%ecx, (%rsi,%r8,4)
	movslq	(%r10), %r8
	leaq	(%rax,%r8,2), %r8
	movl	(%rdi,%r8,4), %r8d
	movslq	(%rdx), %r14
	leaq	(%r14,%r14,2), %r14
	leaq	(%rbx,%r14,4), %r14
	movl	%r8d, (%rsi,%r14,4)
	movslq	(%r10), %r8
	leaq	(%rax,%r8,2), %r8
	movl	%ebx, (%rdi,%r8,4)
	movslq	(%r10), %r8
	leaq	(%r8,%r8,2), %r14
	movslq	%ecx, %r8
	addq	%r8, %r14
	movl	(%rdi,%r14,4), %ebp
	movslq	(%rdx), %r14
	leaq	(%rbx,%r14,8), %r14
	movl	%ebp, (%rsi,%r14,4)
	movslq	(%r10), %r14
	leaq	(%r14,%r14,2), %r14
	addq	%r8, %r14
	movl	%ebx, (%rdi,%r14,4)
	movq	source(%rip), %rbx
	cmpl	%eax, (%rbx)
	jne	.LBB7_7
# %bb.6:
	movslq	(%r10), %rbx
	leaq	(%r8,%rbx,4), %rbx
	movl	%r9d, (%rdi,%rbx,4)
.LBB7_7:
	movq	sink(%rip), %rbx
	cmpl	%ecx, (%rbx)
	jne	.LBB7_9
# %bb.8:
	movslq	(%r10), %rbx
	leaq	(%rax,%rbx,4), %rbx
	movl	%r9d, (%rdi,%rbx,4)
.LBB7_9:
	movslq	(%rdx), %rbx
	leaq	(%r11,%rbx,4), %rbx
	movl	%r9d, (%rsi,%rbx,4)
	movslq	%r11d, %r9
	movl	$0, (%rsi,%r9,4)
	movslq	(%rdx), %rbx
	leaq	(%rbx,%rbx,2), %rbx
	leaq	(%r9,%rbx,2), %rbx
	movl	%ecx, (%rsi,%rbx,4)
	movslq	(%rdx), %rcx
	leaq	(%rcx,%rcx,4), %rcx
	leaq	(%r9,%rcx,2), %rcx
	movl	%eax, (%rsi,%rcx,4)
	movslq	(%r10), %rcx
	leaq	(%r8,%rcx,2), %rcx
	movl	(%rdi,%rcx,4), %ecx
	movslq	(%rdx), %rbx
	leaq	(%rbx,%rbx,2), %rbx
	leaq	(%r9,%rbx,4), %rbx
	movl	%ecx, (%rsi,%rbx,4)
	movslq	(%r10), %rcx
	leaq	(%r8,%rcx,2), %rcx
	movl	%r11d, (%rdi,%rcx,4)
	movslq	(%r10), %rcx
	leaq	(%rcx,%rcx,2), %rcx
	addq	%rax, %rcx
	movl	(%rdi,%rcx,4), %ecx
	movslq	(%rdx), %rdx
	leaq	(%r9,%rdx,8), %rdx
	movl	%ecx, (%rsi,%rdx,4)
	movslq	(%r10), %rcx
	leaq	(%rcx,%rcx,2), %rcx
	addq	%rax, %rcx
	movl	%r11d, (%rdi,%rcx,4)
	jmp	.LBB7_10
.LBB7_3:
	movslq	%r11d, %rax
	addl	%r8d, (%rsi,%rax,4)
	incl	(%rbx)
.LBB7_10:
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end7:
	.size	_Z4linkPiS_iiiiS_, .Lfunc_end7-_Z4linkPiS_iiiiS_
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB8_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB8_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z11first_resetPiS_S_S_S_S_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z10node_resetPiS_S_S_S_S_S_, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z8trace_cuPiS_S_S_S_S_S_S_, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z6aug_cuPiS_S_S_S_S_S_S_S_S_S_, %esi
	movl	$.L__unnamed_4, %edx
	movl	$.L__unnamed_4, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z9flg_resetPi, %esi
	movl	$.L__unnamed_5, %edx
	movl	$.L__unnamed_5, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end8:
	.size	__hip_module_ctor, .Lfunc_end8-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB9_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB9_2:
	retq
.Lfunc_end9:
	.size	__hip_module_dtor, .Lfunc_end9-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	N_NUM,@object                   # @N_NUM
	.bss
	.globl	N_NUM
	.p2align	3, 0x0
N_NUM:
	.quad	0
	.size	N_NUM, 8

	.type	E_NUM,@object                   # @E_NUM
	.globl	E_NUM
	.p2align	3, 0x0
E_NUM:
	.quad	0
	.size	E_NUM, 8

	.type	n_table,@object                 # @n_table
	.globl	n_table
	.p2align	3, 0x0
n_table:
	.quad	0
	.size	n_table, 8

	.type	e_table,@object                 # @e_table
	.globl	e_table
	.p2align	3, 0x0
e_table:
	.quad	0
	.size	e_table, 8

	.type	source,@object                  # @source
	.globl	source
	.p2align	3, 0x0
source:
	.quad	0
	.size	source, 8

	.type	sink,@object                    # @sink
	.globl	sink
	.p2align	3, 0x0
sink:
	.quad	0
	.size	sink, 8

	.type	_Z11first_resetPiS_S_S_S_S_,@object # @_Z11first_resetPiS_S_S_S_S_
	.section	.rodata,"a",@progbits
	.globl	_Z11first_resetPiS_S_S_S_S_
	.p2align	3, 0x0
_Z11first_resetPiS_S_S_S_S_:
	.quad	_Z26__device_stub__first_resetPiS_S_S_S_S_
	.size	_Z11first_resetPiS_S_S_S_S_, 8

	.type	_Z10node_resetPiS_S_S_S_S_S_,@object # @_Z10node_resetPiS_S_S_S_S_S_
	.globl	_Z10node_resetPiS_S_S_S_S_S_
	.p2align	3, 0x0
_Z10node_resetPiS_S_S_S_S_S_:
	.quad	_Z25__device_stub__node_resetPiS_S_S_S_S_S_
	.size	_Z10node_resetPiS_S_S_S_S_S_, 8

	.type	_Z8trace_cuPiS_S_S_S_S_S_S_,@object # @_Z8trace_cuPiS_S_S_S_S_S_S_
	.globl	_Z8trace_cuPiS_S_S_S_S_S_S_
	.p2align	3, 0x0
_Z8trace_cuPiS_S_S_S_S_S_S_:
	.quad	_Z23__device_stub__trace_cuPiS_S_S_S_S_S_S_
	.size	_Z8trace_cuPiS_S_S_S_S_S_S_, 8

	.type	_Z6aug_cuPiS_S_S_S_S_S_S_S_S_S_,@object # @_Z6aug_cuPiS_S_S_S_S_S_S_S_S_S_
	.globl	_Z6aug_cuPiS_S_S_S_S_S_S_S_S_S_
	.p2align	3, 0x0
_Z6aug_cuPiS_S_S_S_S_S_S_S_S_S_:
	.quad	_Z21__device_stub__aug_cuPiS_S_S_S_S_S_S_S_S_S_
	.size	_Z6aug_cuPiS_S_S_S_S_S_S_S_S_S_, 8

	.type	_Z9flg_resetPi,@object          # @_Z9flg_resetPi
	.globl	_Z9flg_resetPi
	.p2align	3, 0x0
_Z9flg_resetPi:
	.quad	_Z24__device_stub__flg_resetPi
	.size	_Z9flg_resetPi, 8

	.type	.L.str.1,@object                # @.str.1
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str.1:
	.asciz	"r"
	.size	.L.str.1, 2

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"Can't open file [%s]\n"
	.size	.L.str.2, 22

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"/home/ubuntu/Datasets/stackv2/train-structured-repos-hip-sm89/greensprin/BK/master/sub.hip"
	.size	.L.str.3, 91

	.type	.L.str.4,@object                # @.str.4
.L.str.4:
	.asciz	"current_flow : %d\n"
	.size	.L.str.4, 19

	.type	.L.str.5,@object                # @.str.5
.L.str.5:
	.asciz	"flow_sum : %d\n"
	.size	.L.str.5, 15

	.type	.L.str.6,@object                # @.str.6
.L.str.6:
	.asciz	"time:%.2f[s]\n"
	.size	.L.str.6, 14

	.type	.L.str.7,@object                # @.str.7
.L.str.7:
	.asciz	"%s %s %d %d\n"
	.size	.L.str.7, 13

	.type	.L.str.8,@object                # @.str.8
.L.str.8:
	.asciz	"%s %d %s\n"
	.size	.L.str.8, 10

	.type	.L.str.9,@object                # @.str.9
.L.str.9:
	.asciz	"%s %d %d %d\n"
	.size	.L.str.9, 13

	.type	.L.str.10,@object               # @.str.10
.L.str.10:
	.asciz	"GPUassert: %s %s %d\n"
	.size	.L.str.10, 21

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z11first_resetPiS_S_S_S_S_"
	.size	.L__unnamed_1, 28

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z10node_resetPiS_S_S_S_S_S_"
	.size	.L__unnamed_2, 29

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z8trace_cuPiS_S_S_S_S_S_S_"
	.size	.L__unnamed_3, 28

	.type	.L__unnamed_4,@object           # @3
.L__unnamed_4:
	.asciz	"_Z6aug_cuPiS_S_S_S_S_S_S_S_S_S_"
	.size	.L__unnamed_4, 32

	.type	.L__unnamed_5,@object           # @4
.L__unnamed_5:
	.asciz	"_Z9flg_resetPi"
	.size	.L__unnamed_5, 15

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.type	.Lstr,@object                   # @str
	.section	.rodata.str1.1,"aMS",@progbits,1
.Lstr:
	.asciz	"Usage: ./bk.exe file.inp"
	.size	.Lstr, 25

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z26__device_stub__first_resetPiS_S_S_S_S_
	.addrsig_sym _Z25__device_stub__node_resetPiS_S_S_S_S_S_
	.addrsig_sym _Z23__device_stub__trace_cuPiS_S_S_S_S_S_S_
	.addrsig_sym _Z21__device_stub__aug_cuPiS_S_S_S_S_S_S_S_S_S_
	.addrsig_sym _Z24__device_stub__flg_resetPi
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym N_NUM
	.addrsig_sym E_NUM
	.addrsig_sym n_table
	.addrsig_sym e_table
	.addrsig_sym source
	.addrsig_sym sink
	.addrsig_sym _Z11first_resetPiS_S_S_S_S_
	.addrsig_sym _Z10node_resetPiS_S_S_S_S_S_
	.addrsig_sym _Z8trace_cuPiS_S_S_S_S_S_S_
	.addrsig_sym _Z6aug_cuPiS_S_S_S_S_S_S_S_S_S_
	.addrsig_sym _Z9flg_resetPi
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z11first_resetPiS_S_S_S_S_ ; -- Begin function _Z11first_resetPiS_S_S_S_S_
	.globl	_Z11first_resetPiS_S_S_S_S_
	.p2align	8
	.type	_Z11first_resetPiS_S_S_S_S_,@function
_Z11first_resetPiS_S_S_S_S_:            ; @_Z11first_resetPiS_S_S_S_S_
; %bb.0:
	s_clause 0x1
	s_load_b128 s[16:19], s[0:1], 0x20
	s_load_b32 s2, s[0:1], 0x3c
	s_waitcnt lgkmcnt(0)
	s_load_b32 s12, s[16:17], 0x0
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	s_waitcnt lgkmcnt(0)
	v_cmpx_gt_i32_e64 s12, v1
	s_cbranch_execz .LBB0_14
; %bb.1:
	s_load_b256 s[4:11], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_load_b32 s0, s[8:9], 0x0
	s_waitcnt lgkmcnt(0)
	v_cmp_ne_u32_e32 vcc_lo, s0, v1
	s_and_saveexec_b32 s0, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s1, exec_lo, s0
	s_cbranch_execz .LBB0_12
; %bb.2:
	s_load_b32 s0, s[10:11], 0x0
	s_waitcnt lgkmcnt(0)
	v_cmp_ne_u32_e32 vcc_lo, s0, v1
	s_and_saveexec_b32 s0, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s2, exec_lo, s0
	s_cbranch_execz .LBB0_9
; %bb.3:
	v_lshl_add_u32 v2, s12, 2, v1
	s_mov_b32 s3, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s4, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
	global_load_b32 v0, v[2:3], off
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u32_e32 -1, v0
	s_cbranch_execz .LBB0_8
; %bb.4:
	s_load_b32 s0, s[18:19], 0x0
	v_add_nc_u32_e32 v4, s12, v1
	v_mov_b32_e32 v6, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v5, 31, v4
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	s_waitcnt lgkmcnt(0)
	v_mad_u64_u32 v[2:3], null, s0, 6, v[0:1]
	v_mov_b32_e32 v0, 1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s6, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
	v_add_co_u32 v4, vcc_lo, s4, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
	global_load_b32 v7, v[2:3], off
	global_store_b32 v[4:5], v0, off
	global_load_b32 v4, v6, s[16:17]
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[2:3], null, v4, 5, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s4, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
	global_store_b32 v[2:3], v0, off
	global_load_b32 v4, v6, s[16:17]
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[2:3], null, v4, 6, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s4, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
	global_store_b32 v[2:3], v0, off
	global_load_b32 v3, v6, s[8:9]
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	v_add_co_u32 v0, s0, s4, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v1, s0, s5, v1, s0
	s_mov_b32 s0, exec_lo
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u32_e64 v7, v3
	s_xor_b32 s0, exec_lo, s0
	s_cbranch_execz .LBB0_6
; %bb.5:
	v_mov_b32_e32 v2, 2
	global_store_b32 v[0:1], v2, off
                                        ; implicit-def: $vgpr0_vgpr1
.LBB0_6:                                ; %Flow
	s_and_not1_saveexec_b32 s0, s0
	s_cbranch_execz .LBB0_8
; %bb.7:
	v_mov_b32_e32 v2, 1
	global_store_b32 v[0:1], v2, off
.LBB0_8:                                ; %Flow82
	s_or_b32 exec_lo, exec_lo, s3
                                        ; implicit-def: $vgpr1_vgpr2
.LBB0_9:                                ; %Flow83
	s_and_not1_saveexec_b32 s0, s2
	s_cbranch_execz .LBB0_11
; %bb.10:
	v_ashrrev_i32_e32 v2, 31, v1
	v_mov_b32_e32 v4, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	v_mov_b32_e32 v2, 2
	v_add_co_u32 v0, vcc_lo, s4, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
	global_store_b32 v[0:1], v2, off
	global_load_b32 v2, v4, s[16:17]
	s_waitcnt vmcnt(0)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, v0, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, v1, v3, vcc_lo
	global_store_b32 v[2:3], v4, off
	global_load_b32 v2, v4, s[16:17]
	s_waitcnt vmcnt(0)
	v_mul_lo_u32 v2, v2, 5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, v0, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, v1, v3, vcc_lo
	global_store_b32 v[2:3], v4, off
	global_load_b32 v2, v4, s[16:17]
	s_waitcnt vmcnt(0)
	v_mul_lo_u32 v2, v2, 6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, v2
	v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo
	global_store_b32 v[0:1], v4, off
.LBB0_11:                               ; %Flow84
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $vgpr1_vgpr2
.LBB0_12:                               ; %Flow85
	s_and_not1_saveexec_b32 s0, s1
	s_cbranch_execz .LBB0_14
; %bb.13:
	v_ashrrev_i32_e32 v2, 31, v1
	v_mov_b32_e32 v4, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	v_mov_b32_e32 v2, 1
	v_add_co_u32 v0, vcc_lo, s4, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
	global_store_b32 v[0:1], v2, off
	global_load_b32 v2, v4, s[16:17]
	s_waitcnt vmcnt(0)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, v0, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, v1, v3, vcc_lo
	global_store_b32 v[2:3], v4, off
	global_load_b32 v2, v4, s[16:17]
	s_waitcnt vmcnt(0)
	v_mul_lo_u32 v2, v2, 5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, v0, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, v1, v3, vcc_lo
	global_store_b32 v[2:3], v4, off
	global_load_b32 v2, v4, s[16:17]
	s_waitcnt vmcnt(0)
	v_mul_lo_u32 v2, v2, 6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, v2
	v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo
	global_store_b32 v[0:1], v4, off
.LBB0_14:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z11first_resetPiS_S_S_S_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 304
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 8
		.amdhsa_next_free_sgpr 20
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z11first_resetPiS_S_S_S_S_, .Lfunc_end0-_Z11first_resetPiS_S_S_S_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1008
; NumSgprs: 22
; NumVgprs: 8
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 22
; NumVGPRsForWavesPerEU: 8
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z10node_resetPiS_S_S_S_S_S_ ; -- Begin function _Z10node_resetPiS_S_S_S_S_S_
	.globl	_Z10node_resetPiS_S_S_S_S_S_
	.p2align	8
	.type	_Z10node_resetPiS_S_S_S_S_S_,@function
_Z10node_resetPiS_S_S_S_S_S_:           ; @_Z10node_resetPiS_S_S_S_S_S_
; %bb.0:
	s_clause 0x1
	s_load_b64 s[8:9], s[0:1], 0x20
	s_load_b32 s2, s[0:1], 0x44
	s_waitcnt lgkmcnt(0)
	s_load_b32 s10, s[8:9], 0x0
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	s_waitcnt lgkmcnt(0)
	v_cmpx_gt_i32_e64 s10, v1
	s_cbranch_execz .LBB1_11
; %bb.1:
	s_load_b256 s[0:7], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_load_b32 s4, s[4:5], 0x0
	s_waitcnt lgkmcnt(0)
	v_cmp_ne_u32_e32 vcc_lo, s4, v1
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB1_11
; %bb.2:
	s_load_b32 s4, s[6:7], 0x0
	s_waitcnt lgkmcnt(0)
	v_cmp_ne_u32_e32 vcc_lo, s4, v1
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB1_11
; %bb.3:
	v_lshl_add_u32 v2, s10, 2, v1
	s_mov_b32 s5, 0
	s_mov_b32 s4, exec_lo
                                        ; implicit-def: $sgpr6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[3:4], 2, v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, s0, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
	global_load_b32 v0, v[3:4], off
                                        ; implicit-def: $vgpr3
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u32_e32 -1, v0
	s_xor_b32 s4, exec_lo, s4
	s_cbranch_execz .LBB1_7
; %bb.4:
	v_add_nc_u32_e32 v2, s10, v2
	v_mov_b32_e32 v4, 1
	v_mov_b32_e32 v0, 0
                                        ; implicit-def: $sgpr6
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s0, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
	global_store_b32 v[2:3], v4, off
	global_load_b32 v4, v0, s[8:9]
	s_waitcnt vmcnt(0)
	v_lshl_add_u32 v2, v4, 2, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s0, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
	global_load_b32 v2, v[2:3], off
	s_waitcnt vmcnt(0)
	v_ashrrev_i32_e32 v3, 31, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	v_add_co_u32 v2, vcc_lo, s2, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
	s_mov_b32 s2, 0
	s_mov_b32 s3, exec_lo
	global_load_b32 v2, v[2:3], off
                                        ; implicit-def: $vgpr3
	s_waitcnt vmcnt(0)
	v_cmpx_eq_u32_e32 0, v2
	s_xor_b32 s3, exec_lo, s3
	s_cbranch_execz .LBB1_6
; %bb.5:
	v_add_nc_u32_e32 v5, v4, v1
	v_ashrrev_i32_e32 v2, 31, v1
	s_mov_b32 s2, exec_lo
	s_mov_b32 s6, -1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v6, 31, v5
	v_lshlrev_b64 v[2:3], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[5:6], 2, v[5:6]
	v_add_co_u32 v5, vcc_lo, s0, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_ci_u32_e32 v6, vcc_lo, s1, v6, vcc_lo
	v_add_co_u32 v2, vcc_lo, s0, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
	s_clause 0x1
	global_store_b32 v[5:6], v4, off
	global_store_b32 v[2:3], v0, off
	global_load_b32 v4, v0, s[8:9]
	s_waitcnt vmcnt(0)
	v_mul_lo_u32 v4, v4, 5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v5, 31, v4
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, v2, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, v3, v5, vcc_lo
	global_store_b32 v[4:5], v0, off
	global_load_b32 v4, v0, s[8:9]
	s_waitcnt vmcnt(0)
	v_mul_lo_u32 v4, v4, 6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v5, 31, v4
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, v2, v4
	v_add_co_ci_u32_e32 v3, vcc_lo, v3, v5, vcc_lo
	global_store_b32 v[2:3], v0, off
	global_load_b32 v0, v0, s[8:9]
	s_waitcnt vmcnt(0)
	v_lshlrev_b32_e32 v3, 2, v0
.LBB1_6:                                ; %Flow72
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s5, s2, exec_lo
.LBB1_7:                                ; %Flow
	s_or_saveexec_b32 s2, s4
	v_mov_b32_e32 v0, s6
	s_xor_b32 exec_lo, exec_lo, s2
	s_cbranch_execz .LBB1_9
; %bb.8:
	v_dual_mov_b32 v0, 0 :: v_dual_add_nc_u32 v3, s10, v1
	v_ashrrev_i32_e32 v2, 31, v1
	v_mov_b32_e32 v7, s10
	s_or_b32 s5, s5, exec_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_ashrrev_i32_e32 v4, 31, v3
	v_lshlrev_b64 v[5:6], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	v_add_co_u32 v2, vcc_lo, s0, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v4, vcc_lo
	v_add_co_u32 v4, vcc_lo, s0, v5
	v_add_co_ci_u32_e32 v5, vcc_lo, s1, v6, vcc_lo
	s_clause 0x1
	global_store_b32 v[2:3], v7, off
	global_store_b32 v[4:5], v0, off
	global_load_b32 v2, v0, s[8:9]
	s_waitcnt vmcnt(0)
	v_mul_lo_u32 v2, v2, 5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, v4, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, v5, v3, vcc_lo
	global_store_b32 v[2:3], v0, off
	global_load_b32 v2, v0, s[8:9]
	s_waitcnt vmcnt(0)
	v_mul_lo_u32 v3, v2, 6
.LBB1_9:                                ; %Flow73
	s_or_b32 exec_lo, exec_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 exec_lo, exec_lo, s5
	s_cbranch_execz .LBB1_11
; %bb.10:                               ; %.sink.split
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v1, v3, v1
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_store_b32 v[1:2], v0, off
.LBB1_11:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z10node_resetPiS_S_S_S_S_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 312
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 8
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z10node_resetPiS_S_S_S_S_S_, .Lfunc_end1-_Z10node_resetPiS_S_S_S_S_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 892
; NumSgprs: 18
; NumVgprs: 8
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 8
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z8trace_cuPiS_S_S_S_S_S_S_ ; -- Begin function _Z8trace_cuPiS_S_S_S_S_S_S_
	.globl	_Z8trace_cuPiS_S_S_S_S_S_S_
	.p2align	8
	.type	_Z8trace_cuPiS_S_S_S_S_S_S_,@function
_Z8trace_cuPiS_S_S_S_S_S_S_:            ; @_Z8trace_cuPiS_S_S_S_S_S_S_
; %bb.0:
	s_load_b256 s[4:11], s[0:1], 0x20
	v_mov_b32_e32 v1, 0
	s_mov_b32 s3, exec_lo
	s_waitcnt lgkmcnt(0)
	global_store_b32 v1, v1, s[8:9]
	global_load_b32 v1, v1, s[4:5]
	s_load_b32 s2, s[0:1], 0x4c
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[2:3], null, s15, s2, v[0:1]
	v_readfirstlane_b32 s2, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_cmpx_lt_i32_e64 v2, v1
	s_cbranch_execz .LBB2_20
; %bb.1:
	s_load_b256 s[12:19], s[0:1], 0x0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s4, s2, 5
	v_add_nc_u32_e32 v0, s4, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v1, 31, v0
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s12, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s13, v1, vcc_lo
	global_load_b32 v3, v[0:1], off
	s_waitcnt vmcnt(0)
	v_cmp_eq_u32_e32 vcc_lo, 1, v3
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB2_20
; %bb.2:
	v_ashrrev_i32_e32 v3, 31, v2
	s_mov_b32 s5, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	v_add_co_u32 v2, vcc_lo, s12, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v3, vcc_lo, s13, v3, vcc_lo
	global_load_b32 v4, v[2:3], off
	s_waitcnt vmcnt(0)
	v_cmp_eq_u32_e32 vcc_lo, 1, v4
	v_cndmask_b32_e64 v4, 3, 2, vcc_lo
	v_mul_lo_u32 v4, v4, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v5, 31, v4
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v4, s0, v2, v4
	v_add_co_ci_u32_e64 v5, s0, v3, v5, s0
	global_load_b32 v8, v[4:5], off
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u32_e32 -1, v8
	s_cbranch_execz .LBB2_19
; %bb.3:                                ; %.lr.ph.lr.ph
	v_mov_b32_e32 v15, 0
	v_cndmask_b32_e64 v5, 4, 6, vcc_lo
	v_cndmask_b32_e64 v7, 3, 5, vcc_lo
	s_ashr_i32 s3, s2, 31
	v_cndmask_b32_e64 v16, 2, 1, vcc_lo
	global_load_b32 v4, v15, s[6:7]
	s_lshl_b64 s[0:1], s[2:3], 2
	s_mul_i32 s10, s2, 6
	v_add_co_u32 v2, vcc_lo, v2, s0
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
	v_mov_b32_e32 v17, 1
	s_ashr_i32 s11, s10, 31
	s_mov_b32 s6, 0
	s_lshl_b64 s[2:3], s[10:11], 2
	s_waitcnt vmcnt(0)
	v_lshlrev_b32_e32 v6, 1, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v4, v5, v6
	v_mul_lo_u32 v6, v7, v6
	v_ashrrev_i32_e32 v5, 31, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v7, 31, v6
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	s_delay_alu instid0(VALU_DEP_2)
	v_lshlrev_b64 v[6:7], 2, v[6:7]
.LBB2_4:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	v_ashrrev_i32_e32 v9, 31, v8
	s_mov_b32 s7, -1
	s_mov_b32 s10, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[9:10], 2, v[8:9]
	v_add_co_u32 v9, vcc_lo, s14, v9
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v10, vcc_lo, s15, v10, vcc_lo
	global_load_b32 v11, v[9:10], off
	s_waitcnt vmcnt(0)
	v_cmpx_gt_i32_e32 1, v11
	s_xor_b32 s10, exec_lo, s10
	s_cbranch_execz .LBB2_6
; %bb.5:                                ;   in Loop: Header=BB2_4 Depth=1
	v_add_co_u32 v8, vcc_lo, v9, v4
	v_add_co_ci_u32_e32 v9, vcc_lo, v10, v5, vcc_lo
	global_load_b32 v8, v[8:9], off
                                        ; implicit-def: $vgpr9
	s_waitcnt vmcnt(0)
	v_cmp_eq_u32_e32 vcc_lo, -1, v8
	s_or_not1_b32 s7, vcc_lo, exec_lo
.LBB2_6:                                ; %Flow100
                                        ;   in Loop: Header=BB2_4 Depth=1
	s_and_not1_saveexec_b32 s10, s10
	s_cbranch_execz .LBB2_18
; %bb.7:                                ;   in Loop: Header=BB2_4 Depth=1
	v_add_co_u32 v11, vcc_lo, v9, v6
	v_add_co_ci_u32_e32 v12, vcc_lo, v10, v7, vcc_lo
	s_mov_b32 s11, exec_lo
	global_load_b32 v13, v[11:12], off
	s_waitcnt vmcnt(0)
	v_ashrrev_i32_e32 v14, 31, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[11:12], 2, v[13:14]
	v_add_co_u32 v11, vcc_lo, s12, v11
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v12, vcc_lo, s13, v12, vcc_lo
	global_load_b32 v14, v[11:12], off
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u32_e32 0, v14
	s_xor_b32 s11, exec_lo, s11
	s_cbranch_execz .LBB2_13
; %bb.8:                                ;   in Loop: Header=BB2_4 Depth=1
	s_mov_b32 s20, exec_lo
	v_cmpx_ne_u32_e64 v14, v16
	s_cbranch_execz .LBB2_12
; %bb.9:                                ;   in Loop: Header=BB2_4 Depth=1
	s_mov_b32 s22, exec_lo
	s_mov_b32 s21, exec_lo
	v_mbcnt_lo_u32_b32 v11, s22, 0
                                        ; implicit-def: $vgpr12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v11
	s_cbranch_execz .LBB2_11
; %bb.10:                               ;   in Loop: Header=BB2_4 Depth=1
	s_bcnt1_i32_b32 s22, s22
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v12, s22
	global_atomic_add_u32 v12, v15, v12, s[16:17] glc
.LBB2_11:                               ;   in Loop: Header=BB2_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s21
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s21, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v11, s21, v11
	v_ashrrev_i32_e32 v12, 31, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[11:12], 2, v[11:12]
	v_add_co_u32 v11, vcc_lo, s18, v11
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v12, vcc_lo, s19, v12, vcc_lo
	global_store_b32 v[11:12], v8, off
.LBB2_12:                               ; %Flow
                                        ;   in Loop: Header=BB2_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s20
                                        ; implicit-def: $vgpr11
                                        ; implicit-def: $vgpr13
.LBB2_13:                               ; %Flow99
                                        ;   in Loop: Header=BB2_4 Depth=1
	s_and_not1_saveexec_b32 s11, s11
	s_cbranch_execz .LBB2_17
; %bb.14:                               ;   in Loop: Header=BB2_4 Depth=1
	v_add_co_u32 v18, vcc_lo, v11, s2
	v_add_co_ci_u32_e32 v19, vcc_lo, s3, v12, vcc_lo
	s_mov_b32 s20, exec_lo
	global_atomic_add_u32 v8, v[18:19], v17, off glc
	s_waitcnt vmcnt(0)
	v_cmpx_eq_u32_e32 0, v8
	s_cbranch_execz .LBB2_16
; %bb.15:                               ;   in Loop: Header=BB2_4 Depth=1
	global_store_b32 v[11:12], v16, off
	global_load_b32 v8, v[2:3], off
	v_add_nc_u32_e32 v13, s4, v13
	v_add_co_u32 v11, vcc_lo, v11, s0
	v_add_co_ci_u32_e32 v12, vcc_lo, s1, v12, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v14, 31, v13
	v_lshlrev_b64 v[13:14], 2, v[13:14]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v13, vcc_lo, s12, v13
	v_add_co_ci_u32_e32 v14, vcc_lo, s13, v14, vcc_lo
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v8, 1, v8
	s_clause 0x1
	global_store_b32 v[11:12], v8, off
	global_store_b32 v[13:14], v17, off
	global_store_b32 v15, v17, s[8:9]
.LBB2_16:                               ; %Flow98
                                        ;   in Loop: Header=BB2_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s20
.LBB2_17:                               ;   in Loop: Header=BB2_4 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s11
	v_add_co_u32 v8, vcc_lo, v9, v4
	v_add_co_ci_u32_e32 v9, vcc_lo, v10, v5, vcc_lo
	s_and_not1_b32 s7, s7, exec_lo
	global_load_b32 v8, v[8:9], off
	s_waitcnt vmcnt(0)
	v_cmp_eq_u32_e32 vcc_lo, -1, v8
	s_and_b32 s11, vcc_lo, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s7, s7, s11
.LBB2_18:                               ; %Flow101
                                        ;   in Loop: Header=BB2_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s7, exec_lo, s7
	s_or_b32 s6, s7, s6
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s6
	s_cbranch_execnz .LBB2_4
.LBB2_19:                               ; %Flow103
	s_or_b32 exec_lo, exec_lo, s5
	v_mov_b32_e32 v2, 0
	global_store_b32 v[0:1], v2, off
.LBB2_20:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z8trace_cuPiS_S_S_S_S_S_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 320
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 20
		.amdhsa_next_free_sgpr 23
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_Z8trace_cuPiS_S_S_S_S_S_S_, .Lfunc_end2-_Z8trace_cuPiS_S_S_S_S_S_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1000
; NumSgprs: 25
; NumVgprs: 20
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 25
; NumVGPRsForWavesPerEU: 20
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z6aug_cuPiS_S_S_S_S_S_S_S_S_S_ ; -- Begin function _Z6aug_cuPiS_S_S_S_S_S_S_S_S_S_
	.globl	_Z6aug_cuPiS_S_S_S_S_S_S_S_S_S_
	.p2align	8
	.type	_Z6aug_cuPiS_S_S_S_S_S_S_S_S_S_,@function
_Z6aug_cuPiS_S_S_S_S_S_S_S_S_S_:        ; @_Z6aug_cuPiS_S_S_S_S_S_S_S_S_S_
; %bb.0:
	s_clause 0x1
	s_load_b512 s[16:31], s[0:1], 0x0
	s_load_b32 s2, s[0:1], 0x64
	s_waitcnt lgkmcnt(0)
	s_load_b32 s3, s[20:21], 0x0
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	s_waitcnt lgkmcnt(0)
	v_cmpx_gt_i32_e64 s3, v1
	s_cbranch_execz .LBB3_44
; %bb.1:
	v_ashrrev_i32_e32 v2, 31, v1
	v_mov_b32_e32 v5, 1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	v_add_co_u32 v0, vcc_lo, s22, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v1, vcc_lo, s23, v1, vcc_lo
	global_load_b32 v0, v[0:1], off
	s_waitcnt vmcnt(0)
	v_ashrrev_i32_e32 v1, 31, v0
	v_lshlrev_b64 v[1:2], 2, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, s28, v1
	v_add_co_ci_u32_e32 v4, vcc_lo, s29, v2, vcc_lo
	global_atomic_swap_b32 v3, v[3:4], v5, off glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u32_e32 vcc_lo, 0, v3
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB3_44
; %bb.2:
	v_add_co_u32 v1, vcc_lo, s18, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s19, v2, vcc_lo
	global_load_b32 v22, v[1:2], off
	s_waitcnt vmcnt(0)
	v_cmp_ne_u32_e32 vcc_lo, 0, v22
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB3_44
; %bb.3:
	s_clause 0x1
	s_load_b128 s[4:7], s[0:1], 0x40
	s_load_b64 s[2:3], s[0:1], 0x50
	v_dual_mov_b32 v23, 0 :: v_dual_mov_b32 v30, 3
	v_mov_b32_e32 v29, 4
	v_dual_mov_b32 v25, 1 :: v_dual_mov_b32 v26, -1
	v_mov_b32_e32 v32, 3
	s_mov_b32 s1, 0
	s_waitcnt lgkmcnt(0)
	global_load_b32 v7, v23, s[6:7]
	v_mov_b32_e32 v27, 1
	s_waitcnt vmcnt(0)
	v_mul_lo_u32 v3, v7, 6
	v_readfirstlane_b32 s0, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v4, 31, v3
	v_lshlrev_b64 v[4:5], 2, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, v1, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, v2, v5, vcc_lo
	global_load_b32 v24, v23, s[4:5]
	global_load_b32 v9, v[4:5], off
	s_lshl_b32 s4, s0, 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_add3_u32 v6, s4, v3, v0
	s_ashr_i32 s5, s4, 31
	s_lshl_b64 s[4:5], s[4:5], 2
	s_waitcnt vmcnt(1)
	v_mul_lo_u32 v28, v24, 6
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v4, v9, v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v5, 31, v4
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, s16, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s17, v5, vcc_lo
	global_load_b32 v11, v[4:5], off
	v_lshlrev_b32_e32 v4, 1, v7
	v_ashrrev_i32_e32 v7, 31, v6
	v_mov_b32_e32 v10, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_ashrrev_i32_e32 v5, 31, v4
	v_lshlrev_b64 v[7:8], 2, v[6:7]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[5:6], 2, v[4:5]
	v_add_co_u32 v7, vcc_lo, s18, v7
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v8, vcc_lo, s19, v8, vcc_lo
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v31, -1, v11
.LBB3_4:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB3_6 Depth 2
                                        ;     Child Loop BB3_27 Depth 2
                                        ;     Child Loop BB3_37 Depth 2
	v_mad_u64_u32 v[11:12], null, v30, v24, v[9:10]
	s_mov_b32 s0, 0
	s_mov_b32 s6, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v12, 31, v11
	v_lshlrev_b64 v[11:12], 2, v[11:12]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v11, vcc_lo, s16, v11
	v_add_co_ci_u32_e32 v12, vcc_lo, s17, v12, vcc_lo
	global_load_b32 v11, v[11:12], off
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u32_e32 -1, v11
	s_cbranch_execz .LBB3_43
; %bb.5:                                ; %.lr.ph
                                        ;   in Loop: Header=BB3_4 Depth=1
	v_mul_lo_u32 v12, v32, v4
	v_mul_lo_u32 v14, v29, v4
	s_mov_b32 s8, 0
                                        ; implicit-def: $sgpr7
                                        ; implicit-def: $sgpr9
                                        ; implicit-def: $sgpr10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v13, 31, v12
	v_ashrrev_i32_e32 v15, 31, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[16:17], 2, v[12:13]
	v_lshlrev_b64 v[18:19], 2, v[14:15]
.LBB3_6:                                ;   Parent Loop BB3_4 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_ashrrev_i32_e32 v12, 31, v11
	s_mov_b32 s11, exec_lo
                                        ; implicit-def: $sgpr12
                                        ; implicit-def: $vgpr15
                                        ; implicit-def: $vgpr14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[20:21], 2, v[11:12]
	v_add_co_u32 v12, vcc_lo, s18, v20
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v13, vcc_lo, s19, v21, vcc_lo
	global_load_b32 v33, v[12:13], off
	s_waitcnt vmcnt(0)
	v_cmp_gt_i32_e32 vcc_lo, 1, v33
	v_cmpx_lt_i32_e32 0, v33
	s_cbranch_execz .LBB3_12
; %bb.7:                                ;   in Loop: Header=BB3_6 Depth=2
	v_add_co_u32 v14, s0, v12, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e64 v15, s0, v13, v17, s0
	s_mov_b32 s14, -1
                                        ; implicit-def: $sgpr12
	global_load_b32 v14, v[14:15], off
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v34, v14, v24
	v_ashrrev_i32_e32 v35, 31, v34
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[34:35], 2, v[34:35]
	v_add_co_u32 v34, s0, s16, v34
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e64 v35, s0, s17, v35, s0
	global_load_b32 v15, v[34:35], off
	s_waitcnt vmcnt(0)
	v_cmp_eq_u32_e64 s0, v15, v31
                                        ; implicit-def: $vgpr15
	s_and_saveexec_b32 s13, s0
	s_cbranch_execz .LBB3_11
; %bb.8:                                ;   in Loop: Header=BB3_6 Depth=2
	v_ashrrev_i32_e32 v15, 31, v14
	s_mov_b32 s15, exec_lo
                                        ; implicit-def: $sgpr12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[34:35], 2, v[14:15]
	v_add_co_u32 v34, s0, s16, v34
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v35, s0, s17, v35, s0
	global_load_b32 v15, v[34:35], off
	s_waitcnt vmcnt(0)
	v_cmp_ne_u32_e64 s14, v15, v27
	v_cmpx_eq_u32_e64 v15, v27
	s_cbranch_execz .LBB3_10
; %bb.9:                                ;   in Loop: Header=BB3_6 Depth=2
	v_add_co_u32 v20, s0, s28, v20
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v21, s0, s29, v21, s0
	s_and_not1_b32 s14, s14, exec_lo
	s_mov_b32 s12, -1
	global_atomic_swap_b32 v15, v[20:21], v25, off glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u32_e64 s0, 0, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, s0, exec_lo
	s_or_b32 s14, s14, s0
.LBB3_10:                               ; %Flow203
                                        ;   in Loop: Header=BB3_6 Depth=2
	s_or_b32 exec_lo, exec_lo, s15
	v_mov_b32_e32 v15, v11
	s_or_not1_b32 s14, s14, exec_lo
.LBB3_11:                               ; %Flow202
                                        ;   in Loop: Header=BB3_6 Depth=2
	s_or_b32 exec_lo, exec_lo, s13
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_and_not1_b32 s0, vcc_lo, exec_lo
	s_and_b32 s13, s14, exec_lo
	s_or_b32 vcc_lo, s0, s13
.LBB3_12:                               ; %Flow201
                                        ;   in Loop: Header=BB3_6 Depth=2
	s_or_b32 exec_lo, exec_lo, s11
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 s0, s10, exec_lo
	s_and_b32 s10, s12, exec_lo
	s_mov_b32 s11, -1
	s_or_b32 s10, s0, s10
                                        ; implicit-def: $vgpr20
                                        ; implicit-def: $sgpr0
	s_and_saveexec_b32 s12, vcc_lo
	s_cbranch_execz .LBB3_14
; %bb.13:                               ;   in Loop: Header=BB3_6 Depth=2
	v_add_co_u32 v14, vcc_lo, v12, v18
	v_add_co_ci_u32_e32 v15, vcc_lo, v13, v19, vcc_lo
	s_mov_b32 s0, 0
	s_and_not1_b32 s10, s10, exec_lo
	global_load_b32 v20, v[14:15], off
	v_mov_b32_e32 v15, v11
                                        ; implicit-def: $vgpr14
	s_waitcnt vmcnt(0)
	v_cmp_eq_u32_e32 vcc_lo, -1, v20
	s_or_not1_b32 s11, vcc_lo, exec_lo
.LBB3_14:                               ; %Flow204
                                        ;   in Loop: Header=BB3_6 Depth=2
	s_or_b32 exec_lo, exec_lo, s12
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s11, exec_lo, s11
	v_mov_b32_e32 v11, v20
	s_or_b32 s8, s11, s8
	s_and_not1_b32 s9, s9, exec_lo
	s_and_b32 s11, s10, exec_lo
	s_and_not1_b32 s7, s7, exec_lo
	s_and_b32 s0, s0, exec_lo
	s_or_b32 s9, s9, s11
	s_or_b32 s7, s7, s0
	s_and_not1_b32 exec_lo, exec_lo, s8
	s_cbranch_execnz .LBB3_6
; %bb.15:                               ; %loop.exit.guard
                                        ;   in Loop: Header=BB3_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s8
	s_and_saveexec_b32 s0, s9
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s8, exec_lo, s0
	s_cbranch_execz .LBB3_42
; %bb.16:                               ;   in Loop: Header=BB3_4 Depth=1
	global_load_b32 v11, v23, s[26:27]
	v_min_i32_e32 v22, v22, v33
	s_mov_b32 s0, exec_lo
                                        ; implicit-def: $sgpr9
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u32_e64 v14, v11
	s_xor_b32 s0, exec_lo, s0
	s_cbranch_execz .LBB3_20
; %bb.17:                               ;   in Loop: Header=BB3_4 Depth=1
	global_load_b32 v9, v23, s[24:25]
	s_mov_b32 s9, exec_lo
	s_waitcnt vmcnt(0)
	v_cmpx_eq_u32_e64 v14, v9
	s_cbranch_execz .LBB3_19
; %bb.18:                               ;   in Loop: Header=BB3_4 Depth=1
	global_load_b32 v14, v[7:8], off
	v_dual_mov_b32 v32, 5 :: v_dual_mov_b32 v29, 6
	v_dual_mov_b32 v30, 2 :: v_dual_mov_b32 v27, 2
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v16, v14, v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v17, 31, v16
	v_lshlrev_b64 v[16:17], 2, v[16:17]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v16, vcc_lo, s16, v16
	v_add_co_ci_u32_e32 v17, vcc_lo, s17, v17, vcc_lo
	global_load_b32 v31, v[16:17], off
.LBB3_19:                               ;   in Loop: Header=BB3_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s9
	v_add_co_u32 v16, vcc_lo, v12, v5
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v31, -1, v31
	v_add_co_ci_u32_e32 v17, vcc_lo, v13, v6, vcc_lo
	v_mov_b32_e32 v9, v14
	s_mov_b32 s9, -1
	global_store_b32 v[16:17], v10, off
                                        ; implicit-def: $vgpr10
.LBB3_20:                               ; %Flow196
                                        ;   in Loop: Header=BB3_4 Depth=1
	s_and_not1_saveexec_b32 s10, s0
	s_cbranch_execz .LBB3_41
; %bb.21:                               ;   in Loop: Header=BB3_4 Depth=1
	v_add_co_u32 v17, vcc_lo, v12, s4
	v_sub_nc_u32_e32 v16, 0, v22
	v_add_co_ci_u32_e32 v18, vcc_lo, s5, v13, vcc_lo
	s_mov_b32 s0, exec_lo
	global_atomic_add_u32 v11, v[12:13], v16, off glc
	global_load_b32 v17, v[17:18], off
	s_waitcnt vmcnt(0)
	v_ashrrev_i32_e32 v18, 31, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[17:18], 2, v[17:18]
	v_add_co_u32 v17, vcc_lo, s18, v17
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v18, vcc_lo, s19, v18, vcc_lo
	global_atomic_add_u32 v[17:18], v22, off
	v_cmpx_eq_u32_e64 v11, v22
	s_cbranch_execz .LBB3_25
; %bb.22:                               ;   in Loop: Header=BB3_4 Depth=1
	v_add_nc_u32_e32 v14, v3, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v15, 31, v14
	v_lshlrev_b64 v[14:15], 2, v[14:15]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v14, vcc_lo, s18, v14
	v_add_co_ci_u32_e32 v15, vcc_lo, s19, v15, vcc_lo
	global_load_b32 v11, v[14:15], off
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v14, v11, v28
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v15, 31, v14
	v_lshlrev_b64 v[14:15], 2, v[14:15]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v14, vcc_lo, s16, v14
	v_add_co_ci_u32_e32 v15, vcc_lo, s17, v15, vcc_lo
	global_atomic_add_u32 v11, v[14:15], v26, off glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u32_e32 vcc_lo, 1, v11
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB3_25
; %bb.23:                               ;   in Loop: Header=BB3_4 Depth=1
	s_mov_b32 s11, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mbcnt_lo_u32_b32 v11, s11, 0
	v_cmp_eq_u32_e32 vcc_lo, 0, v11
	s_and_b32 s12, exec_lo, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 exec_lo, s12
	s_cbranch_execz .LBB3_25
; %bb.24:                               ;   in Loop: Header=BB3_4 Depth=1
	s_bcnt1_i32_b32 s11, s11
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v11, s11
	global_atomic_add_u32 v23, v11, s[2:3]
.LBB3_25:                               ;   in Loop: Header=BB3_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	v_ashrrev_i32_e32 v11, 31, v10
	s_mov_b32 s11, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[14:15], 2, v[10:11]
	v_add_co_u32 v14, vcc_lo, s18, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v15, vcc_lo, s19, v15, vcc_lo
	v_add_co_u32 v17, vcc_lo, v14, s4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v18, vcc_lo, s5, v15, vcc_lo
	global_atomic_add_u32 v15, v[14:15], v16, off glc
	global_load_b32 v17, v[17:18], off
	s_waitcnt vmcnt(0)
	v_ashrrev_i32_e32 v18, 31, v17
	v_lshlrev_b64 v[17:18], 2, v[17:18]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v17, vcc_lo, s18, v17
	v_add_co_ci_u32_e32 v18, vcc_lo, s19, v18, vcc_lo
	global_atomic_add_u32 v[17:18], v22, off
	v_cmpx_ne_u32_e64 v10, v0
	s_cbranch_execz .LBB3_33
; %bb.26:                               ; %.lr.ph.i.preheader
                                        ;   in Loop: Header=BB3_4 Depth=1
	v_dual_mov_b32 v11, 3 :: v_dual_mov_b32 v14, v10
	s_mov_b32 s12, 0
.LBB3_27:                               ; %.lr.ph.i
                                        ;   Parent Loop BB3_4 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v17, v11, v4
	s_mov_b32 s0, exec_lo
	v_ashrrev_i32_e32 v18, 31, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[17:18], 2, v[17:18]
	v_add_co_u32 v19, vcc_lo, v12, v17
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v20, vcc_lo, v13, v18, vcc_lo
	v_add_co_u32 v33, vcc_lo, v1, v17
	v_add_co_ci_u32_e32 v34, vcc_lo, v2, v18, vcc_lo
	global_load_b32 v17, v[19:20], off
	global_load_b32 v18, v[33:34], off
	v_cmpx_eq_u32_e64 v15, v22
	s_cbranch_execz .LBB3_31
; %bb.28:                               ;   in Loop: Header=BB3_27 Depth=2
	s_waitcnt vmcnt(1)
	v_add_nc_u32_e32 v19, v17, v28
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v20, 31, v19
	v_lshlrev_b64 v[19:20], 2, v[19:20]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v19, vcc_lo, s16, v19
	v_add_co_ci_u32_e32 v20, vcc_lo, s17, v20, vcc_lo
	global_atomic_add_u32 v15, v[19:20], v26, off glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u32_e32 vcc_lo, 1, v15
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB3_31
; %bb.29:                               ;   in Loop: Header=BB3_27 Depth=2
	s_mov_b32 s13, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mbcnt_lo_u32_b32 v15, s13, 0
	v_cmp_eq_u32_e32 vcc_lo, 0, v15
	s_and_b32 s14, exec_lo, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 exec_lo, s14
	s_cbranch_execz .LBB3_31
; %bb.30:                               ;   in Loop: Header=BB3_27 Depth=2
	s_bcnt1_i32_b32 s13, s13
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v15, s13
	global_atomic_add_u32 v23, v15, s[2:3]
.LBB3_31:                               ;   in Loop: Header=BB3_27 Depth=2
	s_or_b32 exec_lo, exec_lo, s0
	v_add_nc_u32_e32 v14, v14, v4
	s_waitcnt vmcnt(0)
	v_cmp_ne_u32_e64 s0, v17, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v15, 31, v14
	v_cndmask_b32_e64 v11, 5, v11, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[14:15], 2, v[14:15]
	v_add_co_u32 v14, vcc_lo, s18, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v15, vcc_lo, s19, v15, vcc_lo
	global_load_b32 v14, v[14:15], off
	s_waitcnt vmcnt(0)
	v_ashrrev_i32_e32 v15, 31, v14
	v_lshlrev_b64 v[19:20], 2, v[14:15]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v19, vcc_lo, s18, v19
	v_add_co_ci_u32_e32 v20, vcc_lo, s19, v20, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v33, vcc_lo, v19, s4
	v_add_co_ci_u32_e32 v34, vcc_lo, s5, v20, vcc_lo
	global_atomic_add_u32 v15, v[19:20], v16, off glc
	global_load_b32 v19, v[33:34], off
	s_waitcnt vmcnt(0)
	v_ashrrev_i32_e32 v20, 31, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[19:20], 2, v[19:20]
	v_add_co_u32 v19, vcc_lo, s18, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
	v_add_co_ci_u32_e32 v20, vcc_lo, s19, v20, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, v14, v0
	global_atomic_add_u32 v[19:20], v22, off
	s_or_b32 s12, vcc_lo, s12
	s_and_not1_b32 exec_lo, exec_lo, s12
	s_cbranch_execnz .LBB3_27
; %bb.32:                               ; %Flow192
                                        ;   in Loop: Header=BB3_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s12
.LBB3_33:                               ; %Flow193
                                        ;   in Loop: Header=BB3_4 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s11
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e64 v15, v22
	s_cbranch_execz .LBB3_36
; %bb.34:                               ;   in Loop: Header=BB3_4 Depth=1
	s_mov_b32 s11, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mbcnt_lo_u32_b32 v11, s11, 0
	v_cmp_eq_u32_e32 vcc_lo, 0, v11
	s_and_b32 s12, exec_lo, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 exec_lo, s12
	s_cbranch_execz .LBB3_36
; %bb.35:                               ;   in Loop: Header=BB3_4 Depth=1
	s_bcnt1_i32_b32 s11, s11
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v11, s11
	global_atomic_add_u32 v23, v11, s[2:3]
.LBB3_36:                               ; %_Z6flow_tPiS_iiiiiiS_.exit
                                        ;   in Loop: Header=BB3_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s11, exec_lo
	s_mov_b32 s0, 0
.LBB3_37:                               ; %ComputeLoop
                                        ;   Parent Loop BB3_4 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_ctz_i32_b32 s12, s11
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_readlane_b32 s13, v22, s12
	s_lshl_b32 s12, 1, s12
	s_and_not1_b32 s11, s11, s12
	s_delay_alu instid0(VALU_DEP_1)
	s_add_i32 s0, s0, s13
	s_cmp_lg_u32 s11, 0
	s_cbranch_scc1 .LBB3_37
; %bb.38:                               ; %ComputeEnd
                                        ;   in Loop: Header=BB3_4 Depth=1
	v_mbcnt_lo_u32_b32 v11, exec_lo, 0
	s_mov_b32 s11, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v11
	s_xor_b32 s11, exec_lo, s11
	s_cbranch_execz .LBB3_40
; %bb.39:                               ;   in Loop: Header=BB3_4 Depth=1
	v_mov_b32_e32 v11, s0
	global_atomic_add_u32 v23, v11, s[30:31]
.LBB3_40:                               ; %Flow
                                        ;   in Loop: Header=BB3_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s11
	v_mov_b32_e32 v15, v10
	s_and_not1_b32 s9, s9, exec_lo
.LBB3_41:                               ; %Flow197
                                        ;   in Loop: Header=BB3_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_mov_b32_e32 v10, v15
	s_and_not1_b32 s0, s7, exec_lo
	s_and_b32 s7, s9, exec_lo
	s_or_b32 s7, s0, s7
.LBB3_42:                               ; %Flow198
                                        ;   in Loop: Header=BB3_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s0, s7, exec_lo
.LBB3_43:                               ; %Flow205
                                        ;   in Loop: Header=BB3_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s6
	s_xor_b32 s0, s0, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, exec_lo, s0
	s_or_b32 s1, s0, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s1
	s_cbranch_execnz .LBB3_4
.LBB3_44:                               ; %.loopexit104
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z6aug_cuPiS_S_S_S_S_S_S_S_S_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 344
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 36
		.amdhsa_next_free_sgpr 32
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end3:
	.size	_Z6aug_cuPiS_S_S_S_S_S_S_S_S_S_, .Lfunc_end3-_Z6aug_cuPiS_S_S_S_S_S_S_S_S_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 2332
; NumSgprs: 34
; NumVgprs: 36
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 4
; VGPRBlocks: 4
; NumSGPRsForWavesPerEU: 34
; NumVGPRsForWavesPerEU: 36
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z9flg_resetPi          ; -- Begin function _Z9flg_resetPi
	.globl	_Z9flg_resetPi
	.p2align	8
	.type	_Z9flg_resetPi,@function
_Z9flg_resetPi:                         ; @_Z9flg_resetPi
; %bb.0:
	s_load_b64 s[0:1], s[0:1], 0x0
	v_mov_b32_e32 v0, 0
	s_waitcnt lgkmcnt(0)
	global_store_b32 v0, v0, s[0:1]
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z9flg_resetPi
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 8
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 1
		.amdhsa_next_free_sgpr 2
		.amdhsa_reserve_vcc 0
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end4:
	.size	_Z9flg_resetPi, .Lfunc_end4-_Z9flg_resetPi
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 36
; NumSgprs: 2
; NumVgprs: 1
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 0
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 2
; NumVGPRsForWavesPerEU: 1
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
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amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
