#include "cuda_runtime.h"
#include "device_launch_parameters.h"

#include <stdio.h>

__global__ void radix(int *a, int *b, int n, int count){
	int id = threadIdx.x;
	int i=0, data=0, j=0, pos=0;
	int temp = a[id];
	
	while(j<=count){
		data=temp%10;
		temp/=10;
		j++;
	}

	for(i=0; i<n; i++){
		j=0;
		int data2, temp=a[i];
		while(j<=count){
			data2=temp%10;
			temp/=10;
			j++;
		}
		if(data2<data || (data2==data && i<id))
			pos++;
	}
	b[pos]=a[id];
}

int main(){
	//Standard input
	int A[]={170,450,750,900,802,240,200,660};
	int n=8;
	int i, k=3; //3 digit

	int size = sizeof(int)*n;

	int *d_a, *d_b;

	cudaMalloc((void**)&d_a,size);
	cudaMalloc((void**)&d_b,size);

	for(i=0; i<k; i++){
		cudaMemcpy(d_a,&A,size,cudaMemcpyHostToDevice);
		radix<<<1,n>>>(d_a,d_b,n,i);
		cudaMemcpy(&A,d_b,size,cudaMemcpyDeviceToHost);
	}

	for(i=0; i<8; i++)
		printf("\n%d",A[i]);

	cudaFree(d_a);
	cudaFree(d_b);

	getchar();

	return 0;

}
	.file	"tmpxft_00304c83_00000000-6_aman.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2030:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z28__device_stub__Z5radixPiS_iiPiS_ii
	.type	_Z28__device_stub__Z5radixPiS_iiPiS_ii, @function
_Z28__device_stub__Z5radixPiS_iiPiS_ii:
.LFB2052:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z5radixPiS_ii(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L2:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2052:
	.size	_Z28__device_stub__Z5radixPiS_iiPiS_ii, .-_Z28__device_stub__Z5radixPiS_iiPiS_ii
	.globl	_Z5radixPiS_ii
	.type	_Z5radixPiS_ii, @function
_Z5radixPiS_ii:
.LFB2053:
	.cfi_startproc
	endbr64
	jmp	_Z28__device_stub__Z5radixPiS_iiPiS_ii
	.cfi_endproc
.LFE2053:
	.size	_Z5radixPiS_ii, .-_Z5radixPiS_ii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"\n%d"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%r12
	.cfi_def_cfa_offset 16
	.cfi_offset 12, -16
	movl	$32, %esi
	movabsq	$4294967304, %r12
	pushq	%rbp
	.cfi_def_cfa_offset 24
	.cfi_offset 6, -24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset 3, -32
	xorl	%ebx, %ebx
	subq	$80, %rsp
	.cfi_def_cfa_offset 112
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	movabsq	$1932735283370, %rax
	movq	%rsp, %rdi
	movq	%rax, 40(%rsp)
	movabsq	$3865470567150, %rax
	movq	%rax, 48(%rsp)
	movabsq	$1030792151842, %rax
	movq	%rax, 56(%rsp)
	movabsq	$2834678415560, %rax
	movq	%rax, 64(%rsp)
	call	cudaMalloc@PLT
	leaq	8(%rsp), %rdi
	movl	$32, %esi
	call	cudaMalloc@PLT
.L10:
	movq	(%rsp), %rdi
	leaq	40(%rsp), %rbp
	movl	$1, %ecx
	movl	$32, %edx
	movq	%rbp, %rsi
	call	cudaMemcpy@PLT
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	%r12, %rdx
	movl	$1, %ecx
	movl	$1, %esi
	movabsq	$4294967297, %rdi
	movq	%r12, 28(%rsp)
	movl	$1, 36(%rsp)
	movq	%rdi, 16(%rsp)
	movl	$1, 24(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L9
	movq	8(%rsp), %rsi
	movq	(%rsp), %rdi
	movl	%ebx, %ecx
	movl	$8, %edx
	call	_Z28__device_stub__Z5radixPiS_iiPiS_ii
.L9:
	movq	8(%rsp), %rsi
	movl	$2, %ecx
	movq	%rbp, %rdi
	incl	%ebx
	movl	$32, %edx
	call	cudaMemcpy@PLT
	cmpl	$3, %ebx
	jne	.L10
	xorl	%ebx, %ebx
	leaq	.LC0(%rip), %r12
.L11:
	movl	0(%rbp,%rbx,4), %edx
	movq	%r12, %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	incq	%rbx
	call	__printf_chk@PLT
	cmpq	$8, %rbx
	jne	.L11
	movq	(%rsp), %rdi
	call	cudaFree@PLT
	movq	8(%rsp), %rdi
	call	cudaFree@PLT
	call	getchar@PLT
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L12
	call	__stack_chk_fail@PLT
.L12:
	addq	$80, %rsp
	.cfi_def_cfa_offset 32
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2027:
	.size	main, .-main
	.section	.rodata.str1.1
.LC1:
	.string	"_Z5radixPiS_ii"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC1(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z5radixPiS_ii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2055:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include "hip/hip_runtime.h"


#include <stdio.h>

__global__ void radix(int *a, int *b, int n, int count){
	int id = threadIdx.x;
	int i=0, data=0, j=0, pos=0;
	int temp = a[id];
	
	while(j<=count){
		data=temp%10;
		temp/=10;
		j++;
	}

	for(i=0; i<n; i++){
		j=0;
		int data2, temp=a[i];
		while(j<=count){
			data2=temp%10;
			temp/=10;
			j++;
		}
		if(data2<data || (data2==data && i<id))
			pos++;
	}
	b[pos]=a[id];
}

int main(){
	//Standard input
	int A[]={170,450,750,900,802,240,200,660};
	int n=8;
	int i, k=3; //3 digit

	int size = sizeof(int)*n;

	int *d_a, *d_b;

	hipMalloc((void**)&d_a,size);
	hipMalloc((void**)&d_b,size);

	for(i=0; i<k; i++){
		hipMemcpy(d_a,&A,size,hipMemcpyHostToDevice);
		radix<<<1,n>>>(d_a,d_b,n,i);
		hipMemcpy(&A,d_b,size,hipMemcpyDeviceToHost);
	}

	for(i=0; i<8; i++)
		printf("\n%d",A[i]);

	hipFree(d_a);
	hipFree(d_b);

	getchar();

	return 0;

}
	.text
	.file	"aman.hip"
	.globl	_Z20__device_stub__radixPiS_ii  # -- Begin function _Z20__device_stub__radixPiS_ii
	.type	_Z20__device_stub__radixPiS_ii,@function
_Z20__device_stub__radixPiS_ii:         # @_Z20__device_stub__radixPiS_ii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z5radixPiS_ii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z20__device_stub__radixPiS_ii, .Lfunc_end0-_Z20__device_stub__radixPiS_ii
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst16,"aM",@progbits,16
	.p2align	4, 0x0                          # -- Begin function main
.LCPI1_0:
	.long	170                             # 0xaa
	.long	450                             # 0x1c2
	.long	750                             # 0x2ee
	.long	900                             # 0x384
.LCPI1_1:
	.long	802                             # 0x322
	.long	240                             # 0xf0
	.long	200                             # 0xc8
	.long	660                             # 0x294
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r12
	.cfi_def_cfa_offset 32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	subq	$56, %rsp
	.cfi_def_cfa_offset 96
	.cfi_offset %rbx, -40
	.cfi_offset %r12, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movabsq	$4294967297, %rbx               # imm = 0x100000001
	movaps	.LCPI1_0(%rip), %xmm0           # xmm0 = [170,450,750,900]
	leaq	16(%rsp), %r14
	movaps	%xmm0, (%r14)
	movaps	.LCPI1_1(%rip), %xmm0           # xmm0 = [802,240,200,660]
	movaps	%xmm0, 16(%r14)
	leaq	8(%rsp), %rdi
	movl	$32, %esi
	callq	hipMalloc
	movq	%rsp, %rdi
	movl	$32, %esi
	callq	hipMalloc
	xorl	%r15d, %r15d
	leaq	7(%rbx), %r12
.LBB1_1:                                # =>This Inner Loop Header: Depth=1
	movq	8(%rsp), %rdi
	movl	$32, %edx
	movq	%r14, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	%rbx, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_3
# %bb.2:                                #   in Loop: Header=BB1_1 Depth=1
	movq	8(%rsp), %rdi
	movq	(%rsp), %rsi
	movl	$8, %edx
	movl	%r15d, %ecx
	callq	_Z20__device_stub__radixPiS_ii
.LBB1_3:                                #   in Loop: Header=BB1_1 Depth=1
	movq	(%rsp), %rsi
	movl	$32, %edx
	movq	%r14, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	incl	%r15d
	cmpl	$3, %r15d
	jne	.LBB1_1
# %bb.4:                                # %.preheader.preheader
	xorl	%ebx, %ebx
.LBB1_5:                                # %.preheader
                                        # =>This Inner Loop Header: Depth=1
	movl	16(%rsp,%rbx,4), %esi
	movl	$.L.str, %edi
	xorl	%eax, %eax
	callq	printf
	incq	%rbx
	cmpq	$8, %rbx
	jne	.LBB1_5
# %bb.6:
	movq	8(%rsp), %rdi
	callq	hipFree
	movq	(%rsp), %rdi
	callq	hipFree
	callq	getchar
	xorl	%eax, %eax
	addq	$56, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	main, .Lfunc_end1-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z5radixPiS_ii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z5radixPiS_ii,@object          # @_Z5radixPiS_ii
	.section	.rodata,"a",@progbits
	.globl	_Z5radixPiS_ii
	.p2align	3, 0x0
_Z5radixPiS_ii:
	.quad	_Z20__device_stub__radixPiS_ii
	.size	_Z5radixPiS_ii, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"\n%d"
	.size	.L.str, 4

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z5radixPiS_ii"
	.size	.L__unnamed_1, 15

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z20__device_stub__radixPiS_ii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z5radixPiS_ii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z5radixPiS_ii          ; -- Begin function _Z5radixPiS_ii
	.globl	_Z5radixPiS_ii
	.p2align	8
	.type	_Z5radixPiS_ii,@function
_Z5radixPiS_ii:                         ; @_Z5radixPiS_ii
; %bb.0:
	s_clause 0x1
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b64 s[2:3], s[0:1], 0x10
	v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v1, 2, v0
	s_waitcnt lgkmcnt(0)
	global_load_b32 v3, v1, s[4:5]
	s_cmp_gt_i32 s3, -1
	s_cselect_b32 s1, -1, 0
	s_cmp_lt_i32 s3, 0
	s_cbranch_scc1 .LBB0_4
; %bb.1:                                ; %.lr.ph.preheader
	s_waitcnt vmcnt(0)
	v_mov_b32_e32 v2, v3
	s_add_i32 s0, s3, 1
.LBB0_2:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_mov_b32_e32 v1, v2
	s_add_i32 s0, s0, -1
	s_cmp_eq_u32 s0, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_i32 v2, 0x66666667, v1
	v_lshrrev_b32_e32 v4, 31, v2
	v_ashrrev_i32_e32 v2, 2, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_add_nc_u32_e32 v2, v2, v4
	s_cbranch_scc0 .LBB0_2
; %bb.3:
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v2, v2, 10
	v_sub_nc_u32_e32 v2, v1, v2
.LBB0_4:                                ; %.preheader
	s_cmp_lt_i32 s2, 1
	s_cbranch_scc1 .LBB0_16
; %bb.5:                                ; %.lr.ph50.preheader
	v_mov_b32_e32 v1, 0
	s_mov_b32 s9, 0
	s_add_i32 s3, s3, 1
	s_mov_b32 s8, s9
                                        ; implicit-def: $sgpr10
.LBB0_6:                                ; %.lr.ph50
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_8 Depth 2
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB0_10
; %bb.7:                                ; %.lr.ph45.preheader
                                        ;   in Loop: Header=BB0_6 Depth=1
	s_lshl_b64 s[10:11], s[8:9], 2
	s_mov_b32 s0, s3
	s_add_u32 s10, s4, s10
	s_addc_u32 s11, s5, s11
	s_load_b32 s11, s[10:11], 0x0
.LBB0_8:                                ; %.lr.ph45
                                        ;   Parent Loop BB0_6 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_waitcnt lgkmcnt(0)
	s_mov_b32 s10, s11
	s_mul_hi_i32 s11, s11, 0x66666667
	s_add_i32 s0, s0, -1
	s_lshr_b32 s12, s11, 31
	s_ashr_i32 s11, s11, 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_i32 s11, s11, s12
	s_cmp_lg_u32 s0, 0
	s_cbranch_scc1 .LBB0_8
; %bb.9:                                ; %._crit_edge
                                        ;   in Loop: Header=BB0_6 Depth=1
	s_mul_i32 s0, s11, 10
	s_delay_alu instid0(SALU_CYCLE_1)
	s_sub_i32 s10, s10, s0
.LBB0_10:                               ;   in Loop: Header=BB0_6 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	v_cmp_lt_i32_e64 s11, s10, v2
	s_mov_b32 s12, exec_lo
	v_cmpx_ge_i32_e64 s10, v2
; %bb.11:                               ;   in Loop: Header=BB0_6 Depth=1
	v_cmp_eq_u32_e32 vcc_lo, s10, v2
	v_cmp_lt_u32_e64 s0, s8, v0
	s_and_not1_b32 s11, s11, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, s0, vcc_lo
	s_and_b32 s0, s0, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s11, s11, s0
; %bb.12:                               ; %Flow
                                        ;   in Loop: Header=BB0_6 Depth=1
	s_or_b32 exec_lo, exec_lo, s12
	s_and_saveexec_b32 s0, s11
; %bb.13:                               ;   in Loop: Header=BB0_6 Depth=1
	v_add_nc_u32_e32 v1, 1, v1
; %bb.14:                               ;   in Loop: Header=BB0_6 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	s_add_i32 s8, s8, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u32 s8, s2
	s_cbranch_scc1 .LBB0_6
; %bb.15:                               ; %._crit_edge51.loopexit
	v_ashrrev_i32_e32 v2, 31, v1
	s_branch .LBB0_17
.LBB0_16:
	v_mov_b32_e32 v1, 0
	v_mov_b32_e32 v2, 0
.LBB0_17:                               ; %._crit_edge51
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	v_add_co_u32 v0, vcc_lo, s6, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b32 v[0:1], v3, off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z5radixPiS_ii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 24
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 5
		.amdhsa_next_free_sgpr 13
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z5radixPiS_ii, .Lfunc_end0-_Z5radixPiS_ii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 408
; NumSgprs: 15
; NumVgprs: 5
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 1
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 15
; NumVGPRsForWavesPerEU: 5
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 24
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z5radixPiS_ii
    .private_segment_fixed_size: 0
    .sgpr_count:     15
    .sgpr_spill_count: 0
    .symbol:         _Z5radixPiS_ii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     5
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
