// counting Hamilton cycle, CUDA acceleration
#include<stdio.h>
#include<stdlib.h>
#define MAX_BLOCK_SIZE 1024
#define MAX_ARRAY_SIZE (1024*8)

// any 2 <= mod <= 2^31 should work
__host__ __device__ unsigned mod_sum(unsigned a, unsigned b, unsigned mod) {
    unsigned c = a+b;
    return c >= mod ? c-mod : c;
}

__global__ void ha2(int n, int work, unsigned *part, int *adj, unsigned *ret, unsigned int mod) {
    __shared__ unsigned qc[1024];
    __shared__ unsigned ai[32];
    int k = blockDim.x;
    int tid = threadIdx.x;
    int sha = threadIdx.y * k;
    int bid = threadIdx.y + blockIdx.x * blockDim.y;
    int gridSize = blockDim.y * gridDim.x;
    unsigned s = part[bid];
    unsigned mask = (1u<<k) - 1;
    unsigned total = 0;

    for (int i = tid+sha; i < n; i += blockDim.y * k) {
        unsigned aa = 0;
        for (int j = 0; j < n; j++) {
            aa = aa | adj[i * n + j] << j;
        }
        ai[i] = aa;
    }
    __syncthreads();

    for (int runs = 0; runs < work; runs += gridSize) {
        // first transition
        unsigned row = s;
        for (int i = 0; i < tid; i++) {
            row = row & (row-1);
        }
        unsigned at = __ffs(row)-1;
        row = 0;
        {
            unsigned me = ai[at];
            for (int i = n-2; i >= 0; i--) {
                if (s>>i & 1) {
                    row = row + row + (me>>i & 1);
                }
            }
            qc[tid+sha] = (me >> (n-1)) & 1;
            __syncthreads();
        }

        // calculate each transition, uses GPU SIMD feature
        for (int t = 1; t < n-1; t++) {
            unsigned sum = 0;
            for (int i = 0; i < k; i++) {
                sum = mod_sum(sum, qc[i+sha] * (row>>i & 1), mod);
            }
            __syncthreads();
            qc[tid+sha] = sum;
            __syncthreads();
        }

        // last transition
        {
            if (!(ai[n-1] >> at & 1)) qc[tid+sha] = 0;
            __syncthreads();
            unsigned count = 0;
            for (int i = 0; i < k; i++) {
                count = mod_sum(count, qc[i+sha], mod);
            }
            //if (tid==0) printf("[%d:%d],", s, count);
            if (runs + bid < work) {
                total = mod_sum(count, total, mod);
            }
        }
        unsigned bit = s & (-s);
        s += bit;
        s |= mask >> __popc(s);
        __syncthreads();
    }
    if (tid == 0) {
        // output total for this block
        ret[bid] = total;
    }
}

int n;
int adj[1024];
unsigned part[MAX_ARRAY_SIZE];
unsigned ret[MAX_ARRAY_SIZE];
int nCr[33][33];

unsigned getComb(int idx, int n, int r) {
    unsigned ans = 0;
    n -= 1;
    while (r > 0) {
        if (idx < nCr[n][r]) n -= 1;
        else {
            ans |= 1u<<(n);
            idx -= nCr[n][r];
            n -= 1;
            r -= 1;
        }
    }
    return ans;
}

int main() {
    int *gpu_adj;
    unsigned *gpu_part, *gpu_ret;
    scanf("%d", &n);
    for (int i = 0; i < n; i++) {
        for (int j = 0; j < n; j++) {
            if (i != j) adj[i*n+j] = rand()>>5&1;
        }
    }
    for (int i = 0; i < n; i++) {
        for (int j = 0; j < n; j++) scanf("%d", &adj[i*n+j]);
    }
    for (int i = 0; i <= 32; i++) {
        nCr[i][0] = nCr[i][i] = 1;
        for (int j = 1; j < i; j++) nCr[i][j] = nCr[i-1][j-1] + nCr[i-1][j];
    }
    cudaMalloc(&gpu_part, sizeof part);
    cudaMalloc(&gpu_adj, sizeof adj);
    cudaMalloc(&gpu_ret, sizeof ret);

    cudaMemcpy(gpu_adj, adj, sizeof adj, cudaMemcpyHostToDevice);
    unsigned ans = 0;
    unsigned mod = 0;
    for (int k = 1; k <= n-1; k++) {
        int wo = nCr[n-1][k];
        int blockSize = wo;
        if (blockSize > MAX_BLOCK_SIZE / k) blockSize = MAX_BLOCK_SIZE / k;
        int gridSize = wo / blockSize;
        if (blockSize * gridSize > MAX_ARRAY_SIZE) gridSize = MAX_ARRAY_SIZE / blockSize;
        int totSize = blockSize * gridSize;
        printf("block size = (%d,%d,1) grid size = (%d,1,1)\n", k, blockSize, gridSize);

        //for (int j = 0; j < wo; j++) printf("%d,", getComb(j, n-1, k));

        for (int j = 0; j < totSize; j++) {
            int step = wo / totSize * j;
            if (j < wo % totSize) step += j;
            else step += wo % totSize;
            //printf("step=%d\n", step);
            part[j] = getComb(step, n-1, k);
        }
        cudaMemcpy(gpu_part, part, sizeof(int) * totSize, cudaMemcpyHostToDevice);
        ha2<<<gridSize, dim3(k, blockSize)>>>(n, wo, gpu_part, gpu_adj, gpu_ret, mod);
        cudaDeviceSynchronize();
        cudaMemcpy(ret, gpu_ret, sizeof(int) * totSize, cudaMemcpyDeviceToHost);
        unsigned sum = 0;
        for (int j = 0; j < totSize; j++) {
            sum = mod_sum(sum, ret[j], 0);
        }
        printf("sum = %u\n", sum);
        if ((n-k)%2 == 1) ans = mod_sum(ans, sum, mod);
        else if (sum != 0) ans = mod_sum(ans, mod-sum, mod);
    }
    printf("ans = %u\n", ans);
    cudaFree(gpu_ret);
    cudaFree(gpu_adj);
    cudaFree(gpu_part);
}

	.file	"tmpxft_00329fb6_00000000-6_ha2.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2032:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2032:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z7mod_sumjjj
	.type	_Z7mod_sumjjj, @function
_Z7mod_sumjjj:
.LFB2027:
	.cfi_startproc
	endbr64
	leal	(%rdi,%rsi), %eax
	cmpl	%edx, %eax
	jb	.L2
	subl	%edx, %eax
.L2:
	ret
	.cfi_endproc
.LFE2027:
	.size	_Z7mod_sumjjj, .-_Z7mod_sumjjj
	.globl	_Z7getCombiii
	.type	_Z7getCombiii, @function
_Z7getCombiii:
.LFB2028:
	.cfi_startproc
	endbr64
	leal	-1(%rsi), %ecx
	movl	%edx, %eax
	xorl	%esi, %esi
	movl	$1, %r10d
	leaq	nCr(%rip), %r9
.L6:
	testl	%eax, %eax
	jle	.L9
	movslq	%ecx, %rdx
	movslq	%eax, %r8
	imulq	$33, %rdx, %rdx
	addq	%r8, %rdx
	leal	-1(%rcx), %r8d
	movl	(%r9,%rdx,4), %edx
	cmpl	%edi, %edx
	jg	.L7
	movl	%r10d, %r11d
	subl	%edx, %edi
	decl	%eax
	sall	%cl, %r11d
	orl	%r11d, %esi
.L7:
	movl	%r8d, %ecx
	jmp	.L6
.L9:
	movl	%esi, %eax
	ret
	.cfi_endproc
.LFE2028:
	.size	_Z7getCombiii, .-_Z7getCombiii
	.globl	_Z29__device_stub__Z3ha2iiPjPiS_jiiPjPiS_j
	.type	_Z29__device_stub__Z3ha2iiPjPiS_jiiPjPiS_j, @function
_Z29__device_stub__Z3ha2iiPjPiS_jiiPjPiS_j:
.LFB2054:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movl	%edi, 44(%rsp)
	leaq	72(%rsp), %rdi
	movl	%esi, 40(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 32(%rsp)
	leaq	56(%rsp), %rdx
	movq	%rcx, 24(%rsp)
	leaq	64(%rsp), %rcx
	movq	%r8, 16(%rsp)
	movl	%r9d, 12(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	44(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L10
	pushq	64(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z3ha2iiPjPiS_j(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 208
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L10:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L12
	call	__stack_chk_fail@PLT
.L12:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2054:
	.size	_Z29__device_stub__Z3ha2iiPjPiS_jiiPjPiS_j, .-_Z29__device_stub__Z3ha2iiPjPiS_jiiPjPiS_j
	.globl	_Z3ha2iiPjPiS_j
	.type	_Z3ha2iiPjPiS_j, @function
_Z3ha2iiPjPiS_j:
.LFB2055:
	.cfi_startproc
	endbr64
	jmp	_Z29__device_stub__Z3ha2iiPjPiS_jiiPjPiS_j
	.cfi_endproc
.LFE2055:
	.size	_Z3ha2iiPjPiS_j, .-_Z3ha2iiPjPiS_j
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"%d"
.LC1:
	.string	"block size = (%d,%d,1) grid size = (%d,1,1)\n"
.LC2:
	.string	"sum = %u\n"
.LC3:
	.string	"ans = %u\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2029:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	leaq	n(%rip), %rsi
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	leaq	adj(%rip), %r13
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	leaq	.LC0(%rip), %rbp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movq	%rbp, %rdi
	xorl	%ebx, %ebx
	subq	$88, %rsp
	.cfi_def_cfa_offset 144
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	xorl	%eax, %eax
	call	__isoc23_scanf@PLT
.L16:
	cmpl	%ebx, n(%rip)
	jle	.L43
	xorl	%r12d, %r12d
.L19:
	cmpl	%r12d, n(%rip)
	jle	.L44
	cmpl	%r12d, %ebx
	je	.L17
	call	rand@PLT
	movl	n(%rip), %edx
	sarl	$5, %eax
	imull	%ebx, %edx
	andl	$1, %eax
	addl	%r12d, %edx
	movslq	%edx, %rdx
	movl	%eax, 0(%r13,%rdx,4)
.L17:
	incl	%r12d
	jmp	.L19
.L44:
	incl	%ebx
	jmp	.L16
.L43:
	xorl	%ebx, %ebx
	leaq	adj(%rip), %r13
.L20:
	cmpl	%ebx, n(%rip)
	jle	.L45
	xorl	%r12d, %r12d
.L22:
	movl	n(%rip), %eax
	cmpl	%r12d, %eax
	jle	.L46
	imull	%ebx, %eax
	movq	%rbp, %rdi
	addl	%r12d, %eax
	incl	%r12d
	cltq
	leaq	0(%r13,%rax,4), %rsi
	xorl	%eax, %eax
	call	__isoc23_scanf@PLT
	jmp	.L22
.L46:
	incl	%ebx
	jmp	.L20
.L45:
	leaq	nCr(%rip), %rax
	xorl	%ecx, %ecx
	movq	%rax, %rsi
.L25:
	movl	$1, (%rax)
	movq	%rsi, %rdx
	movl	$1, %edi
	movl	$1, (%rsi)
.L23:
	addq	$4, %rdx
	cmpl	%edi, %ecx
	jle	.L47
	movl	-132(%rdx), %r8d
	addl	-136(%rdx), %r8d
	incl	%edi
	movl	%r8d, (%rdx)
	jmp	.L23
.L47:
	incl	%ecx
	addq	$136, %rax
	addq	$132, %rsi
	cmpl	$33, %ecx
	jne	.L25
	leaq	32(%rsp), %rdi
	movl	$32768, %esi
	movl	$1, %ebp
	xorl	%r14d, %r14d
	call	cudaMalloc@PLT
	leaq	24(%rsp), %rdi
	movl	$4096, %esi
	call	cudaMalloc@PLT
	leaq	40(%rsp), %rdi
	movl	$32768, %esi
	call	cudaMalloc@PLT
	movq	24(%rsp), %rdi
	movl	$1, %ecx
	movl	$4096, %edx
	leaq	adj(%rip), %rsi
	call	cudaMemcpy@PLT
.L26:
	movl	n(%rip), %eax
	cmpl	%ebp, %eax
	jle	.L48
	decl	%eax
	movslq	%ebp, %rdx
	leaq	nCr(%rip), %rcx
	cltq
	imulq	$33, %rax, %rax
	addq	%rdx, %rax
	movl	(%rcx,%rax,4), %r13d
	movl	$1024, %eax
	cltd
	idivl	%ebp
	cmpl	%r13d, %eax
	cmovg	%r13d, %eax
	movl	%eax, %ebx
	movl	%r13d, %eax
	cltd
	idivl	%ebx
	movl	%eax, %r12d
	imull	%ebx, %eax
	cmpl	$8192, %eax
	jle	.L27
	movl	$8192, %eax
	cltd
	idivl	%ebx
	movl	%eax, %r12d
.L27:
	movl	%r12d, %r8d
	movl	%ebx, %ecx
	movl	%ebp, %edx
	movl	$2, %edi
	leaq	.LC1(%rip), %rsi
	xorl	%eax, %eax
	movl	%r12d, %r15d
	call	__printf_chk@PLT
	movl	n(%rip), %eax
	imull	%ebx, %r15d
	xorl	%ecx, %ecx
	leaq	part(%rip), %r8
	decl	%eax
	movl	%eax, (%rsp)
.L28:
	movl	%ecx, %esi
	cmpl	%ecx, %r15d
	jle	.L49
	movl	%r13d, %eax
	cltd
	idivl	%r15d
	imull	%ecx, %eax
	leal	(%rdx,%rax), %edi
	cmpl	%ecx, %edx
	jle	.L30
	leal	(%rsi,%rax), %edi
.L30:
	movl	(%rsp), %esi
	movl	%ebp, %edx
	movq	%rcx, 8(%rsp)
	call	_Z7getCombiii
	movq	8(%rsp), %rcx
	leaq	part(%rip), %r8
	movl	%eax, (%r8,%rcx,4)
	incq	%rcx
	jmp	.L28
.L49:
	movslq	%r15d, %rax
	movq	32(%rsp), %rdi
	movq	%r8, %rsi
	movl	$1, %ecx
	salq	$2, %rax
	movq	%rax, %rdx
	movq	%rax, (%rsp)
	call	cudaMemcpy@PLT
	movl	%ebp, 48(%rsp)
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movabsq	$4294967297, %rax
	movl	%ebx, 52(%rsp)
	movq	48(%rsp), %rdx
	movl	$1, %ecx
	movq	%rax, 64(%rsp)
	movl	68(%rsp), %esi
	movl	%r12d, 60(%rsp)
	movq	60(%rsp), %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L32
	movq	40(%rsp), %r8
	movq	24(%rsp), %rcx
	xorl	%r9d, %r9d
	movl	%r13d, %esi
	movq	32(%rsp), %rdx
	movl	n(%rip), %edi
	call	_Z29__device_stub__Z3ha2iiPjPiS_jiiPjPiS_j
.L32:
	call	cudaDeviceSynchronize@PLT
	movq	(%rsp), %rdx
	movq	40(%rsp), %rsi
	xorl	%ebx, %ebx
	leaq	ret(%rip), %r12
	movl	$2, %ecx
	movq	%r12, %rdi
	call	cudaMemcpy@PLT
	xorl	%eax, %eax
.L33:
	cmpl	%eax, %r15d
	jle	.L50
	addl	(%r12,%rax,4), %ebx
	incq	%rax
	jmp	.L33
.L50:
	movl	%ebx, %edx
	xorl	%eax, %eax
	leaq	.LC2(%rip), %rsi
	movl	$2, %edi
	call	__printf_chk@PLT
	movl	n(%rip), %eax
	movl	$2, %ecx
	subl	%ebp, %eax
	cltd
	idivl	%ecx
	decl	%edx
	jne	.L35
	addl	%ebx, %r14d
	jmp	.L36
.L35:
	subl	%ebx, %r14d
.L36:
	incl	%ebp
	jmp	.L26
.L48:
	movl	%r14d, %edx
	leaq	.LC3(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movq	40(%rsp), %rdi
	call	cudaFree@PLT
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	movq	32(%rsp), %rdi
	call	cudaFree@PLT
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L38
	call	__stack_chk_fail@PLT
.L38:
	addq	$88, %rsp
	.cfi_def_cfa_offset 56
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2029:
	.size	main, .-main
	.section	.rodata.str1.1
.LC4:
	.string	"_Z3ha2iiPjPiS_j"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2057:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC4(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z3ha2iiPjPiS_j(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2057:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.globl	nCr
	.bss
	.align 32
	.type	nCr, @object
	.size	nCr, 4356
nCr:
	.zero	4356
	.globl	ret
	.align 32
	.type	ret, @object
	.size	ret, 32768
ret:
	.zero	32768
	.globl	part
	.align 32
	.type	part, @object
	.size	part, 32768
part:
	.zero	32768
	.globl	adj
	.align 32
	.type	adj, @object
	.size	adj, 4096
adj:
	.zero	4096
	.globl	n
	.align 4
	.type	n, @object
	.size	n, 4
n:
	.zero	4
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

// counting Hamilton cycle, CUDA acceleration

#include <hip/hip_runtime.h>
#include<stdio.h>
#include<stdlib.h>
#define MAX_BLOCK_SIZE 1024
#define MAX_ARRAY_SIZE (1024*8)

// any 2 <= mod <= 2^31 should work
__host__ __device__ unsigned mod_sum(unsigned a, unsigned b, unsigned mod) {
    unsigned c = a+b;
    return c >= mod ? c-mod : c;
}

__global__ void ha2(int n, int work, unsigned *part, int *adj, unsigned *ret, unsigned int mod) {
    __shared__ unsigned qc[1024];
    __shared__ unsigned ai[32];
    int k = blockDim.x;
    int tid = threadIdx.x;
    int sha = threadIdx.y * k;
    int bid = threadIdx.y + blockIdx.x * blockDim.y;
    int gridSize = blockDim.y * gridDim.x;
    unsigned s = part[bid];
    unsigned mask = (1u<<k) - 1;
    unsigned total = 0;

    for (int i = tid+sha; i < n; i += blockDim.y * k) {
        unsigned aa = 0;
        for (int j = 0; j < n; j++) {
            aa = aa | adj[i * n + j] << j;
        }
        ai[i] = aa;
    }
    __syncthreads();

    for (int runs = 0; runs < work; runs += gridSize) {
        // first transition
        unsigned row = s;
        for (int i = 0; i < tid; i++) {
            row = row & (row-1);
        }
        unsigned at = __ffs(row)-1;
        row = 0;
        {
            unsigned me = ai[at];
            for (int i = n-2; i >= 0; i--) {
                if (s>>i & 1) {
                    row = row + row + (me>>i & 1);
                }
            }
            qc[tid+sha] = (me >> (n-1)) & 1;
            __syncthreads();
        }

        // calculate each transition, uses GPU SIMD feature
        for (int t = 1; t < n-1; t++) {
            unsigned sum = 0;
            for (int i = 0; i < k; i++) {
                sum = mod_sum(sum, qc[i+sha] * (row>>i & 1), mod);
            }
            __syncthreads();
            qc[tid+sha] = sum;
            __syncthreads();
        }

        // last transition
        {
            if (!(ai[n-1] >> at & 1)) qc[tid+sha] = 0;
            __syncthreads();
            unsigned count = 0;
            for (int i = 0; i < k; i++) {
                count = mod_sum(count, qc[i+sha], mod);
            }
            //if (tid==0) printf("[%d:%d],", s, count);
            if (runs + bid < work) {
                total = mod_sum(count, total, mod);
            }
        }
        unsigned bit = s & (-s);
        s += bit;
        s |= mask >> __popc(s);
        __syncthreads();
    }
    if (tid == 0) {
        // output total for this block
        ret[bid] = total;
    }
}

int n;
int adj[1024];
unsigned part[MAX_ARRAY_SIZE];
unsigned ret[MAX_ARRAY_SIZE];
int nCr[33][33];

unsigned getComb(int idx, int n, int r) {
    unsigned ans = 0;
    n -= 1;
    while (r > 0) {
        if (idx < nCr[n][r]) n -= 1;
        else {
            ans |= 1u<<(n);
            idx -= nCr[n][r];
            n -= 1;
            r -= 1;
        }
    }
    return ans;
}

int main() {
    int *gpu_adj;
    unsigned *gpu_part, *gpu_ret;
    scanf("%d", &n);
    for (int i = 0; i < n; i++) {
        for (int j = 0; j < n; j++) {
            if (i != j) adj[i*n+j] = rand()>>5&1;
        }
    }
    for (int i = 0; i < n; i++) {
        for (int j = 0; j < n; j++) scanf("%d", &adj[i*n+j]);
    }
    for (int i = 0; i <= 32; i++) {
        nCr[i][0] = nCr[i][i] = 1;
        for (int j = 1; j < i; j++) nCr[i][j] = nCr[i-1][j-1] + nCr[i-1][j];
    }
    hipMalloc(&gpu_part, sizeof part);
    hipMalloc(&gpu_adj, sizeof adj);
    hipMalloc(&gpu_ret, sizeof ret);

    hipMemcpy(gpu_adj, adj, sizeof adj, hipMemcpyHostToDevice);
    unsigned ans = 0;
    unsigned mod = 0;
    for (int k = 1; k <= n-1; k++) {
        int wo = nCr[n-1][k];
        int blockSize = wo;
        if (blockSize > MAX_BLOCK_SIZE / k) blockSize = MAX_BLOCK_SIZE / k;
        int gridSize = wo / blockSize;
        if (blockSize * gridSize > MAX_ARRAY_SIZE) gridSize = MAX_ARRAY_SIZE / blockSize;
        int totSize = blockSize * gridSize;
        printf("block size = (%d,%d,1) grid size = (%d,1,1)\n", k, blockSize, gridSize);

        //for (int j = 0; j < wo; j++) printf("%d,", getComb(j, n-1, k));

        for (int j = 0; j < totSize; j++) {
            int step = wo / totSize * j;
            if (j < wo % totSize) step += j;
            else step += wo % totSize;
            //printf("step=%d\n", step);
            part[j] = getComb(step, n-1, k);
        }
        hipMemcpy(gpu_part, part, sizeof(int) * totSize, hipMemcpyHostToDevice);
        ha2<<<gridSize, dim3(k, blockSize)>>>(n, wo, gpu_part, gpu_adj, gpu_ret, mod);
        hipDeviceSynchronize();
        hipMemcpy(ret, gpu_ret, sizeof(int) * totSize, hipMemcpyDeviceToHost);
        unsigned sum = 0;
        for (int j = 0; j < totSize; j++) {
            sum = mod_sum(sum, ret[j], 0);
        }
        printf("sum = %u\n", sum);
        if ((n-k)%2 == 1) ans = mod_sum(ans, sum, mod);
        else if (sum != 0) ans = mod_sum(ans, mod-sum, mod);
    }
    printf("ans = %u\n", ans);
    hipFree(gpu_ret);
    hipFree(gpu_adj);
    hipFree(gpu_part);
}

	.text
	.file	"ha2.hip"
	.globl	_Z7mod_sumjjj                   # -- Begin function _Z7mod_sumjjj
	.type	_Z7mod_sumjjj,@function
_Z7mod_sumjjj:                          # @_Z7mod_sumjjj
	.cfi_startproc
# %bb.0:
                                        # kill: def $esi killed $esi def $rsi
                                        # kill: def $edi killed $edi def $rdi
	leal	(%rdi,%rsi), %eax
	xorl	%ecx, %ecx
	cmpl	%edx, %eax
	cmovael	%edx, %ecx
	subl	%ecx, %eax
	retq
.Lfunc_end0:
	.size	_Z7mod_sumjjj, .Lfunc_end0-_Z7mod_sumjjj
	.cfi_endproc
                                        # -- End function
	.globl	_Z18__device_stub__ha2iiPjPiS_j # -- Begin function _Z18__device_stub__ha2iiPjPiS_j
	.type	_Z18__device_stub__ha2iiPjPiS_j,@function
_Z18__device_stub__ha2iiPjPiS_j:        # @_Z18__device_stub__ha2iiPjPiS_j
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	20(%rsp), %rax
	movl	%edi, (%rax)
	leaq	16(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	56(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	48(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	40(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	12(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z3ha2iiPjPiS_j, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z18__device_stub__ha2iiPjPiS_j, .Lfunc_end1-_Z18__device_stub__ha2iiPjPiS_j
	.cfi_endproc
                                        # -- End function
	.globl	_Z7getCombiii                   # -- Begin function _Z7getCombiii
	.type	_Z7getCombiii,@function
_Z7getCombiii:                          # @_Z7getCombiii
	.cfi_startproc
# %bb.0:
	testl	%edx, %edx
	jle	.LBB2_1
# %bb.3:                                # %select.unfold.lr.ph.preheader
	movl	%edx, %edx
	leaq	nCr-132(,%rdx,4), %rcx
	xorl	%eax, %eax
.LBB2_5:                                # %select.unfold.lr.ph
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB2_6 Depth 2
	movl	%edi, %r8d
	movslq	%esi, %rdi
	movq	%rdi, %r9
	shlq	$7, %r9
	leaq	(%r9,%rdi,4), %r9
	addq	%rcx, %r9
.LBB2_6:                                # %select.unfold
                                        #   Parent Loop BB2_5 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	decl	%esi
	leaq	-132(%r9), %r10
	movl	%r8d, %edi
	subl	(%r9), %edi
	movq	%r10, %r9
	jl	.LBB2_6
# %bb.4:                                # %.outer.loopexit
                                        #   in Loop: Header=BB2_5 Depth=1
	btsl	%esi, %eax
	leaq	-1(%rdx), %r8
	addq	$-4, %rcx
	cmpq	$2, %rdx
	movq	%r8, %rdx
	jge	.LBB2_5
# %bb.2:                                # %.outer._crit_edge
	retq
.LBB2_1:
	xorl	%eax, %eax
	retq
.Lfunc_end2:
	.size	_Z7getCombiii, .Lfunc_end2-_Z7getCombiii
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$56, %rsp
	.cfi_def_cfa_offset 112
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	$.L.str, %edi
	movl	$n, %esi
	xorl	%eax, %eax
	callq	__isoc23_scanf
	movl	n(%rip), %ecx
	testl	%ecx, %ecx
	jle	.LBB3_14
# %bb.1:                                # %.preheader116.preheader
	xorl	%ebx, %ebx
.LBB3_2:                                # %.preheader116
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB3_4 Depth 2
	testl	%ecx, %ecx
	jle	.LBB3_7
# %bb.3:                                # %.lr.ph.preheader
                                        #   in Loop: Header=BB3_2 Depth=1
	xorl	%r14d, %r14d
.LBB3_4:                                # %.lr.ph
                                        #   Parent Loop BB3_2 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	cmpl	%r14d, %ebx
	je	.LBB3_6
# %bb.5:                                #   in Loop: Header=BB3_4 Depth=2
	callq	rand
	shrl	$5, %eax
	andl	$1, %eax
	movl	n(%rip), %ecx
	movl	%ebx, %edx
	imull	%ecx, %edx
	movslq	%edx, %rdx
	addq	%r14, %rdx
	movl	%eax, adj(,%rdx,4)
.LBB3_6:                                #   in Loop: Header=BB3_4 Depth=2
	incq	%r14
	cmpl	%ecx, %r14d
	jl	.LBB3_4
.LBB3_7:                                # %._crit_edge
                                        #   in Loop: Header=BB3_2 Depth=1
	incq	%rbx
	cmpl	%ecx, %ebx
	jl	.LBB3_2
# %bb.8:                                # %.preheader115
	testl	%ecx, %ecx
	jle	.LBB3_14
# %bb.9:                                # %.preheader114.preheader
	xorl	%ebx, %ebx
.LBB3_10:                               # %.preheader114
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB3_12 Depth 2
	testl	%ecx, %ecx
	jle	.LBB3_13
# %bb.11:                               # %.lr.ph121.preheader
                                        #   in Loop: Header=BB3_10 Depth=1
	xorl	%r14d, %r14d
.LBB3_12:                               # %.lr.ph121
                                        #   Parent Loop BB3_10 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	imull	%ebx, %ecx
	movslq	%ecx, %rax
	addq	%r14, %rax
	leaq	adj(,%rax,4), %rsi
	movl	$.L.str, %edi
	xorl	%eax, %eax
	callq	__isoc23_scanf
	movl	n(%rip), %ecx
	incq	%r14
	cmpl	%ecx, %r14d
	jl	.LBB3_12
.LBB3_13:                               # %._crit_edge122
                                        #   in Loop: Header=BB3_10 Depth=1
	incl	%ebx
	cmpl	%ecx, %ebx
	jl	.LBB3_10
.LBB3_14:                               # %.preheader.preheader
	movl	$nCr, %eax
	xorl	%ecx, %ecx
	movl	$1, %edx
.LBB3_15:                               # %.preheader
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB3_17 Depth 2
	movq	%rcx, %rsi
	shlq	$7, %rsi
	leaq	(%rsi,%rcx,4), %rdi
	movl	%edx, nCr(%rdi,%rcx,4)
	movl	%edx, nCr(%rsi,%rcx,4)
	cmpq	$2, %rcx
	jb	.LBB3_18
# %bb.16:                               # %.lr.ph126
                                        #   in Loop: Header=BB3_15 Depth=1
	movl	nCr-132(%rsi,%rcx,4), %edi
	movl	$1, %esi
.LBB3_17:                               #   Parent Loop BB3_15 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movl	-132(%rax,%rsi,4), %r8d
	addl	%r8d, %edi
	movl	%edi, (%rax,%rsi,4)
	incq	%rsi
	movl	%r8d, %edi
	cmpq	%rsi, %rcx
	jne	.LBB3_17
.LBB3_18:                               # %._crit_edge127
                                        #   in Loop: Header=BB3_15 Depth=1
	incq	%rcx
	addq	$132, %rax
	cmpq	$33, %rcx
	jne	.LBB3_15
# %bb.19:
	leaq	16(%rsp), %rdi
	movl	$32768, %esi                    # imm = 0x8000
	callq	hipMalloc
	leaq	40(%rsp), %rbx
	movl	$4096, %esi                     # imm = 0x1000
	movq	%rbx, %rdi
	callq	hipMalloc
	leaq	8(%rsp), %rdi
	movl	$32768, %esi                    # imm = 0x8000
	callq	hipMalloc
	movq	(%rbx), %rdi
	movl	$adj, %esi
	movl	$4096, %edx                     # imm = 0x1000
	movl	$1, %ecx
	callq	hipMemcpy
	movl	n(%rip), %eax
	xorl	%r15d, %r15d
	cmpl	$2, %eax
	jl	.LBB3_30
# %bb.20:                               # %.lr.ph142.preheader
	movl	$1, %ebx
	leaq	nCr-128(%rip), %rbp
	xorl	%r15d, %r15d
.LBB3_21:                               # %.lr.ph142
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB3_32 Depth 2
                                        #       Child Loop BB3_34 Depth 3
                                        #         Child Loop BB3_35 Depth 4
                                        #     Child Loop BB3_39 Depth 2
	cltq
	leaq	-1(%rax), %rcx
	shlq	$7, %rcx
	leaq	(%rcx,%rax,4), %rax
	addq	$-4, %rax
	movl	nCr(%rax,%rbx,4), %r12d
	movl	$1024, %eax                     # imm = 0x400
	xorl	%edx, %edx
	divl	%ebx
	movl	%eax, %ecx
	cmpl	%eax, %r12d
	cmovll	%r12d, %ecx
	movl	%r12d, %eax
	cltd
	idivl	%ecx
	movl	%eax, %r14d
	imull	%ecx, %r14d
	cmpl	$8193, %r14d                    # imm = 0x2001
	jl	.LBB3_23
# %bb.22:                               #   in Loop: Header=BB3_21 Depth=1
	movl	$8192, %eax                     # imm = 0x2000
	xorl	%edx, %edx
	idivl	%ecx
	movl	%eax, %r14d
	imull	%ecx, %r14d
.LBB3_23:                               #   in Loop: Header=BB3_21 Depth=1
	movl	$.L.str.1, %edi
	movl	%ebx, %esi
	movq	%rcx, 48(%rsp)                  # 8-byte Spill
	movl	%ecx, %edx
	movl	%eax, 32(%rsp)                  # 4-byte Spill
	movl	%eax, %ecx
	xorl	%eax, %eax
	callq	printf
	testl	%r14d, %r14d
	movl	%r14d, 36(%rsp)                 # 4-byte Spill
	jle	.LBB3_24
# %bb.31:                               # %.lr.ph131
                                        #   in Loop: Header=BB3_21 Depth=1
	movl	%r15d, 28(%rsp)                 # 4-byte Spill
	movl	%r12d, 24(%rsp)                 # 4-byte Spill
	movl	%r12d, %eax
	cltd
	idivl	%r14d
	movl	n(%rip), %ecx
	decl	%ecx
	movl	%r14d, %r13d
	xorl	%esi, %esi
.LBB3_32:                               #   Parent Loop BB3_21 Depth=1
                                        # =>  This Loop Header: Depth=2
                                        #       Child Loop BB3_34 Depth 3
                                        #         Child Loop BB3_35 Depth 4
	cmpl	%edx, %esi
	movl	%edx, %edi
	cmovll	%esi, %edi
	movl	%eax, %r11d
	imull	%esi, %r11d
	addl	%edi, %r11d
	xorl	%edi, %edi
	movq	%rbp, %r8
	movq	%rbx, %r10
	movl	%ecx, %r9d
.LBB3_34:                               # %select.unfold.lr.ph.i
                                        #   Parent Loop BB3_21 Depth=1
                                        #     Parent Loop BB3_32 Depth=2
                                        # =>    This Loop Header: Depth=3
                                        #         Child Loop BB3_35 Depth 4
	movl	%r11d, %r14d
	movslq	%r9d, %r11
	movq	%r11, %r12
	shlq	$7, %r12
	leaq	(%r12,%r11,4), %r12
	addq	%r8, %r12
.LBB3_35:                               # %select.unfold.i
                                        #   Parent Loop BB3_21 Depth=1
                                        #     Parent Loop BB3_32 Depth=2
                                        #       Parent Loop BB3_34 Depth=3
                                        # =>      This Inner Loop Header: Depth=4
	decl	%r9d
	leaq	-132(%r12), %r15
	movl	%r14d, %r11d
	subl	(%r12), %r11d
	movq	%r15, %r12
	jl	.LBB3_35
# %bb.33:                               # %.outer.loopexit.i
                                        #   in Loop: Header=BB3_34 Depth=3
	btsl	%r9d, %edi
	leaq	-1(%r10), %r14
	addq	$-4, %r8
	cmpq	$2, %r10
	movq	%r14, %r10
	jge	.LBB3_34
# %bb.36:                               # %_Z7getCombiii.exit
                                        #   in Loop: Header=BB3_32 Depth=2
	movl	%edi, part(,%rsi,4)
	incq	%rsi
	cmpq	%r13, %rsi
	jb	.LBB3_32
# %bb.37:                               #   in Loop: Header=BB3_21 Depth=1
	movl	28(%rsp), %r15d                 # 4-byte Reload
	movl	24(%rsp), %r12d                 # 4-byte Reload
	jmp	.LBB3_25
.LBB3_24:                               # %.._crit_edge132_crit_edge
                                        #   in Loop: Header=BB3_21 Depth=1
	movslq	%r14d, %r13
.LBB3_25:                               # %._crit_edge132
                                        #   in Loop: Header=BB3_21 Depth=1
	movq	16(%rsp), %rdi
	leaq	(,%r13,4), %r14
	movl	$part, %esi
	movq	%r14, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	movl	32(%rsp), %edi                  # 4-byte Reload
	btsq	$32, %rdi
	movq	48(%rsp), %rdx                  # 8-byte Reload
	shlq	$32, %rdx
	orq	%rbx, %rdx
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB3_27
# %bb.26:                               #   in Loop: Header=BB3_21 Depth=1
	movl	n(%rip), %edi
	movq	16(%rsp), %rdx
	movq	40(%rsp), %rcx
	movq	8(%rsp), %r8
	movl	%r12d, %esi
	xorl	%r9d, %r9d
	callq	_Z18__device_stub__ha2iiPjPiS_j
.LBB3_27:                               #   in Loop: Header=BB3_21 Depth=1
	callq	hipDeviceSynchronize
	movq	8(%rsp), %rsi
	movl	$ret, %edi
	movq	%r14, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	cmpl	$0, 36(%rsp)                    # 4-byte Folded Reload
	jle	.LBB3_28
# %bb.38:                               # %.lr.ph136.preheader
                                        #   in Loop: Header=BB3_21 Depth=1
	xorl	%eax, %eax
	xorl	%r14d, %r14d
.LBB3_39:                               # %.lr.ph136
                                        #   Parent Loop BB3_21 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	addl	ret(,%rax,4), %r14d
	incq	%rax
	cmpq	%r13, %rax
	jl	.LBB3_39
	jmp	.LBB3_29
.LBB3_28:                               #   in Loop: Header=BB3_21 Depth=1
	xorl	%r14d, %r14d
.LBB3_29:                               # %._crit_edge137
                                        #   in Loop: Header=BB3_21 Depth=1
	movl	$.L.str.2, %edi
	movl	%r14d, %esi
	xorl	%eax, %eax
	callq	printf
	movslq	n(%rip), %rax
	movl	%eax, %ecx
	subl	%ebx, %ecx
	andl	$-2147483647, %ecx              # imm = 0x80000001
	movl	%r14d, %edx
	negl	%edx
	cmpl	$1, %ecx
	cmovel	%r14d, %edx
	addl	%edx, %r15d
	incq	%rbx
	addq	$4, %rbp
	cmpq	%rax, %rbx
	jl	.LBB3_21
.LBB3_30:                               # %._crit_edge143
	movl	$.L.str.3, %edi
	movl	%r15d, %esi
	xorl	%eax, %eax
	callq	printf
	movq	8(%rsp), %rdi
	callq	hipFree
	movq	40(%rsp), %rdi
	callq	hipFree
	movq	16(%rsp), %rdi
	callq	hipFree
	xorl	%eax, %eax
	addq	$56, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	main, .Lfunc_end3-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB4_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB4_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z3ha2iiPjPiS_j, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end4:
	.size	__hip_module_ctor, .Lfunc_end4-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB5_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB5_2:
	retq
.Lfunc_end5:
	.size	__hip_module_dtor, .Lfunc_end5-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z3ha2iiPjPiS_j,@object         # @_Z3ha2iiPjPiS_j
	.section	.rodata,"a",@progbits
	.globl	_Z3ha2iiPjPiS_j
	.p2align	3, 0x0
_Z3ha2iiPjPiS_j:
	.quad	_Z18__device_stub__ha2iiPjPiS_j
	.size	_Z3ha2iiPjPiS_j, 8

	.type	n,@object                       # @n
	.bss
	.globl	n
	.p2align	2, 0x0
n:
	.long	0                               # 0x0
	.size	n, 4

	.type	adj,@object                     # @adj
	.globl	adj
	.p2align	4, 0x0
adj:
	.zero	4096
	.size	adj, 4096

	.type	part,@object                    # @part
	.globl	part
	.p2align	4, 0x0
part:
	.zero	32768
	.size	part, 32768

	.type	ret,@object                     # @ret
	.globl	ret
	.p2align	4, 0x0
ret:
	.zero	32768
	.size	ret, 32768

	.type	nCr,@object                     # @nCr
	.globl	nCr
	.p2align	4, 0x0
nCr:
	.zero	4356
	.size	nCr, 4356

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"%d"
	.size	.L.str, 3

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"block size = (%d,%d,1) grid size = (%d,1,1)\n"
	.size	.L.str.1, 45

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"sum = %u\n"
	.size	.L.str.2, 10

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"ans = %u\n"
	.size	.L.str.3, 10

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z3ha2iiPjPiS_j"
	.size	.L__unnamed_1, 16

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z18__device_stub__ha2iiPjPiS_j
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z3ha2iiPjPiS_j
	.addrsig_sym n
	.addrsig_sym adj
	.addrsig_sym part
	.addrsig_sym ret
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z3ha2iiPjPiS_j         ; -- Begin function _Z3ha2iiPjPiS_j
	.globl	_Z3ha2iiPjPiS_j
	.p2align	8
	.type	_Z3ha2iiPjPiS_j,@function
_Z3ha2iiPjPiS_j:                        ; @_Z3ha2iiPjPiS_j
; %bb.0:
	s_clause 0x1
	s_load_b32 s8, s[0:1], 0x34
	s_load_b128 s[4:7], s[0:1], 0x8
	v_bfe_u32 v5, v0, 10, 10
	v_and_b32_e32 v0, 0x3ff, v0
	s_mov_b32 s9, exec_lo
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s12, s8, 16
	s_and_b32 s8, s8, 0xffff
	v_mad_u64_u32 v[3:4], null, s15, s12, v[5:6]
	v_mad_u32_u24 v9, v5, s8, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v4, 31, v3
	v_lshlrev_b64 v[1:2], 2, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v6, vcc_lo, s4, v1
	v_add_co_ci_u32_e32 v7, vcc_lo, s5, v2, vcc_lo
	global_load_b32 v4, v[6:7], off
	s_clause 0x2
	s_load_b64 s[4:5], s[0:1], 0x0
	s_load_b64 s[2:3], s[0:1], 0x18
	s_load_b32 s13, s[0:1], 0x28
	s_waitcnt lgkmcnt(0)
	v_cmpx_gt_i32_e64 s4, v9
	s_cbranch_execz .LBB0_5
; %bb.1:                                ; %.preheader117.lr.ph
	v_mul_lo_u32 v6, s4, v9
	v_mov_b32_e32 v10, v9
	s_mul_i32 s10, s12, s8
	s_mov_b32 s14, 0
	s_mul_i32 s11, s10, s4
.LBB0_2:                                ; %.preheader117
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_3 Depth 2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v7, 31, v6
	v_mov_b32_e32 v11, 0
	s_mov_b32 s15, 0
	v_lshlrev_b64 v[7:8], 2, v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v7, vcc_lo, s6, v7
	v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
.LBB0_3:                                ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	global_load_b32 v12, v[7:8], off
	v_add_co_u32 v7, vcc_lo, v7, 4
	v_add_co_ci_u32_e32 v8, vcc_lo, 0, v8, vcc_lo
	s_waitcnt vmcnt(0)
	v_lshl_or_b32 v11, v12, s15, v11
	s_add_i32 s15, s15, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s4, s15
	s_cbranch_scc0 .LBB0_3
; %bb.4:                                ; %._crit_edge
                                        ;   in Loop: Header=BB0_2 Depth=1
	v_lshlrev_b32_e32 v7, 2, v10
	v_add_nc_u32_e32 v10, s10, v10
	v_add_nc_u32_e32 v6, s11, v6
	ds_store_b32 v7, v11 offset:4096
	v_cmp_le_i32_e32 vcc_lo, s4, v10
	s_or_b32 s14, vcc_lo, s14
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s14
	s_cbranch_execnz .LBB0_2
.LBB0_5:                                ; %Flow218
	s_or_b32 exec_lo, exec_lo, s9
	v_mul_u32_u24_e32 v5, s8, v5
	s_cmp_lt_i32 s5, 1
	s_waitcnt vmcnt(0) lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB0_26
; %bb.6:                                ; %.preheader116.lr.ph
	s_load_b32 s1, s[0:1], 0x20
	s_lshl_b32 s7, -1, s8
	s_add_i32 s6, s4, -2
	s_not_b32 s7, s7
	s_cmp_gt_i32 s4, 1
	v_cmp_ne_u32_e64 s0, 0, v0
	s_cselect_b32 s9, -1, 0
	s_add_i32 s10, s4, -1
	s_cmp_gt_i32 s4, 2
	v_lshlrev_b32_e32 v6, 2, v9
	s_cselect_b32 s4, -1, 0
	s_cmp_lg_u32 s8, 0
	v_mov_b32_e32 v9, 0
	s_cselect_b32 s11, -1, 0
	s_lshl_b32 s14, s10, 2
	s_mul_i32 s12, s13, s12
	s_addk_i32 s14, 0x1000
	s_delay_alu instid0(SALU_CYCLE_1)
	v_dual_mov_b32 v8, s14 :: v_dual_lshlrev_b32 v7, 2, v5
	v_mov_b32_e32 v5, 0
	s_mov_b32 s13, 0
.LBB0_7:                                ; %.preheader116
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_9 Depth 2
                                        ;     Child Loop BB0_13 Depth 2
                                        ;     Child Loop BB0_16 Depth 2
                                        ;       Child Loop BB0_18 Depth 3
                                        ;     Child Loop BB0_24 Depth 2
	s_delay_alu instid0(VALU_DEP_1)
	v_mov_b32_e32 v10, v4
	s_and_saveexec_b32 s14, s0
	s_cbranch_execz .LBB0_11
; %bb.8:                                ; %.lr.ph124.preheader
                                        ;   in Loop: Header=BB0_7 Depth=1
	v_mov_b32_e32 v11, v0
	v_mov_b32_e32 v10, v4
	s_mov_b32 s15, 0
.LBB0_9:                                ; %.lr.ph124
                                        ;   Parent Loop BB0_7 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v11, -1, v11
	v_add_nc_u32_e32 v12, -1, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_eq_u32_e32 vcc_lo, 0, v11
	v_and_b32_e32 v10, v12, v10
	s_or_b32 s15, vcc_lo, s15
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s15
	s_cbranch_execnz .LBB0_9
; %bb.10:                               ; %Flow213
                                        ;   in Loop: Header=BB0_7 Depth=1
	s_or_b32 exec_lo, exec_lo, s15
.LBB0_11:                               ; %Flow214
                                        ;   in Loop: Header=BB0_7 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_or_b32 exec_lo, exec_lo, s14
	v_ctz_i32_b32_e32 v10, v10
	s_and_not1_b32 vcc_lo, exec_lo, s9
	s_delay_alu instid0(VALU_DEP_1)
	v_lshlrev_b32_e32 v11, 2, v10
	ds_load_b32 v12, v11 offset:4096
	v_mov_b32_e32 v11, 0
	s_cbranch_vccnz .LBB0_14
; %bb.12:                               ; %.lr.ph130.preheader
                                        ;   in Loop: Header=BB0_7 Depth=1
	v_mov_b32_e32 v11, 0
	s_mov_b32 s14, s6
.LBB0_13:                               ; %.lr.ph130
                                        ;   Parent Loop BB0_7 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
	v_lshlrev_b32_e32 v13, 1, v11
	s_waitcnt lgkmcnt(0)
	v_lshrrev_b32_e32 v14, s14, v12
	v_bfe_u32 v15, v4, s14, 1
	s_add_i32 s14, s14, -1
	s_cmp_eq_u32 s14, -1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_or_b32 v13, v14, 1, v13
	v_cmp_eq_u32_e32 vcc_lo, 0, v15
	s_delay_alu instid0(VALU_DEP_2)
	v_cndmask_b32_e32 v11, v13, v11, vcc_lo
	s_cbranch_scc0 .LBB0_13
.LBB0_14:                               ; %._crit_edge131
                                        ;   in Loop: Header=BB0_7 Depth=1
	s_waitcnt lgkmcnt(0)
	v_bfe_u32 v12, v12, s10, 1
	s_and_not1_b32 vcc_lo, exec_lo, s4
	ds_store_b32 v6, v12
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_vccnz .LBB0_20
; %bb.15:                               ; %.preheader.preheader
                                        ;   in Loop: Header=BB0_7 Depth=1
	s_mov_b32 s14, 1
.LBB0_16:                               ; %.preheader
                                        ;   Parent Loop BB0_7 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB0_18 Depth 3
	v_mov_b32_e32 v12, 0
	s_and_not1_b32 vcc_lo, exec_lo, s11
	s_cbranch_vccnz .LBB0_19
; %bb.17:                               ; %.lr.ph135.preheader
                                        ;   in Loop: Header=BB0_16 Depth=2
	v_mov_b32_e32 v13, v7
	s_mov_b32 s15, 0
.LBB0_18:                               ; %.lr.ph135
                                        ;   Parent Loop BB0_7 Depth=1
                                        ;     Parent Loop BB0_16 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	ds_load_b32 v14, v13
	v_lshrrev_b32_e32 v15, s15, v11
	v_add_nc_u32_e32 v13, 4, v13
	s_add_i32 s15, s15, 1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	s_cmp_eq_u32 s8, s15
	v_and_b32_e32 v15, 1, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_cmp_eq_u32_e32 vcc_lo, 1, v15
	s_waitcnt lgkmcnt(0)
	v_cndmask_b32_e32 v14, 0, v14, vcc_lo
	v_add_nc_u32_e32 v12, v14, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_le_u32_e32 vcc_lo, s1, v12
	v_cndmask_b32_e64 v14, 0, s1, vcc_lo
	v_sub_nc_u32_e32 v12, v12, v14
	s_cbranch_scc0 .LBB0_18
.LBB0_19:                               ; %._crit_edge136
                                        ;   in Loop: Header=BB0_16 Depth=2
	s_add_i32 s14, s14, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s14, s10
	s_barrier
	buffer_gl0_inv
	ds_store_b32 v6, v12
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc0 .LBB0_16
.LBB0_20:                               ; %._crit_edge139
                                        ;   in Loop: Header=BB0_7 Depth=1
	ds_load_b32 v11, v8
	s_mov_b32 s14, exec_lo
	s_waitcnt lgkmcnt(0)
	v_bfe_u32 v10, v11, v10, 1
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v10
	s_cbranch_execz .LBB0_22
; %bb.21:                               ;   in Loop: Header=BB0_7 Depth=1
	ds_store_b32 v6, v9
.LBB0_22:                               ;   in Loop: Header=BB0_7 Depth=1
	s_or_b32 exec_lo, exec_lo, s14
	v_mov_b32_e32 v10, 0
	s_and_not1_b32 vcc_lo, exec_lo, s11
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_vccnz .LBB0_25
; %bb.23:                               ; %.lr.ph143.preheader
                                        ;   in Loop: Header=BB0_7 Depth=1
	v_mov_b32_e32 v11, v7
	s_mov_b32 s14, s8
.LBB0_24:                               ; %.lr.ph143
                                        ;   Parent Loop BB0_7 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	ds_load_b32 v12, v11
	v_add_nc_u32_e32 v11, 4, v11
	s_add_i32 s14, s14, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	s_cmp_eq_u32 s14, 0
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v10, v12, v10
	v_cmp_le_u32_e32 vcc_lo, s1, v10
	v_cndmask_b32_e64 v12, 0, s1, vcc_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_sub_nc_u32_e32 v10, v10, v12
	s_cbranch_scc0 .LBB0_24
.LBB0_25:                               ; %._crit_edge144
                                        ;   in Loop: Header=BB0_7 Depth=1
	v_sub_nc_u32_e32 v11, 0, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v10, v10, v5
	v_add_nc_u32_e32 v13, s13, v3
	s_add_i32 s13, s13, s12
	v_and_b32_e32 v11, v4, v11
	s_delay_alu instid0(VALU_DEP_3)
	v_cmp_le_u32_e32 vcc_lo, s1, v10
	s_cmp_ge_i32 s13, s5
	s_barrier
	buffer_gl0_inv
	v_add_nc_u32_e32 v4, v11, v4
	v_cndmask_b32_e64 v11, 0, s1, vcc_lo
	v_cmp_gt_i32_e32 vcc_lo, s5, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v10, v10, v11
	v_cndmask_b32_e32 v5, v5, v10, vcc_lo
	v_bcnt_u32_b32 v12, v4, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshrrev_b32_e64 v11, v12, s7
	v_or_b32_e32 v4, v11, v4
	s_cbranch_scc0 .LBB0_7
	s_branch .LBB0_27
.LBB0_26:
	v_mov_b32_e32 v5, 0
.LBB0_27:                               ; %._crit_edge149
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB0_29
; %bb.28:
	v_add_co_u32 v0, vcc_lo, s2, v1
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v2, vcc_lo
	global_store_b32 v[0:1], v5, off
.LBB0_29:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z3ha2iiPjPiS_j
		.amdhsa_group_segment_fixed_size 4224
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 16
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z3ha2iiPjPiS_j, .Lfunc_end0-_Z3ha2iiPjPiS_j
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1108
; NumSgprs: 18
; NumVgprs: 16
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 4224 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 16
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     by_value
      - .offset:         4
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         44
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         52
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         54
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         56
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         58
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         60
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         62
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         104
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 4224
    .kernarg_segment_align: 8
    .kernarg_segment_size: 296
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z3ha2iiPjPiS_j
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z3ha2iiPjPiS_j.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     16
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
