#include <iostream>
#include <stdio.h>
#include <cstdlib>

using namespace std;

__global__ void verticalOperation(int size, float *deviceArray, float *deviceResult) {

    int index = blockIdx.x * blockDim.x + threadIdx.x;
    int blockSize = blockDim.x; //NOTE: this would also be the amount of values in shared memory (or it should be anyways)

    //allocated shared memory to reduce global memory access overhead
    extern __shared__ float sdata[];

    //move each value from deviceArray pointer into shared_memory_array
    sdata[threadIdx.x] = deviceArray[index];

    __syncthreads();
    
    //stride is currently the length of the unsorted array that still needs to be compared
    for (int stride = blockSize; stride >= 1; stride /= 2) {
        if (threadIdx.x < stride/2) {
            if (sdata[threadIdx.x + (stride/2)] > sdata[threadIdx.x]) {
                sdata[threadIdx.x] = sdata[threadIdx.x + (stride/2)];
            }
        }
        __syncthreads();
    }
    
    if (threadIdx.x == 0) { deviceResult[blockIdx.x] = sdata[0]; }

    //stride is currently the length of the unsorted array that still needs to be compared
    for (int stride = gridDim.x; stride >= 1; stride /= 2) {
        if (index < stride/2) {
            if (deviceResult[index + (stride/2)] > deviceResult[index]) {
                deviceResult[index] = deviceResult[index + (stride/2)];
            }
        }
    }
}

void testVerticalOperation() {

    int number_of_values = 1 << 18;

    int memSize = number_of_values*sizeof(float);

    int blockSize = 256;
    int numBlocks = (number_of_values/blockSize)+1;

    float *deviceValue, *deviceResult; //device copies
    float initialValue[number_of_values], result[number_of_values]; //host copies

    for (int x = 0; x < number_of_values; x++) {
        initialValue[x] = 0.0f;
    }

    initialValue[2] = 500.0f;
    initialValue[3] = 600.0f;
    initialValue[66] = 998.0f;
    initialValue[30000] = 1000.0f;




    //Allocates "Unified Memory" which is accessible from both the CPU and GPU.
    cudaError_t cudaMallocErr1 = cudaMalloc(&deviceValue, memSize);
    if (cudaMallocErr1 != cudaSuccess) {
        cout << "CUDA Error" << endl;
    }

    //Allocates "Unified Memory" which is accessible from both the CPU and GPU.
    cudaError_t cudaMallocErr2 = cudaMalloc(&deviceResult, memSize);
    if (cudaMallocErr2 != cudaSuccess) {
        cout << "CUDA Error" << endl;
    }


    //copy memory to device from host and print error if found
    cudaError_t cudaMemcpy1Err = cudaMemcpy(deviceValue, &initialValue, memSize, cudaMemcpyHostToDevice);
    if (cudaMemcpy1Err != cudaSuccess) {
        cout << "Memcpy to Device Error: " << cudaMemcpy1Err << endl;
    }

    verticalOperation<<<numBlocks, blockSize, memSize/blockSize>>>(number_of_values, deviceValue, deviceResult);

    //Forces CPU to wait for GPU to finish before accessing
    cudaDeviceSynchronize();


    //copy memory to host from device and print error if found
    cudaError_t cudaMemcpy2Err = cudaMemcpy(&result, deviceResult, memSize, cudaMemcpyDeviceToHost);
    if (cudaMemcpy2Err != cudaSuccess) {
        cout << "Memcpy to Host Error: " << cudaMemcpy2Err << endl;
    }


    cout << result[0] << endl;

    cout << "Done!" << endl;

    // Free memory
    cudaFree(deviceValue);
    cudaFree(deviceResult);
}


int main() {
    //Runs test for verticalOperation kernal on GPU
    testVerticalOperation();

    return 0;

}

	.file	"tmpxft_00322971_00000000-6_max.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3639:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3639:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.align 2
	.type	_ZNSolsEPFRSoS_E.isra.0, @function
_ZNSolsEPFRSoS_E.isra.0:
.LFB4295:
	.cfi_startproc
	jmp	*%rsi
	.cfi_endproc
.LFE4295:
	.size	_ZNSolsEPFRSoS_E.isra.0, .-_ZNSolsEPFRSoS_E.isra.0
	.globl	_Z40__device_stub__Z17verticalOperationiPfS_iPfS_
	.type	_Z40__device_stub__Z17verticalOperationiPfS_iPfS_, @function
_Z40__device_stub__Z17verticalOperationiPfS_iPfS_:
.LFB3661:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movl	%edi, 28(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	28(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L3
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z17verticalOperationiPfS_(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L3:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L5
	call	__stack_chk_fail@PLT
.L5:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3661:
	.size	_Z40__device_stub__Z17verticalOperationiPfS_iPfS_, .-_Z40__device_stub__Z17verticalOperationiPfS_iPfS_
	.globl	_Z17verticalOperationiPfS_
	.type	_Z17verticalOperationiPfS_, @function
_Z17verticalOperationiPfS_:
.LFB3662:
	.cfi_startproc
	endbr64
	jmp	_Z40__device_stub__Z17verticalOperationiPfS_iPfS_
	.cfi_endproc
.LFE3662:
	.size	_Z17verticalOperationiPfS_, .-_Z17verticalOperationiPfS_
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC2:
	.string	"CUDA Error"
.LC3:
	.string	"Memcpy to Device Error: "
.LC4:
	.string	"Memcpy to Host Error: "
.LC5:
	.string	"Done!"
	.text
	.globl	_Z21testVerticalOperationv
	.type	_Z21testVerticalOperationv, @function
_Z21testVerticalOperationv:
.LFB3635:
	.cfi_startproc
	endbr64
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register 6
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$48, %rsp
	.cfi_offset 14, -24
	.cfi_offset 13, -32
	.cfi_offset 12, -40
	.cfi_offset 3, -48
	movq	%fs:40, %rax
	movq	%rax, -40(%rbp)
	xorl	%eax, %eax
	leaq	-1048576(%rsp), %rax
.L10:
	cmpq	%rax, %rsp
	je	.L11
	subq	$4096, %rsp
	orq	$0, 4088(%rsp)
	jmp	.L10
.L11:
	leaq	3(%rsp), %r12
	leaq	-1048576(%rsp), %rax
	movq	%r12, %rdx
	andq	$-4, %r12
	shrq	$2, %rdx
.L13:
	cmpq	%rax, %rsp
	je	.L14
	subq	$4096, %rsp
	orq	$0, 4088(%rsp)
	jmp	.L13
.L14:
	xorl	%eax, %eax
	movl	$262144, %ecx
	movl	$1048576, %esi
	leaq	_ZSt4cout(%rip), %rbx
	movq	%r12, %rdi
	leaq	3(%rsp), %r14
	rep stosl
	leaq	-80(%rbp), %rdi
	movq	%r14, %r13
	andq	$-4, %r14
	movabsq	$4906108845207191552, %rax
	shrq	$2, %r13
	movl	$0x44798000, 264(,%rdx,4)
	movq	%rax, 8(,%rdx,4)
	movl	$0x447a0000, 120000(,%rdx,4)
	call	cudaMalloc@PLT
	testl	%eax, %eax
	je	.L16
	leaq	.LC2(%rip), %rsi
	movq	%rbx, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E.isra.0
.L16:
	leaq	-72(%rbp), %rdi
	movl	$1048576, %esi
	call	cudaMalloc@PLT
	testl	%eax, %eax
	je	.L17
	leaq	.LC2(%rip), %rsi
	movq	%rbx, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E.isra.0
.L17:
	movq	-80(%rbp), %rdi
	movq	%r12, %rsi
	movl	$1, %ecx
	movl	$1048576, %edx
	call	cudaMemcpy@PLT
	movl	%eax, %r12d
	testl	%eax, %eax
	je	.L18
	leaq	.LC3(%rip), %rsi
	movq	%rbx, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	%r12d, %esi
	movq	%rax, %rdi
	call	_ZNSolsEi@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E.isra.0
.L18:
	movl	$16777217, %edx
	xorl	%r9d, %r9d
	movl	$1, %ecx
	movabsq	$4294968321, %rdi
	salq	$8, %rdx
	movl	$1, %esi
	movq	%rdi, -64(%rbp)
	movl	$4096, %r8d
	movq	%rdx, -52(%rbp)
	movl	$1, -44(%rbp)
	movl	$1, -56(%rbp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L19
	movq	-72(%rbp), %rdx
	movq	-80(%rbp), %rsi
	movl	$262144, %edi
	call	_Z40__device_stub__Z17verticalOperationiPfS_iPfS_
.L19:
	call	cudaDeviceSynchronize@PLT
	movq	-72(%rbp), %rsi
	movl	$2, %ecx
	movq	%r14, %rdi
	movl	$1048576, %edx
	call	cudaMemcpy@PLT
	movl	%eax, %r12d
	testl	%eax, %eax
	je	.L20
	leaq	.LC4(%rip), %rsi
	movq	%rbx, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	%r12d, %esi
	movq	%rax, %rdi
	call	_ZNSolsEi@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E.isra.0
.L20:
	cvtss2sd	0(,%r13,4), %xmm0
	movq	%rbx, %rdi
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E.isra.0
	leaq	.LC5(%rip), %rsi
	movq	%rbx, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E.isra.0
	movq	-80(%rbp), %rdi
	call	cudaFree@PLT
	movq	-72(%rbp), %rdi
	call	cudaFree@PLT
	movq	-40(%rbp), %rax
	subq	%fs:40, %rax
	je	.L21
	call	__stack_chk_fail@PLT
.L21:
	leaq	-32(%rbp), %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE3635:
	.size	_Z21testVerticalOperationv, .-_Z21testVerticalOperationv
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB3636:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	call	_Z21testVerticalOperationv
	xorl	%eax, %eax
	popq	%rdx
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3636:
	.size	main, .-main
	.section	.rodata.str1.1
.LC6:
	.string	"_Z17verticalOperationiPfS_"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3664:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC6(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z17verticalOperationiPfS_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3664:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include <iostream>
#include <stdio.h>
#include <cstdlib>

using namespace std;

__global__ void verticalOperation(int size, float *deviceArray, float *deviceResult) {

    int index = blockIdx.x * blockDim.x + threadIdx.x;
    int blockSize = blockDim.x; //NOTE: this would also be the amount of values in shared memory (or it should be anyways)

    //allocated shared memory to reduce global memory access overhead
    extern __shared__ float sdata[];

    //move each value from deviceArray pointer into shared_memory_array
    sdata[threadIdx.x] = deviceArray[index];

    __syncthreads();
    
    //stride is currently the length of the unsorted array that still needs to be compared
    for (int stride = blockSize; stride >= 1; stride /= 2) {
        if (threadIdx.x < stride/2) {
            if (sdata[threadIdx.x + (stride/2)] > sdata[threadIdx.x]) {
                sdata[threadIdx.x] = sdata[threadIdx.x + (stride/2)];
            }
        }
        __syncthreads();
    }
    
    if (threadIdx.x == 0) { deviceResult[blockIdx.x] = sdata[0]; }

    //stride is currently the length of the unsorted array that still needs to be compared
    for (int stride = gridDim.x; stride >= 1; stride /= 2) {
        if (index < stride/2) {
            if (deviceResult[index + (stride/2)] > deviceResult[index]) {
                deviceResult[index] = deviceResult[index + (stride/2)];
            }
        }
    }
}

void testVerticalOperation() {

    int number_of_values = 1 << 18;

    int memSize = number_of_values*sizeof(float);

    int blockSize = 256;
    int numBlocks = (number_of_values/blockSize)+1;

    float *deviceValue, *deviceResult; //device copies
    float initialValue[number_of_values], result[number_of_values]; //host copies

    for (int x = 0; x < number_of_values; x++) {
        initialValue[x] = 0.0f;
    }

    initialValue[2] = 500.0f;
    initialValue[3] = 600.0f;
    initialValue[66] = 998.0f;
    initialValue[30000] = 1000.0f;




    //Allocates "Unified Memory" which is accessible from both the CPU and GPU.
    hipError_t cudaMallocErr1 = hipMalloc(&deviceValue, memSize);
    if (cudaMallocErr1 != hipSuccess) {
        cout << "CUDA Error" << endl;
    }

    //Allocates "Unified Memory" which is accessible from both the CPU and GPU.
    hipError_t cudaMallocErr2 = hipMalloc(&deviceResult, memSize);
    if (cudaMallocErr2 != hipSuccess) {
        cout << "CUDA Error" << endl;
    }


    //copy memory to device from host and print error if found
    hipError_t cudaMemcpy1Err = hipMemcpy(deviceValue, &initialValue, memSize, hipMemcpyHostToDevice);
    if (cudaMemcpy1Err != hipSuccess) {
        cout << "Memcpy to Device Error: " << cudaMemcpy1Err << endl;
    }

    verticalOperation<<<numBlocks, blockSize, memSize/blockSize>>>(number_of_values, deviceValue, deviceResult);

    //Forces CPU to wait for GPU to finish before accessing
    hipDeviceSynchronize();


    //copy memory to host from device and print error if found
    hipError_t cudaMemcpy2Err = hipMemcpy(&result, deviceResult, memSize, hipMemcpyDeviceToHost);
    if (cudaMemcpy2Err != hipSuccess) {
        cout << "Memcpy to Host Error: " << cudaMemcpy2Err << endl;
    }


    cout << result[0] << endl;

    cout << "Done!" << endl;

    // Free memory
    hipFree(deviceValue);
    hipFree(deviceResult);
}


int main() {
    //Runs test for verticalOperation kernal on GPU
    testVerticalOperation();

    return 0;

}

	.text
	.file	"max.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z32__device_stub__verticalOperationiPfS_ # -- Begin function _Z32__device_stub__verticalOperationiPfS_
	.type	_Z32__device_stub__verticalOperationiPfS_,@function
_Z32__device_stub__verticalOperationiPfS_: # @_Z32__device_stub__verticalOperationiPfS_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	12(%rsp), %rax
	movl	%edi, (%rax)
	leaq	40(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	32(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z17verticalOperationiPfS_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z32__device_stub__verticalOperationiPfS_, .Lfunc_end0-_Z32__device_stub__verticalOperationiPfS_
	.cfi_endproc
                                        # -- End function
	.globl	_Z21testVerticalOperationv      # -- Begin function _Z21testVerticalOperationv
	.type	_Z21testVerticalOperationv,@function
_Z21testVerticalOperationv:             # @_Z21testVerticalOperationv
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	subq	$2097168, %rsp                  # imm = 0x200010
	.cfi_def_cfa_offset 2097200
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movq	%rsp, %r14
	leaq	1048592(%rsp), %rbx
	movl	$1048576, %edx                  # imm = 0x100000
	movq	%rbx, %rdi
	xorl	%esi, %esi
	callq	memset@PLT
	movabsq	$4906108845207191552, %rax      # imm = 0x4416000043FA0000
	movq	%rax, 8(%rbx)
	movl	$1148813312, 264(%rbx)          # imm = 0x44798000
	movl	$1148846080, 120000(%rbx)       # imm = 0x447A0000
	leaq	8(%rsp), %rdi
	movl	$1048576, %esi                  # imm = 0x100000
	callq	hipMalloc
	testl	%eax, %eax
	je	.LBB1_2
# %bb.1:
	movl	$_ZSt4cout, %ebx
	movl	$_ZSt4cout, %edi
	movl	$.L.str, %esi
	movl	$10, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	_ZSt4cout(%rip), %rax
	movq	-24(%rax), %rdi
	addq	%rbx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movl	$_ZSt4cout, %edi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
.LBB1_2:
	movq	%rsp, %rdi
	movl	$1048576, %esi                  # imm = 0x100000
	callq	hipMalloc
	testl	%eax, %eax
	je	.LBB1_4
# %bb.3:
	movl	$_ZSt4cout, %ebx
	movl	$_ZSt4cout, %edi
	movl	$.L.str, %esi
	movl	$10, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	_ZSt4cout(%rip), %rax
	movq	-24(%rax), %rdi
	addq	%rbx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movl	$_ZSt4cout, %edi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
.LBB1_4:
	movq	8(%rsp), %rdi
	leaq	1048592(%rsp), %rsi
	movl	$1048576, %edx                  # imm = 0x100000
	movl	$1, %ecx
	callq	hipMemcpy
	testl	%eax, %eax
	je	.LBB1_6
# %bb.5:
	movl	%eax, %ebx
	movl	$_ZSt4cout, %edi
	movl	$.L.str.1, %esi
	movl	$24, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	$_ZSt4cout, %edi
	movl	%ebx, %esi
	callq	_ZNSolsEi
	movq	%rax, %rbx
	movq	(%rax), %rax
	movq	-24(%rax), %rdi
	addq	%rbx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%rbx, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
.LBB1_6:
	movabsq	$4294967552, %rdx               # imm = 0x100000100
	leaq	769(%rdx), %rdi
	movl	$4096, %r8d                     # imm = 0x1000
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_8
# %bb.7:
	movq	8(%rsp), %rsi
	movq	(%rsp), %rdx
	movl	$262144, %edi                   # imm = 0x40000
	callq	_Z32__device_stub__verticalOperationiPfS_
.LBB1_8:
	callq	hipDeviceSynchronize
	movq	(%rsp), %rsi
	leaq	16(%rsp), %rdi
	movl	$1048576, %edx                  # imm = 0x100000
	movl	$2, %ecx
	callq	hipMemcpy
	testl	%eax, %eax
	je	.LBB1_10
# %bb.9:
	movl	%eax, %ebx
	movl	$_ZSt4cout, %edi
	movl	$.L.str.2, %esi
	movl	$22, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	$_ZSt4cout, %edi
	movl	%ebx, %esi
	callq	_ZNSolsEi
	movq	%rax, %rbx
	movq	(%rax), %rax
	movq	-24(%rax), %rdi
	addq	%rbx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%rbx, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
.LBB1_10:
	cvtss2sd	16(%rsp), %xmm0
	movl	$_ZSt4cout, %r15d
	movl	$_ZSt4cout, %edi
	callq	_ZNSo9_M_insertIdEERSoT_
	movq	%rax, %rbx
	movq	(%rax), %rax
	movq	-24(%rax), %rdi
	addq	%rbx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%rbx, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movl	$_ZSt4cout, %edi
	movl	$.L.str.3, %esi
	movl	$5, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	_ZSt4cout(%rip), %rax
	movq	-24(%rax), %rdi
	addq	%r15, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movl	$_ZSt4cout, %edi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movq	8(%rsp), %rdi
	callq	hipFree
	movq	(%rsp), %rdi
	callq	hipFree
	movq	%r14, %rsp
	addq	$2097168, %rsp                  # imm = 0x200010
	.cfi_def_cfa_offset 32
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z21testVerticalOperationv, .Lfunc_end1-_Z21testVerticalOperationv
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	_Z21testVerticalOperationv
	xorl	%eax, %eax
	popq	%rcx
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	main, .Lfunc_end2-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB3_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB3_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z17verticalOperationiPfS_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end3:
	.size	__hip_module_ctor, .Lfunc_end3-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB4_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB4_2:
	retq
.Lfunc_end4:
	.size	__hip_module_dtor, .Lfunc_end4-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z17verticalOperationiPfS_,@object # @_Z17verticalOperationiPfS_
	.section	.rodata,"a",@progbits
	.globl	_Z17verticalOperationiPfS_
	.p2align	3, 0x0
_Z17verticalOperationiPfS_:
	.quad	_Z32__device_stub__verticalOperationiPfS_
	.size	_Z17verticalOperationiPfS_, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"CUDA Error"
	.size	.L.str, 11

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"Memcpy to Device Error: "
	.size	.L.str.1, 25

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"Memcpy to Host Error: "
	.size	.L.str.2, 23

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"Done!"
	.size	.L.str.3, 6

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z17verticalOperationiPfS_"
	.size	.L__unnamed_1, 27

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z32__device_stub__verticalOperationiPfS_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z17verticalOperationiPfS_
	.addrsig_sym _ZSt4cout
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z17verticalOperationiPfS_ ; -- Begin function _Z17verticalOperationiPfS_
	.globl	_Z17verticalOperationiPfS_
	.p2align	8
	.type	_Z17verticalOperationiPfS_,@function
_Z17verticalOperationiPfS_:             ; @_Z17verticalOperationiPfS_
; %bb.0:
	s_clause 0x1
	s_load_b32 s3, s[0:1], 0x24
	s_load_b128 s[4:7], s[0:1], 0x8
	s_mov_b32 s2, s15
	s_load_b32 s0, s[0:1], 0x18
	s_waitcnt lgkmcnt(0)
	s_and_b32 s3, s3, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
	s_cmp_eq_u32 s3, 0
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[1:2]
	v_add_co_u32 v4, vcc_lo, s4, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
	global_load_b32 v5, v[4:5], off
	v_lshl_add_u32 v4, v0, 2, 0
	s_waitcnt vmcnt(0)
	ds_store_b32 v4, v5
	s_waitcnt vmcnt(0) lgkmcnt(0)
	s_waitcnt_vscnt null, 0x0
.LBB0_1:                                ; =>This Inner Loop Header: Depth=1
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB0_6
; %bb.2:                                ; %.lr.ph
                                        ;   in Loop: Header=BB0_1 Depth=1
	s_mov_b32 s1, s3
	s_lshr_b32 s3, s3, 1
	s_mov_b32 s4, exec_lo
	v_cmpx_gt_u32_e64 s3, v0
	s_cbranch_execz .LBB0_5
; %bb.3:                                ;   in Loop: Header=BB0_1 Depth=1
	v_lshl_add_u32 v5, s3, 2, v4
	ds_load_b32 v5, v5
	ds_load_b32 v6, v4
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_f32_e32 vcc_lo, v5, v6
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_5
; %bb.4:                                ;   in Loop: Header=BB0_1 Depth=1
	ds_store_b32 v4, v5
.LBB0_5:                                ;   in Loop: Header=BB0_1 Depth=1
	s_or_b32 exec_lo, exec_lo, s4
	s_waitcnt lgkmcnt(0)
	s_cmp_lt_u32 s1, 2
	s_branch .LBB0_1
.LBB0_6:                                ; %._crit_edge
	s_mov_b32 s1, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB0_8
; %bb.7:
	v_mov_b32_e32 v0, 0
	s_mov_b32 s3, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[2:3], s[2:3], 2
	s_add_u32 s2, s6, s2
	ds_load_b32 v4, v0
	s_addc_u32 s3, s7, s3
	s_waitcnt lgkmcnt(0)
	global_store_b32 v0, v4, s[2:3]
.LBB0_8:
	s_or_b32 exec_lo, exec_lo, s1
	s_cmp_lt_i32 s0, 1
	s_cbranch_scc1 .LBB0_14
; %bb.9:                                ; %.lr.ph33
	v_add_co_u32 v2, vcc_lo, s6, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
	s_mov_b32 s1, 0
.LBB0_10:                               ; =>This Inner Loop Header: Depth=1
	s_mov_b32 s2, s0
	s_lshr_b32 s0, s0, 1
	s_mov_b32 s3, exec_lo
	v_cmpx_gt_i32_e64 s0, v1
	s_cbranch_execz .LBB0_13
; %bb.11:                               ;   in Loop: Header=BB0_10 Depth=1
	s_lshl_b64 s[4:5], s[0:1], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	v_add_co_u32 v4, vcc_lo, v2, s4
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
	s_clause 0x1
	global_load_b32 v0, v[4:5], off
	global_load_b32 v4, v[2:3], off
	s_waitcnt vmcnt(0)
	v_cmp_gt_f32_e32 vcc_lo, v0, v4
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_13
; %bb.12:                               ;   in Loop: Header=BB0_10 Depth=1
	global_store_b32 v[2:3], v0, off
.LBB0_13:                               ;   in Loop: Header=BB0_10 Depth=1
	s_or_b32 exec_lo, exec_lo, s3
	s_cmp_lt_u32 s2, 2
	s_cbranch_scc0 .LBB0_10
.LBB0_14:                               ; %._crit_edge34
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z17verticalOperationiPfS_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 7
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z17verticalOperationiPfS_, .Lfunc_end0-_Z17verticalOperationiPfS_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 432
; NumSgprs: 18
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         144
        .size:           4
        .value_kind:     hidden_dynamic_lds_size
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z17verticalOperationiPfS_
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z17verticalOperationiPfS_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     7
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
