#include <iostream>
#include <cuda.h>
#include <math.h>
#include <fstream>
using namespace std;

#define BLOCKSIZE 32

//test code
/*void mat(const float*A , const float* B, float* C, const int N, const int M, const int K) {
    int i,j,l;
    #pragma omp parallel for shared(A,B,C) private(i,j,l)
    for(i=0; i<N; i++) {
        for(l=0; l<M; l++) {
            float a  = A[M*i+l];
            for(j=0; j<K; j++) {
                C[K*i + j] += a*B[K*l+j];
            }
        }
    }
}*/

__global__ void nmfw(float *a, int r, int c, int k, float *w, float *h, float *wcp)//must be block synchronized!!!
{
	int row = blockIdx.y*blockDim.y + threadIdx.y;
	int col = blockIdx.x*blockDim.x + threadIdx.x;
	
	//compute W
	if (col < k && row < r) {
		//ah'
		float sum = 0.0;
		float temp = 0.0;
		for (int i = 0; i < c; i++)
			sum += a[row*c + i]*h[col*c + i];
		temp =  w[row*k+col]*sum;
		//whh'
		sum = 0.0;
		for (int i = 0; i < c; i++) {
			for (int j = 0; j < k; j++) {
				sum += w[row*k + j]*h[j*c + i]*h[col*c+i];
			}
		}
		__syncthreads();
		wcp[row*k+col] = temp/sum;
	}
}

__global__ void nmfh(float *a, int r, int c, int k, float *w, float *h, float *hcp)//must be block synchronized!!!
{
	int row = blockIdx.y*blockDim.y + threadIdx.y;
	int col = blockIdx.x*blockDim.x + threadIdx.x;
	
	//compute H
	if (row < k && col < c) {
		//w'a
		float temp = 0.0;
		float sum;
		sum = 0.0;
		for (int i = 0; i < r; i++)
			sum += w[i*k + row]*a[i*c+col];

		temp = h[row*c+col]*sum;
		//w'wh
		sum = 0.0;
		for (int i = 0; i < k; i++)
			for (int j = 0; j < r; j++) 
				sum += w[j*k + row]*w[j*k + i]*h[i*c+col];

		__syncthreads();		
		hcp[row*c+col] = temp/sum;
	}
}

__global__ void nmfcpy(float *mat, float *matcp, int m, int n) //kernel copy must be block synchronized!!!
{
	int row = blockIdx.y*blockDim.y + threadIdx.y;
	int col = blockIdx.x*blockDim.x + threadIdx.x;
	
	if (row < m && col < n)
		mat[row*n+col] = matcp[row*n+col];
}

void nmfgpu(float *a, int r, int c, int k, int niters, float *w, float *h)
{
	const dim3 block(BLOCKSIZE, BLOCKSIZE);
	const dim3 grid((c + BLOCKSIZE - 1)/ BLOCKSIZE,(r + BLOCKSIZE - 1)/ BLOCKSIZE);
	//initialize
	float *dev_w, *dev_h, *dev_a, *dev_wcp, *dev_hcp; 
	cudaMalloc((void**)&dev_w, sizeof(float)*r*k);
	cudaMalloc((void**)&dev_h, sizeof(float)*k*c);
	cudaMalloc((void**)&dev_wcp, sizeof(float)*r*k);
	cudaMalloc((void**)&dev_hcp, sizeof(float)*k*c);
	cudaMalloc((void**)&dev_a, sizeof(float)*r*c);
	cudaMemcpy(dev_w, w, sizeof(float)*r*k, cudaMemcpyHostToDevice);
	cudaMemcpy(dev_h, h, sizeof(float)*k*c, cudaMemcpyHostToDevice);
	cudaMemcpy(dev_a, a, sizeof(float)*r*c, cudaMemcpyHostToDevice);
	//
	//kernel
	for (int i=0; i<niters; i++) { //slow way
		nmfw<<<grid, block>>>(dev_a, r, c, k, dev_w, dev_h, dev_wcp);
		nmfcpy<<<grid, block>>>(dev_w, dev_wcp, r, k);
		nmfh<<<grid, block>>>(dev_a, r, c, k, dev_w, dev_h, dev_hcp);
		nmfcpy<<<grid, block>>>(dev_h, dev_hcp, k, c);
	}
	
	//cpy back
	cudaMemcpy(w, dev_w, sizeof(float)*r*k, cudaMemcpyDeviceToHost);
	cudaMemcpy(h, dev_h, sizeof(float)*k*c, cudaMemcpyDeviceToHost);

	//clean up
	cudaFree(dev_w);
	cudaFree(dev_h);
	cudaFree(dev_a);
}

//test code, u can test it if u want
/*int main()
{
	srand(1000);
	float *w, *h;
	const int r = 194;
	int k = 50;

	const int c = 259;

	w = new float[r*k];
	h = new float[k*c];

	float a[r*c];
	ifstream file("af.txt");
	for (int i = 0; i < 194 * 259; i++)
		file >> a[i];
	
	for (int i = 0; i < r*k; i++)
	{
		w[i] = (float)rand()/RAND_MAX;
	}
	for (int i = 0; i < k*c; i++)
	{
		h[i] = (float)rand()/RAND_MAX;
	}

	nmfgpu(a, r, c, k, 100, w, h);
	
	float *res = new float[r*c];

	for (int i = 0; i<r*c; i++)
		res[i] = 0;

	mat(w,h,res,r,k,c);
	
	ofstream output("result.txt");

	for (int i=0; i < r; i++) {
		for (int j=0; j <c; j++)
			output << res[i*c+j] << " ";
		output << "\n";
	}
	
	
}*/

	.file	"tmpxft_0029d93f_00000000-6_nmfgpu.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3769:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3769:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z32__device_stub__Z4nmfwPfiiiS_S_S_PfiiiS_S_S_
	.type	_Z32__device_stub__Z4nmfwPfiiiS_S_S_PfiiiS_S_S_, @function
_Z32__device_stub__Z4nmfwPfiiiS_S_S_PfiiiS_S_S_:
.LFB3791:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	192(%rsp), %rax
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movl	%esi, 36(%rsp)
	leaq	76(%rsp), %rsi
	movl	%edx, 32(%rsp)
	leaq	48(%rsp), %rdx
	movl	%ecx, 28(%rsp)
	leaq	56(%rsp), %rcx
	movq	%r8, 16(%rsp)
	movq	%r9, 8(%rsp)
	movq	%rax, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 112(%rsp)
	leaq	36(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	28(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 152(%rsp)
	movq	%rsp, %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	56(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z4nmfwPfiiiS_S_S_(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 208
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L2:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3791:
	.size	_Z32__device_stub__Z4nmfwPfiiiS_S_S_PfiiiS_S_S_, .-_Z32__device_stub__Z4nmfwPfiiiS_S_S_PfiiiS_S_S_
	.globl	_Z4nmfwPfiiiS_S_S_
	.type	_Z4nmfwPfiiiS_S_S_, @function
_Z4nmfwPfiiiS_S_S_:
.LFB3792:
	.cfi_startproc
	endbr64
	jmp	_Z32__device_stub__Z4nmfwPfiiiS_S_S_PfiiiS_S_S_
	.cfi_endproc
.LFE3792:
	.size	_Z4nmfwPfiiiS_S_S_, .-_Z4nmfwPfiiiS_S_S_
	.globl	_Z32__device_stub__Z4nmfhPfiiiS_S_S_PfiiiS_S_S_
	.type	_Z32__device_stub__Z4nmfhPfiiiS_S_S_PfiiiS_S_S_, @function
_Z32__device_stub__Z4nmfhPfiiiS_S_S_PfiiiS_S_S_:
.LFB3793:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	192(%rsp), %rax
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movl	%esi, 36(%rsp)
	leaq	76(%rsp), %rsi
	movl	%edx, 32(%rsp)
	leaq	48(%rsp), %rdx
	movl	%ecx, 28(%rsp)
	leaq	56(%rsp), %rcx
	movq	%r8, 16(%rsp)
	movq	%r9, 8(%rsp)
	movq	%rax, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 112(%rsp)
	leaq	36(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	28(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 152(%rsp)
	movq	%rsp, %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L8
	pushq	56(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z4nmfhPfiiiS_S_S_(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 208
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L8:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L10
	call	__stack_chk_fail@PLT
.L10:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3793:
	.size	_Z32__device_stub__Z4nmfhPfiiiS_S_S_PfiiiS_S_S_, .-_Z32__device_stub__Z4nmfhPfiiiS_S_S_PfiiiS_S_S_
	.globl	_Z4nmfhPfiiiS_S_S_
	.type	_Z4nmfhPfiiiS_S_S_, @function
_Z4nmfhPfiiiS_S_S_:
.LFB3794:
	.cfi_startproc
	endbr64
	jmp	_Z32__device_stub__Z4nmfhPfiiiS_S_S_PfiiiS_S_S_
	.cfi_endproc
.LFE3794:
	.size	_Z4nmfhPfiiiS_S_S_, .-_Z4nmfhPfiiiS_S_S_
	.globl	_Z29__device_stub__Z6nmfcpyPfS_iiPfS_ii
	.type	_Z29__device_stub__Z6nmfcpyPfS_iiPfS_ii, @function
_Z29__device_stub__Z6nmfcpyPfS_iiPfS_ii:
.LFB3795:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L13
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z6nmfcpyPfS_ii(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L13:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L15
	call	__stack_chk_fail@PLT
.L15:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3795:
	.size	_Z29__device_stub__Z6nmfcpyPfS_iiPfS_ii, .-_Z29__device_stub__Z6nmfcpyPfS_iiPfS_ii
	.globl	_Z6nmfcpyPfS_ii
	.type	_Z6nmfcpyPfS_ii, @function
_Z6nmfcpyPfS_ii:
.LFB3796:
	.cfi_startproc
	endbr64
	jmp	_Z29__device_stub__Z6nmfcpyPfS_iiPfS_ii
	.cfi_endproc
.LFE3796:
	.size	_Z6nmfcpyPfS_ii, .-_Z6nmfcpyPfS_ii
	.globl	_Z6nmfgpuPfiiiiS_S_
	.type	_Z6nmfgpuPfiiiiS_S_, @function
_Z6nmfgpuPfiiiiS_S_:
.LFB3766:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	movl	%r8d, %r14d
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movslq	%edx, %r13
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movl	%ecx, %r12d
	movl	$32, %ecx
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movq	%r13, %rbp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movl	%esi, %ebx
	subq	$136, %rsp
	.cfi_def_cfa_offset 192
	movq	192(%rsp), %rax
	movq	%r9, 16(%rsp)
	movq	%rdi, 32(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rax, 24(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	movabsq	$137438953504, %rax
	movl	$1, 104(%rsp)
	movl	$1, 116(%rsp)
	movq	%rax, 96(%rsp)
	leal	31(%r13), %eax
	cltd
	idivl	%ecx
	movl	%eax, 108(%rsp)
	leal	31(%rsi), %eax
	cltd
	idivl	%ecx
	movslq	%esi, %rdx
	movslq	%r12d, %rcx
	leaq	0(,%rcx,4), %r15
	movq	%rdx, 40(%rsp)
	movl	%eax, 112(%rsp)
	movq	%rdx, %rax
	imulq	%r15, %rax
	imulq	%r13, %r15
	movq	%rax, %rsi
	movq	%rax, (%rsp)
	call	cudaMalloc@PLT
	movq	%r15, %rsi
	leaq	64(%rsp), %rdi
	movq	%r15, 8(%rsp)
	call	cudaMalloc@PLT
	movq	(%rsp), %rsi
	leaq	80(%rsp), %rdi
	call	cudaMalloc@PLT
	movq	8(%rsp), %rsi
	leaq	88(%rsp), %rdi
	call	cudaMalloc@PLT
	movq	40(%rsp), %rdx
	leaq	72(%rsp), %rdi
	imulq	%r13, %rdx
	leaq	0(,%rdx,4), %rax
	movq	%rax, %rsi
	movq	%rax, %r15
	call	cudaMalloc@PLT
	movq	(%rsp), %rdx
	movq	16(%rsp), %rsi
	movl	$1, %ecx
	movq	56(%rsp), %rdi
	call	cudaMemcpy@PLT
	movq	8(%rsp), %rdx
	movq	24(%rsp), %rsi
	movl	$1, %ecx
	movq	64(%rsp), %rdi
	call	cudaMemcpy@PLT
	movq	32(%rsp), %rsi
	movq	72(%rsp), %rdi
	movq	%r15, %rdx
	movl	$1, %ecx
	xorl	%r15d, %r15d
	call	cudaMemcpy@PLT
.L19:
	cmpl	%r14d, %r15d
	jge	.L27
	movl	104(%rsp), %ecx
	movq	96(%rsp), %rdx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	108(%rsp), %rdi
	movl	116(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L20
	pushq	%rsi
	.cfi_def_cfa_offset 200
	movl	%r12d, %ecx
	movl	%ebp, %edx
	movl	%ebx, %esi
	pushq	88(%rsp)
	.cfi_def_cfa_offset 208
	movq	80(%rsp), %r9
	movq	72(%rsp), %r8
	movq	88(%rsp), %rdi
	call	_Z32__device_stub__Z4nmfwPfiiiS_S_S_PfiiiS_S_S_
	popq	%rdi
	.cfi_def_cfa_offset 200
	popq	%r8
	.cfi_def_cfa_offset 192
.L20:
	movl	104(%rsp), %ecx
	movq	96(%rsp), %rdx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	108(%rsp), %rdi
	movl	116(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L21
	movq	80(%rsp), %rsi
	movq	56(%rsp), %rdi
	movl	%r12d, %ecx
	movl	%ebx, %edx
	call	_Z29__device_stub__Z6nmfcpyPfS_iiPfS_ii
.L21:
	movl	104(%rsp), %ecx
	movq	96(%rsp), %rdx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	108(%rsp), %rdi
	movl	116(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L22
	pushq	%rax
	.cfi_def_cfa_offset 200
	movl	%r12d, %ecx
	movl	%ebp, %edx
	movl	%ebx, %esi
	pushq	96(%rsp)
	.cfi_def_cfa_offset 208
	movq	80(%rsp), %r9
	movq	72(%rsp), %r8
	movq	88(%rsp), %rdi
	call	_Z32__device_stub__Z4nmfhPfiiiS_S_S_PfiiiS_S_S_
	popq	%rdx
	.cfi_def_cfa_offset 200
	popq	%rcx
	.cfi_def_cfa_offset 192
.L22:
	movl	104(%rsp), %ecx
	movq	96(%rsp), %rdx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	108(%rsp), %rdi
	movl	116(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L23
	movq	88(%rsp), %rsi
	movq	64(%rsp), %rdi
	movl	%ebp, %ecx
	movl	%r12d, %edx
	call	_Z29__device_stub__Z6nmfcpyPfS_iiPfS_ii
.L23:
	incl	%r15d
	jmp	.L19
.L27:
	movq	(%rsp), %rdx
	movq	56(%rsp), %rsi
	movl	$2, %ecx
	movq	16(%rsp), %rdi
	call	cudaMemcpy@PLT
	movq	8(%rsp), %rdx
	movq	64(%rsp), %rsi
	movl	$2, %ecx
	movq	24(%rsp), %rdi
	call	cudaMemcpy@PLT
	movq	56(%rsp), %rdi
	call	cudaFree@PLT
	movq	64(%rsp), %rdi
	call	cudaFree@PLT
	movq	72(%rsp), %rdi
	call	cudaFree@PLT
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L25
	call	__stack_chk_fail@PLT
.L25:
	addq	$136, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3766:
	.size	_Z6nmfgpuPfiiiiS_S_, .-_Z6nmfgpuPfiiiiS_S_
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z6nmfcpyPfS_ii"
.LC1:
	.string	"_Z4nmfhPfiiiS_S_S_"
.LC2:
	.string	"_Z4nmfwPfiiiS_S_S_"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3798:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z6nmfcpyPfS_ii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC1(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z4nmfhPfiiiS_S_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC2(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z4nmfwPfiiiS_S_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3798:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <iostream>
#include <hip/hip_runtime.h>
#include <math.h>
#include <fstream>
using namespace std;

#define BLOCKSIZE 32

//test code
/*void mat(const float*A , const float* B, float* C, const int N, const int M, const int K) {
    int i,j,l;
    #pragma omp parallel for shared(A,B,C) private(i,j,l)
    for(i=0; i<N; i++) {
        for(l=0; l<M; l++) {
            float a  = A[M*i+l];
            for(j=0; j<K; j++) {
                C[K*i + j] += a*B[K*l+j];
            }
        }
    }
}*/

__global__ void nmfw(float *a, int r, int c, int k, float *w, float *h, float *wcp)//must be block synchronized!!!
{
	int row = blockIdx.y*blockDim.y + threadIdx.y;
	int col = blockIdx.x*blockDim.x + threadIdx.x;
	
	//compute W
	if (col < k && row < r) {
		//ah'
		float sum = 0.0;
		float temp = 0.0;
		for (int i = 0; i < c; i++)
			sum += a[row*c + i]*h[col*c + i];
		temp =  w[row*k+col]*sum;
		//whh'
		sum = 0.0;
		for (int i = 0; i < c; i++) {
			for (int j = 0; j < k; j++) {
				sum += w[row*k + j]*h[j*c + i]*h[col*c+i];
			}
		}
		__syncthreads();
		wcp[row*k+col] = temp/sum;
	}
}

__global__ void nmfh(float *a, int r, int c, int k, float *w, float *h, float *hcp)//must be block synchronized!!!
{
	int row = blockIdx.y*blockDim.y + threadIdx.y;
	int col = blockIdx.x*blockDim.x + threadIdx.x;
	
	//compute H
	if (row < k && col < c) {
		//w'a
		float temp = 0.0;
		float sum;
		sum = 0.0;
		for (int i = 0; i < r; i++)
			sum += w[i*k + row]*a[i*c+col];

		temp = h[row*c+col]*sum;
		//w'wh
		sum = 0.0;
		for (int i = 0; i < k; i++)
			for (int j = 0; j < r; j++) 
				sum += w[j*k + row]*w[j*k + i]*h[i*c+col];

		__syncthreads();		
		hcp[row*c+col] = temp/sum;
	}
}

__global__ void nmfcpy(float *mat, float *matcp, int m, int n) //kernel copy must be block synchronized!!!
{
	int row = blockIdx.y*blockDim.y + threadIdx.y;
	int col = blockIdx.x*blockDim.x + threadIdx.x;
	
	if (row < m && col < n)
		mat[row*n+col] = matcp[row*n+col];
}

void nmfgpu(float *a, int r, int c, int k, int niters, float *w, float *h)
{
	const dim3 block(BLOCKSIZE, BLOCKSIZE);
	const dim3 grid((c + BLOCKSIZE - 1)/ BLOCKSIZE,(r + BLOCKSIZE - 1)/ BLOCKSIZE);
	//initialize
	float *dev_w, *dev_h, *dev_a, *dev_wcp, *dev_hcp; 
	hipMalloc((void**)&dev_w, sizeof(float)*r*k);
	hipMalloc((void**)&dev_h, sizeof(float)*k*c);
	hipMalloc((void**)&dev_wcp, sizeof(float)*r*k);
	hipMalloc((void**)&dev_hcp, sizeof(float)*k*c);
	hipMalloc((void**)&dev_a, sizeof(float)*r*c);
	hipMemcpy(dev_w, w, sizeof(float)*r*k, hipMemcpyHostToDevice);
	hipMemcpy(dev_h, h, sizeof(float)*k*c, hipMemcpyHostToDevice);
	hipMemcpy(dev_a, a, sizeof(float)*r*c, hipMemcpyHostToDevice);
	//
	//kernel
	for (int i=0; i<niters; i++) { //slow way
		nmfw<<<grid, block>>>(dev_a, r, c, k, dev_w, dev_h, dev_wcp);
		nmfcpy<<<grid, block>>>(dev_w, dev_wcp, r, k);
		nmfh<<<grid, block>>>(dev_a, r, c, k, dev_w, dev_h, dev_hcp);
		nmfcpy<<<grid, block>>>(dev_h, dev_hcp, k, c);
	}
	
	//cpy back
	hipMemcpy(w, dev_w, sizeof(float)*r*k, hipMemcpyDeviceToHost);
	hipMemcpy(h, dev_h, sizeof(float)*k*c, hipMemcpyDeviceToHost);

	//clean up
	hipFree(dev_w);
	hipFree(dev_h);
	hipFree(dev_a);
}

//test code, u can test it if u want
/*int main()
{
	srand(1000);
	float *w, *h;
	const int r = 194;
	int k = 50;

	const int c = 259;

	w = new float[r*k];
	h = new float[k*c];

	float a[r*c];
	ifstream file("af.txt");
	for (int i = 0; i < 194 * 259; i++)
		file >> a[i];
	
	for (int i = 0; i < r*k; i++)
	{
		w[i] = (float)rand()/RAND_MAX;
	}
	for (int i = 0; i < k*c; i++)
	{
		h[i] = (float)rand()/RAND_MAX;
	}

	nmfgpu(a, r, c, k, 100, w, h);
	
	float *res = new float[r*c];

	for (int i = 0; i<r*c; i++)
		res[i] = 0;

	mat(w,h,res,r,k,c);
	
	ofstream output("result.txt");

	for (int i=0; i < r; i++) {
		for (int j=0; j <c; j++)
			output << res[i*c+j] << " ";
		output << "\n";
	}
	
	
}*/

	.text
	.file	"nmfgpu.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z19__device_stub__nmfwPfiiiS_S_S_ # -- Begin function _Z19__device_stub__nmfwPfiiiS_S_S_
	.type	_Z19__device_stub__nmfwPfiiiS_S_S_,@function
_Z19__device_stub__nmfwPfiiiS_S_S_:     # @_Z19__device_stub__nmfwPfiiiS_S_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	20(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	16(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	12(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	48(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	40(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z4nmfwPfiiiS_S_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z19__device_stub__nmfwPfiiiS_S_S_, .Lfunc_end0-_Z19__device_stub__nmfwPfiiiS_S_S_
	.cfi_endproc
                                        # -- End function
	.globl	_Z19__device_stub__nmfhPfiiiS_S_S_ # -- Begin function _Z19__device_stub__nmfhPfiiiS_S_S_
	.type	_Z19__device_stub__nmfhPfiiiS_S_S_,@function
_Z19__device_stub__nmfhPfiiiS_S_S_:     # @_Z19__device_stub__nmfhPfiiiS_S_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	20(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	16(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	12(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	48(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	40(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z4nmfhPfiiiS_S_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z19__device_stub__nmfhPfiiiS_S_S_, .Lfunc_end1-_Z19__device_stub__nmfhPfiiiS_S_S_
	.cfi_endproc
                                        # -- End function
	.globl	_Z21__device_stub__nmfcpyPfS_ii # -- Begin function _Z21__device_stub__nmfcpyPfS_ii
	.type	_Z21__device_stub__nmfcpyPfS_ii,@function
_Z21__device_stub__nmfcpyPfS_ii:        # @_Z21__device_stub__nmfcpyPfS_ii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z6nmfcpyPfS_ii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z21__device_stub__nmfcpyPfS_ii, .Lfunc_end2-_Z21__device_stub__nmfcpyPfS_ii
	.cfi_endproc
                                        # -- End function
	.globl	_Z6nmfgpuPfiiiiS_S_             # -- Begin function _Z6nmfgpuPfiiiiS_S_
	.type	_Z6nmfgpuPfiiiiS_S_,@function
_Z6nmfgpuPfiiiiS_S_:                    # @_Z6nmfgpuPfiiiiS_S_
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$104, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%r9, 64(%rsp)                   # 8-byte Spill
	movl	%r8d, %ebp
	movl	%ecx, %r15d
	movl	%edx, %r12d
	movl	%esi, %r13d
	movq	%rdi, 96(%rsp)                  # 8-byte Spill
	leal	31(%r12), %eax
	leal	62(%r12), %ecx
	testl	%eax, %eax
	cmovnsl	%eax, %ecx
	movq	%rcx, 88(%rsp)                  # 8-byte Spill
	leal	31(%r13), %eax
	leal	62(%r13), %r14d
	testl	%eax, %eax
	cmovnsl	%eax, %r14d
	movslq	%esi, %rax
	shlq	$2, %rax
	movq	%rax, 48(%rsp)                  # 8-byte Spill
	movslq	%r15d, %rbx
	movq	%rax, %rsi
	imulq	%rbx, %rsi
	movq	%rsi, 56(%rsp)                  # 8-byte Spill
	leaq	24(%rsp), %rdi
	callq	hipMalloc
	movslq	%r12d, %rax
	movq	%rax, 40(%rsp)                  # 8-byte Spill
	imulq	%rax, %rbx
	shlq	$2, %rbx
	leaq	16(%rsp), %rdi
	movq	%rbx, %rsi
	callq	hipMalloc
	leaq	80(%rsp), %rdi
	movq	56(%rsp), %rsi                  # 8-byte Reload
	callq	hipMalloc
	leaq	72(%rsp), %rdi
	movq	%rbx, %rsi
	callq	hipMalloc
	movq	48(%rsp), %rsi                  # 8-byte Reload
	imulq	40(%rsp), %rsi                  # 8-byte Folded Reload
	movq	%rsi, 48(%rsp)                  # 8-byte Spill
	leaq	32(%rsp), %rdi
	callq	hipMalloc
	leaq	24(%rsp), %rax
	movq	(%rax), %rdi
	movq	64(%rsp), %rsi                  # 8-byte Reload
	movq	56(%rsp), %rdx                  # 8-byte Reload
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	16(%rsp), %rax
	movq	(%rax), %rdi
	movq	160(%rsp), %rsi
	movq	%rbx, 40(%rsp)                  # 8-byte Spill
	movq	%rbx, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	32(%rsp), %rax
	movq	(%rax), %rdi
	movq	96(%rsp), %rsi                  # 8-byte Reload
	movq	48(%rsp), %rdx                  # 8-byte Reload
	movl	$1, %ecx
	callq	hipMemcpy
	testl	%ebp, %ebp
	jle	.LBB3_11
# %bb.1:                                # %.lr.ph.preheader
	movq	88(%rsp), %rax                  # 8-byte Reload
	sarl	$5, %eax
	sarl	$5, %r14d
	shlq	$32, %r14
	orq	%rax, %r14
	movabsq	$137438953504, %rbx             # imm = 0x2000000020
.LBB3_2:                                # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	movq	%r14, %rdi
	movl	$1, %esi
	movq	%rbx, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB3_4
# %bb.3:                                #   in Loop: Header=BB3_2 Depth=1
	movq	32(%rsp), %rdi
	movq	24(%rsp), %r8
	movq	16(%rsp), %r9
	movq	80(%rsp), %rax
	movq	%rax, (%rsp)
	movl	%r13d, %esi
	movl	%r12d, %edx
	movl	%r15d, %ecx
	callq	_Z19__device_stub__nmfwPfiiiS_S_S_
.LBB3_4:                                #   in Loop: Header=BB3_2 Depth=1
	movq	%r14, %rdi
	movl	$1, %esi
	movq	%rbx, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB3_6
# %bb.5:                                #   in Loop: Header=BB3_2 Depth=1
	movq	24(%rsp), %rdi
	movq	80(%rsp), %rsi
	movl	%r13d, %edx
	movl	%r15d, %ecx
	callq	_Z21__device_stub__nmfcpyPfS_ii
.LBB3_6:                                #   in Loop: Header=BB3_2 Depth=1
	movq	%r14, %rdi
	movl	$1, %esi
	movq	%rbx, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB3_8
# %bb.7:                                #   in Loop: Header=BB3_2 Depth=1
	movq	32(%rsp), %rdi
	movq	24(%rsp), %r8
	movq	16(%rsp), %r9
	movq	72(%rsp), %rax
	movq	%rax, (%rsp)
	movl	%r13d, %esi
	movl	%r12d, %edx
	movl	%r15d, %ecx
	callq	_Z19__device_stub__nmfhPfiiiS_S_S_
.LBB3_8:                                #   in Loop: Header=BB3_2 Depth=1
	movq	%r14, %rdi
	movl	$1, %esi
	movq	%rbx, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB3_10
# %bb.9:                                #   in Loop: Header=BB3_2 Depth=1
	movq	16(%rsp), %rdi
	movq	72(%rsp), %rsi
	movl	%r15d, %edx
	movl	%r12d, %ecx
	callq	_Z21__device_stub__nmfcpyPfS_ii
.LBB3_10:                               #   in Loop: Header=BB3_2 Depth=1
	decl	%ebp
	jne	.LBB3_2
.LBB3_11:                               # %._crit_edge
	movq	24(%rsp), %rsi
	movq	64(%rsp), %rdi                  # 8-byte Reload
	movq	56(%rsp), %rdx                  # 8-byte Reload
	movl	$2, %ecx
	callq	hipMemcpy
	movq	16(%rsp), %rsi
	movq	160(%rsp), %rdi
	movq	40(%rsp), %rdx                  # 8-byte Reload
	movl	$2, %ecx
	callq	hipMemcpy
	movq	24(%rsp), %rdi
	callq	hipFree
	movq	16(%rsp), %rdi
	callq	hipFree
	movq	32(%rsp), %rdi
	callq	hipFree
	addq	$104, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	_Z6nmfgpuPfiiiiS_S_, .Lfunc_end3-_Z6nmfgpuPfiiiiS_S_
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB4_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB4_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z4nmfwPfiiiS_S_S_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z4nmfhPfiiiS_S_S_, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z6nmfcpyPfS_ii, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end4:
	.size	__hip_module_ctor, .Lfunc_end4-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB5_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB5_2:
	retq
.Lfunc_end5:
	.size	__hip_module_dtor, .Lfunc_end5-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z4nmfwPfiiiS_S_S_,@object      # @_Z4nmfwPfiiiS_S_S_
	.section	.rodata,"a",@progbits
	.globl	_Z4nmfwPfiiiS_S_S_
	.p2align	3, 0x0
_Z4nmfwPfiiiS_S_S_:
	.quad	_Z19__device_stub__nmfwPfiiiS_S_S_
	.size	_Z4nmfwPfiiiS_S_S_, 8

	.type	_Z4nmfhPfiiiS_S_S_,@object      # @_Z4nmfhPfiiiS_S_S_
	.globl	_Z4nmfhPfiiiS_S_S_
	.p2align	3, 0x0
_Z4nmfhPfiiiS_S_S_:
	.quad	_Z19__device_stub__nmfhPfiiiS_S_S_
	.size	_Z4nmfhPfiiiS_S_S_, 8

	.type	_Z6nmfcpyPfS_ii,@object         # @_Z6nmfcpyPfS_ii
	.globl	_Z6nmfcpyPfS_ii
	.p2align	3, 0x0
_Z6nmfcpyPfS_ii:
	.quad	_Z21__device_stub__nmfcpyPfS_ii
	.size	_Z6nmfcpyPfS_ii, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z4nmfwPfiiiS_S_S_"
	.size	.L__unnamed_1, 19

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z4nmfhPfiiiS_S_S_"
	.size	.L__unnamed_2, 19

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z6nmfcpyPfS_ii"
	.size	.L__unnamed_3, 16

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z19__device_stub__nmfwPfiiiS_S_S_
	.addrsig_sym _Z19__device_stub__nmfhPfiiiS_S_S_
	.addrsig_sym _Z21__device_stub__nmfcpyPfS_ii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z4nmfwPfiiiS_S_S_
	.addrsig_sym _Z4nmfhPfiiiS_S_S_
	.addrsig_sym _Z6nmfcpyPfS_ii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z4nmfwPfiiiS_S_S_      ; -- Begin function _Z4nmfwPfiiiS_S_S_
	.globl	_Z4nmfwPfiiiS_S_S_
	.p2align	8
	.type	_Z4nmfwPfiiiS_S_S_,@function
_Z4nmfwPfiiiS_S_S_:                     ; @_Z4nmfwPfiiiS_S_S_
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x3c
	s_load_b128 s[4:7], s[0:1], 0x8
	v_and_b32_e32 v1, 0x3ff, v0
	v_bfe_u32 v0, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s2, 16
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[2:3], null, s14, s2, v[1:2]
	v_mad_u64_u32 v[3:4], null, s15, s3, v[0:1]
	v_cmp_gt_i32_e32 vcc_lo, s6, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_gt_i32_e64 s2, s4, v3
	s_and_b32 s2, s2, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_13
; %bb.1:                                ; %.preheader58
	s_clause 0x1
	s_load_b128 s[8:11], s[0:1], 0x18
	s_load_b64 s[2:3], s[0:1], 0x28
	v_mul_lo_u32 v0, v2, s5
	s_cmp_gt_i32 s5, 0
	s_cselect_b32 s4, -1, 0
	s_cmp_lt_i32 s5, 1
	s_cbranch_scc1 .LBB0_4
; %bb.2:                                ; %.lr.ph
	s_load_b64 s[0:1], s[0:1], 0x0
	v_mul_lo_u32 v4, v3, s5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v1, 31, v0
	v_lshlrev_b64 v[6:7], 2, v[0:1]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v5, 31, v4
	v_lshlrev_b64 v[8:9], 2, v[4:5]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v4, vcc_lo, s10, v6
	v_add_co_ci_u32_e32 v5, vcc_lo, s11, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v6, vcc_lo, s0, v8
	v_add_co_ci_u32_e32 v7, vcc_lo, s1, v9, vcc_lo
	v_mov_b32_e32 v8, 0
	s_mov_b32 s0, s5
.LBB0_3:                                ; =>This Inner Loop Header: Depth=1
	global_load_b32 v1, v[6:7], off
	global_load_b32 v9, v[4:5], off
	v_add_co_u32 v4, vcc_lo, v4, 4
	v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
	v_add_co_u32 v6, vcc_lo, v6, 4
	v_add_co_ci_u32_e32 v7, vcc_lo, 0, v7, vcc_lo
	s_add_i32 s0, s0, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s0, 0
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v8, v1, v9
	s_cbranch_scc0 .LBB0_3
	s_branch .LBB0_5
.LBB0_4:
	v_mov_b32_e32 v8, 0
.LBB0_5:                                ; %._crit_edge
	v_mul_lo_u32 v3, v3, s6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v1, v3, v2
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v4, vcc_lo, s8, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s9, v2, vcc_lo
	s_and_not1_b32 vcc_lo, exec_lo, s4
	global_load_b32 v9, v[4:5], off
	s_cbranch_vccnz .LBB0_11
; %bb.6:                                ; %.preheader.lr.ph
	v_ashrrev_i32_e32 v4, 31, v3
	v_mov_b32_e32 v7, 0
	s_cmp_gt_i32 s6, 0
	s_mov_b32 s1, 0
	s_cselect_b32 s4, -1, 0
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	s_mov_b32 s7, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, s8, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s9, v4, vcc_lo
.LBB0_7:                                ; %.preheader
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_9 Depth 2
	s_and_not1_b32 vcc_lo, exec_lo, s4
	s_cbranch_vccnz .LBB0_10
; %bb.8:                                ; %.lr.ph63
                                        ;   in Loop: Header=BB0_7 Depth=1
	v_add_nc_u32_e32 v5, s7, v0
	s_mov_b32 s0, s7
	s_mov_b32 s8, s6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v6, 31, v5
	v_lshlrev_b64 v[5:6], 2, v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v5, vcc_lo, s10, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, s11, v6, vcc_lo
	global_load_b32 v10, v[5:6], off
	v_dual_mov_b32 v6, v4 :: v_dual_mov_b32 v5, v3
.LBB0_9:                                ;   Parent Loop BB0_7 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	global_load_b32 v11, v[5:6], off
	s_lshl_b64 s[12:13], s[0:1], 2
	v_add_co_u32 v5, vcc_lo, v5, 4
	s_add_u32 s12, s10, s12
	s_addc_u32 s13, s11, s13
	v_add_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
	s_load_b32 s9, s[12:13], 0x0
	s_add_i32 s8, s8, -1
	s_add_i32 s0, s0, s5
	s_cmp_eq_u32 s8, 0
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_mul_f32_e32 v11, s9, v11
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v7, v11, v10
	s_cbranch_scc0 .LBB0_9
.LBB0_10:                               ; %._crit_edge64
                                        ;   in Loop: Header=BB0_7 Depth=1
	s_add_i32 s7, s7, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s7, s5
	s_cbranch_scc0 .LBB0_7
	s_branch .LBB0_12
.LBB0_11:
	v_mov_b32_e32 v7, 0
.LBB0_12:                               ; %._crit_edge68
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v0, v8, v9
	s_barrier
	buffer_gl0_inv
	v_div_scale_f32 v3, null, v7, v7, v0
	v_div_scale_f32 v6, vcc_lo, v0, v7, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v4, v3
	s_waitcnt_depctr 0xfff
	v_fma_f32 v5, -v3, v4, 1.0
	v_fmac_f32_e32 v4, v5, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v5, v6, v4
	v_fma_f32 v8, -v3, v5, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v5, v8, v4
	v_fma_f32 v3, -v3, v5, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v3, v3, v4, v5
	v_div_fixup_f32 v3, v3, v7, v0
	v_add_co_u32 v0, vcc_lo, s2, v1
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v2, vcc_lo
	global_store_b32 v[0:1], v3, off
.LBB0_13:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z4nmfwPfiiiS_S_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 304
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 12
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z4nmfwPfiiiS_S_S_, .Lfunc_end0-_Z4nmfwPfiiiS_S_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 736
; NumSgprs: 18
; NumVgprs: 12
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 12
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z4nmfhPfiiiS_S_S_      ; -- Begin function _Z4nmfhPfiiiS_S_S_
	.globl	_Z4nmfhPfiiiS_S_S_
	.p2align	8
	.type	_Z4nmfhPfiiiS_S_S_,@function
_Z4nmfhPfiiiS_S_S_:                     ; @_Z4nmfhPfiiiS_S_S_
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x3c
	s_load_b128 s[4:7], s[0:1], 0x8
	v_bfe_u32 v2, v0, 10, 10
	v_and_b32_e32 v3, 0x3ff, v0
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s2, 16
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[0:1], null, s15, s3, v[2:3]
	v_mad_u64_u32 v[1:2], null, s14, s2, v[3:4]
	v_cmp_gt_i32_e32 vcc_lo, s6, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_gt_i32_e64 s2, s5, v1
	s_and_b32 s2, vcc_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB1_12
; %bb.1:                                ; %.preheader58
	s_clause 0x1
	s_load_b128 s[8:11], s[0:1], 0x18
	s_load_b64 s[2:3], s[0:1], 0x28
	s_cmp_gt_i32 s4, 0
	s_cselect_b32 s7, -1, 0
	s_cmp_lt_i32 s4, 1
	s_cbranch_scc1 .LBB1_4
; %bb.2:                                ; %.lr.ph.preheader
	s_load_b64 s[0:1], s[0:1], 0x0
	v_mov_b32_e32 v6, 0
	v_mov_b32_e32 v2, v0
	v_mov_b32_e32 v4, v1
	s_mov_b32 s12, s4
.LBB1_3:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v3, 31, v2
	v_ashrrev_i32_e32 v5, 31, v4
	s_add_i32 s12, s12, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	s_cmp_eq_u32 s12, 0
	v_lshlrev_b64 v[7:8], 2, v[2:3]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_lshlrev_b64 v[9:10], 2, v[4:5]
	v_add_nc_u32_e32 v4, s5, v4
	v_add_nc_u32_e32 v2, s6, v2
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v7, vcc_lo, s8, v7
	v_add_co_ci_u32_e32 v8, vcc_lo, s9, v8, vcc_lo
	v_add_co_u32 v9, vcc_lo, s0, v9
	v_add_co_ci_u32_e32 v10, vcc_lo, s1, v10, vcc_lo
	global_load_b32 v3, v[7:8], off
	global_load_b32 v5, v[9:10], off
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v6, v3, v5
	s_cbranch_scc0 .LBB1_3
	s_branch .LBB1_5
.LBB1_4:
	v_mov_b32_e32 v6, 0
.LBB1_5:                                ; %._crit_edge
	v_mad_u64_u32 v[2:3], null, v0, s5, v[1:2]
	s_cmp_lt_i32 s6, 1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, s10, v2
	v_add_co_ci_u32_e32 v5, vcc_lo, s11, v3, vcc_lo
	global_load_b32 v5, v[4:5], off
	v_mov_b32_e32 v4, 0
	s_cbranch_scc1 .LBB1_11
; %bb.6:                                ; %.preheader.preheader
	s_mov_b32 s1, 0
	s_mov_b32 s12, 0
.LBB1_7:                                ; %.preheader
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB1_9 Depth 2
	s_and_not1_b32 vcc_lo, exec_lo, s7
	s_cbranch_vccnz .LBB1_10
; %bb.8:                                ; %.lr.ph63
                                        ;   in Loop: Header=BB1_7 Depth=1
	v_mad_u64_u32 v[7:8], null, s12, s5, v[1:2]
	s_mov_b32 s13, 0
	s_mov_b32 s14, s4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v8, 31, v7
	v_lshlrev_b64 v[7:8], 2, v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v7, vcc_lo, s10, v7
	v_add_co_ci_u32_e32 v8, vcc_lo, s11, v8, vcc_lo
	global_load_b32 v7, v[7:8], off
.LBB1_9:                                ;   Parent Loop BB1_7 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_add_nc_u32_e32 v8, s13, v0
	s_add_i32 s0, s12, s13
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[16:17], s[0:1], 2
	s_add_u32 s16, s8, s16
	s_delay_alu instid0(VALU_DEP_1)
	v_ashrrev_i32_e32 v9, 31, v8
	s_addc_u32 s17, s9, s17
	s_add_i32 s14, s14, -1
	s_add_i32 s13, s13, s6
	s_cmp_eq_u32 s14, 0
	v_lshlrev_b64 v[8:9], 2, v[8:9]
	s_load_b32 s0, s[16:17], 0x0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v8, vcc_lo, s8, v8
	v_add_co_ci_u32_e32 v9, vcc_lo, s9, v9, vcc_lo
	global_load_b32 v8, v[8:9], off
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_mul_f32_e32 v8, s0, v8
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v4, v8, v7
	s_cbranch_scc0 .LBB1_9
.LBB1_10:                               ; %._crit_edge64
                                        ;   in Loop: Header=BB1_7 Depth=1
	s_add_i32 s12, s12, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s12, s6
	s_cbranch_scc0 .LBB1_7
.LBB1_11:                               ; %._crit_edge68
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v0, v6, v5
	s_barrier
	buffer_gl0_inv
	v_div_scale_f32 v1, null, v4, v4, v0
	v_div_scale_f32 v7, vcc_lo, v0, v4, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v5, v1
	s_waitcnt_depctr 0xfff
	v_fma_f32 v6, -v1, v5, 1.0
	v_fmac_f32_e32 v5, v6, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v6, v7, v5
	v_fma_f32 v8, -v1, v6, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v6, v8, v5
	v_fma_f32 v1, -v1, v6, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v1, v1, v5, v6
	v_div_fixup_f32 v4, v1, v4, v0
	v_add_co_u32 v0, vcc_lo, s2, v2
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v3, vcc_lo
	global_store_b32 v[0:1], v4, off
.LBB1_12:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z4nmfhPfiiiS_S_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 304
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 11
		.amdhsa_next_free_sgpr 18
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z4nmfhPfiiiS_S_S_, .Lfunc_end1-_Z4nmfhPfiiiS_S_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 680
; NumSgprs: 20
; NumVgprs: 11
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 20
; NumVGPRsForWavesPerEU: 11
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z6nmfcpyPfS_ii         ; -- Begin function _Z6nmfcpyPfS_ii
	.globl	_Z6nmfcpyPfS_ii
	.p2align	8
	.type	_Z6nmfcpyPfS_ii,@function
_Z6nmfcpyPfS_ii:                        ; @_Z6nmfcpyPfS_ii
; %bb.0:
	s_clause 0x1
	s_load_b32 s4, s[0:1], 0x24
	s_load_b64 s[2:3], s[0:1], 0x10
	v_bfe_u32 v2, v0, 10, 10
	v_and_b32_e32 v3, 0x3ff, v0
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s5, s4, 16
	s_and_b32 s4, s4, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[0:1], null, s15, s5, v[2:3]
	v_mad_u64_u32 v[1:2], null, s14, s4, v[3:4]
	v_cmp_gt_i32_e32 vcc_lo, s2, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_gt_i32_e64 s2, s3, v1
	s_and_b32 s2, vcc_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s4, s2
	s_cbranch_execz .LBB2_2
; %bb.1:
	s_load_b128 s[4:7], s[0:1], 0x0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[2:3], null, v0, s3, v[1:2]
	v_ashrrev_i32_e32 v3, 31, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[2:3]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v2, vcc_lo, s6, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
	v_add_co_u32 v0, vcc_lo, s4, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
	global_load_b32 v2, v[2:3], off
	s_waitcnt vmcnt(0)
	global_store_b32 v[0:1], v2, off
.LBB2_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z6nmfcpyPfS_ii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 5
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_Z6nmfcpyPfS_ii, .Lfunc_end2-_Z6nmfcpyPfS_ii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 204
; NumSgprs: 18
; NumVgprs: 5
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 5
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .offset:         12
        .size:           4
        .value_kind:     by_value
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         52
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         60
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         62
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         64
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         66
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         68
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         70
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         112
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 304
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z4nmfwPfiiiS_S_S_
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z4nmfwPfiiiS_S_S_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     12
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
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    .name:           _Z4nmfhPfiiiS_S_S_
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amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
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  - 2
...

	.end_amdgpu_metadata
