#include <cassert>
#include <iostream>
#include <cuda_runtime.h>

class CudaTimer {
 private:
  cudaEvent_t _start;
  cudaEvent_t _stop;
 public:
  CudaTimer() noexcept {
    cudaEventCreate(&_start);
    cudaEventCreate(&_stop);
  }

  ~CudaTimer() noexcept {
    cudaEventDestroy(_start);
    cudaEventDestroy(_stop);
  }

  void start() noexcept {
    cudaEventRecord(_start, 0);
  }

  void stop() noexcept {
    cudaEventRecord(_stop, 0);
    cudaEventSynchronize(_stop);
  }

  float count() noexcept {
    float time = 0.0;
    cudaEventElapsedTime(&time, _start, _stop);
    return time;
  }
};

__global__ void count_row_nnz(int m, int n, double *A, int lda, int *rownnz) {
    int tid = threadIdx.x + blockIdx.x * blockDim.x;
    if (tid < m) {
        int     count = 0;
        double *value = A + tid;

        for (int i = 0; i < n; ++i) {
            count += (*value) ?1 :0;
            value += lda;
        }
        rownnz[tid] = count;
    }
}

__global__ void block_scan(int n, int *array, int *buffer) {
  extern __shared__ int shm[]; // size of shm: 2 * blockDim.x * sizeof(int)

  // Initialize shm
  int tid = threadIdx.x + (blockIdx.x << 1) * blockDim.x;
  if (tid < n) {
    shm[threadIdx.x] = array[tid];
  } else {
    shm[threadIdx.x] = 0;
  }
  if (tid + blockDim.x < n) {
    shm[threadIdx.x + blockDim.x] = array[tid + blockDim.x];
  } else {
    shm[threadIdx.x + blockDim.x] = 0;
  }

  __syncthreads();

  int num_elements = blockDim.x << 1;

  // Start up-sweep phase
  int idx = threadIdx.x << 1, shift = 1;
  while (shift < num_elements) {
    if (idx + shift < num_elements) {
      shm[idx + shift] += shm[idx];
    }
    idx += idx + 1;
    shift <<= 1;
  }
  __syncthreads();

  // Start down-sweep phase
  int sum = shm[num_elements - 1];
  if (threadIdx.x == 0) {
    shm[num_elements - 1] = 0;
  }
  idx = (idx - 1) >> 1;
  shift >>= 1;
  while (shift > 0) {
    if (idx + shift < num_elements) {
      int tmp = shm[idx + shift];
      shm[idx + shift] += shm[idx];
      shm[idx] = tmp;
    }
    idx = (idx - 1) >> 1;
    shift >>= 1;
    __syncthreads();
  }
  __syncthreads();

  if (tid < n) {
    array[tid] = shm[threadIdx.x];
  }
  if (tid + blockDim.x < n) {
    array[tid + blockDim.x] = shm[threadIdx.x + blockDim.x];
  }

  if (threadIdx.x == 0) {
    buffer[blockIdx.x] = sum;
  }
}

__global__ void block_add(int n, int *array, int *buf) {
  int tid = blockIdx.x * (blockDim.x << 1) + threadIdx.x;

  int val = buf[blockIdx.x];
  if (tid < n) {
    array[tid] += val;
  }
  if (tid + blockDim.x < n) {
    array[tid + blockDim.x] += val;
  }
}

void exclusive_scan(int n, int *array) {
    int bs = 1024;
    int gs = (n - 1) / (bs << 1) + 1;

    int *buffer;
    cudaError_t cudaErr = cudaMalloc(reinterpret_cast<void **>(&buffer), gs * sizeof(int));
    assert(cudaErr == cudaSuccess);

#ifndef NDEBUG
    CudaTimer scanTimer;
    scanTimer.start();
#endif

    block_scan<<<gs , bs, 2 * bs * sizeof(int)>>>(n, array, buffer);
    assert(cudaGetLastError() == cudaSuccess);

#ifndef NDEBUG
    scanTimer.stop();
    std::cout << scanTimer.count() << ",";
#endif

    if (gs > 1) {
#ifndef NDEBUG
      CudaTimer addTimer;
      addTimer.start();
#endif
      block_add<<<gs - 1, bs>>>(n - (bs << 1), array + (bs << 1), buffer);
      assert(cudaGetLastError() == cudaSuccess);

#ifndef NDEBUG
      addTimer.stop();
      std::cout << addTimer.count() << ",";
#endif
    }

    cudaFree(buffer);
}

__global__ void fill_csr_values(
    int m, int n,
    double *A, int lda,
    int *rowptr, int *colidx, double *values) {
    int tid = threadIdx.x + blockIdx.x * blockDim.x;
    if (tid < m) {
        int     idx = rowptr[tid];
        double *ptr = A + tid;

        for (int i = 0; i < n; ++i) {
            if (*ptr) {
                colidx[idx] = i;
                values[idx] = *ptr;

                ++idx;
            }
            ptr += lda;
        }
    }
}

void full_to_csr(
    int m, int n,
    double *A, int lda,
    int **rowptr, int **colidx, double **values) {

    cudaError_t cudaErr;
    cudaErr = cudaMalloc(rowptr, (m + 1) * sizeof(int));
    assert(cudaErr == cudaSuccess);

#ifndef NDEBUG
    CudaTimer cntNnzTimer;
    cntNnzTimer.start();
#endif
    // Launch kernel to get number of nnz
    int bs = 1024, gs = (m - 1) / bs + 1;
    count_row_nnz<<<gs, bs>>>(m, n, A, lda, *rowptr);
    assert(cudaGetLastError() == cudaSuccess);

#ifndef NDEBUG
    cntNnzTimer.stop();
    std::cout << cntNnzTimer.count() << ",";
#endif

    exclusive_scan(m + 1, *rowptr);

    int nnz = 0;
    cudaErr = cudaMemcpy(&nnz, *rowptr + m, sizeof(int), cudaMemcpyDeviceToHost);
    assert(cudaErr == cudaSuccess);

    cudaErr = cudaMalloc(colidx, nnz * sizeof(int));
    assert(cudaErr == cudaSuccess);

    cudaErr = cudaMalloc(values, nnz * sizeof(double));
    assert(cudaErr == cudaSuccess);

#ifndef NDEBUG
    CudaTimer fillValTimer;
    fillValTimer.start();
#endif

    fill_csr_values<<<gs, bs>>>(m, n, A, lda, *rowptr, *colidx, *values);
    assert(cudaGetLastError() == cudaSuccess);

#ifndef NDEBUG
    fillValTimer.stop();
    std::cout << fillValTimer.count() << std::endl;
#endif
}

	.file	"tmpxft_002b534d_00000000-6_ex4.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3648:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3648:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z38__device_stub__Z13count_row_nnziiPdiPiiiPdiPi
	.type	_Z38__device_stub__Z13count_row_nnziiPdiPiiiPdiPi, @function
_Z38__device_stub__Z13count_row_nnziiPdiPiiiPdiPi:
.LFB3670:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movl	%edi, 28(%rsp)
	leaq	48(%rsp), %rdi
	movl	%esi, 24(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 16(%rsp)
	leaq	32(%rsp), %rdx
	movl	%ecx, 12(%rsp)
	leaq	40(%rsp), %rcx
	movq	%r8, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	28(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	40(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z13count_row_nnziiPdiPi(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 176
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L2:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3670:
	.size	_Z38__device_stub__Z13count_row_nnziiPdiPiiiPdiPi, .-_Z38__device_stub__Z13count_row_nnziiPdiPiiiPdiPi
	.globl	_Z13count_row_nnziiPdiPi
	.type	_Z13count_row_nnziiPdiPi, @function
_Z13count_row_nnziiPdiPi:
.LFB3671:
	.cfi_startproc
	endbr64
	jmp	_Z38__device_stub__Z13count_row_nnziiPdiPiiiPdiPi
	.cfi_endproc
.LFE3671:
	.size	_Z13count_row_nnziiPdiPi, .-_Z13count_row_nnziiPdiPi
	.globl	_Z33__device_stub__Z10block_scaniPiS_iPiS_
	.type	_Z33__device_stub__Z10block_scaniPiS_iPiS_, @function
_Z33__device_stub__Z10block_scaniPiS_iPiS_:
.LFB3672:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movl	%edi, 28(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	28(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L8
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z10block_scaniPiS_(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L8:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L10
	call	__stack_chk_fail@PLT
.L10:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3672:
	.size	_Z33__device_stub__Z10block_scaniPiS_iPiS_, .-_Z33__device_stub__Z10block_scaniPiS_iPiS_
	.globl	_Z10block_scaniPiS_
	.type	_Z10block_scaniPiS_, @function
_Z10block_scaniPiS_:
.LFB3673:
	.cfi_startproc
	endbr64
	jmp	_Z33__device_stub__Z10block_scaniPiS_iPiS_
	.cfi_endproc
.LFE3673:
	.size	_Z10block_scaniPiS_, .-_Z10block_scaniPiS_
	.globl	_Z31__device_stub__Z9block_addiPiS_iPiS_
	.type	_Z31__device_stub__Z9block_addiPiS_iPiS_, @function
_Z31__device_stub__Z9block_addiPiS_iPiS_:
.LFB3674:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movl	%edi, 28(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	28(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L13
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z9block_addiPiS_(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L13:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L15
	call	__stack_chk_fail@PLT
.L15:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3674:
	.size	_Z31__device_stub__Z9block_addiPiS_iPiS_, .-_Z31__device_stub__Z9block_addiPiS_iPiS_
	.globl	_Z9block_addiPiS_
	.type	_Z9block_addiPiS_, @function
_Z9block_addiPiS_:
.LFB3675:
	.cfi_startproc
	endbr64
	jmp	_Z31__device_stub__Z9block_addiPiS_iPiS_
	.cfi_endproc
.LFE3675:
	.size	_Z9block_addiPiS_, .-_Z9block_addiPiS_
	.globl	_Z14exclusive_scaniPi
	.type	_Z14exclusive_scaniPi, @function
_Z14exclusive_scaniPi:
.LFB3644:
	.cfi_startproc
	endbr64
	pushq	%r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	movl	$2048, %ecx
	pushq	%r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	pushq	%rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	movq	%rsi, %rbp
	pushq	%rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	movl	%edi, %ebx
	subq	$56, %rsp
	.cfi_def_cfa_offset 96
	movq	%fs:40, %rax
	movq	%rax, 40(%rsp)
	xorl	%eax, %eax
	leal	-1(%rdi), %eax
	leaq	8(%rsp), %rdi
	cltd
	idivl	%ecx
	leal	1(%rax), %r13d
	movl	%eax, %r12d
	movslq	%r13d, %rsi
	salq	$2, %rsi
	call	cudaMalloc@PLT
	movl	%r13d, 16(%rsp)
	movl	$4194305, %edx
	movabsq	$4294967297, %rax
	movq	%rax, 20(%rsp)
	movq	16(%rsp), %rdi
	salq	$10, %rdx
	xorl	%r9d, %r9d
	movl	24(%rsp), %esi
	movl	$8192, %r8d
	movl	$1, %ecx
	movq	%rdx, 28(%rsp)
	movl	$1, 36(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L19
	movq	8(%rsp), %rdx
	movq	%rbp, %rsi
	movl	%ebx, %edi
	call	_Z33__device_stub__Z10block_scaniPiS_iPiS_
.L19:
	decl	%r13d
	jle	.L20
	movl	%r12d, 16(%rsp)
	movl	$4194305, %edx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movabsq	$4294967297, %rax
	salq	$10, %rdx
	movl	$1, %ecx
	movl	$1, 36(%rsp)
	movq	%rax, 20(%rsp)
	movq	16(%rsp), %rdi
	movl	24(%rsp), %esi
	movq	%rdx, 28(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L20
	movq	8(%rsp), %rdx
	leaq	8192(%rbp), %rsi
	leal	-2048(%rbx), %edi
	call	_Z31__device_stub__Z9block_addiPiS_iPiS_
.L20:
	movq	8(%rsp), %rdi
	call	cudaFree@PLT
	movq	40(%rsp), %rax
	subq	%fs:40, %rax
	je	.L22
	call	__stack_chk_fail@PLT
.L22:
	addq	$56, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3644:
	.size	_Z14exclusive_scaniPi, .-_Z14exclusive_scaniPi
	.globl	_Z45__device_stub__Z15fill_csr_valuesiiPdiPiS0_S_iiPdiPiS0_S_
	.type	_Z45__device_stub__Z15fill_csr_valuesiiPdiPiS0_S_iiPdiPiS0_S_, @function
_Z45__device_stub__Z15fill_csr_valuesiiPdiPiS0_S_iiPdiPiS0_S_:
.LFB3676:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	192(%rsp), %rax
	movl	%edi, 44(%rsp)
	leaq	64(%rsp), %rdi
	movl	%esi, 40(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 32(%rsp)
	leaq	48(%rsp), %rdx
	movl	%ecx, 28(%rsp)
	leaq	56(%rsp), %rcx
	movq	%r8, 16(%rsp)
	movq	%r9, 8(%rsp)
	movq	%rax, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	44(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 112(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	28(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 152(%rsp)
	movq	%rsp, %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L24
	pushq	56(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z15fill_csr_valuesiiPdiPiS0_S_(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 208
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L24:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L26
	call	__stack_chk_fail@PLT
.L26:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3676:
	.size	_Z45__device_stub__Z15fill_csr_valuesiiPdiPiS0_S_iiPdiPiS0_S_, .-_Z45__device_stub__Z15fill_csr_valuesiiPdiPiS0_S_iiPdiPiS0_S_
	.globl	_Z15fill_csr_valuesiiPdiPiS0_S_
	.type	_Z15fill_csr_valuesiiPdiPiS0_S_, @function
_Z15fill_csr_valuesiiPdiPiS0_S_:
.LFB3677:
	.cfi_startproc
	endbr64
	jmp	_Z45__device_stub__Z15fill_csr_valuesiiPdiPiS0_S_iiPdiPiS0_S_
	.cfi_endproc
.LFE3677:
	.size	_Z15fill_csr_valuesiiPdiPiS0_S_, .-_Z15fill_csr_valuesiiPdiPiS0_S_
	.globl	_Z11full_to_csriiPdiPPiS1_PS_
	.type	_Z11full_to_csriiPdiPPiS1_PS_, @function
_Z11full_to_csriiPdiPPiS1_PS_:
.LFB3645:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	leal	1(%rdi), %r15d
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movq	%r9, %r13
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movl	%edi, %r12d
	movq	%r8, %rdi
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movq	%r8, %rbx
	subq	$88, %rsp
	.cfi_def_cfa_offset 144
	movl	%esi, 24(%rsp)
	movq	144(%rsp), %r14
	movq	%rdx, 16(%rsp)
	movl	%ecx, 28(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	xorl	%eax, %eax
	movslq	%r15d, %rax
	salq	$2, %rax
	movq	%rax, %rsi
	movq	%rax, 8(%rsp)
	call	cudaMalloc@PLT
	leal	-1(%r12), %eax
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$1024, %esi
	cltd
	movl	$4194305, %ecx
	movl	$1, 68(%rsp)
	idivl	%esi
	salq	$10, %rcx
	movq	%rcx, 60(%rsp)
	movq	%rcx, %rdx
	movl	$1, %ecx
	leal	1(%rax), %ebp
	movabsq	$4294967297, %rax
	movq	%rax, 52(%rsp)
	movl	56(%rsp), %esi
	movl	%ebp, 48(%rsp)
	movq	48(%rsp), %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L30
	movq	(%rbx), %r8
	movl	28(%rsp), %ecx
	movl	%r12d, %edi
	movq	16(%rsp), %rdx
	movl	24(%rsp), %esi
	call	_Z38__device_stub__Z13count_row_nnziiPdiPiiiPdiPi
.L30:
	movq	(%rbx), %rsi
	movl	%r15d, %edi
	call	_Z14exclusive_scaniPi
	movq	8(%rsp), %rcx
	movq	(%rbx), %rax
	xorl	%esi, %esi
	movl	$4, %edx
	movl	%esi, 44(%rsp)
	leaq	44(%rsp), %rdi
	leaq	-4(%rax,%rcx), %rsi
	movl	$2, %ecx
	call	cudaMemcpy@PLT
	movslq	44(%rsp), %rsi
	movq	%r13, %rdi
	salq	$2, %rsi
	call	cudaMalloc@PLT
	movslq	44(%rsp), %rsi
	movq	%r14, %rdi
	salq	$3, %rsi
	call	cudaMalloc@PLT
	movl	%ebp, 48(%rsp)
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movabsq	$4294967297, %rax
	movl	$4194305, %edx
	movl	$1, %ecx
	movl	$1, 68(%rsp)
	movq	%rax, 52(%rsp)
	movq	48(%rsp), %rdi
	salq	$10, %rdx
	movl	56(%rsp), %esi
	movq	%rdx, 60(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L29
	pushq	%rax
	.cfi_def_cfa_offset 152
	movq	0(%r13), %r9
	movl	%r12d, %edi
	pushq	(%r14)
	.cfi_def_cfa_offset 160
	movq	(%rbx), %r8
	movl	44(%rsp), %ecx
	movq	32(%rsp), %rdx
	movl	40(%rsp), %esi
	call	_Z45__device_stub__Z15fill_csr_valuesiiPdiPiS0_S_iiPdiPiS0_S_
	popq	%rdx
	.cfi_def_cfa_offset 152
	popq	%rcx
	.cfi_def_cfa_offset 144
.L29:
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L32
	call	__stack_chk_fail@PLT
.L32:
	addq	$88, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3645:
	.size	_Z11full_to_csriiPdiPPiS1_PS_, .-_Z11full_to_csriiPdiPPiS1_PS_
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z15fill_csr_valuesiiPdiPiS0_S_"
.LC1:
	.string	"_Z9block_addiPiS_"
.LC2:
	.string	"_Z10block_scaniPiS_"
.LC3:
	.string	"_Z13count_row_nnziiPdiPi"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3679:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z15fill_csr_valuesiiPdiPiS0_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC1(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z9block_addiPiS_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC2(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z10block_scaniPiS_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC3(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z13count_row_nnziiPdiPi(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3679:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <cassert>
#include <iostream>
#include <hip/hip_runtime.h>

class CudaTimer {
 private:
  hipEvent_t _start;
  hipEvent_t _stop;
 public:
  CudaTimer() noexcept {
    hipEventCreate(&_start);
    hipEventCreate(&_stop);
  }

  ~CudaTimer() noexcept {
    hipEventDestroy(_start);
    hipEventDestroy(_stop);
  }

  void start() noexcept {
    hipEventRecord(_start, 0);
  }

  void stop() noexcept {
    hipEventRecord(_stop, 0);
    hipEventSynchronize(_stop);
  }

  float count() noexcept {
    float time = 0.0;
    hipEventElapsedTime(&time, _start, _stop);
    return time;
  }
};

__global__ void count_row_nnz(int m, int n, double *A, int lda, int *rownnz) {
    int tid = threadIdx.x + blockIdx.x * blockDim.x;
    if (tid < m) {
        int     count = 0;
        double *value = A + tid;

        for (int i = 0; i < n; ++i) {
            count += (*value) ?1 :0;
            value += lda;
        }
        rownnz[tid] = count;
    }
}

__global__ void block_scan(int n, int *array, int *buffer) {
  extern __shared__ int shm[]; // size of shm: 2 * blockDim.x * sizeof(int)

  // Initialize shm
  int tid = threadIdx.x + (blockIdx.x << 1) * blockDim.x;
  if (tid < n) {
    shm[threadIdx.x] = array[tid];
  } else {
    shm[threadIdx.x] = 0;
  }
  if (tid + blockDim.x < n) {
    shm[threadIdx.x + blockDim.x] = array[tid + blockDim.x];
  } else {
    shm[threadIdx.x + blockDim.x] = 0;
  }

  __syncthreads();

  int num_elements = blockDim.x << 1;

  // Start up-sweep phase
  int idx = threadIdx.x << 1, shift = 1;
  while (shift < num_elements) {
    if (idx + shift < num_elements) {
      shm[idx + shift] += shm[idx];
    }
    idx += idx + 1;
    shift <<= 1;
  }
  __syncthreads();

  // Start down-sweep phase
  int sum = shm[num_elements - 1];
  if (threadIdx.x == 0) {
    shm[num_elements - 1] = 0;
  }
  idx = (idx - 1) >> 1;
  shift >>= 1;
  while (shift > 0) {
    if (idx + shift < num_elements) {
      int tmp = shm[idx + shift];
      shm[idx + shift] += shm[idx];
      shm[idx] = tmp;
    }
    idx = (idx - 1) >> 1;
    shift >>= 1;
    __syncthreads();
  }
  __syncthreads();

  if (tid < n) {
    array[tid] = shm[threadIdx.x];
  }
  if (tid + blockDim.x < n) {
    array[tid + blockDim.x] = shm[threadIdx.x + blockDim.x];
  }

  if (threadIdx.x == 0) {
    buffer[blockIdx.x] = sum;
  }
}

__global__ void block_add(int n, int *array, int *buf) {
  int tid = blockIdx.x * (blockDim.x << 1) + threadIdx.x;

  int val = buf[blockIdx.x];
  if (tid < n) {
    array[tid] += val;
  }
  if (tid + blockDim.x < n) {
    array[tid + blockDim.x] += val;
  }
}

void exclusive_scan(int n, int *array) {
    int bs = 1024;
    int gs = (n - 1) / (bs << 1) + 1;

    int *buffer;
    hipError_t cudaErr = hipMalloc(reinterpret_cast<void **>(&buffer), gs * sizeof(int));
    assert(cudaErr == hipSuccess);

#ifndef NDEBUG
    CudaTimer scanTimer;
    scanTimer.start();
#endif

    block_scan<<<gs , bs, 2 * bs * sizeof(int)>>>(n, array, buffer);
    assert(hipGetLastError() == hipSuccess);

#ifndef NDEBUG
    scanTimer.stop();
    std::cout << scanTimer.count() << ",";
#endif

    if (gs > 1) {
#ifndef NDEBUG
      CudaTimer addTimer;
      addTimer.start();
#endif
      block_add<<<gs - 1, bs>>>(n - (bs << 1), array + (bs << 1), buffer);
      assert(hipGetLastError() == hipSuccess);

#ifndef NDEBUG
      addTimer.stop();
      std::cout << addTimer.count() << ",";
#endif
    }

    hipFree(buffer);
}

__global__ void fill_csr_values(
    int m, int n,
    double *A, int lda,
    int *rowptr, int *colidx, double *values) {
    int tid = threadIdx.x + blockIdx.x * blockDim.x;
    if (tid < m) {
        int     idx = rowptr[tid];
        double *ptr = A + tid;

        for (int i = 0; i < n; ++i) {
            if (*ptr) {
                colidx[idx] = i;
                values[idx] = *ptr;

                ++idx;
            }
            ptr += lda;
        }
    }
}

void full_to_csr(
    int m, int n,
    double *A, int lda,
    int **rowptr, int **colidx, double **values) {

    hipError_t cudaErr;
    cudaErr = hipMalloc(rowptr, (m + 1) * sizeof(int));
    assert(cudaErr == hipSuccess);

#ifndef NDEBUG
    CudaTimer cntNnzTimer;
    cntNnzTimer.start();
#endif
    // Launch kernel to get number of nnz
    int bs = 1024, gs = (m - 1) / bs + 1;
    count_row_nnz<<<gs, bs>>>(m, n, A, lda, *rowptr);
    assert(hipGetLastError() == hipSuccess);

#ifndef NDEBUG
    cntNnzTimer.stop();
    std::cout << cntNnzTimer.count() << ",";
#endif

    exclusive_scan(m + 1, *rowptr);

    int nnz = 0;
    cudaErr = hipMemcpy(&nnz, *rowptr + m, sizeof(int), hipMemcpyDeviceToHost);
    assert(cudaErr == hipSuccess);

    cudaErr = hipMalloc(colidx, nnz * sizeof(int));
    assert(cudaErr == hipSuccess);

    cudaErr = hipMalloc(values, nnz * sizeof(double));
    assert(cudaErr == hipSuccess);

#ifndef NDEBUG
    CudaTimer fillValTimer;
    fillValTimer.start();
#endif

    fill_csr_values<<<gs, bs>>>(m, n, A, lda, *rowptr, *colidx, *values);
    assert(hipGetLastError() == hipSuccess);

#ifndef NDEBUG
    fillValTimer.stop();
    std::cout << fillValTimer.count() << std::endl;
#endif
}

	.text
	.file	"ex4.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z28__device_stub__count_row_nnziiPdiPi # -- Begin function _Z28__device_stub__count_row_nnziiPdiPi
	.type	_Z28__device_stub__count_row_nnziiPdiPi,@function
_Z28__device_stub__count_row_nnziiPdiPi: # @_Z28__device_stub__count_row_nnziiPdiPi
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	12(%rsp), %rax
	movl	%edi, (%rax)
	leaq	8(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	4(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	32(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z13count_row_nnziiPdiPi, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z28__device_stub__count_row_nnziiPdiPi, .Lfunc_end0-_Z28__device_stub__count_row_nnziiPdiPi
	.cfi_endproc
                                        # -- End function
	.globl	_Z25__device_stub__block_scaniPiS_ # -- Begin function _Z25__device_stub__block_scaniPiS_
	.type	_Z25__device_stub__block_scaniPiS_,@function
_Z25__device_stub__block_scaniPiS_:     # @_Z25__device_stub__block_scaniPiS_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	12(%rsp), %rax
	movl	%edi, (%rax)
	leaq	40(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	32(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z10block_scaniPiS_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z25__device_stub__block_scaniPiS_, .Lfunc_end1-_Z25__device_stub__block_scaniPiS_
	.cfi_endproc
                                        # -- End function
	.globl	_Z24__device_stub__block_addiPiS_ # -- Begin function _Z24__device_stub__block_addiPiS_
	.type	_Z24__device_stub__block_addiPiS_,@function
_Z24__device_stub__block_addiPiS_:      # @_Z24__device_stub__block_addiPiS_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	12(%rsp), %rax
	movl	%edi, (%rax)
	leaq	40(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	32(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z9block_addiPiS_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z24__device_stub__block_addiPiS_, .Lfunc_end2-_Z24__device_stub__block_addiPiS_
	.cfi_endproc
                                        # -- End function
	.globl	_Z14exclusive_scaniPi           # -- Begin function _Z14exclusive_scaniPi
	.type	_Z14exclusive_scaniPi,@function
_Z14exclusive_scaniPi:                  # @_Z14exclusive_scaniPi
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$16, %rsp
	.cfi_def_cfa_offset 64
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movq	%rsi, %rbx
	movl	%edi, %r14d
	movabsq	$4294967296, %r15               # imm = 0x100000000
	leal	-1(%r14), %eax
	leal	2046(%r14), %r13d
	testl	%eax, %eax
	cmovnsl	%eax, %r13d
	sarl	$11, %r13d
	leal	1(%r13), %r12d
	movslq	%r13d, %rax
	leaq	4(,%rax,4), %rsi
	leaq	8(%rsp), %rdi
	callq	hipMalloc
	btsq	$32, %r12
	leaq	1024(%r15), %rdx
	movl	$8192, %r8d                     # imm = 0x2000
	movq	%r12, %rdi
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB3_2
# %bb.1:
	movq	8(%rsp), %rdx
	movl	%r14d, %edi
	movq	%rbx, %rsi
	callq	_Z25__device_stub__block_scaniPiS_
.LBB3_2:
	cmpl	$2049, %r14d                    # imm = 0x801
	jl	.LBB3_5
# %bb.3:
	movl	%r13d, %edi
	orq	%r15, %rdi
	addq	$1024, %r15                     # imm = 0x400
	movl	$1, %esi
	movq	%r15, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB3_5
# %bb.4:
	addl	$-2048, %r14d                   # imm = 0xF800
	addq	$8192, %rbx                     # imm = 0x2000
	movq	8(%rsp), %rdx
	movl	%r14d, %edi
	movq	%rbx, %rsi
	callq	_Z24__device_stub__block_addiPiS_
.LBB3_5:
	movq	8(%rsp), %rdi
	callq	hipFree
	addq	$16, %rsp
	.cfi_def_cfa_offset 48
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	_Z14exclusive_scaniPi, .Lfunc_end3-_Z14exclusive_scaniPi
	.cfi_endproc
                                        # -- End function
	.globl	_Z30__device_stub__fill_csr_valuesiiPdiPiS0_S_ # -- Begin function _Z30__device_stub__fill_csr_valuesiiPdiPiS0_S_
	.type	_Z30__device_stub__fill_csr_valuesiiPdiPiS0_S_,@function
_Z30__device_stub__fill_csr_valuesiiPdiPiS0_S_: # @_Z30__device_stub__fill_csr_valuesiiPdiPiS0_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	20(%rsp), %rax
	movl	%edi, (%rax)
	leaq	16(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	56(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	12(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	48(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	40(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z15fill_csr_valuesiiPdiPiS0_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end4:
	.size	_Z30__device_stub__fill_csr_valuesiiPdiPiS0_S_, .Lfunc_end4-_Z30__device_stub__fill_csr_valuesiiPdiPiS0_S_
	.cfi_endproc
                                        # -- End function
	.globl	_Z11full_to_csriiPdiPPiS1_PS_   # -- Begin function _Z11full_to_csriiPdiPPiS1_PS_
	.type	_Z11full_to_csriiPdiPPiS1_PS_,@function
_Z11full_to_csriiPdiPPiS1_PS_:          # @_Z11full_to_csriiPdiPPiS1_PS_
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$40, %rsp
	.cfi_def_cfa_offset 96
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%r9, 24(%rsp)                   # 8-byte Spill
	movq	%r8, %r13
	movl	%ecx, 12(%rsp)                  # 4-byte Spill
	movq	%rdx, 16(%rsp)                  # 8-byte Spill
	movl	%esi, 8(%rsp)                   # 4-byte Spill
	movl	%edi, %r12d
	movabsq	$4294968320, %r15               # imm = 0x100000400
	leal	1(%r12), %ebx
	movslq	%edi, %rbp
	leaq	4(,%rbp,4), %rsi
	movq	%r8, %rdi
	callq	hipMalloc
	leal	-1(%rbp), %eax
	leal	1022(%rbp), %ecx
	testl	%eax, %eax
	cmovnsl	%eax, %ecx
	sarl	$10, %ecx
	incl	%ecx
	leaq	(%rcx,%r15), %r14
	addq	$-1024, %r14                    # imm = 0xFC00
	movq	%r14, %rdi
	movl	$1, %esi
	movq	%r15, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB5_2
# %bb.1:
	movq	(%r13), %r8
	movl	%r12d, %edi
	movl	8(%rsp), %esi                   # 4-byte Reload
	movq	16(%rsp), %rdx                  # 8-byte Reload
	movl	12(%rsp), %ecx                  # 4-byte Reload
	callq	_Z28__device_stub__count_row_nnziiPdiPi
.LBB5_2:
	movq	(%r13), %rsi
	movl	%ebx, %edi
	callq	_Z14exclusive_scaniPi
	leaq	36(%rsp), %rbx
	movl	$0, (%rbx)
	shlq	$2, %rbp
	addq	(%r13), %rbp
	movl	$4, %edx
	movq	%rbx, %rdi
	movq	%rbp, %rsi
	movl	$2, %ecx
	callq	hipMemcpy
	movslq	(%rbx), %rsi
	shlq	$2, %rsi
	movq	24(%rsp), %r15                  # 8-byte Reload
	movq	%r15, %rdi
	callq	hipMalloc
	movslq	(%rbx), %rsi
	shlq	$3, %rsi
	movq	96(%rsp), %rbx
	movq	%rbx, %rdi
	callq	hipMalloc
	movq	%r14, %rdi
	movl	$1, %esi
	movabsq	$4294968320, %rdx               # imm = 0x100000400
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB5_4
# %bb.3:
	movq	(%r13), %r8
	movq	(%r15), %r9
	movq	(%rbx), %rax
	movq	%rax, (%rsp)
	movl	%r12d, %edi
	movl	8(%rsp), %esi                   # 4-byte Reload
	movq	16(%rsp), %rdx                  # 8-byte Reload
	movl	12(%rsp), %ecx                  # 4-byte Reload
	callq	_Z30__device_stub__fill_csr_valuesiiPdiPiS0_S_
.LBB5_4:
	addq	$40, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end5:
	.size	_Z11full_to_csriiPdiPPiS1_PS_, .Lfunc_end5-_Z11full_to_csriiPdiPPiS1_PS_
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB6_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB6_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z13count_row_nnziiPdiPi, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z10block_scaniPiS_, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z9block_addiPiS_, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z15fill_csr_valuesiiPdiPiS0_S_, %esi
	movl	$.L__unnamed_4, %edx
	movl	$.L__unnamed_4, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end6:
	.size	__hip_module_ctor, .Lfunc_end6-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB7_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB7_2:
	retq
.Lfunc_end7:
	.size	__hip_module_dtor, .Lfunc_end7-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z13count_row_nnziiPdiPi,@object # @_Z13count_row_nnziiPdiPi
	.section	.rodata,"a",@progbits
	.globl	_Z13count_row_nnziiPdiPi
	.p2align	3, 0x0
_Z13count_row_nnziiPdiPi:
	.quad	_Z28__device_stub__count_row_nnziiPdiPi
	.size	_Z13count_row_nnziiPdiPi, 8

	.type	_Z10block_scaniPiS_,@object     # @_Z10block_scaniPiS_
	.globl	_Z10block_scaniPiS_
	.p2align	3, 0x0
_Z10block_scaniPiS_:
	.quad	_Z25__device_stub__block_scaniPiS_
	.size	_Z10block_scaniPiS_, 8

	.type	_Z9block_addiPiS_,@object       # @_Z9block_addiPiS_
	.globl	_Z9block_addiPiS_
	.p2align	3, 0x0
_Z9block_addiPiS_:
	.quad	_Z24__device_stub__block_addiPiS_
	.size	_Z9block_addiPiS_, 8

	.type	_Z15fill_csr_valuesiiPdiPiS0_S_,@object # @_Z15fill_csr_valuesiiPdiPiS0_S_
	.globl	_Z15fill_csr_valuesiiPdiPiS0_S_
	.p2align	3, 0x0
_Z15fill_csr_valuesiiPdiPiS0_S_:
	.quad	_Z30__device_stub__fill_csr_valuesiiPdiPiS0_S_
	.size	_Z15fill_csr_valuesiiPdiPiS0_S_, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z13count_row_nnziiPdiPi"
	.size	.L__unnamed_1, 25

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z10block_scaniPiS_"
	.size	.L__unnamed_2, 20

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z9block_addiPiS_"
	.size	.L__unnamed_3, 18

	.type	.L__unnamed_4,@object           # @3
.L__unnamed_4:
	.asciz	"_Z15fill_csr_valuesiiPdiPiS0_S_"
	.size	.L__unnamed_4, 32

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z28__device_stub__count_row_nnziiPdiPi
	.addrsig_sym _Z25__device_stub__block_scaniPiS_
	.addrsig_sym _Z24__device_stub__block_addiPiS_
	.addrsig_sym _Z30__device_stub__fill_csr_valuesiiPdiPiS0_S_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z13count_row_nnziiPdiPi
	.addrsig_sym _Z10block_scaniPiS_
	.addrsig_sym _Z9block_addiPiS_
	.addrsig_sym _Z15fill_csr_valuesiiPdiPiS0_S_
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z13count_row_nnziiPdiPi ; -- Begin function _Z13count_row_nnziiPdiPi
	.globl	_Z13count_row_nnziiPdiPi
	.p2align	8
	.type	_Z13count_row_nnziiPdiPi,@function
_Z13count_row_nnziiPdiPi:               ; @_Z13count_row_nnziiPdiPi
; %bb.0:
	s_clause 0x1
	s_load_b32 s4, s[0:1], 0x2c
	s_load_b64 s[2:3], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s4, s4, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
	v_cmp_gt_i32_e32 vcc_lo, s2, v1
	s_and_saveexec_b32 s2, vcc_lo
	s_cbranch_execz .LBB0_6
; %bb.1:
	v_ashrrev_i32_e32 v2, 31, v1
	s_cmp_lt_i32 s3, 1
	s_cbranch_scc1 .LBB0_4
; %bb.2:                                ; %.lr.ph
	s_clause 0x1
	s_load_b64 s[4:5], s[0:1], 0x8
	s_load_b32 s6, s[0:1], 0x10
	v_lshlrev_b64 v[3:4], 3, v[1:2]
	v_mov_b32_e32 v0, 0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v3, vcc_lo, s4, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
	s_ashr_i32 s7, s6, 31
	s_delay_alu instid0(SALU_CYCLE_1)
	s_lshl_b64 s[4:5], s[6:7], 3
.LBB0_3:                                ; =>This Inner Loop Header: Depth=1
	global_load_b64 v[5:6], v[3:4], off
	v_add_co_u32 v3, vcc_lo, v3, s4
	v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
	s_add_i32 s3, s3, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s3, 0
	s_waitcnt vmcnt(0)
	v_cmp_neq_f64_e32 vcc_lo, 0, v[5:6]
	v_add_co_ci_u32_e32 v0, vcc_lo, 0, v0, vcc_lo
	s_cbranch_scc0 .LBB0_3
	s_branch .LBB0_5
.LBB0_4:
	v_mov_b32_e32 v0, 0
.LBB0_5:                                ; %Flow33
	s_load_b64 s[0:1], s[0:1], 0x18
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_store_b32 v[1:2], v0, off
.LBB0_6:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z13count_row_nnziiPdiPi
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 7
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z13count_row_nnziiPdiPi, .Lfunc_end0-_Z13count_row_nnziiPdiPi
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 244
; NumSgprs: 18
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z10block_scaniPiS_     ; -- Begin function _Z10block_scaniPiS_
	.globl	_Z10block_scaniPiS_
	.p2align	8
	.type	_Z10block_scaniPiS_,@function
_Z10block_scaniPiS_:                    ; @_Z10block_scaniPiS_
; %bb.0:
	s_clause 0x2
	s_load_b32 s2, s[0:1], 0x24
	s_load_b32 s3, s[0:1], 0x0
	s_load_b128 s[4:7], s[0:1], 0x8
	v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, 0
	s_mov_b32 s8, s15
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s0, s15, s2
	v_lshl_add_u32 v1, s0, 1, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_i32_e32 vcc_lo, s3, v1
	s_and_saveexec_b32 s1, vcc_lo
	s_cbranch_execz .LBB1_2
; %bb.1:
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[1:2]
	v_add_co_u32 v2, s0, s4, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v3, s0, s5, v3, s0
	global_load_b32 v4, v[2:3], off
.LBB1_2:
	s_or_b32 exec_lo, exec_lo, s1
	v_add_nc_u32_e32 v3, s2, v1
	v_lshl_add_u32 v2, v0, 2, 0
	s_delay_alu instid0(VALU_DEP_2)
	v_cmp_gt_u32_e64 s0, s3, v3
	s_waitcnt vmcnt(0)
	ds_store_b32 v2, v4
	s_and_saveexec_b32 s3, s0
	s_cbranch_execz .LBB1_4
; %bb.3:
	v_mov_b32_e32 v4, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 2, v[3:4]
	v_add_co_u32 v4, s1, s4, v4
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v5, s1, s5, v5, s1
	global_load_b32 v5, v[4:5], off
.LBB1_4:
	s_or_b32 exec_lo, exec_lo, s3
	v_lshl_add_u32 v4, s2, 2, v2
	v_lshlrev_b32_e32 v6, 1, v0
	s_lshl_b32 s3, s2, 1
	s_cmp_eq_u32 s2, 0
	s_mov_b32 s9, 1
	s_waitcnt vmcnt(0)
	ds_store_b32 v4, v5
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB1_8
.LBB1_5:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v5, s9, v6
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_i32_e64 s3, v5
	s_cbranch_execz .LBB1_7
; %bb.6:                                ;   in Loop: Header=BB1_5 Depth=1
	v_lshl_add_u32 v7, v6, 2, 0
	v_lshl_add_u32 v5, v5, 2, 0
	ds_load_b32 v7, v7
	ds_load_b32 v8, v5
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v7, v8, v7
	ds_store_b32 v5, v7
.LBB1_7:                                ;   in Loop: Header=BB1_5 Depth=1
	s_or_b32 exec_lo, exec_lo, s2
	v_lshl_or_b32 v6, v6, 1, 1
	s_lshl_b32 s9, s9, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lt_i32 s9, s3
	s_cbranch_scc1 .LBB1_5
.LBB1_8:                                ; %._crit_edge
	s_lshl_b32 s1, s3, 2
	s_waitcnt lgkmcnt(0)
	s_add_i32 s2, s1, 0
	s_barrier
	s_add_i32 s2, s2, -4
	buffer_gl0_inv
	v_mov_b32_e32 v5, s2
	v_cmp_eq_u32_e64 s1, 0, v0
	ds_load_b32 v5, v5
	s_and_saveexec_b32 s10, s1
	s_cbranch_execz .LBB1_10
; %bb.9:
	v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v7, s2
	ds_store_b32 v7, v0
.LBB1_10:
	s_or_b32 exec_lo, exec_lo, s10
	s_cmp_lt_u32 s9, 2
	s_cbranch_scc1 .LBB1_14
.LBB1_11:                               ; %.lr.ph65
                                        ; =>This Inner Loop Header: Depth=1
	v_add_nc_u32_e32 v0, -1, v6
	s_lshr_b32 s10, s9, 1
	s_mov_b32 s11, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v6, 1, v0
	v_add_nc_u32_e32 v0, s10, v6
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e64 s3, v0
	s_cbranch_execz .LBB1_13
; %bb.12:                               ;   in Loop: Header=BB1_11 Depth=1
	v_lshl_add_u32 v0, v0, 2, 0
	v_lshl_add_u32 v7, v6, 2, 0
	ds_load_b32 v8, v0
	ds_load_b32 v9, v7
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v9, v9, v8
	ds_store_b32 v0, v9
	ds_store_b32 v7, v8
.LBB1_13:                               ;   in Loop: Header=BB1_11 Depth=1
	s_or_b32 exec_lo, exec_lo, s11
	s_cmp_gt_u32 s9, 3
	s_mov_b32 s9, s10
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB1_11
.LBB1_14:                               ; %._crit_edge66
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s2, vcc_lo
	s_cbranch_execz .LBB1_16
; %bb.15:
	ds_load_b32 v6, v2
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	v_add_co_u32 v0, vcc_lo, s4, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
	s_waitcnt lgkmcnt(0)
	global_store_b32 v[0:1], v6, off
.LBB1_16:
	s_or_b32 exec_lo, exec_lo, s2
	s_and_saveexec_b32 s2, s0
	s_cbranch_execz .LBB1_18
; %bb.17:
	ds_load_b32 v2, v4
	v_mov_b32_e32 v4, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[3:4]
	v_add_co_u32 v0, vcc_lo, s4, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
	s_waitcnt lgkmcnt(0)
	global_store_b32 v[0:1], v2, off
.LBB1_18:
	s_or_b32 exec_lo, exec_lo, s2
	s_and_saveexec_b32 s0, s1
	s_cbranch_execz .LBB1_20
; %bb.19:
	s_mov_b32 s9, 0
	v_mov_b32_e32 v0, 0
	s_lshl_b64 s[0:1], s[8:9], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s0, s6, s0
	s_addc_u32 s1, s7, s1
	global_store_b32 v0, v5, s[0:1]
.LBB1_20:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z10block_scaniPiS_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 10
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z10block_scaniPiS_, .Lfunc_end1-_Z10block_scaniPiS_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 788
; NumSgprs: 18
; NumVgprs: 10
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 10
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z9block_addiPiS_       ; -- Begin function _Z9block_addiPiS_
	.globl	_Z9block_addiPiS_
	.p2align	8
	.type	_Z9block_addiPiS_,@function
_Z9block_addiPiS_:                      ; @_Z9block_addiPiS_
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x24
	s_load_b128 s[4:7], s[0:1], 0x8
	s_mov_b32 s8, s15
	s_mov_b32 s9, 0
	s_load_b32 s1, s[0:1], 0x0
	s_lshl_b64 s[10:11], s[8:9], 2
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_add_u32 s6, s6, s10
	s_addc_u32 s7, s7, s11
	s_mul_i32 s3, s15, s2
	s_load_b32 s0, s[6:7], 0x0
	v_lshl_add_u32 v0, s3, 1, v0
	s_mov_b32 s3, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e64 s1, v0
	s_cbranch_execz .LBB2_2
; %bb.1:
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[0:1]
	v_add_co_u32 v1, vcc_lo, s4, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
	global_load_b32 v3, v[1:2], off
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_nc_u32_e32 v3, s0, v3
	global_store_b32 v[1:2], v3, off
.LBB2_2:
	s_or_b32 exec_lo, exec_lo, s3
	v_add_nc_u32_e32 v0, s2, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u32_e32 vcc_lo, s1, v0
	s_and_saveexec_b32 s1, vcc_lo
	s_cbranch_execz .LBB2_4
; %bb.3:
	v_mov_b32_e32 v1, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	v_add_co_u32 v0, vcc_lo, s4, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
	global_load_b32 v2, v[0:1], off
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_nc_u32_e32 v2, s0, v2
	global_store_b32 v[0:1], v2, off
.LBB2_4:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z9block_addiPiS_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 4
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_Z9block_addiPiS_, .Lfunc_end2-_Z9block_addiPiS_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 248
; NumSgprs: 18
; NumVgprs: 4
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 4
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z15fill_csr_valuesiiPdiPiS0_S_ ; -- Begin function _Z15fill_csr_valuesiiPdiPiS0_S_
	.globl	_Z15fill_csr_valuesiiPdiPiS0_S_
	.p2align	8
	.type	_Z15fill_csr_valuesiiPdiPiS0_S_,@function
_Z15fill_csr_valuesiiPdiPiS0_S_:        ; @_Z15fill_csr_valuesiiPdiPiS0_S_
; %bb.0:
	s_clause 0x1
	s_load_b32 s4, s[0:1], 0x3c
	s_load_b64 s[2:3], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s4, s4, 0xffff
	s_cmp_gt_i32 s3, 0
	v_mad_u64_u32 v[3:4], null, s15, s4, v[0:1]
	s_cselect_b32 s4, -1, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_cmp_gt_i32_e32 vcc_lo, s2, v3
	s_mov_b32 s2, 0
	s_and_b32 s4, vcc_lo, s4
	s_and_saveexec_b32 s5, s4
	s_cbranch_execz .LBB3_5
; %bb.1:                                ; %.lr.ph
	s_clause 0x1
	s_load_b128 s[4:7], s[0:1], 0x18
	s_load_b64 s[8:9], s[0:1], 0x28
	v_ashrrev_i32_e32 v4, 31, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[3:4]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v0, vcc_lo, s4, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
	global_load_b32 v2, v[0:1], off
	s_clause 0x1
	s_load_b64 s[4:5], s[0:1], 0x8
	s_load_b32 s0, s[0:1], 0x10
	v_lshlrev_b64 v[0:1], 3, v[3:4]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s4, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
	s_ashr_i32 s1, s0, 31
	s_delay_alu instid0(SALU_CYCLE_1)
	s_lshl_b64 s[0:1], s[0:1], 3
.LBB3_2:                                ; =>This Inner Loop Header: Depth=1
	global_load_b64 v[4:5], v[0:1], off
	s_mov_b32 s4, exec_lo
	s_waitcnt vmcnt(0)
	v_cmpx_neq_f64_e32 0, v[4:5]
	s_cbranch_execz .LBB3_4
; %bb.3:                                ;   in Loop: Header=BB3_2 Depth=1
	v_ashrrev_i32_e32 v3, 31, v2
	v_dual_mov_b32 v11, s2 :: v_dual_add_nc_u32 v10, 1, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[6:7], 2, v[2:3]
	v_lshlrev_b64 v[2:3], 3, v[2:3]
	v_add_co_u32 v6, vcc_lo, s6, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v7, vcc_lo, s7, v7, vcc_lo
	v_add_co_u32 v8, vcc_lo, s8, v2
	v_mov_b32_e32 v2, v10
	v_add_co_ci_u32_e32 v9, vcc_lo, s9, v3, vcc_lo
	global_store_b32 v[6:7], v11, off
	global_store_b64 v[8:9], v[4:5], off
.LBB3_4:                                ;   in Loop: Header=BB3_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s4
	v_add_co_u32 v0, vcc_lo, v0, s0
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	s_add_i32 s2, s2, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u32 s3, s2
	s_cbranch_scc1 .LBB3_2
.LBB3_5:                                ; %.loopexit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z15fill_csr_valuesiiPdiPiS0_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 304
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 12
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end3:
	.size	_Z15fill_csr_valuesiiPdiPiS0_S_, .Lfunc_end3-_Z15fill_csr_valuesiiPdiPiS0_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 344
; NumSgprs: 18
; NumVgprs: 12
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 12
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     by_value
      - .offset:         4
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z13count_row_nnziiPdiPi
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z13count_row_nnziiPdiPi.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     7
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         144
        .size:           4
        .value_kind:     hidden_dynamic_lds_size
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z10block_scaniPiS_
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z10block_scaniPiS_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     10
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z9block_addiPiS_
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z9block_addiPiS_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     4
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     by_value
      - .offset:         4
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         52
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         60
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         62
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         64
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         66
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         68
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         70
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         112
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 304
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z15fill_csr_valuesiiPdiPiS0_S_
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z15fill_csr_valuesiiPdiPiS0_S_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     12
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
