#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include "cuda_runtime.h"
#include "device_launch_parameters.h"

#define BLOCK_SIZE 16

__global__ void MatrixMulKernel(float *M, float *N, float *P, int Width)
{ 
    int Row = blockIdx.y * blockDim.y + threadIdx.y; 
    int Col = blockIdx.x * blockDim.x + threadIdx.x;
    
    if( Col < Width && Row < Width) 
    {
    	float Pvalue = 0;
        for(int k = 0; k < Width; ++k) 
        {
            Pvalue += M[Row * Width + k] * N[k * Width + Col];
        }
        P[Row * Width + Col] = Pvalue;
    }
} 


void cpu_matrix_mult(float *M, float *N, float *P, int Width) {
    for (int i = 0; i < Width; ++i) 
    {
        for (int j = 0; j < Width; ++j) 
        {
            int tmp = 0.0;
            for(int k = 0; k < Width; ++k) 
            {
                tmp += M[i * Width + k] * N[k * Width + j];
            }
            P[i * Width + j] = tmp;
        }
    }
}


int main()
{
    int Width =1024;
    srand(3333);

    float *h_a=0, *h_b=0, *h_c=0, *h_cc=0;
    cudaMallocHost((void **) &h_a, sizeof(float)*Width*Width);
    cudaMallocHost((void **) &h_b, sizeof(float)*Width*Width);
    cudaMallocHost((void **) &h_c, sizeof(float)*Width*Width);
    cudaMallocHost((void **) &h_cc, sizeof(float)*Width*Width);	    

    if(h_a==0 || h_b==0 || h_c==0 || h_cc==0)
    {
	printf("No asignacion de memoria\n");
	return 1;
    }
    
    for (int i = 0; i < Width; ++i) {
        for (int j = 0; j < Width; ++j) {
            h_a[i * Width + j] = rand()%1024;
        }
    }

    for (int i = 0; i < Width; ++i) {
        for (int j = 0; j < Width; ++j) {
            h_b[i * Width + j] = rand()%1024;
        }
    }

    float gpu_time_ms, cpu_time_ms;

    cudaEvent_t start, stop;
    cudaEventCreate(&start);
    cudaEventCreate(&stop);

    cudaEventRecord(start, 0);
    float *d_a=0, *d_b=0, *d_c=0;
    cudaMalloc((void **) &d_a, sizeof(float)*Width*Width);
    cudaMalloc((void **) &d_b, sizeof(float)*Width*Width);
    cudaMalloc((void **) &d_c, sizeof(float)*Width*Width);

    if(d_a==0 || d_b==0 || d_c==0)
    {
  		printf("No asignacion Gpu\n");
		return 1;
    }

    cudaMemcpy(d_a, h_a, sizeof(float)*Width*Width, cudaMemcpyHostToDevice);
    cudaMemcpy(d_b, h_b, sizeof(float)*Width*Width, cudaMemcpyHostToDevice);

    dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE); 
    dim3 dimGrid((int)ceil(float(Width)/dimBlock.x), (int)ceil(float(Width)/dimBlock.y));

    MatrixMulKernel<<<dimGrid, dimBlock>>>(d_a, d_b, d_c, Width);

    cudaMemcpy(h_c, d_c, sizeof(int)*Width*Width, cudaMemcpyDeviceToHost);

    cudaThreadSynchronize();
    cudaEventRecord(stop, 0);
    cudaEventSynchronize(stop);

    cudaEventElapsedTime(&gpu_time_ms, start, stop);
    printf("Tiempo transcurrido en GPU: %f ms.\n\n", gpu_time_ms);


    //CPU version
    cudaEventRecord(start, 0);

    cpu_matrix_mult(h_a, h_b, h_cc, Width);

    cudaEventRecord(stop, 0);
    cudaEventSynchronize(stop);
    cudaEventElapsedTime(&cpu_time_ms, start, stop);
    printf("Tiempo transcurrido en CPU: %f ms.\n\n", cpu_time_ms);
	

    //Validando resultados
    int all_ok = 1;
    for (int i = 0; i < Width; ++i)
    {
        for (int j = 0; j < Width; ++j)
        {
            if(h_c[i*Width + j] != h_cc[i*Width + j])
            {
                all_ok = 0;
            }
        }
    }

    if(all_ok)
    {
        printf("Todo bien!!, speedup = %f\n", cpu_time_ms / gpu_time_ms);
    }
    else
    {
        printf("Error\n");
    }

    cudaFree(d_a);
    cudaFree(d_b);
    cudaFree(d_c);
    cudaFreeHost(h_a);
    cudaFreeHost(h_b);
    cudaFreeHost(h_c);
    cudaFreeHost(h_cc);

    cudaEventDestroy(start);
    cudaEventDestroy(stop);
    return 0;
}
















	.file	"tmpxft_0030bcb0_00000000-6_mul_global.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2031:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z15cpu_matrix_multPfS_S_i
	.type	_Z15cpu_matrix_multPfS_S_i, @function
_Z15cpu_matrix_multPfS_S_i:
.LFB2027:
	.cfi_startproc
	endbr64
	movslq	%ecx, %rcx
	xorl	%r8d, %r8d
	movq	%rsi, %r10
	movq	%rdi, %r9
	movq	%rcx, %rax
	movq	%rdx, %r11
	salq	$2, %rcx
	xorl	%esi, %esi
	cmpl	%eax, %r8d
	jl	.L11
	ret
.L11:
	pushq	%r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	pushq	%r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	pushq	%rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
.L7:
	xorl	%edx, %edx
	leaq	(%r9,%rsi), %r12
	leaq	(%r11,%rsi), %r13
.L6:
	leaq	(%r10,%rdx,4), %rbp
	xorl	%edi, %edi
	xorl	%ebx, %ebx
.L4:
	movss	(%r12,%rdi,4), %xmm0
	mulss	0(%rbp), %xmm0
	cvtsi2ssl	%ebx, %xmm1
	incq	%rdi
	addq	%rcx, %rbp
	addss	%xmm1, %xmm0
	cvttss2sil	%xmm0, %ebx
	cmpl	%edi, %eax
	jg	.L4
	cvtsi2ssl	%ebx, %xmm0
	movss	%xmm0, 0(%r13,%rdx,4)
	incq	%rdx
	cmpl	%edx, %eax
	jg	.L6
	incl	%r8d
	addq	%rcx, %rsi
	cmpl	%eax, %r8d
	jl	.L7
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2027:
	.size	_Z15cpu_matrix_multPfS_S_i, .-_Z15cpu_matrix_multPfS_S_i
	.globl	_Z40__device_stub__Z15MatrixMulKernelPfS_S_iPfS_S_i
	.type	_Z40__device_stub__Z15MatrixMulKernelPfS_S_iPfS_S_i, @function
_Z40__device_stub__Z15MatrixMulKernelPfS_S_iPfS_S_i:
.LFB2053:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 4(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L13
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z15MatrixMulKernelPfS_S_i(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L13:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L15
	call	__stack_chk_fail@PLT
.L15:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2053:
	.size	_Z40__device_stub__Z15MatrixMulKernelPfS_S_iPfS_S_i, .-_Z40__device_stub__Z15MatrixMulKernelPfS_S_iPfS_S_i
	.globl	_Z15MatrixMulKernelPfS_S_i
	.type	_Z15MatrixMulKernelPfS_S_i, @function
_Z15MatrixMulKernelPfS_S_i:
.LFB2054:
	.cfi_startproc
	endbr64
	jmp	_Z40__device_stub__Z15MatrixMulKernelPfS_S_iPfS_S_i
	.cfi_endproc
.LFE2054:
	.size	_Z15MatrixMulKernelPfS_S_i, .-_Z15MatrixMulKernelPfS_S_i
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"No asignacion de memoria\n"
.LC1:
	.string	"No asignacion Gpu\n"
.LC2:
	.string	"Tiempo transcurrido en GPU: %f ms.\n\n"
.LC3:
	.string	"Tiempo transcurrido en CPU: %f ms.\n\n"
.LC4:
	.string	"Todo bien!!, speedup = %f\n"
.LC5:
	.string	"Error\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2028:
	.cfi_startproc
	endbr64
	pushq	%r12
	.cfi_def_cfa_offset 16
	.cfi_offset 12, -16
	movl	$3333, %edi
	pushq	%rbp
	.cfi_def_cfa_offset 24
	.cfi_offset 6, -24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset 3, -32
	subq	$112, %rsp
	.cfi_def_cfa_offset 144
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	call	srand@PLT
	xorl	%edx, %edx
	leaq	8(%rsp), %rdi
	movl	$4194304, %esi
	movq	%rdx, 8(%rsp)
	movq	%rdx, 16(%rsp)
	movq	%rdx, 24(%rsp)
	movq	%rdx, 32(%rsp)
	call	cudaMallocHost@PLT
	leaq	16(%rsp), %rdi
	movl	$4194304, %esi
	call	cudaMallocHost@PLT
	leaq	24(%rsp), %rdi
	movl	$4194304, %esi
	call	cudaMallocHost@PLT
	leaq	32(%rsp), %rdi
	movl	$4194304, %esi
	call	cudaMallocHost@PLT
	cmpq	$0, 8(%rsp)
	je	.L19
	cmpq	$0, 16(%rsp)
	je	.L19
	cmpq	$0, 24(%rsp)
	je	.L19
	xorl	%ebp, %ebp
	cmpq	$0, 32(%rsp)
	movl	$1024, %r12d
	jne	.L20
.L19:
	leaq	.LC0(%rip), %rsi
	jmp	.L49
.L20:
	xorl	%ebx, %ebx
.L22:
	call	rand@PLT
	leaq	0(,%rbx,4), %rcx
	incq	%rbx
	addq	8(%rsp), %rcx
	cltd
	idivl	%r12d
	cvtsi2ssl	%edx, %xmm0
	movss	%xmm0, (%rcx,%rbp)
	cmpq	$1024, %rbx
	jne	.L22
	addq	$4096, %rbp
	cmpq	$4194304, %rbp
	jne	.L20
	xorl	%ebp, %ebp
	movl	$1024, %r12d
.L23:
	xorl	%ebx, %ebx
.L24:
	call	rand@PLT
	leaq	0(,%rbx,4), %rcx
	incq	%rbx
	addq	16(%rsp), %rcx
	cltd
	idivl	%r12d
	cvtsi2ssl	%edx, %xmm0
	movss	%xmm0, (%rcx,%rbp)
	cmpq	$1024, %rbx
	jne	.L24
	addq	$4096, %rbp
	cmpq	$4194304, %rbp
	jne	.L23
	leaq	40(%rsp), %rdi
	call	cudaEventCreate@PLT
	leaq	48(%rsp), %rdi
	call	cudaEventCreate@PLT
	movq	40(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	xorl	%eax, %eax
	leaq	56(%rsp), %rdi
	movl	$4194304, %esi
	movq	%rax, 56(%rsp)
	movq	%rax, 64(%rsp)
	movq	%rax, 72(%rsp)
	call	cudaMalloc@PLT
	leaq	64(%rsp), %rdi
	movl	$4194304, %esi
	call	cudaMalloc@PLT
	leaq	72(%rsp), %rdi
	movl	$4194304, %esi
	call	cudaMalloc@PLT
	movq	56(%rsp), %rdi
	testq	%rdi, %rdi
	je	.L26
	cmpq	$0, 64(%rsp)
	je	.L26
	cmpq	$0, 72(%rsp)
	jne	.L27
.L26:
	leaq	.LC1(%rip), %rsi
.L49:
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movl	$1, %eax
	jmp	.L18
.L27:
	movq	8(%rsp), %rsi
	movl	$1, %ecx
	movl	$4194304, %edx
	call	cudaMemcpy@PLT
	movq	16(%rsp), %rsi
	movq	64(%rsp), %rdi
	movl	$1, %ecx
	movl	$4194304, %edx
	call	cudaMemcpy@PLT
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$1, %ecx
	movabsq	$274877907008, %rdi
	movl	$1, %esi
	movabsq	$68719476752, %rdx
	movl	$1, 100(%rsp)
	movq	%rdi, 92(%rsp)
	movq	%rdx, 80(%rsp)
	movl	$1, 88(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L29
	movq	72(%rsp), %rdx
	movq	64(%rsp), %rsi
	movl	$1024, %ecx
	movq	56(%rsp), %rdi
	call	_Z40__device_stub__Z15MatrixMulKernelPfS_S_iPfS_S_i
.L29:
	movq	72(%rsp), %rsi
	movq	24(%rsp), %rdi
	movl	$2, %ecx
	movl	$4194304, %edx
	call	cudaMemcpy@PLT
	call	cudaThreadSynchronize@PLT
	movq	48(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movq	48(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movq	48(%rsp), %rdx
	movq	40(%rsp), %rsi
	movq	%rsp, %rdi
	call	cudaEventElapsedTime@PLT
	leaq	.LC2(%rip), %rsi
	movl	$2, %edi
	movb	$1, %al
	cvtss2sd	(%rsp), %xmm0
	call	__printf_chk@PLT
	movq	40(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movq	32(%rsp), %rdx
	movq	16(%rsp), %rsi
	movl	$1024, %ecx
	movq	8(%rsp), %rdi
	call	_Z15cpu_matrix_multPfS_S_i
	movq	48(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movq	48(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movq	48(%rsp), %rdx
	movq	40(%rsp), %rsi
	leaq	4(%rsp), %rdi
	call	cudaEventElapsedTime@PLT
	leaq	.LC3(%rip), %rsi
	movl	$2, %edi
	movb	$1, %al
	cvtss2sd	4(%rsp), %xmm0
	call	__printf_chk@PLT
	movq	24(%rsp), %rdi
	movq	32(%rsp), %r8
	xorl	%edx, %edx
	movl	$1, %esi
.L30:
	movq	%rdx, %rax
	movl	$1024, %ecx
.L33:
	movss	(%rdi,%rax), %xmm0
	ucomiss	(%r8,%rax), %xmm0
	jp	.L40
	je	.L31
.L40:
	xorl	%esi, %esi
.L31:
	addq	$4, %rax
	decl	%ecx
	jne	.L33
	addq	$4096, %rdx
	cmpq	$4194304, %rdx
	jne	.L30
	testl	%esi, %esi
	je	.L35
	leaq	.LC4(%rip), %rsi
	movl	$2, %edi
	movb	$1, %al
	movss	4(%rsp), %xmm0
	divss	(%rsp), %xmm0
	cvtss2sd	%xmm0, %xmm0
	call	__printf_chk@PLT
	jmp	.L36
.L35:
	leaq	.LC5(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
.L36:
	movq	56(%rsp), %rdi
	call	cudaFree@PLT
	movq	64(%rsp), %rdi
	call	cudaFree@PLT
	movq	72(%rsp), %rdi
	call	cudaFree@PLT
	movq	8(%rsp), %rdi
	call	cudaFreeHost@PLT
	movq	16(%rsp), %rdi
	call	cudaFreeHost@PLT
	movq	24(%rsp), %rdi
	call	cudaFreeHost@PLT
	movq	32(%rsp), %rdi
	call	cudaFreeHost@PLT
	movq	40(%rsp), %rdi
	call	cudaEventDestroy@PLT
	movq	48(%rsp), %rdi
	call	cudaEventDestroy@PLT
	xorl	%eax, %eax
.L18:
	movq	104(%rsp), %rdx
	subq	%fs:40, %rdx
	je	.L37
	call	__stack_chk_fail@PLT
.L37:
	addq	$112, %rsp
	.cfi_def_cfa_offset 32
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2028:
	.size	main, .-main
	.section	.rodata.str1.1
.LC6:
	.string	"_Z15MatrixMulKernelPfS_S_i"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2056:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC6(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z15MatrixMulKernelPfS_S_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2056:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include "hip/hip_runtime.h"


#define BLOCK_SIZE 16

__global__ void MatrixMulKernel(float *M, float *N, float *P, int Width)
{ 
    int Row = blockIdx.y * blockDim.y + threadIdx.y; 
    int Col = blockIdx.x * blockDim.x + threadIdx.x;
    
    if( Col < Width && Row < Width) 
    {
    	float Pvalue = 0;
        for(int k = 0; k < Width; ++k) 
        {
            Pvalue += M[Row * Width + k] * N[k * Width + Col];
        }
        P[Row * Width + Col] = Pvalue;
    }
} 


void cpu_matrix_mult(float *M, float *N, float *P, int Width) {
    for (int i = 0; i < Width; ++i) 
    {
        for (int j = 0; j < Width; ++j) 
        {
            int tmp = 0.0;
            for(int k = 0; k < Width; ++k) 
            {
                tmp += M[i * Width + k] * N[k * Width + j];
            }
            P[i * Width + j] = tmp;
        }
    }
}


int main()
{
    int Width =1024;
    srand(3333);

    float *h_a=0, *h_b=0, *h_c=0, *h_cc=0;
    hipHostMalloc((void **) &h_a, sizeof(float)*Width*Width, hipHostMallocDefault);
    hipHostMalloc((void **) &h_b, sizeof(float)*Width*Width, hipHostMallocDefault);
    hipHostMalloc((void **) &h_c, sizeof(float)*Width*Width, hipHostMallocDefault);
    hipHostMalloc((void **) &h_cc, sizeof(float)*Width*Width, hipHostMallocDefault);	    

    if(h_a==0 || h_b==0 || h_c==0 || h_cc==0)
    {
	printf("No asignacion de memoria\n");
	return 1;
    }
    
    for (int i = 0; i < Width; ++i) {
        for (int j = 0; j < Width; ++j) {
            h_a[i * Width + j] = rand()%1024;
        }
    }

    for (int i = 0; i < Width; ++i) {
        for (int j = 0; j < Width; ++j) {
            h_b[i * Width + j] = rand()%1024;
        }
    }

    float gpu_time_ms, cpu_time_ms;

    hipEvent_t start, stop;
    hipEventCreate(&start);
    hipEventCreate(&stop);

    hipEventRecord(start, 0);
    float *d_a=0, *d_b=0, *d_c=0;
    hipMalloc((void **) &d_a, sizeof(float)*Width*Width);
    hipMalloc((void **) &d_b, sizeof(float)*Width*Width);
    hipMalloc((void **) &d_c, sizeof(float)*Width*Width);

    if(d_a==0 || d_b==0 || d_c==0)
    {
  		printf("No asignacion Gpu\n");
		return 1;
    }

    hipMemcpy(d_a, h_a, sizeof(float)*Width*Width, hipMemcpyHostToDevice);
    hipMemcpy(d_b, h_b, sizeof(float)*Width*Width, hipMemcpyHostToDevice);

    dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE); 
    dim3 dimGrid((int)ceil(float(Width)/dimBlock.x), (int)ceil(float(Width)/dimBlock.y));

    MatrixMulKernel<<<dimGrid, dimBlock>>>(d_a, d_b, d_c, Width);

    hipMemcpy(h_c, d_c, sizeof(int)*Width*Width, hipMemcpyDeviceToHost);

    hipDeviceSynchronize();
    hipEventRecord(stop, 0);
    hipEventSynchronize(stop);

    hipEventElapsedTime(&gpu_time_ms, start, stop);
    printf("Tiempo transcurrido en GPU: %f ms.\n\n", gpu_time_ms);


    //CPU version
    hipEventRecord(start, 0);

    cpu_matrix_mult(h_a, h_b, h_cc, Width);

    hipEventRecord(stop, 0);
    hipEventSynchronize(stop);
    hipEventElapsedTime(&cpu_time_ms, start, stop);
    printf("Tiempo transcurrido en CPU: %f ms.\n\n", cpu_time_ms);
	

    //Validando resultados
    int all_ok = 1;
    for (int i = 0; i < Width; ++i)
    {
        for (int j = 0; j < Width; ++j)
        {
            if(h_c[i*Width + j] != h_cc[i*Width + j])
            {
                all_ok = 0;
            }
        }
    }

    if(all_ok)
    {
        printf("Todo bien!!, speedup = %f\n", cpu_time_ms / gpu_time_ms);
    }
    else
    {
        printf("Error\n");
    }

    hipFree(d_a);
    hipFree(d_b);
    hipFree(d_c);
    hipHostFree(h_a);
    hipHostFree(h_b);
    hipHostFree(h_c);
    hipHostFree(h_cc);

    hipEventDestroy(start);
    hipEventDestroy(stop);
    return 0;
}
















	.text
	.file	"mul_global.hip"
	.globl	_Z30__device_stub__MatrixMulKernelPfS_S_i # -- Begin function _Z30__device_stub__MatrixMulKernelPfS_S_i
	.type	_Z30__device_stub__MatrixMulKernelPfS_S_i,@function
_Z30__device_stub__MatrixMulKernelPfS_S_i: # @_Z30__device_stub__MatrixMulKernelPfS_S_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	4(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z15MatrixMulKernelPfS_S_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z30__device_stub__MatrixMulKernelPfS_S_i, .Lfunc_end0-_Z30__device_stub__MatrixMulKernelPfS_S_i
	.cfi_endproc
                                        # -- End function
	.globl	_Z15cpu_matrix_multPfS_S_i      # -- Begin function _Z15cpu_matrix_multPfS_S_i
	.type	_Z15cpu_matrix_multPfS_S_i,@function
_Z15cpu_matrix_multPfS_S_i:             # @_Z15cpu_matrix_multPfS_S_i
	.cfi_startproc
# %bb.0:
	testl	%ecx, %ecx
	jle	.LBB1_8
# %bb.1:                                # %.preheader26.lr.ph
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%ecx, %eax
	leaq	(,%rax,4), %r8
	xorl	%r9d, %r9d
	xorl	%r10d, %r10d
.LBB1_2:                                # %.preheader.lr.ph
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB1_3 Depth 2
                                        #       Child Loop BB1_4 Depth 3
	movl	%r9d, %r11d
	leaq	(%rdi,%r11,4), %r11
	movq	%r10, %rbx
	imulq	%rax, %rbx
	leaq	(%rdx,%rbx,4), %rbx
	movq	%rsi, %r14
	xorl	%r15d, %r15d
.LBB1_3:                                # %.preheader
                                        #   Parent Loop BB1_2 Depth=1
                                        # =>  This Loop Header: Depth=2
                                        #       Child Loop BB1_4 Depth 3
	xorl	%r12d, %r12d
	movq	%r14, %r13
	xorl	%ebp, %ebp
.LBB1_4:                                #   Parent Loop BB1_2 Depth=1
                                        #     Parent Loop BB1_3 Depth=2
                                        # =>    This Inner Loop Header: Depth=3
	movss	(%r11,%r12,4), %xmm0            # xmm0 = mem[0],zero,zero,zero
	mulss	(%r13), %xmm0
	xorps	%xmm1, %xmm1
	cvtsi2ss	%ebp, %xmm1
	addss	%xmm0, %xmm1
	cvttss2si	%xmm1, %ebp
	incq	%r12
	addq	%r8, %r13
	cmpq	%r12, %rax
	jne	.LBB1_4
# %bb.5:                                # %._crit_edge
                                        #   in Loop: Header=BB1_3 Depth=2
	xorps	%xmm0, %xmm0
	cvtsi2ss	%ebp, %xmm0
	movss	%xmm0, (%rbx,%r15,4)
	incq	%r15
	addq	$4, %r14
	cmpq	%rax, %r15
	jne	.LBB1_3
# %bb.6:                                # %._crit_edge30
                                        #   in Loop: Header=BB1_2 Depth=1
	incq	%r10
	addl	%ecx, %r9d
	cmpq	%rax, %r10
	jne	.LBB1_2
# %bb.7:
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	.cfi_restore %rbx
	.cfi_restore %r12
	.cfi_restore %r13
	.cfi_restore %r14
	.cfi_restore %r15
	.cfi_restore %rbp
.LBB1_8:                                # %._crit_edge32
	retq
.Lfunc_end1:
	.size	_Z15cpu_matrix_multPfS_S_i, .Lfunc_end1-_Z15cpu_matrix_multPfS_S_i
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$88, %rsp
	.cfi_def_cfa_offset 144
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	$3333, %edi                     # imm = 0xD05
	callq	srand
	xorl	%r13d, %r13d
	leaq	64(%rsp), %rbx
	movq	%r13, (%rbx)
	leaq	16(%rsp), %r14
	movq	%r13, (%r14)
	leaq	56(%rsp), %r15
	movq	%r13, (%r15)
	leaq	48(%rsp), %r12
	movq	%r13, (%r12)
	movl	$4194304, %esi                  # imm = 0x400000
	movq	%rbx, %rdi
	xorl	%edx, %edx
	callq	hipHostMalloc
	movl	$4194304, %esi                  # imm = 0x400000
	movq	%r14, %rdi
	xorl	%edx, %edx
	callq	hipHostMalloc
	movl	$4194304, %esi                  # imm = 0x400000
	movq	%r15, %rdi
	xorl	%edx, %edx
	callq	hipHostMalloc
	movl	$4194304, %esi                  # imm = 0x400000
	movq	%r12, %rdi
	xorl	%edx, %edx
	callq	hipHostMalloc
	cmpq	%r13, (%rbx)
	je	.LBB2_27
# %bb.1:
	cmpq	$0, 16(%rsp)
	je	.LBB2_27
# %bb.2:
	cmpq	$0, 56(%rsp)
	je	.LBB2_27
# %bb.3:
	cmpq	$0, 48(%rsp)
	je	.LBB2_27
# %bb.4:                                # %.preheader87.preheader
	xorl	%ebx, %ebx
	xorl	%r14d, %r14d
.LBB2_5:                                # %.preheader87
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB2_6 Depth 2
	xorl	%r15d, %r15d
.LBB2_6:                                #   Parent Loop BB2_5 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	callq	rand
                                        # kill: def $eax killed $eax def $rax
	leal	1023(%rax), %ecx
	testl	%eax, %eax
	cmovnsl	%eax, %ecx
	andl	$-1024, %ecx                    # imm = 0xFC00
	subl	%ecx, %eax
	xorps	%xmm0, %xmm0
	cvtsi2ss	%eax, %xmm0
	movq	64(%rsp), %rax
	addq	%rbx, %rax
	movss	%xmm0, (%rax,%r15,4)
	incq	%r15
	cmpq	$1024, %r15                     # imm = 0x400
	jne	.LBB2_6
# %bb.7:                                #   in Loop: Header=BB2_5 Depth=1
	incq	%r14
	addq	$4096, %rbx                     # imm = 0x1000
	cmpq	$1024, %r14                     # imm = 0x400
	jne	.LBB2_5
# %bb.8:                                # %.preheader85.preheader
	xorl	%ebx, %ebx
	xorl	%r14d, %r14d
.LBB2_9:                                # %.preheader85
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB2_10 Depth 2
	xorl	%r15d, %r15d
.LBB2_10:                               #   Parent Loop BB2_9 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	callq	rand
                                        # kill: def $eax killed $eax def $rax
	leal	1023(%rax), %ecx
	testl	%eax, %eax
	cmovnsl	%eax, %ecx
	andl	$-1024, %ecx                    # imm = 0xFC00
	subl	%ecx, %eax
	xorps	%xmm0, %xmm0
	cvtsi2ss	%eax, %xmm0
	movq	16(%rsp), %rax
	addq	%rbx, %rax
	movss	%xmm0, (%rax,%r15,4)
	incq	%r15
	cmpq	$1024, %r15                     # imm = 0x400
	jne	.LBB2_10
# %bb.11:                               #   in Loop: Header=BB2_9 Depth=1
	incq	%r14
	addq	$4096, %rbx                     # imm = 0x1000
	cmpq	$1024, %r14                     # imm = 0x400
	jne	.LBB2_9
# %bb.12:
	leaq	40(%rsp), %rbx
	movq	%rbx, %rdi
	callq	hipEventCreate
	leaq	8(%rsp), %rdi
	callq	hipEventCreate
	movq	(%rbx), %rdi
	xorl	%r12d, %r12d
	xorl	%esi, %esi
	callq	hipEventRecord
	leaq	80(%rsp), %rbx
	movq	%r12, (%rbx)
	leaq	32(%rsp), %r14
	movq	%r12, (%r14)
	leaq	24(%rsp), %r15
	movq	%r12, (%r15)
	movl	$4194304, %esi                  # imm = 0x400000
	movq	%rbx, %rdi
	callq	hipMalloc
	movl	$4194304, %esi                  # imm = 0x400000
	movq	%r14, %rdi
	callq	hipMalloc
	movl	$4194304, %esi                  # imm = 0x400000
	movq	%r15, %rdi
	callq	hipMalloc
	movq	(%rbx), %rdi
	testq	%rdi, %rdi
	je	.LBB2_15
# %bb.13:
	cmpq	$0, 32(%rsp)
	je	.LBB2_15
# %bb.14:
	cmpq	$0, 24(%rsp)
	je	.LBB2_15
# %bb.16:
	movq	64(%rsp), %rsi
	movl	$1, %ebp
	movl	$4194304, %edx                  # imm = 0x400000
	movl	$1, %ecx
	callq	hipMemcpy
	movq	32(%rsp), %rdi
	movq	16(%rsp), %rsi
	movl	$4194304, %edx                  # imm = 0x400000
	movl	$1, %ecx
	callq	hipMemcpy
	xorl	%r14d, %r14d
	movabsq	$274877907008, %rdi             # imm = 0x4000000040
	movabsq	$68719476752, %rdx              # imm = 0x1000000010
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_18
# %bb.17:
	movq	80(%rsp), %rdi
	movq	32(%rsp), %rsi
	movq	24(%rsp), %rdx
	movl	$1024, %ecx                     # imm = 0x400
	callq	_Z30__device_stub__MatrixMulKernelPfS_S_i
.LBB2_18:
	movq	56(%rsp), %rdi
	movq	24(%rsp), %rsi
	movl	$4194304, %edx                  # imm = 0x400000
	movl	$2, %ecx
	callq	hipMemcpy
	callq	hipDeviceSynchronize
	movq	8(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	8(%rsp), %rdi
	callq	hipEventSynchronize
	movq	40(%rsp), %rsi
	movq	8(%rsp), %rdx
	leaq	76(%rsp), %rbx
	movq	%rbx, %rdi
	callq	hipEventElapsedTime
	cvtss2sd	(%rbx), %xmm0
	movl	$.L.str.2, %edi
	movb	$1, %al
	callq	printf
	movq	40(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	64(%rsp), %rdi
	movq	16(%rsp), %rsi
	movq	48(%rsp), %rdx
	movl	$1024, %ecx                     # imm = 0x400
	callq	_Z15cpu_matrix_multPfS_S_i
	movq	8(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	8(%rsp), %rdi
	callq	hipEventSynchronize
	movq	40(%rsp), %rsi
	movq	8(%rsp), %rdx
	leaq	72(%rsp), %rbx
	movq	%rbx, %rdi
	callq	hipEventElapsedTime
	xorps	%xmm0, %xmm0
	cvtss2sd	(%rbx), %xmm0
	movl	$.L.str.3, %edi
	movb	$1, %al
	callq	printf
	movq	56(%rsp), %rax
	movq	48(%rsp), %rcx
	movl	$4096, %edx                     # imm = 0x1000
	xorl	%esi, %esi
.LBB2_19:                               # %.preheader
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB2_20 Depth 2
	xorl	%edi, %edi
.LBB2_20:                               #   Parent Loop BB2_19 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movss	(%rax,%rdi,4), %xmm0            # xmm0 = mem[0],zero,zero,zero
	ucomiss	(%rcx,%rdi,4), %xmm0
	cmovnel	%r14d, %ebp
	cmovpl	%r14d, %ebp
	incq	%rdi
	cmpq	$1024, %rdi                     # imm = 0x400
	jne	.LBB2_20
# %bb.21:                               #   in Loop: Header=BB2_19 Depth=1
	incq	%rsi
	addq	%rdx, %rcx
	addq	%rdx, %rax
	cmpq	$1024, %rsi                     # imm = 0x400
	jne	.LBB2_19
# %bb.22:
	testl	%ebp, %ebp
	je	.LBB2_24
# %bb.23:
	movss	72(%rsp), %xmm0                 # xmm0 = mem[0],zero,zero,zero
	divss	76(%rsp), %xmm0
	cvtss2sd	%xmm0, %xmm0
	movl	$.L.str.4, %edi
	movb	$1, %al
	callq	printf
	jmp	.LBB2_25
.LBB2_27:
	movl	$.Lstr.2, %edi
	jmp	.LBB2_28
.LBB2_15:
	movl	$.Lstr.1, %edi
.LBB2_28:
	callq	puts@PLT
	movl	$1, %eax
	jmp	.LBB2_26
.LBB2_24:
	movl	$.Lstr, %edi
	callq	puts@PLT
.LBB2_25:
	movq	80(%rsp), %rdi
	callq	hipFree
	movq	32(%rsp), %rdi
	callq	hipFree
	movq	24(%rsp), %rdi
	callq	hipFree
	movq	64(%rsp), %rdi
	callq	hipHostFree
	movq	16(%rsp), %rdi
	callq	hipHostFree
	movq	56(%rsp), %rdi
	callq	hipHostFree
	movq	48(%rsp), %rdi
	callq	hipHostFree
	movq	40(%rsp), %rdi
	callq	hipEventDestroy
	movq	8(%rsp), %rdi
	callq	hipEventDestroy
	xorl	%eax, %eax
.LBB2_26:
	addq	$88, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	main, .Lfunc_end2-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB3_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB3_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z15MatrixMulKernelPfS_S_i, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end3:
	.size	__hip_module_ctor, .Lfunc_end3-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB4_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB4_2:
	retq
.Lfunc_end4:
	.size	__hip_module_dtor, .Lfunc_end4-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z15MatrixMulKernelPfS_S_i,@object # @_Z15MatrixMulKernelPfS_S_i
	.section	.rodata,"a",@progbits
	.globl	_Z15MatrixMulKernelPfS_S_i
	.p2align	3, 0x0
_Z15MatrixMulKernelPfS_S_i:
	.quad	_Z30__device_stub__MatrixMulKernelPfS_S_i
	.size	_Z15MatrixMulKernelPfS_S_i, 8

	.type	.L.str.2,@object                # @.str.2
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str.2:
	.asciz	"Tiempo transcurrido en GPU: %f ms.\n\n"
	.size	.L.str.2, 37

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"Tiempo transcurrido en CPU: %f ms.\n\n"
	.size	.L.str.3, 37

	.type	.L.str.4,@object                # @.str.4
.L.str.4:
	.asciz	"Todo bien!!, speedup = %f\n"
	.size	.L.str.4, 27

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z15MatrixMulKernelPfS_S_i"
	.size	.L__unnamed_1, 27

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.type	.Lstr,@object                   # @str
	.section	.rodata.str1.1,"aMS",@progbits,1
.Lstr:
	.asciz	"Error"
	.size	.Lstr, 6

	.type	.Lstr.1,@object                 # @str.1
.Lstr.1:
	.asciz	"No asignacion Gpu"
	.size	.Lstr.1, 18

	.type	.Lstr.2,@object                 # @str.2
.Lstr.2:
	.asciz	"No asignacion de memoria"
	.size	.Lstr.2, 25

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z30__device_stub__MatrixMulKernelPfS_S_i
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z15MatrixMulKernelPfS_S_i
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z15MatrixMulKernelPfS_S_i ; -- Begin function _Z15MatrixMulKernelPfS_S_i
	.globl	_Z15MatrixMulKernelPfS_S_i
	.p2align	8
	.type	_Z15MatrixMulKernelPfS_S_i,@function
_Z15MatrixMulKernelPfS_S_i:             ; @_Z15MatrixMulKernelPfS_S_i
; %bb.0:
	s_clause 0x1
	s_load_b32 s3, s[0:1], 0x2c
	s_load_b32 s2, s[0:1], 0x18
	v_bfe_u32 v1, v0, 10, 10
	v_and_b32_e32 v4, 0x3ff, v0
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s4, s3, 16
	s_and_b32 s3, s3, 0xffff
	v_mad_u64_u32 v[2:3], null, s15, s4, v[1:2]
	v_mad_u64_u32 v[0:1], null, s14, s3, v[4:5]
	s_mov_b32 s3, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_max_i32_e32 v1, v2, v0
	v_cmpx_gt_i32_e64 s2, v1
	s_cbranch_execz .LBB0_6
; %bb.1:                                ; %.preheader
	s_clause 0x1
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b64 s[0:1], s[0:1], 0x10
	v_mul_lo_u32 v1, v2, s2
	s_cmp_lt_i32 s2, 1
	s_cbranch_scc1 .LBB0_4
; %bb.2:                                ; %.lr.ph.preheader
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_ashrrev_i32_e32 v2, 31, v1
	v_mov_b32_e32 v6, 0
	v_mov_b32_e32 v4, v0
	s_mov_b32 s3, s2
	v_lshlrev_b64 v[2:3], 2, v[1:2]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s4, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
.LBB0_3:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	v_ashrrev_i32_e32 v5, 31, v4
	s_add_i32 s3, s3, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_cmp_eq_u32 s3, 0
	v_lshlrev_b64 v[7:8], 2, v[4:5]
	v_add_nc_u32_e32 v4, s2, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v7, vcc_lo, s6, v7
	v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
	global_load_b32 v5, v[2:3], off
	global_load_b32 v7, v[7:8], off
	v_add_co_u32 v2, vcc_lo, v2, 4
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v6, v5, v7
	s_cbranch_scc0 .LBB0_3
	s_branch .LBB0_5
.LBB0_4:
	v_mov_b32_e32 v6, 0
.LBB0_5:                                ; %Flow46
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v0, v1, v0
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v0, vcc_lo, s0, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	global_store_b32 v[0:1], v6, off
.LBB0_6:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z15MatrixMulKernelPfS_S_i
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 9
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z15MatrixMulKernelPfS_S_i, .Lfunc_end0-_Z15MatrixMulKernelPfS_S_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 332
; NumSgprs: 18
; NumVgprs: 9
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 9
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z15MatrixMulKernelPfS_S_i
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z15MatrixMulKernelPfS_S_i.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     9
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
