/*Realizar un programa CUDA que dado un vector V de N números enteros multiplique a 
cada número por una constante C, se deben realizar dos implementaciones:
a.Tanto C como N deben ser pasados como parámetros al kernel.
b.Tanto C como N deben estar almacenados en la memoria de constantes de la GPU*/
#include "cuda_runtime.h"
#include "device_launch_parameters.h"

#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <math.h>
//M and N number of threads (grid and block)


float secuential(const int array[] , int dim){
	float mean=0;
	for(int i=0; i<dim;i++){
		mean+=array[i];
	}
	mean=mean/dim;
	float sum=0;
	for(int i=0; i<dim;i++){
		sum+=(array[i]-mean)*(array[i]-mean);
	}
	return sqrt(sum/(dim-1));

}

     
__global__ void addAll( const int array[] , int dim,float result[], const int thread_number)
{
    int index = blockIdx.x* blockDim.x* blockDim.y* blockDim.z+threadIdx.z* blockDim.y* blockDim.x+ threadIdx.y* blockDim.x+ threadIdx.x;
 	//printf("sum:%i\n",  result[0]);
	if(index<dim){
		if(dim<=thread_number){ //if more threads than array size
		//	printf("Thread %i; Adding value of index %i\n", index, index, array[index]);
			atomicAdd(result,array[index]);
		}
		else{ //if less threads than array size
			if(index!=thread_number-1){//if not last thread deal with size_array/thread_nb array entries
				for(int i=index*(int)(dim/thread_number); i< index*(int)(dim/thread_number)+(int)(dim/thread_number); i++){
			//		printf("Thread %i; Adding value of index %i\n", index, i, array[i]);
					atomicAdd(result,array[i]);
				}
			}
			else{ //if last thread deal with all remaining array entries
				for(int i=index*(int)(dim/thread_number); i< dim; i++){
				//	printf("Thread %i; Adding value of index %i\n",index, i, array[i]);
					atomicAdd(result,array[i]);
				}
			}
		}
		//printf("sum:%i\n",  result[0]);
	}
	
} 
__global__ void sigma( const int array[] , int dim,float result[], const float mean, const int thread_number)
{
	 int index = blockIdx.x* blockDim.x* blockDim.y* blockDim.z+threadIdx.z* blockDim.y* blockDim.x+ threadIdx.y* blockDim.x+ threadIdx.x;
 	//printf("sum:%i\n",  result[0]);
	if(index<dim){
		if(dim<=thread_number){ //if more threads than array size
			//printf("Thread %i; Adding value of index %i\n", index, index, array[index]);
			atomicAdd(result,(array[index]-mean)*(array[index]-mean));
		}
		else{ //if less threads than array size
			if(index!=thread_number-1){//if not last thread deal with size_array/thread_nb array entries
				for(int i=index*(int)(dim/thread_number); i< index*(int)(dim/thread_number)+(int)(dim/thread_number); i++){
					//printf("Thread %i; Adding value of index %i\n", index, i, array[i]);
					atomicAdd(result,(array[i]-mean)*(array[i]-mean));
				}
			}
			else{ //if last thread deal with all remaining array entries
				for(int i=index*(int)(dim/thread_number); i< dim; i++){
					//printf("Thread %i; Adding value of index %i\n",index, i, array[i]);
					atomicAdd(result,(array[i]-mean)*(array[i]-mean));
				}
			}
		}
		//printf("sum:%i\n",  result[0]);
	}


}

    
int main(int argc, char *argv[]){
	//Measure time
	clock_t time_begin;
	time_begin=clock();
    // pointers to host & device arrays
     int *device_array = 0;
     int *host_array = 0;
	 int size_array=9;
	 float *d_sum=NULL;
	 float *h_sum= 0;
	 float mean;
	 float final_res;
	 int M=1, N=1;
	 if(argc == 4){
		 size_array=atoi(argv[1]);
		 N=atoi(argv[2]);
		 M=atoi(argv[3]);
	 }
	 h_sum=( float*)malloc(sizeof( float));
	 h_sum[0]=0;
      // malloc a host array
     host_array = (int*)malloc( size_array * sizeof(int));
	
    for(int i=0; i<size_array; i++){
        host_array[i]=rand()%10;
       // printf("%i\t", host_array[i]);
    }
    printf("\n");
	
	
     // cudaMalloc a device array
     cudaMalloc(&device_array,size_array * sizeof(int));    
	 cudaError_t er=cudaMalloc(&d_sum, sizeof(float));  
    // download and inspect the result on the host:
    cudaError_t e=cudaMemcpy(device_array, host_array, sizeof(int)*size_array, cudaMemcpyHostToDevice); 
	cudaError_t error=cudaMemcpy(d_sum, h_sum, sizeof(int), cudaMemcpyHostToDevice);
	//cudaerrorinvalidvalue(11)

    dim3 bloque(N,N); //Bloque bidimensional de N*N hilos
    dim3 grid(M,M);  //Grid bidimensional de M*M bloques
	int thread_number= N*N*M*M;
    addAll<<<grid, bloque>>>(device_array, size_array , d_sum, thread_number);
    cudaThreadSynchronize();
    // download and inspect the result on the host:
   //cudaMemcpy(host_array, device_array, sizeof(int)*size_array, cudaMemcpyDeviceToHost); 
	cudaMemcpy(h_sum, d_sum, sizeof(int), cudaMemcpyDeviceToHost); 
   
    printf("Sum of array: %f\n", h_sum[0]);
	mean=h_sum[0]/size_array;
	h_sum[0]=0;

	cudaMemcpy(d_sum, h_sum, sizeof(int), cudaMemcpyHostToDevice);
	sigma<<<grid, bloque>>>(device_array, size_array , d_sum, mean, thread_number);
	cudaThreadSynchronize();
	cudaMemcpy(h_sum, d_sum, sizeof(int), cudaMemcpyDeviceToHost); 

	 printf("Sigma: %f\n", h_sum[0]);
	
	final_res = sqrt(h_sum[0]/(size_array-1));
	printf("GPU time: %f seconds\n", (((float)clock() - (float)time_begin) / 1000000.0F ) * 1000  ); //1.215s
	printf("GPU result: %f\n", final_res);
	time_begin=clock();
	float cpu_res=secuential(host_array, size_array);
	printf("CPU time: %f seconds\n", (((float)clock() - (float)time_begin) / 1000000.0F ) * 1000  ); //1.215s
	printf("CPU result: %f\n", cpu_res);
	if(final_res==cpu_res)
		printf("CPU and GPU have same result\n");
	else
		printf("CPU and GPU have different result\n");
     // deallocate memory
      free(host_array);free(h_sum);
      cudaFree(device_array); cudaFree(d_sum);

	

}
	.file	"tmpxft_0020fc4e_00000000-6_entrega1_2_backup.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2031:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z10secuentialPKii
	.type	_Z10secuentialPKii, @function
_Z10secuentialPKii:
.LFB2027:
	.cfi_startproc
	endbr64
	xorl	%eax, %eax
	xorps	%xmm0, %xmm0
.L3:
	cmpl	%eax, %esi
	jle	.L8
	cvtsi2ssl	(%rdi,%rax,4), %xmm1
	incq	%rax
	addss	%xmm1, %xmm0
	jmp	.L3
.L8:
	cvtsi2ssl	%esi, %xmm1
	movaps	%xmm0, %xmm2
	xorps	%xmm0, %xmm0
	xorl	%eax, %eax
	divss	%xmm1, %xmm2
.L5:
	cmpl	%eax, %esi
	jle	.L9
	cvtsi2ssl	(%rdi,%rax,4), %xmm1
	incq	%rax
	subss	%xmm2, %xmm1
	mulss	%xmm1, %xmm1
	addss	%xmm1, %xmm0
	jmp	.L5
.L9:
	decl	%esi
	cvtsi2ssl	%esi, %xmm1
	divss	%xmm1, %xmm0
	jmp	sqrtf@PLT
	.cfi_endproc
.LFE2027:
	.size	_Z10secuentialPKii, .-_Z10secuentialPKii
	.globl	_Z30__device_stub__Z6addAllPKiiPfiPKiiPfi
	.type	_Z30__device_stub__Z6addAllPKiiPfiPKiiPfi, @function
_Z30__device_stub__Z6addAllPKiiPfiPKiiPfi:
.LFB2053:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movl	%esi, 20(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 16(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L10
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z6addAllPKiiPfi(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L10:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L12
	call	__stack_chk_fail@PLT
.L12:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2053:
	.size	_Z30__device_stub__Z6addAllPKiiPfiPKiiPfi, .-_Z30__device_stub__Z6addAllPKiiPfiPKiiPfi
	.globl	_Z6addAllPKiiPfi
	.type	_Z6addAllPKiiPfi, @function
_Z6addAllPKiiPfi:
.LFB2054:
	.cfi_startproc
	endbr64
	jmp	_Z30__device_stub__Z6addAllPKiiPfiPKiiPfi
	.cfi_endproc
.LFE2054:
	.size	_Z6addAllPKiiPfi, .-_Z6addAllPKiiPfi
	.globl	_Z30__device_stub__Z5sigmaPKiiPffiPKiiPffi
	.type	_Z30__device_stub__Z5sigmaPKiiPffiPKiiPffi, @function
_Z30__device_stub__Z5sigmaPKiiPffiPKiiPffi:
.LFB2055:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rdi
	movl	%esi, 20(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	32(%rsp), %rdx
	movl	%ecx, 4(%rsp)
	leaq	40(%rsp), %rcx
	movss	%xmm0, 16(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L15
	pushq	40(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z5sigmaPKiiPffi(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 176
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L15:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L17
	call	__stack_chk_fail@PLT
.L17:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2055:
	.size	_Z30__device_stub__Z5sigmaPKiiPffiPKiiPffi, .-_Z30__device_stub__Z5sigmaPKiiPffiPKiiPffi
	.globl	_Z5sigmaPKiiPffi
	.type	_Z5sigmaPKiiPffi, @function
_Z5sigmaPKiiPffi:
.LFB2056:
	.cfi_startproc
	endbr64
	jmp	_Z30__device_stub__Z5sigmaPKiiPffiPKiiPffi
	.cfi_endproc
.LFE2056:
	.size	_Z5sigmaPKiiPffi, .-_Z5sigmaPKiiPffi
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC1:
	.string	"\n"
.LC2:
	.string	"Sum of array: %f\n"
.LC3:
	.string	"Sigma: %f\n"
.LC6:
	.string	"GPU time: %f seconds\n"
.LC7:
	.string	"GPU result: %f\n"
.LC8:
	.string	"CPU time: %f seconds\n"
.LC9:
	.string	"CPU result: %f\n"
.LC10:
	.string	"CPU and GPU have same result\n"
.LC11:
	.string	"CPU and GPU have different result\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2028:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movl	%edi, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movq	%rsi, %rbx
	subq	$72, %rsp
	.cfi_def_cfa_offset 128
	movq	%fs:40, %rax
	movq	%rax, 56(%rsp)
	xorl	%eax, %eax
	call	clock@PLT
	movq	%rax, %r15
	xorl	%eax, %eax
	movq	%rax, 16(%rsp)
	movq	%rax, 24(%rsp)
	cmpl	$4, %ebp
	jne	.L30
	movq	8(%rbx), %rdi
	call	atoi@PLT
	movq	16(%rbx), %rdi
	movl	%eax, %r12d
	call	atoi@PLT
	movq	24(%rbx), %rdi
	movl	%eax, %ebp
	call	atoi@PLT
	movl	%eax, %r14d
	jmp	.L21
.L30:
	movl	$1, %ebp
	movl	$1, %r14d
	movl	$9, %r12d
.L21:
	movl	$4, %edi
	call	malloc@PLT
	movl	$0x00000000, (%rax)
	movq	%rax, %rbx
	movslq	%r12d, %rax
	salq	$2, %rax
	movq	%rax, %rdi
	movq	%rax, (%rsp)
	call	malloc@PLT
	xorl	%ecx, %ecx
	movq	%rax, %r13
.L22:
	cmpl	%ecx, %r12d
	jle	.L34
	movq	%rcx, 8(%rsp)
	call	rand@PLT
	movl	$10, %ecx
	cltd
	idivl	%ecx
	movq	8(%rsp), %rcx
	movl	%edx, 0(%r13,%rcx,4)
	incq	%rcx
	jmp	.L22
.L34:
	leaq	.LC1(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movq	(%rsp), %rsi
	leaq	16(%rsp), %rdi
	call	cudaMalloc@PLT
	leaq	24(%rsp), %rdi
	movl	$4, %esi
	call	cudaMalloc@PLT
	movq	(%rsp), %rdx
	movq	16(%rsp), %rdi
	movq	%r13, %rsi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	movq	24(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbx, %rsi
	movl	$4, %edx
	call	cudaMemcpy@PLT
	movl	%ebp, 32(%rsp)
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	%ebp, 36(%rsp)
	imull	%r14d, %ebp
	movq	32(%rsp), %rdx
	movl	$1, %ecx
	movl	%r14d, 44(%rsp)
	movl	$1, %esi
	movl	%r14d, 48(%rsp)
	movq	44(%rsp), %rdi
	imull	%ebp, %ebp
	movl	$1, 40(%rsp)
	movl	$1, 52(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L24
	movq	24(%rsp), %rdx
	movq	16(%rsp), %rdi
	movl	%ebp, %ecx
	movl	%r12d, %esi
	call	_Z30__device_stub__Z6addAllPKiiPfiPKiiPfi
.L24:
	call	cudaThreadSynchronize@PLT
	movq	24(%rsp), %rsi
	movl	$2, %ecx
	movq	%rbx, %rdi
	movl	$4, %edx
	call	cudaMemcpy@PLT
	movl	$2, %edi
	movb	$1, %al
	leaq	.LC2(%rip), %rsi
	cvtss2sd	(%rbx), %xmm0
	call	__printf_chk@PLT
	movss	(%rbx), %xmm0
	movl	$0x00000000, (%rbx)
	movq	24(%rsp), %rdi
	movl	$1, %ecx
	movl	$4, %edx
	movq	%rbx, %rsi
	movss	%xmm0, (%rsp)
	call	cudaMemcpy@PLT
	movl	40(%rsp), %ecx
	movl	52(%rsp), %esi
	xorl	%r9d, %r9d
	movq	32(%rsp), %rdx
	movq	44(%rsp), %rdi
	xorl	%r8d, %r8d
	call	__cudaPushCallConfiguration@PLT
	movss	(%rsp), %xmm0
	testl	%eax, %eax
	jne	.L25
	cvtsi2ssl	%r12d, %xmm1
	movq	24(%rsp), %rdx
	movl	%ebp, %ecx
	movl	%r12d, %esi
	movq	16(%rsp), %rdi
	divss	%xmm1, %xmm0
	call	_Z30__device_stub__Z5sigmaPKiiPffiPKiiPffi
.L25:
	call	cudaThreadSynchronize@PLT
	movq	24(%rsp), %rsi
	movl	$2, %ecx
	movq	%rbx, %rdi
	movl	$4, %edx
	call	cudaMemcpy@PLT
	movl	$2, %edi
	movb	$1, %al
	leaq	.LC3(%rip), %rsi
	cvtss2sd	(%rbx), %xmm0
	call	__printf_chk@PLT
	leal	-1(%r12), %eax
	movss	(%rbx), %xmm0
	cvtsi2ssl	%eax, %xmm1
	divss	%xmm1, %xmm0
	call	sqrtf@PLT
	movss	%xmm0, (%rsp)
	call	clock@PLT
	cvtsi2ssq	%r15, %xmm1
	movl	$2, %edi
	leaq	.LC6(%rip), %rsi
	cvtsi2ssq	%rax, %xmm0
	movb	$1, %al
	subss	%xmm1, %xmm0
	divss	.LC4(%rip), %xmm0
	mulss	.LC5(%rip), %xmm0
	cvtss2sd	%xmm0, %xmm0
	call	__printf_chk@PLT
	movl	$2, %edi
	movb	$1, %al
	leaq	.LC7(%rip), %rsi
	cvtss2sd	(%rsp), %xmm0
	call	__printf_chk@PLT
	call	clock@PLT
	movl	%r12d, %esi
	movq	%r13, %rdi
	movq	%rax, %r14
	call	_Z10secuentialPKii
	movd	%xmm0, %ebp
	call	clock@PLT
	cvtsi2ssq	%r14, %xmm1
	movl	$2, %edi
	leaq	.LC8(%rip), %rsi
	cvtsi2ssq	%rax, %xmm0
	movb	$1, %al
	subss	%xmm1, %xmm0
	divss	.LC4(%rip), %xmm0
	mulss	.LC5(%rip), %xmm0
	cvtss2sd	%xmm0, %xmm0
	call	__printf_chk@PLT
	movd	%ebp, %xmm2
	movl	$2, %edi
	leaq	.LC9(%rip), %rsi
	movb	$1, %al
	cvtss2sd	%xmm2, %xmm0
	call	__printf_chk@PLT
	movd	%ebp, %xmm3
	ucomiss	(%rsp), %xmm3
	jp	.L26
	leaq	.LC10(%rip), %rsi
	je	.L33
.L26:
	leaq	.LC11(%rip), %rsi
.L33:
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movq	%r13, %rdi
	call	free@PLT
	movq	%rbx, %rdi
	call	free@PLT
	movq	16(%rsp), %rdi
	call	cudaFree@PLT
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	movq	56(%rsp), %rax
	subq	%fs:40, %rax
	je	.L29
	call	__stack_chk_fail@PLT
.L29:
	addq	$72, %rsp
	.cfi_def_cfa_offset 56
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2028:
	.size	main, .-main
	.section	.rodata.str1.1
.LC12:
	.string	"_Z5sigmaPKiiPffi"
.LC13:
	.string	"_Z6addAllPKiiPfi"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2058:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC12(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z5sigmaPKiiPffi(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC13(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z6addAllPKiiPfi(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2058:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst4,"aM",@progbits,4
	.align 4
.LC4:
	.long	1232348160
	.align 4
.LC5:
	.long	1148846080
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

/*Realizar un programa CUDA que dado un vector V de N números enteros multiplique a 
cada número por una constante C, se deben realizar dos implementaciones:
a.Tanto C como N deben ser pasados como parámetros al kernel.
b.Tanto C como N deben estar almacenados en la memoria de constantes de la GPU*/
#include "hip/hip_runtime.h"


#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <math.h>
//M and N number of threads (grid and block)


float secuential(const int array[] , int dim){
	float mean=0;
	for(int i=0; i<dim;i++){
		mean+=array[i];
	}
	mean=mean/dim;
	float sum=0;
	for(int i=0; i<dim;i++){
		sum+=(array[i]-mean)*(array[i]-mean);
	}
	return sqrt(sum/(dim-1));

}

     
__global__ void addAll( const int array[] , int dim,float result[], const int thread_number)
{
    int index = blockIdx.x* blockDim.x* blockDim.y* blockDim.z+threadIdx.z* blockDim.y* blockDim.x+ threadIdx.y* blockDim.x+ threadIdx.x;
 	//printf("sum:%i\n",  result[0]);
	if(index<dim){
		if(dim<=thread_number){ //if more threads than array size
		//	printf("Thread %i; Adding value of index %i\n", index, index, array[index]);
			atomicAdd(result,array[index]);
		}
		else{ //if less threads than array size
			if(index!=thread_number-1){//if not last thread deal with size_array/thread_nb array entries
				for(int i=index*(int)(dim/thread_number); i< index*(int)(dim/thread_number)+(int)(dim/thread_number); i++){
			//		printf("Thread %i; Adding value of index %i\n", index, i, array[i]);
					atomicAdd(result,array[i]);
				}
			}
			else{ //if last thread deal with all remaining array entries
				for(int i=index*(int)(dim/thread_number); i< dim; i++){
				//	printf("Thread %i; Adding value of index %i\n",index, i, array[i]);
					atomicAdd(result,array[i]);
				}
			}
		}
		//printf("sum:%i\n",  result[0]);
	}
	
} 
__global__ void sigma( const int array[] , int dim,float result[], const float mean, const int thread_number)
{
	 int index = blockIdx.x* blockDim.x* blockDim.y* blockDim.z+threadIdx.z* blockDim.y* blockDim.x+ threadIdx.y* blockDim.x+ threadIdx.x;
 	//printf("sum:%i\n",  result[0]);
	if(index<dim){
		if(dim<=thread_number){ //if more threads than array size
			//printf("Thread %i; Adding value of index %i\n", index, index, array[index]);
			atomicAdd(result,(array[index]-mean)*(array[index]-mean));
		}
		else{ //if less threads than array size
			if(index!=thread_number-1){//if not last thread deal with size_array/thread_nb array entries
				for(int i=index*(int)(dim/thread_number); i< index*(int)(dim/thread_number)+(int)(dim/thread_number); i++){
					//printf("Thread %i; Adding value of index %i\n", index, i, array[i]);
					atomicAdd(result,(array[i]-mean)*(array[i]-mean));
				}
			}
			else{ //if last thread deal with all remaining array entries
				for(int i=index*(int)(dim/thread_number); i< dim; i++){
					//printf("Thread %i; Adding value of index %i\n",index, i, array[i]);
					atomicAdd(result,(array[i]-mean)*(array[i]-mean));
				}
			}
		}
		//printf("sum:%i\n",  result[0]);
	}


}

    
int main(int argc, char *argv[]){
	//Measure time
	clock_t time_begin;
	time_begin=clock();
    // pointers to host & device arrays
     int *device_array = 0;
     int *host_array = 0;
	 int size_array=9;
	 float *d_sum=NULL;
	 float *h_sum= 0;
	 float mean;
	 float final_res;
	 int M=1, N=1;
	 if(argc == 4){
		 size_array=atoi(argv[1]);
		 N=atoi(argv[2]);
		 M=atoi(argv[3]);
	 }
	 h_sum=( float*)malloc(sizeof( float));
	 h_sum[0]=0;
      // malloc a host array
     host_array = (int*)malloc( size_array * sizeof(int));
	
    for(int i=0; i<size_array; i++){
        host_array[i]=rand()%10;
       // printf("%i\t", host_array[i]);
    }
    printf("\n");
	
	
     // cudaMalloc a device array
     hipMalloc(&device_array,size_array * sizeof(int));    
	 hipError_t er=hipMalloc(&d_sum, sizeof(float));  
    // download and inspect the result on the host:
    hipError_t e=hipMemcpy(device_array, host_array, sizeof(int)*size_array, hipMemcpyHostToDevice); 
	hipError_t error=hipMemcpy(d_sum, h_sum, sizeof(int), hipMemcpyHostToDevice);
	//cudaerrorinvalidvalue(11)

    dim3 bloque(N,N); //Bloque bidimensional de N*N hilos
    dim3 grid(M,M);  //Grid bidimensional de M*M bloques
	int thread_number= N*N*M*M;
    addAll<<<grid, bloque>>>(device_array, size_array , d_sum, thread_number);
    hipDeviceSynchronize();
    // download and inspect the result on the host:
   //cudaMemcpy(host_array, device_array, sizeof(int)*size_array, cudaMemcpyDeviceToHost); 
	hipMemcpy(h_sum, d_sum, sizeof(int), hipMemcpyDeviceToHost); 
   
    printf("Sum of array: %f\n", h_sum[0]);
	mean=h_sum[0]/size_array;
	h_sum[0]=0;

	hipMemcpy(d_sum, h_sum, sizeof(int), hipMemcpyHostToDevice);
	sigma<<<grid, bloque>>>(device_array, size_array , d_sum, mean, thread_number);
	hipDeviceSynchronize();
	hipMemcpy(h_sum, d_sum, sizeof(int), hipMemcpyDeviceToHost); 

	 printf("Sigma: %f\n", h_sum[0]);
	
	final_res = sqrt(h_sum[0]/(size_array-1));
	printf("GPU time: %f seconds\n", (((float)clock() - (float)time_begin) / 1000000.0F ) * 1000  ); //1.215s
	printf("GPU result: %f\n", final_res);
	time_begin=clock();
	float cpu_res=secuential(host_array, size_array);
	printf("CPU time: %f seconds\n", (((float)clock() - (float)time_begin) / 1000000.0F ) * 1000  ); //1.215s
	printf("CPU result: %f\n", cpu_res);
	if(final_res==cpu_res)
		printf("CPU and GPU have same result\n");
	else
		printf("CPU and GPU have different result\n");
     // deallocate memory
      free(host_array);free(h_sum);
      hipFree(device_array); hipFree(d_sum);

	

}
	.text
	.file	"entrega1_2_backup.hip"
	.globl	_Z10secuentialPKii              # -- Begin function _Z10secuentialPKii
	.type	_Z10secuentialPKii,@function
_Z10secuentialPKii:                     # @_Z10secuentialPKii
	.cfi_startproc
# %bb.0:
	xorps	%xmm1, %xmm1
	xorps	%xmm0, %xmm0
	testl	%esi, %esi
	jle	.LBB0_5
# %bb.1:                                # %.lr.ph.preheader
	movl	%esi, %eax
	xorps	%xmm2, %xmm2
	xorl	%ecx, %ecx
.LBB0_2:                                # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	xorps	%xmm0, %xmm0
	cvtsi2ssl	(%rdi,%rcx,4), %xmm0
	addss	%xmm0, %xmm2
	incq	%rcx
	cmpq	%rcx, %rax
	jne	.LBB0_2
# %bb.3:                                # %._crit_edge
	testl	%esi, %esi
	jle	.LBB0_4
# %bb.7:                                # %.lr.ph28.preheader
	xorps	%xmm0, %xmm0
	cvtsi2ss	%esi, %xmm0
	divss	%xmm0, %xmm2
	xorps	%xmm0, %xmm0
	xorl	%ecx, %ecx
.LBB0_8:                                # %.lr.ph28
                                        # =>This Inner Loop Header: Depth=1
	xorps	%xmm3, %xmm3
	cvtsi2ssl	(%rdi,%rcx,4), %xmm3
	subss	%xmm2, %xmm3
	mulss	%xmm3, %xmm3
	addss	%xmm3, %xmm0
	incq	%rcx
	cmpq	%rcx, %rax
	jne	.LBB0_8
	jmp	.LBB0_5
.LBB0_4:
	xorps	%xmm0, %xmm0
.LBB0_5:                                # %._crit_edge29
	decl	%esi
	xorps	%xmm2, %xmm2
	cvtsi2ss	%esi, %xmm2
	divss	%xmm2, %xmm0
	ucomiss	%xmm1, %xmm0
	jb	sqrtf                           # TAILCALL
# %bb.6:                                # %._crit_edge29.split
	sqrtss	%xmm0, %xmm0
	retq
.Lfunc_end0:
	.size	_Z10secuentialPKii, .Lfunc_end0-_Z10secuentialPKii
	.cfi_endproc
                                        # -- End function
	.globl	_Z21__device_stub__addAllPKiiPfi # -- Begin function _Z21__device_stub__addAllPKiiPfi
	.type	_Z21__device_stub__addAllPKiiPfi,@function
_Z21__device_stub__addAllPKiiPfi:       # @_Z21__device_stub__addAllPKiiPfi
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	12(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	32(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z6addAllPKiiPfi, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z21__device_stub__addAllPKiiPfi, .Lfunc_end1-_Z21__device_stub__addAllPKiiPfi
	.cfi_endproc
                                        # -- End function
	.globl	_Z20__device_stub__sigmaPKiiPffi # -- Begin function _Z20__device_stub__sigmaPKiiPffi
	.type	_Z20__device_stub__sigmaPKiiPffi,@function
_Z20__device_stub__sigmaPKiiPffi:       # @_Z20__device_stub__sigmaPKiiPffi
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	12(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	32(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	8(%rsp), %rdx
	movss	%xmm0, (%rdx)
	leaq	4(%rsp), %r8
	movl	%ecx, (%r8)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%r8, 32(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z5sigmaPKiiPffi, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z20__device_stub__sigmaPKiiPffi, .Lfunc_end2-_Z20__device_stub__sigmaPKiiPffi
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0                          # -- Begin function main
.LCPI3_0:
	.long	0x49742400                      # float 1.0E+6
.LCPI3_1:
	.long	0x447a0000                      # float 1000
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$40, %rsp
	.cfi_def_cfa_offset 96
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%rsi, %rbx
	movl	%edi, %ebp
	callq	clock
	xorl	%ecx, %ecx
	movq	%rcx, 24(%rsp)
	movq	%rcx, 8(%rsp)
	cmpl	$4, %ebp
	movq	%rax, 32(%rsp)                  # 8-byte Spill
	jne	.LBB3_1
# %bb.2:
	movq	8(%rbx), %rdi
	callq	atoi
	movl	%eax, %r14d
	movq	16(%rbx), %rdi
	callq	atoi
	movl	%eax, 4(%rsp)                   # 4-byte Spill
	movq	24(%rbx), %rdi
	callq	atoi
	movl	%eax, %ebp
	jmp	.LBB3_3
.LBB3_1:
	movl	$9, %r14d
	movl	$1, 4(%rsp)                     # 4-byte Folded Spill
	movl	$1, %ebp
.LBB3_3:
	movl	$4, %edi
	callq	malloc
	movq	%rax, %rbx
	movl	$0, (%rax)
	movq	%r14, 16(%rsp)                  # 8-byte Spill
	movslq	%r14d, %r15
	leaq	(,%r15,4), %r12
	movq	%r12, %rdi
	callq	malloc
	movq	%rax, %r14
	testl	%r15d, %r15d
	jle	.LBB3_6
# %bb.4:                                # %.lr.ph.preheader
	movl	16(%rsp), %r15d                 # 4-byte Reload
	xorl	%r13d, %r13d
.LBB3_5:                                # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	callq	rand
	cltq
	imulq	$1717986919, %rax, %rcx         # imm = 0x66666667
	movq	%rcx, %rdx
	shrq	$63, %rdx
	sarq	$34, %rcx
	addl	%edx, %ecx
	addl	%ecx, %ecx
	leal	(%rcx,%rcx,4), %ecx
	subl	%ecx, %eax
	movl	%eax, (%r14,%r13,4)
	incq	%r13
	cmpq	%r13, %r15
	jne	.LBB3_5
.LBB3_6:                                # %._crit_edge
	movl	$10, %edi
	callq	putchar@PLT
	leaq	24(%rsp), %r15
	movq	%r15, %rdi
	movq	%r12, %rsi
	callq	hipMalloc
	leaq	8(%rsp), %r13
	movl	$4, %esi
	movq	%r13, %rdi
	callq	hipMalloc
	movq	(%r15), %rdi
	movq	%r14, %rsi
	movq	%r12, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%r13), %rdi
	movl	$4, %edx
	movq	%rbx, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movl	4(%rsp), %ecx                   # 4-byte Reload
	movl	%ecx, %eax
	movq	%rax, %r12
	shlq	$32, %r12
	orq	%rax, %r12
	movl	%ebp, %eax
	movq	%rax, %r15
	shlq	$32, %r15
	orq	%rax, %r15
	imull	%ecx, %ebp
	imull	%ebp, %ebp
	movq	%r15, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	movq	16(%rsp), %r13                  # 8-byte Reload
	jne	.LBB3_8
# %bb.7:
	movq	24(%rsp), %rdi
	movq	8(%rsp), %rdx
	movl	%r13d, %esi
	movl	%ebp, %ecx
	callq	_Z21__device_stub__addAllPKiiPfi
.LBB3_8:
	callq	hipDeviceSynchronize
	movq	8(%rsp), %rsi
	movl	$4, %edx
	movq	%rbx, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	cvtss2sd	(%rbx), %xmm0
	movl	$.L.str.1, %edi
	movb	$1, %al
	callq	printf
	movss	(%rbx), %xmm0                   # xmm0 = mem[0],zero,zero,zero
	movss	%xmm0, 4(%rsp)                  # 4-byte Spill
	movl	$0, (%rbx)
	movq	8(%rsp), %rdi
	movl	$4, %edx
	movq	%rbx, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	%r15, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB3_10
# %bb.9:
	cvtsi2ss	%r13d, %xmm1
	movss	4(%rsp), %xmm0                  # 4-byte Reload
                                        # xmm0 = mem[0],zero,zero,zero
	divss	%xmm1, %xmm0
	movq	24(%rsp), %rdi
	movq	8(%rsp), %rdx
	movl	%r13d, %esi
	movl	%ebp, %ecx
	callq	_Z20__device_stub__sigmaPKiiPffi
.LBB3_10:
	callq	hipDeviceSynchronize
	movq	8(%rsp), %rsi
	movl	$4, %edx
	movq	%rbx, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	xorps	%xmm0, %xmm0
	cvtss2sd	(%rbx), %xmm0
	movl	$.L.str.2, %edi
	movb	$1, %al
	callq	printf
	movss	(%rbx), %xmm0                   # xmm0 = mem[0],zero,zero,zero
	leal	-1(%r13), %eax
	xorps	%xmm1, %xmm1
	cvtsi2ss	%eax, %xmm1
	divss	%xmm1, %xmm0
	xorps	%xmm1, %xmm1
	ucomiss	%xmm1, %xmm0
	jb	.LBB3_12
# %bb.11:
	sqrtss	%xmm0, %xmm0
	jmp	.LBB3_13
.LBB3_12:                               # %call.sqrt
	callq	sqrtf
.LBB3_13:                               # %.split
	movss	%xmm0, 4(%rsp)                  # 4-byte Spill
	callq	clock
	xorps	%xmm0, %xmm0
	cvtsi2ss	%rax, %xmm0
	xorps	%xmm1, %xmm1
	cvtsi2ssq	32(%rsp), %xmm1         # 8-byte Folded Reload
	subss	%xmm1, %xmm0
	divss	.LCPI3_0(%rip), %xmm0
	mulss	.LCPI3_1(%rip), %xmm0
	cvtss2sd	%xmm0, %xmm0
	movl	$.L.str.3, %edi
	movb	$1, %al
	callq	printf
	xorps	%xmm0, %xmm0
	cvtss2sd	4(%rsp), %xmm0                  # 4-byte Folded Reload
	movl	$.L.str.4, %edi
	movb	$1, %al
	callq	printf
	callq	clock
	movq	%rax, %r15
	movq	%r14, %rdi
	movl	%r13d, %esi
	callq	_Z10secuentialPKii
	movss	%xmm0, 16(%rsp)                 # 4-byte Spill
	callq	clock
	xorps	%xmm0, %xmm0
	cvtsi2ss	%rax, %xmm0
	xorps	%xmm1, %xmm1
	cvtsi2ss	%r15, %xmm1
	subss	%xmm1, %xmm0
	divss	.LCPI3_0(%rip), %xmm0
	mulss	.LCPI3_1(%rip), %xmm0
	cvtss2sd	%xmm0, %xmm0
	movl	$.L.str.5, %edi
	movb	$1, %al
	callq	printf
	xorps	%xmm0, %xmm0
	cvtss2sd	16(%rsp), %xmm0                 # 4-byte Folded Reload
	movl	$.L.str.6, %edi
	movb	$1, %al
	callq	printf
	movss	4(%rsp), %xmm0                  # 4-byte Reload
                                        # xmm0 = mem[0],zero,zero,zero
	ucomiss	16(%rsp), %xmm0                 # 4-byte Folded Reload
	movl	$.Lstr, %eax
	movl	$.Lstr.1, %edi
	cmovneq	%rax, %rdi
	cmovpq	%rax, %rdi
	callq	puts@PLT
	movq	%r14, %rdi
	callq	free
	movq	%rbx, %rdi
	callq	free
	movq	24(%rsp), %rdi
	callq	hipFree
	movq	8(%rsp), %rdi
	callq	hipFree
	xorl	%eax, %eax
	addq	$40, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	main, .Lfunc_end3-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB4_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB4_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z6addAllPKiiPfi, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z5sigmaPKiiPffi, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end4:
	.size	__hip_module_ctor, .Lfunc_end4-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB5_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB5_2:
	retq
.Lfunc_end5:
	.size	__hip_module_dtor, .Lfunc_end5-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z6addAllPKiiPfi,@object        # @_Z6addAllPKiiPfi
	.section	.rodata,"a",@progbits
	.globl	_Z6addAllPKiiPfi
	.p2align	3, 0x0
_Z6addAllPKiiPfi:
	.quad	_Z21__device_stub__addAllPKiiPfi
	.size	_Z6addAllPKiiPfi, 8

	.type	_Z5sigmaPKiiPffi,@object        # @_Z5sigmaPKiiPffi
	.globl	_Z5sigmaPKiiPffi
	.p2align	3, 0x0
_Z5sigmaPKiiPffi:
	.quad	_Z20__device_stub__sigmaPKiiPffi
	.size	_Z5sigmaPKiiPffi, 8

	.type	.L.str.1,@object                # @.str.1
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str.1:
	.asciz	"Sum of array: %f\n"
	.size	.L.str.1, 18

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"Sigma: %f\n"
	.size	.L.str.2, 11

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"GPU time: %f seconds\n"
	.size	.L.str.3, 22

	.type	.L.str.4,@object                # @.str.4
.L.str.4:
	.asciz	"GPU result: %f\n"
	.size	.L.str.4, 16

	.type	.L.str.5,@object                # @.str.5
.L.str.5:
	.asciz	"CPU time: %f seconds\n"
	.size	.L.str.5, 22

	.type	.L.str.6,@object                # @.str.6
.L.str.6:
	.asciz	"CPU result: %f\n"
	.size	.L.str.6, 16

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z6addAllPKiiPfi"
	.size	.L__unnamed_1, 17

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z5sigmaPKiiPffi"
	.size	.L__unnamed_2, 17

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.type	.Lstr,@object                   # @str
	.section	.rodata.str1.1,"aMS",@progbits,1
.Lstr:
	.asciz	"CPU and GPU have different result"
	.size	.Lstr, 34

	.type	.Lstr.1,@object                 # @str.1
.Lstr.1:
	.asciz	"CPU and GPU have same result"
	.size	.Lstr.1, 29

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z21__device_stub__addAllPKiiPfi
	.addrsig_sym _Z20__device_stub__sigmaPKiiPffi
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z6addAllPKiiPfi
	.addrsig_sym _Z5sigmaPKiiPffi
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z6addAllPKiiPfi        ; -- Begin function _Z6addAllPKiiPfi
	.globl	_Z6addAllPKiiPfi
	.p2align	8
	.type	_Z6addAllPKiiPfi,@function
_Z6addAllPKiiPfi:                       ; @_Z6addAllPKiiPfi
; %bb.0:
	s_clause 0x1
	s_load_b64 s[2:3], s[0:1], 0x2c
	s_load_b32 s4, s[0:1], 0x8
	v_bfe_u32 v1, v0, 20, 10
	s_waitcnt lgkmcnt(0)
	s_and_b32 s3, s3, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[2:3], null, s15, s3, v[1:2]
	v_bfe_u32 v1, v0, 10, 10
	s_lshr_b32 s3, s2, 16
	v_and_b32_e32 v0, 0x3ff, v0
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[3:4], null, v2, s3, v[1:2]
	v_mad_u64_u32 v[1:2], null, v3, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e64 s4, v1
	s_cbranch_execz .LBB0_31
; %bb.1:
	s_clause 0x2
	s_load_b32 s5, s[0:1], 0x18
	s_load_b64 s[2:3], s[0:1], 0x0
	s_load_b64 s[0:1], s[0:1], 0x10
	s_mov_b32 s6, -1
	s_waitcnt lgkmcnt(0)
	s_cmp_gt_i32 s4, s5
	s_cbranch_scc1 .LBB0_9
; %bb.2:
	v_ashrrev_i32_e32 v2, 31, v1
	s_mov_b32 s6, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[1:2]
	v_add_co_u32 v2, vcc_lo, s2, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
	global_load_b32 v0, v[2:3], off
	s_waitcnt vmcnt(0)
	v_cvt_f32_i32_e32 v2, v0
	v_bfrev_b32_e32 v0, 1
.LBB0_3:                                ; %ComputeLoop
                                        ; =>This Inner Loop Header: Depth=1
	s_ctz_i32_b32 s7, s6
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	v_readlane_b32 s8, v2, s7
	s_lshl_b32 s7, 1, s7
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_not1_b32 s6, s6, s7
	s_cmp_lg_u32 s6, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f32_e32 v0, s8, v0
	s_cbranch_scc1 .LBB0_3
; %bb.4:                                ; %ComputeEnd
	v_mbcnt_lo_u32_b32 v2, exec_lo, 0
	s_mov_b32 s6, 0
	s_mov_b32 s7, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v2
	s_xor_b32 s7, exec_lo, s7
	s_cbranch_execz .LBB0_8
; %bb.5:
	s_load_b32 s8, s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v3, s8
	s_mov_b32 s8, 0
.LBB0_6:                                ; %atomicrmw.start
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f32_e32 v2, v3, v0
	global_atomic_cmpswap_b32 v2, v4, v[2:3], s[0:1] glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u32_e32 vcc_lo, v2, v3
	v_mov_b32_e32 v3, v2
	s_or_b32 s8, vcc_lo, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s8
	s_cbranch_execnz .LBB0_6
; %bb.7:                                ; %Flow
	s_or_b32 exec_lo, exec_lo, s8
.LBB0_8:                                ; %Flow85
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s7
.LBB0_9:                                ; %Flow96
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s6
	s_cbranch_vccz .LBB0_31
; %bb.10:
	s_ashr_i32 s6, s5, 31
	s_ashr_i32 s10, s4, 31
	s_add_i32 s7, s5, s6
	s_add_i32 s11, s4, s10
	s_xor_b32 s7, s7, s6
	s_xor_b32 s11, s11, s10
	v_cvt_f32_u32_e32 v0, s7
	s_sub_i32 s9, 0, s7
	s_add_i32 s5, s5, -1
	s_xor_b32 s6, s10, s6
	v_cmp_ne_u32_e32 vcc_lo, s5, v1
	v_rcp_iflag_f32_e32 v0, v0
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v0, 0x4f7ffffe, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v0, v0
	v_readfirstlane_b32 s8, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s9, s9, s8
	s_mul_hi_u32 s9, s8, s9
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s8, s8, s9
	s_mul_hi_u32 s8, s11, s8
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_mul_i32 s9, s8, s7
	s_add_i32 s10, s8, 1
	s_sub_i32 s9, s11, s9
	s_sub_i32 s11, s9, s7
	s_cmp_ge_u32 s9, s7
	s_cselect_b32 s8, s10, s8
	s_cselect_b32 s9, s11, s9
	s_add_i32 s10, s8, 1
	s_cmp_ge_u32 s9, s7
	s_cselect_b32 s7, s10, s8
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b32 s7, s7, s6
	s_sub_i32 s6, s7, s6
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_mul_lo_u32 v0, s6, v1
	s_and_saveexec_b32 s5, vcc_lo
	s_xor_b32 s5, exec_lo, s5
	s_cbranch_execz .LBB0_21
; %bb.11:
	s_cmp_lt_i32 s6, 1
	s_cbranch_scc1 .LBB0_21
; %bb.12:                               ; %.lr.ph.preheader
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_mov_b32 v4, 0 :: v_dual_add_nc_u32 v3, s6, v0
	s_mov_b32 s6, 0
.LBB0_13:                               ; %.lr.ph
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_14 Depth 2
                                        ;     Child Loop BB0_17 Depth 2
	v_ashrrev_i32_e32 v1, 31, v0
	v_bfrev_b32_e32 v5, 1
	s_mov_b32 s7, exec_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[0:1]
	v_add_co_u32 v1, vcc_lo, s2, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
	global_load_b32 v1, v[1:2], off
	s_waitcnt vmcnt(0)
	v_cvt_f32_i32_e32 v1, v1
.LBB0_14:                               ; %ComputeLoop52
                                        ;   Parent Loop BB0_13 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_ctz_i32_b32 s8, s7
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_readlane_b32 s9, v1, s8
	s_lshl_b32 s8, 1, s8
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_not1_b32 s7, s7, s8
	s_cmp_lg_u32 s7, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f32_e32 v5, s9, v5
	s_cbranch_scc1 .LBB0_14
; %bb.15:                               ; %ComputeEnd53
                                        ;   in Loop: Header=BB0_13 Depth=1
	v_mbcnt_lo_u32_b32 v1, exec_lo, 0
	s_mov_b32 s7, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v1
	s_xor_b32 s7, exec_lo, s7
	s_cbranch_execz .LBB0_19
; %bb.16:                               ;   in Loop: Header=BB0_13 Depth=1
	global_load_b32 v2, v4, s[0:1]
	s_mov_b32 s8, 0
.LBB0_17:                               ; %atomicrmw.start61
                                        ;   Parent Loop BB0_13 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v1, v2, v5
	global_atomic_cmpswap_b32 v1, v4, v[1:2], s[0:1] glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u32_e32 vcc_lo, v1, v2
	v_mov_b32_e32 v2, v1
	s_or_b32 s8, vcc_lo, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s8
	s_cbranch_execnz .LBB0_17
; %bb.18:                               ; %Flow86
                                        ;   in Loop: Header=BB0_13 Depth=1
	s_or_b32 exec_lo, exec_lo, s8
.LBB0_19:                               ; %Flow87
                                        ;   in Loop: Header=BB0_13 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_or_b32 exec_lo, exec_lo, s7
	v_add_nc_u32_e32 v0, 1, v0
	v_cmp_ge_i32_e32 vcc_lo, v0, v3
	s_or_b32 s6, vcc_lo, s6
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s6
	s_cbranch_execnz .LBB0_13
; %bb.20:                               ; %Flow88
	s_or_b32 exec_lo, exec_lo, s6
                                        ; implicit-def: $vgpr0
.LBB0_21:                               ; %Flow94
	s_and_not1_saveexec_b32 s5, s5
	s_cbranch_execz .LBB0_31
; %bb.22:
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_i32_e32 vcc_lo, s4, v0
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_31
; %bb.23:                               ; %.lr.ph48.preheader
	v_mov_b32_e32 v3, 0
	s_mov_b32 s5, 0
.LBB0_24:                               ; %.lr.ph48
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_25 Depth 2
                                        ;     Child Loop BB0_28 Depth 2
	v_ashrrev_i32_e32 v1, 31, v0
	v_bfrev_b32_e32 v4, 1
	s_mov_b32 s6, exec_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[0:1]
	v_add_co_u32 v1, vcc_lo, s2, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
	global_load_b32 v1, v[1:2], off
	s_waitcnt vmcnt(0)
	v_cvt_f32_i32_e32 v1, v1
.LBB0_25:                               ; %ComputeLoop56
                                        ;   Parent Loop BB0_24 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_ctz_i32_b32 s7, s6
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_readlane_b32 s8, v1, s7
	s_lshl_b32 s7, 1, s7
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_not1_b32 s6, s6, s7
	s_cmp_lg_u32 s6, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f32_e32 v4, s8, v4
	s_cbranch_scc1 .LBB0_25
; %bb.26:                               ; %ComputeEnd57
                                        ;   in Loop: Header=BB0_24 Depth=1
	v_mbcnt_lo_u32_b32 v1, exec_lo, 0
	s_mov_b32 s6, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v1
	s_xor_b32 s6, exec_lo, s6
	s_cbranch_execz .LBB0_30
; %bb.27:                               ;   in Loop: Header=BB0_24 Depth=1
	global_load_b32 v2, v3, s[0:1]
	s_mov_b32 s7, 0
.LBB0_28:                               ; %atomicrmw.start67
                                        ;   Parent Loop BB0_24 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v1, v2, v4
	global_atomic_cmpswap_b32 v1, v3, v[1:2], s[0:1] glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u32_e32 vcc_lo, v1, v2
	v_mov_b32_e32 v2, v1
	s_or_b32 s7, vcc_lo, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s7
	s_cbranch_execnz .LBB0_28
; %bb.29:                               ; %Flow90
                                        ;   in Loop: Header=BB0_24 Depth=1
	s_or_b32 exec_lo, exec_lo, s7
.LBB0_30:                               ; %Flow91
                                        ;   in Loop: Header=BB0_24 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_or_b32 exec_lo, exec_lo, s6
	v_add_nc_u32_e32 v0, 1, v0
	v_cmp_le_i32_e32 vcc_lo, s4, v0
	s_or_b32 s5, vcc_lo, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s5
	s_cbranch_execnz .LBB0_24
.LBB0_31:                               ; %.loopexit
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z6addAllPKiiPfi
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 6
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z6addAllPKiiPfi, .Lfunc_end0-_Z6addAllPKiiPfi
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1068
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.text
	.protected	_Z5sigmaPKiiPffi        ; -- Begin function _Z5sigmaPKiiPffi
	.globl	_Z5sigmaPKiiPffi
	.p2align	8
	.type	_Z5sigmaPKiiPffi,@function
_Z5sigmaPKiiPffi:                       ; @_Z5sigmaPKiiPffi
; %bb.0:
	s_load_b64 s[4:5], s[0:1], 0x2c
	v_bfe_u32 v1, v0, 20, 10
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s5, 0xffff
	s_lshr_b32 s3, s4, 16
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[2:3], null, s15, s2, v[1:2]
	v_bfe_u32 v1, v0, 10, 10
	s_load_b32 s2, s[0:1], 0x8
	v_and_b32_e32 v0, 0x3ff, v0
	v_mad_u64_u32 v[3:4], null, v2, s3, v[1:2]
	s_and_b32 s3, s4, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[1:2], null, v3, s3, v[0:1]
	s_mov_b32 s3, exec_lo
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e64 s2, v1
	s_cbranch_execz .LBB1_31
; %bb.1:
	s_clause 0x1
	s_load_b128 s[4:7], s[0:1], 0x10
	s_load_b64 s[0:1], s[0:1], 0x0
	s_mov_b32 s3, -1
	s_waitcnt lgkmcnt(0)
	s_cmp_gt_i32 s2, s7
	s_cbranch_scc1 .LBB1_9
; %bb.2:
	v_ashrrev_i32_e32 v2, 31, v1
	s_mov_b32 s3, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[1:2]
	v_add_co_u32 v2, vcc_lo, s0, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
	global_load_b32 v0, v[2:3], off
	s_waitcnt vmcnt(0)
	v_cvt_f32_i32_e32 v0, v0
	v_subrev_f32_e32 v0, s6, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_mul_f32_e32 v2, v0, v0
	v_bfrev_b32_e32 v0, 1
.LBB1_3:                                ; %ComputeLoop
                                        ; =>This Inner Loop Header: Depth=1
	s_ctz_i32_b32 s8, s3
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	v_readlane_b32 s9, v2, s8
	s_lshl_b32 s8, 1, s8
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_not1_b32 s3, s3, s8
	s_cmp_lg_u32 s3, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f32_e32 v0, s9, v0
	s_cbranch_scc1 .LBB1_3
; %bb.4:                                ; %ComputeEnd
	v_mbcnt_lo_u32_b32 v2, exec_lo, 0
	s_mov_b32 s3, 0
	s_mov_b32 s8, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v2
	s_xor_b32 s8, exec_lo, s8
	s_cbranch_execz .LBB1_8
; %bb.5:
	s_load_b32 s9, s[4:5], 0x0
	s_waitcnt lgkmcnt(0)
	v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v3, s9
	s_mov_b32 s9, 0
.LBB1_6:                                ; %atomicrmw.start
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f32_e32 v2, v3, v0
	global_atomic_cmpswap_b32 v2, v4, v[2:3], s[4:5] glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u32_e32 vcc_lo, v2, v3
	v_mov_b32_e32 v3, v2
	s_or_b32 s9, vcc_lo, s9
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s9
	s_cbranch_execnz .LBB1_6
; %bb.7:                                ; %Flow
	s_or_b32 exec_lo, exec_lo, s9
.LBB1_8:                                ; %Flow101
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s8
.LBB1_9:                                ; %Flow112
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s3
	s_cbranch_vccz .LBB1_31
; %bb.10:
	s_ashr_i32 s3, s7, 31
	s_ashr_i32 s11, s2, 31
	s_add_i32 s8, s7, s3
	s_add_i32 s12, s2, s11
	s_xor_b32 s8, s8, s3
	s_xor_b32 s12, s12, s11
	v_cvt_f32_u32_e32 v0, s8
	s_sub_i32 s10, 0, s8
	s_xor_b32 s3, s11, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v0, v0
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v0, 0x4f7ffffe, v0
	v_cvt_u32_f32_e32 v0, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s9, v0
	s_mul_i32 s10, s10, s9
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_hi_u32 s10, s9, s10
	s_add_i32 s9, s9, s10
	s_add_i32 s10, s7, -1
	s_mul_hi_u32 s9, s12, s9
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_mul_i32 s7, s9, s8
	s_add_i32 s11, s9, 1
	s_sub_i32 s7, s12, s7
	s_sub_i32 s12, s7, s8
	s_cmp_ge_u32 s7, s8
	s_cselect_b32 s9, s11, s9
	s_cselect_b32 s7, s12, s7
	s_add_i32 s11, s9, 1
	s_cmp_ge_u32 s7, s8
	s_cselect_b32 s7, s11, s9
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b32 s7, s7, s3
	s_sub_i32 s7, s7, s3
	s_mov_b32 s3, exec_lo
	v_mul_lo_u32 v0, s7, v1
	v_cmpx_ne_u32_e64 s10, v1
	s_xor_b32 s3, exec_lo, s3
	s_cbranch_execz .LBB1_21
; %bb.11:
	s_cmp_lt_i32 s7, 1
	s_cbranch_scc1 .LBB1_21
; %bb.12:                               ; %.lr.ph.preheader
	s_delay_alu instid0(VALU_DEP_2)
	v_dual_mov_b32 v4, 0 :: v_dual_add_nc_u32 v3, s7, v0
	s_mov_b32 s7, 0
.LBB1_13:                               ; %.lr.ph
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB1_14 Depth 2
                                        ;     Child Loop BB1_17 Depth 2
	v_ashrrev_i32_e32 v1, 31, v0
	v_bfrev_b32_e32 v5, 1
	s_mov_b32 s8, exec_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[0:1]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v1, v[1:2], off
	s_waitcnt vmcnt(0)
	v_cvt_f32_i32_e32 v1, v1
	v_subrev_f32_e32 v1, s6, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_mul_f32_e32 v1, v1, v1
.LBB1_14:                               ; %ComputeLoop64
                                        ;   Parent Loop BB1_13 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_ctz_i32_b32 s9, s8
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_readlane_b32 s10, v1, s9
	s_lshl_b32 s9, 1, s9
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_not1_b32 s8, s8, s9
	s_cmp_lg_u32 s8, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f32_e32 v5, s10, v5
	s_cbranch_scc1 .LBB1_14
; %bb.15:                               ; %ComputeEnd65
                                        ;   in Loop: Header=BB1_13 Depth=1
	v_mbcnt_lo_u32_b32 v1, exec_lo, 0
	s_mov_b32 s8, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v1
	s_xor_b32 s8, exec_lo, s8
	s_cbranch_execz .LBB1_19
; %bb.16:                               ;   in Loop: Header=BB1_13 Depth=1
	global_load_b32 v2, v4, s[4:5]
	s_mov_b32 s9, 0
.LBB1_17:                               ; %atomicrmw.start73
                                        ;   Parent Loop BB1_13 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v1, v2, v5
	global_atomic_cmpswap_b32 v1, v4, v[1:2], s[4:5] glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u32_e32 vcc_lo, v1, v2
	v_mov_b32_e32 v2, v1
	s_or_b32 s9, vcc_lo, s9
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s9
	s_cbranch_execnz .LBB1_17
; %bb.18:                               ; %Flow102
                                        ;   in Loop: Header=BB1_13 Depth=1
	s_or_b32 exec_lo, exec_lo, s9
.LBB1_19:                               ; %Flow103
                                        ;   in Loop: Header=BB1_13 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_or_b32 exec_lo, exec_lo, s8
	v_add_nc_u32_e32 v0, 1, v0
	v_cmp_ge_i32_e32 vcc_lo, v0, v3
	s_or_b32 s7, vcc_lo, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s7
	s_cbranch_execnz .LBB1_13
; %bb.20:                               ; %Flow104
	s_or_b32 exec_lo, exec_lo, s7
                                        ; implicit-def: $vgpr0
.LBB1_21:                               ; %Flow110
	s_and_not1_saveexec_b32 s3, s3
	s_cbranch_execz .LBB1_31
; %bb.22:
	s_delay_alu instid0(VALU_DEP_2)
	v_cmp_gt_i32_e32 vcc_lo, s2, v0
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB1_31
; %bb.23:                               ; %.lr.ph60.preheader
	v_mov_b32_e32 v3, 0
	s_mov_b32 s3, 0
.LBB1_24:                               ; %.lr.ph60
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB1_25 Depth 2
                                        ;     Child Loop BB1_28 Depth 2
	v_ashrrev_i32_e32 v1, 31, v0
	v_bfrev_b32_e32 v4, 1
	s_mov_b32 s7, exec_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[0:1]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v1, v[1:2], off
	s_waitcnt vmcnt(0)
	v_cvt_f32_i32_e32 v1, v1
	v_subrev_f32_e32 v1, s6, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_mul_f32_e32 v1, v1, v1
.LBB1_25:                               ; %ComputeLoop68
                                        ;   Parent Loop BB1_24 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_ctz_i32_b32 s8, s7
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_readlane_b32 s9, v1, s8
	s_lshl_b32 s8, 1, s8
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_not1_b32 s7, s7, s8
	s_cmp_lg_u32 s7, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f32_e32 v4, s9, v4
	s_cbranch_scc1 .LBB1_25
; %bb.26:                               ; %ComputeEnd69
                                        ;   in Loop: Header=BB1_24 Depth=1
	v_mbcnt_lo_u32_b32 v1, exec_lo, 0
	s_mov_b32 s7, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v1
	s_xor_b32 s7, exec_lo, s7
	s_cbranch_execz .LBB1_30
; %bb.27:                               ;   in Loop: Header=BB1_24 Depth=1
	global_load_b32 v2, v3, s[4:5]
	s_mov_b32 s8, 0
.LBB1_28:                               ; %atomicrmw.start79
                                        ;   Parent Loop BB1_24 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v1, v2, v4
	global_atomic_cmpswap_b32 v1, v3, v[1:2], s[4:5] glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u32_e32 vcc_lo, v1, v2
	v_mov_b32_e32 v2, v1
	s_or_b32 s8, vcc_lo, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s8
	s_cbranch_execnz .LBB1_28
; %bb.29:                               ; %Flow106
                                        ;   in Loop: Header=BB1_24 Depth=1
	s_or_b32 exec_lo, exec_lo, s8
.LBB1_30:                               ; %Flow107
                                        ;   in Loop: Header=BB1_24 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_or_b32 exec_lo, exec_lo, s7
	v_add_nc_u32_e32 v0, 1, v0
	v_cmp_le_i32_e32 vcc_lo, s2, v0
	s_or_b32 s3, vcc_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s3
	s_cbranch_execnz .LBB1_24
.LBB1_31:                               ; %.loopexit
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z5sigmaPKiiPffi
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 6
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z5sigmaPKiiPffi, .Lfunc_end1-_Z5sigmaPKiiPffi
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1096
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z6addAllPKiiPfi
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z6addAllPKiiPfi.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     6
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z5sigmaPKiiPffi
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z5sigmaPKiiPffi.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     6
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
