#include <cuda.h>
#include <cuda_runtime.h>
#include "stdio.h"
#include <sys/time.h>
#define DEBUG 1

extern "C" {

  // cleaner error handling; just wrap cuda library calls with gpuErrchk(foo());
  #define gpuErr(ans) { gpuAssert((ans), __FILE__, __LINE__); }
  inline void gpuAssert(cudaError_t code, const char *file, int line, bool abort=true)
  {
    if (code != cudaSuccess) 
    {
        fprintf(stderr,"GPUassert: %s %s %d\n", cudaGetErrorString(code), file, line);
        if (abort) exit(code);
    }
  }

  __device__ int get_tid()
  {
    int blockId = blockIdx.x + blockIdx.y * gridDim.x
      + blockIdx.z * gridDim.x * gridDim.y;
    return  blockId * (blockDim.x * blockDim.y * blockDim.z)
      + (threadIdx.z * (blockDim.x * blockDim.y))
      + (threadIdx.y * blockDim.x)
      + threadIdx.x;
  }

  __global__ void dimer_1min1pls_t4(int n_elem, double *d_H, int *d_i, int *d_j, int *d_dim, float *d_sign, int *d_n_orb1, int *d_n_orb2, double *d_Rc1, double *d_Rcca1, double *d_Ra2, double *d_Rcaa2, double *d_h, double *d_V1, double *d_V2)
  {
    const int tid = get_tid();
    if(tid < n_elem) {
      const int n_orb1 = d_n_orb1[tid];
      const int n_orb2 = d_n_orb2[tid];
      double tmp = 0.0;
      int p,q,r,s;

      // In practice the n calculated here is not equal to the "actual" n here
      // since multiple kernel calls will be needed.
      // n_elem is the length

      // Top Loop
      // Use the tid to calculate variables in five dimensions
      //int n = tid;
      s = tid % n_orb2;
      r = ((tid - s) / (n_orb2)) % n_orb1;
      q = ((tid - r - s) * (n_orb2 * n_orb1)) % n_orb1;
      p = ((tid - q - r - s) / (n_orb2 * n_orb1 * n_orb1)) % n_orb1;
      tmp = d_V1[(((p * n_orb1 + q ) * n_orb1 + r) * n_orb2 + s) * n_elem + tid]
        * d_Rcca1[((q * n_orb1 + p)* n_orb1 + r) * n_elem + tid]
        * d_Ra2[s * n_elem + tid];

      // Middle Loop
      // 5d calculation
      s = tid % n_orb2;
      r = ((tid - s) / (n_orb2)) % n_orb2;
      q = ((tid - r - s) * (n_orb2 * n_orb2)) % n_orb2;
      p = ((tid - q - r - s) / (n_orb2 * n_orb2 * n_orb2)) % n_orb1;

      tmp += d_V2[(((p * n_orb2 + q ) * n_orb2 + r) * n_orb2 + s) * n_elem + tid]
        * d_Rcaa2[((q * n_orb2 + s) * n_orb2 + r) * n_elem + tid]
        * d_Rc1[p * n_elem + tid];
      tmp *= 2.0;

      // Bottom loop
      // 3d calculation
      s = tid % n_orb2;
      r = ((tid - s) / (n_orb2)) % n_orb1;
      tmp += d_h[(r * n_orb2 * s) * n_elem + tid]
        * d_Rc1[r * n_elem + tid]
        * d_Ra2[s * n_elem + tid];
      tmp *= d_sign[tid];

      // Assignment
      int index = d_i[tid] * d_dim[tid] + d_j[tid];
      d_H[index * n_elem + tid] = tmp;

      }
  }

void dimer_1min1pls_loop(int n_elem, double** H, int* i, int* j, int* dim, float* sign, int* n_orb1, int* n_orb2, double** Rc1,  double** Rcca1, double** Ra2, double** Rcaa2, double** h, double** V1, double** V2)
{
    struct timeval start,stop; 
    gettimeofday(&start,0);

    double *d_H, *d_Rc1, *d_Rcca1, *d_Ra2, *d_Rcaa2, *d_h, *d_V1, *d_V2;
    int *d_i, *d_j, *d_n_orb1, *d_n_orb2, *d_dim;
    float *d_sign;

    const int n1 = n_orb1[0];
    const int n2 = n_orb2[0];

    const int V1_len = n_elem * n2 * n1 * n1 * n1;
    const int V2_len = n_elem * n2 * n2 * n2 * n1;
    const int Rc1_len = n_elem * n1;
    const int Ra2_len = n_elem * n2;
    const int Rcca1_len = n_elem * n1 * n1 *n1;
    const int Rcaa2_len = n_elem * n2 * n2 * n2;
    const int h_len = n_elem * n1 * n2;
    const int H_len = n_elem * n1 * n1 * n1 * n2; // could be an issue if n1 != n2


    const int chunks = n1 * n2; // for maximum thread utilization this should go evenly into H_len
    const int elemPerChunk = ceil(n_elem / chunks);
    const int threadsPerChunk = ceil(H_len / chunks);
    const dim3 dimblock(4, 4, 4);
    const dim3 dimgrid(ceil(threadsPerChunk / dimblock.x), ceil(threadsPerChunk / dimblock.y), ceil(threadsPerChunk / dimblock.z));

    if(DEBUG) {
      printf("Chunks: %d\tThreads per chunk: %d\n",chunks,threadsPerChunk);
      printf("dimblock:\t<%d\t%d\t%d>\ndimgrid:\t<%d\t%d\t%d>\n",dimblock.x,dimblock.y,dimblock.z,dimgrid.x,dimgrid.y,dimgrid.z);
    }

    const int V1_size = sizeof(double) * ceil(V1_len / chunks);
    const int V2_size = sizeof(double) * ceil(V2_len / chunks);
    const int Rc1_size = sizeof(double) * ceil(Rc1_len / chunks);
    const int Ra2_size = sizeof(double) * ceil(Ra2_len / chunks);
    const int Rcca1_size = sizeof(double) * ceil(Rcca1_len / chunks);
    const int Rcaa2_size = sizeof(double) * ceil(Rcaa2_len / chunks);
    const int h_size = sizeof(double) * ceil(h_len / chunks);
    const int i_size = sizeof(int) * elemPerChunk; // for all the n-elem int arrays
    const int sign_size = sizeof(float) * elemPerChunk;
    const int H_size = sizeof(double) * threadsPerChunk;

    if(DEBUG) {
      printf("Starting device memory allocation\n");
    }

    gpuErr(cudaMalloc((void **) &d_H,       H_size));
    gpuErr(cudaMalloc((void **) &d_Rc1,     Rc1_size));
    gpuErr(cudaMalloc((void **) &d_V1,      V1_size));
    gpuErr(cudaMalloc((void **) &d_V2,      V2_size));
    gpuErr(cudaMalloc((void **) &d_Ra2,     Ra2_size));
    gpuErr(cudaMalloc((void **) &d_Rcca1,   Rcca1_size));
    gpuErr(cudaMalloc((void **) &d_Rcaa2,   Rcaa2_size));
    gpuErr(cudaMalloc((void **) &d_h,       h_size));
    gpuErr(cudaMalloc((void **) &d_i,       i_size));
    gpuErr(cudaMalloc((void **) &d_j,       i_size));
    gpuErr(cudaMalloc((void **) &d_dim,     i_size));
    gpuErr(cudaMalloc((void **) &d_n_orb1,  i_size));
    gpuErr(cudaMalloc((void **) &d_n_orb2,  i_size));
    gpuErr(cudaMalloc((void **) &d_sign,    sign_size));

    if(DEBUG) {
      printf("Finished device memory allocation\n");
    }

    for(int k=0; k<chunks; k++) {

      if(DEBUG) {
        printf("Chunk %d: starting host to device memcpys\n",k);
      }

      gpuErr(cudaMemcpy(d_Rc1, Rc1 + k * Rc1_len, Rc1_size, cudaMemcpyHostToDevice));
      gpuErr(cudaMemcpy(d_V1, V1 + k * V1_len, V1_size, cudaMemcpyHostToDevice));
      gpuErr(cudaMemcpy(d_V2, V2 + k * V2_len , V2_size, cudaMemcpyHostToDevice));
      gpuErr(cudaMemcpy(d_Ra2, Ra2 + k * Ra2_len, Ra2_size, cudaMemcpyHostToDevice));
      gpuErr(cudaMemcpy(d_Rcca1, Rcca1 + k * Rcca1_len, Rcca1_size, cudaMemcpyHostToDevice));
      gpuErr(cudaMemcpy(d_Rcaa2, Rcaa2 + k * Rcaa2_len, Rcaa2_size, cudaMemcpyHostToDevice));
      gpuErr(cudaMemcpy(d_h, h + k * h_len, h_size, cudaMemcpyHostToDevice));
      gpuErr(cudaMemcpy(d_i, i + k * elemPerChunk, i_size, cudaMemcpyHostToDevice));
      gpuErr(cudaMemcpy(d_j, j + k * elemPerChunk, i_size, cudaMemcpyHostToDevice));
      gpuErr(cudaMemcpy(d_n_orb1, n_orb1 + k * elemPerChunk, i_size, cudaMemcpyHostToDevice));
      gpuErr(cudaMemcpy(d_n_orb2, n_orb2 + k * elemPerChunk, i_size, cudaMemcpyHostToDevice));
      gpuErr(cudaMemcpy(d_sign, sign + k * elemPerChunk, sign_size, cudaMemcpyHostToDevice));

      if(DEBUG) {
        printf("Chunk %d: finished host to device memcpys\n",k);
        printf("Chunk %d: launching dimer_1min1pls_t4 kernel\n",k);
      }

      dimer_1min1pls_t4<<<dimblock,dimgrid>>>(n_elem,d_H,d_i,d_j,d_dim,d_sign,d_n_orb1,d_n_orb2,d_Rc1,d_Rcca1,d_Ra2,d_Rcaa2,d_h,d_V1,d_V2);
      gpuErr(cudaPeekAtLastError());
      gpuErr(cudaDeviceSynchronize());

      memcpy(H+k*H_len, d_H, H_size);


      if(DEBUG) {
        printf("Chunk %d: finished executing dimer_1min1pls_t4 kernel \n",k);
      }


    }

    gpuErr(cudaFree(d_Rc1));
    gpuErr(cudaFree(d_V1));
    gpuErr(cudaFree(d_V2));
    gpuErr(cudaFree(d_Ra2));
    gpuErr(cudaFree(d_Rcca1));
    gpuErr(cudaFree(d_Rcaa2));
    gpuErr(cudaFree(d_h));
    gpuErr(cudaFree(d_i));
    gpuErr(cudaFree(d_j));
    gpuErr(cudaFree(d_n_orb1));
    gpuErr(cudaFree(d_n_orb2));
    gpuErr(cudaFree(d_sign))
    gettimeofday(&stop,0);
    if(DEBUG) {
      double t = (double)(stop.tv_sec-start.tv_sec)*1000+(double)(stop.tv_usec-start.tv_usec)/1000;
      printf("dimer_1min1pls_loop_t4 finished in %f ms\n", t);
    }


}
}

	.file	"tmpxft_00291ee0_00000000-6_t4.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2032:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2032:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.section	.rodata.gpuAssert.str1.1,"aMS",@progbits,1
.LC0:
	.string	"GPUassert: %s %s %d\n"
	.section	.text.gpuAssert,"axG",@progbits,gpuAssert,comdat
	.weak	gpuAssert
	.type	gpuAssert, @function
gpuAssert:
.LFB2027:
	.cfi_startproc
	endbr64
	testl	%edi, %edi
	je	.L8
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	movl	%ecx, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 24
	.cfi_offset 3, -24
	movl	%edi, %ebx
	subq	$24, %rsp
	.cfi_def_cfa_offset 48
	movl	%edx, 12(%rsp)
	movq	%rsi, (%rsp)
	call	cudaGetErrorString@PLT
	movl	12(%rsp), %r9d
	movq	(%rsp), %r8
	leaq	.LC0(%rip), %rdx
	movq	stderr(%rip), %rdi
	movq	%rax, %rcx
	movl	$2, %esi
	xorl	%eax, %eax
	call	__fprintf_chk@PLT
	testb	%bpl, %bpl
	je	.L2
	movl	%ebx, %edi
	call	exit@PLT
.L2:
	addq	$24, %rsp
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	ret
.L8:
	.cfi_restore 3
	.cfi_restore 6
	ret
	.cfi_endproc
.LFE2027:
	.size	gpuAssert, .-gpuAssert
	.text
	.globl	get_tid
	.type	get_tid, @function
get_tid:
.LFB2028:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2028:
	.size	get_tid, .-get_tid
	.globl	_Z68__device_stub__Z17dimer_1min1pls_t4iPdPiS0_S0_PfS0_S0_S_S_S_S_S_S_S_iPdPiS0_S0_PfS0_S0_S_S_S_S_S_S_S_
	.type	_Z68__device_stub__Z17dimer_1min1pls_t4iPdPiS0_S0_PfS0_S0_S_S_S_S_S_S_S_iPdPiS0_S0_PfS0_S0_S_S_S_S_S_S_S_, @function
_Z68__device_stub__Z17dimer_1min1pls_t4iPdPiS0_S0_PfS0_S0_S_S_S_S_S_S_S_iPdPiS0_S0_PfS0_S0_S_S_S_S_S_S_S_:
.LFB2054:
	.cfi_startproc
	endbr64
	subq	$328, %rsp
	.cfi_def_cfa_offset 336
	movq	336(%rsp), %rax
	movl	%edi, 124(%rsp)
	leaq	144(%rsp), %rdi
	movq	%rsi, 112(%rsp)
	leaq	156(%rsp), %rsi
	movq	%rax, 72(%rsp)
	movq	344(%rsp), %rax
	movq	%rdx, 104(%rsp)
	leaq	128(%rsp), %rdx
	movq	%rax, 64(%rsp)
	movq	352(%rsp), %rax
	movq	%rcx, 96(%rsp)
	leaq	136(%rsp), %rcx
	movq	%rax, 56(%rsp)
	movq	360(%rsp), %rax
	movq	%r8, 88(%rsp)
	movq	%rax, 48(%rsp)
	movq	368(%rsp), %rax
	movq	%r9, 80(%rsp)
	movq	%rax, 40(%rsp)
	movq	376(%rsp), %rax
	movq	%rax, 32(%rsp)
	movq	384(%rsp), %rax
	movq	%rax, 24(%rsp)
	movq	392(%rsp), %rax
	movq	%rax, 16(%rsp)
	movq	400(%rsp), %rax
	movq	%rax, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 312(%rsp)
	xorl	%eax, %eax
	leaq	124(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	112(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	104(%rsp), %rax
	movq	%rax, 208(%rsp)
	leaq	96(%rsp), %rax
	movq	%rax, 216(%rsp)
	leaq	88(%rsp), %rax
	movq	%rax, 224(%rsp)
	leaq	80(%rsp), %rax
	movq	%rax, 232(%rsp)
	leaq	72(%rsp), %rax
	movq	%rax, 240(%rsp)
	leaq	64(%rsp), %rax
	movq	%rax, 248(%rsp)
	leaq	56(%rsp), %rax
	movq	%rax, 256(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 264(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 272(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 280(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 288(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 296(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 304(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 144(%rsp)
	movl	$1, 152(%rsp)
	movq	%rax, 156(%rsp)
	movl	$1, 164(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L14
	pushq	136(%rsp)
	.cfi_def_cfa_offset 344
	leaq	dimer_1min1pls_t4(%rip), %rdi
	pushq	136(%rsp)
	.cfi_def_cfa_offset 352
	movq	172(%rsp), %rcx
	movl	180(%rsp), %r8d
	movq	160(%rsp), %rsi
	movl	168(%rsp), %edx
	leaq	208(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 344
	popq	%rdx
	.cfi_def_cfa_offset 336
.L14:
	movq	312(%rsp), %rax
	subq	%fs:40, %rax
	je	.L16
	call	__stack_chk_fail@PLT
.L16:
	addq	$328, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2054:
	.size	_Z68__device_stub__Z17dimer_1min1pls_t4iPdPiS0_S0_PfS0_S0_S_S_S_S_S_S_S_iPdPiS0_S0_PfS0_S0_S_S_S_S_S_S_S_, .-_Z68__device_stub__Z17dimer_1min1pls_t4iPdPiS0_S0_PfS0_S0_S_S_S_S_S_S_S_iPdPiS0_S0_PfS0_S0_S_S_S_S_S_S_S_
	.globl	dimer_1min1pls_t4
	.type	dimer_1min1pls_t4, @function
dimer_1min1pls_t4:
.LFB2055:
	.cfi_startproc
	endbr64
	jmp	_Z68__device_stub__Z17dimer_1min1pls_t4iPdPiS0_S0_PfS0_S0_S_S_S_S_S_S_S_iPdPiS0_S0_PfS0_S0_S_S_S_S_S_S_S_
	.cfi_endproc
.LFE2055:
	.size	dimer_1min1pls_t4, .-dimer_1min1pls_t4
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC1:
	.string	"Chunks: %d\tThreads per chunk: %d\n"
.LC2:
	.string	"dimblock:\t<%d\t%d\t%d>\ndimgrid:\t<%d\t%d\t%d>\n"
.LC3:
	.string	"Starting device memory allocation\n"
.LC4:
	.string	"/home/ubuntu/Datasets/stackv2/train-structured/sskhan67/GPGPU-Programming-/master/QODE/Applications/GPU-pilot/t4.cu"
.LC6:
	.string	"Finished device memory allocation\n"
.LC7:
	.string	"Chunk %d: starting host to device memcpys\n"
.LC8:
	.string	"Chunk %d: finished host to device memcpys\n"
.LC9:
	.string	"Chunk %d: launching dimer_1min1pls_t4 kernel\n"
.LC10:
	.string	"Chunk %d: finished executing dimer_1min1pls_t4 kernel \n"
.LC12:
	.string	"dimer_1min1pls_loop_t4 finished in %f ms\n"
	.text
	.globl	dimer_1min1pls_loop
	.type	dimer_1min1pls_loop, @function
dimer_1min1pls_loop:
.LFB2029:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$440, %rsp
	.cfi_def_cfa_offset 496
	movq	496(%rsp), %rax
	movq	%rdx, 216(%rsp)
	movq	%rcx, 224(%rsp)
	movq	%rax, 136(%rsp)
	movq	504(%rsp), %rax
	movq	%r9, 232(%rsp)
	movq	%rax, 144(%rsp)
	movq	512(%rsp), %rax
	movl	%edi, 20(%rsp)
	leaq	392(%rsp), %rdi
	movq	%rax, 128(%rsp)
	movq	520(%rsp), %rax
	movq	%rsi, 120(%rsp)
	xorl	%esi, %esi
	movq	%rax, 208(%rsp)
	movq	528(%rsp), %rax
	movq	%rax, 200(%rsp)
	movq	536(%rsp), %rax
	movq	%rax, 240(%rsp)
	movq	544(%rsp), %rax
	movq	%rax, 248(%rsp)
	movq	552(%rsp), %rax
	movq	%rax, 184(%rsp)
	movq	560(%rsp), %rax
	movq	%rax, 192(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 424(%rsp)
	xorl	%eax, %eax
	call	gettimeofday@PLT
	movl	20(%rsp), %r12d
	movl	20(%rsp), %r13d
	leaq	.LC1(%rip), %rsi
	movq	144(%rsp), %rbx
	movq	136(%rsp), %rax
	movl	$2, %edi
	movl	(%rbx), %edx
	movl	(%rax), %eax
	imull	%edx, %r12d
	movl	%eax, %ebp
	imull	%eax, %r13d
	movl	%r12d, %ecx
	movl	%r12d, %ebx
	imull	%eax, %ecx
	imull	%edx, %ebx
	imull	%r13d, %ebp
	imull	%eax, %ecx
	imull	%edx, %ebx
	imull	%eax, %ebp
	imull	%eax, %ecx
	movl	%ecx, 88(%rsp)
	movl	%ebx, %ecx
	imull	%eax, %ecx
	imull	%edx, %eax
	movl	%ecx, 96(%rsp)
	movl	%edx, %ecx
	imull	%r13d, %ecx
	movl	%eax, %r15d
	movl	20(%rsp), %eax
	movl	%ecx, 104(%rsp)
	movl	%edx, %ecx
	cltd
	idivl	%r15d
	imull	%ebp, %ecx
	movl	%ecx, 112(%rsp)
	movl	%eax, 8(%rsp)
	movl	%ecx, %eax
	cltd
	idivl	%r15d
	movl	%r15d, %edx
	movl	%eax, %r9d
	movl	%eax, %ecx
	movl	%eax, %r14d
	xorl	%eax, %eax
	shrl	$2, %r9d
	sall	$3, %r14d
	movl	%r9d, 380(%rsp)
	movl	%r9d, 384(%rsp)
	movl	%r9d, 388(%rsp)
	movl	%r9d, 24(%rsp)
	call	__printf_chk@PLT
	movl	24(%rsp), %r9d
	movl	$4, %r8d
	movl	$4, %ecx
	movl	$4, %edx
	leaq	.LC2(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	pushq	%r9
	.cfi_def_cfa_offset 504
	pushq	%r9
	.cfi_def_cfa_offset 512
	call	__printf_chk@PLT
	movslq	24(%rsp), %rax
	movl	$2, %edi
	leaq	.LC3(%rip), %rsi
	movq	%rax, 168(%rsp)
	popq	%rdx
	.cfi_def_cfa_offset 504
	xorl	%eax, %eax
	popq	%rcx
	.cfi_def_cfa_offset 496
	call	__printf_chk@PLT
	movslq	%r14d, %rax
	leaq	256(%rsp), %rdi
	leaq	.LC4(%rip), %r14
	movq	%rax, %rsi
	movq	%rax, 24(%rsp)
	call	cudaMalloc@PLT
	movl	$1, %ecx
	movq	%r14, %rsi
	movl	$130, %edx
	movl	%eax, %edi
	call	gpuAssert
	movl	%r13d, %eax
	leaq	264(%rsp), %rdi
	movslq	%r13d, %r13
	cltd
	idivl	%r15d
	cvtsi2sdl	%eax, %xmm0
	mulsd	.LC5(%rip), %xmm0
	cvttsd2sil	%xmm0, %eax
	cltq
	movq	%rax, %rsi
	movq	%rax, 32(%rsp)
	call	cudaMalloc@PLT
	movl	$1, %ecx
	movq	%r14, %rsi
	movl	$131, %edx
	movl	%eax, %edi
	call	gpuAssert
	movl	88(%rsp), %eax
	leaq	304(%rsp), %rdi
	cltd
	idivl	%r15d
	cvtsi2sdl	%eax, %xmm0
	mulsd	.LC5(%rip), %xmm0
	cvttsd2sil	%xmm0, %eax
	cltq
	movq	%rax, %rsi
	movq	%rax, 40(%rsp)
	call	cudaMalloc@PLT
	movl	$1, %ecx
	movq	%r14, %rsi
	movl	$132, %edx
	movl	%eax, %edi
	call	gpuAssert
	movl	96(%rsp), %eax
	leaq	312(%rsp), %rdi
	cltd
	idivl	%r15d
	cvtsi2sdl	%eax, %xmm0
	mulsd	.LC5(%rip), %xmm0
	cvttsd2sil	%xmm0, %eax
	cltq
	movq	%rax, %rsi
	movq	%rax, 48(%rsp)
	call	cudaMalloc@PLT
	movl	$1, %ecx
	movq	%r14, %rsi
	movl	$133, %edx
	movl	%eax, %edi
	call	gpuAssert
	movl	%r12d, %eax
	leaq	280(%rsp), %rdi
	movslq	%r12d, %r12
	cltd
	idivl	%r15d
	cvtsi2sdl	%eax, %xmm0
	mulsd	.LC5(%rip), %xmm0
	cvttsd2sil	%xmm0, %eax
	cltq
	movq	%rax, %rsi
	movq	%rax, 56(%rsp)
	call	cudaMalloc@PLT
	movl	$1, %ecx
	movq	%r14, %rsi
	movl	$134, %edx
	movl	%eax, %edi
	call	gpuAssert
	movl	%ebp, %eax
	leaq	272(%rsp), %rdi
	movslq	%ebp, %rbp
	cltd
	idivl	%r15d
	cvtsi2sdl	%eax, %xmm0
	mulsd	.LC5(%rip), %xmm0
	cvttsd2sil	%xmm0, %eax
	cltq
	movq	%rax, %rsi
	movq	%rax, 64(%rsp)
	call	cudaMalloc@PLT
	movl	$1, %ecx
	movq	%r14, %rsi
	movl	$135, %edx
	movl	%eax, %edi
	call	gpuAssert
	movl	%ebx, %eax
	leaq	288(%rsp), %rdi
	movslq	%ebx, %rbx
	cltd
	idivl	%r15d
	cvtsi2sdl	%eax, %xmm0
	mulsd	.LC5(%rip), %xmm0
	cvttsd2sil	%xmm0, %eax
	cltq
	movq	%rax, %rsi
	movq	%rax, 72(%rsp)
	call	cudaMalloc@PLT
	movl	$1, %ecx
	movq	%r14, %rsi
	movl	$136, %edx
	movl	%eax, %edi
	call	gpuAssert
	movl	104(%rsp), %eax
	leaq	296(%rsp), %rdi
	cltd
	idivl	%r15d
	cvtsi2sdl	%eax, %xmm0
	mulsd	.LC5(%rip), %xmm0
	cvttsd2sil	%xmm0, %eax
	cltq
	movq	%rax, %rsi
	movq	%rax, 80(%rsp)
	call	cudaMalloc@PLT
	movl	$1, %ecx
	movl	$137, %edx
	movq	%r14, %rsi
	movl	%eax, %edi
	call	gpuAssert
	movl	8(%rsp), %eax
	leaq	320(%rsp), %rdi
	sall	$2, %eax
	cltq
	movq	%rax, %rsi
	movq	%rax, 8(%rsp)
	call	cudaMalloc@PLT
	movl	$1, %ecx
	movl	$138, %edx
	movq	%r14, %rsi
	movl	%eax, %edi
	call	gpuAssert
	movq	8(%rsp), %rsi
	leaq	328(%rsp), %rdi
	call	cudaMalloc@PLT
	movl	$1, %ecx
	movl	$139, %edx
	movq	%r14, %rsi
	movl	%eax, %edi
	call	gpuAssert
	movq	8(%rsp), %rsi
	leaq	352(%rsp), %rdi
	call	cudaMalloc@PLT
	movl	$1, %ecx
	movl	$140, %edx
	movq	%r14, %rsi
	movl	%eax, %edi
	call	gpuAssert
	movq	8(%rsp), %rsi
	leaq	336(%rsp), %rdi
	call	cudaMalloc@PLT
	movl	$1, %ecx
	movl	$141, %edx
	movq	%r14, %rsi
	movl	%eax, %edi
	call	gpuAssert
	movq	8(%rsp), %rsi
	leaq	344(%rsp), %rdi
	call	cudaMalloc@PLT
	movl	$1, %ecx
	movl	$142, %edx
	movq	%r14, %rsi
	movl	%eax, %edi
	call	gpuAssert
	movq	8(%rsp), %rsi
	leaq	360(%rsp), %rdi
	call	cudaMalloc@PLT
	movq	%r14, %rsi
	movl	$1, %ecx
	movl	$143, %edx
	movl	%eax, %edi
	call	gpuAssert
	leaq	.LC6(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movslq	112(%rsp), %rax
	movq	208(%rsp), %r14
	salq	$3, %rax
	movq	%rax, 160(%rsp)
	movq	120(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	0(,%r13,8), %rax
	movq	248(%rsp), %r13
	movq	%rax, 168(%rsp)
	movq	128(%rsp), %rax
	movq	%rax, 120(%rsp)
	movslq	88(%rsp), %rax
	salq	$3, %rax
	movq	%rax, 176(%rsp)
	movq	184(%rsp), %rax
	movq	%rax, 88(%rsp)
	movslq	96(%rsp), %rax
	salq	$3, %rax
	movq	%rax, 184(%rsp)
	movq	192(%rsp), %rax
	movq	%rax, 96(%rsp)
	leaq	0(,%r12,8), %rax
	movq	240(%rsp), %r12
	movq	%rax, 192(%rsp)
	movq	200(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	0(,%rbp,8), %rax
	xorl	%ebp, %ebp
	movq	%rax, 200(%rsp)
	leaq	0(,%rbx,8), %rax
	xorl	%ebx, %ebx
	movq	%rax, 208(%rsp)
	movslq	104(%rsp), %rax
	salq	$3, %rax
	movq	%rax, 104(%rsp)
	movq	152(%rsp), %rax
	salq	$2, %rax
	movq	%rax, 152(%rsp)
.L20:
	cmpl	%r15d, %ebx
	jge	.L25
	movl	%ebx, %edx
	leaq	.LC7(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movq	32(%rsp), %rdx
	movq	120(%rsp), %rsi
	movl	$1, %ecx
	movq	264(%rsp), %rdi
	call	cudaMemcpy@PLT
	movl	$1, %ecx
	movl	$155, %edx
	leaq	.LC4(%rip), %rsi
	movl	%eax, %edi
	call	gpuAssert
	movq	40(%rsp), %rdx
	movq	88(%rsp), %rsi
	movl	$1, %ecx
	movq	304(%rsp), %rdi
	call	cudaMemcpy@PLT
	movl	$1, %ecx
	movl	$156, %edx
	leaq	.LC4(%rip), %rsi
	movl	%eax, %edi
	call	gpuAssert
	movq	48(%rsp), %rdx
	movq	96(%rsp), %rsi
	movl	$1, %ecx
	movq	312(%rsp), %rdi
	call	cudaMemcpy@PLT
	movl	$1, %ecx
	movl	$157, %edx
	leaq	.LC4(%rip), %rsi
	movl	%eax, %edi
	call	gpuAssert
	movq	56(%rsp), %rdx
	movl	$1, %ecx
	movq	128(%rsp), %rsi
	movq	280(%rsp), %rdi
	call	cudaMemcpy@PLT
	movl	$1, %ecx
	movl	$158, %edx
	leaq	.LC4(%rip), %rsi
	movl	%eax, %edi
	call	gpuAssert
	movq	64(%rsp), %rdx
	movl	$1, %ecx
	movq	%r14, %rsi
	movq	272(%rsp), %rdi
	call	cudaMemcpy@PLT
	movl	$1, %ecx
	movl	$159, %edx
	leaq	.LC4(%rip), %rsi
	movl	%eax, %edi
	call	gpuAssert
	movq	72(%rsp), %rdx
	movl	$1, %ecx
	movq	%r12, %rsi
	movq	288(%rsp), %rdi
	call	cudaMemcpy@PLT
	movl	$1, %ecx
	movl	$160, %edx
	leaq	.LC4(%rip), %rsi
	movl	%eax, %edi
	call	gpuAssert
	movq	80(%rsp), %rdx
	movl	$1, %ecx
	movq	%r13, %rsi
	movq	296(%rsp), %rdi
	call	cudaMemcpy@PLT
	movl	$1, %ecx
	movl	$161, %edx
	leaq	.LC4(%rip), %rsi
	movl	%eax, %edi
	call	gpuAssert
	movq	8(%rsp), %rdx
	movl	$1, %ecx
	movq	216(%rsp), %rax
	movq	320(%rsp), %rdi
	leaq	(%rax,%rbp), %rsi
	call	cudaMemcpy@PLT
	movl	$1, %ecx
	movl	$162, %edx
	leaq	.LC4(%rip), %rsi
	movl	%eax, %edi
	call	gpuAssert
	movq	8(%rsp), %rdx
	movl	$1, %ecx
	movq	224(%rsp), %rax
	movq	328(%rsp), %rdi
	leaq	(%rax,%rbp), %rsi
	call	cudaMemcpy@PLT
	movl	$1, %ecx
	movl	$163, %edx
	leaq	.LC4(%rip), %rsi
	movl	%eax, %edi
	call	gpuAssert
	movq	8(%rsp), %rdx
	movl	$1, %ecx
	movq	136(%rsp), %rax
	movq	336(%rsp), %rdi
	leaq	(%rax,%rbp), %rsi
	call	cudaMemcpy@PLT
	movl	$1, %ecx
	movl	$164, %edx
	leaq	.LC4(%rip), %rsi
	movl	%eax, %edi
	call	gpuAssert
	movq	8(%rsp), %rdx
	movl	$1, %ecx
	movq	144(%rsp), %rax
	movq	344(%rsp), %rdi
	leaq	(%rax,%rbp), %rsi
	call	cudaMemcpy@PLT
	movl	$1, %ecx
	movl	$165, %edx
	leaq	.LC4(%rip), %rsi
	movl	%eax, %edi
	call	gpuAssert
	movq	8(%rsp), %rdx
	movl	$1, %ecx
	movq	232(%rsp), %rax
	movq	360(%rsp), %rdi
	leaq	(%rax,%rbp), %rsi
	call	cudaMemcpy@PLT
	movl	$1, %ecx
	movl	$166, %edx
	leaq	.LC4(%rip), %rsi
	movl	%eax, %edi
	call	gpuAssert
	movl	%ebx, %edx
	leaq	.LC8(%rip), %rsi
	xorl	%eax, %eax
	movl	$2, %edi
	call	__printf_chk@PLT
	movl	%ebx, %edx
	leaq	.LC9(%rip), %rsi
	xorl	%eax, %eax
	movl	$2, %edi
	call	__printf_chk@PLT
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$4, %esi
	movl	388(%rsp), %ecx
	movq	380(%rsp), %rdx
	movabsq	$17179869188, %rdi
	movl	$4, 376(%rsp)
	movq	%rdi, 368(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L21
	pushq	%rax
	.cfi_def_cfa_offset 504
	pushq	320(%rsp)
	.cfi_def_cfa_offset 512
	pushq	320(%rsp)
	.cfi_def_cfa_offset 520
	pushq	320(%rsp)
	.cfi_def_cfa_offset 528
	pushq	320(%rsp)
	.cfi_def_cfa_offset 536
	pushq	320(%rsp)
	.cfi_def_cfa_offset 544
	pushq	320(%rsp)
	.cfi_def_cfa_offset 552
	pushq	320(%rsp)
	.cfi_def_cfa_offset 560
	pushq	408(%rsp)
	.cfi_def_cfa_offset 568
	pushq	408(%rsp)
	.cfi_def_cfa_offset 576
	movq	440(%rsp), %r9
	movq	432(%rsp), %r8
	movq	408(%rsp), %rcx
	movq	400(%rsp), %rdx
	movq	336(%rsp), %rsi
	movl	100(%rsp), %edi
	call	_Z68__device_stub__Z17dimer_1min1pls_t4iPdPiS0_S0_PfS0_S0_S_S_S_S_S_S_S_iPdPiS0_S0_PfS0_S0_S_S_S_S_S_S_S_
	addq	$80, %rsp
	.cfi_def_cfa_offset 496
.L21:
	call	cudaPeekAtLastError@PLT
	movl	$1, %ecx
	movl	$174, %edx
	leaq	.LC4(%rip), %rsi
	movl	%eax, %edi
	call	gpuAssert
	call	cudaDeviceSynchronize@PLT
	movl	$1, %ecx
	movl	$175, %edx
	leaq	.LC4(%rip), %rsi
	movl	%eax, %edi
	call	gpuAssert
	movq	112(%rsp), %rdi
	movl	%ebx, %edx
	xorl	%eax, %eax
	movq	256(%rsp), %rsi
	movq	24(%rsp), %rcx
	incl	%ebx
	rep movsb
	leaq	.LC10(%rip), %rsi
	movl	$2, %edi
	call	__printf_chk@PLT
	movq	200(%rsp), %rax
	movq	160(%rsp), %rdx
	movq	176(%rsp), %rcx
	addq	%rdx, 112(%rsp)
	addq	%rax, %r14
	movq	208(%rsp), %rax
	movq	168(%rsp), %rdx
	addq	%rcx, 88(%rsp)
	movq	192(%rsp), %rcx
	addq	%rax, %r12
	movq	104(%rsp), %rax
	addq	%rdx, 120(%rsp)
	addq	%rcx, 128(%rsp)
	movq	184(%rsp), %rdx
	addq	%rax, %r13
	movq	152(%rsp), %rax
	addq	%rdx, 96(%rsp)
	addq	%rax, %rbp
	jmp	.L20
.L25:
	movq	264(%rsp), %rdi
	leaq	.LC4(%rip), %rbx
	call	cudaFree@PLT
	movl	$1, %ecx
	movl	$187, %edx
	movq	%rbx, %rsi
	movl	%eax, %edi
	call	gpuAssert
	movq	304(%rsp), %rdi
	call	cudaFree@PLT
	movl	$1, %ecx
	movl	$188, %edx
	movq	%rbx, %rsi
	movl	%eax, %edi
	call	gpuAssert
	movq	312(%rsp), %rdi
	call	cudaFree@PLT
	movl	$1, %ecx
	movl	$189, %edx
	movq	%rbx, %rsi
	movl	%eax, %edi
	call	gpuAssert
	movq	280(%rsp), %rdi
	call	cudaFree@PLT
	movl	$1, %ecx
	movl	$190, %edx
	movq	%rbx, %rsi
	movl	%eax, %edi
	call	gpuAssert
	movq	272(%rsp), %rdi
	call	cudaFree@PLT
	movl	$1, %ecx
	movl	$191, %edx
	movq	%rbx, %rsi
	movl	%eax, %edi
	call	gpuAssert
	movq	288(%rsp), %rdi
	call	cudaFree@PLT
	movl	$1, %ecx
	movl	$192, %edx
	movq	%rbx, %rsi
	movl	%eax, %edi
	call	gpuAssert
	movq	296(%rsp), %rdi
	call	cudaFree@PLT
	movl	$1, %ecx
	movl	$193, %edx
	movq	%rbx, %rsi
	movl	%eax, %edi
	call	gpuAssert
	movq	320(%rsp), %rdi
	call	cudaFree@PLT
	movl	$1, %ecx
	movl	$194, %edx
	movq	%rbx, %rsi
	movl	%eax, %edi
	call	gpuAssert
	movq	328(%rsp), %rdi
	call	cudaFree@PLT
	movl	$1, %ecx
	movl	$195, %edx
	movq	%rbx, %rsi
	movl	%eax, %edi
	call	gpuAssert
	movq	336(%rsp), %rdi
	call	cudaFree@PLT
	movl	$1, %ecx
	movl	$196, %edx
	movq	%rbx, %rsi
	movl	%eax, %edi
	call	gpuAssert
	movq	344(%rsp), %rdi
	call	cudaFree@PLT
	movl	$1, %ecx
	movl	$197, %edx
	movq	%rbx, %rsi
	movl	%eax, %edi
	call	gpuAssert
	movq	360(%rsp), %rdi
	call	cudaFree@PLT
	movl	$1, %ecx
	movl	$198, %edx
	movq	%rbx, %rsi
	movl	%eax, %edi
	call	gpuAssert
	xorl	%esi, %esi
	leaq	408(%rsp), %rdi
	call	gettimeofday@PLT
	movq	408(%rsp), %rax
	movl	$2, %edi
	subq	392(%rsp), %rax
	cvtsi2sdq	%rax, %xmm0
	movq	416(%rsp), %rax
	subq	400(%rsp), %rax
	leaq	.LC12(%rip), %rsi
	cvtsi2sdq	%rax, %xmm1
	movsd	.LC11(%rip), %xmm2
	movb	$1, %al
	mulsd	%xmm2, %xmm0
	divsd	%xmm2, %xmm1
	addsd	%xmm1, %xmm0
	call	__printf_chk@PLT
	movq	424(%rsp), %rax
	subq	%fs:40, %rax
	je	.L23
	call	__stack_chk_fail@PLT
.L23:
	addq	$440, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2029:
	.size	dimer_1min1pls_loop, .-dimer_1min1pls_loop
	.section	.rodata.str1.1
.LC13:
	.string	"dimer_1min1pls_t4"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2057:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC13(%rip), %rdx
	movq	%rax, %rdi
	leaq	dimer_1min1pls_t4(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2057:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst8,"aM",@progbits,8
	.align 8
.LC5:
	.long	0
	.long	1075838976
	.align 8
.LC11:
	.long	0
	.long	1083129856
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <hip/hip_runtime.h>

#include "stdio.h"
#include <sys/time.h>
#define DEBUG 1

extern "C" {

  // cleaner error handling; just wrap cuda library calls with gpuErrchk(foo());
  #define gpuErr(ans) { gpuAssert((ans), __FILE__, __LINE__); }
  inline void gpuAssert(hipError_t code, const char *file, int line, bool abort=true)
  {
    if (code != hipSuccess) 
    {
        fprintf(stderr,"GPUassert: %s %s %d\n", hipGetErrorString(code), file, line);
        if (abort) exit(code);
    }
  }

  __device__ int get_tid()
  {
    int blockId = blockIdx.x + blockIdx.y * gridDim.x
      + blockIdx.z * gridDim.x * gridDim.y;
    return  blockId * (blockDim.x * blockDim.y * blockDim.z)
      + (threadIdx.z * (blockDim.x * blockDim.y))
      + (threadIdx.y * blockDim.x)
      + threadIdx.x;
  }

  __global__ void dimer_1min1pls_t4(int n_elem, double *d_H, int *d_i, int *d_j, int *d_dim, float *d_sign, int *d_n_orb1, int *d_n_orb2, double *d_Rc1, double *d_Rcca1, double *d_Ra2, double *d_Rcaa2, double *d_h, double *d_V1, double *d_V2)
  {
    const int tid = get_tid();
    if(tid < n_elem) {
      const int n_orb1 = d_n_orb1[tid];
      const int n_orb2 = d_n_orb2[tid];
      double tmp = 0.0;
      int p,q,r,s;

      // In practice the n calculated here is not equal to the "actual" n here
      // since multiple kernel calls will be needed.
      // n_elem is the length

      // Top Loop
      // Use the tid to calculate variables in five dimensions
      //int n = tid;
      s = tid % n_orb2;
      r = ((tid - s) / (n_orb2)) % n_orb1;
      q = ((tid - r - s) * (n_orb2 * n_orb1)) % n_orb1;
      p = ((tid - q - r - s) / (n_orb2 * n_orb1 * n_orb1)) % n_orb1;
      tmp = d_V1[(((p * n_orb1 + q ) * n_orb1 + r) * n_orb2 + s) * n_elem + tid]
        * d_Rcca1[((q * n_orb1 + p)* n_orb1 + r) * n_elem + tid]
        * d_Ra2[s * n_elem + tid];

      // Middle Loop
      // 5d calculation
      s = tid % n_orb2;
      r = ((tid - s) / (n_orb2)) % n_orb2;
      q = ((tid - r - s) * (n_orb2 * n_orb2)) % n_orb2;
      p = ((tid - q - r - s) / (n_orb2 * n_orb2 * n_orb2)) % n_orb1;

      tmp += d_V2[(((p * n_orb2 + q ) * n_orb2 + r) * n_orb2 + s) * n_elem + tid]
        * d_Rcaa2[((q * n_orb2 + s) * n_orb2 + r) * n_elem + tid]
        * d_Rc1[p * n_elem + tid];
      tmp *= 2.0;

      // Bottom loop
      // 3d calculation
      s = tid % n_orb2;
      r = ((tid - s) / (n_orb2)) % n_orb1;
      tmp += d_h[(r * n_orb2 * s) * n_elem + tid]
        * d_Rc1[r * n_elem + tid]
        * d_Ra2[s * n_elem + tid];
      tmp *= d_sign[tid];

      // Assignment
      int index = d_i[tid] * d_dim[tid] + d_j[tid];
      d_H[index * n_elem + tid] = tmp;

      }
  }

void dimer_1min1pls_loop(int n_elem, double** H, int* i, int* j, int* dim, float* sign, int* n_orb1, int* n_orb2, double** Rc1,  double** Rcca1, double** Ra2, double** Rcaa2, double** h, double** V1, double** V2)
{
    struct timeval start,stop; 
    gettimeofday(&start,0);

    double *d_H, *d_Rc1, *d_Rcca1, *d_Ra2, *d_Rcaa2, *d_h, *d_V1, *d_V2;
    int *d_i, *d_j, *d_n_orb1, *d_n_orb2, *d_dim;
    float *d_sign;

    const int n1 = n_orb1[0];
    const int n2 = n_orb2[0];

    const int V1_len = n_elem * n2 * n1 * n1 * n1;
    const int V2_len = n_elem * n2 * n2 * n2 * n1;
    const int Rc1_len = n_elem * n1;
    const int Ra2_len = n_elem * n2;
    const int Rcca1_len = n_elem * n1 * n1 *n1;
    const int Rcaa2_len = n_elem * n2 * n2 * n2;
    const int h_len = n_elem * n1 * n2;
    const int H_len = n_elem * n1 * n1 * n1 * n2; // could be an issue if n1 != n2


    const int chunks = n1 * n2; // for maximum thread utilization this should go evenly into H_len
    const int elemPerChunk = ceil(n_elem / chunks);
    const int threadsPerChunk = ceil(H_len / chunks);
    const dim3 dimblock(4, 4, 4);
    const dim3 dimgrid(ceil(threadsPerChunk / dimblock.x), ceil(threadsPerChunk / dimblock.y), ceil(threadsPerChunk / dimblock.z));

    if(DEBUG) {
      printf("Chunks: %d\tThreads per chunk: %d\n",chunks,threadsPerChunk);
      printf("dimblock:\t<%d\t%d\t%d>\ndimgrid:\t<%d\t%d\t%d>\n",dimblock.x,dimblock.y,dimblock.z,dimgrid.x,dimgrid.y,dimgrid.z);
    }

    const int V1_size = sizeof(double) * ceil(V1_len / chunks);
    const int V2_size = sizeof(double) * ceil(V2_len / chunks);
    const int Rc1_size = sizeof(double) * ceil(Rc1_len / chunks);
    const int Ra2_size = sizeof(double) * ceil(Ra2_len / chunks);
    const int Rcca1_size = sizeof(double) * ceil(Rcca1_len / chunks);
    const int Rcaa2_size = sizeof(double) * ceil(Rcaa2_len / chunks);
    const int h_size = sizeof(double) * ceil(h_len / chunks);
    const int i_size = sizeof(int) * elemPerChunk; // for all the n-elem int arrays
    const int sign_size = sizeof(float) * elemPerChunk;
    const int H_size = sizeof(double) * threadsPerChunk;

    if(DEBUG) {
      printf("Starting device memory allocation\n");
    }

    gpuErr(hipMalloc((void **) &d_H,       H_size));
    gpuErr(hipMalloc((void **) &d_Rc1,     Rc1_size));
    gpuErr(hipMalloc((void **) &d_V1,      V1_size));
    gpuErr(hipMalloc((void **) &d_V2,      V2_size));
    gpuErr(hipMalloc((void **) &d_Ra2,     Ra2_size));
    gpuErr(hipMalloc((void **) &d_Rcca1,   Rcca1_size));
    gpuErr(hipMalloc((void **) &d_Rcaa2,   Rcaa2_size));
    gpuErr(hipMalloc((void **) &d_h,       h_size));
    gpuErr(hipMalloc((void **) &d_i,       i_size));
    gpuErr(hipMalloc((void **) &d_j,       i_size));
    gpuErr(hipMalloc((void **) &d_dim,     i_size));
    gpuErr(hipMalloc((void **) &d_n_orb1,  i_size));
    gpuErr(hipMalloc((void **) &d_n_orb2,  i_size));
    gpuErr(hipMalloc((void **) &d_sign,    sign_size));

    if(DEBUG) {
      printf("Finished device memory allocation\n");
    }

    for(int k=0; k<chunks; k++) {

      if(DEBUG) {
        printf("Chunk %d: starting host to device memcpys\n",k);
      }

      gpuErr(hipMemcpy(d_Rc1, Rc1 + k * Rc1_len, Rc1_size, hipMemcpyHostToDevice));
      gpuErr(hipMemcpy(d_V1, V1 + k * V1_len, V1_size, hipMemcpyHostToDevice));
      gpuErr(hipMemcpy(d_V2, V2 + k * V2_len , V2_size, hipMemcpyHostToDevice));
      gpuErr(hipMemcpy(d_Ra2, Ra2 + k * Ra2_len, Ra2_size, hipMemcpyHostToDevice));
      gpuErr(hipMemcpy(d_Rcca1, Rcca1 + k * Rcca1_len, Rcca1_size, hipMemcpyHostToDevice));
      gpuErr(hipMemcpy(d_Rcaa2, Rcaa2 + k * Rcaa2_len, Rcaa2_size, hipMemcpyHostToDevice));
      gpuErr(hipMemcpy(d_h, h + k * h_len, h_size, hipMemcpyHostToDevice));
      gpuErr(hipMemcpy(d_i, i + k * elemPerChunk, i_size, hipMemcpyHostToDevice));
      gpuErr(hipMemcpy(d_j, j + k * elemPerChunk, i_size, hipMemcpyHostToDevice));
      gpuErr(hipMemcpy(d_n_orb1, n_orb1 + k * elemPerChunk, i_size, hipMemcpyHostToDevice));
      gpuErr(hipMemcpy(d_n_orb2, n_orb2 + k * elemPerChunk, i_size, hipMemcpyHostToDevice));
      gpuErr(hipMemcpy(d_sign, sign + k * elemPerChunk, sign_size, hipMemcpyHostToDevice));

      if(DEBUG) {
        printf("Chunk %d: finished host to device memcpys\n",k);
        printf("Chunk %d: launching dimer_1min1pls_t4 kernel\n",k);
      }

      dimer_1min1pls_t4<<<dimblock,dimgrid>>>(n_elem,d_H,d_i,d_j,d_dim,d_sign,d_n_orb1,d_n_orb2,d_Rc1,d_Rcca1,d_Ra2,d_Rcaa2,d_h,d_V1,d_V2);
      gpuErr(hipPeekAtLastError());
      gpuErr(hipDeviceSynchronize());

      memcpy(H+k*H_len, d_H, H_size);


      if(DEBUG) {
        printf("Chunk %d: finished executing dimer_1min1pls_t4 kernel \n",k);
      }


    }

    gpuErr(hipFree(d_Rc1));
    gpuErr(hipFree(d_V1));
    gpuErr(hipFree(d_V2));
    gpuErr(hipFree(d_Ra2));
    gpuErr(hipFree(d_Rcca1));
    gpuErr(hipFree(d_Rcaa2));
    gpuErr(hipFree(d_h));
    gpuErr(hipFree(d_i));
    gpuErr(hipFree(d_j));
    gpuErr(hipFree(d_n_orb1));
    gpuErr(hipFree(d_n_orb2));
    gpuErr(hipFree(d_sign))
    gettimeofday(&stop,0);
    if(DEBUG) {
      double t = (double)(stop.tv_sec-start.tv_sec)*1000+(double)(stop.tv_usec-start.tv_usec)/1000;
      printf("dimer_1min1pls_loop_t4 finished in %f ms\n", t);
    }


}
}

	.text
	.file	"t4.hip"
	.globl	__device_stub__dimer_1min1pls_t4 # -- Begin function __device_stub__dimer_1min1pls_t4
	.type	__device_stub__dimer_1min1pls_t4,@function
__device_stub__dimer_1min1pls_t4:       # @__device_stub__dimer_1min1pls_t4
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$224, %rsp
	.cfi_def_cfa_offset 272
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	4(%rsp), %rax
	movl	%edi, (%rax)
	leaq	56(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	48(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	40(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	32(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	24(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	272(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	280(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	288(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	296(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	304(%rsp), %rax
	movq	%rax, 80(%rbx)
	leaq	312(%rsp), %rax
	movq	%rax, 88(%rbx)
	leaq	320(%rsp), %rax
	movq	%rax, 96(%rbx)
	leaq	328(%rsp), %rax
	movq	%rax, 104(%rbx)
	leaq	336(%rsp), %rax
	movq	%rax, 112(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$dimer_1min1pls_t4, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$240, %rsp
	.cfi_adjust_cfa_offset -240
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	__device_stub__dimer_1min1pls_t4, .Lfunc_end0-__device_stub__dimer_1min1pls_t4
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0                          # -- Begin function dimer_1min1pls_loop
.LCPI1_0:
	.quad	0x408f400000000000              # double 1000
	.text
	.globl	dimer_1min1pls_loop
	.type	dimer_1min1pls_loop,@function
dimer_1min1pls_loop:                    # @dimer_1min1pls_loop
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$392, %rsp                      # imm = 0x188
	.cfi_def_cfa_offset 448
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%r9, 280(%rsp)                  # 8-byte Spill
	movq	%rcx, 288(%rsp)                 # 8-byte Spill
	movq	%rdx, 304(%rsp)                 # 8-byte Spill
	movq	%rsi, 272(%rsp)                 # 8-byte Spill
	movl	%edi, %ebp
	movq	456(%rsp), %rbx
	movq	448(%rsp), %r14
	leaq	360(%rsp), %rdi
	xorl	%esi, %esi
	callq	gettimeofday
	movl	(%r14), %eax
	movl	(%rbx), %r12d
	movl	%r12d, %ecx
	imull	%ebp, %ecx
	movl	%ecx, 8(%rsp)                   # 4-byte Spill
	movl	%eax, %ebx
	imull	%eax, %ebx
	movl	%ebx, %r13d
	imull	%eax, %r13d
	imull	%ecx, %r13d
	movl	%r12d, %r14d
	imull	%r12d, %r14d
	imull	%ecx, %r14d
	movl	%r14d, %ecx
	imull	%eax, %ecx
	movl	%ecx, 24(%rsp)                  # 4-byte Spill
	movl	%eax, %ecx
	imull	%ebp, %ecx
	imull	%ecx, %ebx
	movl	%ecx, 80(%rsp)                  # 4-byte Spill
	imull	%r12d, %ecx
	movl	%ecx, 16(%rsp)                  # 4-byte Spill
	movl	%ebx, %ecx
	imull	%r12d, %ecx
	imull	%eax, %r12d
	movl	%ebp, 204(%rsp)                 # 4-byte Spill
	movl	%ebp, %eax
	cltd
	idivl	%r12d
                                        # kill: def $eax killed $eax def $rax
	movq	%rax, 72(%rsp)                  # 8-byte Spill
	movl	%ecx, 48(%rsp)                  # 4-byte Spill
	movl	%ecx, %eax
	cltd
	idivl	%r12d
	movl	%eax, %ebp
	movl	%eax, %r15d
	shrl	$2, %r15d
	movl	$.L.str, %edi
	movl	%r12d, %esi
	movl	%eax, %edx
	xorl	%eax, %eax
	callq	printf
	subq	$8, %rsp
	.cfi_adjust_cfa_offset 8
	movl	$.L.str.1, %edi
	movl	$4, %esi
	movl	$4, %edx
	movl	$4, %ecx
	movl	%r15d, %r8d
	movl	%r15d, %r9d
	xorl	%eax, %eax
	movq	%r15, 216(%rsp)                 # 8-byte Spill
	pushq	%r15
	.cfi_adjust_cfa_offset 8
	callq	printf
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	%r13d, %eax
	cltd
	idivl	%r12d
	movl	%eax, %r15d
	movl	24(%rsp), %eax                  # 4-byte Reload
	cltd
	idivl	%r12d
	movl	%eax, %r13d
	movl	8(%rsp), %eax                   # 4-byte Reload
	cltd
	idivl	%r12d
	movl	%eax, 40(%rsp)                  # 4-byte Spill
	movl	%ebx, 64(%rsp)                  # 4-byte Spill
	movl	%ebx, %eax
	cltd
	idivl	%r12d
	movl	%eax, 32(%rsp)                  # 4-byte Spill
	movl	%r14d, 56(%rsp)                 # 4-byte Spill
	movl	%r14d, %eax
	cltd
	idivl	%r12d
	movl	%eax, 96(%rsp)                  # 4-byte Spill
	movl	16(%rsp), %eax                  # 4-byte Reload
	cltd
	idivl	%r12d
	movl	%eax, %ebx
	shll	$3, %ebp
	movl	$.Lstr, %edi
	callq	puts@PLT
	movslq	%ebp, %rsi
	leaq	216(%rsp), %rdi
	movq	%rsi, 264(%rsp)                 # 8-byte Spill
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB1_1
# %bb.3:                                # %gpuAssert.exit
	movl	%ebx, 88(%rsp)                  # 4-byte Spill
	movl	80(%rsp), %eax                  # 4-byte Reload
	movl	%eax, %r14d
	cltd
	idivl	%r12d
	shll	$3, %eax
	movslq	%eax, %rsi
	leaq	192(%rsp), %rdi
	movq	%rsi, 344(%rsp)                 # 8-byte Spill
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB1_4
# %bb.5:                                # %gpuAssert.exit142
	shll	$3, %r15d
	movslq	%r15d, %rsi
	leaq	152(%rsp), %rdi
	movq	%rsi, 336(%rsp)                 # 8-byte Spill
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB1_6
# %bb.8:                                # %gpuAssert.exit144
	shll	$3, %r13d
	movslq	%r13d, %rsi
	leaq	144(%rsp), %rdi
	movq	%rsi, 328(%rsp)                 # 8-byte Spill
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB1_9
# %bb.10:                               # %gpuAssert.exit146
	movl	40(%rsp), %eax                  # 4-byte Reload
	shll	$3, %eax
	movslq	%eax, %rsi
	leaq	176(%rsp), %rdi
	movq	%rsi, 320(%rsp)                 # 8-byte Spill
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB1_11
# %bb.12:                               # %gpuAssert.exit148
	movl	%r14d, %ebp
	movl	32(%rsp), %eax                  # 4-byte Reload
	shll	$3, %eax
	movslq	%eax, %rsi
	leaq	184(%rsp), %rdi
	movq	%rsi, 312(%rsp)                 # 8-byte Spill
	callq	hipMalloc
	testl	%eax, %eax
	movq	72(%rsp), %r14                  # 8-byte Reload
	jne	.LBB1_13
# %bb.14:                               # %gpuAssert.exit150
	movl	96(%rsp), %eax                  # 4-byte Reload
	shll	$3, %eax
	movslq	%eax, %rsi
	leaq	168(%rsp), %rdi
	movq	%rsi, 96(%rsp)                  # 8-byte Spill
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB1_15
# %bb.16:                               # %gpuAssert.exit152
	movl	88(%rsp), %eax                  # 4-byte Reload
	shll	$3, %eax
	movslq	%eax, %rsi
	leaq	160(%rsp), %rdi
	movq	%rsi, 88(%rsp)                  # 8-byte Spill
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB1_17
# %bb.18:                               # %gpuAssert.exit154
	leal	(,%r14,4), %eax
	movslq	%eax, %r15
	leaq	136(%rsp), %rdi
	movq	%r15, %rsi
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB1_19
# %bb.20:                               # %gpuAssert.exit156
	leaq	128(%rsp), %rdi
	movq	%r15, %rsi
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB1_21
# %bb.22:                               # %gpuAssert.exit158
	leaq	352(%rsp), %rdi
	movq	%r15, %rsi
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB1_23
# %bb.24:                               # %gpuAssert.exit160
	leaq	120(%rsp), %rdi
	movq	%r15, %rsi
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB1_25
# %bb.26:                               # %gpuAssert.exit162
	leaq	112(%rsp), %rdi
	movq	%r15, %rsi
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB1_27
# %bb.28:                               # %gpuAssert.exit164
	leaq	104(%rsp), %rdi
	movq	%r15, 296(%rsp)                 # 8-byte Spill
	movq	%r15, %rsi
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB1_29
# %bb.30:                               # %gpuAssert.exit166
	movl	$.Lstr.1, %edi
	callq	puts@PLT
	testl	%r12d, %r12d
	jle	.LBB1_36
# %bb.31:                               # %.lr.ph.preheader
	movq	512(%rsp), %rcx
	movq	496(%rsp), %rax
	movq	%rax, 32(%rsp)                  # 8-byte Spill
	movq	488(%rsp), %r15
	movq	480(%rsp), %rax
	movq	%rax, 40(%rsp)                  # 8-byte Spill
	movq	208(%rsp), %rax                 # 8-byte Reload
	movq	%rax, %rdx
	shlq	$32, %rdx
	orq	%rax, %rdx
	movq	%rdx, 256(%rsp)                 # 8-byte Spill
	movslq	%ebp, %rax
	movslq	24(%rsp), %rdx                  # 4-byte Folded Reload
	movslq	8(%rsp), %rsi                   # 4-byte Folded Reload
	movslq	64(%rsp), %rdi                  # 4-byte Folded Reload
	movslq	56(%rsp), %r8                   # 4-byte Folded Reload
	movslq	16(%rsp), %r9                   # 4-byte Folded Reload
	movslq	%r14d, %r10
	movslq	48(%rsp), %r11                  # 4-byte Folded Reload
	movl	%r12d, %ebx
	movq	%rbx, 224(%rsp)                 # 8-byte Spill
	movq	%rcx, %r14
	shlq	$3, %r11
	movq	%r11, 232(%rsp)                 # 8-byte Spill
	shlq	$2, %r10
	movq	%r10, 240(%rsp)                 # 8-byte Spill
	shlq	$3, %r9
	movq	%r9, 248(%rsp)                  # 8-byte Spill
	shlq	$3, %r8
	movq	%r8, 48(%rsp)                   # 8-byte Spill
	shlq	$3, %rdi
	movq	%rdi, 56(%rsp)                  # 8-byte Spill
	shlq	$3, %rsi
	movq	%rsi, 64(%rsp)                  # 8-byte Spill
	shlq	$3, %rdx
	movq	%rdx, 72(%rsp)                  # 8-byte Spill
	shlq	$3, %rax
	movq	%rax, 80(%rsp)                  # 8-byte Spill
	movq	472(%rsp), %rax
	movq	%rax, 8(%rsp)                   # 8-byte Spill
	movq	464(%rsp), %r12
	xorl	%ebp, %ebp
	xorl	%ebx, %ebx
	xorl	%r13d, %r13d
.LBB1_32:                               # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	movl	$.L.str.5, %edi
	movl	%r13d, %esi
	xorl	%eax, %eax
	callq	printf
	movq	192(%rsp), %rdi
	movq	%r12, 24(%rsp)                  # 8-byte Spill
	movq	%r12, %rsi
	movq	344(%rsp), %rdx                 # 8-byte Reload
	movl	$1, %ecx
	callq	hipMemcpy
	testl	%eax, %eax
	jne	.LBB1_33
# %bb.61:                               # %gpuAssert.exit192
                                        #   in Loop: Header=BB1_32 Depth=1
	movq	152(%rsp), %rdi
	movq	504(%rsp), %rax
	leaq	(%rax,%rbx), %rsi
	movq	336(%rsp), %rdx                 # 8-byte Reload
	movl	$1, %ecx
	callq	hipMemcpy
	testl	%eax, %eax
	jne	.LBB1_62
# %bb.63:                               # %gpuAssert.exit194
                                        #   in Loop: Header=BB1_32 Depth=1
	movq	144(%rsp), %rdi
	movq	%r14, %rsi
	movq	328(%rsp), %rdx                 # 8-byte Reload
	movl	$1, %ecx
	callq	hipMemcpy
	testl	%eax, %eax
	jne	.LBB1_64
# %bb.65:                               # %gpuAssert.exit196
                                        #   in Loop: Header=BB1_32 Depth=1
	movq	176(%rsp), %rdi
	movq	40(%rsp), %rsi                  # 8-byte Reload
	movq	320(%rsp), %rdx                 # 8-byte Reload
	movl	$1, %ecx
	callq	hipMemcpy
	testl	%eax, %eax
	jne	.LBB1_66
# %bb.67:                               # %gpuAssert.exit198
                                        #   in Loop: Header=BB1_32 Depth=1
	movq	184(%rsp), %rdi
	movq	8(%rsp), %rsi                   # 8-byte Reload
	movq	312(%rsp), %rdx                 # 8-byte Reload
	movl	$1, %ecx
	callq	hipMemcpy
	testl	%eax, %eax
	jne	.LBB1_68
# %bb.69:                               # %gpuAssert.exit200
                                        #   in Loop: Header=BB1_32 Depth=1
	movq	168(%rsp), %rdi
	movq	%r15, 16(%rsp)                  # 8-byte Spill
	movq	%r15, %rsi
	movq	96(%rsp), %rdx                  # 8-byte Reload
	movl	$1, %ecx
	callq	hipMemcpy
	testl	%eax, %eax
	jne	.LBB1_70
# %bb.71:                               # %gpuAssert.exit202
                                        #   in Loop: Header=BB1_32 Depth=1
	movq	%r14, %r15
	movq	160(%rsp), %rdi
	movq	32(%rsp), %rsi                  # 8-byte Reload
	movq	88(%rsp), %rdx                  # 8-byte Reload
	movl	$1, %ecx
	callq	hipMemcpy
	testl	%eax, %eax
	jne	.LBB1_72
# %bb.73:                               # %gpuAssert.exit204
                                        #   in Loop: Header=BB1_32 Depth=1
	movq	136(%rsp), %rdi
	movq	304(%rsp), %rax                 # 8-byte Reload
	leaq	(%rax,%rbp), %rsi
	movq	296(%rsp), %r14                 # 8-byte Reload
	movq	%r14, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	testl	%eax, %eax
	jne	.LBB1_74
# %bb.75:                               # %gpuAssert.exit206
                                        #   in Loop: Header=BB1_32 Depth=1
	movq	128(%rsp), %rdi
	movq	288(%rsp), %rax                 # 8-byte Reload
	leaq	(%rax,%rbp), %rsi
	movq	%r14, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	testl	%eax, %eax
	jne	.LBB1_76
# %bb.77:                               # %gpuAssert.exit208
                                        #   in Loop: Header=BB1_32 Depth=1
	movq	120(%rsp), %rdi
	movq	448(%rsp), %rax
	leaq	(%rax,%rbp), %rsi
	movq	%r14, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	testl	%eax, %eax
	jne	.LBB1_78
# %bb.79:                               # %gpuAssert.exit210
                                        #   in Loop: Header=BB1_32 Depth=1
	movq	112(%rsp), %rdi
	movq	456(%rsp), %rax
	leaq	(%rax,%rbp), %rsi
	movq	%r14, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	testl	%eax, %eax
	jne	.LBB1_80
# %bb.81:                               # %gpuAssert.exit212
                                        #   in Loop: Header=BB1_32 Depth=1
	movq	104(%rsp), %rdi
	movq	280(%rsp), %rax                 # 8-byte Reload
	leaq	(%rax,%rbp), %rsi
	movq	%r14, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	testl	%eax, %eax
	jne	.LBB1_82
# %bb.83:                               # %gpuAssert.exit214
                                        #   in Loop: Header=BB1_32 Depth=1
	movl	$.L.str.6, %edi
	movl	%r13d, %esi
	xorl	%eax, %eax
	callq	printf
	movl	$.L.str.7, %edi
	movl	%r13d, %esi
	xorl	%eax, %eax
	callq	printf
	movabsq	$17179869188, %rdi              # imm = 0x400000004
	movl	$4, %esi
	movq	256(%rsp), %rdx                 # 8-byte Reload
	movq	208(%rsp), %rcx                 # 8-byte Reload
                                        # kill: def $ecx killed $ecx killed $rcx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	movq	%r15, %r14
	jne	.LBB1_85
# %bb.84:                               #   in Loop: Header=BB1_32 Depth=1
	movq	216(%rsp), %rsi
	movq	136(%rsp), %rdx
	movq	128(%rsp), %rcx
	movq	352(%rsp), %r8
	movq	104(%rsp), %r9
	subq	$8, %rsp
	.cfi_adjust_cfa_offset 8
	movl	212(%rsp), %edi                 # 4-byte Reload
	pushq	152(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	168(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	184(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	200(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	216(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	232(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	248(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	176(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	192(%rsp)
	.cfi_adjust_cfa_offset 8
	callq	__device_stub__dimer_1min1pls_t4
	addq	$80, %rsp
	.cfi_adjust_cfa_offset -80
.LBB1_85:                               #   in Loop: Header=BB1_32 Depth=1
	callq	hipPeekAtLastError
	testl	%eax, %eax
	movq	16(%rsp), %r15                  # 8-byte Reload
	jne	.LBB1_86
# %bb.87:                               # %gpuAssert.exit216
                                        #   in Loop: Header=BB1_32 Depth=1
	callq	hipDeviceSynchronize
	testl	%eax, %eax
	jne	.LBB1_88
# %bb.35:                               # %gpuAssert.exit218
                                        #   in Loop: Header=BB1_32 Depth=1
	movq	272(%rsp), %rax                 # 8-byte Reload
	leaq	(%rax,%rbx), %rdi
	movq	216(%rsp), %rsi
	movq	264(%rsp), %rdx                 # 8-byte Reload
	callq	memcpy@PLT
	movl	$.L.str.8, %edi
	movl	%r13d, %esi
	xorl	%eax, %eax
	callq	printf
	incq	%r13
	addq	232(%rsp), %rbx                 # 8-byte Folded Reload
	addq	240(%rsp), %rbp                 # 8-byte Folded Reload
	movq	248(%rsp), %rax                 # 8-byte Reload
	addq	%rax, 32(%rsp)                  # 8-byte Folded Spill
	addq	48(%rsp), %r15                  # 8-byte Folded Reload
	movq	8(%rsp), %rax                   # 8-byte Reload
	addq	56(%rsp), %rax                  # 8-byte Folded Reload
	movq	%rax, 8(%rsp)                   # 8-byte Spill
	movq	64(%rsp), %rax                  # 8-byte Reload
	addq	%rax, 40(%rsp)                  # 8-byte Folded Spill
	addq	72(%rsp), %r14                  # 8-byte Folded Reload
	movq	24(%rsp), %r12                  # 8-byte Reload
	addq	80(%rsp), %r12                  # 8-byte Folded Reload
	cmpq	%r13, 224(%rsp)                 # 8-byte Folded Reload
	jne	.LBB1_32
.LBB1_36:                               # %._crit_edge
	movq	192(%rsp), %rdi
	callq	hipFree
	testl	%eax, %eax
	jne	.LBB1_37
# %bb.38:                               # %gpuAssert.exit168
	movq	152(%rsp), %rdi
	callq	hipFree
	testl	%eax, %eax
	jne	.LBB1_39
# %bb.40:                               # %gpuAssert.exit170
	movq	144(%rsp), %rdi
	callq	hipFree
	testl	%eax, %eax
	jne	.LBB1_41
# %bb.42:                               # %gpuAssert.exit172
	movq	176(%rsp), %rdi
	callq	hipFree
	testl	%eax, %eax
	jne	.LBB1_43
# %bb.44:                               # %gpuAssert.exit174
	movq	184(%rsp), %rdi
	callq	hipFree
	testl	%eax, %eax
	jne	.LBB1_45
# %bb.46:                               # %gpuAssert.exit176
	movq	168(%rsp), %rdi
	callq	hipFree
	testl	%eax, %eax
	jne	.LBB1_47
# %bb.48:                               # %gpuAssert.exit178
	movq	160(%rsp), %rdi
	callq	hipFree
	testl	%eax, %eax
	jne	.LBB1_49
# %bb.50:                               # %gpuAssert.exit180
	movq	136(%rsp), %rdi
	callq	hipFree
	testl	%eax, %eax
	jne	.LBB1_51
# %bb.52:                               # %gpuAssert.exit182
	movq	128(%rsp), %rdi
	callq	hipFree
	testl	%eax, %eax
	jne	.LBB1_53
# %bb.54:                               # %gpuAssert.exit184
	movq	120(%rsp), %rdi
	callq	hipFree
	testl	%eax, %eax
	jne	.LBB1_55
# %bb.56:                               # %gpuAssert.exit186
	movq	112(%rsp), %rdi
	callq	hipFree
	testl	%eax, %eax
	jne	.LBB1_57
# %bb.58:                               # %gpuAssert.exit188
	movq	104(%rsp), %rdi
	callq	hipFree
	testl	%eax, %eax
	jne	.LBB1_59
# %bb.60:                               # %gpuAssert.exit190
	leaq	376(%rsp), %rbx
	movq	%rbx, %rdi
	xorl	%esi, %esi
	callq	gettimeofday
	movq	(%rbx), %rax
	movq	8(%rbx), %rcx
	subq	360(%rsp), %rax
	cvtsi2sd	%rax, %xmm1
	movsd	.LCPI1_0(%rip), %xmm2           # xmm2 = mem[0],zero
	mulsd	%xmm2, %xmm1
	subq	368(%rsp), %rcx
	cvtsi2sd	%rcx, %xmm0
	divsd	%xmm2, %xmm0
	addsd	%xmm1, %xmm0
	movl	$.L.str.9, %edi
	movb	$1, %al
	callq	printf
	addq	$392, %rsp                      # imm = 0x188
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB1_88:
	.cfi_def_cfa_offset 448
	movl	%eax, %r12d
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.10, %esi
	movl	$.L.str.3, %ecx
	movq	%rbx, %rdi
	movq	%rax, %rdx
	movl	$175, %r8d
	jmp	.LBB1_34
.LBB1_86:
	movl	%eax, %r12d
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.10, %esi
	movl	$.L.str.3, %ecx
	movq	%rbx, %rdi
	movq	%rax, %rdx
	movl	$174, %r8d
	jmp	.LBB1_34
.LBB1_82:
	movl	%eax, %r12d
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.10, %esi
	movl	$.L.str.3, %ecx
	movq	%rbx, %rdi
	movq	%rax, %rdx
	movl	$166, %r8d
	jmp	.LBB1_34
.LBB1_80:
	movl	%eax, %r12d
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.10, %esi
	movl	$.L.str.3, %ecx
	movq	%rbx, %rdi
	movq	%rax, %rdx
	movl	$165, %r8d
	jmp	.LBB1_34
.LBB1_78:
	movl	%eax, %r12d
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.10, %esi
	movl	$.L.str.3, %ecx
	movq	%rbx, %rdi
	movq	%rax, %rdx
	movl	$164, %r8d
	jmp	.LBB1_34
.LBB1_76:
	movl	%eax, %r12d
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.10, %esi
	movl	$.L.str.3, %ecx
	movq	%rbx, %rdi
	movq	%rax, %rdx
	movl	$163, %r8d
	jmp	.LBB1_34
.LBB1_74:
	movl	%eax, %r12d
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.10, %esi
	movl	$.L.str.3, %ecx
	movq	%rbx, %rdi
	movq	%rax, %rdx
	movl	$162, %r8d
	jmp	.LBB1_34
.LBB1_72:
	movl	%eax, %r12d
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.10, %esi
	movl	$.L.str.3, %ecx
	movq	%rbx, %rdi
	movq	%rax, %rdx
	movl	$161, %r8d
	jmp	.LBB1_34
.LBB1_70:
	movl	%eax, %r12d
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.10, %esi
	movl	$.L.str.3, %ecx
	movq	%rbx, %rdi
	movq	%rax, %rdx
	movl	$160, %r8d
	jmp	.LBB1_34
.LBB1_68:
	movl	%eax, %r12d
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.10, %esi
	movl	$.L.str.3, %ecx
	movq	%rbx, %rdi
	movq	%rax, %rdx
	movl	$159, %r8d
	jmp	.LBB1_34
.LBB1_66:
	movl	%eax, %r12d
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.10, %esi
	movl	$.L.str.3, %ecx
	movq	%rbx, %rdi
	movq	%rax, %rdx
	movl	$158, %r8d
	jmp	.LBB1_34
.LBB1_64:
	movl	%eax, %r12d
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.10, %esi
	movl	$.L.str.3, %ecx
	movq	%rbx, %rdi
	movq	%rax, %rdx
	movl	$157, %r8d
	jmp	.LBB1_34
.LBB1_62:
	movl	%eax, %r12d
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.10, %esi
	movl	$.L.str.3, %ecx
	movq	%rbx, %rdi
	movq	%rax, %rdx
	movl	$156, %r8d
	jmp	.LBB1_34
.LBB1_33:
	movl	%eax, %r12d
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.10, %esi
	movl	$.L.str.3, %ecx
	movq	%rbx, %rdi
	movq	%rax, %rdx
	movl	$155, %r8d
.LBB1_34:
	xorl	%eax, %eax
	callq	fprintf
	movl	%r12d, %edi
	callq	exit
.LBB1_1:
	movl	%eax, %ebp
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.10, %esi
	movl	$.L.str.3, %ecx
	movq	%rbx, %rdi
	movq	%rax, %rdx
	movl	$130, %r8d
	jmp	.LBB1_2
.LBB1_4:
	movl	%eax, %ebp
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.10, %esi
	movl	$.L.str.3, %ecx
	movq	%rbx, %rdi
	movq	%rax, %rdx
	movl	$131, %r8d
.LBB1_2:
	xorl	%eax, %eax
	callq	fprintf
	movl	%ebp, %edi
	callq	exit
.LBB1_6:
	movl	%eax, %ebx
	movq	stderr(%rip), %r14
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.10, %esi
	movl	$.L.str.3, %ecx
	movq	%r14, %rdi
	movq	%rax, %rdx
	movl	$132, %r8d
	jmp	.LBB1_7
.LBB1_9:
	movl	%eax, %ebx
	movq	stderr(%rip), %r14
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.10, %esi
	movl	$.L.str.3, %ecx
	movq	%r14, %rdi
	movq	%rax, %rdx
	movl	$133, %r8d
	jmp	.LBB1_7
.LBB1_11:
	movl	%eax, %ebx
	movq	stderr(%rip), %r14
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.10, %esi
	movl	$.L.str.3, %ecx
	movq	%r14, %rdi
	movq	%rax, %rdx
	movl	$134, %r8d
	jmp	.LBB1_7
.LBB1_13:
	movl	%eax, %ebx
	movq	stderr(%rip), %r14
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.10, %esi
	movl	$.L.str.3, %ecx
	movq	%r14, %rdi
	movq	%rax, %rdx
	movl	$135, %r8d
	jmp	.LBB1_7
.LBB1_15:
	movl	%eax, %ebx
	movq	stderr(%rip), %r14
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.10, %esi
	movl	$.L.str.3, %ecx
	movq	%r14, %rdi
	movq	%rax, %rdx
	movl	$136, %r8d
	jmp	.LBB1_7
.LBB1_17:
	movl	%eax, %ebx
	movq	stderr(%rip), %r14
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.10, %esi
	movl	$.L.str.3, %ecx
	movq	%r14, %rdi
	movq	%rax, %rdx
	movl	$137, %r8d
	jmp	.LBB1_7
.LBB1_19:
	movl	%eax, %ebx
	movq	stderr(%rip), %r14
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.10, %esi
	movl	$.L.str.3, %ecx
	movq	%r14, %rdi
	movq	%rax, %rdx
	movl	$138, %r8d
	jmp	.LBB1_7
.LBB1_21:
	movl	%eax, %ebx
	movq	stderr(%rip), %r14
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.10, %esi
	movl	$.L.str.3, %ecx
	movq	%r14, %rdi
	movq	%rax, %rdx
	movl	$139, %r8d
	jmp	.LBB1_7
.LBB1_23:
	movl	%eax, %ebx
	movq	stderr(%rip), %r14
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.10, %esi
	movl	$.L.str.3, %ecx
	movq	%r14, %rdi
	movq	%rax, %rdx
	movl	$140, %r8d
	jmp	.LBB1_7
.LBB1_25:
	movl	%eax, %ebx
	movq	stderr(%rip), %r14
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.10, %esi
	movl	$.L.str.3, %ecx
	movq	%r14, %rdi
	movq	%rax, %rdx
	movl	$141, %r8d
	jmp	.LBB1_7
.LBB1_27:
	movl	%eax, %ebx
	movq	stderr(%rip), %r14
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.10, %esi
	movl	$.L.str.3, %ecx
	movq	%r14, %rdi
	movq	%rax, %rdx
	movl	$142, %r8d
	jmp	.LBB1_7
.LBB1_29:
	movl	%eax, %ebx
	movq	stderr(%rip), %r14
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.10, %esi
	movl	$.L.str.3, %ecx
	movq	%r14, %rdi
	movq	%rax, %rdx
	movl	$143, %r8d
	jmp	.LBB1_7
.LBB1_37:
	movl	%eax, %ebx
	movq	stderr(%rip), %r14
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.10, %esi
	movl	$.L.str.3, %ecx
	movq	%r14, %rdi
	movq	%rax, %rdx
	movl	$187, %r8d
	jmp	.LBB1_7
.LBB1_39:
	movl	%eax, %ebx
	movq	stderr(%rip), %r14
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.10, %esi
	movl	$.L.str.3, %ecx
	movq	%r14, %rdi
	movq	%rax, %rdx
	movl	$188, %r8d
	jmp	.LBB1_7
.LBB1_41:
	movl	%eax, %ebx
	movq	stderr(%rip), %r14
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.10, %esi
	movl	$.L.str.3, %ecx
	movq	%r14, %rdi
	movq	%rax, %rdx
	movl	$189, %r8d
	jmp	.LBB1_7
.LBB1_43:
	movl	%eax, %ebx
	movq	stderr(%rip), %r14
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.10, %esi
	movl	$.L.str.3, %ecx
	movq	%r14, %rdi
	movq	%rax, %rdx
	movl	$190, %r8d
	jmp	.LBB1_7
.LBB1_45:
	movl	%eax, %ebx
	movq	stderr(%rip), %r14
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.10, %esi
	movl	$.L.str.3, %ecx
	movq	%r14, %rdi
	movq	%rax, %rdx
	movl	$191, %r8d
	jmp	.LBB1_7
.LBB1_47:
	movl	%eax, %ebx
	movq	stderr(%rip), %r14
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.10, %esi
	movl	$.L.str.3, %ecx
	movq	%r14, %rdi
	movq	%rax, %rdx
	movl	$192, %r8d
	jmp	.LBB1_7
.LBB1_49:
	movl	%eax, %ebx
	movq	stderr(%rip), %r14
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.10, %esi
	movl	$.L.str.3, %ecx
	movq	%r14, %rdi
	movq	%rax, %rdx
	movl	$193, %r8d
	jmp	.LBB1_7
.LBB1_51:
	movl	%eax, %ebx
	movq	stderr(%rip), %r14
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.10, %esi
	movl	$.L.str.3, %ecx
	movq	%r14, %rdi
	movq	%rax, %rdx
	movl	$194, %r8d
	jmp	.LBB1_7
.LBB1_53:
	movl	%eax, %ebx
	movq	stderr(%rip), %r14
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.10, %esi
	movl	$.L.str.3, %ecx
	movq	%r14, %rdi
	movq	%rax, %rdx
	movl	$195, %r8d
	jmp	.LBB1_7
.LBB1_55:
	movl	%eax, %ebx
	movq	stderr(%rip), %r14
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.10, %esi
	movl	$.L.str.3, %ecx
	movq	%r14, %rdi
	movq	%rax, %rdx
	movl	$196, %r8d
	jmp	.LBB1_7
.LBB1_57:
	movl	%eax, %ebx
	movq	stderr(%rip), %r14
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.10, %esi
	movl	$.L.str.3, %ecx
	movq	%r14, %rdi
	movq	%rax, %rdx
	movl	$197, %r8d
	jmp	.LBB1_7
.LBB1_59:
	movl	%eax, %ebx
	movq	stderr(%rip), %r14
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.10, %esi
	movl	$.L.str.3, %ecx
	movq	%r14, %rdi
	movq	%rax, %rdx
	movl	$198, %r8d
.LBB1_7:
	xorl	%eax, %eax
	callq	fprintf
	movl	%ebx, %edi
	callq	exit
.Lfunc_end1:
	.size	dimer_1min1pls_loop, .Lfunc_end1-dimer_1min1pls_loop
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$dimer_1min1pls_t4, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	dimer_1min1pls_t4,@object       # @dimer_1min1pls_t4
	.section	.rodata,"a",@progbits
	.globl	dimer_1min1pls_t4
	.p2align	3, 0x0
dimer_1min1pls_t4:
	.quad	__device_stub__dimer_1min1pls_t4
	.size	dimer_1min1pls_t4, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"Chunks: %d\tThreads per chunk: %d\n"
	.size	.L.str, 34

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"dimblock:\t<%d\t%d\t%d>\ndimgrid:\t<%d\t%d\t%d>\n"
	.size	.L.str.1, 42

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"/home/ubuntu/Datasets/stackv2/train-structured-repos-hip-sm89/sskhan67/GPGPU-Programming-/master/QODE/Applications/GPU-pilot/t4.hip"
	.size	.L.str.3, 132

	.type	.L.str.5,@object                # @.str.5
.L.str.5:
	.asciz	"Chunk %d: starting host to device memcpys\n"
	.size	.L.str.5, 43

	.type	.L.str.6,@object                # @.str.6
.L.str.6:
	.asciz	"Chunk %d: finished host to device memcpys\n"
	.size	.L.str.6, 43

	.type	.L.str.7,@object                # @.str.7
.L.str.7:
	.asciz	"Chunk %d: launching dimer_1min1pls_t4 kernel\n"
	.size	.L.str.7, 46

	.type	.L.str.8,@object                # @.str.8
.L.str.8:
	.asciz	"Chunk %d: finished executing dimer_1min1pls_t4 kernel \n"
	.size	.L.str.8, 56

	.type	.L.str.9,@object                # @.str.9
.L.str.9:
	.asciz	"dimer_1min1pls_loop_t4 finished in %f ms\n"
	.size	.L.str.9, 42

	.type	.L.str.10,@object               # @.str.10
.L.str.10:
	.asciz	"GPUassert: %s %s %d\n"
	.size	.L.str.10, 21

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"dimer_1min1pls_t4"
	.size	.L__unnamed_1, 18

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.type	.Lstr,@object                   # @str
	.section	.rodata.str1.1,"aMS",@progbits,1
.Lstr:
	.asciz	"Starting device memory allocation"
	.size	.Lstr, 34

	.type	.Lstr.1,@object                 # @str.1
.Lstr.1:
	.asciz	"Finished device memory allocation"
	.size	.Lstr.1, 34

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __device_stub__dimer_1min1pls_t4
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym dimer_1min1pls_t4
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	dimer_1min1pls_t4       ; -- Begin function dimer_1min1pls_t4
	.globl	dimer_1min1pls_t4
	.p2align	8
	.type	dimer_1min1pls_t4,@function
dimer_1min1pls_t4:                      ; @dimer_1min1pls_t4
; %bb.0:
	s_clause 0x1
	s_load_b64 s[2:3], s[0:1], 0x78
	s_load_b32 s28, s[0:1], 0x0
	v_mov_b32_e32 v1, 0
	s_add_u32 s4, s0, 0x78
	s_addc_u32 s5, s1, 0
	global_load_b32 v4, v1, s[0:1] offset:134
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s3, s3, s15
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s3, s3, s14
	s_mul_i32 s3, s3, s2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_add_i32 s3, s3, s13
	s_cmp_lt_u32 s13, s2
	s_cselect_b32 s2, 12, 18
	v_mov_b32_e32 v1, s2
	s_mov_b32 s2, exec_lo
	global_load_u16 v5, v1, s[4:5]
	v_bfe_u32 v1, v0, 20, 10
	s_waitcnt vmcnt(1)
	v_lshrrev_b32_e32 v6, 16, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[2:3], null, s3, v6, v[1:2]
	v_and_b32_e32 v6, 0xffff, v4
	v_bfe_u32 v1, v0, 10, 10
	v_mad_u64_u32 v[3:4], null, v2, v6, v[1:2]
	v_and_b32_e32 v2, 0x3ff, v0
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[0:1], null, v3, v5, v[2:3]
	v_cmpx_gt_i32_e64 s28, v0
	s_cbranch_execz .LBB0_2
; %bb.1:
	s_load_b512 s[4:19], s[0:1], 0x8
	v_ashrrev_i32_e32 v1, 31, v0
	s_clause 0x1
	s_load_b256 s[20:27], s[0:1], 0x48
	s_load_b128 s[0:3], s[0:1], 0x68
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[0:1]
	v_add_nc_u32_e32 v10, v0, v1
	v_xor_b32_e32 v10, v10, v1
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v4, vcc_lo, s16, v2
	v_add_co_ci_u32_e32 v5, vcc_lo, s17, v3, vcc_lo
	global_load_b32 v4, v[4:5], off
	v_add_co_u32 v5, vcc_lo, s14, v2
	v_add_co_ci_u32_e32 v6, vcc_lo, s15, v3, vcc_lo
	global_load_b32 v5, v[5:6], off
	s_waitcnt vmcnt(1)
	v_ashrrev_i32_e32 v6, 31, v4
	s_delay_alu instid0(VALU_DEP_1)
	v_add_nc_u32_e32 v7, v4, v6
	v_xor_b32_e32 v1, v1, v6
	s_waitcnt vmcnt(0)
	v_ashrrev_i32_e32 v12, 31, v5
	v_mul_lo_u32 v16, v4, v5
	v_xor_b32_e32 v8, v7, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cvt_f32_u32_e32 v7, v8
	v_sub_nc_u32_e32 v9, 0, v8
	v_rcp_iflag_f32_e32 v7, v7
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v7, 0x4f7ffffe, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v7, v7
	v_mul_lo_u32 v9, v9, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v9, v7, v9
	v_add_nc_u32_e32 v9, v7, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v7, v10, v9
	v_mul_lo_u32 v11, v7, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v10, v10, v11
	v_add_nc_u32_e32 v11, 1, v7
	v_sub_nc_u32_e32 v14, v10, v8
	v_cmp_ge_u32_e32 vcc_lo, v10, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_cndmask_b32 v7, v7, v11 :: v_dual_cndmask_b32 v10, v10, v14
	v_add_nc_u32_e32 v11, 1, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_ge_u32_e32 vcc_lo, v10, v8
	v_dual_cndmask_b32 v6, v7, v11 :: v_dual_add_nc_u32 v13, v5, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v15, v13, v12
	v_xor_b32_e32 v6, v6, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_f32_u32_e32 v12, v15
	v_sub_nc_u32_e32 v1, v6, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v7, v12
	v_ashrrev_i32_e32 v10, 31, v1
	s_waitcnt_depctr 0xfff
	v_dual_mul_f32 v6, 0x4f7ffffe, v7 :: v_dual_add_nc_u32 v11, v1, v10
	v_sub_nc_u32_e32 v7, 0, v15
	v_mul_lo_u32 v1, v1, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v11, v11, v10
	v_cvt_u32_f32_e32 v6, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v12, v11, v9
	v_mul_lo_u32 v7, v7, v6
	v_sub_nc_u32_e32 v1, v0, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v7, v6, v7
	v_add_nc_u32_e32 v13, v6, v7
	v_mul_lo_u32 v6, v12, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v7, v11, v13
	v_sub_nc_u32_e32 v6, v11, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v7, v7, v15
	v_sub_nc_u32_e32 v12, v6, v8
	v_cmp_ge_u32_e32 vcc_lo, v6, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e32 v6, v6, v12, vcc_lo
	v_sub_nc_u32_e32 v7, v11, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v11, v6, v8
	v_cmp_ge_u32_e32 vcc_lo, v6, v8
	v_sub_nc_u32_e32 v12, v7, v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v6, v6, v11, vcc_lo
	v_cmp_ge_u32_e32 vcc_lo, v7, v15
	v_cndmask_b32_e32 v7, v7, v12, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v6, v6, v10
	v_mul_lo_u32 v12, v4, v4
	v_sub_nc_u32_e32 v11, v7, v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v6, v6, v10
	v_cmp_ge_u32_e32 vcc_lo, v7, v15
	v_cndmask_b32_e32 v7, v7, v11, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v11, v1, v6
	v_xor_b32_e32 v7, v7, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v14, v0, v11
	v_sub_nc_u32_e32 v7, v7, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v10, v14, v12
	v_mul_lo_u32 v12, v12, v4
	v_ashrrev_i32_e32 v17, 31, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v20, 31, v12
	v_add_nc_u32_e32 v10, v10, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v12, v12, v20
	v_xor_b32_e32 v10, v10, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v9, v10, v9
	v_mul_lo_u32 v9, v9, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v9, v10, v9
	v_xor_b32_e32 v10, v12, v20
	v_mul_lo_u32 v12, v16, v5
	v_cmp_ge_u32_e32 vcc_lo, v9, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f32_u32_e32 v22, v10
	v_rcp_iflag_f32_e32 v22, v22
	v_add_nc_u32_e32 v14, v1, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v18, v0, v14
	v_mul_lo_u32 v18, v18, v16
	v_sub_nc_u32_e32 v16, v9, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cndmask_b32_e32 v9, v9, v16, vcc_lo
	v_ashrrev_i32_e32 v16, 31, v12
	v_ashrrev_i32_e32 v19, 31, v18
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v23, v9, v8
	v_cmp_ge_u32_e32 vcc_lo, v9, v8
	v_add_nc_u32_e32 v18, v18, v19
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v8, v9, v23, vcc_lo
	v_xor_b32_e32 v18, v18, v19
	v_mul_f32_e32 v9, 0x4f7ffffe, v22
	v_sub_nc_u32_e32 v22, 0, v10
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v8, v8, v17
	v_mul_hi_u32 v21, v18, v13
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cvt_u32_f32_e32 v23, v9
	v_sub_nc_u32_e32 v8, v8, v17
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v21, v21, v15
	v_add_nc_u32_e32 v11, v11, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v11, v0, v11
	v_sub_nc_u32_e32 v18, v18, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v21, v18, v15
	v_cmp_ge_u32_e32 vcc_lo, v18, v15
	v_dual_cndmask_b32 v9, v18, v21 :: v_dual_add_nc_u32 v12, v12, v16
	v_mul_lo_u32 v18, v22, v23
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v12, v12, v16
	v_sub_nc_u32_e32 v21, v9, v15
	v_cmp_ge_u32_e32 vcc_lo, v9, v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cvt_f32_u32_e32 v17, v12
	v_mul_hi_u32 v18, v23, v18
	v_cndmask_b32_e32 v9, v9, v21, vcc_lo
	v_ashrrev_i32_e32 v21, 31, v11
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_rcp_iflag_f32_e32 v17, v17
	v_add_nc_u32_e32 v18, v23, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v11, v11, v21
	v_xor_b32_e32 v9, v9, v19
	v_xor_b32_e32 v20, v21, v20
	v_xor_b32_e32 v11, v11, v21
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v17, 0x4f7ffffe, v17
	v_sub_nc_u32_e32 v9, v9, v19
	v_sub_nc_u32_e32 v19, 0, v12
	v_mul_hi_u32 v18, v11, v18
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v17, v17
	v_mul_lo_u32 v19, v19, v17
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v23, v18, v10
	v_mul_hi_u32 v19, v17, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v11, v11, v23
	v_sub_nc_u32_e32 v23, v11, v10
	v_cmp_ge_u32_e32 vcc_lo, v11, v10
	v_add_nc_u32_e32 v14, v14, v9
	v_add_nc_u32_e32 v17, v17, v19
	v_add_nc_u32_e32 v19, 1, v18
	v_cndmask_b32_e32 v11, v11, v23, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_sub_nc_u32_e32 v14, v0, v14
	v_mul_lo_u32 v23, v1, s28
	v_cndmask_b32_e32 v18, v18, v19, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cmp_ge_u32_e32 vcc_lo, v11, v10
	v_ashrrev_i32_e32 v22, 31, v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v19, 1, v18
	v_add_nc_u32_e32 v14, v14, v22
	v_xor_b32_e32 v16, v22, v16
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v10, v18, v19, vcc_lo
	v_xor_b32_e32 v14, v14, v22
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v10, v10, v20
	v_mul_hi_u32 v17, v14, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v10, v10, v20
	v_mul_lo_u32 v21, v17, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v11, v14, v21
	v_sub_nc_u32_e32 v18, v11, v12
	v_cmp_ge_u32_e32 vcc_lo, v11, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_cndmask_b32 v11, v11, v18 :: v_dual_add_nc_u32 v14, 1, v17
	v_cndmask_b32_e32 v14, v17, v14, vcc_lo
	v_ashrrev_i32_e32 v17, 31, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_ge_u32_e32 vcc_lo, v11, v12
	v_add_nc_u32_e32 v18, 1, v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v10, v10, v17
	v_cndmask_b32_e32 v11, v14, v18, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v10, v10, v17
	v_xor_b32_e32 v11, v11, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v12, v10, v13
	v_sub_nc_u32_e32 v11, v11, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v12, v12, v15
	v_ashrrev_i32_e32 v21, 31, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v11, v11, v21
	v_sub_nc_u32_e32 v10, v10, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v12, v11, v21
	v_sub_nc_u32_e32 v11, v10, v15
	v_cmp_ge_u32_e32 vcc_lo, v10, v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_hi_u32 v13, v12, v13
	v_cndmask_b32_e32 v10, v10, v11, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_sub_nc_u32_e32 v11, v10, v15
	v_cmp_ge_u32_e32 vcc_lo, v10, v15
	v_mul_lo_u32 v13, v13, v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v14, v10, v11, vcc_lo
	v_mad_u64_u32 v[10:11], null, v8, v4, v[1:2]
	v_sub_nc_u32_e32 v16, v12, v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v14, v14, v17
	v_mad_u64_u32 v[11:12], null, v10, v4, v[6:7]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_sub_nc_u32_e32 v22, v14, v17
	v_sub_nc_u32_e32 v10, v16, v15
	v_cmp_ge_u32_e32 vcc_lo, v16, v15
	v_mul_lo_u32 v17, v23, v4
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[12:13], null, v22, v4, v[8:9]
	v_mad_u64_u32 v[13:14], null, v11, s28, v[0:1]
	v_cndmask_b32_e32 v8, v16, v10, vcc_lo
	v_mad_u64_u32 v[10:11], null, v12, v4, v[6:7]
	s_delay_alu instid0(VALU_DEP_2)
	v_sub_nc_u32_e32 v6, v8, v15
	v_cmp_ge_u32_e32 vcc_lo, v8, v15
	v_ashrrev_i32_e32 v14, 31, v13
	v_mad_u64_u32 v[15:16], null, v17, v7, v[0:1]
	v_mad_u64_u32 v[17:18], null, v7, s28, v[0:1]
	v_cndmask_b32_e32 v6, v8, v6, vcc_lo
	v_mad_u64_u32 v[11:12], null, v10, v4, v[1:2]
	v_lshlrev_b64 v[12:13], 3, v[13:14]
	v_ashrrev_i32_e32 v16, 31, v15
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v6, v6, v21
	v_ashrrev_i32_e32 v18, 31, v17
	v_add_co_u32 v10, vcc_lo, s24, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v6, v6, v21
	v_mad_u64_u32 v[19:20], null, v11, s28, v[0:1]
	v_add_co_ci_u32_e32 v11, vcc_lo, s25, v13, vcc_lo
	v_mad_u64_u32 v[12:13], null, v6, v5, v[9:10]
	v_mad_u64_u32 v[13:14], null, v9, v5, v[6:7]
	global_load_b64 v[8:9], v[10:11], off
	v_ashrrev_i32_e32 v20, 31, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[10:11], 3, v[19:20]
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[19:20], null, v12, v5, v[7:8]
	v_mad_u64_u32 v[20:21], null, v13, v5, v[7:8]
	v_add_co_u32 v5, vcc_lo, s2, v10
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_ci_u32_e32 v6, vcc_lo, s3, v11, vcc_lo
	v_mad_u64_u32 v[10:11], null, v19, v4, v[1:2]
	s_delay_alu instid0(VALU_DEP_4)
	v_mad_u64_u32 v[11:12], null, v20, s28, v[0:1]
	global_load_b64 v[4:5], v[5:6], off
	v_lshlrev_b64 v[6:7], 3, v[15:16]
	v_lshlrev_b64 v[13:14], 3, v[17:18]
	v_mad_u64_u32 v[15:16], null, v22, s28, v[0:1]
	v_mad_u64_u32 v[17:18], null, v10, s28, v[0:1]
	v_ashrrev_i32_e32 v12, 31, v11
	v_add_co_u32 v6, vcc_lo, s26, v6
	v_add_co_ci_u32_e32 v7, vcc_lo, s27, v7, vcc_lo
	v_ashrrev_i32_e32 v16, 31, v15
	v_ashrrev_i32_e32 v18, 31, v17
	v_lshlrev_b64 v[10:11], 3, v[11:12]
	v_add_co_u32 v12, vcc_lo, s18, v13
	v_add_co_ci_u32_e32 v13, vcc_lo, s19, v14, vcc_lo
	v_lshlrev_b64 v[14:15], 3, v[15:16]
	v_lshlrev_b64 v[16:17], 3, v[17:18]
	v_add_nc_u32_e32 v18, v23, v0
	v_add_co_u32 v10, vcc_lo, s20, v10
	v_add_co_ci_u32_e32 v11, vcc_lo, s21, v11, vcc_lo
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_u32 v16, vcc_lo, s0, v16
	v_add_co_ci_u32_e32 v17, vcc_lo, s1, v17, vcc_lo
	v_add_co_u32 v14, vcc_lo, s18, v14
	v_add_co_ci_u32_e32 v15, vcc_lo, s19, v15, vcc_lo
	global_load_b64 v[6:7], v[6:7], off
	global_load_b64 v[12:13], v[12:13], off
	global_load_b64 v[10:11], v[10:11], off
	global_load_b64 v[16:17], v[16:17], off
	global_load_b64 v[14:15], v[14:15], off
	v_ashrrev_i32_e32 v19, 31, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[18:19], 3, v[18:19]
	v_add_co_u32 v18, vcc_lo, s22, v18
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v19, vcc_lo, s23, v19, vcc_lo
	v_add_co_u32 v20, vcc_lo, s12, v2
	v_add_co_ci_u32_e32 v21, vcc_lo, s13, v3, vcc_lo
	global_load_b64 v[18:19], v[18:19], off
	global_load_b32 v24, v[20:21], off
	v_add_co_u32 v20, vcc_lo, s6, v2
	v_add_co_ci_u32_e32 v21, vcc_lo, s7, v3, vcc_lo
	v_add_co_u32 v22, vcc_lo, s10, v2
	v_add_co_ci_u32_e32 v23, vcc_lo, s11, v3, vcc_lo
	v_add_co_u32 v1, vcc_lo, s8, v2
	v_add_co_ci_u32_e32 v2, vcc_lo, s9, v3, vcc_lo
	global_load_b32 v20, v[20:21], off
	global_load_b32 v21, v[22:23], off
	global_load_b32 v1, v[1:2], off
	s_waitcnt vmcnt(10)
	v_mul_f64 v[2:3], v[4:5], v[8:9]
	s_waitcnt vmcnt(8)
	v_mul_f64 v[4:5], v[6:7], v[12:13]
	s_waitcnt vmcnt(6)
	v_mul_f64 v[6:7], v[16:17], v[10:11]
	s_waitcnt vmcnt(5)
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_f64 v[2:3], v[2:3], v[14:15]
	s_waitcnt vmcnt(4)
	v_mul_f64 v[4:5], v[18:19], v[4:5]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[2:3], v[6:7], v[18:19], v[2:3]
	v_fma_f64 v[2:3], v[2:3], 2.0, v[4:5]
	s_waitcnt vmcnt(3)
	v_cvt_f64_f32_e32 v[4:5], v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_f64 v[2:3], v[2:3], v[4:5]
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[4:5], null, v21, v20, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[5:6], null, v4, s28, v[0:1]
	v_ashrrev_i32_e32 v6, 31, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 3, v[5:6]
	v_add_co_u32 v0, vcc_lo, s4, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
	global_store_b64 v[0:1], v[2:3], off
.LBB0_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel dimer_1min1pls_t4
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 376
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 25
		.amdhsa_next_free_sgpr 29
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	dimer_1min1pls_t4, .Lfunc_end0-dimer_1min1pls_t4
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 2184
; NumSgprs: 31
; NumVgprs: 25
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 3
; NumSGPRsForWavesPerEU: 31
; NumVGPRsForWavesPerEU: 25
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         48
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         56
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         64
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         72
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         80
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         88
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         96
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         104
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         112
        .size:           8
        .value_kind:     global_buffer
      - .offset:         120
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         124
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         128
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         132
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         134
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         136
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         138
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         140
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         142
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         160
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         168
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         176
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         184
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 376
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           dimer_1min1pls_t4
    .private_segment_fixed_size: 0
    .sgpr_count:     31
    .sgpr_spill_count: 0
    .symbol:         dimer_1min1pls_t4.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     25
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
