__global__ void DTW_Diag_Step(float* d0, float* d1, float* d2, float* csm0, float* csm1, float* csm2, float* X, float* Y, int dim, int diagLen, int* box, int reverse, int i, int debug, float* U, float* L, float* UL, float* S) {
    //Other local variables
    int i1, i2, j1, j2; // Endpoints of the diagonal
    int thisi, thisj; // Current indices on the diagonal
    // Optimal score and particular score for up/right/left
    float score, left, up, diag; 
    int idx = threadIdx.x + blockIdx.x*blockDim.x;
    int xi, yj;

    //Process each diagonal
    score = -1;
    if (idx < diagLen) {
        // Figure out indices in X and Y on diagonal
        int M = box[1] - box[0] + 1;
        int N = box[3] - box[2] + 1;
        i1 = i;
        j1 = 0;
        if (i >= M) {
            i1 = M-1;
            j1 = i - (M-1);
        }
        j2 = i;
        i2 = 0;
        if (j2 >= N) {
            j2 = N-1;
            i2 = i - (N-1);
        }
        thisi = i1 - idx;
        thisj = j1 + idx;
        
        if (thisi >= i2 && thisj <= j2) {
            xi = thisi;
            yj = thisj;
            if (reverse == 1) {
                xi = M-1-xi;
                yj = N-1-yj;
            }
            xi += box[0];
            yj += box[2];
            // Step 1: Update csm2
            csm2[idx] = 0.0;
            for (int d = 0; d < dim; d++) {
                float diff = X[xi*dim+d] - Y[yj*dim+d];
                csm2[idx] += diff*diff;
            }
            csm2[idx] = sqrt(csm2[idx]);
            

            // Step 2: Figure out the optimal cost
            if (thisi == 0 && thisj == 0) {
                score = 0;
                if (debug == -1) {
                    S[0] = 0;
                    U[0] = -1;
                    L[0] = -1;
                    UL[0] = -1;
                }
            }
            else {
                left = -1;
                up = -1;
                diag = -1;
                if (j1 == 0) {
                    if (idx > 0) {
                        left = d1[idx-1] + csm1[idx-1];
                    }
                    if (idx > 0 && thisi > 0) {
                        diag = d0[idx-1] + csm0[idx-1];
                    }
                    if (thisi > 0) {
                        up = d1[idx] + csm1[idx];
                    }
                }
                else if (i1 == M-1 && j1 == 1) {
                    left = d1[idx] + csm1[idx];
                    if (thisi > 0) {
                        diag = d0[idx] + csm0[idx];
                        up = d1[idx+1] + csm1[idx+1];
                    }
                }
                else if (i1 == M-1 && j1 > 1) {
                    left = d1[idx] + csm1[idx];
                    if (thisi > 0) {
                        diag = d0[idx+1] + csm0[idx+1];
                        up = d1[idx+1] + csm1[idx+1];
                    }
                }
                if (left > -1) {
                    score = left;
                }
                if (up > -1 && (up < score || score == -1)) {
                    score = up;
                }
                if (diag > -1 && (diag < score || score == -1)) {
                    score = diag;
                }
                if (debug == 1) {
                    U[thisi*N + thisj] = up;
                    L[thisi*N + thisj] = left;
                    UL[thisi*N + thisj] = diag;
                    S[thisi*N + thisj] = score;
                }
            }
        }
        d2[idx] = score;
    }
}

	.file	"tmpxft_00306b23_00000000-6_DTWGPU.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2010:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2010:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z62__device_stub__Z13DTW_Diag_StepPfS_S_S_S_S_S_S_iiPiiiiS_S_S_S_PfS_S_S_S_S_S_S_iiPiiiiS_S_S_S_
	.type	_Z62__device_stub__Z13DTW_Diag_StepPfS_S_S_S_S_S_S_iiPiiiiS_S_S_S_PfS_S_S_S_S_S_S_iiPiiiiS_S_S_S_, @function
_Z62__device_stub__Z13DTW_Diag_StepPfS_S_S_S_S_S_S_iiPiiiiS_S_S_S_PfS_S_S_S_S_S_S_iiPiiiiS_S_S_S_:
.LFB2032:
	.cfi_startproc
	endbr64
	subq	$344, %rsp
	.cfi_def_cfa_offset 352
	movq	352(%rsp), %rax
	movq	%rdi, 104(%rsp)
	leaq	136(%rsp), %rdi
	movq	%rsi, 96(%rsp)
	leaq	148(%rsp), %rsi
	movq	%rax, 56(%rsp)
	movq	360(%rsp), %rax
	movq	%rdx, 88(%rsp)
	leaq	120(%rsp), %rdx
	movq	%rax, 48(%rsp)
	movq	384(%rsp), %rax
	movq	%rcx, 80(%rsp)
	leaq	128(%rsp), %rcx
	movq	%rax, 40(%rsp)
	movq	416(%rsp), %rax
	movq	%r8, 72(%rsp)
	movq	%rax, 32(%rsp)
	movq	424(%rsp), %rax
	movq	%r9, 64(%rsp)
	movq	%rax, 24(%rsp)
	movq	432(%rsp), %rax
	movq	%rax, 16(%rsp)
	movq	440(%rsp), %rax
	movq	%rax, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 328(%rsp)
	xorl	%eax, %eax
	leaq	104(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	96(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	88(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	80(%rsp), %rax
	movq	%rax, 208(%rsp)
	leaq	72(%rsp), %rax
	movq	%rax, 216(%rsp)
	leaq	64(%rsp), %rax
	movq	%rax, 224(%rsp)
	leaq	56(%rsp), %rax
	movq	%rax, 232(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 240(%rsp)
	leaq	368(%rsp), %rax
	movq	%rax, 248(%rsp)
	leaq	376(%rsp), %rax
	movq	%rax, 256(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 264(%rsp)
	leaq	392(%rsp), %rax
	movq	%rax, 272(%rsp)
	leaq	400(%rsp), %rax
	movq	%rax, 280(%rsp)
	leaq	408(%rsp), %rax
	movq	%rax, 288(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 296(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 304(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 312(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 320(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 136(%rsp)
	movl	$1, 144(%rsp)
	movq	%rax, 148(%rsp)
	movl	$1, 156(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	128(%rsp)
	.cfi_def_cfa_offset 360
	leaq	_Z13DTW_Diag_StepPfS_S_S_S_S_S_S_iiPiiiiS_S_S_S_(%rip), %rdi
	pushq	128(%rsp)
	.cfi_def_cfa_offset 368
	movq	164(%rsp), %rcx
	movl	172(%rsp), %r8d
	movq	152(%rsp), %rsi
	movl	160(%rsp), %edx
	leaq	200(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 360
	popq	%rdx
	.cfi_def_cfa_offset 352
.L2:
	movq	328(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$344, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2032:
	.size	_Z62__device_stub__Z13DTW_Diag_StepPfS_S_S_S_S_S_S_iiPiiiiS_S_S_S_PfS_S_S_S_S_S_S_iiPiiiiS_S_S_S_, .-_Z62__device_stub__Z13DTW_Diag_StepPfS_S_S_S_S_S_S_iiPiiiiS_S_S_S_PfS_S_S_S_S_S_S_iiPiiiiS_S_S_S_
	.globl	_Z13DTW_Diag_StepPfS_S_S_S_S_S_S_iiPiiiiS_S_S_S_
	.type	_Z13DTW_Diag_StepPfS_S_S_S_S_S_S_iiPiiiiS_S_S_S_, @function
_Z13DTW_Diag_StepPfS_S_S_S_S_S_S_iiPiiiiS_S_S_S_:
.LFB2033:
	.cfi_startproc
	endbr64
	jmp	_Z62__device_stub__Z13DTW_Diag_StepPfS_S_S_S_S_S_S_iiPiiiiS_S_S_S_PfS_S_S_S_S_S_S_iiPiiiiS_S_S_S_
	.cfi_endproc
.LFE2033:
	.size	_Z13DTW_Diag_StepPfS_S_S_S_S_S_S_iiPiiiiS_S_S_S_, .-_Z13DTW_Diag_StepPfS_S_S_S_S_S_S_iiPiiiiS_S_S_S_
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z13DTW_Diag_StepPfS_S_S_S_S_S_S_iiPiiiiS_S_S_S_"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2035:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z13DTW_Diag_StepPfS_S_S_S_S_S_S_iiPiiiiS_S_S_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2035:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
__global__ void DTW_Diag_Step(float* d0, float* d1, float* d2, float* csm0, float* csm1, float* csm2, float* X, float* Y, int dim, int diagLen, int* box, int reverse, int i, int debug, float* U, float* L, float* UL, float* S) {
    //Other local variables
    int i1, i2, j1, j2; // Endpoints of the diagonal
    int thisi, thisj; // Current indices on the diagonal
    // Optimal score and particular score for up/right/left
    float score, left, up, diag; 
    int idx = threadIdx.x + blockIdx.x*blockDim.x;
    int xi, yj;

    //Process each diagonal
    score = -1;
    if (idx < diagLen) {
        // Figure out indices in X and Y on diagonal
        int M = box[1] - box[0] + 1;
        int N = box[3] - box[2] + 1;
        i1 = i;
        j1 = 0;
        if (i >= M) {
            i1 = M-1;
            j1 = i - (M-1);
        }
        j2 = i;
        i2 = 0;
        if (j2 >= N) {
            j2 = N-1;
            i2 = i - (N-1);
        }
        thisi = i1 - idx;
        thisj = j1 + idx;
        
        if (thisi >= i2 && thisj <= j2) {
            xi = thisi;
            yj = thisj;
            if (reverse == 1) {
                xi = M-1-xi;
                yj = N-1-yj;
            }
            xi += box[0];
            yj += box[2];
            // Step 1: Update csm2
            csm2[idx] = 0.0;
            for (int d = 0; d < dim; d++) {
                float diff = X[xi*dim+d] - Y[yj*dim+d];
                csm2[idx] += diff*diff;
            }
            csm2[idx] = sqrt(csm2[idx]);
            

            // Step 2: Figure out the optimal cost
            if (thisi == 0 && thisj == 0) {
                score = 0;
                if (debug == -1) {
                    S[0] = 0;
                    U[0] = -1;
                    L[0] = -1;
                    UL[0] = -1;
                }
            }
            else {
                left = -1;
                up = -1;
                diag = -1;
                if (j1 == 0) {
                    if (idx > 0) {
                        left = d1[idx-1] + csm1[idx-1];
                    }
                    if (idx > 0 && thisi > 0) {
                        diag = d0[idx-1] + csm0[idx-1];
                    }
                    if (thisi > 0) {
                        up = d1[idx] + csm1[idx];
                    }
                }
                else if (i1 == M-1 && j1 == 1) {
                    left = d1[idx] + csm1[idx];
                    if (thisi > 0) {
                        diag = d0[idx] + csm0[idx];
                        up = d1[idx+1] + csm1[idx+1];
                    }
                }
                else if (i1 == M-1 && j1 > 1) {
                    left = d1[idx] + csm1[idx];
                    if (thisi > 0) {
                        diag = d0[idx+1] + csm0[idx+1];
                        up = d1[idx+1] + csm1[idx+1];
                    }
                }
                if (left > -1) {
                    score = left;
                }
                if (up > -1 && (up < score || score == -1)) {
                    score = up;
                }
                if (diag > -1 && (diag < score || score == -1)) {
                    score = diag;
                }
                if (debug == 1) {
                    U[thisi*N + thisj] = up;
                    L[thisi*N + thisj] = left;
                    UL[thisi*N + thisj] = diag;
                    S[thisi*N + thisj] = score;
                }
            }
        }
        d2[idx] = score;
    }
}

	.text
	.file	"DTWGPU.hip"
	.globl	_Z28__device_stub__DTW_Diag_StepPfS_S_S_S_S_S_S_iiPiiiiS_S_S_S_ # -- Begin function _Z28__device_stub__DTW_Diag_StepPfS_S_S_S_S_S_S_iiPiiiiS_S_S_S_
	.type	_Z28__device_stub__DTW_Diag_StepPfS_S_S_S_S_S_S_iiPiiiiS_S_S_S_,@function
_Z28__device_stub__DTW_Diag_StepPfS_S_S_S_S_S_S_iiPiiiiS_S_S_S_: # @_Z28__device_stub__DTW_Diag_StepPfS_S_S_S_S_S_S_iiPiiiiS_S_S_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$240, %rsp
	.cfi_def_cfa_offset 288
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	288(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	296(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	304(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	312(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	320(%rsp), %rax
	movq	%rax, 80(%rbx)
	leaq	328(%rsp), %rax
	movq	%rax, 88(%rbx)
	leaq	336(%rsp), %rax
	movq	%rax, 96(%rbx)
	leaq	344(%rsp), %rax
	movq	%rax, 104(%rbx)
	leaq	352(%rsp), %rax
	movq	%rax, 112(%rbx)
	leaq	360(%rsp), %rax
	movq	%rax, 120(%rbx)
	leaq	368(%rsp), %rax
	movq	%rax, 128(%rbx)
	leaq	376(%rsp), %rax
	movq	%rax, 136(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z13DTW_Diag_StepPfS_S_S_S_S_S_S_iiPiiiiS_S_S_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$256, %rsp                      # imm = 0x100
	.cfi_adjust_cfa_offset -256
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z28__device_stub__DTW_Diag_StepPfS_S_S_S_S_S_S_iiPiiiiS_S_S_S_, .Lfunc_end0-_Z28__device_stub__DTW_Diag_StepPfS_S_S_S_S_S_S_iiPiiiiS_S_S_S_
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z13DTW_Diag_StepPfS_S_S_S_S_S_S_iiPiiiiS_S_S_S_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z13DTW_Diag_StepPfS_S_S_S_S_S_S_iiPiiiiS_S_S_S_,@object # @_Z13DTW_Diag_StepPfS_S_S_S_S_S_S_iiPiiiiS_S_S_S_
	.section	.rodata,"a",@progbits
	.globl	_Z13DTW_Diag_StepPfS_S_S_S_S_S_S_iiPiiiiS_S_S_S_
	.p2align	3, 0x0
_Z13DTW_Diag_StepPfS_S_S_S_S_S_S_iiPiiiiS_S_S_S_:
	.quad	_Z28__device_stub__DTW_Diag_StepPfS_S_S_S_S_S_S_iiPiiiiS_S_S_S_
	.size	_Z13DTW_Diag_StepPfS_S_S_S_S_S_S_iiPiiiiS_S_S_S_, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z13DTW_Diag_StepPfS_S_S_S_S_S_S_iiPiiiiS_S_S_S_"
	.size	.L__unnamed_1, 49

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z28__device_stub__DTW_Diag_StepPfS_S_S_S_S_S_S_iiPiiiiS_S_S_S_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z13DTW_Diag_StepPfS_S_S_S_S_S_S_iiPiiiiS_S_S_S_
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z13DTW_Diag_StepPfS_S_S_S_S_S_S_iiPiiiiS_S_S_S_ ; -- Begin function _Z13DTW_Diag_StepPfS_S_S_S_S_S_S_iiPiiiiS_S_S_S_
	.globl	_Z13DTW_Diag_StepPfS_S_S_S_S_S_S_iiPiiiiS_S_S_S_
	.p2align	8
	.type	_Z13DTW_Diag_StepPfS_S_S_S_S_S_S_iiPiiiiS_S_S_S_,@function
_Z13DTW_Diag_StepPfS_S_S_S_S_S_S_iiPiiiiS_S_S_S_: ; @_Z13DTW_Diag_StepPfS_S_S_S_S_S_S_iiPiiiiS_S_S_S_
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x8c
	s_load_b64 s[28:29], s[0:1], 0x40
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[2:3], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_i32_e64 s29, v2
	s_cbranch_execz .LBB0_40
; %bb.1:
	s_clause 0x1
	s_load_b64 s[2:3], s[0:1], 0x48
	s_load_b128 s[24:27], s[0:1], 0x50
	v_ashrrev_i32_e32 v3, 31, v2
	s_waitcnt lgkmcnt(0)
	s_load_b128 s[20:23], s[2:3], 0x0
	s_load_b512 s[4:19], s[0:1], 0x0
	s_delay_alu instid0(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[2:3]
	v_mov_b32_e32 v3, -1.0
	s_waitcnt lgkmcnt(0)
	s_sub_i32 s30, s21, s20
	s_sub_i32 s27, s23, s22
	s_sub_i32 s2, s25, s30
	s_cmp_gt_i32 s25, s30
	s_cselect_b32 s29, s2, 0
	s_min_i32 s31, s30, s25
	s_sub_i32 s2, s25, s27
	s_min_i32 s3, s27, s25
	v_sub_nc_u32_e32 v11, s31, v2
	v_add_nc_u32_e32 v12, s29, v2
	s_cmp_gt_i32 s25, s27
	s_cselect_b32 s2, s2, 0
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	v_cmp_le_i32_e32 vcc_lo, s2, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_ge_i32_e64 s2, s3, v12
	s_and_b32 s2, vcc_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_39
; %bb.2:
	v_add_co_u32 v3, vcc_lo, s14, v0
	v_add_co_ci_u32_e32 v4, vcc_lo, s15, v1, vcc_lo
	v_mov_b32_e32 v9, 0
	s_cmp_lt_i32 s28, 1
	global_store_b32 v[3:4], v9, off
	s_cbranch_scc1 .LBB0_5
; %bb.3:                                ; %.lr.ph
	v_sub_nc_u32_e32 v5, s27, v12
	s_cmp_eq_u32 s24, 1
	v_sub_nc_u32_e32 v6, s30, v11
	s_cselect_b32 vcc_lo, -1, 0
	v_mov_b32_e32 v9, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_cndmask_b32 v5, v12, v5 :: v_dual_cndmask_b32 v6, v11, v6
	v_add_nc_u32_e32 v5, s22, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v6, s20, v6
	v_mul_lo_u32 v5, v5, s28
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v7, v6, s28
	v_ashrrev_i32_e32 v6, 31, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v8, 31, v7
	v_lshlrev_b64 v[5:6], 2, v[5:6]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[7:8], 2, v[7:8]
	v_add_co_u32 v5, vcc_lo, s18, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v6, vcc_lo, s19, v6, vcc_lo
	v_add_co_u32 v7, vcc_lo, s16, v7
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v8, vcc_lo, s17, v8, vcc_lo
.LBB0_4:                                ; =>This Inner Loop Header: Depth=1
	global_load_b32 v10, v[7:8], off
	global_load_b32 v13, v[5:6], off
	v_add_co_u32 v5, vcc_lo, v5, 4
	v_add_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
	v_add_co_u32 v7, vcc_lo, v7, 4
	v_add_co_ci_u32_e32 v8, vcc_lo, 0, v8, vcc_lo
	s_add_i32 s28, s28, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	s_cmp_eq_u32 s28, 0
	s_waitcnt vmcnt(0)
	v_sub_f32_e32 v10, v10, v13
	v_fmac_f32_e32 v9, v10, v10
	global_store_b32 v[3:4], v9, off
	s_cbranch_scc0 .LBB0_4
.LBB0_5:                                ; %Flow272
	v_mul_f32_e32 v5, 0x4f800000, v9
	v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v9
	s_load_b256 s[16:23], s[0:1], 0x60
	v_cmp_ne_u32_e64 s0, 0, v12
	s_mov_b32 s15, -1
	v_cndmask_b32_e32 v5, v9, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_sqrt_f32_e32 v6, v5
	s_waitcnt_depctr 0xfff
	v_add_nc_u32_e32 v7, -1, v6
	v_add_nc_u32_e32 v8, 1, v6
	v_fma_f32 v9, -v7, v6, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v10, -v8, v6, v5
	v_cmp_ge_f32_e64 s2, 0, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v6, v6, v7, s2
	v_cmp_lt_f32_e64 s2, 0, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v6, v6, v8, s2
	v_mul_f32_e32 v7, 0x37800000, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v6, v6, v7, vcc_lo
	v_cmp_class_f32_e64 s1, v5, 0x260
	v_cmp_ne_u32_e32 vcc_lo, s31, v2
	v_cndmask_b32_e64 v5, v6, v5, s1
	s_mov_b32 s1, 0
	s_or_b32 s0, vcc_lo, s0
	global_store_b32 v[3:4], v5, off
                                        ; implicit-def: $vgpr3
	s_and_saveexec_b32 s2, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s2, exec_lo, s2
	s_cbranch_execz .LBB0_34
; %bb.6:
	s_cmp_lg_u32 s29, 0
	s_mov_b32 s0, 0
	s_cbranch_scc0 .LBB0_12
; %bb.7:
	s_cmp_ge_i32 s25, s30
	s_cselect_b32 s1, -1, 0
	s_cmp_eq_u32 s29, 1
	s_cselect_b32 s14, -1, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s14, s1, s14
	s_and_not1_b32 vcc_lo, exec_lo, s14
	s_cbranch_vccz .LBB0_13
; %bb.8:
	s_cmp_gt_i32 s29, 1
	s_cselect_b32 s0, -1, 0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s0, s1, s0
	s_mov_b32 s1, 0
	s_and_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccz .LBB0_14
; %bb.9:
	v_add_co_u32 v7, vcc_lo, s6, v0
	v_add_co_ci_u32_e32 v8, vcc_lo, s7, v1, vcc_lo
	v_add_co_u32 v9, vcc_lo, s12, v0
	v_add_co_ci_u32_e32 v10, vcc_lo, s13, v1, vcc_lo
	s_mov_b32 s0, 0
	global_load_b32 v3, v[7:8], off
	global_load_b32 v4, v[9:10], off
	s_mov_b32 s14, exec_lo
                                        ; implicit-def: $vgpr14
                                        ; implicit-def: $vgpr5_vgpr6
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v13, v3, v4
                                        ; implicit-def: $vgpr3_vgpr4
	v_cmpx_lt_i32_e32 0, v11
	s_xor_b32 s14, exec_lo, s14
	s_cbranch_execz .LBB0_11
; %bb.10:
	v_add_co_u32 v3, vcc_lo, s4, v0
	v_add_co_ci_u32_e32 v4, vcc_lo, s5, v1, vcc_lo
	v_add_co_u32 v5, vcc_lo, s10, v0
	v_add_co_ci_u32_e32 v6, vcc_lo, s11, v1, vcc_lo
	s_mov_b32 s0, exec_lo
	global_load_b32 v14, v[3:4], off offset:4
	global_load_b32 v5, v[5:6], off offset:4
	v_add_co_u32 v3, vcc_lo, v7, 4
	v_add_co_ci_u32_e32 v4, vcc_lo, 0, v8, vcc_lo
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v14, v14, v5
	v_add_co_u32 v5, vcc_lo, v9, 4
	v_add_co_ci_u32_e32 v6, vcc_lo, 0, v10, vcc_lo
.LBB0_11:                               ; %Flow263
	s_or_b32 exec_lo, exec_lo, s14
	s_branch .LBB0_15
.LBB0_12:
                                        ; implicit-def: $vgpr14
                                        ; implicit-def: $vgpr13
                                        ; implicit-def: $vgpr3_vgpr4
                                        ; implicit-def: $vgpr5_vgpr6
                                        ; implicit-def: $sgpr14
	s_branch .LBB0_21
.LBB0_13:
	s_mov_b32 s1, -1
                                        ; implicit-def: $vgpr14
                                        ; implicit-def: $vgpr13
                                        ; implicit-def: $vgpr3_vgpr4
                                        ; implicit-def: $vgpr5_vgpr6
                                        ; implicit-def: $sgpr14
	s_branch .LBB0_16
.LBB0_14:
	v_mov_b32_e32 v13, -1.0
	s_mov_b32 s0, 0
                                        ; implicit-def: $vgpr14
                                        ; implicit-def: $vgpr3_vgpr4
                                        ; implicit-def: $vgpr5_vgpr6
.LBB0_15:                               ; %Flow262
	s_mov_b32 s14, -1.0
.LBB0_16:                               ; %Flow261
	s_and_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccz .LBB0_20
; %bb.17:
	v_add_co_u32 v7, vcc_lo, s6, v0
	v_add_co_ci_u32_e32 v8, vcc_lo, s7, v1, vcc_lo
	v_add_co_u32 v9, vcc_lo, s12, v0
	v_add_co_ci_u32_e32 v10, vcc_lo, s13, v1, vcc_lo
	s_mov_b32 s1, exec_lo
	global_load_b32 v3, v[7:8], off
	global_load_b32 v4, v[9:10], off
                                        ; implicit-def: $vgpr14
                                        ; implicit-def: $vgpr5_vgpr6
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v13, v3, v4
                                        ; implicit-def: $vgpr3_vgpr4
	v_cmpx_lt_i32_e32 0, v11
	s_xor_b32 s1, exec_lo, s1
	s_cbranch_execz .LBB0_19
; %bb.18:
	v_add_co_u32 v3, vcc_lo, s4, v0
	v_add_co_ci_u32_e32 v4, vcc_lo, s5, v1, vcc_lo
	v_add_co_u32 v5, vcc_lo, s10, v0
	v_add_co_ci_u32_e32 v6, vcc_lo, s11, v1, vcc_lo
	s_or_b32 s0, s0, exec_lo
	global_load_b32 v14, v[3:4], off
	global_load_b32 v5, v[5:6], off
	v_add_co_u32 v3, vcc_lo, v7, 4
	v_add_co_ci_u32_e32 v4, vcc_lo, 0, v8, vcc_lo
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v14, v14, v5
	v_add_co_u32 v5, vcc_lo, v9, 4
	v_add_co_ci_u32_e32 v6, vcc_lo, 0, v10, vcc_lo
.LBB0_19:                               ; %Flow265
	s_or_b32 exec_lo, exec_lo, s1
	s_mov_b32 s14, -1.0
.LBB0_20:                               ; %Flow264
	s_mov_b32 s15, 0
	s_mov_b32 s1, s0
.LBB0_21:                               ; %Flow260
	s_and_b32 vcc_lo, exec_lo, s15
	s_cbranch_vccz .LBB0_29
; %bb.22:
	v_cmp_lt_i32_e64 s0, 0, v2
	v_dual_mov_b32 v14, -1.0 :: v_dual_mov_b32 v13, -1.0
	v_add_nc_u32_e32 v2, -1, v2
	s_delay_alu instid0(VALU_DEP_3)
	s_and_saveexec_b32 s14, s0
	s_cbranch_execz .LBB0_24
; %bb.23:
	v_mov_b32_e32 v3, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[2:3]
	v_add_co_u32 v5, vcc_lo, s6, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v6, vcc_lo, s7, v4, vcc_lo
	v_add_co_u32 v3, vcc_lo, s12, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s13, v4, vcc_lo
	global_load_b32 v5, v[5:6], off
	global_load_b32 v3, v[3:4], off
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v13, v5, v3
.LBB0_24:
	s_or_b32 exec_lo, exec_lo, s14
	v_cmp_lt_i32_e32 vcc_lo, 0, v11
	s_and_b32 s0, s0, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s14, s0
	s_cbranch_execz .LBB0_26
; %bb.25:
	v_mov_b32_e32 v3, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	v_add_co_u32 v4, s0, s4, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e64 v5, s0, s5, v3, s0
	v_add_co_u32 v2, s0, s10, v2
	v_add_co_ci_u32_e64 v3, s0, s11, v3, s0
	global_load_b32 v4, v[4:5], off
	global_load_b32 v2, v[2:3], off
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v14, v4, v2
.LBB0_26:
	s_or_b32 exec_lo, exec_lo, s14
                                        ; implicit-def: $vgpr3_vgpr4
                                        ; implicit-def: $vgpr5_vgpr6
	s_and_saveexec_b32 s0, vcc_lo
; %bb.27:
	v_add_co_u32 v5, vcc_lo, s12, v0
	v_add_co_ci_u32_e32 v6, vcc_lo, s13, v1, vcc_lo
	v_add_co_u32 v3, vcc_lo, s6, v0
	v_add_co_ci_u32_e32 v4, vcc_lo, s7, v1, vcc_lo
	s_or_b32 s1, s1, exec_lo
; %bb.28:                               ; %Flow267
	s_or_b32 exec_lo, exec_lo, s0
	v_mov_b32_e32 v7, v14
	s_mov_b32 s14, -1.0
	s_branch .LBB0_30
.LBB0_29:
	v_mov_b32_e32 v7, s14
.LBB0_30:                               ; %Flow266
	v_mov_b32_e32 v2, s14
	s_and_saveexec_b32 s0, s1
	s_cbranch_execz .LBB0_32
; %bb.31:                               ; %.sink.split
	global_load_b32 v2, v[3:4], off
	global_load_b32 v3, v[5:6], off
	v_mov_b32_e32 v7, v14
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v2, v2, v3
.LBB0_32:
	s_or_b32 exec_lo, exec_lo, s0
	v_max_f32_e32 v3, v13, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_lt_f32_e64 s1, -1.0, v2
	v_max_f32_e32 v3, -1.0, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_lt_f32_e32 vcc_lo, v2, v3
	v_cmp_eq_f32_e64 s0, -1.0, v3
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	s_and_b32 vcc_lo, s1, s0
	v_cmp_lt_f32_e64 s1, -1.0, v7
	v_cndmask_b32_e32 v3, v3, v2, vcc_lo
	v_cmp_lt_f32_e32 vcc_lo, v7, v3
	v_cmp_eq_f32_e64 s0, -1.0, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s0, vcc_lo, s0
	s_and_b32 vcc_lo, s1, s0
	s_cmp_lg_u32 s26, 1
	v_cndmask_b32_e32 v3, v3, v7, vcc_lo
	s_cbranch_scc1 .LBB0_34
; %bb.33:
	v_mul_lo_u32 v4, v11, s27
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v4, v4, v11, v12
	v_ashrrev_i32_e32 v5, 31, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v8, vcc_lo, s16, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v9, vcc_lo, s17, v5, vcc_lo
	v_add_co_u32 v10, vcc_lo, s18, v4
	v_add_co_ci_u32_e32 v11, vcc_lo, s19, v5, vcc_lo
	v_add_co_u32 v14, vcc_lo, s20, v4
	v_add_co_ci_u32_e32 v15, vcc_lo, s21, v5, vcc_lo
	v_add_co_u32 v4, vcc_lo, s22, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s23, v5, vcc_lo
	global_store_b32 v[8:9], v2, off
	global_store_b32 v[10:11], v13, off
	global_store_b32 v[14:15], v7, off
	global_store_b32 v[4:5], v3, off
.LBB0_34:                               ; %Flow269
	s_and_not1_saveexec_b32 s0, s2
	s_cbranch_execz .LBB0_38
; %bb.35:
	s_cmp_lg_u32 s26, -1
	s_cbranch_scc1 .LBB0_37
; %bb.36:
	v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v3, -1.0
	s_waitcnt lgkmcnt(0)
	s_clause 0x3
	global_store_b32 v2, v2, s[22:23]
	global_store_b32 v2, v3, s[16:17]
	global_store_b32 v2, v3, s[18:19]
	global_store_b32 v2, v3, s[20:21]
.LBB0_37:                               ; %Flow268
	v_mov_b32_e32 v3, 0
.LBB0_38:                               ; %Flow270
	s_or_b32 exec_lo, exec_lo, s0
.LBB0_39:                               ; %Flow273
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s3
	v_add_co_u32 v0, vcc_lo, s8, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s9, v1, vcc_lo
	global_store_b32 v[0:1], v3, off
.LBB0_40:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z13DTW_Diag_StepPfS_S_S_S_S_S_S_iiPiiiiS_S_S_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 384
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 16
		.amdhsa_next_free_sgpr 32
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z13DTW_Diag_StepPfS_S_S_S_S_S_S_iiPiiiiS_S_S_S_, .Lfunc_end0-_Z13DTW_Diag_StepPfS_S_S_S_S_S_S_iiPiiiiS_S_S_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1688
; NumSgprs: 34
; NumVgprs: 16
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 4
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 34
; NumVGPRsForWavesPerEU: 16
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         48
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         56
        .size:           8
        .value_kind:     global_buffer
      - .offset:         64
        .size:           4
        .value_kind:     by_value
      - .offset:         68
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         72
        .size:           8
        .value_kind:     global_buffer
      - .offset:         80
        .size:           4
        .value_kind:     by_value
      - .offset:         84
        .size:           4
        .value_kind:     by_value
      - .offset:         88
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         96
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         104
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         112
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         120
        .size:           8
        .value_kind:     global_buffer
      - .offset:         128
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         132
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         136
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         140
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         142
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         144
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         146
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         148
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         150
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         168
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         176
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         184
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         192
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 384
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z13DTW_Diag_StepPfS_S_S_S_S_S_S_iiPiiiiS_S_S_S_
    .private_segment_fixed_size: 0
    .sgpr_count:     34
    .sgpr_spill_count: 0
    .symbol:         _Z13DTW_Diag_StepPfS_S_S_S_S_S_S_iiPiiiiS_S_S_S_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     16
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
