/* 
 * purpose:      just a demo to show how matrix addition can be done on 
 *               the GPU "the standard way" ie using as many thread blocks
 *               as needed to cover the considered dimension N x N 
 *               n.b. N=256 was set on purpose to evenly divide by the
 *                    number of x/y-threads, ie 16, without any remainder,
 *                    so don't have to worry about these details at this point 
 * compilation:  nvcc ./multiple_thread_blocks_matrix_addition.cu
 * usage:        ./a.out
 */ 

#include <stdio.h>

#define   N 256


/* 
 * GPU kernel 
 */
__global__ void MatAdd(float **A, float **B, float **C)
{
    int i, j;

    i = (blockIdx.x * blockDim.x) + threadIdx.x;
    j = (blockIdx.y * blockDim.y) + threadIdx.y;
    C[i][j] = A[i][j] + B[i][j];
}




/* 
 * host main  
 */
int main()
{
    int i, j;
    dim3 threadsPerBlock, numBlocks;  
    float **A, **B, **C;

   /* 
    * using CUDA unified memory, first allocate 
    * the memory in convenient 2D format, then 
    * initialize with some dummy content        
    */
    cudaMallocManaged(&A, N * sizeof(float *));
    cudaMallocManaged(&B, N * sizeof(float *));
    cudaMallocManaged(&C, N * sizeof(float *));
    for (i = 0; i < N; i++) {
        cudaMallocManaged(&A[i], N * sizeof(float));
        cudaMallocManaged(&B[i], N * sizeof(float));
        cudaMallocManaged(&C[i], N * sizeof(float));
        for (j = 0; j < N; j++) {
            A[i][j] = (float) ((i * N) + j);
            B[i][j] = (float) N  - A[i][j];
            C[i][j] = (float) 0;
        }
    }

   /* set up GPU kernel execution configuration */
    threadsPerBlock.x = 16;
    threadsPerBlock.y = 16;
    numBlocks.x = N / threadsPerBlock.x;
    numBlocks.y = N / threadsPerBlock.y;
   
   /* launch the GPU kernel */
    MatAdd<<<numBlocks, threadsPerBlock>>>(A, B, C);  
    cudaDeviceSynchronize();
 
   /* print result */
    for (i = 0; i < N; i++) {
        for (j = 0; j < N; j++) {
            printf("%d %d %f\n", i, j, C[i][j]);
        }
    }
   
   /* make clean */
    for (i = 0; i < N; i++) {
        cudaFree(C[i]);
        cudaFree(B[i]);
        cudaFree(A[i]);
    }
    cudaFree(C);
    cudaFree(B);
    cudaFree(A);


    return(0);
}

	.file	"tmpxft_0029a186_00000000-6_multiple_thread_blocks_matrix_addition.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2030:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z32__device_stub__Z6MatAddPPfS0_S0_PPfS0_S0_
	.type	_Z32__device_stub__Z6MatAddPPfS0_S0_PPfS0_S0_, @function
_Z32__device_stub__Z6MatAddPPfS0_S0_PPfS0_S0_:
.LFB2052:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z6MatAddPPfS0_S0_(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L2:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2052:
	.size	_Z32__device_stub__Z6MatAddPPfS0_S0_PPfS0_S0_, .-_Z32__device_stub__Z6MatAddPPfS0_S0_PPfS0_S0_
	.globl	_Z6MatAddPPfS0_S0_
	.type	_Z6MatAddPPfS0_S0_, @function
_Z6MatAddPPfS0_S0_:
.LFB2053:
	.cfi_startproc
	endbr64
	jmp	_Z32__device_stub__Z6MatAddPPfS0_S0_PPfS0_S0_
	.cfi_endproc
.LFE2053:
	.size	_Z6MatAddPPfS0_S0_, .-_Z6MatAddPPfS0_S0_
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC2:
	.string	"%d %d %f\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%r14
	.cfi_def_cfa_offset 16
	.cfi_offset 14, -16
	movl	$1, %edx
	movl	$2048, %esi
	pushq	%r13
	.cfi_def_cfa_offset 24
	.cfi_offset 13, -24
	pushq	%r12
	.cfi_def_cfa_offset 32
	.cfi_offset 12, -32
	pushq	%rbp
	.cfi_def_cfa_offset 40
	.cfi_offset 6, -40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	.cfi_offset 3, -48
	xorl	%ebx, %ebx
	subq	$64, %rsp
	.cfi_def_cfa_offset 112
	movq	%fs:40, %rax
	movq	%rax, 56(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rdi
	movl	$1, 40(%rsp)
	movl	$1, 52(%rsp)
	call	cudaMallocManaged@PLT
	leaq	16(%rsp), %rdi
	movl	$1, %edx
	movl	$2048, %esi
	call	cudaMallocManaged@PLT
	leaq	24(%rsp), %rdi
	movl	$1, %edx
	movl	$2048, %esi
	call	cudaMallocManaged@PLT
.L10:
	movq	8(%rsp), %rdi
	movl	$1, %edx
	movl	$1024, %esi
	addq	%rbx, %rdi
	call	cudaMallocManaged@PLT
	movq	16(%rsp), %rdi
	movl	$1, %edx
	movl	$1024, %esi
	addq	%rbx, %rdi
	call	cudaMallocManaged@PLT
	movq	24(%rsp), %rdi
	movl	$1, %edx
	movl	$1024, %esi
	addq	%rbx, %rdi
	call	cudaMallocManaged@PLT
	movq	8(%rsp), %rax
	movl	%ebx, %r8d
	sall	$5, %r8d
	movq	(%rax,%rbx), %rsi
	movq	16(%rsp), %rax
	movq	(%rax,%rbx), %rcx
	movq	24(%rsp), %rax
	movq	(%rax,%rbx), %rdx
	xorl	%eax, %eax
.L9:
	leal	(%r8,%rax), %edi
	movss	.LC0(%rip), %xmm1
	cvtsi2ssl	%edi, %xmm0
	subss	%xmm0, %xmm1
	movss	%xmm0, (%rsi,%rax,4)
	movss	%xmm1, (%rcx,%rax,4)
	movl	$0x00000000, (%rdx,%rax,4)
	incq	%rax
	cmpq	$256, %rax
	jne	.L9
	addq	$8, %rbx
	cmpq	$2048, %rbx
	jne	.L10
	movl	40(%rsp), %ecx
	movl	52(%rsp), %esi
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movabsq	$68719476752, %rdi
	movq	%rdi, %rdx
	movq	%rdi, 44(%rsp)
	movq	%rdi, 32(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L11
	movq	24(%rsp), %rdx
	movq	16(%rsp), %rsi
	movq	8(%rsp), %rdi
	call	_Z32__device_stub__Z6MatAddPPfS0_S0_PPfS0_S0_
.L11:
	call	cudaDeviceSynchronize@PLT
	xorl	%ebp, %ebp
	leaq	.LC2(%rip), %r14
.L12:
	movl	%ebp, %r13d
	leaq	0(,%rbp,8), %r12
	xorl	%ebx, %ebx
.L13:
	movq	24(%rsp), %rax
	movl	%ebx, %ecx
	movl	%r13d, %edx
	movq	%r14, %rsi
	movl	$2, %edi
	movq	(%rax,%r12), %rax
	cvtss2sd	(%rax,%rbx,4), %xmm0
	movb	$1, %al
	incq	%rbx
	call	__printf_chk@PLT
	cmpq	$256, %rbx
	jne	.L13
	incq	%rbp
	cmpq	$256, %rbp
	jne	.L12
	xorl	%ebx, %ebx
.L14:
	movq	24(%rsp), %rax
	movq	(%rax,%rbx), %rdi
	call	cudaFree@PLT
	movq	16(%rsp), %rax
	movq	(%rax,%rbx), %rdi
	call	cudaFree@PLT
	movq	8(%rsp), %rax
	movq	(%rax,%rbx), %rdi
	addq	$8, %rbx
	call	cudaFree@PLT
	cmpq	$2048, %rbx
	jne	.L14
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	movq	16(%rsp), %rdi
	call	cudaFree@PLT
	movq	8(%rsp), %rdi
	call	cudaFree@PLT
	movq	56(%rsp), %rax
	subq	%fs:40, %rax
	je	.L15
	call	__stack_chk_fail@PLT
.L15:
	addq	$64, %rsp
	.cfi_def_cfa_offset 48
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%rbp
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r13
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2027:
	.size	main, .-main
	.section	.rodata.str1.1
.LC3:
	.string	"_Z6MatAddPPfS0_S0_"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC3(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z6MatAddPPfS0_S0_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2055:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst4,"aM",@progbits,4
	.align 4
.LC0:
	.long	1132462080
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

/* 
 * purpose:      just a demo to show how matrix addition can be done on 
 *               the GPU "the standard way" ie using as many thread blocks
 *               as needed to cover the considered dimension N x N 
 *               n.b. N=256 was set on purpose to evenly divide by the
 *                    number of x/y-threads, ie 16, without any remainder,
 *                    so don't have to worry about these details at this point 
 * compilation:  nvcc ./multiple_thread_blocks_matrix_addition.cu
 * usage:        ./a.out
 */ 


#include <hip/hip_runtime.h>
#include <stdio.h>

#define   N 256


/* 
 * GPU kernel 
 */
__global__ void MatAdd(float **A, float **B, float **C)
{
    int i, j;

    i = (blockIdx.x * blockDim.x) + threadIdx.x;
    j = (blockIdx.y * blockDim.y) + threadIdx.y;
    C[i][j] = A[i][j] + B[i][j];
}




/* 
 * host main  
 */
int main()
{
    int i, j;
    dim3 threadsPerBlock, numBlocks;  
    float **A, **B, **C;

   /* 
    * using CUDA unified memory, first allocate 
    * the memory in convenient 2D format, then 
    * initialize with some dummy content        
    */
    hipMallocManaged(&A, N * sizeof(float *));
    hipMallocManaged(&B, N * sizeof(float *));
    hipMallocManaged(&C, N * sizeof(float *));
    for (i = 0; i < N; i++) {
        hipMallocManaged(&A[i], N * sizeof(float));
        hipMallocManaged(&B[i], N * sizeof(float));
        hipMallocManaged(&C[i], N * sizeof(float));
        for (j = 0; j < N; j++) {
            A[i][j] = (float) ((i * N) + j);
            B[i][j] = (float) N  - A[i][j];
            C[i][j] = (float) 0;
        }
    }

   /* set up GPU kernel execution configuration */
    threadsPerBlock.x = 16;
    threadsPerBlock.y = 16;
    numBlocks.x = N / threadsPerBlock.x;
    numBlocks.y = N / threadsPerBlock.y;
   
   /* launch the GPU kernel */
    MatAdd<<<numBlocks, threadsPerBlock>>>(A, B, C);  
    hipDeviceSynchronize();
 
   /* print result */
    for (i = 0; i < N; i++) {
        for (j = 0; j < N; j++) {
            printf("%d %d %f\n", i, j, C[i][j]);
        }
    }
   
   /* make clean */
    for (i = 0; i < N; i++) {
        hipFree(C[i]);
        hipFree(B[i]);
        hipFree(A[i]);
    }
    hipFree(C);
    hipFree(B);
    hipFree(A);


    return(0);
}

	.text
	.file	"multiple_thread_blocks_matrix_addition.hip"
	.globl	_Z21__device_stub__MatAddPPfS0_S0_ # -- Begin function _Z21__device_stub__MatAddPPfS0_S0_
	.type	_Z21__device_stub__MatAddPPfS0_S0_,@function
_Z21__device_stub__MatAddPPfS0_S0_:     # @_Z21__device_stub__MatAddPPfS0_S0_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z6MatAddPPfS0_S0_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z21__device_stub__MatAddPPfS0_S0_, .Lfunc_end0-_Z21__device_stub__MatAddPPfS0_S0_
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0                          # -- Begin function main
.LCPI1_0:
	.long	0x43800000                      # float 256
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r12
	.cfi_def_cfa_offset 32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	subq	$24, %rsp
	.cfi_def_cfa_offset 64
	.cfi_offset %rbx, -40
	.cfi_offset %r12, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	16(%rsp), %rbx
	movl	$2048, %esi                     # imm = 0x800
	movq	%rbx, %rdi
	movl	$1, %edx
	callq	hipMallocManaged
	leaq	8(%rsp), %rdi
	movl	$2048, %esi                     # imm = 0x800
	movl	$1, %edx
	callq	hipMallocManaged
	movq	%rsp, %rdi
	movl	$2048, %esi                     # imm = 0x800
	movl	$1, %edx
	callq	hipMallocManaged
	xorl	%r14d, %r14d
	movq	(%rbx), %rax
	movl	$256, %r15d                     # imm = 0x100
	xorl	%r12d, %r12d
.LBB1_1:                                # =>This Loop Header: Depth=1
                                        #     Child Loop BB1_2 Depth 2
	leaq	(%rax,%r12,8), %rdi
	leaq	(,%r12,8), %rbx
	movl	$1024, %esi                     # imm = 0x400
	movl	$1, %edx
	callq	hipMallocManaged
	movq	8(%rsp), %rdi
	addq	%rbx, %rdi
	movl	$1024, %esi                     # imm = 0x400
	movl	$1, %edx
	callq	hipMallocManaged
	addq	(%rsp), %rbx
	movl	$1024, %esi                     # imm = 0x400
	movq	%rbx, %rdi
	movl	$1, %edx
	callq	hipMallocManaged
	movss	.LCPI1_0(%rip), %xmm2           # xmm2 = mem[0],zero,zero,zero
	movq	16(%rsp), %rax
	movq	(%rax,%r12,8), %rcx
	movq	8(%rsp), %rdx
	movq	(%rdx,%r12,8), %rdx
	movq	(%rsp), %rsi
	movq	(%rsi,%r12,8), %rsi
	xorl	%edi, %edi
.LBB1_2:                                #   Parent Loop BB1_1 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	leal	(%r14,%rdi), %r8d
	xorps	%xmm0, %xmm0
	cvtsi2ss	%r8d, %xmm0
	movss	%xmm0, (%rcx,%rdi,4)
	movaps	%xmm2, %xmm1
	subss	%xmm0, %xmm1
	movss	%xmm1, (%rdx,%rdi,4)
	movl	$0, (%rsi,%rdi,4)
	incq	%rdi
	cmpq	$256, %rdi                      # imm = 0x100
	jne	.LBB1_2
# %bb.3:                                #   in Loop: Header=BB1_1 Depth=1
	incq	%r12
	addq	%r15, %r14
	cmpq	%r15, %r12
	jne	.LBB1_1
# %bb.4:
	movabsq	$68719476752, %rdi              # imm = 0x1000000010
	movl	$1, %esi
	movq	%rdi, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_6
# %bb.5:
	movq	16(%rsp), %rdi
	movq	8(%rsp), %rsi
	movq	(%rsp), %rdx
	callq	_Z21__device_stub__MatAddPPfS0_S0_
.LBB1_6:
	callq	hipDeviceSynchronize
	xorl	%ebx, %ebx
.LBB1_7:                                # %.preheader52
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB1_8 Depth 2
	xorl	%r14d, %r14d
.LBB1_8:                                #   Parent Loop BB1_7 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movq	(%rsp), %rax
	movq	(%rax,%rbx,8), %rax
	xorps	%xmm0, %xmm0
	cvtss2sd	(%rax,%r14,4), %xmm0
	movl	$.L.str, %edi
	movl	%ebx, %esi
	movl	%r14d, %edx
	movb	$1, %al
	callq	printf
	incq	%r14
	cmpq	$256, %r14                      # imm = 0x100
	jne	.LBB1_8
# %bb.9:                                #   in Loop: Header=BB1_7 Depth=1
	incq	%rbx
	cmpq	$256, %rbx                      # imm = 0x100
	jne	.LBB1_7
# %bb.10:                               # %.preheader.preheader
	xorl	%ebx, %ebx
.LBB1_11:                               # %.preheader
                                        # =>This Inner Loop Header: Depth=1
	movq	(%rsp), %rax
	movq	(%rax,%rbx,8), %rdi
	callq	hipFree
	movq	8(%rsp), %rax
	movq	(%rax,%rbx,8), %rdi
	callq	hipFree
	movq	16(%rsp), %rax
	movq	(%rax,%rbx,8), %rdi
	callq	hipFree
	incq	%rbx
	cmpq	$256, %rbx                      # imm = 0x100
	jne	.LBB1_11
# %bb.12:
	movq	(%rsp), %rdi
	callq	hipFree
	movq	8(%rsp), %rdi
	callq	hipFree
	movq	16(%rsp), %rdi
	callq	hipFree
	xorl	%eax, %eax
	addq	$24, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	main, .Lfunc_end1-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z6MatAddPPfS0_S0_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z6MatAddPPfS0_S0_,@object      # @_Z6MatAddPPfS0_S0_
	.section	.rodata,"a",@progbits
	.globl	_Z6MatAddPPfS0_S0_
	.p2align	3, 0x0
_Z6MatAddPPfS0_S0_:
	.quad	_Z21__device_stub__MatAddPPfS0_S0_
	.size	_Z6MatAddPPfS0_S0_, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"%d %d %f\n"
	.size	.L.str, 10

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z6MatAddPPfS0_S0_"
	.size	.L__unnamed_1, 19

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z21__device_stub__MatAddPPfS0_S0_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z6MatAddPPfS0_S0_
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z6MatAddPPfS0_S0_      ; -- Begin function _Z6MatAddPPfS0_S0_
	.globl	_Z6MatAddPPfS0_S0_
	.p2align	8
	.type	_Z6MatAddPPfS0_S0_,@function
_Z6MatAddPPfS0_S0_:                     ; @_Z6MatAddPPfS0_S0_
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x24
	s_load_b128 s[4:7], s[0:1], 0x0
	v_and_b32_e32 v1, 0x3ff, v0
	v_bfe_u32 v0, v0, 10, 10
	s_load_b64 s[0:1], s[0:1], 0x10
	s_waitcnt lgkmcnt(0)
	s_and_b32 s3, s2, 0xffff
	s_lshr_b32 s2, s2, 16
	v_mad_u64_u32 v[2:3], null, s14, s3, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[1:2], 3, v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, s4, v1
	v_add_co_ci_u32_e32 v4, vcc_lo, s5, v2, vcc_lo
	v_add_co_u32 v5, vcc_lo, s6, v1
	v_add_co_ci_u32_e32 v6, vcc_lo, s7, v2, vcc_lo
	v_mad_u64_u32 v[7:8], null, s15, s2, v[0:1]
	global_load_b64 v[3:4], v[3:4], off
	global_load_b64 v[5:6], v[5:6], off
	v_ashrrev_i32_e32 v8, 31, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[7:8], 2, v[7:8]
	s_waitcnt vmcnt(1)
	v_add_co_u32 v3, vcc_lo, v3, v7
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, v4, v8, vcc_lo
	s_waitcnt vmcnt(0)
	v_add_co_u32 v5, vcc_lo, v5, v7
	v_add_co_ci_u32_e32 v6, vcc_lo, v6, v8, vcc_lo
	v_add_co_u32 v0, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v2, v[3:4], off
	global_load_b32 v3, v[5:6], off
	global_load_b64 v[0:1], v[0:1], off
	s_waitcnt vmcnt(1)
	v_add_f32_e32 v2, v2, v3
	s_waitcnt vmcnt(0)
	v_add_co_u32 v0, vcc_lo, v0, v7
	v_add_co_ci_u32_e32 v1, vcc_lo, v1, v8, vcc_lo
	global_store_b32 v[0:1], v2, off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z6MatAddPPfS0_S0_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 9
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z6MatAddPPfS0_S0_, .Lfunc_end0-_Z6MatAddPPfS0_S0_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 268
; NumSgprs: 18
; NumVgprs: 9
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 9
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z6MatAddPPfS0_S0_
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z6MatAddPPfS0_S0_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     9
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
