#include <cmath>
#include <cuda_runtime_api.h>

#include "../include/MatrixOps.cuh"

namespace blas1{

    namespace cudaBlas {

        __global__ void naiveTranspose(float *input, float *output, size_t width, size_t height) {
            unsigned int row_id = blockIdx.y * blockDim.y + threadIdx.y;
            unsigned int column_id = blockIdx.x * blockDim.x + threadIdx.x;

            if ((row_id < height) && (column_id < width)) {
                output[row_id + height * column_id] = input[row_id * width + column_id];
            }
        }

        __global__ void naiveCopy(float *input, float *output, size_t width, size_t height) {

            unsigned int row_id = blockIdx.y * blockDim.y + threadIdx.y;
            unsigned int column_id = blockIdx.x * blockDim.x + threadIdx.x;

            if ((row_id < height) && (column_id < width)) {
                output[row_id * width + column_id] = input[row_id * width + column_id];
            }
        }


        __global__ void transpose_32(float *input, float *output, size_t width, size_t height) {
            const unsigned int BLOCK_SIZE = 32;

            __shared__ float sharedMem[BLOCK_SIZE][BLOCK_SIZE + 1]; // Bank conflict

            unsigned int column_index = blockIdx.x * blockDim.x + threadIdx.x;
            unsigned int row_index = blockIdx.y * blockDim.y + threadIdx.y;

            if ((column_index < width) && (row_index < height)) {

                unsigned element_index = row_index * width + column_index;
                sharedMem[threadIdx.y][threadIdx.x] = input[element_index];
            }

            __syncthreads();

            unsigned int local_row = blockIdx.y * BLOCK_SIZE + threadIdx.x;  // coalesced access
            unsigned int local_column = blockIdx.x * BLOCK_SIZE + threadIdx.y; // coalesced access

            if ((local_row < height) && (local_column < width)) {
                output[local_column * height + local_row] = sharedMem[threadIdx.x][threadIdx.y];
            }
        }

        __global__ void transpose_16(float *input, float *output, size_t width, size_t height) {
            const unsigned int BLOCK_SIZE = 16;

            __shared__ float sharedMem[BLOCK_SIZE][BLOCK_SIZE + 1]; // Bank conflict

            unsigned int column_index = blockIdx.x * blockDim.x + threadIdx.x;
            unsigned int row_index = blockIdx.y * blockDim.y + threadIdx.y;

            if ((column_index < width) && (row_index < height)) {

                unsigned element_index = row_index * width + column_index;
                sharedMem[threadIdx.y][threadIdx.x] = input[element_index];
            }

            __syncthreads();

            unsigned int local_row = blockIdx.y * BLOCK_SIZE + threadIdx.x;  // coalesced access
            unsigned int local_column = blockIdx.x * BLOCK_SIZE + threadIdx.y; // coalesced access

            if ((local_row < height) && (local_column < width)) {
                output[local_column * height + local_row] = sharedMem[threadIdx.x][threadIdx.y];
            }
        }

        __global__ void transposeRowBlock_32(float *input, float *output, size_t width, size_t heights) {
            const unsigned int TILE_SIZE = 32;
            const unsigned int BLOCK_ROWS = 8;

            __shared__ float tile[TILE_SIZE][TILE_SIZE + 1];

            unsigned int x = blockIdx.x * TILE_SIZE + threadIdx.x;
            unsigned int y = blockIdx.y * TILE_SIZE + threadIdx.y;
            auto w = gridDim.x * TILE_SIZE;

            for (int j = 0; j < TILE_SIZE; j += BLOCK_ROWS) {
                tile[threadIdx.y + j][threadIdx.x] = input[(y + j) * w + x];
            }
            __syncthreads();

            auto local_row = blockIdx.y * TILE_SIZE + threadIdx.x;
            auto local_column = blockIdx.x * TILE_SIZE + threadIdx.y;

#pragma unroll
            for (int j = 0; j < TILE_SIZE; j += BLOCK_ROWS) {
                output[(local_column + j) * w + local_row] = tile[threadIdx.x][threadIdx.y + j];
            }
        }


        __global__ void transposeRowBlock_16(float *input, float *output, size_t width, size_t heights) {
            const unsigned int TILE_SIZE = 16;
            const unsigned int BLOCK_ROWS = 8;

            __shared__ float tile[TILE_SIZE][TILE_SIZE + 1];

            unsigned int x = blockIdx.x * TILE_SIZE + threadIdx.x;
            unsigned int y = blockIdx.y * TILE_SIZE + threadIdx.y;
            auto w = gridDim.x * TILE_SIZE;

            for (int j = 0; j < TILE_SIZE; j += BLOCK_ROWS) {
                tile[threadIdx.y + j][threadIdx.x] = input[(y + j) * w + x];
            }
            __syncthreads();

            auto local_row = blockIdx.y * TILE_SIZE + threadIdx.x;
            auto local_column = blockIdx.x * TILE_SIZE + threadIdx.y;

#pragma unroll
            for (int j = 0; j < TILE_SIZE; j += BLOCK_ROWS) {
                output[(local_column + j) * w + local_row] = tile[threadIdx.x][threadIdx.y + j];
            }
        }

        __global__ void MatrixCopy_32(float *input, float *output, size_t width, size_t height) {
            const unsigned int BLOCK_SIZE = 32;

            __shared__ float sharedMem[BLOCK_SIZE][BLOCK_SIZE + 1]; // Bank conflict

            unsigned int column_index = blockIdx.x * blockDim.x + threadIdx.x;
            unsigned int row_index = blockIdx.y * blockDim.y + threadIdx.y;

            if ((column_index < width) && (row_index < height)) {

                unsigned element_index = row_index * width + column_index;
                sharedMem[threadIdx.y][threadIdx.x] = input[element_index];
            }

            __syncthreads();

            unsigned int local_row = blockIdx.y * BLOCK_SIZE + threadIdx.x;  // coalesced access
            unsigned int local_column = blockIdx.x * BLOCK_SIZE + threadIdx.y; // coalesced access

            if ((local_row < height) && (local_column < width)) {
                output[local_row * width + local_column] = sharedMem[threadIdx.x][threadIdx.y];
            }
        }


        __global__ void MatrixCopy_16(float *input, float *output, size_t width, size_t height) {
            const unsigned int BLOCK_SIZE = 32;

            __shared__ float sharedMem[BLOCK_SIZE][BLOCK_SIZE + 1]; // Bank conflict solution

            unsigned int column_index = blockIdx.x * blockDim.x + threadIdx.x;
            unsigned int row_index = blockIdx.y * blockDim.y + threadIdx.y;

            if ((column_index < width) && (row_index < height)) {

                unsigned element_index = row_index * width + column_index;
                sharedMem[threadIdx.y][threadIdx.x] = input[element_index];
            }

            __syncthreads();

            unsigned int local_row = blockIdx.y * BLOCK_SIZE + threadIdx.x;  // coalesced access
            unsigned int local_column = blockIdx.x * BLOCK_SIZE + threadIdx.y; // coalesced access

            if ((local_row < height) && (local_column < width)) {
                output[local_row * width + local_column] = sharedMem[threadIdx.x][threadIdx.y];
            }
        }

    }

}
	.file	"tmpxft_00311607_00000000-6_MatrixOps.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2010:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2010:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z56__device_stub__ZN5blas18cudaBlas14naiveTransposeEPfS1_mmPfS_mm
	.type	_Z56__device_stub__ZN5blas18cudaBlas14naiveTransposeEPfS1_mmPfS_mm, @function
_Z56__device_stub__ZN5blas18cudaBlas14naiveTransposeEPfS1_mmPfS_mm:
.LFB2032:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movq	%rcx, (%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_ZN5blas18cudaBlas14naiveTransposeEPfS1_mm(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L2:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2032:
	.size	_Z56__device_stub__ZN5blas18cudaBlas14naiveTransposeEPfS1_mmPfS_mm, .-_Z56__device_stub__ZN5blas18cudaBlas14naiveTransposeEPfS1_mmPfS_mm
	.globl	_ZN5blas18cudaBlas14naiveTransposeEPfS1_mm
	.type	_ZN5blas18cudaBlas14naiveTransposeEPfS1_mm, @function
_ZN5blas18cudaBlas14naiveTransposeEPfS1_mm:
.LFB2033:
	.cfi_startproc
	endbr64
	jmp	_Z56__device_stub__ZN5blas18cudaBlas14naiveTransposeEPfS1_mmPfS_mm
	.cfi_endproc
.LFE2033:
	.size	_ZN5blas18cudaBlas14naiveTransposeEPfS1_mm, .-_ZN5blas18cudaBlas14naiveTransposeEPfS1_mm
	.globl	_Z50__device_stub__ZN5blas18cudaBlas9naiveCopyEPfS1_mmPfS_mm
	.type	_Z50__device_stub__ZN5blas18cudaBlas9naiveCopyEPfS1_mmPfS_mm, @function
_Z50__device_stub__ZN5blas18cudaBlas9naiveCopyEPfS1_mmPfS_mm:
.LFB2034:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movq	%rcx, (%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L8
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_ZN5blas18cudaBlas9naiveCopyEPfS1_mm(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L8:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L10
	call	__stack_chk_fail@PLT
.L10:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2034:
	.size	_Z50__device_stub__ZN5blas18cudaBlas9naiveCopyEPfS1_mmPfS_mm, .-_Z50__device_stub__ZN5blas18cudaBlas9naiveCopyEPfS1_mmPfS_mm
	.globl	_ZN5blas18cudaBlas9naiveCopyEPfS1_mm
	.type	_ZN5blas18cudaBlas9naiveCopyEPfS1_mm, @function
_ZN5blas18cudaBlas9naiveCopyEPfS1_mm:
.LFB2035:
	.cfi_startproc
	endbr64
	jmp	_Z50__device_stub__ZN5blas18cudaBlas9naiveCopyEPfS1_mmPfS_mm
	.cfi_endproc
.LFE2035:
	.size	_ZN5blas18cudaBlas9naiveCopyEPfS1_mm, .-_ZN5blas18cudaBlas9naiveCopyEPfS1_mm
	.globl	_Z54__device_stub__ZN5blas18cudaBlas12transpose_32EPfS1_mmPfS_mm
	.type	_Z54__device_stub__ZN5blas18cudaBlas12transpose_32EPfS1_mmPfS_mm, @function
_Z54__device_stub__ZN5blas18cudaBlas12transpose_32EPfS1_mmPfS_mm:
.LFB2036:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movq	%rcx, (%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L13
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_ZN5blas18cudaBlas12transpose_32EPfS1_mm(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L13:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L15
	call	__stack_chk_fail@PLT
.L15:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2036:
	.size	_Z54__device_stub__ZN5blas18cudaBlas12transpose_32EPfS1_mmPfS_mm, .-_Z54__device_stub__ZN5blas18cudaBlas12transpose_32EPfS1_mmPfS_mm
	.globl	_ZN5blas18cudaBlas12transpose_32EPfS1_mm
	.type	_ZN5blas18cudaBlas12transpose_32EPfS1_mm, @function
_ZN5blas18cudaBlas12transpose_32EPfS1_mm:
.LFB2037:
	.cfi_startproc
	endbr64
	jmp	_Z54__device_stub__ZN5blas18cudaBlas12transpose_32EPfS1_mmPfS_mm
	.cfi_endproc
.LFE2037:
	.size	_ZN5blas18cudaBlas12transpose_32EPfS1_mm, .-_ZN5blas18cudaBlas12transpose_32EPfS1_mm
	.globl	_Z54__device_stub__ZN5blas18cudaBlas12transpose_16EPfS1_mmPfS_mm
	.type	_Z54__device_stub__ZN5blas18cudaBlas12transpose_16EPfS1_mmPfS_mm, @function
_Z54__device_stub__ZN5blas18cudaBlas12transpose_16EPfS1_mmPfS_mm:
.LFB2038:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movq	%rcx, (%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L18
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_ZN5blas18cudaBlas12transpose_16EPfS1_mm(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L18:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L20
	call	__stack_chk_fail@PLT
.L20:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2038:
	.size	_Z54__device_stub__ZN5blas18cudaBlas12transpose_16EPfS1_mmPfS_mm, .-_Z54__device_stub__ZN5blas18cudaBlas12transpose_16EPfS1_mmPfS_mm
	.globl	_ZN5blas18cudaBlas12transpose_16EPfS1_mm
	.type	_ZN5blas18cudaBlas12transpose_16EPfS1_mm, @function
_ZN5blas18cudaBlas12transpose_16EPfS1_mm:
.LFB2039:
	.cfi_startproc
	endbr64
	jmp	_Z54__device_stub__ZN5blas18cudaBlas12transpose_16EPfS1_mmPfS_mm
	.cfi_endproc
.LFE2039:
	.size	_ZN5blas18cudaBlas12transpose_16EPfS1_mm, .-_ZN5blas18cudaBlas12transpose_16EPfS1_mm
	.globl	_Z62__device_stub__ZN5blas18cudaBlas20transposeRowBlock_32EPfS1_mmPfS_mm
	.type	_Z62__device_stub__ZN5blas18cudaBlas20transposeRowBlock_32EPfS1_mmPfS_mm, @function
_Z62__device_stub__ZN5blas18cudaBlas20transposeRowBlock_32EPfS1_mmPfS_mm:
.LFB2040:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movq	%rcx, (%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L23
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_ZN5blas18cudaBlas20transposeRowBlock_32EPfS1_mm(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L23:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L25
	call	__stack_chk_fail@PLT
.L25:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2040:
	.size	_Z62__device_stub__ZN5blas18cudaBlas20transposeRowBlock_32EPfS1_mmPfS_mm, .-_Z62__device_stub__ZN5blas18cudaBlas20transposeRowBlock_32EPfS1_mmPfS_mm
	.globl	_ZN5blas18cudaBlas20transposeRowBlock_32EPfS1_mm
	.type	_ZN5blas18cudaBlas20transposeRowBlock_32EPfS1_mm, @function
_ZN5blas18cudaBlas20transposeRowBlock_32EPfS1_mm:
.LFB2041:
	.cfi_startproc
	endbr64
	jmp	_Z62__device_stub__ZN5blas18cudaBlas20transposeRowBlock_32EPfS1_mmPfS_mm
	.cfi_endproc
.LFE2041:
	.size	_ZN5blas18cudaBlas20transposeRowBlock_32EPfS1_mm, .-_ZN5blas18cudaBlas20transposeRowBlock_32EPfS1_mm
	.globl	_Z62__device_stub__ZN5blas18cudaBlas20transposeRowBlock_16EPfS1_mmPfS_mm
	.type	_Z62__device_stub__ZN5blas18cudaBlas20transposeRowBlock_16EPfS1_mmPfS_mm, @function
_Z62__device_stub__ZN5blas18cudaBlas20transposeRowBlock_16EPfS1_mmPfS_mm:
.LFB2042:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movq	%rcx, (%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L28
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_ZN5blas18cudaBlas20transposeRowBlock_16EPfS1_mm(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L28:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L30
	call	__stack_chk_fail@PLT
.L30:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2042:
	.size	_Z62__device_stub__ZN5blas18cudaBlas20transposeRowBlock_16EPfS1_mmPfS_mm, .-_Z62__device_stub__ZN5blas18cudaBlas20transposeRowBlock_16EPfS1_mmPfS_mm
	.globl	_ZN5blas18cudaBlas20transposeRowBlock_16EPfS1_mm
	.type	_ZN5blas18cudaBlas20transposeRowBlock_16EPfS1_mm, @function
_ZN5blas18cudaBlas20transposeRowBlock_16EPfS1_mm:
.LFB2043:
	.cfi_startproc
	endbr64
	jmp	_Z62__device_stub__ZN5blas18cudaBlas20transposeRowBlock_16EPfS1_mmPfS_mm
	.cfi_endproc
.LFE2043:
	.size	_ZN5blas18cudaBlas20transposeRowBlock_16EPfS1_mm, .-_ZN5blas18cudaBlas20transposeRowBlock_16EPfS1_mm
	.globl	_Z55__device_stub__ZN5blas18cudaBlas13MatrixCopy_32EPfS1_mmPfS_mm
	.type	_Z55__device_stub__ZN5blas18cudaBlas13MatrixCopy_32EPfS1_mmPfS_mm, @function
_Z55__device_stub__ZN5blas18cudaBlas13MatrixCopy_32EPfS1_mmPfS_mm:
.LFB2044:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movq	%rcx, (%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L33
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_ZN5blas18cudaBlas13MatrixCopy_32EPfS1_mm(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L33:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L35
	call	__stack_chk_fail@PLT
.L35:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2044:
	.size	_Z55__device_stub__ZN5blas18cudaBlas13MatrixCopy_32EPfS1_mmPfS_mm, .-_Z55__device_stub__ZN5blas18cudaBlas13MatrixCopy_32EPfS1_mmPfS_mm
	.globl	_ZN5blas18cudaBlas13MatrixCopy_32EPfS1_mm
	.type	_ZN5blas18cudaBlas13MatrixCopy_32EPfS1_mm, @function
_ZN5blas18cudaBlas13MatrixCopy_32EPfS1_mm:
.LFB2045:
	.cfi_startproc
	endbr64
	jmp	_Z55__device_stub__ZN5blas18cudaBlas13MatrixCopy_32EPfS1_mmPfS_mm
	.cfi_endproc
.LFE2045:
	.size	_ZN5blas18cudaBlas13MatrixCopy_32EPfS1_mm, .-_ZN5blas18cudaBlas13MatrixCopy_32EPfS1_mm
	.globl	_Z55__device_stub__ZN5blas18cudaBlas13MatrixCopy_16EPfS1_mmPfS_mm
	.type	_Z55__device_stub__ZN5blas18cudaBlas13MatrixCopy_16EPfS1_mmPfS_mm, @function
_Z55__device_stub__ZN5blas18cudaBlas13MatrixCopy_16EPfS1_mmPfS_mm:
.LFB2046:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movq	%rcx, (%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L38
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_ZN5blas18cudaBlas13MatrixCopy_16EPfS1_mm(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L38:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L40
	call	__stack_chk_fail@PLT
.L40:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2046:
	.size	_Z55__device_stub__ZN5blas18cudaBlas13MatrixCopy_16EPfS1_mmPfS_mm, .-_Z55__device_stub__ZN5blas18cudaBlas13MatrixCopy_16EPfS1_mmPfS_mm
	.globl	_ZN5blas18cudaBlas13MatrixCopy_16EPfS1_mm
	.type	_ZN5blas18cudaBlas13MatrixCopy_16EPfS1_mm, @function
_ZN5blas18cudaBlas13MatrixCopy_16EPfS1_mm:
.LFB2047:
	.cfi_startproc
	endbr64
	jmp	_Z55__device_stub__ZN5blas18cudaBlas13MatrixCopy_16EPfS1_mmPfS_mm
	.cfi_endproc
.LFE2047:
	.size	_ZN5blas18cudaBlas13MatrixCopy_16EPfS1_mm, .-_ZN5blas18cudaBlas13MatrixCopy_16EPfS1_mm
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_ZN5blas18cudaBlas13MatrixCopy_16EPfS1_mm"
.LC1:
	.string	"_ZN5blas18cudaBlas13MatrixCopy_32EPfS1_mm"
.LC2:
	.string	"_ZN5blas18cudaBlas20transposeRowBlock_16EPfS1_mm"
.LC3:
	.string	"_ZN5blas18cudaBlas20transposeRowBlock_32EPfS1_mm"
.LC4:
	.string	"_ZN5blas18cudaBlas12transpose_16EPfS1_mm"
.LC5:
	.string	"_ZN5blas18cudaBlas12transpose_32EPfS1_mm"
.LC6:
	.string	"_ZN5blas18cudaBlas9naiveCopyEPfS1_mm"
.LC7:
	.string	"_ZN5blas18cudaBlas14naiveTransposeEPfS1_mm"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2049:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_ZN5blas18cudaBlas13MatrixCopy_16EPfS1_mm(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC1(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_ZN5blas18cudaBlas13MatrixCopy_32EPfS1_mm(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC2(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_ZN5blas18cudaBlas20transposeRowBlock_16EPfS1_mm(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC3(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_ZN5blas18cudaBlas20transposeRowBlock_32EPfS1_mm(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC4(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_ZN5blas18cudaBlas12transpose_16EPfS1_mm(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC5(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_ZN5blas18cudaBlas12transpose_32EPfS1_mm(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC6(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_ZN5blas18cudaBlas9naiveCopyEPfS1_mm(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC7(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_ZN5blas18cudaBlas14naiveTransposeEPfS1_mm(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2049:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include <cmath>
#include <hip/hip_runtime_api.h>

#include "../include/MatrixOps.cuh"

namespace blas1{

    namespace cudaBlas {

        __global__ void naiveTranspose(float *input, float *output, size_t width, size_t height) {
            unsigned int row_id = blockIdx.y * blockDim.y + threadIdx.y;
            unsigned int column_id = blockIdx.x * blockDim.x + threadIdx.x;

            if ((row_id < height) && (column_id < width)) {
                output[row_id + height * column_id] = input[row_id * width + column_id];
            }
        }

        __global__ void naiveCopy(float *input, float *output, size_t width, size_t height) {

            unsigned int row_id = blockIdx.y * blockDim.y + threadIdx.y;
            unsigned int column_id = blockIdx.x * blockDim.x + threadIdx.x;

            if ((row_id < height) && (column_id < width)) {
                output[row_id * width + column_id] = input[row_id * width + column_id];
            }
        }


        __global__ void transpose_32(float *input, float *output, size_t width, size_t height) {
            const unsigned int BLOCK_SIZE = 32;

            __shared__ float sharedMem[BLOCK_SIZE][BLOCK_SIZE + 1]; // Bank conflict

            unsigned int column_index = blockIdx.x * blockDim.x + threadIdx.x;
            unsigned int row_index = blockIdx.y * blockDim.y + threadIdx.y;

            if ((column_index < width) && (row_index < height)) {

                unsigned element_index = row_index * width + column_index;
                sharedMem[threadIdx.y][threadIdx.x] = input[element_index];
            }

            __syncthreads();

            unsigned int local_row = blockIdx.y * BLOCK_SIZE + threadIdx.x;  // coalesced access
            unsigned int local_column = blockIdx.x * BLOCK_SIZE + threadIdx.y; // coalesced access

            if ((local_row < height) && (local_column < width)) {
                output[local_column * height + local_row] = sharedMem[threadIdx.x][threadIdx.y];
            }
        }

        __global__ void transpose_16(float *input, float *output, size_t width, size_t height) {
            const unsigned int BLOCK_SIZE = 16;

            __shared__ float sharedMem[BLOCK_SIZE][BLOCK_SIZE + 1]; // Bank conflict

            unsigned int column_index = blockIdx.x * blockDim.x + threadIdx.x;
            unsigned int row_index = blockIdx.y * blockDim.y + threadIdx.y;

            if ((column_index < width) && (row_index < height)) {

                unsigned element_index = row_index * width + column_index;
                sharedMem[threadIdx.y][threadIdx.x] = input[element_index];
            }

            __syncthreads();

            unsigned int local_row = blockIdx.y * BLOCK_SIZE + threadIdx.x;  // coalesced access
            unsigned int local_column = blockIdx.x * BLOCK_SIZE + threadIdx.y; // coalesced access

            if ((local_row < height) && (local_column < width)) {
                output[local_column * height + local_row] = sharedMem[threadIdx.x][threadIdx.y];
            }
        }

        __global__ void transposeRowBlock_32(float *input, float *output, size_t width, size_t heights) {
            const unsigned int TILE_SIZE = 32;
            const unsigned int BLOCK_ROWS = 8;

            __shared__ float tile[TILE_SIZE][TILE_SIZE + 1];

            unsigned int x = blockIdx.x * TILE_SIZE + threadIdx.x;
            unsigned int y = blockIdx.y * TILE_SIZE + threadIdx.y;
            auto w = gridDim.x * TILE_SIZE;

            for (int j = 0; j < TILE_SIZE; j += BLOCK_ROWS) {
                tile[threadIdx.y + j][threadIdx.x] = input[(y + j) * w + x];
            }
            __syncthreads();

            auto local_row = blockIdx.y * TILE_SIZE + threadIdx.x;
            auto local_column = blockIdx.x * TILE_SIZE + threadIdx.y;

#pragma unroll
            for (int j = 0; j < TILE_SIZE; j += BLOCK_ROWS) {
                output[(local_column + j) * w + local_row] = tile[threadIdx.x][threadIdx.y + j];
            }
        }


        __global__ void transposeRowBlock_16(float *input, float *output, size_t width, size_t heights) {
            const unsigned int TILE_SIZE = 16;
            const unsigned int BLOCK_ROWS = 8;

            __shared__ float tile[TILE_SIZE][TILE_SIZE + 1];

            unsigned int x = blockIdx.x * TILE_SIZE + threadIdx.x;
            unsigned int y = blockIdx.y * TILE_SIZE + threadIdx.y;
            auto w = gridDim.x * TILE_SIZE;

            for (int j = 0; j < TILE_SIZE; j += BLOCK_ROWS) {
                tile[threadIdx.y + j][threadIdx.x] = input[(y + j) * w + x];
            }
            __syncthreads();

            auto local_row = blockIdx.y * TILE_SIZE + threadIdx.x;
            auto local_column = blockIdx.x * TILE_SIZE + threadIdx.y;

#pragma unroll
            for (int j = 0; j < TILE_SIZE; j += BLOCK_ROWS) {
                output[(local_column + j) * w + local_row] = tile[threadIdx.x][threadIdx.y + j];
            }
        }

        __global__ void MatrixCopy_32(float *input, float *output, size_t width, size_t height) {
            const unsigned int BLOCK_SIZE = 32;

            __shared__ float sharedMem[BLOCK_SIZE][BLOCK_SIZE + 1]; // Bank conflict

            unsigned int column_index = blockIdx.x * blockDim.x + threadIdx.x;
            unsigned int row_index = blockIdx.y * blockDim.y + threadIdx.y;

            if ((column_index < width) && (row_index < height)) {

                unsigned element_index = row_index * width + column_index;
                sharedMem[threadIdx.y][threadIdx.x] = input[element_index];
            }

            __syncthreads();

            unsigned int local_row = blockIdx.y * BLOCK_SIZE + threadIdx.x;  // coalesced access
            unsigned int local_column = blockIdx.x * BLOCK_SIZE + threadIdx.y; // coalesced access

            if ((local_row < height) && (local_column < width)) {
                output[local_row * width + local_column] = sharedMem[threadIdx.x][threadIdx.y];
            }
        }


        __global__ void MatrixCopy_16(float *input, float *output, size_t width, size_t height) {
            const unsigned int BLOCK_SIZE = 32;

            __shared__ float sharedMem[BLOCK_SIZE][BLOCK_SIZE + 1]; // Bank conflict solution

            unsigned int column_index = blockIdx.x * blockDim.x + threadIdx.x;
            unsigned int row_index = blockIdx.y * blockDim.y + threadIdx.y;

            if ((column_index < width) && (row_index < height)) {

                unsigned element_index = row_index * width + column_index;
                sharedMem[threadIdx.y][threadIdx.x] = input[element_index];
            }

            __syncthreads();

            unsigned int local_row = blockIdx.y * BLOCK_SIZE + threadIdx.x;  // coalesced access
            unsigned int local_column = blockIdx.x * BLOCK_SIZE + threadIdx.y; // coalesced access

            if ((local_row < height) && (local_column < width)) {
                output[local_row * width + local_column] = sharedMem[threadIdx.x][threadIdx.y];
            }
        }

    }

}
	.text
	.file	"MatrixOps.hip"
	.globl	_ZN5blas18cudaBlas29__device_stub__naiveTransposeEPfS1_mm # -- Begin function _ZN5blas18cudaBlas29__device_stub__naiveTransposeEPfS1_mm
	.type	_ZN5blas18cudaBlas29__device_stub__naiveTransposeEPfS1_mm,@function
_ZN5blas18cudaBlas29__device_stub__naiveTransposeEPfS1_mm: # @_ZN5blas18cudaBlas29__device_stub__naiveTransposeEPfS1_mm
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	16(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_ZN5blas18cudaBlas14naiveTransposeEPfS1_mm, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_ZN5blas18cudaBlas29__device_stub__naiveTransposeEPfS1_mm, .Lfunc_end0-_ZN5blas18cudaBlas29__device_stub__naiveTransposeEPfS1_mm
	.cfi_endproc
                                        # -- End function
	.globl	_ZN5blas18cudaBlas24__device_stub__naiveCopyEPfS1_mm # -- Begin function _ZN5blas18cudaBlas24__device_stub__naiveCopyEPfS1_mm
	.type	_ZN5blas18cudaBlas24__device_stub__naiveCopyEPfS1_mm,@function
_ZN5blas18cudaBlas24__device_stub__naiveCopyEPfS1_mm: # @_ZN5blas18cudaBlas24__device_stub__naiveCopyEPfS1_mm
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	16(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_ZN5blas18cudaBlas9naiveCopyEPfS1_mm, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_ZN5blas18cudaBlas24__device_stub__naiveCopyEPfS1_mm, .Lfunc_end1-_ZN5blas18cudaBlas24__device_stub__naiveCopyEPfS1_mm
	.cfi_endproc
                                        # -- End function
	.globl	_ZN5blas18cudaBlas27__device_stub__transpose_32EPfS1_mm # -- Begin function _ZN5blas18cudaBlas27__device_stub__transpose_32EPfS1_mm
	.type	_ZN5blas18cudaBlas27__device_stub__transpose_32EPfS1_mm,@function
_ZN5blas18cudaBlas27__device_stub__transpose_32EPfS1_mm: # @_ZN5blas18cudaBlas27__device_stub__transpose_32EPfS1_mm
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	16(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_ZN5blas18cudaBlas12transpose_32EPfS1_mm, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_ZN5blas18cudaBlas27__device_stub__transpose_32EPfS1_mm, .Lfunc_end2-_ZN5blas18cudaBlas27__device_stub__transpose_32EPfS1_mm
	.cfi_endproc
                                        # -- End function
	.globl	_ZN5blas18cudaBlas27__device_stub__transpose_16EPfS1_mm # -- Begin function _ZN5blas18cudaBlas27__device_stub__transpose_16EPfS1_mm
	.type	_ZN5blas18cudaBlas27__device_stub__transpose_16EPfS1_mm,@function
_ZN5blas18cudaBlas27__device_stub__transpose_16EPfS1_mm: # @_ZN5blas18cudaBlas27__device_stub__transpose_16EPfS1_mm
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	16(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_ZN5blas18cudaBlas12transpose_16EPfS1_mm, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	_ZN5blas18cudaBlas27__device_stub__transpose_16EPfS1_mm, .Lfunc_end3-_ZN5blas18cudaBlas27__device_stub__transpose_16EPfS1_mm
	.cfi_endproc
                                        # -- End function
	.globl	_ZN5blas18cudaBlas35__device_stub__transposeRowBlock_32EPfS1_mm # -- Begin function _ZN5blas18cudaBlas35__device_stub__transposeRowBlock_32EPfS1_mm
	.type	_ZN5blas18cudaBlas35__device_stub__transposeRowBlock_32EPfS1_mm,@function
_ZN5blas18cudaBlas35__device_stub__transposeRowBlock_32EPfS1_mm: # @_ZN5blas18cudaBlas35__device_stub__transposeRowBlock_32EPfS1_mm
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	16(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_ZN5blas18cudaBlas20transposeRowBlock_32EPfS1_mm, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end4:
	.size	_ZN5blas18cudaBlas35__device_stub__transposeRowBlock_32EPfS1_mm, .Lfunc_end4-_ZN5blas18cudaBlas35__device_stub__transposeRowBlock_32EPfS1_mm
	.cfi_endproc
                                        # -- End function
	.globl	_ZN5blas18cudaBlas35__device_stub__transposeRowBlock_16EPfS1_mm # -- Begin function _ZN5blas18cudaBlas35__device_stub__transposeRowBlock_16EPfS1_mm
	.type	_ZN5blas18cudaBlas35__device_stub__transposeRowBlock_16EPfS1_mm,@function
_ZN5blas18cudaBlas35__device_stub__transposeRowBlock_16EPfS1_mm: # @_ZN5blas18cudaBlas35__device_stub__transposeRowBlock_16EPfS1_mm
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	16(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_ZN5blas18cudaBlas20transposeRowBlock_16EPfS1_mm, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end5:
	.size	_ZN5blas18cudaBlas35__device_stub__transposeRowBlock_16EPfS1_mm, .Lfunc_end5-_ZN5blas18cudaBlas35__device_stub__transposeRowBlock_16EPfS1_mm
	.cfi_endproc
                                        # -- End function
	.globl	_ZN5blas18cudaBlas28__device_stub__MatrixCopy_32EPfS1_mm # -- Begin function _ZN5blas18cudaBlas28__device_stub__MatrixCopy_32EPfS1_mm
	.type	_ZN5blas18cudaBlas28__device_stub__MatrixCopy_32EPfS1_mm,@function
_ZN5blas18cudaBlas28__device_stub__MatrixCopy_32EPfS1_mm: # @_ZN5blas18cudaBlas28__device_stub__MatrixCopy_32EPfS1_mm
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	16(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_ZN5blas18cudaBlas13MatrixCopy_32EPfS1_mm, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end6:
	.size	_ZN5blas18cudaBlas28__device_stub__MatrixCopy_32EPfS1_mm, .Lfunc_end6-_ZN5blas18cudaBlas28__device_stub__MatrixCopy_32EPfS1_mm
	.cfi_endproc
                                        # -- End function
	.globl	_ZN5blas18cudaBlas28__device_stub__MatrixCopy_16EPfS1_mm # -- Begin function _ZN5blas18cudaBlas28__device_stub__MatrixCopy_16EPfS1_mm
	.type	_ZN5blas18cudaBlas28__device_stub__MatrixCopy_16EPfS1_mm,@function
_ZN5blas18cudaBlas28__device_stub__MatrixCopy_16EPfS1_mm: # @_ZN5blas18cudaBlas28__device_stub__MatrixCopy_16EPfS1_mm
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	16(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_ZN5blas18cudaBlas13MatrixCopy_16EPfS1_mm, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end7:
	.size	_ZN5blas18cudaBlas28__device_stub__MatrixCopy_16EPfS1_mm, .Lfunc_end7-_ZN5blas18cudaBlas28__device_stub__MatrixCopy_16EPfS1_mm
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB8_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB8_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_ZN5blas18cudaBlas14naiveTransposeEPfS1_mm, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_ZN5blas18cudaBlas9naiveCopyEPfS1_mm, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_ZN5blas18cudaBlas12transpose_32EPfS1_mm, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_ZN5blas18cudaBlas12transpose_16EPfS1_mm, %esi
	movl	$.L__unnamed_4, %edx
	movl	$.L__unnamed_4, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_ZN5blas18cudaBlas20transposeRowBlock_32EPfS1_mm, %esi
	movl	$.L__unnamed_5, %edx
	movl	$.L__unnamed_5, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_ZN5blas18cudaBlas20transposeRowBlock_16EPfS1_mm, %esi
	movl	$.L__unnamed_6, %edx
	movl	$.L__unnamed_6, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_ZN5blas18cudaBlas13MatrixCopy_32EPfS1_mm, %esi
	movl	$.L__unnamed_7, %edx
	movl	$.L__unnamed_7, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_ZN5blas18cudaBlas13MatrixCopy_16EPfS1_mm, %esi
	movl	$.L__unnamed_8, %edx
	movl	$.L__unnamed_8, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end8:
	.size	__hip_module_ctor, .Lfunc_end8-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB9_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB9_2:
	retq
.Lfunc_end9:
	.size	__hip_module_dtor, .Lfunc_end9-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_ZN5blas18cudaBlas14naiveTransposeEPfS1_mm,@object # @_ZN5blas18cudaBlas14naiveTransposeEPfS1_mm
	.section	.rodata,"a",@progbits
	.globl	_ZN5blas18cudaBlas14naiveTransposeEPfS1_mm
	.p2align	3, 0x0
_ZN5blas18cudaBlas14naiveTransposeEPfS1_mm:
	.quad	_ZN5blas18cudaBlas29__device_stub__naiveTransposeEPfS1_mm
	.size	_ZN5blas18cudaBlas14naiveTransposeEPfS1_mm, 8

	.type	_ZN5blas18cudaBlas9naiveCopyEPfS1_mm,@object # @_ZN5blas18cudaBlas9naiveCopyEPfS1_mm
	.globl	_ZN5blas18cudaBlas9naiveCopyEPfS1_mm
	.p2align	3, 0x0
_ZN5blas18cudaBlas9naiveCopyEPfS1_mm:
	.quad	_ZN5blas18cudaBlas24__device_stub__naiveCopyEPfS1_mm
	.size	_ZN5blas18cudaBlas9naiveCopyEPfS1_mm, 8

	.type	_ZN5blas18cudaBlas12transpose_32EPfS1_mm,@object # @_ZN5blas18cudaBlas12transpose_32EPfS1_mm
	.globl	_ZN5blas18cudaBlas12transpose_32EPfS1_mm
	.p2align	3, 0x0
_ZN5blas18cudaBlas12transpose_32EPfS1_mm:
	.quad	_ZN5blas18cudaBlas27__device_stub__transpose_32EPfS1_mm
	.size	_ZN5blas18cudaBlas12transpose_32EPfS1_mm, 8

	.type	_ZN5blas18cudaBlas12transpose_16EPfS1_mm,@object # @_ZN5blas18cudaBlas12transpose_16EPfS1_mm
	.globl	_ZN5blas18cudaBlas12transpose_16EPfS1_mm
	.p2align	3, 0x0
_ZN5blas18cudaBlas12transpose_16EPfS1_mm:
	.quad	_ZN5blas18cudaBlas27__device_stub__transpose_16EPfS1_mm
	.size	_ZN5blas18cudaBlas12transpose_16EPfS1_mm, 8

	.type	_ZN5blas18cudaBlas20transposeRowBlock_32EPfS1_mm,@object # @_ZN5blas18cudaBlas20transposeRowBlock_32EPfS1_mm
	.globl	_ZN5blas18cudaBlas20transposeRowBlock_32EPfS1_mm
	.p2align	3, 0x0
_ZN5blas18cudaBlas20transposeRowBlock_32EPfS1_mm:
	.quad	_ZN5blas18cudaBlas35__device_stub__transposeRowBlock_32EPfS1_mm
	.size	_ZN5blas18cudaBlas20transposeRowBlock_32EPfS1_mm, 8

	.type	_ZN5blas18cudaBlas20transposeRowBlock_16EPfS1_mm,@object # @_ZN5blas18cudaBlas20transposeRowBlock_16EPfS1_mm
	.globl	_ZN5blas18cudaBlas20transposeRowBlock_16EPfS1_mm
	.p2align	3, 0x0
_ZN5blas18cudaBlas20transposeRowBlock_16EPfS1_mm:
	.quad	_ZN5blas18cudaBlas35__device_stub__transposeRowBlock_16EPfS1_mm
	.size	_ZN5blas18cudaBlas20transposeRowBlock_16EPfS1_mm, 8

	.type	_ZN5blas18cudaBlas13MatrixCopy_32EPfS1_mm,@object # @_ZN5blas18cudaBlas13MatrixCopy_32EPfS1_mm
	.globl	_ZN5blas18cudaBlas13MatrixCopy_32EPfS1_mm
	.p2align	3, 0x0
_ZN5blas18cudaBlas13MatrixCopy_32EPfS1_mm:
	.quad	_ZN5blas18cudaBlas28__device_stub__MatrixCopy_32EPfS1_mm
	.size	_ZN5blas18cudaBlas13MatrixCopy_32EPfS1_mm, 8

	.type	_ZN5blas18cudaBlas13MatrixCopy_16EPfS1_mm,@object # @_ZN5blas18cudaBlas13MatrixCopy_16EPfS1_mm
	.globl	_ZN5blas18cudaBlas13MatrixCopy_16EPfS1_mm
	.p2align	3, 0x0
_ZN5blas18cudaBlas13MatrixCopy_16EPfS1_mm:
	.quad	_ZN5blas18cudaBlas28__device_stub__MatrixCopy_16EPfS1_mm
	.size	_ZN5blas18cudaBlas13MatrixCopy_16EPfS1_mm, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_ZN5blas18cudaBlas14naiveTransposeEPfS1_mm"
	.size	.L__unnamed_1, 43

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_ZN5blas18cudaBlas9naiveCopyEPfS1_mm"
	.size	.L__unnamed_2, 37

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_ZN5blas18cudaBlas12transpose_32EPfS1_mm"
	.size	.L__unnamed_3, 41

	.type	.L__unnamed_4,@object           # @3
.L__unnamed_4:
	.asciz	"_ZN5blas18cudaBlas12transpose_16EPfS1_mm"
	.size	.L__unnamed_4, 41

	.type	.L__unnamed_5,@object           # @4
.L__unnamed_5:
	.asciz	"_ZN5blas18cudaBlas20transposeRowBlock_32EPfS1_mm"
	.size	.L__unnamed_5, 49

	.type	.L__unnamed_6,@object           # @5
.L__unnamed_6:
	.asciz	"_ZN5blas18cudaBlas20transposeRowBlock_16EPfS1_mm"
	.size	.L__unnamed_6, 49

	.type	.L__unnamed_7,@object           # @6
.L__unnamed_7:
	.asciz	"_ZN5blas18cudaBlas13MatrixCopy_32EPfS1_mm"
	.size	.L__unnamed_7, 42

	.type	.L__unnamed_8,@object           # @7
.L__unnamed_8:
	.asciz	"_ZN5blas18cudaBlas13MatrixCopy_16EPfS1_mm"
	.size	.L__unnamed_8, 42

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _ZN5blas18cudaBlas29__device_stub__naiveTransposeEPfS1_mm
	.addrsig_sym _ZN5blas18cudaBlas24__device_stub__naiveCopyEPfS1_mm
	.addrsig_sym _ZN5blas18cudaBlas27__device_stub__transpose_32EPfS1_mm
	.addrsig_sym _ZN5blas18cudaBlas27__device_stub__transpose_16EPfS1_mm
	.addrsig_sym _ZN5blas18cudaBlas35__device_stub__transposeRowBlock_32EPfS1_mm
	.addrsig_sym _ZN5blas18cudaBlas35__device_stub__transposeRowBlock_16EPfS1_mm
	.addrsig_sym _ZN5blas18cudaBlas28__device_stub__MatrixCopy_32EPfS1_mm
	.addrsig_sym _ZN5blas18cudaBlas28__device_stub__MatrixCopy_16EPfS1_mm
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _ZN5blas18cudaBlas14naiveTransposeEPfS1_mm
	.addrsig_sym _ZN5blas18cudaBlas9naiveCopyEPfS1_mm
	.addrsig_sym _ZN5blas18cudaBlas12transpose_32EPfS1_mm
	.addrsig_sym _ZN5blas18cudaBlas12transpose_16EPfS1_mm
	.addrsig_sym _ZN5blas18cudaBlas20transposeRowBlock_32EPfS1_mm
	.addrsig_sym _ZN5blas18cudaBlas20transposeRowBlock_16EPfS1_mm
	.addrsig_sym _ZN5blas18cudaBlas13MatrixCopy_32EPfS1_mm
	.addrsig_sym _ZN5blas18cudaBlas13MatrixCopy_16EPfS1_mm
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_ZN5blas18cudaBlas14naiveTransposeEPfS1_mm ; -- Begin function _ZN5blas18cudaBlas14naiveTransposeEPfS1_mm
	.globl	_ZN5blas18cudaBlas14naiveTransposeEPfS1_mm
	.p2align	8
	.type	_ZN5blas18cudaBlas14naiveTransposeEPfS1_mm,@function
_ZN5blas18cudaBlas14naiveTransposeEPfS1_mm: ; @_ZN5blas18cudaBlas14naiveTransposeEPfS1_mm
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x2c
	s_load_b256 s[4:11], s[0:1], 0x0
	v_bfe_u32 v3, v0, 10, 10
	v_mov_b32_e32 v4, 0
	s_add_u32 s0, s0, 32
	s_addc_u32 s1, s1, 0
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s2, s2, 16
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
	v_mov_b32_e32 v2, v4
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_u64_e64 s[10:11], v[1:2]
	s_cbranch_execz .LBB0_3
; %bb.1:
	s_load_b32 s0, s[0:1], 0xc
	v_and_b32_e32 v0, 0x3ff, v0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s0, s0, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[5:6], null, s14, s0, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v3, v5
	v_cmp_gt_u64_e32 vcc_lo, s[8:9], v[3:4]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_3
; %bb.2:
	v_mad_u64_u32 v[5:6], null, v1, s8, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v0, v6
	v_mad_u64_u32 v[6:7], null, v1, s9, v[0:1]
	v_lshlrev_b64 v[7:8], 2, v[3:4]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[5:6], 2, v[5:6]
	v_add_co_u32 v0, vcc_lo, s4, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v6, vcc_lo
	v_add_co_u32 v4, vcc_lo, v0, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v5, vcc_lo, v5, v8, vcc_lo
	global_load_b32 v7, v[4:5], off
	v_mad_u64_u32 v[4:5], null, v3, s10, 0
	v_mov_b32_e32 v0, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[5:6], null, v3, s11, v[0:1]
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	v_lshlrev_b64 v[3:4], 2, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s6, v3
	v_add_co_ci_u32_e32 v3, vcc_lo, s7, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v2, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, v3, v1, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b32 v[0:1], v7, off
.LBB0_3:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _ZN5blas18cudaBlas14naiveTransposeEPfS1_mm
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 9
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_ZN5blas18cudaBlas14naiveTransposeEPfS1_mm, .Lfunc_end0-_ZN5blas18cudaBlas14naiveTransposeEPfS1_mm
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 320
; NumSgprs: 18
; NumVgprs: 9
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 9
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_ZN5blas18cudaBlas9naiveCopyEPfS1_mm ; -- Begin function _ZN5blas18cudaBlas9naiveCopyEPfS1_mm
	.globl	_ZN5blas18cudaBlas9naiveCopyEPfS1_mm
	.p2align	8
	.type	_ZN5blas18cudaBlas9naiveCopyEPfS1_mm,@function
_ZN5blas18cudaBlas9naiveCopyEPfS1_mm:   ; @_ZN5blas18cudaBlas9naiveCopyEPfS1_mm
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x2c
	s_load_b256 s[4:11], s[0:1], 0x0
	v_bfe_u32 v4, v0, 10, 10
	s_add_u32 s0, s0, 32
	s_addc_u32 s1, s1, 0
	v_mov_b32_e32 v3, 0
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s2, s2, 16
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[4:5]
	v_mov_b32_e32 v2, v3
	s_mov_b32 s2, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u64_e64 s[10:11], v[1:2]
	s_cbranch_execz .LBB1_3
; %bb.1:
	s_load_b32 s0, s[0:1], 0xc
	v_and_b32_e32 v0, 0x3ff, v0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s0, s0, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[4:5], null, s14, s0, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v2, v4
	v_cmp_gt_u64_e32 vcc_lo, s[8:9], v[2:3]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB1_3
; %bb.2:
	v_mad_u64_u32 v[4:5], null, v1, s8, v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v0, v5
	v_mad_u64_u32 v[2:3], null, v1, s9, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v5, v2
	v_lshlrev_b64 v[0:1], 2, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s4, v0
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
	v_add_co_u32 v0, vcc_lo, s6, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
	global_load_b32 v2, v[2:3], off
	s_waitcnt vmcnt(0)
	global_store_b32 v[0:1], v2, off
.LBB1_3:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _ZN5blas18cudaBlas9naiveCopyEPfS1_mm
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 6
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_ZN5blas18cudaBlas9naiveCopyEPfS1_mm, .Lfunc_end1-_ZN5blas18cudaBlas9naiveCopyEPfS1_mm
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 244
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_ZN5blas18cudaBlas12transpose_32EPfS1_mm ; -- Begin function _ZN5blas18cudaBlas12transpose_32EPfS1_mm
	.globl	_ZN5blas18cudaBlas12transpose_32EPfS1_mm
	.p2align	8
	.type	_ZN5blas18cudaBlas12transpose_32EPfS1_mm,@function
_ZN5blas18cudaBlas12transpose_32EPfS1_mm: ; @_ZN5blas18cudaBlas12transpose_32EPfS1_mm
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x2c
	s_load_b256 s[4:11], s[0:1], 0x0
	v_and_b32_e32 v3, 0x3ff, v0
	s_add_u32 s0, s0, 32
	s_addc_u32 s1, s1, 0
	v_bfe_u32 v0, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s14, s2, v[3:4]
	v_mov_b32_e32 v2, 0
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_u64_e64 s[8:9], v[1:2]
	s_cbranch_execz .LBB2_3
; %bb.1:
	s_load_b32 s0, s[0:1], 0xc
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s0, s0, 16
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[4:5], null, s15, s0, v[0:1]
	v_mov_b32_e32 v5, v2
	v_cmp_gt_u64_e32 vcc_lo, s[10:11], v[4:5]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB2_3
; %bb.2:
	v_mad_u64_u32 v[5:6], null, v4, s8, v[1:2]
	v_mov_b32_e32 v6, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 2, v[5:6]
	v_add_co_u32 v4, vcc_lo, s4, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
	global_load_b32 v1, v[4:5], off
	v_lshlrev_b32_e32 v4, 2, v3
	v_mad_u32_u24 v4, 0x84, v0, v4
	s_waitcnt vmcnt(0)
	ds_store_b32 v4, v1
.LBB2_3:
	s_or_b32 exec_lo, exec_lo, s2
	v_lshl_add_u32 v1, s15, 5, v3
	v_lshl_add_u32 v4, s14, 5, v0
	v_mov_b32_e32 v5, v2
	s_waitcnt lgkmcnt(0)
	s_barrier
	v_cmp_gt_u64_e32 vcc_lo, s[10:11], v[1:2]
	buffer_gl0_inv
	v_cmp_gt_u64_e64 s0, s[8:9], v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, vcc_lo, s0
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB2_5
; %bb.4:
	v_mad_u64_u32 v[5:6], null, v4, s10, 0
	v_lshlrev_b32_e32 v0, 2, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mad_u32_u24 v0, 0x84, v3, v0
	v_mad_u64_u32 v[7:8], null, v4, s11, v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v6, v7
	ds_load_b32 v7, v0
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	v_lshlrev_b64 v[3:4], 2, v[5:6]
	v_add_co_u32 v2, vcc_lo, s6, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s7, v4, vcc_lo
	v_add_co_u32 v0, vcc_lo, v2, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, v3, v1, vcc_lo
	s_waitcnt lgkmcnt(0)
	global_store_b32 v[0:1], v7, off
.LBB2_5:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _ZN5blas18cudaBlas12transpose_32EPfS1_mm
		.amdhsa_group_segment_fixed_size 4224
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 9
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_ZN5blas18cudaBlas12transpose_32EPfS1_mm, .Lfunc_end2-_ZN5blas18cudaBlas12transpose_32EPfS1_mm
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 400
; NumSgprs: 18
; NumVgprs: 9
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 4224 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 9
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_ZN5blas18cudaBlas12transpose_16EPfS1_mm ; -- Begin function _ZN5blas18cudaBlas12transpose_16EPfS1_mm
	.globl	_ZN5blas18cudaBlas12transpose_16EPfS1_mm
	.p2align	8
	.type	_ZN5blas18cudaBlas12transpose_16EPfS1_mm,@function
_ZN5blas18cudaBlas12transpose_16EPfS1_mm: ; @_ZN5blas18cudaBlas12transpose_16EPfS1_mm
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x2c
	s_load_b256 s[4:11], s[0:1], 0x0
	v_and_b32_e32 v3, 0x3ff, v0
	s_add_u32 s0, s0, 32
	s_addc_u32 s1, s1, 0
	v_bfe_u32 v0, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s14, s2, v[3:4]
	v_mov_b32_e32 v2, 0
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_u64_e64 s[8:9], v[1:2]
	s_cbranch_execz .LBB3_3
; %bb.1:
	s_load_b32 s0, s[0:1], 0xc
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s0, s0, 16
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[4:5], null, s15, s0, v[0:1]
	v_mov_b32_e32 v5, v2
	v_cmp_gt_u64_e32 vcc_lo, s[10:11], v[4:5]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB3_3
; %bb.2:
	v_mad_u64_u32 v[5:6], null, v4, s8, v[1:2]
	v_mov_b32_e32 v6, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 2, v[5:6]
	v_add_co_u32 v4, vcc_lo, s4, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
	global_load_b32 v1, v[4:5], off
	v_lshlrev_b32_e32 v4, 2, v3
	v_mad_u32_u24 v4, 0x44, v0, v4
	s_waitcnt vmcnt(0)
	ds_store_b32 v4, v1
.LBB3_3:
	s_or_b32 exec_lo, exec_lo, s2
	v_lshl_add_u32 v1, s15, 4, v3
	v_lshl_add_u32 v4, s14, 4, v0
	v_mov_b32_e32 v5, v2
	s_waitcnt lgkmcnt(0)
	s_barrier
	v_cmp_gt_u64_e32 vcc_lo, s[10:11], v[1:2]
	buffer_gl0_inv
	v_cmp_gt_u64_e64 s0, s[8:9], v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, vcc_lo, s0
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB3_5
; %bb.4:
	v_mad_u64_u32 v[5:6], null, v4, s10, 0
	v_lshlrev_b32_e32 v0, 2, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mad_u32_u24 v0, 0x44, v3, v0
	v_mad_u64_u32 v[7:8], null, v4, s11, v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v6, v7
	ds_load_b32 v7, v0
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	v_lshlrev_b64 v[3:4], 2, v[5:6]
	v_add_co_u32 v2, vcc_lo, s6, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s7, v4, vcc_lo
	v_add_co_u32 v0, vcc_lo, v2, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, v3, v1, vcc_lo
	s_waitcnt lgkmcnt(0)
	global_store_b32 v[0:1], v7, off
.LBB3_5:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _ZN5blas18cudaBlas12transpose_16EPfS1_mm
		.amdhsa_group_segment_fixed_size 1088
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 9
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end3:
	.size	_ZN5blas18cudaBlas12transpose_16EPfS1_mm, .Lfunc_end3-_ZN5blas18cudaBlas12transpose_16EPfS1_mm
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 400
; NumSgprs: 18
; NumVgprs: 9
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 1088 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 9
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_ZN5blas18cudaBlas20transposeRowBlock_32EPfS1_mm ; -- Begin function _ZN5blas18cudaBlas20transposeRowBlock_32EPfS1_mm
	.globl	_ZN5blas18cudaBlas20transposeRowBlock_32EPfS1_mm
	.p2align	8
	.type	_ZN5blas18cudaBlas20transposeRowBlock_32EPfS1_mm,@function
_ZN5blas18cudaBlas20transposeRowBlock_32EPfS1_mm: ; @_ZN5blas18cudaBlas20transposeRowBlock_32EPfS1_mm
; %bb.0:
	s_load_b32 s5, s[0:1], 0x20
	v_bfe_u32 v2, v0, 10, 10
	s_lshl_b32 s6, s15, 5
	s_load_b128 s[0:3], s[0:1], 0x0
	v_and_b32_e32 v3, 0x3ff, v0
	s_lshl_b32 s7, s14, 5
	v_add_nc_u32_e32 v1, s6, v2
	s_mov_b32 s8, -8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b32_e32 v0, 2, v3
	v_mad_u32_u24 v4, 0x84, v2, v0
	s_waitcnt lgkmcnt(0)
	v_mul_lo_u32 v1, s5, v1
	s_lshl_b32 s4, s5, 8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b32_e32 v1, 5, v1
	v_add3_u32 v0, v3, v1, s7
	v_mov_b32_e32 v1, 0
.LBB4_1:                                ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_lshlrev_b64 v[5:6], 2, v[0:1]
	v_add_nc_u32_e32 v0, s4, v0
	s_add_i32 s8, s8, 8
	s_cmp_gt_u32 s8, 23
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v5, vcc_lo, s0, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, s1, v6, vcc_lo
	global_load_b32 v5, v[5:6], off
	s_waitcnt vmcnt(0)
	ds_store_b32 v4, v5
	v_add_nc_u32_e32 v4, 0x420, v4
	s_cbranch_scc0 .LBB4_1
; %bb.2:
	v_dual_mov_b32 v1, 0 :: v_dual_add_nc_u32 v0, s7, v2
	v_lshlrev_b32_e32 v2, 2, v2
	s_waitcnt lgkmcnt(0)
	s_barrier
	s_delay_alu instid0(VALU_DEP_2)
	v_mul_lo_u32 v0, s5, v0
	buffer_gl0_inv
	v_mad_u32_u24 v6, 0x84, v3, v2
	ds_load_2addr_b32 v[4:5], v6 offset1:8
	ds_load_2addr_b32 v[6:7], v6 offset0:16 offset1:24
	v_lshlrev_b32_e32 v0, 5, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v0, s6, v3, v0
	v_lshlrev_b64 v[2:3], 2, v[0:1]
	v_add_nc_u32_e32 v0, s4, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_lshlrev_b64 v[8:9], 2, v[0:1]
	v_add_nc_u32_e32 v0, s4, v0
	v_add_co_u32 v2, vcc_lo, s2, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[10:11], 2, v[0:1]
	v_add_nc_u32_e32 v0, s4, v0
	v_add_co_u32 v8, vcc_lo, s2, v8
	v_add_co_ci_u32_e32 v9, vcc_lo, s3, v9, vcc_lo
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	v_add_co_u32 v10, vcc_lo, s2, v10
	v_add_co_ci_u32_e32 v11, vcc_lo, s3, v11, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v0, vcc_lo, s2, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
	s_waitcnt lgkmcnt(1)
	s_clause 0x1
	global_store_b32 v[2:3], v4, off
	global_store_b32 v[8:9], v5, off
	s_waitcnt lgkmcnt(0)
	s_clause 0x1
	global_store_b32 v[10:11], v6, off
	global_store_b32 v[0:1], v7, off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _ZN5blas18cudaBlas20transposeRowBlock_32EPfS1_mm
		.amdhsa_group_segment_fixed_size 4224
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 12
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end4:
	.size	_ZN5blas18cudaBlas20transposeRowBlock_32EPfS1_mm, .Lfunc_end4-_ZN5blas18cudaBlas20transposeRowBlock_32EPfS1_mm
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 424
; NumSgprs: 18
; NumVgprs: 12
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 4224 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 12
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_ZN5blas18cudaBlas20transposeRowBlock_16EPfS1_mm ; -- Begin function _ZN5blas18cudaBlas20transposeRowBlock_16EPfS1_mm
	.globl	_ZN5blas18cudaBlas20transposeRowBlock_16EPfS1_mm
	.p2align	8
	.type	_ZN5blas18cudaBlas20transposeRowBlock_16EPfS1_mm,@function
_ZN5blas18cudaBlas20transposeRowBlock_16EPfS1_mm: ; @_ZN5blas18cudaBlas20transposeRowBlock_16EPfS1_mm
; %bb.0:                                ; %.critedge
	s_load_b32 s4, s[0:1], 0x20
	v_bfe_u32 v6, v0, 10, 10
	s_lshl_b32 s5, s15, 4
	s_load_b128 s[0:3], s[0:1], 0x0
	v_and_b32_e32 v7, 0x3ff, v0
	s_lshl_b32 s7, s14, 4
	v_add_nc_u32_e32 v1, s5, v6
	s_waitcnt lgkmcnt(0)
	s_lshl_b32 s6, s4, 4
	s_lshl_b32 s4, s4, 7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v2, v1, s6
	v_add3_u32 v0, s7, v7, v2
	v_mov_b32_e32 v1, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[0:1]
	v_add_nc_u32_e32 v0, s4, v0
	v_lshlrev_b64 v[4:5], 2, v[0:1]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v2, vcc_lo, s0, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
	v_add_nc_u32_e32 v0, s7, v6
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_u32 v4, vcc_lo, s0, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
	s_clause 0x1
	global_load_b32 v2, v[2:3], off
	global_load_b32 v3, v[4:5], off
	v_lshlrev_b32_e32 v4, 2, v7
	v_mul_lo_u32 v0, v0, s6
	v_lshlrev_b32_e32 v5, 2, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u32_u24 v4, 0x44, v6, v4
	v_mad_u32_u24 v5, 0x44, v7, v5
	s_delay_alu instid0(VALU_DEP_4)
	v_add3_u32 v0, s5, v7, v0
	s_waitcnt vmcnt(0)
	ds_store_2addr_b32 v4, v2, v3 offset1:136
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_2addr_b32 v[2:3], v5 offset1:8
	v_lshlrev_b64 v[4:5], 2, v[0:1]
	v_add_nc_u32_e32 v0, s4, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	v_add_co_u32 v4, vcc_lo, s2, v4
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
	v_add_co_u32 v0, vcc_lo, s2, v0
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
	s_waitcnt lgkmcnt(0)
	s_clause 0x1
	global_store_b32 v[4:5], v2, off
	global_store_b32 v[0:1], v3, off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _ZN5blas18cudaBlas20transposeRowBlock_16EPfS1_mm
		.amdhsa_group_segment_fixed_size 1088
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 8
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end5:
	.size	_ZN5blas18cudaBlas20transposeRowBlock_16EPfS1_mm, .Lfunc_end5-_ZN5blas18cudaBlas20transposeRowBlock_16EPfS1_mm
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 344
; NumSgprs: 18
; NumVgprs: 8
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 1088 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 8
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_ZN5blas18cudaBlas13MatrixCopy_32EPfS1_mm ; -- Begin function _ZN5blas18cudaBlas13MatrixCopy_32EPfS1_mm
	.globl	_ZN5blas18cudaBlas13MatrixCopy_32EPfS1_mm
	.p2align	8
	.type	_ZN5blas18cudaBlas13MatrixCopy_32EPfS1_mm,@function
_ZN5blas18cudaBlas13MatrixCopy_32EPfS1_mm: ; @_ZN5blas18cudaBlas13MatrixCopy_32EPfS1_mm
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x2c
	s_load_b256 s[4:11], s[0:1], 0x0
	v_and_b32_e32 v1, 0x3ff, v0
	s_add_u32 s0, s0, 32
	s_addc_u32 s1, s1, 0
	v_bfe_u32 v0, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[2:3], null, s14, s2, v[1:2]
	v_mov_b32_e32 v3, 0
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_u64_e64 s[8:9], v[2:3]
	s_cbranch_execz .LBB6_3
; %bb.1:
	s_load_b32 s0, s[0:1], 0xc
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s0, s0, 16
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[4:5], null, s15, s0, v[0:1]
	v_mov_b32_e32 v5, v3
	v_cmp_gt_u64_e32 vcc_lo, s[10:11], v[4:5]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB6_3
; %bb.2:
	v_mad_u64_u32 v[5:6], null, v4, s8, v[2:3]
	v_mov_b32_e32 v6, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 2, v[5:6]
	v_add_co_u32 v4, vcc_lo, s4, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
	global_load_b32 v2, v[4:5], off
	v_lshlrev_b32_e32 v4, 2, v1
	v_mad_u32_u24 v4, 0x84, v0, v4
	s_waitcnt vmcnt(0)
	ds_store_b32 v4, v2
.LBB6_3:
	s_or_b32 exec_lo, exec_lo, s2
	v_lshl_add_u32 v2, s15, 5, v1
	v_lshl_add_u32 v4, s14, 5, v0
	v_mov_b32_e32 v5, v3
	s_waitcnt lgkmcnt(0)
	s_barrier
	v_cmp_gt_u64_e32 vcc_lo, s[10:11], v[2:3]
	buffer_gl0_inv
	v_cmp_gt_u64_e64 s0, s[8:9], v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, vcc_lo, s0
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB6_5
; %bb.4:
	v_mad_u64_u32 v[6:7], null, v2, s8, 0
	v_lshlrev_b32_e32 v0, 2, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mad_u32_u24 v0, 0x84, v1, v0
	v_mov_b32_e32 v3, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[7:8], null, v2, s9, v[3:4]
	v_lshlrev_b64 v[2:3], 2, v[4:5]
	ds_load_b32 v8, v0
	v_lshlrev_b64 v[0:1], 2, v[6:7]
	v_add_co_u32 v0, vcc_lo, s6, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
	v_add_co_u32 v0, vcc_lo, v0, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo
	s_waitcnt lgkmcnt(0)
	global_store_b32 v[0:1], v8, off
.LBB6_5:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _ZN5blas18cudaBlas13MatrixCopy_32EPfS1_mm
		.amdhsa_group_segment_fixed_size 4224
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 9
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end6:
	.size	_ZN5blas18cudaBlas13MatrixCopy_32EPfS1_mm, .Lfunc_end6-_ZN5blas18cudaBlas13MatrixCopy_32EPfS1_mm
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 400
; NumSgprs: 18
; NumVgprs: 9
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 4224 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 9
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_ZN5blas18cudaBlas13MatrixCopy_16EPfS1_mm ; -- Begin function _ZN5blas18cudaBlas13MatrixCopy_16EPfS1_mm
	.globl	_ZN5blas18cudaBlas13MatrixCopy_16EPfS1_mm
	.p2align	8
	.type	_ZN5blas18cudaBlas13MatrixCopy_16EPfS1_mm,@function
_ZN5blas18cudaBlas13MatrixCopy_16EPfS1_mm: ; @_ZN5blas18cudaBlas13MatrixCopy_16EPfS1_mm
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x2c
	s_load_b256 s[4:11], s[0:1], 0x0
	v_and_b32_e32 v1, 0x3ff, v0
	s_add_u32 s0, s0, 32
	s_addc_u32 s1, s1, 0
	v_bfe_u32 v0, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[2:3], null, s14, s2, v[1:2]
	v_mov_b32_e32 v3, 0
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_u64_e64 s[8:9], v[2:3]
	s_cbranch_execz .LBB7_3
; %bb.1:
	s_load_b32 s0, s[0:1], 0xc
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s0, s0, 16
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[4:5], null, s15, s0, v[0:1]
	v_mov_b32_e32 v5, v3
	v_cmp_gt_u64_e32 vcc_lo, s[10:11], v[4:5]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB7_3
; %bb.2:
	v_mad_u64_u32 v[5:6], null, v4, s8, v[2:3]
	v_mov_b32_e32 v6, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 2, v[5:6]
	v_add_co_u32 v4, vcc_lo, s4, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
	global_load_b32 v2, v[4:5], off
	v_lshlrev_b32_e32 v4, 2, v1
	v_mad_u32_u24 v4, 0x84, v0, v4
	s_waitcnt vmcnt(0)
	ds_store_b32 v4, v2
.LBB7_3:
	s_or_b32 exec_lo, exec_lo, s2
	v_lshl_add_u32 v2, s15, 5, v1
	v_lshl_add_u32 v4, s14, 5, v0
	v_mov_b32_e32 v5, v3
	s_waitcnt lgkmcnt(0)
	s_barrier
	v_cmp_gt_u64_e32 vcc_lo, s[10:11], v[2:3]
	buffer_gl0_inv
	v_cmp_gt_u64_e64 s0, s[8:9], v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, vcc_lo, s0
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB7_5
; %bb.4:
	v_mad_u64_u32 v[6:7], null, v2, s8, 0
	v_lshlrev_b32_e32 v0, 2, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mad_u32_u24 v0, 0x84, v1, v0
	v_mov_b32_e32 v3, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[7:8], null, v2, s9, v[3:4]
	v_lshlrev_b64 v[2:3], 2, v[4:5]
	ds_load_b32 v8, v0
	v_lshlrev_b64 v[0:1], 2, v[6:7]
	v_add_co_u32 v0, vcc_lo, s6, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
	v_add_co_u32 v0, vcc_lo, v0, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo
	s_waitcnt lgkmcnt(0)
	global_store_b32 v[0:1], v8, off
.LBB7_5:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _ZN5blas18cudaBlas13MatrixCopy_16EPfS1_mm
		.amdhsa_group_segment_fixed_size 4224
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 9
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end7:
	.size	_ZN5blas18cudaBlas13MatrixCopy_16EPfS1_mm, .Lfunc_end7-_ZN5blas18cudaBlas13MatrixCopy_16EPfS1_mm
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 400
; NumSgprs: 18
; NumVgprs: 9
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 4224 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 9
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           8
        .value_kind:     by_value
      - .offset:         24
        .size:           8
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _ZN5blas18cudaBlas14naiveTransposeEPfS1_mm
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _ZN5blas18cudaBlas14naiveTransposeEPfS1_mm.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     9
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           8
        .value_kind:     by_value
      - .offset:         24
        .size:           8
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _ZN5blas18cudaBlas9naiveCopyEPfS1_mm
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _ZN5blas18cudaBlas9naiveCopyEPfS1_mm.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     6
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           8
        .value_kind:     by_value
      - .offset:         24
        .size:           8
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 4224
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _ZN5blas18cudaBlas12transpose_32EPfS1_mm
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _ZN5blas18cudaBlas12transpose_32EPfS1_mm.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     9
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           8
        .value_kind:     by_value
      - .offset:         24
        .size:           8
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 1088
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _ZN5blas18cudaBlas12transpose_16EPfS1_mm
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _ZN5blas18cudaBlas12transpose_16EPfS1_mm.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     9
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           8
        .value_kind:     by_value
      - .offset:         24
        .size:           8
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
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...

	.end_amdgpu_metadata
