#include <stdio.h>
#include <stdlib.h>
#include <assert.h>
#include <time.h>
#include <stdbool.h>
#include <cuda_runtime.h>

#define BLOCK_SIZE 16

///
/// function name: gpu_matrix_mult
///
/// description: dot product of two matrix (not only square)
/// 
/// parameters: 
///            &a GPU device pointer to a m X n matrix (A)
///            &b GPU device pointer to a n X k matrix (B)
///            &c GPU device output purpose pointer to a m X k matrix (C) 
///            to store the result
///
/// Note:
///   grid and block should be configured as:
///   dim3 dimGrid((k + BLOCK_SIZE - 1) / BLOCK_SIZE, 
///                (m + BLOCK_SIZE - 1) / BLOCK_SIZE);
///   dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE);
///
/// further speedup can be obtained by using shared memory to decrease 
/// global memory access times
/// return: none
///
__global__ void gpu_matrix_mult(float *d_a, float *d_b, 
                                float *d_result, int N) { 
  __shared__ int tile_a[BLOCK_SIZE][BLOCK_SIZE];
  __shared__ int tile_b[BLOCK_SIZE][BLOCK_SIZE];

  int row = blockIdx.y * BLOCK_SIZE + threadIdx.y;
  int col = blockIdx.x * BLOCK_SIZE + threadIdx.x;
  int idx;
  float tmp = 0.0;
  
  for (int sub = 0; sub < gridDim.x; ++sub) {
    idx = row * N + sub * BLOCK_SIZE + threadIdx.x;
    if(idx >= N*N) {
      /// n may not divisible by BLOCK_SIZE
      tile_a[threadIdx.y][threadIdx.x] = 0;
    } else {
      tile_a[threadIdx.y][threadIdx.x] = d_a[idx];
    }

    idx = (sub * BLOCK_SIZE + threadIdx.y) * N + col;
    if(idx >= N*N) {
      tile_b[threadIdx.y][threadIdx.x] = 0;
    } else {
      tile_b[threadIdx.y][threadIdx.x] = d_b[idx];
    }
    __syncthreads();

    for (int k = 0; k < BLOCK_SIZE; ++k) {
      tmp += tile_a[threadIdx.y][k] * tile_b[k][threadIdx.x];
    }
    __syncthreads();
  }
  if(row < N && col < N) {
    d_result[row * N + col] = tmp;
  }
} 

/// 
/// function name: cpu_matrix_mult
/// 
/// description: dot product of two matrix (not only square) in CPU, 
///              for validating GPU results
/// 
/// parameters: 
///             &a CPU host pointer to a m X n matrix (A)
///             &b CPU host pointer to a n X k matrix (B)
///             &c CPU host output purpose pointer to a m X k matrix (C) 
///             to store the result
/// return: none
/// 
void cpu_matrix_mult(float *h_a, float *h_b, float *h_result, int N) {
  int i,j,k;
  #pragma omp parallel for schedule(dynamic,50) collapse(2) private(i,j,k) shared(h_a,h_b,h_result)
  for( j=0;j<N;j++)
    for(i=0;i<N;i++)
      for(k=0;k<N;k++)
        h_result[j*N+i] += h_a[j*N+k]*h_b[k*N+i];
}

///
/// function name: main
/// 
/// description: test and compare
/// 
/// parameters: 
///             none
/// 
/// return: none
///
int main(int argc, char const *argv[])
{
  int N=2048;
  /// Fixed seed for illustration.
  srand(3333);

  /// allocate memory in host RAM, h_cc is used to store CPU result
  float *h_a, *h_b, *h_c, *h_cc;
  cudaMallocHost((void **) &h_a, sizeof(float)*N*N);
  cudaMallocHost((void **) &h_b, sizeof(float)*N*N);
  cudaMallocHost((void **) &h_c, sizeof(float)*N*N);
  cudaMallocHost((void **) &h_cc, sizeof(float)*N*N);

  /// random initialize matrix A
  for (int j = 0; j < N; ++j) {
    for (int i = 0; i < N; ++i) {
      h_a[j*N + i] = rand() % 1024;
    }
  }

  /// random initialize matrix B
  for (int j = 0; j < N; ++j) {
    for (int i = 0; i < N; ++i) {
      h_b[j*N + i] = rand() % 1024;
    }
  }

  /// c = 0
  for (int j = 0; j < N; ++j) {
    for (int i = 0; i < N; ++i) {
      h_c[j*N + i] = 0.0;
    }
  }

  float gpu_elapsed_time_ms, cpu_elapsed_time_ms;

  /// some events to count the execution time
  cudaEvent_t start, stop;
  cudaEventCreate(&start);
  cudaEventCreate(&stop);

  /// start to count execution time of GPU version
  cudaEventRecord(start, 0);
  
  /// Allocate memory space on the device 
  float *d_a, *d_b, *d_c;
  cudaMalloc((void **) &d_a, sizeof(float)*N*N);
  cudaMalloc((void **) &d_b, sizeof(float)*N*N);
  cudaMalloc((void **) &d_c, sizeof(float)*N*N);

  /// copy matrix A and B from host to device memory
  cudaMemcpy(d_a, h_a, sizeof(int)*N*N, cudaMemcpyHostToDevice);
  cudaMemcpy(d_b, h_b, sizeof(int)*N*N, cudaMemcpyHostToDevice);

  unsigned int grid_rows = (N + BLOCK_SIZE - 1) / BLOCK_SIZE;
  unsigned int grid_cols = (N + BLOCK_SIZE - 1) / BLOCK_SIZE;
  
  dim3 dimGrid(grid_cols, grid_rows);
  dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE);

  /// Launch kernel 
  gpu_matrix_mult<<<dimGrid, dimBlock>>>(d_a, d_b, d_c, N);    
  
  /// Transfer results from device to host 
  cudaMemcpy(h_c, d_c, sizeof(int)*N*N, cudaMemcpyDeviceToHost);
  cudaThreadSynchronize();
    
  /// time counting terminate
  cudaEventRecord(stop, 0);
  cudaEventSynchronize(stop);

  /// compute time elapse on GPU computing
  cudaEventElapsedTime(&gpu_elapsed_time_ms, start, stop);
  printf("Time elapsed on GPU: %f ms.\n\n", gpu_elapsed_time_ms);

  /// start the CPU version
  cudaEventRecord(start, 0);

  cpu_matrix_mult(h_a, h_b, h_cc, N);

  cudaEventRecord(stop, 0);
  cudaEventSynchronize(stop);
  cudaEventElapsedTime(&cpu_elapsed_time_ms, start, stop);
  printf("Time elapsed on on CPU: %f ms.\n\n", cpu_elapsed_time_ms);

  /// validate results computed by GPU
  bool all_ok = true;
  for (int j = 0; j < N; ++j) {
    for (int i = 0; i < N; ++i) {
      if(fabs(h_c[j*N + i] - h_cc[j*N + i]) > 1.e-4) {
        all_ok = false;
      }
    }
  }

  /// roughly compute speedup
  if(all_ok) {
    printf("all results are correct!!!, speedup = %f\n", 
            cpu_elapsed_time_ms / gpu_elapsed_time_ms);
  } else {
    printf("incorrect results\n");
  }

  /// free memory
  cudaFree(d_a);
  cudaFree(d_b);
  cudaFree(d_c);
  cudaFreeHost(h_a);
  cudaFreeHost(h_b);
  cudaFreeHost(h_c);
  cudaFreeHost(h_cc);
  return 0;
}

	.file	"tmpxft_00282551_00000000-6_matrix_cuda_opt_sol.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2031:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z15cpu_matrix_multPfS_S_i
	.type	_Z15cpu_matrix_multPfS_S_i, @function
_Z15cpu_matrix_multPfS_S_i:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	movq	%rdx, %r10
	movq	%rdi, %r8
	xorl	%edx, %edx
	pushq	%r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	pushq	%rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	xorl	%ebp, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	movq	%rsi, %rbx
	movslq	%ecx, %rsi
	movq	%rsi, %rax
	salq	$2, %rsi
.L3:
	cmpl	%eax, %ebp
	jge	.L2
	movq	%rbx, %r11
	leaq	(%r10,%rdx), %rcx
	leaq	(%r8,%rdx), %r13
	xorl	%r9d, %r9d
.L7:
	movq	%r11, %r12
	xorl	%edi, %edi
.L4:
	movss	0(%r13,%rdi,4), %xmm0
	mulss	(%r12), %xmm0
	incq	%rdi
	addq	%rsi, %r12
	addss	(%rcx), %xmm0
	movss	%xmm0, (%rcx)
	cmpl	%edi, %eax
	jg	.L4
	incl	%r9d
	addq	$4, %r11
	addq	$4, %rcx
	cmpl	%r9d, %eax
	jne	.L7
	incl	%ebp
	addq	%rsi, %rdx
	jmp	.L3
.L2:
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2027:
	.size	_Z15cpu_matrix_multPfS_S_i, .-_Z15cpu_matrix_multPfS_S_i
	.globl	_Z40__device_stub__Z15gpu_matrix_multPfS_S_iPfS_S_i
	.type	_Z40__device_stub__Z15gpu_matrix_multPfS_S_iPfS_S_i, @function
_Z40__device_stub__Z15gpu_matrix_multPfS_S_iPfS_S_i:
.LFB2053:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 4(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L11
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z15gpu_matrix_multPfS_S_i(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L11:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L13
	call	__stack_chk_fail@PLT
.L13:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2053:
	.size	_Z40__device_stub__Z15gpu_matrix_multPfS_S_iPfS_S_i, .-_Z40__device_stub__Z15gpu_matrix_multPfS_S_iPfS_S_i
	.globl	_Z15gpu_matrix_multPfS_S_i
	.type	_Z15gpu_matrix_multPfS_S_i, @function
_Z15gpu_matrix_multPfS_S_i:
.LFB2054:
	.cfi_startproc
	endbr64
	jmp	_Z40__device_stub__Z15gpu_matrix_multPfS_S_iPfS_S_i
	.cfi_endproc
.LFE2054:
	.size	_Z15gpu_matrix_multPfS_S_i, .-_Z15gpu_matrix_multPfS_S_i
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"Time elapsed on GPU: %f ms.\n\n"
.LC1:
	.string	"Time elapsed on on CPU: %f ms.\n\n"
.LC4:
	.string	"all results are correct!!!, speedup = %f\n"
.LC5:
	.string	"incorrect results\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2028:
	.cfi_startproc
	endbr64
	pushq	%r12
	.cfi_def_cfa_offset 16
	.cfi_offset 12, -16
	movl	$3333, %edi
	movl	$1024, %r12d
	pushq	%rbp
	.cfi_def_cfa_offset 24
	.cfi_offset 6, -24
	xorl	%ebp, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset 3, -32
	subq	$112, %rsp
	.cfi_def_cfa_offset 144
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	call	srand@PLT
	leaq	8(%rsp), %rdi
	movl	$16777216, %esi
	call	cudaMallocHost@PLT
	leaq	16(%rsp), %rdi
	movl	$16777216, %esi
	call	cudaMallocHost@PLT
	leaq	24(%rsp), %rdi
	movl	$16777216, %esi
	call	cudaMallocHost@PLT
	leaq	32(%rsp), %rdi
	movl	$16777216, %esi
	call	cudaMallocHost@PLT
.L17:
	xorl	%ebx, %ebx
.L18:
	call	rand@PLT
	leaq	0(,%rbx,4), %rcx
	incq	%rbx
	addq	8(%rsp), %rcx
	cltd
	idivl	%r12d
	cvtsi2ssl	%edx, %xmm0
	movss	%xmm0, (%rcx,%rbp)
	cmpq	$2048, %rbx
	jne	.L18
	addq	$8192, %rbp
	cmpq	$16777216, %rbp
	jne	.L17
	xorl	%ebp, %ebp
	movl	$1024, %r12d
.L19:
	xorl	%ebx, %ebx
.L20:
	call	rand@PLT
	leaq	0(,%rbx,4), %rcx
	incq	%rbx
	addq	16(%rsp), %rcx
	cltd
	idivl	%r12d
	cvtsi2ssl	%edx, %xmm0
	movss	%xmm0, (%rcx,%rbp)
	cmpq	$2048, %rbx
	jne	.L20
	addq	$8192, %rbp
	cmpq	$16777216, %rbp
	jne	.L19
	movq	24(%rsp), %rdi
	xorl	%eax, %eax
	movl	$4194304, %ecx
	rep stosl
	leaq	40(%rsp), %rdi
	call	cudaEventCreate@PLT
	leaq	48(%rsp), %rdi
	call	cudaEventCreate@PLT
	movq	40(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	leaq	56(%rsp), %rdi
	movl	$16777216, %esi
	call	cudaMalloc@PLT
	leaq	64(%rsp), %rdi
	movl	$16777216, %esi
	call	cudaMalloc@PLT
	leaq	72(%rsp), %rdi
	movl	$16777216, %esi
	call	cudaMalloc@PLT
	movq	8(%rsp), %rsi
	movq	56(%rsp), %rdi
	movl	$1, %ecx
	movl	$16777216, %edx
	call	cudaMemcpy@PLT
	movq	16(%rsp), %rsi
	movq	64(%rsp), %rdi
	movl	$1, %ecx
	movl	$16777216, %edx
	call	cudaMemcpy@PLT
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$1, %ecx
	movabsq	$549755814016, %rdi
	movl	$1, %esi
	movabsq	$68719476752, %rdx
	movl	$1, 88(%rsp)
	movq	%rdi, 80(%rsp)
	movq	%rdx, 92(%rsp)
	movl	$1, 100(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L21
	movq	72(%rsp), %rdx
	movq	64(%rsp), %rsi
	movl	$2048, %ecx
	movq	56(%rsp), %rdi
	call	_Z40__device_stub__Z15gpu_matrix_multPfS_S_iPfS_S_i
.L21:
	movq	72(%rsp), %rsi
	movq	24(%rsp), %rdi
	movl	$2, %ecx
	movl	$16777216, %edx
	call	cudaMemcpy@PLT
	call	cudaThreadSynchronize@PLT
	movq	48(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movq	48(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movq	48(%rsp), %rdx
	movq	40(%rsp), %rsi
	movq	%rsp, %rdi
	call	cudaEventElapsedTime@PLT
	leaq	.LC0(%rip), %rsi
	movl	$2, %edi
	movb	$1, %al
	cvtss2sd	(%rsp), %xmm0
	call	__printf_chk@PLT
	movq	40(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movq	32(%rsp), %rdx
	movq	16(%rsp), %rsi
	movl	$2048, %ecx
	movq	8(%rsp), %rdi
	call	_Z15cpu_matrix_multPfS_S_i
	movq	48(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movq	48(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movq	48(%rsp), %rdx
	movq	40(%rsp), %rsi
	leaq	4(%rsp), %rdi
	call	cudaEventElapsedTime@PLT
	movl	$2, %edi
	movb	$1, %al
	leaq	.LC1(%rip), %rsi
	cvtss2sd	4(%rsp), %xmm0
	call	__printf_chk@PLT
	xorl	%edx, %edx
	movb	$1, %cl
	movq	24(%rsp), %rdi
	movq	32(%rsp), %r8
	xorl	%r9d, %r9d
	movss	.LC2(%rip), %xmm1
	movsd	.LC3(%rip), %xmm2
.L23:
	movq	%rdx, %rax
	xorl	%esi, %esi
.L25:
	movss	(%rdi,%rax), %xmm0
	subss	(%r8,%rax), %xmm0
	andps	%xmm1, %xmm0
	cvtss2sd	%xmm0, %xmm0
	ucomisd	%xmm2, %xmm0
	cmova	%r9d, %ecx
	incl	%esi
	addq	$4, %rax
	cmpl	$2048, %esi
	jne	.L25
	addq	$8192, %rdx
	cmpq	$16777216, %rdx
	jne	.L23
	testb	%cl, %cl
	je	.L27
	leaq	.LC4(%rip), %rsi
	movl	$2, %edi
	movb	$1, %al
	movss	4(%rsp), %xmm0
	divss	(%rsp), %xmm0
	cvtss2sd	%xmm0, %xmm0
	call	__printf_chk@PLT
	jmp	.L28
.L27:
	leaq	.LC5(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
.L28:
	movq	56(%rsp), %rdi
	call	cudaFree@PLT
	movq	64(%rsp), %rdi
	call	cudaFree@PLT
	movq	72(%rsp), %rdi
	call	cudaFree@PLT
	movq	8(%rsp), %rdi
	call	cudaFreeHost@PLT
	movq	16(%rsp), %rdi
	call	cudaFreeHost@PLT
	movq	24(%rsp), %rdi
	call	cudaFreeHost@PLT
	movq	32(%rsp), %rdi
	call	cudaFreeHost@PLT
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L29
	call	__stack_chk_fail@PLT
.L29:
	addq	$112, %rsp
	.cfi_def_cfa_offset 32
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2028:
	.size	main, .-main
	.section	.rodata.str1.1
.LC6:
	.string	"_Z15gpu_matrix_multPfS_S_i"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2056:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC6(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z15gpu_matrix_multPfS_S_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2056:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst16,"aM",@progbits,16
	.align 16
.LC2:
	.long	2147483647
	.long	0
	.long	0
	.long	0
	.section	.rodata.cst8,"aM",@progbits,8
	.align 8
.LC3:
	.long	-350469331
	.long	1058682594
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <stdio.h>
#include <stdlib.h>
#include <assert.h>
#include <time.h>
#include <stdbool.h>
#include <hip/hip_runtime.h>

#define BLOCK_SIZE 16

///
/// function name: gpu_matrix_mult
///
/// description: dot product of two matrix (not only square)
/// 
/// parameters: 
///            &a GPU device pointer to a m X n matrix (A)
///            &b GPU device pointer to a n X k matrix (B)
///            &c GPU device output purpose pointer to a m X k matrix (C) 
///            to store the result
///
/// Note:
///   grid and block should be configured as:
///   dim3 dimGrid((k + BLOCK_SIZE - 1) / BLOCK_SIZE, 
///                (m + BLOCK_SIZE - 1) / BLOCK_SIZE);
///   dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE);
///
/// further speedup can be obtained by using shared memory to decrease 
/// global memory access times
/// return: none
///
__global__ void gpu_matrix_mult(float *d_a, float *d_b, 
                                float *d_result, int N) { 
  __shared__ int tile_a[BLOCK_SIZE][BLOCK_SIZE];
  __shared__ int tile_b[BLOCK_SIZE][BLOCK_SIZE];

  int row = blockIdx.y * BLOCK_SIZE + threadIdx.y;
  int col = blockIdx.x * BLOCK_SIZE + threadIdx.x;
  int idx;
  float tmp = 0.0;
  
  for (int sub = 0; sub < gridDim.x; ++sub) {
    idx = row * N + sub * BLOCK_SIZE + threadIdx.x;
    if(idx >= N*N) {
      /// n may not divisible by BLOCK_SIZE
      tile_a[threadIdx.y][threadIdx.x] = 0;
    } else {
      tile_a[threadIdx.y][threadIdx.x] = d_a[idx];
    }

    idx = (sub * BLOCK_SIZE + threadIdx.y) * N + col;
    if(idx >= N*N) {
      tile_b[threadIdx.y][threadIdx.x] = 0;
    } else {
      tile_b[threadIdx.y][threadIdx.x] = d_b[idx];
    }
    __syncthreads();

    for (int k = 0; k < BLOCK_SIZE; ++k) {
      tmp += tile_a[threadIdx.y][k] * tile_b[k][threadIdx.x];
    }
    __syncthreads();
  }
  if(row < N && col < N) {
    d_result[row * N + col] = tmp;
  }
} 

/// 
/// function name: cpu_matrix_mult
/// 
/// description: dot product of two matrix (not only square) in CPU, 
///              for validating GPU results
/// 
/// parameters: 
///             &a CPU host pointer to a m X n matrix (A)
///             &b CPU host pointer to a n X k matrix (B)
///             &c CPU host output purpose pointer to a m X k matrix (C) 
///             to store the result
/// return: none
/// 
void cpu_matrix_mult(float *h_a, float *h_b, float *h_result, int N) {
  int i,j,k;
  #pragma omp parallel for schedule(dynamic,50) collapse(2) private(i,j,k) shared(h_a,h_b,h_result)
  for( j=0;j<N;j++)
    for(i=0;i<N;i++)
      for(k=0;k<N;k++)
        h_result[j*N+i] += h_a[j*N+k]*h_b[k*N+i];
}

///
/// function name: main
/// 
/// description: test and compare
/// 
/// parameters: 
///             none
/// 
/// return: none
///
int main(int argc, char const *argv[])
{
  int N=2048;
  /// Fixed seed for illustration.
  srand(3333);

  /// allocate memory in host RAM, h_cc is used to store CPU result
  float *h_a, *h_b, *h_c, *h_cc;
  hipHostMalloc((void **) &h_a, sizeof(float)*N*N, hipHostMallocDefault);
  hipHostMalloc((void **) &h_b, sizeof(float)*N*N, hipHostMallocDefault);
  hipHostMalloc((void **) &h_c, sizeof(float)*N*N, hipHostMallocDefault);
  hipHostMalloc((void **) &h_cc, sizeof(float)*N*N, hipHostMallocDefault);

  /// random initialize matrix A
  for (int j = 0; j < N; ++j) {
    for (int i = 0; i < N; ++i) {
      h_a[j*N + i] = rand() % 1024;
    }
  }

  /// random initialize matrix B
  for (int j = 0; j < N; ++j) {
    for (int i = 0; i < N; ++i) {
      h_b[j*N + i] = rand() % 1024;
    }
  }

  /// c = 0
  for (int j = 0; j < N; ++j) {
    for (int i = 0; i < N; ++i) {
      h_c[j*N + i] = 0.0;
    }
  }

  float gpu_elapsed_time_ms, cpu_elapsed_time_ms;

  /// some events to count the execution time
  hipEvent_t start, stop;
  hipEventCreate(&start);
  hipEventCreate(&stop);

  /// start to count execution time of GPU version
  hipEventRecord(start, 0);
  
  /// Allocate memory space on the device 
  float *d_a, *d_b, *d_c;
  hipMalloc((void **) &d_a, sizeof(float)*N*N);
  hipMalloc((void **) &d_b, sizeof(float)*N*N);
  hipMalloc((void **) &d_c, sizeof(float)*N*N);

  /// copy matrix A and B from host to device memory
  hipMemcpy(d_a, h_a, sizeof(int)*N*N, hipMemcpyHostToDevice);
  hipMemcpy(d_b, h_b, sizeof(int)*N*N, hipMemcpyHostToDevice);

  unsigned int grid_rows = (N + BLOCK_SIZE - 1) / BLOCK_SIZE;
  unsigned int grid_cols = (N + BLOCK_SIZE - 1) / BLOCK_SIZE;
  
  dim3 dimGrid(grid_cols, grid_rows);
  dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE);

  /// Launch kernel 
  gpu_matrix_mult<<<dimGrid, dimBlock>>>(d_a, d_b, d_c, N);    
  
  /// Transfer results from device to host 
  hipMemcpy(h_c, d_c, sizeof(int)*N*N, hipMemcpyDeviceToHost);
  hipDeviceSynchronize();
    
  /// time counting terminate
  hipEventRecord(stop, 0);
  hipEventSynchronize(stop);

  /// compute time elapse on GPU computing
  hipEventElapsedTime(&gpu_elapsed_time_ms, start, stop);
  printf("Time elapsed on GPU: %f ms.\n\n", gpu_elapsed_time_ms);

  /// start the CPU version
  hipEventRecord(start, 0);

  cpu_matrix_mult(h_a, h_b, h_cc, N);

  hipEventRecord(stop, 0);
  hipEventSynchronize(stop);
  hipEventElapsedTime(&cpu_elapsed_time_ms, start, stop);
  printf("Time elapsed on on CPU: %f ms.\n\n", cpu_elapsed_time_ms);

  /// validate results computed by GPU
  bool all_ok = true;
  for (int j = 0; j < N; ++j) {
    for (int i = 0; i < N; ++i) {
      if(fabs(h_c[j*N + i] - h_cc[j*N + i]) > 1.e-4) {
        all_ok = false;
      }
    }
  }

  /// roughly compute speedup
  if(all_ok) {
    printf("all results are correct!!!, speedup = %f\n", 
            cpu_elapsed_time_ms / gpu_elapsed_time_ms);
  } else {
    printf("incorrect results\n");
  }

  /// free memory
  hipFree(d_a);
  hipFree(d_b);
  hipFree(d_c);
  hipHostFree(h_a);
  hipHostFree(h_b);
  hipHostFree(h_c);
  hipHostFree(h_cc);
  return 0;
}

	.text
	.file	"matrix_cuda_opt_sol.hip"
	.globl	_Z30__device_stub__gpu_matrix_multPfS_S_i # -- Begin function _Z30__device_stub__gpu_matrix_multPfS_S_i
	.type	_Z30__device_stub__gpu_matrix_multPfS_S_i,@function
_Z30__device_stub__gpu_matrix_multPfS_S_i: # @_Z30__device_stub__gpu_matrix_multPfS_S_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	4(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z15gpu_matrix_multPfS_S_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z30__device_stub__gpu_matrix_multPfS_S_i, .Lfunc_end0-_Z30__device_stub__gpu_matrix_multPfS_S_i
	.cfi_endproc
                                        # -- End function
	.globl	_Z15cpu_matrix_multPfS_S_i      # -- Begin function _Z15cpu_matrix_multPfS_S_i
	.type	_Z15cpu_matrix_multPfS_S_i,@function
_Z15cpu_matrix_multPfS_S_i:             # @_Z15cpu_matrix_multPfS_S_i
	.cfi_startproc
# %bb.0:
	testl	%ecx, %ecx
	jle	.LBB1_8
# %bb.1:                                # %.preheader23.lr.ph
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movl	%ecx, %eax
	leaq	(,%rax,4), %r8
	xorl	%r9d, %r9d
	xorl	%r10d, %r10d
.LBB1_2:                                # %.preheader.lr.ph
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB1_3 Depth 2
                                        #       Child Loop BB1_4 Depth 3
	movl	%r9d, %r11d
	leaq	(%rdi,%r11,4), %r11
	movq	%r10, %rbx
	imulq	%rax, %rbx
	leaq	(%rdx,%rbx,4), %rbx
	movq	%rsi, %r14
	xorl	%r15d, %r15d
.LBB1_3:                                # %.preheader
                                        #   Parent Loop BB1_2 Depth=1
                                        # =>  This Loop Header: Depth=2
                                        #       Child Loop BB1_4 Depth 3
	movss	(%rbx,%r15,4), %xmm0            # xmm0 = mem[0],zero,zero,zero
	movq	%r14, %r12
	xorl	%r13d, %r13d
.LBB1_4:                                #   Parent Loop BB1_2 Depth=1
                                        #     Parent Loop BB1_3 Depth=2
                                        # =>    This Inner Loop Header: Depth=3
	movss	(%r11,%r13,4), %xmm1            # xmm1 = mem[0],zero,zero,zero
	mulss	(%r12), %xmm1
	addss	%xmm1, %xmm0
	movss	%xmm0, (%rbx,%r15,4)
	incq	%r13
	addq	%r8, %r12
	cmpq	%r13, %rax
	jne	.LBB1_4
# %bb.5:                                # %._crit_edge
                                        #   in Loop: Header=BB1_3 Depth=2
	incq	%r15
	addq	$4, %r14
	cmpq	%rax, %r15
	jne	.LBB1_3
# %bb.6:                                # %._crit_edge26
                                        #   in Loop: Header=BB1_2 Depth=1
	incq	%r10
	addl	%ecx, %r9d
	cmpq	%rax, %r10
	jne	.LBB1_2
# %bb.7:
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	.cfi_restore %rbx
	.cfi_restore %r12
	.cfi_restore %r13
	.cfi_restore %r14
	.cfi_restore %r15
.LBB1_8:                                # %._crit_edge28
	retq
.Lfunc_end1:
	.size	_Z15cpu_matrix_multPfS_S_i, .Lfunc_end1-_Z15cpu_matrix_multPfS_S_i
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst16,"aM",@progbits,16
	.p2align	4, 0x0                          # -- Begin function main
.LCPI2_0:
	.long	0x7fffffff                      # float NaN
	.long	0x7fffffff                      # float NaN
	.long	0x7fffffff                      # float NaN
	.long	0x7fffffff                      # float NaN
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0
.LCPI2_1:
	.quad	0x3f1a36e2eb1c432d              # double 1.0E-4
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	subq	$80, %rsp
	.cfi_def_cfa_offset 112
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movl	$3333, %edi                     # imm = 0xD05
	callq	srand
	leaq	24(%rsp), %rdi
	xorl	%ebx, %ebx
	movl	$16777216, %esi                 # imm = 0x1000000
	xorl	%edx, %edx
	callq	hipHostMalloc
	leaq	16(%rsp), %rdi
	movl	$16777216, %esi                 # imm = 0x1000000
	xorl	%edx, %edx
	callq	hipHostMalloc
	leaq	8(%rsp), %rdi
	movl	$16777216, %esi                 # imm = 0x1000000
	xorl	%edx, %edx
	callq	hipHostMalloc
	leaq	48(%rsp), %rdi
	movl	$16777216, %esi                 # imm = 0x1000000
	xorl	%edx, %edx
	callq	hipHostMalloc
	xorl	%r14d, %r14d
.LBB2_1:                                # %.preheader88
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB2_2 Depth 2
	xorl	%r15d, %r15d
.LBB2_2:                                #   Parent Loop BB2_1 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	callq	rand
                                        # kill: def $eax killed $eax def $rax
	leal	1023(%rax), %ecx
	testl	%eax, %eax
	cmovnsl	%eax, %ecx
	andl	$-1024, %ecx                    # imm = 0xFC00
	subl	%ecx, %eax
	xorps	%xmm0, %xmm0
	cvtsi2ss	%eax, %xmm0
	movq	24(%rsp), %rax
	addq	%rbx, %rax
	movss	%xmm0, (%rax,%r15,4)
	incq	%r15
	cmpq	$2048, %r15                     # imm = 0x800
	jne	.LBB2_2
# %bb.3:                                #   in Loop: Header=BB2_1 Depth=1
	incq	%r14
	addq	$8192, %rbx                     # imm = 0x2000
	cmpq	$2048, %r14                     # imm = 0x800
	jne	.LBB2_1
# %bb.4:                                # %.preheader86.preheader
	xorl	%ebx, %ebx
	xorl	%r14d, %r14d
.LBB2_5:                                # %.preheader86
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB2_6 Depth 2
	xorl	%r15d, %r15d
.LBB2_6:                                #   Parent Loop BB2_5 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	callq	rand
                                        # kill: def $eax killed $eax def $rax
	leal	1023(%rax), %ecx
	testl	%eax, %eax
	cmovnsl	%eax, %ecx
	andl	$-1024, %ecx                    # imm = 0xFC00
	subl	%ecx, %eax
	xorps	%xmm0, %xmm0
	cvtsi2ss	%eax, %xmm0
	movq	16(%rsp), %rax
	addq	%rbx, %rax
	movss	%xmm0, (%rax,%r15,4)
	incq	%r15
	cmpq	$2048, %r15                     # imm = 0x800
	jne	.LBB2_6
# %bb.7:                                #   in Loop: Header=BB2_5 Depth=1
	incq	%r14
	addq	$8192, %rbx                     # imm = 0x2000
	cmpq	$2048, %r14                     # imm = 0x800
	jne	.LBB2_5
# %bb.8:                                # %.preheader85
	movq	8(%rsp), %rdi
	movl	$16777216, %edx                 # imm = 0x1000000
	xorl	%esi, %esi
	callq	memset@PLT
	leaq	40(%rsp), %rbx
	movq	%rbx, %rdi
	callq	hipEventCreate
	movq	%rsp, %rdi
	callq	hipEventCreate
	movq	(%rbx), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	leaq	72(%rsp), %rbx
	movl	$16777216, %esi                 # imm = 0x1000000
	movq	%rbx, %rdi
	callq	hipMalloc
	leaq	64(%rsp), %r14
	movl	$16777216, %esi                 # imm = 0x1000000
	movq	%r14, %rdi
	callq	hipMalloc
	leaq	32(%rsp), %rdi
	movl	$16777216, %esi                 # imm = 0x1000000
	callq	hipMalloc
	movq	(%rbx), %rdi
	movq	24(%rsp), %rsi
	movl	$16777216, %edx                 # imm = 0x1000000
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%r14), %rdi
	movq	16(%rsp), %rsi
	movl	$16777216, %edx                 # imm = 0x1000000
	movl	$1, %ecx
	callq	hipMemcpy
	movabsq	$549755814016, %rdi             # imm = 0x8000000080
	movabsq	$68719476752, %rdx              # imm = 0x1000000010
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_10
# %bb.9:
	movq	72(%rsp), %rdi
	movq	64(%rsp), %rsi
	movq	32(%rsp), %rdx
	movl	$2048, %ecx                     # imm = 0x800
	callq	_Z30__device_stub__gpu_matrix_multPfS_S_i
.LBB2_10:
	movq	8(%rsp), %rdi
	movq	32(%rsp), %rsi
	movl	$16777216, %edx                 # imm = 0x1000000
	movl	$2, %ecx
	callq	hipMemcpy
	callq	hipDeviceSynchronize
	movq	(%rsp), %rdi
	xorl	%r14d, %r14d
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	(%rsp), %rdi
	callq	hipEventSynchronize
	movq	40(%rsp), %rsi
	movq	(%rsp), %rdx
	leaq	60(%rsp), %rbx
	movq	%rbx, %rdi
	callq	hipEventElapsedTime
	cvtss2sd	(%rbx), %xmm0
	movl	$.L.str, %edi
	movb	$1, %al
	callq	printf
	movq	40(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	24(%rsp), %rax
	movq	16(%rsp), %rcx
	movq	48(%rsp), %rdx
.LBB2_11:                               # %.preheader.lr.ph.i
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB2_12 Depth 2
                                        #       Child Loop BB2_13 Depth 3
	movq	%r14, %rsi
	shlq	$13, %rsi
	addq	%rdx, %rsi
	movq	%rcx, %rdi
	xorl	%r8d, %r8d
.LBB2_12:                               # %.preheader.i
                                        #   Parent Loop BB2_11 Depth=1
                                        # =>  This Loop Header: Depth=2
                                        #       Child Loop BB2_13 Depth 3
	movss	(%rsi,%r8,4), %xmm0             # xmm0 = mem[0],zero,zero,zero
	movq	%rdi, %r9
	xorl	%r10d, %r10d
.LBB2_13:                               #   Parent Loop BB2_11 Depth=1
                                        #     Parent Loop BB2_12 Depth=2
                                        # =>    This Inner Loop Header: Depth=3
	movss	(%rax,%r10,4), %xmm1            # xmm1 = mem[0],zero,zero,zero
	mulss	(%r9), %xmm1
	addss	%xmm1, %xmm0
	movss	%xmm0, (%rsi,%r8,4)
	incq	%r10
	addq	$8192, %r9                      # imm = 0x2000
	cmpq	$2048, %r10                     # imm = 0x800
	jne	.LBB2_13
# %bb.14:                               # %._crit_edge.i
                                        #   in Loop: Header=BB2_12 Depth=2
	incq	%r8
	addq	$4, %rdi
	cmpq	$2048, %r8                      # imm = 0x800
	jne	.LBB2_12
# %bb.15:                               # %._crit_edge26.i
                                        #   in Loop: Header=BB2_11 Depth=1
	incq	%r14
	addq	$8192, %rax                     # imm = 0x2000
	cmpq	$2048, %r14                     # imm = 0x800
	jne	.LBB2_11
# %bb.16:                               # %_Z15cpu_matrix_multPfS_S_i.exit
	movq	(%rsp), %rdi
	xorl	%r14d, %r14d
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	(%rsp), %rdi
	callq	hipEventSynchronize
	movq	40(%rsp), %rsi
	movq	(%rsp), %rdx
	leaq	56(%rsp), %rbx
	movq	%rbx, %rdi
	callq	hipEventElapsedTime
	xorps	%xmm0, %xmm0
	cvtss2sd	(%rbx), %xmm0
	movb	$1, %bl
	movl	$.L.str.1, %edi
	movb	$1, %al
	callq	printf
	movq	8(%rsp), %rax
	movq	48(%rsp), %rcx
	movaps	.LCPI2_0(%rip), %xmm0           # xmm0 = [NaN,NaN,NaN,NaN]
	movsd	.LCPI2_1(%rip), %xmm1           # xmm1 = mem[0],zero
	movl	$8192, %edx                     # imm = 0x2000
.LBB2_17:                               # %.preheader
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB2_18 Depth 2
	xorl	%esi, %esi
.LBB2_18:                               #   Parent Loop BB2_17 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movss	(%rax,%rsi,4), %xmm2            # xmm2 = mem[0],zero,zero,zero
	subss	(%rcx,%rsi,4), %xmm2
	andps	%xmm0, %xmm2
	cvtss2sd	%xmm2, %xmm2
	xorl	%edi, %edi
	ucomisd	%xmm1, %xmm2
	ja	.LBB2_20
# %bb.19:                               #   in Loop: Header=BB2_18 Depth=2
	movzbl	%bl, %edi
.LBB2_20:                               #   in Loop: Header=BB2_18 Depth=2
	movl	%edi, %ebx
	incq	%rsi
	cmpq	$2048, %rsi                     # imm = 0x800
	jne	.LBB2_18
# %bb.21:                               #   in Loop: Header=BB2_17 Depth=1
	incq	%r14
	addq	%rdx, %rcx
	addq	%rdx, %rax
	cmpq	$2048, %r14                     # imm = 0x800
	jne	.LBB2_17
# %bb.22:
	testb	$1, %bl
	jne	.LBB2_23
# %bb.24:
	movl	$.Lstr, %edi
	callq	puts@PLT
	jmp	.LBB2_25
.LBB2_23:
	movss	56(%rsp), %xmm0                 # xmm0 = mem[0],zero,zero,zero
	divss	60(%rsp), %xmm0
	cvtss2sd	%xmm0, %xmm0
	movl	$.L.str.2, %edi
	movb	$1, %al
	callq	printf
.LBB2_25:
	movq	72(%rsp), %rdi
	callq	hipFree
	movq	64(%rsp), %rdi
	callq	hipFree
	movq	32(%rsp), %rdi
	callq	hipFree
	movq	24(%rsp), %rdi
	callq	hipHostFree
	movq	16(%rsp), %rdi
	callq	hipHostFree
	movq	8(%rsp), %rdi
	callq	hipHostFree
	movq	48(%rsp), %rdi
	callq	hipHostFree
	xorl	%eax, %eax
	addq	$80, %rsp
	.cfi_def_cfa_offset 32
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	main, .Lfunc_end2-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB3_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB3_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z15gpu_matrix_multPfS_S_i, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end3:
	.size	__hip_module_ctor, .Lfunc_end3-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB4_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB4_2:
	retq
.Lfunc_end4:
	.size	__hip_module_dtor, .Lfunc_end4-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z15gpu_matrix_multPfS_S_i,@object # @_Z15gpu_matrix_multPfS_S_i
	.section	.rodata,"a",@progbits
	.globl	_Z15gpu_matrix_multPfS_S_i
	.p2align	3, 0x0
_Z15gpu_matrix_multPfS_S_i:
	.quad	_Z30__device_stub__gpu_matrix_multPfS_S_i
	.size	_Z15gpu_matrix_multPfS_S_i, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"Time elapsed on GPU: %f ms.\n\n"
	.size	.L.str, 30

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"Time elapsed on on CPU: %f ms.\n\n"
	.size	.L.str.1, 33

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"all results are correct!!!, speedup = %f\n"
	.size	.L.str.2, 42

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z15gpu_matrix_multPfS_S_i"
	.size	.L__unnamed_1, 27

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.type	.Lstr,@object                   # @str
	.section	.rodata.str1.1,"aMS",@progbits,1
.Lstr:
	.asciz	"incorrect results"
	.size	.Lstr, 18

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z30__device_stub__gpu_matrix_multPfS_S_i
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z15gpu_matrix_multPfS_S_i
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z15gpu_matrix_multPfS_S_i ; -- Begin function _Z15gpu_matrix_multPfS_S_i
	.globl	_Z15gpu_matrix_multPfS_S_i
	.p2align	8
	.type	_Z15gpu_matrix_multPfS_S_i,@function
_Z15gpu_matrix_multPfS_S_i:             ; @_Z15gpu_matrix_multPfS_S_i
; %bb.0:
	s_clause 0x3
	s_load_b32 s3, s[0:1], 0x20
	s_load_b32 s2, s[0:1], 0x18
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b64 s[0:1], s[0:1], 0x10
	v_bfe_u32 v6, v0, 10, 10
	v_and_b32_e32 v3, 0x3ff, v0
	s_mov_b32 s8, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshl_add_u32 v4, s15, 4, v6
	v_lshl_add_u32 v0, s14, 4, v3
	s_waitcnt lgkmcnt(0)
	s_cmp_eq_u32 s3, 0
	s_cbranch_scc1 .LBB0_9
; %bb.1:                                ; %.lr.ph
	v_lshlrev_b32_e32 v5, 2, v3
	v_lshlrev_b32_e32 v7, 6, v6
	v_mad_u64_u32 v[1:2], null, v4, s2, v[3:4]
	s_mul_i32 s9, s2, s2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v8, 0x400, v5
	v_add_nc_u32_e32 v9, v7, v5
	s_delay_alu instid0(VALU_DEP_2)
	v_dual_mov_b32 v5, 0 :: v_dual_add_nc_u32 v10, v8, v7
.LBB0_2:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_7 Depth 2
	s_lshl_b32 s10, s8, 4
	s_mov_b32 s11, exec_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v11, 0 :: v_dual_add_nc_u32 v2, s10, v1
	v_cmpx_gt_i32_e64 s9, v2
	s_cbranch_execz .LBB0_4
; %bb.3:                                ;   in Loop: Header=BB0_2 Depth=1
	v_ashrrev_i32_e32 v3, 31, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	v_add_co_u32 v2, vcc_lo, s4, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
	global_load_b32 v2, v[2:3], off
	s_waitcnt vmcnt(0)
	v_cvt_i32_f32_e32 v11, v2
.LBB0_4:                                ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s11
	v_add_nc_u32_e32 v12, s10, v6
	s_mov_b32 s10, exec_lo
	ds_store_b32 v9, v11
	v_mad_u64_u32 v[2:3], null, v12, s2, v[0:1]
	v_mov_b32_e32 v3, 0
	s_delay_alu instid0(VALU_DEP_2)
	v_cmpx_gt_i32_e64 s9, v2
	s_cbranch_execz .LBB0_6
; %bb.5:                                ;   in Loop: Header=BB0_2 Depth=1
	v_ashrrev_i32_e32 v3, 31, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	v_add_co_u32 v2, vcc_lo, s6, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
	global_load_b32 v2, v[2:3], off
	s_waitcnt vmcnt(0)
	v_cvt_i32_f32_e32 v3, v2
.LBB0_6:                                ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
	v_mov_b32_e32 v2, v8
	s_mov_b32 s10, 0
	ds_store_b32 v10, v3
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
.LBB0_7:                                ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_add_nc_u32_e32 v3, s10, v7
	s_add_i32 s10, s10, 4
	ds_load_b32 v11, v2
	ds_load_b32 v3, v3
	s_cmp_eq_u32 s10, 64
	s_waitcnt lgkmcnt(0)
	v_mul_lo_u32 v3, v11, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f32_i32_e32 v3, v3
	v_dual_add_f32 v5, v5, v3 :: v_dual_add_nc_u32 v2, 64, v2
	s_cbranch_scc0 .LBB0_7
; %bb.8:                                ;   in Loop: Header=BB0_2 Depth=1
	s_add_i32 s8, s8, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s8, s3
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc0 .LBB0_2
	s_branch .LBB0_10
.LBB0_9:
	v_mov_b32_e32 v5, 0
.LBB0_10:                               ; %Flow63
	v_max_i32_e32 v1, v4, v0
	s_mov_b32 s3, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e64 s2, v1
	s_cbranch_execz .LBB0_12
; %bb.11:
	v_mad_u64_u32 v[1:2], null, v4, s2, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v2, 31, v1
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	global_store_b32 v[0:1], v5, off
.LBB0_12:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z15gpu_matrix_multPfS_S_i
		.amdhsa_group_segment_fixed_size 2048
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 13
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z15gpu_matrix_multPfS_S_i, .Lfunc_end0-_Z15gpu_matrix_multPfS_S_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 528
; NumSgprs: 18
; NumVgprs: 13
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 2048 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 13
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 2048
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z15gpu_matrix_multPfS_S_i
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z15gpu_matrix_multPfS_S_i.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     13
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
