// Copyright (c) OpenMMLab. All rights reserved.

#include <cuda_runtime.h>

#include <cstdint>

namespace mmdeploy {
namespace operation {
namespace cuda {
namespace impl {

template <typename T, int channels>
__global__ void normalize(const T* src, int height, int width, int stride, float* output,
                          const float3 mean, const float3 std, bool to_rgb) {
  int x = (int)(blockIdx.x * blockDim.x + threadIdx.x);
  int y = (int)(blockIdx.y * blockDim.y + threadIdx.y);

  if (x >= width || y >= height) {
    return;
  }

  int loc = y * stride + x * channels;
  auto mean_ptr = &mean.x;
  auto std_ptr = &std.x;
  if (to_rgb) {
    for (int c = 0; c < channels; ++c) {
      output[loc + c] = ((float)src[loc + channels - 1 - c] - mean_ptr[c]) * std_ptr[c];
    }
  } else {
    for (int c = 0; c < channels; ++c) {
      output[loc + c] = ((float)src[loc + c] - mean_ptr[c]) * std_ptr[c];
    }
  }
}

template <typename T, int channels>
void Normalize(const T* src, int height, int width, int stride, float* output, const float* mean,
               const float* std, bool to_rgb, cudaStream_t stream) {
  const dim3 thread_block(16, 16);
  const dim3 num_blocks((width + thread_block.x - 1) / thread_block.x,
                        (height + thread_block.y - 1) / thread_block.y);
  const float3 _mean{mean[0], mean[1], mean[2]};
  const float3 _std{float(1. / std[0]), float(1. / std[1]), float(1. / std[2])};
  normalize<T, channels><<<num_blocks, thread_block, 0, stream>>>(src, height, width, stride,
                                                                  output, _mean, _std, to_rgb);
}

template void Normalize<uint8_t, 3>(const uint8_t* src, int height, int width, int stride,
                                    float* output, const float* mean, const float* std, bool to_rgb,
                                    cudaStream_t stream);
template void Normalize<uint8_t, 1>(const uint8_t* src, int height, int width, int stride,
                                    float* output, const float* mean, const float* std, bool to_rgb,
                                    cudaStream_t stream);

template void Normalize<float, 3>(const float* src, int height, int width, int stride,
                                  float* output, const float* mean, const float* std, bool to_rgb,
                                  cudaStream_t stream);
template void Normalize<float, 1>(const float* src, int height, int width, int stride,
                                  float* output, const float* mean, const float* std, bool to_rgb,
                                  cudaStream_t stream);
}  // namespace impl
}  // namespace cuda
}  // namespace operation
}  // namespace mmdeploy

	.file	"tmpxft_00307a44_00000000-6_normalize.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2013:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2013:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.type	_ZL85__device_stub__ZN8mmdeploy9operation4cuda4impl9normalizeIfLi1EEEvPKT_iiiPf6float3S8_bPKfiiiPfRK6float3S4_b, @function
_ZL85__device_stub__ZN8mmdeploy9operation4cuda4impl9normalizeIfLi1EEEvPKT_iiiPf6float3S8_bPKfiiiPfRK6float3S4_b:
.LFB2041:
	.cfi_startproc
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movl	200(%rsp), %eax
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movl	%esi, 20(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 16(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 12(%rsp)
	leaq	48(%rsp), %rcx
	movq	%r8, (%rsp)
	movb	%al, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movq	%r9, 144(%rsp)
	movq	%rax, 104(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 128(%rsp)
	movq	%rsp, %rax
	movq	%rax, 136(%rsp)
	movq	192(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 152(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	48(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_ZN8mmdeploy9operation4cuda4impl9normalizeIfLi1EEEvPKT_iiiPf6float3S8_b(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 208
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L2:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2041:
	.size	_ZL85__device_stub__ZN8mmdeploy9operation4cuda4impl9normalizeIfLi1EEEvPKT_iiiPf6float3S8_bPKfiiiPfRK6float3S4_b, .-_ZL85__device_stub__ZN8mmdeploy9operation4cuda4impl9normalizeIfLi1EEEvPKT_iiiPf6float3S8_bPKfiiiPfRK6float3S4_b
	.section	.text._ZN8mmdeploy9operation4cuda4impl9normalizeIfLi1EEEvPKT_iiiPf6float3S8_b,"axG",@progbits,_ZN8mmdeploy9operation4cuda4impl9normalizeIfLi1EEEvPKT_iiiPf6float3S8_b,comdat
	.weak	_ZN8mmdeploy9operation4cuda4impl9normalizeIfLi1EEEvPKT_iiiPf6float3S8_b
	.type	_ZN8mmdeploy9operation4cuda4impl9normalizeIfLi1EEEvPKT_iiiPf6float3S8_b, @function
_ZN8mmdeploy9operation4cuda4impl9normalizeIfLi1EEEvPKT_iiiPf6float3S8_b:
.LFB2099:
	.cfi_startproc
	endbr64
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movzbl	%r9b, %r9d
	movq	%xmm0, 16(%rsp)
	movss	%xmm1, 24(%rsp)
	movq	%xmm2, (%rsp)
	movss	%xmm3, 8(%rsp)
	pushq	%r9
	.cfi_def_cfa_offset 56
	leaq	8(%rsp), %rax
	pushq	%rax
	.cfi_def_cfa_offset 64
	leaq	32(%rsp), %r9
	call	_ZL85__device_stub__ZN8mmdeploy9operation4cuda4impl9normalizeIfLi1EEEvPKT_iiiPf6float3S8_bPKfiiiPfRK6float3S4_b
	addq	$56, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2099:
	.size	_ZN8mmdeploy9operation4cuda4impl9normalizeIfLi1EEEvPKT_iiiPf6float3S8_b, .-_ZN8mmdeploy9operation4cuda4impl9normalizeIfLi1EEEvPKT_iiiPf6float3S8_b
	.text
	.type	_ZL85__device_stub__ZN8mmdeploy9operation4cuda4impl9normalizeIhLi3EEEvPKT_iiiPf6float3S8_bPKhiiiPfRK6float3S4_b, @function
_ZL85__device_stub__ZN8mmdeploy9operation4cuda4impl9normalizeIhLi3EEEvPKT_iiiPf6float3S8_bPKhiiiPfRK6float3S4_b:
.LFB2035:
	.cfi_startproc
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movl	200(%rsp), %eax
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movl	%esi, 20(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 16(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 12(%rsp)
	leaq	48(%rsp), %rcx
	movq	%r8, (%rsp)
	movb	%al, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movq	%r9, 144(%rsp)
	movq	%rax, 104(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 128(%rsp)
	movq	%rsp, %rax
	movq	%rax, 136(%rsp)
	movq	192(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 152(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L9
	pushq	48(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_ZN8mmdeploy9operation4cuda4impl9normalizeIhLi3EEEvPKT_iiiPf6float3S8_b(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 208
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L9:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L11
	call	__stack_chk_fail@PLT
.L11:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2035:
	.size	_ZL85__device_stub__ZN8mmdeploy9operation4cuda4impl9normalizeIhLi3EEEvPKT_iiiPf6float3S8_bPKhiiiPfRK6float3S4_b, .-_ZL85__device_stub__ZN8mmdeploy9operation4cuda4impl9normalizeIhLi3EEEvPKT_iiiPf6float3S8_bPKhiiiPfRK6float3S4_b
	.section	.text._ZN8mmdeploy9operation4cuda4impl9normalizeIhLi3EEEvPKT_iiiPf6float3S8_b,"axG",@progbits,_ZN8mmdeploy9operation4cuda4impl9normalizeIhLi3EEEvPKT_iiiPf6float3S8_b,comdat
	.weak	_ZN8mmdeploy9operation4cuda4impl9normalizeIhLi3EEEvPKT_iiiPf6float3S8_b
	.type	_ZN8mmdeploy9operation4cuda4impl9normalizeIhLi3EEEvPKT_iiiPf6float3S8_b, @function
_ZN8mmdeploy9operation4cuda4impl9normalizeIhLi3EEEvPKT_iiiPf6float3S8_b:
.LFB2095:
	.cfi_startproc
	endbr64
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movzbl	%r9b, %r9d
	movq	%xmm0, 16(%rsp)
	movss	%xmm1, 24(%rsp)
	movq	%xmm2, (%rsp)
	movss	%xmm3, 8(%rsp)
	pushq	%r9
	.cfi_def_cfa_offset 56
	leaq	8(%rsp), %rax
	pushq	%rax
	.cfi_def_cfa_offset 64
	leaq	32(%rsp), %r9
	call	_ZL85__device_stub__ZN8mmdeploy9operation4cuda4impl9normalizeIhLi3EEEvPKT_iiiPf6float3S8_bPKhiiiPfRK6float3S4_b
	addq	$56, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2095:
	.size	_ZN8mmdeploy9operation4cuda4impl9normalizeIhLi3EEEvPKT_iiiPf6float3S8_b, .-_ZN8mmdeploy9operation4cuda4impl9normalizeIhLi3EEEvPKT_iiiPf6float3S8_b
	.text
	.type	_ZL85__device_stub__ZN8mmdeploy9operation4cuda4impl9normalizeIhLi1EEEvPKT_iiiPf6float3S8_bPKhiiiPfRK6float3S4_b, @function
_ZL85__device_stub__ZN8mmdeploy9operation4cuda4impl9normalizeIhLi1EEEvPKT_iiiPf6float3S8_bPKhiiiPfRK6float3S4_b:
.LFB2037:
	.cfi_startproc
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movl	200(%rsp), %eax
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movl	%esi, 20(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 16(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 12(%rsp)
	leaq	48(%rsp), %rcx
	movq	%r8, (%rsp)
	movb	%al, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movq	%r9, 144(%rsp)
	movq	%rax, 104(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 128(%rsp)
	movq	%rsp, %rax
	movq	%rax, 136(%rsp)
	movq	192(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 152(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L15
	pushq	48(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_ZN8mmdeploy9operation4cuda4impl9normalizeIhLi1EEEvPKT_iiiPf6float3S8_b(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 208
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L15:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L17
	call	__stack_chk_fail@PLT
.L17:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2037:
	.size	_ZL85__device_stub__ZN8mmdeploy9operation4cuda4impl9normalizeIhLi1EEEvPKT_iiiPf6float3S8_bPKhiiiPfRK6float3S4_b, .-_ZL85__device_stub__ZN8mmdeploy9operation4cuda4impl9normalizeIhLi1EEEvPKT_iiiPf6float3S8_bPKhiiiPfRK6float3S4_b
	.section	.text._ZN8mmdeploy9operation4cuda4impl9normalizeIhLi1EEEvPKT_iiiPf6float3S8_b,"axG",@progbits,_ZN8mmdeploy9operation4cuda4impl9normalizeIhLi1EEEvPKT_iiiPf6float3S8_b,comdat
	.weak	_ZN8mmdeploy9operation4cuda4impl9normalizeIhLi1EEEvPKT_iiiPf6float3S8_b
	.type	_ZN8mmdeploy9operation4cuda4impl9normalizeIhLi1EEEvPKT_iiiPf6float3S8_b, @function
_ZN8mmdeploy9operation4cuda4impl9normalizeIhLi1EEEvPKT_iiiPf6float3S8_b:
.LFB2097:
	.cfi_startproc
	endbr64
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movzbl	%r9b, %r9d
	movq	%xmm0, 16(%rsp)
	movss	%xmm1, 24(%rsp)
	movq	%xmm2, (%rsp)
	movss	%xmm3, 8(%rsp)
	pushq	%r9
	.cfi_def_cfa_offset 56
	leaq	8(%rsp), %rax
	pushq	%rax
	.cfi_def_cfa_offset 64
	leaq	32(%rsp), %r9
	call	_ZL85__device_stub__ZN8mmdeploy9operation4cuda4impl9normalizeIhLi1EEEvPKT_iiiPf6float3S8_bPKhiiiPfRK6float3S4_b
	addq	$56, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2097:
	.size	_ZN8mmdeploy9operation4cuda4impl9normalizeIhLi1EEEvPKT_iiiPf6float3S8_b, .-_ZN8mmdeploy9operation4cuda4impl9normalizeIhLi1EEEvPKT_iiiPf6float3S8_b
	.text
	.type	_ZL85__device_stub__ZN8mmdeploy9operation4cuda4impl9normalizeIfLi3EEEvPKT_iiiPf6float3S8_bPKfiiiPfRK6float3S4_b, @function
_ZL85__device_stub__ZN8mmdeploy9operation4cuda4impl9normalizeIfLi3EEEvPKT_iiiPf6float3S8_bPKfiiiPfRK6float3S4_b:
.LFB2039:
	.cfi_startproc
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movl	200(%rsp), %eax
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movl	%esi, 20(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 16(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 12(%rsp)
	leaq	48(%rsp), %rcx
	movq	%r8, (%rsp)
	movb	%al, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movq	%r9, 144(%rsp)
	movq	%rax, 104(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 128(%rsp)
	movq	%rsp, %rax
	movq	%rax, 136(%rsp)
	movq	192(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 152(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L21
	pushq	48(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_ZN8mmdeploy9operation4cuda4impl9normalizeIfLi3EEEvPKT_iiiPf6float3S8_b(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 208
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L21:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L23
	call	__stack_chk_fail@PLT
.L23:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2039:
	.size	_ZL85__device_stub__ZN8mmdeploy9operation4cuda4impl9normalizeIfLi3EEEvPKT_iiiPf6float3S8_bPKfiiiPfRK6float3S4_b, .-_ZL85__device_stub__ZN8mmdeploy9operation4cuda4impl9normalizeIfLi3EEEvPKT_iiiPf6float3S8_bPKfiiiPfRK6float3S4_b
	.section	.text._ZN8mmdeploy9operation4cuda4impl9normalizeIfLi3EEEvPKT_iiiPf6float3S8_b,"axG",@progbits,_ZN8mmdeploy9operation4cuda4impl9normalizeIfLi3EEEvPKT_iiiPf6float3S8_b,comdat
	.weak	_ZN8mmdeploy9operation4cuda4impl9normalizeIfLi3EEEvPKT_iiiPf6float3S8_b
	.type	_ZN8mmdeploy9operation4cuda4impl9normalizeIfLi3EEEvPKT_iiiPf6float3S8_b, @function
_ZN8mmdeploy9operation4cuda4impl9normalizeIfLi3EEEvPKT_iiiPf6float3S8_b:
.LFB2098:
	.cfi_startproc
	endbr64
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movzbl	%r9b, %r9d
	movq	%xmm0, 16(%rsp)
	movss	%xmm1, 24(%rsp)
	movq	%xmm2, (%rsp)
	movss	%xmm3, 8(%rsp)
	pushq	%r9
	.cfi_def_cfa_offset 56
	leaq	8(%rsp), %rax
	pushq	%rax
	.cfi_def_cfa_offset 64
	leaq	32(%rsp), %r9
	call	_ZL85__device_stub__ZN8mmdeploy9operation4cuda4impl9normalizeIfLi3EEEvPKT_iiiPf6float3S8_bPKfiiiPfRK6float3S4_b
	addq	$56, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2098:
	.size	_ZN8mmdeploy9operation4cuda4impl9normalizeIfLi3EEEvPKT_iiiPf6float3S8_b, .-_ZN8mmdeploy9operation4cuda4impl9normalizeIfLi3EEEvPKT_iiiPf6float3S8_b
	.section	.text._ZN8mmdeploy9operation4cuda4impl9NormalizeIhLi3EEEvPKT_iiiPfPKfS9_bP11CUstream_st,"axG",@progbits,_ZN8mmdeploy9operation4cuda4impl9NormalizeIhLi3EEEvPKT_iiiPfPKfS9_bP11CUstream_st,comdat
	.weak	_ZN8mmdeploy9operation4cuda4impl9NormalizeIhLi3EEEvPKT_iiiPfPKfS9_bP11CUstream_st
	.type	_ZN8mmdeploy9operation4cuda4impl9NormalizeIhLi3EEEvPKT_iiiPfPKfS9_bP11CUstream_st, @function
_ZN8mmdeploy9operation4cuda4impl9NormalizeIhLi3EEEvPKT_iiiPfPKfS9_bP11CUstream_st:
.LFB2090:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movl	%edx, %r15d
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movq	%r8, %r13
	xorl	%r8d, %r8d
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movl	%ecx, %r12d
	movl	$1, %ecx
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movl	%esi, %ebx
	subq	$104, %rsp
	.cfi_def_cfa_offset 160
	movss	8(%r9), %xmm0
	movq	(%r9), %rbp
	movq	%rdi, 16(%rsp)
	movq	160(%rsp), %rax
	movq	176(%rsp), %r9
	movl	168(%rsp), %r14d
	movss	(%rax), %xmm2
	movss	4(%rax), %xmm3
	movq	%fs:40, %rdx
	movq	%rdx, 88(%rsp)
	xorl	%edx, %edx
	leal	15(%r15), %edx
	movss	8(%rax), %xmm4
	movss	%xmm0, 28(%rsp)
	shrl	$4, %edx
	movss	%xmm2, 8(%rsp)
	movl	%edx, 52(%rsp)
	leal	15(%rsi), %edx
	movl	$1, %esi
	shrl	$4, %edx
	movss	%xmm3, 12(%rsp)
	movl	%edx, 56(%rsp)
	movq	52(%rsp), %rdi
	movabsq	$68719476752, %rdx
	movss	%xmm4, 24(%rsp)
	call	__cudaPushCallConfiguration@PLT
	movss	28(%rsp), %xmm0
	testl	%eax, %eax
	jne	.L27
	movss	%xmm0, 72(%rsp)
	movzbl	%r14b, %r14d
	movl	%r15d, %edx
	movq	%r13, %r8
	movss	.LC0(%rip), %xmm0
	movq	%rbp, 64(%rsp)
	movl	%r12d, %ecx
	movl	%ebx, %esi
	movaps	%xmm0, %xmm1
	divss	8(%rsp), %xmm1
	movss	%xmm1, 76(%rsp)
	movaps	%xmm0, %xmm1
	divss	24(%rsp), %xmm0
	divss	12(%rsp), %xmm1
	movss	%xmm0, 84(%rsp)
	movss	%xmm1, 80(%rsp)
	pushq	%r14
	.cfi_def_cfa_offset 168
	leaq	84(%rsp), %rax
	pushq	%rax
	.cfi_def_cfa_offset 176
	movq	32(%rsp), %rdi
	leaq	80(%rsp), %r9
	call	_ZL85__device_stub__ZN8mmdeploy9operation4cuda4impl9normalizeIhLi3EEEvPKT_iiiPf6float3S8_bPKhiiiPfRK6float3S4_b
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L27:
	movq	88(%rsp), %rax
	subq	%fs:40, %rax
	je	.L29
	call	__stack_chk_fail@PLT
.L29:
	addq	$104, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2090:
	.size	_ZN8mmdeploy9operation4cuda4impl9NormalizeIhLi3EEEvPKT_iiiPfPKfS9_bP11CUstream_st, .-_ZN8mmdeploy9operation4cuda4impl9NormalizeIhLi3EEEvPKT_iiiPfPKfS9_bP11CUstream_st
	.section	.text._ZN8mmdeploy9operation4cuda4impl9NormalizeIhLi1EEEvPKT_iiiPfPKfS9_bP11CUstream_st,"axG",@progbits,_ZN8mmdeploy9operation4cuda4impl9NormalizeIhLi1EEEvPKT_iiiPfPKfS9_bP11CUstream_st,comdat
	.weak	_ZN8mmdeploy9operation4cuda4impl9NormalizeIhLi1EEEvPKT_iiiPfPKfS9_bP11CUstream_st
	.type	_ZN8mmdeploy9operation4cuda4impl9NormalizeIhLi1EEEvPKT_iiiPfPKfS9_bP11CUstream_st, @function
_ZN8mmdeploy9operation4cuda4impl9NormalizeIhLi1EEEvPKT_iiiPfPKfS9_bP11CUstream_st:
.LFB2091:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movl	%edx, %r15d
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movq	%r8, %r13
	xorl	%r8d, %r8d
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movl	%ecx, %r12d
	movl	$1, %ecx
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movl	%esi, %ebx
	subq	$104, %rsp
	.cfi_def_cfa_offset 160
	movss	8(%r9), %xmm0
	movq	(%r9), %rbp
	movq	%rdi, 16(%rsp)
	movq	160(%rsp), %rax
	movq	176(%rsp), %r9
	movl	168(%rsp), %r14d
	movss	(%rax), %xmm2
	movss	4(%rax), %xmm3
	movq	%fs:40, %rdx
	movq	%rdx, 88(%rsp)
	xorl	%edx, %edx
	leal	15(%r15), %edx
	movss	8(%rax), %xmm4
	movss	%xmm0, 28(%rsp)
	shrl	$4, %edx
	movss	%xmm2, 8(%rsp)
	movl	%edx, 52(%rsp)
	leal	15(%rsi), %edx
	movl	$1, %esi
	shrl	$4, %edx
	movss	%xmm3, 12(%rsp)
	movl	%edx, 56(%rsp)
	movq	52(%rsp), %rdi
	movabsq	$68719476752, %rdx
	movss	%xmm4, 24(%rsp)
	call	__cudaPushCallConfiguration@PLT
	movss	28(%rsp), %xmm0
	testl	%eax, %eax
	jne	.L31
	movss	%xmm0, 72(%rsp)
	movzbl	%r14b, %r14d
	movl	%r15d, %edx
	movq	%r13, %r8
	movss	.LC0(%rip), %xmm0
	movq	%rbp, 64(%rsp)
	movl	%r12d, %ecx
	movl	%ebx, %esi
	movaps	%xmm0, %xmm1
	divss	8(%rsp), %xmm1
	movss	%xmm1, 76(%rsp)
	movaps	%xmm0, %xmm1
	divss	24(%rsp), %xmm0
	divss	12(%rsp), %xmm1
	movss	%xmm0, 84(%rsp)
	movss	%xmm1, 80(%rsp)
	pushq	%r14
	.cfi_def_cfa_offset 168
	leaq	84(%rsp), %rax
	pushq	%rax
	.cfi_def_cfa_offset 176
	movq	32(%rsp), %rdi
	leaq	80(%rsp), %r9
	call	_ZL85__device_stub__ZN8mmdeploy9operation4cuda4impl9normalizeIhLi1EEEvPKT_iiiPf6float3S8_bPKhiiiPfRK6float3S4_b
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L31:
	movq	88(%rsp), %rax
	subq	%fs:40, %rax
	je	.L33
	call	__stack_chk_fail@PLT
.L33:
	addq	$104, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2091:
	.size	_ZN8mmdeploy9operation4cuda4impl9NormalizeIhLi1EEEvPKT_iiiPfPKfS9_bP11CUstream_st, .-_ZN8mmdeploy9operation4cuda4impl9NormalizeIhLi1EEEvPKT_iiiPfPKfS9_bP11CUstream_st
	.section	.text._ZN8mmdeploy9operation4cuda4impl9NormalizeIfLi3EEEvPKT_iiiPfPKfS9_bP11CUstream_st,"axG",@progbits,_ZN8mmdeploy9operation4cuda4impl9NormalizeIfLi3EEEvPKT_iiiPfPKfS9_bP11CUstream_st,comdat
	.weak	_ZN8mmdeploy9operation4cuda4impl9NormalizeIfLi3EEEvPKT_iiiPfPKfS9_bP11CUstream_st
	.type	_ZN8mmdeploy9operation4cuda4impl9NormalizeIfLi3EEEvPKT_iiiPfPKfS9_bP11CUstream_st, @function
_ZN8mmdeploy9operation4cuda4impl9NormalizeIfLi3EEEvPKT_iiiPfPKfS9_bP11CUstream_st:
.LFB2092:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movl	%edx, %r15d
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movq	%r8, %r13
	xorl	%r8d, %r8d
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movl	%ecx, %r12d
	movl	$1, %ecx
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movl	%esi, %ebx
	subq	$104, %rsp
	.cfi_def_cfa_offset 160
	movss	8(%r9), %xmm0
	movq	(%r9), %rbp
	movq	%rdi, 16(%rsp)
	movq	160(%rsp), %rax
	movq	176(%rsp), %r9
	movl	168(%rsp), %r14d
	movss	(%rax), %xmm2
	movss	4(%rax), %xmm3
	movq	%fs:40, %rdx
	movq	%rdx, 88(%rsp)
	xorl	%edx, %edx
	leal	15(%r15), %edx
	movss	8(%rax), %xmm4
	movss	%xmm0, 28(%rsp)
	shrl	$4, %edx
	movss	%xmm2, 8(%rsp)
	movl	%edx, 52(%rsp)
	leal	15(%rsi), %edx
	movl	$1, %esi
	shrl	$4, %edx
	movss	%xmm3, 12(%rsp)
	movl	%edx, 56(%rsp)
	movq	52(%rsp), %rdi
	movabsq	$68719476752, %rdx
	movss	%xmm4, 24(%rsp)
	call	__cudaPushCallConfiguration@PLT
	movss	28(%rsp), %xmm0
	testl	%eax, %eax
	jne	.L35
	movss	%xmm0, 72(%rsp)
	movzbl	%r14b, %r14d
	movl	%r15d, %edx
	movq	%r13, %r8
	movss	.LC0(%rip), %xmm0
	movq	%rbp, 64(%rsp)
	movl	%r12d, %ecx
	movl	%ebx, %esi
	movaps	%xmm0, %xmm1
	divss	8(%rsp), %xmm1
	movss	%xmm1, 76(%rsp)
	movaps	%xmm0, %xmm1
	divss	24(%rsp), %xmm0
	divss	12(%rsp), %xmm1
	movss	%xmm0, 84(%rsp)
	movss	%xmm1, 80(%rsp)
	pushq	%r14
	.cfi_def_cfa_offset 168
	leaq	84(%rsp), %rax
	pushq	%rax
	.cfi_def_cfa_offset 176
	movq	32(%rsp), %rdi
	leaq	80(%rsp), %r9
	call	_ZL85__device_stub__ZN8mmdeploy9operation4cuda4impl9normalizeIfLi3EEEvPKT_iiiPf6float3S8_bPKfiiiPfRK6float3S4_b
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L35:
	movq	88(%rsp), %rax
	subq	%fs:40, %rax
	je	.L37
	call	__stack_chk_fail@PLT
.L37:
	addq	$104, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2092:
	.size	_ZN8mmdeploy9operation4cuda4impl9NormalizeIfLi3EEEvPKT_iiiPfPKfS9_bP11CUstream_st, .-_ZN8mmdeploy9operation4cuda4impl9NormalizeIfLi3EEEvPKT_iiiPfPKfS9_bP11CUstream_st
	.section	.text._ZN8mmdeploy9operation4cuda4impl9NormalizeIfLi1EEEvPKT_iiiPfPKfS9_bP11CUstream_st,"axG",@progbits,_ZN8mmdeploy9operation4cuda4impl9NormalizeIfLi1EEEvPKT_iiiPfPKfS9_bP11CUstream_st,comdat
	.weak	_ZN8mmdeploy9operation4cuda4impl9NormalizeIfLi1EEEvPKT_iiiPfPKfS9_bP11CUstream_st
	.type	_ZN8mmdeploy9operation4cuda4impl9NormalizeIfLi1EEEvPKT_iiiPfPKfS9_bP11CUstream_st, @function
_ZN8mmdeploy9operation4cuda4impl9NormalizeIfLi1EEEvPKT_iiiPfPKfS9_bP11CUstream_st:
.LFB2093:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movl	%edx, %r15d
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movq	%r8, %r13
	xorl	%r8d, %r8d
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movl	%ecx, %r12d
	movl	$1, %ecx
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movl	%esi, %ebx
	subq	$104, %rsp
	.cfi_def_cfa_offset 160
	movss	8(%r9), %xmm0
	movq	(%r9), %rbp
	movq	%rdi, 16(%rsp)
	movq	160(%rsp), %rax
	movq	176(%rsp), %r9
	movl	168(%rsp), %r14d
	movss	(%rax), %xmm2
	movss	4(%rax), %xmm3
	movq	%fs:40, %rdx
	movq	%rdx, 88(%rsp)
	xorl	%edx, %edx
	leal	15(%r15), %edx
	movss	8(%rax), %xmm4
	movss	%xmm0, 28(%rsp)
	shrl	$4, %edx
	movss	%xmm2, 8(%rsp)
	movl	%edx, 52(%rsp)
	leal	15(%rsi), %edx
	movl	$1, %esi
	shrl	$4, %edx
	movss	%xmm3, 12(%rsp)
	movl	%edx, 56(%rsp)
	movq	52(%rsp), %rdi
	movabsq	$68719476752, %rdx
	movss	%xmm4, 24(%rsp)
	call	__cudaPushCallConfiguration@PLT
	movss	28(%rsp), %xmm0
	testl	%eax, %eax
	jne	.L39
	movss	%xmm0, 72(%rsp)
	movzbl	%r14b, %r14d
	movl	%r15d, %edx
	movq	%r13, %r8
	movss	.LC0(%rip), %xmm0
	movq	%rbp, 64(%rsp)
	movl	%r12d, %ecx
	movl	%ebx, %esi
	movaps	%xmm0, %xmm1
	divss	8(%rsp), %xmm1
	movss	%xmm1, 76(%rsp)
	movaps	%xmm0, %xmm1
	divss	24(%rsp), %xmm0
	divss	12(%rsp), %xmm1
	movss	%xmm0, 84(%rsp)
	movss	%xmm1, 80(%rsp)
	pushq	%r14
	.cfi_def_cfa_offset 168
	leaq	84(%rsp), %rax
	pushq	%rax
	.cfi_def_cfa_offset 176
	movq	32(%rsp), %rdi
	leaq	80(%rsp), %r9
	call	_ZL85__device_stub__ZN8mmdeploy9operation4cuda4impl9normalizeIfLi1EEEvPKT_iiiPf6float3S8_bPKfiiiPfRK6float3S4_b
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L39:
	movq	88(%rsp), %rax
	subq	%fs:40, %rax
	je	.L41
	call	__stack_chk_fail@PLT
.L41:
	addq	$104, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2093:
	.size	_ZN8mmdeploy9operation4cuda4impl9NormalizeIfLi1EEEvPKT_iiiPfPKfS9_bP11CUstream_st, .-_ZN8mmdeploy9operation4cuda4impl9NormalizeIfLi1EEEvPKT_iiiPfPKfS9_bP11CUstream_st
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC1:
	.string	"_ZN8mmdeploy9operation4cuda4impl9normalizeIfLi1EEEvPKT_iiiPf6float3S8_b"
.LC2:
	.string	"_ZN8mmdeploy9operation4cuda4impl9normalizeIfLi3EEEvPKT_iiiPf6float3S8_b"
.LC3:
	.string	"_ZN8mmdeploy9operation4cuda4impl9normalizeIhLi1EEEvPKT_iiiPf6float3S8_b"
.LC4:
	.string	"_ZN8mmdeploy9operation4cuda4impl9normalizeIhLi3EEEvPKT_iiiPf6float3S8_b"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2044:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC1(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_ZN8mmdeploy9operation4cuda4impl9normalizeIfLi1EEEvPKT_iiiPf6float3S8_b(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC2(%rip), %rdx
	orl	$-1, %r8d
	leaq	_ZN8mmdeploy9operation4cuda4impl9normalizeIfLi3EEEvPKT_iiiPf6float3S8_b(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC3(%rip), %rdx
	orl	$-1, %r8d
	leaq	_ZN8mmdeploy9operation4cuda4impl9normalizeIhLi1EEEvPKT_iiiPf6float3S8_b(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC4(%rip), %rdx
	orl	$-1, %r8d
	leaq	_ZN8mmdeploy9operation4cuda4impl9normalizeIhLi3EEEvPKT_iiiPf6float3S8_b(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2044:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst4,"aM",@progbits,4
	.align 4
.LC0:
	.long	1065353216
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

// Copyright (c) OpenMMLab. All rights reserved.

#include <hip/hip_runtime.h>

#include <cstdint>

namespace mmdeploy {
namespace operation {
namespace cuda {
namespace impl {

template <typename T, int channels>
__global__ void normalize(const T* src, int height, int width, int stride, float* output,
                          const float3 mean, const float3 std, bool to_rgb) {
  int x = (int)(blockIdx.x * blockDim.x + threadIdx.x);
  int y = (int)(blockIdx.y * blockDim.y + threadIdx.y);

  if (x >= width || y >= height) {
    return;
  }

  int loc = y * stride + x * channels;
  auto mean_ptr = &mean.x;
  auto std_ptr = &std.x;
  if (to_rgb) {
    for (int c = 0; c < channels; ++c) {
      output[loc + c] = ((float)src[loc + channels - 1 - c] - mean_ptr[c]) * std_ptr[c];
    }
  } else {
    for (int c = 0; c < channels; ++c) {
      output[loc + c] = ((float)src[loc + c] - mean_ptr[c]) * std_ptr[c];
    }
  }
}

template <typename T, int channels>
void Normalize(const T* src, int height, int width, int stride, float* output, const float* mean,
               const float* std, bool to_rgb, hipStream_t stream) {
  const dim3 thread_block(16, 16);
  const dim3 num_blocks((width + thread_block.x - 1) / thread_block.x,
                        (height + thread_block.y - 1) / thread_block.y);
  const float3 _mean{mean[0], mean[1], mean[2]};
  const float3 _std{float(1. / std[0]), float(1. / std[1]), float(1. / std[2])};
  normalize<T, channels><<<num_blocks, thread_block, 0, stream>>>(src, height, width, stride,
                                                                  output, _mean, _std, to_rgb);
}

template void Normalize<uint8_t, 3>(const uint8_t* src, int height, int width, int stride,
                                    float* output, const float* mean, const float* std, bool to_rgb,
                                    hipStream_t stream);
template void Normalize<uint8_t, 1>(const uint8_t* src, int height, int width, int stride,
                                    float* output, const float* mean, const float* std, bool to_rgb,
                                    hipStream_t stream);

template void Normalize<float, 3>(const float* src, int height, int width, int stride,
                                  float* output, const float* mean, const float* std, bool to_rgb,
                                  hipStream_t stream);
template void Normalize<float, 1>(const float* src, int height, int width, int stride,
                                  float* output, const float* mean, const float* std, bool to_rgb,
                                  hipStream_t stream);
}  // namespace impl
}  // namespace cuda
}  // namespace operation
}  // namespace mmdeploy

	.text
	.file	"normalize.hip"
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0                          # -- Begin function _ZN8mmdeploy9operation4cuda4impl9NormalizeIhLi3EEEvPKT_iiiPfPKfS9_bP12ihipStream_t
.LCPI0_0:
	.long	0x3f800000                      # float 1
	.section	.text._ZN8mmdeploy9operation4cuda4impl9NormalizeIhLi3EEEvPKT_iiiPfPKfS9_bP12ihipStream_t,"axG",@progbits,_ZN8mmdeploy9operation4cuda4impl9NormalizeIhLi3EEEvPKT_iiiPfPKfS9_bP12ihipStream_t,comdat
	.weak	_ZN8mmdeploy9operation4cuda4impl9NormalizeIhLi3EEEvPKT_iiiPfPKfS9_bP12ihipStream_t
	.type	_ZN8mmdeploy9operation4cuda4impl9NormalizeIhLi3EEEvPKT_iiiPfPKfS9_bP12ihipStream_t,@function
_ZN8mmdeploy9operation4cuda4impl9NormalizeIhLi3EEEvPKT_iiiPfPKfS9_bP12ihipStream_t: # @_ZN8mmdeploy9operation4cuda4impl9NormalizeIhLi3EEEvPKT_iiiPfPKfS9_bP12ihipStream_t
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$56, %rsp
	.cfi_def_cfa_offset 112
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%r9, %rax
	movq	%r8, %rbx
	movl	%ecx, %ebp
	movl	%edx, %r14d
	movl	%esi, %r15d
	movq	%rdi, %r12
	movb	120(%rsp), %r13b
	movq	128(%rsp), %r9
	movq	112(%rsp), %rcx
	leal	15(%r14), %edx
	shrl	$4, %edx
	leal	15(%r15), %edi
	shrl	$4, %edi
	shlq	$32, %rdi
	orq	%rdx, %rdi
	movss	(%rax), %xmm0                   # xmm0 = mem[0],zero,zero,zero
	movaps	%xmm0, 32(%rsp)                 # 16-byte Spill
	movss	4(%rax), %xmm0                  # xmm0 = mem[0],zero,zero,zero
	movaps	%xmm0, 16(%rsp)                 # 16-byte Spill
	movss	8(%rax), %xmm0                  # xmm0 = mem[0],zero,zero,zero
	movss	%xmm0, 12(%rsp)                 # 4-byte Spill
	movss	(%rcx), %xmm0                   # xmm0 = mem[0],zero,zero,zero
	movss	%xmm0, (%rsp)                   # 4-byte Spill
	movss	4(%rcx), %xmm0                  # xmm0 = mem[0],zero,zero,zero
	movss	%xmm0, 4(%rsp)                  # 4-byte Spill
	movss	8(%rcx), %xmm0                  # xmm0 = mem[0],zero,zero,zero
	movss	%xmm0, 8(%rsp)                  # 4-byte Spill
	movabsq	$68719476752, %rdx              # imm = 0x1000000010
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	je	.LBB0_2
# %bb.1:
	addq	$56, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB0_2:
	.cfi_def_cfa_offset 112
	movss	.LCPI0_0(%rip), %xmm3           # xmm3 = mem[0],zero,zero,zero
	movaps	%xmm3, %xmm2
	divss	(%rsp), %xmm2                   # 4-byte Folded Reload
	movaps	%xmm3, %xmm0
	divss	4(%rsp), %xmm0                  # 4-byte Folded Reload
	unpcklps	%xmm0, %xmm2                    # xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1]
	divss	8(%rsp), %xmm3                  # 4-byte Folded Reload
	movaps	32(%rsp), %xmm0                 # 16-byte Reload
	unpcklps	16(%rsp), %xmm0                 # 16-byte Folded Reload
                                        # xmm0 = xmm0[0],mem[0],xmm0[1],mem[1]
	movzbl	%r13b, %r9d
	movq	%r12, %rdi
	movl	%r15d, %esi
	movl	%r14d, %edx
	movl	%ebp, %ecx
	movq	%rbx, %r8
	movss	12(%rsp), %xmm1                 # 4-byte Reload
                                        # xmm1 = mem[0],zero,zero,zero
	addq	$56, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_ZN8mmdeploy9operation4cuda4impl24__device_stub__normalizeIhLi3EEEvPKT_iiiPf15HIP_vector_typeIfLj3EES9_b # TAILCALL
.Lfunc_end0:
	.size	_ZN8mmdeploy9operation4cuda4impl9NormalizeIhLi3EEEvPKT_iiiPfPKfS9_bP12ihipStream_t, .Lfunc_end0-_ZN8mmdeploy9operation4cuda4impl9NormalizeIhLi3EEEvPKT_iiiPfPKfS9_bP12ihipStream_t
	.cfi_endproc
                                        # -- End function
	.section	.text._ZN8mmdeploy9operation4cuda4impl24__device_stub__normalizeIhLi3EEEvPKT_iiiPf15HIP_vector_typeIfLj3EES9_b,"axG",@progbits,_ZN8mmdeploy9operation4cuda4impl24__device_stub__normalizeIhLi3EEEvPKT_iiiPf15HIP_vector_typeIfLj3EES9_b,comdat
	.weak	_ZN8mmdeploy9operation4cuda4impl24__device_stub__normalizeIhLi3EEEvPKT_iiiPf15HIP_vector_typeIfLj3EES9_b # -- Begin function _ZN8mmdeploy9operation4cuda4impl24__device_stub__normalizeIhLi3EEEvPKT_iiiPf15HIP_vector_typeIfLj3EES9_b
	.type	_ZN8mmdeploy9operation4cuda4impl24__device_stub__normalizeIhLi3EEEvPKT_iiiPf15HIP_vector_typeIfLj3EES9_b,@function
_ZN8mmdeploy9operation4cuda4impl24__device_stub__normalizeIhLi3EEEvPKT_iiiPf15HIP_vector_typeIfLj3EES9_b: # @_ZN8mmdeploy9operation4cuda4impl24__device_stub__normalizeIhLi3EEEvPKT_iiiPf15HIP_vector_typeIfLj3EES9_b
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$176, %rsp
	.cfi_def_cfa_offset 224
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	96(%rsp), %rax
	movlps	%xmm0, (%rax)
	movss	%xmm1, 8(%rax)
	leaq	80(%rsp), %r10
	movlps	%xmm2, (%r10)
	movss	%xmm3, 8(%r10)
	leaq	40(%rsp), %r11
	movq	%rdi, (%r11)
	leaq	12(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	8(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	4(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	32(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	3(%rsp), %r8
	movb	%r9b, (%r8)
	leaq	112(%rsp), %rbx
	movq	%r11, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%rax, 40(%rbx)
	movq	%r10, 48(%rbx)
	movq	%r8, 56(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_ZN8mmdeploy9operation4cuda4impl9normalizeIhLi3EEEvPKT_iiiPf15HIP_vector_typeIfLj3EES9_b, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$192, %rsp
	.cfi_adjust_cfa_offset -192
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_ZN8mmdeploy9operation4cuda4impl24__device_stub__normalizeIhLi3EEEvPKT_iiiPf15HIP_vector_typeIfLj3EES9_b, .Lfunc_end1-_ZN8mmdeploy9operation4cuda4impl24__device_stub__normalizeIhLi3EEEvPKT_iiiPf15HIP_vector_typeIfLj3EES9_b
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0                          # -- Begin function _ZN8mmdeploy9operation4cuda4impl9NormalizeIhLi1EEEvPKT_iiiPfPKfS9_bP12ihipStream_t
.LCPI2_0:
	.long	0x3f800000                      # float 1
	.section	.text._ZN8mmdeploy9operation4cuda4impl9NormalizeIhLi1EEEvPKT_iiiPfPKfS9_bP12ihipStream_t,"axG",@progbits,_ZN8mmdeploy9operation4cuda4impl9NormalizeIhLi1EEEvPKT_iiiPfPKfS9_bP12ihipStream_t,comdat
	.weak	_ZN8mmdeploy9operation4cuda4impl9NormalizeIhLi1EEEvPKT_iiiPfPKfS9_bP12ihipStream_t
	.type	_ZN8mmdeploy9operation4cuda4impl9NormalizeIhLi1EEEvPKT_iiiPfPKfS9_bP12ihipStream_t,@function
_ZN8mmdeploy9operation4cuda4impl9NormalizeIhLi1EEEvPKT_iiiPfPKfS9_bP12ihipStream_t: # @_ZN8mmdeploy9operation4cuda4impl9NormalizeIhLi1EEEvPKT_iiiPfPKfS9_bP12ihipStream_t
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$56, %rsp
	.cfi_def_cfa_offset 112
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%r9, %rax
	movq	%r8, %rbx
	movl	%ecx, %ebp
	movl	%edx, %r14d
	movl	%esi, %r15d
	movq	%rdi, %r12
	movb	120(%rsp), %r13b
	movq	128(%rsp), %r9
	movq	112(%rsp), %rcx
	leal	15(%r14), %edx
	shrl	$4, %edx
	leal	15(%r15), %edi
	shrl	$4, %edi
	shlq	$32, %rdi
	orq	%rdx, %rdi
	movss	(%rax), %xmm0                   # xmm0 = mem[0],zero,zero,zero
	movaps	%xmm0, 32(%rsp)                 # 16-byte Spill
	movss	4(%rax), %xmm0                  # xmm0 = mem[0],zero,zero,zero
	movaps	%xmm0, 16(%rsp)                 # 16-byte Spill
	movss	8(%rax), %xmm0                  # xmm0 = mem[0],zero,zero,zero
	movss	%xmm0, 12(%rsp)                 # 4-byte Spill
	movss	(%rcx), %xmm0                   # xmm0 = mem[0],zero,zero,zero
	movss	%xmm0, (%rsp)                   # 4-byte Spill
	movss	4(%rcx), %xmm0                  # xmm0 = mem[0],zero,zero,zero
	movss	%xmm0, 4(%rsp)                  # 4-byte Spill
	movss	8(%rcx), %xmm0                  # xmm0 = mem[0],zero,zero,zero
	movss	%xmm0, 8(%rsp)                  # 4-byte Spill
	movabsq	$68719476752, %rdx              # imm = 0x1000000010
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	je	.LBB2_2
# %bb.1:
	addq	$56, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB2_2:
	.cfi_def_cfa_offset 112
	movss	.LCPI2_0(%rip), %xmm3           # xmm3 = mem[0],zero,zero,zero
	movaps	%xmm3, %xmm2
	divss	(%rsp), %xmm2                   # 4-byte Folded Reload
	movaps	%xmm3, %xmm0
	divss	4(%rsp), %xmm0                  # 4-byte Folded Reload
	unpcklps	%xmm0, %xmm2                    # xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1]
	divss	8(%rsp), %xmm3                  # 4-byte Folded Reload
	movaps	32(%rsp), %xmm0                 # 16-byte Reload
	unpcklps	16(%rsp), %xmm0                 # 16-byte Folded Reload
                                        # xmm0 = xmm0[0],mem[0],xmm0[1],mem[1]
	movzbl	%r13b, %r9d
	movq	%r12, %rdi
	movl	%r15d, %esi
	movl	%r14d, %edx
	movl	%ebp, %ecx
	movq	%rbx, %r8
	movss	12(%rsp), %xmm1                 # 4-byte Reload
                                        # xmm1 = mem[0],zero,zero,zero
	addq	$56, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_ZN8mmdeploy9operation4cuda4impl24__device_stub__normalizeIhLi1EEEvPKT_iiiPf15HIP_vector_typeIfLj3EES9_b # TAILCALL
.Lfunc_end2:
	.size	_ZN8mmdeploy9operation4cuda4impl9NormalizeIhLi1EEEvPKT_iiiPfPKfS9_bP12ihipStream_t, .Lfunc_end2-_ZN8mmdeploy9operation4cuda4impl9NormalizeIhLi1EEEvPKT_iiiPfPKfS9_bP12ihipStream_t
	.cfi_endproc
                                        # -- End function
	.section	.text._ZN8mmdeploy9operation4cuda4impl24__device_stub__normalizeIhLi1EEEvPKT_iiiPf15HIP_vector_typeIfLj3EES9_b,"axG",@progbits,_ZN8mmdeploy9operation4cuda4impl24__device_stub__normalizeIhLi1EEEvPKT_iiiPf15HIP_vector_typeIfLj3EES9_b,comdat
	.weak	_ZN8mmdeploy9operation4cuda4impl24__device_stub__normalizeIhLi1EEEvPKT_iiiPf15HIP_vector_typeIfLj3EES9_b # -- Begin function _ZN8mmdeploy9operation4cuda4impl24__device_stub__normalizeIhLi1EEEvPKT_iiiPf15HIP_vector_typeIfLj3EES9_b
	.type	_ZN8mmdeploy9operation4cuda4impl24__device_stub__normalizeIhLi1EEEvPKT_iiiPf15HIP_vector_typeIfLj3EES9_b,@function
_ZN8mmdeploy9operation4cuda4impl24__device_stub__normalizeIhLi1EEEvPKT_iiiPf15HIP_vector_typeIfLj3EES9_b: # @_ZN8mmdeploy9operation4cuda4impl24__device_stub__normalizeIhLi1EEEvPKT_iiiPf15HIP_vector_typeIfLj3EES9_b
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$176, %rsp
	.cfi_def_cfa_offset 224
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	96(%rsp), %rax
	movlps	%xmm0, (%rax)
	movss	%xmm1, 8(%rax)
	leaq	80(%rsp), %r10
	movlps	%xmm2, (%r10)
	movss	%xmm3, 8(%r10)
	leaq	40(%rsp), %r11
	movq	%rdi, (%r11)
	leaq	12(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	8(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	4(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	32(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	3(%rsp), %r8
	movb	%r9b, (%r8)
	leaq	112(%rsp), %rbx
	movq	%r11, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%rax, 40(%rbx)
	movq	%r10, 48(%rbx)
	movq	%r8, 56(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_ZN8mmdeploy9operation4cuda4impl9normalizeIhLi1EEEvPKT_iiiPf15HIP_vector_typeIfLj3EES9_b, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$192, %rsp
	.cfi_adjust_cfa_offset -192
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	_ZN8mmdeploy9operation4cuda4impl24__device_stub__normalizeIhLi1EEEvPKT_iiiPf15HIP_vector_typeIfLj3EES9_b, .Lfunc_end3-_ZN8mmdeploy9operation4cuda4impl24__device_stub__normalizeIhLi1EEEvPKT_iiiPf15HIP_vector_typeIfLj3EES9_b
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0                          # -- Begin function _ZN8mmdeploy9operation4cuda4impl9NormalizeIfLi3EEEvPKT_iiiPfPKfS9_bP12ihipStream_t
.LCPI4_0:
	.long	0x3f800000                      # float 1
	.section	.text._ZN8mmdeploy9operation4cuda4impl9NormalizeIfLi3EEEvPKT_iiiPfPKfS9_bP12ihipStream_t,"axG",@progbits,_ZN8mmdeploy9operation4cuda4impl9NormalizeIfLi3EEEvPKT_iiiPfPKfS9_bP12ihipStream_t,comdat
	.weak	_ZN8mmdeploy9operation4cuda4impl9NormalizeIfLi3EEEvPKT_iiiPfPKfS9_bP12ihipStream_t
	.type	_ZN8mmdeploy9operation4cuda4impl9NormalizeIfLi3EEEvPKT_iiiPfPKfS9_bP12ihipStream_t,@function
_ZN8mmdeploy9operation4cuda4impl9NormalizeIfLi3EEEvPKT_iiiPfPKfS9_bP12ihipStream_t: # @_ZN8mmdeploy9operation4cuda4impl9NormalizeIfLi3EEEvPKT_iiiPfPKfS9_bP12ihipStream_t
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$56, %rsp
	.cfi_def_cfa_offset 112
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%r9, %rax
	movq	%r8, %rbx
	movl	%ecx, %ebp
	movl	%edx, %r14d
	movl	%esi, %r15d
	movq	%rdi, %r12
	movb	120(%rsp), %r13b
	movq	128(%rsp), %r9
	movq	112(%rsp), %rcx
	leal	15(%r14), %edx
	shrl	$4, %edx
	leal	15(%r15), %edi
	shrl	$4, %edi
	shlq	$32, %rdi
	orq	%rdx, %rdi
	movss	(%rax), %xmm0                   # xmm0 = mem[0],zero,zero,zero
	movaps	%xmm0, 32(%rsp)                 # 16-byte Spill
	movss	4(%rax), %xmm0                  # xmm0 = mem[0],zero,zero,zero
	movaps	%xmm0, 16(%rsp)                 # 16-byte Spill
	movss	8(%rax), %xmm0                  # xmm0 = mem[0],zero,zero,zero
	movss	%xmm0, 12(%rsp)                 # 4-byte Spill
	movss	(%rcx), %xmm0                   # xmm0 = mem[0],zero,zero,zero
	movss	%xmm0, (%rsp)                   # 4-byte Spill
	movss	4(%rcx), %xmm0                  # xmm0 = mem[0],zero,zero,zero
	movss	%xmm0, 4(%rsp)                  # 4-byte Spill
	movss	8(%rcx), %xmm0                  # xmm0 = mem[0],zero,zero,zero
	movss	%xmm0, 8(%rsp)                  # 4-byte Spill
	movabsq	$68719476752, %rdx              # imm = 0x1000000010
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	je	.LBB4_2
# %bb.1:
	addq	$56, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB4_2:
	.cfi_def_cfa_offset 112
	movss	.LCPI4_0(%rip), %xmm3           # xmm3 = mem[0],zero,zero,zero
	movaps	%xmm3, %xmm2
	divss	(%rsp), %xmm2                   # 4-byte Folded Reload
	movaps	%xmm3, %xmm0
	divss	4(%rsp), %xmm0                  # 4-byte Folded Reload
	unpcklps	%xmm0, %xmm2                    # xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1]
	divss	8(%rsp), %xmm3                  # 4-byte Folded Reload
	movaps	32(%rsp), %xmm0                 # 16-byte Reload
	unpcklps	16(%rsp), %xmm0                 # 16-byte Folded Reload
                                        # xmm0 = xmm0[0],mem[0],xmm0[1],mem[1]
	movzbl	%r13b, %r9d
	movq	%r12, %rdi
	movl	%r15d, %esi
	movl	%r14d, %edx
	movl	%ebp, %ecx
	movq	%rbx, %r8
	movss	12(%rsp), %xmm1                 # 4-byte Reload
                                        # xmm1 = mem[0],zero,zero,zero
	addq	$56, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_ZN8mmdeploy9operation4cuda4impl24__device_stub__normalizeIfLi3EEEvPKT_iiiPf15HIP_vector_typeIfLj3EES9_b # TAILCALL
.Lfunc_end4:
	.size	_ZN8mmdeploy9operation4cuda4impl9NormalizeIfLi3EEEvPKT_iiiPfPKfS9_bP12ihipStream_t, .Lfunc_end4-_ZN8mmdeploy9operation4cuda4impl9NormalizeIfLi3EEEvPKT_iiiPfPKfS9_bP12ihipStream_t
	.cfi_endproc
                                        # -- End function
	.section	.text._ZN8mmdeploy9operation4cuda4impl24__device_stub__normalizeIfLi3EEEvPKT_iiiPf15HIP_vector_typeIfLj3EES9_b,"axG",@progbits,_ZN8mmdeploy9operation4cuda4impl24__device_stub__normalizeIfLi3EEEvPKT_iiiPf15HIP_vector_typeIfLj3EES9_b,comdat
	.weak	_ZN8mmdeploy9operation4cuda4impl24__device_stub__normalizeIfLi3EEEvPKT_iiiPf15HIP_vector_typeIfLj3EES9_b # -- Begin function _ZN8mmdeploy9operation4cuda4impl24__device_stub__normalizeIfLi3EEEvPKT_iiiPf15HIP_vector_typeIfLj3EES9_b
	.type	_ZN8mmdeploy9operation4cuda4impl24__device_stub__normalizeIfLi3EEEvPKT_iiiPf15HIP_vector_typeIfLj3EES9_b,@function
_ZN8mmdeploy9operation4cuda4impl24__device_stub__normalizeIfLi3EEEvPKT_iiiPf15HIP_vector_typeIfLj3EES9_b: # @_ZN8mmdeploy9operation4cuda4impl24__device_stub__normalizeIfLi3EEEvPKT_iiiPf15HIP_vector_typeIfLj3EES9_b
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$176, %rsp
	.cfi_def_cfa_offset 224
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	96(%rsp), %rax
	movlps	%xmm0, (%rax)
	movss	%xmm1, 8(%rax)
	leaq	80(%rsp), %r10
	movlps	%xmm2, (%r10)
	movss	%xmm3, 8(%r10)
	leaq	40(%rsp), %r11
	movq	%rdi, (%r11)
	leaq	12(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	8(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	4(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	32(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	3(%rsp), %r8
	movb	%r9b, (%r8)
	leaq	112(%rsp), %rbx
	movq	%r11, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%rax, 40(%rbx)
	movq	%r10, 48(%rbx)
	movq	%r8, 56(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_ZN8mmdeploy9operation4cuda4impl9normalizeIfLi3EEEvPKT_iiiPf15HIP_vector_typeIfLj3EES9_b, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$192, %rsp
	.cfi_adjust_cfa_offset -192
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end5:
	.size	_ZN8mmdeploy9operation4cuda4impl24__device_stub__normalizeIfLi3EEEvPKT_iiiPf15HIP_vector_typeIfLj3EES9_b, .Lfunc_end5-_ZN8mmdeploy9operation4cuda4impl24__device_stub__normalizeIfLi3EEEvPKT_iiiPf15HIP_vector_typeIfLj3EES9_b
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0                          # -- Begin function _ZN8mmdeploy9operation4cuda4impl9NormalizeIfLi1EEEvPKT_iiiPfPKfS9_bP12ihipStream_t
.LCPI6_0:
	.long	0x3f800000                      # float 1
	.section	.text._ZN8mmdeploy9operation4cuda4impl9NormalizeIfLi1EEEvPKT_iiiPfPKfS9_bP12ihipStream_t,"axG",@progbits,_ZN8mmdeploy9operation4cuda4impl9NormalizeIfLi1EEEvPKT_iiiPfPKfS9_bP12ihipStream_t,comdat
	.weak	_ZN8mmdeploy9operation4cuda4impl9NormalizeIfLi1EEEvPKT_iiiPfPKfS9_bP12ihipStream_t
	.type	_ZN8mmdeploy9operation4cuda4impl9NormalizeIfLi1EEEvPKT_iiiPfPKfS9_bP12ihipStream_t,@function
_ZN8mmdeploy9operation4cuda4impl9NormalizeIfLi1EEEvPKT_iiiPfPKfS9_bP12ihipStream_t: # @_ZN8mmdeploy9operation4cuda4impl9NormalizeIfLi1EEEvPKT_iiiPfPKfS9_bP12ihipStream_t
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$56, %rsp
	.cfi_def_cfa_offset 112
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%r9, %rax
	movq	%r8, %rbx
	movl	%ecx, %ebp
	movl	%edx, %r14d
	movl	%esi, %r15d
	movq	%rdi, %r12
	movb	120(%rsp), %r13b
	movq	128(%rsp), %r9
	movq	112(%rsp), %rcx
	leal	15(%r14), %edx
	shrl	$4, %edx
	leal	15(%r15), %edi
	shrl	$4, %edi
	shlq	$32, %rdi
	orq	%rdx, %rdi
	movss	(%rax), %xmm0                   # xmm0 = mem[0],zero,zero,zero
	movaps	%xmm0, 32(%rsp)                 # 16-byte Spill
	movss	4(%rax), %xmm0                  # xmm0 = mem[0],zero,zero,zero
	movaps	%xmm0, 16(%rsp)                 # 16-byte Spill
	movss	8(%rax), %xmm0                  # xmm0 = mem[0],zero,zero,zero
	movss	%xmm0, 12(%rsp)                 # 4-byte Spill
	movss	(%rcx), %xmm0                   # xmm0 = mem[0],zero,zero,zero
	movss	%xmm0, (%rsp)                   # 4-byte Spill
	movss	4(%rcx), %xmm0                  # xmm0 = mem[0],zero,zero,zero
	movss	%xmm0, 4(%rsp)                  # 4-byte Spill
	movss	8(%rcx), %xmm0                  # xmm0 = mem[0],zero,zero,zero
	movss	%xmm0, 8(%rsp)                  # 4-byte Spill
	movabsq	$68719476752, %rdx              # imm = 0x1000000010
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	je	.LBB6_2
# %bb.1:
	addq	$56, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB6_2:
	.cfi_def_cfa_offset 112
	movss	.LCPI6_0(%rip), %xmm3           # xmm3 = mem[0],zero,zero,zero
	movaps	%xmm3, %xmm2
	divss	(%rsp), %xmm2                   # 4-byte Folded Reload
	movaps	%xmm3, %xmm0
	divss	4(%rsp), %xmm0                  # 4-byte Folded Reload
	unpcklps	%xmm0, %xmm2                    # xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1]
	divss	8(%rsp), %xmm3                  # 4-byte Folded Reload
	movaps	32(%rsp), %xmm0                 # 16-byte Reload
	unpcklps	16(%rsp), %xmm0                 # 16-byte Folded Reload
                                        # xmm0 = xmm0[0],mem[0],xmm0[1],mem[1]
	movzbl	%r13b, %r9d
	movq	%r12, %rdi
	movl	%r15d, %esi
	movl	%r14d, %edx
	movl	%ebp, %ecx
	movq	%rbx, %r8
	movss	12(%rsp), %xmm1                 # 4-byte Reload
                                        # xmm1 = mem[0],zero,zero,zero
	addq	$56, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_ZN8mmdeploy9operation4cuda4impl24__device_stub__normalizeIfLi1EEEvPKT_iiiPf15HIP_vector_typeIfLj3EES9_b # TAILCALL
.Lfunc_end6:
	.size	_ZN8mmdeploy9operation4cuda4impl9NormalizeIfLi1EEEvPKT_iiiPfPKfS9_bP12ihipStream_t, .Lfunc_end6-_ZN8mmdeploy9operation4cuda4impl9NormalizeIfLi1EEEvPKT_iiiPfPKfS9_bP12ihipStream_t
	.cfi_endproc
                                        # -- End function
	.section	.text._ZN8mmdeploy9operation4cuda4impl24__device_stub__normalizeIfLi1EEEvPKT_iiiPf15HIP_vector_typeIfLj3EES9_b,"axG",@progbits,_ZN8mmdeploy9operation4cuda4impl24__device_stub__normalizeIfLi1EEEvPKT_iiiPf15HIP_vector_typeIfLj3EES9_b,comdat
	.weak	_ZN8mmdeploy9operation4cuda4impl24__device_stub__normalizeIfLi1EEEvPKT_iiiPf15HIP_vector_typeIfLj3EES9_b # -- Begin function _ZN8mmdeploy9operation4cuda4impl24__device_stub__normalizeIfLi1EEEvPKT_iiiPf15HIP_vector_typeIfLj3EES9_b
	.type	_ZN8mmdeploy9operation4cuda4impl24__device_stub__normalizeIfLi1EEEvPKT_iiiPf15HIP_vector_typeIfLj3EES9_b,@function
_ZN8mmdeploy9operation4cuda4impl24__device_stub__normalizeIfLi1EEEvPKT_iiiPf15HIP_vector_typeIfLj3EES9_b: # @_ZN8mmdeploy9operation4cuda4impl24__device_stub__normalizeIfLi1EEEvPKT_iiiPf15HIP_vector_typeIfLj3EES9_b
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$176, %rsp
	.cfi_def_cfa_offset 224
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	96(%rsp), %rax
	movlps	%xmm0, (%rax)
	movss	%xmm1, 8(%rax)
	leaq	80(%rsp), %r10
	movlps	%xmm2, (%r10)
	movss	%xmm3, 8(%r10)
	leaq	40(%rsp), %r11
	movq	%rdi, (%r11)
	leaq	12(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	8(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	4(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	32(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	3(%rsp), %r8
	movb	%r9b, (%r8)
	leaq	112(%rsp), %rbx
	movq	%r11, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%rax, 40(%rbx)
	movq	%r10, 48(%rbx)
	movq	%r8, 56(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_ZN8mmdeploy9operation4cuda4impl9normalizeIfLi1EEEvPKT_iiiPf15HIP_vector_typeIfLj3EES9_b, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$192, %rsp
	.cfi_adjust_cfa_offset -192
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end7:
	.size	_ZN8mmdeploy9operation4cuda4impl24__device_stub__normalizeIfLi1EEEvPKT_iiiPf15HIP_vector_typeIfLj3EES9_b, .Lfunc_end7-_ZN8mmdeploy9operation4cuda4impl24__device_stub__normalizeIfLi1EEEvPKT_iiiPf15HIP_vector_typeIfLj3EES9_b
	.cfi_endproc
                                        # -- End function
	.text
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB8_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB8_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_ZN8mmdeploy9operation4cuda4impl9normalizeIhLi3EEEvPKT_iiiPf15HIP_vector_typeIfLj3EES9_b, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_ZN8mmdeploy9operation4cuda4impl9normalizeIhLi1EEEvPKT_iiiPf15HIP_vector_typeIfLj3EES9_b, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_ZN8mmdeploy9operation4cuda4impl9normalizeIfLi3EEEvPKT_iiiPf15HIP_vector_typeIfLj3EES9_b, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_ZN8mmdeploy9operation4cuda4impl9normalizeIfLi1EEEvPKT_iiiPf15HIP_vector_typeIfLj3EES9_b, %esi
	movl	$.L__unnamed_4, %edx
	movl	$.L__unnamed_4, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end8:
	.size	__hip_module_ctor, .Lfunc_end8-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB9_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB9_2:
	retq
.Lfunc_end9:
	.size	__hip_module_dtor, .Lfunc_end9-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_ZN8mmdeploy9operation4cuda4impl9normalizeIhLi3EEEvPKT_iiiPf15HIP_vector_typeIfLj3EES9_b,@object # @_ZN8mmdeploy9operation4cuda4impl9normalizeIhLi3EEEvPKT_iiiPf15HIP_vector_typeIfLj3EES9_b
	.section	.rodata._ZN8mmdeploy9operation4cuda4impl9normalizeIhLi3EEEvPKT_iiiPf15HIP_vector_typeIfLj3EES9_b,"aG",@progbits,_ZN8mmdeploy9operation4cuda4impl9normalizeIhLi3EEEvPKT_iiiPf15HIP_vector_typeIfLj3EES9_b,comdat
	.weak	_ZN8mmdeploy9operation4cuda4impl9normalizeIhLi3EEEvPKT_iiiPf15HIP_vector_typeIfLj3EES9_b
	.p2align	3, 0x0
_ZN8mmdeploy9operation4cuda4impl9normalizeIhLi3EEEvPKT_iiiPf15HIP_vector_typeIfLj3EES9_b:
	.quad	_ZN8mmdeploy9operation4cuda4impl24__device_stub__normalizeIhLi3EEEvPKT_iiiPf15HIP_vector_typeIfLj3EES9_b
	.size	_ZN8mmdeploy9operation4cuda4impl9normalizeIhLi3EEEvPKT_iiiPf15HIP_vector_typeIfLj3EES9_b, 8

	.type	_ZN8mmdeploy9operation4cuda4impl9normalizeIhLi1EEEvPKT_iiiPf15HIP_vector_typeIfLj3EES9_b,@object # @_ZN8mmdeploy9operation4cuda4impl9normalizeIhLi1EEEvPKT_iiiPf15HIP_vector_typeIfLj3EES9_b
	.section	.rodata._ZN8mmdeploy9operation4cuda4impl9normalizeIhLi1EEEvPKT_iiiPf15HIP_vector_typeIfLj3EES9_b,"aG",@progbits,_ZN8mmdeploy9operation4cuda4impl9normalizeIhLi1EEEvPKT_iiiPf15HIP_vector_typeIfLj3EES9_b,comdat
	.weak	_ZN8mmdeploy9operation4cuda4impl9normalizeIhLi1EEEvPKT_iiiPf15HIP_vector_typeIfLj3EES9_b
	.p2align	3, 0x0
_ZN8mmdeploy9operation4cuda4impl9normalizeIhLi1EEEvPKT_iiiPf15HIP_vector_typeIfLj3EES9_b:
	.quad	_ZN8mmdeploy9operation4cuda4impl24__device_stub__normalizeIhLi1EEEvPKT_iiiPf15HIP_vector_typeIfLj3EES9_b
	.size	_ZN8mmdeploy9operation4cuda4impl9normalizeIhLi1EEEvPKT_iiiPf15HIP_vector_typeIfLj3EES9_b, 8

	.type	_ZN8mmdeploy9operation4cuda4impl9normalizeIfLi3EEEvPKT_iiiPf15HIP_vector_typeIfLj3EES9_b,@object # @_ZN8mmdeploy9operation4cuda4impl9normalizeIfLi3EEEvPKT_iiiPf15HIP_vector_typeIfLj3EES9_b
	.section	.rodata._ZN8mmdeploy9operation4cuda4impl9normalizeIfLi3EEEvPKT_iiiPf15HIP_vector_typeIfLj3EES9_b,"aG",@progbits,_ZN8mmdeploy9operation4cuda4impl9normalizeIfLi3EEEvPKT_iiiPf15HIP_vector_typeIfLj3EES9_b,comdat
	.weak	_ZN8mmdeploy9operation4cuda4impl9normalizeIfLi3EEEvPKT_iiiPf15HIP_vector_typeIfLj3EES9_b
	.p2align	3, 0x0
_ZN8mmdeploy9operation4cuda4impl9normalizeIfLi3EEEvPKT_iiiPf15HIP_vector_typeIfLj3EES9_b:
	.quad	_ZN8mmdeploy9operation4cuda4impl24__device_stub__normalizeIfLi3EEEvPKT_iiiPf15HIP_vector_typeIfLj3EES9_b
	.size	_ZN8mmdeploy9operation4cuda4impl9normalizeIfLi3EEEvPKT_iiiPf15HIP_vector_typeIfLj3EES9_b, 8

	.type	_ZN8mmdeploy9operation4cuda4impl9normalizeIfLi1EEEvPKT_iiiPf15HIP_vector_typeIfLj3EES9_b,@object # @_ZN8mmdeploy9operation4cuda4impl9normalizeIfLi1EEEvPKT_iiiPf15HIP_vector_typeIfLj3EES9_b
	.section	.rodata._ZN8mmdeploy9operation4cuda4impl9normalizeIfLi1EEEvPKT_iiiPf15HIP_vector_typeIfLj3EES9_b,"aG",@progbits,_ZN8mmdeploy9operation4cuda4impl9normalizeIfLi1EEEvPKT_iiiPf15HIP_vector_typeIfLj3EES9_b,comdat
	.weak	_ZN8mmdeploy9operation4cuda4impl9normalizeIfLi1EEEvPKT_iiiPf15HIP_vector_typeIfLj3EES9_b
	.p2align	3, 0x0
_ZN8mmdeploy9operation4cuda4impl9normalizeIfLi1EEEvPKT_iiiPf15HIP_vector_typeIfLj3EES9_b:
	.quad	_ZN8mmdeploy9operation4cuda4impl24__device_stub__normalizeIfLi1EEEvPKT_iiiPf15HIP_vector_typeIfLj3EES9_b
	.size	_ZN8mmdeploy9operation4cuda4impl9normalizeIfLi1EEEvPKT_iiiPf15HIP_vector_typeIfLj3EES9_b, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_ZN8mmdeploy9operation4cuda4impl9normalizeIhLi3EEEvPKT_iiiPf15HIP_vector_typeIfLj3EES9_b"
	.size	.L__unnamed_1, 89

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_ZN8mmdeploy9operation4cuda4impl9normalizeIhLi1EEEvPKT_iiiPf15HIP_vector_typeIfLj3EES9_b"
	.size	.L__unnamed_2, 89

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_ZN8mmdeploy9operation4cuda4impl9normalizeIfLi3EEEvPKT_iiiPf15HIP_vector_typeIfLj3EES9_b"
	.size	.L__unnamed_3, 89

	.type	.L__unnamed_4,@object           # @3
.L__unnamed_4:
	.asciz	"_ZN8mmdeploy9operation4cuda4impl9normalizeIfLi1EEEvPKT_iiiPf15HIP_vector_typeIfLj3EES9_b"
	.size	.L__unnamed_4, 89

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _ZN8mmdeploy9operation4cuda4impl24__device_stub__normalizeIhLi3EEEvPKT_iiiPf15HIP_vector_typeIfLj3EES9_b
	.addrsig_sym _ZN8mmdeploy9operation4cuda4impl24__device_stub__normalizeIhLi1EEEvPKT_iiiPf15HIP_vector_typeIfLj3EES9_b
	.addrsig_sym _ZN8mmdeploy9operation4cuda4impl24__device_stub__normalizeIfLi3EEEvPKT_iiiPf15HIP_vector_typeIfLj3EES9_b
	.addrsig_sym _ZN8mmdeploy9operation4cuda4impl24__device_stub__normalizeIfLi1EEEvPKT_iiiPf15HIP_vector_typeIfLj3EES9_b
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _ZN8mmdeploy9operation4cuda4impl9normalizeIhLi3EEEvPKT_iiiPf15HIP_vector_typeIfLj3EES9_b
	.addrsig_sym _ZN8mmdeploy9operation4cuda4impl9normalizeIhLi1EEEvPKT_iiiPf15HIP_vector_typeIfLj3EES9_b
	.addrsig_sym _ZN8mmdeploy9operation4cuda4impl9normalizeIfLi3EEEvPKT_iiiPf15HIP_vector_typeIfLj3EES9_b
	.addrsig_sym _ZN8mmdeploy9operation4cuda4impl9normalizeIfLi1EEEvPKT_iiiPf15HIP_vector_typeIfLj3EES9_b
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.section	.text._ZN8mmdeploy9operation4cuda4impl9normalizeIhLi3EEEvPKT_iiiPf15HIP_vector_typeIfLj3EES9_b,"axG",@progbits,_ZN8mmdeploy9operation4cuda4impl9normalizeIhLi3EEEvPKT_iiiPf15HIP_vector_typeIfLj3EES9_b,comdat
	.protected	_ZN8mmdeploy9operation4cuda4impl9normalizeIhLi3EEEvPKT_iiiPf15HIP_vector_typeIfLj3EES9_b ; -- Begin function _ZN8mmdeploy9operation4cuda4impl9normalizeIhLi3EEEvPKT_iiiPf15HIP_vector_typeIfLj3EES9_b
	.globl	_ZN8mmdeploy9operation4cuda4impl9normalizeIhLi3EEEvPKT_iiiPf15HIP_vector_typeIfLj3EES9_b
	.p2align	8
	.type	_ZN8mmdeploy9operation4cuda4impl9normalizeIhLi3EEEvPKT_iiiPf15HIP_vector_typeIfLj3EES9_b,@function
_ZN8mmdeploy9operation4cuda4impl9normalizeIhLi3EEEvPKT_iiiPf15HIP_vector_typeIfLj3EES9_b: ; @_ZN8mmdeploy9operation4cuda4impl9normalizeIhLi3EEEvPKT_iiiPf15HIP_vector_typeIfLj3EES9_b
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x4c
	s_load_b128 s[4:7], s[0:1], 0x8
	v_and_b32_e32 v2, 0x3ff, v0
	v_bfe_u32 v4, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s2, 16
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[0:1], null, s14, s2, v[2:3]
	v_mad_u64_u32 v[2:3], null, s15, s3, v[4:5]
	v_cmp_gt_i32_e32 vcc_lo, s5, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_gt_i32_e64 s2, s4, v2
	s_and_b32 s2, vcc_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_8
; %bb.1:
	s_clause 0x2
	s_load_b32 s7, s[0:1], 0x38
	s_load_b64 s[2:3], s[0:1], 0x0
	s_load_b64 s[4:5], s[0:1], 0x18
	v_lshl_add_u32 v3, v0, 1, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[0:1], null, v2, s6, v[3:4]
	s_waitcnt lgkmcnt(0)
	s_bitcmp1_b32 s7, 0
	s_cselect_b32 s6, -1, 0
	s_and_b32 vcc_lo, exec_lo, s6
	s_mov_b32 s6, -1
	s_cbranch_vccnz .LBB0_5
; %bb.2:                                ; %.preheader38.preheader
	s_delay_alu instid0(VALU_DEP_1)
	v_mov_b32_e32 v1, v0
	s_mov_b64 s[6:7], 0
.LBB0_3:                                ; %.preheader38
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v2, 31, v1
	v_add_co_u32 v3, vcc_lo, s2, v1
	s_add_u32 s8, s0, s6
	s_addc_u32 s9, s1, s7
	v_add_co_ci_u32_e32 v4, vcc_lo, s3, v2, vcc_lo
	s_add_u32 s6, s6, 4
	s_addc_u32 s7, s7, 0
	s_cmp_lg_u32 s6, 12
	global_load_u8 v3, v[3:4], off
	s_clause 0x1
	s_load_b32 s10, s[8:9], 0x20
	s_load_b32 s8, s[8:9], 0x2c
	s_waitcnt vmcnt(0)
	v_cvt_f32_ubyte0_e32 v4, v3
	v_lshlrev_b64 v[2:3], 2, v[1:2]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_subrev_f32 v4, s10, v4 :: v_dual_add_nc_u32 v1, 1, v1
	v_add_co_u32 v2, vcc_lo, s4, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
	v_mul_f32_e32 v4, s8, v4
	global_store_b32 v[2:3], v4, off
	s_cbranch_scc1 .LBB0_3
; %bb.4:                                ; %Flow
	s_mov_b32 s6, 0
.LBB0_5:                                ; %Flow82
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s6
	s_cbranch_vccz .LBB0_8
; %bb.6:                                ; %.preheader
	v_add_nc_u32_e32 v2, 2, v0
	s_mov_b64 s[6:7], 0
.LBB0_7:                                ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v1, 31, v2
	v_add_co_u32 v3, vcc_lo, s2, v2
	s_add_u32 s8, s0, s6
	s_addc_u32 s9, s1, s7
	v_add_co_ci_u32_e32 v4, vcc_lo, s3, v1, vcc_lo
	v_ashrrev_i32_e32 v1, 31, v0
	s_add_u32 s6, s6, 4
	s_addc_u32 s7, s7, 0
	global_load_u8 v3, v[3:4], off
	s_clause 0x1
	s_load_b32 s10, s[8:9], 0x20
	s_load_b32 s8, s[8:9], 0x2c
	s_cmp_eq_u32 s6, 12
	s_waitcnt vmcnt(0)
	v_cvt_f32_ubyte0_e32 v5, v3
	v_lshlrev_b64 v[3:4], 2, v[0:1]
	v_add_nc_u32_e32 v2, -1, v2
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_subrev_f32 v1, s10, v5 :: v_dual_add_nc_u32 v0, 1, v0
	v_add_co_u32 v3, vcc_lo, s4, v3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
	v_mul_f32_e32 v1, s8, v1
	global_store_b32 v[3:4], v1, off
	s_cbranch_scc0 .LBB0_7
.LBB0_8:                                ; %.loopexit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _ZN8mmdeploy9operation4cuda4impl9normalizeIhLi3EEEvPKT_iiiPf15HIP_vector_typeIfLj3EES9_b
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 320
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 6
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._ZN8mmdeploy9operation4cuda4impl9normalizeIhLi3EEEvPKT_iiiPf15HIP_vector_typeIfLj3EES9_b,"axG",@progbits,_ZN8mmdeploy9operation4cuda4impl9normalizeIhLi3EEEvPKT_iiiPf15HIP_vector_typeIfLj3EES9_b,comdat
.Lfunc_end0:
	.size	_ZN8mmdeploy9operation4cuda4impl9normalizeIhLi3EEEvPKT_iiiPf15HIP_vector_typeIfLj3EES9_b, .Lfunc_end0-_ZN8mmdeploy9operation4cuda4impl9normalizeIhLi3EEEvPKT_iiiPf15HIP_vector_typeIfLj3EES9_b
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 496
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.section	.text._ZN8mmdeploy9operation4cuda4impl9normalizeIhLi1EEEvPKT_iiiPf15HIP_vector_typeIfLj3EES9_b,"axG",@progbits,_ZN8mmdeploy9operation4cuda4impl9normalizeIhLi1EEEvPKT_iiiPf15HIP_vector_typeIfLj3EES9_b,comdat
	.protected	_ZN8mmdeploy9operation4cuda4impl9normalizeIhLi1EEEvPKT_iiiPf15HIP_vector_typeIfLj3EES9_b ; -- Begin function _ZN8mmdeploy9operation4cuda4impl9normalizeIhLi1EEEvPKT_iiiPf15HIP_vector_typeIfLj3EES9_b
	.globl	_ZN8mmdeploy9operation4cuda4impl9normalizeIhLi1EEEvPKT_iiiPf15HIP_vector_typeIfLj3EES9_b
	.p2align	8
	.type	_ZN8mmdeploy9operation4cuda4impl9normalizeIhLi1EEEvPKT_iiiPf15HIP_vector_typeIfLj3EES9_b,@function
_ZN8mmdeploy9operation4cuda4impl9normalizeIhLi1EEEvPKT_iiiPf15HIP_vector_typeIfLj3EES9_b: ; @_ZN8mmdeploy9operation4cuda4impl9normalizeIhLi1EEEvPKT_iiiPf15HIP_vector_typeIfLj3EES9_b
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x4c
	s_load_b128 s[4:7], s[0:1], 0x8
	v_and_b32_e32 v2, 0x3ff, v0
	v_bfe_u32 v3, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s2, 16
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[0:1], null, s14, s2, v[2:3]
	v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_i32_e32 vcc_lo, s5, v0
	v_cmp_gt_i32_e64 s2, s4, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, vcc_lo, s2
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB1_2
; %bb.1:
	s_load_b64 s[2:3], s[0:1], 0x0
	v_mad_u64_u32 v[2:3], null, v1, s6, v[0:1]
	s_clause 0x2
	s_load_b64 s[4:5], s[0:1], 0x18
	s_load_b32 s6, s[0:1], 0x20
	s_load_b32 s0, s[0:1], 0x2c
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v3, 31, v2
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v0, vcc_lo, s2, v2
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v3, vcc_lo
	global_load_u8 v0, v[0:1], off
	s_waitcnt vmcnt(0)
	v_cvt_f32_ubyte0_e32 v0, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_f32_e32 v4, s6, v0
	v_lshlrev_b64 v[0:1], 2, v[2:3]
	v_mul_f32_e32 v2, s0, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v0, vcc_lo, s4, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
	global_store_b32 v[0:1], v2, off
.LBB1_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _ZN8mmdeploy9operation4cuda4impl9normalizeIhLi1EEEvPKT_iiiPf15HIP_vector_typeIfLj3EES9_b
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 320
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 5
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._ZN8mmdeploy9operation4cuda4impl9normalizeIhLi1EEEvPKT_iiiPf15HIP_vector_typeIfLj3EES9_b,"axG",@progbits,_ZN8mmdeploy9operation4cuda4impl9normalizeIhLi1EEEvPKT_iiiPf15HIP_vector_typeIfLj3EES9_b,comdat
.Lfunc_end1:
	.size	_ZN8mmdeploy9operation4cuda4impl9normalizeIhLi1EEEvPKT_iiiPf15HIP_vector_typeIfLj3EES9_b, .Lfunc_end1-_ZN8mmdeploy9operation4cuda4impl9normalizeIhLi1EEEvPKT_iiiPf15HIP_vector_typeIfLj3EES9_b
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 244
; NumSgprs: 18
; NumVgprs: 5
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 5
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.section	.text._ZN8mmdeploy9operation4cuda4impl9normalizeIfLi3EEEvPKT_iiiPf15HIP_vector_typeIfLj3EES9_b,"axG",@progbits,_ZN8mmdeploy9operation4cuda4impl9normalizeIfLi3EEEvPKT_iiiPf15HIP_vector_typeIfLj3EES9_b,comdat
	.protected	_ZN8mmdeploy9operation4cuda4impl9normalizeIfLi3EEEvPKT_iiiPf15HIP_vector_typeIfLj3EES9_b ; -- Begin function _ZN8mmdeploy9operation4cuda4impl9normalizeIfLi3EEEvPKT_iiiPf15HIP_vector_typeIfLj3EES9_b
	.globl	_ZN8mmdeploy9operation4cuda4impl9normalizeIfLi3EEEvPKT_iiiPf15HIP_vector_typeIfLj3EES9_b
	.p2align	8
	.type	_ZN8mmdeploy9operation4cuda4impl9normalizeIfLi3EEEvPKT_iiiPf15HIP_vector_typeIfLj3EES9_b,@function
_ZN8mmdeploy9operation4cuda4impl9normalizeIfLi3EEEvPKT_iiiPf15HIP_vector_typeIfLj3EES9_b: ; @_ZN8mmdeploy9operation4cuda4impl9normalizeIfLi3EEEvPKT_iiiPf15HIP_vector_typeIfLj3EES9_b
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x4c
	s_load_b128 s[4:7], s[0:1], 0x8
	v_and_b32_e32 v2, 0x3ff, v0
	v_bfe_u32 v4, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s2, 16
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[0:1], null, s14, s2, v[2:3]
	v_mad_u64_u32 v[2:3], null, s15, s3, v[4:5]
	v_cmp_gt_i32_e32 vcc_lo, s5, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_gt_i32_e64 s2, s4, v2
	s_and_b32 s2, vcc_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB2_8
; %bb.1:
	s_clause 0x2
	s_load_b32 s7, s[0:1], 0x38
	s_load_b64 s[2:3], s[0:1], 0x0
	s_load_b64 s[4:5], s[0:1], 0x18
	v_lshl_add_u32 v3, v0, 1, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[0:1], null, v2, s6, v[3:4]
	s_waitcnt lgkmcnt(0)
	s_bitcmp1_b32 s7, 0
	s_cselect_b32 s6, -1, 0
	s_and_b32 vcc_lo, exec_lo, s6
	s_mov_b32 s6, -1
	s_cbranch_vccnz .LBB2_5
; %bb.2:                                ; %.preheader38.preheader
	s_delay_alu instid0(VALU_DEP_1)
	v_mov_b32_e32 v1, v0
	s_mov_b64 s[6:7], 0
.LBB2_3:                                ; %.preheader38
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1)
	v_ashrrev_i32_e32 v2, 31, v1
	s_add_u32 s8, s0, s6
	s_addc_u32 s9, s1, s7
	s_add_u32 s6, s6, 4
	s_addc_u32 s7, s7, 0
	v_lshlrev_b64 v[2:3], 2, v[1:2]
	s_cmp_lg_u32 s6, 12
	v_add_nc_u32_e32 v1, 1, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v4, vcc_lo, s2, v2
	v_add_co_ci_u32_e32 v5, vcc_lo, s3, v3, vcc_lo
	v_add_co_u32 v2, vcc_lo, s4, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
	global_load_b32 v4, v[4:5], off
	s_clause 0x1
	s_load_b32 s10, s[8:9], 0x20
	s_load_b32 s8, s[8:9], 0x2c
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_subrev_f32_e32 v4, s10, v4
	s_delay_alu instid0(VALU_DEP_1)
	v_mul_f32_e32 v4, s8, v4
	global_store_b32 v[2:3], v4, off
	s_cbranch_scc1 .LBB2_3
; %bb.4:                                ; %Flow
	s_mov_b32 s6, 0
.LBB2_5:                                ; %Flow82
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s6
	s_cbranch_vccz .LBB2_8
; %bb.6:                                ; %.preheader
	v_add_nc_u32_e32 v2, 2, v0
	s_mov_b64 s[6:7], 0
.LBB2_7:                                ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	s_add_u32 s8, s0, s6
	s_addc_u32 s9, s1, s7
	v_ashrrev_i32_e32 v1, 31, v0
	s_add_u32 s6, s6, 4
	v_lshlrev_b64 v[3:4], 2, v[2:3]
	s_addc_u32 s7, s7, 0
	s_cmp_eq_u32 s6, 12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, s2, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
	global_load_b32 v5, v[3:4], off
	s_clause 0x1
	s_load_b32 s10, s[8:9], 0x20
	s_load_b32 s8, s[8:9], 0x2c
	v_lshlrev_b64 v[3:4], 2, v[0:1]
	v_add_nc_u32_e32 v2, -1, v2
	v_add_nc_u32_e32 v0, 1, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v3, vcc_lo, s4, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_subrev_f32_e32 v1, s10, v5
	s_delay_alu instid0(VALU_DEP_1)
	v_mul_f32_e32 v1, s8, v1
	global_store_b32 v[3:4], v1, off
	s_cbranch_scc0 .LBB2_7
.LBB2_8:                                ; %.loopexit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _ZN8mmdeploy9operation4cuda4impl9normalizeIfLi3EEEvPKT_iiiPf15HIP_vector_typeIfLj3EES9_b
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 320
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 6
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._ZN8mmdeploy9operation4cuda4impl9normalizeIfLi3EEEvPKT_iiiPf15HIP_vector_typeIfLj3EES9_b,"axG",@progbits,_ZN8mmdeploy9operation4cuda4impl9normalizeIfLi3EEEvPKT_iiiPf15HIP_vector_typeIfLj3EES9_b,comdat
.Lfunc_end2:
	.size	_ZN8mmdeploy9operation4cuda4impl9normalizeIfLi3EEEvPKT_iiiPf15HIP_vector_typeIfLj3EES9_b, .Lfunc_end2-_ZN8mmdeploy9operation4cuda4impl9normalizeIfLi3EEEvPKT_iiiPf15HIP_vector_typeIfLj3EES9_b
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 492
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.section	.text._ZN8mmdeploy9operation4cuda4impl9normalizeIfLi1EEEvPKT_iiiPf15HIP_vector_typeIfLj3EES9_b,"axG",@progbits,_ZN8mmdeploy9operation4cuda4impl9normalizeIfLi1EEEvPKT_iiiPf15HIP_vector_typeIfLj3EES9_b,comdat
	.protected	_ZN8mmdeploy9operation4cuda4impl9normalizeIfLi1EEEvPKT_iiiPf15HIP_vector_typeIfLj3EES9_b ; -- Begin function _ZN8mmdeploy9operation4cuda4impl9normalizeIfLi1EEEvPKT_iiiPf15HIP_vector_typeIfLj3EES9_b
	.globl	_ZN8mmdeploy9operation4cuda4impl9normalizeIfLi1EEEvPKT_iiiPf15HIP_vector_typeIfLj3EES9_b
	.p2align	8
	.type	_ZN8mmdeploy9operation4cuda4impl9normalizeIfLi1EEEvPKT_iiiPf15HIP_vector_typeIfLj3EES9_b,@function
_ZN8mmdeploy9operation4cuda4impl9normalizeIfLi1EEEvPKT_iiiPf15HIP_vector_typeIfLj3EES9_b: ; @_ZN8mmdeploy9operation4cuda4impl9normalizeIfLi1EEEvPKT_iiiPf15HIP_vector_typeIfLj3EES9_b
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x4c
	s_load_b128 s[4:7], s[0:1], 0x8
	v_and_b32_e32 v2, 0x3ff, v0
	v_bfe_u32 v3, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s2, 16
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[0:1], null, s14, s2, v[2:3]
	v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_i32_e32 vcc_lo, s5, v0
	v_cmp_gt_i32_e64 s2, s4, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, vcc_lo, s2
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB3_2
; %bb.1:
	s_load_b64 s[2:3], s[0:1], 0x0
	v_mad_u64_u32 v[2:3], null, v1, s6, v[0:1]
	s_clause 0x2
	s_load_b64 s[4:5], s[0:1], 0x18
	s_load_b32 s6, s[0:1], 0x20
	s_load_b32 s0, s[0:1], 0x2c
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[0:1], 2, v[2:3]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s2, v0
	v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
	v_add_co_u32 v0, vcc_lo, s4, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
	global_load_b32 v2, v[2:3], off
	s_waitcnt vmcnt(0)
	v_subrev_f32_e32 v2, s6, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_mul_f32_e32 v2, s0, v2
	global_store_b32 v[0:1], v2, off
.LBB3_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _ZN8mmdeploy9operation4cuda4impl9normalizeIfLi1EEEvPKT_iiiPf15HIP_vector_typeIfLj3EES9_b
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 320
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 5
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._ZN8mmdeploy9operation4cuda4impl9normalizeIfLi1EEEvPKT_iiiPf15HIP_vector_typeIfLj3EES9_b,"axG",@progbits,_ZN8mmdeploy9operation4cuda4impl9normalizeIfLi1EEEvPKT_iiiPf15HIP_vector_typeIfLj3EES9_b,comdat
.Lfunc_end3:
	.size	_ZN8mmdeploy9operation4cuda4impl9normalizeIfLi1EEEvPKT_iiiPf15HIP_vector_typeIfLj3EES9_b, .Lfunc_end3-_ZN8mmdeploy9operation4cuda4impl9normalizeIfLi1EEEvPKT_iiiPf15HIP_vector_typeIfLj3EES9_b
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 240
; NumSgprs: 18
; NumVgprs: 5
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 5
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .offset:         12
        .size:           4
        .value_kind:     by_value
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .offset:         32
        .size:           12
        .value_kind:     by_value
      - .offset:         44
        .size:           12
        .value_kind:     by_value
      - .offset:         56
        .size:           1
        .value_kind:     by_value
      - .offset:         64
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         68
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         72
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         76
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         78
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         80
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         82
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         84
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         86
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         112
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         120
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         128
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 320
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _ZN8mmdeploy9operation4cuda4impl9normalizeIhLi3EEEvPKT_iiiPf15HIP_vector_typeIfLj3EES9_b
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _ZN8mmdeploy9operation4cuda4impl9normalizeIhLi3EEEvPKT_iiiPf15HIP_vector_typeIfLj3EES9_b.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     6
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .offset:         12
        .size:           4
        .value_kind:     by_value
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .offset:         32
        .size:           12
        .value_kind:     by_value
      - .offset:         44
        .size:           12
        .value_kind:     by_value
      - .offset:         56
        .size:           1
        .value_kind:     by_value
      - .offset:         64
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         68
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         72
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         76
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         78
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         80
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         82
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         84
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         86
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         112
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         120
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         128
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 320
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _ZN8mmdeploy9operation4cuda4impl9normalizeIhLi1EEEvPKT_iiiPf15HIP_vector_typeIfLj3EES9_b
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _ZN8mmdeploy9operation4cuda4impl9normalizeIhLi1EEEvPKT_iiiPf15HIP_vector_typeIfLj3EES9_b.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     5
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .offset:         12
        .size:           4
        .value_kind:     by_value
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         24
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        .value_kind:     global_buffer
      - .offset:         32
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      - .offset:         44
        .size:           12
        .value_kind:     by_value
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        .value_kind:     by_value
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        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         68
        .size:           4
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        .size:           4
        .value_kind:     hidden_block_count_z
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        .value_kind:     hidden_group_size_x
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        .value_kind:     hidden_group_size_y
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        .size:           2
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      - .offset:         84
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         86
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         112
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         120
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         128
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 320
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _ZN8mmdeploy9operation4cuda4impl9normalizeIfLi3EEEvPKT_iiiPf15HIP_vector_typeIfLj3EES9_b
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _ZN8mmdeploy9operation4cuda4impl9normalizeIfLi3EEEvPKT_iiiPf15HIP_vector_typeIfLj3EES9_b.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     6
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .offset:         12
        .size:           4
        .value_kind:     by_value
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .offset:         32
        .size:           12
        .value_kind:     by_value
      - .offset:         44
        .size:           12
        .value_kind:     by_value
      - .offset:         56
        .size:           1
        .value_kind:     by_value
      - .offset:         64
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         68
        .size:           4
        .value_kind:     hidden_block_count_y
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        .size:           4
        .value_kind:     hidden_block_count_z
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        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         78
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         80
        .size:           2
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      - .offset:         84
        .size:           2
        .value_kind:     hidden_remainder_y
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        .value_kind:     hidden_remainder_z
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        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         112
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         120
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         128
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 320
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _ZN8mmdeploy9operation4cuda4impl9normalizeIfLi1EEEvPKT_iiiPf15HIP_vector_typeIfLj3EES9_b
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _ZN8mmdeploy9operation4cuda4impl9normalizeIfLi1EEEvPKT_iiiPf15HIP_vector_typeIfLj3EES9_b.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     5
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
