//*****************************************************************************
//Projet HPC fusion et trie de tableaux sur GPU
//Auteur: ROBIN Clement et SAULNIER Solene
//Promo: MAIN5
//Date: decembre 2020
//Question 5 avec streams et utilisation de la shared
//*****************************************************************************

#include <stdio.h> 
#include <stdlib.h>
#define N 536870912 //taille max du tableau =d dans le projet
#define threadsPerBlock 1024
#define numBlocks 65535


//*****************************************************************************
//Fonctions CPU fusion et verification
//*****************************************************************************
int verif_trie(int *tab,int size)
{
    for (int i=0; i<size-1; i=i+1)
      if (tab[i]>tab[i+1])
          return i;
    return -1;
    
}

//*****************************************************************************
//Fonctions GPU (merge tableau) small
//*****************************************************************************
__device__ void mergeSmallBatch_k(int *A, int *B, int *M, int size_A, int size_B, int size_M, int slice_size)
{

    int i = threadIdx.x;
    if (i < size_A+size_B)
    {

     /*Merge*/
      int K[2],P[2],Q[2];
      int offset;

      if (i>size_A)
      {
          K[0]=i-size_A;
          K[1]=size_A;
          P[0]=size_A;
          P[1]=i-size_A;
      }
      else
      {
          K[0]=0;
          K[1]=i;
          P[0]=i;
          P[1]=0;
      }
      while (1)
      {
          offset=abs(K[1]-P[1])/2;
          Q[1]=K[1]-offset;
          Q[0]=K[0]+offset;
          if (Q[1] >= 0 && Q[0] <= size_B && (Q[1]== size_A || Q[0]==0 || A[Q[1]]>B[Q[0]-1]))
          {
              if (Q[0]==size_B || Q[1]==0 || A[Q[1]-1]<=B[Q[0]])
              {
                  if (Q[1]<size_A && (Q[0]==size_B || A[Q[1]]<=B[Q[0]]))
                      M[blockIdx.x * slice_size + i]=A[Q[1]];
                   
                  else
                      M[blockIdx.x * slice_size + i]=B[Q[0]]; 
                   
                  break;
              }
              else
              {
                  K[0]=Q[0]+1;
                  K[1]=Q[1]-1;
              }
          }
          else
          {
            P[0]=Q[0]-1;
            P[1]=Q[1]+1;
          }
      }
    }

}

__global__ void small_sortManager(int *M, int size_A, int size_B, int size_M, int number_of_slices)
{

      int slice_size = size_A + size_B;
        

      /*Chargement de A et B dans la shared memory*/
      /*Comme on a une seule shared memory*/
      __shared__ int shared_AB[1024];  //Comme A et B ne peuvent pas dépasser 1024
 
      int* s_A = (int*) &shared_AB[0];
      int* s_B = (int*) &s_A[size_A];
 
      __syncthreads();
 
      if (threadIdx.x < size_A)
        s_A[threadIdx.x] = M[blockIdx.x *slice_size+ threadIdx.x];

        

      if (threadIdx.x >= size_A && threadIdx.x < size_B + size_A  )
        s_B[threadIdx.x-size_A] = M[blockIdx.x *slice_size+ threadIdx.x]; 


      __syncthreads();
      /*if (size_A==1 && size_B==1)
      {
          //swap pour 2 elements
          if (threadIdx.x==0)
          {
              if (s_A[0]>s_B[0])
              {
                  M[blockIdx.x * 2]=s_B[0];
                  M[blockIdx.x * 2+1]=s_A[0];
              }
              else
              {
                  M[blockIdx.x * 2]=s_A[0];
                  M[blockIdx.x * 2+1]=s_B[0];
              }
          }
      }
      else*/ 
        mergeSmallBatch_k(s_A, s_B, M, size_A, size_B, size_M,slice_size);    
}

__global__ void small_sortManager_extraSlice(int *M ,int size_A,int size_B,int size_A_extra,int size_B_extra,int size_M,int number_of_slices)
{

        int slice_size = size_A + size_B;

      /*Chargement de A et B dans la shared memory*/
      /*Comme on a une seule shared memory*/
      __shared__ int shared_AB[1024];  //Comme A et B ne peuvent pas dépasser 1024
 
      int* s_A = (int*) &shared_AB[0];
     
      int* s_B;
     
      if (blockIdx.x == number_of_slices)
        s_B = (int*) &s_A[size_A_extra];

      else
        s_B = (int*) &s_A[size_A];
 
      __syncthreads();
 
      if (threadIdx.x < size_A)
        s_A[threadIdx.x] = M[blockIdx.x *slice_size+ threadIdx.x];

 
      if (threadIdx.x >= size_A && threadIdx.x < size_B + size_A)
        s_B[threadIdx.x-size_A] = M[blockIdx.x *slice_size+ threadIdx.x]; 

     
      if (blockIdx.x == number_of_slices && threadIdx.x < size_A_extra)
        s_A[threadIdx.x] = M[blockIdx.x *slice_size+ threadIdx.x];
     
      if (blockIdx.x == number_of_slices && threadIdx.x >= size_A_extra && threadIdx.x < size_B_extra + size_A_extra)
        s_B[threadIdx.x-size_A_extra] = M[blockIdx.x *slice_size+ threadIdx.x]; 
     

      __syncthreads();

     if (blockIdx.x == number_of_slices)
     {
         /*
         if (size_A_extra==1 && size_B_extra==1)
         {
          //swap pour 2 elements
          if (threadIdx.x==0)
          {
              if (s_A[0]>s_B[0])
              {
                  M[blockIdx.x * 2]=s_B[0];
                  M[blockIdx.x * 2+1]=s_A[0];
              }
              else
              {
                  M[blockIdx.x * 2]=s_A[0];
                  M[blockIdx.x * 2+1]=s_B[0];
              }
            }
          }
          else*/
          //{ 
              if (size_A_extra < size_B_extra)
                mergeSmallBatch_k(s_B, s_A, M, size_B_extra, size_A_extra, size_M, slice_size);  
      
              else
                mergeSmallBatch_k(s_A, s_B, M, size_A_extra, size_B_extra, size_M, slice_size); 
          //}
     }

    else
    {
      /*if (size_A==1 && size_B==1)
      {
          //swap pour 2 elements
          if (threadIdx.x==0)
          {
              if (s_A[0]>s_B[0])
              {
                  M[blockIdx.x * 2]=s_B[0];
                  M[blockIdx.x * 2+1]=s_A[0];
              }
              else
              {
                  M[blockIdx.x * 2]=s_A[0];
                  M[blockIdx.x * 2+1]=s_B[0];
              }
          }
      }
      else */
         mergeSmallBatch_k(s_A, s_B, M, size_A, size_B, size_M,slice_size); 
    }
      
    
 
}

//*****************************************************************************
//Fonctions GPU (merge tableau) big
//*****************************************************************************

__device__ void pathBig_k(int *A, int *B, int *Path, int size_A, int size_B, int size_M)
{
    for(int i = blockIdx.x * blockDim.x + threadIdx.x; i<size_M; i = i+blockDim.x*gridDim.x)
    {
      int K[2],P[2],Q[2];
      int offset;

      if (i>size_A)
      {
          K[0]=i-size_A;
          K[1]=size_A;
          P[0]=size_A;
          P[1]=i-size_A;
      }
      else
      {
          K[0]=0;
          K[1]=i;
          P[0]=i;
          P[1]=0;
      }
      while (1)
      {
          offset=abs(K[1]-P[1])/2;
          Q[1]=K[1]-offset;
          Q[0]=K[0]+offset;
          if (Q[1] >= 0 && Q[0] <= size_B && (Q[1]== size_A || Q[0]==0 || A[Q[1]]>B[Q[0]-1]))
          {
              if (Q[0]==size_B || Q[1]==0 || A[Q[1]-1]<=B[Q[0]])
              {
                  if (Q[1]<size_A && (Q[0]==size_B || A[Q[1]]<=B[Q[0]]))
                  {
                      Path[i]=1;
                      Path[i+size_M]=Q[1];
                  }
                  else
                  {
                      Path[i]=0;
                      Path[i+size_M]=Q[0];
                  }
                  break;
              }
              else
              {
                  K[0]=Q[0]+1;
                  K[1]=Q[1]-1;
              }
          }
          else
          {
            P[0]=Q[0]-1;
            P[1]=Q[1]+1;
          }
      }
    }
}


__device__ void mergeBig_k(int *A, int *B, int *M,int *Path, int size_A, int size_B, int size_M)
{
    for(int i = blockIdx.x * blockDim.x + threadIdx.x; i<size_M; i = i+blockDim.x*gridDim.x)
    {
        if (Path[i]==1)
          M[i]=A[Path[i+size_M]];
        else if (Path[i]==0)
          M[i]=B[Path[i+size_M]];
        else
          printf("ERROR thread num %d block %d",i,blockIdx.x);
                  
    }
}

__global__ void sortManager_GPU(int *A, int *B, int *M,int *Path, int size_A, int size_B, int size_M)
{
    pathBig_k(A, B, Path, size_A, size_B, size_M);
    mergeBig_k(A, B, M, Path, size_A, size_B, size_M);
}
//****************************************************************************************************
// Fonctions CPU
//****************************************************************************************************
void sortManager_CPU(int *h_M,int h_size_A,int h_size_B,int h_slice_size,int i,cudaStream_t stream[])
{
    
    /*Variables CPU*/ 
    int h_size_M_tmp= h_size_A+h_size_B;
    int *h_A;
    int *h_B;
    int *h_M_tmp;
    h_A=(int *)malloc(h_size_A*sizeof(int));
    h_B=(int *)malloc(h_size_B*sizeof(int));
    h_M_tmp=(int *)malloc(h_size_M_tmp*sizeof(int));

    /*Remplir A et B*/
    for (int j=0; j<h_size_A; j++)
      h_A[j] = h_M[i*h_slice_size+j];

    for (int j=0; j<h_size_B; j++)
      h_B[j] = h_M[i*h_slice_size+j+h_size_A];
 
    /*Variables GPU*/
    int *d_A;
    int *d_B;
    int *d_M_tmp;
    int *d_Path_tmp;
    cudaMalloc(&d_A,h_size_A*sizeof(int));
    cudaMalloc(&d_B,h_size_B*sizeof(int));
    cudaMalloc(&d_M_tmp,h_size_M_tmp*sizeof(int));
    cudaMalloc(&d_Path_tmp,h_size_M_tmp*sizeof(int));

  
    /*Transfert*/
    cudaMemcpyAsync(d_A, h_A, h_size_A*sizeof(int), cudaMemcpyHostToDevice, stream[i]);
    cudaMemcpyAsync(d_B, h_B, h_size_B*sizeof(int), cudaMemcpyHostToDevice, stream[i]);
 
    /*Sort*/
    if (h_size_A<h_size_B)
      sortManager_GPU<<<numBlocks,threadsPerBlock,0, stream[i]>>>(d_B, d_A, d_M_tmp, d_Path_tmp, h_size_B, h_size_A, h_size_M_tmp);
    else
      sortManager_GPU<<<numBlocks,threadsPerBlock,0, stream[i]>>>(d_A, d_B, d_M_tmp, d_Path_tmp, h_size_A, h_size_B, h_size_M_tmp);   
    
    /*Transfert memoire GPU*/
    cudaMemcpyAsync(h_M_tmp, d_M_tmp, h_size_M_tmp*sizeof(int), cudaMemcpyDeviceToHost, stream[i]);

    
    /*Copie de h_M_tmp dans h_M*/
    for (int j=0; j<h_size_M_tmp; j++)
      h_M[i*h_slice_size+j]=h_M_tmp[j];
 
    
    /*Liberation*/
    free(h_A);
    free(h_B);
    free(h_M_tmp);
    cudaFree(d_A);
    cudaFree(d_B);
    cudaFree(d_M_tmp);
    cudaFree(d_Path_tmp);
}


//*****************************************************************************
//MAIN
//*****************************************************************************
int main(int argc, char const *argv[])
{
  //srand (time (NULL));
  srand (42);


  /*Déclaration des variables CPU*/
  /*Taille des tableaux*/
  int h_taille_M=N;

  /*Traitement des options*/
  for (int i=0; i<argc-1; i=i+1)
  {
      if (strcmp(argv[i],"--s")==0 && atoi(argv[i+1])<N )
          h_taille_M=atoi(argv[i+1]);   
  }

  /*Tableaux et allocation memoire*/
  int *h_M;
  h_M=(int *)malloc(h_taille_M*sizeof(int));
 
  /*Déclaration des variables GPU*/  
  int *d_M;
  cudaMalloc(&d_M,h_taille_M*sizeof(int));

  /*Initialisation et preparation des tableaux*/
  for (int i=0; i<h_taille_M;i++)
    h_M[i]=rand()%10000;

  /*Merge tableau*/
  /*variables generales*/
  int h_slice_size=1;
  int h_number_of_slices=1024/2;
  int h_slice_reste_precedent=0;
  int h_slice_reste=0;
  
  /*Cas tailles de moins de 1024*/
  /*variables pour moins de 1024*/
  int h_is_irregular_batch=0;
  int h_irregular_batch_size=0;
  int h_irregular_slice_size=1;
  int h_irregular_number_of_slices=h_irregular_batch_size/2;
  int h_irregular_slice_reste_precedent=0;
  int h_irregular_slice_reste=0;


  /*Decoupage de M en batches de 1024*/
  int h_number_of_batches=h_taille_M/1024;
  if (h_taille_M%1024!=0)
  {
      h_irregular_batch_size=h_taille_M%1024;
      h_is_irregular_batch=1;
      h_irregular_number_of_slices=h_irregular_batch_size/2;   
  }
      

  /*Allocation et initialisation des batches*/
  /*Batches CPU*/
  int **h_batch_M;
  int *h_irregular_batch_M;
  h_batch_M = (int **) malloc( h_number_of_batches* sizeof(int *) );


  for (int b=0; b<h_number_of_batches; b++)
  {
    h_batch_M[b]=(int *) malloc (1024 * sizeof(int ));
    for (int ind=0; ind<1024; ind++)
        h_batch_M[b][ind]=h_M[b*1024+ind]; 
  }
  h_irregular_batch_M = (int *) malloc( h_irregular_batch_size* sizeof(int ) );
  for (int ind=0; ind<h_irregular_batch_size; ind++)
        h_irregular_batch_M[ind]=h_M[h_number_of_batches*1024+ind]; 
  
  /*Batches GPU*/
  int *d_batch_M;
  int *d_irregular_batch_M;
  cudaMalloc(&d_batch_M,1024*sizeof(int));
  cudaMalloc(&d_irregular_batch_M,h_irregular_batch_size*sizeof(int));
  

  /*Declaration et creation des streams*/
  cudaStream_t stream[h_number_of_batches+h_is_irregular_batch];
  for (int ind_stream=0; ind_stream<h_number_of_batches; ind_stream++)
      cudaStreamCreate(&stream[ind_stream]);
  if (h_is_irregular_batch==1)
      cudaStreamCreate(&stream[h_number_of_batches]);


  /*Timer*/
  cudaEvent_t start, stop;
  cudaEventCreate(&start);
  cudaEventCreate(&stop);

  /*Slices inferieures a 1024*/
  cudaEventRecord(start);
  while (h_number_of_slices > 0)
  {   
      /*Mise a jour taille et indices*/
      h_slice_size=2*h_slice_size;
      h_slice_reste_precedent=h_slice_reste;
      h_slice_reste=1024%h_slice_size;
      h_number_of_slices=1024/h_slice_size;
      
      for (int b=0; b<h_number_of_batches;b++)
      {   
          cudaMemcpyAsync(d_batch_M, h_batch_M[b], 1024*sizeof(int), cudaMemcpyHostToDevice, stream[b]);
          
          if (h_slice_reste_precedent!=0 && h_slice_reste!=0)
          {
              int h_taille_A_extra=h_slice_reste-h_slice_reste_precedent;
              int h_taille_B_extra=h_slice_reste_precedent;
              small_sortManager_extraSlice<<<h_number_of_slices+1,1024,0,stream[b]>>>(d_batch_M,h_slice_size/2,h_slice_size/2,h_taille_A_extra,h_taille_B_extra,1024,h_number_of_slices);
          }
          else
            small_sortManager<<<h_number_of_slices,1024,0,stream[b]>>>(d_batch_M, h_slice_size/2, h_slice_size/2,h_slice_size,h_number_of_slices);

          cudaMemcpyAsync(h_batch_M[b], d_batch_M, 1024*sizeof(int), cudaMemcpyDeviceToHost, stream[b]);
      }
      if (h_is_irregular_batch==1 && h_irregular_number_of_slices>0)
      {
          
           h_irregular_slice_size=2*h_irregular_slice_size;
           h_irregular_slice_reste_precedent=h_irregular_slice_reste;
           h_irregular_slice_reste=h_irregular_batch_size%h_irregular_slice_size;
           h_irregular_number_of_slices=h_irregular_batch_size/h_irregular_slice_size;

           cudaMemcpyAsync(d_irregular_batch_M, h_irregular_batch_M, h_irregular_batch_size*sizeof(int), cudaMemcpyHostToDevice, stream[h_number_of_batches]);

           if (h_irregular_slice_reste_precedent!=0 && h_irregular_slice_reste!=0)
           {
              
              int h_taille_A_extra=h_irregular_slice_reste-h_irregular_slice_reste_precedent;
              int h_taille_B_extra=h_irregular_slice_reste_precedent;
              small_sortManager_extraSlice<<<h_irregular_number_of_slices+1,h_irregular_batch_size,0,stream[h_number_of_batches]>>>(d_irregular_batch_M,h_irregular_slice_size/2,h_irregular_slice_size/2,h_taille_A_extra,h_taille_B_extra,h_irregular_batch_size,h_irregular_number_of_slices);

           }
           else
            small_sortManager<<<h_irregular_number_of_slices,h_irregular_batch_size,0,stream[h_number_of_batches]>>>(d_irregular_batch_M, h_irregular_slice_size/2, h_irregular_slice_size/2,h_irregular_slice_size,h_irregular_number_of_slices);
          
          cudaMemcpyAsync(h_irregular_batch_M, d_irregular_batch_M, h_irregular_batch_size*sizeof(int), cudaMemcpyDeviceToHost, stream[h_number_of_batches]);
          
      
      }
      

  }
  cudaDeviceSynchronize();

  /*re ecriture de M*/
  for (int b=0; b<h_number_of_batches; b++)
      for (int ind=0; ind<1024; ind++)
          h_M[b*1024+ind]=h_batch_M[b][ind];
  if (h_is_irregular_batch==1)
      for (int ind=0; ind<h_irregular_batch_size; ind++)
          h_M[h_number_of_batches*1024+ind]=h_irregular_batch_M[ind];
  
  
  /*Slices superieures a 1024*/

  /*Mise a jour taille et indices*/
  h_slice_size=1024;


  /*Destruction des streams qui ne servent pas*/
  for (int i=(h_taille_M/h_slice_size); i<h_number_of_batches+h_is_irregular_batch; i++)
      cudaStreamDestroy(stream[i]);
       

  /*Mise a jour taille et indices suite*/    
  h_number_of_slices=h_taille_M/h_slice_size;
  h_slice_reste=h_irregular_batch_size;
  int compteur=0;
  while (h_number_of_slices>0)
  {   
      compteur=compteur+1;
      /*Mise a jour taille et indices*/
      h_slice_size=2*h_slice_size;
   
      /*Destruction des streams qui ne servent pas*/
      if (compteur>1)
        for (int i=(h_taille_M/h_slice_size)+1; i<h_number_of_slices+1; i++)
          cudaStreamDestroy(stream[i]);
   
      /*Mise a jour taille et indices suite*/
      h_slice_reste_precedent=h_slice_reste;
      h_slice_reste=h_taille_M%h_slice_size;
      h_number_of_slices=h_taille_M/h_slice_size;
      
      
      for (int i=0; i<h_number_of_slices; i++)
      {   
          sortManager_CPU(h_M,h_slice_size/2,h_slice_size/2,h_slice_size,i, stream);
          
      }
      if (h_slice_reste_precedent!=0 && h_slice_reste!=0)
      {
          int h_taille_A=h_slice_reste-h_slice_reste_precedent;
          int h_taille_B=h_slice_reste_precedent;
          sortManager_CPU(h_M,h_taille_A,h_taille_B,h_slice_size,h_number_of_slices,stream);

      }
      cudaDeviceSynchronize();
       
  }
  
  cudaDeviceSynchronize();
  cudaEventRecord(stop);

  /*Affichage du chrono*/
  cudaEventSynchronize(stop);
  float ms = 0;
  cudaEventElapsedTime(&ms, start, stop);
  fprintf(stderr,"mergeBatches Taille_M: %d, nbthreads: %d, numblocks: %d, Temps: %.5f, verif: %d\n", h_taille_M, threadsPerBlock, numBlocks, ms,verif_trie(h_M,h_taille_M));
  
  /*Destructions des streams restants*/
  for (int i=0; i<h_number_of_slices; i++)
    cudaStreamDestroy(stream[i]);

  /*Verification*/
  if (verif_trie(h_M,h_taille_M)==-1)
    printf("ok tableau trie");
  else
    printf("KO recommencer %d ",verif_trie(h_M,h_taille_M) );

  /*Liberation*/
  cudaFree(d_M);
  cudaFree(d_batch_M);
  cudaFree(d_irregular_batch_M);

  for (int b=0;b<h_number_of_batches;b++)
      free(h_batch_M[b]);
    
  free(h_M);
  free(h_batch_M);
  free(h_irregular_batch_M);


    return 0;
}
	.file	"tmpxft_002bd615_00000000-6_mergeBatches.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2035:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2035:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z10verif_triePii
	.type	_Z10verif_triePii, @function
_Z10verif_triePii:
.LFB2027:
	.cfi_startproc
	endbr64
	xorl	%eax, %eax
	decl	%esi
.L3:
	cmpl	%eax, %esi
	jle	.L8
	movl	4(%rdi,%rax,4), %ecx
	leaq	1(%rax), %rdx
	cmpl	%ecx, (%rdi,%rax,4)
	jg	.L2
	movq	%rdx, %rax
	jmp	.L3
.L8:
	orl	$-1, %eax
.L2:
	ret
	.cfi_endproc
.LFE2027:
	.size	_Z10verif_triePii, .-_Z10verif_triePii
	.globl	_Z17mergeSmallBatch_kPiS_S_iiii
	.type	_Z17mergeSmallBatch_kPiS_S_iiii, @function
_Z17mergeSmallBatch_kPiS_S_iiii:
.LFB2028:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2028:
	.size	_Z17mergeSmallBatch_kPiS_S_iiii, .-_Z17mergeSmallBatch_kPiS_S_iiii
	.globl	_Z9pathBig_kPiS_S_iii
	.type	_Z9pathBig_kPiS_S_iii, @function
_Z9pathBig_kPiS_S_iii:
.LFB2029:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2029:
	.size	_Z9pathBig_kPiS_S_iii, .-_Z9pathBig_kPiS_S_iii
	.globl	_Z10mergeBig_kPiS_S_S_iii
	.type	_Z10mergeBig_kPiS_S_S_iii, @function
_Z10mergeBig_kPiS_S_S_iii:
.LFB2030:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2030:
	.size	_Z10mergeBig_kPiS_S_S_iii, .-_Z10mergeBig_kPiS_S_S_iii
	.globl	_Z41__device_stub__Z17small_sortManagerPiiiiiPiiiii
	.type	_Z41__device_stub__Z17small_sortManagerPiiiiiPiiiii, @function
_Z41__device_stub__Z17small_sortManagerPiiiiiPiiiii:
.LFB2057:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rdi
	movl	%esi, 20(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 16(%rsp)
	leaq	32(%rsp), %rdx
	movl	%ecx, 12(%rsp)
	leaq	40(%rsp), %rcx
	movl	%r8d, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L15
	pushq	40(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z17small_sortManagerPiiiii(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 176
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L15:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L17
	call	__stack_chk_fail@PLT
.L17:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2057:
	.size	_Z41__device_stub__Z17small_sortManagerPiiiiiPiiiii, .-_Z41__device_stub__Z17small_sortManagerPiiiiiPiiiii
	.globl	_Z17small_sortManagerPiiiii
	.type	_Z17small_sortManagerPiiiii, @function
_Z17small_sortManagerPiiiii:
.LFB2058:
	.cfi_startproc
	endbr64
	jmp	_Z41__device_stub__Z17small_sortManagerPiiiiiPiiiii
	.cfi_endproc
.LFE2058:
	.size	_Z17small_sortManagerPiiiii, .-_Z17small_sortManagerPiiiii
	.globl	_Z54__device_stub__Z28small_sortManager_extraSlicePiiiiiiiPiiiiiii
	.type	_Z54__device_stub__Z28small_sortManager_extraSlicePiiiiiiiPiiiiiii, @function
_Z54__device_stub__Z28small_sortManager_extraSlicePiiiiiiiPiiiiiii:
.LFB2059:
	.cfi_startproc
	endbr64
	subq	$168, %rsp
	.cfi_def_cfa_offset 176
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rdi
	movl	%esi, 20(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 16(%rsp)
	leaq	32(%rsp), %rdx
	movl	%ecx, 12(%rsp)
	leaq	40(%rsp), %rcx
	movl	%r8d, 8(%rsp)
	movl	%r9d, 4(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 152(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	176(%rsp), %rax
	movq	%rax, 144(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L20
	pushq	40(%rsp)
	.cfi_def_cfa_offset 184
	leaq	_Z28small_sortManager_extraSlicePiiiiiii(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 192
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 184
	popq	%rdx
	.cfi_def_cfa_offset 176
.L20:
	movq	152(%rsp), %rax
	subq	%fs:40, %rax
	je	.L22
	call	__stack_chk_fail@PLT
.L22:
	addq	$168, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2059:
	.size	_Z54__device_stub__Z28small_sortManager_extraSlicePiiiiiiiPiiiiiii, .-_Z54__device_stub__Z28small_sortManager_extraSlicePiiiiiiiPiiiiiii
	.globl	_Z28small_sortManager_extraSlicePiiiiiii
	.type	_Z28small_sortManager_extraSlicePiiiiiii, @function
_Z28small_sortManager_extraSlicePiiiiiii:
.LFB2060:
	.cfi_startproc
	endbr64
	jmp	_Z54__device_stub__Z28small_sortManager_extraSlicePiiiiiiiPiiiiiii
	.cfi_endproc
.LFE2060:
	.size	_Z28small_sortManager_extraSlicePiiiiiii, .-_Z28small_sortManager_extraSlicePiiiiiii
	.globl	_Z44__device_stub__Z15sortManager_GPUPiS_S_S_iiiPiS_S_S_iii
	.type	_Z44__device_stub__Z15sortManager_GPUPiS_S_S_iiiPiS_S_S_iii, @function
_Z44__device_stub__Z15sortManager_GPUPiS_S_S_iiiPiS_S_S_iii:
.LFB2061:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	48(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	56(%rsp), %rcx
	movl	%r8d, 12(%rsp)
	movl	%r9d, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 112(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	192(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L25
	pushq	56(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z15sortManager_GPUPiS_S_S_iii(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 208
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L25:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L27
	call	__stack_chk_fail@PLT
.L27:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2061:
	.size	_Z44__device_stub__Z15sortManager_GPUPiS_S_S_iiiPiS_S_S_iii, .-_Z44__device_stub__Z15sortManager_GPUPiS_S_S_iiiPiS_S_S_iii
	.globl	_Z15sortManager_GPUPiS_S_S_iii
	.type	_Z15sortManager_GPUPiS_S_S_iii, @function
_Z15sortManager_GPUPiS_S_S_iii:
.LFB2062:
	.cfi_startproc
	endbr64
	jmp	_Z44__device_stub__Z15sortManager_GPUPiS_S_S_iiiPiS_S_S_iii
	.cfi_endproc
.LFE2062:
	.size	_Z15sortManager_GPUPiS_S_S_iii, .-_Z15sortManager_GPUPiS_S_S_iii
	.globl	_Z15sortManager_CPUPiiiiiPP11CUstream_st
	.type	_Z15sortManager_CPUPiiiiiPP11CUstream_st, @function
_Z15sortManager_CPUPiiiiiPP11CUstream_st:
.LFB2031:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movl	%ecx, %r15d
	movslq	%esi, %rcx
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	leal	(%rsi,%rdx), %r14d
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movslq	%r8d, %r12
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movl	%edx, %ebp
	imull	%r12d, %r15d
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movl	%esi, %ebx
	subq	$136, %rsp
	.cfi_def_cfa_offset 192
	movq	%r9, 40(%rsp)
	movq	%rdi, 56(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	0(,%rcx,4), %rax
	movq	%rcx, 48(%rsp)
	movq	%rax, %rdi
	movq	%rax, 8(%rsp)
	call	malloc@PLT
	movq	%rax, 24(%rsp)
	movslq	%ebp, %rax
	salq	$2, %rax
	movq	%rax, %rdi
	movq	%rax, 16(%rsp)
	call	malloc@PLT
	movq	%rax, 32(%rsp)
	movslq	%r14d, %rax
	salq	$2, %rax
	movq	%rax, %rdi
	movq	%rax, (%rsp)
	call	malloc@PLT
	movq	56(%rsp), %r10
	movq	48(%rsp), %rcx
	xorl	%edx, %edx
	movq	%rax, %r13
	movslq	%r15d, %rax
	leaq	(%r10,%rax,4), %r15
.L31:
	cmpl	%edx, %ebx
	jle	.L44
	movl	(%r15,%rdx,4), %esi
	movq	24(%rsp), %rdi
	movl	%esi, (%rdi,%rdx,4)
	incq	%rdx
	jmp	.L31
.L44:
	addq	%rax, %rcx
	xorl	%eax, %eax
	leaq	(%r10,%rcx,4), %rdx
.L33:
	cmpl	%eax, %ebp
	jle	.L45
	movl	(%rdx,%rax,4), %ecx
	movq	32(%rsp), %rsi
	movl	%ecx, (%rsi,%rax,4)
	incq	%rax
	jmp	.L33
.L45:
	movq	8(%rsp), %rsi
	leaq	64(%rsp), %rdi
	call	cudaMalloc@PLT
	movq	16(%rsp), %rsi
	leaq	72(%rsp), %rdi
	call	cudaMalloc@PLT
	movq	(%rsp), %rsi
	leaq	80(%rsp), %rdi
	call	cudaMalloc@PLT
	movq	(%rsp), %rsi
	leaq	88(%rsp), %rdi
	call	cudaMalloc@PLT
	movq	40(%rsp), %rax
	movq	8(%rsp), %rdx
	movl	$1, %ecx
	movq	24(%rsp), %rsi
	movq	64(%rsp), %rdi
	leaq	(%rax,%r12,8), %r12
	movq	(%r12), %r8
	call	cudaMemcpyAsync@PLT
	movq	(%r12), %r8
	movq	16(%rsp), %rdx
	movl	$1, %ecx
	movq	32(%rsp), %rsi
	movq	72(%rsp), %rdi
	call	cudaMemcpyAsync@PLT
	movl	$4194305, %edx
	movq	(%r12), %r9
	movabsq	$4295032831, %rdi
	salq	$10, %rdx
	cmpl	%ebp, %ebx
	movl	$1, 116(%rsp)
	movl	$0, %r8d
	movq	%rdx, 108(%rsp)
	movl	$1, %ecx
	movl	$1, %esi
	movq	%rdi, 96(%rsp)
	movl	$1, 104(%rsp)
	jge	.L35
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L37
	movl	%ebx, %r9d
	pushq	%rsi
	.cfi_remember_state
	.cfi_def_cfa_offset 200
	movl	%ebp, %r8d
	pushq	%r14
	.cfi_def_cfa_offset 208
	movq	104(%rsp), %rcx
	movq	96(%rsp), %rdx
	movq	80(%rsp), %rsi
	movq	88(%rsp), %rdi
	jmp	.L43
.L35:
	.cfi_restore_state
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L37
	pushq	%rcx
	.cfi_def_cfa_offset 200
	movl	%ebp, %r9d
	movl	%ebx, %r8d
	pushq	%r14
	.cfi_def_cfa_offset 208
	movq	104(%rsp), %rcx
	movq	96(%rsp), %rdx
	movq	88(%rsp), %rsi
	movq	80(%rsp), %rdi
.L43:
	call	_Z44__device_stub__Z15sortManager_GPUPiS_S_S_iiiPiS_S_S_iii
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L37:
	movq	(%r12), %r8
	movq	(%rsp), %rdx
	movl	$2, %ecx
	movq	%r13, %rdi
	movq	80(%rsp), %rsi
	call	cudaMemcpyAsync@PLT
	xorl	%eax, %eax
.L39:
	cmpl	%eax, %r14d
	jle	.L46
	movl	0(%r13,%rax,4), %edx
	movl	%edx, (%r15,%rax,4)
	incq	%rax
	jmp	.L39
.L46:
	movq	24(%rsp), %rdi
	call	free@PLT
	movq	32(%rsp), %rdi
	call	free@PLT
	movq	%r13, %rdi
	call	free@PLT
	movq	64(%rsp), %rdi
	call	cudaFree@PLT
	movq	72(%rsp), %rdi
	call	cudaFree@PLT
	movq	80(%rsp), %rdi
	call	cudaFree@PLT
	movq	88(%rsp), %rdi
	call	cudaFree@PLT
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L41
	call	__stack_chk_fail@PLT
.L41:
	addq	$136, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2031:
	.size	_Z15sortManager_CPUPiiiiiPP11CUstream_st, .-_Z15sortManager_CPUPiiiiiPP11CUstream_st
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"--s"
.LC2:
	.string	"mergeBatches Taille_M: %d, nbthreads: %d, numblocks: %d, Temps: %.5f, verif: %d\n"
.LC3:
	.string	"ok tableau trie"
.LC4:
	.string	"KO recommencer %d "
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2032:
	.cfi_startproc
	endbr64
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register 6
	pushq	%r15
	pushq	%r14
	.cfi_offset 15, -24
	.cfi_offset 14, -32
	leaq	.LC0(%rip), %r14
	pushq	%r13
	.cfi_offset 13, -40
	movq	%rsi, %r13
	pushq	%r12
	.cfi_offset 12, -48
	movl	%edi, %r12d
	movl	$42, %edi
	pushq	%rbx
	decl	%r12d
	.cfi_offset 3, -56
	xorl	%ebx, %ebx
	subq	$216, %rsp
	movq	%fs:40, %rax
	movq	%rax, -56(%rbp)
	xorl	%eax, %eax
	call	srand@PLT
	movl	$536870912, -136(%rbp)
.L48:
	cmpl	%ebx, %r12d
	jle	.L129
	movq	0(%r13,%rbx,8), %rdi
	movq	%r14, %rsi
	call	strcmp@PLT
	testl	%eax, %eax
	jne	.L49
	movq	8(%r13,%rbx,8), %rdi
	call	atoi@PLT
	cmpl	$536870911, %eax
	cmovg	-136(%rbp), %eax
	movl	%eax, -136(%rbp)
.L49:
	incq	%rbx
	jmp	.L48
.L129:
	movslq	-136(%rbp), %rbx
	movl	$10000, %r12d
	salq	$2, %rbx
	movq	%rbx, %rdi
	call	malloc@PLT
	movq	%rbx, %rsi
	leaq	-120(%rbp), %rdi
	xorl	%ebx, %ebx
	movq	%rax, -152(%rbp)
	call	cudaMalloc@PLT
.L51:
	cmpl	%ebx, -136(%rbp)
	jle	.L130
	call	rand@PLT
	cltd
	idivl	%r12d
	movq	-152(%rbp), %rax
	movl	%edx, (%rax,%rbx,4)
	incq	%rbx
	jmp	.L51
.L130:
	movl	-136(%rbp), %eax
	movl	$1024, %ecx
	cltd
	idivl	%ecx
	movl	%eax, -140(%rbp)
	movl	-136(%rbp), %eax
	andl	$1023, %eax
	movl	%eax, -156(%rbp)
	je	.L98
	movl	%edx, %eax
	movl	%edx, -132(%rbp)
	movl	$2, %ecx
	movl	$1, -160(%rbp)
	cltd
	idivl	%ecx
	movl	%eax, -156(%rbp)
	jmp	.L53
.L98:
	xorl	%edi, %edi
	movl	%edi, -132(%rbp)
	movl	%edi, -160(%rbp)
.L53:
	movslq	-140(%rbp), %r15
	xorl	%r12d, %r12d
	leaq	0(,%r15,8), %rbx
	movq	%rbx, %rdi
	call	malloc@PLT
	movq	%rax, -168(%rbp)
	movq	-152(%rbp), %rax
	movq	%rax, -232(%rbp)
	movq	%rax, %r13
.L54:
	cmpl	%r12d, -140(%rbp)
	jle	.L131
	movl	$4096, %edi
	call	malloc@PLT
	movq	-168(%rbp), %rsi
	movl	$1024, %ecx
	movq	%rax, %rdi
	movq	%rax, (%rsi,%r12,8)
	movq	%r13, %rsi
	incq	%r12
	addq	$4096, %r13
	rep movsl
	jmp	.L54
.L131:
	movslq	-132(%rbp), %rax
	salq	$2, %rax
	movq	%rax, %rdi
	movq	%rax, -192(%rbp)
	call	malloc@PLT
	movq	-152(%rbp), %rcx
	movq	%rax, -176(%rbp)
	movl	-140(%rbp), %eax
	sall	$10, %eax
	cltq
	leaq	(%rcx,%rax,4), %rax
	movq	%rax, -216(%rbp)
	xorl	%eax, %eax
.L56:
	cmpl	%eax, -132(%rbp)
	jle	.L132
	movq	-216(%rbp), %rdx
	movq	-176(%rbp), %rsi
	movl	(%rdx,%rax,4), %edx
	movl	%edx, (%rsi,%rax,4)
	incq	%rax
	jmp	.L56
.L132:
	leaq	-112(%rbp), %rdi
	movl	$4096, %esi
	call	cudaMalloc@PLT
	movq	-192(%rbp), %rsi
	leaq	-104(%rbp), %rdi
	call	cudaMalloc@PLT
	movl	-140(%rbp), %edx
	movl	-160(%rbp), %eax
	movq	%rsp, %rcx
	addl	%edx, %eax
	movl	%eax, -236(%rbp)
	cltq
	leaq	15(,%rax,8), %rdx
	movq	%rdx, %rax
	andq	$-4096, %rdx
	andq	$-16, %rax
	subq	%rdx, %rcx
.L58:
	cmpq	%rcx, %rsp
	je	.L59
	subq	$4096, %rsp
	orq	$0, 4088(%rsp)
	jmp	.L58
.L59:
	andl	$4095, %eax
	subq	%rax, %rsp
	testq	%rax, %rax
	je	.L60
	orq	$0, -8(%rsp,%rax)
.L60:
	movq	%rsp, %r14
	xorl	%r12d, %r12d
	movq	%r14, %r13
.L61:
	movl	-140(%rbp), %eax
	cmpl	%eax, %r12d
	jge	.L133
	movq	%r13, %rdi
	incl	%r12d
	addq	$8, %r13
	call	cudaStreamCreate@PLT
	jmp	.L61
.L133:
	cmpl	$1, -160(%rbp)
	jne	.L63
	leaq	(%r14,%rbx), %rdi
	call	cudaStreamCreate@PLT
.L63:
	leaq	-96(%rbp), %rdi
	call	cudaEventCreate@PLT
	leaq	-88(%rbp), %rdi
	call	cudaEventCreate@PLT
	movq	-96(%rbp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	xorl	%ecx, %ecx
	xorl	%esi, %esi
	movslq	-140(%rbp), %r12
	movl	$11, -244(%rbp)
	movl	%ecx, -180(%rbp)
	movl	$1, -144(%rbp)
	movl	%esi, -240(%rbp)
	movl	$1, -196(%rbp)
.L75:
	movl	-196(%rbp), %eax
	sall	-196(%rbp)
	xorl	%ebx, %ebx
	movabsq	$4294968320, %r13
	movl	%eax, -184(%rbp)
	movl	-240(%rbp), %eax
	movl	%eax, -204(%rbp)
	movl	$1024, %eax
	cltd
	idivl	-196(%rbp)
	movl	%edx, -208(%rbp)
	movl	%eax, -200(%rbp)
	movl	%edx, -240(%rbp)
.L64:
	cmpl	%ebx, -140(%rbp)
	jle	.L134
	movq	-168(%rbp), %rax
	movq	(%r14,%rbx,8), %r8
	movl	$1, %ecx
	movl	$4096, %edx
	movq	-112(%rbp), %rdi
	movq	(%rax,%rbx,8), %rax
	movq	%rax, %rsi
	movq	%rax, -224(%rbp)
	call	cudaMemcpyAsync@PLT
	cmpl	$0, -204(%rbp)
	movq	(%r14,%rbx,8), %r9
	je	.L65
	cmpl	$0, -208(%rbp)
	je	.L65
	movl	-200(%rbp), %eax
	xorl	%r8d, %r8d
	movq	%r13, %rdx
	movq	%r13, -68(%rbp)
	movl	$1, %ecx
	movl	$1, -60(%rbp)
	incl	%eax
	movl	%eax, -80(%rbp)
	movabsq	$4294967297, %rax
	movq	%rax, -76(%rbp)
	movq	-80(%rbp), %rdi
	movl	-72(%rbp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L67
	movl	-204(%rbp), %eax
	movl	-208(%rbp), %ecx
	pushq	%r11
	movl	$1024, %r9d
	movl	-184(%rbp), %edx
	movl	-204(%rbp), %r8d
	subl	%eax, %ecx
	movl	-200(%rbp), %eax
	movq	-112(%rbp), %rdi
	movl	%edx, %esi
	pushq	%rax
	call	_Z54__device_stub__Z28small_sortManager_extraSlicePiiiiiiiPiiiiiii
	popq	%rax
	popq	%rdx
	jmp	.L67
.L65:
	movl	-200(%rbp), %eax
	xorl	%r8d, %r8d
	movq	%r13, %rdx
	movq	%r13, -68(%rbp)
	movl	$1, %ecx
	movl	$1, -60(%rbp)
	movl	%eax, -80(%rbp)
	movabsq	$4294967297, %rax
	movq	%rax, -76(%rbp)
	movq	-80(%rbp), %rdi
	movl	-72(%rbp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L67
	movl	-184(%rbp), %edx
	movl	-200(%rbp), %r8d
	movl	-196(%rbp), %ecx
	movq	-112(%rbp), %rdi
	movl	%edx, %esi
	call	_Z41__device_stub__Z17small_sortManagerPiiiiiPiiiii
.L67:
	movq	(%r14,%rbx,8), %r8
	movq	-112(%rbp), %rsi
	movl	$2, %ecx
	incq	%rbx
	movq	-224(%rbp), %rdi
	movl	$4096, %edx
	call	cudaMemcpyAsync@PLT
	jmp	.L64
.L134:
	cmpl	$0, -156(%rbp)
	jle	.L70
	cmpl	$0, -160(%rbp)
	je	.L70
	movl	-144(%rbp), %eax
	movq	(%r14,%r12,8), %r8
	movl	$1, %ecx
	movq	-176(%rbp), %rsi
	movq	-104(%rbp), %rdi
	leal	(%rax,%rax), %ebx
	movl	-132(%rbp), %eax
	cltd
	idivl	%ebx
	movl	%edx, %r13d
	movq	-192(%rbp), %rdx
	movl	%eax, -184(%rbp)
	movl	%eax, -156(%rbp)
	call	cudaMemcpyAsync@PLT
	cmpl	$0, -180(%rbp)
	je	.L71
	testl	%r13d, %r13d
	je	.L71
	movl	-132(%rbp), %eax
	movl	-156(%rbp), %esi
	xorl	%r8d, %r8d
	movq	(%r14,%r12,8), %r9
	leal	1(%rsi), %edx
	movl	%eax, -68(%rbp)
	movabsq	$4294967297, %rax
	movq	%rax, -64(%rbp)
	movl	-60(%rbp), %ecx
	movl	%edx, -80(%rbp)
	movq	-68(%rbp), %rdx
	movq	%rax, -76(%rbp)
	movq	-80(%rbp), %rdi
	movl	-72(%rbp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L73
	movl	-180(%rbp), %eax
	movl	%r13d, %ecx
	pushq	%r8
	movl	-144(%rbp), %edx
	movl	-132(%rbp), %r9d
	subl	%eax, %ecx
	movl	-156(%rbp), %eax
	movl	-180(%rbp), %r8d
	movq	-104(%rbp), %rdi
	movl	%edx, %esi
	pushq	%rax
	call	_Z54__device_stub__Z28small_sortManager_extraSlicePiiiiiiiPiiiiiii
	popq	%r9
	popq	%r10
	jmp	.L73
.L71:
	movl	-132(%rbp), %eax
	movl	-184(%rbp), %ecx
	xorl	%r8d, %r8d
	movq	(%r14,%r12,8), %r9
	movl	%eax, -68(%rbp)
	movabsq	$4294967297, %rax
	movq	%rax, -64(%rbp)
	movq	-68(%rbp), %rdx
	movl	%ecx, -80(%rbp)
	movl	-60(%rbp), %ecx
	movq	%rax, -76(%rbp)
	movq	-80(%rbp), %rdi
	movl	-72(%rbp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L73
	movl	-144(%rbp), %edx
	movl	-184(%rbp), %r8d
	movl	%ebx, %ecx
	movq	-104(%rbp), %rdi
	movl	%edx, %esi
	call	_Z41__device_stub__Z17small_sortManagerPiiiiiPiiiii
.L73:
	movq	(%r14,%r12,8), %r8
	movq	-104(%rbp), %rsi
	movl	$2, %ecx
	movq	-192(%rbp), %rdx
	movq	-176(%rbp), %rdi
	call	cudaMemcpyAsync@PLT
	movl	%r13d, -180(%rbp)
	movl	%ebx, -144(%rbp)
.L70:
	decl	-244(%rbp)
	jne	.L75
	call	cudaDeviceSynchronize@PLT
	xorl	%eax, %eax
.L76:
	cmpl	%eax, -140(%rbp)
	jle	.L135
	movq	-168(%rbp), %rbx
	movq	-232(%rbp), %rdi
	movl	$1024, %ecx
	addq	$4096, -232(%rbp)
	movq	(%rbx,%rax,8), %rsi
	incq	%rax
	rep movsl
	jmp	.L76
.L135:
	cmpl	$1, -160(%rbp)
	jne	.L79
	xorl	%eax, %eax
.L78:
	cmpl	%eax, -132(%rbp)
	jle	.L79
	movq	-176(%rbp), %rbx
	movq	-216(%rbp), %rsi
	movl	(%rbx,%rax,4), %edx
	movl	%edx, (%rsi,%rax,4)
	incq	%rax
	jmp	.L78
.L79:
	cmpl	%r15d, -236(%rbp)
	jle	.L136
	movq	(%r14,%r15,8), %rdi
	incq	%r15
	call	cudaStreamDestroy@PLT
	jmp	.L79
.L136:
	xorl	%edi, %edi
	movl	-140(%rbp), %r13d
	movl	$1024, %r12d
	movl	%edi, -144(%rbp)
.L83:
	testl	%r13d, %r13d
	jle	.L137
	incl	-144(%rbp)
	cmpl	$1, -144(%rbp)
	leal	(%r12,%r12), %ebx
	jne	.L84
.L88:
	movl	-136(%rbp), %eax
	xorl	%r8d, %r8d
	cltd
	idivl	%ebx
	movl	%edx, %r15d
	movl	%eax, %r13d
	jmp	.L85
.L84:
	movl	-136(%rbp), %eax
	cltd
	idivl	%ebx
	incl	%eax
	movslq	%eax, %r15
.L86:
	cmpl	%r15d, %r13d
	jl	.L88
	movq	(%r14,%r15,8), %rdi
	incq	%r15
	call	cudaStreamDestroy@PLT
	jmp	.L86
.L85:
	cmpl	%eax, %r8d
	jge	.L138
	movq	-152(%rbp), %rdi
	movq	%r14, %r9
	movl	%ebx, %ecx
	movl	%r12d, %edx
	movl	%r12d, %esi
	movl	%eax, -160(%rbp)
	movl	%r8d, -156(%rbp)
	call	_Z15sortManager_CPUPiiiiiPP11CUstream_st
	movl	-156(%rbp), %r8d
	movl	-160(%rbp), %eax
	incl	%r8d
	jmp	.L85
.L138:
	cmpl	$0, -132(%rbp)
	je	.L90
	testl	%r15d, %r15d
	je	.L90
	movl	-132(%rbp), %edx
	movl	%r15d, %esi
	movq	%r14, %r9
	movl	%eax, %r8d
	movq	-152(%rbp), %rdi
	movl	%ebx, %ecx
	subl	%edx, %esi
	call	_Z15sortManager_CPUPiiiiiPP11CUstream_st
.L90:
	call	cudaDeviceSynchronize@PLT
	movl	%ebx, %r12d
	movl	%r15d, -132(%rbp)
	jmp	.L83
.L137:
	call	cudaDeviceSynchronize@PLT
	movq	-88(%rbp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movq	-88(%rbp), %rdi
	call	cudaEventSynchronize@PLT
	movq	-88(%rbp), %rdx
	movq	-96(%rbp), %rsi
	leaq	-68(%rbp), %rdi
	movl	$0x00000000, -68(%rbp)
	call	cudaEventElapsedTime@PLT
	movl	-136(%rbp), %esi
	movq	-152(%rbp), %rdi
	movl	$65535, %r9d
	movl	$1024, %r8d
	call	_Z10verif_triePii
	cvtss2sd	-68(%rbp), %xmm0
	movl	$2, %esi
	pushq	%rdx
	movl	-136(%rbp), %ecx
	leaq	.LC2(%rip), %rdx
	pushq	%rax
	movq	stderr(%rip), %rdi
	movb	$1, %al
	call	__fprintf_chk@PLT
	movl	-136(%rbp), %esi
	movq	-152(%rbp), %rdi
	call	_Z10verif_triePii
	popq	%rcx
	popq	%rsi
	movl	%eax, %edx
	cmpl	$-1, %eax
	jne	.L92
	leaq	.LC3(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	jmp	.L93
.L92:
	leaq	.LC4(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
.L93:
	movq	-120(%rbp), %rdi
	xorl	%ebx, %ebx
	call	cudaFree@PLT
	movq	-112(%rbp), %rdi
	call	cudaFree@PLT
	movq	-104(%rbp), %rdi
	call	cudaFree@PLT
.L94:
	cmpl	%ebx, -140(%rbp)
	jle	.L139
	movq	-168(%rbp), %rax
	movq	(%rax,%rbx,8), %rdi
	incq	%rbx
	call	free@PLT
	jmp	.L94
.L139:
	movq	-152(%rbp), %rdi
	call	free@PLT
	movq	-168(%rbp), %rdi
	call	free@PLT
	movq	-176(%rbp), %rdi
	call	free@PLT
	movq	-56(%rbp), %rax
	subq	%fs:40, %rax
	je	.L96
	call	__stack_chk_fail@PLT
.L96:
	leaq	-40(%rbp), %rsp
	xorl	%eax, %eax
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE2032:
	.size	main, .-main
	.section	.rodata.str1.1
.LC5:
	.string	"_Z15sortManager_GPUPiS_S_S_iii"
.LC6:
	.string	"_Z28small_sortManager_extraSlicePiiiiiii"
.LC7:
	.string	"_Z17small_sortManagerPiiiii"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2064:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC5(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z15sortManager_GPUPiS_S_S_iii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC6(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z28small_sortManager_extraSlicePiiiiiii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC7(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z17small_sortManagerPiiiii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2064:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

//*****************************************************************************
//Projet HPC fusion et trie de tableaux sur GPU
//Auteur: ROBIN Clement et SAULNIER Solene
//Promo: MAIN5
//Date: decembre 2020
//Question 5 avec streams et utilisation de la shared
//*****************************************************************************


#include <hip/hip_runtime.h>
#include <stdio.h> 
#include <stdlib.h>
#define N 536870912 //taille max du tableau =d dans le projet
#define threadsPerBlock 1024
#define numBlocks 65535


//*****************************************************************************
//Fonctions CPU fusion et verification
//*****************************************************************************
int verif_trie(int *tab,int size)
{
    for (int i=0; i<size-1; i=i+1)
      if (tab[i]>tab[i+1])
          return i;
    return -1;
    
}

//*****************************************************************************
//Fonctions GPU (merge tableau) small
//*****************************************************************************
__device__ void mergeSmallBatch_k(int *A, int *B, int *M, int size_A, int size_B, int size_M, int slice_size)
{

    int i = threadIdx.x;
    if (i < size_A+size_B)
    {

     /*Merge*/
      int K[2],P[2],Q[2];
      int offset;

      if (i>size_A)
      {
          K[0]=i-size_A;
          K[1]=size_A;
          P[0]=size_A;
          P[1]=i-size_A;
      }
      else
      {
          K[0]=0;
          K[1]=i;
          P[0]=i;
          P[1]=0;
      }
      while (1)
      {
          offset=abs(K[1]-P[1])/2;
          Q[1]=K[1]-offset;
          Q[0]=K[0]+offset;
          if (Q[1] >= 0 && Q[0] <= size_B && (Q[1]== size_A || Q[0]==0 || A[Q[1]]>B[Q[0]-1]))
          {
              if (Q[0]==size_B || Q[1]==0 || A[Q[1]-1]<=B[Q[0]])
              {
                  if (Q[1]<size_A && (Q[0]==size_B || A[Q[1]]<=B[Q[0]]))
                      M[blockIdx.x * slice_size + i]=A[Q[1]];
                   
                  else
                      M[blockIdx.x * slice_size + i]=B[Q[0]]; 
                   
                  break;
              }
              else
              {
                  K[0]=Q[0]+1;
                  K[1]=Q[1]-1;
              }
          }
          else
          {
            P[0]=Q[0]-1;
            P[1]=Q[1]+1;
          }
      }
    }

}

__global__ void small_sortManager(int *M, int size_A, int size_B, int size_M, int number_of_slices)
{

      int slice_size = size_A + size_B;
        

      /*Chargement de A et B dans la shared memory*/
      /*Comme on a une seule shared memory*/
      __shared__ int shared_AB[1024];  //Comme A et B ne peuvent pas dépasser 1024
 
      int* s_A = (int*) &shared_AB[0];
      int* s_B = (int*) &s_A[size_A];
 
      __syncthreads();
 
      if (threadIdx.x < size_A)
        s_A[threadIdx.x] = M[blockIdx.x *slice_size+ threadIdx.x];

        

      if (threadIdx.x >= size_A && threadIdx.x < size_B + size_A  )
        s_B[threadIdx.x-size_A] = M[blockIdx.x *slice_size+ threadIdx.x]; 


      __syncthreads();
      /*if (size_A==1 && size_B==1)
      {
          //swap pour 2 elements
          if (threadIdx.x==0)
          {
              if (s_A[0]>s_B[0])
              {
                  M[blockIdx.x * 2]=s_B[0];
                  M[blockIdx.x * 2+1]=s_A[0];
              }
              else
              {
                  M[blockIdx.x * 2]=s_A[0];
                  M[blockIdx.x * 2+1]=s_B[0];
              }
          }
      }
      else*/ 
        mergeSmallBatch_k(s_A, s_B, M, size_A, size_B, size_M,slice_size);    
}

__global__ void small_sortManager_extraSlice(int *M ,int size_A,int size_B,int size_A_extra,int size_B_extra,int size_M,int number_of_slices)
{

        int slice_size = size_A + size_B;

      /*Chargement de A et B dans la shared memory*/
      /*Comme on a une seule shared memory*/
      __shared__ int shared_AB[1024];  //Comme A et B ne peuvent pas dépasser 1024
 
      int* s_A = (int*) &shared_AB[0];
     
      int* s_B;
     
      if (blockIdx.x == number_of_slices)
        s_B = (int*) &s_A[size_A_extra];

      else
        s_B = (int*) &s_A[size_A];
 
      __syncthreads();
 
      if (threadIdx.x < size_A)
        s_A[threadIdx.x] = M[blockIdx.x *slice_size+ threadIdx.x];

 
      if (threadIdx.x >= size_A && threadIdx.x < size_B + size_A)
        s_B[threadIdx.x-size_A] = M[blockIdx.x *slice_size+ threadIdx.x]; 

     
      if (blockIdx.x == number_of_slices && threadIdx.x < size_A_extra)
        s_A[threadIdx.x] = M[blockIdx.x *slice_size+ threadIdx.x];
     
      if (blockIdx.x == number_of_slices && threadIdx.x >= size_A_extra && threadIdx.x < size_B_extra + size_A_extra)
        s_B[threadIdx.x-size_A_extra] = M[blockIdx.x *slice_size+ threadIdx.x]; 
     

      __syncthreads();

     if (blockIdx.x == number_of_slices)
     {
         /*
         if (size_A_extra==1 && size_B_extra==1)
         {
          //swap pour 2 elements
          if (threadIdx.x==0)
          {
              if (s_A[0]>s_B[0])
              {
                  M[blockIdx.x * 2]=s_B[0];
                  M[blockIdx.x * 2+1]=s_A[0];
              }
              else
              {
                  M[blockIdx.x * 2]=s_A[0];
                  M[blockIdx.x * 2+1]=s_B[0];
              }
            }
          }
          else*/
          //{ 
              if (size_A_extra < size_B_extra)
                mergeSmallBatch_k(s_B, s_A, M, size_B_extra, size_A_extra, size_M, slice_size);  
      
              else
                mergeSmallBatch_k(s_A, s_B, M, size_A_extra, size_B_extra, size_M, slice_size); 
          //}
     }

    else
    {
      /*if (size_A==1 && size_B==1)
      {
          //swap pour 2 elements
          if (threadIdx.x==0)
          {
              if (s_A[0]>s_B[0])
              {
                  M[blockIdx.x * 2]=s_B[0];
                  M[blockIdx.x * 2+1]=s_A[0];
              }
              else
              {
                  M[blockIdx.x * 2]=s_A[0];
                  M[blockIdx.x * 2+1]=s_B[0];
              }
          }
      }
      else */
         mergeSmallBatch_k(s_A, s_B, M, size_A, size_B, size_M,slice_size); 
    }
      
    
 
}

//*****************************************************************************
//Fonctions GPU (merge tableau) big
//*****************************************************************************

__device__ void pathBig_k(int *A, int *B, int *Path, int size_A, int size_B, int size_M)
{
    for(int i = blockIdx.x * blockDim.x + threadIdx.x; i<size_M; i = i+blockDim.x*gridDim.x)
    {
      int K[2],P[2],Q[2];
      int offset;

      if (i>size_A)
      {
          K[0]=i-size_A;
          K[1]=size_A;
          P[0]=size_A;
          P[1]=i-size_A;
      }
      else
      {
          K[0]=0;
          K[1]=i;
          P[0]=i;
          P[1]=0;
      }
      while (1)
      {
          offset=abs(K[1]-P[1])/2;
          Q[1]=K[1]-offset;
          Q[0]=K[0]+offset;
          if (Q[1] >= 0 && Q[0] <= size_B && (Q[1]== size_A || Q[0]==0 || A[Q[1]]>B[Q[0]-1]))
          {
              if (Q[0]==size_B || Q[1]==0 || A[Q[1]-1]<=B[Q[0]])
              {
                  if (Q[1]<size_A && (Q[0]==size_B || A[Q[1]]<=B[Q[0]]))
                  {
                      Path[i]=1;
                      Path[i+size_M]=Q[1];
                  }
                  else
                  {
                      Path[i]=0;
                      Path[i+size_M]=Q[0];
                  }
                  break;
              }
              else
              {
                  K[0]=Q[0]+1;
                  K[1]=Q[1]-1;
              }
          }
          else
          {
            P[0]=Q[0]-1;
            P[1]=Q[1]+1;
          }
      }
    }
}


__device__ void mergeBig_k(int *A, int *B, int *M,int *Path, int size_A, int size_B, int size_M)
{
    for(int i = blockIdx.x * blockDim.x + threadIdx.x; i<size_M; i = i+blockDim.x*gridDim.x)
    {
        if (Path[i]==1)
          M[i]=A[Path[i+size_M]];
        else if (Path[i]==0)
          M[i]=B[Path[i+size_M]];
        else
          printf("ERROR thread num %d block %d",i,blockIdx.x);
                  
    }
}

__global__ void sortManager_GPU(int *A, int *B, int *M,int *Path, int size_A, int size_B, int size_M)
{
    pathBig_k(A, B, Path, size_A, size_B, size_M);
    mergeBig_k(A, B, M, Path, size_A, size_B, size_M);
}
//****************************************************************************************************
// Fonctions CPU
//****************************************************************************************************
void sortManager_CPU(int *h_M,int h_size_A,int h_size_B,int h_slice_size,int i,hipStream_t stream[])
{
    
    /*Variables CPU*/ 
    int h_size_M_tmp= h_size_A+h_size_B;
    int *h_A;
    int *h_B;
    int *h_M_tmp;
    h_A=(int *)malloc(h_size_A*sizeof(int));
    h_B=(int *)malloc(h_size_B*sizeof(int));
    h_M_tmp=(int *)malloc(h_size_M_tmp*sizeof(int));

    /*Remplir A et B*/
    for (int j=0; j<h_size_A; j++)
      h_A[j] = h_M[i*h_slice_size+j];

    for (int j=0; j<h_size_B; j++)
      h_B[j] = h_M[i*h_slice_size+j+h_size_A];
 
    /*Variables GPU*/
    int *d_A;
    int *d_B;
    int *d_M_tmp;
    int *d_Path_tmp;
    hipMalloc(&d_A,h_size_A*sizeof(int));
    hipMalloc(&d_B,h_size_B*sizeof(int));
    hipMalloc(&d_M_tmp,h_size_M_tmp*sizeof(int));
    hipMalloc(&d_Path_tmp,h_size_M_tmp*sizeof(int));

  
    /*Transfert*/
    hipMemcpyAsync(d_A, h_A, h_size_A*sizeof(int), hipMemcpyHostToDevice, stream[i]);
    hipMemcpyAsync(d_B, h_B, h_size_B*sizeof(int), hipMemcpyHostToDevice, stream[i]);
 
    /*Sort*/
    if (h_size_A<h_size_B)
      sortManager_GPU<<<numBlocks,threadsPerBlock,0, stream[i]>>>(d_B, d_A, d_M_tmp, d_Path_tmp, h_size_B, h_size_A, h_size_M_tmp);
    else
      sortManager_GPU<<<numBlocks,threadsPerBlock,0, stream[i]>>>(d_A, d_B, d_M_tmp, d_Path_tmp, h_size_A, h_size_B, h_size_M_tmp);   
    
    /*Transfert memoire GPU*/
    hipMemcpyAsync(h_M_tmp, d_M_tmp, h_size_M_tmp*sizeof(int), hipMemcpyDeviceToHost, stream[i]);

    
    /*Copie de h_M_tmp dans h_M*/
    for (int j=0; j<h_size_M_tmp; j++)
      h_M[i*h_slice_size+j]=h_M_tmp[j];
 
    
    /*Liberation*/
    free(h_A);
    free(h_B);
    free(h_M_tmp);
    hipFree(d_A);
    hipFree(d_B);
    hipFree(d_M_tmp);
    hipFree(d_Path_tmp);
}


//*****************************************************************************
//MAIN
//*****************************************************************************
int main(int argc, char const *argv[])
{
  //srand (time (NULL));
  srand (42);


  /*Déclaration des variables CPU*/
  /*Taille des tableaux*/
  int h_taille_M=N;

  /*Traitement des options*/
  for (int i=0; i<argc-1; i=i+1)
  {
      if (strcmp(argv[i],"--s")==0 && atoi(argv[i+1])<N )
          h_taille_M=atoi(argv[i+1]);   
  }

  /*Tableaux et allocation memoire*/
  int *h_M;
  h_M=(int *)malloc(h_taille_M*sizeof(int));
 
  /*Déclaration des variables GPU*/  
  int *d_M;
  hipMalloc(&d_M,h_taille_M*sizeof(int));

  /*Initialisation et preparation des tableaux*/
  for (int i=0; i<h_taille_M;i++)
    h_M[i]=rand()%10000;

  /*Merge tableau*/
  /*variables generales*/
  int h_slice_size=1;
  int h_number_of_slices=1024/2;
  int h_slice_reste_precedent=0;
  int h_slice_reste=0;
  
  /*Cas tailles de moins de 1024*/
  /*variables pour moins de 1024*/
  int h_is_irregular_batch=0;
  int h_irregular_batch_size=0;
  int h_irregular_slice_size=1;
  int h_irregular_number_of_slices=h_irregular_batch_size/2;
  int h_irregular_slice_reste_precedent=0;
  int h_irregular_slice_reste=0;


  /*Decoupage de M en batches de 1024*/
  int h_number_of_batches=h_taille_M/1024;
  if (h_taille_M%1024!=0)
  {
      h_irregular_batch_size=h_taille_M%1024;
      h_is_irregular_batch=1;
      h_irregular_number_of_slices=h_irregular_batch_size/2;   
  }
      

  /*Allocation et initialisation des batches*/
  /*Batches CPU*/
  int **h_batch_M;
  int *h_irregular_batch_M;
  h_batch_M = (int **) malloc( h_number_of_batches* sizeof(int *) );


  for (int b=0; b<h_number_of_batches; b++)
  {
    h_batch_M[b]=(int *) malloc (1024 * sizeof(int ));
    for (int ind=0; ind<1024; ind++)
        h_batch_M[b][ind]=h_M[b*1024+ind]; 
  }
  h_irregular_batch_M = (int *) malloc( h_irregular_batch_size* sizeof(int ) );
  for (int ind=0; ind<h_irregular_batch_size; ind++)
        h_irregular_batch_M[ind]=h_M[h_number_of_batches*1024+ind]; 
  
  /*Batches GPU*/
  int *d_batch_M;
  int *d_irregular_batch_M;
  hipMalloc(&d_batch_M,1024*sizeof(int));
  hipMalloc(&d_irregular_batch_M,h_irregular_batch_size*sizeof(int));
  

  /*Declaration et creation des streams*/
  hipStream_t stream[h_number_of_batches+h_is_irregular_batch];
  for (int ind_stream=0; ind_stream<h_number_of_batches; ind_stream++)
      hipStreamCreate(&stream[ind_stream]);
  if (h_is_irregular_batch==1)
      hipStreamCreate(&stream[h_number_of_batches]);


  /*Timer*/
  hipEvent_t start, stop;
  hipEventCreate(&start);
  hipEventCreate(&stop);

  /*Slices inferieures a 1024*/
  hipEventRecord(start);
  while (h_number_of_slices > 0)
  {   
      /*Mise a jour taille et indices*/
      h_slice_size=2*h_slice_size;
      h_slice_reste_precedent=h_slice_reste;
      h_slice_reste=1024%h_slice_size;
      h_number_of_slices=1024/h_slice_size;
      
      for (int b=0; b<h_number_of_batches;b++)
      {   
          hipMemcpyAsync(d_batch_M, h_batch_M[b], 1024*sizeof(int), hipMemcpyHostToDevice, stream[b]);
          
          if (h_slice_reste_precedent!=0 && h_slice_reste!=0)
          {
              int h_taille_A_extra=h_slice_reste-h_slice_reste_precedent;
              int h_taille_B_extra=h_slice_reste_precedent;
              small_sortManager_extraSlice<<<h_number_of_slices+1,1024,0,stream[b]>>>(d_batch_M,h_slice_size/2,h_slice_size/2,h_taille_A_extra,h_taille_B_extra,1024,h_number_of_slices);
          }
          else
            small_sortManager<<<h_number_of_slices,1024,0,stream[b]>>>(d_batch_M, h_slice_size/2, h_slice_size/2,h_slice_size,h_number_of_slices);

          hipMemcpyAsync(h_batch_M[b], d_batch_M, 1024*sizeof(int), hipMemcpyDeviceToHost, stream[b]);
      }
      if (h_is_irregular_batch==1 && h_irregular_number_of_slices>0)
      {
          
           h_irregular_slice_size=2*h_irregular_slice_size;
           h_irregular_slice_reste_precedent=h_irregular_slice_reste;
           h_irregular_slice_reste=h_irregular_batch_size%h_irregular_slice_size;
           h_irregular_number_of_slices=h_irregular_batch_size/h_irregular_slice_size;

           hipMemcpyAsync(d_irregular_batch_M, h_irregular_batch_M, h_irregular_batch_size*sizeof(int), hipMemcpyHostToDevice, stream[h_number_of_batches]);

           if (h_irregular_slice_reste_precedent!=0 && h_irregular_slice_reste!=0)
           {
              
              int h_taille_A_extra=h_irregular_slice_reste-h_irregular_slice_reste_precedent;
              int h_taille_B_extra=h_irregular_slice_reste_precedent;
              small_sortManager_extraSlice<<<h_irregular_number_of_slices+1,h_irregular_batch_size,0,stream[h_number_of_batches]>>>(d_irregular_batch_M,h_irregular_slice_size/2,h_irregular_slice_size/2,h_taille_A_extra,h_taille_B_extra,h_irregular_batch_size,h_irregular_number_of_slices);

           }
           else
            small_sortManager<<<h_irregular_number_of_slices,h_irregular_batch_size,0,stream[h_number_of_batches]>>>(d_irregular_batch_M, h_irregular_slice_size/2, h_irregular_slice_size/2,h_irregular_slice_size,h_irregular_number_of_slices);
          
          hipMemcpyAsync(h_irregular_batch_M, d_irregular_batch_M, h_irregular_batch_size*sizeof(int), hipMemcpyDeviceToHost, stream[h_number_of_batches]);
          
      
      }
      

  }
  hipDeviceSynchronize();

  /*re ecriture de M*/
  for (int b=0; b<h_number_of_batches; b++)
      for (int ind=0; ind<1024; ind++)
          h_M[b*1024+ind]=h_batch_M[b][ind];
  if (h_is_irregular_batch==1)
      for (int ind=0; ind<h_irregular_batch_size; ind++)
          h_M[h_number_of_batches*1024+ind]=h_irregular_batch_M[ind];
  
  
  /*Slices superieures a 1024*/

  /*Mise a jour taille et indices*/
  h_slice_size=1024;


  /*Destruction des streams qui ne servent pas*/
  for (int i=(h_taille_M/h_slice_size); i<h_number_of_batches+h_is_irregular_batch; i++)
      hipStreamDestroy(stream[i]);
       

  /*Mise a jour taille et indices suite*/    
  h_number_of_slices=h_taille_M/h_slice_size;
  h_slice_reste=h_irregular_batch_size;
  int compteur=0;
  while (h_number_of_slices>0)
  {   
      compteur=compteur+1;
      /*Mise a jour taille et indices*/
      h_slice_size=2*h_slice_size;
   
      /*Destruction des streams qui ne servent pas*/
      if (compteur>1)
        for (int i=(h_taille_M/h_slice_size)+1; i<h_number_of_slices+1; i++)
          hipStreamDestroy(stream[i]);
   
      /*Mise a jour taille et indices suite*/
      h_slice_reste_precedent=h_slice_reste;
      h_slice_reste=h_taille_M%h_slice_size;
      h_number_of_slices=h_taille_M/h_slice_size;
      
      
      for (int i=0; i<h_number_of_slices; i++)
      {   
          sortManager_CPU(h_M,h_slice_size/2,h_slice_size/2,h_slice_size,i, stream);
          
      }
      if (h_slice_reste_precedent!=0 && h_slice_reste!=0)
      {
          int h_taille_A=h_slice_reste-h_slice_reste_precedent;
          int h_taille_B=h_slice_reste_precedent;
          sortManager_CPU(h_M,h_taille_A,h_taille_B,h_slice_size,h_number_of_slices,stream);

      }
      hipDeviceSynchronize();
       
  }
  
  hipDeviceSynchronize();
  hipEventRecord(stop);

  /*Affichage du chrono*/
  hipEventSynchronize(stop);
  float ms = 0;
  hipEventElapsedTime(&ms, start, stop);
  fprintf(stderr,"mergeBatches Taille_M: %d, nbthreads: %d, numblocks: %d, Temps: %.5f, verif: %d\n", h_taille_M, threadsPerBlock, numBlocks, ms,verif_trie(h_M,h_taille_M));
  
  /*Destructions des streams restants*/
  for (int i=0; i<h_number_of_slices; i++)
    hipStreamDestroy(stream[i]);

  /*Verification*/
  if (verif_trie(h_M,h_taille_M)==-1)
    printf("ok tableau trie");
  else
    printf("KO recommencer %d ",verif_trie(h_M,h_taille_M) );

  /*Liberation*/
  hipFree(d_M);
  hipFree(d_batch_M);
  hipFree(d_irregular_batch_M);

  for (int b=0;b<h_number_of_batches;b++)
      free(h_batch_M[b]);
    
  free(h_M);
  free(h_batch_M);
  free(h_irregular_batch_M);


    return 0;
}
	.text
	.file	"mergeBatches.hip"
	.globl	_Z10verif_triePii               # -- Begin function _Z10verif_triePii
	.type	_Z10verif_triePii,@function
_Z10verif_triePii:                      # @_Z10verif_triePii
	.cfi_startproc
# %bb.0:
	cmpl	$2, %esi
	movl	$1, %ecx
	cmovgel	%esi, %ecx
	decl	%ecx
	xorl	%edx, %edx
.LBB0_1:                                # =>This Inner Loop Header: Depth=1
	cmpq	%rdx, %rcx
	je	.LBB0_4
# %bb.2:                                #   in Loop: Header=BB0_1 Depth=1
	movl	(%rdi,%rdx,4), %esi
	leaq	1(%rdx), %rax
	cmpl	4(%rdi,%rdx,4), %esi
	movq	%rax, %rdx
	jle	.LBB0_1
# %bb.3:                                # %.split.loop.exit
	decl	%eax
                                        # kill: def $eax killed $eax killed $rax
	retq
.LBB0_4:
	movl	$-1, %eax
                                        # kill: def $eax killed $eax killed $rax
	retq
.Lfunc_end0:
	.size	_Z10verif_triePii, .Lfunc_end0-_Z10verif_triePii
	.cfi_endproc
                                        # -- End function
	.globl	_Z32__device_stub__small_sortManagerPiiiii # -- Begin function _Z32__device_stub__small_sortManagerPiiiii
	.type	_Z32__device_stub__small_sortManagerPiiiii,@function
_Z32__device_stub__small_sortManagerPiiiii: # @_Z32__device_stub__small_sortManagerPiiiii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	20(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	16(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	12(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	8(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z17small_sortManagerPiiiii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z32__device_stub__small_sortManagerPiiiii, .Lfunc_end1-_Z32__device_stub__small_sortManagerPiiiii
	.cfi_endproc
                                        # -- End function
	.globl	_Z43__device_stub__small_sortManager_extraSlicePiiiiiii # -- Begin function _Z43__device_stub__small_sortManager_extraSlicePiiiiiii
	.type	_Z43__device_stub__small_sortManager_extraSlicePiiiiiii,@function
_Z43__device_stub__small_sortManager_extraSlicePiiiiiii: # @_Z43__device_stub__small_sortManager_extraSlicePiiiiiii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	20(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	16(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	12(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	8(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	4(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	192(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z28small_sortManager_extraSlicePiiiiiii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z43__device_stub__small_sortManager_extraSlicePiiiiiii, .Lfunc_end2-_Z43__device_stub__small_sortManager_extraSlicePiiiiiii
	.cfi_endproc
                                        # -- End function
	.globl	_Z30__device_stub__sortManager_GPUPiS_S_S_iii # -- Begin function _Z30__device_stub__sortManager_GPUPiS_S_S_iii
	.type	_Z30__device_stub__sortManager_GPUPiS_S_S_iii,@function
_Z30__device_stub__sortManager_GPUPiS_S_S_iii: # @_Z30__device_stub__sortManager_GPUPiS_S_S_iii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	12(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	8(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z15sortManager_GPUPiS_S_S_iii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	_Z30__device_stub__sortManager_GPUPiS_S_S_iii, .Lfunc_end3-_Z30__device_stub__sortManager_GPUPiS_S_S_iii
	.cfi_endproc
                                        # -- End function
	.globl	_Z15sortManager_CPUPiiiiiPP12ihipStream_t # -- Begin function _Z15sortManager_CPUPiiiiiPP12ihipStream_t
	.type	_Z15sortManager_CPUPiiiiiPP12ihipStream_t,@function
_Z15sortManager_CPUPiiiiiPP12ihipStream_t: # @_Z15sortManager_CPUPiiiiiPP12ihipStream_t
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$120, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%r9, 96(%rsp)                   # 8-byte Spill
	movl	%r8d, 28(%rsp)                  # 4-byte Spill
	movl	%ecx, 24(%rsp)                  # 4-byte Spill
	movl	%edx, %r14d
	movl	%esi, %r13d
	movq	%rdi, %r15
	leal	(%r14,%r13), %ebp
	movslq	%esi, %rbx
	leaq	(,%rbx,4), %rdi
	movq	%rdi, 104(%rsp)                 # 8-byte Spill
	callq	malloc
	movq	%rax, 56(%rsp)                  # 8-byte Spill
	movq	%r14, 16(%rsp)                  # 8-byte Spill
	movslq	%r14d, %r14
	shlq	$2, %r14
	movq	%r14, %rdi
	callq	malloc
	movq	%rax, %r12
	movq	%rbp, 72(%rsp)                  # 8-byte Spill
	movslq	%ebp, %rdi
	movl	28(%rsp), %ebp                  # 4-byte Reload
	shlq	$2, %rdi
	movq	%rdi, 88(%rsp)                  # 8-byte Spill
	callq	malloc
	movq	%rax, 112(%rsp)                 # 8-byte Spill
	testl	%ebx, %ebx
	movl	24(%rsp), %ebx                  # 4-byte Reload
	jle	.LBB4_2
# %bb.1:                                # %.lr.ph
	movl	%ebp, %eax
	imull	%ebx, %eax
	cltq
	leaq	(%r15,%rax,4), %rsi
	movl	%r13d, %edx
	shlq	$2, %rdx
	movq	56(%rsp), %rdi                  # 8-byte Reload
	callq	memcpy@PLT
.LBB4_2:                                # %.preheader
	movq	%r13, 80(%rsp)                  # 8-byte Spill
	cmpl	$0, 16(%rsp)                    # 4-byte Folded Reload
	movl	%ebp, %r13d
	jle	.LBB4_5
# %bb.3:                                # %.lr.ph85
	movl	%r13d, %eax
	imull	%ebx, %eax
	movl	16(%rsp), %ecx                  # 4-byte Reload
	addl	80(%rsp), %eax                  # 4-byte Folded Reload
	xorl	%edx, %edx
.LBB4_4:                                # =>This Inner Loop Header: Depth=1
	leal	(%rax,%rdx), %esi
	movslq	%esi, %rsi
	movl	(%r15,%rsi,4), %esi
	movl	%esi, (%r12,%rdx,4)
	incq	%rdx
	cmpq	%rdx, %rcx
	jne	.LBB4_4
.LBB4_5:                                # %._crit_edge
	leaq	48(%rsp), %rdi
	movq	104(%rsp), %rbp                 # 8-byte Reload
	movq	%rbp, %rsi
	callq	hipMalloc
	leaq	40(%rsp), %rdi
	movq	%r14, %rsi
	callq	hipMalloc
	leaq	32(%rsp), %rdi
	movq	88(%rsp), %rbx                  # 8-byte Reload
	movq	%rbx, %rsi
	callq	hipMalloc
	leaq	64(%rsp), %rdi
	movq	%rbx, %rsi
	callq	hipMalloc
	leaq	48(%rsp), %rax
	movq	(%rax), %rdi
	movslq	%r13d, %rbx
	movq	96(%rsp), %r13                  # 8-byte Reload
	movq	(%r13,%rbx,8), %r8
	movq	56(%rsp), %rsi                  # 8-byte Reload
	movq	%rbp, %rdx
	movl	$1, %ecx
	callq	hipMemcpyAsync
	leaq	40(%rsp), %rax
	movq	(%rax), %rdi
	movq	(%r13,%rbx,8), %r8
	movq	%r12, %rsi
	movq	%r14, %rdx
	movl	$1, %ecx
	callq	hipMemcpyAsync
	movq	(%r13,%rbx,8), %r9
	movabsq	$4294968320, %rdx               # imm = 0x100000400
	leaq	64511(%rdx), %rdi
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	callq	__hipPushCallConfiguration
	movq	80(%rsp), %r9                   # 8-byte Reload
	cmpl	16(%rsp), %r9d                  # 4-byte Folded Reload
	jge	.LBB4_8
# %bb.6:
	testl	%eax, %eax
	movq	72(%rsp), %r14                  # 8-byte Reload
	jne	.LBB4_11
# %bb.7:
	movq	40(%rsp), %rdi
	movq	48(%rsp), %rsi
	movq	32(%rsp), %rdx
	movq	64(%rsp), %rcx
	movl	%r14d, (%rsp)
	movq	16(%rsp), %r8                   # 8-byte Reload
                                        # kill: def $r8d killed $r8d killed $r8
	jmp	.LBB4_10
.LBB4_8:
	testl	%eax, %eax
	movq	72(%rsp), %r14                  # 8-byte Reload
	jne	.LBB4_11
# %bb.9:
	movq	48(%rsp), %rdi
	movq	40(%rsp), %rsi
	movq	32(%rsp), %rdx
	movq	64(%rsp), %rcx
	movl	%r14d, (%rsp)
	movl	%r9d, %r8d
	movq	16(%rsp), %r9                   # 8-byte Reload
.LBB4_10:
                                        # kill: def $r9d killed $r9d killed $r9
	callq	_Z30__device_stub__sortManager_GPUPiS_S_S_iii
.LBB4_11:
	movq	32(%rsp), %rsi
	movq	96(%rsp), %rax                  # 8-byte Reload
	movq	(%rax,%rbx,8), %r8
	movq	112(%rsp), %rbp                 # 8-byte Reload
	movq	%rbp, %rdi
	movq	88(%rsp), %rdx                  # 8-byte Reload
	movl	$2, %ecx
	callq	hipMemcpyAsync
	testl	%r14d, %r14d
	movq	56(%rsp), %rbx                  # 8-byte Reload
	movl	28(%rsp), %eax                  # 4-byte Reload
	jle	.LBB4_13
# %bb.12:                               # %.lr.ph88
	imull	24(%rsp), %eax                  # 4-byte Folded Reload
	cltq
	leaq	(%r15,%rax,4), %rdi
	decl	%r14d
	leaq	4(,%r14,4), %rdx
	movq	%rbp, %rsi
	callq	memcpy@PLT
.LBB4_13:                               # %._crit_edge89
	movq	%rbx, %rdi
	callq	free
	movq	%r12, %rdi
	callq	free
	movq	%rbp, %rdi
	callq	free
	movq	48(%rsp), %rdi
	callq	hipFree
	movq	40(%rsp), %rdi
	callq	hipFree
	movq	32(%rsp), %rdi
	callq	hipFree
	movq	64(%rsp), %rdi
	callq	hipFree
	addq	$120, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end4:
	.size	_Z15sortManager_CPUPiiiiiPP12ihipStream_t, .Lfunc_end4-_Z15sortManager_CPUPiiiiiPP12ihipStream_t
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$232, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rsi, %rbx
	movl	%edi, %r14d
	movl	$42, %edi
	callq	srand
	movl	$536870912, %eax                # imm = 0x20000000
	movq	%rax, -56(%rbp)                 # 8-byte Spill
	cmpl	$2, %r14d
	jl	.LBB5_5
# %bb.1:                                # %.lr.ph.preheader
	decl	%r14d
	movl	$536870912, %eax                # imm = 0x20000000
	movq	%rax, -56(%rbp)                 # 8-byte Spill
	xorl	%r15d, %r15d
.LBB5_2:                                # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	movq	(%rbx,%r15,8), %rdi
	movl	$.L.str, %esi
	callq	strcmp
	testl	%eax, %eax
	jne	.LBB5_4
# %bb.3:                                #   in Loop: Header=BB5_2 Depth=1
	movq	8(%rbx,%r15,8), %rdi
	callq	atoi
	cmpl	$536870912, %eax                # imm = 0x20000000
	movq	-56(%rbp), %rcx                 # 8-byte Reload
	cmovll	%eax, %ecx
	movq	%rcx, -56(%rbp)                 # 8-byte Spill
.LBB5_4:                                #   in Loop: Header=BB5_2 Depth=1
	incq	%r15
	cmpq	%r15, %r14
	jne	.LBB5_2
.LBB5_5:                                # %._crit_edge
	movslq	-56(%rbp), %r14                 # 4-byte Folded Reload
	leaq	(,%r14,4), %rbx
	movq	%rbx, %rdi
	callq	malloc
	movq	%rax, %r15
	leaq	-264(%rbp), %rdi
	movq	%rbx, %rsi
	callq	hipMalloc
	testl	%r14d, %r14d
	jle	.LBB5_8
# %bb.6:                                # %.lr.ph316.preheader
	movl	-56(%rbp), %ebx                 # 4-byte Reload
	xorl	%r14d, %r14d
.LBB5_7:                                # %.lr.ph316
                                        # =>This Inner Loop Header: Depth=1
	callq	rand
	cltq
	imulq	$1759218605, %rax, %rcx         # imm = 0x68DB8BAD
	movq	%rcx, %rdx
	shrq	$63, %rdx
	sarq	$44, %rcx
	addl	%edx, %ecx
	imull	$10000, %ecx, %ecx              # imm = 0x2710
	subl	%ecx, %eax
	movl	%eax, (%r15,%r14,4)
	incq	%r14
	cmpq	%r14, %rbx
	jne	.LBB5_7
.LBB5_8:                                # %._crit_edge317
	movq	%r15, -72(%rbp)                 # 8-byte Spill
	movq	-56(%rbp), %rbx                 # 8-byte Reload
	leal	1023(%rbx), %eax
	testl	%ebx, %ebx
	cmovnsl	%ebx, %eax
	movl	%eax, %r14d
	sarl	$10, %r14d
	andl	$-1024, %eax                    # imm = 0xFC00
	movl	%ebx, %ecx
	subl	%eax, %ecx
	setne	-64(%rbp)                       # 1-byte Folded Spill
	movl	%ecx, -44(%rbp)                 # 4-byte Spill
	movzwl	%cx, %r15d
	shrl	$15, %r15d
	movslq	%r14d, %rax
	movq	%rax, -168(%rbp)                # 8-byte Spill
	leaq	(,%rax,8), %rdi
	callq	malloc
	movq	%rax, %r13
	movl	%r14d, -76(%rbp)                # 4-byte Spill
	movl	%r14d, %r14d
	cmpl	$1024, %ebx                     # imm = 0x400
	jl	.LBB5_11
# %bb.9:                                # %.lr.ph321.preheader
	xorl	%r12d, %r12d
	movq	-72(%rbp), %rbx                 # 8-byte Reload
.LBB5_10:                               # %.lr.ph321
                                        # =>This Inner Loop Header: Depth=1
	movl	$4096, %edi                     # imm = 0x1000
	callq	malloc
	movq	%rax, (%r13,%r12,8)
	movl	$4096, %edx                     # imm = 0x1000
	movq	%rax, %rdi
	movq	%rbx, %rsi
	callq	memcpy@PLT
	incq	%r12
	addq	$4096, %rbx                     # imm = 0x1000
	cmpq	%r12, %r14
	jne	.LBB5_10
.LBB5_11:                               # %._crit_edge322
	movq	%r14, -144(%rbp)                # 8-byte Spill
	movl	-44(%rbp), %r14d                # 4-byte Reload
	addl	%r14d, %r15d
	xorl	%r12d, %r12d
	movb	-64(%rbp), %al                  # 1-byte Reload
	movb	%al, %r12b
	movslq	%r14d, %rdi
	shlq	$2, %rdi
	movq	%rdi, -176(%rbp)                # 8-byte Spill
	callq	malloc
	movq	%rax, %rbx
	movl	%r14d, %eax
	movq	%rax, -152(%rbp)                # 8-byte Spill
	testl	%r14d, %r14d
	movl	-76(%rbp), %r14d                # 4-byte Reload
	jle	.LBB5_13
# %bb.12:                               # %.lr.ph325
	movl	%r14d, %eax
	shll	$10, %eax
	cltq
	movq	-72(%rbp), %rcx                 # 8-byte Reload
	leaq	(%rcx,%rax,4), %rsi
	movq	-152(%rbp), %rax                # 8-byte Reload
	leaq	(,%rax,4), %rdx
	movq	%rbx, %rdi
	callq	memcpy@PLT
.LBB5_13:                               # %._crit_edge326
	movq	%rbx, -160(%rbp)                # 8-byte Spill
	leaq	-128(%rbp), %rdi
	movl	$4096, %esi                     # imm = 0x1000
	callq	hipMalloc
	leaq	-120(%rbp), %rdi
	movq	-176(%rbp), %rsi                # 8-byte Reload
	callq	hipMalloc
	movq	%rsp, -248(%rbp)                # 8-byte Spill
	addl	%r14d, %r12d
	movq	%r12, -240(%rbp)                # 8-byte Spill
	leaq	15(,%r12,8), %rax
	andq	$-16, %rax
	movq	%rsp, %rbx
	subq	%rax, %rbx
	movq	%rbx, %rsp
	cmpl	$1024, -56(%rbp)                # 4-byte Folded Reload
                                        # imm = 0x400
	jl	.LBB5_16
# %bb.14:                               # %.lr.ph329.preheader
	movq	-144(%rbp), %r12                # 8-byte Reload
	movq	%rbx, %r14
.LBB5_15:                               # %.lr.ph329
                                        # =>This Inner Loop Header: Depth=1
	movq	%r14, %rdi
	callq	hipStreamCreate
	addq	$8, %r14
	decq	%r12
	jne	.LBB5_15
.LBB5_16:                               # %._crit_edge330
	movq	%r13, -208(%rbp)                # 8-byte Spill
	movswl	%r15w, %r14d
	cmpl	$0, -44(%rbp)                   # 4-byte Folded Reload
	je	.LBB5_18
# %bb.17:
	movq	-168(%rbp), %rax                # 8-byte Reload
	leaq	(%rbx,%rax,8), %rdi
	callq	hipStreamCreate
.LBB5_18:
	sarl	%r14d
	movq	%r14, -96(%rbp)                 # 8-byte Spill
	movabsq	$4294967296, %r15               # imm = 0x100000000
	leaq	-256(%rbp), %r14
	movq	%r14, %rdi
	callq	hipEventCreate
	leaq	-216(%rbp), %rdi
	callq	hipEventCreate
	movq	(%r14), %rdi
	xorl	%eax, %eax
	movq	%rax, -184(%rbp)                # 8-byte Spill
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	-152(%rbp), %rax                # 8-byte Reload
	btsq	$32, %rax
	movq	%rax, -232(%rbp)                # 8-byte Spill
	movl	$1, -84(%rbp)                   # 4-byte Folded Spill
	leaq	1024(%r15), %rax
	movq	%rax, -64(%rbp)                 # 8-byte Spill
	movl	$1, %eax
	movq	%rax, -104(%rbp)                # 8-byte Spill
	movl	$0, -80(%rbp)                   # 4-byte Folded Spill
.LBB5_19:                               # =>This Loop Header: Depth=1
                                        #     Child Loop BB5_21 Depth 2
	movq	-184(%rbp), %rax                # 8-byte Reload
                                        # kill: def $eax killed $eax killed $rax
	movl	%eax, -132(%rbp)                # 4-byte Spill
	movl	-84(%rbp), %eax                 # 4-byte Reload
                                        # kill: def $eax killed $eax def $rax
	leal	(%rax,%rax), %esi
	movq	%rax, -112(%rbp)                # 8-byte Spill
	leal	-1(,%rax,2), %eax
	movl	$1024, %ecx                     # imm = 0x400
	andl	%ecx, %eax
	movq	%rax, -184(%rbp)                # 8-byte Spill
	movl	$1024, %eax                     # imm = 0x400
	xorl	%edx, %edx
	movl	%esi, -84(%rbp)                 # 4-byte Spill
	divl	%esi
                                        # kill: def $eax killed $eax def $rax
	movq	%rax, -192(%rbp)                # 8-byte Spill
	cmpl	%ecx, -56(%rbp)                 # 4-byte Folded Reload
	jl	.LBB5_24
# %bb.20:                               # %.lr.ph333
                                        #   in Loop: Header=BB5_19 Depth=1
	movl	-132(%rbp), %edx                # 4-byte Reload
	testl	%edx, %edx
	setne	%al
	movq	-184(%rbp), %rcx                # 8-byte Reload
	testl	%ecx, %ecx
	setne	%r12b
	andb	%al, %r12b
	movl	-192(%rbp), %r13d               # 4-byte Reload
	movabsq	$4294967296, %rax               # imm = 0x100000000
	leaq	(%rax,%r13), %rsi
	incq	%rsi
	movq	%rsi, -200(%rbp)                # 8-byte Spill
	orq	%rax, %r13
	movl	%ecx, %eax
	subl	%edx, %eax
	movl	%eax, -220(%rbp)                # 4-byte Spill
	xorl	%r14d, %r14d
.LBB5_21:                               #   Parent Loop BB5_19 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movq	-128(%rbp), %rdi
	movq	-208(%rbp), %rax                # 8-byte Reload
	movq	(%rax,%r14,8), %r15
	movq	(%rbx,%r14,8), %r8
	movl	$4096, %edx                     # imm = 0x1000
	movq	%r15, %rsi
	movl	$1, %ecx
	callq	hipMemcpyAsync
	movq	(%rbx,%r14,8), %r9
	testb	%r12b, %r12b
	je	.LBB5_31
# %bb.22:                               #   in Loop: Header=BB5_21 Depth=2
	movq	-200(%rbp), %rdi                # 8-byte Reload
	movl	$1, %esi
	movq	-64(%rbp), %rdx                 # 8-byte Reload
	movl	$1, %ecx
	xorl	%r8d, %r8d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB5_33
# %bb.23:                               #   in Loop: Header=BB5_21 Depth=2
	movq	-128(%rbp), %rdi
	subq	$8, %rsp
	movq	-112(%rbp), %rdx                # 8-byte Reload
	movl	%edx, %esi
                                        # kill: def $edx killed $edx killed $rdx
	movl	-220(%rbp), %ecx                # 4-byte Reload
	movl	-132(%rbp), %r8d                # 4-byte Reload
	movl	$1024, %r9d                     # imm = 0x400
	pushq	-192(%rbp)                      # 8-byte Folded Reload
	callq	_Z43__device_stub__small_sortManager_extraSlicePiiiiiii
	addq	$16, %rsp
	jmp	.LBB5_33
.LBB5_31:                               #   in Loop: Header=BB5_21 Depth=2
	movq	%r13, %rdi
	movl	$1, %esi
	movq	-64(%rbp), %rdx                 # 8-byte Reload
	movl	$1, %ecx
	xorl	%r8d, %r8d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB5_33
# %bb.32:                               #   in Loop: Header=BB5_21 Depth=2
	movq	-128(%rbp), %rdi
	movq	-112(%rbp), %rdx                # 8-byte Reload
	movl	%edx, %esi
                                        # kill: def $edx killed $edx killed $rdx
	movl	-84(%rbp), %ecx                 # 4-byte Reload
	movq	-192(%rbp), %r8                 # 8-byte Reload
                                        # kill: def $r8d killed $r8d killed $r8
	callq	_Z32__device_stub__small_sortManagerPiiiii
.LBB5_33:                               #   in Loop: Header=BB5_21 Depth=2
	movq	-128(%rbp), %rsi
	movq	(%rbx,%r14,8), %r8
	movl	$4096, %edx                     # imm = 0x1000
	movq	%r15, %rdi
	movl	$2, %ecx
	callq	hipMemcpyAsync
	incq	%r14
	cmpq	%r14, -144(%rbp)                # 8-byte Folded Reload
	jne	.LBB5_21
.LBB5_24:                               # %._crit_edge334
                                        #   in Loop: Header=BB5_19 Depth=1
	cmpl	$0, -44(%rbp)                   # 4-byte Folded Reload
	je	.LBB5_25
# %bb.26:                               # %._crit_edge334
                                        #   in Loop: Header=BB5_19 Depth=1
	cmpl	$0, -96(%rbp)                   # 4-byte Folded Reload
	movq	-168(%rbp), %r12                # 8-byte Reload
	jle	.LBB5_25
# %bb.27:                               #   in Loop: Header=BB5_19 Depth=1
	movq	-104(%rbp), %rax                # 8-byte Reload
	leal	(%rax,%rax), %r13d
	movl	-44(%rbp), %eax                 # 4-byte Reload
	cltd
	idivl	%r13d
                                        # kill: def $eax killed $eax def $rax
	movq	%rax, -96(%rbp)                 # 8-byte Spill
	movl	%edx, %r15d
	movq	-120(%rbp), %rdi
	movq	(%rbx,%r12,8), %r8
	movq	-160(%rbp), %r14                # 8-byte Reload
	movq	%r14, %rsi
	movq	-176(%rbp), %rdx                # 8-byte Reload
	movl	$1, %ecx
	callq	hipMemcpyAsync
	cmpl	$0, -80(%rbp)                   # 4-byte Folded Reload
	je	.LBB5_34
# %bb.28:                               #   in Loop: Header=BB5_19 Depth=1
	testl	%r15d, %r15d
	je	.LBB5_34
# %bb.29:                               #   in Loop: Header=BB5_19 Depth=1
	movq	-96(%rbp), %rdi                 # 8-byte Reload
                                        # kill: def $edi killed $edi killed $rdi def $rdi
	incl	%edi
	movq	(%rbx,%r12,8), %r9
	movabsq	$4294967296, %rax               # imm = 0x100000000
	orq	%rax, %rdi
	movl	$1, %esi
	movq	-232(%rbp), %rdx                # 8-byte Reload
	movl	$1, %ecx
	xorl	%r8d, %r8d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB5_36
# %bb.30:                               #   in Loop: Header=BB5_19 Depth=1
	movl	%r15d, %ecx
	movl	-80(%rbp), %r8d                 # 4-byte Reload
	subl	%r8d, %ecx
	movq	-120(%rbp), %rdi
	subq	$8, %rsp
	movq	-104(%rbp), %rdx                # 8-byte Reload
	movl	%edx, %esi
                                        # kill: def $edx killed $edx killed $rdx
	movl	-44(%rbp), %r9d                 # 4-byte Reload
	pushq	-96(%rbp)                       # 8-byte Folded Reload
	callq	_Z43__device_stub__small_sortManager_extraSlicePiiiiiii
	addq	$16, %rsp
	jmp	.LBB5_36
.LBB5_25:                               #   in Loop: Header=BB5_19 Depth=1
	movq	-104(%rbp), %rax                # 8-byte Reload
	movl	%eax, %r13d
	jmp	.LBB5_37
.LBB5_34:                               #   in Loop: Header=BB5_19 Depth=1
	movq	(%rbx,%r12,8), %r9
	movl	-96(%rbp), %edi                 # 4-byte Reload
	movabsq	$4294967296, %rax               # imm = 0x100000000
	orq	%rax, %rdi
	movl	$1, %esi
	movq	-232(%rbp), %rdx                # 8-byte Reload
	movl	$1, %ecx
	xorl	%r8d, %r8d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB5_36
# %bb.35:                               #   in Loop: Header=BB5_19 Depth=1
	movq	-120(%rbp), %rdi
	movq	-104(%rbp), %rdx                # 8-byte Reload
	movl	%edx, %esi
                                        # kill: def $edx killed $edx killed $rdx
	movl	%r13d, %ecx
	movq	-96(%rbp), %r8                  # 8-byte Reload
                                        # kill: def $r8d killed $r8d killed $r8
	callq	_Z32__device_stub__small_sortManagerPiiiii
.LBB5_36:                               #   in Loop: Header=BB5_19 Depth=1
	movq	-120(%rbp), %rsi
	movq	(%rbx,%r12,8), %r8
	movq	%r14, %rdi
	movq	-176(%rbp), %rdx                # 8-byte Reload
	movl	$2, %ecx
	callq	hipMemcpyAsync
	movl	%r15d, -80(%rbp)                # 4-byte Spill
.LBB5_37:                               #   in Loop: Header=BB5_19 Depth=1
	movl	%r13d, %eax
	movq	%rax, -104(%rbp)                # 8-byte Spill
	cmpl	$513, -112(%rbp)                # 4-byte Folded Reload
                                        # imm = 0x201
	jb	.LBB5_19
# %bb.38:
	callq	hipDeviceSynchronize
	cmpl	$1024, -56(%rbp)                # 4-byte Folded Reload
                                        # imm = 0x400
	movq	-208(%rbp), %r12                # 8-byte Reload
	movq	-144(%rbp), %r13                # 8-byte Reload
	jl	.LBB5_41
# %bb.39:                               # %.preheader308.preheader
	xorl	%r15d, %r15d
	movq	-72(%rbp), %r14                 # 8-byte Reload
.LBB5_40:                               # %.preheader308
                                        # =>This Inner Loop Header: Depth=1
	movq	(%r12,%r15,8), %rsi
	movl	$4096, %edx                     # imm = 0x1000
	movq	%r14, %rdi
	callq	memcpy@PLT
	incq	%r15
	addq	$4096, %r14                     # imm = 0x1000
	cmpq	%r15, %r13
	jne	.LBB5_40
.LBB5_41:                               # %._crit_edge342
	cmpl	$0, -44(%rbp)                   # 4-byte Folded Reload
	je	.LBB5_46
# %bb.42:                               # %.preheader306
	jle	.LBB5_44
# %bb.43:                               # %.lr.ph344
	movl	-76(%rbp), %eax                 # 4-byte Reload
	shll	$10, %eax
	cltq
	movq	-72(%rbp), %rcx                 # 8-byte Reload
	leaq	(%rcx,%rax,4), %rdi
	movq	-152(%rbp), %rdx                # 8-byte Reload
	shlq	$2, %rdx
	movq	-160(%rbp), %rsi                # 8-byte Reload
	callq	memcpy@PLT
.LBB5_44:                               # %.lr.ph347.preheader
	movslq	-240(%rbp), %r14                # 4-byte Folded Reload
	movq	-168(%rbp), %r15                # 8-byte Reload
.LBB5_45:                               # %.lr.ph347
                                        # =>This Inner Loop Header: Depth=1
	movq	(%rbx,%r15,8), %rdi
	callq	hipStreamDestroy
	incq	%r15
	cmpq	%r14, %r15
	jl	.LBB5_45
.LBB5_46:                               # %.preheader305
	cmpl	$1024, -56(%rbp)                # 4-byte Folded Reload
                                        # imm = 0x400
	movl	-76(%rbp), %r14d                # 4-byte Reload
	jl	.LBB5_59
# %bb.47:                               # %.lr.ph359.preheader
	movl	$1024, %eax                     # imm = 0x400
	xorl	%r13d, %r13d
.LBB5_48:                               # %.lr.ph359
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB5_51 Depth 2
                                        #     Child Loop BB5_54 Depth 2
	movl	%eax, %r12d
	leal	(%r12,%r12), %ecx
	movq	-56(%rbp), %rax                 # 8-byte Reload
                                        # kill: def $eax killed $eax killed $rax
	xorl	%edx, %edx
	movl	%ecx, -64(%rbp)                 # 4-byte Spill
	divl	%ecx
	movl	%eax, %r15d
	movl	%r13d, -200(%rbp)               # 4-byte Spill
	testl	%r13d, %r13d
	je	.LBB5_52
# %bb.49:                               # %.lr.ph359
                                        #   in Loop: Header=BB5_48 Depth=1
	cmpl	%r14d, %r15d
	jge	.LBB5_52
# %bb.50:                               # %.lr.ph350.preheader
                                        #   in Loop: Header=BB5_48 Depth=1
	movq	-56(%rbp), %rax                 # 8-byte Reload
                                        # kill: def $eax killed $eax killed $rax
	xorl	%edx, %edx
	divl	-64(%rbp)                       # 4-byte Folded Reload
	movl	%eax, %r13d
.LBB5_51:                               # %.lr.ph350
                                        #   Parent Loop BB5_48 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movq	8(%rbx,%r13,8), %rdi
	incq	%r13
	callq	hipStreamDestroy
	cmpl	%r13d, %r14d
	jg	.LBB5_51
.LBB5_52:                               # %.loopexit
                                        #   in Loop: Header=BB5_48 Depth=1
	movq	-56(%rbp), %rax                 # 8-byte Reload
                                        # kill: def $eax killed $eax killed $rax
	cltd
	idivl	-64(%rbp)                       # 4-byte Folded Reload
	movl	%edx, -112(%rbp)                # 4-byte Spill
	testl	%r15d, %r15d
	movq	-72(%rbp), %r14                 # 8-byte Reload
	jle	.LBB5_55
# %bb.53:                               # %.lr.ph353.preheader
                                        #   in Loop: Header=BB5_48 Depth=1
	xorl	%r13d, %r13d
.LBB5_54:                               # %.lr.ph353
                                        #   Parent Loop BB5_48 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movq	%r14, %rdi
	movl	%r12d, %esi
	movl	%r12d, %edx
	movl	-64(%rbp), %ecx                 # 4-byte Reload
	movl	%r13d, %r8d
	movq	%rbx, %r9
	callq	_Z15sortManager_CPUPiiiiiPP12ihipStream_t
	incl	%r13d
	cmpl	%r15d, %r13d
	jl	.LBB5_54
.LBB5_55:                               # %._crit_edge354
                                        #   in Loop: Header=BB5_48 Depth=1
	movl	%r15d, %r14d
	cmpl	$0, -44(%rbp)                   # 4-byte Folded Reload
	movl	-200(%rbp), %r13d               # 4-byte Reload
	movl	-112(%rbp), %r12d               # 4-byte Reload
	je	.LBB5_58
# %bb.56:                               # %._crit_edge354
                                        #   in Loop: Header=BB5_48 Depth=1
	testl	%r12d, %r12d
	je	.LBB5_58
# %bb.57:                               #   in Loop: Header=BB5_48 Depth=1
	movl	%r12d, %esi
	movl	-44(%rbp), %edx                 # 4-byte Reload
	subl	%edx, %esi
	movq	-72(%rbp), %rdi                 # 8-byte Reload
	movl	-64(%rbp), %ecx                 # 4-byte Reload
	movl	%r14d, %r8d
	movq	%rbx, %r9
	callq	_Z15sortManager_CPUPiiiiiPP12ihipStream_t
.LBB5_58:                               #   in Loop: Header=BB5_48 Depth=1
	incl	%r13d
	callq	hipDeviceSynchronize
	movl	%r12d, -44(%rbp)                # 4-byte Spill
	testl	%r15d, %r15d
	movl	-64(%rbp), %eax                 # 4-byte Reload
	jg	.LBB5_48
.LBB5_59:                               # %._crit_edge360
	callq	hipDeviceSynchronize
	movq	-216(%rbp), %rdi
	xorl	%r14d, %r14d
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	-216(%rbp), %rdi
	callq	hipEventSynchronize
	leaq	-268(%rbp), %rbx
	movl	$0, (%rbx)
	movq	-256(%rbp), %rsi
	movq	-216(%rbp), %rdx
	movq	%rbx, %rdi
	callq	hipEventElapsedTime
	movq	stderr(%rip), %rdi
	cvtss2sd	(%rbx), %xmm0
	movq	-56(%rbp), %rax                 # 8-byte Reload
	cmpl	$2, %eax
	movl	$1, %ebx
	cmovgel	%eax, %ebx
	decl	%ebx
	movq	-72(%rbp), %r15                 # 8-byte Reload
.LBB5_60:                               # =>This Inner Loop Header: Depth=1
	cmpq	%r14, %rbx
	je	.LBB5_61
# %bb.62:                               #   in Loop: Header=BB5_60 Depth=1
	movl	(%r15,%r14,4), %eax
	leaq	1(%r14), %r9
	cmpl	4(%r15,%r14,4), %eax
	movq	%r9, %r14
	jle	.LBB5_60
# %bb.63:                               # %.split.loop.exit.i
	decl	%r9d
	jmp	.LBB5_64
.LBB5_61:
	movl	$-1, %r9d
.LBB5_64:                               # %_Z10verif_triePii.exit
	movl	$.L.str.1, %esi
	movq	-56(%rbp), %rdx                 # 8-byte Reload
                                        # kill: def $edx killed $edx killed $rdx
	movl	$1024, %ecx                     # imm = 0x400
	movl	$65535, %r8d                    # imm = 0xFFFF
                                        # kill: def $r9d killed $r9d killed $r9
	movb	$1, %al
	callq	fprintf
	xorl	%eax, %eax
	movq	-144(%rbp), %r14                # 8-byte Reload
	movq	-208(%rbp), %r12                # 8-byte Reload
.LBB5_65:                               # =>This Inner Loop Header: Depth=1
	cmpq	%rax, %rbx
	je	.LBB5_78
# %bb.66:                               #   in Loop: Header=BB5_65 Depth=1
	movl	(%r15,%rax,4), %edx
	leaq	1(%rax), %rcx
	cmpl	4(%r15,%rax,4), %edx
	movq	%rcx, %rax
	jle	.LBB5_65
# %bb.67:                               # %_Z10verif_triePii.exit273
	movabsq	$4294967296, %rax               # imm = 0x100000000
	cmpq	%rcx, %rax
	jne	.LBB5_68
.LBB5_78:                               # %_Z10verif_triePii.exit273.thread
	movl	$.L.str.2, %edi
	xorl	%eax, %eax
	callq	printf
	jmp	.LBB5_74
.LBB5_68:                               # %.preheader.preheader
	xorl	%eax, %eax
.LBB5_69:                               # %.preheader
                                        # =>This Inner Loop Header: Depth=1
	cmpq	%rax, %rbx
	je	.LBB5_70
# %bb.71:                               #   in Loop: Header=BB5_69 Depth=1
	movl	(%r15,%rax,4), %ecx
	leaq	1(%rax), %rsi
	cmpl	4(%r15,%rax,4), %ecx
	movq	%rsi, %rax
	jle	.LBB5_69
# %bb.72:                               # %.split.loop.exit.i279
	decl	%esi
	jmp	.LBB5_73
.LBB5_70:
	movl	$-1, %esi
.LBB5_73:                               # %_Z10verif_triePii.exit281
	movl	$.L.str.3, %edi
                                        # kill: def $esi killed $esi killed $rsi
	xorl	%eax, %eax
	callq	printf
.LBB5_74:
	movq	-264(%rbp), %rdi
	callq	hipFree
	movq	-128(%rbp), %rdi
	callq	hipFree
	movq	-120(%rbp), %rdi
	callq	hipFree
	cmpl	$1024, -56(%rbp)                # 4-byte Folded Reload
                                        # imm = 0x400
	jl	.LBB5_77
# %bb.75:                               # %.lr.ph363.preheader
	xorl	%ebx, %ebx
.LBB5_76:                               # %.lr.ph363
                                        # =>This Inner Loop Header: Depth=1
	movq	(%r12,%rbx,8), %rdi
	callq	free
	incq	%rbx
	cmpq	%rbx, %r14
	jne	.LBB5_76
.LBB5_77:                               # %._crit_edge364
	movq	%r15, %rdi
	callq	free
	movq	%r12, %rdi
	callq	free
	movq	-160(%rbp), %rdi                # 8-byte Reload
	callq	free
	movq	-248(%rbp), %rsp                # 8-byte Reload
	xorl	%eax, %eax
	leaq	-40(%rbp), %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	.cfi_def_cfa %rsp, 8
	retq
.Lfunc_end5:
	.size	main, .Lfunc_end5-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB6_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB6_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z17small_sortManagerPiiiii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z28small_sortManager_extraSlicePiiiiiii, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z15sortManager_GPUPiS_S_S_iii, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end6:
	.size	__hip_module_ctor, .Lfunc_end6-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB7_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB7_2:
	retq
.Lfunc_end7:
	.size	__hip_module_dtor, .Lfunc_end7-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z17small_sortManagerPiiiii,@object # @_Z17small_sortManagerPiiiii
	.section	.rodata,"a",@progbits
	.globl	_Z17small_sortManagerPiiiii
	.p2align	3, 0x0
_Z17small_sortManagerPiiiii:
	.quad	_Z32__device_stub__small_sortManagerPiiiii
	.size	_Z17small_sortManagerPiiiii, 8

	.type	_Z28small_sortManager_extraSlicePiiiiiii,@object # @_Z28small_sortManager_extraSlicePiiiiiii
	.globl	_Z28small_sortManager_extraSlicePiiiiiii
	.p2align	3, 0x0
_Z28small_sortManager_extraSlicePiiiiiii:
	.quad	_Z43__device_stub__small_sortManager_extraSlicePiiiiiii
	.size	_Z28small_sortManager_extraSlicePiiiiiii, 8

	.type	_Z15sortManager_GPUPiS_S_S_iii,@object # @_Z15sortManager_GPUPiS_S_S_iii
	.globl	_Z15sortManager_GPUPiS_S_S_iii
	.p2align	3, 0x0
_Z15sortManager_GPUPiS_S_S_iii:
	.quad	_Z30__device_stub__sortManager_GPUPiS_S_S_iii
	.size	_Z15sortManager_GPUPiS_S_S_iii, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"--s"
	.size	.L.str, 4

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"mergeBatches Taille_M: %d, nbthreads: %d, numblocks: %d, Temps: %.5f, verif: %d\n"
	.size	.L.str.1, 81

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"ok tableau trie"
	.size	.L.str.2, 16

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"KO recommencer %d "
	.size	.L.str.3, 19

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z17small_sortManagerPiiiii"
	.size	.L__unnamed_1, 28

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z28small_sortManager_extraSlicePiiiiiii"
	.size	.L__unnamed_2, 41

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z15sortManager_GPUPiS_S_S_iii"
	.size	.L__unnamed_3, 31

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z32__device_stub__small_sortManagerPiiiii
	.addrsig_sym _Z43__device_stub__small_sortManager_extraSlicePiiiiiii
	.addrsig_sym _Z30__device_stub__sortManager_GPUPiS_S_S_iii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z17small_sortManagerPiiiii
	.addrsig_sym _Z28small_sortManager_extraSlicePiiiiiii
	.addrsig_sym _Z15sortManager_GPUPiS_S_S_iii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z17small_sortManagerPiiiii ; -- Begin function _Z17small_sortManagerPiiiii
	.globl	_Z17small_sortManagerPiiiii
	.p2align	8
	.type	_Z17small_sortManagerPiiiii,@function
_Z17small_sortManagerPiiiii:            ; @_Z17small_sortManagerPiiiii
; %bb.0:
	s_load_b128 s[4:7], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_add_i32 s2, s7, s6
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_max_u32 s0, s6, s2
	v_cmp_gt_u32_e32 vcc_lo, s0, v0
	s_and_saveexec_b32 s0, vcc_lo
	s_cbranch_execz .LBB0_2
; %bb.1:                                ; %.sink.split
	v_mad_u64_u32 v[1:2], null, s2, s15, v[0:1]
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s4, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
	global_load_b32 v1, v[1:2], off
	v_lshlrev_b32_e32 v2, 2, v0
	s_waitcnt vmcnt(0)
	ds_store_b32 v2, v1
.LBB0_2:
	s_or_b32 exec_lo, exec_lo, s0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_i32_e64 s2, v0
	s_cbranch_execz .LBB0_26
; %bb.3:
	v_subrev_nc_u32_e32 v1, s6, v0
	v_cmp_lt_i32_e32 vcc_lo, s6, v0
	v_min_i32_e32 v7, s6, v0
	s_lshl_b32 s3, s6, 2
	s_mov_b32 s9, 0
	s_add_i32 s10, s3, -4
	v_cndmask_b32_e32 v2, 0, v1, vcc_lo
                                        ; implicit-def: $sgpr8
	s_delay_alu instid0(VALU_DEP_1)
	v_mov_b32_e32 v1, v2
.LBB0_4:                                ; %.outer
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_5 Depth 2
	v_mov_b32_e32 v5, v7
	s_mov_b32 s11, 0
                                        ; implicit-def: $sgpr17
                                        ; implicit-def: $sgpr14
                                        ; implicit-def: $sgpr12
                                        ; implicit-def: $sgpr16
                                        ; implicit-def: $sgpr13
.LBB0_5:                                ;   Parent Loop BB0_4 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v3, v5, v2
	s_or_b32 s13, s13, exec_lo
	s_and_not1_b32 s16, s16, exec_lo
	s_or_b32 s12, s12, exec_lo
                                        ; implicit-def: $vgpr6
	v_sub_nc_u32_e32 v4, 0, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_max_i32_e32 v3, v3, v4
	v_lshrrev_b32_e32 v7, 1, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v4, v5, v7
	v_add_nc_u32_e32 v3, v7, v1
	v_cmp_lt_i32_e32 vcc_lo, -1, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_ge_i32_e64 s0, s7, v3
	s_and_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s18, s0
	s_cbranch_execz .LBB0_15
; %bb.6:                                ;   in Loop: Header=BB0_5 Depth=2
	v_cmp_eq_u32_e32 vcc_lo, s6, v4
	v_cmp_eq_u32_e64 s0, 0, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s1, vcc_lo, s0
	s_xor_b32 s19, s1, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s0, s19
	s_cbranch_execz .LBB0_8
; %bb.7:                                ;   in Loop: Header=BB0_5 Depth=2
	v_lshlrev_b32_e32 v6, 2, v4
	v_lshl_add_u32 v8, v3, 2, s10
	s_and_not1_b32 s1, s1, exec_lo
	ds_load_b32 v6, v6
	ds_load_b32 v8, v8
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_i32_e32 vcc_lo, v6, v8
	s_and_b32 s19, vcc_lo, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s1, s1, s19
.LBB0_8:                                ; %Flow56
                                        ;   in Loop: Header=BB0_5 Depth=2
	s_or_b32 exec_lo, exec_lo, s0
	s_mov_b32 s0, -1
	s_mov_b32 s21, -1
                                        ; implicit-def: $sgpr20
                                        ; implicit-def: $vgpr6
	s_and_saveexec_b32 s19, s1
	s_cbranch_execz .LBB0_14
; %bb.9:                                ;   in Loop: Header=BB0_5 Depth=2
	v_cmp_ne_u32_e64 s0, s7, v3
	v_cmp_ne_u32_e64 s1, v5, v7
	v_cmp_eq_u32_e32 vcc_lo, s7, v3
                                        ; implicit-def: $vgpr6
	s_delay_alu instid0(VALU_DEP_2)
	s_and_b32 s20, s1, s0
	s_mov_b32 s0, -1
	s_and_saveexec_b32 s1, s20
	s_cbranch_execz .LBB0_13
; %bb.10:                               ;   in Loop: Header=BB0_5 Depth=2
	v_add_nc_u32_e32 v6, -1, v4
	v_lshl_add_u32 v8, v3, 2, s3
	s_mov_b32 s20, -1
	s_mov_b32 s21, exec_lo
	s_delay_alu instid0(VALU_DEP_2)
	v_lshlrev_b32_e32 v7, 2, v6
	ds_load_b32 v7, v7
	ds_load_b32 v8, v8
	s_waitcnt lgkmcnt(0)
	v_cmpx_gt_i32_e64 v7, v8
; %bb.11:                               ;   in Loop: Header=BB0_5 Depth=2
	v_add_nc_u32_e32 v1, 1, v3
	s_xor_b32 s20, exec_lo, -1
                                        ; implicit-def: $vgpr5
                                        ; implicit-def: $vgpr4
                                        ; implicit-def: $vgpr3
; %bb.12:                               ; %Flow59
                                        ;   in Loop: Header=BB0_5 Depth=2
	s_or_b32 exec_lo, exec_lo, s21
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, vcc_lo, exec_lo
	s_or_not1_b32 s0, s20, exec_lo
.LBB0_13:                               ; %Flow58
                                        ;   in Loop: Header=BB0_5 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s21, exec_lo, -1
	s_and_b32 s20, vcc_lo, exec_lo
	s_or_not1_b32 s0, s0, exec_lo
.LBB0_14:                               ; %Flow57
                                        ;   in Loop: Header=BB0_5 Depth=2
	s_or_b32 exec_lo, exec_lo, s19
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 s1, s13, exec_lo
	s_and_b32 s13, s21, exec_lo
	s_and_not1_b32 s12, s12, exec_lo
	s_or_b32 s13, s1, s13
	s_and_not1_b32 s1, s16, exec_lo
	s_and_b32 s16, s20, exec_lo
	s_and_b32 s0, s0, exec_lo
	s_or_b32 s16, s1, s16
	s_or_b32 s12, s12, s0
.LBB0_15:                               ; %Flow55
                                        ;   in Loop: Header=BB0_5 Depth=2
	s_or_b32 exec_lo, exec_lo, s18
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s0, exec_lo, s12
	v_mov_b32_e32 v7, v5
	s_or_b32 s11, s0, s11
	v_mov_b32_e32 v5, v6
	s_and_not1_b32 s0, s14, exec_lo
	s_and_b32 s1, s13, exec_lo
	s_and_not1_b32 s17, s17, exec_lo
	s_and_b32 s18, s16, exec_lo
	s_or_b32 s14, s0, s1
	s_or_b32 s17, s17, s18
	s_and_not1_b32 exec_lo, exec_lo, s11
	s_cbranch_execnz .LBB0_5
; %bb.16:                               ; %loop.exit.guard
                                        ;   in Loop: Header=BB0_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s11
	s_mov_b32 s1, -1
	s_xor_b32 s0, s17, -1
                                        ; implicit-def: $vgpr2
	s_and_saveexec_b32 s11, s14
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s11, exec_lo, s11
; %bb.17:                               ;   in Loop: Header=BB0_4 Depth=1
	v_add_nc_u32_e32 v2, 1, v4
	s_xor_b32 s1, exec_lo, -1
; %bb.18:                               ; %Flow60
                                        ;   in Loop: Header=BB0_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s11
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s1, exec_lo, s1
	s_or_b32 s9, s1, s9
	s_and_not1_b32 s1, s8, exec_lo
	s_and_b32 s0, s0, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s8, s1, s0
	s_and_not1_b32 exec_lo, exec_lo, s9
	s_cbranch_execnz .LBB0_4
; %bb.19:
	s_or_b32 exec_lo, exec_lo, s9
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
                                        ; implicit-def: $vgpr1
	v_cmpx_le_i32_e64 s6, v4
	s_xor_b32 s0, exec_lo, s0
	s_cbranch_execz .LBB0_21
; %bb.20:                               ; %._crit_edge.i
	v_lshl_add_u32 v1, v3, 2, s3
	ds_load_b32 v1, v1
.LBB0_21:                               ; %Flow54
	s_and_not1_saveexec_b32 s0, s0
	s_cbranch_execz .LBB0_25
; %bb.22:
	s_waitcnt lgkmcnt(0)
	v_lshlrev_b32_e32 v1, 2, v4
	ds_load_b32 v1, v1
	s_and_saveexec_b32 s1, s8
	s_cbranch_execz .LBB0_24
; %bb.23:
	v_lshl_add_u32 v2, v3, 2, s3
	ds_load_b32 v2, v2
	s_waitcnt lgkmcnt(0)
	v_min_i32_e32 v1, v1, v2
.LBB0_24:                               ; %Flow
	s_or_b32 exec_lo, exec_lo, s1
.LBB0_25:                               ; %.sink.split.i
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_or_b32 exec_lo, exec_lo, s0
	s_waitcnt lgkmcnt(0)
	v_mad_u64_u32 v[2:3], null, s2, s15, v[0:1]
	v_mov_b32_e32 v3, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	v_add_co_u32 v2, vcc_lo, s4, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
	global_store_b32 v[2:3], v1, off
.LBB0_26:                               ; %_Z17mergeSmallBatch_kPiS_S_iiii.exit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z17small_sortManagerPiiiii
		.amdhsa_group_segment_fixed_size 4096
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 24
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 9
		.amdhsa_next_free_sgpr 22
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z17small_sortManagerPiiiii, .Lfunc_end0-_Z17small_sortManagerPiiiii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 868
; NumSgprs: 24
; NumVgprs: 9
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 4096 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 24
; NumVGPRsForWavesPerEU: 9
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z28small_sortManager_extraSlicePiiiiiii ; -- Begin function _Z28small_sortManager_extraSlicePiiiiiii
	.globl	_Z28small_sortManager_extraSlicePiiiiiii
	.p2align	8
	.type	_Z28small_sortManager_extraSlicePiiiiiii,@function
_Z28small_sortManager_extraSlicePiiiiiii: ; @_Z28small_sortManager_extraSlicePiiiiiii
; %bb.0:
	s_clause 0x2
	s_load_b128 s[4:7], s[0:1], 0x8
	s_load_b32 s10, s[0:1], 0x1c
	s_load_b64 s[8:9], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_add_i32 s3, s5, s4
	s_cmp_lg_u32 s15, s10
	s_cselect_b32 s1, -1, 0
	s_cmp_eq_u32 s15, s10
	s_cselect_b32 s0, -1, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, s0, exec_lo
	s_cselect_b32 s2, s6, s4
	s_lshl_b32 s11, s2, 2
	s_mov_b32 s2, exec_lo
	v_cmpx_le_u32_e64 s4, v0
	s_xor_b32 s2, exec_lo, s2
	s_cbranch_execz .LBB1_4
; %bb.1:                                ; %.critedge
	s_mov_b32 s12, exec_lo
	v_cmpx_gt_u32_e64 s3, v0
	s_cbranch_execz .LBB1_3
; %bb.2:
	v_mad_u64_u32 v[1:2], null, s3, s15, v[0:1]
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s8, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v2, vcc_lo, s9, v2, vcc_lo
	global_load_b32 v1, v[1:2], off
	v_subrev_nc_u32_e32 v2, s4, v0
	v_lshl_add_u32 v2, v2, 2, s11
	s_waitcnt vmcnt(0)
	ds_store_b32 v2, v1
.LBB1_3:                                ; %Flow252
	s_or_b32 exec_lo, exec_lo, s12
.LBB1_4:                                ; %Flow253
	s_and_not1_saveexec_b32 s2, s2
	s_cbranch_execz .LBB1_6
; %bb.5:
	v_mad_u64_u32 v[1:2], null, s3, s15, v[0:1]
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s8, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, s9, v2, vcc_lo
	global_load_b32 v1, v[1:2], off
	v_lshlrev_b32_e32 v2, 2, v0
	s_waitcnt vmcnt(0)
	ds_store_b32 v2, v1
.LBB1_6:
	s_or_b32 exec_lo, exec_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccnz .LBB1_12
; %bb.7:
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e64 s6, v0
	s_cbranch_execz .LBB1_9
; %bb.8:
	v_mad_u64_u32 v[1:2], null, s3, s10, v[0:1]
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s8, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, s9, v2, vcc_lo
	global_load_b32 v1, v[1:2], off
	v_lshlrev_b32_e32 v2, 2, v0
	s_waitcnt vmcnt(0)
	ds_store_b32 v2, v1
.LBB1_9:
	s_or_b32 exec_lo, exec_lo, s0
	s_add_i32 s0, s7, s6
	v_cmp_le_u32_e32 vcc_lo, s6, v0
	v_cmp_gt_u32_e64 s0, s0, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, vcc_lo, s0
	s_and_saveexec_b32 s0, s2
	s_cbranch_execz .LBB1_11
; %bb.10:
	v_mad_u64_u32 v[1:2], null, s3, s10, v[0:1]
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s8, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v2, vcc_lo, s9, v2, vcc_lo
	global_load_b32 v1, v[1:2], off
	v_subrev_nc_u32_e32 v2, s6, v0
	v_lshl_add_u32 v2, v2, 2, s11
	s_waitcnt vmcnt(0)
	ds_store_b32 v2, v1
.LBB1_11:                               ; %Flow250
	s_or_b32 exec_lo, exec_lo, s0
.LBB1_12:                               ; %.critedge115
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s1
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_vccz .LBB1_38
; %bb.13:
	s_mov_b32 s2, 0
	s_mov_b32 s12, 0
	s_mov_b32 s13, exec_lo
                                        ; implicit-def: $vgpr1
                                        ; implicit-def: $vgpr2
	v_cmpx_gt_i32_e64 s3, v0
	s_cbranch_execz .LBB1_37
; %bb.14:
	v_subrev_nc_u32_e32 v1, s4, v0
	v_cmp_lt_i32_e32 vcc_lo, s4, v0
	v_min_i32_e32 v7, s4, v0
	s_mov_b32 s14, 0
	s_add_i32 s16, s11, -4
                                        ; implicit-def: $sgpr12
	v_cndmask_b32_e32 v2, 0, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_mov_b32_e32 v1, v2
.LBB1_15:                               ; %.outer156
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB1_16 Depth 2
	v_mov_b32_e32 v5, v7
	s_mov_b32 s17, 0
                                        ; implicit-def: $sgpr22
                                        ; implicit-def: $sgpr20
                                        ; implicit-def: $sgpr18
                                        ; implicit-def: $sgpr21
                                        ; implicit-def: $sgpr19
.LBB1_16:                               ;   Parent Loop BB1_15 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v3, v5, v2
	s_or_b32 s19, s19, exec_lo
	s_and_not1_b32 s21, s21, exec_lo
	s_or_b32 s18, s18, exec_lo
                                        ; implicit-def: $vgpr6
	v_sub_nc_u32_e32 v4, 0, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_max_i32_e32 v3, v3, v4
	v_lshrrev_b32_e32 v7, 1, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v4, v5, v7
	v_add_nc_u32_e32 v3, v7, v1
	v_cmp_lt_i32_e32 vcc_lo, -1, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_ge_i32_e64 s0, s5, v3
	s_and_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s23, s0
	s_cbranch_execz .LBB1_26
; %bb.17:                               ;   in Loop: Header=BB1_16 Depth=2
	v_cmp_eq_u32_e32 vcc_lo, s4, v4
	v_cmp_eq_u32_e64 s0, 0, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s1, vcc_lo, s0
	s_xor_b32 s24, s1, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s0, s24
	s_cbranch_execz .LBB1_19
; %bb.18:                               ;   in Loop: Header=BB1_16 Depth=2
	v_lshlrev_b32_e32 v6, 2, v4
	v_lshl_add_u32 v8, v3, 2, s16
	s_and_not1_b32 s1, s1, exec_lo
	ds_load_b32 v6, v6
	ds_load_b32 v8, v8
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_i32_e32 vcc_lo, v6, v8
	s_and_b32 s24, vcc_lo, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s1, s1, s24
.LBB1_19:                               ; %Flow219
                                        ;   in Loop: Header=BB1_16 Depth=2
	s_or_b32 exec_lo, exec_lo, s0
	s_mov_b32 s0, -1
	s_mov_b32 s26, -1
                                        ; implicit-def: $sgpr25
                                        ; implicit-def: $vgpr6
	s_and_saveexec_b32 s24, s1
	s_cbranch_execz .LBB1_25
; %bb.20:                               ;   in Loop: Header=BB1_16 Depth=2
	v_cmp_ne_u32_e64 s0, s5, v3
	v_cmp_ne_u32_e64 s1, v5, v7
	v_cmp_eq_u32_e32 vcc_lo, s5, v3
                                        ; implicit-def: $vgpr6
	s_delay_alu instid0(VALU_DEP_2)
	s_and_b32 s25, s1, s0
	s_mov_b32 s0, -1
	s_and_saveexec_b32 s1, s25
	s_cbranch_execz .LBB1_24
; %bb.21:                               ;   in Loop: Header=BB1_16 Depth=2
	v_add_nc_u32_e32 v6, -1, v4
	v_lshl_add_u32 v8, v3, 2, s11
	s_mov_b32 s25, -1
	s_mov_b32 s26, exec_lo
	s_delay_alu instid0(VALU_DEP_2)
	v_lshlrev_b32_e32 v7, 2, v6
	ds_load_b32 v7, v7
	ds_load_b32 v8, v8
	s_waitcnt lgkmcnt(0)
	v_cmpx_gt_i32_e64 v7, v8
; %bb.22:                               ;   in Loop: Header=BB1_16 Depth=2
	v_add_nc_u32_e32 v1, 1, v3
	s_xor_b32 s25, exec_lo, -1
                                        ; implicit-def: $vgpr5
                                        ; implicit-def: $vgpr4
                                        ; implicit-def: $vgpr3
; %bb.23:                               ; %Flow222
                                        ;   in Loop: Header=BB1_16 Depth=2
	s_or_b32 exec_lo, exec_lo, s26
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, vcc_lo, exec_lo
	s_or_not1_b32 s0, s25, exec_lo
.LBB1_24:                               ; %Flow221
                                        ;   in Loop: Header=BB1_16 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s26, exec_lo, -1
	s_and_b32 s25, vcc_lo, exec_lo
	s_or_not1_b32 s0, s0, exec_lo
.LBB1_25:                               ; %Flow220
                                        ;   in Loop: Header=BB1_16 Depth=2
	s_or_b32 exec_lo, exec_lo, s24
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 s1, s19, exec_lo
	s_and_b32 s19, s26, exec_lo
	s_and_not1_b32 s18, s18, exec_lo
	s_or_b32 s19, s1, s19
	s_and_not1_b32 s1, s21, exec_lo
	s_and_b32 s21, s25, exec_lo
	s_and_b32 s0, s0, exec_lo
	s_or_b32 s21, s1, s21
	s_or_b32 s18, s18, s0
.LBB1_26:                               ; %Flow218
                                        ;   in Loop: Header=BB1_16 Depth=2
	s_or_b32 exec_lo, exec_lo, s23
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s0, exec_lo, s18
	v_mov_b32_e32 v7, v5
	s_or_b32 s17, s0, s17
	v_mov_b32_e32 v5, v6
	s_and_not1_b32 s0, s20, exec_lo
	s_and_b32 s1, s19, exec_lo
	s_and_not1_b32 s22, s22, exec_lo
	s_and_b32 s23, s21, exec_lo
	s_or_b32 s20, s0, s1
	s_or_b32 s22, s22, s23
	s_and_not1_b32 exec_lo, exec_lo, s17
	s_cbranch_execnz .LBB1_16
; %bb.27:                               ; %loop.exit.guard
                                        ;   in Loop: Header=BB1_15 Depth=1
	s_or_b32 exec_lo, exec_lo, s17
	s_mov_b32 s1, -1
	s_xor_b32 s0, s22, -1
                                        ; implicit-def: $vgpr2
	s_and_saveexec_b32 s17, s20
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s17, exec_lo, s17
; %bb.28:                               ;   in Loop: Header=BB1_15 Depth=1
	v_add_nc_u32_e32 v2, 1, v4
	s_xor_b32 s1, exec_lo, -1
; %bb.29:                               ; %Flow223
                                        ;   in Loop: Header=BB1_15 Depth=1
	s_or_b32 exec_lo, exec_lo, s17
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s1, exec_lo, s1
	s_or_b32 s14, s1, s14
	s_and_not1_b32 s1, s12, exec_lo
	s_and_b32 s0, s0, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s12, s1, s0
	s_and_not1_b32 exec_lo, exec_lo, s14
	s_cbranch_execnz .LBB1_15
; %bb.30:
	s_or_b32 exec_lo, exec_lo, s14
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
                                        ; implicit-def: $vgpr1
	v_cmpx_le_i32_e64 s4, v4
	s_xor_b32 s0, exec_lo, s0
	s_cbranch_execz .LBB1_32
; %bb.31:                               ; %._crit_edge.i103
	v_lshl_add_u32 v1, v3, 2, s11
	ds_load_b32 v1, v1
.LBB1_32:                               ; %Flow216
	s_or_saveexec_b32 s0, s0
	v_mov_b32_e32 v2, s15
	s_xor_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB1_36
; %bb.33:
	s_waitcnt lgkmcnt(0)
	v_lshlrev_b32_e32 v1, 2, v4
	ds_load_b32 v1, v1
	s_and_saveexec_b32 s1, s12
	s_cbranch_execz .LBB1_35
; %bb.34:
	v_lshl_add_u32 v2, v3, 2, s11
	ds_load_b32 v2, v2
	s_waitcnt lgkmcnt(0)
	v_min_i32_e32 v1, v1, v2
.LBB1_35:                               ; %Flow
	s_or_b32 exec_lo, exec_lo, s1
	v_mov_b32_e32 v2, s15
.LBB1_36:                               ; %Flow217
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s12, exec_lo
.LBB1_37:                               ; %Flow244
	s_or_b32 exec_lo, exec_lo, s13
	s_branch .LBB1_39
.LBB1_38:
	s_mov_b32 s2, -1
	s_mov_b32 s12, 0
                                        ; implicit-def: $vgpr1
                                        ; implicit-def: $vgpr2
.LBB1_39:                               ; %Flow243
	s_and_b32 vcc_lo, exec_lo, s2
	s_cbranch_vccz .LBB1_93
; %bb.40:
	s_add_i32 s0, s7, s6
	s_cmp_ge_i32 s6, s7
	v_cmp_gt_i32_e64 s0, s0, v0
	s_cbranch_scc0 .LBB1_66
; %bb.41:
                                        ; implicit-def: $vgpr1
                                        ; implicit-def: $vgpr2
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s4, s0
	s_cbranch_execz .LBB1_65
; %bb.42:
	s_waitcnt lgkmcnt(0)
	v_subrev_nc_u32_e32 v1, s6, v0
	v_cmp_lt_i32_e32 vcc_lo, s6, v0
	v_min_i32_e32 v7, s6, v0
	s_mov_b32 s13, 0
	s_add_i32 s14, s11, -4
                                        ; implicit-def: $sgpr5
	v_cndmask_b32_e32 v2, 0, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_mov_b32_e32 v1, v2
.LBB1_43:                               ; %.outer150
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB1_44 Depth 2
	v_mov_b32_e32 v5, v7
	s_mov_b32 s15, 0
                                        ; implicit-def: $sgpr20
                                        ; implicit-def: $sgpr18
                                        ; implicit-def: $sgpr16
                                        ; implicit-def: $sgpr19
                                        ; implicit-def: $sgpr17
.LBB1_44:                               ;   Parent Loop BB1_43 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v3, v5, v2
	s_or_b32 s17, s17, exec_lo
	s_and_not1_b32 s19, s19, exec_lo
	s_or_b32 s16, s16, exec_lo
                                        ; implicit-def: $vgpr6
	v_sub_nc_u32_e32 v4, 0, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_max_i32_e32 v3, v3, v4
	v_lshrrev_b32_e32 v7, 1, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v4, v5, v7
	v_add_nc_u32_e32 v3, v7, v1
	v_cmp_lt_i32_e32 vcc_lo, -1, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_ge_i32_e64 s1, s7, v3
	s_and_b32 s1, vcc_lo, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s21, s1
	s_cbranch_execz .LBB1_54
; %bb.45:                               ;   in Loop: Header=BB1_44 Depth=2
	v_cmp_eq_u32_e32 vcc_lo, s6, v4
	v_cmp_eq_u32_e64 s1, 0, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s2, vcc_lo, s1
	s_xor_b32 s22, s2, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s1, s22
	s_cbranch_execz .LBB1_47
; %bb.46:                               ;   in Loop: Header=BB1_44 Depth=2
	v_lshlrev_b32_e32 v6, 2, v4
	v_lshl_add_u32 v8, v3, 2, s14
	s_and_not1_b32 s2, s2, exec_lo
	ds_load_b32 v6, v6
	ds_load_b32 v8, v8
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_i32_e32 vcc_lo, v6, v8
	s_and_b32 s22, vcc_lo, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s2, s2, s22
.LBB1_47:                               ; %Flow228
                                        ;   in Loop: Header=BB1_44 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	s_mov_b32 s1, -1
	s_mov_b32 s24, -1
                                        ; implicit-def: $sgpr23
                                        ; implicit-def: $vgpr6
	s_and_saveexec_b32 s22, s2
	s_cbranch_execz .LBB1_53
; %bb.48:                               ;   in Loop: Header=BB1_44 Depth=2
	v_cmp_ne_u32_e64 s1, s7, v3
	v_cmp_ne_u32_e64 s2, v5, v7
	v_cmp_eq_u32_e32 vcc_lo, s7, v3
                                        ; implicit-def: $vgpr6
	s_delay_alu instid0(VALU_DEP_2)
	s_and_b32 s23, s2, s1
	s_mov_b32 s1, -1
	s_and_saveexec_b32 s2, s23
	s_cbranch_execz .LBB1_52
; %bb.49:                               ;   in Loop: Header=BB1_44 Depth=2
	v_add_nc_u32_e32 v6, -1, v4
	v_lshl_add_u32 v8, v3, 2, s11
	s_mov_b32 s23, -1
	s_mov_b32 s24, exec_lo
	s_delay_alu instid0(VALU_DEP_2)
	v_lshlrev_b32_e32 v7, 2, v6
	ds_load_b32 v7, v7
	ds_load_b32 v8, v8
	s_waitcnt lgkmcnt(0)
	v_cmpx_gt_i32_e64 v7, v8
; %bb.50:                               ;   in Loop: Header=BB1_44 Depth=2
	v_add_nc_u32_e32 v1, 1, v3
	s_xor_b32 s23, exec_lo, -1
                                        ; implicit-def: $vgpr5
                                        ; implicit-def: $vgpr4
                                        ; implicit-def: $vgpr3
; %bb.51:                               ; %Flow231
                                        ;   in Loop: Header=BB1_44 Depth=2
	s_or_b32 exec_lo, exec_lo, s24
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, vcc_lo, exec_lo
	s_or_not1_b32 s1, s23, exec_lo
.LBB1_52:                               ; %Flow230
                                        ;   in Loop: Header=BB1_44 Depth=2
	s_or_b32 exec_lo, exec_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s24, exec_lo, -1
	s_and_b32 s23, vcc_lo, exec_lo
	s_or_not1_b32 s1, s1, exec_lo
.LBB1_53:                               ; %Flow229
                                        ;   in Loop: Header=BB1_44 Depth=2
	s_or_b32 exec_lo, exec_lo, s22
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 s2, s17, exec_lo
	s_and_b32 s17, s24, exec_lo
	s_and_not1_b32 s16, s16, exec_lo
	s_or_b32 s17, s2, s17
	s_and_not1_b32 s2, s19, exec_lo
	s_and_b32 s19, s23, exec_lo
	s_and_b32 s1, s1, exec_lo
	s_or_b32 s19, s2, s19
	s_or_b32 s16, s16, s1
.LBB1_54:                               ; %Flow227
                                        ;   in Loop: Header=BB1_44 Depth=2
	s_or_b32 exec_lo, exec_lo, s21
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s1, exec_lo, s16
	v_mov_b32_e32 v7, v5
	s_or_b32 s15, s1, s15
	v_mov_b32_e32 v5, v6
	s_and_not1_b32 s1, s18, exec_lo
	s_and_b32 s2, s17, exec_lo
	s_and_not1_b32 s20, s20, exec_lo
	s_and_b32 s21, s19, exec_lo
	s_or_b32 s18, s1, s2
	s_or_b32 s20, s20, s21
	s_and_not1_b32 exec_lo, exec_lo, s15
	s_cbranch_execnz .LBB1_44
; %bb.55:                               ; %loop.exit.guard208
                                        ;   in Loop: Header=BB1_43 Depth=1
	s_or_b32 exec_lo, exec_lo, s15
	s_mov_b32 s2, -1
	s_xor_b32 s1, s20, -1
                                        ; implicit-def: $vgpr2
	s_and_saveexec_b32 s15, s18
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s15, exec_lo, s15
; %bb.56:                               ;   in Loop: Header=BB1_43 Depth=1
	v_add_nc_u32_e32 v2, 1, v4
	s_xor_b32 s2, exec_lo, -1
; %bb.57:                               ; %Flow232
                                        ;   in Loop: Header=BB1_43 Depth=1
	s_or_b32 exec_lo, exec_lo, s15
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, exec_lo, s2
	s_or_b32 s13, s2, s13
	s_and_not1_b32 s2, s5, exec_lo
	s_and_b32 s1, s1, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s5, s2, s1
	s_and_not1_b32 exec_lo, exec_lo, s13
	s_cbranch_execnz .LBB1_43
; %bb.58:
	s_or_b32 exec_lo, exec_lo, s13
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s1, exec_lo
                                        ; implicit-def: $vgpr1
	v_cmpx_le_i32_e64 s6, v4
	s_xor_b32 s1, exec_lo, s1
	s_cbranch_execz .LBB1_60
; %bb.59:                               ; %._crit_edge.i76
	v_lshl_add_u32 v1, v3, 2, s11
	ds_load_b32 v1, v1
.LBB1_60:                               ; %Flow225
	s_or_saveexec_b32 s1, s1
	v_mov_b32_e32 v2, s10
	s_xor_b32 exec_lo, exec_lo, s1
	s_cbranch_execz .LBB1_64
; %bb.61:
	s_waitcnt lgkmcnt(0)
	v_lshlrev_b32_e32 v1, 2, v4
	ds_load_b32 v1, v1
	s_and_saveexec_b32 s2, s5
	s_cbranch_execz .LBB1_63
; %bb.62:
	v_lshl_add_u32 v2, v3, 2, s11
	ds_load_b32 v2, v2
	s_waitcnt lgkmcnt(0)
	v_min_i32_e32 v1, v1, v2
.LBB1_63:                               ; %Flow224
	s_or_b32 exec_lo, exec_lo, s2
	v_mov_b32_e32 v2, s10
.LBB1_64:                               ; %Flow226
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s12, s12, exec_lo
.LBB1_65:                               ; %Flow247
	s_or_b32 exec_lo, exec_lo, s4
	s_mov_b32 s1, 0
	s_branch .LBB1_67
.LBB1_66:
	s_mov_b32 s1, -1
                                        ; implicit-def: $vgpr1
                                        ; implicit-def: $vgpr2
.LBB1_67:                               ; %Flow246
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccz .LBB1_93
; %bb.68:
                                        ; implicit-def: $vgpr1
                                        ; implicit-def: $vgpr2
	s_and_saveexec_b32 s2, s0
	s_cbranch_execz .LBB1_92
; %bb.69:
	s_waitcnt lgkmcnt(0)
	v_subrev_nc_u32_e32 v1, s7, v0
	v_cmp_lt_i32_e32 vcc_lo, s7, v0
	v_min_i32_e32 v7, s7, v0
	s_mov_b32 s5, 0
                                        ; implicit-def: $sgpr4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v2, 0, v1, vcc_lo
	v_mov_b32_e32 v1, v2
.LBB1_70:                               ; %.outer
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB1_71 Depth 2
	s_delay_alu instid0(VALU_DEP_3)
	v_mov_b32_e32 v5, v7
	s_mov_b32 s13, 0
                                        ; implicit-def: $sgpr18
                                        ; implicit-def: $sgpr16
                                        ; implicit-def: $sgpr14
                                        ; implicit-def: $sgpr17
                                        ; implicit-def: $sgpr15
.LBB1_71:                               ;   Parent Loop BB1_70 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v3, v5, v2
	s_or_b32 s15, s15, exec_lo
	s_and_not1_b32 s17, s17, exec_lo
	s_or_b32 s14, s14, exec_lo
                                        ; implicit-def: $vgpr6
	v_sub_nc_u32_e32 v4, 0, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_max_i32_e32 v3, v3, v4
	v_lshrrev_b32_e32 v7, 1, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v4, v5, v7
	v_add_nc_u32_e32 v3, v7, v1
	v_cmp_lt_i32_e32 vcc_lo, -1, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_ge_i32_e64 s0, s6, v3
	s_and_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s19, s0
	s_cbranch_execz .LBB1_81
; %bb.72:                               ;   in Loop: Header=BB1_71 Depth=2
	v_cmp_eq_u32_e32 vcc_lo, s7, v4
	v_cmp_eq_u32_e64 s0, 0, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s1, vcc_lo, s0
	s_xor_b32 s20, s1, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s0, s20
	s_cbranch_execz .LBB1_74
; %bb.73:                               ;   in Loop: Header=BB1_71 Depth=2
	v_lshl_add_u32 v6, v4, 2, s11
	v_lshl_add_u32 v8, v3, 2, -4
	s_and_not1_b32 s1, s1, exec_lo
	ds_load_b32 v6, v6
	ds_load_b32 v8, v8
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_i32_e32 vcc_lo, v6, v8
	s_and_b32 s20, vcc_lo, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s1, s1, s20
.LBB1_74:                               ; %Flow237
                                        ;   in Loop: Header=BB1_71 Depth=2
	s_or_b32 exec_lo, exec_lo, s0
	s_mov_b32 s0, -1
	s_mov_b32 s22, -1
                                        ; implicit-def: $sgpr21
                                        ; implicit-def: $vgpr6
	s_and_saveexec_b32 s20, s1
	s_cbranch_execz .LBB1_80
; %bb.75:                               ;   in Loop: Header=BB1_71 Depth=2
	v_cmp_ne_u32_e64 s0, s6, v3
	v_cmp_ne_u32_e64 s1, v5, v7
	v_cmp_eq_u32_e32 vcc_lo, s6, v3
                                        ; implicit-def: $vgpr6
	s_delay_alu instid0(VALU_DEP_2)
	s_and_b32 s21, s1, s0
	s_mov_b32 s0, -1
	s_and_saveexec_b32 s1, s21
	s_cbranch_execz .LBB1_79
; %bb.76:                               ;   in Loop: Header=BB1_71 Depth=2
	v_add_nc_u32_e32 v6, -1, v4
	v_lshlrev_b32_e32 v8, 2, v3
	s_mov_b32 s21, -1
	s_mov_b32 s22, exec_lo
	s_delay_alu instid0(VALU_DEP_2)
	v_lshl_add_u32 v7, v6, 2, s11
	ds_load_b32 v7, v7
	ds_load_b32 v8, v8
	s_waitcnt lgkmcnt(0)
	v_cmpx_gt_i32_e64 v7, v8
; %bb.77:                               ;   in Loop: Header=BB1_71 Depth=2
	v_add_nc_u32_e32 v1, 1, v3
	s_xor_b32 s21, exec_lo, -1
                                        ; implicit-def: $vgpr5
                                        ; implicit-def: $vgpr4
                                        ; implicit-def: $vgpr3
; %bb.78:                               ; %Flow240
                                        ;   in Loop: Header=BB1_71 Depth=2
	s_or_b32 exec_lo, exec_lo, s22
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, vcc_lo, exec_lo
	s_or_not1_b32 s0, s21, exec_lo
.LBB1_79:                               ; %Flow239
                                        ;   in Loop: Header=BB1_71 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s22, exec_lo, -1
	s_and_b32 s21, vcc_lo, exec_lo
	s_or_not1_b32 s0, s0, exec_lo
.LBB1_80:                               ; %Flow238
                                        ;   in Loop: Header=BB1_71 Depth=2
	s_or_b32 exec_lo, exec_lo, s20
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 s1, s15, exec_lo
	s_and_b32 s15, s22, exec_lo
	s_and_not1_b32 s14, s14, exec_lo
	s_or_b32 s15, s1, s15
	s_and_not1_b32 s1, s17, exec_lo
	s_and_b32 s17, s21, exec_lo
	s_and_b32 s0, s0, exec_lo
	s_or_b32 s17, s1, s17
	s_or_b32 s14, s14, s0
.LBB1_81:                               ; %Flow236
                                        ;   in Loop: Header=BB1_71 Depth=2
	s_or_b32 exec_lo, exec_lo, s19
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s0, exec_lo, s14
	v_mov_b32_e32 v7, v5
	s_or_b32 s13, s0, s13
	v_mov_b32_e32 v5, v6
	s_and_not1_b32 s0, s16, exec_lo
	s_and_b32 s1, s15, exec_lo
	s_and_not1_b32 s18, s18, exec_lo
	s_and_b32 s19, s17, exec_lo
	s_or_b32 s16, s0, s1
	s_or_b32 s18, s18, s19
	s_and_not1_b32 exec_lo, exec_lo, s13
	s_cbranch_execnz .LBB1_71
; %bb.82:                               ; %loop.exit.guard212
                                        ;   in Loop: Header=BB1_70 Depth=1
	s_or_b32 exec_lo, exec_lo, s13
	s_mov_b32 s1, -1
	s_xor_b32 s0, s18, -1
                                        ; implicit-def: $vgpr2
	s_and_saveexec_b32 s13, s16
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s13, exec_lo, s13
; %bb.83:                               ;   in Loop: Header=BB1_70 Depth=1
	v_add_nc_u32_e32 v2, 1, v4
	s_xor_b32 s1, exec_lo, -1
; %bb.84:                               ; %Flow241
                                        ;   in Loop: Header=BB1_70 Depth=1
	s_or_b32 exec_lo, exec_lo, s13
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s1, exec_lo, s1
	s_or_b32 s5, s1, s5
	s_and_not1_b32 s1, s4, exec_lo
	s_and_b32 s0, s0, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s4, s1, s0
	s_and_not1_b32 exec_lo, exec_lo, s5
	s_cbranch_execnz .LBB1_70
; %bb.85:
	s_or_b32 exec_lo, exec_lo, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
                                        ; implicit-def: $vgpr1
	v_cmpx_le_i32_e64 s7, v4
	s_xor_b32 s0, exec_lo, s0
	s_cbranch_execz .LBB1_87
; %bb.86:                               ; %._crit_edge.i
	v_lshlrev_b32_e32 v1, 2, v3
	ds_load_b32 v1, v1
.LBB1_87:                               ; %Flow234
	s_or_saveexec_b32 s0, s0
	v_mov_b32_e32 v2, s10
	s_xor_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB1_91
; %bb.88:
	s_waitcnt lgkmcnt(0)
	v_lshl_add_u32 v1, v4, 2, s11
	ds_load_b32 v1, v1
	s_and_saveexec_b32 s1, s4
	s_cbranch_execz .LBB1_90
; %bb.89:
	v_lshlrev_b32_e32 v2, 2, v3
	ds_load_b32 v2, v2
	s_waitcnt lgkmcnt(0)
	v_min_i32_e32 v1, v1, v2
.LBB1_90:                               ; %Flow233
	s_or_b32 exec_lo, exec_lo, s1
	v_mov_b32_e32 v2, s10
.LBB1_91:                               ; %Flow235
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s12, s12, exec_lo
.LBB1_92:                               ; %Flow249
	s_or_b32 exec_lo, exec_lo, s2
.LBB1_93:                               ; %Flow245
	s_and_saveexec_b32 s0, s12
	s_cbranch_execz .LBB1_95
; %bb.94:                               ; %_Z17mergeSmallBatch_kPiS_S_iiii.exit.sink.split
	s_waitcnt lgkmcnt(0)
	v_mad_u64_u32 v[3:4], null, s3, v2, v[0:1]
	v_mov_b32_e32 v4, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[3:4]
	v_add_co_u32 v2, vcc_lo, s8, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
	global_store_b32 v[2:3], v1, off
.LBB1_95:                               ; %_Z17mergeSmallBatch_kPiS_S_iiii.exit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z28small_sortManager_extraSlicePiiiiiii
		.amdhsa_group_segment_fixed_size 4096
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 32
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 9
		.amdhsa_next_free_sgpr 27
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z28small_sortManager_extraSlicePiiiiiii, .Lfunc_end1-_Z28small_sortManager_extraSlicePiiiiiii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 2704
; NumSgprs: 29
; NumVgprs: 9
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 4096 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 29
; NumVGPRsForWavesPerEU: 9
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z15sortManager_GPUPiS_S_S_iii ; -- Begin function _Z15sortManager_GPUPiS_S_S_iii
	.globl	_Z15sortManager_GPUPiS_S_S_iii
	.p2align	8
	.type	_Z15sortManager_GPUPiS_S_S_iii,@function
_Z15sortManager_GPUPiS_S_S_iii:         ; @_Z15sortManager_GPUPiS_S_S_iii
; %bb.0:
	s_clause 0x1
	s_load_b32 s12, s[0:1], 0x30
	s_load_b128 s[16:19], s[0:1], 0x20
	s_add_u32 s2, s0, 48
	s_addc_u32 s3, s1, 0
	s_waitcnt lgkmcnt(0)
	s_cmp_lt_u32 s15, s12
	s_cselect_b32 s4, 12, 18
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v1, s4
	s_mov_b32 s4, exec_lo
	global_load_u16 v1, v1, s[2:3]
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[29:30], null, s15, v1, v[0:1]
	v_cmpx_gt_i32_e64 s18, v29
	s_cbranch_execz .LBB2_235
; %bb.1:                                ; %.lr.ph.i
	s_load_b256 s[4:11], s[0:1], 0x0
	v_mul_lo_u32 v34, s12, v1
	v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v2, v29
	s_mov_b32 s21, 0
	s_waitcnt lgkmcnt(0)
	s_add_u32 s14, s6, -4
	s_addc_u32 s20, s7, -1
	s_ashr_i32 s19, s18, 31
	s_delay_alu instid0(SALU_CYCLE_1)
	s_lshl_b64 s[12:13], s[18:19], 2
.LBB2_2:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB2_3 Depth 2
                                        ;       Child Loop BB2_4 Depth 3
	v_subrev_nc_u32_e32 v0, s16, v2
	v_cmp_lt_i32_e32 vcc_lo, s16, v2
	v_min_i32_e32 v5, s16, v2
	s_mov_b32 s22, 0
                                        ; implicit-def: $sgpr19
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v8, 0, v0, vcc_lo
	v_mov_b32_e32 v3, v8
.LBB2_3:                                ; %.outer
                                        ;   Parent Loop BB2_2 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB2_4 Depth 3
	s_delay_alu instid0(VALU_DEP_3)
	v_mov_b32_e32 v9, v5
	s_mov_b32 s23, 0
                                        ; implicit-def: $sgpr28
                                        ; implicit-def: $sgpr26
                                        ; implicit-def: $sgpr24
                                        ; implicit-def: $sgpr27
                                        ; implicit-def: $sgpr25
.LBB2_4:                                ;   Parent Loop BB2_2 Depth=1
                                        ;     Parent Loop BB2_3 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v0, v9, v8
	s_or_b32 s25, s25, exec_lo
	s_and_not1_b32 s27, s27, exec_lo
	s_or_b32 s24, s24, exec_lo
	v_sub_nc_u32_e32 v4, 0, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_max_i32_e32 v0, v0, v4
	v_lshrrev_b32_e32 v0, 1, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v4, v9, v0
	v_add_nc_u32_e32 v6, v0, v3
	v_cmp_lt_i32_e32 vcc_lo, -1, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_ge_i32_e64 s0, s17, v6
	s_and_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s29, s0
	s_cbranch_execz .LBB2_14
; %bb.5:                                ;   in Loop: Header=BB2_4 Depth=3
	v_cmp_eq_u32_e32 vcc_lo, s16, v4
	v_cmp_eq_u32_e64 s0, 0, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s0, vcc_lo, s0
	s_xor_b32 s30, s0, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s1, s30
	s_cbranch_execz .LBB2_7
; %bb.6:                                ;   in Loop: Header=BB2_4 Depth=3
	v_mov_b32_e32 v5, v1
	v_ashrrev_i32_e32 v7, 31, v6
	s_and_not1_b32 s0, s0, exec_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[10:11], 2, v[4:5]
	v_lshlrev_b64 v[12:13], 2, v[6:7]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v10, vcc_lo, s4, v10
	v_add_co_ci_u32_e32 v11, vcc_lo, s5, v11, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v12, vcc_lo, s14, v12
	v_add_co_ci_u32_e32 v13, vcc_lo, s20, v13, vcc_lo
	global_load_b32 v5, v[10:11], off
	global_load_b32 v7, v[12:13], off
	s_waitcnt vmcnt(0)
	v_cmp_gt_i32_e32 vcc_lo, v5, v7
	s_and_b32 s30, vcc_lo, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s0, s0, s30
.LBB2_7:                                ; %Flow422
                                        ;   in Loop: Header=BB2_4 Depth=3
	s_or_b32 exec_lo, exec_lo, s1
	s_mov_b32 s1, -1
	s_mov_b32 s33, -1
                                        ; implicit-def: $sgpr31
	s_and_saveexec_b32 s30, s0
	s_cbranch_execz .LBB2_13
; %bb.8:                                ;   in Loop: Header=BB2_4 Depth=3
	v_cmp_ne_u32_e64 s0, s17, v6
	v_cmp_ne_u32_e64 s1, v9, v0
	v_cmp_eq_u32_e32 vcc_lo, s17, v6
	s_delay_alu instid0(VALU_DEP_2)
	s_and_b32 s31, s1, s0
	s_mov_b32 s0, -1
	s_and_saveexec_b32 s1, s31
	s_cbranch_execz .LBB2_12
; %bb.9:                                ;   in Loop: Header=BB2_4 Depth=3
	v_add_nc_u32_e32 v0, -1, v4
	v_ashrrev_i32_e32 v7, 31, v6
	s_mov_b32 s31, -1
	s_mov_b32 s33, exec_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[10:11], 2, v[0:1]
	v_lshlrev_b64 v[12:13], 2, v[6:7]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v10, s0, s4, v10
	v_add_co_ci_u32_e64 v11, s0, s5, v11, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v12, s0, s6, v12
	v_add_co_ci_u32_e64 v13, s0, s7, v13, s0
	global_load_b32 v5, v[10:11], off
	global_load_b32 v7, v[12:13], off
	s_waitcnt vmcnt(0)
	v_cmpx_gt_i32_e64 v5, v7
; %bb.10:                               ;   in Loop: Header=BB2_4 Depth=3
	v_add_nc_u32_e32 v3, 1, v6
	s_xor_b32 s31, exec_lo, -1
                                        ; implicit-def: $vgpr9
                                        ; implicit-def: $vgpr4
                                        ; implicit-def: $vgpr6
; %bb.11:                               ; %Flow425
                                        ;   in Loop: Header=BB2_4 Depth=3
	s_or_b32 exec_lo, exec_lo, s33
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, vcc_lo, exec_lo
	s_or_not1_b32 s0, s31, exec_lo
.LBB2_12:                               ; %Flow424
                                        ;   in Loop: Header=BB2_4 Depth=3
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s33, exec_lo, -1
	s_and_b32 s31, vcc_lo, exec_lo
	s_or_not1_b32 s1, s0, exec_lo
.LBB2_13:                               ; %Flow423
                                        ;   in Loop: Header=BB2_4 Depth=3
	s_or_b32 exec_lo, exec_lo, s30
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 s0, s25, exec_lo
	s_and_b32 s25, s33, exec_lo
	s_and_not1_b32 s24, s24, exec_lo
	s_or_b32 s25, s0, s25
	s_and_not1_b32 s0, s27, exec_lo
	s_and_b32 s27, s31, exec_lo
	s_and_b32 s1, s1, exec_lo
	s_or_b32 s27, s0, s27
	s_or_b32 s24, s24, s1
.LBB2_14:                               ; %Flow421
                                        ;   in Loop: Header=BB2_4 Depth=3
	s_or_b32 exec_lo, exec_lo, s29
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s0, exec_lo, s24
	v_mov_b32_e32 v5, v9
	s_or_b32 s23, s0, s23
	v_mov_b32_e32 v9, v0
	s_and_not1_b32 s0, s26, exec_lo
	s_and_b32 s1, s25, exec_lo
	s_and_not1_b32 s28, s28, exec_lo
	s_and_b32 s29, s27, exec_lo
	s_or_b32 s26, s0, s1
	s_or_b32 s28, s28, s29
	s_and_not1_b32 exec_lo, exec_lo, s23
	s_cbranch_execnz .LBB2_4
; %bb.15:                               ; %loop.exit.guard
                                        ;   in Loop: Header=BB2_3 Depth=2
	s_or_b32 exec_lo, exec_lo, s23
	s_mov_b32 s1, -1
	s_xor_b32 s0, s28, -1
                                        ; implicit-def: $vgpr8
	s_and_saveexec_b32 s23, s26
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s23, exec_lo, s23
; %bb.16:                               ;   in Loop: Header=BB2_3 Depth=2
	v_add_nc_u32_e32 v8, 1, v4
	s_xor_b32 s1, exec_lo, -1
; %bb.17:                               ; %Flow426
                                        ;   in Loop: Header=BB2_3 Depth=2
	s_or_b32 exec_lo, exec_lo, s23
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s1, exec_lo, s1
	s_or_b32 s22, s1, s22
	s_and_not1_b32 s1, s19, exec_lo
	s_and_b32 s0, s0, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s19, s1, s0
	s_and_not1_b32 exec_lo, exec_lo, s22
	s_cbranch_execnz .LBB2_3
; %bb.18:                               ;   in Loop: Header=BB2_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s22
	s_mov_b32 s1, -1
	s_mov_b32 s0, exec_lo
                                        ; implicit-def: $sgpr22
	v_cmpx_gt_i32_e64 s16, v4
	s_cbranch_execz .LBB2_22
; %bb.19:                               ;   in Loop: Header=BB2_2 Depth=1
	s_mov_b32 s23, 0
	s_and_saveexec_b32 s1, s19
	s_cbranch_execz .LBB2_21
; %bb.20:                               ;   in Loop: Header=BB2_2 Depth=1
	v_mov_b32_e32 v5, v1
	v_ashrrev_i32_e32 v7, 31, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[8:9], 2, v[4:5]
	v_lshlrev_b64 v[10:11], 2, v[6:7]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v7, vcc_lo, s4, v8
	v_add_co_ci_u32_e32 v8, vcc_lo, s5, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v9, vcc_lo, s6, v10
	v_add_co_ci_u32_e32 v10, vcc_lo, s7, v11, vcc_lo
	global_load_b32 v0, v[7:8], off
	global_load_b32 v3, v[9:10], off
	s_waitcnt vmcnt(0)
	v_cmp_gt_i32_e32 vcc_lo, v0, v3
	s_and_b32 s23, vcc_lo, exec_lo
.LBB2_21:                               ; %Flow420
                                        ;   in Loop: Header=BB2_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_mov_b32 s22, 1
	s_or_not1_b32 s1, s23, exec_lo
.LBB2_22:                               ; %Flow419
                                        ;   in Loop: Header=BB2_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	v_mov_b32_e32 v0, s22
	s_and_saveexec_b32 s0, s1
; %bb.23:                               ;   in Loop: Header=BB2_2 Depth=1
	v_mov_b32_e32 v0, 0
	v_mov_b32_e32 v4, v6
; %bb.24:                               ;   in Loop: Header=BB2_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	v_ashrrev_i32_e32 v3, 31, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[5:6], 2, v[2:3]
	v_add_nc_u32_e32 v2, v2, v34
	v_add_co_u32 v5, vcc_lo, s10, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v6, vcc_lo, s11, v6, vcc_lo
	v_cmp_le_i32_e32 vcc_lo, s18, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v7, s0, v5, s12
	v_add_co_ci_u32_e64 v8, s0, s13, v6, s0
	s_or_b32 s21, vcc_lo, s21
	s_clause 0x1
	global_store_b32 v[5:6], v0, off
	global_store_b32 v[7:8], v4, off
	s_and_not1_b32 exec_lo, exec_lo, s21
	s_cbranch_execnz .LBB2_2
; %bb.25:                               ; %.lr.ph.i16
	s_or_b32 exec_lo, exec_lo, s21
	v_mbcnt_lo_u32_b32 v35, -1, 0
	v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v5, 2
	v_mov_b32_e32 v6, 1
	v_mov_b32_e32 v0, 33
	s_mov_b32 s20, 0
	s_mov_b32 s19, 0
	s_mov_b32 s14, s20
.LBB2_26:                               ; %NodeBlock
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB2_34 Depth 2
                                        ;     Child Loop BB2_42 Depth 2
                                        ;     Child Loop BB2_48 Depth 2
                                        ;     Child Loop BB2_57 Depth 2
                                        ;     Child Loop BB2_60 Depth 2
                                        ;       Child Loop BB2_63 Depth 3
                                        ;       Child Loop BB2_71 Depth 3
                                        ;       Child Loop BB2_79 Depth 3
                                        ;       Child Loop BB2_87 Depth 3
                                        ;       Child Loop BB2_95 Depth 3
                                        ;       Child Loop BB2_103 Depth 3
                                        ;       Child Loop BB2_111 Depth 3
                                        ;       Child Loop BB2_119 Depth 3
                                        ;       Child Loop BB2_127 Depth 3
                                        ;       Child Loop BB2_133 Depth 3
                                        ;       Child Loop BB2_142 Depth 3
                                        ;     Child Loop BB2_150 Depth 2
                                        ;     Child Loop BB2_158 Depth 2
                                        ;     Child Loop BB2_164 Depth 2
                                        ;     Child Loop BB2_173 Depth 2
                                        ;     Child Loop BB2_178 Depth 2
                                        ;     Child Loop BB2_186 Depth 2
                                        ;     Child Loop BB2_192 Depth 2
                                        ;     Child Loop BB2_201 Depth 2
                                        ;     Child Loop BB2_205 Depth 2
                                        ;     Child Loop BB2_213 Depth 2
                                        ;     Child Loop BB2_219 Depth 2
                                        ;     Child Loop BB2_228 Depth 2
	v_ashrrev_i32_e32 v30, 31, v29
	s_mov_b32 s34, 0
	s_mov_b32 s0, 0
	s_mov_b32 s33, 0
	s_mov_b32 s1, exec_lo
	v_lshlrev_b64 v[30:31], 2, v[29:30]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v32, vcc_lo, s10, v30
	v_add_co_ci_u32_e32 v33, vcc_lo, s11, v31, vcc_lo
	global_load_b32 v1, v[32:33], off
	s_waitcnt vmcnt(0)
	v_cmpx_lt_i32_e32 0, v1
	s_xor_b32 s1, exec_lo, s1
; %bb.27:                               ; %LeafBlock303
                                        ;   in Loop: Header=BB2_26 Depth=1
	v_cmp_ne_u32_e32 vcc_lo, 1, v1
	s_mov_b32 s33, exec_lo
                                        ; implicit-def: $vgpr1
	s_and_b32 s0, vcc_lo, exec_lo
; %bb.28:                               ; %Flow413
                                        ;   in Loop: Header=BB2_26 Depth=1
	s_and_not1_saveexec_b32 s1, s1
; %bb.29:                               ; %LeafBlock
                                        ;   in Loop: Header=BB2_26 Depth=1
	v_cmp_ne_u32_e32 vcc_lo, 0, v1
	s_and_not1_b32 s0, s0, exec_lo
	s_mov_b32 s34, exec_lo
	s_and_b32 s16, vcc_lo, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s0, s0, s16
; %bb.30:                               ; %Flow414
                                        ;   in Loop: Header=BB2_26 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_and_saveexec_b32 s35, s0
	s_cbranch_execz .LBB2_230
; %bb.31:                               ;   in Loop: Header=BB2_26 Depth=1
	s_load_b64 s[16:17], s[2:3], 0x50
	v_mov_b32_e32 v1, v35
	v_mov_b32_e32 v3, 0
	v_mov_b32_e32 v4, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s0, v1
	v_cmp_eq_u32_e64 s0, s0, v1
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB2_37
; %bb.32:                               ;   in Loop: Header=BB2_26 Depth=1
	s_waitcnt lgkmcnt(0)
	global_load_b64 v[9:10], v2, s[16:17] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[3:4], v2, s[16:17] offset:40
	global_load_b64 v[7:8], v2, s[16:17]
	s_mov_b32 s21, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v4, v4, v10
	v_and_b32_e32 v3, v3, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v4, v4, 24
	v_mul_hi_u32 v11, v3, 24
	v_mul_lo_u32 v3, v3, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v4, v11, v4
	s_waitcnt vmcnt(0)
	v_add_co_u32 v3, vcc_lo, v7, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, v8, v4, vcc_lo
	global_load_b64 v[7:8], v[3:4], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[3:4], v2, v[7:10], s[16:17] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[3:4], v[9:10]
	s_cbranch_execz .LBB2_36
; %bb.33:                               ; %.preheader3.i.i.i.i.preheader
                                        ;   in Loop: Header=BB2_26 Depth=1
	s_mov_b32 s22, 0
.LBB2_34:                               ; %.preheader3.i.i.i.i
                                        ;   Parent Loop BB2_26 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[7:8], v2, s[16:17] offset:40
	global_load_b64 v[11:12], v2, s[16:17]
	v_dual_mov_b32 v10, v4 :: v_dual_mov_b32 v9, v3
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v7, v7, v9
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[3:4], null, v7, 24, v[11:12]
	v_and_b32_e32 v11, v8, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[7:8], null, v11, 24, v[4:5]
	v_mov_b32_e32 v4, v7
	global_load_b64 v[7:8], v[3:4], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[3:4], v2, v[7:10], s[16:17] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[3:4], v[9:10]
	s_or_b32 s22, vcc_lo, s22
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s22
	s_cbranch_execnz .LBB2_34
; %bb.35:                               ; %Flow410
                                        ;   in Loop: Header=BB2_26 Depth=1
	s_or_b32 exec_lo, exec_lo, s22
.LBB2_36:                               ; %Flow412
                                        ;   in Loop: Header=BB2_26 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s21
.LBB2_37:                               ; %.loopexit4.i.i.i.i
                                        ;   in Loop: Header=BB2_26 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_waitcnt lgkmcnt(0)
	s_clause 0x1
	global_load_b64 v[11:12], v2, s[16:17] offset:40
	global_load_b128 v[7:10], v2, s[16:17]
	v_readfirstlane_b32 s24, v3
	v_readfirstlane_b32 s25, v4
	s_mov_b32 s21, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s22, v11
	v_readfirstlane_b32 s23, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[22:23], s[24:25], s[22:23]
	s_mul_i32 s1, s23, 24
	s_mul_hi_u32 s26, s22, 24
	s_mul_i32 s27, s22, 24
	s_and_saveexec_b32 s28, s0
	s_cbranch_execz .LBB2_39
; %bb.38:                               ;   in Loop: Header=BB2_26 Depth=1
	s_add_i32 s29, s26, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v11, vcc_lo, v7, s27
	v_add_co_ci_u32_e32 v12, vcc_lo, s29, v8, vcc_lo
	v_dual_mov_b32 v3, s21 :: v_dual_mov_b32 v4, v2
	global_store_b128 v[11:12], v[3:6], off offset:8
.LBB2_39:                               ;   in Loop: Header=BB2_26 Depth=1
	s_or_b32 exec_lo, exec_lo, s28
	s_lshl_b64 s[22:23], s[22:23], 12
	v_lshlrev_b64 v[3:4], 6, v[1:2]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v1, vcc_lo, v9, s22
	v_add_co_ci_u32_e32 v9, vcc_lo, s23, v10, vcc_lo
	s_mov_b32 s21, s20
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v13, vcc_lo, v1, v3
	s_mov_b32 s22, s20
	s_mov_b32 s23, s20
	v_add_co_ci_u32_e32 v14, vcc_lo, v9, v4, vcc_lo
	v_mov_b32_e32 v1, v2
	v_mov_b32_e32 v3, v2
	v_dual_mov_b32 v9, s20 :: v_dual_mov_b32 v12, s23
	v_dual_mov_b32 v10, s21 :: v_dual_mov_b32 v11, s22
	s_clause 0x3
	global_store_b128 v[13:14], v[0:3], off
	global_store_b128 v[13:14], v[9:12], off offset:16
	global_store_b128 v[13:14], v[9:12], off offset:32
	global_store_b128 v[13:14], v[9:12], off offset:48
	s_and_saveexec_b32 s21, s0
	s_cbranch_execz .LBB2_47
; %bb.40:                               ;   in Loop: Header=BB2_26 Depth=1
	s_clause 0x1
	global_load_b64 v[17:18], v2, s[16:17] offset:32 glc
	global_load_b64 v[3:4], v2, s[16:17] offset:40
	v_mov_b32_e32 v15, s24
	s_mov_b32 s22, exec_lo
	s_waitcnt vmcnt(0)
	v_dual_mov_b32 v16, s25 :: v_dual_and_b32 v1, s25, v4
	v_and_b32_e32 v3, s24, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v1, v1, 24
	v_mul_hi_u32 v4, v3, 24
	v_mul_lo_u32 v3, v3, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v1, v4, v1
	v_add_co_u32 v3, vcc_lo, v7, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, v8, v1, vcc_lo
	global_store_b64 v[3:4], v[17:18], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[11:12], v2, v[15:18], s[16:17] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[11:12], v[17:18]
	s_cbranch_execz .LBB2_43
; %bb.41:                               ; %.preheader1.i.i.i.i.preheader
                                        ;   in Loop: Header=BB2_26 Depth=1
	s_mov_b32 s23, 0
.LBB2_42:                               ; %.preheader1.i.i.i.i
                                        ;   Parent Loop BB2_26 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_dual_mov_b32 v9, s24 :: v_dual_mov_b32 v10, s25
	s_sleep 1
	global_store_b64 v[3:4], v[11:12], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[9:10], v2, v[9:12], s[16:17] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[9:10], v[11:12]
	v_dual_mov_b32 v12, v10 :: v_dual_mov_b32 v11, v9
	s_or_b32 s23, vcc_lo, s23
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s23
	s_cbranch_execnz .LBB2_42
.LBB2_43:                               ; %Flow408
                                        ;   in Loop: Header=BB2_26 Depth=1
	s_or_b32 exec_lo, exec_lo, s22
	global_load_b64 v[3:4], v2, s[16:17] offset:16
	s_mov_b32 s23, exec_lo
	s_mov_b32 s22, exec_lo
	v_mbcnt_lo_u32_b32 v1, s23, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v1
	s_cbranch_execz .LBB2_45
; %bb.44:                               ;   in Loop: Header=BB2_26 Depth=1
	s_bcnt1_i32_b32 s23, s23
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v1, s23
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[3:4], v[1:2], off offset:8
.LBB2_45:                               ;   in Loop: Header=BB2_26 Depth=1
	s_or_b32 exec_lo, exec_lo, s22
	s_waitcnt vmcnt(0)
	global_load_b64 v[9:10], v[3:4], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[9:10]
	s_cbranch_vccnz .LBB2_47
; %bb.46:                               ;   in Loop: Header=BB2_26 Depth=1
	global_load_b32 v1, v[3:4], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s22, v1
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[9:10], v[1:2], off
	s_and_b32 m0, s22, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB2_47:                               ; %Flow409
                                        ;   in Loop: Header=BB2_26 Depth=1
	s_or_b32 exec_lo, exec_lo, s21
	s_add_i32 s26, s26, s1
	v_add_co_u32 v1, vcc_lo, v7, s27
	v_add_co_ci_u32_e32 v4, vcc_lo, s26, v8, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, v1, 20
	v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
.LBB2_48:                               ;   Parent Loop BB2_26 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_mov_b32_e32 v1, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB2_50
; %bb.49:                               ;   in Loop: Header=BB2_48 Depth=2
	global_load_b32 v1, v[3:4], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v1, 1, v1
.LBB2_50:                               ;   in Loop: Header=BB2_48 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v1
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB2_52
; %bb.51:                               ;   in Loop: Header=BB2_48 Depth=2
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB2_53
.LBB2_52:                               ;   in Loop: Header=BB2_48 Depth=2
	s_mov_b32 s1, -1
.LBB2_53:                               ; %Flow403
                                        ;   in Loop: Header=BB2_48 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB2_48
; %bb.54:                               ;   in Loop: Header=BB2_26 Depth=1
	global_load_b64 v[7:8], v[13:14], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB2_58
; %bb.55:                               ;   in Loop: Header=BB2_26 Depth=1
	s_clause 0x2
	global_load_b64 v[3:4], v2, s[16:17] offset:40
	global_load_b64 v[13:14], v2, s[16:17] offset:24 glc
	global_load_b64 v[11:12], v2, s[16:17]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v1, vcc_lo, v3, 1
	v_add_co_ci_u32_e32 v15, vcc_lo, 0, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v9, vcc_lo, v1, s24
	v_add_co_ci_u32_e32 v10, vcc_lo, s25, v15, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[9:10]
	v_dual_cndmask_b32 v10, v10, v15 :: v_dual_cndmask_b32 v9, v9, v1
	v_and_b32_e32 v1, v10, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v3, v9, v3
	v_mul_lo_u32 v1, v1, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v4, v3, 24
	v_mul_lo_u32 v3, v3, 24
	v_add_nc_u32_e32 v1, v4, v1
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v3, vcc_lo, v11, v3
	v_mov_b32_e32 v11, v13
	v_add_co_ci_u32_e32 v4, vcc_lo, v12, v1, vcc_lo
	v_mov_b32_e32 v12, v14
	global_store_b64 v[3:4], v[13:14], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[11:12], v2, v[9:12], s[16:17] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[11:12], v[13:14]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB2_58
; %bb.56:                               ; %.preheader.i.i.i.i.preheader
                                        ;   in Loop: Header=BB2_26 Depth=1
	s_mov_b32 s0, 0
.LBB2_57:                               ; %.preheader.i.i.i.i
                                        ;   Parent Loop BB2_26 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	global_store_b64 v[3:4], v[11:12], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[13:14], v2, v[9:12], s[16:17] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[13:14], v[11:12]
	v_dual_mov_b32 v11, v13 :: v_dual_mov_b32 v12, v14
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB2_57
.LBB2_58:                               ; %__ockl_printf_begin.exit.i
                                        ;   in Loop: Header=BB2_26 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_getpc_b64 s[22:23]
	s_add_u32 s22, s22, .str@rel32@lo+4
	s_addc_u32 s23, s23, .str@rel32@hi+12
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u64 s[22:23], 0
	s_cbranch_scc0 .LBB2_145
; %bb.59:                               ;   in Loop: Header=BB2_26 Depth=1
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v36, 2, v7
	v_dual_mov_b32 v10, v8 :: v_dual_and_b32 v9, -3, v7
	s_mov_b64 s[24:25], 29
.LBB2_60:                               ;   Parent Loop BB2_26 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB2_63 Depth 3
                                        ;       Child Loop BB2_71 Depth 3
                                        ;       Child Loop BB2_79 Depth 3
                                        ;       Child Loop BB2_87 Depth 3
                                        ;       Child Loop BB2_95 Depth 3
                                        ;       Child Loop BB2_103 Depth 3
                                        ;       Child Loop BB2_111 Depth 3
                                        ;       Child Loop BB2_119 Depth 3
                                        ;       Child Loop BB2_127 Depth 3
                                        ;       Child Loop BB2_133 Depth 3
                                        ;       Child Loop BB2_142 Depth 3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_u64_e64 s0, s[24:25], 56
	s_and_b32 s0, s0, exec_lo
	s_cselect_b32 s26, s24, 56
	s_cselect_b32 s27, s25, 0
	s_cmp_gt_u32 s26, 7
	s_cbranch_scc1 .LBB2_65
; %bb.61:                               ;   in Loop: Header=BB2_60 Depth=2
	s_waitcnt vmcnt(0)
	v_mov_b32_e32 v11, 0
	v_mov_b32_e32 v12, 0
	s_cmp_eq_u32 s26, 0
	s_cbranch_scc1 .LBB2_64
; %bb.62:                               ; %.preheader31.i.i.preheader
                                        ;   in Loop: Header=BB2_60 Depth=2
	s_lshl_b64 s[0:1], s[26:27], 3
	s_mov_b64 s[28:29], 0
	s_mov_b64 s[30:31], s[22:23]
.LBB2_63:                               ; %.preheader31.i.i
                                        ;   Parent Loop BB2_26 Depth=1
                                        ;     Parent Loop BB2_60 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	global_load_u8 v1, v2, s[30:31]
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v1, 0xffff, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], s28, v[1:2]
	s_add_u32 s28, s28, 8
	s_addc_u32 s29, s29, 0
	s_add_u32 s30, s30, 1
	s_addc_u32 s31, s31, 0
	s_cmp_lg_u32 s0, s28
	v_or_b32_e32 v11, v3, v11
	v_or_b32_e32 v12, v4, v12
	s_cbranch_scc1 .LBB2_63
.LBB2_64:                               ; %Flow379
                                        ;   in Loop: Header=BB2_60 Depth=2
	s_mov_b32 s0, 0
	s_mov_b32 s21, 0
	s_branch .LBB2_66
.LBB2_65:                               ;   in Loop: Header=BB2_60 Depth=2
	s_mov_b32 s0, -1
                                        ; implicit-def: $vgpr11_vgpr12
                                        ; implicit-def: $sgpr21
.LBB2_66:                               ; %Flow381
                                        ;   in Loop: Header=BB2_60 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s0
	s_mov_b64 s[0:1], s[22:23]
	s_cbranch_vccnz .LBB2_68
; %bb.67:                               ;   in Loop: Header=BB2_60 Depth=2
	global_load_b64 v[11:12], v2, s[22:23]
	s_add_i32 s21, s26, -8
	s_add_u32 s0, s22, 8
	s_addc_u32 s1, s23, 0
.LBB2_68:                               ; %.loopexit32.i.i
                                        ;   in Loop: Header=BB2_60 Depth=2
	s_cmp_gt_u32 s21, 7
	s_cbranch_scc1 .LBB2_73
; %bb.69:                               ;   in Loop: Header=BB2_60 Depth=2
	v_mov_b32_e32 v13, 0
	v_mov_b32_e32 v14, 0
	s_cmp_eq_u32 s21, 0
	s_cbranch_scc1 .LBB2_72
; %bb.70:                               ; %.preheader29.i.i.preheader
                                        ;   in Loop: Header=BB2_60 Depth=2
	s_mov_b64 s[28:29], 0
	s_mov_b64 s[30:31], 0
.LBB2_71:                               ; %.preheader29.i.i
                                        ;   Parent Loop BB2_26 Depth=1
                                        ;     Parent Loop BB2_60 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s36, s0, s30
	s_addc_u32 s37, s1, s31
	s_add_u32 s30, s30, 1
	global_load_u8 v1, v2, s[36:37]
	s_addc_u32 s31, s31, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v1, 0xffff, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], s28, v[1:2]
	s_add_u32 s28, s28, 8
	s_addc_u32 s29, s29, 0
	s_cmp_lg_u32 s21, s30
	v_or_b32_e32 v13, v3, v13
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v14, v4, v14
	s_cbranch_scc1 .LBB2_71
.LBB2_72:                               ; %Flow374
                                        ;   in Loop: Header=BB2_60 Depth=2
	s_mov_b32 s28, 0
	s_mov_b32 s36, 0
	s_branch .LBB2_74
.LBB2_73:                               ;   in Loop: Header=BB2_60 Depth=2
	s_mov_b32 s28, -1
                                        ; implicit-def: $vgpr13_vgpr14
                                        ; implicit-def: $sgpr36
.LBB2_74:                               ; %Flow376
                                        ;   in Loop: Header=BB2_60 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s28
	s_cbranch_vccnz .LBB2_76
; %bb.75:                               ;   in Loop: Header=BB2_60 Depth=2
	global_load_b64 v[13:14], v2, s[0:1]
	s_add_i32 s36, s21, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB2_76:                               ; %.loopexit30.i.i
                                        ;   in Loop: Header=BB2_60 Depth=2
	s_cmp_gt_u32 s36, 7
	s_cbranch_scc1 .LBB2_81
; %bb.77:                               ;   in Loop: Header=BB2_60 Depth=2
	v_mov_b32_e32 v15, 0
	v_mov_b32_e32 v16, 0
	s_cmp_eq_u32 s36, 0
	s_cbranch_scc1 .LBB2_80
; %bb.78:                               ; %.preheader27.i.i.preheader
                                        ;   in Loop: Header=BB2_60 Depth=2
	s_mov_b64 s[28:29], 0
	s_mov_b64 s[30:31], 0
.LBB2_79:                               ; %.preheader27.i.i
                                        ;   Parent Loop BB2_26 Depth=1
                                        ;     Parent Loop BB2_60 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s38, s0, s30
	s_addc_u32 s39, s1, s31
	s_add_u32 s30, s30, 1
	global_load_u8 v1, v2, s[38:39]
	s_addc_u32 s31, s31, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v1, 0xffff, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], s28, v[1:2]
	s_add_u32 s28, s28, 8
	s_addc_u32 s29, s29, 0
	s_cmp_lg_u32 s36, s30
	v_or_b32_e32 v15, v3, v15
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v16, v4, v16
	s_cbranch_scc1 .LBB2_79
.LBB2_80:                               ; %Flow369
                                        ;   in Loop: Header=BB2_60 Depth=2
	s_mov_b32 s28, 0
	s_mov_b32 s21, 0
	s_branch .LBB2_82
.LBB2_81:                               ;   in Loop: Header=BB2_60 Depth=2
	s_mov_b32 s28, -1
                                        ; implicit-def: $sgpr21
.LBB2_82:                               ; %Flow371
                                        ;   in Loop: Header=BB2_60 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s28
	s_cbranch_vccnz .LBB2_84
; %bb.83:                               ;   in Loop: Header=BB2_60 Depth=2
	global_load_b64 v[15:16], v2, s[0:1]
	s_add_i32 s21, s36, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB2_84:                               ; %.loopexit28.i.i
                                        ;   in Loop: Header=BB2_60 Depth=2
	s_cmp_gt_u32 s21, 7
	s_cbranch_scc1 .LBB2_89
; %bb.85:                               ;   in Loop: Header=BB2_60 Depth=2
	v_mov_b32_e32 v17, 0
	v_mov_b32_e32 v18, 0
	s_cmp_eq_u32 s21, 0
	s_cbranch_scc1 .LBB2_88
; %bb.86:                               ; %.preheader25.i.i.preheader
                                        ;   in Loop: Header=BB2_60 Depth=2
	s_mov_b64 s[28:29], 0
	s_mov_b64 s[30:31], 0
.LBB2_87:                               ; %.preheader25.i.i
                                        ;   Parent Loop BB2_26 Depth=1
                                        ;     Parent Loop BB2_60 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s36, s0, s30
	s_addc_u32 s37, s1, s31
	s_add_u32 s30, s30, 1
	global_load_u8 v1, v2, s[36:37]
	s_addc_u32 s31, s31, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v1, 0xffff, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], s28, v[1:2]
	s_add_u32 s28, s28, 8
	s_addc_u32 s29, s29, 0
	s_cmp_lg_u32 s21, s30
	v_or_b32_e32 v17, v3, v17
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v18, v4, v18
	s_cbranch_scc1 .LBB2_87
.LBB2_88:                               ; %Flow364
                                        ;   in Loop: Header=BB2_60 Depth=2
	s_mov_b32 s28, 0
	s_mov_b32 s36, 0
	s_branch .LBB2_90
.LBB2_89:                               ;   in Loop: Header=BB2_60 Depth=2
	s_mov_b32 s28, -1
                                        ; implicit-def: $vgpr17_vgpr18
                                        ; implicit-def: $sgpr36
.LBB2_90:                               ; %Flow366
                                        ;   in Loop: Header=BB2_60 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s28
	s_cbranch_vccnz .LBB2_92
; %bb.91:                               ;   in Loop: Header=BB2_60 Depth=2
	global_load_b64 v[17:18], v2, s[0:1]
	s_add_i32 s36, s21, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB2_92:                               ; %.loopexit26.i.i
                                        ;   in Loop: Header=BB2_60 Depth=2
	s_cmp_gt_u32 s36, 7
	s_cbranch_scc1 .LBB2_97
; %bb.93:                               ;   in Loop: Header=BB2_60 Depth=2
	v_mov_b32_e32 v19, 0
	v_mov_b32_e32 v20, 0
	s_cmp_eq_u32 s36, 0
	s_cbranch_scc1 .LBB2_96
; %bb.94:                               ; %.preheader23.i.i.preheader
                                        ;   in Loop: Header=BB2_60 Depth=2
	s_mov_b64 s[28:29], 0
	s_mov_b64 s[30:31], 0
.LBB2_95:                               ; %.preheader23.i.i
                                        ;   Parent Loop BB2_26 Depth=1
                                        ;     Parent Loop BB2_60 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s38, s0, s30
	s_addc_u32 s39, s1, s31
	s_add_u32 s30, s30, 1
	global_load_u8 v1, v2, s[38:39]
	s_addc_u32 s31, s31, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v1, 0xffff, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], s28, v[1:2]
	s_add_u32 s28, s28, 8
	s_addc_u32 s29, s29, 0
	s_cmp_lg_u32 s36, s30
	v_or_b32_e32 v19, v3, v19
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v20, v4, v20
	s_cbranch_scc1 .LBB2_95
.LBB2_96:                               ; %Flow359
                                        ;   in Loop: Header=BB2_60 Depth=2
	s_mov_b32 s28, 0
	s_mov_b32 s21, 0
	s_branch .LBB2_98
.LBB2_97:                               ;   in Loop: Header=BB2_60 Depth=2
	s_mov_b32 s28, -1
                                        ; implicit-def: $sgpr21
.LBB2_98:                               ; %Flow361
                                        ;   in Loop: Header=BB2_60 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s28
	s_cbranch_vccnz .LBB2_100
; %bb.99:                               ;   in Loop: Header=BB2_60 Depth=2
	global_load_b64 v[19:20], v2, s[0:1]
	s_add_i32 s21, s36, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB2_100:                              ; %.loopexit24.i.i
                                        ;   in Loop: Header=BB2_60 Depth=2
	s_cmp_gt_u32 s21, 7
	s_cbranch_scc1 .LBB2_105
; %bb.101:                              ;   in Loop: Header=BB2_60 Depth=2
	v_mov_b32_e32 v21, 0
	v_mov_b32_e32 v22, 0
	s_cmp_eq_u32 s21, 0
	s_cbranch_scc1 .LBB2_104
; %bb.102:                              ; %.preheader21.i.i.preheader
                                        ;   in Loop: Header=BB2_60 Depth=2
	s_mov_b64 s[28:29], 0
	s_mov_b64 s[30:31], 0
.LBB2_103:                              ; %.preheader21.i.i
                                        ;   Parent Loop BB2_26 Depth=1
                                        ;     Parent Loop BB2_60 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s36, s0, s30
	s_addc_u32 s37, s1, s31
	s_add_u32 s30, s30, 1
	global_load_u8 v1, v2, s[36:37]
	s_addc_u32 s31, s31, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v1, 0xffff, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], s28, v[1:2]
	s_add_u32 s28, s28, 8
	s_addc_u32 s29, s29, 0
	s_cmp_lg_u32 s21, s30
	v_or_b32_e32 v21, v3, v21
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v22, v4, v22
	s_cbranch_scc1 .LBB2_103
.LBB2_104:                              ; %Flow354
                                        ;   in Loop: Header=BB2_60 Depth=2
	s_mov_b32 s28, 0
	s_mov_b32 s36, 0
	s_branch .LBB2_106
.LBB2_105:                              ;   in Loop: Header=BB2_60 Depth=2
	s_mov_b32 s28, -1
                                        ; implicit-def: $vgpr21_vgpr22
                                        ; implicit-def: $sgpr36
.LBB2_106:                              ; %Flow356
                                        ;   in Loop: Header=BB2_60 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s28
	s_cbranch_vccnz .LBB2_108
; %bb.107:                              ;   in Loop: Header=BB2_60 Depth=2
	global_load_b64 v[21:22], v2, s[0:1]
	s_add_i32 s36, s21, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB2_108:                              ; %.loopexit22.i.i
                                        ;   in Loop: Header=BB2_60 Depth=2
	s_cmp_gt_u32 s36, 7
	s_cbranch_scc1 .LBB2_113
; %bb.109:                              ;   in Loop: Header=BB2_60 Depth=2
	v_mov_b32_e32 v23, 0
	v_mov_b32_e32 v24, 0
	s_cmp_eq_u32 s36, 0
	s_cbranch_scc1 .LBB2_112
; %bb.110:                              ; %.preheader.i.i.preheader
                                        ;   in Loop: Header=BB2_60 Depth=2
	s_mov_b64 s[28:29], 0
	s_mov_b64 s[30:31], s[0:1]
.LBB2_111:                              ; %.preheader.i.i
                                        ;   Parent Loop BB2_26 Depth=1
                                        ;     Parent Loop BB2_60 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	global_load_u8 v1, v2, s[30:31]
	s_add_i32 s36, s36, -1
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v1, 0xffff, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], s28, v[1:2]
	s_add_u32 s28, s28, 8
	s_addc_u32 s29, s29, 0
	s_add_u32 s30, s30, 1
	s_addc_u32 s31, s31, 0
	s_cmp_lg_u32 s36, 0
	v_or_b32_e32 v23, v3, v23
	v_or_b32_e32 v24, v4, v24
	s_cbranch_scc1 .LBB2_111
.LBB2_112:                              ; %Flow349
                                        ;   in Loop: Header=BB2_60 Depth=2
	s_mov_b32 s21, 0
	s_branch .LBB2_114
.LBB2_113:                              ;   in Loop: Header=BB2_60 Depth=2
	s_mov_b32 s21, -1
.LBB2_114:                              ; %Flow351
                                        ;   in Loop: Header=BB2_60 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s21
	s_cbranch_vccnz .LBB2_116
; %bb.115:                              ;   in Loop: Header=BB2_60 Depth=2
	global_load_b64 v[23:24], v2, s[0:1]
.LBB2_116:                              ; %.loopexit.i.i
                                        ;   in Loop: Header=BB2_60 Depth=2
	v_mov_b32_e32 v1, v35
	v_mov_b32_e32 v3, 0
	v_mov_b32_e32 v4, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s0, v1
	v_cmp_eq_u32_e64 s0, s0, v1
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB2_122
; %bb.117:                              ;   in Loop: Header=BB2_60 Depth=2
	global_load_b64 v[27:28], v2, s[16:17] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[3:4], v2, s[16:17] offset:40
	global_load_b64 v[25:26], v2, s[16:17]
	s_mov_b32 s21, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v4, v4, v28
	v_and_b32_e32 v3, v3, v27
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v4, v4, 24
	v_mul_hi_u32 v37, v3, 24
	v_mul_lo_u32 v3, v3, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v4, v37, v4
	s_waitcnt vmcnt(0)
	v_add_co_u32 v3, vcc_lo, v25, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, v26, v4, vcc_lo
	global_load_b64 v[25:26], v[3:4], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[3:4], v2, v[25:28], s[16:17] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[3:4], v[27:28]
	s_cbranch_execz .LBB2_121
; %bb.118:                              ; %.preheader3.i.i19.i.i.preheader
                                        ;   in Loop: Header=BB2_60 Depth=2
	s_mov_b32 s28, 0
.LBB2_119:                              ; %.preheader3.i.i19.i.i
                                        ;   Parent Loop BB2_26 Depth=1
                                        ;     Parent Loop BB2_60 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[25:26], v2, s[16:17] offset:40
	global_load_b64 v[37:38], v2, s[16:17]
	v_dual_mov_b32 v28, v4 :: v_dual_mov_b32 v27, v3
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v25, v25, v27
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[3:4], null, v25, 24, v[37:38]
	v_and_b32_e32 v37, v26, v28
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[25:26], null, v37, 24, v[4:5]
	v_mov_b32_e32 v4, v25
	global_load_b64 v[25:26], v[3:4], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[3:4], v2, v[25:28], s[16:17] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[3:4], v[27:28]
	s_or_b32 s28, vcc_lo, s28
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s28
	s_cbranch_execnz .LBB2_119
; %bb.120:                              ; %Flow344
                                        ;   in Loop: Header=BB2_60 Depth=2
	s_or_b32 exec_lo, exec_lo, s28
.LBB2_121:                              ; %Flow346
                                        ;   in Loop: Header=BB2_60 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s21
.LBB2_122:                              ; %.loopexit4.i.i14.i.i
                                        ;   in Loop: Header=BB2_60 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_clause 0x1
	global_load_b64 v[37:38], v2, s[16:17] offset:40
	global_load_b128 v[25:28], v2, s[16:17]
	v_readfirstlane_b32 s28, v3
	v_readfirstlane_b32 s29, v4
	s_mov_b32 s37, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s30, v37
	v_readfirstlane_b32 s31, v38
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[30:31], s[28:29], s[30:31]
	s_mul_i32 s1, s31, 24
	s_mul_hi_u32 s21, s30, 24
	s_mul_i32 s36, s30, 24
	s_and_saveexec_b32 s38, s0
	s_cbranch_execz .LBB2_124
; %bb.123:                              ;   in Loop: Header=BB2_60 Depth=2
	s_add_i32 s39, s21, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v37, vcc_lo, v25, s36
	v_add_co_ci_u32_e32 v38, vcc_lo, s39, v26, vcc_lo
	v_dual_mov_b32 v3, s37 :: v_dual_mov_b32 v4, v2
	global_store_b128 v[37:38], v[3:6], off offset:8
.LBB2_124:                              ;   in Loop: Header=BB2_60 Depth=2
	s_or_b32 exec_lo, exec_lo, s38
	v_cmp_gt_u64_e64 vcc_lo, s[24:25], 56
	v_or_b32_e32 v3, 0, v10
	v_or_b32_e32 v4, v9, v36
	s_lshl_b64 s[30:31], s[30:31], 12
	s_lshl_b32 s37, s26, 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_add_i32 s37, s37, 28
	v_dual_cndmask_b32 v10, v3, v10 :: v_dual_cndmask_b32 v9, v4, v9
	v_lshlrev_b64 v[3:4], 6, v[1:2]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v1, vcc_lo, v27, s30
	v_add_co_ci_u32_e32 v27, vcc_lo, s31, v28, vcc_lo
	s_and_b32 s37, s37, 0x1e0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v3, vcc_lo, v1, v3
	v_and_or_b32 v9, 0xffffff1f, v9, s37
	v_add_co_ci_u32_e32 v4, vcc_lo, v27, v4, vcc_lo
	s_clause 0x3
	global_store_b128 v[3:4], v[9:12], off
	global_store_b128 v[3:4], v[13:16], off offset:16
	global_store_b128 v[3:4], v[17:20], off offset:32
	global_store_b128 v[3:4], v[21:24], off offset:48
	s_and_saveexec_b32 s30, s0
	s_cbranch_execz .LBB2_132
; %bb.125:                              ;   in Loop: Header=BB2_60 Depth=2
	s_clause 0x1
	global_load_b64 v[17:18], v2, s[16:17] offset:32 glc
	global_load_b64 v[9:10], v2, s[16:17] offset:40
	v_dual_mov_b32 v15, s28 :: v_dual_mov_b32 v16, s29
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s38, v9
	v_readfirstlane_b32 s39, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[38:39], s[38:39], s[28:29]
	s_mul_i32 s31, s39, 24
	s_mul_hi_u32 s37, s38, 24
	s_mul_i32 s38, s38, 24
	s_add_i32 s37, s37, s31
	v_add_co_u32 v13, vcc_lo, v25, s38
	v_add_co_ci_u32_e32 v14, vcc_lo, s37, v26, vcc_lo
	s_mov_b32 s31, exec_lo
	global_store_b64 v[13:14], v[17:18], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[11:12], v2, v[15:18], s[16:17] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[11:12], v[17:18]
	s_cbranch_execz .LBB2_128
; %bb.126:                              ; %.preheader1.i.i17.i.i.preheader
                                        ;   in Loop: Header=BB2_60 Depth=2
	s_mov_b32 s37, 0
.LBB2_127:                              ; %.preheader1.i.i17.i.i
                                        ;   Parent Loop BB2_26 Depth=1
                                        ;     Parent Loop BB2_60 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	v_dual_mov_b32 v9, s28 :: v_dual_mov_b32 v10, s29
	s_sleep 1
	global_store_b64 v[13:14], v[11:12], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[9:10], v2, v[9:12], s[16:17] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[9:10], v[11:12]
	v_dual_mov_b32 v12, v10 :: v_dual_mov_b32 v11, v9
	s_or_b32 s37, vcc_lo, s37
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s37
	s_cbranch_execnz .LBB2_127
.LBB2_128:                              ; %Flow342
                                        ;   in Loop: Header=BB2_60 Depth=2
	s_or_b32 exec_lo, exec_lo, s31
	global_load_b64 v[9:10], v2, s[16:17] offset:16
	s_mov_b32 s37, exec_lo
	s_mov_b32 s31, exec_lo
	v_mbcnt_lo_u32_b32 v1, s37, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v1
	s_cbranch_execz .LBB2_130
; %bb.129:                              ;   in Loop: Header=BB2_60 Depth=2
	s_bcnt1_i32_b32 s37, s37
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v1, s37
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[9:10], v[1:2], off offset:8
.LBB2_130:                              ;   in Loop: Header=BB2_60 Depth=2
	s_or_b32 exec_lo, exec_lo, s31
	s_waitcnt vmcnt(0)
	global_load_b64 v[11:12], v[9:10], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[11:12]
	s_cbranch_vccnz .LBB2_132
; %bb.131:                              ;   in Loop: Header=BB2_60 Depth=2
	global_load_b32 v1, v[9:10], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s31, v1
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[11:12], v[1:2], off
	s_and_b32 m0, s31, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB2_132:                              ; %Flow343
                                        ;   in Loop: Header=BB2_60 Depth=2
	s_or_b32 exec_lo, exec_lo, s30
	s_add_i32 s21, s21, s1
	v_add_co_u32 v1, vcc_lo, v25, s36
	v_add_co_ci_u32_e32 v10, vcc_lo, s21, v26, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v9, vcc_lo, v1, 20
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v10, vcc_lo
.LBB2_133:                              ;   Parent Loop BB2_26 Depth=1
                                        ;     Parent Loop BB2_60 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	v_mov_b32_e32 v1, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB2_135
; %bb.134:                              ;   in Loop: Header=BB2_133 Depth=3
	global_load_b32 v1, v[9:10], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v1, 1, v1
.LBB2_135:                              ;   in Loop: Header=BB2_133 Depth=3
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v1
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB2_137
; %bb.136:                              ;   in Loop: Header=BB2_133 Depth=3
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB2_138
.LBB2_137:                              ;   in Loop: Header=BB2_133 Depth=3
	s_mov_b32 s1, -1
.LBB2_138:                              ; %Flow337
                                        ;   in Loop: Header=BB2_133 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB2_133
; %bb.139:                              ;   in Loop: Header=BB2_60 Depth=2
	global_load_b128 v[9:12], v[3:4], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB2_143
; %bb.140:                              ;   in Loop: Header=BB2_60 Depth=2
	s_clause 0x2
	global_load_b64 v[3:4], v2, s[16:17] offset:40
	global_load_b64 v[15:16], v2, s[16:17] offset:24 glc
	global_load_b64 v[13:14], v2, s[16:17]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v1, vcc_lo, v3, 1
	v_add_co_ci_u32_e32 v17, vcc_lo, 0, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v11, vcc_lo, v1, s28
	v_add_co_ci_u32_e32 v12, vcc_lo, s29, v17, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[11:12]
	v_cndmask_b32_e32 v11, v11, v1, vcc_lo
	v_dual_cndmask_b32 v12, v12, v17 :: v_dual_and_b32 v3, v11, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v1, v12, v4
	v_mul_hi_u32 v4, v3, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v1, v1, 24
	v_mul_lo_u32 v3, v3, 24
	v_add_nc_u32_e32 v1, v4, v1
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v3, vcc_lo, v13, v3
	v_mov_b32_e32 v13, v15
	v_add_co_ci_u32_e32 v4, vcc_lo, v14, v1, vcc_lo
	v_mov_b32_e32 v14, v16
	global_store_b64 v[3:4], v[15:16], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[13:14], v2, v[11:14], s[16:17] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[13:14], v[15:16]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB2_143
; %bb.141:                              ; %.preheader.i.i16.i.i.preheader
                                        ;   in Loop: Header=BB2_60 Depth=2
	s_mov_b32 s0, 0
.LBB2_142:                              ; %.preheader.i.i16.i.i
                                        ;   Parent Loop BB2_26 Depth=1
                                        ;     Parent Loop BB2_60 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_sleep 1
	global_store_b64 v[3:4], v[13:14], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[15:16], v2, v[11:14], s[16:17] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[15:16], v[13:14]
	v_dual_mov_b32 v13, v15 :: v_dual_mov_b32 v14, v16
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB2_142
.LBB2_143:                              ; %__ockl_hostcall_preview.exit20.i.i
                                        ;   in Loop: Header=BB2_60 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	s_sub_u32 s24, s24, s26
	s_subb_u32 s25, s25, s27
	s_add_u32 s22, s22, s26
	s_addc_u32 s23, s23, s27
	s_cmp_lg_u64 s[24:25], 0
	s_cbranch_scc1 .LBB2_60
; %bb.144:                              ; %Flow382
                                        ;   in Loop: Header=BB2_26 Depth=1
	s_mov_b32 s0, 0
	s_branch .LBB2_146
.LBB2_145:                              ;   in Loop: Header=BB2_26 Depth=1
	s_mov_b32 s0, -1
                                        ; implicit-def: $vgpr9_vgpr10
.LBB2_146:                              ; %Flow397
                                        ;   in Loop: Header=BB2_26 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccz .LBB2_175
; %bb.147:                              ;   in Loop: Header=BB2_26 Depth=1
	v_mov_b32_e32 v1, v35
	v_mov_b32_e32 v3, 0
	v_mov_b32_e32 v4, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s0, v1
	v_cmp_eq_u32_e64 s0, s0, v1
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB2_153
; %bb.148:                              ;   in Loop: Header=BB2_26 Depth=1
	global_load_b64 v[11:12], v2, s[16:17] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[3:4], v2, s[16:17] offset:40
	global_load_b64 v[9:10], v2, s[16:17]
	s_mov_b32 s21, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v4, v4, v12
	v_and_b32_e32 v3, v3, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v4, v4, 24
	v_mul_hi_u32 v13, v3, 24
	v_mul_lo_u32 v3, v3, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v4, v13, v4
	s_waitcnt vmcnt(0)
	v_add_co_u32 v3, vcc_lo, v9, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, v10, v4, vcc_lo
	global_load_b64 v[9:10], v[3:4], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[3:4], v2, v[9:12], s[16:17] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[3:4], v[11:12]
	s_cbranch_execz .LBB2_152
; %bb.149:                              ; %.preheader3.i.i.i26.i.preheader
                                        ;   in Loop: Header=BB2_26 Depth=1
	s_mov_b32 s22, 0
.LBB2_150:                              ; %.preheader3.i.i.i26.i
                                        ;   Parent Loop BB2_26 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[9:10], v2, s[16:17] offset:40
	global_load_b64 v[13:14], v2, s[16:17]
	v_dual_mov_b32 v12, v4 :: v_dual_mov_b32 v11, v3
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v9, v9, v11
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[3:4], null, v9, 24, v[13:14]
	v_and_b32_e32 v13, v10, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[9:10], null, v13, 24, v[4:5]
	v_mov_b32_e32 v4, v9
	global_load_b64 v[9:10], v[3:4], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[3:4], v2, v[9:12], s[16:17] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[3:4], v[11:12]
	s_or_b32 s22, vcc_lo, s22
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s22
	s_cbranch_execnz .LBB2_150
; %bb.151:                              ; %Flow394
                                        ;   in Loop: Header=BB2_26 Depth=1
	s_or_b32 exec_lo, exec_lo, s22
.LBB2_152:                              ; %Flow396
                                        ;   in Loop: Header=BB2_26 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s21
.LBB2_153:                              ; %.loopexit4.i.i.i21.i
                                        ;   in Loop: Header=BB2_26 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_clause 0x1
	global_load_b64 v[9:10], v2, s[16:17] offset:40
	global_load_b128 v[11:14], v2, s[16:17]
	v_readfirstlane_b32 s24, v3
	v_readfirstlane_b32 s25, v4
	s_mov_b32 s21, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s22, v9
	v_readfirstlane_b32 s23, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[22:23], s[24:25], s[22:23]
	s_mul_i32 s1, s23, 24
	s_mul_hi_u32 s26, s22, 24
	s_mul_i32 s27, s22, 24
	s_and_saveexec_b32 s28, s0
	s_cbranch_execz .LBB2_155
; %bb.154:                              ;   in Loop: Header=BB2_26 Depth=1
	s_add_i32 s29, s26, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v9, vcc_lo, v11, s27
	v_add_co_ci_u32_e32 v10, vcc_lo, s29, v12, vcc_lo
	v_dual_mov_b32 v3, s21 :: v_dual_mov_b32 v4, v2
	global_store_b128 v[9:10], v[3:6], off offset:8
.LBB2_155:                              ;   in Loop: Header=BB2_26 Depth=1
	s_or_b32 exec_lo, exec_lo, s28
	s_lshl_b64 s[22:23], s[22:23], 12
	v_lshlrev_b64 v[3:4], 6, v[1:2]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v1, vcc_lo, v13, s22
	v_add_co_ci_u32_e32 v9, vcc_lo, s23, v14, vcc_lo
	s_mov_b32 s21, s20
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, v1, v3
	s_mov_b32 s22, s20
	s_mov_b32 s23, s20
	v_and_or_b32 v7, 0xffffff1f, v7, 32
	v_add_co_ci_u32_e32 v4, vcc_lo, v9, v4, vcc_lo
	v_mov_b32_e32 v9, v2
	v_dual_mov_b32 v10, v2 :: v_dual_mov_b32 v13, s20
	v_dual_mov_b32 v14, s21 :: v_dual_mov_b32 v15, s22
	v_mov_b32_e32 v16, s23
	s_clause 0x3
	global_store_b128 v[3:4], v[7:10], off
	global_store_b128 v[3:4], v[13:16], off offset:16
	global_store_b128 v[3:4], v[13:16], off offset:32
	global_store_b128 v[3:4], v[13:16], off offset:48
	s_and_saveexec_b32 s21, s0
	s_cbranch_execz .LBB2_163
; %bb.156:                              ;   in Loop: Header=BB2_26 Depth=1
	s_clause 0x1
	global_load_b64 v[17:18], v2, s[16:17] offset:32 glc
	global_load_b64 v[7:8], v2, s[16:17] offset:40
	v_dual_mov_b32 v15, s24 :: v_dual_mov_b32 v16, s25
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s22, v7
	v_readfirstlane_b32 s23, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[22:23], s[22:23], s[24:25]
	s_mul_i32 s23, s23, 24
	s_mul_hi_u32 s28, s22, 24
	s_mul_i32 s22, s22, 24
	s_add_i32 s28, s28, s23
	v_add_co_u32 v13, vcc_lo, v11, s22
	v_add_co_ci_u32_e32 v14, vcc_lo, s28, v12, vcc_lo
	s_mov_b32 s22, exec_lo
	global_store_b64 v[13:14], v[17:18], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[9:10], v2, v[15:18], s[16:17] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[9:10], v[17:18]
	s_cbranch_execz .LBB2_159
; %bb.157:                              ; %.preheader1.i.i.i24.i.preheader
                                        ;   in Loop: Header=BB2_26 Depth=1
	s_mov_b32 s23, 0
.LBB2_158:                              ; %.preheader1.i.i.i24.i
                                        ;   Parent Loop BB2_26 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_dual_mov_b32 v7, s24 :: v_dual_mov_b32 v8, s25
	s_sleep 1
	global_store_b64 v[13:14], v[9:10], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[7:8], v2, v[7:10], s[16:17] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[9:10]
	v_dual_mov_b32 v10, v8 :: v_dual_mov_b32 v9, v7
	s_or_b32 s23, vcc_lo, s23
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s23
	s_cbranch_execnz .LBB2_158
.LBB2_159:                              ; %Flow392
                                        ;   in Loop: Header=BB2_26 Depth=1
	s_or_b32 exec_lo, exec_lo, s22
	global_load_b64 v[7:8], v2, s[16:17] offset:16
	s_mov_b32 s23, exec_lo
	s_mov_b32 s22, exec_lo
	v_mbcnt_lo_u32_b32 v1, s23, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v1
	s_cbranch_execz .LBB2_161
; %bb.160:                              ;   in Loop: Header=BB2_26 Depth=1
	s_bcnt1_i32_b32 s23, s23
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v1, s23
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[7:8], v[1:2], off offset:8
.LBB2_161:                              ;   in Loop: Header=BB2_26 Depth=1
	s_or_b32 exec_lo, exec_lo, s22
	s_waitcnt vmcnt(0)
	global_load_b64 v[9:10], v[7:8], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[9:10]
	s_cbranch_vccnz .LBB2_163
; %bb.162:                              ;   in Loop: Header=BB2_26 Depth=1
	global_load_b32 v1, v[7:8], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s22, v1
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[9:10], v[1:2], off
	s_and_b32 m0, s22, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB2_163:                              ; %Flow393
                                        ;   in Loop: Header=BB2_26 Depth=1
	s_or_b32 exec_lo, exec_lo, s21
	s_add_i32 s26, s26, s1
	v_add_co_u32 v1, vcc_lo, v11, s27
	v_add_co_ci_u32_e32 v8, vcc_lo, s26, v12, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v7, vcc_lo, v1, 20
	v_add_co_ci_u32_e32 v8, vcc_lo, 0, v8, vcc_lo
.LBB2_164:                              ;   Parent Loop BB2_26 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_mov_b32_e32 v1, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB2_166
; %bb.165:                              ;   in Loop: Header=BB2_164 Depth=2
	global_load_b32 v1, v[7:8], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v1, 1, v1
.LBB2_166:                              ;   in Loop: Header=BB2_164 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v1
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB2_168
; %bb.167:                              ;   in Loop: Header=BB2_164 Depth=2
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB2_169
.LBB2_168:                              ;   in Loop: Header=BB2_164 Depth=2
	s_mov_b32 s1, -1
.LBB2_169:                              ; %Flow387
                                        ;   in Loop: Header=BB2_164 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB2_164
; %bb.170:                              ;   in Loop: Header=BB2_26 Depth=1
	global_load_b128 v[9:12], v[3:4], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB2_174
; %bb.171:                              ;   in Loop: Header=BB2_26 Depth=1
	s_clause 0x2
	global_load_b64 v[3:4], v2, s[16:17] offset:40
	global_load_b64 v[7:8], v2, s[16:17] offset:24 glc
	global_load_b64 v[13:14], v2, s[16:17]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v1, vcc_lo, v3, 1
	v_add_co_ci_u32_e32 v15, vcc_lo, 0, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v11, vcc_lo, v1, s24
	v_add_co_ci_u32_e32 v12, vcc_lo, s25, v15, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[11:12]
	v_dual_cndmask_b32 v12, v12, v15 :: v_dual_cndmask_b32 v11, v11, v1
	v_and_b32_e32 v1, v12, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v3, v11, v3
	v_mul_lo_u32 v1, v1, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v4, v3, 24
	v_mul_lo_u32 v3, v3, 24
	v_add_nc_u32_e32 v1, v4, v1
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v3, vcc_lo, v13, v3
	v_mov_b32_e32 v13, v7
	v_add_co_ci_u32_e32 v4, vcc_lo, v14, v1, vcc_lo
	v_mov_b32_e32 v14, v8
	global_store_b64 v[3:4], v[7:8], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[13:14], v2, v[11:14], s[16:17] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[13:14], v[7:8]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB2_174
; %bb.172:                              ; %.preheader.i.i.i23.i.preheader
                                        ;   in Loop: Header=BB2_26 Depth=1
	s_mov_b32 s0, 0
.LBB2_173:                              ; %.preheader.i.i.i23.i
                                        ;   Parent Loop BB2_26 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	global_store_b64 v[3:4], v[13:14], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[7:8], v2, v[11:14], s[16:17] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[13:14]
	v_dual_mov_b32 v14, v8 :: v_dual_mov_b32 v13, v7
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB2_173
.LBB2_174:                              ; %__ockl_hostcall_preview.exit.i.i
                                        ;   in Loop: Header=BB2_26 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
.LBB2_175:                              ; %__ockl_printf_append_string_n.exit.i
                                        ;   in Loop: Header=BB2_26 Depth=1
	v_mov_b32_e32 v1, v35
	v_mov_b32_e32 v3, 0
	v_mov_b32_e32 v4, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s0, v1
	v_cmp_eq_u32_e64 s0, s0, v1
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB2_181
; %bb.176:                              ;   in Loop: Header=BB2_26 Depth=1
	global_load_b64 v[13:14], v2, s[16:17] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[3:4], v2, s[16:17] offset:40
	global_load_b64 v[7:8], v2, s[16:17]
	s_mov_b32 s21, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v4, v4, v14
	v_and_b32_e32 v3, v3, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v4, v4, 24
	v_mul_hi_u32 v11, v3, 24
	v_mul_lo_u32 v3, v3, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v4, v11, v4
	s_waitcnt vmcnt(0)
	v_add_co_u32 v3, vcc_lo, v7, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, v8, v4, vcc_lo
	global_load_b64 v[11:12], v[3:4], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[3:4], v2, v[11:14], s[16:17] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[3:4], v[13:14]
	s_cbranch_execz .LBB2_180
; %bb.177:                              ; %.preheader3.i.i.i33.i.preheader
                                        ;   in Loop: Header=BB2_26 Depth=1
	s_mov_b32 s22, 0
.LBB2_178:                              ; %.preheader3.i.i.i33.i
                                        ;   Parent Loop BB2_26 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[7:8], v2, s[16:17] offset:40
	global_load_b64 v[11:12], v2, s[16:17]
	v_dual_mov_b32 v14, v4 :: v_dual_mov_b32 v13, v3
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v7, v7, v13
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[3:4], null, v7, 24, v[11:12]
	v_and_b32_e32 v11, v8, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[7:8], null, v11, 24, v[4:5]
	v_mov_b32_e32 v4, v7
	global_load_b64 v[11:12], v[3:4], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[3:4], v2, v[11:14], s[16:17] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[3:4], v[13:14]
	s_or_b32 s22, vcc_lo, s22
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s22
	s_cbranch_execnz .LBB2_178
; %bb.179:                              ; %Flow330
                                        ;   in Loop: Header=BB2_26 Depth=1
	s_or_b32 exec_lo, exec_lo, s22
.LBB2_180:                              ; %Flow332
                                        ;   in Loop: Header=BB2_26 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s21
.LBB2_181:                              ; %.loopexit4.i.i.i27.i
                                        ;   in Loop: Header=BB2_26 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_clause 0x1
	global_load_b64 v[7:8], v2, s[16:17] offset:40
	global_load_b128 v[13:16], v2, s[16:17]
	v_readfirstlane_b32 s24, v3
	v_readfirstlane_b32 s25, v4
	s_mov_b32 s21, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s22, v7
	v_readfirstlane_b32 s23, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[22:23], s[24:25], s[22:23]
	s_mul_i32 s1, s23, 24
	s_mul_hi_u32 s26, s22, 24
	s_mul_i32 s27, s22, 24
	s_and_saveexec_b32 s28, s0
	s_cbranch_execz .LBB2_183
; %bb.182:                              ;   in Loop: Header=BB2_26 Depth=1
	s_add_i32 s29, s26, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v7, vcc_lo, v13, s27
	v_add_co_ci_u32_e32 v8, vcc_lo, s29, v14, vcc_lo
	v_dual_mov_b32 v3, s21 :: v_dual_mov_b32 v4, v2
	global_store_b128 v[7:8], v[3:6], off offset:8
.LBB2_183:                              ;   in Loop: Header=BB2_26 Depth=1
	s_or_b32 exec_lo, exec_lo, s28
	s_lshl_b64 s[22:23], s[22:23], 12
	v_lshlrev_b64 v[3:4], 6, v[1:2]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v1, vcc_lo, v15, s22
	v_add_co_ci_u32_e32 v7, vcc_lo, s23, v16, vcc_lo
	s_mov_b32 s21, s20
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, v1, v3
	s_mov_b32 s22, s20
	s_mov_b32 s23, s20
	v_and_or_b32 v9, 0xffffff1f, v9, 32
	v_add_co_ci_u32_e32 v4, vcc_lo, v7, v4, vcc_lo
	v_dual_mov_b32 v11, v29 :: v_dual_mov_b32 v12, v2
	v_dual_mov_b32 v15, s20 :: v_dual_mov_b32 v16, s21
	v_dual_mov_b32 v17, s22 :: v_dual_mov_b32 v18, s23
	s_clause 0x3
	global_store_b128 v[3:4], v[9:12], off
	global_store_b128 v[3:4], v[15:18], off offset:16
	global_store_b128 v[3:4], v[15:18], off offset:32
	global_store_b128 v[3:4], v[15:18], off offset:48
	s_and_saveexec_b32 s21, s0
	s_cbranch_execz .LBB2_191
; %bb.184:                              ;   in Loop: Header=BB2_26 Depth=1
	s_clause 0x1
	global_load_b64 v[17:18], v2, s[16:17] offset:32 glc
	global_load_b64 v[7:8], v2, s[16:17] offset:40
	v_dual_mov_b32 v15, s24 :: v_dual_mov_b32 v16, s25
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s22, v7
	v_readfirstlane_b32 s23, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[22:23], s[22:23], s[24:25]
	s_mul_i32 s23, s23, 24
	s_mul_hi_u32 s28, s22, 24
	s_mul_i32 s22, s22, 24
	s_add_i32 s28, s28, s23
	v_add_co_u32 v11, vcc_lo, v13, s22
	v_add_co_ci_u32_e32 v12, vcc_lo, s28, v14, vcc_lo
	s_mov_b32 s22, exec_lo
	global_store_b64 v[11:12], v[17:18], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[9:10], v2, v[15:18], s[16:17] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[9:10], v[17:18]
	s_cbranch_execz .LBB2_187
; %bb.185:                              ; %.preheader1.i.i.i31.i.preheader
                                        ;   in Loop: Header=BB2_26 Depth=1
	s_mov_b32 s23, 0
.LBB2_186:                              ; %.preheader1.i.i.i31.i
                                        ;   Parent Loop BB2_26 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_dual_mov_b32 v7, s24 :: v_dual_mov_b32 v8, s25
	s_sleep 1
	global_store_b64 v[11:12], v[9:10], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[7:8], v2, v[7:10], s[16:17] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[9:10]
	v_dual_mov_b32 v10, v8 :: v_dual_mov_b32 v9, v7
	s_or_b32 s23, vcc_lo, s23
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s23
	s_cbranch_execnz .LBB2_186
.LBB2_187:                              ; %Flow328
                                        ;   in Loop: Header=BB2_26 Depth=1
	s_or_b32 exec_lo, exec_lo, s22
	global_load_b64 v[7:8], v2, s[16:17] offset:16
	s_mov_b32 s23, exec_lo
	s_mov_b32 s22, exec_lo
	v_mbcnt_lo_u32_b32 v1, s23, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v1
	s_cbranch_execz .LBB2_189
; %bb.188:                              ;   in Loop: Header=BB2_26 Depth=1
	s_bcnt1_i32_b32 s23, s23
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v1, s23
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[7:8], v[1:2], off offset:8
.LBB2_189:                              ;   in Loop: Header=BB2_26 Depth=1
	s_or_b32 exec_lo, exec_lo, s22
	s_waitcnt vmcnt(0)
	global_load_b64 v[9:10], v[7:8], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[9:10]
	s_cbranch_vccnz .LBB2_191
; %bb.190:                              ;   in Loop: Header=BB2_26 Depth=1
	global_load_b32 v1, v[7:8], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s22, v1
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[9:10], v[1:2], off
	s_and_b32 m0, s22, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB2_191:                              ; %Flow329
                                        ;   in Loop: Header=BB2_26 Depth=1
	s_or_b32 exec_lo, exec_lo, s21
	s_add_i32 s26, s26, s1
	v_add_co_u32 v1, vcc_lo, v13, s27
	v_add_co_ci_u32_e32 v8, vcc_lo, s26, v14, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v7, vcc_lo, v1, 20
	v_add_co_ci_u32_e32 v8, vcc_lo, 0, v8, vcc_lo
.LBB2_192:                              ;   Parent Loop BB2_26 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_mov_b32_e32 v1, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB2_194
; %bb.193:                              ;   in Loop: Header=BB2_192 Depth=2
	global_load_b32 v1, v[7:8], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v1, 1, v1
.LBB2_194:                              ;   in Loop: Header=BB2_192 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v1
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB2_196
; %bb.195:                              ;   in Loop: Header=BB2_192 Depth=2
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB2_197
.LBB2_196:                              ;   in Loop: Header=BB2_192 Depth=2
	s_mov_b32 s1, -1
.LBB2_197:                              ; %Flow323
                                        ;   in Loop: Header=BB2_192 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB2_192
; %bb.198:                              ;   in Loop: Header=BB2_26 Depth=1
	global_load_b64 v[7:8], v[3:4], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB2_202
; %bb.199:                              ;   in Loop: Header=BB2_26 Depth=1
	s_clause 0x2
	global_load_b64 v[3:4], v2, s[16:17] offset:40
	global_load_b64 v[13:14], v2, s[16:17] offset:24 glc
	global_load_b64 v[11:12], v2, s[16:17]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v1, vcc_lo, v3, 1
	v_add_co_ci_u32_e32 v15, vcc_lo, 0, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v9, vcc_lo, v1, s24
	v_add_co_ci_u32_e32 v10, vcc_lo, s25, v15, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[9:10]
	v_dual_cndmask_b32 v10, v10, v15 :: v_dual_cndmask_b32 v9, v9, v1
	v_and_b32_e32 v1, v10, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v3, v9, v3
	v_mul_lo_u32 v1, v1, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v4, v3, 24
	v_mul_lo_u32 v3, v3, 24
	v_add_nc_u32_e32 v1, v4, v1
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v3, vcc_lo, v11, v3
	v_mov_b32_e32 v11, v13
	v_add_co_ci_u32_e32 v4, vcc_lo, v12, v1, vcc_lo
	v_mov_b32_e32 v12, v14
	global_store_b64 v[3:4], v[13:14], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[11:12], v2, v[9:12], s[16:17] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[11:12], v[13:14]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB2_202
; %bb.200:                              ; %.preheader.i.i.i30.i.preheader
                                        ;   in Loop: Header=BB2_26 Depth=1
	s_mov_b32 s0, 0
.LBB2_201:                              ; %.preheader.i.i.i30.i
                                        ;   Parent Loop BB2_26 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	global_store_b64 v[3:4], v[11:12], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[13:14], v2, v[9:12], s[16:17] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[13:14], v[11:12]
	v_dual_mov_b32 v11, v13 :: v_dual_mov_b32 v12, v14
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB2_201
.LBB2_202:                              ; %__ockl_printf_append_args.exit.i
                                        ;   in Loop: Header=BB2_26 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	v_mov_b32_e32 v1, v35
	v_mov_b32_e32 v3, 0
	v_mov_b32_e32 v4, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s0, v1
	v_cmp_eq_u32_e64 s0, s0, v1
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB2_208
; %bb.203:                              ;   in Loop: Header=BB2_26 Depth=1
	global_load_b64 v[11:12], v2, s[16:17] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[3:4], v2, s[16:17] offset:40
	global_load_b64 v[9:10], v2, s[16:17]
	s_mov_b32 s21, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v4, v4, v12
	v_and_b32_e32 v3, v3, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v4, v4, 24
	v_mul_hi_u32 v13, v3, 24
	v_mul_lo_u32 v3, v3, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v4, v13, v4
	s_waitcnt vmcnt(0)
	v_add_co_u32 v3, vcc_lo, v9, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, v10, v4, vcc_lo
	global_load_b64 v[9:10], v[3:4], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[3:4], v2, v[9:12], s[16:17] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[3:4], v[11:12]
	s_cbranch_execz .LBB2_207
; %bb.204:                              ; %.preheader3.i.i.i40.i.preheader
                                        ;   in Loop: Header=BB2_26 Depth=1
	s_mov_b32 s22, 0
.LBB2_205:                              ; %.preheader3.i.i.i40.i
                                        ;   Parent Loop BB2_26 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[9:10], v2, s[16:17] offset:40
	global_load_b64 v[13:14], v2, s[16:17]
	v_dual_mov_b32 v12, v4 :: v_dual_mov_b32 v11, v3
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v9, v9, v11
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[3:4], null, v9, 24, v[13:14]
	v_and_b32_e32 v13, v10, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[9:10], null, v13, 24, v[4:5]
	v_mov_b32_e32 v4, v9
	global_load_b64 v[9:10], v[3:4], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[3:4], v2, v[9:12], s[16:17] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[3:4], v[11:12]
	s_or_b32 s22, vcc_lo, s22
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s22
	s_cbranch_execnz .LBB2_205
; %bb.206:                              ; %Flow316
                                        ;   in Loop: Header=BB2_26 Depth=1
	s_or_b32 exec_lo, exec_lo, s22
.LBB2_207:                              ; %Flow318
                                        ;   in Loop: Header=BB2_26 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s21
.LBB2_208:                              ; %.loopexit4.i.i.i34.i
                                        ;   in Loop: Header=BB2_26 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_clause 0x1
	global_load_b64 v[9:10], v2, s[16:17] offset:40
	global_load_b128 v[11:14], v2, s[16:17]
	v_readfirstlane_b32 s24, v3
	v_readfirstlane_b32 s25, v4
	s_mov_b32 s21, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s22, v9
	v_readfirstlane_b32 s23, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[22:23], s[24:25], s[22:23]
	s_mul_i32 s1, s23, 24
	s_mul_hi_u32 s26, s22, 24
	s_mul_i32 s27, s22, 24
	s_and_saveexec_b32 s28, s0
	s_cbranch_execz .LBB2_210
; %bb.209:                              ;   in Loop: Header=BB2_26 Depth=1
	s_add_i32 s29, s26, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v9, vcc_lo, v11, s27
	v_add_co_ci_u32_e32 v10, vcc_lo, s29, v12, vcc_lo
	v_dual_mov_b32 v3, s21 :: v_dual_mov_b32 v4, v2
	global_store_b128 v[9:10], v[3:6], off offset:8
.LBB2_210:                              ;   in Loop: Header=BB2_26 Depth=1
	s_or_b32 exec_lo, exec_lo, s28
	s_lshl_b64 s[22:23], s[22:23], 12
	v_lshlrev_b64 v[3:4], 6, v[1:2]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v1, vcc_lo, v13, s22
	v_add_co_ci_u32_e32 v9, vcc_lo, s23, v14, vcc_lo
	s_mov_b32 s21, s20
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, v1, v3
	s_mov_b32 s22, s20
	s_mov_b32 s23, s20
	v_and_or_b32 v7, 0xffffff1d, v7, 34
	v_add_co_ci_u32_e32 v4, vcc_lo, v9, v4, vcc_lo
	v_dual_mov_b32 v9, s15 :: v_dual_mov_b32 v10, s14
	v_dual_mov_b32 v13, s20 :: v_dual_mov_b32 v14, s21
	v_dual_mov_b32 v15, s22 :: v_dual_mov_b32 v16, s23
	s_clause 0x3
	global_store_b128 v[3:4], v[7:10], off
	global_store_b128 v[3:4], v[13:16], off offset:16
	global_store_b128 v[3:4], v[13:16], off offset:32
	global_store_b128 v[3:4], v[13:16], off offset:48
	s_and_saveexec_b32 s21, s0
	s_cbranch_execz .LBB2_218
; %bb.211:                              ;   in Loop: Header=BB2_26 Depth=1
	s_clause 0x1
	global_load_b64 v[15:16], v2, s[16:17] offset:32 glc
	global_load_b64 v[3:4], v2, s[16:17] offset:40
	v_dual_mov_b32 v13, s24 :: v_dual_mov_b32 v14, s25
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s22, v3
	v_readfirstlane_b32 s23, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[22:23], s[22:23], s[24:25]
	s_mul_i32 s23, s23, 24
	s_mul_hi_u32 s28, s22, 24
	s_mul_i32 s22, s22, 24
	s_add_i32 s28, s28, s23
	v_add_co_u32 v3, vcc_lo, v11, s22
	v_add_co_ci_u32_e32 v4, vcc_lo, s28, v12, vcc_lo
	s_mov_b32 s22, exec_lo
	global_store_b64 v[3:4], v[15:16], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[9:10], v2, v[13:16], s[16:17] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[9:10], v[15:16]
	s_cbranch_execz .LBB2_214
; %bb.212:                              ; %.preheader1.i.i.i38.i.preheader
                                        ;   in Loop: Header=BB2_26 Depth=1
	s_mov_b32 s23, 0
.LBB2_213:                              ; %.preheader1.i.i.i38.i
                                        ;   Parent Loop BB2_26 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_dual_mov_b32 v7, s24 :: v_dual_mov_b32 v8, s25
	s_sleep 1
	global_store_b64 v[3:4], v[9:10], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[7:8], v2, v[7:10], s[16:17] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[9:10]
	v_dual_mov_b32 v10, v8 :: v_dual_mov_b32 v9, v7
	s_or_b32 s23, vcc_lo, s23
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s23
	s_cbranch_execnz .LBB2_213
.LBB2_214:                              ; %Flow314
                                        ;   in Loop: Header=BB2_26 Depth=1
	s_or_b32 exec_lo, exec_lo, s22
	global_load_b64 v[3:4], v2, s[16:17] offset:16
	s_mov_b32 s23, exec_lo
	s_mov_b32 s22, exec_lo
	v_mbcnt_lo_u32_b32 v1, s23, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v1
	s_cbranch_execz .LBB2_216
; %bb.215:                              ;   in Loop: Header=BB2_26 Depth=1
	s_bcnt1_i32_b32 s23, s23
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v1, s23
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[3:4], v[1:2], off offset:8
.LBB2_216:                              ;   in Loop: Header=BB2_26 Depth=1
	s_or_b32 exec_lo, exec_lo, s22
	s_waitcnt vmcnt(0)
	global_load_b64 v[7:8], v[3:4], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[7:8]
	s_cbranch_vccnz .LBB2_218
; %bb.217:                              ;   in Loop: Header=BB2_26 Depth=1
	global_load_b32 v1, v[3:4], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s22, v1
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[7:8], v[1:2], off
	s_and_b32 m0, s22, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB2_218:                              ; %Flow315
                                        ;   in Loop: Header=BB2_26 Depth=1
	s_or_b32 exec_lo, exec_lo, s21
	s_add_i32 s26, s26, s1
	v_add_co_u32 v1, vcc_lo, v11, s27
	v_add_co_ci_u32_e32 v4, vcc_lo, s26, v12, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, v1, 20
	v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
.LBB2_219:                              ;   Parent Loop BB2_26 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_mov_b32_e32 v1, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB2_221
; %bb.220:                              ;   in Loop: Header=BB2_219 Depth=2
	global_load_b32 v1, v[3:4], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v1, 1, v1
.LBB2_221:                              ;   in Loop: Header=BB2_219 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v1
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB2_223
; %bb.222:                              ;   in Loop: Header=BB2_219 Depth=2
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB2_224
.LBB2_223:                              ;   in Loop: Header=BB2_219 Depth=2
	s_mov_b32 s1, -1
.LBB2_224:                              ; %Flow309
                                        ;   in Loop: Header=BB2_219 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB2_219
; %bb.225:                              ;   in Loop: Header=BB2_26 Depth=1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB2_229
; %bb.226:                              ;   in Loop: Header=BB2_26 Depth=1
	s_clause 0x2
	global_load_b64 v[3:4], v2, s[16:17] offset:40
	global_load_b64 v[11:12], v2, s[16:17] offset:24 glc
	global_load_b64 v[9:10], v2, s[16:17]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v1, vcc_lo, v3, 1
	v_add_co_ci_u32_e32 v13, vcc_lo, 0, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v7, vcc_lo, v1, s24
	v_add_co_ci_u32_e32 v8, vcc_lo, s25, v13, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[7:8]
	v_cndmask_b32_e32 v7, v7, v1, vcc_lo
	v_dual_cndmask_b32 v8, v8, v13 :: v_dual_and_b32 v3, v7, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v1, v8, v4
	v_mul_hi_u32 v4, v3, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v1, v1, 24
	v_mul_lo_u32 v3, v3, 24
	v_add_nc_u32_e32 v1, v4, v1
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v3, vcc_lo, v9, v3
	v_mov_b32_e32 v9, v11
	v_add_co_ci_u32_e32 v4, vcc_lo, v10, v1, vcc_lo
	v_mov_b32_e32 v10, v12
	global_store_b64 v[3:4], v[11:12], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[9:10], v2, v[7:10], s[16:17] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[9:10], v[11:12]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB2_229
; %bb.227:                              ; %.preheader.i.i.i37.i.preheader
                                        ;   in Loop: Header=BB2_26 Depth=1
	s_mov_b32 s0, 0
.LBB2_228:                              ; %.preheader.i.i.i37.i
                                        ;   Parent Loop BB2_26 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	global_store_b64 v[3:4], v[9:10], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[11:12], v2, v[7:10], s[16:17] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[11:12], v[9:10]
	v_dual_mov_b32 v9, v11 :: v_dual_mov_b32 v10, v12
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB2_228
.LBB2_229:                              ; %Flow307
                                        ;   in Loop: Header=BB2_26 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 s33, s33, exec_lo
	s_and_not1_b32 s34, s34, exec_lo
.LBB2_230:                              ; %Flow415
                                        ;   in Loop: Header=BB2_26 Depth=1
	s_or_b32 exec_lo, exec_lo, s35
	v_dual_mov_b32 v3, s4 :: v_dual_mov_b32 v4, s5
	s_and_saveexec_b32 s0, s34
; %bb.231:                              ;   in Loop: Header=BB2_26 Depth=1
	v_dual_mov_b32 v3, s6 :: v_dual_mov_b32 v4, s7
	s_or_b32 s33, s33, exec_lo
; %bb.232:                              ; %Flow416
                                        ;   in Loop: Header=BB2_26 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	s_and_saveexec_b32 s0, s33
	s_cbranch_execz .LBB2_234
; %bb.233:                              ; %__ockl_printf_append_args.exit41.sink.split.i
                                        ;   in Loop: Header=BB2_26 Depth=1
	v_add_co_u32 v7, vcc_lo, v32, s12
	v_add_co_ci_u32_e32 v8, vcc_lo, s13, v33, vcc_lo
	global_load_b32 v7, v[7:8], off
	s_waitcnt vmcnt(0)
	v_ashrrev_i32_e32 v8, 31, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[7:8], 2, v[7:8]
	v_add_co_u32 v3, vcc_lo, v3, v7
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, v4, v8, vcc_lo
	global_load_b32 v1, v[3:4], off
	v_add_co_u32 v3, vcc_lo, s8, v30
	v_add_co_ci_u32_e32 v4, vcc_lo, s9, v31, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b32 v[3:4], v1, off
.LBB2_234:                              ; %__ockl_printf_append_args.exit41.i
                                        ;   in Loop: Header=BB2_26 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	v_add_nc_u32_e32 v29, v29, v34
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_le_i32_e32 vcc_lo, s18, v29
	s_or_b32 s19, vcc_lo, s19
	s_and_not1_b32 exec_lo, exec_lo, s19
	s_cbranch_execnz .LBB2_26
.LBB2_235:                              ; %_Z10mergeBig_kPiS_S_S_iii.exit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z15sortManager_GPUPiS_S_S_iii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 304
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 39
		.amdhsa_next_free_sgpr 40
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_Z15sortManager_GPUPiS_S_S_iii, .Lfunc_end2-_Z15sortManager_GPUPiS_S_S_iii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 9232
; NumSgprs: 42
; NumVgprs: 39
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 5
; VGPRBlocks: 4
; NumSGPRsForWavesPerEU: 42
; NumVGPRsForWavesPerEU: 39
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	.str,@object                    ; @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.str:
	.asciz	"ERROR thread num %d block %d"
	.size	.str, 29

	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .offset:         12
        .size:           4
        .value_kind:     by_value
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
    .group_segment_fixed_size: 4096
    .kernarg_segment_align: 8
    .kernarg_segment_size: 24
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z17small_sortManagerPiiiii
    .private_segment_fixed_size: 0
    .sgpr_count:     24
    .sgpr_spill_count: 0
    .symbol:         _Z17small_sortManagerPiiiii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     9
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .offset:         12
        .size:           4
        .value_kind:     by_value
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
    .group_segment_fixed_size: 4096
    .kernarg_segment_align: 8
    .kernarg_segment_size: 32
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z28small_sortManager_extraSlicePiiiiiii
    .private_segment_fixed_size: 0
    .sgpr_count:     29
    .sgpr_spill_count: 0
    .symbol:         _Z28small_sortManager_extraSlicePiiiiiii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     9
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         36
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         52
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         60
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         62
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         64
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         66
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         68
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         70
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         112
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         128
        .size:           8
        .value_kind:     hidden_hostcall_buffer
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 304
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z15sortManager_GPUPiS_S_S_iii
    .private_segment_fixed_size: 0
    .sgpr_count:     42
    .sgpr_spill_count: 0
    .symbol:         _Z15sortManager_GPUPiS_S_S_iii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     39
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
