#include <stdio.h>
#include <stdlib.h>
#include <time.h>

#define R 4096
#define C 4096
#define BLOCK_W 32
#define BLOCK_H 32

float *a, *b, *result;

__global__ void multiple(float *A, float *B, float *res){
    int row = blockIdx.y * blockDim.y + threadIdx.y;
    int col = blockIdx.x * blockDim.x + threadIdx.x;

    float ret = 0;

    for (int i = 0; i < C; i += BLOCK_W){
        for (int j = i; j < i + BLOCK_W; j++){
            ret += A[row * C + j] * B[j * C + col];
        }
    }

    res[row * C + col] = ret;
}

int main(){
  float *d_a, *d_b, *d_r;
  cudaEvent_t start, end;
  float etime;
  dim3 block(BLOCK_W, BLOCK_H);
  dim3 grid(C/BLOCK_W, R/BLOCK_H);

  a = (float*)malloc(sizeof(float)*R*C);
  b = (float*)malloc(sizeof(float)*R*C);
  result = (float*)malloc(sizeof(float)*R*C);

  cudaEventCreate(&start);
	cudaEventCreate(&end);
	srand(time(NULL));

  // random number creation
	for (int i = 0; i < R; i++)
    for (int j = 0; j < C; j++){
       a[i * C + j] = (rand() % 1000000) / (float)10000;
       b[i * C + j] = (rand() % 1000000) / (float)10000;
    }

  // cuda var initialization
  cudaMalloc((void**)&d_a, sizeof(float)*R*C);
  cudaMalloc((void**)&d_b, sizeof(float)*R*C);
  cudaMalloc((void**)&d_r, sizeof(float)*R*C);
  

  // kernel call & exec time check
  cudaEventRecord(start, 0);
  cudaMemcpy(d_a, a, sizeof(float)*R*C, cudaMemcpyHostToDevice);
  cudaMemcpy(d_b, b, sizeof(float)*R*C, cudaMemcpyHostToDevice);
	multiple<<<grid, block>>>(d_a, d_b, d_r);
  cudaMemcpy(result, d_r, sizeof(float)*R*C, cudaMemcpyDeviceToHost);
	cudaEventRecord(end, 0);
	cudaEventSynchronize(end);
	cudaEventElapsedTime(&etime, start, end);

	printf("EXEC TIME : %f ms\n", etime);

  cudaEventDestroy(start);
	cudaEventDestroy(end);
  cudaFree(d_a);
  cudaFree(d_b);
  cudaFree(d_r);

	return 0;
}
	.file	"tmpxft_0024fc6b_00000000-6_matrixMul_1.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2030:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z31__device_stub__Z8multiplePfS_S_PfS_S_
	.type	_Z31__device_stub__Z8multiplePfS_S_PfS_S_, @function
_Z31__device_stub__Z8multiplePfS_S_PfS_S_:
.LFB2052:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z8multiplePfS_S_(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L2:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2052:
	.size	_Z31__device_stub__Z8multiplePfS_S_PfS_S_, .-_Z31__device_stub__Z8multiplePfS_S_PfS_S_
	.globl	_Z8multiplePfS_S_
	.type	_Z8multiplePfS_S_, @function
_Z8multiplePfS_S_:
.LFB2053:
	.cfi_startproc
	endbr64
	jmp	_Z31__device_stub__Z8multiplePfS_S_PfS_S_
	.cfi_endproc
.LFE2053:
	.size	_Z8multiplePfS_S_, .-_Z8multiplePfS_S_
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC1:
	.string	"EXEC TIME : %f ms\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	movl	$67108864, %edi
	pushq	%r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	pushq	%rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	xorl	%ebp, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	subq	$88, %rsp
	.cfi_def_cfa_offset 128
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	movabsq	$137438953504, %rax
	movl	$1, 56(%rsp)
	movl	$1, 68(%rsp)
	movq	%rax, 48(%rsp)
	movabsq	$549755814016, %rax
	movq	%rax, 60(%rsp)
	call	malloc@PLT
	movl	$67108864, %edi
	movq	%rax, a(%rip)
	call	malloc@PLT
	movl	$67108864, %edi
	movq	%rax, b(%rip)
	call	malloc@PLT
	leaq	32(%rsp), %rdi
	movq	%rax, result(%rip)
	call	cudaEventCreate@PLT
	leaq	40(%rsp), %rdi
	call	cudaEventCreate@PLT
	xorl	%edi, %edi
	call	time@PLT
	movl	%eax, %edi
	call	srand@PLT
.L9:
	xorl	%ebx, %ebx
.L10:
	call	rand@PLT
	movl	$1000000, %r12d
	leaq	0(%rbp,%rbx,4), %r13
	incq	%rbx
	cltd
	idivl	%r12d
	movq	a(%rip), %rax
	cvtsi2ssl	%edx, %xmm0
	divss	.LC0(%rip), %xmm0
	movss	%xmm0, (%rax,%r13)
	call	rand@PLT
	cltd
	idivl	%r12d
	movq	b(%rip), %rax
	cvtsi2ssl	%edx, %xmm0
	divss	.LC0(%rip), %xmm0
	movss	%xmm0, (%rax,%r13)
	cmpq	$4096, %rbx
	jne	.L10
	addq	$16384, %rbp
	cmpq	$67108864, %rbp
	jne	.L9
	leaq	8(%rsp), %rdi
	movl	$67108864, %esi
	call	cudaMalloc@PLT
	leaq	16(%rsp), %rdi
	movl	$67108864, %esi
	call	cudaMalloc@PLT
	leaq	24(%rsp), %rdi
	movl	$67108864, %esi
	call	cudaMalloc@PLT
	movq	32(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movq	8(%rsp), %rdi
	movl	$1, %ecx
	movq	a(%rip), %rsi
	movl	$67108864, %edx
	call	cudaMemcpy@PLT
	movq	16(%rsp), %rdi
	movl	$1, %ecx
	movq	b(%rip), %rsi
	movl	$67108864, %edx
	call	cudaMemcpy@PLT
	movl	56(%rsp), %ecx
	movl	68(%rsp), %esi
	xorl	%r9d, %r9d
	movq	48(%rsp), %rdx
	movq	60(%rsp), %rdi
	xorl	%r8d, %r8d
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L12
	movq	24(%rsp), %rdx
	movq	16(%rsp), %rsi
	movq	8(%rsp), %rdi
	call	_Z31__device_stub__Z8multiplePfS_S_PfS_S_
.L12:
	movq	24(%rsp), %rsi
	movl	$2, %ecx
	movl	$67108864, %edx
	movq	result(%rip), %rdi
	call	cudaMemcpy@PLT
	movq	40(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movq	40(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movq	40(%rsp), %rdx
	movq	32(%rsp), %rsi
	leaq	4(%rsp), %rdi
	call	cudaEventElapsedTime@PLT
	leaq	.LC1(%rip), %rsi
	movl	$2, %edi
	movb	$1, %al
	cvtss2sd	4(%rsp), %xmm0
	call	__printf_chk@PLT
	movq	32(%rsp), %rdi
	call	cudaEventDestroy@PLT
	movq	40(%rsp), %rdi
	call	cudaEventDestroy@PLT
	movq	8(%rsp), %rdi
	call	cudaFree@PLT
	movq	16(%rsp), %rdi
	call	cudaFree@PLT
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L13
	call	__stack_chk_fail@PLT
.L13:
	addq	$88, %rsp
	.cfi_def_cfa_offset 40
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2027:
	.size	main, .-main
	.section	.rodata.str1.1
.LC2:
	.string	"_Z8multiplePfS_S_"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC2(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z8multiplePfS_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2055:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.globl	result
	.bss
	.align 8
	.type	result, @object
	.size	result, 8
result:
	.zero	8
	.globl	b
	.align 8
	.type	b, @object
	.size	b, 8
b:
	.zero	8
	.globl	a
	.align 8
	.type	a, @object
	.size	a, 8
a:
	.zero	8
	.section	.rodata.cst4,"aM",@progbits,4
	.align 4
.LC0:
	.long	1176256512
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>

#define R 4096
#define C 4096
#define BLOCK_W 32
#define BLOCK_H 32

float *a, *b, *result;

__global__ void multiple(float *A, float *B, float *res){
    int row = blockIdx.y * blockDim.y + threadIdx.y;
    int col = blockIdx.x * blockDim.x + threadIdx.x;

    float ret = 0;

    for (int i = 0; i < C; i += BLOCK_W){
        for (int j = i; j < i + BLOCK_W; j++){
            ret += A[row * C + j] * B[j * C + col];
        }
    }

    res[row * C + col] = ret;
}

int main(){
  float *d_a, *d_b, *d_r;
  hipEvent_t start, end;
  float etime;
  dim3 block(BLOCK_W, BLOCK_H);
  dim3 grid(C/BLOCK_W, R/BLOCK_H);

  a = (float*)malloc(sizeof(float)*R*C);
  b = (float*)malloc(sizeof(float)*R*C);
  result = (float*)malloc(sizeof(float)*R*C);

  hipEventCreate(&start);
	hipEventCreate(&end);
	srand(time(NULL));

  // random number creation
	for (int i = 0; i < R; i++)
    for (int j = 0; j < C; j++){
       a[i * C + j] = (rand() % 1000000) / (float)10000;
       b[i * C + j] = (rand() % 1000000) / (float)10000;
    }

  // cuda var initialization
  hipMalloc((void**)&d_a, sizeof(float)*R*C);
  hipMalloc((void**)&d_b, sizeof(float)*R*C);
  hipMalloc((void**)&d_r, sizeof(float)*R*C);
  

  // kernel call & exec time check
  hipEventRecord(start, 0);
  hipMemcpy(d_a, a, sizeof(float)*R*C, hipMemcpyHostToDevice);
  hipMemcpy(d_b, b, sizeof(float)*R*C, hipMemcpyHostToDevice);
	multiple<<<grid, block>>>(d_a, d_b, d_r);
  hipMemcpy(result, d_r, sizeof(float)*R*C, hipMemcpyDeviceToHost);
	hipEventRecord(end, 0);
	hipEventSynchronize(end);
	hipEventElapsedTime(&etime, start, end);

	printf("EXEC TIME : %f ms\n", etime);

  hipEventDestroy(start);
	hipEventDestroy(end);
  hipFree(d_a);
  hipFree(d_b);
  hipFree(d_r);

	return 0;
}
	.text
	.file	"matrixMul_1.hip"
	.globl	_Z23__device_stub__multiplePfS_S_ # -- Begin function _Z23__device_stub__multiplePfS_S_
	.type	_Z23__device_stub__multiplePfS_S_,@function
_Z23__device_stub__multiplePfS_S_:      # @_Z23__device_stub__multiplePfS_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z8multiplePfS_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z23__device_stub__multiplePfS_S_, .Lfunc_end0-_Z23__device_stub__multiplePfS_S_
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0                          # -- Begin function main
.LCPI1_0:
	.long	0x461c4000                      # float 1.0E+4
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r12
	.cfi_def_cfa_offset 32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	subq	$56, %rsp
	.cfi_def_cfa_offset 96
	.cfi_offset %rbx, -40
	.cfi_offset %r12, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movl	$67108864, %edi                 # imm = 0x4000000
	callq	malloc
	movq	%rax, a(%rip)
	movl	$67108864, %edi                 # imm = 0x4000000
	callq	malloc
	movq	%rax, b(%rip)
	movl	$67108864, %edi                 # imm = 0x4000000
	callq	malloc
	movq	%rax, result(%rip)
	leaq	16(%rsp), %rdi
	callq	hipEventCreate
	leaq	8(%rsp), %rdi
	callq	hipEventCreate
	xorl	%ebx, %ebx
	xorl	%edi, %edi
	callq	time
	movl	%eax, %edi
	callq	srand
	xorl	%r14d, %r14d
.LBB1_1:                                # %.preheader
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB1_2 Depth 2
	movl	$4096, %r15d                    # imm = 0x1000
	movq	%rbx, %r12
.LBB1_2:                                #   Parent Loop BB1_1 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	callq	rand
	cltq
	imulq	$1125899907, %rax, %rcx         # imm = 0x431BDE83
	movq	%rcx, %rdx
	shrq	$63, %rdx
	sarq	$50, %rcx
	addl	%edx, %ecx
	imull	$1000000, %ecx, %ecx            # imm = 0xF4240
	subl	%ecx, %eax
	xorps	%xmm0, %xmm0
	cvtsi2ss	%eax, %xmm0
	divss	.LCPI1_0(%rip), %xmm0
	movq	a(%rip), %rax
	movss	%xmm0, (%rax,%r12)
	callq	rand
	movss	.LCPI1_0(%rip), %xmm1           # xmm1 = mem[0],zero,zero,zero
	cltq
	imulq	$1125899907, %rax, %rcx         # imm = 0x431BDE83
	movq	%rcx, %rdx
	shrq	$63, %rdx
	sarq	$50, %rcx
	addl	%edx, %ecx
	imull	$1000000, %ecx, %ecx            # imm = 0xF4240
	subl	%ecx, %eax
	xorps	%xmm0, %xmm0
	cvtsi2ss	%eax, %xmm0
	divss	%xmm1, %xmm0
	movq	b(%rip), %rax
	movss	%xmm0, (%rax,%r12)
	addq	$4, %r12
	decq	%r15
	jne	.LBB1_2
# %bb.3:                                #   in Loop: Header=BB1_1 Depth=1
	incq	%r14
	addq	$16384, %rbx                    # imm = 0x4000
	cmpq	$4096, %r14                     # imm = 0x1000
	jne	.LBB1_1
# %bb.4:
	leaq	40(%rsp), %r14
	movl	$67108864, %esi                 # imm = 0x4000000
	movq	%r14, %rdi
	callq	hipMalloc
	leaq	32(%rsp), %rbx
	movl	$67108864, %esi                 # imm = 0x4000000
	movq	%rbx, %rdi
	callq	hipMalloc
	leaq	24(%rsp), %rdi
	movl	$67108864, %esi                 # imm = 0x4000000
	callq	hipMalloc
	movq	16(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	(%r14), %rdi
	movq	a(%rip), %rsi
	movl	$67108864, %edx                 # imm = 0x4000000
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%rbx), %rdi
	movq	b(%rip), %rsi
	movl	$67108864, %edx                 # imm = 0x4000000
	movl	$1, %ecx
	callq	hipMemcpy
	movabsq	$549755814016, %rdi             # imm = 0x8000000080
	movabsq	$137438953504, %rdx             # imm = 0x2000000020
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_6
# %bb.5:
	movq	40(%rsp), %rdi
	movq	32(%rsp), %rsi
	movq	24(%rsp), %rdx
	callq	_Z23__device_stub__multiplePfS_S_
.LBB1_6:
	movq	result(%rip), %rdi
	movq	24(%rsp), %rsi
	movl	$67108864, %edx                 # imm = 0x4000000
	movl	$2, %ecx
	callq	hipMemcpy
	movq	8(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	8(%rsp), %rdi
	callq	hipEventSynchronize
	movq	16(%rsp), %rsi
	movq	8(%rsp), %rdx
	leaq	52(%rsp), %rbx
	movq	%rbx, %rdi
	callq	hipEventElapsedTime
	xorps	%xmm0, %xmm0
	cvtss2sd	(%rbx), %xmm0
	movl	$.L.str, %edi
	movb	$1, %al
	callq	printf
	movq	16(%rsp), %rdi
	callq	hipEventDestroy
	movq	8(%rsp), %rdi
	callq	hipEventDestroy
	movq	40(%rsp), %rdi
	callq	hipFree
	movq	32(%rsp), %rdi
	callq	hipFree
	movq	24(%rsp), %rdi
	callq	hipFree
	xorl	%eax, %eax
	addq	$56, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	main, .Lfunc_end1-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z8multiplePfS_S_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	a,@object                       # @a
	.bss
	.globl	a
	.p2align	3, 0x0
a:
	.quad	0
	.size	a, 8

	.type	b,@object                       # @b
	.globl	b
	.p2align	3, 0x0
b:
	.quad	0
	.size	b, 8

	.type	result,@object                  # @result
	.globl	result
	.p2align	3, 0x0
result:
	.quad	0
	.size	result, 8

	.type	_Z8multiplePfS_S_,@object       # @_Z8multiplePfS_S_
	.section	.rodata,"a",@progbits
	.globl	_Z8multiplePfS_S_
	.p2align	3, 0x0
_Z8multiplePfS_S_:
	.quad	_Z23__device_stub__multiplePfS_S_
	.size	_Z8multiplePfS_S_, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"EXEC TIME : %f ms\n"
	.size	.L.str, 19

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z8multiplePfS_S_"
	.size	.L__unnamed_1, 18

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z23__device_stub__multiplePfS_S_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z8multiplePfS_S_
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z8multiplePfS_S_       ; -- Begin function _Z8multiplePfS_S_
	.globl	_Z8multiplePfS_S_
	.p2align	8
	.type	_Z8multiplePfS_S_,@function
_Z8multiplePfS_S_:                      ; @_Z8multiplePfS_S_
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x24
	s_load_b128 s[4:7], s[0:1], 0x0
	v_bfe_u32 v1, v0, 10, 10
	s_load_b64 s[0:1], s[0:1], 0x10
	v_and_b32_e32 v0, 0x3ff, v0
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s2, 16
	s_and_b32 s2, s2, 0xffff
	s_mul_i32 s15, s15, s3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_lshl_u32 v1, s15, v1, 12
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[5:6], 2, v[1:2]
	v_mad_u64_u32 v[2:3], null, s14, s2, v[0:1]
	v_mov_b32_e32 v0, 0
	v_add_co_u32 v5, vcc_lo, s4, v5
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
	v_mov_b32_e32 v7, v2
	s_mov_b32 s4, 0
.LBB0_1:                                ; %.preheader
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_2 Depth 2
	s_delay_alu instid0(VALU_DEP_1)
	v_mov_b32_e32 v3, v7
	s_mov_b64 s[2:3], 0
.LBB0_2:                                ;   Parent Loop BB0_1 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_ashrrev_i32_e32 v4, 31, v3
	v_add_co_u32 v8, vcc_lo, v5, s2
	v_add_co_ci_u32_e32 v9, vcc_lo, s3, v6, vcc_lo
	v_lshlrev_b64 v[10:11], 2, v[3:4]
	s_add_u32 s2, s2, 4
	s_addc_u32 s3, s3, 0
	s_cmpk_eq_i32 s2, 0x80
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v10, vcc_lo, s6, v10
	v_add_co_ci_u32_e32 v11, vcc_lo, s7, v11, vcc_lo
	global_load_b32 v4, v[8:9], off
	global_load_b32 v8, v[10:11], off
	s_waitcnt vmcnt(0)
	v_dual_fmac_f32 v0, v4, v8 :: v_dual_add_nc_u32 v3, 0x1000, v3
	s_cbranch_scc0 .LBB0_2
; %bb.3:                                ; %.loopexit
                                        ;   in Loop: Header=BB0_1 Depth=1
	v_add_co_u32 v5, vcc_lo, 0x80, v5
	v_add_nc_u32_e32 v7, 0x20000, v7
	v_add_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
	s_add_i32 s2, s4, 32
	s_cmpk_gt_u32 s4, 0xfdf
	s_cbranch_scc1 .LBB0_5
; %bb.4:                                ;   in Loop: Header=BB0_1 Depth=1
	s_mov_b32 s4, s2
	s_branch .LBB0_1
.LBB0_5:
	v_add_nc_u32_e32 v1, v1, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v2, 31, v1
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_store_b32 v[1:2], v0, off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z8multiplePfS_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 12
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z8multiplePfS_S_, .Lfunc_end0-_Z8multiplePfS_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 332
; NumSgprs: 18
; NumVgprs: 12
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 12
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z8multiplePfS_S_
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z8multiplePfS_S_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     12
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
