/**
 * Matrix multiplication Exercise : P = M . N.
 *
 * This program basically follows the tutorial in class.
 *
 * Given the 1024*1024 matrix test case, this program got the best performance
 * boost using TILE_WIDTH = 16. This was also suggested in the slide set.
 *
 * This exercise was executed on a MacBook Pro, with GeForce GT 650M
 * Using the CPU matrixMultiplication code, it takes about 18 seconds
 * Using this TILED approach, it only take about 0.13 ~0.15 seconds
 * 
 * See also:
 * Zhou Bin@ Nvidia & USTC, 2014, October, "CUDA Programming (2)" Lecture Slides
 * 
 *
 */

#include "stdio.h" 
#include "stdlib.h"

#include "cuda.h"
#include "cuda_runtime.h"


#define W 1024
#define TILE_WIDTH 16
#define DEBUG 1

void printMatrix(float *Matrix)
{
	const int MAX_SIZE_PRINTED = 4;
	
	printf("This is a %d by %d matrix.\n", W,W);
	
	if (W > MAX_SIZE_PRINTED) {
		printf("Actual displayed size is cut in 2 parts shown as");
		printf(" %d by %d matrix.\n", MAX_SIZE_PRINTED, MAX_SIZE_PRINTED);
		printf("   The Top_LEFT CORNER OF the %d * %d matrix:\n", W, W);
	}
	
	for(int i=0;i<W;i++)
	{
		  for(int j=0;j<W;j++)
		  	if(i < MAX_SIZE_PRINTED && j < MAX_SIZE_PRINTED){
		     if (DEBUG) printf("%5.2f ",*(Matrix+i*W+j));
			}
			if(i < MAX_SIZE_PRINTED && DEBUG) printf("\n");
	}
		
	if (W > MAX_SIZE_PRINTED){
		
		printf("   The LOWER_RIGHT CORNER OF the %d * %d matrix\n", W, W);
		
		for(int i=W-MAX_SIZE_PRINTED;i<W;i++)
		{
		  for(int j=W-MAX_SIZE_PRINTED;j<W;j++)
		  	if (DEBUG) printf("%5.2f ",*(Matrix+i*W+j));

			if(DEBUG) printf("\n");
		}
		
	}
		
}


/*
 *  This code is mostly copied from the slide set with some comments written by Ben Koo.
 *  
 *  In this test case, W = 1024, TILE_WIDTH = 16, making the dimGrid = 64 * 64
 *  Within each block, there are 16 * 16 threads.
 *
 *
 */
__global__ void matrixMulKernel_usingTile(float* Md, float* Nd, float* Pd, int Width)
{

	//This delcares the device memory as 16 * 16 float matrices
	__shared__ float Mds[TILE_WIDTH][TILE_WIDTH];
	__shared__ float Nds[TILE_WIDTH][TILE_WIDTH];

    // When W = 1024,t he block IDs (x * y) should be (64 * 64)
	int bx = blockIdx.x; int by = blockIdx.y;
	
    // When W = 1024, the thread IDs (x * y) should be (16 * 16)
	int tx = threadIdx.x; int ty = threadIdx.y;

	int Row = by * TILE_WIDTH + ty;
	int Col = bx * TILE_WIDTH + tx;



	float PValue = 0;
	
	// When W = 1024, m should go from 0 to 63
	for (int m =0; m < Width/TILE_WIDTH; ++m){
	  // The following memory access takes place in shared memory
	  Mds[ty][tx] = Md[Row*Width + (m*TILE_WIDTH + tx)];
	  Nds[ty][tx] = Nd[Col + (m*TILE_WIDTH+ty)*Width];
	  
	  //Make sure that all data are written in sync.
	  __syncthreads();

	  //Perform TILE level matrix multiplication and addition in synchrony.
	  for (int k = 0; k< TILE_WIDTH; ++k)	
		PValue += Mds[ty][k] * Nds[k][tx];
		__syncthreads();
	}
	
	//Take individually caldulated PValue and place it to the Pd (device memory array).
	Pd[Row * Width + Col] = PValue;
}
 
 
int main()
{
	int sNo = 0;
	cudaSetDevice(sNo%8);

	int size = W*W*sizeof(float);
 
	float *M,*N,*P;
	float *d_M,*d_N,*d_P;

	M = (float *) malloc(size);
	N = (float *) malloc(size);
	P = (float *) malloc(size);

	cudaMalloc((void **)&d_M,size);
	cudaMalloc((void **)&d_N,size);
	cudaMalloc((void **)&d_P,size);


    //Populate initial values to the M, N and P matrices
	for(int i=0;i<W*W;i++)
	{
	  *(M+i) = i;
      *(N+i) = i+1;
      *(P+i) = 0;
	}

    cudaMemcpy(d_M, M,size,cudaMemcpyHostToDevice);
    cudaMemcpy(d_N, N,size,cudaMemcpyHostToDevice);
	
	//Starting from here, set up CUDA timing mechanism
	float time_elapsed = 0;
	
	cudaEvent_t start, stop;

	cudaEventCreate(&start);
	cudaEventCreate(&stop);

	cudaEventRecord(start, 0);

	dim3 dimGrid(W /TILE_WIDTH, W / TILE_WIDTH);
	dim3 dimBlock(TILE_WIDTH, TILE_WIDTH);
		
	matrixMulKernel_usingTile<<< dimGrid, dimBlock >>>(d_M,d_N,d_P,W);
	
    cudaEventRecord(stop,0);

	cudaEventSynchronize(start);

	cudaEventSynchronize(stop);

	//The following function returns time_elapsed using milli-seconds as time units
	cudaEventElapsedTime(&time_elapsed, start, stop);
	
	//Finished timing for CUDA execution

    //To display time_elapsed into a number, divide it by 1000 first.
	printf("\n\nGPU Elapsed Time:%f\n", time_elapsed/1000);
	
        
    cudaMemcpy(P,d_P,size,cudaMemcpyDeviceToHost);

	printMatrix(P);
	
	free(M);free(N);free(P);
	cudaFree(d_M);cudaFree(d_N);cudaFree(d_P);

	return 0;

}


	.file	"tmpxft_0020daa3_00000000-6_Tiled_MatrixMul.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2031:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"This is a %d by %d matrix.\n"
.LC1:
	.string	"Actual displayed size is cut in 2 parts shown as"
.LC2:
	.string	" %d by %d matrix.\n"
.LC3:
	.string	"   The Top_LEFT CORNER OF the %d * %d matrix:\n"
.LC4:
	.string	"%5.2f "
.LC5:
	.string	"\n"
.LC6:
	.string	"   The LOWER_RIGHT CORNER OF the %d * %d matrix\n"
	.text
	.globl	_Z11printMatrixPf
	.type	_Z11printMatrixPf, @function
_Z11printMatrixPf:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%r14
	.cfi_def_cfa_offset 16
	.cfi_offset 14, -16
	movl	$1024, %ecx
	movl	$1024, %edx
	xorl	%eax, %eax
	pushq	%r13
	.cfi_def_cfa_offset 24
	.cfi_offset 13, -24
	leaq	.LC0(%rip), %rsi
	leaq	.LC4(%rip), %r13
	pushq	%r12
	.cfi_def_cfa_offset 32
	.cfi_offset 12, -32
	pushq	%rbp
	.cfi_def_cfa_offset 40
	.cfi_offset 6, -40
	movq	%rdi, %rbp
	movl	$2, %edi
	pushq	%rbx
	.cfi_def_cfa_offset 48
	.cfi_offset 3, -48
	xorl	%ebx, %ebx
	call	__printf_chk@PLT
	leaq	.LC1(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movl	$4, %ecx
	movl	$4, %edx
	xorl	%eax, %eax
	leaq	.LC2(%rip), %rsi
	movl	$2, %edi
	call	__printf_chk@PLT
	movl	$1024, %ecx
	movl	$1024, %edx
	xorl	%eax, %eax
	leaq	.LC3(%rip), %rsi
	movl	$2, %edi
	call	__printf_chk@PLT
.L3:
	movq	%rbx, %r12
	xorl	%eax, %eax
	salq	$12, %r12
	addq	%rbp, %r12
.L9:
	cmpl	$3, %ebx
	movl	%ebx, %edx
	leaq	1(%rax), %r14
	jg	.L4
	cmpl	$3, %eax
	jg	.L4
	cvtss2sd	(%r12,%rax,4), %xmm0
	movq	%r13, %rsi
	movl	$2, %edi
	movb	$1, %al
	call	__printf_chk@PLT
	movq	%r14, %rax
	jmp	.L9
.L4:
	movq	%r14, %rax
	cmpq	$1024, %r14
	jne	.L9
	cmpl	$3, %edx
	leaq	1(%rbx), %rbx
	jg	.L6
	leaq	.LC5(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	jmp	.L3
.L6:
	cmpq	$1024, %rbx
	jne	.L3
	movl	$1024, %ecx
	movl	$1024, %edx
	leaq	.LC6(%rip), %rsi
	xorl	%eax, %eax
	movl	$2, %edi
	movl	$1044480, %r12d
	leaq	.LC4(%rip), %r14
	call	__printf_chk@PLT
.L10:
	leaq	0(%rbp,%r12,4), %r13
	movl	$1020, %ebx
.L11:
	cvtss2sd	0(%r13,%rbx,4), %xmm0
	movq	%r14, %rsi
	movl	$2, %edi
	movb	$1, %al
	call	__printf_chk@PLT
	incq	%rbx
	cmpq	$1024, %rbx
	jne	.L11
	leaq	.LC5(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	addq	$1024, %r12
	call	__printf_chk@PLT
	cmpq	$1048576, %r12
	jne	.L10
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%rbp
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r13
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2027:
	.size	_Z11printMatrixPf, .-_Z11printMatrixPf
	.globl	_Z50__device_stub__Z25matrixMulKernel_usingTilePfS_S_iPfS_S_i
	.type	_Z50__device_stub__Z25matrixMulKernel_usingTilePfS_S_iPfS_S_i, @function
_Z50__device_stub__Z25matrixMulKernel_usingTilePfS_S_iPfS_S_i:
.LFB2053:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 4(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L22
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z25matrixMulKernel_usingTilePfS_S_i(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L22:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L24
	call	__stack_chk_fail@PLT
.L24:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2053:
	.size	_Z50__device_stub__Z25matrixMulKernel_usingTilePfS_S_iPfS_S_i, .-_Z50__device_stub__Z25matrixMulKernel_usingTilePfS_S_iPfS_S_i
	.globl	_Z25matrixMulKernel_usingTilePfS_S_i
	.type	_Z25matrixMulKernel_usingTilePfS_S_i, @function
_Z25matrixMulKernel_usingTilePfS_S_i:
.LFB2054:
	.cfi_startproc
	endbr64
	jmp	_Z50__device_stub__Z25matrixMulKernel_usingTilePfS_S_iPfS_S_i
	.cfi_endproc
.LFE2054:
	.size	_Z25matrixMulKernel_usingTilePfS_S_i, .-_Z25matrixMulKernel_usingTilePfS_S_i
	.section	.rodata.str1.1
.LC9:
	.string	"\n\nGPU Elapsed Time:%f\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2028:
	.cfi_startproc
	endbr64
	pushq	%r12
	.cfi_def_cfa_offset 16
	.cfi_offset 12, -16
	xorl	%edi, %edi
	pushq	%rbp
	.cfi_def_cfa_offset 24
	.cfi_offset 6, -24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset 3, -32
	subq	$80, %rsp
	.cfi_def_cfa_offset 112
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	xorl	%eax, %eax
	call	cudaSetDevice@PLT
	movl	$4194304, %edi
	call	malloc@PLT
	movl	$4194304, %edi
	movq	%rax, %r12
	call	malloc@PLT
	movl	$4194304, %edi
	movq	%rax, %rbp
	call	malloc@PLT
	leaq	8(%rsp), %rdi
	movl	$4194304, %esi
	movq	%rax, %rbx
	call	cudaMalloc@PLT
	leaq	16(%rsp), %rdi
	movl	$4194304, %esi
	call	cudaMalloc@PLT
	leaq	24(%rsp), %rdi
	movl	$4194304, %esi
	call	cudaMalloc@PLT
	xorl	%ecx, %ecx
.L28:
	cvtsi2ssl	%ecx, %xmm0
	leal	1(%rcx), %eax
	movss	%xmm0, (%r12,%rcx,4)
	cvtsi2ssl	%eax, %xmm0
	movss	%xmm0, 0(%rbp,%rcx,4)
	incq	%rcx
	cmpq	$1048576, %rcx
	jne	.L28
	xorl	%eax, %eax
	movq	%rbx, %rdi
	movl	$4194304, %edx
	movq	%r12, %rsi
	rep stosl
	movq	8(%rsp), %rdi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	movq	16(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbp, %rsi
	movl	$4194304, %edx
	call	cudaMemcpy@PLT
	leaq	32(%rsp), %rdi
	movl	$0x00000000, 4(%rsp)
	call	cudaEventCreate@PLT
	leaq	40(%rsp), %rdi
	call	cudaEventCreate@PLT
	movq	32(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$1, %ecx
	movabsq	$68719476752, %rdx
	movl	$1, %esi
	movabsq	$274877907008, %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L29
	movq	24(%rsp), %rdx
	movq	16(%rsp), %rsi
	movl	$1024, %ecx
	movq	8(%rsp), %rdi
	call	_Z50__device_stub__Z25matrixMulKernel_usingTilePfS_S_iPfS_S_i
.L29:
	movq	40(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movq	32(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movq	40(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movq	40(%rsp), %rdx
	movq	32(%rsp), %rsi
	leaq	4(%rsp), %rdi
	call	cudaEventElapsedTime@PLT
	leaq	.LC9(%rip), %rsi
	movl	$2, %edi
	movb	$1, %al
	movss	4(%rsp), %xmm0
	divss	.LC8(%rip), %xmm0
	cvtss2sd	%xmm0, %xmm0
	call	__printf_chk@PLT
	movq	24(%rsp), %rsi
	movl	$2, %ecx
	movq	%rbx, %rdi
	movl	$4194304, %edx
	call	cudaMemcpy@PLT
	movq	%rbx, %rdi
	call	_Z11printMatrixPf
	movq	%r12, %rdi
	call	free@PLT
	movq	%rbp, %rdi
	call	free@PLT
	movq	%rbx, %rdi
	call	free@PLT
	movq	8(%rsp), %rdi
	call	cudaFree@PLT
	movq	16(%rsp), %rdi
	call	cudaFree@PLT
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L30
	call	__stack_chk_fail@PLT
.L30:
	addq	$80, %rsp
	.cfi_def_cfa_offset 32
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2028:
	.size	main, .-main
	.section	.rodata.str1.1
.LC10:
	.string	"_Z25matrixMulKernel_usingTilePfS_S_i"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2056:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC10(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z25matrixMulKernel_usingTilePfS_S_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2056:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst4,"aM",@progbits,4
	.align 4
.LC8:
	.long	1148846080
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

/**
 * Matrix multiplication Exercise : P = M . N.
 *
 * This program basically follows the tutorial in class.
 *
 * Given the 1024*1024 matrix test case, this program got the best performance
 * boost using TILE_WIDTH = 16. This was also suggested in the slide set.
 *
 * This exercise was executed on a MacBook Pro, with GeForce GT 650M
 * Using the CPU matrixMultiplication code, it takes about 18 seconds
 * Using this TILED approach, it only take about 0.13 ~0.15 seconds
 * 
 * See also:
 * Zhou Bin@ Nvidia & USTC, 2014, October, "CUDA Programming (2)" Lecture Slides
 * 
 *
 */

#include "stdio.h" 
#include "stdlib.h"

#include "hip/hip_runtime.h"



#define W 1024
#define TILE_WIDTH 16
#define DEBUG 1

void printMatrix(float *Matrix)
{
	const int MAX_SIZE_PRINTED = 4;
	
	printf("This is a %d by %d matrix.\n", W,W);
	
	if (W > MAX_SIZE_PRINTED) {
		printf("Actual displayed size is cut in 2 parts shown as");
		printf(" %d by %d matrix.\n", MAX_SIZE_PRINTED, MAX_SIZE_PRINTED);
		printf("   The Top_LEFT CORNER OF the %d * %d matrix:\n", W, W);
	}
	
	for(int i=0;i<W;i++)
	{
		  for(int j=0;j<W;j++)
		  	if(i < MAX_SIZE_PRINTED && j < MAX_SIZE_PRINTED){
		     if (DEBUG) printf("%5.2f ",*(Matrix+i*W+j));
			}
			if(i < MAX_SIZE_PRINTED && DEBUG) printf("\n");
	}
		
	if (W > MAX_SIZE_PRINTED){
		
		printf("   The LOWER_RIGHT CORNER OF the %d * %d matrix\n", W, W);
		
		for(int i=W-MAX_SIZE_PRINTED;i<W;i++)
		{
		  for(int j=W-MAX_SIZE_PRINTED;j<W;j++)
		  	if (DEBUG) printf("%5.2f ",*(Matrix+i*W+j));

			if(DEBUG) printf("\n");
		}
		
	}
		
}


/*
 *  This code is mostly copied from the slide set with some comments written by Ben Koo.
 *  
 *  In this test case, W = 1024, TILE_WIDTH = 16, making the dimGrid = 64 * 64
 *  Within each block, there are 16 * 16 threads.
 *
 *
 */
__global__ void matrixMulKernel_usingTile(float* Md, float* Nd, float* Pd, int Width)
{

	//This delcares the device memory as 16 * 16 float matrices
	__shared__ float Mds[TILE_WIDTH][TILE_WIDTH];
	__shared__ float Nds[TILE_WIDTH][TILE_WIDTH];

    // When W = 1024,t he block IDs (x * y) should be (64 * 64)
	int bx = blockIdx.x; int by = blockIdx.y;
	
    // When W = 1024, the thread IDs (x * y) should be (16 * 16)
	int tx = threadIdx.x; int ty = threadIdx.y;

	int Row = by * TILE_WIDTH + ty;
	int Col = bx * TILE_WIDTH + tx;



	float PValue = 0;
	
	// When W = 1024, m should go from 0 to 63
	for (int m =0; m < Width/TILE_WIDTH; ++m){
	  // The following memory access takes place in shared memory
	  Mds[ty][tx] = Md[Row*Width + (m*TILE_WIDTH + tx)];
	  Nds[ty][tx] = Nd[Col + (m*TILE_WIDTH+ty)*Width];
	  
	  //Make sure that all data are written in sync.
	  __syncthreads();

	  //Perform TILE level matrix multiplication and addition in synchrony.
	  for (int k = 0; k< TILE_WIDTH; ++k)	
		PValue += Mds[ty][k] * Nds[k][tx];
		__syncthreads();
	}
	
	//Take individually caldulated PValue and place it to the Pd (device memory array).
	Pd[Row * Width + Col] = PValue;
}
 
 
int main()
{
	int sNo = 0;
	hipSetDevice(sNo%8);

	int size = W*W*sizeof(float);
 
	float *M,*N,*P;
	float *d_M,*d_N,*d_P;

	M = (float *) malloc(size);
	N = (float *) malloc(size);
	P = (float *) malloc(size);

	hipMalloc((void **)&d_M,size);
	hipMalloc((void **)&d_N,size);
	hipMalloc((void **)&d_P,size);


    //Populate initial values to the M, N and P matrices
	for(int i=0;i<W*W;i++)
	{
	  *(M+i) = i;
      *(N+i) = i+1;
      *(P+i) = 0;
	}

    hipMemcpy(d_M, M,size,hipMemcpyHostToDevice);
    hipMemcpy(d_N, N,size,hipMemcpyHostToDevice);
	
	//Starting from here, set up CUDA timing mechanism
	float time_elapsed = 0;
	
	hipEvent_t start, stop;

	hipEventCreate(&start);
	hipEventCreate(&stop);

	hipEventRecord(start, 0);

	dim3 dimGrid(W /TILE_WIDTH, W / TILE_WIDTH);
	dim3 dimBlock(TILE_WIDTH, TILE_WIDTH);
		
	matrixMulKernel_usingTile<<< dimGrid, dimBlock >>>(d_M,d_N,d_P,W);
	
    hipEventRecord(stop,0);

	hipEventSynchronize(start);

	hipEventSynchronize(stop);

	//The following function returns time_elapsed using milli-seconds as time units
	hipEventElapsedTime(&time_elapsed, start, stop);
	
	//Finished timing for CUDA execution

    //To display time_elapsed into a number, divide it by 1000 first.
	printf("\n\nGPU Elapsed Time:%f\n", time_elapsed/1000);
	
        
    hipMemcpy(P,d_P,size,hipMemcpyDeviceToHost);

	printMatrix(P);
	
	free(M);free(N);free(P);
	hipFree(d_M);hipFree(d_N);hipFree(d_P);

	return 0;

}


	.text
	.file	"Tiled_MatrixMul.hip"
	.globl	_Z11printMatrixPf               # -- Begin function _Z11printMatrixPf
	.type	_Z11printMatrixPf,@function
_Z11printMatrixPf:                      # @_Z11printMatrixPf
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r12
	.cfi_def_cfa_offset 32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	pushq	%rax
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -40
	.cfi_offset %r12, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movq	%rdi, %rbx
	xorl	%r14d, %r14d
	movl	$.L.str, %edi
	movl	$1024, %esi                     # imm = 0x400
	movl	$1024, %edx                     # imm = 0x400
	xorl	%eax, %eax
	callq	printf
	movl	$.L.str.1, %edi
	xorl	%eax, %eax
	callq	printf
	movl	$.L.str.2, %edi
	movl	$4, %esi
	movl	$4, %edx
	xorl	%eax, %eax
	callq	printf
	movl	$.L.str.3, %edi
	movl	$1024, %esi                     # imm = 0x400
	movl	$1024, %edx                     # imm = 0x400
	xorl	%eax, %eax
	callq	printf
	movq	%rbx, %r15
.LBB0_1:                                # %.preheader21
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB0_2 Depth 2
	xorl	%r12d, %r12d
.LBB0_2:                                #   Parent Loop BB0_1 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movl	%r12d, %eax
	orl	%r14d, %eax
	testl	$-4, %eax
	jne	.LBB0_4
# %bb.3:                                #   in Loop: Header=BB0_2 Depth=2
	xorps	%xmm0, %xmm0
	cvtss2sd	(%r15,%r12,4), %xmm0
	movl	$.L.str.4, %edi
	movb	$1, %al
	callq	printf
.LBB0_4:                                #   in Loop: Header=BB0_2 Depth=2
	incq	%r12
	cmpq	$1024, %r12                     # imm = 0x400
	jne	.LBB0_2
# %bb.5:                                #   in Loop: Header=BB0_1 Depth=1
	cmpq	$4, %r14
	jae	.LBB0_7
# %bb.6:                                #   in Loop: Header=BB0_1 Depth=1
	movl	$10, %edi
	callq	putchar@PLT
.LBB0_7:                                #   in Loop: Header=BB0_1 Depth=1
	incq	%r14
	addq	$4096, %r15                     # imm = 0x1000
	cmpq	$1024, %r14                     # imm = 0x400
	jne	.LBB0_1
# %bb.8:
	movl	$.L.str.6, %edi
	movl	$1024, %esi                     # imm = 0x400
	movl	$1024, %edx                     # imm = 0x400
	xorl	%eax, %eax
	callq	printf
	addq	$4182000, %rbx                  # imm = 0x3FCFF0
	movl	$1020, %r14d                    # imm = 0x3FC
.LBB0_9:                                # %.preheader
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB0_10 Depth 2
	xorl	%r15d, %r15d
.LBB0_10:                               #   Parent Loop BB0_9 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	xorps	%xmm0, %xmm0
	cvtss2sd	(%rbx,%r15,4), %xmm0
	movl	$.L.str.4, %edi
	movb	$1, %al
	callq	printf
	incq	%r15
	cmpq	$4, %r15
	jne	.LBB0_10
# %bb.11:                               #   in Loop: Header=BB0_9 Depth=1
	movl	$10, %edi
	callq	putchar@PLT
	incq	%r14
	addq	$4096, %rbx                     # imm = 0x1000
	cmpq	$1024, %r14                     # imm = 0x400
	jne	.LBB0_9
# %bb.12:
	addq	$8, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z11printMatrixPf, .Lfunc_end0-_Z11printMatrixPf
	.cfi_endproc
                                        # -- End function
	.globl	_Z40__device_stub__matrixMulKernel_usingTilePfS_S_i # -- Begin function _Z40__device_stub__matrixMulKernel_usingTilePfS_S_i
	.type	_Z40__device_stub__matrixMulKernel_usingTilePfS_S_i,@function
_Z40__device_stub__matrixMulKernel_usingTilePfS_S_i: # @_Z40__device_stub__matrixMulKernel_usingTilePfS_S_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	4(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z25matrixMulKernel_usingTilePfS_S_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z40__device_stub__matrixMulKernel_usingTilePfS_S_i, .Lfunc_end1-_Z40__device_stub__matrixMulKernel_usingTilePfS_S_i
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0                          # -- Begin function main
.LCPI2_0:
	.long	0x447a0000                      # float 1000
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r12
	.cfi_def_cfa_offset 32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	subq	$56, %rsp
	.cfi_def_cfa_offset 96
	.cfi_offset %rbx, -40
	.cfi_offset %r12, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	xorl	%r12d, %r12d
	xorl	%edi, %edi
	callq	hipSetDevice
	movl	$4194304, %edi                  # imm = 0x400000
	callq	malloc
	movq	%rax, %rbx
	movl	$4194304, %edi                  # imm = 0x400000
	callq	malloc
	movq	%rax, %r14
	movl	$1, %edi
	movl	$4194304, %esi                  # imm = 0x400000
	callq	calloc@PLT
	movq	%rax, %r15
	leaq	32(%rsp), %rdi
	movl	$4194304, %esi                  # imm = 0x400000
	callq	hipMalloc
	leaq	24(%rsp), %rdi
	movl	$4194304, %esi                  # imm = 0x400000
	callq	hipMalloc
	leaq	16(%rsp), %rdi
	movl	$4194304, %esi                  # imm = 0x400000
	callq	hipMalloc
.LBB2_1:                                # =>This Inner Loop Header: Depth=1
	xorps	%xmm0, %xmm0
	cvtsi2ss	%r12d, %xmm0
	leaq	1(%r12), %rax
	xorps	%xmm1, %xmm1
	cvtsi2ss	%eax, %xmm1
	movss	%xmm0, (%rbx,%r12,4)
	movss	%xmm1, (%r14,%r12,4)
	movq	%rax, %r12
	cmpq	$1048576, %rax                  # imm = 0x100000
	jne	.LBB2_1
# %bb.2:
	movq	32(%rsp), %rdi
	movl	$4194304, %edx                  # imm = 0x400000
	movq	%rbx, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	24(%rsp), %rdi
	movl	$4194304, %edx                  # imm = 0x400000
	movq	%r14, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movl	$0, 44(%rsp)
	leaq	48(%rsp), %r12
	movq	%r12, %rdi
	callq	hipEventCreate
	leaq	8(%rsp), %rdi
	callq	hipEventCreate
	movq	(%r12), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movabsq	$274877907008, %rdi             # imm = 0x4000000040
	movabsq	$68719476752, %rdx              # imm = 0x1000000010
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_4
# %bb.3:
	movq	32(%rsp), %rdi
	movq	24(%rsp), %rsi
	movq	16(%rsp), %rdx
	movl	$1024, %ecx                     # imm = 0x400
	callq	_Z40__device_stub__matrixMulKernel_usingTilePfS_S_i
.LBB2_4:
	movq	8(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	48(%rsp), %rdi
	callq	hipEventSynchronize
	movq	8(%rsp), %rdi
	callq	hipEventSynchronize
	movq	48(%rsp), %rsi
	movq	8(%rsp), %rdx
	leaq	44(%rsp), %r12
	movq	%r12, %rdi
	callq	hipEventElapsedTime
	movss	(%r12), %xmm0                   # xmm0 = mem[0],zero,zero,zero
	divss	.LCPI2_0(%rip), %xmm0
	cvtss2sd	%xmm0, %xmm0
	movl	$.L.str.7, %edi
	movb	$1, %al
	callq	printf
	movq	16(%rsp), %rsi
	movl	$4194304, %edx                  # imm = 0x400000
	movq	%r15, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movq	%r15, %rdi
	callq	_Z11printMatrixPf
	movq	%rbx, %rdi
	callq	free
	movq	%r14, %rdi
	callq	free
	movq	%r15, %rdi
	callq	free
	movq	32(%rsp), %rdi
	callq	hipFree
	movq	24(%rsp), %rdi
	callq	hipFree
	movq	16(%rsp), %rdi
	callq	hipFree
	xorl	%eax, %eax
	addq	$56, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	main, .Lfunc_end2-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB3_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB3_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z25matrixMulKernel_usingTilePfS_S_i, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end3:
	.size	__hip_module_ctor, .Lfunc_end3-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB4_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB4_2:
	retq
.Lfunc_end4:
	.size	__hip_module_dtor, .Lfunc_end4-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"This is a %d by %d matrix.\n"
	.size	.L.str, 28

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"Actual displayed size is cut in 2 parts shown as"
	.size	.L.str.1, 49

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	" %d by %d matrix.\n"
	.size	.L.str.2, 19

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"   The Top_LEFT CORNER OF the %d * %d matrix:\n"
	.size	.L.str.3, 47

	.type	.L.str.4,@object                # @.str.4
.L.str.4:
	.asciz	"%5.2f "
	.size	.L.str.4, 7

	.type	.L.str.6,@object                # @.str.6
.L.str.6:
	.asciz	"   The LOWER_RIGHT CORNER OF the %d * %d matrix\n"
	.size	.L.str.6, 49

	.type	_Z25matrixMulKernel_usingTilePfS_S_i,@object # @_Z25matrixMulKernel_usingTilePfS_S_i
	.section	.rodata,"a",@progbits
	.globl	_Z25matrixMulKernel_usingTilePfS_S_i
	.p2align	3, 0x0
_Z25matrixMulKernel_usingTilePfS_S_i:
	.quad	_Z40__device_stub__matrixMulKernel_usingTilePfS_S_i
	.size	_Z25matrixMulKernel_usingTilePfS_S_i, 8

	.type	.L.str.7,@object                # @.str.7
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str.7:
	.asciz	"\n\nGPU Elapsed Time:%f\n"
	.size	.L.str.7, 23

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z25matrixMulKernel_usingTilePfS_S_i"
	.size	.L__unnamed_1, 37

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z40__device_stub__matrixMulKernel_usingTilePfS_S_i
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z25matrixMulKernel_usingTilePfS_S_i
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z25matrixMulKernel_usingTilePfS_S_i ; -- Begin function _Z25matrixMulKernel_usingTilePfS_S_i
	.globl	_Z25matrixMulKernel_usingTilePfS_S_i
	.p2align	8
	.type	_Z25matrixMulKernel_usingTilePfS_S_i,@function
_Z25matrixMulKernel_usingTilePfS_S_i:   ; @_Z25matrixMulKernel_usingTilePfS_S_i
; %bb.0:
	s_clause 0x2
	s_load_b32 s2, s[0:1], 0x18
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b64 s[0:1], s[0:1], 0x10
	v_bfe_u32 v2, v0, 10, 10
	v_dual_mov_b32 v3, 0 :: v_dual_and_b32 v6, 0x3ff, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshl_add_u32 v1, s15, 4, v2
	v_lshl_add_u32 v0, s14, 4, v6
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2)
	v_mul_lo_u32 v1, v1, s2
	s_cmp_lt_i32 s2, 16
	s_cbranch_scc1 .LBB0_5
; %bb.1:                                ; %.lr.ph
	v_lshlrev_b32_e32 v3, 2, v6
	v_lshlrev_b32_e32 v4, 6, v2
	s_ashr_i32 s3, s2, 31
	s_delay_alu instid0(VALU_DEP_3)
	v_add_nc_u32_e32 v6, v1, v6
	s_lshr_b32 s3, s3, 28
	v_add_nc_u32_e32 v5, 0x400, v3
	v_add_nc_u32_e32 v7, v4, v3
	v_mov_b32_e32 v3, 0
	s_add_i32 s3, s2, s3
	s_mov_b32 s8, 0
	v_add_nc_u32_e32 v8, v5, v4
	s_ashr_i32 s3, s3, 4
.LBB0_2:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_3 Depth 2
	s_lshl_b32 s9, s8, 4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v10, s9, v2
	v_add_nc_u32_e32 v9, s9, v6
	s_mov_b32 s9, 0
	v_mad_u64_u32 v[11:12], null, v10, s2, v[0:1]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v10, 31, v9
	v_lshlrev_b64 v[9:10], 2, v[9:10]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v12, 31, v11
	v_add_co_u32 v9, vcc_lo, s4, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_lshlrev_b64 v[11:12], 2, v[11:12]
	v_add_co_ci_u32_e32 v10, vcc_lo, s5, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v11, vcc_lo, s6, v11
	v_add_co_ci_u32_e32 v12, vcc_lo, s7, v12, vcc_lo
	global_load_b32 v10, v[9:10], off
	global_load_b32 v11, v[11:12], off
	v_mov_b32_e32 v9, v5
	s_waitcnt vmcnt(1)
	ds_store_b32 v7, v10
	s_waitcnt vmcnt(0)
	ds_store_b32 v8, v11
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
.LBB0_3:                                ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_add_nc_u32_e32 v10, s9, v4
	s_add_i32 s9, s9, 4
	ds_load_b32 v11, v9
	ds_load_b32 v10, v10
	v_add_nc_u32_e32 v9, 64, v9
	s_cmp_eq_u32 s9, 64
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v3, v10, v11
	s_cbranch_scc0 .LBB0_3
; %bb.4:                                ;   in Loop: Header=BB0_2 Depth=1
	s_add_i32 s8, s8, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s8, s3
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc0 .LBB0_2
.LBB0_5:                                ; %Flow56
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v0, v1, v0
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	v_add_co_u32 v0, vcc_lo, s0, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	global_store_b32 v[0:1], v3, off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z25matrixMulKernel_usingTilePfS_S_i
		.amdhsa_group_segment_fixed_size 2048
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 28
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 13
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z25matrixMulKernel_usingTilePfS_S_i, .Lfunc_end0-_Z25matrixMulKernel_usingTilePfS_S_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 432
; NumSgprs: 18
; NumVgprs: 13
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 2048 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 13
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
    .group_segment_fixed_size: 2048
    .kernarg_segment_align: 8
    .kernarg_segment_size: 28
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z25matrixMulKernel_usingTilePfS_S_i
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z25matrixMulKernel_usingTilePfS_S_i.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     13
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
