/* Best config: */
/* [('tile_r', [1, 1, 32, 2]), ('tile_y', [8, 1, 2, 4]), ('tile_x', [16, 1, 1, 4]), ('tile_rs', [32, 2, 1]), ('auto_unroll_max_step', 0), ('unroll_explicit', 1)],,None,50730168 */
/* Finish loading 23776 records */
/* Time cost of this operator: 0.000020 */

extern "C"
__global__
void default_function_kernel0( float* __restrict__ U,  float* __restrict__ K,  float* __restrict__ C) {
   float C_local[32];
  __shared__ float U_shared[64];
  __shared__ float K_shared[128];
   float U_shared_local[16];
   float K_shared_local[2];
  for (int x_c_init = 0; x_c_init < 4; ++x_c_init) {
    for (int y_c_init = 0; y_c_init < 4; ++y_c_init) {
      for (int r_c_init = 0; r_c_init < 2; ++r_c_init) {
        C_local[((x_c_init * 8) + (y_c_init * 2)) + r_c_init] = 0.0f;
      }
    }
  }
  for (int sdim_outer = 0; sdim_outer < 32; ++sdim_outer) {
    __syncthreads();

    int ty = (int)threadIdx.y;
    int tz_2 = (int)threadIdx.z * 2;
    int tz_strd = ((int)threadIdx.z / 8) * 4096;
    int tz_strd_2 = ((int)threadIdx.z % 8) * 64;
    int bx_16384 = (((int)blockIdx.x) * 16384);
    int by_512 = (int)blockIdx.y * 512;

    U_shared[tz_2 + ty] = U[(bx_16384 + tz_strd + by_512 + tz_strd_2) + ty + (sdim_outer * 2)];

    for (int ax0_ax1_fused_inner_inner_inner = 0; ax0_ax1_fused_inner_inner_inner < 2; ++ax0_ax1_fused_inner_inner_inner) {
      K_shared[(((((int)threadIdx.z) * 4) + (((int)threadIdx.y) * 2)) + ax0_ax1_fused_inner_inner_inner)] = K[((((sdim_outer * 128) + (((int)threadIdx.z) * 4)) + (((int)threadIdx.y) * 2)) + ax0_ax1_fused_inner_inner_inner)];
    }
    __syncthreads();
    for (int sdim_inner_outer = 0; sdim_inner_outer < 2; ++sdim_inner_outer) {
      for (int ax1 = 0; ax1 < 4; ++ax1) {
        for (int ax2 = 0; ax2 < 4; ++ax2) {
          U_shared_local[((ax1 * 4) + ax2)] = U_shared[((((ax1 * 16) + (((int)threadIdx.y) * 8)) + (ax2 * 2)) + sdim_inner_outer)];
        }
      }
      for (int ax11 = 0; ax11 < 2; ++ax11) {
        K_shared_local[ax11] = K_shared[(((sdim_inner_outer * 64) + (((int)threadIdx.z) * 2)) + ax11)];
      }
      for (int x_c = 0; x_c < 4; ++x_c) {
        for (int y_c = 0; y_c < 4; ++y_c) {
          for (int r_c = 0; r_c < 2; ++r_c) {
            C_local[(((x_c * 8) + (y_c * 2)) + r_c)] = (C_local[(((x_c * 8) + (y_c * 2)) + r_c)] + (U_shared_local[((x_c * 4) + y_c)] * K_shared_local[r_c]));
          }
        }
      }
    }
  }
  for (int x_inner_inner_inner = 0; x_inner_inner_inner < 4; ++x_inner_inner_inner) {
    for (int y_inner_inner_inner = 0; y_inner_inner_inner < 4; ++y_inner_inner_inner) {
      for (int r_inner_inner_inner = 0; r_inner_inner_inner < 2; ++r_inner_inner_inner) {
        C[(((((((((int)blockIdx.x) * 16384) + (x_inner_inner_inner * 4096)) + (((int)blockIdx.y) * 512)) + (((int)threadIdx.y) * 256)) + (y_inner_inner_inner * 64)) + (((int)threadIdx.z) * 2)) + r_inner_inner_inner)] = C_local[(((x_inner_inner_inner * 8) + (y_inner_inner_inner * 2)) + r_inner_inner_inner)];
      }
    }
  }
}

	.file	"tmpxft_003278a4_00000000-6_nmode_4_2_op_kernel.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2010:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2010:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z48__device_stub__Z24default_function_kernel0PfS_S_PfS_S_
	.type	_Z48__device_stub__Z24default_function_kernel0PfS_S_PfS_S_, @function
_Z48__device_stub__Z24default_function_kernel0PfS_S_PfS_S_:
.LFB2032:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movq	%rdi, 8(%rsp)
	leaq	40(%rsp), %rcx
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	leaq	48(%rsp), %rdi
	movq	%rax, 104(%rsp)
	leaq	24(%rsp), %rax
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	32(%rsp), %rdx
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movl	$1, 56(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	default_function_kernel0(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L2:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2032:
	.size	_Z48__device_stub__Z24default_function_kernel0PfS_S_PfS_S_, .-_Z48__device_stub__Z24default_function_kernel0PfS_S_PfS_S_
	.globl	default_function_kernel0
	.type	default_function_kernel0, @function
default_function_kernel0:
.LFB2033:
	.cfi_startproc
	endbr64
	jmp	_Z48__device_stub__Z24default_function_kernel0PfS_S_PfS_S_
	.cfi_endproc
.LFE2033:
	.size	default_function_kernel0, .-default_function_kernel0
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"default_function_kernel0"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2035:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	default_function_kernel0(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2035:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
/* Best config: */
/* [('tile_r', [1, 1, 32, 2]), ('tile_y', [8, 1, 2, 4]), ('tile_x', [16, 1, 1, 4]), ('tile_rs', [32, 2, 1]), ('auto_unroll_max_step', 0), ('unroll_explicit', 1)],,None,50730168 */
/* Finish loading 23776 records */
/* Time cost of this operator: 0.000020 */

extern "C"
__global__
void default_function_kernel0( float* __restrict__ U,  float* __restrict__ K,  float* __restrict__ C) {
   float C_local[32];
  __shared__ float U_shared[64];
  __shared__ float K_shared[128];
   float U_shared_local[16];
   float K_shared_local[2];
  for (int x_c_init = 0; x_c_init < 4; ++x_c_init) {
    for (int y_c_init = 0; y_c_init < 4; ++y_c_init) {
      for (int r_c_init = 0; r_c_init < 2; ++r_c_init) {
        C_local[((x_c_init * 8) + (y_c_init * 2)) + r_c_init] = 0.0f;
      }
    }
  }
  for (int sdim_outer = 0; sdim_outer < 32; ++sdim_outer) {
    __syncthreads();

    int ty = (int)threadIdx.y;
    int tz_2 = (int)threadIdx.z * 2;
    int tz_strd = ((int)threadIdx.z / 8) * 4096;
    int tz_strd_2 = ((int)threadIdx.z % 8) * 64;
    int bx_16384 = (((int)blockIdx.x) * 16384);
    int by_512 = (int)blockIdx.y * 512;

    U_shared[tz_2 + ty] = U[(bx_16384 + tz_strd + by_512 + tz_strd_2) + ty + (sdim_outer * 2)];

    for (int ax0_ax1_fused_inner_inner_inner = 0; ax0_ax1_fused_inner_inner_inner < 2; ++ax0_ax1_fused_inner_inner_inner) {
      K_shared[(((((int)threadIdx.z) * 4) + (((int)threadIdx.y) * 2)) + ax0_ax1_fused_inner_inner_inner)] = K[((((sdim_outer * 128) + (((int)threadIdx.z) * 4)) + (((int)threadIdx.y) * 2)) + ax0_ax1_fused_inner_inner_inner)];
    }
    __syncthreads();
    for (int sdim_inner_outer = 0; sdim_inner_outer < 2; ++sdim_inner_outer) {
      for (int ax1 = 0; ax1 < 4; ++ax1) {
        for (int ax2 = 0; ax2 < 4; ++ax2) {
          U_shared_local[((ax1 * 4) + ax2)] = U_shared[((((ax1 * 16) + (((int)threadIdx.y) * 8)) + (ax2 * 2)) + sdim_inner_outer)];
        }
      }
      for (int ax11 = 0; ax11 < 2; ++ax11) {
        K_shared_local[ax11] = K_shared[(((sdim_inner_outer * 64) + (((int)threadIdx.z) * 2)) + ax11)];
      }
      for (int x_c = 0; x_c < 4; ++x_c) {
        for (int y_c = 0; y_c < 4; ++y_c) {
          for (int r_c = 0; r_c < 2; ++r_c) {
            C_local[(((x_c * 8) + (y_c * 2)) + r_c)] = (C_local[(((x_c * 8) + (y_c * 2)) + r_c)] + (U_shared_local[((x_c * 4) + y_c)] * K_shared_local[r_c]));
          }
        }
      }
    }
  }
  for (int x_inner_inner_inner = 0; x_inner_inner_inner < 4; ++x_inner_inner_inner) {
    for (int y_inner_inner_inner = 0; y_inner_inner_inner < 4; ++y_inner_inner_inner) {
      for (int r_inner_inner_inner = 0; r_inner_inner_inner < 2; ++r_inner_inner_inner) {
        C[(((((((((int)blockIdx.x) * 16384) + (x_inner_inner_inner * 4096)) + (((int)blockIdx.y) * 512)) + (((int)threadIdx.y) * 256)) + (y_inner_inner_inner * 64)) + (((int)threadIdx.z) * 2)) + r_inner_inner_inner)] = C_local[(((x_inner_inner_inner * 8) + (y_inner_inner_inner * 2)) + r_inner_inner_inner)];
      }
    }
  }
}

	.text
	.file	"nmode_4_2_op_kernel.hip"
	.globl	__device_stub__default_function_kernel0 # -- Begin function __device_stub__default_function_kernel0
	.type	__device_stub__default_function_kernel0,@function
__device_stub__default_function_kernel0: # @__device_stub__default_function_kernel0
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$default_function_kernel0, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	__device_stub__default_function_kernel0, .Lfunc_end0-__device_stub__default_function_kernel0
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$default_function_kernel0, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	default_function_kernel0,@object # @default_function_kernel0
	.section	.rodata,"a",@progbits
	.globl	default_function_kernel0
	.p2align	3, 0x0
default_function_kernel0:
	.quad	__device_stub__default_function_kernel0
	.size	default_function_kernel0, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"default_function_kernel0"
	.size	.L__unnamed_1, 25

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __device_stub__default_function_kernel0
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym default_function_kernel0
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	default_function_kernel0 ; -- Begin function default_function_kernel0
	.globl	default_function_kernel0
	.p2align	8
	.type	default_function_kernel0,@function
default_function_kernel0:               ; @default_function_kernel0
; %bb.0:
	s_clause 0x1
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b64 s[0:1], s[0:1], 0x10
	v_mov_b32_e32 v3, 16
	v_mov_b32_e32 v1, 0
	s_mov_b32 s2, 0
.LBB0_1:                                ; %.preheader102
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_2 Depth 2
	s_mov_b32 s3, 0
.LBB0_2:                                ; %.preheader101
                                        ;   Parent Loop BB0_1 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_add_nc_u32_e32 v4, s3, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_mov_b32_e32 v2, v1
	s_add_i32 s3, s3, 8
	s_cmp_lg_u32 s3, 32
	scratch_store_b64 v4, v[1:2], off
	s_cbranch_scc1 .LBB0_2
; %bb.3:                                ;   in Loop: Header=BB0_1 Depth=1
	v_add_nc_u32_e32 v3, 32, v3
	s_add_i32 s2, s2, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s2, 4
	s_cbranch_scc0 .LBB0_1
; %bb.4:                                ; %.preheader100
	v_bfe_u32 v1, v0, 20, 10
	v_bfe_u32 v20, v0, 10, 10
	s_lshl_b32 s11, s14, 14
	v_lshrrev_b32_e32 v2, 11, v0
	v_lshrrev_b32_e32 v0, 14, v0
	v_lshlrev_b32_e32 v21, 1, v1
	v_or_b32_e32 v3, s11, v20
	v_lshlrev_b32_e32 v1, 2, v1
	s_lshl_b32 s12, s15, 9
	v_dual_mov_b32 v17, 0 :: v_dual_and_b32 v2, 0x7f000, v2
	v_and_b32_e32 v0, 0x1c0, v0
	v_add_nc_u32_e32 v3, s12, v3
	v_add_nc_u32_e32 v4, v21, v20
	v_lshl_add_u32 v22, v20, 1, v1
	v_lshl_add_u32 v26, v20, 5, 0x200
	s_or_b32 s10, 16, 4
	v_add3_u32 v23, v3, v2, v0
	v_lshl_add_u32 v24, v4, 2, 0x200
	v_lshlrev_b32_e32 v25, 2, v22
	s_mov_b32 s13, 0
                                        ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
.LBB0_5:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_6 Depth 2
                                        ;       Child Loop BB0_7 Depth 3
                                        ;         Child Loop BB0_8 Depth 4
                                        ;       Child Loop BB0_11 Depth 3
                                        ;         Child Loop BB0_12 Depth 4
	s_delay_alu instid0(VALU_DEP_3) | instid1(SALU_CYCLE_1)
	v_lshl_add_u32 v18, s13, 1, v23
	v_lshl_add_u32 v16, s13, 7, v22
	s_waitcnt lgkmcnt(0)
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	v_ashrrev_i32_e32 v19, 31, v18
	v_lshlrev_b64 v[27:28], 2, v[16:17]
	s_mov_b32 s2, -1
	s_mov_b32 s15, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[18:19], 2, v[18:19]
	v_add_co_u32 v18, vcc_lo, s4, v18
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v19, vcc_lo, s5, v19, vcc_lo
	v_add_co_u32 v27, vcc_lo, s6, v27
	v_add_co_ci_u32_e32 v28, vcc_lo, s7, v28, vcc_lo
	global_load_b32 v16, v[18:19], off
	global_load_b64 v[18:19], v[27:28], off
	s_waitcnt vmcnt(1)
	ds_store_b32 v24, v16
	s_waitcnt vmcnt(0)
	ds_store_b64 v25, v[18:19]
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
.LBB0_6:                                ; %.preheader99
                                        ;   Parent Loop BB0_5 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB0_7 Depth 3
                                        ;         Child Loop BB0_8 Depth 4
                                        ;       Child Loop BB0_11 Depth 3
                                        ;         Child Loop BB0_12 Depth 4
	v_lshl_add_u32 v16, s15, 2, v26
	s_xor_b32 s14, s2, -1
	s_mov_b32 s16, 0
	s_mov_b64 s[2:3], 0
.LBB0_7:                                ; %.preheader96
                                        ;   Parent Loop BB0_5 Depth=1
                                        ;     Parent Loop BB0_6 Depth=2
                                        ; =>    This Loop Header: Depth=3
                                        ;         Child Loop BB0_8 Depth 4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b64 s[8:9], s[2:3]
	s_mov_b32 s17, 0
.LBB0_8:                                ;   Parent Loop BB0_5 Depth=1
                                        ;     Parent Loop BB0_6 Depth=2
                                        ;       Parent Loop BB0_7 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	s_delay_alu instid0(SALU_CYCLE_1)
	v_add_nc_u32_e32 v18, s17, v16
	s_add_i32 s17, s17, 8
	s_mov_b32 m0, s8
	s_add_u32 s8, s8, 1
	s_addc_u32 s9, s9, 0
	ds_load_b32 v18, v18
	s_cmp_eq_u32 s17, 32
	s_waitcnt lgkmcnt(0)
	v_movreld_b32_e32 v0, v18
	s_cbranch_scc0 .LBB0_8
; %bb.9:                                ;   in Loop: Header=BB0_7 Depth=3
	s_add_i32 s16, s16, 1
	v_add_nc_u32_e32 v16, 64, v16
	s_add_u32 s2, s2, 4
	s_addc_u32 s3, s3, 0
	s_cmp_eq_u32 s16, 4
	s_cbranch_scc0 .LBB0_7
; %bb.10:                               ; %.preheader98
                                        ;   in Loop: Header=BB0_6 Depth=2
	s_lshl_b32 s2, s15, 6
	s_mov_b32 s15, 0
	v_add_lshl_u32 v16, s2, v21, 2
	s_mov_b64 s[2:3], 0
	s_mov_b32 s16, s10
	ds_load_b64 v[18:19], v16
.LBB0_11:                               ; %.preheader95
                                        ;   Parent Loop BB0_5 Depth=1
                                        ;     Parent Loop BB0_6 Depth=2
                                        ; =>    This Loop Header: Depth=3
                                        ;         Child Loop BB0_12 Depth 4
	s_mov_b32 s17, s16
	s_mov_b64 s[8:9], 0
.LBB0_12:                               ; %.preheader94
                                        ;   Parent Loop BB0_5 Depth=1
                                        ;     Parent Loop BB0_6 Depth=2
                                        ;       Parent Loop BB0_11 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	scratch_load_b64 v[27:28], off, s17 offset:-4
	s_add_i32 s18, s2, s8
	s_add_u32 s8, s8, 1
	s_mov_b32 m0, s18
	s_addc_u32 s9, s9, 0
	v_movrels_b32_e32 v16, v0
	s_waitcnt vmcnt(0) lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f32 v27, v16, v18, v27
	v_fmac_f32_e32 v28, v16, v19
	scratch_store_b64 off, v[27:28], s17 offset:-4
	s_add_i32 s17, s17, 8
	s_cmp_lg_u32 s8, 4
	s_cbranch_scc1 .LBB0_12
; %bb.13:                               ;   in Loop: Header=BB0_11 Depth=3
	s_add_i32 s15, s15, 1
	s_add_i32 s16, s16, 32
	s_add_u32 s2, s2, 4
	s_addc_u32 s3, s3, 0
	s_cmp_eq_u32 s15, 4
	s_cbranch_scc0 .LBB0_11
; %bb.14:                               ;   in Loop: Header=BB0_6 Depth=2
	s_mov_b32 s15, 1
	s_and_b32 vcc_lo, exec_lo, s14
	s_mov_b32 s2, 0
	s_cbranch_vccz .LBB0_6
; %bb.15:                               ;   in Loop: Header=BB0_5 Depth=1
	s_add_i32 s13, s13, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s13, 32
	s_cbranch_scc0 .LBB0_5
; %bb.16:                               ; %.preheader93
	v_lshlrev_b32_e32 v0, 8, v20
	s_add_i32 s11, s11, s12
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_add3_u32 v0, s11, v0, v21
.LBB0_17:                               ; %.preheader92
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_18 Depth 2
	s_mov_b32 s3, s10
	s_mov_b32 s4, 0
.LBB0_18:                               ; %.preheader
                                        ;   Parent Loop BB0_17 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	scratch_load_b64 v[1:2], off, s3 offset:-4
	v_add_nc_u32_e32 v3, s4, v0
	s_add_i32 s4, s4, 64
	s_add_i32 s3, s3, 8
	s_cmpk_lg_i32 s4, 0x100
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v4, 31, v3
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, s0, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b64 v[3:4], v[1:2], off
	s_cbranch_scc1 .LBB0_18
; %bb.19:                               ;   in Loop: Header=BB0_17 Depth=1
	v_add_nc_u32_e32 v0, 0x1000, v0
	s_add_i32 s2, s2, 1
	s_add_i32 s10, s10, 32
	s_cmp_eq_u32 s2, 4
	s_cbranch_scc0 .LBB0_17
; %bb.20:
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel default_function_kernel0
		.amdhsa_group_segment_fixed_size 768
		.amdhsa_private_segment_fixed_size 144
		.amdhsa_kernarg_size 24
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 1
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 29
		.amdhsa_next_free_sgpr 19
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	default_function_kernel0, .Lfunc_end0-default_function_kernel0
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 768
; NumSgprs: 21
; NumVgprs: 29
; ScratchSize: 144
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 768 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 3
; NumSGPRsForWavesPerEU: 21
; NumVGPRsForWavesPerEU: 29
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 1
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .actual_access:  read_only
        .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .actual_access:  read_only
        .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .actual_access:  write_only
        .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
    .group_segment_fixed_size: 768
    .kernarg_segment_align: 8
    .kernarg_segment_size: 24
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           default_function_kernel0
    .private_segment_fixed_size: 144
    .sgpr_count:     21
    .sgpr_spill_count: 0
    .symbol:         default_function_kernel0.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     29
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
