
#include <stdlib.h>
#include <stdio.h>

#include <cuda.h>

#define BLOCKSIZE 256

__global__ void vectorReductionKernel(int N, int *c_a, int *c_suma){

  volatile __shared__ int s_a[BLOCKSIZE];  // size must be specified at compile time
  
  int threadIndex = threadIdx.x;
  int blockIndex  = blockIdx.x;
  int threadCount = blockDim.x;

  int n = threadIndex + threadCount*blockIndex;
  
  // check if n is in [0,N)
  if(n<N){
    s_a[threadIndex] = c_a[n];
  }else{
    s_a[threadIndex] = 0;
  }

  // barrier for all threads in thread block
  __syncthreads(); // make sure 256 values stored in shared

  if(threadIndex<128)
    s_a[threadIndex] += s_a[threadIndex+128];

  __syncthreads();

  if(threadIndex<64)
    s_a[threadIndex] += s_a[threadIndex+64];

  __syncthreads();

  if(threadIndex<32)
    s_a[threadIndex] += s_a[threadIndex+32];

  //  __syncthreads();

  if(threadIndex<16)
    s_a[threadIndex] += s_a[threadIndex+16];

  //  __syncthreads();

  if(threadIndex<8)
    s_a[threadIndex] += s_a[threadIndex+8]; 

  //  __syncthreads();

  if(threadIndex<4)
    s_a[threadIndex] += s_a[threadIndex+4];

  //  __syncthreads();

  if(threadIndex<2)
    s_a[threadIndex] += s_a[threadIndex+2];

  //  __syncthreads();

  if(threadIndex<1)
    s_a[threadIndex] += s_a[threadIndex+1];
  
  if(threadIndex==0)
    c_suma[blockIndex] = s_a[0];
  
}


int main(int argc, char **argv){

  int N = 100000000;

  int threadsPerBlock = BLOCKSIZE;
  int blocks = ( N+threadsPerBlock-1)/threadsPerBlock;
  
  // ON HOST
  int *h_a = (int*) malloc(N*sizeof(int));
  int *h_b = (int*) malloc(blocks*sizeof(int));
  
  int n;
  for(n=0;n<N;++n){
    h_a[n] = 1;
  }

  // ON DEVICE
  int *c_a, *c_b;

  cudaMalloc(&c_a, N*sizeof(int));
  cudaMalloc(&c_b, blocks*sizeof(int));
  
  cudaMemcpy(c_a, h_a, N*sizeof(int), cudaMemcpyHostToDevice);

  cudaEvent_t start, end;

  cudaEventCreate(&start);
  cudaEventCreate(&end);

  cudaEventRecord(start);

  // INITIATE KERNEL ON DEVICE
  vectorReductionKernel <<< blocks, threadsPerBlock >>> (N, c_a, c_b);

  cudaEventRecord(end);
  
  cudaEventSynchronize(end);

  float elapsed;
  cudaEventElapsedTime(&elapsed, start, end);
  
  elapsed /= 1000.f;

  printf("elapsed time = %g\n", elapsed);

  int NbytesRead = N*sizeof(int);
  int NbytesWritten = blocks*sizeof(int);

  float bandwidth = (NbytesRead + NbytesWritten)/elapsed;

  printf("bandwidth %g GB/s\n", bandwidth/1.e9);


  // COPY DATA FROM DEVICE TO HOST
  cudaMemcpy(h_b, c_b, blocks*sizeof(int), cudaMemcpyDeviceToHost);

  int reda = 0;
  for(n=0;n<blocks;++n)
    reda += h_b[n];

  printf("sum entries a is %d\n", reda);

  // PRINT ENTRIES
  for(n=0;n<5;++n){
    printf("suma[%d] = %d\n", n, h_b[n]);
  }

  cudaDeviceSynchronize();
  cudaFree(c_a);
  cudaFree(c_b);
}

	.file	"tmpxft_002740db_00000000-6_reduction.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2030:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z44__device_stub__Z21vectorReductionKerneliPiS_iPiS_
	.type	_Z44__device_stub__Z21vectorReductionKerneliPiS_iPiS_, @function
_Z44__device_stub__Z21vectorReductionKerneliPiS_iPiS_:
.LFB2052:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movl	%edi, 28(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	28(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z21vectorReductionKerneliPiS_(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L2:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2052:
	.size	_Z44__device_stub__Z21vectorReductionKerneliPiS_iPiS_, .-_Z44__device_stub__Z21vectorReductionKerneliPiS_iPiS_
	.globl	_Z21vectorReductionKerneliPiS_
	.type	_Z21vectorReductionKerneliPiS_, @function
_Z21vectorReductionKerneliPiS_:
.LFB2053:
	.cfi_startproc
	endbr64
	jmp	_Z44__device_stub__Z21vectorReductionKerneliPiS_iPiS_
	.cfi_endproc
.LFE2053:
	.size	_Z21vectorReductionKerneliPiS_, .-_Z21vectorReductionKerneliPiS_
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC1:
	.string	"elapsed time = %g\n"
.LC4:
	.string	"bandwidth %g GB/s\n"
.LC5:
	.string	"sum entries a is %d\n"
.LC6:
	.string	"suma[%d] = %d\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%r12
	.cfi_def_cfa_offset 16
	.cfi_offset 12, -16
	movl	$400000000, %edi
	pushq	%rbp
	.cfi_def_cfa_offset 24
	.cfi_offset 6, -24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset 3, -32
	subq	$64, %rsp
	.cfi_def_cfa_offset 96
	movq	%fs:40, %rax
	movq	%rax, 56(%rsp)
	xorl	%eax, %eax
	call	malloc@PLT
	movl	$1562500, %edi
	movq	%rax, %rbp
	call	malloc@PLT
	movq	%rax, %rbx
	xorl	%eax, %eax
.L9:
	movl	$1, 0(%rbp,%rax,4)
	incq	%rax
	cmpq	$100000000, %rax
	jne	.L9
	movq	%rsp, %rdi
	movl	$400000000, %esi
	call	cudaMalloc@PLT
	leaq	8(%rsp), %rdi
	movl	$1562500, %esi
	call	cudaMalloc@PLT
	movq	(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbp, %rsi
	movl	$400000000, %edx
	call	cudaMemcpy@PLT
	leaq	16(%rsp), %rdi
	call	cudaEventCreate@PLT
	leaq	24(%rsp), %rdi
	call	cudaEventCreate@PLT
	movq	16(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movl	$16777217, %edx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	salq	$8, %rdx
	movl	$1, %ecx
	movabsq	$4295357921, %rdi
	movl	$1, %esi
	movq	%rdx, 44(%rsp)
	movl	$1, 52(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L10
	movq	8(%rsp), %rdx
	movq	(%rsp), %rsi
	movl	$100000000, %edi
	call	_Z44__device_stub__Z21vectorReductionKerneliPiS_iPiS_
.L10:
	movq	24(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movq	24(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movq	24(%rsp), %rdx
	movq	16(%rsp), %rsi
	leaq	44(%rsp), %rdi
	call	cudaEventElapsedTime@PLT
	leaq	.LC1(%rip), %rsi
	movl	$2, %edi
	movb	$1, %al
	movss	44(%rsp), %xmm0
	divss	.LC0(%rip), %xmm0
	movss	%xmm0, 44(%rsp)
	cvtss2sd	%xmm0, %xmm0
	call	__printf_chk@PLT
	leaq	.LC4(%rip), %rsi
	movb	$1, %al
	movl	$2, %edi
	movss	.LC2(%rip), %xmm0
	divss	44(%rsp), %xmm0
	cvtss2sd	%xmm0, %xmm0
	divsd	.LC3(%rip), %xmm0
	call	__printf_chk@PLT
	movq	8(%rsp), %rsi
	movl	$1562500, %edx
	movq	%rbx, %rdi
	movl	$2, %ecx
	call	cudaMemcpy@PLT
	xorl	%eax, %eax
	xorl	%edx, %edx
.L11:
	addl	(%rbx,%rax,4), %edx
	incq	%rax
	cmpq	$390625, %rax
	jne	.L11
	leaq	.LC5(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	xorl	%ebp, %ebp
	call	__printf_chk@PLT
	leaq	.LC6(%rip), %r12
.L12:
	movl	(%rbx,%rbp,4), %ecx
	movl	%ebp, %edx
	movq	%r12, %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	incq	%rbp
	call	__printf_chk@PLT
	cmpq	$5, %rbp
	jne	.L12
	call	cudaDeviceSynchronize@PLT
	movq	(%rsp), %rdi
	call	cudaFree@PLT
	movq	8(%rsp), %rdi
	call	cudaFree@PLT
	movq	56(%rsp), %rax
	subq	%fs:40, %rax
	je	.L13
	call	__stack_chk_fail@PLT
.L13:
	addq	$64, %rsp
	.cfi_def_cfa_offset 32
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2027:
	.size	main, .-main
	.section	.rodata.str1.1
.LC7:
	.string	"_Z21vectorReductionKerneliPiS_"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC7(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z21vectorReductionKerneliPiS_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2055:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst4,"aM",@progbits,4
	.align 4
.LC0:
	.long	1148846080
	.align 4
.LC2:
	.long	1304394460
	.section	.rodata.cst8,"aM",@progbits,8
	.align 8
.LC3:
	.long	0
	.long	1104006501
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <stdlib.h>
#include <stdio.h>

#include <hip/hip_runtime.h>

#define BLOCKSIZE 256

__global__ void vectorReductionKernel(int N, int *c_a, int *c_suma){

  volatile __shared__ int s_a[BLOCKSIZE];  // size must be specified at compile time
  
  int threadIndex = threadIdx.x;
  int blockIndex  = blockIdx.x;
  int threadCount = blockDim.x;

  int n = threadIndex + threadCount*blockIndex;
  
  // check if n is in [0,N)
  if(n<N){
    s_a[threadIndex] = c_a[n];
  }else{
    s_a[threadIndex] = 0;
  }

  // barrier for all threads in thread block
  __syncthreads(); // make sure 256 values stored in shared

  if(threadIndex<128)
    s_a[threadIndex] += s_a[threadIndex+128];

  __syncthreads();

  if(threadIndex<64)
    s_a[threadIndex] += s_a[threadIndex+64];

  __syncthreads();

  if(threadIndex<32)
    s_a[threadIndex] += s_a[threadIndex+32];

  //  __syncthreads();

  if(threadIndex<16)
    s_a[threadIndex] += s_a[threadIndex+16];

  //  __syncthreads();

  if(threadIndex<8)
    s_a[threadIndex] += s_a[threadIndex+8]; 

  //  __syncthreads();

  if(threadIndex<4)
    s_a[threadIndex] += s_a[threadIndex+4];

  //  __syncthreads();

  if(threadIndex<2)
    s_a[threadIndex] += s_a[threadIndex+2];

  //  __syncthreads();

  if(threadIndex<1)
    s_a[threadIndex] += s_a[threadIndex+1];
  
  if(threadIndex==0)
    c_suma[blockIndex] = s_a[0];
  
}


int main(int argc, char **argv){

  int N = 100000000;

  int threadsPerBlock = BLOCKSIZE;
  int blocks = ( N+threadsPerBlock-1)/threadsPerBlock;
  
  // ON HOST
  int *h_a = (int*) malloc(N*sizeof(int));
  int *h_b = (int*) malloc(blocks*sizeof(int));
  
  int n;
  for(n=0;n<N;++n){
    h_a[n] = 1;
  }

  // ON DEVICE
  int *c_a, *c_b;

  hipMalloc(&c_a, N*sizeof(int));
  hipMalloc(&c_b, blocks*sizeof(int));
  
  hipMemcpy(c_a, h_a, N*sizeof(int), hipMemcpyHostToDevice);

  hipEvent_t start, end;

  hipEventCreate(&start);
  hipEventCreate(&end);

  hipEventRecord(start);

  // INITIATE KERNEL ON DEVICE
  vectorReductionKernel <<< blocks, threadsPerBlock >>> (N, c_a, c_b);

  hipEventRecord(end);
  
  hipEventSynchronize(end);

  float elapsed;
  hipEventElapsedTime(&elapsed, start, end);
  
  elapsed /= 1000.f;

  printf("elapsed time = %g\n", elapsed);

  int NbytesRead = N*sizeof(int);
  int NbytesWritten = blocks*sizeof(int);

  float bandwidth = (NbytesRead + NbytesWritten)/elapsed;

  printf("bandwidth %g GB/s\n", bandwidth/1.e9);


  // COPY DATA FROM DEVICE TO HOST
  hipMemcpy(h_b, c_b, blocks*sizeof(int), hipMemcpyDeviceToHost);

  int reda = 0;
  for(n=0;n<blocks;++n)
    reda += h_b[n];

  printf("sum entries a is %d\n", reda);

  // PRINT ENTRIES
  for(n=0;n<5;++n){
    printf("suma[%d] = %d\n", n, h_b[n]);
  }

  hipDeviceSynchronize();
  hipFree(c_a);
  hipFree(c_b);
}

	.text
	.file	"reduction.hip"
	.globl	_Z36__device_stub__vectorReductionKerneliPiS_ # -- Begin function _Z36__device_stub__vectorReductionKerneliPiS_
	.type	_Z36__device_stub__vectorReductionKerneliPiS_,@function
_Z36__device_stub__vectorReductionKerneliPiS_: # @_Z36__device_stub__vectorReductionKerneliPiS_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	12(%rsp), %rax
	movl	%edi, (%rax)
	leaq	40(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	32(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z21vectorReductionKerneliPiS_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z36__device_stub__vectorReductionKerneliPiS_, .Lfunc_end0-_Z36__device_stub__vectorReductionKerneliPiS_
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0                          # -- Begin function main
.LCPI1_0:
	.long	0x447a0000                      # float 1000
.LCPI1_1:
	.long	0x4dbf7adc                      # float 401562496
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0
.LCPI1_2:
	.quad	0x41cdcd6500000000              # double 1.0E+9
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	subq	$48, %rsp
	.cfi_def_cfa_offset 80
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movl	$400000000, %edi                # imm = 0x17D78400
	callq	malloc
	movq	%rax, %r14
	movl	$1562500, %edi                  # imm = 0x17D784
	callq	malloc
	movq	%rax, %rbx
	xorl	%eax, %eax
.LBB1_1:                                # =>This Inner Loop Header: Depth=1
	movl	$1, (%r14,%rax,4)
	incq	%rax
	cmpq	$100000000, %rax                # imm = 0x5F5E100
	jne	.LBB1_1
# %bb.2:
	leaq	24(%rsp), %r15
	movl	$400000000, %esi                # imm = 0x17D78400
	movq	%r15, %rdi
	callq	hipMalloc
	leaq	16(%rsp), %rdi
	movl	$1562500, %esi                  # imm = 0x17D784
	callq	hipMalloc
	movq	(%r15), %rdi
	movl	$400000000, %edx                # imm = 0x17D78400
	movq	%r14, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	32(%rsp), %r14
	movq	%r14, %rdi
	callq	hipEventCreate
	leaq	8(%rsp), %rdi
	callq	hipEventCreate
	movq	(%r14), %rdi
	xorl	%r14d, %r14d
	xorl	%esi, %esi
	callq	hipEventRecord
	movabsq	$4294967552, %rdx               # imm = 0x100000100
	leaq	390369(%rdx), %rdi
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_4
# %bb.3:
	movq	24(%rsp), %rsi
	movq	16(%rsp), %rdx
	movl	$100000000, %edi                # imm = 0x5F5E100
	callq	_Z36__device_stub__vectorReductionKerneliPiS_
.LBB1_4:
	movq	8(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	8(%rsp), %rdi
	callq	hipEventSynchronize
	movq	32(%rsp), %rsi
	movq	8(%rsp), %rdx
	leaq	44(%rsp), %r15
	movq	%r15, %rdi
	callq	hipEventElapsedTime
	movss	(%r15), %xmm0                   # xmm0 = mem[0],zero,zero,zero
	divss	.LCPI1_0(%rip), %xmm0
	movss	%xmm0, (%r15)
	cvtss2sd	%xmm0, %xmm0
	movl	$.L.str, %edi
	movb	$1, %al
	callq	printf
	movss	.LCPI1_1(%rip), %xmm0           # xmm0 = mem[0],zero,zero,zero
	divss	(%r15), %xmm0
	cvtss2sd	%xmm0, %xmm0
	divsd	.LCPI1_2(%rip), %xmm0
	movl	$.L.str.1, %edi
	movb	$1, %al
	callq	printf
	movq	16(%rsp), %rsi
	movl	$1562500, %edx                  # imm = 0x17D784
	movq	%rbx, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	xorl	%eax, %eax
.LBB1_5:                                # =>This Inner Loop Header: Depth=1
	addl	(%rbx,%rax,4), %r14d
	incq	%rax
	cmpq	$390625, %rax                   # imm = 0x5F5E1
	jne	.LBB1_5
# %bb.6:
	movl	$.L.str.2, %edi
	movl	%r14d, %esi
	xorl	%eax, %eax
	callq	printf
	xorl	%r14d, %r14d
.LBB1_7:                                # =>This Inner Loop Header: Depth=1
	movl	(%rbx,%r14,4), %edx
	movl	$.L.str.3, %edi
	movl	%r14d, %esi
	xorl	%eax, %eax
	callq	printf
	incq	%r14
	cmpq	$5, %r14
	jne	.LBB1_7
# %bb.8:
	callq	hipDeviceSynchronize
	movq	24(%rsp), %rdi
	callq	hipFree
	movq	16(%rsp), %rdi
	callq	hipFree
	xorl	%eax, %eax
	addq	$48, %rsp
	.cfi_def_cfa_offset 32
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	main, .Lfunc_end1-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z21vectorReductionKerneliPiS_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z21vectorReductionKerneliPiS_,@object # @_Z21vectorReductionKerneliPiS_
	.section	.rodata,"a",@progbits
	.globl	_Z21vectorReductionKerneliPiS_
	.p2align	3, 0x0
_Z21vectorReductionKerneliPiS_:
	.quad	_Z36__device_stub__vectorReductionKerneliPiS_
	.size	_Z21vectorReductionKerneliPiS_, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"elapsed time = %g\n"
	.size	.L.str, 19

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"bandwidth %g GB/s\n"
	.size	.L.str.1, 19

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"sum entries a is %d\n"
	.size	.L.str.2, 21

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"suma[%d] = %d\n"
	.size	.L.str.3, 15

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z21vectorReductionKerneliPiS_"
	.size	.L__unnamed_1, 31

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z36__device_stub__vectorReductionKerneliPiS_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z21vectorReductionKerneliPiS_
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z21vectorReductionKerneliPiS_ ; -- Begin function _Z21vectorReductionKerneliPiS_
	.globl	_Z21vectorReductionKerneliPiS_
	.p2align	8
	.type	_Z21vectorReductionKerneliPiS_,@function
_Z21vectorReductionKerneliPiS_:         ; @_Z21vectorReductionKerneliPiS_
; %bb.0:
	s_clause 0x2
	s_load_b32 s5, s[0:1], 0x24
	s_load_b32 s6, s[0:1], 0x0
	s_load_b128 s[0:3], s[0:1], 0x8
	s_mov_b32 s4, s15
	v_mov_b32_e32 v3, 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s5, s5, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s4, s5, v[0:1]
	s_mov_b32 s5, exec_lo
	v_cmpx_gt_i32_e64 s6, v1
	s_cbranch_execz .LBB0_2
; %bb.1:
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v3, v[1:2], off
.LBB0_2:
	s_or_b32 exec_lo, exec_lo, s5
	v_lshlrev_b32_e32 v1, 2, v0
	s_mov_b64 s[0:1], src_shared_base
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v1
	v_cndmask_b32_e32 v1, 0, v1, vcc_lo
	v_cndmask_b32_e64 v2, 0, s1, vcc_lo
	s_waitcnt vmcnt(0)
	flat_store_b32 v[1:2], v3 dlc
	s_waitcnt_vscnt null, 0x0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 0x80, v0
	s_cbranch_execz .LBB0_4
; %bb.3:
	v_lshl_add_u32 v3, v0, 2, 0x200
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v3
	v_cndmask_b32_e32 v3, 0, v3, vcc_lo
	v_cndmask_b32_e64 v4, 0, s1, vcc_lo
	flat_load_b32 v3, v[3:4] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v4, v[1:2] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_nc_u32_e32 v3, v4, v3
	flat_store_b32 v[1:2], v3 dlc
	s_waitcnt_vscnt null, 0x0
.LBB0_4:
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 64, v0
	s_cbranch_execz .LBB0_6
; %bb.5:
	v_lshl_add_u32 v3, v0, 2, 0x100
	s_mov_b64 s[6:7], src_shared_base
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v3
	v_cndmask_b32_e32 v3, 0, v3, vcc_lo
	v_cndmask_b32_e64 v4, 0, s7, vcc_lo
	flat_load_b32 v3, v[3:4] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v4, v[1:2] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_nc_u32_e32 v3, v4, v3
	flat_store_b32 v[1:2], v3 dlc
	s_waitcnt_vscnt null, 0x0
.LBB0_6:
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v0
	s_cbranch_execz .LBB0_8
; %bb.7:
	v_lshl_add_u32 v3, v0, 2, 0x80
	s_mov_b64 s[6:7], src_shared_base
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v3
	v_cndmask_b32_e32 v3, 0, v3, vcc_lo
	v_cndmask_b32_e64 v4, 0, s7, vcc_lo
	flat_load_b32 v3, v[3:4] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v4, v[1:2] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_nc_u32_e32 v3, v4, v3
	flat_store_b32 v[1:2], v3 dlc
	s_waitcnt_vscnt null, 0x0
.LBB0_8:
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 16, v0
	s_cbranch_execz .LBB0_10
; %bb.9:
	v_lshl_add_u32 v3, v0, 2, 64
	s_mov_b64 s[6:7], src_shared_base
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v3
	v_cndmask_b32_e32 v3, 0, v3, vcc_lo
	v_cndmask_b32_e64 v4, 0, s7, vcc_lo
	flat_load_b32 v3, v[3:4] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v4, v[1:2] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_nc_u32_e32 v3, v4, v3
	flat_store_b32 v[1:2], v3 dlc
	s_waitcnt_vscnt null, 0x0
.LBB0_10:
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 8, v0
	s_cbranch_execz .LBB0_12
; %bb.11:
	v_lshl_add_u32 v3, v0, 2, 32
	s_mov_b64 s[6:7], src_shared_base
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v3
	v_cndmask_b32_e32 v3, 0, v3, vcc_lo
	v_cndmask_b32_e64 v4, 0, s7, vcc_lo
	flat_load_b32 v3, v[3:4] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v4, v[1:2] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_nc_u32_e32 v3, v4, v3
	flat_store_b32 v[1:2], v3 dlc
	s_waitcnt_vscnt null, 0x0
.LBB0_12:
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 4, v0
	s_cbranch_execz .LBB0_14
; %bb.13:
	v_lshl_add_u32 v3, v0, 2, 16
	s_mov_b64 s[6:7], src_shared_base
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v3
	v_cndmask_b32_e32 v3, 0, v3, vcc_lo
	v_cndmask_b32_e64 v4, 0, s7, vcc_lo
	flat_load_b32 v3, v[3:4] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v4, v[1:2] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_nc_u32_e32 v3, v4, v3
	flat_store_b32 v[1:2], v3 dlc
	s_waitcnt_vscnt null, 0x0
.LBB0_14:
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 2, v0
	s_cbranch_execz .LBB0_16
; %bb.15:
	v_lshl_add_u32 v3, v0, 2, 8
	s_mov_b64 s[6:7], src_shared_base
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v3
	v_cndmask_b32_e32 v3, 0, v3, vcc_lo
	v_cndmask_b32_e64 v4, 0, s7, vcc_lo
	flat_load_b32 v3, v[3:4] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v4, v[1:2] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_nc_u32_e32 v3, v4, v3
	flat_store_b32 v[1:2], v3 dlc
	s_waitcnt_vscnt null, 0x0
.LBB0_16:
	s_or_b32 exec_lo, exec_lo, s0
	s_mov_b32 s0, 0
	s_mov_b32 s1, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB0_18
; %bb.17:
	s_mov_b64 s[6:7], src_shared_base
	s_delay_alu instid0(SALU_CYCLE_1)
	v_dual_mov_b32 v0, 4 :: v_dual_mov_b32 v1, s7
	s_mov_b32 s1, s7
	s_ashr_i32 s5, s4, 31
	v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0
	s_lshl_b64 s[0:1], s[4:5], 2
	flat_load_b32 v0, v[0:1] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v1, v[2:3] glc dlc
	s_waitcnt vmcnt(0)
	s_add_u32 s0, s2, s0
	s_addc_u32 s1, s3, s1
	s_waitcnt lgkmcnt(0)
	v_dual_mov_b32 v1, 0 :: v_dual_add_nc_u32 v0, v1, v0
	flat_store_b32 v[2:3], v0 dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b32 v0, v[2:3] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	global_store_b32 v1, v0, s[0:1]
.LBB0_18:
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z21vectorReductionKerneliPiS_
		.amdhsa_group_segment_fixed_size 1024
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 5
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z21vectorReductionKerneliPiS_, .Lfunc_end0-_Z21vectorReductionKerneliPiS_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1004
; NumSgprs: 18
; NumVgprs: 5
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 1024 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 5
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 1024
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z21vectorReductionKerneliPiS_
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z21vectorReductionKerneliPiS_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     5
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
