#include <cuda_runtime.h>
#include <curand_kernel.h>
#include <device_launch_parameters.h>
#include <stdio.h>
#include <stdlib.h>
#include <stdint.h>
#include <string.h>
#include <iostream>
#include <math.h>
#include <ctype.h>
#include <cuda.h>
#include <time.h>

#define DATAMB(bytes)			(bytes/1024/1024)
#define DATABW(bytes,timems)	((float)bytes/(timems * 1.024*1024.0*1024.0))
#define	CEIL(a,b)				((a+b-1)/b)

typedef unsigned char uch;
typedef unsigned long ul;
typedef unsigned int  ui;

struct ImgProp{
	int Hpixels;
	int Vpixels;
	uch HeaderInfo[54];
	ul Hbytes;
} ip;


typedef struct{
	ui i;
	ui j;
}pixelCoords;

// buffers for images
uch *TheImg, *CopyImg;				
uch *GPUImg, *GPUCopyImg, *GPUptr, *GPUResult, *NoiseMap, *KernelIndices;
double *GPU_PREV_BW, *GPU_CURR_BW;

// noisy pixel locations
pixelCoords *NoisyPixelCoords;

// mutex variables for tracking noisy pixels
ui *GlobalMax, *GlobalMin, *NumNoisyPixelsGPU, *GPUmutexes, *GPU_SAD;


#define	IPHB		ip.Hbytes
#define	IPH			ip.Hpixels
#define	IPV			ip.Vpixels
#define	IMAGESIZE	(IPHB*IPV)
#define	IMAGEPIX	(IPH*IPV)



// Kernel that locates potentially noisy pixels in an image by using impulse noise detection
__global__
void findNoisyPixels(pixelCoords *locations, uch *ImgSrc, uch *noiseMap, ui*globalMax, ui*globalMin, ui*ListLength, ui Hpixels, ui Vpixels)
{

	// 3x3 matrix of pixels around current pixel
	//uch mat3x3[8]; // 3 x 3 - 1 = 8

	// threads/blocks info and IDs
	ui ThrPerBlk = blockDim.x;
	ui MYbid = blockIdx.x;
	ui MYtid = threadIdx.x;
	ui MYgtid = ThrPerBlk * MYbid + MYtid;

	//ui NumBlocks = gridDim.x;
	ui BlkPerRow = CEIL(Hpixels, ThrPerBlk);
	ui MYrow = MYbid / BlkPerRow;
	ui MYcol = MYgtid - MYrow*BlkPerRow*ThrPerBlk;

	// leave buffer frame around image to avoid 8 edge cases for convolutions
	if (MYcol > Hpixels-4 || MYcol < 3 || MYrow > Vpixels-4 || MYrow < 3) return;

	ui MYpixIndex = MYrow * Hpixels + MYcol; // pixel index in B&W image

	uch pIJ = ImgSrc[MYpixIndex];
	uch max = 0;
	uch min = 255;
	uch curr;
	uch nMax;
	uch nMin;
	uch oldMax;
	uch oldMin;
	int row;
	int col;
	int indx;
	
	// find min and max pixel intensities in current window
	for (int i = -1; i <= 1; i++){
		for (int j = -1; j <= 1; j++){

			if(!(j==0 && i==0)){

				row = MYrow + i;
				col = MYcol + j;
				indx = row*Hpixels + col;
				curr = ImgSrc[indx];

				if(curr > max)
					max = curr;
				if(curr < min)
					min = curr;
			}
		}
	}

	// atomically update global max and min pixel intensities
	oldMax = atomicMax(globalMax, (ui)max);
	oldMin = atomicMin(globalMin, (ui)min);

	// if the old max wasn't updated, then max is "salt" noise
	// otherwise, we must assume that 255 is "salt" noise
	if(oldMax == max)
		nMax = max;
	else
		nMax = 255;

	// if the old min wasn't updated, then min is "pepper" noise
	// otherwise, we must assume that 0 is "pepper" noise
	if(oldMin == min)
		nMin = min;
	else
		nMin = 0;
	
	// if the current pixel intensity is equal to min or max,
	// then it is likely s&p noise. Mark as such.
	if(pIJ == nMin || pIJ == nMax){

		int listIndex = atomicAdd(ListLength, (ui)1); 

		locations[listIndex].i = MYrow;
		locations[listIndex].j = MYcol;

		noiseMap[MYpixIndex] = 0;

	}

	// if(pIJ == 255 || pIJ == 0){

	// 	ui listIndex = atomicAdd(ListLength, (ui)1); 

	// 	locations[listIndex].i = MYrow;
	// 	locations[listIndex].j = MYcol;

	// 	noiseMap[MYpixIndex] = 0;

	// }
	
}


// __device__
// uch Horz[5][5] = {	{ 0, 0,  0,  0,  0 },
// 					{ 1, 1,  1,  1,  1 },
// 					{ 1, 1,  0,  1,  1 },
// 					{ 1, 1,  1,  1,  1 },
// 					{ 0, 0,  0,  0,  0 } };

// __device__
// uch Vert[5][5] = {	{ 0, 1,  1,  1,  0 },
// 					{ 0, 1,  1,  1,  0 },
// 					{ 0, 1,  0,  1,  0 },
// 					{ 0, 1,  1,  1,  0 },
// 					{ 0, 1,  1,  1,  0 } };

// __device__
// uch mask45[7][7]={	{0, 0, 0, 0, 1, 0, 0},
// 					{0, 0, 0, 1, 1, 1, 0},
// 					{0, 0, 1, 1, 1, 1, 1},
// 					{0, 1, 1, 0, 1, 1, 0},
// 					{1, 1, 1, 1, 1, 0, 0},
// 					{0, 1, 1, 1, 0, 0, 0},
// 					{0, 0, 1, 0, 0, 0, 0}};

// __device__
// uch mask135[7][7]={	{0, 0, 1, 0, 0, 0, 0},
//                   	{0, 1, 1, 1, 0, 0, 0},
//                   	{1, 1, 1, 1, 1, 0, 0},
//                   	{0, 1, 1, 0, 1, 1, 0},
//                   	{0, 0, 1, 1, 1, 1, 1},
//                   	{0, 0, 0, 1, 1, 1, 0},
//                   	{0, 0, 0, 0, 1, 0, 0}};


//3x3 standard mask
__constant__
double mask0[3][3] = {  {0.1036,	0.1464,	0.1036},
						{0.1464,	0,		0.1464},
						{0.1036,	0.1464,	0.1036}};

// horizontal 5x5 mask
__constant__
double mask1[5][5] = {  {0,			0,		0,			0,		0		},
						{0.0465,	0.0735,	0.1040,		0.0735,	0.0465	},
						{0.0520,	0.1040,	0,			0.1040,	0.0520	},
						{0.0465,	0.0735,	0.1040,		0.0735,	0.0465	},
						{0,			0,		0,			0,		0		}};

//vertical 5x5 mask						
__constant__
double mask2[5][5] = {  {0,	0.0465,	0.0520,	0.0465,	0},
						{0,	0.0735,	0.1040,	0.0735,	0},
						{0,	0.1040,	0,		0.1040,	0},
						{0,	0.0735,	0.1040,	0.0735,	0},
						{0,	0.0465,	0.0520,	0.0465,	0}};

//45 degree 7x7 mask					
__constant__
double mask3[7][7] = {	{0,			0,		0,		0,		0.0251,	0,		0		},
						{0,			0,		0,		0.0397,	0.0355,	0.0281,	0		},
						{0,			0,		0.0562,	0.0794,	0.0562,	0.0355,	0.0251	},
						{0,			0.0397,	0.0794,	0,		0.0794,	0.0397,	0		},
						{0.0251,	0.0355,	0.0562,	0.0794,	0.0562,	0,		0		},
						{0,			0.0281,	0.0355,	0.0397,	0,		0,		0		},
						{0,			0,		0.0251,	0,		0,		0,		0		}};
						
//135 degree 7x7 mask							
__constant__						
double mask4[7][7] = {  {0,			0,		0.0251,	0,		0,		0,		0		},
						{0,			0.0281,	0.0355,	0.0397,	0,		0,		0		},
						{0.0251,	0.0355,	0.0562,	0.0794,	0.0562,	0,		0		},
						{0,			0.0397,	0.0794,	0,		0.0794,	0.0397,	0		},
						{0,			0,		0.0562,	0.0794,	0.0562,	0.0355,	0.0251	},
						{0,			0,		0,		0.0397,	0.0355,	0.0281,	0		},
						{0,			0,		0,		0,		0.0251,	0,		0		}};


// Kernel that determines appropriate inpainting mask to use based on surrounding noiseless pixels
__global__
void determineMasks(pixelCoords *locations, uch *ImgSrc, uch *noiseMap, uch *kernelIndices, ui ListLength, ui Hpixels, ui R) {

	// threads/blocks info and IDs
	ui ThrPerBlk = blockDim.x;
	ui MYbid = blockIdx.x;
	ui MYtid = threadIdx.x;
	ui MYgtid = ThrPerBlk * MYbid + MYtid;

	// ensure not out-of-bounds
	if (MYgtid > ListLength) return;

	// masked arrays of those pixels denoted as noise-free
	uch noiseFreeLists[60];
	uch *maskA = noiseFreeLists;
	uch *maskB = maskA+14;
	uch *maskC = maskB+14;
	uch *maskD = maskC+14;
	uch *listLengths = maskD+14;
	uch *currMask;
	uch currListLength;

	// control and tracking variables
	int i, j, row, col, indx, maskAIndx=0, maskBIndx=0, maskCIndx=0, maskDIndx=0, chosenMask;
	float minStdDev=1000000.0, currStdDev, sum = 0.0, mean, standardDeviation = 0.0;

	// obtain current noisy pixel indices
	pixelCoords currCoord = locations[MYgtid];

	ui MYrow = currCoord.i;
	ui MYcol = currCoord.j;

	// iterate through both 5x5 masks to find values of noise-free pixels
	for (i = -2; i <= 2; i++){
		for (j = -2; j <= 2; j++){

			// find current absolute index
			row = MYrow + i;
			col = MYcol + j;
			indx = row*Hpixels + col;

			// if the current pixel is noise-free AND
			if(noiseMap[indx]){

				// if the current 5x5 horizontal mask cell is set to TRUE
				if(mask1[i+2][j+2]) {

					// obtain noise free pixel and add to list
					maskA[maskAIndx] = ImgSrc[indx];
					maskAIndx++;
				}

				// if the current 5x5 vertical mask cell is set to TRUE
				if(mask2[i+2][j+2]) {

					// obtain noise free pixel and add to list
					maskB[maskBIndx] = ImgSrc[indx];
					maskBIndx++;
				}

			}
		}
	}

	// iterate through both 7x7 masks to find values of noise-free pixels
	for (i = -3; i <= 3; i++){
		for ( j = -3; j <= 3; j++){

			// find current absolute index
			row = MYrow + i;
			col = MYcol + j;
			indx = row*Hpixels + col;

			// if the current pixel is noise-free AND
			if(noiseMap[indx]){

				// if the current 7x7 45 degree mask cell is set to TRUE
				if(mask3[i+3][j+3]) {
					// obtain noise free pixel and add to list
					maskC[maskCIndx] = ImgSrc[indx];
					maskCIndx++;
				}

				// if the current 7x7 135 degree mask cell is set to TRUE
				if(mask4[i+3][j+3]) {
					// obtain noise free pixel and add to list
					maskD[maskDIndx] = ImgSrc[indx];
					maskDIndx++;
				}

			}
		}
	}

	// if the amounts of noise free pixels in any of the directional masks is 
	// below threshold R, then we use 3x3 convolution
	// this helps to mitigate promoting false edges
	if(maskAIndx < R || maskBIndx < R || maskCIndx < R || maskDIndx < R)
		chosenMask = 0;

	else {

		// assign list lengths for smoother access
		listLengths[0] = maskAIndx;
		listLengths[1] = maskBIndx;
		listLengths[2] = maskCIndx;
		listLengths[3] = maskDIndx;

		// find the mask index (from 1 to 4) of minimum standard deviation
		for(i=0; i < 4; i++) {

			currListLength = listLengths[i];
			currMask = maskA+(i*14);
			
			// first find mean of array
			for(j = 0; j < currListLength; j++)
			{
				sum += (float)currMask[j];
			}
			mean = sum/currListLength;

			// then find sum of individual deviations
			for(j = 0; j < currListLength; j++)
				standardDeviation += pow((float)currMask[j] - mean, 2);

			// final StdDev is normalized by list length
			currStdDev = standardDeviation / currListLength;

			if(currStdDev < minStdDev) {
				chosenMask = i+1;
				minStdDev = currStdDev;
			}

		}

	}

	// assign the mask index that was chosen
	kernelIndices[MYgtid] = chosenMask;

}




// convolutions based on kernel indices
__global__
void Convolute(double *ImgCurr, double *ImgBW,  pixelCoords *pc,  uch *kernalI, ui numNoisy, ui Hpixels)
{
	ui ThrPerBlk = blockDim.x;
	ui MYbid = blockIdx.x;
	ui MYtid = threadIdx.x;
	ui MYgtid = ThrPerBlk * MYbid + MYtid;

	if (MYgtid >= numNoisy) return;			// index out of range

	// current noisy pixel coordinates
	ui i=pc[MYgtid].i,j=pc[MYgtid].j,m=kernalI[MYgtid];

	// absolute pixel index
	ui MYpixIndex = i * Hpixels + j;

	int a,b,row,col,index;
	double C = 0.0;

	switch(m)
	{
		case 0: for (a = -1; a <= 1; a++){
					for (b = -1; b <= 1; b++){
						row = i + a;
						col = j + b;
						index = row*Hpixels + col;
						C += (ImgBW[index] * mask0[a + 1][b + 1]);
					}
				}
				ImgCurr[MYpixIndex] = C;
				break;
		case 1: for (a = -2; a <= 2; a++){
					for (b = -2; b <= 2; b++){
						row = i + a;
						col = j + b;
						index = row*Hpixels + col;
						C += (ImgBW[index] * mask1[a + 2][b + 2]);
					}
				}
				ImgCurr[MYpixIndex] = C;
				break;
		case 2: for (a = -2; a <= 2; a++){
					for (b = -2; b <= 2; b++){
						row = i + a;
						col = j + b;
						index = row*Hpixels + col;
						C += (ImgBW[index] * mask2[a + 2][b + 2]);
					}
				}
				ImgCurr[MYpixIndex] = C;
				break;
		case 3: for (a = -3; a <= 3; a++){
					for (b = -3; b <= 3; b++){
						row = i + a;
						col = j + b;
						index = row*Hpixels + col;
						C += (ImgBW[index] * mask3[a + 3][b + 3]);
					}
				}
				ImgCurr[MYpixIndex] = C;
				break;
		default: for (a = -3; a <= 3; a++){
					for (b = -3; b <= 3; b++){
						row = i + a;
						col = j + b;
						index = row*Hpixels + col;
						C += (ImgBW[index] * mask4[a + 3][b + 3]);
					}
				}

				// assign convolution sum to current noisy pixel index
				ImgCurr[MYpixIndex] = C;
				break;
	}
		
}


// sum of absolute differences, reconstruction progress tracking mechanism
__global__
void SAD(ui *sad, double *prev, double *current, pixelCoords *pc, ui numNoisy, ui Hpixels, ui Vpixels)
{
	// thread IDs
	ui ThrPerBlk = blockDim.x;
	ui MYbid = blockIdx.x;
	ui MYtid = threadIdx.x;
	ui MYgtid = ThrPerBlk * MYbid + MYtid;
	
	if (MYgtid >= numNoisy) return;			// index out of range

	ui i=pc[MYgtid].i, j=pc[MYgtid].j; // current noisy pixel coordinates

	ui MYpixIndex = i * Hpixels + j; // absolute index
	
	// difference of old and updated pixel values, round to nearest integer
	int absDiff=(int)(prev[MYpixIndex]-current[MYpixIndex]+0.5);

	// absolute difference
	if(absDiff<0)
		absDiff = absDiff*(-1);
	
	atomicAdd(sad, (ui)absDiff); // update global sum

}


// Kernel that calculates a B&W image from an RGB image
// resulting image has a double type for each pixel position
__global__
void BWKernel(uch *ImgBW, uch *ImgGPU, double *ImgfpBW, ui Hpixels)
{
	ui ThrPerBlk = blockDim.x;
	ui MYbid = blockIdx.x;
	ui MYtid = threadIdx.x;
	ui MYgtid = ThrPerBlk * MYbid + MYtid;
	double R, G, B;

	//ui NumBlocks = gridDim.x;
	ui BlkPerRow = CEIL(Hpixels, ThrPerBlk);
	ui RowBytes = (Hpixels * 3 + 3) & (~3);
	ui MYrow = MYbid / BlkPerRow;
	ui MYcol = MYgtid - MYrow*BlkPerRow*ThrPerBlk;
	if (MYcol >= Hpixels) return;			// col out of range

	ui MYsrcIndex = MYrow * RowBytes + 3 * MYcol;
	ui MYpixIndex = MYrow * Hpixels + MYcol;

	B = (double)ImgGPU[MYsrcIndex];
	G = (double)ImgGPU[MYsrcIndex + 1];
	R = (double)ImgGPU[MYsrcIndex + 2];
	ImgBW[MYpixIndex] = (uch)((R+G+B)/3.0);
	ImgfpBW[MYpixIndex] = (R+G+B)/3.0;
}


// Kernel that calculates a RGB (grayscale) version of B&W image for filing as Windows BMP
__global__
void RGBKernel(uch *ImgRGB, double *ImgBW, ui Hpixels)
{
	ui ThrPerBlk = blockDim.x;
	ui MYbid = blockIdx.x;
	ui MYtid = threadIdx.x;
	ui MYgtid = ThrPerBlk * MYbid + MYtid;

	//ui NumBlocks = gridDim.x;
	ui BlkPerRow = CEIL(Hpixels, ThrPerBlk);
	ui RowBytes = (Hpixels * 3 + 3) & (~3);
	ui MYrow = MYbid / BlkPerRow;
	ui MYcol = MYgtid - MYrow*BlkPerRow*ThrPerBlk;
	if (MYcol >= Hpixels) return;			// col out of range

	ui MYdstIndex = MYrow * RowBytes + 3 * MYcol;
	ui MYpixIndex = MYrow * Hpixels + MYcol;

	uch pixInt = ImgBW[MYpixIndex];

	ImgRGB[MYdstIndex] = pixInt;
	ImgRGB[MYdstIndex+1] = pixInt;
	ImgRGB[MYdstIndex+2] = pixInt;
}


// Kernel that copies an image from one part of the
// GPU memory (ImgSrc) to another (ImgDst)
__global__
void NoisyPixCopy(double *NPDst, double *ImgSrc, pixelCoords *pc, ui NoisyPixelListLength, ui Hpixels)
{
	ui ThrPerBlk = blockDim.x;
	ui MYbid = blockIdx.x;
	ui MYtid = threadIdx.x;
	ui MYgtid = ThrPerBlk * MYbid + MYtid;

	if (MYgtid >= NoisyPixelListLength) return;// outside the allocated memory

	pixelCoords currCoord = pc[MYgtid];

	ui srcIndex = currCoord.i * Hpixels + currCoord.j;

	NPDst[srcIndex] = ImgSrc[srcIndex];
}


// Kernel that copies an image from one part of the
// GPU memory (ImgSrc) to another (ImgDst)
__global__
void PixCopy(double *ImgDst, double *ImgSrc, ui FS)
{
	ui ThrPerBlk = blockDim.x;
	ui MYbid = blockIdx.x;
	ui MYtid = threadIdx.x;
	ui MYgtid = ThrPerBlk * MYbid + MYtid;

	if (MYgtid > FS) return;				// outside the allocated memory
	ImgDst[MYgtid] = ImgSrc[MYgtid];
}


/*
// helper function that wraps CUDA API calls, reports any error and exits
void chkCUDAErr(cudaError_t error_id)
{
	if (error_id != CUDA_SUCCESS)
	{
		printf("CUDA ERROR :::%\n", cudaGetErrorString(error_id));
		exit(EXIT_FAILURE);
	}
}
*/


// Read a 24-bit/pixel BMP file into a 1D linear array.
// Allocate memory to store the 1D image and return its pointer.
uch *ReadBMPlin(char* fn)
{
	static uch *Img;
	FILE* f = fopen(fn, "rb");
	if (f == NULL){	printf("\n\n%s NOT FOUND\n\n", fn);	exit(EXIT_FAILURE); }

	uch HeaderInfo[54];
	fread(HeaderInfo, sizeof(uch), 54, f); // read the 54-byte header
	// extract image height and width from header
	int width = *(int*)&HeaderInfo[18];			ip.Hpixels = width;
	int height = *(int*)&HeaderInfo[22];		ip.Vpixels = height;
	int RowBytes = (width * 3 + 3) & (~3);		ip.Hbytes = RowBytes;
	//save header for re-use
	memcpy(ip.HeaderInfo, HeaderInfo,54);
	printf("\n Input File name: %17s  (%u x %u)   File Size=%u", fn, 
			ip.Hpixels, ip.Vpixels, IMAGESIZE);
	// allocate memory to store the main image (1 Dimensional array)
	Img  = (uch *)malloc(IMAGESIZE);
	if (Img == NULL) return Img;      // Cannot allocate memory
	// read the image from disk
	fread(Img, sizeof(uch), IMAGESIZE, f);
	fclose(f);
	return Img;
}


// Write the 1D linear-memory stored image into file.
void WriteBMPlin(uch *Img, char* fn)
{
	FILE* f = fopen(fn, "wb");
	if (f == NULL){ printf("\n\nFILE CREATION ERROR: %s\n\n", fn); exit(1); }
	//write header
	fwrite(ip.HeaderInfo, sizeof(uch), 54, f);
	//write data
	fwrite(Img, sizeof(uch), IMAGESIZE, f);
	printf("\nOutput File name: %17s  (%u x %u)   File Size=%u", fn, ip.Hpixels, ip.Vpixels, IMAGESIZE);
	fclose(f);
}


int main(int argc, char **argv)
{

	float /*totalTime, tfrCPUtoGPU, tfrGPUtoCPU,*/ kernelExecutionTime; // GPU code run times
	cudaError_t cudaStatus;
	cudaEvent_t time1, time2;//, time3, time4;
	char InputFileName[255], OutputFileName[255], ProgName[255];
	ui BlkPerRow, ThrPerBlk=256, NumBlocks, /* GPUDataTransfer,*/ NumBlocksNP;
	cudaDeviceProp GPUprop;
	ul SupportedKBlocks, SupportedMBlocks, MaxThrPerBlk;		char SupportedBlocks[100]; 

	ui GPUtotalBufferSize, R = 5, T = 5, NumNoisyPixelsCPU, mutexInit[4] = {0, 255, 0, 0};
	ui CPU_SAD;

	strcpy(ProgName, "randNoiseRemoval");
	switch (argc){
	case 6:  ThrPerBlk = atoi(argv[5]);
	case 5:  R = atoi(argv[4]);
	case 4:  T = atoi(argv[3]);
	case 3:  strcpy(InputFileName, argv[1]);
			 strcpy(OutputFileName, argv[2]);
			 break;
	default: printf("\n\nUsage:   %s InputFilename OutputFilename [T] [R] [ThrPerBlk]", ProgName);
			 printf("\n\nExample: %s Astronaut.bmp Output.bmp", ProgName);
			 printf("\n\nExample: %s Astronaut.bmp Output.bmp 5", ProgName);
			 printf("\n\nExample: %s Astronaut.bmp Output.bmp 5 5",ProgName);
			 printf("\n\nExample: %s Astronaut.bmp Output.bmp 5 5 128",ProgName);
			 printf("\n\nT = reconstruction threshold, R = mask selection threshold\n\n");
			 exit(EXIT_FAILURE);
	}

	if ((ThrPerBlk < 32) || (ThrPerBlk > 1024)) {
		printf("Invalid ThrPerBlk option '%u'. Must be between 32 and 1024. \n", ThrPerBlk);
		exit(EXIT_FAILURE);
	}
	

	// Create CPU memory to store the input and output images
	TheImg = ReadBMPlin(InputFileName); // Read the input image if memory can be allocated
	if (TheImg == NULL){
		printf("Cannot allocate memory for the input image...\n");
		exit(EXIT_FAILURE);
	}
	CopyImg = (uch *)malloc(IMAGESIZE);
	if (CopyImg == NULL){
		free(TheImg);
		printf("Cannot allocate memory for the input image...\n");
		exit(EXIT_FAILURE);
	}


	// Choose which GPU to run on, change this on a multi-GPU system.
	int NumGPUs = 0;
	cudaGetDeviceCount(&NumGPUs);
	if (NumGPUs == 0){
		printf("\nNo CUDA Device is available\n");
		exit(EXIT_FAILURE);
	}
	cudaStatus = cudaSetDevice(0);
	if (cudaStatus != cudaSuccess) {
		fprintf(stderr, "cudaSetDevice failed!  Do you have a CUDA-capable GPU installed?");
		exit(EXIT_FAILURE);
	}

	
	cudaGetDeviceProperties(&GPUprop, 0);
	SupportedKBlocks = (ui)GPUprop.maxGridSize[0] * (ui)GPUprop.maxGridSize[1] * (ui)GPUprop.maxGridSize[2] / 1024;
	SupportedMBlocks = SupportedKBlocks / 1024;
	sprintf(SupportedBlocks, "%u %c", (SupportedMBlocks >= 5) ? SupportedMBlocks : SupportedKBlocks, (SupportedMBlocks >= 5) ? 'M' : 'K');
	MaxThrPerBlk = (ui)GPUprop.maxThreadsPerBlock;

	cudaEventCreate(&time1);
	cudaEventCreate(&time2);
	// cudaEventCreate(&time3);
	// cudaEventCreate(&time4);

	

/*
	>>> GPU STORAGE DETAILS >>>
	GPUImage: IMAGESIZE
	GPUCopyImage(BW) : IMAGEPIX
	NoisyPixelCoords: IMAGEPIX*sizeof(pixelCoords)
	NoiseMap : IMAGEPIX
	KernelIndices : IMAGEPIX
	GlobalMax : sizeof(ui)
	GlobalMin : sizeof(ui)
	NumNoisyPixelsGPU : sizeof(ui)
	GPU_PREV_BW : sizeof(double) * IMAGEPIX
	GPU_CURR_BW : sizeof(double) * IMAGEPIX  
	GPU_SAD : sizeof(ui)
	 ***********************

*/
	// allocate sufficient memory on the GPU to hold all above items
	GPUtotalBufferSize = IMAGESIZE+(IMAGEPIX*sizeof(pixelCoords))+IMAGEPIX*3+sizeof(ui)*4+2*(sizeof(double)*IMAGEPIX);
	cudaStatus = cudaMalloc((void**)&GPUptr, GPUtotalBufferSize);
	if (cudaStatus != cudaSuccess) {
		fprintf(stderr, "cudaMalloc failed! Can't allocate GPU memory for buffers");
		exit(EXIT_FAILURE);
	}

	// setup buffer pointers for functions
	GPUImg			= (uch *)GPUptr;
	GPUCopyImg	= GPUImg + IMAGESIZE;
	NoiseMap = GPUCopyImg + IMAGEPIX;  // add the previous image/array of noisy pixel intensities
	KernelIndices = NoiseMap + IMAGEPIX;
	NoisyPixelCoords = (pixelCoords*)(KernelIndices + IMAGEPIX);
	GPU_PREV_BW = (double*)(NoisyPixelCoords+IMAGEPIX);
	GPU_CURR_BW = GPU_PREV_BW + IMAGEPIX;
	GlobalMax = (ui*)(GPU_CURR_BW + IMAGEPIX);
	GlobalMin = GlobalMax+1;
	NumNoisyPixelsGPU = GlobalMin+1;
	GPU_SAD = NumNoisyPixelsGPU+1;


	// Copy input vectors from host memory to GPU buffers.
	cudaStatus = cudaMemcpy(GPUImg, TheImg, IMAGESIZE, cudaMemcpyHostToDevice);
	if (cudaStatus != cudaSuccess) {
		fprintf(stderr, "cudaMemcpy for input image CPU to GPU  failed!");
		exit(EXIT_FAILURE);
	}

	// Copy mutex initializations from CPU to GPU
	cudaStatus = cudaMemcpy(GlobalMax, mutexInit, 4*sizeof(ui), cudaMemcpyHostToDevice);
	if (cudaStatus != cudaSuccess) {
		fprintf(stderr, "cudaMemcpy for mutex initializations CPU to GPU  failed!");
		exit(EXIT_FAILURE);
	}

	// assume pixels are not noisy by default
	cudaStatus = cudaMemset (NoiseMap, 1, IMAGEPIX );
	if (cudaStatus != cudaSuccess) {
		fprintf(stderr, "cudaMemset for Noise Map failed!");
		exit(EXIT_FAILURE);
	}

	cudaEventRecord(time1, 0);		// Time stamp at the start of the GPU transfer

	
	BlkPerRow = CEIL(ip.Hpixels, ThrPerBlk);
	NumBlocks = IPV*BlkPerRow;
	

	BWKernel <<< NumBlocks, ThrPerBlk >>> (GPUCopyImg, GPUImg, GPU_CURR_BW, IPH);
	cudaStatus = cudaDeviceSynchronize();
	if (cudaStatus != cudaSuccess) {
		fprintf(stderr, "\n\n cudaDeviceSynchronize for B&WKernel returned error code %d after launching the kernel!\n", cudaStatus);
		exit(EXIT_FAILURE);
	}


	findNoisyPixels <<< NumBlocks, ThrPerBlk >>> (NoisyPixelCoords, GPUCopyImg, NoiseMap, GlobalMax, GlobalMin, NumNoisyPixelsGPU, IPH, IPV);
	
	// cudaDeviceSynchronize waits for the kernel to finish, and returns
	// any errors encountered during the launch.
	cudaStatus = cudaDeviceSynchronize();
	if (cudaStatus != cudaSuccess) {
		fprintf(stderr, "\n\ncudaDeviceSynchronize for findNoisyPixels returned error code %d after launching the kernel!\n", cudaStatus);
		exit(EXIT_FAILURE);
	}

	//cudaEventRecord(time3, 0);

	cudaStatus = cudaMemcpy(&NumNoisyPixelsCPU, NumNoisyPixelsGPU, sizeof(ui), cudaMemcpyDeviceToHost);
	if (cudaStatus != cudaSuccess) {
		fprintf(stderr, "cudaMemcpy of NumNoisyPixels, GPU to CPU  failed!");
		exit(EXIT_FAILURE);
	}


	// only schedule as many threads are needed for NoisyPixelListLength
	NumBlocksNP = CEIL(NumNoisyPixelsCPU, ThrPerBlk);
	
	determineMasks <<< NumBlocksNP, ThrPerBlk >>> (NoisyPixelCoords, GPUCopyImg, NoiseMap, KernelIndices, NumNoisyPixelsCPU, IPH, R);

	cudaStatus = cudaDeviceSynchronize();
	if (cudaStatus != cudaSuccess) {
		fprintf(stderr, "\n\ncudaDeviceSynchronize for determineMasks returned error code %d after launching the kernel!\n", cudaStatus);
		exit(EXIT_FAILURE);
	}

	PixCopy <<< NumBlocks, ThrPerBlk >>> (GPU_PREV_BW, GPU_CURR_BW, IMAGEPIX);
	cudaStatus = cudaDeviceSynchronize();
	if (cudaStatus != cudaSuccess) {
		fprintf(stderr, "\n\ncudaDeviceSynchronize for PixCopy returned error code %d after launching the kernel!\n", cudaStatus);
		exit(EXIT_FAILURE);
	}

int t=1;
	// progress tracking 
	do{

		// reset SAD (sum of absolute pixel differences)
		cudaStatus = cudaMemset (GPU_SAD, 0, sizeof(ui) );
		if (cudaStatus != cudaSuccess) {
			fprintf(stderr, "cudaMemset for GPU_SAD failed!");
			exit(EXIT_FAILURE);
		}
		
		Convolute <<< NumBlocksNP, ThrPerBlk >>> (GPU_CURR_BW, GPU_PREV_BW,  NoisyPixelCoords,  KernelIndices, NumNoisyPixelsCPU, IPH);

		cudaStatus = cudaDeviceSynchronize();
		if (cudaStatus != cudaSuccess) {
			fprintf(stderr, "\n\n cudaDeviceSynchronize for Convolute returned error code %d after launching the kernel!\n", cudaStatus);
			exit(EXIT_FAILURE);
		}

		SAD <<< NumBlocksNP, ThrPerBlk >>> (GPU_SAD, GPU_PREV_BW, GPU_CURR_BW, NoisyPixelCoords, NumNoisyPixelsCPU, IPH, IPV);

		cudaStatus = cudaDeviceSynchronize();
		if (cudaStatus != cudaSuccess) {
			fprintf(stderr, "\n\n cudaDeviceSynchronize for SAD returned error code %d after launching the kernel!\n", cudaStatus);
			exit(EXIT_FAILURE);
		}

		NoisyPixCopy <<< NumBlocksNP, ThrPerBlk >>> (GPU_PREV_BW, GPU_CURR_BW, NoisyPixelCoords, NumNoisyPixelsCPU, IPH);

		cudaStatus = cudaDeviceSynchronize();
		if (cudaStatus != cudaSuccess) {
			fprintf(stderr, "\n\n cudaDeviceSynchronize for NoisyPixCopy returned error code %d after launching the kernel!\n", cudaStatus);
			exit(EXIT_FAILURE);
		}

		// CudaMemcpy the SAD from GPU to CPU 
		cudaStatus = cudaMemcpy(&CPU_SAD, GPU_SAD, sizeof(ui), cudaMemcpyDeviceToHost);
		if (cudaStatus != cudaSuccess) {
			fprintf(stderr, "cudaMemcpy of SAD from GPU to CPU  failed!");
			exit(EXIT_FAILURE);
		}

        
    
    // must convert floating point B&W back to unsigned char format
	NumBlocks = IPV*BlkPerRow;
	RGBKernel <<< NumBlocks, ThrPerBlk >>> (GPUImg, GPU_CURR_BW, IPH);
    GPUResult = GPUImg;
    
    //Copy output (results) from GPU buffer to host (CPU) memory.
	cudaStatus = cudaMemcpy(CopyImg, GPUResult, IMAGESIZE, cudaMemcpyDeviceToHost);
	if (cudaStatus != cudaSuccess) {
		fprintf(stderr, "cudaMemcpy GPU to CPU  failed!");
		exit(EXIT_FAILURE);
    }
        
        sprintf(OutputFileName, "%s%d%s", "stages/stage", t++, ".bmp");
        WriteBMPlin(CopyImg, OutputFileName);		// Write the flipped image back to disk

	} while(CPU_SAD > T);


	

	cudaEventRecord(time2, 0);		// Time stamp after the CPU --> GPU tfr is done

	//GPUDataTransfer = GPUtotalBufferSize;

	

	//cudaEventRecord(time4, 0);

	cudaEventSynchronize(time1);
	cudaEventSynchronize(time2);
	//cudaEventSynchronize(time3);
	//cudaEventSynchronize(time4);

	//cudaEventElapsedTime(&totalTime, time1, time4);
	//cudaEventElapsedTime(&tfrCPUtoGPU, time1, time2);
	cudaEventElapsedTime(&kernelExecutionTime, time1, time2);
	//cudaEventElapsedTime(&tfrGPUtoCPU, time3, time4);

	cudaStatus = cudaDeviceSynchronize();
	//checkError(cudaGetLastError());	// screen for errors in kernel launches
	if (cudaStatus != cudaSuccess) {
		fprintf(stderr, "\n Program failed after cudaDeviceSynchronize()!");
		free(TheImg);
		free(CopyImg);
		exit(EXIT_FAILURE);
	}
	
	printf("\n\n--------------------------------------------------------------------------\n");
	printf("%s    ComputeCapab=%d.%d  [max %s blocks; %d thr/blk] \n", 
			GPUprop.name, GPUprop.major, GPUprop.minor, SupportedBlocks, MaxThrPerBlk);
	printf("--------------------------------------------------------------------------\n");
	printf("%s %s %s %d %d %u   [%u BLOCKS, %u BLOCKS/ROW]\n", ProgName, InputFileName, OutputFileName,
			T, R, ThrPerBlk, NumBlocks, BlkPerRow);
	// printf("--------------------------------------------------------------------------\n");
	// printf("CPU->GPU Transfer   =%7.2f ms  ...  %4d MB  ...  %6.2f GB/s\n", tfrCPUtoGPU, DATAMB(IMAGESIZE), DATABW(IMAGESIZE, tfrCPUtoGPU));
	printf("Kernel Execution    =%7.2f ms\n", kernelExecutionTime);//, DATAMB(GPUDataTransfer), DATABW(GPUDataTransfer, kernelExecutionTime));  ...  %4d MB  ...  %6.2f GB/s
	// printf("GPU->CPU Transfer   =%7.2f ms  ...  %4d MB  ...  %6.2f GB/s\n", tfrGPUtoCPU, DATAMB(IMAGESIZE), DATABW(IMAGESIZE, tfrGPUtoCPU));
	// printf("--------------------------------------------------------------------------\n");
	// printf("Total time elapsed  =%7.2f ms       %4d MB  ...  %6.2f GB/s\n", totalTime, DATAMB((2 * IMAGESIZE + GPUDataTransfer)), DATABW((2 * IMAGESIZE + GPUDataTransfer), totalTime));
	printf("--------------------------------------------------------------------------\n\n");

	// Deallocate CPU, GPU memory and destroy events.
	cudaFree(GPUptr);
	cudaEventDestroy(time1);
	cudaEventDestroy(time2);
	// cudaEventDestroy(time3);
	// cudaEventDestroy(time4);
	// cudaDeviceReset must be called before exiting in order for profiling and
	// tracing tools such as Parallel Nsight and Visual Profiler to show complete traces.
	cudaStatus = cudaDeviceReset();
	if (cudaStatus != cudaSuccess) {
		fprintf(stderr, "cudaDeviceReset failed!");
		free(TheImg);
		free(CopyImg);
		exit(EXIT_FAILURE);
	}

	free(TheImg);
	free(CopyImg);
	return(EXIT_SUCCESS);
}




	.file	"tmpxft_0030e3e7_00000000-6_randNoiseRemovergif.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3854:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3854:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"rb"
.LC1:
	.string	"\n\n%s NOT FOUND\n\n"
.LC2:
	.string	"\n Input File name: %17s  (%u x %u)   File Size=%u"
	.text
	.globl	_Z10ReadBMPlinPc
	.type	_Z10ReadBMPlinPc, @function
_Z10ReadBMPlinPc:
.LFB3849:
	.cfi_startproc
	endbr64
	pushq	%r12
	.cfi_def_cfa_offset 16
	.cfi_offset 12, -16
	leaq	.LC0(%rip), %rsi
	pushq	%rbp
	.cfi_def_cfa_offset 24
	.cfi_offset 6, -24
	movq	%rdi, %rbp
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset 3, -32
	subq	$64, %rsp
	.cfi_def_cfa_offset 96
	movq	%fs:40, %rax
	movq	%rax, 56(%rsp)
	xorl	%eax, %eax
	call	fopen@PLT
	testq	%rax, %rax
	jne	.L3
	movl	$2, %edi
	movq	%rbp, %rdx
	leaq	.LC1(%rip), %rsi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movl	$1, %edi
	call	exit@PLT
.L3:
	leaq	2(%rsp), %r12
	movq	%rax, %r8
	movl	$54, %ecx
	movq	%rax, %rbx
	movl	$1, %edx
	movl	$54, %esi
	movq	%r12, %rdi
	call	__fread_chk@PLT
	movl	20(%rsp), %edx
	movl	24(%rsp), %r8d
	movq	%r12, %rsi
	leaq	8+ip(%rip), %r9
	movl	$54, %ecx
	leal	1(%rdx), %eax
	movq	%r9, %rdi
	movslq	%r8d, %r9
	movl	%edx, ip(%rip)
	rep movsb
	leal	(%rax,%rax,2), %eax
	movl	%edx, %ecx
	leaq	.LC2(%rip), %rsi
	andl	$-4, %eax
	movq	%rbp, %rdx
	movl	$2, %edi
	movl	%r8d, 4+ip(%rip)
	cltq
	imulq	%rax, %r9
	movq	%rax, 64+ip(%rip)
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movslq	4+ip(%rip), %rbp
	imulq	64+ip(%rip), %rbp
	movq	%rbp, %rdi
	call	malloc@PLT
	movq	%rax, _ZZ10ReadBMPlinPcE3Img(%rip)
	testq	%rax, %rax
	je	.L2
	movq	%rbx, %r8
	movq	%rbp, %rcx
	movl	$1, %edx
	movq	%rbp, %rsi
	movq	%rax, %rdi
	call	__fread_chk@PLT
	movq	%rbx, %rdi
	call	fclose@PLT
	movq	_ZZ10ReadBMPlinPcE3Img(%rip), %rax
.L2:
	movq	56(%rsp), %rdx
	subq	%fs:40, %rdx
	je	.L5
	call	__stack_chk_fail@PLT
.L5:
	addq	$64, %rsp
	.cfi_def_cfa_offset 32
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3849:
	.size	_Z10ReadBMPlinPc, .-_Z10ReadBMPlinPc
	.section	.rodata.str1.1
.LC3:
	.string	"wb"
.LC4:
	.string	"\n\nFILE CREATION ERROR: %s\n\n"
.LC5:
	.string	"\nOutput File name: %17s  (%u x %u)   File Size=%u"
	.text
	.globl	_Z11WriteBMPlinPhPc
	.type	_Z11WriteBMPlinPhPc, @function
_Z11WriteBMPlinPhPc:
.LFB3850:
	.cfi_startproc
	endbr64
	pushq	%r12
	.cfi_def_cfa_offset 16
	.cfi_offset 12, -16
	movq	%rdi, %r12
	pushq	%rbp
	.cfi_def_cfa_offset 24
	.cfi_offset 6, -24
	movq	%rsi, %rbp
	leaq	.LC3(%rip), %rsi
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset 3, -32
	movq	%rbp, %rdi
	call	fopen@PLT
	testq	%rax, %rax
	jne	.L12
	movl	$2, %edi
	movq	%rbp, %rdx
	leaq	.LC4(%rip), %rsi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movl	$1, %edi
	call	exit@PLT
.L12:
	movq	%rax, %rcx
	movl	$54, %edx
	movl	$1, %esi
	movq	%rax, %rbx
	leaq	8+ip(%rip), %rdi
	call	fwrite@PLT
	movq	%rbx, %rcx
	movq	%r12, %rdi
	movl	$1, %esi
	movslq	4+ip(%rip), %rdx
	imulq	64+ip(%rip), %rdx
	call	fwrite@PLT
	movl	ip(%rip), %ecx
	movq	%rbp, %rdx
	xorl	%eax, %eax
	movslq	4+ip(%rip), %r9
	imulq	64+ip(%rip), %r9
	movl	$2, %edi
	leaq	.LC5(%rip), %rsi
	movl	4+ip(%rip), %r8d
	call	__printf_chk@PLT
	movq	%rbx, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	jmp	fclose@PLT
	.cfi_endproc
.LFE3850:
	.size	_Z11WriteBMPlinPhPc, .-_Z11WriteBMPlinPhPc
	.globl	_Z62__device_stub__Z15findNoisyPixelsP11pixelCoordsPhS1_PjS2_S2_jjP11pixelCoordsPhS1_PjS2_S2_jj
	.type	_Z62__device_stub__Z15findNoisyPixelsP11pixelCoordsPhS1_PjS2_S2_jjP11pixelCoordsPhS1_PjS2_S2_jj, @function
_Z62__device_stub__Z15findNoisyPixelsP11pixelCoordsPhS1_PjS2_S2_jjP11pixelCoordsPhS1_PjS2_S2_jj:
.LFB3876:
	.cfi_startproc
	endbr64
	subq	$200, %rsp
	.cfi_def_cfa_offset 208
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	56(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	64(%rsp), %rcx
	movq	%r8, 8(%rsp)
	movq	%r9, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 184(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 152(%rsp)
	movq	%rsp, %rax
	movq	%rax, 160(%rsp)
	leaq	208(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	216(%rsp), %rax
	movq	%rax, 176(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L14
	pushq	64(%rsp)
	.cfi_def_cfa_offset 216
	leaq	_Z15findNoisyPixelsP11pixelCoordsPhS1_PjS2_S2_jj(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 224
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 216
	popq	%rdx
	.cfi_def_cfa_offset 208
.L14:
	movq	184(%rsp), %rax
	subq	%fs:40, %rax
	je	.L16
	call	__stack_chk_fail@PLT
.L16:
	addq	$200, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3876:
	.size	_Z62__device_stub__Z15findNoisyPixelsP11pixelCoordsPhS1_PjS2_S2_jjP11pixelCoordsPhS1_PjS2_S2_jj, .-_Z62__device_stub__Z15findNoisyPixelsP11pixelCoordsPhS1_PjS2_S2_jjP11pixelCoordsPhS1_PjS2_S2_jj
	.globl	_Z15findNoisyPixelsP11pixelCoordsPhS1_PjS2_S2_jj
	.type	_Z15findNoisyPixelsP11pixelCoordsPhS1_PjS2_S2_jj, @function
_Z15findNoisyPixelsP11pixelCoordsPhS1_PjS2_S2_jj:
.LFB3877:
	.cfi_startproc
	endbr64
	jmp	_Z62__device_stub__Z15findNoisyPixelsP11pixelCoordsPhS1_PjS2_S2_jjP11pixelCoordsPhS1_PjS2_S2_jj
	.cfi_endproc
.LFE3877:
	.size	_Z15findNoisyPixelsP11pixelCoordsPhS1_PjS2_S2_jj, .-_Z15findNoisyPixelsP11pixelCoordsPhS1_PjS2_S2_jj
	.globl	_Z57__device_stub__Z14determineMasksP11pixelCoordsPhS1_S1_jjjP11pixelCoordsPhS1_S1_jjj
	.type	_Z57__device_stub__Z14determineMasksP11pixelCoordsPhS1_S1_jjjP11pixelCoordsPhS1_S1_jjj, @function
_Z57__device_stub__Z14determineMasksP11pixelCoordsPhS1_S1_jjjP11pixelCoordsPhS1_S1_jjj:
.LFB3878:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	48(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	56(%rsp), %rcx
	movl	%r8d, 12(%rsp)
	movl	%r9d, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 112(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	192(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L19
	pushq	56(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z14determineMasksP11pixelCoordsPhS1_S1_jjj(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 208
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L19:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L21
	call	__stack_chk_fail@PLT
.L21:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3878:
	.size	_Z57__device_stub__Z14determineMasksP11pixelCoordsPhS1_S1_jjjP11pixelCoordsPhS1_S1_jjj, .-_Z57__device_stub__Z14determineMasksP11pixelCoordsPhS1_S1_jjjP11pixelCoordsPhS1_S1_jjj
	.globl	_Z14determineMasksP11pixelCoordsPhS1_S1_jjj
	.type	_Z14determineMasksP11pixelCoordsPhS1_S1_jjj, @function
_Z14determineMasksP11pixelCoordsPhS1_S1_jjj:
.LFB3879:
	.cfi_startproc
	endbr64
	jmp	_Z57__device_stub__Z14determineMasksP11pixelCoordsPhS1_S1_jjjP11pixelCoordsPhS1_S1_jjj
	.cfi_endproc
.LFE3879:
	.size	_Z14determineMasksP11pixelCoordsPhS1_S1_jjj, .-_Z14determineMasksP11pixelCoordsPhS1_S1_jjj
	.globl	_Z48__device_stub__Z9ConvolutePdS_P11pixelCoordsPhjjPdS_P11pixelCoordsPhjj
	.type	_Z48__device_stub__Z9ConvolutePdS_P11pixelCoordsPhjjPdS_P11pixelCoordsPhjj, @function
_Z48__device_stub__Z9ConvolutePdS_P11pixelCoordsPhjjPdS_P11pixelCoordsPhjj:
.LFB3880:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	56(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	64(%rsp), %rcx
	movl	%r8d, 12(%rsp)
	movl	%r9d, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L24
	pushq	64(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z9ConvolutePdS_P11pixelCoordsPhjj(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 208
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L24:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L26
	call	__stack_chk_fail@PLT
.L26:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3880:
	.size	_Z48__device_stub__Z9ConvolutePdS_P11pixelCoordsPhjjPdS_P11pixelCoordsPhjj, .-_Z48__device_stub__Z9ConvolutePdS_P11pixelCoordsPhjjPdS_P11pixelCoordsPhjj
	.globl	_Z9ConvolutePdS_P11pixelCoordsPhjj
	.type	_Z9ConvolutePdS_P11pixelCoordsPhjj, @function
_Z9ConvolutePdS_P11pixelCoordsPhjj:
.LFB3881:
	.cfi_startproc
	endbr64
	jmp	_Z48__device_stub__Z9ConvolutePdS_P11pixelCoordsPhjjPdS_P11pixelCoordsPhjj
	.cfi_endproc
.LFE3881:
	.size	_Z9ConvolutePdS_P11pixelCoordsPhjj, .-_Z9ConvolutePdS_P11pixelCoordsPhjj
	.globl	_Z44__device_stub__Z3SADPjPdS0_P11pixelCoordsjjjPjPdS0_P11pixelCoordsjjj
	.type	_Z44__device_stub__Z3SADPjPdS0_P11pixelCoordsjjjPjPdS0_P11pixelCoordsjjj, @function
_Z44__device_stub__Z3SADPjPdS0_P11pixelCoordsjjjPjPdS0_P11pixelCoordsjjj:
.LFB3882:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	48(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	56(%rsp), %rcx
	movl	%r8d, 12(%rsp)
	movl	%r9d, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 112(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	192(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L29
	pushq	56(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z3SADPjPdS0_P11pixelCoordsjjj(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 208
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L29:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L31
	call	__stack_chk_fail@PLT
.L31:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3882:
	.size	_Z44__device_stub__Z3SADPjPdS0_P11pixelCoordsjjjPjPdS0_P11pixelCoordsjjj, .-_Z44__device_stub__Z3SADPjPdS0_P11pixelCoordsjjjPjPdS0_P11pixelCoordsjjj
	.globl	_Z3SADPjPdS0_P11pixelCoordsjjj
	.type	_Z3SADPjPdS0_P11pixelCoordsjjj, @function
_Z3SADPjPdS0_P11pixelCoordsjjj:
.LFB3883:
	.cfi_startproc
	endbr64
	jmp	_Z44__device_stub__Z3SADPjPdS0_P11pixelCoordsjjjPjPdS0_P11pixelCoordsjjj
	.cfi_endproc
.LFE3883:
	.size	_Z3SADPjPdS0_P11pixelCoordsjjj, .-_Z3SADPjPdS0_P11pixelCoordsjjj
	.globl	_Z32__device_stub__Z8BWKernelPhS_PdjPhS_Pdj
	.type	_Z32__device_stub__Z8BWKernelPhS_PdjPhS_Pdj, @function
_Z32__device_stub__Z8BWKernelPhS_PdjPhS_Pdj:
.LFB3884:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 4(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L34
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z8BWKernelPhS_Pdj(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L34:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L36
	call	__stack_chk_fail@PLT
.L36:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3884:
	.size	_Z32__device_stub__Z8BWKernelPhS_PdjPhS_Pdj, .-_Z32__device_stub__Z8BWKernelPhS_PdjPhS_Pdj
	.globl	_Z8BWKernelPhS_Pdj
	.type	_Z8BWKernelPhS_Pdj, @function
_Z8BWKernelPhS_Pdj:
.LFB3885:
	.cfi_startproc
	endbr64
	jmp	_Z32__device_stub__Z8BWKernelPhS_PdjPhS_Pdj
	.cfi_endproc
.LFE3885:
	.size	_Z8BWKernelPhS_Pdj, .-_Z8BWKernelPhS_Pdj
	.globl	_Z31__device_stub__Z9RGBKernelPhPdjPhPdj
	.type	_Z31__device_stub__Z9RGBKernelPhPdjPhPdj, @function
_Z31__device_stub__Z9RGBKernelPhPdjPhPdj:
.LFB3886:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L39
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z9RGBKernelPhPdj(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L39:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L41
	call	__stack_chk_fail@PLT
.L41:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3886:
	.size	_Z31__device_stub__Z9RGBKernelPhPdjPhPdj, .-_Z31__device_stub__Z9RGBKernelPhPdjPhPdj
	.globl	_Z9RGBKernelPhPdj
	.type	_Z9RGBKernelPhPdj, @function
_Z9RGBKernelPhPdj:
.LFB3887:
	.cfi_startproc
	endbr64
	jmp	_Z31__device_stub__Z9RGBKernelPhPdjPhPdj
	.cfi_endproc
.LFE3887:
	.size	_Z9RGBKernelPhPdj, .-_Z9RGBKernelPhPdj
	.globl	_Z50__device_stub__Z12NoisyPixCopyPdS_P11pixelCoordsjjPdS_P11pixelCoordsjj
	.type	_Z50__device_stub__Z12NoisyPixCopyPdS_P11pixelCoordsjjPdS_P11pixelCoordsjj, @function
_Z50__device_stub__Z12NoisyPixCopyPdS_P11pixelCoordsjjPdS_P11pixelCoordsjj:
.LFB3888:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	32(%rsp), %rdx
	movl	%ecx, 4(%rsp)
	leaq	40(%rsp), %rcx
	movl	%r8d, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L44
	pushq	40(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z12NoisyPixCopyPdS_P11pixelCoordsjj(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 176
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L44:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L46
	call	__stack_chk_fail@PLT
.L46:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3888:
	.size	_Z50__device_stub__Z12NoisyPixCopyPdS_P11pixelCoordsjjPdS_P11pixelCoordsjj, .-_Z50__device_stub__Z12NoisyPixCopyPdS_P11pixelCoordsjjPdS_P11pixelCoordsjj
	.globl	_Z12NoisyPixCopyPdS_P11pixelCoordsjj
	.type	_Z12NoisyPixCopyPdS_P11pixelCoordsjj, @function
_Z12NoisyPixCopyPdS_P11pixelCoordsjj:
.LFB3889:
	.cfi_startproc
	endbr64
	jmp	_Z50__device_stub__Z12NoisyPixCopyPdS_P11pixelCoordsjjPdS_P11pixelCoordsjj
	.cfi_endproc
.LFE3889:
	.size	_Z12NoisyPixCopyPdS_P11pixelCoordsjj, .-_Z12NoisyPixCopyPdS_P11pixelCoordsjj
	.globl	_Z29__device_stub__Z7PixCopyPdS_jPdS_j
	.type	_Z29__device_stub__Z7PixCopyPdS_jPdS_j, @function
_Z29__device_stub__Z7PixCopyPdS_jPdS_j:
.LFB3890:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L49
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z7PixCopyPdS_j(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L49:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L51
	call	__stack_chk_fail@PLT
.L51:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3890:
	.size	_Z29__device_stub__Z7PixCopyPdS_jPdS_j, .-_Z29__device_stub__Z7PixCopyPdS_jPdS_j
	.globl	_Z7PixCopyPdS_j
	.type	_Z7PixCopyPdS_j, @function
_Z7PixCopyPdS_j:
.LFB3891:
	.cfi_startproc
	endbr64
	jmp	_Z29__device_stub__Z7PixCopyPdS_jPdS_j
	.cfi_endproc
.LFE3891:
	.size	_Z7PixCopyPdS_j, .-_Z7PixCopyPdS_j
	.section	.rodata.str1.1
.LC6:
	.string	"\n\nUsage:   %s InputFilename OutputFilename [T] [R] [ThrPerBlk]"
.LC7:
	.string	"\n\nExample: %s Astronaut.bmp Output.bmp"
.LC8:
	.string	"\n\nExample: %s Astronaut.bmp Output.bmp 5"
.LC9:
	.string	"\n\nExample: %s Astronaut.bmp Output.bmp 5 5"
.LC10:
	.string	"\n\nExample: %s Astronaut.bmp Output.bmp 5 5 128"
.LC11:
	.string	"\n\nT = reconstruction threshold, R = mask selection threshold\n\n"
.LC12:
	.string	"Invalid ThrPerBlk option '%u'. Must be between 32 and 1024. \n"
.LC13:
	.string	"Cannot allocate memory for the input image...\n"
.LC14:
	.string	"\nNo CUDA Device is available\n"
.LC15:
	.string	"cudaSetDevice failed!  Do you have a CUDA-capable GPU installed?"
.LC16:
	.string	"%u %c"
.LC17:
	.string	"cudaMalloc failed! Can't allocate GPU memory for buffers"
.LC18:
	.string	"cudaMemcpy for input image CPU to GPU  failed!"
.LC19:
	.string	"cudaMemcpy for mutex initializations CPU to GPU  failed!"
.LC20:
	.string	"cudaMemset for Noise Map failed!"
.LC21:
	.string	"\n\n cudaDeviceSynchronize for B&WKernel returned error code %d after launching the kernel!\n"
.LC22:
	.string	"\n\ncudaDeviceSynchronize for findNoisyPixels returned error code %d after launching the kernel!\n"
.LC23:
	.string	"cudaMemcpy of NumNoisyPixels, GPU to CPU  failed!"
.LC24:
	.string	"\n\ncudaDeviceSynchronize for determineMasks returned error code %d after launching the kernel!\n"
.LC25:
	.string	"\n\ncudaDeviceSynchronize for PixCopy returned error code %d after launching the kernel!\n"
.LC26:
	.string	"cudaMemset for GPU_SAD failed!"
.LC27:
	.string	"\n\n cudaDeviceSynchronize for Convolute returned error code %d after launching the kernel!\n"
.LC28:
	.string	"\n\n cudaDeviceSynchronize for SAD returned error code %d after launching the kernel!\n"
.LC29:
	.string	"\n\n cudaDeviceSynchronize for NoisyPixCopy returned error code %d after launching the kernel!\n"
.LC30:
	.string	"cudaMemcpy of SAD from GPU to CPU  failed!"
.LC31:
	.string	"cudaMemcpy GPU to CPU  failed!"
.LC32:
	.string	"stages/stage"
.LC33:
	.string	"%s%d%s"
.LC34:
	.string	".bmp"
.LC35:
	.string	"\n Program failed after cudaDeviceSynchronize()!"
.LC36:
	.string	"\n\n--------------------------------------------------------------------------\n"
.LC37:
	.string	"%s    ComputeCapab=%d.%d  [max %s blocks; %d thr/blk] \n"
.LC38:
	.string	"--------------------------------------------------------------------------\n"
.LC39:
	.string	"%s %s %s %d %d %u   [%u BLOCKS, %u BLOCKS/ROW]\n"
.LC40:
	.string	"Kernel Execution    =%7.2f ms\n"
.LC41:
	.string	"--------------------------------------------------------------------------\n\n"
.LC42:
	.string	"cudaDeviceReset failed!"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB3851:
	.cfi_startproc
	endbr64
	movabsq	$7809653449785954917, %rdx
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movq	%rsi, %rbp
	xorl	%esi, %esi
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$2040, %rsp
	.cfi_def_cfa_offset 2096
	movq	%fs:40, %rax
	movq	%rax, 2024(%rsp)
	movabsq	$1095216660480, %rax
	movq	%rsi, 112(%rsp)
	movq	%rdx, 1777(%rsp)
	movb	$0, 1785(%rsp)
	movq	%rax, 104(%rsp)
	movabsq	$8316300569399419250, %rax
	movq	%rax, 1769(%rsp)
	cmpl	$5, %edi
	je	.L93
	jg	.L56
	cmpl	$3, %edi
	je	.L94
	movl	$5, %r12d
	movl	$256, %ebx
	cmpl	$4, %edi
	je	.L58
	jmp	.L59
.L56:
	cmpl	$6, %edi
	jne	.L59
	movq	40(%rbp), %rdi
	call	atoi@PLT
	movl	%eax, %ebx
	jmp	.L55
.L93:
	movl	$256, %ebx
.L55:
	movq	32(%rbp), %rdi
	call	atoi@PLT
	movl	%eax, %r12d
.L58:
	movq	24(%rbp), %rdi
	call	atoi@PLT
	movl	%eax, 4(%rsp)
	jmp	.L57
.L94:
	movl	$5, 4(%rsp)
	movl	$5, %r12d
	movl	$256, %ebx
.L57:
	movq	8(%rbp), %rsi
	leaq	1259(%rsp), %r13
	movl	$255, %edx
	movq	%r13, %rdi
	call	__strcpy_chk@PLT
	movq	16(%rbp), %rsi
	movl	$255, %edx
	leaq	1514(%rsp), %rdi
	call	__strcpy_chk@PLT
	leal	-32(%rbx), %eax
	cmpl	$992, %eax
	jbe	.L101
	movl	%ebx, %edx
	leaq	.LC12(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	jmp	.L103
.L59:
	leaq	1769(%rsp), %rbx
	leaq	.LC6(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	movq	%rbx, %rdx
	call	__printf_chk@PLT
	movq	%rbx, %rdx
	movl	$2, %edi
	xorl	%eax, %eax
	leaq	.LC7(%rip), %rsi
	call	__printf_chk@PLT
	movq	%rbx, %rdx
	movl	$2, %edi
	xorl	%eax, %eax
	leaq	.LC8(%rip), %rsi
	call	__printf_chk@PLT
	movq	%rbx, %rdx
	movl	$2, %edi
	xorl	%eax, %eax
	leaq	.LC9(%rip), %rsi
	call	__printf_chk@PLT
	movq	%rbx, %rdx
	movl	$2, %edi
	xorl	%eax, %eax
	leaq	.LC10(%rip), %rsi
	call	__printf_chk@PLT
	leaq	.LC11(%rip), %rsi
	jmp	.L104
.L101:
	movq	%r13, %rdi
	call	_Z10ReadBMPlinPc
	movq	%rax, TheImg(%rip)
	movq	%rax, %rbp
	testq	%rax, %rax
	jne	.L62
.L105:
	leaq	.LC13(%rip), %rsi
.L104:
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
.L103:
	movl	$1, %edi
	call	exit@PLT
.L62:
	movslq	4+ip(%rip), %rdi
	imulq	64+ip(%rip), %rdi
	call	malloc@PLT
	movq	%rax, CopyImg(%rip)
	testq	%rax, %rax
	jne	.L63
	movq	%rbp, %rdi
	call	free@PLT
	jmp	.L105
.L63:
	xorl	%ecx, %ecx
	leaq	60(%rsp), %rdi
	movl	%ecx, 60(%rsp)
	call	cudaGetDeviceCount@PLT
	cmpl	$0, 60(%rsp)
	leaq	.LC14(%rip), %rsi
	je	.L104
	xorl	%edi, %edi
	call	cudaSetDevice@PLT
	leaq	.LC15(%rip), %rdx
	testl	%eax, %eax
	jne	.L106
	leaq	120(%rsp), %rax
	xorl	%esi, %esi
	movq	%rax, %rdi
	movq	%rax, 16(%rsp)
	call	cudaGetDeviceProperties_v2@PLT
	movl	456(%rsp), %eax
	imull	460(%rsp), %eax
	movl	$75, %r9d
	imull	464(%rsp), %eax
	shrl	$10, %eax
	movl	%eax, %r8d
	cmpl	$5119, %eax
	jbe	.L66
	shrq	$10, %r8
	movl	$77, %r9d
.L66:
	leaq	1159(%rsp), %rax
	movl	$100, %edx
	movl	$2, %esi
	leaq	.LC16(%rip), %rcx
	movq	%rax, %rdi
	movq	%rax, 24(%rsp)
	xorl	%eax, %eax
	call	__sprintf_chk@PLT
	movl	440(%rsp), %eax
	leaq	64(%rsp), %rdi
	movq	%rax, 32(%rsp)
	call	cudaEventCreate@PLT
	leaq	72(%rsp), %rdi
	call	cudaEventCreate@PLT
	movl	4+ip(%rip), %edx
	movl	ip(%rip), %eax
	leaq	GPUptr(%rip), %rdi
	imull	%edx, %eax
	imull	64+ip(%rip), %edx
	leal	(%rax,%rax,2), %ecx
	imull	$24, %eax, %eax
	leal	16(%rdx,%rcx), %edx
	leal	(%rdx,%rax), %esi
	call	cudaMalloc@PLT
	leaq	.LC17(%rip), %rdx
	testl	%eax, %eax
	jne	.L106
	movslq	4+ip(%rip), %rdx
	movq	GPUptr(%rip), %rdi
	movq	TheImg(%rip), %rsi
	movq	%rdx, %rcx
	imulq	64+ip(%rip), %rdx
	movq	%rdi, GPUImg(%rip)
	imull	ip(%rip), %ecx
	leaq	(%rdi,%rdx), %rax
	movslq	%ecx, %rcx
	movq	%rax, GPUCopyImg(%rip)
	addq	%rcx, %rax
	movq	%rax, NoiseMap(%rip)
	addq	%rcx, %rax
	movq	%rax, KernelIndices(%rip)
	addq	%rcx, %rax
	salq	$3, %rcx
	movq	%rax, NoisyPixelCoords(%rip)
	addq	%rcx, %rax
	movq	%rax, GPU_PREV_BW(%rip)
	addq	%rcx, %rax
	movq	%rax, GPU_CURR_BW(%rip)
	addq	%rcx, %rax
	leaq	4(%rax), %rcx
	movq	%rax, GlobalMax(%rip)
	movq	%rcx, GlobalMin(%rip)
	leaq	8(%rax), %rcx
	addq	$12, %rax
	movq	%rcx, NumNoisyPixelsGPU(%rip)
	movl	$1, %ecx
	movq	%rax, GPU_SAD(%rip)
	call	cudaMemcpy@PLT
	leaq	.LC18(%rip), %rdx
	testl	%eax, %eax
	jne	.L106
	movl	$16, %edx
	leaq	104(%rsp), %rsi
	movl	$1, %ecx
	movq	GlobalMax(%rip), %rdi
	call	cudaMemcpy@PLT
	leaq	.LC19(%rip), %rdx
	testl	%eax, %eax
	jne	.L106
	movl	ip(%rip), %edx
	imull	4+ip(%rip), %edx
	movl	$1, %esi
	movq	NoiseMap(%rip), %rdi
	movslq	%edx, %rdx
	call	cudaMemset@PLT
	leaq	.LC20(%rip), %rdx
	testl	%eax, %eax
	jne	.L106
	movq	64(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movl	ip(%rip), %eax
	xorl	%edx, %edx
	xorl	%r9d, %r9d
	movl	4+ip(%rip), %ebp
	movl	%ebx, 92(%rsp)
	xorl	%r8d, %r8d
	leal	-1(%rbx,%rax), %eax
	divl	%ebx
	imull	%eax, %ebp
	movl	%eax, 40(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 96(%rsp)
	movl	100(%rsp), %ecx
	movq	%rax, 84(%rsp)
	movq	92(%rsp), %rdx
	movl	%ebp, 80(%rsp)
	movl	88(%rsp), %esi
	movq	80(%rsp), %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L71
	movl	ip(%rip), %ecx
	movq	GPU_CURR_BW(%rip), %rdx
	movq	GPUImg(%rip), %rsi
	movq	GPUCopyImg(%rip), %rdi
	call	_Z32__device_stub__Z8BWKernelPhS_PdjPhS_Pdj
.L71:
	call	cudaDeviceSynchronize@PLT
	leaq	.LC21(%rip), %rdx
	movl	%eax, %ecx
	testl	%eax, %eax
	jne	.L107
	movabsq	$4294967297, %rax
	movl	%ebx, 92(%rsp)
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	%rax, 96(%rsp)
	movl	100(%rsp), %ecx
	movq	%rax, 84(%rsp)
	movq	92(%rsp), %rdx
	movl	%ebp, 80(%rsp)
	movl	88(%rsp), %esi
	movq	80(%rsp), %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L73
	movl	4+ip(%rip), %eax
	movq	NoiseMap(%rip), %rdx
	movq	NumNoisyPixelsGPU(%rip), %r9
	movq	GlobalMin(%rip), %r8
	movq	GlobalMax(%rip), %rcx
	movq	GPUCopyImg(%rip), %rsi
	pushq	%rax
	.cfi_def_cfa_offset 2104
	movl	ip(%rip), %eax
	movq	NoisyPixelCoords(%rip), %rdi
	pushq	%rax
	.cfi_def_cfa_offset 2112
	call	_Z62__device_stub__Z15findNoisyPixelsP11pixelCoordsPhS1_PjS2_S2_jjP11pixelCoordsPhS1_PjS2_S2_jj
	popq	%rax
	.cfi_def_cfa_offset 2104
	popq	%rdx
	.cfi_def_cfa_offset 2096
.L73:
	call	cudaDeviceSynchronize@PLT
	leaq	.LC22(%rip), %rdx
	movl	%eax, %ecx
	testl	%eax, %eax
	jne	.L107
	movl	$4, %edx
	leaq	52(%rsp), %rdi
	movl	$2, %ecx
	movq	NumNoisyPixelsGPU(%rip), %rsi
	call	cudaMemcpy@PLT
	leaq	.LC23(%rip), %rdx
	testl	%eax, %eax
	jne	.L106
	movl	52(%rsp), %eax
	xorl	%edx, %edx
	movl	%ebx, 92(%rsp)
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	leal	-1(%rbx,%rax), %eax
	divl	%ebx
	movl	%eax, %r13d
	movabsq	$4294967297, %rax
	movq	%rax, 96(%rsp)
	movl	100(%rsp), %ecx
	movq	%rax, 84(%rsp)
	movq	92(%rsp), %rdx
	movl	%r13d, 80(%rsp)
	movl	88(%rsp), %esi
	movq	80(%rsp), %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L76
	movl	ip(%rip), %r9d
	movq	KernelIndices(%rip), %rcx
	pushq	%r14
	.cfi_def_cfa_offset 2104
	movq	NoiseMap(%rip), %rdx
	movq	GPUCopyImg(%rip), %rsi
	pushq	%r12
	.cfi_def_cfa_offset 2112
	movq	NoisyPixelCoords(%rip), %rdi
	movl	68(%rsp), %r8d
	call	_Z57__device_stub__Z14determineMasksP11pixelCoordsPhS1_S1_jjjP11pixelCoordsPhS1_S1_jjj
	popq	%r15
	.cfi_def_cfa_offset 2104
	popq	%rax
	.cfi_def_cfa_offset 2096
.L76:
	call	cudaDeviceSynchronize@PLT
	leaq	.LC24(%rip), %rdx
	movl	%eax, %ecx
	testl	%eax, %eax
	jne	.L107
	movabsq	$4294967297, %rax
	movl	%ebx, 92(%rsp)
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	%rax, 96(%rsp)
	movl	100(%rsp), %ecx
	movq	%rax, 84(%rsp)
	movq	92(%rsp), %rdx
	movl	%ebp, 80(%rsp)
	movl	88(%rsp), %esi
	movq	80(%rsp), %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L78
	movl	ip(%rip), %edx
	imull	4+ip(%rip), %edx
	movq	GPU_CURR_BW(%rip), %rsi
	movq	GPU_PREV_BW(%rip), %rdi
	call	_Z29__device_stub__Z7PixCopyPdS_jPdS_j
.L78:
	call	cudaDeviceSynchronize@PLT
	movl	$1, %r14d
	movabsq	$4294967297, %rbp
	leaq	.LC25(%rip), %rdx
	movl	%eax, %ecx
	testl	%eax, %eax
	jne	.L107
.L79:
	movq	GPU_SAD(%rip), %rdi
	xorl	%esi, %esi
	movl	$4, %edx
	call	cudaMemset@PLT
	testl	%eax, %eax
	je	.L80
	leaq	.LC26(%rip), %rdx
	jmp	.L106
.L80:
	movq	%rbp, 96(%rsp)
	movl	100(%rsp), %ecx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	%rbp, 84(%rsp)
	movl	88(%rsp), %esi
	movl	%ebx, 92(%rsp)
	movq	92(%rsp), %rdx
	movl	%r13d, 80(%rsp)
	movq	80(%rsp), %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L81
	movl	ip(%rip), %r9d
	movl	52(%rsp), %r8d
	movq	KernelIndices(%rip), %rcx
	movq	NoisyPixelCoords(%rip), %rdx
	movq	GPU_PREV_BW(%rip), %rsi
	movq	GPU_CURR_BW(%rip), %rdi
	call	_Z48__device_stub__Z9ConvolutePdS_P11pixelCoordsPhjjPdS_P11pixelCoordsPhjj
.L81:
	call	cudaDeviceSynchronize@PLT
	movl	%eax, %ecx
	testl	%eax, %eax
	je	.L82
	leaq	.LC27(%rip), %rdx
	jmp	.L107
.L82:
	movq	%rbp, 96(%rsp)
	movl	100(%rsp), %ecx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	%rbp, 84(%rsp)
	movl	88(%rsp), %esi
	movl	%ebx, 92(%rsp)
	movq	92(%rsp), %rdx
	movl	%r13d, 80(%rsp)
	movq	80(%rsp), %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L83
	movl	4+ip(%rip), %eax
	movq	NoisyPixelCoords(%rip), %rcx
	pushq	%r9
	.cfi_def_cfa_offset 2104
	movq	GPU_CURR_BW(%rip), %rdx
	movl	ip(%rip), %r9d
	movq	GPU_PREV_BW(%rip), %rsi
	movq	GPU_SAD(%rip), %rdi
	pushq	%rax
	.cfi_def_cfa_offset 2112
	movl	68(%rsp), %r8d
	call	_Z44__device_stub__Z3SADPjPdS0_P11pixelCoordsjjjPjPdS0_P11pixelCoordsjjj
	popq	%r10
	.cfi_def_cfa_offset 2104
	popq	%r11
	.cfi_def_cfa_offset 2096
.L83:
	call	cudaDeviceSynchronize@PLT
	movl	%eax, %ecx
	testl	%eax, %eax
	je	.L84
	leaq	.LC28(%rip), %rdx
	jmp	.L107
.L84:
	movq	%rbp, 96(%rsp)
	movl	100(%rsp), %ecx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	%rbp, 84(%rsp)
	movl	88(%rsp), %esi
	movl	%ebx, 92(%rsp)
	movq	92(%rsp), %rdx
	movl	%r13d, 80(%rsp)
	movq	80(%rsp), %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L85
	movl	ip(%rip), %r8d
	movl	52(%rsp), %ecx
	movq	NoisyPixelCoords(%rip), %rdx
	movq	GPU_CURR_BW(%rip), %rsi
	movq	GPU_PREV_BW(%rip), %rdi
	call	_Z50__device_stub__Z12NoisyPixCopyPdS_P11pixelCoordsjjPdS_P11pixelCoordsjj
.L85:
	call	cudaDeviceSynchronize@PLT
	movl	%eax, %ecx
	testl	%eax, %eax
	je	.L86
	leaq	.LC29(%rip), %rdx
.L107:
	movq	stderr(%rip), %rdi
	movl	$2, %esi
	xorl	%eax, %eax
	call	__fprintf_chk@PLT
	jmp	.L103
.L86:
	leaq	56(%rsp), %rdi
	movl	$2, %ecx
	movl	$4, %edx
	movq	GPU_SAD(%rip), %rsi
	call	cudaMemcpy@PLT
	testl	%eax, %eax
	je	.L87
	leaq	.LC30(%rip), %rdx
	jmp	.L106
.L87:
	movl	40(%rsp), %r15d
	movq	%rbp, 96(%rsp)
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	imull	4+ip(%rip), %r15d
	movl	100(%rsp), %ecx
	movq	%rbp, 84(%rsp)
	movl	%ebx, 92(%rsp)
	movl	88(%rsp), %esi
	movq	92(%rsp), %rdx
	movl	%r15d, 80(%rsp)
	movq	80(%rsp), %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L88
	movl	ip(%rip), %edx
	movq	GPU_CURR_BW(%rip), %rsi
	movq	GPUImg(%rip), %rdi
	call	_Z31__device_stub__Z9RGBKernelPhPdjPhPdj
.L88:
	movslq	4+ip(%rip), %rdx
	imulq	64+ip(%rip), %rdx
	movl	$2, %ecx
	movq	GPUImg(%rip), %rsi
	movq	CopyImg(%rip), %rdi
	movq	%rsi, GPUResult(%rip)
	call	cudaMemcpy@PLT
	testl	%eax, %eax
	je	.L89
	leaq	.LC31(%rip), %rdx
.L106:
	movq	stderr(%rip), %rdi
	movl	$2, %esi
	xorl	%eax, %eax
	call	__fprintf_chk@PLT
	jmp	.L103
.L89:
	leal	1(%r14), %eax
	movl	%r14d, %r9d
	leaq	.LC32(%rip), %r8
	movl	$255, %edx
	movl	%eax, 44(%rsp)
	leaq	1514(%rsp), %rax
	leaq	.LC33(%rip), %rcx
	movq	%rax, 8(%rsp)
	leaq	.LC34(%rip), %rax
	pushq	%rsi
	.cfi_def_cfa_offset 2104
	movl	$2, %esi
	pushq	%rax
	.cfi_def_cfa_offset 2112
	movq	24(%rsp), %rdi
	xorl	%eax, %eax
	call	__sprintf_chk@PLT
	popq	%rdi
	.cfi_def_cfa_offset 2104
	movq	CopyImg(%rip), %rdi
	popq	%r8
	.cfi_def_cfa_offset 2096
	movq	8(%rsp), %rsi
	call	_Z11WriteBMPlinPhPc
	movl	4(%rsp), %eax
	cmpl	56(%rsp), %eax
	jnb	.L109
	movl	44(%rsp), %r14d
	jmp	.L79
.L109:
	movq	72(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movq	64(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movq	72(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movq	72(%rsp), %rdx
	movq	64(%rsp), %rsi
	leaq	92(%rsp), %rdi
	call	cudaEventElapsedTime@PLT
	call	cudaDeviceSynchronize@PLT
	leaq	.LC35(%rip), %rdx
	testl	%eax, %eax
	jne	.L108
	leaq	.LC36(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	leaq	.LC37(%rip), %rsi
	movl	$2, %edi
	pushq	%rax
	.cfi_def_cfa_offset 2104
	xorl	%eax, %eax
	pushq	40(%rsp)
	.cfi_def_cfa_offset 2112
	movq	40(%rsp), %r9
	movl	500(%rsp), %r8d
	movl	496(%rsp), %ecx
	movq	32(%rsp), %rdx
	call	__printf_chk@PLT
	popq	%rdx
	.cfi_def_cfa_offset 2104
	leaq	.LC38(%rip), %rsi
	popq	%rcx
	.cfi_def_cfa_offset 2096
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movl	40(%rsp), %eax
	leaq	1259(%rsp), %rcx
	leaq	1769(%rsp), %rdx
	leaq	.LC39(%rip), %rsi
	movl	$2, %edi
	pushq	%rax
	.cfi_def_cfa_offset 2104
	xorl	%eax, %eax
	pushq	%r15
	.cfi_def_cfa_offset 2112
	pushq	%rbx
	.cfi_def_cfa_offset 2120
	pushq	%r12
	.cfi_def_cfa_offset 2128
	movl	36(%rsp), %r9d
	movq	40(%rsp), %r8
	call	__printf_chk@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 2096
	movl	$2, %edi
	movb	$1, %al
	leaq	.LC40(%rip), %rsi
	cvtss2sd	92(%rsp), %xmm0
	call	__printf_chk@PLT
	leaq	.LC41(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movq	GPUptr(%rip), %rdi
	call	cudaFree@PLT
	movq	64(%rsp), %rdi
	call	cudaEventDestroy@PLT
	movq	72(%rsp), %rdi
	call	cudaEventDestroy@PLT
	call	cudaDeviceReset@PLT
	testl	%eax, %eax
	je	.L91
	leaq	.LC42(%rip), %rdx
.L108:
	movq	stderr(%rip), %rdi
	movl	$2, %esi
	xorl	%eax, %eax
	call	__fprintf_chk@PLT
	movq	TheImg(%rip), %rdi
	call	free@PLT
	movq	CopyImg(%rip), %rdi
	call	free@PLT
	jmp	.L103
.L91:
	movq	TheImg(%rip), %rdi
	call	free@PLT
	movq	CopyImg(%rip), %rdi
	call	free@PLT
	movq	2024(%rsp), %rax
	subq	%fs:40, %rax
	je	.L92
	call	__stack_chk_fail@PLT
.L92:
	addq	$2040, %rsp
	.cfi_def_cfa_offset 56
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3851:
	.size	main, .-main
	.section	.rodata.str1.1
.LC43:
	.string	"_Z7PixCopyPdS_j"
.LC44:
	.string	"_Z12NoisyPixCopyPdS_P11pixelCoordsjj"
.LC45:
	.string	"_Z9RGBKernelPhPdj"
.LC46:
	.string	"_Z8BWKernelPhS_Pdj"
.LC47:
	.string	"_Z3SADPjPdS0_P11pixelCoordsjjj"
.LC48:
	.string	"_Z9ConvolutePdS_P11pixelCoordsPhjj"
.LC49:
	.string	"_Z14determineMasksP11pixelCoordsPhS1_S1_jjj"
.LC50:
	.string	"_Z15findNoisyPixelsP11pixelCoordsPhS1_PjS2_S2_jj"
.LC51:
	.string	"precalc_xorwow_matrix"
.LC52:
	.string	"precalc_xorwow_offset_matrix"
.LC53:
	.string	"mrg32k3aM1"
.LC54:
	.string	"mrg32k3aM2"
.LC55:
	.string	"mrg32k3aM1SubSeq"
.LC56:
	.string	"mrg32k3aM2SubSeq"
.LC57:
	.string	"mrg32k3aM1Seq"
.LC58:
	.string	"mrg32k3aM2Seq"
.LC59:
	.string	"__cr_lgamma_table"
.LC60:
	.string	"mask0"
.LC61:
	.string	"mask1"
.LC62:
	.string	"mask2"
.LC63:
	.string	"mask3"
.LC64:
	.string	"mask4"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3893:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC43(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z7PixCopyPdS_j(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC44(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z12NoisyPixCopyPdS_P11pixelCoordsjj(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC45(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z9RGBKernelPhPdj(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC46(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z8BWKernelPhS_Pdj(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC47(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z3SADPjPdS0_P11pixelCoordsjjj(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC48(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z9ConvolutePdS_P11pixelCoordsPhjj(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC49(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z14determineMasksP11pixelCoordsPhS1_S1_jjj(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC50(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z15findNoisyPixelsP11pixelCoordsPhS1_PjS2_S2_jj(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	leaq	.LC51(%rip), %rdx
	pushq	$0
	.cfi_def_cfa_offset 24
	movq	%rdx, %rcx
	movl	$102400, %r9d
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	_ZL21precalc_xorwow_matrix(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC52(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$102400, %r9d
	leaq	_ZL28precalc_xorwow_offset_matrix(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC53(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$2304, %r9d
	leaq	_ZL10mrg32k3aM1(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	popq	%r8
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC54(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$2304, %r9d
	leaq	_ZL10mrg32k3aM2(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r9
	.cfi_def_cfa_offset 24
	popq	%r10
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC55(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$2016, %r9d
	leaq	_ZL16mrg32k3aM1SubSeq(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r11
	.cfi_def_cfa_offset 24
	popq	%rax
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC56(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$2016, %r9d
	leaq	_ZL16mrg32k3aM2SubSeq(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC57(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$2304, %r9d
	leaq	_ZL13mrg32k3aM1Seq(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC58(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$2304, %r9d
	leaq	_ZL13mrg32k3aM2Seq(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	popq	%r8
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC59(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$72, %r9d
	leaq	_ZL17__cr_lgamma_table(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r9
	.cfi_def_cfa_offset 24
	popq	%r10
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC60(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$72, %r9d
	leaq	_ZL5mask0(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r11
	.cfi_def_cfa_offset 24
	popq	%rax
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC61(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$200, %r9d
	leaq	_ZL5mask1(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC62(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$200, %r9d
	leaq	_ZL5mask2(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC63(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$392, %r9d
	leaq	_ZL5mask3(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	popq	%r8
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC64(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movl	$392, %r9d
	movq	%rdx, %rcx
	leaq	_ZL5mask4(%rip), %rsi
	call	__cudaRegisterVar@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	popq	%r9
	.cfi_def_cfa_offset 24
	popq	%r10
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3893:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.local	_ZZ10ReadBMPlinPcE3Img
	.comm	_ZZ10ReadBMPlinPcE3Img,8,8
	.local	_ZL5mask4
	.comm	_ZL5mask4,392,32
	.local	_ZL5mask3
	.comm	_ZL5mask3,392,32
	.local	_ZL5mask2
	.comm	_ZL5mask2,200,32
	.local	_ZL5mask1
	.comm	_ZL5mask1,200,32
	.local	_ZL5mask0
	.comm	_ZL5mask0,72,32
	.globl	GPU_SAD
	.bss
	.align 8
	.type	GPU_SAD, @object
	.size	GPU_SAD, 8
GPU_SAD:
	.zero	8
	.globl	GPUmutexes
	.align 8
	.type	GPUmutexes, @object
	.size	GPUmutexes, 8
GPUmutexes:
	.zero	8
	.globl	NumNoisyPixelsGPU
	.align 8
	.type	NumNoisyPixelsGPU, @object
	.size	NumNoisyPixelsGPU, 8
NumNoisyPixelsGPU:
	.zero	8
	.globl	GlobalMin
	.align 8
	.type	GlobalMin, @object
	.size	GlobalMin, 8
GlobalMin:
	.zero	8
	.globl	GlobalMax
	.align 8
	.type	GlobalMax, @object
	.size	GlobalMax, 8
GlobalMax:
	.zero	8
	.globl	NoisyPixelCoords
	.align 8
	.type	NoisyPixelCoords, @object
	.size	NoisyPixelCoords, 8
NoisyPixelCoords:
	.zero	8
	.globl	GPU_CURR_BW
	.align 8
	.type	GPU_CURR_BW, @object
	.size	GPU_CURR_BW, 8
GPU_CURR_BW:
	.zero	8
	.globl	GPU_PREV_BW
	.align 8
	.type	GPU_PREV_BW, @object
	.size	GPU_PREV_BW, 8
GPU_PREV_BW:
	.zero	8
	.globl	KernelIndices
	.align 8
	.type	KernelIndices, @object
	.size	KernelIndices, 8
KernelIndices:
	.zero	8
	.globl	NoiseMap
	.align 8
	.type	NoiseMap, @object
	.size	NoiseMap, 8
NoiseMap:
	.zero	8
	.globl	GPUResult
	.align 8
	.type	GPUResult, @object
	.size	GPUResult, 8
GPUResult:
	.zero	8
	.globl	GPUptr
	.align 8
	.type	GPUptr, @object
	.size	GPUptr, 8
GPUptr:
	.zero	8
	.globl	GPUCopyImg
	.align 8
	.type	GPUCopyImg, @object
	.size	GPUCopyImg, 8
GPUCopyImg:
	.zero	8
	.globl	GPUImg
	.align 8
	.type	GPUImg, @object
	.size	GPUImg, 8
GPUImg:
	.zero	8
	.globl	CopyImg
	.align 8
	.type	CopyImg, @object
	.size	CopyImg, 8
CopyImg:
	.zero	8
	.globl	TheImg
	.align 8
	.type	TheImg, @object
	.size	TheImg, 8
TheImg:
	.zero	8
	.globl	ip
	.align 32
	.type	ip, @object
	.size	ip, 72
ip:
	.zero	72
	.local	_ZL17__cr_lgamma_table
	.comm	_ZL17__cr_lgamma_table,72,32
	.local	_ZL13mrg32k3aM2Seq
	.comm	_ZL13mrg32k3aM2Seq,2304,32
	.local	_ZL13mrg32k3aM1Seq
	.comm	_ZL13mrg32k3aM1Seq,2304,32
	.local	_ZL16mrg32k3aM2SubSeq
	.comm	_ZL16mrg32k3aM2SubSeq,2016,32
	.local	_ZL16mrg32k3aM1SubSeq
	.comm	_ZL16mrg32k3aM1SubSeq,2016,32
	.local	_ZL10mrg32k3aM2
	.comm	_ZL10mrg32k3aM2,2304,32
	.local	_ZL10mrg32k3aM1
	.comm	_ZL10mrg32k3aM1,2304,32
	.local	_ZL28precalc_xorwow_offset_matrix
	.comm	_ZL28precalc_xorwow_offset_matrix,102400,32
	.local	_ZL21precalc_xorwow_matrix
	.comm	_ZL21precalc_xorwow_matrix,102400,32
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <hip/hip_runtime.h>
#include <hiprand/hiprand_kernel.h>

#include <stdio.h>
#include <stdlib.h>
#include <stdint.h>
#include <string.h>
#include <iostream>
#include <math.h>
#include <ctype.h>

#include <time.h>

#define DATAMB(bytes)			(bytes/1024/1024)
#define DATABW(bytes,timems)	((float)bytes/(timems * 1.024*1024.0*1024.0))
#define	CEIL(a,b)				((a+b-1)/b)

typedef unsigned char uch;
typedef unsigned long ul;
typedef unsigned int  ui;

struct ImgProp{
	int Hpixels;
	int Vpixels;
	uch HeaderInfo[54];
	ul Hbytes;
} ip;


typedef struct{
	ui i;
	ui j;
}pixelCoords;

// buffers for images
uch *TheImg, *CopyImg;				
uch *GPUImg, *GPUCopyImg, *GPUptr, *GPUResult, *NoiseMap, *KernelIndices;
double *GPU_PREV_BW, *GPU_CURR_BW;

// noisy pixel locations
pixelCoords *NoisyPixelCoords;

// mutex variables for tracking noisy pixels
ui *GlobalMax, *GlobalMin, *NumNoisyPixelsGPU, *GPUmutexes, *GPU_SAD;


#define	IPHB		ip.Hbytes
#define	IPH			ip.Hpixels
#define	IPV			ip.Vpixels
#define	IMAGESIZE	(IPHB*IPV)
#define	IMAGEPIX	(IPH*IPV)



// Kernel that locates potentially noisy pixels in an image by using impulse noise detection
__global__
void findNoisyPixels(pixelCoords *locations, uch *ImgSrc, uch *noiseMap, ui*globalMax, ui*globalMin, ui*ListLength, ui Hpixels, ui Vpixels)
{

	// 3x3 matrix of pixels around current pixel
	//uch mat3x3[8]; // 3 x 3 - 1 = 8

	// threads/blocks info and IDs
	ui ThrPerBlk = blockDim.x;
	ui MYbid = blockIdx.x;
	ui MYtid = threadIdx.x;
	ui MYgtid = ThrPerBlk * MYbid + MYtid;

	//ui NumBlocks = gridDim.x;
	ui BlkPerRow = CEIL(Hpixels, ThrPerBlk);
	ui MYrow = MYbid / BlkPerRow;
	ui MYcol = MYgtid - MYrow*BlkPerRow*ThrPerBlk;

	// leave buffer frame around image to avoid 8 edge cases for convolutions
	if (MYcol > Hpixels-4 || MYcol < 3 || MYrow > Vpixels-4 || MYrow < 3) return;

	ui MYpixIndex = MYrow * Hpixels + MYcol; // pixel index in B&W image

	uch pIJ = ImgSrc[MYpixIndex];
	uch max = 0;
	uch min = 255;
	uch curr;
	uch nMax;
	uch nMin;
	uch oldMax;
	uch oldMin;
	int row;
	int col;
	int indx;
	
	// find min and max pixel intensities in current window
	for (int i = -1; i <= 1; i++){
		for (int j = -1; j <= 1; j++){

			if(!(j==0 && i==0)){

				row = MYrow + i;
				col = MYcol + j;
				indx = row*Hpixels + col;
				curr = ImgSrc[indx];

				if(curr > max)
					max = curr;
				if(curr < min)
					min = curr;
			}
		}
	}

	// atomically update global max and min pixel intensities
	oldMax = atomicMax(globalMax, (ui)max);
	oldMin = atomicMin(globalMin, (ui)min);

	// if the old max wasn't updated, then max is "salt" noise
	// otherwise, we must assume that 255 is "salt" noise
	if(oldMax == max)
		nMax = max;
	else
		nMax = 255;

	// if the old min wasn't updated, then min is "pepper" noise
	// otherwise, we must assume that 0 is "pepper" noise
	if(oldMin == min)
		nMin = min;
	else
		nMin = 0;
	
	// if the current pixel intensity is equal to min or max,
	// then it is likely s&p noise. Mark as such.
	if(pIJ == nMin || pIJ == nMax){

		int listIndex = atomicAdd(ListLength, (ui)1); 

		locations[listIndex].i = MYrow;
		locations[listIndex].j = MYcol;

		noiseMap[MYpixIndex] = 0;

	}

	// if(pIJ == 255 || pIJ == 0){

	// 	ui listIndex = atomicAdd(ListLength, (ui)1); 

	// 	locations[listIndex].i = MYrow;
	// 	locations[listIndex].j = MYcol;

	// 	noiseMap[MYpixIndex] = 0;

	// }
	
}


// __device__
// uch Horz[5][5] = {	{ 0, 0,  0,  0,  0 },
// 					{ 1, 1,  1,  1,  1 },
// 					{ 1, 1,  0,  1,  1 },
// 					{ 1, 1,  1,  1,  1 },
// 					{ 0, 0,  0,  0,  0 } };

// __device__
// uch Vert[5][5] = {	{ 0, 1,  1,  1,  0 },
// 					{ 0, 1,  1,  1,  0 },
// 					{ 0, 1,  0,  1,  0 },
// 					{ 0, 1,  1,  1,  0 },
// 					{ 0, 1,  1,  1,  0 } };

// __device__
// uch mask45[7][7]={	{0, 0, 0, 0, 1, 0, 0},
// 					{0, 0, 0, 1, 1, 1, 0},
// 					{0, 0, 1, 1, 1, 1, 1},
// 					{0, 1, 1, 0, 1, 1, 0},
// 					{1, 1, 1, 1, 1, 0, 0},
// 					{0, 1, 1, 1, 0, 0, 0},
// 					{0, 0, 1, 0, 0, 0, 0}};

// __device__
// uch mask135[7][7]={	{0, 0, 1, 0, 0, 0, 0},
//                   	{0, 1, 1, 1, 0, 0, 0},
//                   	{1, 1, 1, 1, 1, 0, 0},
//                   	{0, 1, 1, 0, 1, 1, 0},
//                   	{0, 0, 1, 1, 1, 1, 1},
//                   	{0, 0, 0, 1, 1, 1, 0},
//                   	{0, 0, 0, 0, 1, 0, 0}};


//3x3 standard mask
__constant__
double mask0[3][3] = {  {0.1036,	0.1464,	0.1036},
						{0.1464,	0,		0.1464},
						{0.1036,	0.1464,	0.1036}};

// horizontal 5x5 mask
__constant__
double mask1[5][5] = {  {0,			0,		0,			0,		0		},
						{0.0465,	0.0735,	0.1040,		0.0735,	0.0465	},
						{0.0520,	0.1040,	0,			0.1040,	0.0520	},
						{0.0465,	0.0735,	0.1040,		0.0735,	0.0465	},
						{0,			0,		0,			0,		0		}};

//vertical 5x5 mask						
__constant__
double mask2[5][5] = {  {0,	0.0465,	0.0520,	0.0465,	0},
						{0,	0.0735,	0.1040,	0.0735,	0},
						{0,	0.1040,	0,		0.1040,	0},
						{0,	0.0735,	0.1040,	0.0735,	0},
						{0,	0.0465,	0.0520,	0.0465,	0}};

//45 degree 7x7 mask					
__constant__
double mask3[7][7] = {	{0,			0,		0,		0,		0.0251,	0,		0		},
						{0,			0,		0,		0.0397,	0.0355,	0.0281,	0		},
						{0,			0,		0.0562,	0.0794,	0.0562,	0.0355,	0.0251	},
						{0,			0.0397,	0.0794,	0,		0.0794,	0.0397,	0		},
						{0.0251,	0.0355,	0.0562,	0.0794,	0.0562,	0,		0		},
						{0,			0.0281,	0.0355,	0.0397,	0,		0,		0		},
						{0,			0,		0.0251,	0,		0,		0,		0		}};
						
//135 degree 7x7 mask							
__constant__						
double mask4[7][7] = {  {0,			0,		0.0251,	0,		0,		0,		0		},
						{0,			0.0281,	0.0355,	0.0397,	0,		0,		0		},
						{0.0251,	0.0355,	0.0562,	0.0794,	0.0562,	0,		0		},
						{0,			0.0397,	0.0794,	0,		0.0794,	0.0397,	0		},
						{0,			0,		0.0562,	0.0794,	0.0562,	0.0355,	0.0251	},
						{0,			0,		0,		0.0397,	0.0355,	0.0281,	0		},
						{0,			0,		0,		0,		0.0251,	0,		0		}};


// Kernel that determines appropriate inpainting mask to use based on surrounding noiseless pixels
__global__
void determineMasks(pixelCoords *locations, uch *ImgSrc, uch *noiseMap, uch *kernelIndices, ui ListLength, ui Hpixels, ui R) {

	// threads/blocks info and IDs
	ui ThrPerBlk = blockDim.x;
	ui MYbid = blockIdx.x;
	ui MYtid = threadIdx.x;
	ui MYgtid = ThrPerBlk * MYbid + MYtid;

	// ensure not out-of-bounds
	if (MYgtid > ListLength) return;

	// masked arrays of those pixels denoted as noise-free
	uch noiseFreeLists[60];
	uch *maskA = noiseFreeLists;
	uch *maskB = maskA+14;
	uch *maskC = maskB+14;
	uch *maskD = maskC+14;
	uch *listLengths = maskD+14;
	uch *currMask;
	uch currListLength;

	// control and tracking variables
	int i, j, row, col, indx, maskAIndx=0, maskBIndx=0, maskCIndx=0, maskDIndx=0, chosenMask;
	float minStdDev=1000000.0, currStdDev, sum = 0.0, mean, standardDeviation = 0.0;

	// obtain current noisy pixel indices
	pixelCoords currCoord = locations[MYgtid];

	ui MYrow = currCoord.i;
	ui MYcol = currCoord.j;

	// iterate through both 5x5 masks to find values of noise-free pixels
	for (i = -2; i <= 2; i++){
		for (j = -2; j <= 2; j++){

			// find current absolute index
			row = MYrow + i;
			col = MYcol + j;
			indx = row*Hpixels + col;

			// if the current pixel is noise-free AND
			if(noiseMap[indx]){

				// if the current 5x5 horizontal mask cell is set to TRUE
				if(mask1[i+2][j+2]) {

					// obtain noise free pixel and add to list
					maskA[maskAIndx] = ImgSrc[indx];
					maskAIndx++;
				}

				// if the current 5x5 vertical mask cell is set to TRUE
				if(mask2[i+2][j+2]) {

					// obtain noise free pixel and add to list
					maskB[maskBIndx] = ImgSrc[indx];
					maskBIndx++;
				}

			}
		}
	}

	// iterate through both 7x7 masks to find values of noise-free pixels
	for (i = -3; i <= 3; i++){
		for ( j = -3; j <= 3; j++){

			// find current absolute index
			row = MYrow + i;
			col = MYcol + j;
			indx = row*Hpixels + col;

			// if the current pixel is noise-free AND
			if(noiseMap[indx]){

				// if the current 7x7 45 degree mask cell is set to TRUE
				if(mask3[i+3][j+3]) {
					// obtain noise free pixel and add to list
					maskC[maskCIndx] = ImgSrc[indx];
					maskCIndx++;
				}

				// if the current 7x7 135 degree mask cell is set to TRUE
				if(mask4[i+3][j+3]) {
					// obtain noise free pixel and add to list
					maskD[maskDIndx] = ImgSrc[indx];
					maskDIndx++;
				}

			}
		}
	}

	// if the amounts of noise free pixels in any of the directional masks is 
	// below threshold R, then we use 3x3 convolution
	// this helps to mitigate promoting false edges
	if(maskAIndx < R || maskBIndx < R || maskCIndx < R || maskDIndx < R)
		chosenMask = 0;

	else {

		// assign list lengths for smoother access
		listLengths[0] = maskAIndx;
		listLengths[1] = maskBIndx;
		listLengths[2] = maskCIndx;
		listLengths[3] = maskDIndx;

		// find the mask index (from 1 to 4) of minimum standard deviation
		for(i=0; i < 4; i++) {

			currListLength = listLengths[i];
			currMask = maskA+(i*14);
			
			// first find mean of array
			for(j = 0; j < currListLength; j++)
			{
				sum += (float)currMask[j];
			}
			mean = sum/currListLength;

			// then find sum of individual deviations
			for(j = 0; j < currListLength; j++)
				standardDeviation += pow((float)currMask[j] - mean, 2);

			// final StdDev is normalized by list length
			currStdDev = standardDeviation / currListLength;

			if(currStdDev < minStdDev) {
				chosenMask = i+1;
				minStdDev = currStdDev;
			}

		}

	}

	// assign the mask index that was chosen
	kernelIndices[MYgtid] = chosenMask;

}




// convolutions based on kernel indices
__global__
void Convolute(double *ImgCurr, double *ImgBW,  pixelCoords *pc,  uch *kernalI, ui numNoisy, ui Hpixels)
{
	ui ThrPerBlk = blockDim.x;
	ui MYbid = blockIdx.x;
	ui MYtid = threadIdx.x;
	ui MYgtid = ThrPerBlk * MYbid + MYtid;

	if (MYgtid >= numNoisy) return;			// index out of range

	// current noisy pixel coordinates
	ui i=pc[MYgtid].i,j=pc[MYgtid].j,m=kernalI[MYgtid];

	// absolute pixel index
	ui MYpixIndex = i * Hpixels + j;

	int a,b,row,col,index;
	double C = 0.0;

	switch(m)
	{
		case 0: for (a = -1; a <= 1; a++){
					for (b = -1; b <= 1; b++){
						row = i + a;
						col = j + b;
						index = row*Hpixels + col;
						C += (ImgBW[index] * mask0[a + 1][b + 1]);
					}
				}
				ImgCurr[MYpixIndex] = C;
				break;
		case 1: for (a = -2; a <= 2; a++){
					for (b = -2; b <= 2; b++){
						row = i + a;
						col = j + b;
						index = row*Hpixels + col;
						C += (ImgBW[index] * mask1[a + 2][b + 2]);
					}
				}
				ImgCurr[MYpixIndex] = C;
				break;
		case 2: for (a = -2; a <= 2; a++){
					for (b = -2; b <= 2; b++){
						row = i + a;
						col = j + b;
						index = row*Hpixels + col;
						C += (ImgBW[index] * mask2[a + 2][b + 2]);
					}
				}
				ImgCurr[MYpixIndex] = C;
				break;
		case 3: for (a = -3; a <= 3; a++){
					for (b = -3; b <= 3; b++){
						row = i + a;
						col = j + b;
						index = row*Hpixels + col;
						C += (ImgBW[index] * mask3[a + 3][b + 3]);
					}
				}
				ImgCurr[MYpixIndex] = C;
				break;
		default: for (a = -3; a <= 3; a++){
					for (b = -3; b <= 3; b++){
						row = i + a;
						col = j + b;
						index = row*Hpixels + col;
						C += (ImgBW[index] * mask4[a + 3][b + 3]);
					}
				}

				// assign convolution sum to current noisy pixel index
				ImgCurr[MYpixIndex] = C;
				break;
	}
		
}


// sum of absolute differences, reconstruction progress tracking mechanism
__global__
void SAD(ui *sad, double *prev, double *current, pixelCoords *pc, ui numNoisy, ui Hpixels, ui Vpixels)
{
	// thread IDs
	ui ThrPerBlk = blockDim.x;
	ui MYbid = blockIdx.x;
	ui MYtid = threadIdx.x;
	ui MYgtid = ThrPerBlk * MYbid + MYtid;
	
	if (MYgtid >= numNoisy) return;			// index out of range

	ui i=pc[MYgtid].i, j=pc[MYgtid].j; // current noisy pixel coordinates

	ui MYpixIndex = i * Hpixels + j; // absolute index
	
	// difference of old and updated pixel values, round to nearest integer
	int absDiff=(int)(prev[MYpixIndex]-current[MYpixIndex]+0.5);

	// absolute difference
	if(absDiff<0)
		absDiff = absDiff*(-1);
	
	atomicAdd(sad, (ui)absDiff); // update global sum

}


// Kernel that calculates a B&W image from an RGB image
// resulting image has a double type for each pixel position
__global__
void BWKernel(uch *ImgBW, uch *ImgGPU, double *ImgfpBW, ui Hpixels)
{
	ui ThrPerBlk = blockDim.x;
	ui MYbid = blockIdx.x;
	ui MYtid = threadIdx.x;
	ui MYgtid = ThrPerBlk * MYbid + MYtid;
	double R, G, B;

	//ui NumBlocks = gridDim.x;
	ui BlkPerRow = CEIL(Hpixels, ThrPerBlk);
	ui RowBytes = (Hpixels * 3 + 3) & (~3);
	ui MYrow = MYbid / BlkPerRow;
	ui MYcol = MYgtid - MYrow*BlkPerRow*ThrPerBlk;
	if (MYcol >= Hpixels) return;			// col out of range

	ui MYsrcIndex = MYrow * RowBytes + 3 * MYcol;
	ui MYpixIndex = MYrow * Hpixels + MYcol;

	B = (double)ImgGPU[MYsrcIndex];
	G = (double)ImgGPU[MYsrcIndex + 1];
	R = (double)ImgGPU[MYsrcIndex + 2];
	ImgBW[MYpixIndex] = (uch)((R+G+B)/3.0);
	ImgfpBW[MYpixIndex] = (R+G+B)/3.0;
}


// Kernel that calculates a RGB (grayscale) version of B&W image for filing as Windows BMP
__global__
void RGBKernel(uch *ImgRGB, double *ImgBW, ui Hpixels)
{
	ui ThrPerBlk = blockDim.x;
	ui MYbid = blockIdx.x;
	ui MYtid = threadIdx.x;
	ui MYgtid = ThrPerBlk * MYbid + MYtid;

	//ui NumBlocks = gridDim.x;
	ui BlkPerRow = CEIL(Hpixels, ThrPerBlk);
	ui RowBytes = (Hpixels * 3 + 3) & (~3);
	ui MYrow = MYbid / BlkPerRow;
	ui MYcol = MYgtid - MYrow*BlkPerRow*ThrPerBlk;
	if (MYcol >= Hpixels) return;			// col out of range

	ui MYdstIndex = MYrow * RowBytes + 3 * MYcol;
	ui MYpixIndex = MYrow * Hpixels + MYcol;

	uch pixInt = ImgBW[MYpixIndex];

	ImgRGB[MYdstIndex] = pixInt;
	ImgRGB[MYdstIndex+1] = pixInt;
	ImgRGB[MYdstIndex+2] = pixInt;
}


// Kernel that copies an image from one part of the
// GPU memory (ImgSrc) to another (ImgDst)
__global__
void NoisyPixCopy(double *NPDst, double *ImgSrc, pixelCoords *pc, ui NoisyPixelListLength, ui Hpixels)
{
	ui ThrPerBlk = blockDim.x;
	ui MYbid = blockIdx.x;
	ui MYtid = threadIdx.x;
	ui MYgtid = ThrPerBlk * MYbid + MYtid;

	if (MYgtid >= NoisyPixelListLength) return;// outside the allocated memory

	pixelCoords currCoord = pc[MYgtid];

	ui srcIndex = currCoord.i * Hpixels + currCoord.j;

	NPDst[srcIndex] = ImgSrc[srcIndex];
}


// Kernel that copies an image from one part of the
// GPU memory (ImgSrc) to another (ImgDst)
__global__
void PixCopy(double *ImgDst, double *ImgSrc, ui FS)
{
	ui ThrPerBlk = blockDim.x;
	ui MYbid = blockIdx.x;
	ui MYtid = threadIdx.x;
	ui MYgtid = ThrPerBlk * MYbid + MYtid;

	if (MYgtid > FS) return;				// outside the allocated memory
	ImgDst[MYgtid] = ImgSrc[MYgtid];
}


/*
// helper function that wraps CUDA API calls, reports any error and exits
void chkCUDAErr(cudaError_t error_id)
{
	if (error_id != CUDA_SUCCESS)
	{
		printf("CUDA ERROR :::%\n", cudaGetErrorString(error_id));
		exit(EXIT_FAILURE);
	}
}
*/


// Read a 24-bit/pixel BMP file into a 1D linear array.
// Allocate memory to store the 1D image and return its pointer.
uch *ReadBMPlin(char* fn)
{
	static uch *Img;
	FILE* f = fopen(fn, "rb");
	if (f == NULL){	printf("\n\n%s NOT FOUND\n\n", fn);	exit(EXIT_FAILURE); }

	uch HeaderInfo[54];
	fread(HeaderInfo, sizeof(uch), 54, f); // read the 54-byte header
	// extract image height and width from header
	int width = *(int*)&HeaderInfo[18];			ip.Hpixels = width;
	int height = *(int*)&HeaderInfo[22];		ip.Vpixels = height;
	int RowBytes = (width * 3 + 3) & (~3);		ip.Hbytes = RowBytes;
	//save header for re-use
	memcpy(ip.HeaderInfo, HeaderInfo,54);
	printf("\n Input File name: %17s  (%u x %u)   File Size=%u", fn, 
			ip.Hpixels, ip.Vpixels, IMAGESIZE);
	// allocate memory to store the main image (1 Dimensional array)
	Img  = (uch *)malloc(IMAGESIZE);
	if (Img == NULL) return Img;      // Cannot allocate memory
	// read the image from disk
	fread(Img, sizeof(uch), IMAGESIZE, f);
	fclose(f);
	return Img;
}


// Write the 1D linear-memory stored image into file.
void WriteBMPlin(uch *Img, char* fn)
{
	FILE* f = fopen(fn, "wb");
	if (f == NULL){ printf("\n\nFILE CREATION ERROR: %s\n\n", fn); exit(1); }
	//write header
	fwrite(ip.HeaderInfo, sizeof(uch), 54, f);
	//write data
	fwrite(Img, sizeof(uch), IMAGESIZE, f);
	printf("\nOutput File name: %17s  (%u x %u)   File Size=%u", fn, ip.Hpixels, ip.Vpixels, IMAGESIZE);
	fclose(f);
}


int main(int argc, char **argv)
{

	float /*totalTime, tfrCPUtoGPU, tfrGPUtoCPU,*/ kernelExecutionTime; // GPU code run times
	hipError_t cudaStatus;
	hipEvent_t time1, time2;//, time3, time4;
	char InputFileName[255], OutputFileName[255], ProgName[255];
	ui BlkPerRow, ThrPerBlk=256, NumBlocks, /* GPUDataTransfer,*/ NumBlocksNP;
	hipDeviceProp_t GPUprop;
	ul SupportedKBlocks, SupportedMBlocks, MaxThrPerBlk;		char SupportedBlocks[100]; 

	ui GPUtotalBufferSize, R = 5, T = 5, NumNoisyPixelsCPU, mutexInit[4] = {0, 255, 0, 0};
	ui CPU_SAD;

	strcpy(ProgName, "randNoiseRemoval");
	switch (argc){
	case 6:  ThrPerBlk = atoi(argv[5]);
	case 5:  R = atoi(argv[4]);
	case 4:  T = atoi(argv[3]);
	case 3:  strcpy(InputFileName, argv[1]);
			 strcpy(OutputFileName, argv[2]);
			 break;
	default: printf("\n\nUsage:   %s InputFilename OutputFilename [T] [R] [ThrPerBlk]", ProgName);
			 printf("\n\nExample: %s Astronaut.bmp Output.bmp", ProgName);
			 printf("\n\nExample: %s Astronaut.bmp Output.bmp 5", ProgName);
			 printf("\n\nExample: %s Astronaut.bmp Output.bmp 5 5",ProgName);
			 printf("\n\nExample: %s Astronaut.bmp Output.bmp 5 5 128",ProgName);
			 printf("\n\nT = reconstruction threshold, R = mask selection threshold\n\n");
			 exit(EXIT_FAILURE);
	}

	if ((ThrPerBlk < 32) || (ThrPerBlk > 1024)) {
		printf("Invalid ThrPerBlk option '%u'. Must be between 32 and 1024. \n", ThrPerBlk);
		exit(EXIT_FAILURE);
	}
	

	// Create CPU memory to store the input and output images
	TheImg = ReadBMPlin(InputFileName); // Read the input image if memory can be allocated
	if (TheImg == NULL){
		printf("Cannot allocate memory for the input image...\n");
		exit(EXIT_FAILURE);
	}
	CopyImg = (uch *)malloc(IMAGESIZE);
	if (CopyImg == NULL){
		free(TheImg);
		printf("Cannot allocate memory for the input image...\n");
		exit(EXIT_FAILURE);
	}


	// Choose which GPU to run on, change this on a multi-GPU system.
	int NumGPUs = 0;
	hipGetDeviceCount(&NumGPUs);
	if (NumGPUs == 0){
		printf("\nNo CUDA Device is available\n");
		exit(EXIT_FAILURE);
	}
	cudaStatus = hipSetDevice(0);
	if (cudaStatus != hipSuccess) {
		fprintf(stderr, "hipSetDevice failed!  Do you have a CUDA-capable GPU installed?");
		exit(EXIT_FAILURE);
	}

	
	hipGetDeviceProperties(&GPUprop, 0);
	SupportedKBlocks = (ui)GPUprop.maxGridSize[0] * (ui)GPUprop.maxGridSize[1] * (ui)GPUprop.maxGridSize[2] / 1024;
	SupportedMBlocks = SupportedKBlocks / 1024;
	sprintf(SupportedBlocks, "%u %c", (SupportedMBlocks >= 5) ? SupportedMBlocks : SupportedKBlocks, (SupportedMBlocks >= 5) ? 'M' : 'K');
	MaxThrPerBlk = (ui)GPUprop.maxThreadsPerBlock;

	hipEventCreate(&time1);
	hipEventCreate(&time2);
	// cudaEventCreate(&time3);
	// cudaEventCreate(&time4);

	

/*
	>>> GPU STORAGE DETAILS >>>
	GPUImage: IMAGESIZE
	GPUCopyImage(BW) : IMAGEPIX
	NoisyPixelCoords: IMAGEPIX*sizeof(pixelCoords)
	NoiseMap : IMAGEPIX
	KernelIndices : IMAGEPIX
	GlobalMax : sizeof(ui)
	GlobalMin : sizeof(ui)
	NumNoisyPixelsGPU : sizeof(ui)
	GPU_PREV_BW : sizeof(double) * IMAGEPIX
	GPU_CURR_BW : sizeof(double) * IMAGEPIX  
	GPU_SAD : sizeof(ui)
	 ***********************

*/
	// allocate sufficient memory on the GPU to hold all above items
	GPUtotalBufferSize = IMAGESIZE+(IMAGEPIX*sizeof(pixelCoords))+IMAGEPIX*3+sizeof(ui)*4+2*(sizeof(double)*IMAGEPIX);
	cudaStatus = hipMalloc((void**)&GPUptr, GPUtotalBufferSize);
	if (cudaStatus != hipSuccess) {
		fprintf(stderr, "hipMalloc failed! Can't allocate GPU memory for buffers");
		exit(EXIT_FAILURE);
	}

	// setup buffer pointers for functions
	GPUImg			= (uch *)GPUptr;
	GPUCopyImg	= GPUImg + IMAGESIZE;
	NoiseMap = GPUCopyImg + IMAGEPIX;  // add the previous image/array of noisy pixel intensities
	KernelIndices = NoiseMap + IMAGEPIX;
	NoisyPixelCoords = (pixelCoords*)(KernelIndices + IMAGEPIX);
	GPU_PREV_BW = (double*)(NoisyPixelCoords+IMAGEPIX);
	GPU_CURR_BW = GPU_PREV_BW + IMAGEPIX;
	GlobalMax = (ui*)(GPU_CURR_BW + IMAGEPIX);
	GlobalMin = GlobalMax+1;
	NumNoisyPixelsGPU = GlobalMin+1;
	GPU_SAD = NumNoisyPixelsGPU+1;


	// Copy input vectors from host memory to GPU buffers.
	cudaStatus = hipMemcpy(GPUImg, TheImg, IMAGESIZE, hipMemcpyHostToDevice);
	if (cudaStatus != hipSuccess) {
		fprintf(stderr, "hipMemcpy for input image CPU to GPU  failed!");
		exit(EXIT_FAILURE);
	}

	// Copy mutex initializations from CPU to GPU
	cudaStatus = hipMemcpy(GlobalMax, mutexInit, 4*sizeof(ui), hipMemcpyHostToDevice);
	if (cudaStatus != hipSuccess) {
		fprintf(stderr, "hipMemcpy for mutex initializations CPU to GPU  failed!");
		exit(EXIT_FAILURE);
	}

	// assume pixels are not noisy by default
	cudaStatus = hipMemset (NoiseMap, 1, IMAGEPIX );
	if (cudaStatus != hipSuccess) {
		fprintf(stderr, "hipMemset for Noise Map failed!");
		exit(EXIT_FAILURE);
	}

	hipEventRecord(time1, 0);		// Time stamp at the start of the GPU transfer

	
	BlkPerRow = CEIL(ip.Hpixels, ThrPerBlk);
	NumBlocks = IPV*BlkPerRow;
	

	BWKernel <<< NumBlocks, ThrPerBlk >>> (GPUCopyImg, GPUImg, GPU_CURR_BW, IPH);
	cudaStatus = hipDeviceSynchronize();
	if (cudaStatus != hipSuccess) {
		fprintf(stderr, "\n\n hipDeviceSynchronize for B&WKernel returned error code %d after launching the kernel!\n", cudaStatus);
		exit(EXIT_FAILURE);
	}


	findNoisyPixels <<< NumBlocks, ThrPerBlk >>> (NoisyPixelCoords, GPUCopyImg, NoiseMap, GlobalMax, GlobalMin, NumNoisyPixelsGPU, IPH, IPV);
	
	// cudaDeviceSynchronize waits for the kernel to finish, and returns
	// any errors encountered during the launch.
	cudaStatus = hipDeviceSynchronize();
	if (cudaStatus != hipSuccess) {
		fprintf(stderr, "\n\nhipDeviceSynchronize for findNoisyPixels returned error code %d after launching the kernel!\n", cudaStatus);
		exit(EXIT_FAILURE);
	}

	//cudaEventRecord(time3, 0);

	cudaStatus = hipMemcpy(&NumNoisyPixelsCPU, NumNoisyPixelsGPU, sizeof(ui), hipMemcpyDeviceToHost);
	if (cudaStatus != hipSuccess) {
		fprintf(stderr, "hipMemcpy of NumNoisyPixels, GPU to CPU  failed!");
		exit(EXIT_FAILURE);
	}


	// only schedule as many threads are needed for NoisyPixelListLength
	NumBlocksNP = CEIL(NumNoisyPixelsCPU, ThrPerBlk);
	
	determineMasks <<< NumBlocksNP, ThrPerBlk >>> (NoisyPixelCoords, GPUCopyImg, NoiseMap, KernelIndices, NumNoisyPixelsCPU, IPH, R);

	cudaStatus = hipDeviceSynchronize();
	if (cudaStatus != hipSuccess) {
		fprintf(stderr, "\n\nhipDeviceSynchronize for determineMasks returned error code %d after launching the kernel!\n", cudaStatus);
		exit(EXIT_FAILURE);
	}

	PixCopy <<< NumBlocks, ThrPerBlk >>> (GPU_PREV_BW, GPU_CURR_BW, IMAGEPIX);
	cudaStatus = hipDeviceSynchronize();
	if (cudaStatus != hipSuccess) {
		fprintf(stderr, "\n\nhipDeviceSynchronize for PixCopy returned error code %d after launching the kernel!\n", cudaStatus);
		exit(EXIT_FAILURE);
	}

int t=1;
	// progress tracking 
	do{

		// reset SAD (sum of absolute pixel differences)
		cudaStatus = hipMemset (GPU_SAD, 0, sizeof(ui) );
		if (cudaStatus != hipSuccess) {
			fprintf(stderr, "hipMemset for GPU_SAD failed!");
			exit(EXIT_FAILURE);
		}
		
		Convolute <<< NumBlocksNP, ThrPerBlk >>> (GPU_CURR_BW, GPU_PREV_BW,  NoisyPixelCoords,  KernelIndices, NumNoisyPixelsCPU, IPH);

		cudaStatus = hipDeviceSynchronize();
		if (cudaStatus != hipSuccess) {
			fprintf(stderr, "\n\n hipDeviceSynchronize for Convolute returned error code %d after launching the kernel!\n", cudaStatus);
			exit(EXIT_FAILURE);
		}

		SAD <<< NumBlocksNP, ThrPerBlk >>> (GPU_SAD, GPU_PREV_BW, GPU_CURR_BW, NoisyPixelCoords, NumNoisyPixelsCPU, IPH, IPV);

		cudaStatus = hipDeviceSynchronize();
		if (cudaStatus != hipSuccess) {
			fprintf(stderr, "\n\n hipDeviceSynchronize for SAD returned error code %d after launching the kernel!\n", cudaStatus);
			exit(EXIT_FAILURE);
		}

		NoisyPixCopy <<< NumBlocksNP, ThrPerBlk >>> (GPU_PREV_BW, GPU_CURR_BW, NoisyPixelCoords, NumNoisyPixelsCPU, IPH);

		cudaStatus = hipDeviceSynchronize();
		if (cudaStatus != hipSuccess) {
			fprintf(stderr, "\n\n hipDeviceSynchronize for NoisyPixCopy returned error code %d after launching the kernel!\n", cudaStatus);
			exit(EXIT_FAILURE);
		}

		// CudaMemcpy the SAD from GPU to CPU 
		cudaStatus = hipMemcpy(&CPU_SAD, GPU_SAD, sizeof(ui), hipMemcpyDeviceToHost);
		if (cudaStatus != hipSuccess) {
			fprintf(stderr, "hipMemcpy of SAD from GPU to CPU  failed!");
			exit(EXIT_FAILURE);
		}

        
    
    // must convert floating point B&W back to unsigned char format
	NumBlocks = IPV*BlkPerRow;
	RGBKernel <<< NumBlocks, ThrPerBlk >>> (GPUImg, GPU_CURR_BW, IPH);
    GPUResult = GPUImg;
    
    //Copy output (results) from GPU buffer to host (CPU) memory.
	cudaStatus = hipMemcpy(CopyImg, GPUResult, IMAGESIZE, hipMemcpyDeviceToHost);
	if (cudaStatus != hipSuccess) {
		fprintf(stderr, "hipMemcpy GPU to CPU  failed!");
		exit(EXIT_FAILURE);
    }
        
        sprintf(OutputFileName, "%s%d%s", "stages/stage", t++, ".bmp");
        WriteBMPlin(CopyImg, OutputFileName);		// Write the flipped image back to disk

	} while(CPU_SAD > T);


	

	hipEventRecord(time2, 0);		// Time stamp after the CPU --> GPU tfr is done

	//GPUDataTransfer = GPUtotalBufferSize;

	

	//cudaEventRecord(time4, 0);

	hipEventSynchronize(time1);
	hipEventSynchronize(time2);
	//cudaEventSynchronize(time3);
	//cudaEventSynchronize(time4);

	//cudaEventElapsedTime(&totalTime, time1, time4);
	//cudaEventElapsedTime(&tfrCPUtoGPU, time1, time2);
	hipEventElapsedTime(&kernelExecutionTime, time1, time2);
	//cudaEventElapsedTime(&tfrGPUtoCPU, time3, time4);

	cudaStatus = hipDeviceSynchronize();
	//checkError(cudaGetLastError());	// screen for errors in kernel launches
	if (cudaStatus != hipSuccess) {
		fprintf(stderr, "\n Program failed after cudaDeviceSynchronize()!");
		free(TheImg);
		free(CopyImg);
		exit(EXIT_FAILURE);
	}
	
	printf("\n\n--------------------------------------------------------------------------\n");
	printf("%s    ComputeCapab=%d.%d  [max %s blocks; %d thr/blk] \n", 
			GPUprop.name, GPUprop.major, GPUprop.minor, SupportedBlocks, MaxThrPerBlk);
	printf("--------------------------------------------------------------------------\n");
	printf("%s %s %s %d %d %u   [%u BLOCKS, %u BLOCKS/ROW]\n", ProgName, InputFileName, OutputFileName,
			T, R, ThrPerBlk, NumBlocks, BlkPerRow);
	// printf("--------------------------------------------------------------------------\n");
	// printf("CPU->GPU Transfer   =%7.2f ms  ...  %4d MB  ...  %6.2f GB/s\n", tfrCPUtoGPU, DATAMB(IMAGESIZE), DATABW(IMAGESIZE, tfrCPUtoGPU));
	printf("Kernel Execution    =%7.2f ms\n", kernelExecutionTime);//, DATAMB(GPUDataTransfer), DATABW(GPUDataTransfer, kernelExecutionTime));  ...  %4d MB  ...  %6.2f GB/s
	// printf("GPU->CPU Transfer   =%7.2f ms  ...  %4d MB  ...  %6.2f GB/s\n", tfrGPUtoCPU, DATAMB(IMAGESIZE), DATABW(IMAGESIZE, tfrGPUtoCPU));
	// printf("--------------------------------------------------------------------------\n");
	// printf("Total time elapsed  =%7.2f ms       %4d MB  ...  %6.2f GB/s\n", totalTime, DATAMB((2 * IMAGESIZE + GPUDataTransfer)), DATABW((2 * IMAGESIZE + GPUDataTransfer), totalTime));
	printf("--------------------------------------------------------------------------\n\n");

	// Deallocate CPU, GPU memory and destroy events.
	hipFree(GPUptr);
	hipEventDestroy(time1);
	hipEventDestroy(time2);
	// cudaEventDestroy(time3);
	// cudaEventDestroy(time4);
	// cudaDeviceReset must be called before exiting in order for profiling and
	// tracing tools such as Parallel Nsight and Visual Profiler to show complete traces.
	cudaStatus = hipDeviceReset();
	if (cudaStatus != hipSuccess) {
		fprintf(stderr, "hipDeviceReset failed!");
		free(TheImg);
		free(CopyImg);
		exit(EXIT_FAILURE);
	}

	free(TheImg);
	free(CopyImg);
	return(EXIT_SUCCESS);
}




	.text
	.file	"randNoiseRemovergif.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z30__device_stub__findNoisyPixelsP11pixelCoordsPhS1_PjS2_S2_jj # -- Begin function _Z30__device_stub__findNoisyPixelsP11pixelCoordsPhS1_PjS2_S2_jj
	.type	_Z30__device_stub__findNoisyPixelsP11pixelCoordsPhS1_PjS2_S2_jj,@function
_Z30__device_stub__findNoisyPixelsP11pixelCoordsPhS1_PjS2_S2_jj: # @_Z30__device_stub__findNoisyPixelsP11pixelCoordsPhS1_PjS2_S2_jj
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	216(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z15findNoisyPixelsP11pixelCoordsPhS1_PjS2_S2_jj, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z30__device_stub__findNoisyPixelsP11pixelCoordsPhS1_PjS2_S2_jj, .Lfunc_end0-_Z30__device_stub__findNoisyPixelsP11pixelCoordsPhS1_PjS2_S2_jj
	.cfi_endproc
                                        # -- End function
	.globl	_Z29__device_stub__determineMasksP11pixelCoordsPhS1_S1_jjj # -- Begin function _Z29__device_stub__determineMasksP11pixelCoordsPhS1_S1_jjj
	.type	_Z29__device_stub__determineMasksP11pixelCoordsPhS1_S1_jjj,@function
_Z29__device_stub__determineMasksP11pixelCoordsPhS1_S1_jjj: # @_Z29__device_stub__determineMasksP11pixelCoordsPhS1_S1_jjj
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	12(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	8(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z14determineMasksP11pixelCoordsPhS1_S1_jjj, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z29__device_stub__determineMasksP11pixelCoordsPhS1_S1_jjj, .Lfunc_end1-_Z29__device_stub__determineMasksP11pixelCoordsPhS1_S1_jjj
	.cfi_endproc
                                        # -- End function
	.globl	_Z24__device_stub__ConvolutePdS_P11pixelCoordsPhjj # -- Begin function _Z24__device_stub__ConvolutePdS_P11pixelCoordsPhjj
	.type	_Z24__device_stub__ConvolutePdS_P11pixelCoordsPhjj,@function
_Z24__device_stub__ConvolutePdS_P11pixelCoordsPhjj: # @_Z24__device_stub__ConvolutePdS_P11pixelCoordsPhjj
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	12(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	8(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z9ConvolutePdS_P11pixelCoordsPhjj, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z24__device_stub__ConvolutePdS_P11pixelCoordsPhjj, .Lfunc_end2-_Z24__device_stub__ConvolutePdS_P11pixelCoordsPhjj
	.cfi_endproc
                                        # -- End function
	.globl	_Z18__device_stub__SADPjPdS0_P11pixelCoordsjjj # -- Begin function _Z18__device_stub__SADPjPdS0_P11pixelCoordsjjj
	.type	_Z18__device_stub__SADPjPdS0_P11pixelCoordsjjj,@function
_Z18__device_stub__SADPjPdS0_P11pixelCoordsjjj: # @_Z18__device_stub__SADPjPdS0_P11pixelCoordsjjj
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	12(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	8(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z3SADPjPdS0_P11pixelCoordsjjj, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	_Z18__device_stub__SADPjPdS0_P11pixelCoordsjjj, .Lfunc_end3-_Z18__device_stub__SADPjPdS0_P11pixelCoordsjjj
	.cfi_endproc
                                        # -- End function
	.globl	_Z23__device_stub__BWKernelPhS_Pdj # -- Begin function _Z23__device_stub__BWKernelPhS_Pdj
	.type	_Z23__device_stub__BWKernelPhS_Pdj,@function
_Z23__device_stub__BWKernelPhS_Pdj:     # @_Z23__device_stub__BWKernelPhS_Pdj
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	4(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z8BWKernelPhS_Pdj, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end4:
	.size	_Z23__device_stub__BWKernelPhS_Pdj, .Lfunc_end4-_Z23__device_stub__BWKernelPhS_Pdj
	.cfi_endproc
                                        # -- End function
	.globl	_Z24__device_stub__RGBKernelPhPdj # -- Begin function _Z24__device_stub__RGBKernelPhPdj
	.type	_Z24__device_stub__RGBKernelPhPdj,@function
_Z24__device_stub__RGBKernelPhPdj:      # @_Z24__device_stub__RGBKernelPhPdj
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z9RGBKernelPhPdj, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end5:
	.size	_Z24__device_stub__RGBKernelPhPdj, .Lfunc_end5-_Z24__device_stub__RGBKernelPhPdj
	.cfi_endproc
                                        # -- End function
	.globl	_Z27__device_stub__NoisyPixCopyPdS_P11pixelCoordsjj # -- Begin function _Z27__device_stub__NoisyPixCopyPdS_P11pixelCoordsjj
	.type	_Z27__device_stub__NoisyPixCopyPdS_P11pixelCoordsjj,@function
_Z27__device_stub__NoisyPixCopyPdS_P11pixelCoordsjj: # @_Z27__device_stub__NoisyPixCopyPdS_P11pixelCoordsjj
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	4(%rsp), %rdx
	movl	%ecx, (%rdx)
	movq	%rsp, %rcx
	movl	%r8d, (%rcx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z12NoisyPixCopyPdS_P11pixelCoordsjj, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end6:
	.size	_Z27__device_stub__NoisyPixCopyPdS_P11pixelCoordsjj, .Lfunc_end6-_Z27__device_stub__NoisyPixCopyPdS_P11pixelCoordsjj
	.cfi_endproc
                                        # -- End function
	.globl	_Z22__device_stub__PixCopyPdS_j # -- Begin function _Z22__device_stub__PixCopyPdS_j
	.type	_Z22__device_stub__PixCopyPdS_j,@function
_Z22__device_stub__PixCopyPdS_j:        # @_Z22__device_stub__PixCopyPdS_j
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7PixCopyPdS_j, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end7:
	.size	_Z22__device_stub__PixCopyPdS_j, .Lfunc_end7-_Z22__device_stub__PixCopyPdS_j
	.cfi_endproc
                                        # -- End function
	.globl	_Z10ReadBMPlinPc                # -- Begin function _Z10ReadBMPlinPc
	.type	_Z10ReadBMPlinPc,@function
_Z10ReadBMPlinPc:                       # @_Z10ReadBMPlinPc
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	subq	$64, %rsp
	.cfi_def_cfa_offset 96
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movq	%rdi, %r14
	movl	$.L.str, %esi
	callq	fopen
	testq	%rax, %rax
	je	.LBB8_4
# %bb.1:
	movq	%rax, %rbx
	movq	%rsp, %r15
	movl	$1, %esi
	movl	$54, %edx
	movq	%r15, %rdi
	movq	%rax, %rcx
	callq	fread
	movslq	18(%r15), %rdx
	movl	%edx, ip(%rip)
	movslq	22(%r15), %rcx
	movl	%ecx, ip+4(%rip)
	leaq	(%rdx,%rdx,2), %r8
	addq	$3, %r8
	andq	$-4, %r8
	movq	%r8, ip+64(%rip)
	movaps	(%r15), %xmm0
	movaps	16(%r15), %xmm1
	movaps	32(%r15), %xmm2
	movups	%xmm0, ip+8(%rip)
	movups	%xmm1, ip+24(%rip)
	movups	%xmm2, ip+40(%rip)
	movq	46(%r15), %rax
	movq	%rax, ip+54(%rip)
	imulq	%rcx, %r8
	xorl	%r15d, %r15d
	movl	$.L.str.2, %edi
	movq	%r14, %rsi
                                        # kill: def $edx killed $edx killed $rdx
                                        # kill: def $ecx killed $ecx killed $rcx
	xorl	%eax, %eax
	callq	printf
	movslq	ip+4(%rip), %r14
	imulq	ip+64(%rip), %r14
	movq	%r14, %rdi
	callq	malloc
	movq	%rax, _ZZ10ReadBMPlinPcE3Img(%rip)
	testq	%rax, %rax
	je	.LBB8_3
# %bb.2:
	movl	$1, %esi
	movq	%rax, %rdi
	movq	%r14, %rdx
	movq	%rbx, %rcx
	callq	fread
	movq	%rbx, %rdi
	callq	fclose
	movq	_ZZ10ReadBMPlinPcE3Img(%rip), %r15
.LBB8_3:
	movq	%r15, %rax
	addq	$64, %rsp
	.cfi_def_cfa_offset 32
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.LBB8_4:
	.cfi_def_cfa_offset 96
	movl	$.L.str.1, %edi
	movq	%r14, %rsi
	xorl	%eax, %eax
	callq	printf
	movl	$1, %edi
	callq	exit
.Lfunc_end8:
	.size	_Z10ReadBMPlinPc, .Lfunc_end8-_Z10ReadBMPlinPc
	.cfi_endproc
                                        # -- End function
	.globl	_Z11WriteBMPlinPhPc             # -- Begin function _Z11WriteBMPlinPhPc
	.type	_Z11WriteBMPlinPhPc,@function
_Z11WriteBMPlinPhPc:                    # @_Z11WriteBMPlinPhPc
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movq	%rsi, %rbx
	movq	%rdi, %r15
	movl	$.L.str.3, %esi
	movq	%rbx, %rdi
	callq	fopen
	testq	%rax, %rax
	je	.LBB9_1
# %bb.2:
	movq	%rax, %r14
	movl	$ip+8, %edi
	movl	$1, %esi
	movl	$54, %edx
	movq	%rax, %rcx
	callq	fwrite
	movslq	ip+4(%rip), %rdx
	imulq	ip+64(%rip), %rdx
	movl	$1, %esi
	movq	%r15, %rdi
	movq	%r14, %rcx
	callq	fwrite
	movl	ip(%rip), %edx
	movslq	ip+4(%rip), %rcx
	movq	%rcx, %r8
	imulq	ip+64(%rip), %r8
	movl	$.L.str.5, %edi
	movq	%rbx, %rsi
                                        # kill: def $ecx killed $ecx killed $rcx
	xorl	%eax, %eax
	callq	printf
	movq	%r14, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	fclose                          # TAILCALL
.LBB9_1:
	.cfi_def_cfa_offset 32
	movl	$.L.str.4, %edi
	movq	%rbx, %rsi
	xorl	%eax, %eax
	callq	printf
	movl	$1, %edi
	callq	exit
.Lfunc_end9:
	.size	_Z11WriteBMPlinPhPc, .Lfunc_end9-_Z11WriteBMPlinPhPc
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst16,"aM",@progbits,16
	.p2align	4, 0x0                          # -- Begin function main
.LCPI10_0:
	.long	0                               # 0x0
	.long	255                             # 0xff
	.long	0                               # 0x0
	.long	0                               # 0x0
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$2456, %rsp                     # imm = 0x998
	.cfi_def_cfa_offset 2512
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
                                        # kill: def $edi killed $edi def $rdi
	movaps	.LCPI10_0(%rip), %xmm0          # xmm0 = [0,255,0,0]
	movaps	%xmm0, 80(%rsp)
	movups	.L.str.6(%rip), %xmm0
	movaps	%xmm0, 208(%rsp)
	movb	$0, 224(%rsp)
	addl	$-3, %edi
	cmpl	$3, %edi
	ja	.LBB10_73
# %bb.1:
	movq	%rsi, %rbx
	movl	$5, %r12d
	movl	$256, %r14d                     # imm = 0x100
	movl	$5, %r15d
	jmpq	*.LJTI10_0(,%rdi,8)
.LBB10_2:
	movq	40(%rbx), %rdi
	callq	atoi
	movl	%eax, %r14d
.LBB10_3:
	movq	32(%rbx), %rdi
	callq	atoi
	movl	%eax, %r12d
.LBB10_4:
	movl	%r12d, %r15d
	movq	24(%rbx), %rdi
	callq	atoi
	movl	%eax, %r12d
.LBB10_5:
	movq	8(%rbx), %rsi
	leaq	720(%rsp), %rdi
	callq	strcpy
	movq	16(%rbx), %rsi
	leaq	464(%rsp), %rdi
	callq	strcpy
	leal	-1025(%r14), %eax
	cmpl	$-993, %eax                     # imm = 0xFC1F
	jb	.LBB10_55
# %bb.6:
	leaq	720(%rsp), %rdi
	callq	_Z10ReadBMPlinPc
	movq	%rax, TheImg(%rip)
	testq	%rax, %rax
	je	.LBB10_57
# %bb.7:
	movq	%rax, %rbx
	movslq	ip+4(%rip), %rdi
	imulq	ip+64(%rip), %rdi
	callq	malloc
	movq	%rax, CopyImg(%rip)
	testq	%rax, %rax
	je	.LBB10_56
# %bb.8:
	leaq	76(%rsp), %rbx
	movl	$0, (%rbx)
	movq	%rbx, %rdi
	callq	hipGetDeviceCount
	cmpl	$0, (%rbx)
	je	.LBB10_58
# %bb.9:
	xorl	%edi, %edi
	callq	hipSetDevice
	testl	%eax, %eax
	jne	.LBB10_59
# %bb.10:
	leaq	984(%rsp), %rbx
	movq	%rbx, %rdi
	xorl	%esi, %esi
	callq	hipGetDevicePropertiesR0600
	movl	340(%rbx), %eax
	imull	336(%rbx), %eax
	imull	344(%rbx), %eax
	movl	%eax, %ecx
	shrl	$10, %ecx
	movl	%eax, %edx
	shrl	$20, %edx
	xorl	%esi, %esi
	cmpl	$5242880, %eax                  # imm = 0x500000
	setae	%sil
	cmovbq	%rcx, %rdx
	leal	75(,%rsi,2), %ecx
	leaq	96(%rsp), %rdi
	movl	$.L.str.17, %esi
	xorl	%eax, %eax
	callq	sprintf
	movl	320(%rbx), %ebx
	leaq	24(%rsp), %rdi
	callq	hipEventCreate
	leaq	16(%rsp), %rdi
	callq	hipEventCreate
	movl	ip+4(%rip), %eax
	movl	ip+64(%rip), %ecx
	imull	%eax, %ecx
	imull	ip(%rip), %eax
	leal	(%rax,%rax,2), %eax
	addl	%eax, %ecx
	leal	(%rcx,%rax,8), %esi
	addl	$16, %esi
	movl	$GPUptr, %edi
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB10_60
# %bb.11:
	movq	GPUptr(%rip), %rdi
	movq	%rdi, GPUImg(%rip)
	movslq	ip+4(%rip), %rax
	movq	ip+64(%rip), %rdx
	imulq	%rax, %rdx
	leaq	(%rdi,%rdx), %rcx
	movq	%rcx, GPUCopyImg(%rip)
	movslq	ip(%rip), %rsi
	imulq	%rax, %rsi
	addq	%rsi, %rcx
	movq	%rcx, NoiseMap(%rip)
	addq	%rsi, %rcx
	movq	%rcx, KernelIndices(%rip)
	addq	%rsi, %rcx
	movq	%rcx, NoisyPixelCoords(%rip)
	leaq	(%rcx,%rsi,8), %rax
	movq	%rax, GPU_PREV_BW(%rip)
	leaq	(%rax,%rsi,8), %rax
	movq	%rax, GPU_CURR_BW(%rip)
	leaq	(%rax,%rsi,8), %rcx
	movq	%rcx, GlobalMax(%rip)
	leaq	4(%rax,%rsi,8), %rcx
	movq	%rcx, GlobalMin(%rip)
	leaq	8(%rax,%rsi,8), %rcx
	movq	%rcx, NumNoisyPixelsGPU(%rip)
	leaq	12(%rax,%rsi,8), %rax
	movq	%rax, GPU_SAD(%rip)
	movq	TheImg(%rip), %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	testl	%eax, %eax
	jne	.LBB10_61
# %bb.12:
	movq	GlobalMax(%rip), %rdi
	leaq	80(%rsp), %rsi
	movl	$16, %edx
	movl	$1, %ecx
	callq	hipMemcpy
	testl	%eax, %eax
	jne	.LBB10_62
# %bb.13:
	movq	%rbx, 64(%rsp)                  # 8-byte Spill
	movq	NoiseMap(%rip), %rdi
	movslq	ip(%rip), %rax
	movslq	ip+4(%rip), %rdx
	imulq	%rax, %rdx
	movl	$1, %esi
	callq	hipMemset
	testl	%eax, %eax
	jne	.LBB10_64
# %bb.14:
	movq	24(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	leal	-1(%r14), %ebp
	movl	ip(%rip), %eax
	addl	%ebp, %eax
	xorl	%edx, %edx
	divl	%r14d
                                        # kill: def $eax killed $eax def $rax
	movl	ip+4(%rip), %ebx
	movq	%rax, 48(%rsp)                  # 8-byte Spill
	imull	%eax, %ebx
	btsq	$32, %rbx
	movl	%r14d, %r13d
	btsq	$32, %r13
	movq	%rbx, %rdi
	movl	$1, %esi
	movq	%r13, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB10_16
# %bb.15:
	movq	GPUCopyImg(%rip), %rdi
	movq	GPUImg(%rip), %rsi
	movq	GPU_CURR_BW(%rip), %rdx
	movl	ip(%rip), %ecx
	callq	_Z23__device_stub__BWKernelPhS_Pdj
.LBB10_16:
	callq	hipDeviceSynchronize
	testl	%eax, %eax
	jne	.LBB10_65
# %bb.17:
	movq	%rbx, %rdi
	movl	$1, %esi
	movq	%r13, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB10_19
# %bb.18:
	movq	NoisyPixelCoords(%rip), %rdi
	movq	GPUCopyImg(%rip), %rsi
	movq	NoiseMap(%rip), %rdx
	movq	GlobalMax(%rip), %rcx
	movq	GlobalMin(%rip), %r8
	movq	NumNoisyPixelsGPU(%rip), %r9
	movl	ip(%rip), %eax
	movl	ip+4(%rip), %r10d
	pushq	%r10
	.cfi_adjust_cfa_offset 8
	pushq	%rax
	.cfi_adjust_cfa_offset 8
	callq	_Z30__device_stub__findNoisyPixelsP11pixelCoordsPhS1_PjS2_S2_jj
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
.LBB10_19:
	callq	hipDeviceSynchronize
	testl	%eax, %eax
	jne	.LBB10_66
# %bb.20:
	movq	%r15, 40(%rsp)                  # 8-byte Spill
	movq	NumNoisyPixelsGPU(%rip), %rsi
	leaq	12(%rsp), %rdi
	movl	$4, %edx
	movl	$2, %ecx
	callq	hipMemcpy
	testl	%eax, %eax
	jne	.LBB10_67
# %bb.21:
	movabsq	$4294967296, %rcx               # imm = 0x100000000
	addl	12(%rsp), %ebp
	movl	%ebp, %eax
	xorl	%edx, %edx
	divl	%r14d
	movl	%eax, %r15d
	orq	%rcx, %r15
	movq	%r15, %rdi
	movl	$1, %esi
	movq	%r13, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB10_23
# %bb.22:
	movq	NoisyPixelCoords(%rip), %rdi
	movq	GPUCopyImg(%rip), %rsi
	movq	NoiseMap(%rip), %rdx
	movq	KernelIndices(%rip), %rcx
	movl	12(%rsp), %r8d
	movl	ip(%rip), %r9d
	subq	$8, %rsp
	.cfi_adjust_cfa_offset 8
	pushq	48(%rsp)                        # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	callq	_Z29__device_stub__determineMasksP11pixelCoordsPhS1_S1_jjj
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
.LBB10_23:
	callq	hipDeviceSynchronize
	testl	%eax, %eax
	jne	.LBB10_68
# %bb.24:
	movq	%rbx, %rdi
	movl	$1, %esi
	movq	%r13, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB10_26
# %bb.25:
	movq	GPU_PREV_BW(%rip), %rdi
	movq	GPU_CURR_BW(%rip), %rsi
	movl	ip+4(%rip), %edx
	imull	ip(%rip), %edx
	callq	_Z22__device_stub__PixCopyPdS_j
.LBB10_26:
	movq	%r14, 56(%rsp)                  # 8-byte Spill
	callq	hipDeviceSynchronize
	testl	%eax, %eax
	jne	.LBB10_69
# %bb.27:                               # %.preheader.preheader
	movl	$1, %ebx
.LBB10_28:                              # %.preheader
                                        # =>This Inner Loop Header: Depth=1
	movq	GPU_SAD(%rip), %rdi
	movl	$4, %edx
	xorl	%esi, %esi
	callq	hipMemset
	testl	%eax, %eax
	jne	.LBB10_52
# %bb.29:                               #   in Loop: Header=BB10_28 Depth=1
	movq	%r15, %rdi
	movl	$1, %esi
	movq	%r13, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB10_31
# %bb.30:                               #   in Loop: Header=BB10_28 Depth=1
	movq	GPU_CURR_BW(%rip), %rdi
	movq	GPU_PREV_BW(%rip), %rsi
	movq	NoisyPixelCoords(%rip), %rdx
	movq	KernelIndices(%rip), %rcx
	movl	12(%rsp), %r8d
	movl	ip(%rip), %r9d
	callq	_Z24__device_stub__ConvolutePdS_P11pixelCoordsPhjj
.LBB10_31:                              #   in Loop: Header=BB10_28 Depth=1
	callq	hipDeviceSynchronize
	testl	%eax, %eax
	jne	.LBB10_50
# %bb.32:                               #   in Loop: Header=BB10_28 Depth=1
	movq	%r15, %rdi
	movl	$1, %esi
	movq	%r13, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB10_34
# %bb.33:                               #   in Loop: Header=BB10_28 Depth=1
	movq	GPU_SAD(%rip), %rdi
	movq	GPU_PREV_BW(%rip), %rsi
	movq	GPU_CURR_BW(%rip), %rdx
	movq	NoisyPixelCoords(%rip), %rcx
	movl	12(%rsp), %r8d
	movl	ip(%rip), %r9d
	movl	ip+4(%rip), %eax
	subq	$8, %rsp
	.cfi_adjust_cfa_offset 8
	pushq	%rax
	.cfi_adjust_cfa_offset 8
	callq	_Z18__device_stub__SADPjPdS0_P11pixelCoordsjjj
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
.LBB10_34:                              #   in Loop: Header=BB10_28 Depth=1
	callq	hipDeviceSynchronize
	testl	%eax, %eax
	jne	.LBB10_49
# %bb.35:                               #   in Loop: Header=BB10_28 Depth=1
	movq	%r15, %rdi
	movl	$1, %esi
	movq	%r13, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB10_37
# %bb.36:                               #   in Loop: Header=BB10_28 Depth=1
	movq	GPU_PREV_BW(%rip), %rdi
	movq	GPU_CURR_BW(%rip), %rsi
	movq	NoisyPixelCoords(%rip), %rdx
	movl	12(%rsp), %ecx
	movl	ip(%rip), %r8d
	callq	_Z27__device_stub__NoisyPixCopyPdS_P11pixelCoordsjj
.LBB10_37:                              #   in Loop: Header=BB10_28 Depth=1
	callq	hipDeviceSynchronize
	testl	%eax, %eax
	jne	.LBB10_48
# %bb.38:                               #   in Loop: Header=BB10_28 Depth=1
	movq	GPU_SAD(%rip), %rsi
	movl	$4, %edx
	leaq	32(%rsp), %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	testl	%eax, %eax
	jne	.LBB10_47
# %bb.39:                               #   in Loop: Header=BB10_28 Depth=1
	movl	ip+4(%rip), %r14d
	imull	48(%rsp), %r14d                 # 4-byte Folded Reload
	movq	%r14, %rdi
	movabsq	$4294967296, %rax               # imm = 0x100000000
	orq	%rax, %rdi
	movl	$1, %esi
	movq	%r13, %rbp
	movq	%r13, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB10_41
# %bb.40:                               #   in Loop: Header=BB10_28 Depth=1
	movq	GPUImg(%rip), %rdi
	movq	GPU_CURR_BW(%rip), %rsi
	movl	ip(%rip), %edx
	callq	_Z24__device_stub__RGBKernelPhPdj
.LBB10_41:                              #   in Loop: Header=BB10_28 Depth=1
	movq	%r15, %r13
	movq	GPUImg(%rip), %rsi
	movq	%rsi, GPUResult(%rip)
	movq	CopyImg(%rip), %rdi
	movslq	ip+4(%rip), %rdx
	imulq	ip+64(%rip), %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	testl	%eax, %eax
	jne	.LBB10_46
# %bb.42:                               #   in Loop: Header=BB10_28 Depth=1
	movq	%rbx, %rcx
	incl	%ebx
	movl	$.L.str.33, %esi
	movl	$.L.str.34, %edx
	movl	$.L.str.35, %r8d
	leaq	464(%rsp), %r15
	movq	%r15, %rdi
                                        # kill: def $ecx killed $ecx killed $rcx
	xorl	%eax, %eax
	callq	sprintf
	movq	CopyImg(%rip), %rdi
	movq	%r15, %rsi
	callq	_Z11WriteBMPlinPhPc
                                        # kill: def $ebx killed $ebx def $rbx
	cmpl	%r12d, 32(%rsp)
	movq	%r13, %r15
	movq	%rbp, %r13
	ja	.LBB10_28
# %bb.43:
	movq	16(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	24(%rsp), %rdi
	callq	hipEventSynchronize
	movq	16(%rsp), %rdi
	callq	hipEventSynchronize
	movq	24(%rsp), %rsi
	movq	16(%rsp), %rdx
	leaq	36(%rsp), %rdi
	callq	hipEventElapsedTime
	callq	hipDeviceSynchronize
	testl	%eax, %eax
	jne	.LBB10_70
# %bb.44:
	movl	$.Lstr, %edi
	callq	puts@PLT
	leaq	984(%rsp), %rsi
	movl	360(%rsi), %edx
	movl	364(%rsi), %ecx
	leaq	96(%rsp), %r8
	movl	$.L.str.38, %edi
	movq	64(%rsp), %r9                   # 8-byte Reload
	xorl	%eax, %eax
	callq	printf
	movl	$.Lstr.1, %edi
	callq	puts@PLT
	subq	$8, %rsp
	.cfi_adjust_cfa_offset 8
	leaq	216(%rsp), %rsi
	leaq	728(%rsp), %rdx
	leaq	472(%rsp), %rcx
	movl	$.L.str.40, %edi
	movl	%r12d, %r8d
	movq	48(%rsp), %r9                   # 8-byte Reload
                                        # kill: def $r9d killed $r9d killed $r9
	xorl	%eax, %eax
	pushq	56(%rsp)                        # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	%r14
	.cfi_adjust_cfa_offset 8
	pushq	80(%rsp)                        # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	callq	printf
	addq	$32, %rsp
	.cfi_adjust_cfa_offset -32
	cvtss2sd	36(%rsp), %xmm0
	movl	$.L.str.41, %edi
	movb	$1, %al
	callq	printf
	movl	$.Lstr.2, %edi
	callq	puts@PLT
	movq	GPUptr(%rip), %rdi
	callq	hipFree
	movq	24(%rsp), %rdi
	callq	hipEventDestroy
	movq	16(%rsp), %rdi
	callq	hipEventDestroy
	callq	hipDeviceReset
	testl	%eax, %eax
	jne	.LBB10_71
# %bb.45:
	movq	TheImg(%rip), %rdi
	callq	free
	movq	CopyImg(%rip), %rdi
	callq	free
	xorl	%eax, %eax
	addq	$2456, %rsp                     # imm = 0x998
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB10_46:
	.cfi_def_cfa_offset 2512
	movq	stderr(%rip), %rcx
	movl	$.L.str.32, %edi
	jmp	.LBB10_53
.LBB10_47:
	movq	stderr(%rip), %rcx
	movl	$.L.str.31, %edi
	movl	$41, %esi
	jmp	.LBB10_54
.LBB10_48:
	movq	stderr(%rip), %rdi
	movl	$.L.str.30, %esi
	jmp	.LBB10_51
.LBB10_49:
	movq	stderr(%rip), %rdi
	movl	$.L.str.29, %esi
	jmp	.LBB10_51
.LBB10_50:
	movq	stderr(%rip), %rdi
	movl	$.L.str.28, %esi
.LBB10_51:
	movl	%eax, %edx
	xorl	%eax, %eax
	callq	fprintf
	jmp	.LBB10_75
.LBB10_52:
	movq	stderr(%rip), %rcx
	movl	$.L.str.27, %edi
.LBB10_53:
	movl	$29, %esi
.LBB10_54:
	movl	$1, %edx
	callq	fwrite
.LBB10_75:
	movl	$1, %edi
	callq	exit
.LBB10_55:
	movl	$.L.str.13, %edi
	movl	%r14d, %esi
	xorl	%eax, %eax
	callq	printf
	jmp	.LBB10_75
.LBB10_56:
	movq	%rbx, %rdi
	callq	free
.LBB10_57:
	movl	$.Lstr.5, %edi
	jmp	.LBB10_74
.LBB10_58:
	movl	$.Lstr.3, %edi
	jmp	.LBB10_74
.LBB10_59:
	movq	stderr(%rip), %rcx
	movl	$.L.str.16, %edi
	movl	$63, %esi
	jmp	.LBB10_54
.LBB10_60:
	movq	stderr(%rip), %rcx
	movl	$.L.str.18, %edi
	jmp	.LBB10_63
.LBB10_61:
	movq	stderr(%rip), %rcx
	movl	$.L.str.19, %edi
	movl	$45, %esi
	jmp	.LBB10_54
.LBB10_62:
	movq	stderr(%rip), %rcx
	movl	$.L.str.20, %edi
.LBB10_63:
	movl	$55, %esi
	jmp	.LBB10_54
.LBB10_64:
	movq	stderr(%rip), %rcx
	movl	$.L.str.21, %edi
	movl	$31, %esi
	jmp	.LBB10_54
.LBB10_65:
	movq	stderr(%rip), %rdi
	movl	$.L.str.22, %esi
	jmp	.LBB10_51
.LBB10_66:
	movq	stderr(%rip), %rdi
	movl	$.L.str.23, %esi
	jmp	.LBB10_51
.LBB10_67:
	movq	stderr(%rip), %rcx
	movl	$.L.str.24, %edi
	movl	$48, %esi
	jmp	.LBB10_54
.LBB10_68:
	movq	stderr(%rip), %rdi
	movl	$.L.str.25, %esi
	jmp	.LBB10_51
.LBB10_69:
	movq	stderr(%rip), %rdi
	movl	$.L.str.26, %esi
	jmp	.LBB10_51
.LBB10_70:
	movq	stderr(%rip), %rcx
	movl	$.L.str.36, %edi
	movl	$47, %esi
	jmp	.LBB10_72
.LBB10_71:
	movq	stderr(%rip), %rcx
	movl	$.L.str.43, %edi
	movl	$22, %esi
.LBB10_72:
	movl	$1, %edx
	callq	fwrite
	movq	TheImg(%rip), %rdi
	callq	free
	movq	CopyImg(%rip), %rdi
	callq	free
	jmp	.LBB10_75
.LBB10_73:
	leaq	208(%rsp), %rbx
	movl	$.L.str.7, %edi
	movq	%rbx, %rsi
	xorl	%eax, %eax
	callq	printf
	movl	$.L.str.8, %edi
	movq	%rbx, %rsi
	xorl	%eax, %eax
	callq	printf
	movl	$.L.str.9, %edi
	movq	%rbx, %rsi
	xorl	%eax, %eax
	callq	printf
	movl	$.L.str.10, %edi
	movq	%rbx, %rsi
	xorl	%eax, %eax
	callq	printf
	movl	$.L.str.11, %edi
	movq	%rbx, %rsi
	xorl	%eax, %eax
	callq	printf
	movl	$.Lstr.6, %edi
.LBB10_74:
	callq	puts@PLT
	jmp	.LBB10_75
.Lfunc_end10:
	.size	main, .Lfunc_end10-main
	.cfi_endproc
	.section	.rodata,"a",@progbits
	.p2align	3, 0x0
.LJTI10_0:
	.quad	.LBB10_5
	.quad	.LBB10_4
	.quad	.LBB10_3
	.quad	.LBB10_2
                                        # -- End function
	.text
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB11_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB11_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z15findNoisyPixelsP11pixelCoordsPhS1_PjS2_S2_jj, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z14determineMasksP11pixelCoordsPhS1_S1_jjj, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z9ConvolutePdS_P11pixelCoordsPhjj, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z3SADPjPdS0_P11pixelCoordsjjj, %esi
	movl	$.L__unnamed_4, %edx
	movl	$.L__unnamed_4, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z8BWKernelPhS_Pdj, %esi
	movl	$.L__unnamed_5, %edx
	movl	$.L__unnamed_5, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z9RGBKernelPhPdj, %esi
	movl	$.L__unnamed_6, %edx
	movl	$.L__unnamed_6, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z12NoisyPixCopyPdS_P11pixelCoordsjj, %esi
	movl	$.L__unnamed_7, %edx
	movl	$.L__unnamed_7, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z7PixCopyPdS_j, %esi
	movl	$.L__unnamed_8, %edx
	movl	$.L__unnamed_8, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$0, 8(%rsp)
	movl	$1, (%rsp)
	movl	$mask0, %esi
	movl	$.L__unnamed_9, %edx
	movl	$.L__unnamed_9, %ecx
	movl	$72, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	callq	__hipRegisterVar
	movl	$0, 8(%rsp)
	movl	$1, (%rsp)
	movl	$mask1, %esi
	movl	$.L__unnamed_10, %edx
	movl	$.L__unnamed_10, %ecx
	movl	$200, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	callq	__hipRegisterVar
	movl	$0, 8(%rsp)
	movl	$1, (%rsp)
	movl	$mask2, %esi
	movl	$.L__unnamed_11, %edx
	movl	$.L__unnamed_11, %ecx
	movl	$200, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	callq	__hipRegisterVar
	movl	$0, 8(%rsp)
	movl	$1, (%rsp)
	movl	$mask3, %esi
	movl	$.L__unnamed_12, %edx
	movl	$.L__unnamed_12, %ecx
	movl	$392, %r9d                      # imm = 0x188
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	callq	__hipRegisterVar
	movl	$0, 8(%rsp)
	movl	$1, (%rsp)
	movl	$mask4, %esi
	movl	$.L__unnamed_13, %edx
	movl	$.L__unnamed_13, %ecx
	movl	$392, %r9d                      # imm = 0x188
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	callq	__hipRegisterVar
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end11:
	.size	__hip_module_ctor, .Lfunc_end11-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB12_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB12_2:
	retq
.Lfunc_end12:
	.size	__hip_module_dtor, .Lfunc_end12-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	ip,@object                      # @ip
	.bss
	.globl	ip
	.p2align	3, 0x0
ip:
	.zero	72
	.size	ip, 72

	.type	TheImg,@object                  # @TheImg
	.globl	TheImg
	.p2align	3, 0x0
TheImg:
	.quad	0
	.size	TheImg, 8

	.type	CopyImg,@object                 # @CopyImg
	.globl	CopyImg
	.p2align	3, 0x0
CopyImg:
	.quad	0
	.size	CopyImg, 8

	.type	GPUImg,@object                  # @GPUImg
	.globl	GPUImg
	.p2align	3, 0x0
GPUImg:
	.quad	0
	.size	GPUImg, 8

	.type	GPUCopyImg,@object              # @GPUCopyImg
	.globl	GPUCopyImg
	.p2align	3, 0x0
GPUCopyImg:
	.quad	0
	.size	GPUCopyImg, 8

	.type	GPUptr,@object                  # @GPUptr
	.globl	GPUptr
	.p2align	3, 0x0
GPUptr:
	.quad	0
	.size	GPUptr, 8

	.type	GPUResult,@object               # @GPUResult
	.globl	GPUResult
	.p2align	3, 0x0
GPUResult:
	.quad	0
	.size	GPUResult, 8

	.type	NoiseMap,@object                # @NoiseMap
	.globl	NoiseMap
	.p2align	3, 0x0
NoiseMap:
	.quad	0
	.size	NoiseMap, 8

	.type	KernelIndices,@object           # @KernelIndices
	.globl	KernelIndices
	.p2align	3, 0x0
KernelIndices:
	.quad	0
	.size	KernelIndices, 8

	.type	GPU_PREV_BW,@object             # @GPU_PREV_BW
	.globl	GPU_PREV_BW
	.p2align	3, 0x0
GPU_PREV_BW:
	.quad	0
	.size	GPU_PREV_BW, 8

	.type	GPU_CURR_BW,@object             # @GPU_CURR_BW
	.globl	GPU_CURR_BW
	.p2align	3, 0x0
GPU_CURR_BW:
	.quad	0
	.size	GPU_CURR_BW, 8

	.type	NoisyPixelCoords,@object        # @NoisyPixelCoords
	.globl	NoisyPixelCoords
	.p2align	3, 0x0
NoisyPixelCoords:
	.quad	0
	.size	NoisyPixelCoords, 8

	.type	GlobalMax,@object               # @GlobalMax
	.globl	GlobalMax
	.p2align	3, 0x0
GlobalMax:
	.quad	0
	.size	GlobalMax, 8

	.type	GlobalMin,@object               # @GlobalMin
	.globl	GlobalMin
	.p2align	3, 0x0
GlobalMin:
	.quad	0
	.size	GlobalMin, 8

	.type	NumNoisyPixelsGPU,@object       # @NumNoisyPixelsGPU
	.globl	NumNoisyPixelsGPU
	.p2align	3, 0x0
NumNoisyPixelsGPU:
	.quad	0
	.size	NumNoisyPixelsGPU, 8

	.type	GPUmutexes,@object              # @GPUmutexes
	.globl	GPUmutexes
	.p2align	3, 0x0
GPUmutexes:
	.quad	0
	.size	GPUmutexes, 8

	.type	GPU_SAD,@object                 # @GPU_SAD
	.globl	GPU_SAD
	.p2align	3, 0x0
GPU_SAD:
	.quad	0
	.size	GPU_SAD, 8

	.type	_Z15findNoisyPixelsP11pixelCoordsPhS1_PjS2_S2_jj,@object # @_Z15findNoisyPixelsP11pixelCoordsPhS1_PjS2_S2_jj
	.section	.rodata,"a",@progbits
	.globl	_Z15findNoisyPixelsP11pixelCoordsPhS1_PjS2_S2_jj
	.p2align	3, 0x0
_Z15findNoisyPixelsP11pixelCoordsPhS1_PjS2_S2_jj:
	.quad	_Z30__device_stub__findNoisyPixelsP11pixelCoordsPhS1_PjS2_S2_jj
	.size	_Z15findNoisyPixelsP11pixelCoordsPhS1_PjS2_S2_jj, 8

	.type	mask0,@object                   # @mask0
	.local	mask0
	.comm	mask0,72,16
	.type	mask1,@object                   # @mask1
	.local	mask1
	.comm	mask1,200,16
	.type	mask2,@object                   # @mask2
	.local	mask2
	.comm	mask2,200,16
	.type	mask3,@object                   # @mask3
	.local	mask3
	.comm	mask3,392,16
	.type	mask4,@object                   # @mask4
	.local	mask4
	.comm	mask4,392,16
	.type	_Z14determineMasksP11pixelCoordsPhS1_S1_jjj,@object # @_Z14determineMasksP11pixelCoordsPhS1_S1_jjj
	.globl	_Z14determineMasksP11pixelCoordsPhS1_S1_jjj
	.p2align	3, 0x0
_Z14determineMasksP11pixelCoordsPhS1_S1_jjj:
	.quad	_Z29__device_stub__determineMasksP11pixelCoordsPhS1_S1_jjj
	.size	_Z14determineMasksP11pixelCoordsPhS1_S1_jjj, 8

	.type	_Z9ConvolutePdS_P11pixelCoordsPhjj,@object # @_Z9ConvolutePdS_P11pixelCoordsPhjj
	.globl	_Z9ConvolutePdS_P11pixelCoordsPhjj
	.p2align	3, 0x0
_Z9ConvolutePdS_P11pixelCoordsPhjj:
	.quad	_Z24__device_stub__ConvolutePdS_P11pixelCoordsPhjj
	.size	_Z9ConvolutePdS_P11pixelCoordsPhjj, 8

	.type	_Z3SADPjPdS0_P11pixelCoordsjjj,@object # @_Z3SADPjPdS0_P11pixelCoordsjjj
	.globl	_Z3SADPjPdS0_P11pixelCoordsjjj
	.p2align	3, 0x0
_Z3SADPjPdS0_P11pixelCoordsjjj:
	.quad	_Z18__device_stub__SADPjPdS0_P11pixelCoordsjjj
	.size	_Z3SADPjPdS0_P11pixelCoordsjjj, 8

	.type	_Z8BWKernelPhS_Pdj,@object      # @_Z8BWKernelPhS_Pdj
	.globl	_Z8BWKernelPhS_Pdj
	.p2align	3, 0x0
_Z8BWKernelPhS_Pdj:
	.quad	_Z23__device_stub__BWKernelPhS_Pdj
	.size	_Z8BWKernelPhS_Pdj, 8

	.type	_Z9RGBKernelPhPdj,@object       # @_Z9RGBKernelPhPdj
	.globl	_Z9RGBKernelPhPdj
	.p2align	3, 0x0
_Z9RGBKernelPhPdj:
	.quad	_Z24__device_stub__RGBKernelPhPdj
	.size	_Z9RGBKernelPhPdj, 8

	.type	_Z12NoisyPixCopyPdS_P11pixelCoordsjj,@object # @_Z12NoisyPixCopyPdS_P11pixelCoordsjj
	.globl	_Z12NoisyPixCopyPdS_P11pixelCoordsjj
	.p2align	3, 0x0
_Z12NoisyPixCopyPdS_P11pixelCoordsjj:
	.quad	_Z27__device_stub__NoisyPixCopyPdS_P11pixelCoordsjj
	.size	_Z12NoisyPixCopyPdS_P11pixelCoordsjj, 8

	.type	_Z7PixCopyPdS_j,@object         # @_Z7PixCopyPdS_j
	.globl	_Z7PixCopyPdS_j
	.p2align	3, 0x0
_Z7PixCopyPdS_j:
	.quad	_Z22__device_stub__PixCopyPdS_j
	.size	_Z7PixCopyPdS_j, 8

	.type	_ZZ10ReadBMPlinPcE3Img,@object  # @_ZZ10ReadBMPlinPcE3Img
	.local	_ZZ10ReadBMPlinPcE3Img
	.comm	_ZZ10ReadBMPlinPcE3Img,8,8
	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"rb"
	.size	.L.str, 3

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"\n\n%s NOT FOUND\n\n"
	.size	.L.str.1, 17

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"\n Input File name: %17s  (%u x %u)   File Size=%u"
	.size	.L.str.2, 50

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"wb"
	.size	.L.str.3, 3

	.type	.L.str.4,@object                # @.str.4
.L.str.4:
	.asciz	"\n\nFILE CREATION ERROR: %s\n\n"
	.size	.L.str.4, 28

	.type	.L.str.5,@object                # @.str.5
.L.str.5:
	.asciz	"\nOutput File name: %17s  (%u x %u)   File Size=%u"
	.size	.L.str.5, 50

	.type	.L.str.6,@object                # @.str.6
.L.str.6:
	.asciz	"randNoiseRemoval"
	.size	.L.str.6, 17

	.type	.L.str.7,@object                # @.str.7
.L.str.7:
	.asciz	"\n\nUsage:   %s InputFilename OutputFilename [T] [R] [ThrPerBlk]"
	.size	.L.str.7, 63

	.type	.L.str.8,@object                # @.str.8
.L.str.8:
	.asciz	"\n\nExample: %s Astronaut.bmp Output.bmp"
	.size	.L.str.8, 39

	.type	.L.str.9,@object                # @.str.9
.L.str.9:
	.asciz	"\n\nExample: %s Astronaut.bmp Output.bmp 5"
	.size	.L.str.9, 41

	.type	.L.str.10,@object               # @.str.10
.L.str.10:
	.asciz	"\n\nExample: %s Astronaut.bmp Output.bmp 5 5"
	.size	.L.str.10, 43

	.type	.L.str.11,@object               # @.str.11
.L.str.11:
	.asciz	"\n\nExample: %s Astronaut.bmp Output.bmp 5 5 128"
	.size	.L.str.11, 47

	.type	.L.str.13,@object               # @.str.13
.L.str.13:
	.asciz	"Invalid ThrPerBlk option '%u'. Must be between 32 and 1024. \n"
	.size	.L.str.13, 62

	.type	.L.str.16,@object               # @.str.16
.L.str.16:
	.asciz	"hipSetDevice failed!  Do you have a CUDA-capable GPU installed?"
	.size	.L.str.16, 64

	.type	.L.str.17,@object               # @.str.17
.L.str.17:
	.asciz	"%u %c"
	.size	.L.str.17, 6

	.type	.L.str.18,@object               # @.str.18
.L.str.18:
	.asciz	"hipMalloc failed! Can't allocate GPU memory for buffers"
	.size	.L.str.18, 56

	.type	.L.str.19,@object               # @.str.19
.L.str.19:
	.asciz	"hipMemcpy for input image CPU to GPU  failed!"
	.size	.L.str.19, 46

	.type	.L.str.20,@object               # @.str.20
.L.str.20:
	.asciz	"hipMemcpy for mutex initializations CPU to GPU  failed!"
	.size	.L.str.20, 56

	.type	.L.str.21,@object               # @.str.21
.L.str.21:
	.asciz	"hipMemset for Noise Map failed!"
	.size	.L.str.21, 32

	.type	.L.str.22,@object               # @.str.22
.L.str.22:
	.asciz	"\n\n hipDeviceSynchronize for B&WKernel returned error code %d after launching the kernel!\n"
	.size	.L.str.22, 90

	.type	.L.str.23,@object               # @.str.23
.L.str.23:
	.asciz	"\n\nhipDeviceSynchronize for findNoisyPixels returned error code %d after launching the kernel!\n"
	.size	.L.str.23, 95

	.type	.L.str.24,@object               # @.str.24
.L.str.24:
	.asciz	"hipMemcpy of NumNoisyPixels, GPU to CPU  failed!"
	.size	.L.str.24, 49

	.type	.L.str.25,@object               # @.str.25
.L.str.25:
	.asciz	"\n\nhipDeviceSynchronize for determineMasks returned error code %d after launching the kernel!\n"
	.size	.L.str.25, 94

	.type	.L.str.26,@object               # @.str.26
.L.str.26:
	.asciz	"\n\nhipDeviceSynchronize for PixCopy returned error code %d after launching the kernel!\n"
	.size	.L.str.26, 87

	.type	.L.str.27,@object               # @.str.27
.L.str.27:
	.asciz	"hipMemset for GPU_SAD failed!"
	.size	.L.str.27, 30

	.type	.L.str.28,@object               # @.str.28
.L.str.28:
	.asciz	"\n\n hipDeviceSynchronize for Convolute returned error code %d after launching the kernel!\n"
	.size	.L.str.28, 90

	.type	.L.str.29,@object               # @.str.29
.L.str.29:
	.asciz	"\n\n hipDeviceSynchronize for SAD returned error code %d after launching the kernel!\n"
	.size	.L.str.29, 84

	.type	.L.str.30,@object               # @.str.30
.L.str.30:
	.asciz	"\n\n hipDeviceSynchronize for NoisyPixCopy returned error code %d after launching the kernel!\n"
	.size	.L.str.30, 93

	.type	.L.str.31,@object               # @.str.31
.L.str.31:
	.asciz	"hipMemcpy of SAD from GPU to CPU  failed!"
	.size	.L.str.31, 42

	.type	.L.str.32,@object               # @.str.32
.L.str.32:
	.asciz	"hipMemcpy GPU to CPU  failed!"
	.size	.L.str.32, 30

	.type	.L.str.33,@object               # @.str.33
.L.str.33:
	.asciz	"%s%d%s"
	.size	.L.str.33, 7

	.type	.L.str.34,@object               # @.str.34
.L.str.34:
	.asciz	"stages/stage"
	.size	.L.str.34, 13

	.type	.L.str.35,@object               # @.str.35
.L.str.35:
	.asciz	".bmp"
	.size	.L.str.35, 5

	.type	.L.str.36,@object               # @.str.36
.L.str.36:
	.asciz	"\n Program failed after cudaDeviceSynchronize()!"
	.size	.L.str.36, 48

	.type	.L.str.38,@object               # @.str.38
.L.str.38:
	.asciz	"%s    ComputeCapab=%d.%d  [max %s blocks; %d thr/blk] \n"
	.size	.L.str.38, 56

	.type	.L.str.40,@object               # @.str.40
.L.str.40:
	.asciz	"%s %s %s %d %d %u   [%u BLOCKS, %u BLOCKS/ROW]\n"
	.size	.L.str.40, 48

	.type	.L.str.41,@object               # @.str.41
.L.str.41:
	.asciz	"Kernel Execution    =%7.2f ms\n"
	.size	.L.str.41, 31

	.type	.L.str.43,@object               # @.str.43
.L.str.43:
	.asciz	"hipDeviceReset failed!"
	.size	.L.str.43, 23

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z15findNoisyPixelsP11pixelCoordsPhS1_PjS2_S2_jj"
	.size	.L__unnamed_1, 49

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z14determineMasksP11pixelCoordsPhS1_S1_jjj"
	.size	.L__unnamed_2, 44

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z9ConvolutePdS_P11pixelCoordsPhjj"
	.size	.L__unnamed_3, 35

	.type	.L__unnamed_4,@object           # @3
.L__unnamed_4:
	.asciz	"_Z3SADPjPdS0_P11pixelCoordsjjj"
	.size	.L__unnamed_4, 31

	.type	.L__unnamed_5,@object           # @4
.L__unnamed_5:
	.asciz	"_Z8BWKernelPhS_Pdj"
	.size	.L__unnamed_5, 19

	.type	.L__unnamed_6,@object           # @5
.L__unnamed_6:
	.asciz	"_Z9RGBKernelPhPdj"
	.size	.L__unnamed_6, 18

	.type	.L__unnamed_7,@object           # @6
.L__unnamed_7:
	.asciz	"_Z12NoisyPixCopyPdS_P11pixelCoordsjj"
	.size	.L__unnamed_7, 37

	.type	.L__unnamed_8,@object           # @7
.L__unnamed_8:
	.asciz	"_Z7PixCopyPdS_j"
	.size	.L__unnamed_8, 16

	.type	.L__unnamed_9,@object           # @8
.L__unnamed_9:
	.asciz	"mask0"
	.size	.L__unnamed_9, 6

	.type	.L__unnamed_10,@object          # @9
.L__unnamed_10:
	.asciz	"mask1"
	.size	.L__unnamed_10, 6

	.type	.L__unnamed_11,@object          # @10
.L__unnamed_11:
	.asciz	"mask2"
	.size	.L__unnamed_11, 6

	.type	.L__unnamed_12,@object          # @11
.L__unnamed_12:
	.asciz	"mask3"
	.size	.L__unnamed_12, 6

	.type	.L__unnamed_13,@object          # @12
.L__unnamed_13:
	.asciz	"mask4"
	.size	.L__unnamed_13, 6

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.type	.Lstr,@object                   # @str
	.section	.rodata.str1.1,"aMS",@progbits,1
.Lstr:
	.asciz	"\n\n--------------------------------------------------------------------------"
	.size	.Lstr, 77

	.type	.Lstr.1,@object                 # @str.1
.Lstr.1:
	.asciz	"--------------------------------------------------------------------------"
	.size	.Lstr.1, 75

	.type	.Lstr.2,@object                 # @str.2
.Lstr.2:
	.asciz	"--------------------------------------------------------------------------\n"
	.size	.Lstr.2, 76

	.type	.Lstr.3,@object                 # @str.3
.Lstr.3:
	.asciz	"\nNo CUDA Device is available"
	.size	.Lstr.3, 29

	.type	.Lstr.5,@object                 # @str.5
.Lstr.5:
	.asciz	"Cannot allocate memory for the input image..."
	.size	.Lstr.5, 46

	.type	.Lstr.6,@object                 # @str.6
.Lstr.6:
	.asciz	"\n\nT = reconstruction threshold, R = mask selection threshold\n"
	.size	.Lstr.6, 62

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z30__device_stub__findNoisyPixelsP11pixelCoordsPhS1_PjS2_S2_jj
	.addrsig_sym _Z29__device_stub__determineMasksP11pixelCoordsPhS1_S1_jjj
	.addrsig_sym _Z24__device_stub__ConvolutePdS_P11pixelCoordsPhjj
	.addrsig_sym _Z18__device_stub__SADPjPdS0_P11pixelCoordsjjj
	.addrsig_sym _Z23__device_stub__BWKernelPhS_Pdj
	.addrsig_sym _Z24__device_stub__RGBKernelPhPdj
	.addrsig_sym _Z27__device_stub__NoisyPixCopyPdS_P11pixelCoordsjj
	.addrsig_sym _Z22__device_stub__PixCopyPdS_j
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym ip
	.addrsig_sym GPUptr
	.addrsig_sym _Z15findNoisyPixelsP11pixelCoordsPhS1_PjS2_S2_jj
	.addrsig_sym mask0
	.addrsig_sym mask1
	.addrsig_sym mask2
	.addrsig_sym mask3
	.addrsig_sym mask4
	.addrsig_sym _Z14determineMasksP11pixelCoordsPhS1_S1_jjj
	.addrsig_sym _Z9ConvolutePdS_P11pixelCoordsPhjj
	.addrsig_sym _Z3SADPjPdS0_P11pixelCoordsjjj
	.addrsig_sym _Z8BWKernelPhS_Pdj
	.addrsig_sym _Z9RGBKernelPhPdj
	.addrsig_sym _Z12NoisyPixCopyPdS_P11pixelCoordsjj
	.addrsig_sym _Z7PixCopyPdS_j
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z15findNoisyPixelsP11pixelCoordsPhS1_PjS2_S2_jj ; -- Begin function _Z15findNoisyPixelsP11pixelCoordsPhS1_PjS2_S2_jj
	.globl	_Z15findNoisyPixelsP11pixelCoordsPhS1_PjS2_S2_jj
	.p2align	8
	.type	_Z15findNoisyPixelsP11pixelCoordsPhS1_PjS2_S2_jj,@function
_Z15findNoisyPixelsP11pixelCoordsPhS1_PjS2_S2_jj: ; @_Z15findNoisyPixelsP11pixelCoordsPhS1_PjS2_S2_jj
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x44
	s_load_b64 s[12:13], s[0:1], 0x30
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_cvt_f32_u32_e32 v1, s2
	s_sub_i32 s4, 0, s2
	s_add_i32 s5, s12, s2
	s_add_i32 s5, s5, -1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v1, v1
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v1, 0x4f7ffffe, v1
	v_cvt_u32_f32_e32 v1, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s3, v1
	s_mul_i32 s4, s4, s3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_hi_u32 s4, s3, s4
	s_add_i32 s3, s3, s4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_hi_u32 s3, s5, s3
	s_mul_i32 s4, s3, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_sub_i32 s4, s5, s4
	s_add_i32 s5, s3, 1
	s_sub_i32 s6, s4, s2
	s_cmp_ge_u32 s4, s2
	s_cselect_b32 s3, s5, s3
	s_cselect_b32 s4, s6, s4
	s_add_i32 s5, s3, 1
	s_cmp_ge_u32 s4, s2
	s_cselect_b32 s3, s5, s3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cvt_f32_u32_e32 v1, s3
	s_sub_i32 s5, 0, s3
	v_rcp_iflag_f32_e32 v1, v1
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v1, 0x4f7ffffe, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v1, v1
	v_readfirstlane_b32 s4, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s5, s5, s4
	s_mul_hi_u32 s5, s4, s5
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s4, s4, s5
	s_mul_hi_u32 s4, s15, s4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_mul_i32 s5, s4, s3
	s_add_i32 s6, s4, 1
	s_sub_i32 s5, s15, s5
	s_sub_i32 s7, s5, s3
	s_cmp_ge_u32 s5, s3
	s_cselect_b32 s4, s6, s4
	s_cselect_b32 s5, s7, s5
	s_add_i32 s6, s4, 1
	s_cmp_ge_u32 s5, s3
	s_cselect_b32 s14, s6, s4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s3, s14, s3
	s_sub_i32 s15, s15, s3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	s_mul_i32 s15, s15, s2
	s_add_i32 s2, s12, -4
	v_add_nc_u32_e32 v1, s15, v0
	v_cmp_ge_u32_e32 vcc_lo, s2, v1
	v_cmp_lt_u32_e64 s2, 2, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, vcc_lo, s2
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_20
; %bb.1:
	s_add_i32 s2, s13, -4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
	s_cmp_gt_u32 s14, s2
	s_cselect_b32 s2, -1, 0
	s_cmp_lt_u32 s14, 3
	s_cselect_b32 s3, -1, 0
	s_or_b32 s2, s2, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s2
	s_cbranch_vccnz .LBB0_20
; %bb.2:
	s_load_b256 s[4:11], s[0:1], 0x0
	v_mov_b32_e32 v4, v1
	s_load_b128 s[0:3], s[0:1], 0x20
	s_add_i32 s13, s14, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_mul_i32 s13, s12, s13
	v_mad_u64_u32 v[2:3], null, s14, s12, v[4:5]
	s_add_i32 s15, s15, s13
	v_mov_b32_e32 v4, 0
	v_add3_u32 v5, s15, v0, -1
	v_mov_b32_e32 v0, 0xff
	s_mov_b32 s13, -1
	s_waitcnt lgkmcnt(0)
	global_load_u8 v3, v2, s[6:7]
.LBB0_3:                                ; %.preheader
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_4 Depth 2
	s_mov_b32 s15, -1
.LBB0_4:                                ;   Parent Loop BB0_3 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s16, s15, s13
	s_cmp_eq_u32 s16, 0
	s_cbranch_scc1 .LBB0_6
; %bb.5:                                ;   in Loop: Header=BB0_4 Depth=2
	v_add3_u32 v6, v5, s15, 1
	v_and_b32_e32 v4, 0xff, v4
	v_and_b32_e32 v0, 0xff, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v7, 31, v6
	v_add_co_u32 v6, vcc_lo, s6, v6
	v_add_co_ci_u32_e32 v7, vcc_lo, s7, v7, vcc_lo
	global_load_u8 v6, v[6:7], off
	s_waitcnt vmcnt(0)
	v_max_u16 v4, v6, v4
	v_min_u16 v0, v6, v0
.LBB0_6:                                ;   in Loop: Header=BB0_4 Depth=2
	s_add_i32 s15, s15, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s15, 2
	s_cbranch_scc0 .LBB0_4
; %bb.7:                                ;   in Loop: Header=BB0_3 Depth=1
	v_add_nc_u32_e32 v5, s12, v5
	s_add_i32 s13, s13, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s13, 2
	s_cbranch_scc0 .LBB0_3
; %bb.8:
	v_and_b32_e32 v4, 0xff, v4
	s_mov_b32 s7, exec_lo
	s_mov_b32 s6, 0
                                        ; implicit-def: $vgpr5
.LBB0_9:                                ; %ComputeLoop
                                        ; =>This Inner Loop Header: Depth=1
	s_ctz_i32_b32 s12, s7
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_readlane_b32 s13, v4, s12
	s_lshl_b32 s15, 1, s12
	v_writelane_b32 v5, s6, s12
	s_and_not1_b32 s7, s7, s15
	s_delay_alu instid0(VALU_DEP_2)
	s_max_u32 s6, s6, s13
	s_cmp_lg_u32 s7, 0
	s_cbranch_scc1 .LBB0_9
; %bb.10:                               ; %ComputeEnd
	v_mbcnt_lo_u32_b32 v6, exec_lo, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_eq_u32_e32 vcc_lo, 0, v6
                                        ; implicit-def: $vgpr6
	s_and_saveexec_b32 s7, vcc_lo
	s_xor_b32 s7, exec_lo, s7
	s_cbranch_execz .LBB0_12
; %bb.11:
	v_dual_mov_b32 v6, 0 :: v_dual_mov_b32 v7, s6
	global_atomic_max_u32 v6, v6, v7, s[10:11] glc
.LBB0_12:
	s_or_b32 exec_lo, exec_lo, s7
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s6, v6
	v_and_b32_e32 v0, 0xff, v0
	s_mov_b32 s10, exec_lo
	s_mov_b32 s7, -1
                                        ; implicit-def: $vgpr6
.LBB0_13:                               ; %ComputeLoop96
                                        ; =>This Inner Loop Header: Depth=1
	s_ctz_i32_b32 s11, s10
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_readlane_b32 s12, v0, s11
	s_lshl_b32 s13, 1, s11
	v_writelane_b32 v6, s7, s11
	s_and_not1_b32 s10, s10, s13
	s_delay_alu instid0(VALU_DEP_2)
	s_min_u32 s7, s7, s12
	s_cmp_lg_u32 s10, 0
	s_cbranch_scc1 .LBB0_13
; %bb.14:                               ; %ComputeEnd97
	v_mbcnt_lo_u32_b32 v7, exec_lo, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_eq_u32_e32 vcc_lo, 0, v7
                                        ; implicit-def: $vgpr7
	s_and_saveexec_b32 s10, vcc_lo
	s_xor_b32 s10, exec_lo, s10
	s_cbranch_execz .LBB0_16
; %bb.15:
	v_dual_mov_b32 v7, 0 :: v_dual_mov_b32 v8, s7
	global_atomic_min_u32 v7, v7, v8, s[0:1] glc
.LBB0_16:
	s_or_b32 exec_lo, exec_lo, s10
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s0, v7
	v_max_u32_e32 v5, s6, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_min_u32_e32 v6, s0, v6
	v_and_b32_e32 v6, 0xff, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cmp_eq_u16_e32 vcc_lo, v0, v6
	v_dual_cndmask_b32 v0, 0, v0 :: v_dual_and_b32 v5, 0xff, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u16_e32 vcc_lo, v4, v5
	v_dual_cndmask_b32 v4, 0xff, v4 :: v_dual_and_b32 v3, 0xff, v3
	v_cmp_eq_u32_e32 vcc_lo, v0, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_eq_u32_e64 s0, v4, v3
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB0_20
; %bb.17:
	s_mov_b32 s1, exec_lo
	s_mov_b32 s0, exec_lo
	v_mbcnt_lo_u32_b32 v0, s1, 0
                                        ; implicit-def: $vgpr3
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB0_19
; %bb.18:
	s_bcnt1_i32_b32 s1, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v4, s1
	global_atomic_add_u32 v3, v3, v4, s[2:3] glc
.LBB0_19:
	s_or_b32 exec_lo, exec_lo, s0
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s0, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v0, s14 :: v_dual_add_nc_u32 v3, s0, v0
	v_add_co_u32 v5, s0, s8, v2
	v_add_co_ci_u32_e64 v6, null, s9, 0, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v4, 31, v3
	v_lshlrev_b64 v[3:4], 3, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s4, v3
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v4, vcc_lo
	v_mov_b32_e32 v4, 0
	global_store_b64 v[2:3], v[0:1], off
	global_store_b8 v[5:6], v4, off
.LBB0_20:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z15findNoisyPixelsP11pixelCoordsPhS1_PjS2_S2_jj
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 312
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 9
		.amdhsa_next_free_sgpr 17
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z15findNoisyPixelsP11pixelCoordsPhS1_PjS2_S2_jj, .Lfunc_end0-_Z15findNoisyPixelsP11pixelCoordsPhS1_PjS2_S2_jj
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1052
; NumSgprs: 19
; NumVgprs: 9
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 19
; NumVGPRsForWavesPerEU: 9
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z14determineMasksP11pixelCoordsPhS1_S1_jjj ; -- Begin function _Z14determineMasksP11pixelCoordsPhS1_S1_jjj
	.globl	_Z14determineMasksP11pixelCoordsPhS1_S1_jjj
	.p2align	8
	.type	_Z14determineMasksP11pixelCoordsPhS1_S1_jjj,@function
_Z14determineMasksP11pixelCoordsPhS1_S1_jjj: ; @_Z14determineMasksP11pixelCoordsPhS1_S1_jjj
; %bb.0:
	s_clause 0x1
	s_load_b32 s4, s[2:3], 0x3c
	s_load_b128 s[16:19], s[2:3], 0x20
	v_and_b32_e32 v5, 0x3ff, v0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s4, s4, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[1:2], null, s15, s4, v[5:6]
	s_mov_b32 s4, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_ge_u32_e64 s16, v1
	s_cbranch_execz .LBB1_31
; %bb.1:
	s_load_b256 s[4:11], s[2:3], 0x0
	v_mov_b32_e32 v2, 0
	s_load_b64 s[0:1], s[0:1], 0x4
	v_bfe_u32 v6, v0, 10, 10
	v_bfe_u32 v0, v0, 20, 10
	s_mov_b32 s12, -2
	v_lshlrev_b64 v[3:4], 3, v[1:2]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, s4, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
	s_lshr_b32 s0, s0, 16
	v_mul_u32_u24_e32 v6, s1, v6
	s_mul_i32 s0, s0, s1
	global_load_b64 v[3:4], v[3:4], off
	v_mul_lo_u32 v5, s0, v5
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, mask2@rel32@lo+4
	s_addc_u32 s1, s1, mask2@rel32@hi+12
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, mask1@rel32@lo+4
	s_addc_u32 s3, s3, mask1@rel32@hi+12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v0, v5, v6, v0
	v_mul_lo_u32 v0, v0, 60
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v7, -2, v3
	v_mov_b32_e32 v5, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v7, s17, v7
	v_add3_u32 v6, v4, v7, -2
.LBB1_2:                                ; %.preheader148
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB1_3 Depth 2
	s_delay_alu instid0(VALU_DEP_1)
	v_mov_b32_e32 v7, v6
	s_mov_b64 s[4:5], 0
.LBB1_3:                                ;   Parent Loop BB1_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v8, 31, v7
	v_add_co_u32 v9, vcc_lo, s8, v7
	s_mov_b32 s13, exec_lo
	v_add_co_ci_u32_e32 v10, vcc_lo, s9, v8, vcc_lo
	global_load_u8 v9, v[9:10], off
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u16_e32 0, v9
	s_cbranch_execz .LBB1_8
; %bb.4:                                ;   in Loop: Header=BB1_3 Depth=2
	s_add_u32 s14, s2, s4
	s_addc_u32 s15, s3, s5
	s_load_b64 s[14:15], s[14:15], 0x0
	s_waitcnt lgkmcnt(0)
	v_cmp_eq_f64_e64 s14, s[14:15], 0
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 vcc_lo, exec_lo, s14
	s_cbranch_vccnz .LBB1_6
; %bb.5:                                ;   in Loop: Header=BB1_3 Depth=2
	v_add_co_u32 v9, vcc_lo, s6, v7
	v_add_co_ci_u32_e32 v10, vcc_lo, s7, v8, vcc_lo
	v_add_nc_u32_e32 v11, v0, v5
	global_load_u8 v9, v[9:10], off
	v_add_nc_u32_e32 v10, 1, v5
	s_delay_alu instid0(VALU_DEP_1)
	v_mov_b32_e32 v5, v10
	s_waitcnt vmcnt(0)
	ds_store_b8 v11, v9
.LBB1_6:                                ;   in Loop: Header=BB1_3 Depth=2
	s_add_u32 s14, s0, s4
	s_addc_u32 s15, s1, s5
	s_load_b64 s[14:15], s[14:15], 0x0
	s_waitcnt lgkmcnt(0)
	v_cmp_eq_f64_e64 s14, s[14:15], 0
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 vcc_lo, exec_lo, s14
	s_cbranch_vccnz .LBB1_8
; %bb.7:                                ;   in Loop: Header=BB1_3 Depth=2
	v_add_co_u32 v9, vcc_lo, s6, v7
	v_add_co_ci_u32_e32 v10, vcc_lo, s7, v8, vcc_lo
	global_load_u8 v8, v[9:10], off
	v_add_nc_u32_e32 v9, 1, v2
	v_add_nc_u32_e32 v10, v0, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_mov_b32_e32 v2, v9
	s_waitcnt vmcnt(0)
	ds_store_b8 v10, v8 offset:14
.LBB1_8:                                ; %Flow265
                                        ;   in Loop: Header=BB1_3 Depth=2
	s_or_b32 exec_lo, exec_lo, s13
	v_add_nc_u32_e32 v7, 1, v7
	s_add_u32 s4, s4, 8
	s_addc_u32 s5, s5, 0
	s_cmp_lg_u32 s4, 40
	s_cbranch_scc1 .LBB1_3
; %bb.9:                                ;   in Loop: Header=BB1_2 Depth=1
	s_add_i32 s12, s12, 1
	s_add_u32 s0, s0, 40
	s_addc_u32 s1, s1, 0
	v_add_nc_u32_e32 v6, s17, v6
	s_add_u32 s2, s2, 40
	s_addc_u32 s3, s3, 0
	s_cmp_eq_u32 s12, 3
	s_cbranch_scc0 .LBB1_2
; %bb.10:                               ; %.preheader147
	v_dual_mov_b32 v6, 0 :: v_dual_add_nc_u32 v3, -3, v3
	s_mov_b32 s12, -3
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, mask4@rel32@lo+4
	s_addc_u32 s1, s1, mask4@rel32@hi+12
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, mask3@rel32@lo+4
	s_addc_u32 s3, s3, mask3@rel32@hi+12
	v_mul_lo_u32 v3, s17, v3
	s_delay_alu instid0(VALU_DEP_1)
	v_add3_u32 v3, v4, v3, -3
	v_mov_b32_e32 v4, 0
.LBB1_11:                               ; %.preheader
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB1_12 Depth 2
	s_delay_alu instid0(VALU_DEP_2)
	v_mov_b32_e32 v7, v3
	s_mov_b64 s[4:5], 0
.LBB1_12:                               ;   Parent Loop BB1_11 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v8, 31, v7
	v_add_co_u32 v9, vcc_lo, s8, v7
	s_mov_b32 s13, exec_lo
	v_add_co_ci_u32_e32 v10, vcc_lo, s9, v8, vcc_lo
	global_load_u8 v9, v[9:10], off
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u16_e32 0, v9
	s_cbranch_execz .LBB1_17
; %bb.13:                               ;   in Loop: Header=BB1_12 Depth=2
	s_add_u32 s14, s2, s4
	s_addc_u32 s15, s3, s5
	s_load_b64 s[14:15], s[14:15], 0x0
	s_waitcnt lgkmcnt(0)
	v_cmp_eq_f64_e64 s14, s[14:15], 0
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 vcc_lo, exec_lo, s14
	s_cbranch_vccnz .LBB1_15
; %bb.14:                               ;   in Loop: Header=BB1_12 Depth=2
	v_add_co_u32 v9, vcc_lo, s6, v7
	v_add_co_ci_u32_e32 v10, vcc_lo, s7, v8, vcc_lo
	global_load_u8 v9, v[9:10], off
	v_add_nc_u32_e32 v10, 1, v4
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_mov_b32 v4, v10 :: v_dual_add_nc_u32 v11, v0, v4
	s_waitcnt vmcnt(0)
	ds_store_b8 v11, v9 offset:28
.LBB1_15:                               ;   in Loop: Header=BB1_12 Depth=2
	s_add_u32 s14, s0, s4
	s_addc_u32 s15, s1, s5
	s_load_b64 s[14:15], s[14:15], 0x0
	s_waitcnt lgkmcnt(0)
	v_cmp_eq_f64_e64 s14, s[14:15], 0
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 vcc_lo, exec_lo, s14
	s_cbranch_vccnz .LBB1_17
; %bb.16:                               ;   in Loop: Header=BB1_12 Depth=2
	v_add_co_u32 v9, vcc_lo, s6, v7
	v_add_co_ci_u32_e32 v10, vcc_lo, s7, v8, vcc_lo
	global_load_u8 v8, v[9:10], off
	v_add_nc_u32_e32 v9, 1, v6
	v_add_nc_u32_e32 v10, v0, v6
	s_delay_alu instid0(VALU_DEP_2)
	v_mov_b32_e32 v6, v9
	s_waitcnt vmcnt(0)
	ds_store_b8 v10, v8 offset:42
.LBB1_17:                               ; %Flow263
                                        ;   in Loop: Header=BB1_12 Depth=2
	s_or_b32 exec_lo, exec_lo, s13
	v_add_nc_u32_e32 v7, 1, v7
	s_add_u32 s4, s4, 8
	s_addc_u32 s5, s5, 0
	s_cmp_lg_u32 s4, 56
	s_cbranch_scc1 .LBB1_12
; %bb.18:                               ;   in Loop: Header=BB1_11 Depth=1
	s_add_i32 s12, s12, 1
	s_add_u32 s0, s0, 56
	s_addc_u32 s1, s1, 0
	v_add_nc_u32_e32 v3, s17, v3
	s_add_u32 s2, s2, 56
	s_addc_u32 s3, s3, 0
	s_cmp_lg_u32 s12, 4
	s_cbranch_scc1 .LBB1_11
; %bb.19:
	v_min3_u32 v3, v5, v2, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_min_u32_e32 v3, v3, v6
	v_cmp_le_u32_e32 vcc_lo, s18, v3
	v_mov_b32_e32 v3, 0
	s_and_saveexec_b32 s1, vcc_lo
	s_cbranch_execz .LBB1_30
; %bb.20:
	v_lshlrev_b16 v2, 8, v2
	v_and_b32_e32 v3, 0xff, v5
	v_lshlrev_b16 v5, 8, v6
	v_and_b32_e32 v4, 0xff, v4
	s_mov_b32 s2, 0
	s_mov_b32 s3, 0x3e76c4e1
	v_or_b32_e32 v2, v3, v2
	v_mov_b32_e32 v6, 0
	v_or_b32_e32 v3, v4, v5
	v_mov_b32_e32 v4, 0x49742400
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_mov_b32 v2, 0 :: v_dual_and_b32 v5, 0xffff, v2
	v_lshlrev_b32_e32 v3, 16, v3
	s_delay_alu instid0(VALU_DEP_1)
	v_or_b32_e32 v3, v5, v3
	v_mov_b32_e32 v5, v0
	ds_store_b32 v0, v3 offset:56
                                        ; implicit-def: $vgpr3
.LBB1_21:                               ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB1_23 Depth 2
                                        ;     Child Loop BB1_27 Depth 2
	v_add_nc_u32_e32 v7, s2, v0
	ds_load_u8 v8, v7 offset:56
	s_waitcnt lgkmcnt(0)
	v_and_b32_e32 v7, 0xffff, v8
	v_cmp_ne_u16_e32 vcc_lo, 0, v8
	s_and_saveexec_b32 s4, vcc_lo
	s_cbranch_execz .LBB1_25
; %bb.22:                               ; %.lr.ph.preheader
                                        ;   in Loop: Header=BB1_21 Depth=1
	s_delay_alu instid0(VALU_DEP_2)
	v_dual_mov_b32 v9, v5 :: v_dual_mov_b32 v10, v7
	s_mov_b32 s5, 0
.LBB1_23:                               ; %.lr.ph
                                        ;   Parent Loop BB1_21 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	ds_load_u8 v11, v9
	v_add_nc_u32_e32 v10, -1, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_eq_u32_e64 s0, 0, v10
	s_or_b32 s5, s0, s5
	s_waitcnt lgkmcnt(0)
	v_cvt_f32_ubyte0_e32 v11, v11
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_add_f32 v6, v6, v11 :: v_dual_add_nc_u32 v9, 1, v9
	s_and_not1_b32 exec_lo, exec_lo, s5
	s_cbranch_execnz .LBB1_23
; %bb.24:                               ; %Flow259
                                        ;   in Loop: Header=BB1_21 Depth=1
	s_or_b32 exec_lo, exec_lo, s5
.LBB1_25:                               ; %Flow260
                                        ;   in Loop: Header=BB1_21 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s4
	v_cvt_f32_ubyte0_e32 v8, v8
	s_and_saveexec_b32 s0, vcc_lo
	s_cbranch_execz .LBB1_29
; %bb.26:                               ; %.lr.ph167.preheader
                                        ;   in Loop: Header=BB1_21 Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_div_scale_f32 v9, null, v8, v8, v6
	s_mov_b32 s4, 0
	s_mov_b32 s5, 0
	v_rcp_f32_e32 v10, v9
	s_waitcnt_depctr 0xfff
	v_fma_f32 v11, -v9, v10, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v10, v11, v10
	v_div_scale_f32 v11, vcc_lo, v6, v8, v6
	v_mul_f32_e32 v12, v11, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v13, -v9, v12, v11
	v_fmac_f32_e32 v12, v13, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v9, -v9, v12, v11
	v_div_fmas_f32 v9, v9, v10, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_div_fixup_f32 v9, v9, v8, v6
.LBB1_27:                               ; %.lr.ph167
                                        ;   Parent Loop BB1_21 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_add_nc_u32_e32 v10, s5, v5
	s_add_i32 s5, s5, 1
	ds_load_u8 v10, v10
	s_waitcnt lgkmcnt(0)
	v_cvt_f32_ubyte0_e32 v10, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v10, v10, v9
	v_frexp_mant_f32_e64 v11, |v10|
	v_frexp_exp_i32_f32_e32 v12, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cmp_gt_f32_e32 vcc_lo, 0x3f2aaaab, v11
	v_cndmask_b32_e64 v13, 0, 1, vcc_lo
	v_subrev_co_ci_u32_e32 v12, vcc_lo, 0, v12, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ldexp_f32 v11, v11, v13
	v_cvt_f32_i32_e32 v12, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v13, 1.0, v11
	v_mul_f32_e32 v17, 0x3f317218, v12
	v_cmp_neq_f32_e64 s6, 0x7f800000, |v10|
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v15, v13
	v_add_f32_e32 v16, -1.0, v13
	v_dual_add_f32 v14, -1.0, v11 :: v_dual_sub_f32 v11, v11, v16
	v_fma_f32 v16, 0x3f317218, v12, -v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v16, 0xb102e308, v12
	s_waitcnt_depctr 0xfff
	v_dual_mul_f32 v18, v14, v15 :: v_dual_add_f32 v19, v17, v16
	v_mul_f32_e32 v12, v13, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v13, v18, v13, -v12
	v_fmac_f32_e32 v13, v18, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v11, v12, v13
	v_sub_f32_e32 v20, v14, v11
	v_sub_f32_e32 v12, v11, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v12, v12, v13
	v_sub_f32_e32 v14, v14, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v11, v14, v11
	v_add_f32_e32 v11, v12, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v11, v20, v11
	v_mul_f32_e32 v11, v15, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v12, v18, v11
	v_sub_f32_e32 v13, v12, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v11, v11, v13 :: v_dual_mul_f32 v14, v12, v12
	v_ldexp_f32 v15, v12, 1
	v_add_f32_e32 v18, v11, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v13, v12, v12, -v14
	v_ldexp_f32 v20, v11, 1
	v_fmac_f32_e32 v13, v12, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v18, v14, v13
	v_fmaak_f32 v21, s3, v18, 0x3e91f4c4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v22, v12, v18 :: v_dual_fmaak_f32 v21, v18, v21, 0x3ecccdef
	v_sub_f32_e32 v14, v18, v14
	v_sub_f32_e32 v13, v13, v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v14, v18, v12, -v22
	v_fmac_f32_e32 v14, v18, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v23, v18, v21 :: v_dual_fmac_f32 v14, v13, v12
	v_fma_f32 v11, v18, v21, -v23
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v11, v13, v21
	v_dual_add_f32 v13, v23, v11 :: v_dual_add_f32 v12, v22, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v21, v13, v23 :: v_dual_sub_f32 v18, v12, v22
	v_add_f32_e32 v22, 0x3f2aaaaa, v13
	v_dual_sub_f32 v11, v11, v21 :: v_dual_sub_f32 v14, v14, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v11, 0x31739010, v11
	v_add_f32_e32 v18, 0xbf2aaaaa, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v13, v13, v18
	v_add_f32_e32 v11, v11, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v13, v22, v11
	v_sub_f32_e32 v18, v22, v13
	v_mul_f32_e32 v21, v12, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v11, v11, v18
	v_fma_f32 v18, v12, v13, -v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v18, v12, v11
	v_fmac_f32_e32 v18, v14, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v11, v21, v18
	v_add_f32_e32 v12, v15, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v14, v12, v15 :: v_dual_sub_f32 v13, v11, v21
	v_sub_f32_e32 v15, v19, v17
	v_sub_f32_e32 v11, v11, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v15, v16, v15
	v_sub_f32_e32 v13, v18, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v13, v20, v13
	v_add_f32_e32 v11, v13, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v13, v12, v11
	v_add_f32_e32 v14, v19, v13
	v_sub_f32_e32 v12, v13, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v16, v14, v19 :: v_dual_sub_f32 v11, v11, v12
	v_sub_f32_e32 v12, v13, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v17, v14, v16 :: v_dual_add_f32 v16, v15, v11
	v_sub_f32_e32 v13, v19, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v12, v12, v13
	v_sub_f32_e32 v13, v16, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v12, v16, v12
	v_sub_f32_e32 v16, v16, v13
	v_sub_f32_e32 v11, v11, v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v17, v14, v12
	v_dual_sub_f32 v13, v15, v16 :: v_dual_sub_f32 v14, v17, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v11, v11, v13 :: v_dual_sub_f32 v12, v12, v14
	v_add_f32_e32 v11, v11, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v12, v17, v11
	v_add_f32_e32 v14, v12, v12
	v_sub_f32_e32 v13, v12, v17
	v_mul_f32_e32 v15, 0, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v12, v12, 2.0, -v14
	v_sub_f32_e32 v11, v11, v13
	v_cmp_class_f32_e64 vcc_lo, v14, 0x204
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v15, 2.0, v11
	v_add_f32_e32 v11, v12, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v12, v14, v11
	v_cndmask_b32_e32 v13, v12, v14, vcc_lo
	v_sub_f32_e32 v12, v12, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_eq_f32_e32 vcc_lo, 0x42b17218, v13
	v_sub_f32_e32 v11, v11, v12
	v_cndmask_b32_e64 v15, 0, 0x37000000, vcc_lo
	v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v13|
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v16, v13, v15
	v_cndmask_b32_e32 v11, 0, v11, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v17, 0x3fb8aa3b, v16
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v16
	v_add_f32_e32 v11, v15, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f32 v18, 0x3fb8aa3b, v16, -v17
	v_rndne_f32_e32 v19, v17
	v_dual_fmac_f32 v18, 0x32a5705f, v16 :: v_dual_sub_f32 v17, v17, v19
	v_cvt_i32_f32_e32 v14, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v17, v17, v18
	v_exp_f32_e32 v17, v17
	s_waitcnt_depctr 0xfff
	v_ldexp_f32 v12, v17, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v12, 0, v12, vcc_lo
	v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v16
	v_cndmask_b32_e32 v12, 0x7f800000, v12, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v11, v12, v11, v12
	v_cmp_eq_f32_e32 vcc_lo, 0x7f800000, v12
	v_cndmask_b32_e32 v11, v11, v12, vcc_lo
	v_cmp_neq_f32_e32 vcc_lo, 0, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v11, 0x7f800000, |v11|, s6
	v_cndmask_b32_e32 v10, 0, v11, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, s5, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_add_f32_e32 v2, v2, v10
	s_or_b32 s4, vcc_lo, s4
	s_and_not1_b32 exec_lo, exec_lo, s4
	s_cbranch_execnz .LBB1_27
; %bb.28:                               ; %Flow
                                        ;   in Loop: Header=BB1_21 Depth=1
	s_or_b32 exec_lo, exec_lo, s4
.LBB1_29:                               ; %Flow258
                                        ;   in Loop: Header=BB1_21 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_or_b32 exec_lo, exec_lo, s0
	v_div_scale_f32 v7, null, v8, v8, v2
	v_div_scale_f32 v11, vcc_lo, v2, v8, v2
	s_add_i32 s2, s2, 1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v9, v7
	v_add_nc_u32_e32 v5, 14, v5
	s_cmp_lg_u32 s2, 4
	s_waitcnt_depctr 0xfff
	v_fma_f32 v10, -v7, v9, 1.0
	v_fmac_f32_e32 v9, v10, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v10, v11, v9
	v_fma_f32 v12, -v7, v10, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v10, v12, v9
	v_fma_f32 v7, -v7, v10, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v7, v7, v9, v10
	v_div_fixup_f32 v7, v7, v8, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_lt_f32_e32 vcc_lo, v7, v4
	v_cndmask_b32_e32 v4, v4, v7, vcc_lo
	v_cndmask_b32_e64 v3, v3, s2, vcc_lo
	s_cbranch_scc1 .LBB1_21
.LBB1_30:                               ; %Flow261
	s_or_b32 exec_lo, exec_lo, s1
	v_add_co_u32 v0, s0, s10, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v1, null, s11, 0, s0
	global_store_b8 v[0:1], v3, off
.LBB1_31:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z14determineMasksP11pixelCoordsPhS1_S1_jjj
		.amdhsa_group_segment_fixed_size 61440
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 304
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 1
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 24
		.amdhsa_next_free_sgpr 20
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z14determineMasksP11pixelCoordsPhS1_S1_jjj, .Lfunc_end1-_Z14determineMasksP11pixelCoordsPhS1_S1_jjj
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 2436
; NumSgprs: 22
; NumVgprs: 24
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 61440 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 22
; NumVGPRsForWavesPerEU: 24
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.text
	.protected	_Z9ConvolutePdS_P11pixelCoordsPhjj ; -- Begin function _Z9ConvolutePdS_P11pixelCoordsPhjj
	.globl	_Z9ConvolutePdS_P11pixelCoordsPhjj
	.p2align	8
	.type	_Z9ConvolutePdS_P11pixelCoordsPhjj,@function
_Z9ConvolutePdS_P11pixelCoordsPhjj:     ; @_Z9ConvolutePdS_P11pixelCoordsPhjj
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x34
	s_load_b64 s[8:9], s[0:1], 0x20
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_u32_e64 s8, v1
	s_cbranch_execz .LBB2_34
; %bb.1:                                ; %NodeBlock268
	s_load_b256 s[0:7], s[0:1], 0x0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 3, v[1:2]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v2, vcc_lo, s4, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
	s_mov_b32 s4, exec_lo
	global_load_u8 v4, v1, s[6:7]
	global_load_b64 v[0:1], v[2:3], off
                                        ; implicit-def: $vgpr2_vgpr3
	s_waitcnt vmcnt(1)
	v_cmpx_lt_i16_e32 1, v4
	s_xor_b32 s8, exec_lo, s4
	s_cbranch_execz .LBB2_21
; %bb.2:                                ; %NodeBlock266
                                        ; implicit-def: $vgpr2_vgpr3
	s_mov_b32 s4, exec_lo
	v_cmpx_lt_i16_e32 2, v4
	s_xor_b32 s10, exec_lo, s4
	s_cbranch_execz .LBB2_15
; %bb.3:                                ; %LeafBlock
	v_cmp_ne_u16_e32 vcc_lo, 3, v4
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v4, -3, v0
                                        ; implicit-def: $vgpr2_vgpr3
	s_and_saveexec_b32 s4, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s11, exec_lo, s4
	s_cbranch_execz .LBB2_9
; %bb.4:                                ; %.preheader.preheader
	s_delay_alu instid0(VALU_DEP_1)
	v_mul_lo_u32 v4, s9, v4
	v_mov_b32_e32 v2, 0
	v_mov_b32_e32 v3, 0
	s_mov_b32 s12, -3
	s_getpc_b64 s[4:5]
	s_add_u32 s4, s4, mask4@rel32@lo+4
	s_addc_u32 s5, s5, mask4@rel32@hi+12
	s_delay_alu instid0(VALU_DEP_3)
	v_add3_u32 v6, v1, v4, -3
.LBB2_5:                                ; %.preheader
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB2_6 Depth 2
	s_delay_alu instid0(VALU_DEP_1)
	v_mov_b32_e32 v4, v6
	s_mov_b64 s[6:7], 0
.LBB2_6:                                ;   Parent Loop BB2_5 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(VALU_DEP_1)
	v_ashrrev_i32_e32 v5, 31, v4
	s_add_u32 s14, s4, s6
	s_addc_u32 s15, s5, s7
	s_add_u32 s6, s6, 8
	s_load_b64 s[14:15], s[14:15], 0x0
	v_lshlrev_b64 v[7:8], 3, v[4:5]
	v_add_nc_u32_e32 v4, 1, v4
	s_addc_u32 s7, s7, 0
	s_cmp_lg_u32 s6, 56
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v7, vcc_lo, s2, v7
	v_add_co_ci_u32_e32 v8, vcc_lo, s3, v8, vcc_lo
	global_load_b64 v[7:8], v[7:8], off
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_fma_f64 v[2:3], v[7:8], s[14:15], v[2:3]
	s_cbranch_scc1 .LBB2_6
; %bb.7:                                ;   in Loop: Header=BB2_5 Depth=1
	s_add_i32 s12, s12, 1
	v_add_nc_u32_e32 v6, s9, v6
	s_add_u32 s4, s4, 56
	s_addc_u32 s5, s5, 0
	s_cmp_lg_u32 s12, 4
	s_cbranch_scc1 .LBB2_5
; %bb.8:                                ; %Flow
                                        ; implicit-def: $vgpr4
.LBB2_9:                                ; %Flow271
	s_and_not1_saveexec_b32 s11, s11
	s_cbranch_execz .LBB2_14
; %bb.10:                               ; %.preheader131.preheader
	v_mul_lo_u32 v4, s9, v4
	v_mov_b32_e32 v2, 0
	v_mov_b32_e32 v3, 0
	s_mov_b32 s12, -3
	s_getpc_b64 s[4:5]
	s_add_u32 s4, s4, mask3@rel32@lo+4
	s_addc_u32 s5, s5, mask3@rel32@hi+12
	s_delay_alu instid0(VALU_DEP_3)
	v_add3_u32 v6, v1, v4, -3
.LBB2_11:                               ; %.preheader131
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB2_12 Depth 2
	s_delay_alu instid0(VALU_DEP_1)
	v_mov_b32_e32 v4, v6
	s_mov_b64 s[6:7], 0
.LBB2_12:                               ;   Parent Loop BB2_11 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(VALU_DEP_1)
	v_ashrrev_i32_e32 v5, 31, v4
	s_add_u32 s14, s4, s6
	s_addc_u32 s15, s5, s7
	s_add_u32 s6, s6, 8
	s_load_b64 s[14:15], s[14:15], 0x0
	v_lshlrev_b64 v[7:8], 3, v[4:5]
	v_add_nc_u32_e32 v4, 1, v4
	s_addc_u32 s7, s7, 0
	s_cmp_lg_u32 s6, 56
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v7, vcc_lo, s2, v7
	v_add_co_ci_u32_e32 v8, vcc_lo, s3, v8, vcc_lo
	global_load_b64 v[7:8], v[7:8], off
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_fma_f64 v[2:3], v[7:8], s[14:15], v[2:3]
	s_cbranch_scc1 .LBB2_12
; %bb.13:                               ;   in Loop: Header=BB2_11 Depth=1
	s_add_i32 s12, s12, 1
	v_add_nc_u32_e32 v6, s9, v6
	s_add_u32 s4, s4, 56
	s_addc_u32 s5, s5, 0
	s_cmp_eq_u32 s12, 4
	s_cbranch_scc0 .LBB2_11
.LBB2_14:                               ; %Flow272
	s_or_b32 exec_lo, exec_lo, s11
.LBB2_15:                               ; %Flow274
	s_and_not1_saveexec_b32 s10, s10
	s_cbranch_execz .LBB2_20
; %bb.16:                               ; %.preheader129.preheader
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v2, -2, v0
	s_mov_b32 s11, -2
	s_getpc_b64 s[4:5]
	s_add_u32 s4, s4, mask2@rel32@lo+4
	s_addc_u32 s5, s5, mask2@rel32@hi+12
	v_mul_lo_u32 v4, s9, v2
	v_mov_b32_e32 v2, 0
	v_mov_b32_e32 v3, 0
	s_delay_alu instid0(VALU_DEP_3)
	v_add3_u32 v6, v1, v4, -2
.LBB2_17:                               ; %.preheader129
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB2_18 Depth 2
	s_delay_alu instid0(VALU_DEP_1)
	v_mov_b32_e32 v4, v6
	s_mov_b64 s[6:7], 0
.LBB2_18:                               ;   Parent Loop BB2_17 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(VALU_DEP_1)
	v_ashrrev_i32_e32 v5, 31, v4
	s_add_u32 s12, s4, s6
	s_addc_u32 s13, s5, s7
	s_add_u32 s6, s6, 8
	s_load_b64 s[12:13], s[12:13], 0x0
	v_lshlrev_b64 v[7:8], 3, v[4:5]
	v_add_nc_u32_e32 v4, 1, v4
	s_addc_u32 s7, s7, 0
	s_cmp_lg_u32 s6, 40
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v7, vcc_lo, s2, v7
	v_add_co_ci_u32_e32 v8, vcc_lo, s3, v8, vcc_lo
	global_load_b64 v[7:8], v[7:8], off
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_fma_f64 v[2:3], v[7:8], s[12:13], v[2:3]
	s_cbranch_scc1 .LBB2_18
; %bb.19:                               ;   in Loop: Header=BB2_17 Depth=1
	s_add_i32 s11, s11, 1
	v_add_nc_u32_e32 v6, s9, v6
	s_add_u32 s4, s4, 40
	s_addc_u32 s5, s5, 0
	s_cmp_eq_u32 s11, 3
	s_cbranch_scc0 .LBB2_17
.LBB2_20:                               ; %Flow275
	s_or_b32 exec_lo, exec_lo, s10
                                        ; implicit-def: $vgpr4
.LBB2_21:                               ; %Flow280
	s_and_not1_saveexec_b32 s8, s8
	s_cbranch_execz .LBB2_33
; %bb.22:                               ; %NodeBlock
                                        ; implicit-def: $vgpr2_vgpr3
	s_mov_b32 s4, exec_lo
	v_cmpx_lt_i16_e32 0, v4
	s_xor_b32 s10, exec_lo, s4
	s_cbranch_execz .LBB2_27
; %bb.23:                               ; %.preheader127.preheader
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v2, -2, v0
	s_mov_b32 s11, -2
	s_getpc_b64 s[4:5]
	s_add_u32 s4, s4, mask1@rel32@lo+4
	s_addc_u32 s5, s5, mask1@rel32@hi+12
	v_mul_lo_u32 v4, s9, v2
	v_mov_b32_e32 v2, 0
	v_mov_b32_e32 v3, 0
	s_delay_alu instid0(VALU_DEP_3)
	v_add3_u32 v6, v1, v4, -2
.LBB2_24:                               ; %.preheader127
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB2_25 Depth 2
	s_delay_alu instid0(VALU_DEP_1)
	v_mov_b32_e32 v4, v6
	s_mov_b64 s[6:7], 0
.LBB2_25:                               ;   Parent Loop BB2_24 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(VALU_DEP_1)
	v_ashrrev_i32_e32 v5, 31, v4
	s_add_u32 s12, s4, s6
	s_addc_u32 s13, s5, s7
	s_add_u32 s6, s6, 8
	s_load_b64 s[12:13], s[12:13], 0x0
	v_lshlrev_b64 v[7:8], 3, v[4:5]
	v_add_nc_u32_e32 v4, 1, v4
	s_addc_u32 s7, s7, 0
	s_cmp_lg_u32 s6, 40
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v7, vcc_lo, s2, v7
	v_add_co_ci_u32_e32 v8, vcc_lo, s3, v8, vcc_lo
	global_load_b64 v[7:8], v[7:8], off
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_fma_f64 v[2:3], v[7:8], s[12:13], v[2:3]
	s_cbranch_scc1 .LBB2_25
; %bb.26:                               ;   in Loop: Header=BB2_24 Depth=1
	s_add_i32 s11, s11, 1
	v_add_nc_u32_e32 v6, s9, v6
	s_add_u32 s4, s4, 40
	s_addc_u32 s5, s5, 0
	s_cmp_eq_u32 s11, 3
	s_cbranch_scc0 .LBB2_24
.LBB2_27:                               ; %Flow278
	s_and_not1_saveexec_b32 s10, s10
	s_cbranch_execz .LBB2_32
; %bb.28:                               ; %.preheader125.preheader
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v2, -1, v0
	s_mov_b32 s11, -1
	s_getpc_b64 s[4:5]
	s_add_u32 s4, s4, mask0@rel32@lo+4
	s_addc_u32 s5, s5, mask0@rel32@hi+12
	v_mul_lo_u32 v4, s9, v2
	v_mov_b32_e32 v2, 0
	v_mov_b32_e32 v3, 0
	s_delay_alu instid0(VALU_DEP_3)
	v_add3_u32 v6, v1, v4, -1
.LBB2_29:                               ; %.preheader125
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB2_30 Depth 2
	s_delay_alu instid0(VALU_DEP_1)
	v_mov_b32_e32 v4, v6
	s_mov_b64 s[6:7], 0
.LBB2_30:                               ;   Parent Loop BB2_29 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(VALU_DEP_1)
	v_ashrrev_i32_e32 v5, 31, v4
	s_add_u32 s12, s4, s6
	s_addc_u32 s13, s5, s7
	s_add_u32 s6, s6, 8
	s_load_b64 s[12:13], s[12:13], 0x0
	v_lshlrev_b64 v[7:8], 3, v[4:5]
	v_add_nc_u32_e32 v4, 1, v4
	s_addc_u32 s7, s7, 0
	s_cmp_lg_u32 s6, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v7, vcc_lo, s2, v7
	v_add_co_ci_u32_e32 v8, vcc_lo, s3, v8, vcc_lo
	global_load_b64 v[7:8], v[7:8], off
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_fma_f64 v[2:3], v[7:8], s[12:13], v[2:3]
	s_cbranch_scc1 .LBB2_30
; %bb.31:                               ;   in Loop: Header=BB2_29 Depth=1
	s_add_i32 s11, s11, 1
	v_add_nc_u32_e32 v6, s9, v6
	s_add_u32 s4, s4, 24
	s_addc_u32 s5, s5, 0
	s_cmp_eq_u32 s11, 2
	s_cbranch_scc0 .LBB2_29
.LBB2_32:                               ; %Flow279
	s_or_b32 exec_lo, exec_lo, s10
.LBB2_33:                               ; %.sink.split
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	s_or_b32 exec_lo, exec_lo, s8
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[4:5], null, v0, s9, v[1:2]
	v_mov_b32_e32 v5, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 3, v[4:5]
	v_add_co_u32 v0, vcc_lo, s0, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	global_store_b64 v[0:1], v[2:3], off
.LBB2_34:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z9ConvolutePdS_P11pixelCoordsPhjj
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 9
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_Z9ConvolutePdS_P11pixelCoordsPhjj, .Lfunc_end2-_Z9ConvolutePdS_P11pixelCoordsPhjj
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1224
; NumSgprs: 18
; NumVgprs: 9
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 9
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z3SADPjPdS0_P11pixelCoordsjjj ; -- Begin function _Z3SADPjPdS0_P11pixelCoordsjjj
	.globl	_Z3SADPjPdS0_P11pixelCoordsjjj
	.p2align	8
	.type	_Z3SADPjPdS0_P11pixelCoordsjjj,@function
_Z3SADPjPdS0_P11pixelCoordsjjj:         ; @_Z3SADPjPdS0_P11pixelCoordsjjj
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x3c
	s_load_b64 s[8:9], s[0:1], 0x20
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_u32_e64 s8, v1
	s_cbranch_execz .LBB3_5
; %bb.1:
	s_load_b256 s[0:7], s[0:1], 0x0
	v_mov_b32_e32 v2, 0
	s_mov_b32 s8, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 3, v[1:2]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v0, vcc_lo, s6, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
	global_load_b64 v[0:1], v[0:1], off
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[3:4], null, v0, s9, v[1:2]
	v_mov_b32_e32 v4, v2
	v_lshlrev_b64 v[0:1], 3, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s2, v0
	v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
	v_add_co_u32 v0, vcc_lo, s4, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
	s_mov_b32 s2, 0
	global_load_b64 v[2:3], v[2:3], off
	global_load_b64 v[0:1], v[0:1], off
	s_waitcnt vmcnt(0)
	v_add_f64 v[0:1], v[2:3], -v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[0:1], v[0:1], 0.5
	v_cvt_i32_f64_e32 v0, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v1, 0, v0
	v_max_i32_e32 v0, v0, v1
.LBB3_2:                                ; %ComputeLoop
                                        ; =>This Inner Loop Header: Depth=1
	s_ctz_i32_b32 s3, s8
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_readlane_b32 s4, v0, s3
	s_lshl_b32 s3, 1, s3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_and_not1_b32 s8, s8, s3
	s_add_i32 s2, s2, s4
	s_cmp_lg_u32 s8, 0
	s_cbranch_scc1 .LBB3_2
; %bb.3:                                ; %ComputeEnd
	v_mbcnt_lo_u32_b32 v0, exec_lo, 0
	s_mov_b32 s3, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v0
	s_xor_b32 s3, exec_lo, s3
	s_cbranch_execz .LBB3_5
; %bb.4:
	v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
	global_atomic_add_u32 v0, v1, s[0:1]
.LBB3_5:                                ; %Flow42
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z3SADPjPdS0_P11pixelCoordsjjj
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 304
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 5
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end3:
	.size	_Z3SADPjPdS0_P11pixelCoordsjjj, .Lfunc_end3-_Z3SADPjPdS0_P11pixelCoordsjjj
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 324
; NumSgprs: 18
; NumVgprs: 5
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 5
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z8BWKernelPhS_Pdj      ; -- Begin function _Z8BWKernelPhS_Pdj
	.globl	_Z8BWKernelPhS_Pdj
	.p2align	8
	.type	_Z8BWKernelPhS_Pdj,@function
_Z8BWKernelPhS_Pdj:                     ; @_Z8BWKernelPhS_Pdj
; %bb.0:
	s_load_b32 s2, s[0:1], 0x2c
	s_waitcnt lgkmcnt(0)
	s_and_b32 s4, s2, 0xffff
	s_load_b32 s2, s[0:1], 0x18
	v_cvt_f32_u32_e32 v1, s4
	s_sub_i32 s5, 0, s4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v1, v1
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v1, 0x4f7ffffe, v1
	s_waitcnt lgkmcnt(0)
	s_add_i32 s6, s2, s4
	v_cvt_u32_f32_e32 v1, v1
	s_add_i32 s6, s6, -1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s3, v1
	s_mul_i32 s5, s5, s3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_hi_u32 s5, s3, s5
	s_add_i32 s3, s3, s5
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_hi_u32 s3, s6, s3
	s_mul_i32 s5, s3, s4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_sub_i32 s5, s6, s5
	s_add_i32 s6, s3, 1
	s_sub_i32 s7, s5, s4
	s_cmp_ge_u32 s5, s4
	s_cselect_b32 s3, s6, s3
	s_cselect_b32 s5, s7, s5
	s_add_i32 s6, s3, 1
	s_cmp_ge_u32 s5, s4
	s_cselect_b32 s5, s6, s3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cvt_f32_u32_e32 v1, s5
	s_sub_i32 s6, 0, s5
	v_rcp_iflag_f32_e32 v1, v1
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v1, 0x4f7ffffe, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v1, v1
	v_readfirstlane_b32 s3, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s6, s6, s3
	s_mul_hi_u32 s6, s3, s6
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s3, s3, s6
	s_mul_hi_u32 s3, s15, s3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_mul_i32 s6, s3, s5
	s_add_i32 s7, s3, 1
	s_sub_i32 s6, s15, s6
	s_sub_i32 s8, s6, s5
	s_cmp_ge_u32 s6, s5
	s_cselect_b32 s3, s7, s3
	s_cselect_b32 s6, s8, s6
	s_add_i32 s7, s3, 1
	s_cmp_ge_u32 s6, s5
	s_cselect_b32 s3, s7, s3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s5, s3, s5
	s_sub_i32 s5, s15, s5
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s5, s4, v[0:1]
	s_mov_b32 s4, exec_lo
	v_cmpx_gt_u32_e64 s2, v1
	s_cbranch_execz .LBB4_2
; %bb.1:
	s_mul_i32 s8, s2, 3
	s_load_b128 s[4:7], s[0:1], 0x0
	s_add_i32 s8, s8, 3
	s_load_b64 s[0:1], s[0:1], 0x10
	s_and_b32 s8, s8, -4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s8, s3, s8
	v_mad_u64_u32 v[2:3], null, v1, 3, s[8:9]
	s_delay_alu instid0(VALU_DEP_1)
	v_add_nc_u32_e32 v0, 1, v2
	v_add_nc_u32_e32 v3, 2, v2
	s_waitcnt lgkmcnt(0)
	s_clause 0x2
	global_load_u8 v0, v0, s[6:7]
	global_load_u8 v4, v3, s[6:7]
	global_load_u8 v6, v2, s[6:7]
	s_waitcnt vmcnt(2)
	v_cvt_f64_u32_e32 v[2:3], v0
	s_waitcnt vmcnt(1)
	v_cvt_f64_u32_e32 v[4:5], v4
	s_waitcnt vmcnt(0)
	v_cvt_f64_u32_e32 v[6:7], v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[2:3], v[2:3], v[4:5]
	v_add_f64 v[2:3], v[2:3], v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f64 v[4:5], null, 0x40080000, 0x40080000, v[2:3]
	v_div_scale_f64 v[10:11], vcc_lo, v[2:3], 0x40080000, v[2:3]
	v_rcp_f64_e32 v[6:7], v[4:5]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
	v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
	v_mul_f64 v[8:9], v[10:11], v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[4:5], -v[4:5], v[8:9], v[10:11]
	v_div_fmas_f64 v[4:5], v[4:5], v[6:7], v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f64 v[2:3], v[4:5], 0x40080000, v[2:3]
	v_cvt_i32_f64_e32 v6, v[2:3]
	v_mad_u64_u32 v[4:5], null, s3, s2, v[1:2]
	v_mov_b32_e32 v5, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 3, v[4:5]
	v_add_co_u32 v0, vcc_lo, s0, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	global_store_b8 v4, v6, s[4:5]
	global_store_b64 v[0:1], v[2:3], off
.LBB4_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z8BWKernelPhS_Pdj
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 12
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end4:
	.size	_Z8BWKernelPhS_Pdj, .Lfunc_end4-_Z8BWKernelPhS_Pdj
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 620
; NumSgprs: 18
; NumVgprs: 12
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 12
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z9RGBKernelPhPdj       ; -- Begin function _Z9RGBKernelPhPdj
	.globl	_Z9RGBKernelPhPdj
	.p2align	8
	.type	_Z9RGBKernelPhPdj,@function
_Z9RGBKernelPhPdj:                      ; @_Z9RGBKernelPhPdj
; %bb.0:
	s_load_b32 s2, s[0:1], 0x24
	s_waitcnt lgkmcnt(0)
	s_and_b32 s4, s2, 0xffff
	s_load_b32 s2, s[0:1], 0x10
	v_cvt_f32_u32_e32 v1, s4
	s_sub_i32 s5, 0, s4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v1, v1
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v1, 0x4f7ffffe, v1
	s_waitcnt lgkmcnt(0)
	s_add_i32 s6, s2, s4
	v_cvt_u32_f32_e32 v1, v1
	s_add_i32 s6, s6, -1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s3, v1
	s_mul_i32 s5, s5, s3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_hi_u32 s5, s3, s5
	s_add_i32 s3, s3, s5
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_hi_u32 s3, s6, s3
	s_mul_i32 s5, s3, s4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_sub_i32 s5, s6, s5
	s_add_i32 s6, s3, 1
	s_sub_i32 s7, s5, s4
	s_cmp_ge_u32 s5, s4
	s_cselect_b32 s3, s6, s3
	s_cselect_b32 s5, s7, s5
	s_add_i32 s6, s3, 1
	s_cmp_ge_u32 s5, s4
	s_cselect_b32 s5, s6, s3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cvt_f32_u32_e32 v1, s5
	s_sub_i32 s6, 0, s5
	v_rcp_iflag_f32_e32 v1, v1
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v1, 0x4f7ffffe, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v1, v1
	v_readfirstlane_b32 s3, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s6, s6, s3
	s_mul_hi_u32 s6, s3, s6
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s3, s3, s6
	s_mul_hi_u32 s3, s15, s3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_mul_i32 s6, s3, s5
	s_add_i32 s7, s3, 1
	s_sub_i32 s6, s15, s6
	s_sub_i32 s8, s6, s5
	s_cmp_ge_u32 s6, s5
	s_cselect_b32 s3, s7, s3
	s_cselect_b32 s6, s8, s6
	s_add_i32 s7, s3, 1
	s_cmp_ge_u32 s6, s5
	s_cselect_b32 s3, s7, s3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s5, s3, s5
	s_sub_i32 s5, s15, s5
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s5, s4, v[0:1]
	s_mov_b32 s4, exec_lo
	v_cmpx_gt_u32_e64 s2, v1
	s_cbranch_execz .LBB5_2
; %bb.1:
	s_load_b128 s[4:7], s[0:1], 0x0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[2:3], null, s3, s2, v[1:2]
	v_mov_b32_e32 v3, 0
	s_mul_i32 s0, s2, 3
	s_add_i32 s0, s0, 3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_and_b32 s0, s0, -4
	v_lshlrev_b64 v[2:3], 3, v[2:3]
	s_mul_i32 s0, s3, s0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s6, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
	global_load_b64 v[2:3], v[2:3], off
	s_waitcnt vmcnt(0)
	v_cvt_i32_f64_e32 v0, v[2:3]
	v_mad_u64_u32 v[2:3], null, v1, 3, s[0:1]
	s_delay_alu instid0(VALU_DEP_1)
	v_add_nc_u32_e32 v1, 1, v2
	v_add_nc_u32_e32 v3, 2, v2
	s_clause 0x2
	global_store_b8 v2, v0, s[4:5]
	global_store_b8 v1, v0, s[4:5]
	global_store_b8 v3, v0, s[4:5]
.LBB5_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z9RGBKernelPhPdj
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 4
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end5:
	.size	_Z9RGBKernelPhPdj, .Lfunc_end5-_Z9RGBKernelPhPdj
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 444
; NumSgprs: 18
; NumVgprs: 4
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 4
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z12NoisyPixCopyPdS_P11pixelCoordsjj ; -- Begin function _Z12NoisyPixCopyPdS_P11pixelCoordsjj
	.globl	_Z12NoisyPixCopyPdS_P11pixelCoordsjj
	.p2align	8
	.type	_Z12NoisyPixCopyPdS_P11pixelCoordsjj,@function
_Z12NoisyPixCopyPdS_P11pixelCoordsjj:   ; @_Z12NoisyPixCopyPdS_P11pixelCoordsjj
; %bb.0:
	s_clause 0x1
	s_load_b32 s4, s[0:1], 0x2c
	s_load_b64 s[2:3], s[0:1], 0x18
	s_waitcnt lgkmcnt(0)
	s_and_b32 s4, s4, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
	v_cmp_gt_u32_e32 vcc_lo, s2, v1
	s_and_saveexec_b32 s2, vcc_lo
	s_cbranch_execz .LBB6_2
; %bb.1:
	s_load_b64 s[4:5], s[0:1], 0x10
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 3, v[1:2]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v0, vcc_lo, s4, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
	s_load_b128 s[4:7], s[0:1], 0x0
	global_load_b64 v[0:1], v[0:1], off
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[3:4], null, v0, s3, v[1:2]
	v_mov_b32_e32 v4, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 3, v[3:4]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v2, vcc_lo, s6, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
	v_add_co_u32 v0, vcc_lo, s4, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
	global_load_b64 v[2:3], v[2:3], off
	s_waitcnt vmcnt(0)
	global_store_b64 v[0:1], v[2:3], off
.LBB6_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z12NoisyPixCopyPdS_P11pixelCoordsjj
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 5
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end6:
	.size	_Z12NoisyPixCopyPdS_P11pixelCoordsjj, .Lfunc_end6-_Z12NoisyPixCopyPdS_P11pixelCoordsjj
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 208
; NumSgprs: 18
; NumVgprs: 5
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 5
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z7PixCopyPdS_j         ; -- Begin function _Z7PixCopyPdS_j
	.globl	_Z7PixCopyPdS_j
	.p2align	8
	.type	_Z7PixCopyPdS_j,@function
_Z7PixCopyPdS_j:                        ; @_Z7PixCopyPdS_j
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x24
	s_load_b32 s3, s[0:1], 0x10
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_cmpx_ge_u32_e64 s3, v1
	s_cbranch_execz .LBB7_2
; %bb.1:
	s_load_b128 s[0:3], s[0:1], 0x0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 3, v[1:2]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v2, vcc_lo, s2, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
	v_add_co_u32 v0, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	global_load_b64 v[2:3], v[2:3], off
	s_waitcnt vmcnt(0)
	global_store_b64 v[0:1], v[2:3], off
.LBB7_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7PixCopyPdS_j
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 4
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end7:
	.size	_Z7PixCopyPdS_j, .Lfunc_end7-_Z7PixCopyPdS_j
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 148
; NumSgprs: 18
; NumVgprs: 4
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 4
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
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	.type	mask0,@object
	.data
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	.p2align	4, 0x0
mask0:
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	.protected	mask1                   ; @mask1
	.type	mask1,@object
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mask1:
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	.type	mask2,@object
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mask2:
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	.protected	mask3                   ; @mask3
	.type	mask3,@object
	.globl	mask3
	.p2align	4, 0x0
mask3:
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	.protected	mask4                   ; @mask4
	.type	mask4,@object
	.globl	mask4
	.p2align	4, 0x0
mask4:
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	.size	mask4, 392

	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym mask0
	.addrsig_sym mask1
	.addrsig_sym mask2
	.addrsig_sym mask3
	.addrsig_sym mask4
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
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        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
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        .size:           8
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        .size:           8
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        .value_kind:     hidden_block_count_z
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        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 312
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z15findNoisyPixelsP11pixelCoordsPhS1_PjS2_S2_jj
    .private_segment_fixed_size: 0
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    .sgpr_spill_count: 0
    .symbol:         _Z15findNoisyPixelsP11pixelCoordsPhS1_PjS2_S2_jj.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
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    .vgpr_spill_count: 0
    .wavefront_size: 32
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    .language:       OpenCL C
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    .kernarg_segment_size: 296
    .language:       OpenCL C
    .language_version:
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      - 0
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    .name:           _Z9ConvolutePdS_P11pixelCoordsPhjj
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    .sgpr_spill_count: 0
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...

	.end_amdgpu_metadata
