#include <stdio.h>
#include "cuda.h"
#define max(x,y)  ((x) > (y)? (x) : (y))
#define min(x,y)  ((x) < (y)? (x) : (y))
#define ceil(a,b) ((a) % (b) == 0 ? (a) / (b) : ((a) / (b)) + 1)

void check_error (const char* message) {
	cudaError_t error = cudaGetLastError ();
	if (error != cudaSuccess) {
		printf ("CUDA error : %s, %s\n", message, cudaGetErrorString (error));
		exit(-1);
	}
}

__global__ void j3d125pt (double * __restrict__ t_in, double * __restrict__ t_out, int N) {
	//Determing the block's indices
	int i0 = (int)(blockIdx.x)*(int)(blockDim.x) + 2;
	int i = max(i0,2) + (int)(threadIdx.x);
	int j0 = 4*(int)(blockIdx.y)*(int)(blockDim.y) + 2;
	int j = max(j0,2) + 4*(int)(threadIdx.y);
	int k0 = (int)(blockIdx.z)*(int)(blockDim.z) + 2;
	int k = max(k0,2) + (int)(threadIdx.z);

	double (*in)[516][516] = (double (*)[516][516])t_in;
	double (*out)[516][516] = (double (*)[516][516])t_out;
	if (i>=2 && i<=N-3 && j>=2 && j<=N-3 && k>=2 && k<=N-3) {
double _t_3_ = in[k][j-2][i-2];
_t_3_ += in[k][j-2][i+2];
_t_3_ += in[k-1][j-1][i];
double _t_11_ = in[k-1][j-1][i];
_t_3_ += in[k-1][j][i-1];
double _t_7_ = in[k-1][j][i-1];
double _t_19_ = in[k-1][j][i-1];
_t_3_ += in[k-1][j][i+1];
_t_7_ += in[k-1][j][i+1];
_t_19_ += in[k-1][j][i+1];
_t_3_ += in[k-1][j+1][i];
double _t_12_ = in[k-1][j+1][i];
double _t_17_ = in[k-1][j+1][i];
double _t_25_ = in[k-1][j+1][i];
_t_3_ += in[k][j+2][i-2];
_t_11_ += in[k][j+2][i-2];
double _t_16_ = in[k][j+2][i-2];
_t_25_ += in[k][j+2][i-2];
_t_3_ += in[k][j+2][i+2];
_t_11_ += in[k][j+2][i+2];
_t_16_ += in[k][j+2][i+2];
_t_25_ += in[k][j+2][i+2];
_t_3_ += in[k+1][j-1][i];
_t_11_ += in[k+1][j-1][i];
_t_3_ += in[k+1][j][i-1];
_t_7_ += in[k+1][j][i-1];
_t_19_ += in[k+1][j][i-1];
_t_3_ += in[k+1][j][i+1];
_t_7_ += in[k+1][j][i+1];
_t_19_ += in[k+1][j][i+1];
_t_3_ += in[k+1][j+1][i];
_t_12_ += in[k+1][j+1][i];
_t_17_ += in[k+1][j+1][i];
_t_25_ += in[k+1][j+1][i];
_t_3_ += in[k-2][j][i-2];
double _t_9_ = in[k-2][j][i-2];
_t_9_ += in[k-2][j][i-2];
double _t_14_ = in[k-2][j][i-2];
double _t_15_ = in[k-2][j][i-2];
_t_3_ += in[k-2][j-2][i];
_t_3_ += in[k-2][j+2][i];
_t_11_ += in[k-2][j+2][i];
_t_11_ += in[k-2][j+2][i];
_t_16_ += in[k-2][j+2][i];
_t_16_ += in[k-2][j+2][i];
_t_25_ += in[k-2][j+2][i];
_t_25_ += in[k-2][j+2][i];
_t_3_ += in[k-2][j][i-2];
_t_3_ += in[k-2][j][i+2];
_t_9_ += in[k-2][j][i+2];
_t_9_ += in[k-2][j][i+2];
_t_14_ += in[k-2][j][i+2];
_t_15_ += in[k-2][j][i+2];
_t_3_ += in[k-2][j+2][i];
double outkc0jc0ic0 = 0.217 * _t_3_;
double _t_2_ = in[k-1][j-2][i-2];
_t_2_ += in[k-1][j-2][i+2];
_t_2_ += in[k][j-2][i];
_t_2_ += in[k+1][j-2][i-2];
_t_2_ += in[k+1][j-2][i+2];
_t_2_ += in[k-1][j+2][i-2];
_t_12_ += in[k-1][j+2][i-2];
double _t_18_ = in[k-1][j+2][i-2];
double _t_26_ = in[k-1][j+2][i-2];
_t_2_ += in[k-1][j+2][i+2];
_t_12_ += in[k-1][j+2][i+2];
_t_18_ += in[k-1][j+2][i+2];
_t_26_ += in[k-1][j+2][i+2];
_t_2_ += in[k][j][i-2];
_t_11_ += in[k][j][i-2];
_t_17_ += in[k][j][i-2];
_t_2_ += in[k][j][i+2];
_t_11_ += in[k][j][i+2];
_t_17_ += in[k][j][i+2];
_t_2_ += in[k][j+2][i];
_t_7_ += in[k][j+2][i];
_t_18_ += in[k][j+2][i];
double _t_21_ = in[k][j+2][i];
_t_2_ += in[k+1][j+2][i-2];
_t_12_ += in[k+1][j+2][i-2];
_t_18_ += in[k+1][j+2][i-2];
_t_26_ += in[k+1][j+2][i-2];
_t_2_ += in[k+1][j+2][i+2];
_t_12_ += in[k+1][j+2][i+2];
_t_18_ += in[k+1][j+2][i+2];
_t_26_ += in[k+1][j+2][i+2];
_t_2_ += in[k-2][j][i];
_t_11_ += in[k-2][j][i];
_t_11_ += in[k-2][j][i];
_t_17_ += in[k-2][j][i];
_t_17_ += in[k-2][j][i];
_t_2_ += in[k-2][j-1][i+2];
_t_7_ += in[k-2][j-1][i+2];
double _t_8_ = in[k-2][j-1][i+2];
_t_2_ += in[k-2][j+2][i+1];
_t_12_ += in[k-2][j+2][i+1];
double _t_13_ = in[k-2][j+2][i+1];
_t_18_ += in[k-2][j+2][i+1];
_t_18_ += in[k-2][j+2][i+1];
_t_26_ += in[k-2][j+2][i+1];
double _t_27_ = in[k-2][j+2][i+1];
_t_2_ += in[k-2][j+2][i-1];
_t_12_ += in[k-2][j+2][i-1];
_t_13_ += in[k-2][j+2][i-1];
_t_18_ += in[k-2][j+2][i-1];
_t_18_ += in[k-2][j+2][i-1];
_t_26_ += in[k-2][j+2][i-1];
_t_27_ += in[k-2][j+2][i-1];
_t_2_ += in[k-2][j-1][i+2];
_t_2_ += in[k-2][j+1][i+2];
double _t_10_ = in[k-2][j+1][i+2];
_t_10_ += in[k-2][j+1][i+2];
_t_16_ += in[k-2][j+1][i+2];
_t_16_ += in[k-2][j+1][i+2];
_t_21_ += in[k-2][j+1][i+2];
double _t_22_ = in[k-2][j+1][i+2];
_t_2_ += in[k-2][j+1][i+2];
_t_2_ += in[k-2][j][i];
_t_2_ += in[k-2][j+1][i-2];
_t_10_ += in[k-2][j+1][i-2];
_t_10_ += in[k-2][j+1][i-2];
_t_16_ += in[k-2][j+1][i-2];
_t_16_ += in[k-2][j+1][i-2];
_t_21_ += in[k-2][j+1][i-2];
_t_22_ += in[k-2][j+1][i-2];
_t_2_ += in[k-2][j+2][i-1];
_t_2_ += in[k-2][j-1][i-2];
_t_7_ += in[k-2][j-1][i-2];
_t_8_ += in[k-2][j-1][i-2];
_t_2_ += in[k-2][j+1][i-2];
_t_2_ += in[k-2][j-1][i-2];
outkc0jc0ic0 += 1.132 * _t_2_;
double _t_4_ = in[k-1][j-2][i];
_t_4_ += in[k][j-2][i-1];
_t_4_ += in[k][j-2][i+1];
_t_4_ += in[k+1][j-2][i];
_t_4_ += in[k-1][j][i-2];
_t_12_ += in[k-1][j][i-2];
_t_16_ += in[k-1][j][i-2];
_t_4_ += in[k-1][j][i+2];
_t_12_ += in[k-1][j][i+2];
_t_16_ += in[k-1][j][i+2];
_t_4_ += in[k-1][j+2][i];
_t_10_ += in[k-1][j+2][i];
_t_19_ += in[k-1][j+2][i];
double _t_24_ = in[k-1][j+2][i];
_t_4_ += in[k][j-1][i-2];
_t_10_ += in[k][j-1][i-2];
_t_4_ += in[k][j-1][i+2];
_t_10_ += in[k][j-1][i+2];
_t_4_ += in[k][j][i];
_t_7_ += in[k][j][i];
_t_16_ += in[k][j][i];
_t_4_ += in[k][j+1][i-2];
_t_9_ += in[k][j+1][i-2];
_t_18_ += in[k][j+1][i-2];
_t_24_ += in[k][j+1][i-2];
_t_4_ += in[k][j+1][i+2];
_t_9_ += in[k][j+1][i+2];
_t_18_ += in[k][j+1][i+2];
_t_24_ += in[k][j+1][i+2];
_t_4_ += in[k][j+2][i-1];
_t_12_ += in[k][j+2][i-1];
_t_14_ += in[k][j+2][i-1];
_t_26_ += in[k][j+2][i-1];
_t_4_ += in[k][j+2][i+1];
_t_12_ += in[k][j+2][i+1];
_t_14_ += in[k][j+2][i+1];
_t_26_ += in[k][j+2][i+1];
_t_4_ += in[k+1][j][i-2];
_t_12_ += in[k+1][j][i-2];
_t_16_ += in[k+1][j][i-2];
_t_4_ += in[k+1][j][i+2];
_t_12_ += in[k+1][j][i+2];
_t_16_ += in[k+1][j][i+2];
_t_4_ += in[k+1][j+2][i];
_t_10_ += in[k+1][j+2][i];
_t_19_ += in[k+1][j+2][i];
_t_24_ += in[k+1][j+2][i];
_t_4_ += in[k-2][j-1][i];
_t_10_ += in[k-2][j-1][i];
_t_10_ += in[k-2][j-1][i];
_t_4_ += in[k-2][j][i-1];
_t_12_ += in[k-2][j][i-1];
_t_13_ += in[k-2][j][i-1];
_t_16_ += in[k-2][j][i-1];
_t_16_ += in[k-2][j][i-1];
_t_4_ += in[k-2][j][i+1];
_t_12_ += in[k-2][j][i+1];
_t_13_ += in[k-2][j][i+1];
_t_16_ += in[k-2][j][i+1];
_t_16_ += in[k-2][j][i+1];
_t_4_ += in[k-2][j+1][i];
_t_9_ += in[k-2][j+1][i];
_t_9_ += in[k-2][j+1][i];
_t_18_ += in[k-2][j+1][i];
_t_18_ += in[k-2][j+1][i];
_t_24_ += in[k-2][j+1][i];
_t_24_ += in[k-2][j+1][i];
_t_4_ += in[k-2][j-1][i];
_t_4_ += in[k-2][j][i-1];
_t_4_ += in[k-2][j][i+1];
_t_4_ += in[k-2][j+1][i];
outkc0jc0ic0 += 2.13 * _t_4_;
double _t_0_ = in[k-2][j-2][i-2];
_t_0_ += in[k-2][j-2][i+2];
double _t_1_ = in[k-2][j-2][i-2];
_t_1_ += in[k-2][j-2][i+2];
_t_0_ += in[k-2][j+2][i-2];
_t_9_ += in[k-2][j+2][i-2];
_t_9_ += in[k-2][j+2][i-2];
_t_17_ += in[k-2][j+2][i-2];
_t_17_ += in[k-2][j+2][i-2];
double _t_23_ = in[k-2][j+2][i-2];
_t_23_ += in[k-2][j+2][i-2];
_t_0_ += in[k-2][j+2][i+2];
_t_9_ += in[k-2][j+2][i+2];
_t_9_ += in[k-2][j+2][i+2];
_t_17_ += in[k-2][j+2][i+2];
_t_17_ += in[k-2][j+2][i+2];
_t_23_ += in[k-2][j+2][i+2];
_t_23_ += in[k-2][j+2][i+2];
_t_0_ += in[k-1][j-1][i-1];
_t_12_ += in[k-1][j-1][i-1];
_t_0_ += in[k-1][j-1][i+1];
_t_12_ += in[k-1][j-1][i+1];
_t_0_ += in[k-1][j+1][i-1];
_t_10_ += in[k-1][j+1][i-1];
_t_14_ += in[k-1][j+1][i-1];
_t_26_ += in[k-1][j+1][i-1];
_t_0_ += in[k-1][j+1][i+1];
_t_10_ += in[k-1][j+1][i+1];
_t_14_ += in[k-1][j+1][i+1];
_t_26_ += in[k-1][j+1][i+1];
_t_0_ += in[k][j-1][i];
_t_9_ += in[k][j-1][i];
_t_0_ += in[k][j][i-1];
_t_12_ += in[k][j][i-1];
_t_18_ += in[k][j][i-1];
_t_0_ += in[k][j][i+1];
_t_12_ += in[k][j][i+1];
_t_18_ += in[k][j][i+1];
_t_0_ += in[k][j+1][i];
_t_11_ += in[k][j+1][i];
_t_14_ += in[k][j+1][i];
_t_23_ += in[k][j+1][i];
_t_0_ += in[k+1][j-1][i-1];
_t_12_ += in[k+1][j-1][i-1];
_t_0_ += in[k+1][j-1][i+1];
_t_12_ += in[k+1][j-1][i+1];
_t_0_ += in[k+1][j+1][i-1];
_t_10_ += in[k+1][j+1][i-1];
_t_14_ += in[k+1][j+1][i-1];
_t_26_ += in[k+1][j+1][i-1];
_t_0_ += in[k+1][j+1][i+1];
_t_10_ += in[k+1][j+1][i+1];
_t_14_ += in[k+1][j+1][i+1];
_t_26_ += in[k+1][j+1][i+1];
outkc0jc0ic0 += 0.75 * _t_0_;
_t_1_ += in[k-2][j+2][i-2];
_t_1_ += in[k-2][j+2][i+2];
outkc0jc0ic0 += 0.76 * _t_1_;
double _t_5_ = in[k-1][j-2][i-1];
_t_5_ += in[k-1][j-2][i+1];
_t_5_ += in[k+1][j-2][i-1];
_t_5_ += in[k+1][j-2][i+1];
_t_5_ += in[k-2][j-1][i-1];
_t_9_ += in[k-2][j-1][i-1];
_t_9_ += in[k-2][j-1][i-1];
_t_5_ += in[k-2][j-1][i+1];
_t_9_ += in[k-2][j-1][i+1];
_t_9_ += in[k-2][j-1][i+1];
_t_5_ += in[k-2][j+1][i-1];
_t_11_ += in[k-2][j+1][i-1];
_t_11_ += in[k-2][j+1][i-1];
_t_19_ += in[k-2][j+1][i-1];
double _t_20_ = in[k-2][j+1][i-1];
_t_23_ += in[k-2][j+1][i-1];
_t_23_ += in[k-2][j+1][i-1];
_t_5_ += in[k-2][j+1][i+1];
_t_11_ += in[k-2][j+1][i+1];
_t_11_ += in[k-2][j+1][i+1];
_t_19_ += in[k-2][j+1][i+1];
_t_20_ += in[k-2][j+1][i+1];
_t_23_ += in[k-2][j+1][i+1];
_t_23_ += in[k-2][j+1][i+1];
_t_5_ += in[k-1][j-1][i-2];
_t_9_ += in[k-1][j-1][i-2];
_t_5_ += in[k-1][j-1][i+2];
_t_9_ += in[k-1][j-1][i+2];
_t_5_ += in[k-1][j][i];
_t_10_ += in[k-1][j][i];
_t_18_ += in[k-1][j][i];
_t_5_ += in[k-1][j+1][i-2];
_t_11_ += in[k-1][j+1][i-2];
_t_19_ += in[k-1][j+1][i-2];
_t_23_ += in[k-1][j+1][i-2];
_t_5_ += in[k-1][j+1][i+2];
_t_11_ += in[k-1][j+1][i+2];
_t_19_ += in[k-1][j+1][i+2];
_t_23_ += in[k-1][j+1][i+2];
_t_5_ += in[k-1][j+2][i-1];
_t_7_ += in[k-1][j+2][i-1];
_t_17_ += in[k-1][j+2][i-1];
_t_21_ += in[k-1][j+2][i-1];
_t_5_ += in[k-1][j+2][i+1];
_t_7_ += in[k-1][j+2][i+1];
_t_17_ += in[k-1][j+2][i+1];
_t_21_ += in[k-1][j+2][i+1];
_t_5_ += in[k][j-1][i-1];
_t_11_ += in[k][j-1][i-1];
_t_5_ += in[k][j-1][i+1];
_t_11_ += in[k][j-1][i+1];
_t_5_ += in[k][j+1][i-1];
_t_7_ += in[k][j+1][i-1];
_t_19_ += in[k][j+1][i-1];
_t_25_ += in[k][j+1][i-1];
_t_5_ += in[k][j+1][i+1];
_t_7_ += in[k][j+1][i+1];
_t_19_ += in[k][j+1][i+1];
_t_25_ += in[k][j+1][i+1];
_t_5_ += in[k+1][j-1][i-2];
_t_9_ += in[k+1][j-1][i-2];
_t_5_ += in[k+1][j-1][i+2];
_t_9_ += in[k+1][j-1][i+2];
_t_5_ += in[k+1][j][i];
_t_10_ += in[k+1][j][i];
_t_18_ += in[k+1][j][i];
_t_5_ += in[k+1][j+1][i-2];
_t_11_ += in[k+1][j+1][i-2];
_t_19_ += in[k+1][j+1][i-2];
_t_23_ += in[k+1][j+1][i-2];
_t_5_ += in[k+1][j+1][i+2];
_t_11_ += in[k+1][j+1][i+2];
_t_19_ += in[k+1][j+1][i+2];
_t_23_ += in[k+1][j+1][i+2];
_t_5_ += in[k+1][j+2][i-1];
_t_7_ += in[k+1][j+2][i-1];
_t_17_ += in[k+1][j+2][i-1];
_t_21_ += in[k+1][j+2][i-1];
_t_5_ += in[k+1][j+2][i+1];
_t_7_ += in[k+1][j+2][i+1];
_t_17_ += in[k+1][j+2][i+1];
_t_21_ += in[k+1][j+2][i+1];
outkc0jc0ic0 += 0.331 * _t_5_;
double _t_6_ = in[k-2][j-1][i-1];
_t_6_ += in[k-2][j-1][i+1];
_t_6_ += in[k-2][j+1][i-1];
_t_6_ += in[k-2][j+1][i+1];
outkc0jc0ic0 += 0.332 * _t_6_;

_t_7_ += in[k-2][j+3][i-2];
_t_16_ += in[k-2][j+3][i-2];
_t_16_ += in[k-2][j+3][i-2];
_t_24_ += in[k-2][j+3][i-2];
_t_24_ += in[k-2][j+3][i-2];
_t_7_ += in[k-2][j+3][i+2];
_t_16_ += in[k-2][j+3][i+2];
_t_16_ += in[k-2][j+3][i+2];
_t_24_ += in[k-2][j+3][i+2];
_t_24_ += in[k-2][j+3][i+2];
double outkc0jp1ic0 = 0.75 * _t_7_;
_t_8_ += in[k-2][j+3][i-2];
_t_8_ += in[k-2][j+3][i+2];
outkc0jp1ic0 += 0.76 * _t_8_;
_t_9_ += in[k-2][j+3][i-1];
_t_19_ += in[k-2][j+3][i-1];
_t_25_ += in[k-2][j+3][i-1];
_t_25_ += in[k-2][j+3][i-1];
_t_9_ += in[k-2][j+3][i+1];
_t_19_ += in[k-2][j+3][i+1];
_t_25_ += in[k-2][j+3][i+1];
_t_25_ += in[k-2][j+3][i+1];
_t_9_ += in[k-2][j+3][i-1];
_t_9_ += in[k-2][j+3][i+1];
_t_9_ += in[k-1][j+3][i-2];
_t_19_ += in[k-1][j+3][i-2];
_t_25_ += in[k-1][j+3][i-2];
_t_9_ += in[k-1][j+3][i+2];
_t_19_ += in[k-1][j+3][i+2];
_t_25_ += in[k-1][j+3][i+2];
_t_9_ += in[k][j+3][i];
_t_14_ += in[k][j+3][i];
_t_25_ += in[k][j+3][i];
_t_9_ += in[k+1][j+3][i-2];
_t_19_ += in[k+1][j+3][i-2];
_t_25_ += in[k+1][j+3][i-2];
_t_9_ += in[k+1][j+3][i+2];
_t_19_ += in[k+1][j+3][i+2];
_t_25_ += in[k+1][j+3][i+2];
outkc0jp1ic0 += 1.132 * _t_9_;
_t_20_ += in[k-2][j+3][i-1];
_t_20_ += in[k-2][j+3][i+1];
double outkc0jp2ic0 = 0.332 * _t_20_;
_t_10_ += in[k-2][j+3][i];
_t_18_ += in[k-2][j+3][i];
_t_18_ += in[k-2][j+3][i];
_t_23_ += in[k-2][j+3][i];
_t_23_ += in[k-2][j+3][i];
_t_10_ += in[k-2][j+3][i];
_t_10_ += in[k][j+3][i-2];
_t_18_ += in[k][j+3][i-2];
_t_23_ += in[k][j+3][i-2];
_t_10_ += in[k][j+3][i+2];
_t_18_ += in[k][j+3][i+2];
_t_23_ += in[k][j+3][i+2];
outkc0jp1ic0 += 0.217 * _t_10_;
_t_11_ += in[k-1][j+3][i];
_t_17_ += in[k-1][j+3][i];
_t_26_ += in[k-1][j+3][i];
_t_11_ += in[k][j+3][i-1];
_t_19_ += in[k][j+3][i-1];
_t_21_ += in[k][j+3][i-1];
_t_11_ += in[k][j+3][i+1];
_t_19_ += in[k][j+3][i+1];
_t_21_ += in[k][j+3][i+1];
_t_11_ += in[k+1][j+3][i];
_t_17_ += in[k+1][j+3][i];
_t_26_ += in[k+1][j+3][i];
outkc0jp1ic0 += 2.13 * _t_11_;
_t_12_ += in[k-1][j+3][i-1];
_t_14_ += in[k-1][j+3][i-1];
_t_24_ += in[k-1][j+3][i-1];
_t_12_ += in[k-1][j+3][i+1];
_t_14_ += in[k-1][j+3][i+1];
_t_24_ += in[k-1][j+3][i+1];
_t_12_ += in[k+1][j+3][i-1];
_t_14_ += in[k+1][j+3][i-1];
_t_24_ += in[k+1][j+3][i-1];
_t_12_ += in[k+1][j+3][i+1];
_t_14_ += in[k+1][j+3][i+1];
_t_24_ += in[k+1][j+3][i+1];
outkc0jp1ic0 += 0.331 * _t_12_;
outkc0jp1ic0 += 0.332 * _t_13_;

_t_14_ += in[k-2][j+4][i-2];
_t_23_ += in[k-2][j+4][i-2];
_t_23_ += in[k-2][j+4][i-2];
_t_14_ += in[k-2][j+4][i+2];
_t_23_ += in[k-2][j+4][i+2];
_t_23_ += in[k-2][j+4][i+2];
outkc0jp2ic0 += 0.75 * _t_14_;
_t_15_ += in[k-2][j+4][i-2];
_t_15_ += in[k-2][j+4][i+2];
outkc0jp2ic0 += 0.76 * _t_15_;
_t_16_ += in[k-2][j+4][i-1];
_t_16_ += in[k-2][j+4][i+1];
_t_16_ += in[k-2][j+4][i-1];
_t_16_ += in[k-2][j+4][i+1];
_t_16_ += in[k-1][j+4][i-2];
_t_16_ += in[k-1][j+4][i+2];
_t_16_ += in[k][j+4][i];
_t_21_ += in[k][j+4][i];
_t_16_ += in[k+1][j+4][i-2];
_t_16_ += in[k+1][j+4][i+2];
outkc0jp2ic0 += 1.132 * _t_16_;
_t_27_ += in[k-2][j+4][i-1];
_t_27_ += in[k-2][j+4][i+1];
double outkc0jp3ic0 = 0.332 * _t_27_;
_t_17_ += in[k-2][j+4][i];
_t_17_ += in[k-2][j+4][i];
_t_17_ += in[k][j+4][i-2];
_t_17_ += in[k][j+4][i+2];
outkc0jp2ic0 += 0.217 * _t_17_;
_t_25_ += in[k-2][j+4][i];
_t_25_ += in[k-2][j+4][i];
_t_25_ += in[k][j+4][i-2];
_t_25_ += in[k][j+4][i+2];
_t_25_ += in[k-1][j+5][i];
_t_25_ += in[k][j+5][i-1];
_t_25_ += in[k][j+5][i+1];
_t_25_ += in[k+1][j+5][i];
outkc0jp3ic0 += 2.13 * _t_25_;
_t_18_ += in[k-1][j+4][i];
_t_24_ += in[k-1][j+4][i];
_t_18_ += in[k][j+4][i-1];
_t_18_ += in[k][j+4][i+1];
_t_18_ += in[k+1][j+4][i];
_t_24_ += in[k+1][j+4][i];
outkc0jp2ic0 += 2.13 * _t_18_;
_t_19_ += in[k-1][j+4][i-1];
_t_21_ += in[k-1][j+4][i-1];
_t_19_ += in[k-1][j+4][i+1];
_t_21_ += in[k-1][j+4][i+1];
_t_19_ += in[k+1][j+4][i-1];
_t_21_ += in[k+1][j+4][i-1];
_t_19_ += in[k+1][j+4][i+1];
_t_21_ += in[k+1][j+4][i+1];
outkc0jp2ic0 += 0.331 * _t_19_;
_t_26_ += in[k-1][j+4][i-2];
_t_26_ += in[k-1][j+4][i+2];
_t_26_ += in[k][j+4][i-1];
_t_26_ += in[k][j+4][i+1];
_t_26_ += in[k+1][j+4][i-2];
_t_26_ += in[k+1][j+4][i+2];
_t_26_ += in[k-1][j+5][i-1];
_t_26_ += in[k-1][j+5][i+1];
_t_26_ += in[k+1][j+5][i-1];
_t_26_ += in[k+1][j+5][i+1];
_t_26_ += in[k-2][j+4][i-1];
_t_26_ += in[k-2][j+4][i+1];
outkc0jp3ic0 += 0.331 * _t_26_;

_t_21_ += in[k-2][j+5][i-2];
_t_21_ += in[k-2][j+5][i+2];
_t_22_ += in[k-2][j+5][i-2];
_t_22_ += in[k-2][j+5][i+2];
outkc0jp3ic0 += 0.75 * _t_21_;
outkc0jp3ic0 += 0.76 * _t_22_;
_t_23_ += in[k-2][j+5][i+1];
outkc0jp3ic0 += 1.132 * _t_23_;
_t_24_ += in[k-2][j+5][i];
outkc0jp3ic0 += 0.217 * _t_24_;

out[k][j][i] = outkc0jc0ic0;
out[k][j+1][i] = outkc0jp1ic0;
out[k][j+2][i] = outkc0jp2ic0;
out[k][j+3][i] = outkc0jp3ic0;
	}
}

extern "C" void host_code (double *h_in, double *h_out, int N) {
	double *in;
	cudaMalloc (&in, sizeof(double)*N*N*N);
	check_error ("Failed to allocate device memory for in\n");
	cudaMemcpy (in, h_in, sizeof(double)*N*N*N, cudaMemcpyHostToDevice);
	double *out;
	cudaMalloc (&out, sizeof(double)*N*N*N);
	check_error ("Failed to allocate device memory for out\n");

	dim3 blockconfig (16, 4, 4);
	dim3 gridconfig (ceil(N-4, blockconfig.x), ceil(N-4, 4*blockconfig.y), ceil(N-4, blockconfig.z));

	j3d125pt<<<gridconfig, blockconfig>>> (in, out, N);

	cudaMemcpy (h_out, out, sizeof(double)*N*N*N, cudaMemcpyDeviceToHost);

	cudaFree (in); 
	cudaFree (out);
}

	.file	"tmpxft_002d46a8_00000000-6_reordered-b.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2031:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"CUDA error : %s, %s\n"
	.text
	.globl	_Z11check_errorPKc
	.type	_Z11check_errorPKc, @function
_Z11check_errorPKc:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	movq	%rdi, %rbx
	call	cudaGetLastError@PLT
	testl	%eax, %eax
	je	.L2
	movl	%eax, %edi
	call	cudaGetErrorString@PLT
	movl	$2, %edi
	movq	%rbx, %rdx
	leaq	.LC0(%rip), %rsi
	movq	%rax, %rcx
	xorl	%eax, %eax
	call	__printf_chk@PLT
	orl	$-1, %edi
	call	exit@PLT
.L2:
	popq	%rbx
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2027:
	.size	_Z11check_errorPKc, .-_Z11check_errorPKc
	.globl	_Z30__device_stub__Z8j3d125ptPdS_iPdS_i
	.type	_Z30__device_stub__Z8j3d125ptPdS_iPdS_i, @function
_Z30__device_stub__Z8j3d125ptPdS_iPdS_i:
.LFB2053:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rcx
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	16(%rsp), %rax
	movq	%rdi, 16(%rsp)
	leaq	48(%rsp), %rdi
	movq	%rax, 96(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	12(%rsp), %rax
	movq	%rsi, 24(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movl	$1, 56(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L6
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z8j3d125ptPdS_i(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L6:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L8
	call	__stack_chk_fail@PLT
.L8:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2053:
	.size	_Z30__device_stub__Z8j3d125ptPdS_iPdS_i, .-_Z30__device_stub__Z8j3d125ptPdS_iPdS_i
	.globl	_Z8j3d125ptPdS_i
	.type	_Z8j3d125ptPdS_i, @function
_Z8j3d125ptPdS_i:
.LFB2054:
	.cfi_startproc
	endbr64
	jmp	_Z30__device_stub__Z8j3d125ptPdS_iPdS_i
	.cfi_endproc
.LFE2054:
	.size	_Z8j3d125ptPdS_i, .-_Z8j3d125ptPdS_i
	.section	.rodata.str1.1
.LC1:
	.string	"Failed to allocate device memory for in\n"
.LC2:
	.string	"Failed to allocate device memory for out\n"
	.text
	.globl	host_code
	.type	host_code, @function
host_code:
.LFB2028:
	.cfi_startproc
	endbr64
	pushq	%r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	movq	%rdi, %r13
	pushq	%r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	movq	%rsi, %r12
	pushq	%rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	movl	%edx, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	subq	$56, %rsp
	.cfi_def_cfa_offset 96
	movq	%fs:40, %rax
	movq	%rax, 40(%rsp)
	xorl	%eax, %eax
	movslq	%edx, %rax
	movq	%rsp, %rdi
	movq	%rax, %rbx
	imulq	%rax, %rbx
	imulq	%rax, %rbx
	salq	$3, %rbx
	movq	%rbx, %rsi
	call	cudaMalloc@PLT
	leaq	.LC1(%rip), %rdi
	call	_Z11check_errorPKc
	movq	(%rsp), %rdi
	movq	%rbx, %rdx
	movq	%r13, %rsi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	movq	%rbx, %rsi
	leaq	8(%rsp), %rdi
	call	cudaMalloc@PLT
	leaq	.LC2(%rip), %rdi
	call	_Z11check_errorPKc
	leal	-4(%rbp), %eax
	movl	%ebp, %edx
	movl	$4, %ecx
	movl	%eax, %esi
	andl	$3, %edx
	shrl	$2, %esi
	cmpl	$1, %edx
	movl	%eax, %edx
	sbbl	$-1, %esi
	andl	$15, %eax
	shrl	$4, %edx
	cmpl	$1, %eax
	sbbl	$-1, %edx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	%edx, 28(%rsp)
	movl	%edx, 32(%rsp)
	movl	$1073741825, %edx
	movq	28(%rsp), %rdi
	salq	$4, %rdx
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L14
	movq	8(%rsp), %rsi
	movq	(%rsp), %rdi
	movl	%ebp, %edx
	call	_Z30__device_stub__Z8j3d125ptPdS_iPdS_i
.L14:
	movq	8(%rsp), %rsi
	movl	$2, %ecx
	movq	%rbx, %rdx
	movq	%r12, %rdi
	call	cudaMemcpy@PLT
	movq	(%rsp), %rdi
	call	cudaFree@PLT
	movq	8(%rsp), %rdi
	call	cudaFree@PLT
	movq	40(%rsp), %rax
	subq	%fs:40, %rax
	je	.L15
	call	__stack_chk_fail@PLT
.L15:
	addq	$56, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2028:
	.size	host_code, .-host_code
	.section	.rodata.str1.1
.LC3:
	.string	"_Z8j3d125ptPdS_i"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2056:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC3(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z8j3d125ptPdS_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2056:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <stdio.h>
#include "hip/hip_runtime.h"
#define max(x,y)  ((x) > (y)? (x) : (y))
#define min(x,y)  ((x) < (y)? (x) : (y))
#define ceil(a,b) ((a) % (b) == 0 ? (a) / (b) : ((a) / (b)) + 1)

void check_error (const char* message) {
	hipError_t error = hipGetLastError ();
	if (error != hipSuccess) {
		printf ("CUDA error : %s, %s\n", message, hipGetErrorString (error));
		exit(-1);
	}
}

__global__ void j3d125pt (double * __restrict__ t_in, double * __restrict__ t_out, int N) {
	//Determing the block's indices
	int i0 = (int)(blockIdx.x)*(int)(blockDim.x) + 2;
	int i = max(i0,2) + (int)(threadIdx.x);
	int j0 = 4*(int)(blockIdx.y)*(int)(blockDim.y) + 2;
	int j = max(j0,2) + 4*(int)(threadIdx.y);
	int k0 = (int)(blockIdx.z)*(int)(blockDim.z) + 2;
	int k = max(k0,2) + (int)(threadIdx.z);

	double (*in)[516][516] = (double (*)[516][516])t_in;
	double (*out)[516][516] = (double (*)[516][516])t_out;
	if (i>=2 && i<=N-3 && j>=2 && j<=N-3 && k>=2 && k<=N-3) {
double _t_3_ = in[k][j-2][i-2];
_t_3_ += in[k][j-2][i+2];
_t_3_ += in[k-1][j-1][i];
double _t_11_ = in[k-1][j-1][i];
_t_3_ += in[k-1][j][i-1];
double _t_7_ = in[k-1][j][i-1];
double _t_19_ = in[k-1][j][i-1];
_t_3_ += in[k-1][j][i+1];
_t_7_ += in[k-1][j][i+1];
_t_19_ += in[k-1][j][i+1];
_t_3_ += in[k-1][j+1][i];
double _t_12_ = in[k-1][j+1][i];
double _t_17_ = in[k-1][j+1][i];
double _t_25_ = in[k-1][j+1][i];
_t_3_ += in[k][j+2][i-2];
_t_11_ += in[k][j+2][i-2];
double _t_16_ = in[k][j+2][i-2];
_t_25_ += in[k][j+2][i-2];
_t_3_ += in[k][j+2][i+2];
_t_11_ += in[k][j+2][i+2];
_t_16_ += in[k][j+2][i+2];
_t_25_ += in[k][j+2][i+2];
_t_3_ += in[k+1][j-1][i];
_t_11_ += in[k+1][j-1][i];
_t_3_ += in[k+1][j][i-1];
_t_7_ += in[k+1][j][i-1];
_t_19_ += in[k+1][j][i-1];
_t_3_ += in[k+1][j][i+1];
_t_7_ += in[k+1][j][i+1];
_t_19_ += in[k+1][j][i+1];
_t_3_ += in[k+1][j+1][i];
_t_12_ += in[k+1][j+1][i];
_t_17_ += in[k+1][j+1][i];
_t_25_ += in[k+1][j+1][i];
_t_3_ += in[k-2][j][i-2];
double _t_9_ = in[k-2][j][i-2];
_t_9_ += in[k-2][j][i-2];
double _t_14_ = in[k-2][j][i-2];
double _t_15_ = in[k-2][j][i-2];
_t_3_ += in[k-2][j-2][i];
_t_3_ += in[k-2][j+2][i];
_t_11_ += in[k-2][j+2][i];
_t_11_ += in[k-2][j+2][i];
_t_16_ += in[k-2][j+2][i];
_t_16_ += in[k-2][j+2][i];
_t_25_ += in[k-2][j+2][i];
_t_25_ += in[k-2][j+2][i];
_t_3_ += in[k-2][j][i-2];
_t_3_ += in[k-2][j][i+2];
_t_9_ += in[k-2][j][i+2];
_t_9_ += in[k-2][j][i+2];
_t_14_ += in[k-2][j][i+2];
_t_15_ += in[k-2][j][i+2];
_t_3_ += in[k-2][j+2][i];
double outkc0jc0ic0 = 0.217 * _t_3_;
double _t_2_ = in[k-1][j-2][i-2];
_t_2_ += in[k-1][j-2][i+2];
_t_2_ += in[k][j-2][i];
_t_2_ += in[k+1][j-2][i-2];
_t_2_ += in[k+1][j-2][i+2];
_t_2_ += in[k-1][j+2][i-2];
_t_12_ += in[k-1][j+2][i-2];
double _t_18_ = in[k-1][j+2][i-2];
double _t_26_ = in[k-1][j+2][i-2];
_t_2_ += in[k-1][j+2][i+2];
_t_12_ += in[k-1][j+2][i+2];
_t_18_ += in[k-1][j+2][i+2];
_t_26_ += in[k-1][j+2][i+2];
_t_2_ += in[k][j][i-2];
_t_11_ += in[k][j][i-2];
_t_17_ += in[k][j][i-2];
_t_2_ += in[k][j][i+2];
_t_11_ += in[k][j][i+2];
_t_17_ += in[k][j][i+2];
_t_2_ += in[k][j+2][i];
_t_7_ += in[k][j+2][i];
_t_18_ += in[k][j+2][i];
double _t_21_ = in[k][j+2][i];
_t_2_ += in[k+1][j+2][i-2];
_t_12_ += in[k+1][j+2][i-2];
_t_18_ += in[k+1][j+2][i-2];
_t_26_ += in[k+1][j+2][i-2];
_t_2_ += in[k+1][j+2][i+2];
_t_12_ += in[k+1][j+2][i+2];
_t_18_ += in[k+1][j+2][i+2];
_t_26_ += in[k+1][j+2][i+2];
_t_2_ += in[k-2][j][i];
_t_11_ += in[k-2][j][i];
_t_11_ += in[k-2][j][i];
_t_17_ += in[k-2][j][i];
_t_17_ += in[k-2][j][i];
_t_2_ += in[k-2][j-1][i+2];
_t_7_ += in[k-2][j-1][i+2];
double _t_8_ = in[k-2][j-1][i+2];
_t_2_ += in[k-2][j+2][i+1];
_t_12_ += in[k-2][j+2][i+1];
double _t_13_ = in[k-2][j+2][i+1];
_t_18_ += in[k-2][j+2][i+1];
_t_18_ += in[k-2][j+2][i+1];
_t_26_ += in[k-2][j+2][i+1];
double _t_27_ = in[k-2][j+2][i+1];
_t_2_ += in[k-2][j+2][i-1];
_t_12_ += in[k-2][j+2][i-1];
_t_13_ += in[k-2][j+2][i-1];
_t_18_ += in[k-2][j+2][i-1];
_t_18_ += in[k-2][j+2][i-1];
_t_26_ += in[k-2][j+2][i-1];
_t_27_ += in[k-2][j+2][i-1];
_t_2_ += in[k-2][j-1][i+2];
_t_2_ += in[k-2][j+1][i+2];
double _t_10_ = in[k-2][j+1][i+2];
_t_10_ += in[k-2][j+1][i+2];
_t_16_ += in[k-2][j+1][i+2];
_t_16_ += in[k-2][j+1][i+2];
_t_21_ += in[k-2][j+1][i+2];
double _t_22_ = in[k-2][j+1][i+2];
_t_2_ += in[k-2][j+1][i+2];
_t_2_ += in[k-2][j][i];
_t_2_ += in[k-2][j+1][i-2];
_t_10_ += in[k-2][j+1][i-2];
_t_10_ += in[k-2][j+1][i-2];
_t_16_ += in[k-2][j+1][i-2];
_t_16_ += in[k-2][j+1][i-2];
_t_21_ += in[k-2][j+1][i-2];
_t_22_ += in[k-2][j+1][i-2];
_t_2_ += in[k-2][j+2][i-1];
_t_2_ += in[k-2][j-1][i-2];
_t_7_ += in[k-2][j-1][i-2];
_t_8_ += in[k-2][j-1][i-2];
_t_2_ += in[k-2][j+1][i-2];
_t_2_ += in[k-2][j-1][i-2];
outkc0jc0ic0 += 1.132 * _t_2_;
double _t_4_ = in[k-1][j-2][i];
_t_4_ += in[k][j-2][i-1];
_t_4_ += in[k][j-2][i+1];
_t_4_ += in[k+1][j-2][i];
_t_4_ += in[k-1][j][i-2];
_t_12_ += in[k-1][j][i-2];
_t_16_ += in[k-1][j][i-2];
_t_4_ += in[k-1][j][i+2];
_t_12_ += in[k-1][j][i+2];
_t_16_ += in[k-1][j][i+2];
_t_4_ += in[k-1][j+2][i];
_t_10_ += in[k-1][j+2][i];
_t_19_ += in[k-1][j+2][i];
double _t_24_ = in[k-1][j+2][i];
_t_4_ += in[k][j-1][i-2];
_t_10_ += in[k][j-1][i-2];
_t_4_ += in[k][j-1][i+2];
_t_10_ += in[k][j-1][i+2];
_t_4_ += in[k][j][i];
_t_7_ += in[k][j][i];
_t_16_ += in[k][j][i];
_t_4_ += in[k][j+1][i-2];
_t_9_ += in[k][j+1][i-2];
_t_18_ += in[k][j+1][i-2];
_t_24_ += in[k][j+1][i-2];
_t_4_ += in[k][j+1][i+2];
_t_9_ += in[k][j+1][i+2];
_t_18_ += in[k][j+1][i+2];
_t_24_ += in[k][j+1][i+2];
_t_4_ += in[k][j+2][i-1];
_t_12_ += in[k][j+2][i-1];
_t_14_ += in[k][j+2][i-1];
_t_26_ += in[k][j+2][i-1];
_t_4_ += in[k][j+2][i+1];
_t_12_ += in[k][j+2][i+1];
_t_14_ += in[k][j+2][i+1];
_t_26_ += in[k][j+2][i+1];
_t_4_ += in[k+1][j][i-2];
_t_12_ += in[k+1][j][i-2];
_t_16_ += in[k+1][j][i-2];
_t_4_ += in[k+1][j][i+2];
_t_12_ += in[k+1][j][i+2];
_t_16_ += in[k+1][j][i+2];
_t_4_ += in[k+1][j+2][i];
_t_10_ += in[k+1][j+2][i];
_t_19_ += in[k+1][j+2][i];
_t_24_ += in[k+1][j+2][i];
_t_4_ += in[k-2][j-1][i];
_t_10_ += in[k-2][j-1][i];
_t_10_ += in[k-2][j-1][i];
_t_4_ += in[k-2][j][i-1];
_t_12_ += in[k-2][j][i-1];
_t_13_ += in[k-2][j][i-1];
_t_16_ += in[k-2][j][i-1];
_t_16_ += in[k-2][j][i-1];
_t_4_ += in[k-2][j][i+1];
_t_12_ += in[k-2][j][i+1];
_t_13_ += in[k-2][j][i+1];
_t_16_ += in[k-2][j][i+1];
_t_16_ += in[k-2][j][i+1];
_t_4_ += in[k-2][j+1][i];
_t_9_ += in[k-2][j+1][i];
_t_9_ += in[k-2][j+1][i];
_t_18_ += in[k-2][j+1][i];
_t_18_ += in[k-2][j+1][i];
_t_24_ += in[k-2][j+1][i];
_t_24_ += in[k-2][j+1][i];
_t_4_ += in[k-2][j-1][i];
_t_4_ += in[k-2][j][i-1];
_t_4_ += in[k-2][j][i+1];
_t_4_ += in[k-2][j+1][i];
outkc0jc0ic0 += 2.13 * _t_4_;
double _t_0_ = in[k-2][j-2][i-2];
_t_0_ += in[k-2][j-2][i+2];
double _t_1_ = in[k-2][j-2][i-2];
_t_1_ += in[k-2][j-2][i+2];
_t_0_ += in[k-2][j+2][i-2];
_t_9_ += in[k-2][j+2][i-2];
_t_9_ += in[k-2][j+2][i-2];
_t_17_ += in[k-2][j+2][i-2];
_t_17_ += in[k-2][j+2][i-2];
double _t_23_ = in[k-2][j+2][i-2];
_t_23_ += in[k-2][j+2][i-2];
_t_0_ += in[k-2][j+2][i+2];
_t_9_ += in[k-2][j+2][i+2];
_t_9_ += in[k-2][j+2][i+2];
_t_17_ += in[k-2][j+2][i+2];
_t_17_ += in[k-2][j+2][i+2];
_t_23_ += in[k-2][j+2][i+2];
_t_23_ += in[k-2][j+2][i+2];
_t_0_ += in[k-1][j-1][i-1];
_t_12_ += in[k-1][j-1][i-1];
_t_0_ += in[k-1][j-1][i+1];
_t_12_ += in[k-1][j-1][i+1];
_t_0_ += in[k-1][j+1][i-1];
_t_10_ += in[k-1][j+1][i-1];
_t_14_ += in[k-1][j+1][i-1];
_t_26_ += in[k-1][j+1][i-1];
_t_0_ += in[k-1][j+1][i+1];
_t_10_ += in[k-1][j+1][i+1];
_t_14_ += in[k-1][j+1][i+1];
_t_26_ += in[k-1][j+1][i+1];
_t_0_ += in[k][j-1][i];
_t_9_ += in[k][j-1][i];
_t_0_ += in[k][j][i-1];
_t_12_ += in[k][j][i-1];
_t_18_ += in[k][j][i-1];
_t_0_ += in[k][j][i+1];
_t_12_ += in[k][j][i+1];
_t_18_ += in[k][j][i+1];
_t_0_ += in[k][j+1][i];
_t_11_ += in[k][j+1][i];
_t_14_ += in[k][j+1][i];
_t_23_ += in[k][j+1][i];
_t_0_ += in[k+1][j-1][i-1];
_t_12_ += in[k+1][j-1][i-1];
_t_0_ += in[k+1][j-1][i+1];
_t_12_ += in[k+1][j-1][i+1];
_t_0_ += in[k+1][j+1][i-1];
_t_10_ += in[k+1][j+1][i-1];
_t_14_ += in[k+1][j+1][i-1];
_t_26_ += in[k+1][j+1][i-1];
_t_0_ += in[k+1][j+1][i+1];
_t_10_ += in[k+1][j+1][i+1];
_t_14_ += in[k+1][j+1][i+1];
_t_26_ += in[k+1][j+1][i+1];
outkc0jc0ic0 += 0.75 * _t_0_;
_t_1_ += in[k-2][j+2][i-2];
_t_1_ += in[k-2][j+2][i+2];
outkc0jc0ic0 += 0.76 * _t_1_;
double _t_5_ = in[k-1][j-2][i-1];
_t_5_ += in[k-1][j-2][i+1];
_t_5_ += in[k+1][j-2][i-1];
_t_5_ += in[k+1][j-2][i+1];
_t_5_ += in[k-2][j-1][i-1];
_t_9_ += in[k-2][j-1][i-1];
_t_9_ += in[k-2][j-1][i-1];
_t_5_ += in[k-2][j-1][i+1];
_t_9_ += in[k-2][j-1][i+1];
_t_9_ += in[k-2][j-1][i+1];
_t_5_ += in[k-2][j+1][i-1];
_t_11_ += in[k-2][j+1][i-1];
_t_11_ += in[k-2][j+1][i-1];
_t_19_ += in[k-2][j+1][i-1];
double _t_20_ = in[k-2][j+1][i-1];
_t_23_ += in[k-2][j+1][i-1];
_t_23_ += in[k-2][j+1][i-1];
_t_5_ += in[k-2][j+1][i+1];
_t_11_ += in[k-2][j+1][i+1];
_t_11_ += in[k-2][j+1][i+1];
_t_19_ += in[k-2][j+1][i+1];
_t_20_ += in[k-2][j+1][i+1];
_t_23_ += in[k-2][j+1][i+1];
_t_23_ += in[k-2][j+1][i+1];
_t_5_ += in[k-1][j-1][i-2];
_t_9_ += in[k-1][j-1][i-2];
_t_5_ += in[k-1][j-1][i+2];
_t_9_ += in[k-1][j-1][i+2];
_t_5_ += in[k-1][j][i];
_t_10_ += in[k-1][j][i];
_t_18_ += in[k-1][j][i];
_t_5_ += in[k-1][j+1][i-2];
_t_11_ += in[k-1][j+1][i-2];
_t_19_ += in[k-1][j+1][i-2];
_t_23_ += in[k-1][j+1][i-2];
_t_5_ += in[k-1][j+1][i+2];
_t_11_ += in[k-1][j+1][i+2];
_t_19_ += in[k-1][j+1][i+2];
_t_23_ += in[k-1][j+1][i+2];
_t_5_ += in[k-1][j+2][i-1];
_t_7_ += in[k-1][j+2][i-1];
_t_17_ += in[k-1][j+2][i-1];
_t_21_ += in[k-1][j+2][i-1];
_t_5_ += in[k-1][j+2][i+1];
_t_7_ += in[k-1][j+2][i+1];
_t_17_ += in[k-1][j+2][i+1];
_t_21_ += in[k-1][j+2][i+1];
_t_5_ += in[k][j-1][i-1];
_t_11_ += in[k][j-1][i-1];
_t_5_ += in[k][j-1][i+1];
_t_11_ += in[k][j-1][i+1];
_t_5_ += in[k][j+1][i-1];
_t_7_ += in[k][j+1][i-1];
_t_19_ += in[k][j+1][i-1];
_t_25_ += in[k][j+1][i-1];
_t_5_ += in[k][j+1][i+1];
_t_7_ += in[k][j+1][i+1];
_t_19_ += in[k][j+1][i+1];
_t_25_ += in[k][j+1][i+1];
_t_5_ += in[k+1][j-1][i-2];
_t_9_ += in[k+1][j-1][i-2];
_t_5_ += in[k+1][j-1][i+2];
_t_9_ += in[k+1][j-1][i+2];
_t_5_ += in[k+1][j][i];
_t_10_ += in[k+1][j][i];
_t_18_ += in[k+1][j][i];
_t_5_ += in[k+1][j+1][i-2];
_t_11_ += in[k+1][j+1][i-2];
_t_19_ += in[k+1][j+1][i-2];
_t_23_ += in[k+1][j+1][i-2];
_t_5_ += in[k+1][j+1][i+2];
_t_11_ += in[k+1][j+1][i+2];
_t_19_ += in[k+1][j+1][i+2];
_t_23_ += in[k+1][j+1][i+2];
_t_5_ += in[k+1][j+2][i-1];
_t_7_ += in[k+1][j+2][i-1];
_t_17_ += in[k+1][j+2][i-1];
_t_21_ += in[k+1][j+2][i-1];
_t_5_ += in[k+1][j+2][i+1];
_t_7_ += in[k+1][j+2][i+1];
_t_17_ += in[k+1][j+2][i+1];
_t_21_ += in[k+1][j+2][i+1];
outkc0jc0ic0 += 0.331 * _t_5_;
double _t_6_ = in[k-2][j-1][i-1];
_t_6_ += in[k-2][j-1][i+1];
_t_6_ += in[k-2][j+1][i-1];
_t_6_ += in[k-2][j+1][i+1];
outkc0jc0ic0 += 0.332 * _t_6_;

_t_7_ += in[k-2][j+3][i-2];
_t_16_ += in[k-2][j+3][i-2];
_t_16_ += in[k-2][j+3][i-2];
_t_24_ += in[k-2][j+3][i-2];
_t_24_ += in[k-2][j+3][i-2];
_t_7_ += in[k-2][j+3][i+2];
_t_16_ += in[k-2][j+3][i+2];
_t_16_ += in[k-2][j+3][i+2];
_t_24_ += in[k-2][j+3][i+2];
_t_24_ += in[k-2][j+3][i+2];
double outkc0jp1ic0 = 0.75 * _t_7_;
_t_8_ += in[k-2][j+3][i-2];
_t_8_ += in[k-2][j+3][i+2];
outkc0jp1ic0 += 0.76 * _t_8_;
_t_9_ += in[k-2][j+3][i-1];
_t_19_ += in[k-2][j+3][i-1];
_t_25_ += in[k-2][j+3][i-1];
_t_25_ += in[k-2][j+3][i-1];
_t_9_ += in[k-2][j+3][i+1];
_t_19_ += in[k-2][j+3][i+1];
_t_25_ += in[k-2][j+3][i+1];
_t_25_ += in[k-2][j+3][i+1];
_t_9_ += in[k-2][j+3][i-1];
_t_9_ += in[k-2][j+3][i+1];
_t_9_ += in[k-1][j+3][i-2];
_t_19_ += in[k-1][j+3][i-2];
_t_25_ += in[k-1][j+3][i-2];
_t_9_ += in[k-1][j+3][i+2];
_t_19_ += in[k-1][j+3][i+2];
_t_25_ += in[k-1][j+3][i+2];
_t_9_ += in[k][j+3][i];
_t_14_ += in[k][j+3][i];
_t_25_ += in[k][j+3][i];
_t_9_ += in[k+1][j+3][i-2];
_t_19_ += in[k+1][j+3][i-2];
_t_25_ += in[k+1][j+3][i-2];
_t_9_ += in[k+1][j+3][i+2];
_t_19_ += in[k+1][j+3][i+2];
_t_25_ += in[k+1][j+3][i+2];
outkc0jp1ic0 += 1.132 * _t_9_;
_t_20_ += in[k-2][j+3][i-1];
_t_20_ += in[k-2][j+3][i+1];
double outkc0jp2ic0 = 0.332 * _t_20_;
_t_10_ += in[k-2][j+3][i];
_t_18_ += in[k-2][j+3][i];
_t_18_ += in[k-2][j+3][i];
_t_23_ += in[k-2][j+3][i];
_t_23_ += in[k-2][j+3][i];
_t_10_ += in[k-2][j+3][i];
_t_10_ += in[k][j+3][i-2];
_t_18_ += in[k][j+3][i-2];
_t_23_ += in[k][j+3][i-2];
_t_10_ += in[k][j+3][i+2];
_t_18_ += in[k][j+3][i+2];
_t_23_ += in[k][j+3][i+2];
outkc0jp1ic0 += 0.217 * _t_10_;
_t_11_ += in[k-1][j+3][i];
_t_17_ += in[k-1][j+3][i];
_t_26_ += in[k-1][j+3][i];
_t_11_ += in[k][j+3][i-1];
_t_19_ += in[k][j+3][i-1];
_t_21_ += in[k][j+3][i-1];
_t_11_ += in[k][j+3][i+1];
_t_19_ += in[k][j+3][i+1];
_t_21_ += in[k][j+3][i+1];
_t_11_ += in[k+1][j+3][i];
_t_17_ += in[k+1][j+3][i];
_t_26_ += in[k+1][j+3][i];
outkc0jp1ic0 += 2.13 * _t_11_;
_t_12_ += in[k-1][j+3][i-1];
_t_14_ += in[k-1][j+3][i-1];
_t_24_ += in[k-1][j+3][i-1];
_t_12_ += in[k-1][j+3][i+1];
_t_14_ += in[k-1][j+3][i+1];
_t_24_ += in[k-1][j+3][i+1];
_t_12_ += in[k+1][j+3][i-1];
_t_14_ += in[k+1][j+3][i-1];
_t_24_ += in[k+1][j+3][i-1];
_t_12_ += in[k+1][j+3][i+1];
_t_14_ += in[k+1][j+3][i+1];
_t_24_ += in[k+1][j+3][i+1];
outkc0jp1ic0 += 0.331 * _t_12_;
outkc0jp1ic0 += 0.332 * _t_13_;

_t_14_ += in[k-2][j+4][i-2];
_t_23_ += in[k-2][j+4][i-2];
_t_23_ += in[k-2][j+4][i-2];
_t_14_ += in[k-2][j+4][i+2];
_t_23_ += in[k-2][j+4][i+2];
_t_23_ += in[k-2][j+4][i+2];
outkc0jp2ic0 += 0.75 * _t_14_;
_t_15_ += in[k-2][j+4][i-2];
_t_15_ += in[k-2][j+4][i+2];
outkc0jp2ic0 += 0.76 * _t_15_;
_t_16_ += in[k-2][j+4][i-1];
_t_16_ += in[k-2][j+4][i+1];
_t_16_ += in[k-2][j+4][i-1];
_t_16_ += in[k-2][j+4][i+1];
_t_16_ += in[k-1][j+4][i-2];
_t_16_ += in[k-1][j+4][i+2];
_t_16_ += in[k][j+4][i];
_t_21_ += in[k][j+4][i];
_t_16_ += in[k+1][j+4][i-2];
_t_16_ += in[k+1][j+4][i+2];
outkc0jp2ic0 += 1.132 * _t_16_;
_t_27_ += in[k-2][j+4][i-1];
_t_27_ += in[k-2][j+4][i+1];
double outkc0jp3ic0 = 0.332 * _t_27_;
_t_17_ += in[k-2][j+4][i];
_t_17_ += in[k-2][j+4][i];
_t_17_ += in[k][j+4][i-2];
_t_17_ += in[k][j+4][i+2];
outkc0jp2ic0 += 0.217 * _t_17_;
_t_25_ += in[k-2][j+4][i];
_t_25_ += in[k-2][j+4][i];
_t_25_ += in[k][j+4][i-2];
_t_25_ += in[k][j+4][i+2];
_t_25_ += in[k-1][j+5][i];
_t_25_ += in[k][j+5][i-1];
_t_25_ += in[k][j+5][i+1];
_t_25_ += in[k+1][j+5][i];
outkc0jp3ic0 += 2.13 * _t_25_;
_t_18_ += in[k-1][j+4][i];
_t_24_ += in[k-1][j+4][i];
_t_18_ += in[k][j+4][i-1];
_t_18_ += in[k][j+4][i+1];
_t_18_ += in[k+1][j+4][i];
_t_24_ += in[k+1][j+4][i];
outkc0jp2ic0 += 2.13 * _t_18_;
_t_19_ += in[k-1][j+4][i-1];
_t_21_ += in[k-1][j+4][i-1];
_t_19_ += in[k-1][j+4][i+1];
_t_21_ += in[k-1][j+4][i+1];
_t_19_ += in[k+1][j+4][i-1];
_t_21_ += in[k+1][j+4][i-1];
_t_19_ += in[k+1][j+4][i+1];
_t_21_ += in[k+1][j+4][i+1];
outkc0jp2ic0 += 0.331 * _t_19_;
_t_26_ += in[k-1][j+4][i-2];
_t_26_ += in[k-1][j+4][i+2];
_t_26_ += in[k][j+4][i-1];
_t_26_ += in[k][j+4][i+1];
_t_26_ += in[k+1][j+4][i-2];
_t_26_ += in[k+1][j+4][i+2];
_t_26_ += in[k-1][j+5][i-1];
_t_26_ += in[k-1][j+5][i+1];
_t_26_ += in[k+1][j+5][i-1];
_t_26_ += in[k+1][j+5][i+1];
_t_26_ += in[k-2][j+4][i-1];
_t_26_ += in[k-2][j+4][i+1];
outkc0jp3ic0 += 0.331 * _t_26_;

_t_21_ += in[k-2][j+5][i-2];
_t_21_ += in[k-2][j+5][i+2];
_t_22_ += in[k-2][j+5][i-2];
_t_22_ += in[k-2][j+5][i+2];
outkc0jp3ic0 += 0.75 * _t_21_;
outkc0jp3ic0 += 0.76 * _t_22_;
_t_23_ += in[k-2][j+5][i+1];
outkc0jp3ic0 += 1.132 * _t_23_;
_t_24_ += in[k-2][j+5][i];
outkc0jp3ic0 += 0.217 * _t_24_;

out[k][j][i] = outkc0jc0ic0;
out[k][j+1][i] = outkc0jp1ic0;
out[k][j+2][i] = outkc0jp2ic0;
out[k][j+3][i] = outkc0jp3ic0;
	}
}

extern "C" void host_code (double *h_in, double *h_out, int N) {
	double *in;
	hipMalloc (&in, sizeof(double)*N*N*N);
	check_error ("Failed to allocate device memory for in\n");
	hipMemcpy (in, h_in, sizeof(double)*N*N*N, hipMemcpyHostToDevice);
	double *out;
	hipMalloc (&out, sizeof(double)*N*N*N);
	check_error ("Failed to allocate device memory for out\n");

	dim3 blockconfig (16, 4, 4);
	dim3 gridconfig (ceil(N-4, blockconfig.x), ceil(N-4, 4*blockconfig.y), ceil(N-4, blockconfig.z));

	j3d125pt<<<gridconfig, blockconfig>>> (in, out, N);

	hipMemcpy (h_out, out, sizeof(double)*N*N*N, hipMemcpyDeviceToHost);

	hipFree (in); 
	hipFree (out);
}

	.text
	.file	"reordered-b.hip"
	.globl	_Z11check_errorPKc              # -- Begin function _Z11check_errorPKc
	.type	_Z11check_errorPKc,@function
_Z11check_errorPKc:                     # @_Z11check_errorPKc
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset %rbx, -16
	movq	%rdi, %rbx
	callq	hipGetLastError
	testl	%eax, %eax
	jne	.LBB0_2
# %bb.1:
	popq	%rbx
	.cfi_def_cfa_offset 8
	retq
.LBB0_2:
	.cfi_def_cfa_offset 16
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str, %edi
	movq	%rbx, %rsi
	movq	%rax, %rdx
	xorl	%eax, %eax
	callq	printf
	movl	$-1, %edi
	callq	exit
.Lfunc_end0:
	.size	_Z11check_errorPKc, .Lfunc_end0-_Z11check_errorPKc
	.cfi_endproc
                                        # -- End function
	.globl	_Z23__device_stub__j3d125ptPdS_i # -- Begin function _Z23__device_stub__j3d125ptPdS_i
	.type	_Z23__device_stub__j3d125ptPdS_i,@function
_Z23__device_stub__j3d125ptPdS_i:       # @_Z23__device_stub__j3d125ptPdS_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z8j3d125ptPdS_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z23__device_stub__j3d125ptPdS_i, .Lfunc_end1-_Z23__device_stub__j3d125ptPdS_i
	.cfi_endproc
                                        # -- End function
	.globl	host_code                       # -- Begin function host_code
	.type	host_code,@function
host_code:                              # @host_code
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$24, %rsp
	.cfi_def_cfa_offset 80
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%edx, %ebp
	movq	%rsi, %rbx
	movq	%rdi, %r15
	movslq	%edx, %r13
	movq	%r13, %r14
	imulq	%r13, %r14
	imulq	%r13, %r14
	shlq	$3, %r14
	leaq	16(%rsp), %r12
	movq	%r12, %rdi
	movq	%r14, %rsi
	callq	hipMalloc
	movl	$.L.str.1, %edi
	callq	_Z11check_errorPKc
	movq	(%r12), %rdi
	movq	%r15, %rsi
	movq	%r14, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	8(%rsp), %rdi
	movq	%r14, %rsi
	callq	hipMalloc
	movl	$.L.str.2, %edi
	callq	_Z11check_errorPKc
	leal	-4(%r13), %esi
	movl	%esi, %eax
	andl	$15, %eax
	movl	%esi, %ecx
	shrl	$4, %ecx
	cmpl	$1, %eax
	sbbl	$-1, %ecx
	andl	$3, %r13d
	shrl	$2, %esi
	cmpl	$1, %r13d
	sbbl	$-1, %esi
	movq	%rcx, %rdi
	shlq	$32, %rdi
	orq	%rcx, %rdi
	movabsq	$17179869200, %rdx              # imm = 0x400000010
	movl	$4, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_2
# %bb.1:
	movq	16(%rsp), %rdi
	movq	8(%rsp), %rsi
	movl	%ebp, %edx
	callq	_Z23__device_stub__j3d125ptPdS_i
.LBB2_2:
	movq	8(%rsp), %rsi
	movq	%rbx, %rdi
	movq	%r14, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	movq	16(%rsp), %rdi
	callq	hipFree
	movq	8(%rsp), %rdi
	callq	hipFree
	addq	$24, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	host_code, .Lfunc_end2-host_code
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB3_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB3_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z8j3d125ptPdS_i, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end3:
	.size	__hip_module_ctor, .Lfunc_end3-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB4_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB4_2:
	retq
.Lfunc_end4:
	.size	__hip_module_dtor, .Lfunc_end4-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"CUDA error : %s, %s\n"
	.size	.L.str, 21

	.type	_Z8j3d125ptPdS_i,@object        # @_Z8j3d125ptPdS_i
	.section	.rodata,"a",@progbits
	.globl	_Z8j3d125ptPdS_i
	.p2align	3, 0x0
_Z8j3d125ptPdS_i:
	.quad	_Z23__device_stub__j3d125ptPdS_i
	.size	_Z8j3d125ptPdS_i, 8

	.type	.L.str.1,@object                # @.str.1
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str.1:
	.asciz	"Failed to allocate device memory for in\n"
	.size	.L.str.1, 41

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"Failed to allocate device memory for out\n"
	.size	.L.str.2, 42

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z8j3d125ptPdS_i"
	.size	.L__unnamed_1, 17

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z23__device_stub__j3d125ptPdS_i
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z8j3d125ptPdS_i
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z8j3d125ptPdS_i        ; -- Begin function _Z8j3d125ptPdS_i
	.globl	_Z8j3d125ptPdS_i
	.p2align	8
	.type	_Z8j3d125ptPdS_i,@function
_Z8j3d125ptPdS_i:                       ; @_Z8j3d125ptPdS_i
; %bb.0:
	s_clause 0x1
	s_load_b32 s3, s[0:1], 0x24
	s_load_b32 s2, s[0:1], 0x10
	v_and_b32_e32 v1, 0x3ff, v0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s4, s3, 0xffff
	s_add_i32 s2, s2, -3
	s_mul_i32 s13, s13, s4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_max_i32 s4, s13, 0
	v_add_nc_u32_e32 v6, s4, v1
	s_mov_b32 s4, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v8, 2, v6
	v_cmpx_ge_i32_e64 s2, v8
	s_cbranch_execz .LBB0_3
; %bb.1:
	s_load_b32 s4, s[0:1], 0x28
	s_lshr_b32 s3, s3, 16
	v_bfe_u32 v1, v0, 20, 10
	s_mul_i32 s14, s14, s3
	v_bfe_u32 v0, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_and_b32 s3, s4, 0xffff
	s_lshl_b32 s4, s14, 2
	s_and_b32 s3, s3, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mul_i32 s15, s15, s3
	s_or_b32 s3, s4, 2
	s_max_i32 s4, s15, 0
	s_max_i32 s3, s3, 2
	v_add_nc_u32_e32 v12, s4, v1
	v_lshl_add_u32 v101, v0, 2, s3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v100, 2, v12
	v_max_u32_e32 v0, v101, v100
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ge_u32_e32 vcc_lo, s2, v0
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_3
; %bb.2:
	s_load_b128 s[0:3], s[0:1], 0x0
	v_dual_mov_b32 v7, 0 :: v_dual_add_nc_u32 v2, -2, v101
	v_add_nc_u32_e32 v23, -1, v101
	v_mad_u64_u32 v[54:55], null, 0x1020, v101, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mad_u64_u32 v[0:1], null, 0x1020, v2, 0
	v_lshlrev_b64 v[72:73], 3, v[6:7]
	v_mov_b32_e32 v9, v7
	v_add_nc_u32_e32 v17, 2, v101
	s_mov_b32 s4, 0x83126e9
	s_mov_b32 s5, 0x3ff21cac
	s_mov_b32 s6, 0x70a3d70a
	s_mov_b32 s7, 0x40010a3d
	s_mov_b32 s8, 0x851eb852
	s_mov_b32 s9, 0x3fe851eb
	s_mov_b32 s10, 0x9fbe76c9
	s_mov_b32 s11, 0x3fd52f1a
	s_mov_b32 s12, 0xed916873
	s_waitcnt lgkmcnt(0)
	v_mad_u64_u32 v[82:83], null, 0x208080, v100, s[0:1]
	s_mov_b32 s13, 0x3fd53f7c
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, v82, v0
	v_add_co_ci_u32_e32 v3, vcc_lo, v83, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, v2, v72
	v_add_co_ci_u32_e32 v3, vcc_lo, v3, v73, vcc_lo
	s_clause 0x2
	global_load_b64 v[4:5], v[2:3], off offset:32
	global_load_b128 v[24:27], v[2:3], off offset:16
	global_load_b128 v[28:31], v[2:3], off
	v_dual_mov_b32 v3, v7 :: v_dual_add_nc_u32 v2, 4, v6
	s_waitcnt vmcnt(0)
	v_add_f64 v[10:11], v[28:29], v[4:5]
	v_add_co_u32 v4, vcc_lo, 0xffdf7f80, v82
	v_add_co_ci_u32_e32 v5, vcc_lo, -1, v83, vcc_lo
	v_lshlrev_b64 v[28:29], 3, v[8:9]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[13:14], null, 0x1020, v23, v[4:5]
	v_add_co_u32 v8, vcc_lo, v13, v28
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v9, vcc_lo, v14, v29, vcc_lo
	v_dual_mov_b32 v14, v7 :: v_dual_add_nc_u32 v13, 1, v6
	v_add_co_u32 v102, vcc_lo, v4, v54
	global_load_b64 v[8:9], v[8:9], off
	v_add_co_ci_u32_e32 v103, vcc_lo, v5, v55, vcc_lo
	v_lshlrev_b64 v[68:69], 3, v[13:14]
	v_add_nc_u32_e32 v6, 3, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v58, vcc_lo, v102, v68
	v_add_co_ci_u32_e32 v59, vcc_lo, v103, v69, vcc_lo
	s_delay_alu instid0(VALU_DEP_3)
	v_lshlrev_b64 v[56:57], 3, v[6:7]
	global_load_b64 v[13:14], v[58:59], off
	v_add_co_u32 v60, vcc_lo, v102, v56
	v_add_co_ci_u32_e32 v61, vcc_lo, v103, v57, vcc_lo
	global_load_b64 v[6:7], v[60:61], off
	s_waitcnt vmcnt(2)
	v_add_f64 v[10:11], v[10:11], v[8:9]
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_add_f64 v[10:11], v[10:11], v[13:14]
	s_waitcnt vmcnt(0)
	v_add_f64 v[13:14], v[13:14], v[6:7]
	v_add_f64 v[10:11], v[10:11], v[6:7]
	v_or_b32_e32 v6, 1, v101
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[52:53], null, 0x1020, v6, 0
	v_add_co_u32 v104, vcc_lo, v4, v52
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v105, vcc_lo, v5, v53, vcc_lo
	v_add_co_u32 v6, vcc_lo, v104, v28
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v7, vcc_lo, v105, v29, vcc_lo
	global_load_b64 v[15:16], v[6:7], off
	v_mad_u64_u32 v[6:7], null, 0x1020, v17, 0
	v_add_co_u32 v17, vcc_lo, v82, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v18, vcc_lo, v83, v7, vcc_lo
	v_add_co_u32 v17, vcc_lo, v17, v72
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v18, vcc_lo, v18, v73, vcc_lo
	s_clause 0x2
	global_load_b64 v[19:20], v[17:18], off offset:32
	global_load_b128 v[32:35], v[17:18], off offset:16
	global_load_b128 v[36:39], v[17:18], off
	s_waitcnt vmcnt(3)
	v_add_f64 v[10:11], v[10:11], v[15:16]
	s_waitcnt vmcnt(0)
	v_add_f64 v[8:9], v[8:9], v[36:37]
	v_add_f64 v[17:18], v[15:16], v[36:37]
	v_add_f64 v[70:71], v[36:37], v[19:20]
	s_delay_alu instid0(VALU_DEP_4)
	v_add_f64 v[10:11], v[10:11], v[36:37]
	v_mad_u64_u32 v[36:37], null, 0x208080, v12, s[0:1]
	s_mov_b32 s0, 0xef9db22d
	s_mov_b32 s1, 0x3fcbc6a7
	v_add_f64 v[21:22], v[8:9], v[19:20]
	v_add_co_u32 v8, vcc_lo, 0x208080, v82
	v_add_co_ci_u32_e32 v9, vcc_lo, 0, v83, vcc_lo
	v_add_f64 v[17:18], v[17:18], v[19:20]
	v_add_f64 v[10:11], v[10:11], v[19:20]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[19:20], null, 0x1020, v23, v[8:9]
	v_add_co_u32 v19, vcc_lo, v19, v28
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v20, vcc_lo, v20, v29, vcc_lo
	v_add_co_u32 v108, vcc_lo, v8, v54
	v_add_co_ci_u32_e32 v109, vcc_lo, v9, v55, vcc_lo
	global_load_b64 v[19:20], v[19:20], off
	v_add_co_u32 v62, vcc_lo, v108, v68
	v_add_co_ci_u32_e32 v63, vcc_lo, v109, v69, vcc_lo
	v_add_co_u32 v64, vcc_lo, v108, v56
	v_add_co_ci_u32_e32 v65, vcc_lo, v109, v57, vcc_lo
	v_add_co_u32 v106, vcc_lo, v8, v52
	v_add_co_ci_u32_e32 v107, vcc_lo, v9, v53, vcc_lo
	s_waitcnt vmcnt(0)
	v_add_f64 v[10:11], v[10:11], v[19:20]
	v_add_f64 v[74:75], v[21:22], v[19:20]
	global_load_b64 v[19:20], v[62:63], off
	s_waitcnt vmcnt(0)
	v_add_f64 v[10:11], v[10:11], v[19:20]
	v_add_f64 v[13:14], v[13:14], v[19:20]
	global_load_b64 v[19:20], v[64:65], off
	s_waitcnt vmcnt(0)
	v_add_f64 v[84:85], v[13:14], v[19:20]
	v_add_co_u32 v13, vcc_lo, v106, v28
	v_add_co_ci_u32_e32 v14, vcc_lo, v107, v29, vcc_lo
	v_add_f64 v[10:11], v[10:11], v[19:20]
	v_add_co_u32 v12, vcc_lo, v36, v54
	global_load_b64 v[13:14], v[13:14], off
	s_waitcnt vmcnt(0)
	v_add_f64 v[19:20], v[10:11], v[13:14]
	v_add_f64 v[10:11], v[15:16], v[13:14]
	v_add_f64 v[14:15], v[17:18], v[13:14]
	v_add_co_ci_u32_e32 v13, vcc_lo, v37, v55, vcc_lo
	v_add_co_u32 v66, vcc_lo, v12, v72
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v67, vcc_lo, v13, v73, vcc_lo
	s_clause 0x2
	global_load_b64 v[16:17], v[66:67], off offset:32
	global_load_b128 v[40:43], v[66:67], off offset:16
	global_load_b128 v[44:47], v[66:67], off
	v_add_co_u32 v78, vcc_lo, 0xffffdfc0, v66
	v_add_co_ci_u32_e32 v79, vcc_lo, -1, v67, vcc_lo
	s_waitcnt vmcnt(0)
	v_add_f64 v[12:13], v[19:20], v[44:45]
	global_load_b64 v[18:19], v[78:79], off offset:16
	s_waitcnt vmcnt(0)
	v_add_f64 v[12:13], v[12:13], v[18:19]
	v_add_co_u32 v18, vcc_lo, v36, v6
	v_add_co_ci_u32_e32 v19, vcc_lo, v37, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v18, vcc_lo, v18, v68
	v_add_co_ci_u32_e32 v19, vcc_lo, v19, v69, vcc_lo
	s_clause 0x1
	global_load_b128 v[20:23], v[18:19], off offset:16
	global_load_b128 v[48:51], v[18:19], off
	v_add_co_u32 v122, vcc_lo, v4, v0
	v_add_co_ci_u32_e32 v123, vcc_lo, v5, v1, vcc_lo
	s_waitcnt vmcnt(0)
	v_add_f64 v[18:19], v[12:13], v[50:51]
	v_add_f64 v[14:15], v[14:15], v[50:51]
	v_add_f64 v[12:13], v[74:75], v[50:51]
	v_add_f64 v[70:71], v[70:71], v[50:51]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[74:75], v[50:51], v[14:15]
	v_add_f64 v[14:15], v[44:45], v[18:19]
	v_add_f64 v[92:93], v[50:51], v[70:71]
	v_fma_f64 v[18:19], v[44:45], 2.0, v[16:17]
	v_add_f64 v[70:71], v[44:45], v[16:17]
	v_lshlrev_b64 v[44:45], 3, v[2:3]
	v_add_f64 v[12:13], v[50:51], v[12:13]
	v_add_f64 v[14:15], v[16:17], v[14:15]
	v_add_f64 v[86:87], v[16:17], v[18:19]
	s_delay_alu instid0(VALU_DEP_2)
	v_add_f64 v[96:97], v[50:51], v[14:15]
	v_add_co_u32 v14, vcc_lo, v122, v72
	v_add_co_ci_u32_e32 v15, vcc_lo, v123, v73, vcc_lo
	v_add_co_u32 v2, vcc_lo, v122, v44
	v_add_co_ci_u32_e32 v3, vcc_lo, v123, v45, vcc_lo
	global_load_b64 v[14:15], v[14:15], off
	v_add_co_u32 v120, vcc_lo, v8, v0
	global_load_b64 v[2:3], v[2:3], off
	v_add_co_ci_u32_e32 v121, vcc_lo, v9, v1, vcc_lo
	v_add_co_u32 v0, vcc_lo, v120, v72
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v1, vcc_lo, v121, v73, vcc_lo
	global_load_b64 v[0:1], v[0:1], off
	s_waitcnt vmcnt(1)
	v_add_f64 v[2:3], v[14:15], v[2:3]
	v_add_f64 v[2:3], v[2:3], v[24:25]
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[0:1], v[2:3], v[0:1]
	v_add_co_u32 v2, vcc_lo, v120, v44
	v_add_co_ci_u32_e32 v3, vcc_lo, v121, v45, vcc_lo
	v_add_co_u32 v114, vcc_lo, v4, v6
	v_add_co_ci_u32_e32 v115, vcc_lo, v5, v7, vcc_lo
	global_load_b64 v[2:3], v[2:3], off
	s_waitcnt vmcnt(0)
	v_add_f64 v[0:1], v[0:1], v[2:3]
	v_add_co_u32 v2, vcc_lo, v114, v72
	v_add_co_ci_u32_e32 v3, vcc_lo, v115, v73, vcc_lo
	v_add_co_u32 v14, vcc_lo, v114, v44
	v_add_co_ci_u32_e32 v15, vcc_lo, v115, v45, vcc_lo
	global_load_b64 v[2:3], v[2:3], off
	v_add_co_u32 v112, vcc_lo, v82, v54
	global_load_b64 v[14:15], v[14:15], off
	v_add_co_ci_u32_e32 v113, vcc_lo, v83, v55, vcc_lo
	v_add_co_u32 v50, vcc_lo, v112, v72
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v51, vcc_lo, v113, v73, vcc_lo
	v_add_co_u32 v118, vcc_lo, v112, v44
	v_add_co_ci_u32_e32 v119, vcc_lo, v113, v45, vcc_lo
	v_add_co_u32 v24, vcc_lo, v112, v68
	v_add_co_ci_u32_e32 v25, vcc_lo, v113, v69, vcc_lo
	v_add_co_u32 v116, vcc_lo, v8, v6
	v_add_co_ci_u32_e32 v117, vcc_lo, v9, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v6, vcc_lo, v116, v72
	v_add_co_ci_u32_e32 v7, vcc_lo, v117, v73, vcc_lo
	s_waitcnt vmcnt(1)
	v_add_f64 v[0:1], v[0:1], v[2:3]
	v_add_f64 v[4:5], v[10:11], v[2:3]
	s_waitcnt vmcnt(0)
	v_add_f64 v[2:3], v[2:3], v[14:15]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[0:1], v[0:1], v[14:15]
	v_add_f64 v[4:5], v[4:5], v[14:15]
	global_load_b64 v[14:15], v[50:51], off
	v_add_f64 v[80:81], v[2:3], v[32:33]
	s_waitcnt vmcnt(0)
	v_add_f64 v[0:1], v[0:1], v[14:15]
	v_add_f64 v[76:77], v[12:13], v[14:15]
	v_add_f64 v[10:11], v[10:11], v[14:15]
	s_clause 0x2
	global_load_b128 v[12:15], v[24:25], off offset:16
	global_load_b128 v[16:19], v[24:25], off
	global_load_b64 v[6:7], v[6:7], off
	s_waitcnt vmcnt(2)
	v_add_f64 v[0:1], v[0:1], v[14:15]
	v_add_f64 v[76:77], v[76:77], v[14:15]
	s_waitcnt vmcnt(0)
	v_add_f64 v[4:5], v[4:5], v[6:7]
	v_add_f64 v[8:9], v[80:81], v[6:7]
	v_add_f64 v[2:3], v[2:3], v[6:7]
	v_add_f64 v[10:11], v[10:11], v[14:15]
	v_add_f64 v[14:15], v[84:85], v[32:33]
	v_add_f64 v[0:1], v[0:1], v[32:33]
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[0:1], v[0:1], v[6:7]
	v_add_co_u32 v6, vcc_lo, v116, v44
	v_add_co_ci_u32_e32 v7, vcc_lo, v117, v45, vcc_lo
	global_load_b64 v[6:7], v[6:7], off
	s_waitcnt vmcnt(0)
	v_add_f64 v[0:1], v[0:1], v[6:7]
	v_add_f64 v[88:89], v[4:5], v[6:7]
	v_add_co_u32 v4, vcc_lo, 0xffffefe0, v66
	v_add_co_ci_u32_e32 v5, vcc_lo, -1, v67, vcc_lo
	v_add_f64 v[8:9], v[8:9], v[6:7]
	v_add_f64 v[90:91], v[2:3], v[6:7]
	v_add_f64 v[94:95], v[0:1], v[40:41]
	v_add_f64 v[0:1], v[76:77], v[40:41]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[8:9], v[8:9], v[20:21]
	v_add_f64 v[76:77], v[40:41], v[0:1]
	v_add_f64 v[0:1], v[10:11], v[40:41]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[8:9], v[20:21], v[8:9]
	v_add_f64 v[80:81], v[40:41], v[0:1]
	v_add_co_u32 v0, vcc_lo, 0xfffff000, v66
	v_add_co_ci_u32_e32 v1, vcc_lo, -1, v67, vcc_lo
	s_clause 0x2
	global_load_b128 v[0:3], v[0:1], off offset:-32
	global_load_b64 v[124:125], v[66:67], off offset:-4096
	global_load_b128 v[4:7], v[4:5], off offset:16
	v_add_f64 v[8:9], v[48:49], v[8:9]
	v_add_co_u32 v110, vcc_lo, v36, v52
	v_add_co_ci_u32_e32 v111, vcc_lo, v37, v53, vcc_lo
	s_waitcnt vmcnt(1)
	v_add_f64 v[10:11], v[94:95], v[124:125]
	v_add_f64 v[126:127], v[14:15], v[124:125]
	v_add_f64 v[14:15], v[88:89], v[20:21]
	v_add_f64 v[88:89], v[90:91], v[20:21]
	v_add_f64 v[90:91], v[48:49], v[8:9]
	v_add_co_u32 v8, vcc_lo, v110, v56
	v_add_co_ci_u32_e32 v9, vcc_lo, v111, v57, vcc_lo
	v_add_f64 v[10:11], v[10:11], v[20:21]
	v_add_f64 v[94:95], v[14:15], v[48:49]
	v_add_f64 v[14:15], v[20:21], v[48:49]
	v_add_f64 v[88:89], v[88:89], v[48:49]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[10:11], v[10:11], v[48:49]
	v_add_f64 v[20:21], v[124:125], v[10:11]
	global_load_b128 v[8:11], v[8:9], off
	s_waitcnt vmcnt(0)
	v_add_f64 v[20:21], v[10:11], v[20:21]
	v_add_f64 v[92:93], v[92:93], v[10:11]
	v_add_f64 v[32:33], v[32:33], v[10:11]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[20:21], v[10:11], v[20:21]
	v_add_f64 v[98:99], v[10:11], v[92:93]
	s_delay_alu instid0(VALU_DEP_2)
	v_add_f64 v[20:21], v[40:41], v[20:21]
	v_add_co_u32 v40, vcc_lo, v110, v72
	v_add_co_ci_u32_e32 v41, vcc_lo, v111, v73, vcc_lo
	global_load_b64 v[128:129], v[40:41], off
	s_waitcnt vmcnt(0)
	v_add_f64 v[20:21], v[128:129], v[20:21]
	v_fma_f64 v[40:41], v[10:11], 2.0, v[128:129]
	v_add_f64 v[10:11], v[10:11], v[128:129]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[20:21], v[48:49], v[20:21]
	v_add_f64 v[92:93], v[128:129], v[40:41]
	v_add_f64 v[40:41], v[128:129], v[98:99]
	v_add_f64 v[48:49], v[126:127], v[0:1]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[20:21], v[0:1], v[20:21]
	v_add_f64 v[98:99], v[128:129], v[40:41]
	v_add_f64 v[40:41], v[32:33], v[128:129]
	v_add_f64 v[32:33], v[124:125], v[0:1]
	v_add_f64 v[48:49], v[48:49], v[18:19]
	v_add_f64 v[20:21], v[128:129], v[20:21]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[0:1], v[0:1], v[20:21]
	v_mul_f64 v[0:1], v[0:1], s[4:5]
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[96:97], v[96:97], s[0:1], v[0:1]
	v_add_co_u32 v0, vcc_lo, v122, v28
	v_add_co_ci_u32_e32 v1, vcc_lo, v123, v29, vcc_lo
	v_add_co_u32 v20, vcc_lo, v120, v28
	v_add_co_ci_u32_e32 v21, vcc_lo, v121, v29, vcc_lo
	s_clause 0x1
	global_load_b64 v[0:1], v[0:1], off
	global_load_b64 v[20:21], v[20:21], off
	s_waitcnt vmcnt(1)
	v_add_f64 v[0:1], v[0:1], v[30:31]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f64 v[0:1], v[0:1], v[26:27]
	s_waitcnt vmcnt(0)
	v_add_f64 v[0:1], v[0:1], v[20:21]
	v_add_co_u32 v20, vcc_lo, v102, v72
	v_add_co_ci_u32_e32 v21, vcc_lo, v103, v73, vcc_lo
	global_load_b64 v[26:27], v[20:21], off
	s_waitcnt vmcnt(0)
	v_add_f64 v[0:1], v[0:1], v[26:27]
	v_add_f64 v[30:31], v[94:95], v[26:27]
	v_add_f64 v[94:95], v[98:99], v[26:27]
	v_add_co_u32 v26, vcc_lo, v102, v44
	v_add_co_ci_u32_e32 v27, vcc_lo, v103, v45, vcc_lo
	global_load_b64 v[98:99], v[26:27], off
	s_waitcnt vmcnt(0)
	v_add_f64 v[0:1], v[0:1], v[98:99]
	v_add_f64 v[30:31], v[30:31], v[98:99]
	v_add_f64 v[94:95], v[94:95], v[98:99]
	v_add_co_u32 v98, vcc_lo, v114, v28
	v_add_co_ci_u32_e32 v99, vcc_lo, v115, v29, vcc_lo
	global_load_b64 v[120:121], v[98:99], off
	v_add_co_u32 v98, vcc_lo, 0xfffff000, v50
	v_add_co_ci_u32_e32 v99, vcc_lo, -1, v51, vcc_lo
	global_load_b64 v[98:99], v[98:99], off offset:-32
	v_add_f64 v[94:95], v[94:95], v[18:19]
	s_waitcnt vmcnt(1)
	v_add_f64 v[0:1], v[0:1], v[120:121]
	v_add_f64 v[92:93], v[92:93], v[120:121]
	v_add_f64 v[84:85], v[84:85], v[120:121]
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[0:1], v[0:1], v[98:99]
	v_add_f64 v[92:93], v[92:93], v[98:99]
	v_add_co_u32 v98, vcc_lo, 0xfffff000, v118
	v_add_co_ci_u32_e32 v99, vcc_lo, -1, v119, vcc_lo
	v_add_co_u32 v114, vcc_lo, v112, v28
	v_add_co_ci_u32_e32 v115, vcc_lo, v113, v29, vcc_lo
	global_load_b64 v[98:99], v[98:99], off offset:-32
	s_waitcnt vmcnt(0)
	v_add_f64 v[0:1], v[0:1], v[98:99]
	v_add_f64 v[92:93], v[92:93], v[98:99]
	v_add_co_u32 v98, vcc_lo, v82, v52
	v_add_co_ci_u32_e32 v99, vcc_lo, v83, v53, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[0:1], v[0:1], v[18:19]
	v_add_co_u32 v18, vcc_lo, v98, v72
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v19, vcc_lo, v99, v73, vcc_lo
	global_load_b64 v[18:19], v[18:19], off
	s_waitcnt vmcnt(0)
	v_add_f64 v[82:83], v[86:87], v[18:19]
	v_add_f64 v[86:87], v[90:91], v[18:19]
	v_add_co_u32 v90, vcc_lo, v98, v44
	v_add_co_ci_u32_e32 v91, vcc_lo, v99, v45, vcc_lo
	v_add_f64 v[0:1], v[0:1], v[18:19]
	v_add_f64 v[18:19], v[120:121], v[18:19]
	global_load_b64 v[90:91], v[90:91], off
	s_waitcnt vmcnt(0)
	v_add_f64 v[0:1], v[0:1], v[90:91]
	v_add_f64 v[118:119], v[82:83], v[90:91]
	v_add_f64 v[120:121], v[86:87], v[90:91]
	v_add_f64 v[90:91], v[18:19], v[90:91]
	v_add_f64 v[18:19], v[30:31], v[38:39]
	v_add_f64 v[30:31], v[70:71], v[38:39]
	v_add_f64 v[0:1], v[0:1], v[38:39]
	v_add_f64 v[38:39], v[88:89], v[38:39]
	s_delay_alu instid0(VALU_DEP_4)
	v_add_f64 v[82:83], v[18:19], v[34:35]
	v_add_co_u32 v18, vcc_lo, v108, v72
	v_add_co_ci_u32_e32 v19, vcc_lo, v109, v73, vcc_lo
	v_add_f64 v[86:87], v[30:31], v[34:35]
	global_load_b64 v[30:31], v[18:19], off
	v_add_f64 v[0:1], v[0:1], v[34:35]
	v_add_f64 v[88:89], v[38:39], v[34:35]
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2)
	v_add_f64 v[0:1], v[0:1], v[30:31]
	v_add_f64 v[34:35], v[82:83], v[30:31]
	v_add_f64 v[38:39], v[94:95], v[30:31]
	v_add_co_u32 v30, vcc_lo, v108, v44
	v_add_co_ci_u32_e32 v31, vcc_lo, v109, v45, vcc_lo
	global_load_b64 v[82:83], v[30:31], off
	s_waitcnt vmcnt(0)
	v_add_f64 v[0:1], v[0:1], v[82:83]
	v_add_f64 v[34:35], v[34:35], v[82:83]
	v_add_f64 v[38:39], v[38:39], v[82:83]
	v_add_co_u32 v82, vcc_lo, v116, v28
	v_add_co_ci_u32_e32 v83, vcc_lo, v117, v29, vcc_lo
	global_load_b64 v[94:95], v[82:83], off
	v_add_f64 v[34:35], v[34:35], v[46:47]
	v_add_f64 v[38:39], v[38:39], v[46:47]
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[38:39], v[46:47], v[38:39]
	s_waitcnt vmcnt(0)
	v_add_f64 v[92:93], v[92:93], v[94:95]
	v_add_f64 v[82:83], v[84:85], v[94:95]
	v_add_f64 v[0:1], v[0:1], v[94:95]
	v_add_f64 v[116:117], v[90:91], v[94:95]
	s_delay_alu instid0(VALU_DEP_4)
	v_add_f64 v[84:85], v[92:93], v[4:5]
	v_add_f64 v[92:93], v[34:35], v[42:43]
	v_add_f64 v[34:35], v[42:43], v[38:39]
	v_add_co_u32 v38, vcc_lo, v110, v28
	v_add_co_ci_u32_e32 v39, vcc_lo, v111, v29, vcc_lo
	v_add_f64 v[0:1], v[0:1], v[4:5]
	global_load_b64 v[122:123], v[38:39], off
	v_add_f64 v[90:91], v[4:5], v[84:85]
	v_add_f64 v[84:85], v[14:15], v[46:47]
	v_add_f64 v[34:35], v[42:43], v[34:35]
	v_add_f64 v[0:1], v[0:1], v[46:47]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[94:95], v[0:1], v[42:43]
	v_add_f64 v[0:1], v[84:85], v[42:43]
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[124:125], v[94:95], v[122:123]
	v_add_f64 v[38:39], v[118:119], v[122:123]
	v_add_f64 v[4:5], v[4:5], v[124:125]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[94:95], v[122:123], v[38:39]
	v_add_f64 v[38:39], v[120:121], v[122:123]
	v_add_f64 v[4:5], v[46:47], v[4:5]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[84:85], v[122:123], v[38:39]
	v_add_f64 v[38:39], v[116:117], v[122:123]
	v_add_f64 v[4:5], v[42:43], v[4:5]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[38:39], v[122:123], v[38:39]
	v_add_f64 v[4:5], v[122:123], v[4:5]
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[42:43], v[4:5], s[6:7], v[96:97]
	v_add_co_u32 v4, vcc_lo, 0xffffe000, v66
	v_add_co_ci_u32_e32 v5, vcc_lo, -1, v67, vcc_lo
	s_clause 0x1
	global_load_b64 v[4:5], v[4:5], off offset:-64
	global_load_b64 v[46:47], v[78:79], off offset:32
	s_waitcnt vmcnt(0)
	v_add_f64 v[4:5], v[4:5], v[46:47]
	v_add_co_u32 v46, vcc_lo, 0x2000, v66
	v_add_co_ci_u32_e32 v47, vcc_lo, 0, v67, vcc_lo
	global_load_b64 v[78:79], v[46:47], off offset:64
	s_waitcnt vmcnt(0)
	v_add_f64 v[46:47], v[94:95], v[78:79]
	v_add_f64 v[4:5], v[4:5], v[78:79]
	v_add_f64 v[80:81], v[80:81], v[78:79]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[46:47], v[78:79], v[46:47]
	v_add_f64 v[96:97], v[78:79], v[80:81]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[80:81], v[4:5], v[22:23]
	v_add_f64 v[4:5], v[22:23], v[46:47]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[94:95], v[22:23], v[4:5]
	v_add_f64 v[4:5], v[22:23], v[96:97]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f64 v[46:47], v[22:23], v[4:5]
	v_fma_f64 v[4:5], v[78:79], 2.0, v[22:23]
	v_add_f64 v[4:5], v[22:23], v[4:5]
	v_add_co_u32 v22, vcc_lo, 0xfffff000, v58
	v_add_co_ci_u32_e32 v23, vcc_lo, -1, v59, vcc_lo
	global_load_b64 v[22:23], v[22:23], off offset:-32
	s_waitcnt vmcnt(0)
	v_add_f64 v[78:79], v[80:81], v[22:23]
	v_add_f64 v[22:23], v[92:93], v[22:23]
	v_add_co_u32 v92, vcc_lo, 0xfffff000, v60
	v_add_co_ci_u32_e32 v93, vcc_lo, -1, v61, vcc_lo
	global_load_b64 v[92:93], v[92:93], off offset:-32
	s_waitcnt vmcnt(0)
	v_add_f64 v[78:79], v[78:79], v[92:93]
	v_add_f64 v[92:93], v[22:23], v[92:93]
	v_add_co_u32 v22, vcc_lo, v104, v68
	v_add_co_ci_u32_e32 v23, vcc_lo, v105, v69, vcc_lo
	global_load_b64 v[22:23], v[22:23], off
	v_add_f64 v[92:93], v[92:93], v[16:17]
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[92:93], v[92:93], v[12:13]
	s_waitcnt vmcnt(0)
	v_add_f64 v[78:79], v[78:79], v[22:23]
	v_add_f64 v[90:91], v[90:91], v[22:23]
	v_add_f64 v[86:87], v[86:87], v[22:23]
	v_add_f64 v[88:89], v[88:89], v[22:23]
	v_add_co_u32 v22, vcc_lo, v104, v56
	v_add_co_ci_u32_e32 v23, vcc_lo, v105, v57, vcc_lo
	global_load_b64 v[96:97], v[22:23], off
	s_waitcnt vmcnt(0)
	v_add_f64 v[116:117], v[78:79], v[96:97]
	v_add_f64 v[78:79], v[88:89], v[96:97]
	v_add_co_u32 v88, vcc_lo, 0xfffff000, v114
	v_add_co_ci_u32_e32 v89, vcc_lo, -1, v115, vcc_lo
	v_add_f64 v[22:23], v[90:91], v[96:97]
	v_add_f64 v[86:87], v[86:87], v[96:97]
	global_load_b64 v[88:89], v[88:89], off offset:-32
	s_waitcnt vmcnt(0)
	v_add_f64 v[90:91], v[116:117], v[88:89]
	v_add_f64 v[88:89], v[94:95], v[88:89]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_add_f64 v[94:95], v[90:91], v[16:17]
	v_add_f64 v[16:17], v[84:85], v[16:17]
	v_add_co_u32 v90, vcc_lo, v112, v56
	v_add_co_ci_u32_e32 v91, vcc_lo, v113, v57, vcc_lo
	v_add_f64 v[84:85], v[94:95], v[12:13]
	s_delay_alu instid0(VALU_DEP_4)
	v_add_f64 v[12:13], v[16:17], v[12:13]
	v_add_co_u32 v16, vcc_lo, v98, v28
	v_add_co_ci_u32_e32 v17, vcc_lo, v99, v29, vcc_lo
	global_load_b64 v[16:17], v[16:17], off
	s_waitcnt vmcnt(0)
	v_add_f64 v[94:95], v[4:5], v[16:17]
	v_add_co_u32 v4, vcc_lo, 0xfffff000, v62
	v_add_co_ci_u32_e32 v5, vcc_lo, -1, v63, vcc_lo
	v_add_f64 v[84:85], v[84:85], v[16:17]
	v_add_f64 v[76:77], v[76:77], v[16:17]
	v_add_f64 v[86:87], v[86:87], v[16:17]
	global_load_b64 v[4:5], v[4:5], off offset:-32
	s_waitcnt vmcnt(0)
	v_add_f64 v[16:17], v[84:85], v[4:5]
	v_add_co_u32 v84, vcc_lo, 0xfffff000, v64
	v_add_co_ci_u32_e32 v85, vcc_lo, -1, v65, vcc_lo
	v_add_f64 v[4:5], v[92:93], v[4:5]
	global_load_b64 v[84:85], v[84:85], off offset:-32
	s_waitcnt vmcnt(0)
	v_add_f64 v[16:17], v[16:17], v[84:85]
	v_add_f64 v[4:5], v[4:5], v[84:85]
	v_add_co_u32 v84, vcc_lo, v106, v68
	v_add_co_ci_u32_e32 v85, vcc_lo, v107, v69, vcc_lo
	global_load_b64 v[84:85], v[84:85], off
	s_waitcnt vmcnt(0)
	v_add_f64 v[16:17], v[16:17], v[84:85]
	v_add_f64 v[22:23], v[22:23], v[84:85]
	v_add_f64 v[86:87], v[86:87], v[84:85]
	v_add_f64 v[84:85], v[78:79], v[84:85]
	v_add_co_u32 v78, vcc_lo, v106, v56
	v_add_co_ci_u32_e32 v79, vcc_lo, v107, v57, vcc_lo
	global_load_b64 v[92:93], v[78:79], off
	s_waitcnt vmcnt(0)
	v_add_f64 v[96:97], v[16:17], v[92:93]
	v_add_f64 v[112:113], v[22:23], v[92:93]
	v_add_f64 v[78:79], v[86:87], v[92:93]
	v_add_f64 v[16:17], v[84:85], v[92:93]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[22:23], 0x3fe80000, v[96:97], v[42:43]
	v_fma_f64 v[92:93], v[80:81], s[8:9], v[22:23]
	v_add_co_u32 v22, vcc_lo, 0xffffe000, v58
	v_add_co_ci_u32_e32 v23, vcc_lo, -1, v59, vcc_lo
	v_add_co_u32 v42, vcc_lo, 0xffffe000, v60
	v_add_co_ci_u32_e32 v43, vcc_lo, -1, v61, vcc_lo
	s_clause 0x1
	global_load_b64 v[22:23], v[22:23], off offset:-64
	global_load_b64 v[42:43], v[42:43], off offset:-64
	s_waitcnt vmcnt(0)
	v_add_f64 v[22:23], v[22:23], v[42:43]
	v_add_co_u32 v42, vcc_lo, 0xffffe000, v62
	v_add_co_ci_u32_e32 v43, vcc_lo, -1, v63, vcc_lo
	global_load_b64 v[42:43], v[42:43], off offset:-64
	s_waitcnt vmcnt(0)
	v_add_f64 v[22:23], v[22:23], v[42:43]
	v_add_co_u32 v42, vcc_lo, 0xffffe000, v64
	v_add_co_ci_u32_e32 v43, vcc_lo, -1, v65, vcc_lo
	v_add_co_u32 v80, vcc_lo, v110, v68
	v_add_co_ci_u32_e32 v81, vcc_lo, v111, v69, vcc_lo
	global_load_b64 v[42:43], v[42:43], off offset:-64
	v_add_co_u32 v86, vcc_lo, 0xfffff000, v20
	global_load_b64 v[96:97], v[80:81], off
	v_add_co_ci_u32_e32 v87, vcc_lo, -1, v21, vcc_lo
	global_load_b64 v[86:87], v[86:87], off offset:-32
	s_waitcnt vmcnt(2)
	v_add_f64 v[22:23], v[22:23], v[42:43]
	v_add_f64 v[42:43], v[88:89], v[2:3]
	s_waitcnt vmcnt(1)
	v_add_f64 v[80:81], v[82:83], v[96:97]
	v_add_f64 v[82:83], v[94:95], v[96:97]
	v_add_f64 v[76:77], v[76:77], v[96:97]
	v_add_f64 v[22:23], v[22:23], v[2:3]
	v_add_f64 v[42:43], v[2:3], v[42:43]
	v_add_f64 v[2:3], v[2:3], v[6:7]
	v_add_f64 v[84:85], v[80:81], v[8:9]
	v_add_f64 v[82:83], v[96:97], v[82:83]
	v_add_f64 v[76:77], v[96:97], v[76:77]
	v_add_f64 v[80:81], v[96:97], v[8:9]
	v_add_f64 v[22:23], v[22:23], v[6:7]
	v_add_f64 v[42:43], v[6:7], v[42:43]
	v_add_f64 v[2:3], v[2:3], v[96:97]
	v_add_f64 v[82:83], v[8:9], v[82:83]
	v_add_f64 v[76:77], v[8:9], v[76:77]
	v_add_f64 v[22:23], v[22:23], v[96:97]
	v_add_f64 v[42:43], v[6:7], v[42:43]
	v_add_f64 v[2:3], v[2:3], v[8:9]
	v_add_f64 v[82:83], v[8:9], v[82:83]
	v_add_f64 v[76:77], v[8:9], v[76:77]
	v_add_f64 v[22:23], v[22:23], v[8:9]
	s_waitcnt vmcnt(0)
	v_add_f64 v[42:43], v[42:43], v[86:87]
	s_delay_alu instid0(VALU_DEP_2)
	v_add_f64 v[22:23], v[22:23], v[86:87]
	v_add_co_u32 v86, vcc_lo, 0xfffff000, v26
	v_add_co_ci_u32_e32 v87, vcc_lo, -1, v27, vcc_lo
	global_load_b64 v[86:87], v[86:87], off offset:-32
	s_waitcnt vmcnt(0)
	v_add_f64 v[88:89], v[22:23], v[86:87]
	v_add_co_u32 v22, vcc_lo, v102, v28
	v_add_co_ci_u32_e32 v23, vcc_lo, v103, v29, vcc_lo
	v_add_f64 v[42:43], v[42:43], v[86:87]
	global_load_b64 v[86:87], v[22:23], off
	s_waitcnt vmcnt(0)
	v_add_f64 v[88:89], v[88:89], v[86:87]
	v_add_f64 v[94:95], v[112:113], v[86:87]
	v_add_f64 v[12:13], v[12:13], v[86:87]
	v_add_co_u32 v86, vcc_lo, v104, v72
	v_add_co_ci_u32_e32 v87, vcc_lo, v105, v73, vcc_lo
	global_load_b64 v[86:87], v[86:87], off
	s_waitcnt vmcnt(0)
	v_add_f64 v[88:89], v[88:89], v[86:87]
	v_add_f64 v[76:77], v[76:77], v[86:87]
	v_add_f64 v[84:85], v[84:85], v[86:87]
	v_add_f64 v[82:83], v[82:83], v[86:87]
	v_add_co_u32 v86, vcc_lo, v104, v44
	v_add_co_ci_u32_e32 v87, vcc_lo, v105, v45, vcc_lo
	global_load_b64 v[86:87], v[86:87], off
	s_waitcnt vmcnt(0)
	v_add_f64 v[88:89], v[88:89], v[86:87]
	v_add_f64 v[76:77], v[76:77], v[86:87]
	v_add_f64 v[84:85], v[84:85], v[86:87]
	v_add_f64 v[86:87], v[82:83], v[86:87]
	v_add_co_u32 v82, vcc_lo, 0x2000, v58
	v_add_co_ci_u32_e32 v83, vcc_lo, 0, v59, vcc_lo
	global_load_b64 v[82:83], v[82:83], off offset:64
	s_waitcnt vmcnt(0)
	v_add_f64 v[88:89], v[88:89], v[82:83]
	v_add_f64 v[48:49], v[48:49], v[82:83]
	v_add_f64 v[46:47], v[46:47], v[82:83]
	v_add_f64 v[40:41], v[40:41], v[82:83]
	v_add_co_u32 v82, vcc_lo, 0x2000, v60
	v_add_co_ci_u32_e32 v83, vcc_lo, 0, v61, vcc_lo
	global_load_b64 v[82:83], v[82:83], off offset:64
	s_waitcnt vmcnt(0)
	v_add_f64 v[104:105], v[40:41], v[82:83]
	v_add_co_u32 v40, vcc_lo, 0xfffff000, v24
	v_add_co_ci_u32_e32 v41, vcc_lo, -1, v25, vcc_lo
	v_add_f64 v[88:89], v[88:89], v[82:83]
	v_add_f64 v[102:103], v[46:47], v[82:83]
	v_add_f64 v[48:49], v[48:49], v[82:83]
	global_load_b64 v[40:41], v[40:41], off offset:-32
	s_waitcnt vmcnt(0)
	v_add_f64 v[46:47], v[88:89], v[40:41]
	v_add_f64 v[40:41], v[76:77], v[40:41]
	v_add_co_u32 v76, vcc_lo, 0xfffff000, v90
	v_add_co_ci_u32_e32 v77, vcc_lo, -1, v91, vcc_lo
	global_load_b64 v[76:77], v[76:77], off offset:-32
	s_waitcnt vmcnt(0)
	v_add_f64 v[46:47], v[46:47], v[76:77]
	v_add_f64 v[76:77], v[40:41], v[76:77]
	v_add_co_u32 v40, vcc_lo, v98, v68
	v_add_co_ci_u32_e32 v41, vcc_lo, v99, v69, vcc_lo
	global_load_b64 v[40:41], v[40:41], off
	s_waitcnt vmcnt(0)
	v_add_f64 v[46:47], v[46:47], v[40:41]
	v_add_f64 v[48:49], v[48:49], v[40:41]
	v_add_f64 v[82:83], v[84:85], v[40:41]
	v_add_f64 v[40:41], v[74:75], v[40:41]
	v_add_co_u32 v74, vcc_lo, v98, v56
	v_add_co_ci_u32_e32 v75, vcc_lo, v99, v57, vcc_lo
	global_load_b64 v[74:75], v[74:75], off
	s_waitcnt vmcnt(0)
	v_add_f64 v[98:99], v[82:83], v[74:75]
	v_add_f64 v[82:83], v[40:41], v[74:75]
	v_add_co_u32 v40, vcc_lo, 0xfffff000, v18
	v_add_co_ci_u32_e32 v41, vcc_lo, -1, v19, vcc_lo
	v_add_f64 v[46:47], v[46:47], v[74:75]
	v_add_f64 v[88:89], v[48:49], v[74:75]
	global_load_b64 v[40:41], v[40:41], off offset:-32
	s_waitcnt vmcnt(0)
	v_add_f64 v[46:47], v[46:47], v[40:41]
	v_add_f64 v[40:41], v[42:43], v[40:41]
	v_add_co_u32 v42, vcc_lo, 0xfffff000, v30
	v_add_co_ci_u32_e32 v43, vcc_lo, -1, v31, vcc_lo
	global_load_b64 v[42:43], v[42:43], off offset:-32
	s_waitcnt vmcnt(0)
	v_add_f64 v[84:85], v[40:41], v[42:43]
	v_add_co_u32 v40, vcc_lo, v108, v28
	v_add_co_ci_u32_e32 v41, vcc_lo, v109, v29, vcc_lo
	v_add_f64 v[46:47], v[46:47], v[42:43]
	global_load_b64 v[42:43], v[40:41], off
	s_waitcnt vmcnt(0)
	v_add_f64 v[48:49], v[12:13], v[42:43]
	v_add_co_u32 v12, vcc_lo, v106, v72
	v_add_co_ci_u32_e32 v13, vcc_lo, v107, v73, vcc_lo
	v_add_f64 v[74:75], v[46:47], v[42:43]
	v_add_f64 v[46:47], v[94:95], v[42:43]
	global_load_b64 v[12:13], v[12:13], off
	s_waitcnt vmcnt(0)
	v_add_f64 v[72:73], v[76:77], v[12:13]
	v_add_co_u32 v76, vcc_lo, v106, v44
	v_add_co_ci_u32_e32 v77, vcc_lo, v107, v45, vcc_lo
	v_add_f64 v[42:43], v[74:75], v[12:13]
	v_add_f64 v[74:75], v[98:99], v[12:13]
	v_add_f64 v[12:13], v[86:87], v[12:13]
	global_load_b64 v[76:77], v[76:77], off
	s_waitcnt vmcnt(0)
	v_add_f64 v[94:95], v[42:43], v[76:77]
	v_add_f64 v[42:43], v[72:73], v[76:77]
	v_add_f64 v[86:87], v[74:75], v[76:77]
	v_add_f64 v[76:77], v[12:13], v[76:77]
	v_add_co_u32 v12, vcc_lo, 0x2000, v62
	v_add_co_ci_u32_e32 v13, vcc_lo, 0, v63, vcc_lo
	global_load_b64 v[12:13], v[12:13], off offset:64
	s_waitcnt vmcnt(0)
	v_add_f64 v[74:75], v[88:89], v[12:13]
	v_add_co_u32 v88, vcc_lo, 0x2000, v64
	v_add_co_ci_u32_e32 v89, vcc_lo, 0, v65, vcc_lo
	v_add_f64 v[72:73], v[94:95], v[12:13]
	v_add_f64 v[94:95], v[102:103], v[12:13]
	v_add_f64 v[12:13], v[104:105], v[12:13]
	global_load_b64 v[98:99], v[88:89], off offset:64
	s_waitcnt vmcnt(0)
	v_add_f64 v[102:103], v[72:73], v[98:99]
	v_add_f64 v[72:73], v[12:13], v[98:99]
	v_add_f64 v[88:89], v[74:75], v[98:99]
	v_add_f64 v[74:75], v[94:95], v[98:99]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f64 v[12:13], v[102:103], s[10:11], v[92:93]
	v_add_nc_u32_e32 v92, 3, v101
	v_mad_u64_u32 v[96:97], null, 0x1020, v92, v[36:37]
	s_delay_alu instid0(VALU_DEP_3)
	v_fma_f64 v[12:13], v[2:3], s[12:13], v[12:13]
	v_add_co_u32 v2, vcc_lo, 0x3000, v66
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v67, vcc_lo
	global_load_b64 v[8:9], v[2:3], off offset:96
	s_waitcnt vmcnt(0)
	v_add_f64 v[6:7], v[88:89], v[8:9]
	v_add_co_u32 v88, vcc_lo, v96, v56
	v_add_co_ci_u32_e32 v89, vcc_lo, v97, v57, vcc_lo
	v_add_f64 v[34:35], v[34:35], v[8:9]
	v_add_f64 v[38:39], v[38:39], v[8:9]
	global_load_b128 v[92:95], v[88:89], off
	v_add_f64 v[34:35], v[8:9], v[34:35]
	v_add_f64 v[38:39], v[8:9], v[38:39]
	v_add_f64 v[8:9], v[32:33], v[8:9]
	v_add_co_u32 v32, vcc_lo, v96, v68
	v_add_co_ci_u32_e32 v33, vcc_lo, v97, v69, vcc_lo
	s_waitcnt vmcnt(0)
	v_add_f64 v[98:99], v[6:7], v[94:95]
	v_add_f64 v[6:7], v[94:95], v[34:35]
	v_add_f64 v[34:35], v[94:95], v[38:39]
	global_load_b64 v[38:39], v[32:33], off
	v_add_f64 v[8:9], v[8:9], v[94:95]
	v_add_f64 v[6:7], v[94:95], v[6:7]
	v_add_f64 v[88:89], v[94:95], v[34:35]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[8:9], v[8:9], s[8:9]
	v_fma_f64 v[8:9], 0x3fe80000, v[98:99], v[8:9]
	s_waitcnt vmcnt(0)
	v_add_f64 v[32:33], v[84:85], v[38:39]
	v_add_co_u32 v84, vcc_lo, 0x3000, v20
	v_add_co_ci_u32_e32 v85, vcc_lo, 0, v21, vcc_lo
	v_add_f64 v[82:83], v[82:83], v[38:39]
	v_add_f64 v[34:35], v[86:87], v[38:39]
	global_load_b64 v[84:85], v[84:85], off offset:96
	v_add_f64 v[32:33], v[32:33], v[92:93]
	v_add_f64 v[82:83], v[38:39], v[82:83]
	v_add_f64 v[34:35], v[34:35], v[92:93]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[32:33], v[38:39], v[32:33]
	v_add_f64 v[82:83], v[92:93], v[82:83]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[32:33], v[92:93], v[32:33]
	v_add_f64 v[82:83], v[92:93], v[82:83]
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[32:33], v[84:85], v[32:33]
	v_add_f64 v[34:35], v[34:35], v[84:85]
	v_add_f64 v[82:83], v[84:85], v[82:83]
	v_add_co_u32 v84, vcc_lo, 0x3000, v26
	v_add_co_ci_u32_e32 v85, vcc_lo, 0, v27, vcc_lo
	global_load_b64 v[84:85], v[84:85], off offset:96
	s_waitcnt vmcnt(0)
	v_add_f64 v[96:97], v[84:85], v[82:83]
	v_add_co_u32 v82, vcc_lo, 0x3060, v24
	v_add_co_ci_u32_e32 v83, vcc_lo, 0, v25, vcc_lo
	v_add_f64 v[86:87], v[84:85], v[32:33]
	v_add_co_u32 v32, vcc_lo, 0x3000, v24
	v_add_co_ci_u32_e32 v33, vcc_lo, 0, v25, vcc_lo
	v_add_f64 v[94:95], v[34:35], v[84:85]
	s_clause 0x2
	global_load_b128 v[32:35], v[32:33], off offset:96
	global_load_b128 v[82:85], v[82:83], off offset:16
	global_load_b64 v[2:3], v[2:3], off offset:112
	s_waitcnt vmcnt(2)
	v_add_f64 v[98:99], v[78:79], v[34:35]
	v_add_co_u32 v78, vcc_lo, 0x3000, v18
	v_add_co_ci_u32_e32 v79, vcc_lo, 0, v19, vcc_lo
	v_add_f64 v[86:87], v[34:35], v[86:87]
	v_add_f64 v[34:35], v[34:35], v[96:97]
	global_load_b64 v[78:79], v[78:79], off offset:96
	s_waitcnt vmcnt(0)
	v_add_f64 v[86:87], v[78:79], v[86:87]
	v_add_f64 v[94:95], v[94:95], v[78:79]
	v_add_f64 v[34:35], v[78:79], v[34:35]
	v_add_co_u32 v78, vcc_lo, 0x3000, v30
	v_add_co_ci_u32_e32 v79, vcc_lo, 0, v31, vcc_lo
	global_load_b64 v[78:79], v[78:79], off offset:96
	s_waitcnt vmcnt(0)
	v_add_f64 v[86:87], v[78:79], v[86:87]
	v_add_f64 v[94:95], v[94:95], v[78:79]
	v_add_f64 v[78:79], v[78:79], v[34:35]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)
	v_fma_f64 v[34:35], v[86:87], s[4:5], v[8:9]
	v_add_f64 v[8:9], v[80:81], v[38:39]
	v_add_f64 v[38:39], v[46:47], v[2:3]
	v_add_f64 v[46:47], v[48:49], v[2:3]
	v_add_f64 v[48:49], v[76:77], v[2:3]
	v_add_f64 v[8:9], v[8:9], v[92:93]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[46:47], v[2:3], v[46:47]
	v_add_f64 v[48:49], v[2:3], v[48:49]
	v_add_f64 v[2:3], v[2:3], v[38:39]
	v_add_co_u32 v38, vcc_lo, 0x3000, v50
	v_add_co_ci_u32_e32 v39, vcc_lo, 0, v51, vcc_lo
	global_load_b64 v[38:39], v[38:39], off offset:96
	s_waitcnt vmcnt(0)
	v_add_f64 v[2:3], v[38:39], v[2:3]
	v_add_f64 v[46:47], v[38:39], v[46:47]
	v_add_f64 v[48:49], v[38:39], v[48:49]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[2:3], v[84:85], v[2:3]
	v_add_f64 v[38:39], v[84:85], v[46:47]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[48:49], v[84:85], v[48:49]
	v_fma_f64 v[2:3], v[2:3], s[0:1], v[34:35]
	v_add_co_u32 v34, vcc_lo, 0x3000, v22
	v_add_co_ci_u32_e32 v35, vcc_lo, 0, v23, vcc_lo
	global_load_b64 v[34:35], v[34:35], off offset:96
	s_waitcnt vmcnt(0)
	v_add_f64 v[42:43], v[42:43], v[34:35]
	v_add_f64 v[46:47], v[74:75], v[34:35]
	v_add_f64 v[16:17], v[16:17], v[34:35]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_add_f64 v[34:35], v[42:43], v[32:33]
	v_add_f64 v[42:43], v[94:95], v[32:33]
	v_add_f64 v[32:33], v[72:73], v[32:33]
	v_add_f64 v[34:35], v[34:35], v[82:83]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[42:43], v[42:43], v[82:83]
	v_add_f64 v[74:75], v[32:33], v[82:83]
	v_add_co_u32 v32, vcc_lo, 0x3000, v40
	v_add_co_ci_u32_e32 v33, vcc_lo, 0, v41, vcc_lo
	global_load_b64 v[32:33], v[32:33], off offset:96
	s_waitcnt vmcnt(0)
	v_add_f64 v[76:77], v[34:35], v[32:33]
	v_add_f64 v[34:35], v[16:17], v[32:33]
	v_add_co_u32 v16, vcc_lo, 0x3000, v58
	v_add_co_ci_u32_e32 v17, vcc_lo, 0, v59, vcc_lo
	v_add_f64 v[72:73], v[46:47], v[32:33]
	v_add_co_u32 v46, vcc_lo, 0x3000, v60
	global_load_b64 v[16:17], v[16:17], off offset:96
	v_add_co_ci_u32_e32 v47, vcc_lo, 0, v61, vcc_lo
	global_load_b64 v[46:47], v[46:47], off offset:96
	v_fma_f64 v[2:3], v[76:77], s[6:7], v[2:3]
	s_waitcnt vmcnt(1)
	v_add_f64 v[4:5], v[4:5], v[16:17]
	v_add_f64 v[32:33], v[98:99], v[16:17]
	v_add_f64 v[16:17], v[88:89], v[16:17]
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[4:5], v[4:5], v[46:47]
	v_add_f64 v[32:33], v[32:33], v[46:47]
	s_delay_alu instid0(VALU_DEP_3)
	v_add_f64 v[16:17], v[16:17], v[46:47]
	v_add_co_u32 v46, vcc_lo, 0x3000, v62
	v_add_co_ci_u32_e32 v47, vcc_lo, 0, v63, vcc_lo
	global_load_b64 v[46:47], v[46:47], off offset:96
	s_waitcnt vmcnt(0)
	v_add_f64 v[4:5], v[4:5], v[46:47]
	v_add_f64 v[32:33], v[32:33], v[46:47]
	v_add_f64 v[16:17], v[16:17], v[46:47]
	v_add_co_u32 v46, vcc_lo, 0x3000, v64
	v_add_co_ci_u32_e32 v47, vcc_lo, 0, v65, vcc_lo
	v_add_co_u32 v76, vcc_lo, 0x4000, v66
	v_add_co_ci_u32_e32 v77, vcc_lo, 0, v67, vcc_lo
	global_load_b64 v[46:47], v[46:47], off offset:96
	s_waitcnt vmcnt(0)
	v_add_f64 v[4:5], v[4:5], v[46:47]
	v_add_f64 v[32:33], v[32:33], v[46:47]
	v_add_f64 v[46:47], v[16:17], v[46:47]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_fma_f64 v[2:3], v[4:5], s[10:11], v[2:3]
	global_load_b64 v[4:5], v[76:77], off offset:128
	v_fma_f64 v[16:17], v[0:1], s[12:13], v[2:3]
	v_add_nc_u32_e32 v2, 4, v101
	v_mad_u64_u32 v[80:81], null, 0x1020, v2, v[36:37]
	s_waitcnt vmcnt(0)
	v_add_f64 v[0:1], v[48:49], v[4:5]
	v_add_f64 v[32:33], v[32:33], v[4:5]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[48:49], v[4:5], v[0:1]
	v_add_co_u32 v0, vcc_lo, v80, v56
	v_add_co_ci_u32_e32 v1, vcc_lo, v81, v57, vcc_lo
	v_add_f64 v[4:5], v[70:71], v[4:5]
	global_load_b128 v[0:3], v[0:1], off
	s_waitcnt vmcnt(0)
	v_add_f64 v[82:83], v[32:33], v[2:3]
	v_add_f64 v[32:33], v[2:3], v[48:49]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[48:49], 0x3fe80000, v[82:83]
	v_add_f64 v[32:33], v[2:3], v[32:33]
	v_add_f64 v[2:3], v[4:5], v[2:3]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[8:9], v[8:9], s[12:13], v[48:49]
	v_fma_f64 v[70:71], v[2:3], s[8:9], v[8:9]
	v_add_co_u32 v2, vcc_lo, v80, v68
	v_add_co_ci_u32_e32 v3, vcc_lo, v81, v69, vcc_lo
	v_add_co_u32 v4, vcc_lo, 0x4000, v20
	v_add_co_ci_u32_e32 v5, vcc_lo, 0, v21, vcc_lo
	s_clause 0x1
	global_load_b64 v[48:49], v[2:3], off
	global_load_b64 v[20:21], v[4:5], off offset:128
	v_add_co_u32 v4, vcc_lo, 0x4000, v26
	v_add_co_ci_u32_e32 v5, vcc_lo, 0, v27, vcc_lo
	global_load_b64 v[26:27], v[4:5], off offset:128
	s_waitcnt vmcnt(2)
	v_add_f64 v[2:3], v[6:7], v[48:49]
	v_add_co_u32 v6, vcc_lo, 0x4080, v24
	v_add_co_ci_u32_e32 v7, vcc_lo, 0, v25, vcc_lo
	v_add_f64 v[14:15], v[14:15], v[48:49]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[2:3], v[2:3], v[0:1]
	v_add_f64 v[2:3], v[48:49], v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f64 v[2:3], v[0:1], v[2:3]
	s_waitcnt vmcnt(1)
	v_add_f64 v[2:3], v[20:21], v[2:3]
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[68:69], v[26:27], v[2:3]
	v_add_co_u32 v2, vcc_lo, 0x4000, v24
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v25, vcc_lo
	s_clause 0x1
	global_load_b128 v[2:5], v[2:3], off offset:128
	global_load_b128 v[6:9], v[6:7], off offset:16
	v_add_co_u32 v18, vcc_lo, 0x4000, v18
	v_add_co_ci_u32_e32 v19, vcc_lo, 0, v19, vcc_lo
	v_add_co_u32 v30, vcc_lo, 0x4000, v30
	v_add_co_ci_u32_e32 v31, vcc_lo, 0, v31, vcc_lo
	global_load_b64 v[18:19], v[18:19], off offset:128
	v_add_co_u32 v50, vcc_lo, 0x4000, v50
	global_load_b64 v[30:31], v[30:31], off offset:128
	v_add_co_ci_u32_e32 v51, vcc_lo, 0, v51, vcc_lo
	global_load_b64 v[50:51], v[50:51], off offset:128
	s_waitcnt vmcnt(4)
	v_add_f64 v[68:69], v[4:5], v[68:69]
	v_add_f64 v[4:5], v[74:75], v[4:5]
	global_load_b64 v[74:75], v[76:77], off offset:144
	s_waitcnt vmcnt(3)
	v_add_f64 v[68:69], v[18:19], v[68:69]
	s_waitcnt vmcnt(2)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[68:69], v[30:31], v[68:69]
	v_fma_f64 v[70:71], v[68:69], s[4:5], v[70:71]
	v_add_f64 v[68:69], v[14:15], v[0:1]
	s_waitcnt vmcnt(0)
	v_add_f64 v[14:15], v[72:73], v[74:75]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[14:15], v[74:75], v[14:15]
	v_add_f64 v[14:15], v[50:51], v[14:15]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[14:15], v[8:9], v[14:15]
	v_fma_f64 v[14:15], v[14:15], s[0:1], v[70:71]
	v_add_f64 v[70:71], v[78:79], v[74:75]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[70:71], v[74:75], v[70:71]
	v_add_f64 v[50:51], v[50:51], v[70:71]
	v_add_co_u32 v70, vcc_lo, 0x5000, v22
	v_add_co_ci_u32_e32 v71, vcc_lo, 0, v23, vcc_lo
	v_add_co_u32 v24, vcc_lo, 0x5000, v24
	v_add_co_ci_u32_e32 v25, vcc_lo, 0, v25, vcc_lo
	s_clause 0x1
	global_load_b64 v[70:71], v[70:71], off offset:160
	global_load_b64 v[24:25], v[24:25], off offset:160
	v_add_f64 v[8:9], v[8:9], v[50:51]
	v_add_nc_u32_e32 v50, 5, v101
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f64 v[8:9], v[70:71], v[8:9]
	s_waitcnt vmcnt(0)
	v_add_f64 v[8:9], v[24:25], v[8:9]
	v_add_co_u32 v24, vcc_lo, 0x5000, v90
	v_add_co_ci_u32_e32 v25, vcc_lo, 0, v91, vcc_lo
	global_load_b64 v[24:25], v[24:25], off offset:160
	s_waitcnt vmcnt(0)
	v_add_f64 v[8:9], v[24:25], v[8:9]
	v_add_co_u32 v24, vcc_lo, 0x5000, v40
	v_add_co_ci_u32_e32 v25, vcc_lo, 0, v41, vcc_lo
	global_load_b64 v[24:25], v[24:25], off offset:160
	s_waitcnt vmcnt(0)
	v_add_f64 v[8:9], v[24:25], v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[8:9], v[8:9], s[6:7]
	v_fma_f64 v[24:25], v[68:69], s[12:13], v[8:9]
	v_add_co_u32 v8, vcc_lo, 0x4000, v22
	v_add_co_ci_u32_e32 v9, vcc_lo, 0, v23, vcc_lo
	global_load_b64 v[8:9], v[8:9], off offset:128
	s_waitcnt vmcnt(0)
	v_add_f64 v[22:23], v[38:39], v[8:9]
	v_add_co_u32 v38, vcc_lo, 0x4000, v40
	v_add_co_ci_u32_e32 v39, vcc_lo, 0, v41, vcc_lo
	v_add_f64 v[8:9], v[46:47], v[8:9]
	global_load_b64 v[38:39], v[38:39], off offset:128
	v_add_f64 v[22:23], v[22:23], v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f64 v[22:23], v[22:23], v[6:7]
	s_waitcnt vmcnt(0)
	v_add_f64 v[22:23], v[22:23], v[38:39]
	v_add_f64 v[8:9], v[8:9], v[38:39]
	s_delay_alu instid0(VALU_DEP_2)
	v_fma_f64 v[14:15], v[22:23], s[6:7], v[14:15]
	v_add_co_u32 v22, vcc_lo, 0x4000, v58
	v_add_co_ci_u32_e32 v23, vcc_lo, 0, v59, vcc_lo
	global_load_b64 v[22:23], v[22:23], off offset:128
	s_waitcnt vmcnt(0)
	v_add_f64 v[38:39], v[42:43], v[22:23]
	v_add_f64 v[4:5], v[4:5], v[22:23]
	v_add_co_u32 v22, vcc_lo, 0x4000, v60
	v_add_co_ci_u32_e32 v23, vcc_lo, 0, v61, vcc_lo
	global_load_b64 v[22:23], v[22:23], off offset:128
	s_waitcnt vmcnt(0)
	v_add_f64 v[38:39], v[38:39], v[22:23]
	v_add_f64 v[4:5], v[4:5], v[22:23]
	v_add_co_u32 v22, vcc_lo, 0x4000, v62
	v_add_co_ci_u32_e32 v23, vcc_lo, 0, v63, vcc_lo
	global_load_b64 v[22:23], v[22:23], off offset:128
	s_waitcnt vmcnt(0)
	v_add_f64 v[38:39], v[38:39], v[22:23]
	v_add_f64 v[4:5], v[4:5], v[22:23]
	v_add_co_u32 v22, vcc_lo, 0x4000, v64
	v_add_co_ci_u32_e32 v23, vcc_lo, 0, v65, vcc_lo
	global_load_b64 v[22:23], v[22:23], off offset:128
	s_waitcnt vmcnt(0)
	v_add_f64 v[38:39], v[38:39], v[22:23]
	v_add_f64 v[22:23], v[4:5], v[22:23]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f64 v[4:5], v[38:39], s[10:11], v[14:15]
	v_add_f64 v[14:15], v[34:35], v[20:21]
	v_add_f64 v[14:15], v[14:15], v[26:27]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[2:3], v[14:15], v[2:3]
	v_add_f64 v[2:3], v[2:3], v[6:7]
	v_add_co_u32 v6, vcc_lo, 0x5000, v58
	v_add_co_ci_u32_e32 v7, vcc_lo, 0, v59, vcc_lo
	global_load_b64 v[6:7], v[6:7], off offset:160
	v_add_f64 v[2:3], v[18:19], v[2:3]
	v_mad_u64_u32 v[18:19], null, 0x1020, v50, v[36:37]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f64 v[2:3], v[30:31], v[2:3]
	s_waitcnt vmcnt(0)
	v_add_f64 v[2:3], v[2:3], v[6:7]
	v_add_co_u32 v6, vcc_lo, 0x5000, v60
	v_add_co_ci_u32_e32 v7, vcc_lo, 0, v61, vcc_lo
	global_load_b64 v[6:7], v[6:7], off offset:160
	s_waitcnt vmcnt(0)
	v_add_f64 v[2:3], v[2:3], v[6:7]
	v_add_co_u32 v6, vcc_lo, 0x5000, v62
	v_add_co_ci_u32_e32 v7, vcc_lo, 0, v63, vcc_lo
	global_load_b64 v[6:7], v[6:7], off offset:160
	s_waitcnt vmcnt(0)
	v_add_f64 v[2:3], v[2:3], v[6:7]
	v_add_co_u32 v6, vcc_lo, 0x5000, v64
	v_add_co_ci_u32_e32 v7, vcc_lo, 0, v65, vcc_lo
	global_load_b64 v[6:7], v[6:7], off offset:160
	s_waitcnt vmcnt(0)
	v_add_f64 v[2:3], v[2:3], v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[2:3], v[48:49], v[2:3]
	v_add_f64 v[0:1], v[0:1], v[2:3]
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[2:3], v[0:1], s[10:11], v[24:25]
	v_add_co_u32 v0, vcc_lo, 0x5000, v66
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v67, vcc_lo
	v_add_co_u32 v20, vcc_lo, v18, v44
	v_add_co_ci_u32_e32 v21, vcc_lo, v19, v45, vcc_lo
	s_clause 0x2
	global_load_b64 v[6:7], v[0:1], off offset:160
	global_load_b64 v[20:21], v[20:21], off
	global_load_b64 v[0:1], v[0:1], off offset:176
	s_waitcnt vmcnt(2)
	v_add_f64 v[14:15], v[22:23], v[6:7]
	v_add_f64 v[6:7], v[10:11], v[6:7]
	s_waitcnt vmcnt(0)
	v_add_f64 v[0:1], v[8:9], v[0:1]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[14:15], v[14:15], v[20:21]
	v_add_f64 v[6:7], v[6:7], v[20:21]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[2:3], 0x3fe80000, v[14:15], v[2:3]
	v_fma_f64 v[2:3], v[6:7], s[8:9], v[2:3]
	v_add_co_u32 v6, vcc_lo, v18, v56
	v_add_co_ci_u32_e32 v7, vcc_lo, v19, v57, vcc_lo
	global_load_b64 v[6:7], v[6:7], off
	s_waitcnt vmcnt(0)
	v_add_f64 v[6:7], v[32:33], v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[2:3], v[6:7], s[4:5], v[2:3]
	v_fma_f64 v[0:1], v[0:1], s[0:1], v[2:3]
	v_mad_u64_u32 v[2:3], null, 0x208080, v100, s[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v6, vcc_lo, v2, v54
	v_add_co_ci_u32_e32 v7, vcc_lo, v3, v55, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v6, vcc_lo, v6, v28
	v_add_co_ci_u32_e32 v7, vcc_lo, v7, v29, vcc_lo
	v_add_co_u32 v2, vcc_lo, v2, v52
	v_add_co_ci_u32_e32 v3, vcc_lo, v3, v53, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, v2, v28
	v_add_co_ci_u32_e32 v3, vcc_lo, v3, v29, vcc_lo
	s_clause 0x1
	global_store_b64 v[6:7], v[12:13], off
	global_store_b64 v[2:3], v[16:17], off
	v_add_co_u32 v2, vcc_lo, 0x2000, v6
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v7, vcc_lo
	global_store_b64 v[2:3], v[4:5], off offset:64
	v_add_co_u32 v2, vcc_lo, 0x3000, v6
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v7, vcc_lo
	global_store_b64 v[2:3], v[0:1], off offset:96
.LBB0_3:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z8j3d125ptPdS_i
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 130
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z8j3d125ptPdS_i, .Lfunc_end0-_Z8j3d125ptPdS_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 8308
; NumSgprs: 18
; NumVgprs: 130
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 16
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 130
; Occupancy: 10
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .actual_access:  read_only
        .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .actual_access:  write_only
        .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z8j3d125ptPdS_i
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z8j3d125ptPdS_i.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     130
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
