# include <cuda.h>
# include <cuda_runtime.h>
extern "C"
unsigned char * convolutionGPU(unsigned char * rowdata, int width, int height, signed char * kernell, int kernelSize, int nchann);

__global__ void convolute_1PixelGPU(unsigned char * data_dev, unsigned char * convData_dev, int width, int height, signed char * kernellDev, int kernelSize, int nchann){
    int posThread = blockIdx.x*blockDim.x + threadIdx.x;
    if(posThread < width*height*nchann){
        //Compute the sum of the kernell elements
        int sumKernell = 0;
        for(int i = 0; i < kernelSize*kernelSize; i++)
            sumKernell += kernellDev[i];
        sumKernell = (sumKernell <= 0) ? 1: sumKernell;

        // Start to convolute:
        int acumm = 0;
        int midSZ = (kernelSize - 1)/2;
        for(int ky = 0; ky < kernelSize; ky++){
            for(int kx = 0; kx < kernelSize; kx++){
                int pdata = posThread + nchann*width*(ky - midSZ) - midSZ*nchann + kx*nchann;
                if(pdata > 0 && pdata < width*height*nchann)
                    acumm += data_dev[pdata]*kernellDev[kx + ky*kernelSize];
            }
        }
        int ans = acumm/sumKernell;
        if(ans > 255)
            ans = 255;
        if(ans < 0)
            ans = 0;
        convData_dev[posThread] =(unsigned char) ans;
    }
}

unsigned char * convolutionGPU(unsigned char * rowdata, int width, int height, signed char * kernell, int kernelSize, int nchann){
    int size = nchann*width*height;
    unsigned char * convolutedData = new unsigned char[size];
    unsigned char * dataDev;
    unsigned char * convDataDev;
    signed char * kernellDev;

    cudaMalloc((void**)&dataDev, size*sizeof(unsigned char));
    cudaMalloc((void**)&convDataDev, size*sizeof(unsigned char));
    cudaMalloc((void**)&kernellDev, kernelSize*sizeof(signed char));
    cudaMemcpy(dataDev, rowdata, size*sizeof(unsigned char), cudaMemcpyHostToDevice);
    cudaMemcpy(kernellDev, kernell, kernelSize*sizeof(signed char), cudaMemcpyHostToDevice);


    int nThreads = 1024;
    int nBlocks = (size % nThreads > 0)? size/nThreads + 1: size/nThreads;
    convolute_1PixelGPU<<<nBlocks, nThreads>>>(dataDev, convDataDev, width, height, kernellDev, kernelSize, nchann);
    cudaMemcpy(convolutedData, convDataDev, size*sizeof(unsigned char), cudaMemcpyDeviceToHost);
    cudaFree(dataDev);
    cudaFree(convDataDev);
    cudaFree(kernellDev);
    return convolutedData;
}
int main(){

}

	.file	"tmpxft_003177f0_00000000-6_convolution.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2012:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2012:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2009:
	.cfi_startproc
	endbr64
	xorl	%eax, %eax
	ret
	.cfi_endproc
.LFE2009:
	.size	main, .-main
	.text
	.globl	_Z47__device_stub__Z19convolute_1PixelGPUPhS_iiPaiiPhS_iiPaii
	.type	_Z47__device_stub__Z19convolute_1PixelGPUPhS_iiPaiiPhS_iiPaii, @function
_Z47__device_stub__Z19convolute_1PixelGPUPhS_iiPaiiPhS_iiPaii:
.LFB2034:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movl	%edx, 28(%rsp)
	leaq	48(%rsp), %rdx
	movl	%ecx, 24(%rsp)
	leaq	56(%rsp), %rcx
	movq	%r8, 16(%rsp)
	movl	%r9d, 12(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 112(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	28(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	192(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L3
	pushq	56(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z19convolute_1PixelGPUPhS_iiPaii(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 208
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L3:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L5
	call	__stack_chk_fail@PLT
.L5:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2034:
	.size	_Z47__device_stub__Z19convolute_1PixelGPUPhS_iiPaiiPhS_iiPaii, .-_Z47__device_stub__Z19convolute_1PixelGPUPhS_iiPaiiPhS_iiPaii
	.globl	_Z19convolute_1PixelGPUPhS_iiPaii
	.type	_Z19convolute_1PixelGPUPhS_iiPaii, @function
_Z19convolute_1PixelGPUPhS_iiPaii:
.LFB2035:
	.cfi_startproc
	endbr64
	jmp	_Z47__device_stub__Z19convolute_1PixelGPUPhS_iiPaiiPhS_iiPaii
	.cfi_endproc
.LFE2035:
	.size	_Z19convolute_1PixelGPUPhS_iiPaii, .-_Z19convolute_1PixelGPUPhS_iiPaii
	.globl	convolutionGPU
	.type	convolutionGPU, @function
convolutionGPU:
.LFB2008:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movslq	%r8d, %r15
	movl	%r9d, %r8d
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	imull	%esi, %r8d
	movq	%rdi, %r14
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movl	%r9d, %r13d
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movq	%r15, %r12
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	imull	%edx, %r8d
	movl	%edx, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movl	%esi, %ebx
	subq	$104, %rsp
	.cfi_def_cfa_offset 160
	movq	%rcx, 16(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 88(%rsp)
	xorl	%eax, %eax
	movslq	%r8d, %rax
	movl	%r8d, 28(%rsp)
	movq	%rax, %rdi
	movq	%rax, (%rsp)
	call	_Znam@PLT
	movq	(%rsp), %rsi
	leaq	40(%rsp), %rdi
	movq	%rax, 8(%rsp)
	call	cudaMalloc@PLT
	movq	(%rsp), %rsi
	leaq	48(%rsp), %rdi
	call	cudaMalloc@PLT
	leaq	56(%rsp), %rdi
	movq	%r15, %rsi
	call	cudaMalloc@PLT
	movq	(%rsp), %rdx
	movq	40(%rsp), %rdi
	movq	%r14, %rsi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	movq	16(%rsp), %rsi
	movq	56(%rsp), %rdi
	movq	%r15, %rdx
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	movl	28(%rsp), %r8d
	movl	$1024, %ecx
	movl	%r8d, %eax
	cltd
	idivl	%ecx
	testl	%edx, %edx
	jle	.L11
	sarl	$10, %r8d
	leal	1(%r8), %eax
.L11:
	movl	%eax, 64(%rsp)
	movl	$4194305, %edx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movabsq	$4294967297, %rax
	salq	$10, %rdx
	movl	$1, %ecx
	movq	%rax, 68(%rsp)
	movq	64(%rsp), %rdi
	movl	72(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L12
	pushq	%rax
	.cfi_def_cfa_offset 168
	movl	%ebp, %ecx
	movl	%ebx, %edx
	movl	%r12d, %r9d
	pushq	%r13
	.cfi_def_cfa_offset 176
	movq	72(%rsp), %r8
	movq	64(%rsp), %rsi
	movq	56(%rsp), %rdi
	call	_Z47__device_stub__Z19convolute_1PixelGPUPhS_iiPaiiPhS_iiPaii
	popq	%rdx
	.cfi_def_cfa_offset 168
	popq	%rcx
	.cfi_def_cfa_offset 160
.L12:
	movq	(%rsp), %rdx
	movq	48(%rsp), %rsi
	movl	$2, %ecx
	movq	8(%rsp), %rdi
	call	cudaMemcpy@PLT
	movq	40(%rsp), %rdi
	call	cudaFree@PLT
	movq	48(%rsp), %rdi
	call	cudaFree@PLT
	movq	56(%rsp), %rdi
	call	cudaFree@PLT
	movq	88(%rsp), %rax
	subq	%fs:40, %rax
	je	.L13
	call	__stack_chk_fail@PLT
.L13:
	movq	8(%rsp), %rax
	addq	$104, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2008:
	.size	convolutionGPU, .-convolutionGPU
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z19convolute_1PixelGPUPhS_iiPaii"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2037:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z19convolute_1PixelGPUPhS_iiPaii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2037:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

# include <hip/hip_runtime.h>

extern "C"
unsigned char * convolutionGPU(unsigned char * rowdata, int width, int height, signed char * kernell, int kernelSize, int nchann);

__global__ void convolute_1PixelGPU(unsigned char * data_dev, unsigned char * convData_dev, int width, int height, signed char * kernellDev, int kernelSize, int nchann){
    int posThread = blockIdx.x*blockDim.x + threadIdx.x;
    if(posThread < width*height*nchann){
        //Compute the sum of the kernell elements
        int sumKernell = 0;
        for(int i = 0; i < kernelSize*kernelSize; i++)
            sumKernell += kernellDev[i];
        sumKernell = (sumKernell <= 0) ? 1: sumKernell;

        // Start to convolute:
        int acumm = 0;
        int midSZ = (kernelSize - 1)/2;
        for(int ky = 0; ky < kernelSize; ky++){
            for(int kx = 0; kx < kernelSize; kx++){
                int pdata = posThread + nchann*width*(ky - midSZ) - midSZ*nchann + kx*nchann;
                if(pdata > 0 && pdata < width*height*nchann)
                    acumm += data_dev[pdata]*kernellDev[kx + ky*kernelSize];
            }
        }
        int ans = acumm/sumKernell;
        if(ans > 255)
            ans = 255;
        if(ans < 0)
            ans = 0;
        convData_dev[posThread] =(unsigned char) ans;
    }
}

unsigned char * convolutionGPU(unsigned char * rowdata, int width, int height, signed char * kernell, int kernelSize, int nchann){
    int size = nchann*width*height;
    unsigned char * convolutedData = new unsigned char[size];
    unsigned char * dataDev;
    unsigned char * convDataDev;
    signed char * kernellDev;

    hipMalloc((void**)&dataDev, size*sizeof(unsigned char));
    hipMalloc((void**)&convDataDev, size*sizeof(unsigned char));
    hipMalloc((void**)&kernellDev, kernelSize*sizeof(signed char));
    hipMemcpy(dataDev, rowdata, size*sizeof(unsigned char), hipMemcpyHostToDevice);
    hipMemcpy(kernellDev, kernell, kernelSize*sizeof(signed char), hipMemcpyHostToDevice);


    int nThreads = 1024;
    int nBlocks = (size % nThreads > 0)? size/nThreads + 1: size/nThreads;
    convolute_1PixelGPU<<<nBlocks, nThreads>>>(dataDev, convDataDev, width, height, kernellDev, kernelSize, nchann);
    hipMemcpy(convolutedData, convDataDev, size*sizeof(unsigned char), hipMemcpyDeviceToHost);
    hipFree(dataDev);
    hipFree(convDataDev);
    hipFree(kernellDev);
    return convolutedData;
}
int main(){

}

	.text
	.file	"convolution.hip"
	.globl	_Z34__device_stub__convolute_1PixelGPUPhS_iiPaii # -- Begin function _Z34__device_stub__convolute_1PixelGPUPhS_iiPaii
	.type	_Z34__device_stub__convolute_1PixelGPUPhS_iiPaii,@function
_Z34__device_stub__convolute_1PixelGPUPhS_iiPaii: # @_Z34__device_stub__convolute_1PixelGPUPhS_iiPaii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	20(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	16(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	40(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	12(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z19convolute_1PixelGPUPhS_iiPaii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z34__device_stub__convolute_1PixelGPUPhS_iiPaii, .Lfunc_end0-_Z34__device_stub__convolute_1PixelGPUPhS_iiPaii
	.cfi_endproc
                                        # -- End function
	.globl	convolutionGPU                  # -- Begin function convolutionGPU
	.type	convolutionGPU,@function
convolutionGPU:                         # @convolutionGPU
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$56, %rsp
	.cfi_def_cfa_offset 112
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%r8d, %ebx
	movq	%rcx, %rbp
	movq	%rdi, %r15
	movl	%edx, 24(%rsp)                  # 4-byte Spill
	movl	%edx, %eax
	movl	%esi, 16(%rsp)                  # 4-byte Spill
	imull	%esi, %eax
	movl	%r9d, 20(%rsp)                  # 4-byte Spill
	imull	%r9d, %eax
	movslq	%eax, %r14
	movq	%r14, %rdi
	callq	_Znam
	movq	%rax, 48(%rsp)                  # 8-byte Spill
	leaq	40(%rsp), %r12
	movq	%r12, %rdi
	movq	%r14, %rsi
	callq	hipMalloc
	leaq	8(%rsp), %rdi
	movq	%r14, %rsi
	callq	hipMalloc
	movl	%ebx, 28(%rsp)                  # 4-byte Spill
	movslq	%ebx, %r13
	leaq	32(%rsp), %rbx
	movq	%rbx, %rdi
	movq	%r13, %rsi
	callq	hipMalloc
	movq	(%r12), %rdi
	movq	%r15, %rsi
	movq	%r14, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%rbx), %rdi
	movq	%rbp, %rsi
	movq	%r13, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	xorl	%edi, %edi
	testl	$-2147482625, %r14d             # imm = 0x800003FF
	setg	%dil
	leal	1023(%r14), %eax
	testl	%r14d, %r14d
	cmovnsl	%r14d, %eax
	sarl	$10, %eax
	addl	%eax, %edi
	btsq	$32, %rdi
	movabsq	$4294967296, %rdx               # imm = 0x100000000
	orq	$1024, %rdx                     # imm = 0x400
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_2
# %bb.1:
	movq	40(%rsp), %rdi
	movq	8(%rsp), %rsi
	movq	32(%rsp), %r8
	movl	20(%rsp), %eax                  # 4-byte Reload
	movl	%eax, (%rsp)
	movl	16(%rsp), %edx                  # 4-byte Reload
	movl	24(%rsp), %ecx                  # 4-byte Reload
	movl	28(%rsp), %r9d                  # 4-byte Reload
	callq	_Z34__device_stub__convolute_1PixelGPUPhS_iiPaii
.LBB1_2:
	movq	8(%rsp), %rsi
	movq	48(%rsp), %rbx                  # 8-byte Reload
	movq	%rbx, %rdi
	movq	%r14, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	movq	40(%rsp), %rdi
	callq	hipFree
	movq	8(%rsp), %rdi
	callq	hipFree
	movq	32(%rsp), %rdi
	callq	hipFree
	movq	%rbx, %rax
	addq	$56, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	convolutionGPU, .Lfunc_end1-convolutionGPU
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	xorl	%eax, %eax
	retq
.Lfunc_end2:
	.size	main, .Lfunc_end2-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB3_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB3_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z19convolute_1PixelGPUPhS_iiPaii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end3:
	.size	__hip_module_ctor, .Lfunc_end3-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB4_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB4_2:
	retq
.Lfunc_end4:
	.size	__hip_module_dtor, .Lfunc_end4-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z19convolute_1PixelGPUPhS_iiPaii,@object # @_Z19convolute_1PixelGPUPhS_iiPaii
	.section	.rodata,"a",@progbits
	.globl	_Z19convolute_1PixelGPUPhS_iiPaii
	.p2align	3, 0x0
_Z19convolute_1PixelGPUPhS_iiPaii:
	.quad	_Z34__device_stub__convolute_1PixelGPUPhS_iiPaii
	.size	_Z19convolute_1PixelGPUPhS_iiPaii, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z19convolute_1PixelGPUPhS_iiPaii"
	.size	.L__unnamed_1, 34

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z34__device_stub__convolute_1PixelGPUPhS_iiPaii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z19convolute_1PixelGPUPhS_iiPaii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z19convolute_1PixelGPUPhS_iiPaii ; -- Begin function _Z19convolute_1PixelGPUPhS_iiPaii
	.globl	_Z19convolute_1PixelGPUPhS_iiPaii
	.p2align	8
	.type	_Z19convolute_1PixelGPUPhS_iiPaii,@function
_Z19convolute_1PixelGPUPhS_iiPaii:      ; @_Z19convolute_1PixelGPUPhS_iiPaii
; %bb.0:
	s_clause 0x2
	s_load_b32 s4, s[0:1], 0x34
	s_load_b64 s[10:11], s[0:1], 0x10
	s_load_b64 s[2:3], s[0:1], 0x20
	s_waitcnt lgkmcnt(0)
	s_and_b32 s4, s4, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	s_mul_i32 s15, s15, s4
	s_mul_i32 s12, s3, s10
	v_add_nc_u32_e32 v1, s15, v0
	s_mul_i32 s11, s12, s11
	s_mov_b32 s4, exec_lo
	v_cmpx_gt_i32_e64 s11, v1
	s_cbranch_execz .LBB0_13
; %bb.1:                                ; %.preheader61
	s_load_b64 s[8:9], s[0:1], 0x18
	v_mov_b32_e32 v2, 0
	s_cmp_eq_u32 s2, 0
	s_cbranch_scc1 .LBB0_4
; %bb.2:                                ; %.lr.ph.preheader
	v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v2, 0
	s_mul_i32 s4, s2, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_max_u32 s6, s4, 1
	s_waitcnt lgkmcnt(0)
	s_mov_b64 s[4:5], s[8:9]
.LBB0_3:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	global_load_i8 v4, v3, s[4:5]
	s_add_i32 s6, s6, -1
	s_add_u32 s4, s4, 1
	s_addc_u32 s5, s5, 0
	s_cmp_eq_u32 s6, 0
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v2, v2, v4
	s_cbranch_scc0 .LBB0_3
.LBB0_4:                                ; %._crit_edge
	s_load_b128 s[4:7], s[0:1], 0x0
	s_cmp_lt_i32 s2, 1
	s_cbranch_scc1 .LBB0_11
; %bb.5:                                ; %.preheader.preheader
	s_add_i32 s0, s2, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshr_b32 s1, s0, 31
	s_add_i32 s0, s0, s1
	s_not_b32 s1, s10
	s_ashr_i32 s0, s0, 1
	s_mov_b32 s10, 0
	s_mul_i32 s0, s0, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mul_i32 s0, s0, s1
	s_mov_b32 s1, 0
	v_add3_u32 v3, s15, s0, v0
	v_mov_b32_e32 v0, 0
.LBB0_6:                                ; %.preheader
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_7 Depth 2
	s_delay_alu instid0(VALU_DEP_2)
	v_mov_b32_e32 v4, v3
	s_mov_b32 s13, 0
.LBB0_7:                                ;   Parent Loop BB0_6 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_lt_i32_e32 vcc_lo, 0, v4
	v_cmp_gt_i32_e64 s0, s11, v4
	s_and_b32 s14, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s0, s14
	s_cbranch_execz .LBB0_9
; %bb.8:                                ;   in Loop: Header=BB0_7 Depth=2
	s_add_i32 s14, s1, s13
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v5, s14
	s_waitcnt lgkmcnt(0)
	global_load_u8 v6, v4, s[4:5]
	global_load_i8 v5, v5, s[8:9]
	s_waitcnt vmcnt(0)
	v_mad_i32_i24 v0, v5, v6, v0
.LBB0_9:                                ;   in Loop: Header=BB0_7 Depth=2
	s_or_b32 exec_lo, exec_lo, s0
	v_add_nc_u32_e32 v4, s3, v4
	s_add_i32 s13, s13, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s2, s13
	s_cbranch_scc0 .LBB0_7
; %bb.10:                               ; %._crit_edge67
                                        ;   in Loop: Header=BB0_6 Depth=1
	v_add_nc_u32_e32 v3, s12, v3
	s_add_i32 s10, s10, 1
	s_add_i32 s1, s1, s2
	s_cmp_eq_u32 s10, s2
	s_cbranch_scc0 .LBB0_6
	s_branch .LBB0_12
.LBB0_11:
	v_mov_b32_e32 v0, 0
.LBB0_12:                               ; %._crit_edge71
	v_max_i32_e32 v2, 1, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v5, 31, v0
	v_cvt_f32_u32_e32 v3, v2
	v_sub_nc_u32_e32 v4, 0, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v0, v0, v5
	v_rcp_iflag_f32_e32 v3, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v0, v0, v5
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v3, 0x4f7ffffe, v3
	v_cvt_u32_f32_e32 v3, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v4, v4, v3
	v_mul_hi_u32 v4, v3, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v3, v3, v4
	v_mul_hi_u32 v3, v0, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v4, v3, v2
	v_sub_nc_u32_e32 v0, v0, v4
	v_add_nc_u32_e32 v4, 1, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v6, v0, v2
	v_cmp_ge_u32_e32 vcc_lo, v0, v2
	v_dual_cndmask_b32 v0, v0, v6 :: v_dual_cndmask_b32 v3, v3, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_ge_u32_e32 vcc_lo, v0, v2
	v_add_nc_u32_e32 v4, 1, v3
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v0, v3, v4, vcc_lo
	v_xor_b32_e32 v0, v0, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v0, v0, v5
	v_med3_i32 v3, v0, 0, 0xff
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v0, vcc_lo, s6, v1
	v_add_co_ci_u32_e32 v1, vcc_lo, s7, v2, vcc_lo
	global_store_b8 v[0:1], v3, off
.LBB0_13:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z19convolute_1PixelGPUPhS_iiPaii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 7
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z19convolute_1PixelGPUPhS_iiPaii, .Lfunc_end0-_Z19convolute_1PixelGPUPhS_iiPaii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 588
; NumSgprs: 18
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         36
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         44
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         52
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         54
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         56
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         58
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         60
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         62
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         104
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 296
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z19convolute_1PixelGPUPhS_iiPaii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z19convolute_1PixelGPUPhS_iiPaii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     7
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
