/*
 ============================================================================
 Name        : VSB-PAII.cu
 Author      : Dave
 Version     :
 Copyright   : Your copyright notice
 Description : CUDA compute reciprocals
 ============================================================================
 */

/*
 ============================================================================
 Name        : cuda1.cu
 Author      : david
 Version     :
 Copyright   : Your copyright notice
 Description : CUDA compute reciprocals
 ============================================================================
 */

#include <iostream>
#include <numeric>
#include <stdlib.h>
#include <cuda_runtime.h>

#define CUDA_CHECK_RETURN(value) CheckCudaErrorAux(__FILE__,__LINE__, #value, value)

__global__ void VectorAdd(int *A,int *B,int *C,int M)
{
	int i = threadIdx.x;
	if(i < M)
	{
		C[i] = A[i] + B[i];
	}
}
__global__ void VectorAddMN(int *A,int *B,int *C,int M,int N)
{
	const int i = blockIdx.x * blockDim.x + threadIdx.x;
	const int j = blockIdx.y * blockDim.y + threadIdx.y;
	if (i < M && j < N)
	{
		C[i * M + j] = A[i * M + j] + B[i * M + j];
	}
}

__global__ void VectorAddMN_2(int *A,int *B,int *C,int M,int N)
{
	const int i = blockIdx.x * blockDim.x + threadIdx.x;
	const int j = blockIdx.y * blockDim.y + threadIdx.y;
	if (i < M && j < N)
	{

		for (int i = 0; i < M * N; ++i) {
			int row = i / N;
			int col = i % N;

			C[row + col] = A[row + col] + B[row + col];
		}
	}
}
void CV1_1()
{
	const unsigned int M = 10;
		const unsigned int bytes = M * sizeof(int);


		//Host allocate
		int *A_vectorHost = (int*)malloc(bytes);
		int *B_vectorHost = (int*)malloc(bytes);
		int *C_vectorHost = (int*)malloc(bytes);


		//Allocate the DEVICE memory to be able to copy data from HOST.
		int *A_vectorDevice;
		cudaMalloc(&A_vectorDevice, bytes);

		int *B_vectorDevice;
		cudaMalloc(&B_vectorDevice, bytes);

		int *C_vectorDevice;
		cudaMalloc(&C_vectorDevice, bytes);


		for(int i=0; i < M;i++)
		{
			A_vectorHost[i] = i;
			B_vectorHost[i] = i;
			C_vectorHost[i] = 0;
		}
		cudaMemcpy(A_vectorDevice, A_vectorHost, bytes, cudaMemcpyHostToDevice);
		cudaMemcpy(B_vectorDevice, B_vectorHost, bytes, cudaMemcpyHostToDevice);
		cudaMemcpy(C_vectorDevice, C_vectorHost, bytes, cudaMemcpyHostToDevice);

		VectorAdd<<<1,M >>>(A_vectorDevice, B_vectorDevice, C_vectorDevice,M);

		cudaMemcpy(C_vectorHost, C_vectorDevice, bytes, cudaMemcpyDeviceToHost);

		for (int i = 0; i < 10; i++)
			{
				printf("\n %d", C_vectorHost[i]);
			}

		free(A_vectorHost);
		free(B_vectorHost);
		free(C_vectorHost);

		A_vectorHost = NULL;
		B_vectorHost = NULL;
		C_vectorHost = NULL;

		cudaFree(A_vectorDevice);
		cudaFree(B_vectorDevice);
		cudaFree(C_vectorDevice);
}

void CV1_2()
{
	const unsigned int M = 10;
    const unsigned int N = 10;

	//Host allocate
	int *A_Host = (int*)malloc(M*N*sizeof(int));
	int *B_Host = (int*)malloc(M*N*sizeof(int));
	int *C_Host = (int*)malloc(M*N*sizeof(int));

	for(int i=0; i < M;i++)
	{
		for(int j=0; j < N;j++)
			{
			A_Host[i * M + j] = i  * j ;
			B_Host[i * M + j] = i  * j ;

			}
	}

	int *A_Device;
	cudaMalloc(&A_Device,M*N*sizeof(int));

	int *B_Device;
	cudaMalloc(&B_Device,M*N*sizeof(int));
	int *C_Device;
	cudaMalloc(&C_Device,M*N*sizeof(int) );

	cudaMemcpy(A_Device, A_Host,M*N*sizeof(int), cudaMemcpyHostToDevice);
	cudaMemcpy(B_Device, B_Host, M*N*sizeof(int), cudaMemcpyHostToDevice);
	cudaMemcpy(C_Device, C_Host, M*sizeof(int), cudaMemcpyHostToDevice);

	dim3 dimBlock(M, N);
	dim3 dimGrid(1, 1);

	VectorAddMN<<<dimGrid, dimBlock>>>(A_Device,B_Device,C_Device,M,N);

	cudaMemcpy(C_Host, C_Device, M*N*sizeof(int), cudaMemcpyDeviceToHost);


	for (int i = 0; i < M; i++)
		{
			std::cout << i << "| " ;
			for (int j = 0; j < N; j++)
			{
				std::cout << C_Host[i * M + j] << "   ";
			}
			std::cout << std::endl;
		}

	free(A_Host);
	free(B_Host);
	free(C_Host);
	cudaFree(A_Device);
	cudaFree(B_Device);
	cudaFree(C_Device);
};


void CV1_2_2()
{
	const unsigned int M = 10;
    const unsigned int N = 10;

    // M rows N cols
    int** A_Host = new int*[M];
    int** B_Host = new int*[M];
    int** C_Host = new int*[M];


    A_Host[0] = new int[M * N];
    B_Host[0] = new int[M * N];
    C_Host[0] = new int[M * N];

    for (int i = 1; i < M; ++i){
    	A_Host[i] = A_Host[i-1] + N;
    	B_Host[i] = B_Host[i-1] + N;
    	C_Host[i] = C_Host[i-1] + N;
    }

    //Fill
    for (int i = 0; i < M; ++i) {
     for (int j = 0; j < N; ++j) {
      A_Host[i][j] = i*j;
      B_Host[i][j] = i*j;
     }
    }


    int *A_Device;
    cudaMalloc((void **)&A_Device, sizeof(int) * M * N);


    int *B_Device;
    cudaMalloc((void **)&B_Device, sizeof(int) * M * N);


    int *C_Device;
    cudaMalloc((void **)&C_Device, sizeof(int) * M * N);

    cudaMemcpy(A_Device, A_Host[0],M*N*sizeof(int), cudaMemcpyHostToDevice);
	cudaMemcpy(B_Device, B_Host[0], M*N*sizeof(int), cudaMemcpyHostToDevice);
	cudaMemcpy(C_Device, C_Host[0], M*N*sizeof(int), cudaMemcpyHostToDevice);

	dim3 dimBlock(M, N);
	dim3 dimGrid(1, 1);

	VectorAddMN_2<<<dimGrid, dimBlock>>>(A_Device,B_Device,C_Device,M,N);

	cudaMemcpy(C_Host, C_Device, M*N*sizeof(int), cudaMemcpyDeviceToHost);


	for (int i = 0; i < M; i++)
		{
			std::cout << i << "| " ;
			for (int j = 0; j < N; j++)
			{
				std::cout << C_Host[i][j] << "   ";
			}
			std::cout << std::endl;
		}

	free(A_Host);
	free(B_Host);
	free(C_Host);
	cudaFree(A_Device);
	cudaFree(B_Device);
	cudaFree(C_Device);
};

int main(int argc, char *argv[])
{

CV1_2();

}




	.file	"tmpxft_00338167_00000000-6_VSB-PAII.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3680:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3680:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z33__device_stub__Z9VectorAddPiS_S_iPiS_S_i
	.type	_Z33__device_stub__Z9VectorAddPiS_S_iPiS_S_i, @function
_Z33__device_stub__Z9VectorAddPiS_S_iPiS_S_i:
.LFB3702:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 4(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z9VectorAddPiS_S_i(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L2:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3702:
	.size	_Z33__device_stub__Z9VectorAddPiS_S_iPiS_S_i, .-_Z33__device_stub__Z9VectorAddPiS_S_iPiS_S_i
	.globl	_Z9VectorAddPiS_S_i
	.type	_Z9VectorAddPiS_S_i, @function
_Z9VectorAddPiS_S_i:
.LFB3703:
	.cfi_startproc
	endbr64
	jmp	_Z33__device_stub__Z9VectorAddPiS_S_iPiS_S_i
	.cfi_endproc
.LFE3703:
	.size	_Z9VectorAddPiS_S_i, .-_Z9VectorAddPiS_S_i
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"\n %d"
	.text
	.globl	_Z5CV1_1v
	.type	_Z5CV1_1v, @function
_Z5CV1_1v:
.LFB3674:
	.cfi_startproc
	endbr64
	pushq	%r14
	.cfi_def_cfa_offset 16
	.cfi_offset 14, -16
	movl	$40, %edi
	pushq	%r13
	.cfi_def_cfa_offset 24
	.cfi_offset 13, -24
	pushq	%r12
	.cfi_def_cfa_offset 32
	.cfi_offset 12, -32
	pushq	%rbp
	.cfi_def_cfa_offset 40
	.cfi_offset 6, -40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	.cfi_offset 3, -48
	subq	$64, %rsp
	.cfi_def_cfa_offset 112
	movq	%fs:40, %rax
	movq	%rax, 56(%rsp)
	xorl	%eax, %eax
	call	malloc@PLT
	movl	$40, %edi
	movq	%rax, %r12
	call	malloc@PLT
	movl	$40, %edi
	movq	%rax, %rbp
	call	malloc@PLT
	leaq	8(%rsp), %rdi
	movl	$40, %esi
	movq	%rax, %rbx
	call	cudaMalloc@PLT
	leaq	16(%rsp), %rdi
	movl	$40, %esi
	call	cudaMalloc@PLT
	leaq	24(%rsp), %rdi
	movl	$40, %esi
	call	cudaMalloc@PLT
	xorl	%ecx, %ecx
.L9:
	movl	%ecx, (%r12,%rcx,4)
	movl	%ecx, 0(%rbp,%rcx,4)
	incq	%rcx
	cmpq	$10, %rcx
	jne	.L9
	xorl	%eax, %eax
	movq	%rbx, %rdi
	movl	$40, %edx
	movq	%r12, %rsi
	rep stosl
	movq	8(%rsp), %rdi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	movq	16(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbp, %rsi
	movl	$40, %edx
	call	cudaMemcpy@PLT
	movq	24(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbx, %rsi
	movl	$40, %edx
	call	cudaMemcpy@PLT
	movl	$2147483653, %edx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	addq	%rdx, %rdx
	movl	$1, %ecx
	movl	$1, %esi
	movabsq	$4294967297, %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L10
	movq	24(%rsp), %rdx
	movq	16(%rsp), %rsi
	movl	$10, %ecx
	movq	8(%rsp), %rdi
	call	_Z33__device_stub__Z9VectorAddPiS_S_iPiS_S_i
.L10:
	movq	24(%rsp), %rsi
	movl	$2, %ecx
	movq	%rbx, %rdi
	xorl	%r13d, %r13d
	movl	$40, %edx
	leaq	.LC0(%rip), %r14
	call	cudaMemcpy@PLT
.L11:
	movl	(%rbx,%r13,4), %edx
	movq	%r14, %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	incq	%r13
	call	__printf_chk@PLT
	cmpq	$10, %r13
	jne	.L11
	movq	%r12, %rdi
	call	free@PLT
	movq	%rbp, %rdi
	call	free@PLT
	movq	%rbx, %rdi
	call	free@PLT
	movq	8(%rsp), %rdi
	call	cudaFree@PLT
	movq	16(%rsp), %rdi
	call	cudaFree@PLT
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	movq	56(%rsp), %rax
	subq	%fs:40, %rax
	je	.L12
	call	__stack_chk_fail@PLT
.L12:
	addq	$64, %rsp
	.cfi_def_cfa_offset 48
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%rbp
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r13
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3674:
	.size	_Z5CV1_1v, .-_Z5CV1_1v
	.globl	_Z37__device_stub__Z11VectorAddMNPiS_S_iiPiS_S_ii
	.type	_Z37__device_stub__Z11VectorAddMNPiS_S_iiPiS_S_ii, @function
_Z37__device_stub__Z11VectorAddMNPiS_S_iiPiS_S_ii:
.LFB3704:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	32(%rsp), %rdx
	movl	%ecx, 4(%rsp)
	leaq	40(%rsp), %rcx
	movl	%r8d, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L16
	pushq	40(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z11VectorAddMNPiS_S_ii(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 176
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L16:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L18
	call	__stack_chk_fail@PLT
.L18:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3704:
	.size	_Z37__device_stub__Z11VectorAddMNPiS_S_iiPiS_S_ii, .-_Z37__device_stub__Z11VectorAddMNPiS_S_iiPiS_S_ii
	.globl	_Z11VectorAddMNPiS_S_ii
	.type	_Z11VectorAddMNPiS_S_ii, @function
_Z11VectorAddMNPiS_S_ii:
.LFB3705:
	.cfi_startproc
	endbr64
	jmp	_Z37__device_stub__Z11VectorAddMNPiS_S_iiPiS_S_ii
	.cfi_endproc
.LFE3705:
	.size	_Z11VectorAddMNPiS_S_ii, .-_Z11VectorAddMNPiS_S_ii
	.section	.rodata.str1.1
.LC1:
	.string	"| "
.LC2:
	.string	"   "
	.text
	.globl	_Z5CV1_2v
	.type	_Z5CV1_2v, @function
_Z5CV1_2v:
.LFB3675:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movl	$400, %edi
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$72, %rsp
	.cfi_def_cfa_offset 128
	movq	%fs:40, %rax
	movq	%rax, 56(%rsp)
	xorl	%eax, %eax
	call	malloc@PLT
	movl	$400, %edi
	movq	%rax, %r12
	call	malloc@PLT
	movl	$400, %edi
	movq	%rax, %rbp
	call	malloc@PLT
	movq	%rax, %rbx
	xorl	%eax, %eax
.L22:
	imulq	$40, %rax, %rcx
	movl	%eax, %edi
	xorl	%edx, %edx
	xorl	%esi, %esi
.L23:
	incl	%esi
	movl	%edx, (%r12,%rcx)
	movl	%edx, 0(%rbp,%rcx)
	addl	%edi, %edx
	addq	$4, %rcx
	cmpl	$10, %esi
	jne	.L23
	incq	%rax
	cmpq	$10, %rax
	jne	.L22
	leaq	8(%rsp), %rdi
	movl	$400, %esi
	call	cudaMalloc@PLT
	leaq	16(%rsp), %rdi
	movl	$400, %esi
	call	cudaMalloc@PLT
	leaq	24(%rsp), %rdi
	movl	$400, %esi
	call	cudaMalloc@PLT
	movq	8(%rsp), %rdi
	movl	$1, %ecx
	movq	%r12, %rsi
	movl	$400, %edx
	call	cudaMemcpy@PLT
	movq	16(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbp, %rsi
	movl	$400, %edx
	call	cudaMemcpy@PLT
	movq	24(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbx, %rsi
	movl	$40, %edx
	call	cudaMemcpy@PLT
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$1, %ecx
	movabsq	$42949672970, %rdx
	movl	$1, %esi
	movabsq	$4294967297, %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L25
	movq	24(%rsp), %rdx
	movq	16(%rsp), %rsi
	movl	$10, %ecx
	movl	$10, %r8d
	movq	8(%rsp), %rdi
	call	_Z37__device_stub__Z11VectorAddMNPiS_S_iiPiS_S_ii
.L25:
	movq	24(%rsp), %rsi
	movl	$2, %ecx
	movq	%rbx, %rdi
	xorl	%r13d, %r13d
	movl	$400, %edx
	call	cudaMemcpy@PLT
.L27:
	movl	%r13d, %esi
	leaq	_ZSt4cout(%rip), %rdi
	xorl	%r14d, %r14d
	call	_ZNSolsEi@PLT
	movl	$2, %edx
	leaq	.LC1(%rip), %rsi
	movq	%rax, %rdi
	call	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
	imulq	$40, %r13, %r8
	leaq	(%rbx,%r8), %r15
.L26:
	movl	(%r15,%r14,4), %esi
	leaq	_ZSt4cout(%rip), %rdi
	incq	%r14
	call	_ZNSolsEi@PLT
	movl	$3, %edx
	leaq	.LC2(%rip), %rsi
	movq	%rax, %rdi
	call	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
	cmpq	$10, %r14
	jne	.L26
	leaq	_ZSt4cout(%rip), %rdi
	incq	%r13
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
	cmpq	$10, %r13
	jne	.L27
	movq	%r12, %rdi
	call	free@PLT
	movq	%rbp, %rdi
	call	free@PLT
	movq	%rbx, %rdi
	call	free@PLT
	movq	8(%rsp), %rdi
	call	cudaFree@PLT
	movq	16(%rsp), %rdi
	call	cudaFree@PLT
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	movq	56(%rsp), %rax
	subq	%fs:40, %rax
	je	.L28
	call	__stack_chk_fail@PLT
.L28:
	addq	$72, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3675:
	.size	_Z5CV1_2v, .-_Z5CV1_2v
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB3677:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	call	_Z5CV1_2v
	xorl	%eax, %eax
	popq	%rdx
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3677:
	.size	main, .-main
	.text
	.globl	_Z39__device_stub__Z13VectorAddMN_2PiS_S_iiPiS_S_ii
	.type	_Z39__device_stub__Z13VectorAddMN_2PiS_S_iiPiS_S_ii, @function
_Z39__device_stub__Z13VectorAddMN_2PiS_S_iiPiS_S_ii:
.LFB3706:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	32(%rsp), %rdx
	movl	%ecx, 4(%rsp)
	leaq	40(%rsp), %rcx
	movl	%r8d, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L35
	pushq	40(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z13VectorAddMN_2PiS_S_ii(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 176
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L35:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L37
	call	__stack_chk_fail@PLT
.L37:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3706:
	.size	_Z39__device_stub__Z13VectorAddMN_2PiS_S_iiPiS_S_ii, .-_Z39__device_stub__Z13VectorAddMN_2PiS_S_iiPiS_S_ii
	.globl	_Z13VectorAddMN_2PiS_S_ii
	.type	_Z13VectorAddMN_2PiS_S_ii, @function
_Z13VectorAddMN_2PiS_S_ii:
.LFB3707:
	.cfi_startproc
	endbr64
	jmp	_Z39__device_stub__Z13VectorAddMN_2PiS_S_iiPiS_S_ii
	.cfi_endproc
.LFE3707:
	.size	_Z13VectorAddMN_2PiS_S_ii, .-_Z13VectorAddMN_2PiS_S_ii
	.globl	_Z7CV1_2_2v
	.type	_Z7CV1_2_2v, @function
_Z7CV1_2_2v:
.LFB3676:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movl	$80, %edi
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$72, %rsp
	.cfi_def_cfa_offset 128
	movq	%fs:40, %rax
	movq	%rax, 56(%rsp)
	xorl	%eax, %eax
	call	_Znam@PLT
	movl	$80, %edi
	movq	%rax, %r12
	call	_Znam@PLT
	movl	$80, %edi
	movq	%rax, %rbp
	call	_Znam@PLT
	movl	$400, %edi
	movq	%rax, %rbx
	call	_Znam@PLT
	movl	$400, %edi
	movq	%rax, (%r12)
	call	_Znam@PLT
	movl	$400, %edi
	movq	%rax, 0(%rbp)
	call	_Znam@PLT
	movq	%rax, (%rbx)
	xorl	%eax, %eax
.L41:
	movq	(%r12,%rax), %rcx
	leaq	40(%rcx), %rdx
	movq	0(%rbp,%rax), %rcx
	movq	%rdx, 8(%r12,%rax)
	leaq	40(%rcx), %rdx
	movq	(%rbx,%rax), %rcx
	movq	%rdx, 8(%rbp,%rax)
	leaq	40(%rcx), %rdx
	movq	%rdx, 8(%rbx,%rax)
	addq	$8, %rax
	cmpq	$72, %rax
	jne	.L41
	xorl	%eax, %eax
.L42:
	movq	(%r12,%rax,8), %r8
	movq	0(%rbp,%rax,8), %rdi
	movl	%eax, %esi
	xorl	%edx, %edx
	xorl	%ecx, %ecx
.L43:
	movl	%ecx, (%r8,%rdx)
	movl	%ecx, (%rdi,%rdx)
	addq	$4, %rdx
	addl	%esi, %ecx
	cmpq	$40, %rdx
	jne	.L43
	incq	%rax
	cmpq	$10, %rax
	jne	.L42
	leaq	8(%rsp), %rdi
	movl	$400, %esi
	call	cudaMalloc@PLT
	leaq	16(%rsp), %rdi
	movl	$400, %esi
	call	cudaMalloc@PLT
	leaq	24(%rsp), %rdi
	movl	$400, %esi
	call	cudaMalloc@PLT
	movq	(%r12), %rsi
	movq	8(%rsp), %rdi
	movl	$1, %ecx
	movl	$400, %edx
	call	cudaMemcpy@PLT
	movq	0(%rbp), %rsi
	movq	16(%rsp), %rdi
	movl	$1, %ecx
	movl	$400, %edx
	call	cudaMemcpy@PLT
	movq	(%rbx), %rsi
	movq	24(%rsp), %rdi
	movl	$1, %ecx
	movl	$400, %edx
	call	cudaMemcpy@PLT
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$1, %ecx
	movabsq	$42949672970, %rdx
	movl	$1, %esi
	movabsq	$4294967297, %rdi
	movl	$1, 40(%rsp)
	movq	%rdx, 32(%rsp)
	movq	%rdi, 44(%rsp)
	movl	$1, 52(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L45
	movq	24(%rsp), %rdx
	movq	16(%rsp), %rsi
	movl	$10, %ecx
	movl	$10, %r8d
	movq	8(%rsp), %rdi
	call	_Z39__device_stub__Z13VectorAddMN_2PiS_S_iiPiS_S_ii
.L45:
	movq	24(%rsp), %rsi
	movl	$2, %ecx
	movq	%rbx, %rdi
	xorl	%r13d, %r13d
	movl	$400, %edx
	call	cudaMemcpy@PLT
.L47:
	movl	%r13d, %esi
	leaq	_ZSt4cout(%rip), %rdi
	xorl	%r14d, %r14d
	call	_ZNSolsEi@PLT
	movl	$2, %edx
	leaq	.LC1(%rip), %rsi
	leaq	.LC2(%rip), %r15
	movq	%rax, %rdi
	call	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
.L46:
	movq	(%rbx,%r13,8), %rax
	leaq	_ZSt4cout(%rip), %rdi
	movl	(%rax,%r14), %esi
	addq	$4, %r14
	call	_ZNSolsEi@PLT
	movl	$3, %edx
	movq	%r15, %rsi
	movq	%rax, %rdi
	call	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
	cmpq	$40, %r14
	jne	.L46
	leaq	_ZSt4cout(%rip), %rdi
	incq	%r13
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
	cmpq	$10, %r13
	jne	.L47
	movq	%r12, %rdi
	call	free@PLT
	movq	%rbp, %rdi
	call	free@PLT
	movq	%rbx, %rdi
	call	free@PLT
	movq	8(%rsp), %rdi
	call	cudaFree@PLT
	movq	16(%rsp), %rdi
	call	cudaFree@PLT
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	movq	56(%rsp), %rax
	subq	%fs:40, %rax
	je	.L48
	call	__stack_chk_fail@PLT
.L48:
	addq	$72, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3676:
	.size	_Z7CV1_2_2v, .-_Z7CV1_2_2v
	.section	.rodata.str1.1
.LC3:
	.string	"_Z13VectorAddMN_2PiS_S_ii"
.LC4:
	.string	"_Z11VectorAddMNPiS_S_ii"
.LC5:
	.string	"_Z9VectorAddPiS_S_i"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3709:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC3(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z13VectorAddMN_2PiS_S_ii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC4(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z11VectorAddMNPiS_S_ii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC5(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z9VectorAddPiS_S_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3709:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

/*
 ============================================================================
 Name        : VSB-PAII.cu
 Author      : Dave
 Version     :
 Copyright   : Your copyright notice
 Description : CUDA compute reciprocals
 ============================================================================
 */

/*
 ============================================================================
 Name        : cuda1.cu
 Author      : david
 Version     :
 Copyright   : Your copyright notice
 Description : CUDA compute reciprocals
 ============================================================================
 */

#include <iostream>
#include <numeric>
#include <stdlib.h>
#include <hip/hip_runtime.h>

#define CUDA_CHECK_RETURN(value) CheckCudaErrorAux(__FILE__,__LINE__, #value, value)

__global__ void VectorAdd(int *A,int *B,int *C,int M)
{
	int i = threadIdx.x;
	if(i < M)
	{
		C[i] = A[i] + B[i];
	}
}
__global__ void VectorAddMN(int *A,int *B,int *C,int M,int N)
{
	const int i = blockIdx.x * blockDim.x + threadIdx.x;
	const int j = blockIdx.y * blockDim.y + threadIdx.y;
	if (i < M && j < N)
	{
		C[i * M + j] = A[i * M + j] + B[i * M + j];
	}
}

__global__ void VectorAddMN_2(int *A,int *B,int *C,int M,int N)
{
	const int i = blockIdx.x * blockDim.x + threadIdx.x;
	const int j = blockIdx.y * blockDim.y + threadIdx.y;
	if (i < M && j < N)
	{

		for (int i = 0; i < M * N; ++i) {
			int row = i / N;
			int col = i % N;

			C[row + col] = A[row + col] + B[row + col];
		}
	}
}
void CV1_1()
{
	const unsigned int M = 10;
		const unsigned int bytes = M * sizeof(int);


		//Host allocate
		int *A_vectorHost = (int*)malloc(bytes);
		int *B_vectorHost = (int*)malloc(bytes);
		int *C_vectorHost = (int*)malloc(bytes);


		//Allocate the DEVICE memory to be able to copy data from HOST.
		int *A_vectorDevice;
		hipMalloc(&A_vectorDevice, bytes);

		int *B_vectorDevice;
		hipMalloc(&B_vectorDevice, bytes);

		int *C_vectorDevice;
		hipMalloc(&C_vectorDevice, bytes);


		for(int i=0; i < M;i++)
		{
			A_vectorHost[i] = i;
			B_vectorHost[i] = i;
			C_vectorHost[i] = 0;
		}
		hipMemcpy(A_vectorDevice, A_vectorHost, bytes, hipMemcpyHostToDevice);
		hipMemcpy(B_vectorDevice, B_vectorHost, bytes, hipMemcpyHostToDevice);
		hipMemcpy(C_vectorDevice, C_vectorHost, bytes, hipMemcpyHostToDevice);

		VectorAdd<<<1,M >>>(A_vectorDevice, B_vectorDevice, C_vectorDevice,M);

		hipMemcpy(C_vectorHost, C_vectorDevice, bytes, hipMemcpyDeviceToHost);

		for (int i = 0; i < 10; i++)
			{
				printf("\n %d", C_vectorHost[i]);
			}

		free(A_vectorHost);
		free(B_vectorHost);
		free(C_vectorHost);

		A_vectorHost = NULL;
		B_vectorHost = NULL;
		C_vectorHost = NULL;

		hipFree(A_vectorDevice);
		hipFree(B_vectorDevice);
		hipFree(C_vectorDevice);
}

void CV1_2()
{
	const unsigned int M = 10;
    const unsigned int N = 10;

	//Host allocate
	int *A_Host = (int*)malloc(M*N*sizeof(int));
	int *B_Host = (int*)malloc(M*N*sizeof(int));
	int *C_Host = (int*)malloc(M*N*sizeof(int));

	for(int i=0; i < M;i++)
	{
		for(int j=0; j < N;j++)
			{
			A_Host[i * M + j] = i  * j ;
			B_Host[i * M + j] = i  * j ;

			}
	}

	int *A_Device;
	hipMalloc(&A_Device,M*N*sizeof(int));

	int *B_Device;
	hipMalloc(&B_Device,M*N*sizeof(int));
	int *C_Device;
	hipMalloc(&C_Device,M*N*sizeof(int) );

	hipMemcpy(A_Device, A_Host,M*N*sizeof(int), hipMemcpyHostToDevice);
	hipMemcpy(B_Device, B_Host, M*N*sizeof(int), hipMemcpyHostToDevice);
	hipMemcpy(C_Device, C_Host, M*sizeof(int), hipMemcpyHostToDevice);

	dim3 dimBlock(M, N);
	dim3 dimGrid(1, 1);

	VectorAddMN<<<dimGrid, dimBlock>>>(A_Device,B_Device,C_Device,M,N);

	hipMemcpy(C_Host, C_Device, M*N*sizeof(int), hipMemcpyDeviceToHost);


	for (int i = 0; i < M; i++)
		{
			std::cout << i << "| " ;
			for (int j = 0; j < N; j++)
			{
				std::cout << C_Host[i * M + j] << "   ";
			}
			std::cout << std::endl;
		}

	free(A_Host);
	free(B_Host);
	free(C_Host);
	hipFree(A_Device);
	hipFree(B_Device);
	hipFree(C_Device);
};


void CV1_2_2()
{
	const unsigned int M = 10;
    const unsigned int N = 10;

    // M rows N cols
    int** A_Host = new int*[M];
    int** B_Host = new int*[M];
    int** C_Host = new int*[M];


    A_Host[0] = new int[M * N];
    B_Host[0] = new int[M * N];
    C_Host[0] = new int[M * N];

    for (int i = 1; i < M; ++i){
    	A_Host[i] = A_Host[i-1] + N;
    	B_Host[i] = B_Host[i-1] + N;
    	C_Host[i] = C_Host[i-1] + N;
    }

    //Fill
    for (int i = 0; i < M; ++i) {
     for (int j = 0; j < N; ++j) {
      A_Host[i][j] = i*j;
      B_Host[i][j] = i*j;
     }
    }


    int *A_Device;
    hipMalloc((void **)&A_Device, sizeof(int) * M * N);


    int *B_Device;
    hipMalloc((void **)&B_Device, sizeof(int) * M * N);


    int *C_Device;
    hipMalloc((void **)&C_Device, sizeof(int) * M * N);

    hipMemcpy(A_Device, A_Host[0],M*N*sizeof(int), hipMemcpyHostToDevice);
	hipMemcpy(B_Device, B_Host[0], M*N*sizeof(int), hipMemcpyHostToDevice);
	hipMemcpy(C_Device, C_Host[0], M*N*sizeof(int), hipMemcpyHostToDevice);

	dim3 dimBlock(M, N);
	dim3 dimGrid(1, 1);

	VectorAddMN_2<<<dimGrid, dimBlock>>>(A_Device,B_Device,C_Device,M,N);

	hipMemcpy(C_Host, C_Device, M*N*sizeof(int), hipMemcpyDeviceToHost);


	for (int i = 0; i < M; i++)
		{
			std::cout << i << "| " ;
			for (int j = 0; j < N; j++)
			{
				std::cout << C_Host[i][j] << "   ";
			}
			std::cout << std::endl;
		}

	free(A_Host);
	free(B_Host);
	free(C_Host);
	hipFree(A_Device);
	hipFree(B_Device);
	hipFree(C_Device);
};

int main(int argc, char *argv[])
{

CV1_2();

}




	.text
	.file	"VSB-PAII.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z24__device_stub__VectorAddPiS_S_i # -- Begin function _Z24__device_stub__VectorAddPiS_S_i
	.type	_Z24__device_stub__VectorAddPiS_S_i,@function
_Z24__device_stub__VectorAddPiS_S_i:    # @_Z24__device_stub__VectorAddPiS_S_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	4(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z9VectorAddPiS_S_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z24__device_stub__VectorAddPiS_S_i, .Lfunc_end0-_Z24__device_stub__VectorAddPiS_S_i
	.cfi_endproc
                                        # -- End function
	.globl	_Z26__device_stub__VectorAddMNPiS_S_ii # -- Begin function _Z26__device_stub__VectorAddMNPiS_S_ii
	.type	_Z26__device_stub__VectorAddMNPiS_S_ii,@function
_Z26__device_stub__VectorAddMNPiS_S_ii: # @_Z26__device_stub__VectorAddMNPiS_S_ii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	4(%rsp), %rdx
	movl	%ecx, (%rdx)
	movq	%rsp, %rcx
	movl	%r8d, (%rcx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z11VectorAddMNPiS_S_ii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z26__device_stub__VectorAddMNPiS_S_ii, .Lfunc_end1-_Z26__device_stub__VectorAddMNPiS_S_ii
	.cfi_endproc
                                        # -- End function
	.globl	_Z28__device_stub__VectorAddMN_2PiS_S_ii # -- Begin function _Z28__device_stub__VectorAddMN_2PiS_S_ii
	.type	_Z28__device_stub__VectorAddMN_2PiS_S_ii,@function
_Z28__device_stub__VectorAddMN_2PiS_S_ii: # @_Z28__device_stub__VectorAddMN_2PiS_S_ii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	4(%rsp), %rdx
	movl	%ecx, (%rdx)
	movq	%rsp, %rcx
	movl	%r8d, (%rcx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z13VectorAddMN_2PiS_S_ii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z28__device_stub__VectorAddMN_2PiS_S_ii, .Lfunc_end2-_Z28__device_stub__VectorAddMN_2PiS_S_ii
	.cfi_endproc
                                        # -- End function
	.globl	_Z5CV1_1v                       # -- Begin function _Z5CV1_1v
	.type	_Z5CV1_1v,@function
_Z5CV1_1v:                              # @_Z5CV1_1v
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r12
	.cfi_def_cfa_offset 32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	subq	$24, %rsp
	.cfi_def_cfa_offset 64
	.cfi_offset %rbx, -40
	.cfi_offset %r12, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movl	$40, %edi
	callq	malloc
	movq	%rax, %rbx
	movl	$40, %edi
	callq	malloc
	movq	%rax, %r14
	movl	$1, %edi
	movl	$40, %esi
	callq	calloc@PLT
	movq	%rax, %r15
	leaq	16(%rsp), %rdi
	movl	$40, %esi
	callq	hipMalloc
	leaq	8(%rsp), %rdi
	movl	$40, %esi
	callq	hipMalloc
	movq	%rsp, %rdi
	movl	$40, %esi
	callq	hipMalloc
	xorl	%eax, %eax
.LBB3_1:                                # =>This Inner Loop Header: Depth=1
	movl	%eax, (%rbx,%rax,4)
	movl	%eax, (%r14,%rax,4)
	incq	%rax
	cmpq	$10, %rax
	jne	.LBB3_1
# %bb.2:
	movq	16(%rsp), %rdi
	movl	$40, %edx
	movq	%rbx, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	8(%rsp), %rdi
	movl	$40, %edx
	movq	%r14, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%rsp), %rdi
	movl	$40, %edx
	movq	%r15, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movabsq	$4294967297, %rdi               # imm = 0x100000001
	leaq	9(%rdi), %rdx
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB3_4
# %bb.3:
	movq	16(%rsp), %rdi
	movq	8(%rsp), %rsi
	movq	(%rsp), %rdx
	movl	$10, %ecx
	callq	_Z24__device_stub__VectorAddPiS_S_i
.LBB3_4:
	movq	(%rsp), %rsi
	movl	$40, %edx
	movq	%r15, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	xorl	%r12d, %r12d
.LBB3_5:                                # =>This Inner Loop Header: Depth=1
	movl	(%r15,%r12,4), %esi
	movl	$.L.str, %edi
	xorl	%eax, %eax
	callq	printf
	incq	%r12
	cmpq	$10, %r12
	jne	.LBB3_5
# %bb.6:
	movq	%rbx, %rdi
	callq	free
	movq	%r14, %rdi
	callq	free
	movq	%r15, %rdi
	callq	free
	movq	16(%rsp), %rdi
	callq	hipFree
	movq	8(%rsp), %rdi
	callq	hipFree
	movq	(%rsp), %rdi
	callq	hipFree
	addq	$24, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	_Z5CV1_1v, .Lfunc_end3-_Z5CV1_1v
	.cfi_endproc
                                        # -- End function
	.globl	_Z5CV1_2v                       # -- Begin function _Z5CV1_2v
	.type	_Z5CV1_2v,@function
_Z5CV1_2v:                              # @_Z5CV1_2v
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$40, %rsp
	.cfi_def_cfa_offset 96
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	$400, %edi                      # imm = 0x190
	callq	malloc
	movq	%rax, %rbx
	movl	$400, %edi                      # imm = 0x190
	callq	malloc
	movq	%rax, %r14
	movl	$400, %edi                      # imm = 0x190
	callq	malloc
	movq	%rax, %r15
	xorl	%eax, %eax
	movq	%r14, %rcx
	movq	%rbx, %rdx
.LBB4_1:                                # %.preheader
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB4_2 Depth 2
	xorl	%esi, %esi
	xorl	%edi, %edi
.LBB4_2:                                #   Parent Loop BB4_1 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movl	%esi, (%rdx,%rdi,4)
	movl	%esi, (%rcx,%rdi,4)
	incq	%rdi
	addl	%eax, %esi
	cmpq	$10, %rdi
	jne	.LBB4_2
# %bb.3:                                #   in Loop: Header=BB4_1 Depth=1
	incq	%rax
	addq	$40, %rdx
	addq	$40, %rcx
	cmpq	$10, %rax
	jne	.LBB4_1
# %bb.4:
	leaq	24(%rsp), %r12
	movl	$400, %esi                      # imm = 0x190
	movq	%r12, %rdi
	callq	hipMalloc
	leaq	16(%rsp), %r13
	movl	$400, %esi                      # imm = 0x190
	movq	%r13, %rdi
	callq	hipMalloc
	leaq	8(%rsp), %rbp
	movl	$400, %esi                      # imm = 0x190
	movq	%rbp, %rdi
	callq	hipMalloc
	movq	(%r12), %rdi
	movl	$400, %edx                      # imm = 0x190
	movq	%rbx, 32(%rsp)                  # 8-byte Spill
	movq	%rbx, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%r13), %rdi
	movl	$400, %edx                      # imm = 0x190
	movq	%r14, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%rbp), %rdi
	movl	$40, %edx
	movq	%r15, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movabsq	$4294967297, %rdi               # imm = 0x100000001
	movabsq	$42949672970, %rdx              # imm = 0xA0000000A
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB4_6
# %bb.5:
	movq	24(%rsp), %rdi
	movq	16(%rsp), %rsi
	movq	8(%rsp), %rdx
	movl	$10, %ecx
	movl	$10, %r8d
	callq	_Z26__device_stub__VectorAddMNPiS_S_ii
.LBB4_6:
	movq	8(%rsp), %rsi
	movl	$400, %edx                      # imm = 0x190
	movq	%r15, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	xorl	%r12d, %r12d
	movl	$_ZSt4cout, %r13d
	movq	%r15, %rbp
.LBB4_7:                                # =>This Loop Header: Depth=1
                                        #     Child Loop BB4_8 Depth 2
	movl	$_ZSt4cout, %edi
	movl	%r12d, %esi
	callq	_ZNSolsEi
	movl	$.L.str.1, %esi
	movl	$2, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	xorl	%ebx, %ebx
.LBB4_8:                                #   Parent Loop BB4_7 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movl	(%rbp,%rbx,4), %esi
	movl	$_ZSt4cout, %edi
	callq	_ZNSolsEi
	movl	$.L.str.2, %esi
	movl	$3, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	incq	%rbx
	cmpq	$10, %rbx
	jne	.LBB4_8
# %bb.9:                                #   in Loop: Header=BB4_7 Depth=1
	movq	_ZSt4cout(%rip), %rax
	movq	-24(%rax), %rdi
	addq	%r13, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movl	$_ZSt4cout, %edi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	incq	%r12
	addq	$40, %rbp
	cmpq	$10, %r12
	jne	.LBB4_7
# %bb.10:
	movq	32(%rsp), %rdi                  # 8-byte Reload
	callq	free
	movq	%r14, %rdi
	callq	free
	movq	%r15, %rdi
	callq	free
	movq	24(%rsp), %rdi
	callq	hipFree
	movq	16(%rsp), %rdi
	callq	hipFree
	movq	8(%rsp), %rdi
	callq	hipFree
	addq	$40, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end4:
	.size	_Z5CV1_2v, .Lfunc_end4-_Z5CV1_2v
	.cfi_endproc
                                        # -- End function
	.globl	_Z7CV1_2_2v                     # -- Begin function _Z7CV1_2_2v
	.type	_Z7CV1_2_2v,@function
_Z7CV1_2_2v:                            # @_Z7CV1_2_2v
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$40, %rsp
	.cfi_def_cfa_offset 96
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	$80, %edi
	callq	_Znam
	movq	%rax, %rbx
	movl	$80, %edi
	callq	_Znam
	movq	%rax, %r14
	movl	$80, %edi
	callq	_Znam
	movq	%rax, %r15
	movl	$400, %edi                      # imm = 0x190
	callq	_Znam
	movq	%rax, %rbp
	leaq	40(%rax), %r12
	movq	%rax, (%rbx)
	movl	$400, %edi                      # imm = 0x190
	callq	_Znam
	leaq	40(%rax), %r13
	movq	%rax, 24(%rsp)                  # 8-byte Spill
	movq	%rax, (%r14)
	movl	$400, %edi                      # imm = 0x190
	callq	_Znam
	leaq	40(%rax), %rdi
	movq	%rax, 32(%rsp)                  # 8-byte Spill
	movq	%rax, (%r15)
	movl	$8, %ecx
	xorl	%edx, %edx
.LBB5_1:                                # =>This Inner Loop Header: Depth=1
	leaq	(%r12,%rdx), %rsi
	movq	%rsi, (%rbx,%rcx)
	leaq	(%rdx,%r13), %rsi
	movq	%rsi, (%r14,%rcx)
	leaq	(%rdi,%rdx), %rsi
	movq	%rsi, (%r15,%rcx)
	addq	$40, %rdx
	addq	$8, %rcx
	cmpq	$360, %rdx                      # imm = 0x168
	jne	.LBB5_1
# %bb.2:                                # %.preheader.preheader
	xorl	%eax, %eax
.LBB5_3:                                # %.preheader
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB5_4 Depth 2
	movq	(%rbx,%rax,8), %rcx
	movq	(%r14,%rax,8), %rdx
	xorl	%esi, %esi
	xorl	%edi, %edi
.LBB5_4:                                #   Parent Loop BB5_3 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movl	%esi, (%rcx,%rdi,4)
	movl	%esi, (%rdx,%rdi,4)
	incq	%rdi
	addl	%eax, %esi
	cmpq	$10, %rdi
	jne	.LBB5_4
# %bb.5:                                #   in Loop: Header=BB5_3 Depth=1
	incq	%rax
	cmpq	$10, %rax
	jne	.LBB5_3
# %bb.6:
	leaq	16(%rsp), %r12
	movl	$400, %esi                      # imm = 0x190
	movq	%r12, %rdi
	callq	hipMalloc
	leaq	8(%rsp), %r13
	movl	$400, %esi                      # imm = 0x190
	movq	%r13, %rdi
	callq	hipMalloc
	movq	%rsp, %rdi
	movl	$400, %esi                      # imm = 0x190
	callq	hipMalloc
	movq	(%r12), %rdi
	movl	$400, %edx                      # imm = 0x190
	movq	%rbp, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%r13), %rdi
	movl	$400, %edx                      # imm = 0x190
	movq	24(%rsp), %rsi                  # 8-byte Reload
	movl	$1, %ecx
	callq	hipMemcpy
	movq	%rsp, %rax
	movq	(%rax), %rdi
	movl	$400, %edx                      # imm = 0x190
	movq	32(%rsp), %rsi                  # 8-byte Reload
	movl	$1, %ecx
	callq	hipMemcpy
	movabsq	$4294967297, %rdi               # imm = 0x100000001
	movabsq	$42949672970, %rdx              # imm = 0xA0000000A
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB5_8
# %bb.7:
	movq	16(%rsp), %rdi
	movq	8(%rsp), %rsi
	movq	(%rsp), %rdx
	movl	$10, %ecx
	movl	$10, %r8d
	callq	_Z28__device_stub__VectorAddMN_2PiS_S_ii
.LBB5_8:
	movq	(%rsp), %rsi
	movl	$400, %edx                      # imm = 0x190
	movq	%r15, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	xorl	%r12d, %r12d
	movl	$_ZSt4cout, %r13d
.LBB5_9:                                # =>This Loop Header: Depth=1
                                        #     Child Loop BB5_10 Depth 2
	movl	$_ZSt4cout, %edi
	movl	%r12d, %esi
	callq	_ZNSolsEi
	movl	$.L.str.1, %esi
	movl	$2, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	xorl	%ebp, %ebp
.LBB5_10:                               #   Parent Loop BB5_9 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movq	(%r15,%r12,8), %rax
	movl	(%rax,%rbp,4), %esi
	movl	$_ZSt4cout, %edi
	callq	_ZNSolsEi
	movl	$.L.str.2, %esi
	movl	$3, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	incq	%rbp
	cmpq	$10, %rbp
	jne	.LBB5_10
# %bb.11:                               #   in Loop: Header=BB5_9 Depth=1
	movq	_ZSt4cout(%rip), %rax
	movq	-24(%rax), %rdi
	addq	%r13, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movl	$_ZSt4cout, %edi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	incq	%r12
	cmpq	$10, %r12
	jne	.LBB5_9
# %bb.12:
	movq	%rbx, %rdi
	callq	free
	movq	%r14, %rdi
	callq	free
	movq	%r15, %rdi
	callq	free
	movq	16(%rsp), %rdi
	callq	hipFree
	movq	8(%rsp), %rdi
	callq	hipFree
	movq	(%rsp), %rdi
	callq	hipFree
	addq	$40, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end5:
	.size	_Z7CV1_2_2v, .Lfunc_end5-_Z7CV1_2_2v
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	_Z5CV1_2v
	xorl	%eax, %eax
	popq	%rcx
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end6:
	.size	main, .Lfunc_end6-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB7_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB7_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z9VectorAddPiS_S_i, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z11VectorAddMNPiS_S_ii, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z13VectorAddMN_2PiS_S_ii, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end7:
	.size	__hip_module_ctor, .Lfunc_end7-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB8_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB8_2:
	retq
.Lfunc_end8:
	.size	__hip_module_dtor, .Lfunc_end8-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z9VectorAddPiS_S_i,@object     # @_Z9VectorAddPiS_S_i
	.section	.rodata,"a",@progbits
	.globl	_Z9VectorAddPiS_S_i
	.p2align	3, 0x0
_Z9VectorAddPiS_S_i:
	.quad	_Z24__device_stub__VectorAddPiS_S_i
	.size	_Z9VectorAddPiS_S_i, 8

	.type	_Z11VectorAddMNPiS_S_ii,@object # @_Z11VectorAddMNPiS_S_ii
	.globl	_Z11VectorAddMNPiS_S_ii
	.p2align	3, 0x0
_Z11VectorAddMNPiS_S_ii:
	.quad	_Z26__device_stub__VectorAddMNPiS_S_ii
	.size	_Z11VectorAddMNPiS_S_ii, 8

	.type	_Z13VectorAddMN_2PiS_S_ii,@object # @_Z13VectorAddMN_2PiS_S_ii
	.globl	_Z13VectorAddMN_2PiS_S_ii
	.p2align	3, 0x0
_Z13VectorAddMN_2PiS_S_ii:
	.quad	_Z28__device_stub__VectorAddMN_2PiS_S_ii
	.size	_Z13VectorAddMN_2PiS_S_ii, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"\n %d"
	.size	.L.str, 5

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"| "
	.size	.L.str.1, 3

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"   "
	.size	.L.str.2, 4

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z9VectorAddPiS_S_i"
	.size	.L__unnamed_1, 20

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z11VectorAddMNPiS_S_ii"
	.size	.L__unnamed_2, 24

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z13VectorAddMN_2PiS_S_ii"
	.size	.L__unnamed_3, 26

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z24__device_stub__VectorAddPiS_S_i
	.addrsig_sym _Z26__device_stub__VectorAddMNPiS_S_ii
	.addrsig_sym _Z28__device_stub__VectorAddMN_2PiS_S_ii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z9VectorAddPiS_S_i
	.addrsig_sym _Z11VectorAddMNPiS_S_ii
	.addrsig_sym _Z13VectorAddMN_2PiS_S_ii
	.addrsig_sym _ZSt4cout
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z9VectorAddPiS_S_i     ; -- Begin function _Z9VectorAddPiS_S_i
	.globl	_Z9VectorAddPiS_S_i
	.p2align	8
	.type	_Z9VectorAddPiS_S_i,@function
_Z9VectorAddPiS_S_i:                    ; @_Z9VectorAddPiS_S_i
; %bb.0:
	s_load_b32 s2, s[0:1], 0x18
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_i32_e32 vcc_lo, s2, v0
	s_and_saveexec_b32 s2, vcc_lo
	s_cbranch_execz .LBB0_2
; %bb.1:
	s_load_b128 s[4:7], s[0:1], 0x0
	v_lshlrev_b32_e32 v0, 2, v0
	s_load_b64 s[0:1], s[0:1], 0x10
	s_waitcnt lgkmcnt(0)
	s_clause 0x1
	global_load_b32 v1, v0, s[4:5]
	global_load_b32 v2, v0, s[6:7]
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v1, v2, v1
	global_store_b32 v0, v1, s[0:1]
.LBB0_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z9VectorAddPiS_S_i
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 28
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 3
		.amdhsa_next_free_sgpr 8
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z9VectorAddPiS_S_i, .Lfunc_end0-_Z9VectorAddPiS_S_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 96
; NumSgprs: 10
; NumVgprs: 3
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 1
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 10
; NumVGPRsForWavesPerEU: 3
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z11VectorAddMNPiS_S_ii ; -- Begin function _Z11VectorAddMNPiS_S_ii
	.globl	_Z11VectorAddMNPiS_S_ii
	.p2align	8
	.type	_Z11VectorAddMNPiS_S_ii,@function
_Z11VectorAddMNPiS_S_ii:                ; @_Z11VectorAddMNPiS_S_ii
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x2c
	s_load_b64 s[4:5], s[0:1], 0x18
	v_and_b32_e32 v2, 0x3ff, v0
	v_bfe_u32 v3, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s2, 16
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[0:1], null, s14, s2, v[2:3]
	v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_i32_e32 vcc_lo, s4, v0
	v_cmp_gt_i32_e64 s2, s5, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, vcc_lo, s2
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB1_2
; %bb.1:
	s_load_b128 s[8:11], s[0:1], 0x0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[2:3], null, v0, s4, v[1:2]
	s_load_b64 s[0:1], s[0:1], 0x10
	v_ashrrev_i32_e32 v3, 31, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[2:3]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v2, vcc_lo, s8, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s9, v1, vcc_lo
	v_add_co_u32 v4, vcc_lo, s10, v0
	v_add_co_ci_u32_e32 v5, vcc_lo, s11, v1, vcc_lo
	v_add_co_u32 v0, vcc_lo, s0, v0
	global_load_b32 v2, v[2:3], off
	global_load_b32 v3, v[4:5], off
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v2, v3, v2
	global_store_b32 v[0:1], v2, off
.LBB1_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z11VectorAddMNPiS_S_ii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 6
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z11VectorAddMNPiS_S_ii, .Lfunc_end1-_Z11VectorAddMNPiS_S_ii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 236
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z13VectorAddMN_2PiS_S_ii ; -- Begin function _Z13VectorAddMN_2PiS_S_ii
	.globl	_Z13VectorAddMN_2PiS_S_ii
	.p2align	8
	.type	_Z13VectorAddMN_2PiS_S_ii,@function
_Z13VectorAddMN_2PiS_S_ii:              ; @_Z13VectorAddMN_2PiS_S_ii
; %bb.0:
	s_clause 0x1
	s_load_b32 s6, s[0:1], 0x2c
	s_load_b64 s[2:3], s[0:1], 0x18
	v_and_b32_e32 v1, 0x3ff, v0
	s_add_u32 s4, s0, 32
	s_addc_u32 s5, s1, 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s6, s6, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[2:3], null, s14, s6, v[1:2]
	s_mov_b32 s6, exec_lo
	v_cmpx_gt_i32_e64 s2, v2
	s_cbranch_execz .LBB2_5
; %bb.1:
	s_load_b32 s4, s[4:5], 0xc
	v_bfe_u32 v0, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s4, s4, 16
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_i32_e32 vcc_lo, s3, v1
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB2_5
; %bb.2:                                ; %.preheader
	s_mul_i32 s2, s3, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lt_i32 s2, 1
	s_cbranch_scc1 .LBB2_5
; %bb.3:                                ; %.lr.ph.preheader
	s_ashr_i32 s8, s3, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s4, s3, s8
	s_xor_b32 s9, s4, s8
	s_clause 0x1
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b64 s[0:1], s[0:1], 0x10
	v_cvt_f32_u32_e32 v0, s9
	s_sub_i32 s10, 0, s9
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v0, v0
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v0, 0x4f7ffffe, v0
	v_cvt_u32_f32_e32 v0, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s11, v0
	v_mov_b32_e32 v0, 0
	s_mul_i32 s10, s10, s11
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mul_hi_u32 s12, s11, s10
	s_mov_b32 s10, 0
	s_add_i32 s11, s11, s12
	s_lshr_b32 s12, s3, 31
.LBB2_4:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_mul_hi_u32 s13, s10, s11
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_mul_i32 s14, s13, s9
	s_add_i32 s15, s13, 1
	s_sub_i32 s14, s10, s14
	s_sub_i32 s16, s14, s9
	s_cmp_ge_u32 s14, s9
	s_cselect_b32 s13, s15, s13
	s_cselect_b32 s14, s16, s14
	s_add_i32 s15, s13, 1
	s_cmp_ge_u32 s14, s9
	s_cselect_b32 s13, s15, s13
	s_add_i32 s15, s12, s10
	s_xor_b32 s13, s13, s8
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_sub_i32 s14, s13, s8
	s_mul_i32 s14, s14, s3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_sub_i32 s13, s13, s14
	s_add_i32 s14, s15, s13
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_ashr_i32 s15, s14, 31
	s_lshl_b64 s[14:15], s[14:15], 2
	s_waitcnt lgkmcnt(0)
	s_add_u32 s16, s4, s14
	s_addc_u32 s17, s5, s15
	s_add_u32 s18, s6, s14
	s_addc_u32 s19, s7, s15
	s_clause 0x1
	global_load_b32 v1, v0, s[16:17]
	global_load_b32 v2, v0, s[18:19]
	s_add_u32 s14, s0, s14
	s_addc_u32 s15, s1, s15
	s_add_i32 s10, s10, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u32 s2, s10
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v1, v2, v1
	global_store_b32 v0, v1, s[14:15]
	s_cbranch_scc1 .LBB2_4
.LBB2_5:                                ; %.loopexit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z13VectorAddMN_2PiS_S_ii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 4
		.amdhsa_next_free_sgpr 20
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_Z13VectorAddMN_2PiS_S_ii, .Lfunc_end2-_Z13VectorAddMN_2PiS_S_ii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 432
; NumSgprs: 22
; NumVgprs: 4
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 22
; NumVGPRsForWavesPerEU: 4
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 28
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z9VectorAddPiS_S_i
    .private_segment_fixed_size: 0
    .sgpr_count:     10
    .sgpr_spill_count: 0
    .symbol:         _Z9VectorAddPiS_S_i.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     3
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z11VectorAddMNPiS_S_ii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z11VectorAddMNPiS_S_ii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     6
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z13VectorAddMN_2PiS_S_ii
    .private_segment_fixed_size: 0
    .sgpr_count:     22
    .sgpr_spill_count: 0
    .symbol:         _Z13VectorAddMN_2PiS_S_ii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     4
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
