/*
 ============================================================================
 Name        : NavierStokesSolver.cu
 Author      : Matt Kennedy
 Version     : 1.0
 Description : Solve the Navier-Stokes over a flat plate
 ============================================================================
 */

#include <iostream>
#include <numeric>
#include <stdlib.h>
#include <stdio.h>
#include <string.h>

using namespace std;



#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(cudaError_t code, const char *file, int line, bool abort=true)
{
   if (code != cudaSuccess)
   {
      fprintf(stderr,"GPUassert: %s %s %d\n", cudaGetErrorString(code), file, line);
      if (abort) exit(code);
   }
}



// ================================================================
// ================================================================
// define any configuration parameters needed by both CPU and GPU
// ================================================================
// ================================================================

// note that we'll probably get segfaults if the cpu and gpu variables are set to different values!
// (they didn't seem to be happy trying to set one from the other, so need to manually change both for now)
// (and host code isn't happy about reading from a device global variable)
int jmax = 70;
int kmax = 70;
__constant__ int jmax_d = 70;
__constant__ int kmax_d = 70;

double plateLength = 0.00001;
__constant__ double plateLength_d = 0.00001;

double CFL = 0.2; // can fudge this to help stability
__constant__ double CFL_d = 0.2; // can fudge this to help stability

double M0 = 4.0;

double dx = plateLength / (jmax - 1); // uniform for now
//double dy = plateLength / (kmax - 1);
double dy = 1.1869 * pow(10.0,-7); // calculated from boundary layer


__constant__ double u0_d = 1361.12;



// ================================================================
// ================================================================
// define any global variables needed by the GPU
// ================================================================
// ================================================================

__constant__ double gam_d = 1.4; // seems "gamma" is a protected name from the numeric library
__constant__ double Pr_d = 0.71; // Prandtl number
__constant__ double R_d = 287.0; // specific gas constant
__constant__ double Cv_d = 0.7171*1000; // specific heat capacity of air
__constant__ double Cp_d = 1.006 * 1000; // specific heat capacity of air
__constant__ double mu0_d = 1.7894E-5; // dynamic viscosity of air
__constant__ double T0_d = 288.16;
__constant__ double p0_d = 101325.0;



// ================================================================
// ================================================================
// define any global variables needed by the CPU
// ================================================================
// ================================================================


double a0 = 340.28;
double u0 = M0*a0;

double p0 = 101325.0;
double T0 = 288.16;


double v0 = 0;

double gam = 1.4; // seems "gamma" is a protected name from the numeric library
double Pr = 0.71; // Prandtl number
double R = 287.0; // specific gas constant
double Cv = 0.7171*1000; // specific heat capacity of air
double Cp = 1.006 * 1000; // specific heat capacity of air

double rho0 = p0 / (R * T0);
double e0 = T0 * Cv;

double mu0 = 1.7894E-5; // dynamic viscosity of air
double Re = rho0 * u0 * plateLength / mu0;







__device__ void calc_Q(double* Q_d, double* u_d, double* v_d, double* p_d, double* T_d, int j, int k) {

	int ind2 = j*kmax_d + k; // flattened index for our 2d arrays
	int ind3_0 = (j + 0*jmax_d)*kmax_d + k; // flattened index for the first dim of our 3d arrays
	int ind3_1 = (j + 1*jmax_d)*kmax_d + k; // stack them like extra rows
	int ind3_2 = (j + 2*jmax_d)*kmax_d + k;
	int ind3_3 = (j + 3*jmax_d)*kmax_d + k;

	double rho_val = p_d[ind2] / (R_d * T_d[ind2]);
	double e_val = Cv_d * T_d[ind2]; // energy of air based on temp
	double Et_val = rho_val * (e_val + 0.5*(u_d[ind2]*u_d[ind2] + v_d[ind2]*v_d[ind2]));

	Q_d[ind3_0] = rho_val;
	Q_d[ind3_1] = rho_val * u_d[ind2];
	Q_d[ind3_2] = rho_val * v_d[ind2];
	Q_d[ind3_3] = Et_val;

}


__device__ void heatFluxParameters(double* T_d, double mu_val, bool isPredictor, int j, int k, double dx, double dy, double* q) {

	double dTdx;
	double dTdy;

	if (isPredictor) { // scheme is forward, make this backward

		if (j > 0)
			dTdx = (T_d[j*kmax_d + k] - T_d[(j-1)*kmax_d + k])/dx;
		else if (j == 0)
			dTdx = (T_d[(j+1)*kmax_d + k] - T_d[j*kmax_d + k])/dx;

		if (k > 0)
			dTdy = (T_d[j*kmax_d + k] - T_d[j*kmax_d + (k-1)])/dy;
		else if (k == 0)
			dTdy = (T_d[j*kmax_d + k + 1] - T_d[j*kmax_d + k])/dy;

	}
	else { // scheme is backward, make this forward

		if (j < jmax_d-1)
			dTdx = (T_d[(j+1)*kmax_d + k] - T_d[j*kmax_d + k])/dx;
		else if (j == jmax_d - 1)
			dTdx = (T_d[j*kmax_d + k] - T_d[(j-1)*kmax_d + k]) / dx;

		if (k < kmax_d-1)
			dTdy = (T_d[j*kmax_d+k+1] - T_d[j*kmax_d + k]) / dy;
		else if (k == kmax_d - 1)
			dTdy = (T_d[j*kmax_d + k] - T_d[j*kmax_d + k-1]) / dy;

	}

	double k_cond = mu_val * Cp_d / Pr_d;

	q[0] = -k_cond * dTdx;
	q[1] = -k_cond * dTdy;
}

__device__ void shearParameters(double* u_d, double* v_d, double mu, bool isPredictor, int j, int k, double dx, double dy, double* shears) {

	// calculate shear for a single location (j,k)
	// inputs are assumed to be entire matrices

	double dvdx_FB;
	double dudx_FB;
	double dvdy_FB;
	double dudy_FB;
	double dvdx_C;
	double dudx_C;
	double dvdy_C;
	double dudy_C;

	// calculate the forward or backward differenced versions
	if (isPredictor) {
	    // want opposite direction from scheme step differencing
	    // scheme is forward, make this backward

	    if (j > 0) {
	        dvdx_FB = (v_d[j*kmax_d + k] - v_d[(j-1)*kmax_d + k])/dx;
	        dudx_FB = (u_d[j*kmax_d + k] - u_d[(j-1)*kmax_d + k])/dx;
	    }
	    else {
	        dvdx_FB = (v_d[(j+1)*kmax_d + k] - v_d[j*kmax_d + k])/dx; // except first point forward
	        dudx_FB = (u_d[(j+1)*kmax_d + k] - u_d[j*kmax_d + k])/dx; // except first point forward
	    }



	    if (k > 0) {
	        dudy_FB = (u_d[j*kmax_d+k] - u_d[j*kmax_d+k-1])/dy;
	        dvdy_FB = (v_d[j*kmax_d+k] - v_d[j*kmax_d+k-1])/dy;
	    }
	    else {
	        dudy_FB = (u_d[j*kmax_d+k+1] - u_d[j*kmax_d+k])/dy; // except first point forward
	        dvdy_FB = (v_d[j*kmax_d+k+1] - v_d[j*kmax_d+k])/dy; // except first point forward
	    }

	}
	else {

	    // scheme is backward, make this forward

	    if (j < jmax_d - 1) {
	        dvdx_FB = (v_d[(j+1)*kmax_d + k] - v_d[j*kmax_d + k])/dx;
	        dudx_FB = (u_d[(j+1)*kmax_d + k] - u_d[j*kmax_d + k])/dx;
	    }
	    else {
	        dvdx_FB = (v_d[j*kmax_d+k] - v_d[(j-1)*kmax_d + k])/dx; // except jmax backward
	        dudx_FB = (u_d[j*kmax_d+k] - u_d[(j-1)*kmax_d + k])/dx; // except jmax backward
	    }

	    if (k < kmax_d-1) {
	        dudy_FB = (u_d[j*kmax_d + k+1] - u_d[j*kmax_d + k])/dy;
	        dvdy_FB = (v_d[j*kmax_d + k+1] - v_d[j*kmax_d + k])/dy;
	    }
	    else {
	    	dudy_FB = (u_d[j*kmax_d + k] - u_d[j*kmax_d + k-1])/dy; // except kmax backward
			dvdy_FB = (v_d[j*kmax_d + k] - v_d[j*kmax_d + k-1])/dy; // except kmax backward
	    }


	}

	// and then we want centeral differenced versions

	if (j == 0) {
	    dvdx_C = (v_d[(j+1)*kmax_d + k] - v_d[j*kmax_d + k])/dx;
	    dudx_C = (u_d[(j+1)*kmax_d + k] - u_d[j*kmax_d + k])/dx;
	}
	else if (j == jmax_d - 1)
	{
	    dvdx_C = (v_d[j*kmax_d + k] - v_d[(j-1)*kmax_d + k])/dx;
	    dudx_C = (u_d[j*kmax_d + k] - u_d[(j-1)*kmax_d + k])/dx;
	}
	else {
	    dvdx_C = (v_d[(j+1)*kmax_d + k] - v_d[(j-1)*kmax_d + k])/(2*dx);
	    dudx_C = (u_d[(j+1)*kmax_d + k] - u_d[(j-1)*kmax_d + k])/(2*dx);
	}



	if (k == 0) {
	    dudy_C = (u_d[j*kmax_d + k+1] - u_d[j*kmax_d + k])/dy;
	    dvdy_C = (v_d[j*kmax_d + k+1] - v_d[j*kmax_d + k])/dy;
	}
	else if (k == kmax_d-1) {
	    dudy_C = (u_d[j*kmax_d + k] - u_d[j*kmax_d + k-1])/dy;
	    dvdy_C = (v_d[j*kmax_d + k] - v_d[j*kmax_d + k-1])/dy;
	}
	else {
	    dudy_C = (u_d[j*kmax_d + k+1] - u_d[j*kmax_d + k-1])/(2*dy);
	    dvdy_C = (v_d[j*kmax_d + k+1] - v_d[j*kmax_d + k-1])/(2*dy);
	}


	// these come from page 65 and 66 in Anderson

	double lambda = -(2.0/3.0) * mu; // second viscosity coefficient estimated by Stokes

	// use the forward/backward du/dx and central dv/dy for both F and G
	double txx = lambda * ( dudx_FB + dvdy_C ) + 2 * mu * dudx_FB;

	// use the forward/backward dv/dy and central du/dx for both F and G
	double tyy = lambda * ( dudx_C + dvdy_FB ) + 2 * mu * dvdy_FB;

	double txy_F = mu * ( dvdx_FB + dudy_C );
	double txy_G = mu * ( dvdx_C + dudy_FB );

	shears[0] = txx;
	shears[1] = tyy;
	shears[2] = txy_F;
	shears[3] = txy_G;

}


__device__ void calc_FG(double* F_d, double* G_d, double* u_d, double* v_d, double* p_d, double* T_d, bool isPredictor, int j, int k, double dx, double dy) {

	int ind2 = j*kmax_d + k; // flattened index for our 2d arrays
	int ind3_0 = (j + 0*jmax_d)*kmax_d + k; // flattened index for the first dim of our 3d arrays
	int ind3_1 = (j + 1*jmax_d)*kmax_d + k; // stack them like extra rows
	int ind3_2 = (j + 2*jmax_d)*kmax_d + k;
	int ind3_3 = (j + 3*jmax_d)*kmax_d + k;

	double rho_val = p_d[ind2] / (R_d * T_d[ind2]);
	double e_val = Cv_d * T_d[ind2]; // energy of air based on temp
	double Et_val = rho_val * (e_val + 0.5*(u_d[ind2]*u_d[ind2] + v_d[ind2]*v_d[ind2]));

	double mu_val = mu0_d * pow(T_d[ind2] / T0_d, 1.5) * (T0_d + 110)/(T_d[ind2] + 110); // sutherlands law

	double q[2];
	double shears[4];

	heatFluxParameters(T_d, mu_val, isPredictor, j, k, dx, dy, q);
	shearParameters(u_d, v_d, mu_val, isPredictor, j, k, dx, dy, shears);

	// and unpack these for easier use
	double qx = q[0];
	double qy = q[1];
	double txx = shears[0];
	double tyy = shears[1];
	double txy_F = shears[2];
	double txy_G = shears[3];


	F_d[ind3_0] = rho_val * u_d[ind2];
	F_d[ind3_1] = rho_val * pow(u_d[ind2],2) + p_d[ind2] - txx;
	F_d[ind3_2] = rho_val * u_d[ind2]*v_d[ind2] - txy_F;
	F_d[ind3_3] = (Et_val + p_d[ind2]) * u_d[ind2] - u_d[ind2] * txx - v_d[ind2] * txy_F + qx;

	G_d[ind3_0] = rho_val * v_d[ind2];
	G_d[ind3_1] = rho_val * u_d[ind2] * v_d[ind2] - txy_G;
	G_d[ind3_2] = rho_val * pow(v_d[ind2],2) + p_d[ind2] - tyy;
	G_d[ind3_3] = (Et_val + p_d[ind2]) * v_d[ind2] - u_d[ind2] * txy_G - v_d[ind2] * tyy + qy;

}


__device__ void MacCormackPredictorUniform(double* Q_pred_d, double* Q_d, double* F_d, double* G_d, double dt, int j, int k, double dx, double dy) {

// DO MACCORMACKS FOR INTERIOR POINTS ONLY
	if (j == 0 || k == 0 || j == jmax_d-1 || k == kmax_d-1)
		return;

	// have each thread calculate all 4 dimensions at a single loc
	double flux;
	for (int dim=0; dim<4; dim++) {

		int ind_this = (j + dim*jmax_d)*kmax_d + k;
		int ind_nextJ = (j+1 + dim*jmax_d)*kmax_d + k;
		int ind_nextK = (j + dim*jmax_d)*kmax_d + k+1;

		flux = (F_d[ind_nextJ] - F_d[ind_this])/dx + (G_d[ind_nextK] - G_d[ind_this])/dy;
		Q_pred_d[ind_this] = Q_d[ind_this] - dt * flux;
	}
}


__device__ void MacCormackCorrectorUniform(double* Q_pred_d, double* Q_d, double* F_d, double* G_d, double dt, int j, int k, double dx, double dy) {

	// DO MACCORMACKS FOR INTERIOR POINTS ONLY
	if (j == 0 || k == 0 || j == jmax_d-1 || k == kmax_d-1)
		return;

	// have each thread calculate all 4 dimensions at a single (j,k) location
	double flux;
	for (int dim=0; dim<4; dim++) {

		int ind_this = (j + dim*jmax_d)*kmax_d + k;
		int ind_prevJ = (j-1 + dim*jmax_d)*kmax_d + k;
		int ind_prevK = (j + dim*jmax_d)*kmax_d + k-1;

		flux = (F_d[ind_this] - F_d[ind_prevJ])/dx + (G_d[ind_this] - G_d[ind_prevK])/dy;
		Q_d[ind_this] = 0.5*( Q_d[ind_this] + Q_pred_d[ind_this] - dt*flux );
	}
}


__device__ void primativesFromQ(double* Q_d, double* rho_d, double* u_d, double* v_d, double* p_d, double* T_d, double* e_d, int j, int k) {

	int ind2 = j*kmax_d + k; // flattened index for our 2d arrays
	int ind3_0 = (j + 0*jmax_d)*kmax_d + k; // flattened index for the first dim of our 3d arrays
	int ind3_1 = (j + 1*jmax_d)*kmax_d + k; // stack them like extra rows
	int ind3_2 = (j + 2*jmax_d)*kmax_d + k;
	int ind3_3 = (j + 3*jmax_d)*kmax_d + k;

	rho_d[ind2] = Q_d[ind3_0];
	u_d[ind2] = Q_d[ind3_1] / Q_d[ind3_0];
	v_d[ind2] = Q_d[ind3_2] / Q_d[ind3_0];
	e_d[ind2] = Q_d[ind3_3] / Q_d[ind3_0] - 0.5*( pow(u_d[ind2], 2) + pow(v_d[ind2], 2) );

	T_d[ind2] = e_d[ind2] / Cv_d;
	p_d[ind2] = Q_d[ind3_0] * R_d * T_d[ind2];

}


__device__ void enforceBC_nonSurface(double* u_d, double* v_d, double* p_d, double* T_d, int j, int k) {

	// need to first establish all the boundary conditions at the non-surface
	// values, and then go back and do the surface boundary conditions

	// this is really only needed if the surface goes all the way to the outflow
	// so that the last surface point can be interpolated with updated values

	int ind = j*kmax_d + k;

	if ( j == 0 && k == 0) {  // leading edge

		u_d[ind] = 0;
		v_d[ind] = 0;
		p_d[ind] = p0_d;
		T_d[ind] = T0_d;
	}
	else if (j == 0 || k == kmax_d-1) { // inflow from upstream OR upper boundary

		u_d[ind] = u0_d;
		v_d[ind] = 0;
		p_d[ind] = p0_d;
		T_d[ind] = T0_d;
	}
	else if (j == jmax_d-1) { // outflow -- extrapolate from interior values
		int ind1 = (j-1)*kmax_d + k;
		int ind2 = (j-2)*kmax_d + k;

		u_d[ind] = 2*u_d[ind1] - u_d[ind2];
		v_d[ind] = 2*v_d[ind1] - v_d[ind2];
		p_d[ind] = 2*p_d[ind1] - p_d[ind2];
		T_d[ind] = 2*T_d[ind1] - T_d[ind2];

	}
}


__device__ void enforceBC_surface(double* u_d, double* v_d, double* p_d, double* T_d, int j, int k) {

	// need to first establish all the boundary conditions at the non-surface
	// values, and then go back and do the surface boundary conditions

	// this is really only needed if the surface goes all the way to the outflow
	// so that the last surface point can be interpolated with updated values

	int ind = j*kmax_d + k;

	if (k == 0 && j > 0){
		u_d[ind] = 0;
		v_d[ind] = 0;
		p_d[ind] = 2*p_d[j*kmax_d + 1] - p_d[j*kmax_d + 2];
		T_d[ind] = T_d[j*kmax_d + 1];
	}

}




__global__ void iterateScheme_part1(double* x_d, double* y_d, double* u_d, double* v_d, double* p_d, double* T_d, double* rho_d, double* e_d, double* Q_d, double* Q_pred_d, double* F_d, double* G_d, double dx, double dy, double dt) {

	int j = blockIdx.x * blockDim.x + threadIdx.x;
	int k = blockIdx.y * blockDim.y + threadIdx.y;

	if (j < jmax_d && k < kmax_d)
	{

		calc_Q(Q_d, u_d, v_d, p_d, T_d, j, k);

		bool isPredictor = true;
		calc_FG(F_d, G_d, u_d, v_d, p_d, T_d, isPredictor, j, k, dx, dy);


		// think we need to actually do different kernel launches here ...
		// seems to be no easy way to sync all blocks, and inherently not all blocks may be executed at once if the grid gets too large

//		MacCormackPredictorUniform(Q_pred_d, Q_d, F_d, G_d, dt, j, k, dx, dy);

	}
}


__global__ void iterateScheme_part2(double* x_d, double* y_d, double* u_d, double* v_d, double* p_d, double* T_d, double* rho_d, double* e_d, double* Q_d, double* Q_pred_d, double* F_d, double* G_d, double dx, double dy, double dt) {

	int j = blockIdx.x * blockDim.x + threadIdx.x;
	int k = blockIdx.y * blockDim.y + threadIdx.y;

	if (j < jmax_d && k < kmax_d)
	{

		// think we need to actually do different kernel launches here ...
		// seems to be no easy way to sync all blocks, and inherently not all blocks may be executed at once if the grid gets too large

		MacCormackPredictorUniform(Q_pred_d, Q_d, F_d, G_d, dt, j, k, dx, dy);

		primativesFromQ(Q_pred_d, rho_d, u_d, v_d, p_d, T_d, e_d, j, k);

	}
}


__global__ void iterateScheme_part3(double* x_d, double* y_d, double* u_d, double* v_d, double* p_d, double* T_d, double* rho_d, double* e_d, double* Q_d, double* Q_pred_d, double* F_d, double* G_d, double dx, double dy, double dt) {

	int j = blockIdx.x * blockDim.x + threadIdx.x;
	int k = blockIdx.y * blockDim.y + threadIdx.y;

	if (j < jmax_d && k < kmax_d)
	{

		enforceBC_nonSurface(u_d, v_d, p_d, T_d, j, k);

	}
}


__global__ void iterateScheme_part4(double* x_d, double* y_d, double* u_d, double* v_d, double* p_d, double* T_d, double* rho_d, double* e_d, double* Q_d, double* Q_pred_d, double* F_d, double* G_d, double dx, double dy, double dt) {

	int j = blockIdx.x * blockDim.x + threadIdx.x;
	int k = blockIdx.y * blockDim.y + threadIdx.y;

	if (j < jmax_d && k < kmax_d)
	{

		enforceBC_surface(u_d, v_d, p_d, T_d, j, k);

	}
}


__global__ void iterateScheme_part5(double* x_d, double* y_d, double* u_d, double* v_d, double* p_d, double* T_d, double* rho_d, double* e_d, double* Q_d, double* Q_pred_d, double* F_d, double* G_d, double dx, double dy, double dt) {

	int j = blockIdx.x * blockDim.x + threadIdx.x;
	int k = blockIdx.y * blockDim.y + threadIdx.y;

	if (j < jmax_d && k < kmax_d)
	{

		bool isPredictor = false;
		calc_FG(F_d, G_d, u_d, v_d, p_d, T_d, isPredictor, j, k, dx, dy);

	}
}


__global__ void iterateScheme_part6(double* x_d, double* y_d, double* u_d, double* v_d, double* p_d, double* T_d, double* rho_d, double* e_d, double* Q_d, double* Q_pred_d, double* F_d, double* G_d, double dx, double dy, double dt) {

	int j = blockIdx.x * blockDim.x + threadIdx.x;
	int k = blockIdx.y * blockDim.y + threadIdx.y;

	if (j < jmax_d && k < kmax_d)
	{

		MacCormackCorrectorUniform(Q_pred_d, Q_d, F_d, G_d, dt, j, k, dx, dy);

		primativesFromQ(Q_d, rho_d, u_d, v_d, p_d, T_d, e_d, j, k);

	}
}


__global__ void iterateScheme_part7(double* x_d, double* y_d, double* u_d, double* v_d, double* p_d, double* T_d, double* rho_d, double* e_d, double* Q_d, double* Q_pred_d, double* F_d, double* G_d, double dx, double dy, double dt) {

	int j = blockIdx.x * blockDim.x + threadIdx.x;
	int k = blockIdx.y * blockDim.y + threadIdx.y;

	if (j < jmax_d && k < kmax_d)
	{

		enforceBC_nonSurface(u_d, v_d, p_d, T_d, j, k);

	}
}


__global__ void iterateScheme_part8(double* x_d, double* y_d, double* u_d, double* v_d, double* p_d, double* T_d, double* rho_d, double* e_d, double* Q_d, double* Q_pred_d, double* F_d, double* G_d, double dx, double dy, double dt) {

	int j = blockIdx.x * blockDim.x + threadIdx.x;
	int k = blockIdx.y * blockDim.y + threadIdx.y;

	if (j < jmax_d && k < kmax_d)
	{

		enforceBC_surface(u_d, v_d, p_d, T_d, j, k);

	}
}






double BoundaryLayerThickness() {
	return 5 * plateLength / sqrt(Re);
}

void setupGrid(double* x, double* y) {
	// just do a uniform grid for now

	for (int j=0; j<jmax; j++)
		x[j] = j*dx;
	for (int k=0; k<kmax; k++)
		y[k] = k*dy;
}

void initializePrimatives(double* u, double* v, double* p, double* T, double* rho, double* e) {

	for (int j=0; j<jmax; j++) {
		for (int k=0; k<kmax; k++) {
			u[j*kmax+k] = u0;
			v[j*kmax+k] = v0;
			p[j*kmax+k] = p0;
			T[j*kmax+k] = T0;
			rho[j*kmax+k] = rho0;
			e[j*kmax+k] = e0;
		}
	}
}


void applyBC_UpperPlate(double* u, double* v, double* p, double* T) {


	// leading edge
	u[0*kmax+0] = 0;
	v[0*kmax+0] = 0;
	p[0*kmax+0] = p0;
	T[0*kmax+0] = T0;

	// inflow (j=0, k=all)
	for (int k=0; k<kmax; k++) {
		u[0*kmax+k] = u0;
		v[0*kmax+k] = 0;
		p[0*kmax+k] = p0;
		T[0*kmax+k] = T0;
	}

	// upper boundary (j=all, k=kmax-1)
	for (int j=0; j<jmax; j++) {
		u[j*kmax+kmax-1] = u0;
		v[j*kmax+kmax-1] = 0;
		p[j*kmax+kmax-1] = p0;
		T[j*kmax+kmax-1] = T0;
	}

	// outflow (j=jmax-1, k=all)
	// extrapolate from interior values
	for (int k=0; k<kmax; k++) {
		u[(jmax-1)*kmax + k] = 2*u[(jmax-2)*kmax + k] - u[(jmax-3)*kmax + k];
		v[(jmax-1)*kmax + k] = 2*v[(jmax-2)*kmax + k] - v[(jmax-3)*kmax + k];
		p[(jmax-1)*kmax + k] = 2*p[(jmax-2)*kmax + k] - p[(jmax-3)*kmax + k];
		T[(jmax-1)*kmax + k] = 2*T[(jmax-2)*kmax + k] - T[(jmax-3)*kmax + k];
	}

	// and plate surface (j=all, k=0)
	for (int j=0; j<jmax; j++) {
		u[j*kmax + 0] = 0;
		v[j*kmax + 0] = 0;
		p[j*kmax + 0] = 2*p[j*kmax + 1] - p[j*kmax + 2];
		T[j*kmax + 0] = T[j*kmax + 1];
	}


}


double calc_dt(double* u, double* v, double* p, double* T, double dx, double dy) {

	// not sure the best way to do this on the GPU
	// seems to be some parallel reduce functions which can be called as their own kernels
	// which would at least prevent us from having to copy back the primative variables to the host every iteration
	// but lets not worry about that for now

	double rho_val;
	double mu_val;
	double temp_val;

	double vprime = -INFINITY;
	for (int j=0; j<jmax; j++) {
		for (int k=0; k<kmax; k++) {

			int ind = j*kmax + k;

			rho_val = p[ind] / (R * T[ind]);
			mu_val = mu0 * pow(T[ind]/T0, 1.5) * (T0 + 110)/(T[ind] + 110);

			temp_val = (4/3) * mu_val * (gam * mu_val / Pr) / rho_val; // find the max of this
			if (temp_val > vprime)
				vprime = temp_val;
		}
	}

	double spaceUnit = pow( 1/(dx*dx) + 1/(dy*dy), 0.5 );
	double term1;
	double term2;
	double term3;
	double term4;
	double dt_cfl;

	double dt = INFINITY;
	for (int j=0; j<jmax; j++) {
		for (int k=0; k<kmax; k++) {

			int ind = j*kmax + k;

			rho_val = p[ind] / (R * T[ind]);

			term1 = abs( u[ind] ) / dx;
			term2 = abs( v[ind] ) / dy;
			term3 = pow( gam*p[ind]/rho_val, 0.5 ) * spaceUnit;
			term4 = 2 * vprime * pow(spaceUnit, 2);

			dt_cfl = 1/(term1 + term2 + term3 + term4);

			if (CFL*dt_cfl < dt)
				dt = CFL*dt_cfl;
		}
	}

	return dt;
}



void arrayToCSV(double* values, char* filename, int numDims) {
 FILE *fp;
 fp = fopen(filename, "w+");

 for (int dim=0; dim<numDims; dim++) {
	 for (int j=0; j<jmax; j++) {
		 for (int k=0; k<kmax; k++) {

			 fprintf(fp, ", %f", values[(j + dim*jmax)*kmax + k]);
		 }
		 fprintf(fp, "\n");
	 }

	 if (dim < numDims-1)
		 fprintf(fp, "Dimension Starting: %i\n", dim+1);
 }


}


int main(void)
{

	double* x = (double*)malloc(jmax*sizeof(double));
	double* y = (double*)malloc(kmax*sizeof(double));

	double* u = (double*)malloc( jmax*kmax*sizeof(double) );
	double* v = (double*)malloc( jmax*kmax*sizeof(double) );
	double* p = (double*)malloc( jmax*kmax*sizeof(double) );
	double* T = (double*)malloc( jmax*kmax*sizeof(double) );
	double* rho = (double*)malloc( jmax*kmax*sizeof(double) );
	double* e = (double*)malloc( jmax*kmax*sizeof(double) );



	initializePrimatives(u, v, p, T, rho, e);
	applyBC_UpperPlate(u, v, p, T);




	// technically only needed in GPU memory, but I assume we may want to copy back intermediate results for debugging
	// calculating these will be a main component of what's being done in parallel, so don't need to initialize anything
	double* Q = (double*)malloc( 4*jmax*kmax*sizeof(double));
	double* Q_pred = (double*)malloc( 4*jmax*kmax*sizeof(double));
	double* F = (double*)malloc( 4*jmax*kmax*sizeof(double));
	double* G = (double*)malloc( 4*jmax*kmax*sizeof(double));


	// iniitialize and allocate device variables
	double* x_d;
	double* y_d;
	double* u_d;
	double* v_d;
	double* p_d;
	double* T_d;
	double* rho_d;
	double* e_d;
	double* Q_d;
	double* Q_pred_d;
	double* F_d;
	double* G_d;

	cudaError_t err;

	err = cudaMalloc((void**)&x_d, jmax*kmax*sizeof(double) );
	err = cudaMalloc((void**)&y_d, jmax*kmax*sizeof(double) );
	err = cudaMalloc((void**)&u_d, jmax*kmax*sizeof(double) );
	err = cudaMalloc((void**)&v_d, jmax*kmax*sizeof(double) );
	err = cudaMalloc((void**)&p_d, jmax*kmax*sizeof(double) );
	err = cudaMalloc((void**)&T_d, jmax*kmax*sizeof(double) );
	err = cudaMalloc((void**)&rho_d, jmax*kmax*sizeof(double) );
	err = cudaMalloc((void**)&e_d, jmax*kmax*sizeof(double) );

	// these are all 3d arrays
	err = cudaMalloc((void**)&Q_d, 4*jmax*kmax*sizeof(double) );
	err = cudaMalloc((void**)&Q_pred_d, 4*jmax*kmax*sizeof(double) );
	err = cudaMalloc((void**)&F_d, 4*jmax*kmax*sizeof(double) );
	err = cudaMalloc((void**)&G_d, 4*jmax*kmax*sizeof(double) );


	err = cudaMemcpy(x_d, x, jmax*kmax*sizeof(double), cudaMemcpyHostToDevice);
	err = cudaMemcpy(y_d, y, jmax*kmax*sizeof(double), cudaMemcpyHostToDevice);
	err = cudaMemcpy(u_d, u, jmax*kmax*sizeof(double), cudaMemcpyHostToDevice);
	err = cudaMemcpy(v_d, v, jmax*kmax*sizeof(double), cudaMemcpyHostToDevice);
	err = cudaMemcpy(p_d, p, jmax*kmax*sizeof(double), cudaMemcpyHostToDevice);
	err = cudaMemcpy(T_d, T, jmax*kmax*sizeof(double), cudaMemcpyHostToDevice);
	err = cudaMemcpy(rho_d, rho, jmax*kmax*sizeof(double), cudaMemcpyHostToDevice);
	gpuErrchk( cudaMemcpy(e_d, e, jmax*kmax*sizeof(double), cudaMemcpyHostToDevice) );






	dim3 threadsPerBlock(16,16);
	dim3 numBlocks(jmax/threadsPerBlock.x + 1, kmax/threadsPerBlock.y + 1);

	// so to force the threads to sync I think it's safer to just do the different stages in different kernel calls, at least initially
	int maxIter = 1000;
	for (int iter=0; iter<maxIter; iter++) {

		printf("Calculating iteration %i / %i\n", iter+1, maxIter);

		double dt = calc_dt(u, v, p, T, dx, dy);

		// calculate F, G, and Q
		iterateScheme_part1<<<numBlocks, threadsPerBlock>>> (x_d, y_d, u_d, v_d, p_d, T_d, rho_d, e_d, Q_d, Q_pred_d, F_d, G_d, dx, dy, dt);
		gpuErrchk( cudaPeekAtLastError() );
		gpuErrchk( cudaDeviceSynchronize() );


		// calculate MacCormack's Predictor and get back primatives out of Q
		iterateScheme_part2<<<numBlocks, threadsPerBlock>>> (x_d, y_d, u_d, v_d, p_d, T_d, rho_d, e_d, Q_d, Q_pred_d, F_d, G_d, dx, dy, dt);
		gpuErrchk( cudaPeekAtLastError() );
		gpuErrchk( cudaDeviceSynchronize() );

		// enforce boundary conditions at non-surface points
		iterateScheme_part3<<<numBlocks, threadsPerBlock>>> (x_d, y_d, u_d, v_d, p_d, T_d, rho_d, e_d, Q_d, Q_pred_d, F_d, G_d, dx, dy, dt);
		gpuErrchk( cudaPeekAtLastError() );
		gpuErrchk( cudaDeviceSynchronize() );

		// enforce boundary conditions at surface points
		iterateScheme_part4<<<numBlocks, threadsPerBlock>>> (x_d, y_d, u_d, v_d, p_d, T_d, rho_d, e_d, Q_d, Q_pred_d, F_d, G_d, dx, dy, dt);
		gpuErrchk( cudaPeekAtLastError() );
		gpuErrchk( cudaDeviceSynchronize() );

		// update F and G for corrected primatives
		iterateScheme_part5<<<numBlocks, threadsPerBlock>>> (x_d, y_d, u_d, v_d, p_d, T_d, rho_d, e_d, Q_d, Q_pred_d, F_d, G_d, dx, dy, dt);
		gpuErrchk( cudaPeekAtLastError() );
		gpuErrchk( cudaDeviceSynchronize() );

		// calculate MacCormack's Corrector and get back primatives out of Q
		iterateScheme_part6<<<numBlocks, threadsPerBlock>>> (x_d, y_d, u_d, v_d, p_d, T_d, rho_d, e_d, Q_d, Q_pred_d, F_d, G_d, dx, dy, dt);
		gpuErrchk( cudaPeekAtLastError() );
		gpuErrchk( cudaDeviceSynchronize() );

		// enforce boundary conditions at non-surface points
		iterateScheme_part7<<<numBlocks, threadsPerBlock>>> (x_d, y_d, u_d, v_d, p_d, T_d, rho_d, e_d, Q_d, Q_pred_d, F_d, G_d, dx, dy, dt);
		gpuErrchk( cudaPeekAtLastError() );
		gpuErrchk( cudaDeviceSynchronize() );

		// enforce boundary conditions at surface points
		iterateScheme_part8<<<numBlocks, threadsPerBlock>>> (x_d, y_d, u_d, v_d, p_d, T_d, rho_d, e_d, Q_d, Q_pred_d, F_d, G_d, dx, dy, dt);
		gpuErrchk( cudaPeekAtLastError() );
		gpuErrchk( cudaDeviceSynchronize() );

		cudaMemcpy(u, u_d, jmax*kmax*sizeof(double), cudaMemcpyDeviceToHost);
		cudaMemcpy(v, v_d, jmax*kmax*sizeof(double), cudaMemcpyDeviceToHost);
		cudaMemcpy(p, p_d, jmax*kmax*sizeof(double), cudaMemcpyDeviceToHost);
		cudaMemcpy(T, T_d, jmax*kmax*sizeof(double), cudaMemcpyDeviceToHost);

	}


	cudaMemcpy(F, F_d, 4*jmax*kmax*sizeof(double), cudaMemcpyDeviceToHost);
	cudaMemcpy(G, G_d, 4*jmax*kmax*sizeof(double), cudaMemcpyDeviceToHost);
	cudaMemcpy(Q, Q_d, 4*jmax*kmax*sizeof(double), cudaMemcpyDeviceToHost);

	arrayToCSV(u, "u.csv", 1);
	arrayToCSV(v, "v.csv", 1);
	arrayToCSV(p, "p.csv", 1);
	arrayToCSV(T, "T.csv", 1);

	arrayToCSV(F, "F.csv", 4);
	arrayToCSV(G, "G.csv", 4);
	arrayToCSV(Q, "Q.csv", 4);






	free(x);
	free(y);
	free(u);
	free(v);
	free(p);
	free(T);
	free(rho);
	free(e);
	free(Q);
	free(Q_pred);
	free(F);
	free(G);

	cudaFree(x_d);
	cudaFree(y_d);
	cudaFree(u_d);
	cudaFree(v_d);
	cudaFree(p_d);
	cudaFree(T_d);
	cudaFree(rho_d);
	cudaFree(e_d);

	cudaFree(Q_d);
	cudaFree(Q_pred_d);
	cudaFree(F_d);
	cudaFree(G_d);

	printf("Finishing!\n");

	return 0;
}


	.file	"tmpxft_003502ac_00000000-6_NavierStokesSolver.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3694:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3694:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.section	.rodata._Z9gpuAssert9cudaErrorPKcib.str1.1,"aMS",@progbits,1
.LC0:
	.string	"GPUassert: %s %s %d\n"
	.section	.text._Z9gpuAssert9cudaErrorPKcib,"axG",@progbits,_Z9gpuAssert9cudaErrorPKcib,comdat
	.weak	_Z9gpuAssert9cudaErrorPKcib
	.type	_Z9gpuAssert9cudaErrorPKcib, @function
_Z9gpuAssert9cudaErrorPKcib:
.LFB3674:
	.cfi_startproc
	endbr64
	testl	%edi, %edi
	je	.L8
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	movl	%ecx, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 24
	.cfi_offset 3, -24
	movl	%edi, %ebx
	subq	$24, %rsp
	.cfi_def_cfa_offset 48
	movl	%edx, 12(%rsp)
	movq	%rsi, (%rsp)
	call	cudaGetErrorString@PLT
	movl	12(%rsp), %r9d
	movq	(%rsp), %r8
	leaq	.LC0(%rip), %rdx
	movq	stderr(%rip), %rdi
	movq	%rax, %rcx
	movl	$2, %esi
	xorl	%eax, %eax
	call	__fprintf_chk@PLT
	testb	%bpl, %bpl
	je	.L2
	movl	%ebx, %edi
	call	exit@PLT
.L2:
	addq	$24, %rsp
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	ret
.L8:
	.cfi_restore 3
	.cfi_restore 6
	ret
	.cfi_endproc
.LFE3674:
	.size	_Z9gpuAssert9cudaErrorPKcib, .-_Z9gpuAssert9cudaErrorPKcib
	.text
	.globl	_Z6calc_QPdS_S_S_S_ii
	.type	_Z6calc_QPdS_S_S_S_ii, @function
_Z6calc_QPdS_S_S_S_ii:
.LFB3676:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE3676:
	.size	_Z6calc_QPdS_S_S_S_ii, .-_Z6calc_QPdS_S_S_S_ii
	.globl	_Z18heatFluxParametersPddbiiddS_
	.type	_Z18heatFluxParametersPddbiiddS_, @function
_Z18heatFluxParametersPddbiiddS_:
.LFB3677:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE3677:
	.size	_Z18heatFluxParametersPddbiiddS_, .-_Z18heatFluxParametersPddbiiddS_
	.globl	_Z15shearParametersPdS_dbiiddS_
	.type	_Z15shearParametersPdS_dbiiddS_, @function
_Z15shearParametersPdS_dbiiddS_:
.LFB3678:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE3678:
	.size	_Z15shearParametersPdS_dbiiddS_, .-_Z15shearParametersPdS_dbiiddS_
	.globl	_Z7calc_FGPdS_S_S_S_S_biidd
	.type	_Z7calc_FGPdS_S_S_S_S_biidd, @function
_Z7calc_FGPdS_S_S_S_S_biidd:
.LFB3679:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE3679:
	.size	_Z7calc_FGPdS_S_S_S_S_biidd, .-_Z7calc_FGPdS_S_S_S_S_biidd
	.globl	_Z26MacCormackPredictorUniformPdS_S_S_diidd
	.type	_Z26MacCormackPredictorUniformPdS_S_S_diidd, @function
_Z26MacCormackPredictorUniformPdS_S_S_diidd:
.LFB3680:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE3680:
	.size	_Z26MacCormackPredictorUniformPdS_S_S_diidd, .-_Z26MacCormackPredictorUniformPdS_S_S_diidd
	.globl	_Z26MacCormackCorrectorUniformPdS_S_S_diidd
	.type	_Z26MacCormackCorrectorUniformPdS_S_S_diidd, @function
_Z26MacCormackCorrectorUniformPdS_S_S_diidd:
.LFB4356:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE4356:
	.size	_Z26MacCormackCorrectorUniformPdS_S_S_diidd, .-_Z26MacCormackCorrectorUniformPdS_S_S_diidd
	.globl	_Z15primativesFromQPdS_S_S_S_S_S_ii
	.type	_Z15primativesFromQPdS_S_S_S_S_S_ii, @function
_Z15primativesFromQPdS_S_S_S_S_S_ii:
.LFB3682:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE3682:
	.size	_Z15primativesFromQPdS_S_S_S_S_S_ii, .-_Z15primativesFromQPdS_S_S_S_S_S_ii
	.globl	_Z20enforceBC_nonSurfacePdS_S_S_ii
	.type	_Z20enforceBC_nonSurfacePdS_S_S_ii, @function
_Z20enforceBC_nonSurfacePdS_S_S_ii:
.LFB3683:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE3683:
	.size	_Z20enforceBC_nonSurfacePdS_S_S_ii, .-_Z20enforceBC_nonSurfacePdS_S_S_ii
	.globl	_Z17enforceBC_surfacePdS_S_S_ii
	.type	_Z17enforceBC_surfacePdS_S_S_ii, @function
_Z17enforceBC_surfacePdS_S_S_ii:
.LFB4358:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE4358:
	.size	_Z17enforceBC_surfacePdS_S_S_ii, .-_Z17enforceBC_surfacePdS_S_S_ii
	.globl	_Z22BoundaryLayerThicknessv
	.type	_Z22BoundaryLayerThicknessv, @function
_Z22BoundaryLayerThicknessv:
.LFB3685:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movsd	.LC1(%rip), %xmm0
	movsd	plateLength(%rip), %xmm1
	mulsd	%xmm0, %xmm1
	movsd	Re(%rip), %xmm0
	movsd	%xmm1, 8(%rsp)
	call	sqrt@PLT
	movsd	8(%rsp), %xmm1
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	divsd	%xmm0, %xmm1
	movaps	%xmm1, %xmm0
	ret
	.cfi_endproc
.LFE3685:
	.size	_Z22BoundaryLayerThicknessv, .-_Z22BoundaryLayerThicknessv
	.globl	_Z9setupGridPdS_
	.type	_Z9setupGridPdS_, @function
_Z9setupGridPdS_:
.LFB3686:
	.cfi_startproc
	endbr64
	movl	jmax(%rip), %edx
	xorl	%eax, %eax
.L33:
	cmpl	%eax, %edx
	jle	.L37
	cvtsi2sdl	%eax, %xmm0
	mulsd	dx(%rip), %xmm0
	movsd	%xmm0, (%rdi,%rax,8)
	incq	%rax
	jmp	.L33
.L37:
	movl	kmax(%rip), %edx
	xorl	%eax, %eax
.L35:
	cmpl	%eax, %edx
	jle	.L38
	cvtsi2sdl	%eax, %xmm0
	mulsd	dy(%rip), %xmm0
	movsd	%xmm0, (%rsi,%rax,8)
	incq	%rax
	jmp	.L35
.L38:
	ret
	.cfi_endproc
.LFE3686:
	.size	_Z9setupGridPdS_, .-_Z9setupGridPdS_
	.globl	_Z20initializePrimativesPdS_S_S_S_S_
	.type	_Z20initializePrimativesPdS_S_S_S_S_, @function
_Z20initializePrimativesPdS_S_S_S_S_:
.LFB3687:
	.cfi_startproc
	endbr64
	pushq	%r12
	.cfi_def_cfa_offset 16
	.cfi_offset 12, -16
	movl	jmax(%rip), %r12d
	movq	%rsi, %r10
	movq	%rdx, %r11
	pushq	%rbp
	.cfi_def_cfa_offset 24
	.cfi_offset 6, -24
	movl	kmax(%rip), %ebp
	xorl	%esi, %esi
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset 3, -32
	movq	%rcx, %rbx
	xorl	%ecx, %ecx
.L40:
	cmpl	%esi, %r12d
	jle	.L39
	movslq	%ecx, %rax
	xorl	%edx, %edx
	salq	$3, %rax
.L43:
	cmpl	%edx, %ebp
	jle	.L45
	movsd	u0(%rip), %xmm0
	incl	%edx
	movsd	%xmm0, (%rdi,%rax)
	movsd	v0(%rip), %xmm0
	movsd	%xmm0, (%r10,%rax)
	movsd	p0(%rip), %xmm0
	movsd	%xmm0, (%r11,%rax)
	movsd	T0(%rip), %xmm0
	movsd	%xmm0, (%rbx,%rax)
	movsd	rho0(%rip), %xmm0
	movsd	%xmm0, (%r8,%rax)
	movsd	e0(%rip), %xmm0
	movsd	%xmm0, (%r9,%rax)
	addq	$8, %rax
	jmp	.L43
.L45:
	incl	%esi
	addl	%ebp, %ecx
	jmp	.L40
.L39:
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3687:
	.size	_Z20initializePrimativesPdS_S_S_S_S_, .-_Z20initializePrimativesPdS_S_S_S_S_
	.globl	_Z18applyBC_UpperPlatePdS_S_S_
	.type	_Z18applyBC_UpperPlatePdS_S_S_, @function
_Z18applyBC_UpperPlatePdS_S_S_:
.LFB3688:
	.cfi_startproc
	endbr64
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	movl	kmax(%rip), %r10d
	movq	%rsi, %r8
	xorl	%eax, %eax
	pushq	%rbx
	.cfi_def_cfa_offset 24
	.cfi_offset 3, -24
	movq	$0x000000000, (%rdi)
	movq	$0x000000000, (%rsi)
	movsd	p0(%rip), %xmm0
	movsd	%xmm0, (%rdx)
	movsd	T0(%rip), %xmm0
	movsd	%xmm0, (%rcx)
.L47:
	cmpl	%eax, %r10d
	jle	.L56
	movsd	u0(%rip), %xmm0
	movsd	%xmm0, (%rdi,%rax,8)
	movq	$0x000000000, (%r8,%rax,8)
	movsd	p0(%rip), %xmm0
	movsd	%xmm0, (%rdx,%rax,8)
	movsd	T0(%rip), %xmm0
	movsd	%xmm0, (%rcx,%rax,8)
	incq	%rax
	jmp	.L47
.L56:
	movslq	%r10d, %r11
	movl	jmax(%rip), %ebx
	xorl	%eax, %eax
	xorl	%esi, %esi
	salq	$3, %r11
.L49:
	addq	%r11, %rax
	cmpl	%esi, %ebx
	jle	.L57
	movsd	u0(%rip), %xmm0
	incl	%esi
	movsd	%xmm0, -8(%rdi,%rax)
	movq	$0x000000000, -8(%r8,%rax)
	movsd	p0(%rip), %xmm0
	movsd	%xmm0, -8(%rdx,%rax)
	movsd	T0(%rip), %xmm0
	movsd	%xmm0, -8(%rcx,%rax)
	jmp	.L49
.L57:
	leal	-2(%rbx), %eax
	xorl	%ebp, %ebp
	imull	%r10d, %eax
	movl	%eax, %esi
	cltq
	subl	%r10d, %esi
	salq	$3, %rax
	movslq	%esi, %r9
	leal	(%rsi,%r10,2), %esi
	movslq	%esi, %rsi
	salq	$3, %r9
	salq	$3, %rsi
.L51:
	cmpl	%ebp, %r10d
	jle	.L58
	movsd	(%rdi,%rax), %xmm0
	incl	%ebp
	addsd	%xmm0, %xmm0
	subsd	(%rdi,%r9), %xmm0
	movsd	%xmm0, (%rdi,%rsi)
	movsd	(%r8,%rax), %xmm0
	addsd	%xmm0, %xmm0
	subsd	(%r8,%r9), %xmm0
	movsd	%xmm0, (%r8,%rsi)
	movsd	(%rdx,%rax), %xmm0
	addsd	%xmm0, %xmm0
	subsd	(%rdx,%r9), %xmm0
	movsd	%xmm0, (%rdx,%rsi)
	movsd	(%rcx,%rax), %xmm0
	addq	$8, %rax
	addsd	%xmm0, %xmm0
	subsd	(%rcx,%r9), %xmm0
	addq	$8, %r9
	movsd	%xmm0, (%rcx,%rsi)
	addq	$8, %rsi
	jmp	.L51
.L58:
	xorl	%eax, %eax
	xorl	%esi, %esi
.L53:
	cmpl	%esi, %ebx
	jle	.L59
	movq	$0x000000000, (%rdi,%rax)
	incl	%esi
	movq	$0x000000000, (%r8,%rax)
	movsd	8(%rdx,%rax), %xmm0
	addsd	%xmm0, %xmm0
	subsd	16(%rdx,%rax), %xmm0
	movsd	%xmm0, (%rdx,%rax)
	movsd	8(%rcx,%rax), %xmm0
	movsd	%xmm0, (%rcx,%rax)
	addq	%r11, %rax
	jmp	.L53
.L59:
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3688:
	.size	_Z18applyBC_UpperPlatePdS_S_S_, .-_Z18applyBC_UpperPlatePdS_S_S_
	.globl	_Z7calc_dtPdS_S_S_dd
	.type	_Z7calc_dtPdS_S_S_dd, @function
_Z7calc_dtPdS_S_S_dd:
.LFB3689:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	xorl	%r15d, %r15d
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movq	%rsi, %r13
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movq	%rdi, %r12
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movq	%rcx, %rbp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movq	%rdx, %rbx
	subq	$72, %rsp
	.cfi_def_cfa_offset 128
	movsd	.LC3(%rip), %xmm6
	movsd	%xmm0, 8(%rsp)
	movsd	%xmm1, 16(%rsp)
	movsd	%xmm6, (%rsp)
.L61:
	movl	jmax(%rip), %r14d
	cmpl	%r15d, %r14d
	jle	.L72
	xorl	%r14d, %r14d
.L64:
	movl	kmax(%rip), %eax
	cmpl	%r14d, %eax
	jle	.L73
	imull	%r15d, %eax
	movsd	R(%rip), %xmm0
	movsd	T0(%rip), %xmm3
	movsd	%xmm3, 32(%rsp)
	addl	%r14d, %eax
	incl	%r14d
	cltq
	movsd	0(%rbp,%rax,8), %xmm2
	movsd	(%rbx,%rax,8), %xmm1
	mulsd	%xmm2, %xmm0
	movsd	%xmm2, 40(%rsp)
	divsd	%xmm0, %xmm1
	movaps	%xmm2, %xmm0
	divsd	%xmm3, %xmm0
	movsd	%xmm1, 24(%rsp)
	movsd	.LC5(%rip), %xmm1
	call	pow@PLT
	movsd	.LC6(%rip), %xmm1
	mulsd	mu0(%rip), %xmm0
	movsd	32(%rsp), %xmm3
	movsd	40(%rsp), %xmm2
	addsd	%xmm1, %xmm3
	addsd	%xmm1, %xmm2
	movsd	gam(%rip), %xmm1
	mulsd	%xmm3, %xmm0
	divsd	%xmm2, %xmm0
	mulsd	%xmm0, %xmm1
	divsd	Pr(%rip), %xmm1
	mulsd	%xmm0, %xmm1
	divsd	24(%rsp), %xmm1
	maxsd	(%rsp), %xmm1
	movsd	%xmm1, (%rsp)
	jmp	.L64
.L73:
	incl	%r15d
	jmp	.L61
.L72:
	movsd	8(%rsp), %xmm1
	movsd	16(%rsp), %xmm2
	xorl	%r15d, %r15d
	movsd	.LC8(%rip), %xmm0
	mulsd	%xmm1, %xmm1
	mulsd	%xmm2, %xmm2
	divsd	%xmm1, %xmm0
	movsd	.LC8(%rip), %xmm1
	divsd	%xmm2, %xmm1
	addsd	%xmm1, %xmm0
	movsd	.LC7(%rip), %xmm1
	call	pow@PLT
	movsd	.LC4(%rip), %xmm3
	movq	.LC9(%rip), %xmm4
	movaps	%xmm0, %xmm2
.L65:
	cmpl	%r15d, %r14d
	jle	.L74
	xorl	%edx, %edx
.L68:
	movl	kmax(%rip), %eax
	cmpl	%edx, %eax
	jle	.L75
	imull	%r15d, %eax
	movl	%edx, 40(%rsp)
	movsd	%xmm3, 56(%rsp)
	movsd	%xmm2, 48(%rsp)
	addl	%edx, %eax
	cltq
	movsd	(%r12,%rax,8), %xmm0
	movsd	0(%rbp,%rax,8), %xmm5
	mulsd	R(%rip), %xmm5
	movsd	(%rbx,%rax,8), %xmm1
	andps	%xmm4, %xmm0
	divsd	8(%rsp), %xmm0
	movsd	%xmm0, 24(%rsp)
	movsd	0(%r13,%rax,8), %xmm0
	andps	%xmm4, %xmm0
	divsd	16(%rsp), %xmm0
	movsd	%xmm0, 32(%rsp)
	movsd	gam(%rip), %xmm0
	mulsd	%xmm1, %xmm0
	divsd	%xmm5, %xmm1
	divsd	%xmm1, %xmm0
	movsd	.LC7(%rip), %xmm1
	call	pow@PLT
	movsd	48(%rsp), %xmm2
	movsd	24(%rsp), %xmm1
	addsd	32(%rsp), %xmm1
	movsd	56(%rsp), %xmm3
	mulsd	%xmm2, %xmm0
	movaps	%xmm2, %xmm5
	movl	40(%rsp), %edx
	movq	.LC9(%rip), %xmm4
	mulsd	%xmm2, %xmm5
	incl	%edx
	addsd	%xmm0, %xmm1
	movsd	(%rsp), %xmm0
	addsd	%xmm0, %xmm0
	mulsd	%xmm5, %xmm0
	addsd	%xmm0, %xmm1
	movsd	.LC8(%rip), %xmm0
	divsd	%xmm1, %xmm0
	mulsd	CFL(%rip), %xmm0
	minsd	%xmm3, %xmm0
	movaps	%xmm0, %xmm3
	jmp	.L68
.L75:
	incl	%r15d
	jmp	.L65
.L74:
	addq	$72, %rsp
	.cfi_def_cfa_offset 56
	movaps	%xmm3, %xmm0
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3689:
	.size	_Z7calc_dtPdS_S_S_dd, .-_Z7calc_dtPdS_S_S_dd
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC10:
	.string	"w+"
.LC11:
	.string	", %f"
.LC12:
	.string	"\n"
.LC13:
	.string	"Dimension Starting: %i\n"
	.text
	.globl	_Z10arrayToCSVPdPci
	.type	_Z10arrayToCSVPdPci, @function
_Z10arrayToCSVPdPci:
.LFB3690:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	xorl	%r14d, %r14d
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	leaq	.LC11(%rip), %r13
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movq	%rdi, %r12
	movq	%rsi, %rdi
	leaq	.LC10(%rip), %rsi
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movl	%edx, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$24, %rsp
	.cfi_def_cfa_offset 80
	call	fopen@PLT
	movq	%rax, 8(%rsp)
.L77:
	cmpl	%ebp, %r14d
	jge	.L85
	xorl	%r15d, %r15d
.L81:
	cmpl	%r15d, jmax(%rip)
	jle	.L86
	xorl	%ebx, %ebx
.L79:
	movl	kmax(%rip), %edx
	cmpl	%ebx, %edx
	jle	.L87
	movl	jmax(%rip), %eax
	movq	8(%rsp), %rdi
	movl	$2, %esi
	imull	%r14d, %eax
	addl	%r15d, %eax
	imull	%edx, %eax
	movq	%r13, %rdx
	addl	%ebx, %eax
	incl	%ebx
	cltq
	movsd	(%r12,%rax,8), %xmm0
	movb	$1, %al
	call	__fprintf_chk@PLT
	jmp	.L79
.L87:
	movq	8(%rsp), %rdi
	movl	$2, %esi
	xorl	%eax, %eax
	incl	%r15d
	leaq	.LC12(%rip), %rdx
	call	__fprintf_chk@PLT
	jmp	.L81
.L86:
	leal	-1(%rbp), %eax
	leal	1(%r14), %r15d
	cmpl	%r14d, %eax
	jle	.L80
	movq	8(%rsp), %rdi
	movl	%r15d, %ecx
	movl	$2, %esi
	xorl	%eax, %eax
	leaq	.LC13(%rip), %rdx
	call	__fprintf_chk@PLT
.L80:
	movl	%r15d, %r14d
	jmp	.L77
.L85:
	addq	$24, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3690:
	.size	_Z10arrayToCSVPdPci, .-_Z10arrayToCSVPdPci
	.globl	_Z64__device_stub__Z19iterateScheme_part1PdS_S_S_S_S_S_S_S_S_S_S_dddPdS_S_S_S_S_S_S_S_S_S_S_ddd
	.type	_Z64__device_stub__Z19iterateScheme_part1PdS_S_S_S_S_S_S_S_S_S_S_dddPdS_S_S_S_S_S_S_S_S_S_S_ddd, @function
_Z64__device_stub__Z19iterateScheme_part1PdS_S_S_S_S_S_S_S_S_S_S_dddPdS_S_S_S_S_S_S_S_S_S_S_ddd:
.LFB3716:
	.cfi_startproc
	endbr64
	subq	$328, %rsp
	.cfi_def_cfa_offset 336
	movq	336(%rsp), %rax
	movq	%rdi, 120(%rsp)
	leaq	144(%rsp), %rdi
	movq	%rsi, 112(%rsp)
	leaq	156(%rsp), %rsi
	movq	%rax, 72(%rsp)
	movq	344(%rsp), %rax
	movq	%rdx, 104(%rsp)
	leaq	128(%rsp), %rdx
	movq	%rax, 64(%rsp)
	movq	352(%rsp), %rax
	movq	%rcx, 96(%rsp)
	leaq	136(%rsp), %rcx
	movq	%rax, 56(%rsp)
	movq	360(%rsp), %rax
	movq	%r8, 88(%rsp)
	movq	%rax, 48(%rsp)
	movq	368(%rsp), %rax
	movq	%r9, 80(%rsp)
	movq	%rax, 40(%rsp)
	movq	376(%rsp), %rax
	movsd	%xmm0, 24(%rsp)
	movq	%rax, 32(%rsp)
	movsd	%xmm1, 16(%rsp)
	movsd	%xmm2, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 312(%rsp)
	xorl	%eax, %eax
	leaq	120(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	112(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	104(%rsp), %rax
	movq	%rax, 208(%rsp)
	leaq	96(%rsp), %rax
	movq	%rax, 216(%rsp)
	leaq	88(%rsp), %rax
	movq	%rax, 224(%rsp)
	leaq	80(%rsp), %rax
	movq	%rax, 232(%rsp)
	leaq	72(%rsp), %rax
	movq	%rax, 240(%rsp)
	leaq	64(%rsp), %rax
	movq	%rax, 248(%rsp)
	leaq	56(%rsp), %rax
	movq	%rax, 256(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 264(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 272(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 280(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 288(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 296(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 304(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 144(%rsp)
	movl	$1, 152(%rsp)
	movq	%rax, 156(%rsp)
	movl	$1, 164(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L88
	pushq	136(%rsp)
	.cfi_def_cfa_offset 344
	leaq	_Z19iterateScheme_part1PdS_S_S_S_S_S_S_S_S_S_S_ddd(%rip), %rdi
	pushq	136(%rsp)
	.cfi_def_cfa_offset 352
	movq	172(%rsp), %rcx
	movl	180(%rsp), %r8d
	movq	160(%rsp), %rsi
	movl	168(%rsp), %edx
	leaq	208(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 344
	popq	%rdx
	.cfi_def_cfa_offset 336
.L88:
	movq	312(%rsp), %rax
	subq	%fs:40, %rax
	je	.L90
	call	__stack_chk_fail@PLT
.L90:
	addq	$328, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3716:
	.size	_Z64__device_stub__Z19iterateScheme_part1PdS_S_S_S_S_S_S_S_S_S_S_dddPdS_S_S_S_S_S_S_S_S_S_S_ddd, .-_Z64__device_stub__Z19iterateScheme_part1PdS_S_S_S_S_S_S_S_S_S_S_dddPdS_S_S_S_S_S_S_S_S_S_S_ddd
	.globl	_Z19iterateScheme_part1PdS_S_S_S_S_S_S_S_S_S_S_ddd
	.type	_Z19iterateScheme_part1PdS_S_S_S_S_S_S_S_S_S_S_ddd, @function
_Z19iterateScheme_part1PdS_S_S_S_S_S_S_S_S_S_S_ddd:
.LFB3717:
	.cfi_startproc
	endbr64
	jmp	_Z64__device_stub__Z19iterateScheme_part1PdS_S_S_S_S_S_S_S_S_S_S_dddPdS_S_S_S_S_S_S_S_S_S_S_ddd
	.cfi_endproc
.LFE3717:
	.size	_Z19iterateScheme_part1PdS_S_S_S_S_S_S_S_S_S_S_ddd, .-_Z19iterateScheme_part1PdS_S_S_S_S_S_S_S_S_S_S_ddd
	.globl	_Z64__device_stub__Z19iterateScheme_part2PdS_S_S_S_S_S_S_S_S_S_S_dddPdS_S_S_S_S_S_S_S_S_S_S_ddd
	.type	_Z64__device_stub__Z19iterateScheme_part2PdS_S_S_S_S_S_S_S_S_S_S_dddPdS_S_S_S_S_S_S_S_S_S_S_ddd, @function
_Z64__device_stub__Z19iterateScheme_part2PdS_S_S_S_S_S_S_S_S_S_S_dddPdS_S_S_S_S_S_S_S_S_S_S_ddd:
.LFB3718:
	.cfi_startproc
	endbr64
	subq	$328, %rsp
	.cfi_def_cfa_offset 336
	movq	336(%rsp), %rax
	movq	%rdi, 120(%rsp)
	leaq	144(%rsp), %rdi
	movq	%rsi, 112(%rsp)
	leaq	156(%rsp), %rsi
	movq	%rax, 72(%rsp)
	movq	344(%rsp), %rax
	movq	%rdx, 104(%rsp)
	leaq	128(%rsp), %rdx
	movq	%rax, 64(%rsp)
	movq	352(%rsp), %rax
	movq	%rcx, 96(%rsp)
	leaq	136(%rsp), %rcx
	movq	%rax, 56(%rsp)
	movq	360(%rsp), %rax
	movq	%r8, 88(%rsp)
	movq	%rax, 48(%rsp)
	movq	368(%rsp), %rax
	movq	%r9, 80(%rsp)
	movq	%rax, 40(%rsp)
	movq	376(%rsp), %rax
	movsd	%xmm0, 24(%rsp)
	movq	%rax, 32(%rsp)
	movsd	%xmm1, 16(%rsp)
	movsd	%xmm2, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 312(%rsp)
	xorl	%eax, %eax
	leaq	120(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	112(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	104(%rsp), %rax
	movq	%rax, 208(%rsp)
	leaq	96(%rsp), %rax
	movq	%rax, 216(%rsp)
	leaq	88(%rsp), %rax
	movq	%rax, 224(%rsp)
	leaq	80(%rsp), %rax
	movq	%rax, 232(%rsp)
	leaq	72(%rsp), %rax
	movq	%rax, 240(%rsp)
	leaq	64(%rsp), %rax
	movq	%rax, 248(%rsp)
	leaq	56(%rsp), %rax
	movq	%rax, 256(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 264(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 272(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 280(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 288(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 296(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 304(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 144(%rsp)
	movl	$1, 152(%rsp)
	movq	%rax, 156(%rsp)
	movl	$1, 164(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L93
	pushq	136(%rsp)
	.cfi_def_cfa_offset 344
	leaq	_Z19iterateScheme_part2PdS_S_S_S_S_S_S_S_S_S_S_ddd(%rip), %rdi
	pushq	136(%rsp)
	.cfi_def_cfa_offset 352
	movq	172(%rsp), %rcx
	movl	180(%rsp), %r8d
	movq	160(%rsp), %rsi
	movl	168(%rsp), %edx
	leaq	208(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 344
	popq	%rdx
	.cfi_def_cfa_offset 336
.L93:
	movq	312(%rsp), %rax
	subq	%fs:40, %rax
	je	.L95
	call	__stack_chk_fail@PLT
.L95:
	addq	$328, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3718:
	.size	_Z64__device_stub__Z19iterateScheme_part2PdS_S_S_S_S_S_S_S_S_S_S_dddPdS_S_S_S_S_S_S_S_S_S_S_ddd, .-_Z64__device_stub__Z19iterateScheme_part2PdS_S_S_S_S_S_S_S_S_S_S_dddPdS_S_S_S_S_S_S_S_S_S_S_ddd
	.globl	_Z19iterateScheme_part2PdS_S_S_S_S_S_S_S_S_S_S_ddd
	.type	_Z19iterateScheme_part2PdS_S_S_S_S_S_S_S_S_S_S_ddd, @function
_Z19iterateScheme_part2PdS_S_S_S_S_S_S_S_S_S_S_ddd:
.LFB3719:
	.cfi_startproc
	endbr64
	jmp	_Z64__device_stub__Z19iterateScheme_part2PdS_S_S_S_S_S_S_S_S_S_S_dddPdS_S_S_S_S_S_S_S_S_S_S_ddd
	.cfi_endproc
.LFE3719:
	.size	_Z19iterateScheme_part2PdS_S_S_S_S_S_S_S_S_S_S_ddd, .-_Z19iterateScheme_part2PdS_S_S_S_S_S_S_S_S_S_S_ddd
	.globl	_Z64__device_stub__Z19iterateScheme_part3PdS_S_S_S_S_S_S_S_S_S_S_dddPdS_S_S_S_S_S_S_S_S_S_S_ddd
	.type	_Z64__device_stub__Z19iterateScheme_part3PdS_S_S_S_S_S_S_S_S_S_S_dddPdS_S_S_S_S_S_S_S_S_S_S_ddd, @function
_Z64__device_stub__Z19iterateScheme_part3PdS_S_S_S_S_S_S_S_S_S_S_dddPdS_S_S_S_S_S_S_S_S_S_S_ddd:
.LFB3720:
	.cfi_startproc
	endbr64
	subq	$328, %rsp
	.cfi_def_cfa_offset 336
	movq	336(%rsp), %rax
	movq	%rdi, 120(%rsp)
	leaq	144(%rsp), %rdi
	movq	%rsi, 112(%rsp)
	leaq	156(%rsp), %rsi
	movq	%rax, 72(%rsp)
	movq	344(%rsp), %rax
	movq	%rdx, 104(%rsp)
	leaq	128(%rsp), %rdx
	movq	%rax, 64(%rsp)
	movq	352(%rsp), %rax
	movq	%rcx, 96(%rsp)
	leaq	136(%rsp), %rcx
	movq	%rax, 56(%rsp)
	movq	360(%rsp), %rax
	movq	%r8, 88(%rsp)
	movq	%rax, 48(%rsp)
	movq	368(%rsp), %rax
	movq	%r9, 80(%rsp)
	movq	%rax, 40(%rsp)
	movq	376(%rsp), %rax
	movsd	%xmm0, 24(%rsp)
	movq	%rax, 32(%rsp)
	movsd	%xmm1, 16(%rsp)
	movsd	%xmm2, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 312(%rsp)
	xorl	%eax, %eax
	leaq	120(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	112(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	104(%rsp), %rax
	movq	%rax, 208(%rsp)
	leaq	96(%rsp), %rax
	movq	%rax, 216(%rsp)
	leaq	88(%rsp), %rax
	movq	%rax, 224(%rsp)
	leaq	80(%rsp), %rax
	movq	%rax, 232(%rsp)
	leaq	72(%rsp), %rax
	movq	%rax, 240(%rsp)
	leaq	64(%rsp), %rax
	movq	%rax, 248(%rsp)
	leaq	56(%rsp), %rax
	movq	%rax, 256(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 264(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 272(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 280(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 288(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 296(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 304(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 144(%rsp)
	movl	$1, 152(%rsp)
	movq	%rax, 156(%rsp)
	movl	$1, 164(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L98
	pushq	136(%rsp)
	.cfi_def_cfa_offset 344
	leaq	_Z19iterateScheme_part3PdS_S_S_S_S_S_S_S_S_S_S_ddd(%rip), %rdi
	pushq	136(%rsp)
	.cfi_def_cfa_offset 352
	movq	172(%rsp), %rcx
	movl	180(%rsp), %r8d
	movq	160(%rsp), %rsi
	movl	168(%rsp), %edx
	leaq	208(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 344
	popq	%rdx
	.cfi_def_cfa_offset 336
.L98:
	movq	312(%rsp), %rax
	subq	%fs:40, %rax
	je	.L100
	call	__stack_chk_fail@PLT
.L100:
	addq	$328, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3720:
	.size	_Z64__device_stub__Z19iterateScheme_part3PdS_S_S_S_S_S_S_S_S_S_S_dddPdS_S_S_S_S_S_S_S_S_S_S_ddd, .-_Z64__device_stub__Z19iterateScheme_part3PdS_S_S_S_S_S_S_S_S_S_S_dddPdS_S_S_S_S_S_S_S_S_S_S_ddd
	.globl	_Z19iterateScheme_part3PdS_S_S_S_S_S_S_S_S_S_S_ddd
	.type	_Z19iterateScheme_part3PdS_S_S_S_S_S_S_S_S_S_S_ddd, @function
_Z19iterateScheme_part3PdS_S_S_S_S_S_S_S_S_S_S_ddd:
.LFB3721:
	.cfi_startproc
	endbr64
	jmp	_Z64__device_stub__Z19iterateScheme_part3PdS_S_S_S_S_S_S_S_S_S_S_dddPdS_S_S_S_S_S_S_S_S_S_S_ddd
	.cfi_endproc
.LFE3721:
	.size	_Z19iterateScheme_part3PdS_S_S_S_S_S_S_S_S_S_S_ddd, .-_Z19iterateScheme_part3PdS_S_S_S_S_S_S_S_S_S_S_ddd
	.globl	_Z64__device_stub__Z19iterateScheme_part4PdS_S_S_S_S_S_S_S_S_S_S_dddPdS_S_S_S_S_S_S_S_S_S_S_ddd
	.type	_Z64__device_stub__Z19iterateScheme_part4PdS_S_S_S_S_S_S_S_S_S_S_dddPdS_S_S_S_S_S_S_S_S_S_S_ddd, @function
_Z64__device_stub__Z19iterateScheme_part4PdS_S_S_S_S_S_S_S_S_S_S_dddPdS_S_S_S_S_S_S_S_S_S_S_ddd:
.LFB3722:
	.cfi_startproc
	endbr64
	subq	$328, %rsp
	.cfi_def_cfa_offset 336
	movq	336(%rsp), %rax
	movq	%rdi, 120(%rsp)
	leaq	144(%rsp), %rdi
	movq	%rsi, 112(%rsp)
	leaq	156(%rsp), %rsi
	movq	%rax, 72(%rsp)
	movq	344(%rsp), %rax
	movq	%rdx, 104(%rsp)
	leaq	128(%rsp), %rdx
	movq	%rax, 64(%rsp)
	movq	352(%rsp), %rax
	movq	%rcx, 96(%rsp)
	leaq	136(%rsp), %rcx
	movq	%rax, 56(%rsp)
	movq	360(%rsp), %rax
	movq	%r8, 88(%rsp)
	movq	%rax, 48(%rsp)
	movq	368(%rsp), %rax
	movq	%r9, 80(%rsp)
	movq	%rax, 40(%rsp)
	movq	376(%rsp), %rax
	movsd	%xmm0, 24(%rsp)
	movq	%rax, 32(%rsp)
	movsd	%xmm1, 16(%rsp)
	movsd	%xmm2, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 312(%rsp)
	xorl	%eax, %eax
	leaq	120(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	112(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	104(%rsp), %rax
	movq	%rax, 208(%rsp)
	leaq	96(%rsp), %rax
	movq	%rax, 216(%rsp)
	leaq	88(%rsp), %rax
	movq	%rax, 224(%rsp)
	leaq	80(%rsp), %rax
	movq	%rax, 232(%rsp)
	leaq	72(%rsp), %rax
	movq	%rax, 240(%rsp)
	leaq	64(%rsp), %rax
	movq	%rax, 248(%rsp)
	leaq	56(%rsp), %rax
	movq	%rax, 256(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 264(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 272(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 280(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 288(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 296(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 304(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 144(%rsp)
	movl	$1, 152(%rsp)
	movq	%rax, 156(%rsp)
	movl	$1, 164(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L103
	pushq	136(%rsp)
	.cfi_def_cfa_offset 344
	leaq	_Z19iterateScheme_part4PdS_S_S_S_S_S_S_S_S_S_S_ddd(%rip), %rdi
	pushq	136(%rsp)
	.cfi_def_cfa_offset 352
	movq	172(%rsp), %rcx
	movl	180(%rsp), %r8d
	movq	160(%rsp), %rsi
	movl	168(%rsp), %edx
	leaq	208(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 344
	popq	%rdx
	.cfi_def_cfa_offset 336
.L103:
	movq	312(%rsp), %rax
	subq	%fs:40, %rax
	je	.L105
	call	__stack_chk_fail@PLT
.L105:
	addq	$328, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3722:
	.size	_Z64__device_stub__Z19iterateScheme_part4PdS_S_S_S_S_S_S_S_S_S_S_dddPdS_S_S_S_S_S_S_S_S_S_S_ddd, .-_Z64__device_stub__Z19iterateScheme_part4PdS_S_S_S_S_S_S_S_S_S_S_dddPdS_S_S_S_S_S_S_S_S_S_S_ddd
	.globl	_Z19iterateScheme_part4PdS_S_S_S_S_S_S_S_S_S_S_ddd
	.type	_Z19iterateScheme_part4PdS_S_S_S_S_S_S_S_S_S_S_ddd, @function
_Z19iterateScheme_part4PdS_S_S_S_S_S_S_S_S_S_S_ddd:
.LFB3723:
	.cfi_startproc
	endbr64
	jmp	_Z64__device_stub__Z19iterateScheme_part4PdS_S_S_S_S_S_S_S_S_S_S_dddPdS_S_S_S_S_S_S_S_S_S_S_ddd
	.cfi_endproc
.LFE3723:
	.size	_Z19iterateScheme_part4PdS_S_S_S_S_S_S_S_S_S_S_ddd, .-_Z19iterateScheme_part4PdS_S_S_S_S_S_S_S_S_S_S_ddd
	.globl	_Z64__device_stub__Z19iterateScheme_part5PdS_S_S_S_S_S_S_S_S_S_S_dddPdS_S_S_S_S_S_S_S_S_S_S_ddd
	.type	_Z64__device_stub__Z19iterateScheme_part5PdS_S_S_S_S_S_S_S_S_S_S_dddPdS_S_S_S_S_S_S_S_S_S_S_ddd, @function
_Z64__device_stub__Z19iterateScheme_part5PdS_S_S_S_S_S_S_S_S_S_S_dddPdS_S_S_S_S_S_S_S_S_S_S_ddd:
.LFB3724:
	.cfi_startproc
	endbr64
	subq	$328, %rsp
	.cfi_def_cfa_offset 336
	movq	336(%rsp), %rax
	movq	%rdi, 120(%rsp)
	leaq	144(%rsp), %rdi
	movq	%rsi, 112(%rsp)
	leaq	156(%rsp), %rsi
	movq	%rax, 72(%rsp)
	movq	344(%rsp), %rax
	movq	%rdx, 104(%rsp)
	leaq	128(%rsp), %rdx
	movq	%rax, 64(%rsp)
	movq	352(%rsp), %rax
	movq	%rcx, 96(%rsp)
	leaq	136(%rsp), %rcx
	movq	%rax, 56(%rsp)
	movq	360(%rsp), %rax
	movq	%r8, 88(%rsp)
	movq	%rax, 48(%rsp)
	movq	368(%rsp), %rax
	movq	%r9, 80(%rsp)
	movq	%rax, 40(%rsp)
	movq	376(%rsp), %rax
	movsd	%xmm0, 24(%rsp)
	movq	%rax, 32(%rsp)
	movsd	%xmm1, 16(%rsp)
	movsd	%xmm2, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 312(%rsp)
	xorl	%eax, %eax
	leaq	120(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	112(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	104(%rsp), %rax
	movq	%rax, 208(%rsp)
	leaq	96(%rsp), %rax
	movq	%rax, 216(%rsp)
	leaq	88(%rsp), %rax
	movq	%rax, 224(%rsp)
	leaq	80(%rsp), %rax
	movq	%rax, 232(%rsp)
	leaq	72(%rsp), %rax
	movq	%rax, 240(%rsp)
	leaq	64(%rsp), %rax
	movq	%rax, 248(%rsp)
	leaq	56(%rsp), %rax
	movq	%rax, 256(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 264(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 272(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 280(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 288(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 296(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 304(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 144(%rsp)
	movl	$1, 152(%rsp)
	movq	%rax, 156(%rsp)
	movl	$1, 164(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L108
	pushq	136(%rsp)
	.cfi_def_cfa_offset 344
	leaq	_Z19iterateScheme_part5PdS_S_S_S_S_S_S_S_S_S_S_ddd(%rip), %rdi
	pushq	136(%rsp)
	.cfi_def_cfa_offset 352
	movq	172(%rsp), %rcx
	movl	180(%rsp), %r8d
	movq	160(%rsp), %rsi
	movl	168(%rsp), %edx
	leaq	208(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 344
	popq	%rdx
	.cfi_def_cfa_offset 336
.L108:
	movq	312(%rsp), %rax
	subq	%fs:40, %rax
	je	.L110
	call	__stack_chk_fail@PLT
.L110:
	addq	$328, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3724:
	.size	_Z64__device_stub__Z19iterateScheme_part5PdS_S_S_S_S_S_S_S_S_S_S_dddPdS_S_S_S_S_S_S_S_S_S_S_ddd, .-_Z64__device_stub__Z19iterateScheme_part5PdS_S_S_S_S_S_S_S_S_S_S_dddPdS_S_S_S_S_S_S_S_S_S_S_ddd
	.globl	_Z19iterateScheme_part5PdS_S_S_S_S_S_S_S_S_S_S_ddd
	.type	_Z19iterateScheme_part5PdS_S_S_S_S_S_S_S_S_S_S_ddd, @function
_Z19iterateScheme_part5PdS_S_S_S_S_S_S_S_S_S_S_ddd:
.LFB3725:
	.cfi_startproc
	endbr64
	jmp	_Z64__device_stub__Z19iterateScheme_part5PdS_S_S_S_S_S_S_S_S_S_S_dddPdS_S_S_S_S_S_S_S_S_S_S_ddd
	.cfi_endproc
.LFE3725:
	.size	_Z19iterateScheme_part5PdS_S_S_S_S_S_S_S_S_S_S_ddd, .-_Z19iterateScheme_part5PdS_S_S_S_S_S_S_S_S_S_S_ddd
	.globl	_Z64__device_stub__Z19iterateScheme_part6PdS_S_S_S_S_S_S_S_S_S_S_dddPdS_S_S_S_S_S_S_S_S_S_S_ddd
	.type	_Z64__device_stub__Z19iterateScheme_part6PdS_S_S_S_S_S_S_S_S_S_S_dddPdS_S_S_S_S_S_S_S_S_S_S_ddd, @function
_Z64__device_stub__Z19iterateScheme_part6PdS_S_S_S_S_S_S_S_S_S_S_dddPdS_S_S_S_S_S_S_S_S_S_S_ddd:
.LFB3726:
	.cfi_startproc
	endbr64
	subq	$328, %rsp
	.cfi_def_cfa_offset 336
	movq	336(%rsp), %rax
	movq	%rdi, 120(%rsp)
	leaq	144(%rsp), %rdi
	movq	%rsi, 112(%rsp)
	leaq	156(%rsp), %rsi
	movq	%rax, 72(%rsp)
	movq	344(%rsp), %rax
	movq	%rdx, 104(%rsp)
	leaq	128(%rsp), %rdx
	movq	%rax, 64(%rsp)
	movq	352(%rsp), %rax
	movq	%rcx, 96(%rsp)
	leaq	136(%rsp), %rcx
	movq	%rax, 56(%rsp)
	movq	360(%rsp), %rax
	movq	%r8, 88(%rsp)
	movq	%rax, 48(%rsp)
	movq	368(%rsp), %rax
	movq	%r9, 80(%rsp)
	movq	%rax, 40(%rsp)
	movq	376(%rsp), %rax
	movsd	%xmm0, 24(%rsp)
	movq	%rax, 32(%rsp)
	movsd	%xmm1, 16(%rsp)
	movsd	%xmm2, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 312(%rsp)
	xorl	%eax, %eax
	leaq	120(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	112(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	104(%rsp), %rax
	movq	%rax, 208(%rsp)
	leaq	96(%rsp), %rax
	movq	%rax, 216(%rsp)
	leaq	88(%rsp), %rax
	movq	%rax, 224(%rsp)
	leaq	80(%rsp), %rax
	movq	%rax, 232(%rsp)
	leaq	72(%rsp), %rax
	movq	%rax, 240(%rsp)
	leaq	64(%rsp), %rax
	movq	%rax, 248(%rsp)
	leaq	56(%rsp), %rax
	movq	%rax, 256(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 264(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 272(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 280(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 288(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 296(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 304(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 144(%rsp)
	movl	$1, 152(%rsp)
	movq	%rax, 156(%rsp)
	movl	$1, 164(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L113
	pushq	136(%rsp)
	.cfi_def_cfa_offset 344
	leaq	_Z19iterateScheme_part6PdS_S_S_S_S_S_S_S_S_S_S_ddd(%rip), %rdi
	pushq	136(%rsp)
	.cfi_def_cfa_offset 352
	movq	172(%rsp), %rcx
	movl	180(%rsp), %r8d
	movq	160(%rsp), %rsi
	movl	168(%rsp), %edx
	leaq	208(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 344
	popq	%rdx
	.cfi_def_cfa_offset 336
.L113:
	movq	312(%rsp), %rax
	subq	%fs:40, %rax
	je	.L115
	call	__stack_chk_fail@PLT
.L115:
	addq	$328, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3726:
	.size	_Z64__device_stub__Z19iterateScheme_part6PdS_S_S_S_S_S_S_S_S_S_S_dddPdS_S_S_S_S_S_S_S_S_S_S_ddd, .-_Z64__device_stub__Z19iterateScheme_part6PdS_S_S_S_S_S_S_S_S_S_S_dddPdS_S_S_S_S_S_S_S_S_S_S_ddd
	.globl	_Z19iterateScheme_part6PdS_S_S_S_S_S_S_S_S_S_S_ddd
	.type	_Z19iterateScheme_part6PdS_S_S_S_S_S_S_S_S_S_S_ddd, @function
_Z19iterateScheme_part6PdS_S_S_S_S_S_S_S_S_S_S_ddd:
.LFB3727:
	.cfi_startproc
	endbr64
	jmp	_Z64__device_stub__Z19iterateScheme_part6PdS_S_S_S_S_S_S_S_S_S_S_dddPdS_S_S_S_S_S_S_S_S_S_S_ddd
	.cfi_endproc
.LFE3727:
	.size	_Z19iterateScheme_part6PdS_S_S_S_S_S_S_S_S_S_S_ddd, .-_Z19iterateScheme_part6PdS_S_S_S_S_S_S_S_S_S_S_ddd
	.globl	_Z64__device_stub__Z19iterateScheme_part7PdS_S_S_S_S_S_S_S_S_S_S_dddPdS_S_S_S_S_S_S_S_S_S_S_ddd
	.type	_Z64__device_stub__Z19iterateScheme_part7PdS_S_S_S_S_S_S_S_S_S_S_dddPdS_S_S_S_S_S_S_S_S_S_S_ddd, @function
_Z64__device_stub__Z19iterateScheme_part7PdS_S_S_S_S_S_S_S_S_S_S_dddPdS_S_S_S_S_S_S_S_S_S_S_ddd:
.LFB3728:
	.cfi_startproc
	endbr64
	subq	$328, %rsp
	.cfi_def_cfa_offset 336
	movq	336(%rsp), %rax
	movq	%rdi, 120(%rsp)
	leaq	144(%rsp), %rdi
	movq	%rsi, 112(%rsp)
	leaq	156(%rsp), %rsi
	movq	%rax, 72(%rsp)
	movq	344(%rsp), %rax
	movq	%rdx, 104(%rsp)
	leaq	128(%rsp), %rdx
	movq	%rax, 64(%rsp)
	movq	352(%rsp), %rax
	movq	%rcx, 96(%rsp)
	leaq	136(%rsp), %rcx
	movq	%rax, 56(%rsp)
	movq	360(%rsp), %rax
	movq	%r8, 88(%rsp)
	movq	%rax, 48(%rsp)
	movq	368(%rsp), %rax
	movq	%r9, 80(%rsp)
	movq	%rax, 40(%rsp)
	movq	376(%rsp), %rax
	movsd	%xmm0, 24(%rsp)
	movq	%rax, 32(%rsp)
	movsd	%xmm1, 16(%rsp)
	movsd	%xmm2, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 312(%rsp)
	xorl	%eax, %eax
	leaq	120(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	112(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	104(%rsp), %rax
	movq	%rax, 208(%rsp)
	leaq	96(%rsp), %rax
	movq	%rax, 216(%rsp)
	leaq	88(%rsp), %rax
	movq	%rax, 224(%rsp)
	leaq	80(%rsp), %rax
	movq	%rax, 232(%rsp)
	leaq	72(%rsp), %rax
	movq	%rax, 240(%rsp)
	leaq	64(%rsp), %rax
	movq	%rax, 248(%rsp)
	leaq	56(%rsp), %rax
	movq	%rax, 256(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 264(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 272(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 280(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 288(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 296(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 304(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 144(%rsp)
	movl	$1, 152(%rsp)
	movq	%rax, 156(%rsp)
	movl	$1, 164(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L118
	pushq	136(%rsp)
	.cfi_def_cfa_offset 344
	leaq	_Z19iterateScheme_part7PdS_S_S_S_S_S_S_S_S_S_S_ddd(%rip), %rdi
	pushq	136(%rsp)
	.cfi_def_cfa_offset 352
	movq	172(%rsp), %rcx
	movl	180(%rsp), %r8d
	movq	160(%rsp), %rsi
	movl	168(%rsp), %edx
	leaq	208(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 344
	popq	%rdx
	.cfi_def_cfa_offset 336
.L118:
	movq	312(%rsp), %rax
	subq	%fs:40, %rax
	je	.L120
	call	__stack_chk_fail@PLT
.L120:
	addq	$328, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3728:
	.size	_Z64__device_stub__Z19iterateScheme_part7PdS_S_S_S_S_S_S_S_S_S_S_dddPdS_S_S_S_S_S_S_S_S_S_S_ddd, .-_Z64__device_stub__Z19iterateScheme_part7PdS_S_S_S_S_S_S_S_S_S_S_dddPdS_S_S_S_S_S_S_S_S_S_S_ddd
	.globl	_Z19iterateScheme_part7PdS_S_S_S_S_S_S_S_S_S_S_ddd
	.type	_Z19iterateScheme_part7PdS_S_S_S_S_S_S_S_S_S_S_ddd, @function
_Z19iterateScheme_part7PdS_S_S_S_S_S_S_S_S_S_S_ddd:
.LFB3729:
	.cfi_startproc
	endbr64
	jmp	_Z64__device_stub__Z19iterateScheme_part7PdS_S_S_S_S_S_S_S_S_S_S_dddPdS_S_S_S_S_S_S_S_S_S_S_ddd
	.cfi_endproc
.LFE3729:
	.size	_Z19iterateScheme_part7PdS_S_S_S_S_S_S_S_S_S_S_ddd, .-_Z19iterateScheme_part7PdS_S_S_S_S_S_S_S_S_S_S_ddd
	.globl	_Z64__device_stub__Z19iterateScheme_part8PdS_S_S_S_S_S_S_S_S_S_S_dddPdS_S_S_S_S_S_S_S_S_S_S_ddd
	.type	_Z64__device_stub__Z19iterateScheme_part8PdS_S_S_S_S_S_S_S_S_S_S_dddPdS_S_S_S_S_S_S_S_S_S_S_ddd, @function
_Z64__device_stub__Z19iterateScheme_part8PdS_S_S_S_S_S_S_S_S_S_S_dddPdS_S_S_S_S_S_S_S_S_S_S_ddd:
.LFB3730:
	.cfi_startproc
	endbr64
	subq	$328, %rsp
	.cfi_def_cfa_offset 336
	movq	336(%rsp), %rax
	movq	%rdi, 120(%rsp)
	leaq	144(%rsp), %rdi
	movq	%rsi, 112(%rsp)
	leaq	156(%rsp), %rsi
	movq	%rax, 72(%rsp)
	movq	344(%rsp), %rax
	movq	%rdx, 104(%rsp)
	leaq	128(%rsp), %rdx
	movq	%rax, 64(%rsp)
	movq	352(%rsp), %rax
	movq	%rcx, 96(%rsp)
	leaq	136(%rsp), %rcx
	movq	%rax, 56(%rsp)
	movq	360(%rsp), %rax
	movq	%r8, 88(%rsp)
	movq	%rax, 48(%rsp)
	movq	368(%rsp), %rax
	movq	%r9, 80(%rsp)
	movq	%rax, 40(%rsp)
	movq	376(%rsp), %rax
	movsd	%xmm0, 24(%rsp)
	movq	%rax, 32(%rsp)
	movsd	%xmm1, 16(%rsp)
	movsd	%xmm2, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 312(%rsp)
	xorl	%eax, %eax
	leaq	120(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	112(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	104(%rsp), %rax
	movq	%rax, 208(%rsp)
	leaq	96(%rsp), %rax
	movq	%rax, 216(%rsp)
	leaq	88(%rsp), %rax
	movq	%rax, 224(%rsp)
	leaq	80(%rsp), %rax
	movq	%rax, 232(%rsp)
	leaq	72(%rsp), %rax
	movq	%rax, 240(%rsp)
	leaq	64(%rsp), %rax
	movq	%rax, 248(%rsp)
	leaq	56(%rsp), %rax
	movq	%rax, 256(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 264(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 272(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 280(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 288(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 296(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 304(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 144(%rsp)
	movl	$1, 152(%rsp)
	movq	%rax, 156(%rsp)
	movl	$1, 164(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L123
	pushq	136(%rsp)
	.cfi_def_cfa_offset 344
	leaq	_Z19iterateScheme_part8PdS_S_S_S_S_S_S_S_S_S_S_ddd(%rip), %rdi
	pushq	136(%rsp)
	.cfi_def_cfa_offset 352
	movq	172(%rsp), %rcx
	movl	180(%rsp), %r8d
	movq	160(%rsp), %rsi
	movl	168(%rsp), %edx
	leaq	208(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 344
	popq	%rdx
	.cfi_def_cfa_offset 336
.L123:
	movq	312(%rsp), %rax
	subq	%fs:40, %rax
	je	.L125
	call	__stack_chk_fail@PLT
.L125:
	addq	$328, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3730:
	.size	_Z64__device_stub__Z19iterateScheme_part8PdS_S_S_S_S_S_S_S_S_S_S_dddPdS_S_S_S_S_S_S_S_S_S_S_ddd, .-_Z64__device_stub__Z19iterateScheme_part8PdS_S_S_S_S_S_S_S_S_S_S_dddPdS_S_S_S_S_S_S_S_S_S_S_ddd
	.globl	_Z19iterateScheme_part8PdS_S_S_S_S_S_S_S_S_S_S_ddd
	.type	_Z19iterateScheme_part8PdS_S_S_S_S_S_S_S_S_S_S_ddd, @function
_Z19iterateScheme_part8PdS_S_S_S_S_S_S_S_S_S_S_ddd:
.LFB3731:
	.cfi_startproc
	endbr64
	jmp	_Z64__device_stub__Z19iterateScheme_part8PdS_S_S_S_S_S_S_S_S_S_S_dddPdS_S_S_S_S_S_S_S_S_S_S_ddd
	.cfi_endproc
.LFE3731:
	.size	_Z19iterateScheme_part8PdS_S_S_S_S_S_S_S_S_S_S_ddd, .-_Z19iterateScheme_part8PdS_S_S_S_S_S_S_S_S_S_S_ddd
	.section	.rodata.str1.1
.LC14:
	.string	"/home/ubuntu/Datasets/stackv2/train-structured/mattkennedy416/NavierStokes/master/report/code/NavierStokesSolver.cu"
.LC15:
	.string	"Calculating iteration %i / %i\n"
.LC16:
	.string	"u.csv"
.LC17:
	.string	"v.csv"
.LC18:
	.string	"p.csv"
.LC19:
	.string	"T.csv"
.LC20:
	.string	"F.csv"
.LC21:
	.string	"G.csv"
.LC22:
	.string	"Q.csv"
.LC23:
	.string	"Finishing!\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB3691:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$200, %rsp
	.cfi_def_cfa_offset 256
	movslq	jmax(%rip), %rdi
	movq	%fs:40, %rax
	movq	%rax, 184(%rsp)
	xorl	%eax, %eax
	movq	%rdi, %rbp
	salq	$3, %rdi
	call	malloc@PLT
	movslq	kmax(%rip), %rdi
	movq	%rax, %r14
	movq	%rdi, %rbx
	salq	$3, %rdi
	call	malloc@PLT
	imull	%ebx, %ebp
	movq	%rax, 56(%rsp)
	movslq	%ebp, %rbx
	sall	$2, %ebp
	salq	$3, %rbx
	movslq	%ebp, %rbp
	movq	%rbx, %rdi
	salq	$3, %rbp
	call	malloc@PLT
	movq	%rbx, %rdi
	movq	%rax, 8(%rsp)
	call	malloc@PLT
	movq	%rbx, %rdi
	movq	%rax, 16(%rsp)
	call	malloc@PLT
	movq	%rbx, %rdi
	movq	%rax, 24(%rsp)
	call	malloc@PLT
	movq	%rbx, %rdi
	movq	%rax, 32(%rsp)
	call	malloc@PLT
	movq	%rbx, %rdi
	movq	%rax, 40(%rsp)
	call	malloc@PLT
	movq	40(%rsp), %r8
	movq	32(%rsp), %rcx
	movq	24(%rsp), %rdx
	movq	16(%rsp), %rsi
	movq	%rax, %r9
	movq	%rax, 48(%rsp)
	movq	8(%rsp), %rdi
	call	_Z20initializePrimativesPdS_S_S_S_S_
	movq	32(%rsp), %rcx
	movq	24(%rsp), %rdx
	movq	16(%rsp), %rsi
	movq	8(%rsp), %rdi
	call	_Z18applyBC_UpperPlatePdS_S_S_
	movq	%rbp, %rdi
	call	malloc@PLT
	movq	%rbp, %rdi
	movq	%rax, %r13
	call	malloc@PLT
	movq	%rbp, %rdi
	movq	%rax, %r12
	call	malloc@PLT
	movq	%rbx, %rsi
	leaq	64(%rsp), %rdi
	leaq	.LC14(%rip), %rbx
	movq	%rax, %rbp
	call	cudaMalloc@PLT
	movl	jmax(%rip), %esi
	leaq	72(%rsp), %rdi
	imull	kmax(%rip), %esi
	movslq	%esi, %rsi
	salq	$3, %rsi
	call	cudaMalloc@PLT
	movl	jmax(%rip), %esi
	leaq	80(%rsp), %rdi
	imull	kmax(%rip), %esi
	movslq	%esi, %rsi
	salq	$3, %rsi
	call	cudaMalloc@PLT
	movl	jmax(%rip), %esi
	leaq	88(%rsp), %rdi
	imull	kmax(%rip), %esi
	movslq	%esi, %rsi
	salq	$3, %rsi
	call	cudaMalloc@PLT
	movl	jmax(%rip), %esi
	leaq	96(%rsp), %rdi
	imull	kmax(%rip), %esi
	movslq	%esi, %rsi
	salq	$3, %rsi
	call	cudaMalloc@PLT
	movl	jmax(%rip), %esi
	leaq	104(%rsp), %rdi
	imull	kmax(%rip), %esi
	movslq	%esi, %rsi
	salq	$3, %rsi
	call	cudaMalloc@PLT
	movl	jmax(%rip), %esi
	leaq	112(%rsp), %rdi
	imull	kmax(%rip), %esi
	movslq	%esi, %rsi
	salq	$3, %rsi
	call	cudaMalloc@PLT
	movl	jmax(%rip), %esi
	leaq	120(%rsp), %rdi
	imull	kmax(%rip), %esi
	movslq	%esi, %rsi
	salq	$3, %rsi
	call	cudaMalloc@PLT
	movl	jmax(%rip), %esi
	imull	kmax(%rip), %esi
	leaq	128(%rsp), %rdi
	sall	$2, %esi
	movslq	%esi, %rsi
	salq	$3, %rsi
	call	cudaMalloc@PLT
	movl	jmax(%rip), %esi
	imull	kmax(%rip), %esi
	leaq	136(%rsp), %rdi
	sall	$2, %esi
	movslq	%esi, %rsi
	salq	$3, %rsi
	call	cudaMalloc@PLT
	movl	jmax(%rip), %esi
	imull	kmax(%rip), %esi
	leaq	144(%rsp), %rdi
	sall	$2, %esi
	movslq	%esi, %rsi
	salq	$3, %rsi
	call	cudaMalloc@PLT
	movl	jmax(%rip), %esi
	imull	kmax(%rip), %esi
	leaq	152(%rsp), %rdi
	sall	$2, %esi
	movslq	%esi, %rsi
	salq	$3, %rsi
	call	cudaMalloc@PLT
	movl	jmax(%rip), %edx
	movq	64(%rsp), %rdi
	movq	%r14, %rsi
	imull	kmax(%rip), %edx
	movl	$1, %ecx
	movslq	%edx, %rdx
	salq	$3, %rdx
	call	cudaMemcpy@PLT
	movl	jmax(%rip), %edx
	movq	56(%rsp), %rsi
	movl	$1, %ecx
	imull	kmax(%rip), %edx
	movq	72(%rsp), %rdi
	movslq	%edx, %rdx
	salq	$3, %rdx
	call	cudaMemcpy@PLT
	movl	jmax(%rip), %edx
	movq	8(%rsp), %rsi
	xorl	%r15d, %r15d
	imull	kmax(%rip), %edx
	movq	80(%rsp), %rdi
	movl	$1, %ecx
	movslq	%edx, %rdx
	salq	$3, %rdx
	call	cudaMemcpy@PLT
	movl	jmax(%rip), %edx
	movq	16(%rsp), %rsi
	movl	$1, %ecx
	imull	kmax(%rip), %edx
	movq	88(%rsp), %rdi
	movslq	%edx, %rdx
	salq	$3, %rdx
	call	cudaMemcpy@PLT
	movl	jmax(%rip), %edx
	movq	24(%rsp), %rsi
	movl	$1, %ecx
	imull	kmax(%rip), %edx
	movq	96(%rsp), %rdi
	movslq	%edx, %rdx
	salq	$3, %rdx
	call	cudaMemcpy@PLT
	movl	jmax(%rip), %edx
	movq	32(%rsp), %rsi
	movl	$1, %ecx
	imull	kmax(%rip), %edx
	movq	104(%rsp), %rdi
	movslq	%edx, %rdx
	salq	$3, %rdx
	call	cudaMemcpy@PLT
	movl	jmax(%rip), %edx
	movq	40(%rsp), %rsi
	movl	$1, %ecx
	imull	kmax(%rip), %edx
	movq	112(%rsp), %rdi
	movslq	%edx, %rdx
	salq	$3, %rdx
	call	cudaMemcpy@PLT
	movl	jmax(%rip), %edx
	movq	48(%rsp), %rsi
	movl	$1, %ecx
	imull	kmax(%rip), %edx
	movq	120(%rsp), %rdi
	movslq	%edx, %rdx
	salq	$3, %rdx
	call	cudaMemcpy@PLT
	movl	$804, %edx
	movl	$1, %ecx
	movq	%rbx, %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKcib
	movl	kmax(%rip), %eax
	movl	jmax(%rip), %edx
	movl	$1, 168(%rsp)
	movl	$1, 180(%rsp)
	shrl	$4, %eax
	shrl	$4, %edx
	incl	%eax
	incl	%edx
	movl	%edx, 172(%rsp)
	movl	%eax, 176(%rsp)
.L137:
	incl	%r15d
	movl	$1000, %ecx
	movl	$2, %edi
	xorl	%eax, %eax
	movl	%r15d, %edx
	leaq	.LC15(%rip), %rsi
	call	__printf_chk@PLT
	movq	32(%rsp), %rcx
	movq	24(%rsp), %rdx
	movq	16(%rsp), %rsi
	movq	8(%rsp), %rdi
	movsd	dy(%rip), %xmm1
	movsd	dx(%rip), %xmm0
	call	_Z7calc_dtPdS_S_S_dd
	movl	168(%rsp), %ecx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	172(%rsp), %rdi
	movl	180(%rsp), %esi
	movsd	%xmm0, (%rsp)
	movabsq	$68719476752, %rdx
	movq	%rdx, 160(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L129
	pushq	152(%rsp)
	.cfi_def_cfa_offset 264
	movsd	dy(%rip), %xmm1
	movsd	dx(%rip), %xmm0
	pushq	152(%rsp)
	.cfi_def_cfa_offset 272
	pushq	152(%rsp)
	.cfi_def_cfa_offset 280
	pushq	152(%rsp)
	.cfi_def_cfa_offset 288
	pushq	152(%rsp)
	.cfi_def_cfa_offset 296
	pushq	152(%rsp)
	.cfi_def_cfa_offset 304
	movsd	48(%rsp), %xmm2
	movq	152(%rsp), %r9
	movq	144(%rsp), %r8
	movq	136(%rsp), %rcx
	movq	128(%rsp), %rdx
	movq	120(%rsp), %rsi
	movq	112(%rsp), %rdi
	call	_Z64__device_stub__Z19iterateScheme_part1PdS_S_S_S_S_S_S_S_S_S_S_dddPdS_S_S_S_S_S_S_S_S_S_S_ddd
	addq	$48, %rsp
	.cfi_def_cfa_offset 256
.L129:
	call	cudaPeekAtLastError@PLT
	movl	$1, %ecx
	movl	$824, %edx
	movq	%rbx, %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKcib
	call	cudaDeviceSynchronize@PLT
	movl	$1, %ecx
	movl	$825, %edx
	movq	%rbx, %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKcib
	movl	168(%rsp), %ecx
	xorl	%r9d, %r9d
	movq	160(%rsp), %rdx
	movq	172(%rsp), %rdi
	movl	180(%rsp), %esi
	xorl	%r8d, %r8d
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L130
	pushq	152(%rsp)
	.cfi_def_cfa_offset 264
	movsd	dy(%rip), %xmm1
	movsd	dx(%rip), %xmm0
	pushq	152(%rsp)
	.cfi_def_cfa_offset 272
	pushq	152(%rsp)
	.cfi_def_cfa_offset 280
	pushq	152(%rsp)
	.cfi_def_cfa_offset 288
	pushq	152(%rsp)
	.cfi_def_cfa_offset 296
	pushq	152(%rsp)
	.cfi_def_cfa_offset 304
	movsd	48(%rsp), %xmm2
	movq	152(%rsp), %r9
	movq	144(%rsp), %r8
	movq	136(%rsp), %rcx
	movq	128(%rsp), %rdx
	movq	120(%rsp), %rsi
	movq	112(%rsp), %rdi
	call	_Z64__device_stub__Z19iterateScheme_part2PdS_S_S_S_S_S_S_S_S_S_S_dddPdS_S_S_S_S_S_S_S_S_S_S_ddd
	addq	$48, %rsp
	.cfi_def_cfa_offset 256
.L130:
	call	cudaPeekAtLastError@PLT
	movl	$1, %ecx
	movl	$830, %edx
	movq	%rbx, %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKcib
	call	cudaDeviceSynchronize@PLT
	movl	$1, %ecx
	movl	$831, %edx
	movq	%rbx, %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKcib
	movl	168(%rsp), %ecx
	xorl	%r9d, %r9d
	movq	160(%rsp), %rdx
	movq	172(%rsp), %rdi
	movl	180(%rsp), %esi
	xorl	%r8d, %r8d
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L131
	pushq	152(%rsp)
	.cfi_def_cfa_offset 264
	movsd	dy(%rip), %xmm1
	movsd	dx(%rip), %xmm0
	pushq	152(%rsp)
	.cfi_def_cfa_offset 272
	pushq	152(%rsp)
	.cfi_def_cfa_offset 280
	pushq	152(%rsp)
	.cfi_def_cfa_offset 288
	pushq	152(%rsp)
	.cfi_def_cfa_offset 296
	pushq	152(%rsp)
	.cfi_def_cfa_offset 304
	movsd	48(%rsp), %xmm2
	movq	152(%rsp), %r9
	movq	144(%rsp), %r8
	movq	136(%rsp), %rcx
	movq	128(%rsp), %rdx
	movq	120(%rsp), %rsi
	movq	112(%rsp), %rdi
	call	_Z64__device_stub__Z19iterateScheme_part3PdS_S_S_S_S_S_S_S_S_S_S_dddPdS_S_S_S_S_S_S_S_S_S_S_ddd
	addq	$48, %rsp
	.cfi_def_cfa_offset 256
.L131:
	call	cudaPeekAtLastError@PLT
	movl	$1, %ecx
	movl	$835, %edx
	movq	%rbx, %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKcib
	call	cudaDeviceSynchronize@PLT
	movl	$1, %ecx
	movl	$836, %edx
	movq	%rbx, %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKcib
	movl	168(%rsp), %ecx
	xorl	%r9d, %r9d
	movq	160(%rsp), %rdx
	movq	172(%rsp), %rdi
	movl	180(%rsp), %esi
	xorl	%r8d, %r8d
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L132
	pushq	152(%rsp)
	.cfi_def_cfa_offset 264
	movsd	dy(%rip), %xmm1
	movsd	dx(%rip), %xmm0
	pushq	152(%rsp)
	.cfi_def_cfa_offset 272
	pushq	152(%rsp)
	.cfi_def_cfa_offset 280
	pushq	152(%rsp)
	.cfi_def_cfa_offset 288
	pushq	152(%rsp)
	.cfi_def_cfa_offset 296
	pushq	152(%rsp)
	.cfi_def_cfa_offset 304
	movsd	48(%rsp), %xmm2
	movq	152(%rsp), %r9
	movq	144(%rsp), %r8
	movq	136(%rsp), %rcx
	movq	128(%rsp), %rdx
	movq	120(%rsp), %rsi
	movq	112(%rsp), %rdi
	call	_Z64__device_stub__Z19iterateScheme_part4PdS_S_S_S_S_S_S_S_S_S_S_dddPdS_S_S_S_S_S_S_S_S_S_S_ddd
	addq	$48, %rsp
	.cfi_def_cfa_offset 256
.L132:
	call	cudaPeekAtLastError@PLT
	movl	$1, %ecx
	movl	$840, %edx
	movq	%rbx, %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKcib
	call	cudaDeviceSynchronize@PLT
	movl	$1, %ecx
	movl	$841, %edx
	movq	%rbx, %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKcib
	movl	168(%rsp), %ecx
	xorl	%r9d, %r9d
	movq	160(%rsp), %rdx
	movq	172(%rsp), %rdi
	movl	180(%rsp), %esi
	xorl	%r8d, %r8d
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L133
	pushq	152(%rsp)
	.cfi_def_cfa_offset 264
	movsd	dy(%rip), %xmm1
	movsd	dx(%rip), %xmm0
	pushq	152(%rsp)
	.cfi_def_cfa_offset 272
	pushq	152(%rsp)
	.cfi_def_cfa_offset 280
	pushq	152(%rsp)
	.cfi_def_cfa_offset 288
	pushq	152(%rsp)
	.cfi_def_cfa_offset 296
	pushq	152(%rsp)
	.cfi_def_cfa_offset 304
	movsd	48(%rsp), %xmm2
	movq	152(%rsp), %r9
	movq	144(%rsp), %r8
	movq	136(%rsp), %rcx
	movq	128(%rsp), %rdx
	movq	120(%rsp), %rsi
	movq	112(%rsp), %rdi
	call	_Z64__device_stub__Z19iterateScheme_part5PdS_S_S_S_S_S_S_S_S_S_S_dddPdS_S_S_S_S_S_S_S_S_S_S_ddd
	addq	$48, %rsp
	.cfi_def_cfa_offset 256
.L133:
	call	cudaPeekAtLastError@PLT
	movl	$1, %ecx
	movl	$845, %edx
	movq	%rbx, %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKcib
	call	cudaDeviceSynchronize@PLT
	movl	$1, %ecx
	movl	$846, %edx
	movq	%rbx, %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKcib
	movl	168(%rsp), %ecx
	xorl	%r9d, %r9d
	movq	160(%rsp), %rdx
	movq	172(%rsp), %rdi
	movl	180(%rsp), %esi
	xorl	%r8d, %r8d
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L134
	pushq	152(%rsp)
	.cfi_def_cfa_offset 264
	movsd	dy(%rip), %xmm1
	movsd	dx(%rip), %xmm0
	pushq	152(%rsp)
	.cfi_def_cfa_offset 272
	pushq	152(%rsp)
	.cfi_def_cfa_offset 280
	pushq	152(%rsp)
	.cfi_def_cfa_offset 288
	pushq	152(%rsp)
	.cfi_def_cfa_offset 296
	pushq	152(%rsp)
	.cfi_def_cfa_offset 304
	movsd	48(%rsp), %xmm2
	movq	152(%rsp), %r9
	movq	144(%rsp), %r8
	movq	136(%rsp), %rcx
	movq	128(%rsp), %rdx
	movq	120(%rsp), %rsi
	movq	112(%rsp), %rdi
	call	_Z64__device_stub__Z19iterateScheme_part6PdS_S_S_S_S_S_S_S_S_S_S_dddPdS_S_S_S_S_S_S_S_S_S_S_ddd
	addq	$48, %rsp
	.cfi_def_cfa_offset 256
.L134:
	call	cudaPeekAtLastError@PLT
	movl	$1, %ecx
	movl	$850, %edx
	movq	%rbx, %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKcib
	call	cudaDeviceSynchronize@PLT
	movl	$1, %ecx
	movl	$851, %edx
	movq	%rbx, %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKcib
	movl	168(%rsp), %ecx
	xorl	%r9d, %r9d
	movq	160(%rsp), %rdx
	movq	172(%rsp), %rdi
	movl	180(%rsp), %esi
	xorl	%r8d, %r8d
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L135
	pushq	152(%rsp)
	.cfi_def_cfa_offset 264
	movsd	dy(%rip), %xmm1
	movsd	dx(%rip), %xmm0
	pushq	152(%rsp)
	.cfi_def_cfa_offset 272
	pushq	152(%rsp)
	.cfi_def_cfa_offset 280
	pushq	152(%rsp)
	.cfi_def_cfa_offset 288
	pushq	152(%rsp)
	.cfi_def_cfa_offset 296
	pushq	152(%rsp)
	.cfi_def_cfa_offset 304
	movsd	48(%rsp), %xmm2
	movq	152(%rsp), %r9
	movq	144(%rsp), %r8
	movq	136(%rsp), %rcx
	movq	128(%rsp), %rdx
	movq	120(%rsp), %rsi
	movq	112(%rsp), %rdi
	call	_Z64__device_stub__Z19iterateScheme_part7PdS_S_S_S_S_S_S_S_S_S_S_dddPdS_S_S_S_S_S_S_S_S_S_S_ddd
	addq	$48, %rsp
	.cfi_def_cfa_offset 256
.L135:
	call	cudaPeekAtLastError@PLT
	movl	$1, %ecx
	movl	$855, %edx
	movq	%rbx, %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKcib
	call	cudaDeviceSynchronize@PLT
	movl	$1, %ecx
	movl	$856, %edx
	movq	%rbx, %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKcib
	movl	168(%rsp), %ecx
	xorl	%r9d, %r9d
	movq	160(%rsp), %rdx
	movq	172(%rsp), %rdi
	movl	180(%rsp), %esi
	xorl	%r8d, %r8d
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L136
	pushq	152(%rsp)
	.cfi_def_cfa_offset 264
	movsd	dy(%rip), %xmm1
	movsd	dx(%rip), %xmm0
	pushq	152(%rsp)
	.cfi_def_cfa_offset 272
	pushq	152(%rsp)
	.cfi_def_cfa_offset 280
	pushq	152(%rsp)
	.cfi_def_cfa_offset 288
	pushq	152(%rsp)
	.cfi_def_cfa_offset 296
	pushq	152(%rsp)
	.cfi_def_cfa_offset 304
	movsd	48(%rsp), %xmm2
	movq	152(%rsp), %r9
	movq	144(%rsp), %r8
	movq	136(%rsp), %rcx
	movq	128(%rsp), %rdx
	movq	120(%rsp), %rsi
	movq	112(%rsp), %rdi
	call	_Z64__device_stub__Z19iterateScheme_part8PdS_S_S_S_S_S_S_S_S_S_S_dddPdS_S_S_S_S_S_S_S_S_S_S_ddd
	addq	$48, %rsp
	.cfi_def_cfa_offset 256
.L136:
	call	cudaPeekAtLastError@PLT
	movl	$1, %ecx
	movl	$860, %edx
	movq	%rbx, %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKcib
	call	cudaDeviceSynchronize@PLT
	movl	$1, %ecx
	movl	$861, %edx
	movq	%rbx, %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKcib
	movl	jmax(%rip), %edx
	movq	80(%rsp), %rsi
	movl	$2, %ecx
	imull	kmax(%rip), %edx
	movq	8(%rsp), %rdi
	movslq	%edx, %rdx
	salq	$3, %rdx
	call	cudaMemcpy@PLT
	movl	jmax(%rip), %edx
	movq	88(%rsp), %rsi
	movl	$2, %ecx
	imull	kmax(%rip), %edx
	movq	16(%rsp), %rdi
	movslq	%edx, %rdx
	salq	$3, %rdx
	call	cudaMemcpy@PLT
	movl	jmax(%rip), %edx
	movq	96(%rsp), %rsi
	movl	$2, %ecx
	imull	kmax(%rip), %edx
	movq	24(%rsp), %rdi
	movslq	%edx, %rdx
	salq	$3, %rdx
	call	cudaMemcpy@PLT
	movl	jmax(%rip), %edx
	movq	104(%rsp), %rsi
	movl	$2, %ecx
	imull	kmax(%rip), %edx
	movq	32(%rsp), %rdi
	movslq	%edx, %rdx
	salq	$3, %rdx
	call	cudaMemcpy@PLT
	cmpl	$1000, %r15d
	jne	.L137
	movl	jmax(%rip), %edx
	imull	kmax(%rip), %edx
	movl	$2, %ecx
	movq	%r12, %rdi
	movq	144(%rsp), %rsi
	sall	$2, %edx
	movslq	%edx, %rdx
	salq	$3, %rdx
	call	cudaMemcpy@PLT
	movl	jmax(%rip), %edx
	movl	$2, %ecx
	movq	%rbp, %rdi
	imull	kmax(%rip), %edx
	movq	152(%rsp), %rsi
	sall	$2, %edx
	movslq	%edx, %rdx
	salq	$3, %rdx
	call	cudaMemcpy@PLT
	movl	jmax(%rip), %edx
	movl	$2, %ecx
	movq	%r13, %rdi
	imull	kmax(%rip), %edx
	movq	128(%rsp), %rsi
	sall	$2, %edx
	movslq	%edx, %rdx
	salq	$3, %rdx
	call	cudaMemcpy@PLT
	movq	8(%rsp), %rdi
	movl	$1, %edx
	leaq	.LC16(%rip), %rsi
	call	_Z10arrayToCSVPdPci
	movq	16(%rsp), %rdi
	movl	$1, %edx
	leaq	.LC17(%rip), %rsi
	call	_Z10arrayToCSVPdPci
	movq	24(%rsp), %rdi
	movl	$1, %edx
	leaq	.LC18(%rip), %rsi
	call	_Z10arrayToCSVPdPci
	movq	32(%rsp), %rdi
	movl	$1, %edx
	leaq	.LC19(%rip), %rsi
	call	_Z10arrayToCSVPdPci
	movl	$4, %edx
	leaq	.LC20(%rip), %rsi
	movq	%r12, %rdi
	call	_Z10arrayToCSVPdPci
	movl	$4, %edx
	leaq	.LC21(%rip), %rsi
	movq	%rbp, %rdi
	call	_Z10arrayToCSVPdPci
	leaq	.LC22(%rip), %rsi
	movl	$4, %edx
	movq	%r13, %rdi
	call	_Z10arrayToCSVPdPci
	movq	%r14, %rdi
	call	free@PLT
	movq	56(%rsp), %rdi
	call	free@PLT
	movq	8(%rsp), %rdi
	call	free@PLT
	movq	16(%rsp), %rdi
	call	free@PLT
	movq	24(%rsp), %rdi
	call	free@PLT
	movq	32(%rsp), %rdi
	call	free@PLT
	movq	40(%rsp), %rdi
	call	free@PLT
	movq	48(%rsp), %rdi
	call	free@PLT
	movq	%r13, %rdi
	call	free@PLT
	movq	%r12, %rdi
	call	free@PLT
	movq	%rbp, %rdi
	call	free@PLT
	movq	64(%rsp), %rdi
	call	cudaFree@PLT
	movq	72(%rsp), %rdi
	call	cudaFree@PLT
	movq	80(%rsp), %rdi
	call	cudaFree@PLT
	movq	88(%rsp), %rdi
	call	cudaFree@PLT
	movq	96(%rsp), %rdi
	call	cudaFree@PLT
	movq	104(%rsp), %rdi
	call	cudaFree@PLT
	movq	112(%rsp), %rdi
	call	cudaFree@PLT
	movq	120(%rsp), %rdi
	call	cudaFree@PLT
	movq	128(%rsp), %rdi
	call	cudaFree@PLT
	movq	136(%rsp), %rdi
	call	cudaFree@PLT
	movq	144(%rsp), %rdi
	call	cudaFree@PLT
	movq	152(%rsp), %rdi
	call	cudaFree@PLT
	xorl	%eax, %eax
	movl	$2, %edi
	leaq	.LC23(%rip), %rsi
	call	__printf_chk@PLT
	movq	184(%rsp), %rax
	subq	%fs:40, %rax
	je	.L138
	call	__stack_chk_fail@PLT
.L138:
	addq	$200, %rsp
	.cfi_def_cfa_offset 56
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3691:
	.size	main, .-main
	.section	.rodata.str1.1
.LC24:
	.string	"_Z19iterateScheme_part8PdS_S_S_S_S_S_S_S_S_S_S_ddd"
.LC25:
	.string	"_Z19iterateScheme_part7PdS_S_S_S_S_S_S_S_S_S_S_ddd"
.LC26:
	.string	"_Z19iterateScheme_part6PdS_S_S_S_S_S_S_S_S_S_S_ddd"
.LC27:
	.string	"_Z19iterateScheme_part5PdS_S_S_S_S_S_S_S_S_S_S_ddd"
.LC28:
	.string	"_Z19iterateScheme_part4PdS_S_S_S_S_S_S_S_S_S_S_ddd"
.LC29:
	.string	"_Z19iterateScheme_part3PdS_S_S_S_S_S_S_S_S_S_S_ddd"
.LC30:
	.string	"_Z19iterateScheme_part2PdS_S_S_S_S_S_S_S_S_S_S_ddd"
.LC31:
	.string	"_Z19iterateScheme_part1PdS_S_S_S_S_S_S_S_S_S_S_ddd"
.LC32:
	.string	"jmax_d"
.LC33:
	.string	"kmax_d"
.LC34:
	.string	"plateLength_d"
.LC35:
	.string	"CFL_d"
.LC36:
	.string	"u0_d"
.LC37:
	.string	"gam_d"
.LC38:
	.string	"Pr_d"
.LC39:
	.string	"R_d"
.LC40:
	.string	"Cv_d"
.LC41:
	.string	"Cp_d"
.LC42:
	.string	"mu0_d"
.LC43:
	.string	"T0_d"
.LC44:
	.string	"p0_d"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3733:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC24(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z19iterateScheme_part8PdS_S_S_S_S_S_S_S_S_S_S_ddd(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC25(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z19iterateScheme_part7PdS_S_S_S_S_S_S_S_S_S_S_ddd(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC26(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z19iterateScheme_part6PdS_S_S_S_S_S_S_S_S_S_S_ddd(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC27(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z19iterateScheme_part5PdS_S_S_S_S_S_S_S_S_S_S_ddd(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC28(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z19iterateScheme_part4PdS_S_S_S_S_S_S_S_S_S_S_ddd(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC29(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z19iterateScheme_part3PdS_S_S_S_S_S_S_S_S_S_S_ddd(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC30(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z19iterateScheme_part2PdS_S_S_S_S_S_S_S_S_S_S_ddd(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC31(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z19iterateScheme_part1PdS_S_S_S_S_S_S_S_S_S_S_ddd(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	leaq	.LC32(%rip), %rdx
	pushq	$0
	.cfi_def_cfa_offset 24
	movq	%rdx, %rcx
	movl	$4, %r9d
	xorl	%r8d, %r8d
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	_ZL6jmax_d(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC33(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$4, %r9d
	leaq	_ZL6kmax_d(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC34(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL13plateLength_d(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	popq	%r8
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC35(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL5CFL_d(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r9
	.cfi_def_cfa_offset 24
	popq	%r10
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC36(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL4u0_d(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r11
	.cfi_def_cfa_offset 24
	popq	%rax
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC37(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL5gam_d(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC38(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL4Pr_d(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC39(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL3R_d(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	popq	%r8
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC40(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL4Cv_d(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r9
	.cfi_def_cfa_offset 24
	popq	%r10
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC41(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL4Cp_d(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r11
	.cfi_def_cfa_offset 24
	popq	%rax
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC42(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL5mu0_d(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC43(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL4T0_d(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC44(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movl	$8, %r9d
	movq	%rdx, %rcx
	leaq	_ZL4p0_d(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	popq	%r8
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3733:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.text.startup
	.type	_GLOBAL__sub_I_jmax, @function
_GLOBAL__sub_I_jmax:
.LFB4353:
	.cfi_startproc
	endbr64
	movl	jmax(%rip), %eax
	movsd	plateLength(%rip), %xmm3
	movsd	T0(%rip), %xmm2
	movsd	R(%rip), %xmm4
	decl	%eax
	movaps	%xmm3, %xmm0
	cvtsi2sdl	%eax, %xmm1
	mulsd	%xmm2, %xmm4
	mulsd	Cv(%rip), %xmm2
	divsd	%xmm1, %xmm0
	movsd	p0(%rip), %xmm1
	movsd	%xmm2, e0(%rip)
	divsd	%xmm4, %xmm1
	movsd	%xmm0, dx(%rip)
	movsd	M0(%rip), %xmm0
	mulsd	a0(%rip), %xmm0
	movsd	%xmm0, u0(%rip)
	mulsd	%xmm1, %xmm0
	movsd	%xmm1, rho0(%rip)
	mulsd	%xmm3, %xmm0
	divsd	mu0(%rip), %xmm0
	movsd	%xmm0, Re(%rip)
	ret
	.cfi_endproc
.LFE4353:
	.size	_GLOBAL__sub_I_jmax, .-_GLOBAL__sub_I_jmax
	.section	.init_array
	.align 8
	.quad	_GLOBAL__sub_I_jmax
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.globl	Re
	.bss
	.align 8
	.type	Re, @object
	.size	Re, 8
Re:
	.zero	8
	.globl	mu0
	.data
	.align 8
	.type	mu0, @object
	.size	mu0, 8
mu0:
	.long	1360276203
	.long	1056097122
	.globl	e0
	.bss
	.align 8
	.type	e0, @object
	.size	e0, 8
e0:
	.zero	8
	.globl	rho0
	.align 8
	.type	rho0, @object
	.size	rho0, 8
rho0:
	.zero	8
	.globl	Cp
	.data
	.align 8
	.type	Cp, @object
	.size	Cp, 8
Cp:
	.long	0
	.long	1083142144
	.globl	Cv
	.align 8
	.type	Cv, @object
	.size	Cv, 8
Cv:
	.long	-858993460
	.long	1082550476
	.globl	R
	.align 8
	.type	R, @object
	.size	R, 8
R:
	.long	0
	.long	1081208832
	.globl	Pr
	.align 8
	.type	Pr, @object
	.size	Pr, 8
Pr:
	.long	-343597384
	.long	1072085073
	.globl	gam
	.align 8
	.type	gam, @object
	.size	gam, 8
gam:
	.long	1717986918
	.long	1073112678
	.globl	v0
	.bss
	.align 8
	.type	v0, @object
	.size	v0, 8
v0:
	.zero	8
	.globl	T0
	.data
	.align 8
	.type	T0, @object
	.size	T0, 8
T0:
	.long	1546188227
	.long	1081213583
	.globl	p0
	.align 8
	.type	p0, @object
	.size	p0, 8
p0:
	.long	0
	.long	1090043088
	.globl	u0
	.bss
	.align 8
	.type	u0, @object
	.size	u0, 8
u0:
	.zero	8
	.globl	a0
	.data
	.align 8
	.type	a0, @object
	.size	a0, 8
a0:
	.long	-515396076
	.long	1081427066
	.local	_ZL4p0_d
	.comm	_ZL4p0_d,8,8
	.local	_ZL4T0_d
	.comm	_ZL4T0_d,8,8
	.local	_ZL5mu0_d
	.comm	_ZL5mu0_d,8,8
	.local	_ZL4Cp_d
	.comm	_ZL4Cp_d,8,8
	.local	_ZL4Cv_d
	.comm	_ZL4Cv_d,8,8
	.local	_ZL3R_d
	.comm	_ZL3R_d,8,8
	.local	_ZL4Pr_d
	.comm	_ZL4Pr_d,8,8
	.local	_ZL5gam_d
	.comm	_ZL5gam_d,8,8
	.local	_ZL4u0_d
	.comm	_ZL4u0_d,8,8
	.globl	dy
	.align 8
	.type	dy, @object
	.size	dy, 8
dy:
	.long	-1882863261
	.long	1048566864
	.globl	dx
	.bss
	.align 8
	.type	dx, @object
	.size	dx, 8
dx:
	.zero	8
	.globl	M0
	.data
	.align 8
	.type	M0, @object
	.size	M0, 8
M0:
	.long	0
	.long	1074790400
	.local	_ZL5CFL_d
	.comm	_ZL5CFL_d,8,8
	.globl	CFL
	.align 8
	.type	CFL, @object
	.size	CFL, 8
CFL:
	.long	-1717986918
	.long	1070176665
	.local	_ZL13plateLength_d
	.comm	_ZL13plateLength_d,8,8
	.globl	plateLength
	.align 8
	.type	plateLength, @object
	.size	plateLength, 8
plateLength:
	.long	-1998362383
	.long	1055193269
	.local	_ZL6kmax_d
	.comm	_ZL6kmax_d,4,4
	.local	_ZL6jmax_d
	.comm	_ZL6jmax_d,4,4
	.globl	kmax
	.align 4
	.type	kmax, @object
	.size	kmax, 4
kmax:
	.long	70
	.globl	jmax
	.align 4
	.type	jmax, @object
	.size	jmax, 4
jmax:
	.long	70
	.section	.rodata.cst8,"aM",@progbits,8
	.align 8
.LC1:
	.long	0
	.long	1075052544
	.align 8
.LC3:
	.long	0
	.long	-1048576
	.align 8
.LC4:
	.long	0
	.long	2146435072
	.align 8
.LC5:
	.long	0
	.long	1073217536
	.align 8
.LC6:
	.long	0
	.long	1079738368
	.align 8
.LC7:
	.long	0
	.long	1071644672
	.align 8
.LC8:
	.long	0
	.long	1072693248
	.section	.rodata.cst16,"aM",@progbits,16
	.align 16
.LC9:
	.long	-1
	.long	2147483647
	.long	0
	.long	0
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

/*
 ============================================================================
 Name        : NavierStokesSolver.cu
 Author      : Matt Kennedy
 Version     : 1.0
 Description : Solve the Navier-Stokes over a flat plate
 ============================================================================
 */


#include <hip/hip_runtime.h>
#include <iostream>
#include <numeric>
#include <stdlib.h>
#include <stdio.h>
#include <string.h>

using namespace std;



#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(hipError_t code, const char *file, int line, bool abort=true)
{
   if (code != hipSuccess)
   {
      fprintf(stderr,"GPUassert: %s %s %d\n", hipGetErrorString(code), file, line);
      if (abort) exit(code);
   }
}



// ================================================================
// ================================================================
// define any configuration parameters needed by both CPU and GPU
// ================================================================
// ================================================================

// note that we'll probably get segfaults if the cpu and gpu variables are set to different values!
// (they didn't seem to be happy trying to set one from the other, so need to manually change both for now)
// (and host code isn't happy about reading from a device global variable)
int jmax = 70;
int kmax = 70;
__constant__ int jmax_d = 70;
__constant__ int kmax_d = 70;

double plateLength = 0.00001;
__constant__ double plateLength_d = 0.00001;

double CFL = 0.2; // can fudge this to help stability
__constant__ double CFL_d = 0.2; // can fudge this to help stability

double M0 = 4.0;

double dx = plateLength / (jmax - 1); // uniform for now
//double dy = plateLength / (kmax - 1);
double dy = 1.1869 * pow(10.0,-7); // calculated from boundary layer


__constant__ double u0_d = 1361.12;



// ================================================================
// ================================================================
// define any global variables needed by the GPU
// ================================================================
// ================================================================

__constant__ double gam_d = 1.4; // seems "gamma" is a protected name from the numeric library
__constant__ double Pr_d = 0.71; // Prandtl number
__constant__ double R_d = 287.0; // specific gas constant
__constant__ double Cv_d = 0.7171*1000; // specific heat capacity of air
__constant__ double Cp_d = 1.006 * 1000; // specific heat capacity of air
__constant__ double mu0_d = 1.7894E-5; // dynamic viscosity of air
__constant__ double T0_d = 288.16;
__constant__ double p0_d = 101325.0;



// ================================================================
// ================================================================
// define any global variables needed by the CPU
// ================================================================
// ================================================================


double a0 = 340.28;
double u0 = M0*a0;

double p0 = 101325.0;
double T0 = 288.16;


double v0 = 0;

double gam = 1.4; // seems "gamma" is a protected name from the numeric library
double Pr = 0.71; // Prandtl number
double R = 287.0; // specific gas constant
double Cv = 0.7171*1000; // specific heat capacity of air
double Cp = 1.006 * 1000; // specific heat capacity of air

double rho0 = p0 / (R * T0);
double e0 = T0 * Cv;

double mu0 = 1.7894E-5; // dynamic viscosity of air
double Re = rho0 * u0 * plateLength / mu0;







__device__ void calc_Q(double* Q_d, double* u_d, double* v_d, double* p_d, double* T_d, int j, int k) {

	int ind2 = j*kmax_d + k; // flattened index for our 2d arrays
	int ind3_0 = (j + 0*jmax_d)*kmax_d + k; // flattened index for the first dim of our 3d arrays
	int ind3_1 = (j + 1*jmax_d)*kmax_d + k; // stack them like extra rows
	int ind3_2 = (j + 2*jmax_d)*kmax_d + k;
	int ind3_3 = (j + 3*jmax_d)*kmax_d + k;

	double rho_val = p_d[ind2] / (R_d * T_d[ind2]);
	double e_val = Cv_d * T_d[ind2]; // energy of air based on temp
	double Et_val = rho_val * (e_val + 0.5*(u_d[ind2]*u_d[ind2] + v_d[ind2]*v_d[ind2]));

	Q_d[ind3_0] = rho_val;
	Q_d[ind3_1] = rho_val * u_d[ind2];
	Q_d[ind3_2] = rho_val * v_d[ind2];
	Q_d[ind3_3] = Et_val;

}


__device__ void heatFluxParameters(double* T_d, double mu_val, bool isPredictor, int j, int k, double dx, double dy, double* q) {

	double dTdx;
	double dTdy;

	if (isPredictor) { // scheme is forward, make this backward

		if (j > 0)
			dTdx = (T_d[j*kmax_d + k] - T_d[(j-1)*kmax_d + k])/dx;
		else if (j == 0)
			dTdx = (T_d[(j+1)*kmax_d + k] - T_d[j*kmax_d + k])/dx;

		if (k > 0)
			dTdy = (T_d[j*kmax_d + k] - T_d[j*kmax_d + (k-1)])/dy;
		else if (k == 0)
			dTdy = (T_d[j*kmax_d + k + 1] - T_d[j*kmax_d + k])/dy;

	}
	else { // scheme is backward, make this forward

		if (j < jmax_d-1)
			dTdx = (T_d[(j+1)*kmax_d + k] - T_d[j*kmax_d + k])/dx;
		else if (j == jmax_d - 1)
			dTdx = (T_d[j*kmax_d + k] - T_d[(j-1)*kmax_d + k]) / dx;

		if (k < kmax_d-1)
			dTdy = (T_d[j*kmax_d+k+1] - T_d[j*kmax_d + k]) / dy;
		else if (k == kmax_d - 1)
			dTdy = (T_d[j*kmax_d + k] - T_d[j*kmax_d + k-1]) / dy;

	}

	double k_cond = mu_val * Cp_d / Pr_d;

	q[0] = -k_cond * dTdx;
	q[1] = -k_cond * dTdy;
}

__device__ void shearParameters(double* u_d, double* v_d, double mu, bool isPredictor, int j, int k, double dx, double dy, double* shears) {

	// calculate shear for a single location (j,k)
	// inputs are assumed to be entire matrices

	double dvdx_FB;
	double dudx_FB;
	double dvdy_FB;
	double dudy_FB;
	double dvdx_C;
	double dudx_C;
	double dvdy_C;
	double dudy_C;

	// calculate the forward or backward differenced versions
	if (isPredictor) {
	    // want opposite direction from scheme step differencing
	    // scheme is forward, make this backward

	    if (j > 0) {
	        dvdx_FB = (v_d[j*kmax_d + k] - v_d[(j-1)*kmax_d + k])/dx;
	        dudx_FB = (u_d[j*kmax_d + k] - u_d[(j-1)*kmax_d + k])/dx;
	    }
	    else {
	        dvdx_FB = (v_d[(j+1)*kmax_d + k] - v_d[j*kmax_d + k])/dx; // except first point forward
	        dudx_FB = (u_d[(j+1)*kmax_d + k] - u_d[j*kmax_d + k])/dx; // except first point forward
	    }



	    if (k > 0) {
	        dudy_FB = (u_d[j*kmax_d+k] - u_d[j*kmax_d+k-1])/dy;
	        dvdy_FB = (v_d[j*kmax_d+k] - v_d[j*kmax_d+k-1])/dy;
	    }
	    else {
	        dudy_FB = (u_d[j*kmax_d+k+1] - u_d[j*kmax_d+k])/dy; // except first point forward
	        dvdy_FB = (v_d[j*kmax_d+k+1] - v_d[j*kmax_d+k])/dy; // except first point forward
	    }

	}
	else {

	    // scheme is backward, make this forward

	    if (j < jmax_d - 1) {
	        dvdx_FB = (v_d[(j+1)*kmax_d + k] - v_d[j*kmax_d + k])/dx;
	        dudx_FB = (u_d[(j+1)*kmax_d + k] - u_d[j*kmax_d + k])/dx;
	    }
	    else {
	        dvdx_FB = (v_d[j*kmax_d+k] - v_d[(j-1)*kmax_d + k])/dx; // except jmax backward
	        dudx_FB = (u_d[j*kmax_d+k] - u_d[(j-1)*kmax_d + k])/dx; // except jmax backward
	    }

	    if (k < kmax_d-1) {
	        dudy_FB = (u_d[j*kmax_d + k+1] - u_d[j*kmax_d + k])/dy;
	        dvdy_FB = (v_d[j*kmax_d + k+1] - v_d[j*kmax_d + k])/dy;
	    }
	    else {
	    	dudy_FB = (u_d[j*kmax_d + k] - u_d[j*kmax_d + k-1])/dy; // except kmax backward
			dvdy_FB = (v_d[j*kmax_d + k] - v_d[j*kmax_d + k-1])/dy; // except kmax backward
	    }


	}

	// and then we want centeral differenced versions

	if (j == 0) {
	    dvdx_C = (v_d[(j+1)*kmax_d + k] - v_d[j*kmax_d + k])/dx;
	    dudx_C = (u_d[(j+1)*kmax_d + k] - u_d[j*kmax_d + k])/dx;
	}
	else if (j == jmax_d - 1)
	{
	    dvdx_C = (v_d[j*kmax_d + k] - v_d[(j-1)*kmax_d + k])/dx;
	    dudx_C = (u_d[j*kmax_d + k] - u_d[(j-1)*kmax_d + k])/dx;
	}
	else {
	    dvdx_C = (v_d[(j+1)*kmax_d + k] - v_d[(j-1)*kmax_d + k])/(2*dx);
	    dudx_C = (u_d[(j+1)*kmax_d + k] - u_d[(j-1)*kmax_d + k])/(2*dx);
	}



	if (k == 0) {
	    dudy_C = (u_d[j*kmax_d + k+1] - u_d[j*kmax_d + k])/dy;
	    dvdy_C = (v_d[j*kmax_d + k+1] - v_d[j*kmax_d + k])/dy;
	}
	else if (k == kmax_d-1) {
	    dudy_C = (u_d[j*kmax_d + k] - u_d[j*kmax_d + k-1])/dy;
	    dvdy_C = (v_d[j*kmax_d + k] - v_d[j*kmax_d + k-1])/dy;
	}
	else {
	    dudy_C = (u_d[j*kmax_d + k+1] - u_d[j*kmax_d + k-1])/(2*dy);
	    dvdy_C = (v_d[j*kmax_d + k+1] - v_d[j*kmax_d + k-1])/(2*dy);
	}


	// these come from page 65 and 66 in Anderson

	double lambda = -(2.0/3.0) * mu; // second viscosity coefficient estimated by Stokes

	// use the forward/backward du/dx and central dv/dy for both F and G
	double txx = lambda * ( dudx_FB + dvdy_C ) + 2 * mu * dudx_FB;

	// use the forward/backward dv/dy and central du/dx for both F and G
	double tyy = lambda * ( dudx_C + dvdy_FB ) + 2 * mu * dvdy_FB;

	double txy_F = mu * ( dvdx_FB + dudy_C );
	double txy_G = mu * ( dvdx_C + dudy_FB );

	shears[0] = txx;
	shears[1] = tyy;
	shears[2] = txy_F;
	shears[3] = txy_G;

}


__device__ void calc_FG(double* F_d, double* G_d, double* u_d, double* v_d, double* p_d, double* T_d, bool isPredictor, int j, int k, double dx, double dy) {

	int ind2 = j*kmax_d + k; // flattened index for our 2d arrays
	int ind3_0 = (j + 0*jmax_d)*kmax_d + k; // flattened index for the first dim of our 3d arrays
	int ind3_1 = (j + 1*jmax_d)*kmax_d + k; // stack them like extra rows
	int ind3_2 = (j + 2*jmax_d)*kmax_d + k;
	int ind3_3 = (j + 3*jmax_d)*kmax_d + k;

	double rho_val = p_d[ind2] / (R_d * T_d[ind2]);
	double e_val = Cv_d * T_d[ind2]; // energy of air based on temp
	double Et_val = rho_val * (e_val + 0.5*(u_d[ind2]*u_d[ind2] + v_d[ind2]*v_d[ind2]));

	double mu_val = mu0_d * pow(T_d[ind2] / T0_d, 1.5) * (T0_d + 110)/(T_d[ind2] + 110); // sutherlands law

	double q[2];
	double shears[4];

	heatFluxParameters(T_d, mu_val, isPredictor, j, k, dx, dy, q);
	shearParameters(u_d, v_d, mu_val, isPredictor, j, k, dx, dy, shears);

	// and unpack these for easier use
	double qx = q[0];
	double qy = q[1];
	double txx = shears[0];
	double tyy = shears[1];
	double txy_F = shears[2];
	double txy_G = shears[3];


	F_d[ind3_0] = rho_val * u_d[ind2];
	F_d[ind3_1] = rho_val * pow(u_d[ind2],2) + p_d[ind2] - txx;
	F_d[ind3_2] = rho_val * u_d[ind2]*v_d[ind2] - txy_F;
	F_d[ind3_3] = (Et_val + p_d[ind2]) * u_d[ind2] - u_d[ind2] * txx - v_d[ind2] * txy_F + qx;

	G_d[ind3_0] = rho_val * v_d[ind2];
	G_d[ind3_1] = rho_val * u_d[ind2] * v_d[ind2] - txy_G;
	G_d[ind3_2] = rho_val * pow(v_d[ind2],2) + p_d[ind2] - tyy;
	G_d[ind3_3] = (Et_val + p_d[ind2]) * v_d[ind2] - u_d[ind2] * txy_G - v_d[ind2] * tyy + qy;

}


__device__ void MacCormackPredictorUniform(double* Q_pred_d, double* Q_d, double* F_d, double* G_d, double dt, int j, int k, double dx, double dy) {

// DO MACCORMACKS FOR INTERIOR POINTS ONLY
	if (j == 0 || k == 0 || j == jmax_d-1 || k == kmax_d-1)
		return;

	// have each thread calculate all 4 dimensions at a single loc
	double flux;
	for (int dim=0; dim<4; dim++) {

		int ind_this = (j + dim*jmax_d)*kmax_d + k;
		int ind_nextJ = (j+1 + dim*jmax_d)*kmax_d + k;
		int ind_nextK = (j + dim*jmax_d)*kmax_d + k+1;

		flux = (F_d[ind_nextJ] - F_d[ind_this])/dx + (G_d[ind_nextK] - G_d[ind_this])/dy;
		Q_pred_d[ind_this] = Q_d[ind_this] - dt * flux;
	}
}


__device__ void MacCormackCorrectorUniform(double* Q_pred_d, double* Q_d, double* F_d, double* G_d, double dt, int j, int k, double dx, double dy) {

	// DO MACCORMACKS FOR INTERIOR POINTS ONLY
	if (j == 0 || k == 0 || j == jmax_d-1 || k == kmax_d-1)
		return;

	// have each thread calculate all 4 dimensions at a single (j,k) location
	double flux;
	for (int dim=0; dim<4; dim++) {

		int ind_this = (j + dim*jmax_d)*kmax_d + k;
		int ind_prevJ = (j-1 + dim*jmax_d)*kmax_d + k;
		int ind_prevK = (j + dim*jmax_d)*kmax_d + k-1;

		flux = (F_d[ind_this] - F_d[ind_prevJ])/dx + (G_d[ind_this] - G_d[ind_prevK])/dy;
		Q_d[ind_this] = 0.5*( Q_d[ind_this] + Q_pred_d[ind_this] - dt*flux );
	}
}


__device__ void primativesFromQ(double* Q_d, double* rho_d, double* u_d, double* v_d, double* p_d, double* T_d, double* e_d, int j, int k) {

	int ind2 = j*kmax_d + k; // flattened index for our 2d arrays
	int ind3_0 = (j + 0*jmax_d)*kmax_d + k; // flattened index for the first dim of our 3d arrays
	int ind3_1 = (j + 1*jmax_d)*kmax_d + k; // stack them like extra rows
	int ind3_2 = (j + 2*jmax_d)*kmax_d + k;
	int ind3_3 = (j + 3*jmax_d)*kmax_d + k;

	rho_d[ind2] = Q_d[ind3_0];
	u_d[ind2] = Q_d[ind3_1] / Q_d[ind3_0];
	v_d[ind2] = Q_d[ind3_2] / Q_d[ind3_0];
	e_d[ind2] = Q_d[ind3_3] / Q_d[ind3_0] - 0.5*( pow(u_d[ind2], 2) + pow(v_d[ind2], 2) );

	T_d[ind2] = e_d[ind2] / Cv_d;
	p_d[ind2] = Q_d[ind3_0] * R_d * T_d[ind2];

}


__device__ void enforceBC_nonSurface(double* u_d, double* v_d, double* p_d, double* T_d, int j, int k) {

	// need to first establish all the boundary conditions at the non-surface
	// values, and then go back and do the surface boundary conditions

	// this is really only needed if the surface goes all the way to the outflow
	// so that the last surface point can be interpolated with updated values

	int ind = j*kmax_d + k;

	if ( j == 0 && k == 0) {  // leading edge

		u_d[ind] = 0;
		v_d[ind] = 0;
		p_d[ind] = p0_d;
		T_d[ind] = T0_d;
	}
	else if (j == 0 || k == kmax_d-1) { // inflow from upstream OR upper boundary

		u_d[ind] = u0_d;
		v_d[ind] = 0;
		p_d[ind] = p0_d;
		T_d[ind] = T0_d;
	}
	else if (j == jmax_d-1) { // outflow -- extrapolate from interior values
		int ind1 = (j-1)*kmax_d + k;
		int ind2 = (j-2)*kmax_d + k;

		u_d[ind] = 2*u_d[ind1] - u_d[ind2];
		v_d[ind] = 2*v_d[ind1] - v_d[ind2];
		p_d[ind] = 2*p_d[ind1] - p_d[ind2];
		T_d[ind] = 2*T_d[ind1] - T_d[ind2];

	}
}


__device__ void enforceBC_surface(double* u_d, double* v_d, double* p_d, double* T_d, int j, int k) {

	// need to first establish all the boundary conditions at the non-surface
	// values, and then go back and do the surface boundary conditions

	// this is really only needed if the surface goes all the way to the outflow
	// so that the last surface point can be interpolated with updated values

	int ind = j*kmax_d + k;

	if (k == 0 && j > 0){
		u_d[ind] = 0;
		v_d[ind] = 0;
		p_d[ind] = 2*p_d[j*kmax_d + 1] - p_d[j*kmax_d + 2];
		T_d[ind] = T_d[j*kmax_d + 1];
	}

}




__global__ void iterateScheme_part1(double* x_d, double* y_d, double* u_d, double* v_d, double* p_d, double* T_d, double* rho_d, double* e_d, double* Q_d, double* Q_pred_d, double* F_d, double* G_d, double dx, double dy, double dt) {

	int j = blockIdx.x * blockDim.x + threadIdx.x;
	int k = blockIdx.y * blockDim.y + threadIdx.y;

	if (j < jmax_d && k < kmax_d)
	{

		calc_Q(Q_d, u_d, v_d, p_d, T_d, j, k);

		bool isPredictor = true;
		calc_FG(F_d, G_d, u_d, v_d, p_d, T_d, isPredictor, j, k, dx, dy);


		// think we need to actually do different kernel launches here ...
		// seems to be no easy way to sync all blocks, and inherently not all blocks may be executed at once if the grid gets too large

//		MacCormackPredictorUniform(Q_pred_d, Q_d, F_d, G_d, dt, j, k, dx, dy);

	}
}


__global__ void iterateScheme_part2(double* x_d, double* y_d, double* u_d, double* v_d, double* p_d, double* T_d, double* rho_d, double* e_d, double* Q_d, double* Q_pred_d, double* F_d, double* G_d, double dx, double dy, double dt) {

	int j = blockIdx.x * blockDim.x + threadIdx.x;
	int k = blockIdx.y * blockDim.y + threadIdx.y;

	if (j < jmax_d && k < kmax_d)
	{

		// think we need to actually do different kernel launches here ...
		// seems to be no easy way to sync all blocks, and inherently not all blocks may be executed at once if the grid gets too large

		MacCormackPredictorUniform(Q_pred_d, Q_d, F_d, G_d, dt, j, k, dx, dy);

		primativesFromQ(Q_pred_d, rho_d, u_d, v_d, p_d, T_d, e_d, j, k);

	}
}


__global__ void iterateScheme_part3(double* x_d, double* y_d, double* u_d, double* v_d, double* p_d, double* T_d, double* rho_d, double* e_d, double* Q_d, double* Q_pred_d, double* F_d, double* G_d, double dx, double dy, double dt) {

	int j = blockIdx.x * blockDim.x + threadIdx.x;
	int k = blockIdx.y * blockDim.y + threadIdx.y;

	if (j < jmax_d && k < kmax_d)
	{

		enforceBC_nonSurface(u_d, v_d, p_d, T_d, j, k);

	}
}


__global__ void iterateScheme_part4(double* x_d, double* y_d, double* u_d, double* v_d, double* p_d, double* T_d, double* rho_d, double* e_d, double* Q_d, double* Q_pred_d, double* F_d, double* G_d, double dx, double dy, double dt) {

	int j = blockIdx.x * blockDim.x + threadIdx.x;
	int k = blockIdx.y * blockDim.y + threadIdx.y;

	if (j < jmax_d && k < kmax_d)
	{

		enforceBC_surface(u_d, v_d, p_d, T_d, j, k);

	}
}


__global__ void iterateScheme_part5(double* x_d, double* y_d, double* u_d, double* v_d, double* p_d, double* T_d, double* rho_d, double* e_d, double* Q_d, double* Q_pred_d, double* F_d, double* G_d, double dx, double dy, double dt) {

	int j = blockIdx.x * blockDim.x + threadIdx.x;
	int k = blockIdx.y * blockDim.y + threadIdx.y;

	if (j < jmax_d && k < kmax_d)
	{

		bool isPredictor = false;
		calc_FG(F_d, G_d, u_d, v_d, p_d, T_d, isPredictor, j, k, dx, dy);

	}
}


__global__ void iterateScheme_part6(double* x_d, double* y_d, double* u_d, double* v_d, double* p_d, double* T_d, double* rho_d, double* e_d, double* Q_d, double* Q_pred_d, double* F_d, double* G_d, double dx, double dy, double dt) {

	int j = blockIdx.x * blockDim.x + threadIdx.x;
	int k = blockIdx.y * blockDim.y + threadIdx.y;

	if (j < jmax_d && k < kmax_d)
	{

		MacCormackCorrectorUniform(Q_pred_d, Q_d, F_d, G_d, dt, j, k, dx, dy);

		primativesFromQ(Q_d, rho_d, u_d, v_d, p_d, T_d, e_d, j, k);

	}
}


__global__ void iterateScheme_part7(double* x_d, double* y_d, double* u_d, double* v_d, double* p_d, double* T_d, double* rho_d, double* e_d, double* Q_d, double* Q_pred_d, double* F_d, double* G_d, double dx, double dy, double dt) {

	int j = blockIdx.x * blockDim.x + threadIdx.x;
	int k = blockIdx.y * blockDim.y + threadIdx.y;

	if (j < jmax_d && k < kmax_d)
	{

		enforceBC_nonSurface(u_d, v_d, p_d, T_d, j, k);

	}
}


__global__ void iterateScheme_part8(double* x_d, double* y_d, double* u_d, double* v_d, double* p_d, double* T_d, double* rho_d, double* e_d, double* Q_d, double* Q_pred_d, double* F_d, double* G_d, double dx, double dy, double dt) {

	int j = blockIdx.x * blockDim.x + threadIdx.x;
	int k = blockIdx.y * blockDim.y + threadIdx.y;

	if (j < jmax_d && k < kmax_d)
	{

		enforceBC_surface(u_d, v_d, p_d, T_d, j, k);

	}
}






double BoundaryLayerThickness() {
	return 5 * plateLength / sqrt(Re);
}

void setupGrid(double* x, double* y) {
	// just do a uniform grid for now

	for (int j=0; j<jmax; j++)
		x[j] = j*dx;
	for (int k=0; k<kmax; k++)
		y[k] = k*dy;
}

void initializePrimatives(double* u, double* v, double* p, double* T, double* rho, double* e) {

	for (int j=0; j<jmax; j++) {
		for (int k=0; k<kmax; k++) {
			u[j*kmax+k] = u0;
			v[j*kmax+k] = v0;
			p[j*kmax+k] = p0;
			T[j*kmax+k] = T0;
			rho[j*kmax+k] = rho0;
			e[j*kmax+k] = e0;
		}
	}
}


void applyBC_UpperPlate(double* u, double* v, double* p, double* T) {


	// leading edge
	u[0*kmax+0] = 0;
	v[0*kmax+0] = 0;
	p[0*kmax+0] = p0;
	T[0*kmax+0] = T0;

	// inflow (j=0, k=all)
	for (int k=0; k<kmax; k++) {
		u[0*kmax+k] = u0;
		v[0*kmax+k] = 0;
		p[0*kmax+k] = p0;
		T[0*kmax+k] = T0;
	}

	// upper boundary (j=all, k=kmax-1)
	for (int j=0; j<jmax; j++) {
		u[j*kmax+kmax-1] = u0;
		v[j*kmax+kmax-1] = 0;
		p[j*kmax+kmax-1] = p0;
		T[j*kmax+kmax-1] = T0;
	}

	// outflow (j=jmax-1, k=all)
	// extrapolate from interior values
	for (int k=0; k<kmax; k++) {
		u[(jmax-1)*kmax + k] = 2*u[(jmax-2)*kmax + k] - u[(jmax-3)*kmax + k];
		v[(jmax-1)*kmax + k] = 2*v[(jmax-2)*kmax + k] - v[(jmax-3)*kmax + k];
		p[(jmax-1)*kmax + k] = 2*p[(jmax-2)*kmax + k] - p[(jmax-3)*kmax + k];
		T[(jmax-1)*kmax + k] = 2*T[(jmax-2)*kmax + k] - T[(jmax-3)*kmax + k];
	}

	// and plate surface (j=all, k=0)
	for (int j=0; j<jmax; j++) {
		u[j*kmax + 0] = 0;
		v[j*kmax + 0] = 0;
		p[j*kmax + 0] = 2*p[j*kmax + 1] - p[j*kmax + 2];
		T[j*kmax + 0] = T[j*kmax + 1];
	}


}


double calc_dt(double* u, double* v, double* p, double* T, double dx, double dy) {

	// not sure the best way to do this on the GPU
	// seems to be some parallel reduce functions which can be called as their own kernels
	// which would at least prevent us from having to copy back the primative variables to the host every iteration
	// but lets not worry about that for now

	double rho_val;
	double mu_val;
	double temp_val;

	double vprime = -INFINITY;
	for (int j=0; j<jmax; j++) {
		for (int k=0; k<kmax; k++) {

			int ind = j*kmax + k;

			rho_val = p[ind] / (R * T[ind]);
			mu_val = mu0 * pow(T[ind]/T0, 1.5) * (T0 + 110)/(T[ind] + 110);

			temp_val = (4/3) * mu_val * (gam * mu_val / Pr) / rho_val; // find the max of this
			if (temp_val > vprime)
				vprime = temp_val;
		}
	}

	double spaceUnit = pow( 1/(dx*dx) + 1/(dy*dy), 0.5 );
	double term1;
	double term2;
	double term3;
	double term4;
	double dt_cfl;

	double dt = INFINITY;
	for (int j=0; j<jmax; j++) {
		for (int k=0; k<kmax; k++) {

			int ind = j*kmax + k;

			rho_val = p[ind] / (R * T[ind]);

			term1 = abs( u[ind] ) / dx;
			term2 = abs( v[ind] ) / dy;
			term3 = pow( gam*p[ind]/rho_val, 0.5 ) * spaceUnit;
			term4 = 2 * vprime * pow(spaceUnit, 2);

			dt_cfl = 1/(term1 + term2 + term3 + term4);

			if (CFL*dt_cfl < dt)
				dt = CFL*dt_cfl;
		}
	}

	return dt;
}



void arrayToCSV(double* values, char* filename, int numDims) {
 FILE *fp;
 fp = fopen(filename, "w+");

 for (int dim=0; dim<numDims; dim++) {
	 for (int j=0; j<jmax; j++) {
		 for (int k=0; k<kmax; k++) {

			 fprintf(fp, ", %f", values[(j + dim*jmax)*kmax + k]);
		 }
		 fprintf(fp, "\n");
	 }

	 if (dim < numDims-1)
		 fprintf(fp, "Dimension Starting: %i\n", dim+1);
 }


}


int main(void)
{

	double* x = (double*)malloc(jmax*sizeof(double));
	double* y = (double*)malloc(kmax*sizeof(double));

	double* u = (double*)malloc( jmax*kmax*sizeof(double) );
	double* v = (double*)malloc( jmax*kmax*sizeof(double) );
	double* p = (double*)malloc( jmax*kmax*sizeof(double) );
	double* T = (double*)malloc( jmax*kmax*sizeof(double) );
	double* rho = (double*)malloc( jmax*kmax*sizeof(double) );
	double* e = (double*)malloc( jmax*kmax*sizeof(double) );



	initializePrimatives(u, v, p, T, rho, e);
	applyBC_UpperPlate(u, v, p, T);




	// technically only needed in GPU memory, but I assume we may want to copy back intermediate results for debugging
	// calculating these will be a main component of what's being done in parallel, so don't need to initialize anything
	double* Q = (double*)malloc( 4*jmax*kmax*sizeof(double));
	double* Q_pred = (double*)malloc( 4*jmax*kmax*sizeof(double));
	double* F = (double*)malloc( 4*jmax*kmax*sizeof(double));
	double* G = (double*)malloc( 4*jmax*kmax*sizeof(double));


	// iniitialize and allocate device variables
	double* x_d;
	double* y_d;
	double* u_d;
	double* v_d;
	double* p_d;
	double* T_d;
	double* rho_d;
	double* e_d;
	double* Q_d;
	double* Q_pred_d;
	double* F_d;
	double* G_d;

	hipError_t err;

	err = hipMalloc((void**)&x_d, jmax*kmax*sizeof(double) );
	err = hipMalloc((void**)&y_d, jmax*kmax*sizeof(double) );
	err = hipMalloc((void**)&u_d, jmax*kmax*sizeof(double) );
	err = hipMalloc((void**)&v_d, jmax*kmax*sizeof(double) );
	err = hipMalloc((void**)&p_d, jmax*kmax*sizeof(double) );
	err = hipMalloc((void**)&T_d, jmax*kmax*sizeof(double) );
	err = hipMalloc((void**)&rho_d, jmax*kmax*sizeof(double) );
	err = hipMalloc((void**)&e_d, jmax*kmax*sizeof(double) );

	// these are all 3d arrays
	err = hipMalloc((void**)&Q_d, 4*jmax*kmax*sizeof(double) );
	err = hipMalloc((void**)&Q_pred_d, 4*jmax*kmax*sizeof(double) );
	err = hipMalloc((void**)&F_d, 4*jmax*kmax*sizeof(double) );
	err = hipMalloc((void**)&G_d, 4*jmax*kmax*sizeof(double) );


	err = hipMemcpy(x_d, x, jmax*kmax*sizeof(double), hipMemcpyHostToDevice);
	err = hipMemcpy(y_d, y, jmax*kmax*sizeof(double), hipMemcpyHostToDevice);
	err = hipMemcpy(u_d, u, jmax*kmax*sizeof(double), hipMemcpyHostToDevice);
	err = hipMemcpy(v_d, v, jmax*kmax*sizeof(double), hipMemcpyHostToDevice);
	err = hipMemcpy(p_d, p, jmax*kmax*sizeof(double), hipMemcpyHostToDevice);
	err = hipMemcpy(T_d, T, jmax*kmax*sizeof(double), hipMemcpyHostToDevice);
	err = hipMemcpy(rho_d, rho, jmax*kmax*sizeof(double), hipMemcpyHostToDevice);
	gpuErrchk( hipMemcpy(e_d, e, jmax*kmax*sizeof(double), hipMemcpyHostToDevice) );






	dim3 threadsPerBlock(16,16);
	dim3 numBlocks(jmax/threadsPerBlock.x + 1, kmax/threadsPerBlock.y + 1);

	// so to force the threads to sync I think it's safer to just do the different stages in different kernel calls, at least initially
	int maxIter = 1000;
	for (int iter=0; iter<maxIter; iter++) {

		printf("Calculating iteration %i / %i\n", iter+1, maxIter);

		double dt = calc_dt(u, v, p, T, dx, dy);

		// calculate F, G, and Q
		iterateScheme_part1<<<numBlocks, threadsPerBlock>>> (x_d, y_d, u_d, v_d, p_d, T_d, rho_d, e_d, Q_d, Q_pred_d, F_d, G_d, dx, dy, dt);
		gpuErrchk( hipPeekAtLastError() );
		gpuErrchk( hipDeviceSynchronize() );


		// calculate MacCormack's Predictor and get back primatives out of Q
		iterateScheme_part2<<<numBlocks, threadsPerBlock>>> (x_d, y_d, u_d, v_d, p_d, T_d, rho_d, e_d, Q_d, Q_pred_d, F_d, G_d, dx, dy, dt);
		gpuErrchk( hipPeekAtLastError() );
		gpuErrchk( hipDeviceSynchronize() );

		// enforce boundary conditions at non-surface points
		iterateScheme_part3<<<numBlocks, threadsPerBlock>>> (x_d, y_d, u_d, v_d, p_d, T_d, rho_d, e_d, Q_d, Q_pred_d, F_d, G_d, dx, dy, dt);
		gpuErrchk( hipPeekAtLastError() );
		gpuErrchk( hipDeviceSynchronize() );

		// enforce boundary conditions at surface points
		iterateScheme_part4<<<numBlocks, threadsPerBlock>>> (x_d, y_d, u_d, v_d, p_d, T_d, rho_d, e_d, Q_d, Q_pred_d, F_d, G_d, dx, dy, dt);
		gpuErrchk( hipPeekAtLastError() );
		gpuErrchk( hipDeviceSynchronize() );

		// update F and G for corrected primatives
		iterateScheme_part5<<<numBlocks, threadsPerBlock>>> (x_d, y_d, u_d, v_d, p_d, T_d, rho_d, e_d, Q_d, Q_pred_d, F_d, G_d, dx, dy, dt);
		gpuErrchk( hipPeekAtLastError() );
		gpuErrchk( hipDeviceSynchronize() );

		// calculate MacCormack's Corrector and get back primatives out of Q
		iterateScheme_part6<<<numBlocks, threadsPerBlock>>> (x_d, y_d, u_d, v_d, p_d, T_d, rho_d, e_d, Q_d, Q_pred_d, F_d, G_d, dx, dy, dt);
		gpuErrchk( hipPeekAtLastError() );
		gpuErrchk( hipDeviceSynchronize() );

		// enforce boundary conditions at non-surface points
		iterateScheme_part7<<<numBlocks, threadsPerBlock>>> (x_d, y_d, u_d, v_d, p_d, T_d, rho_d, e_d, Q_d, Q_pred_d, F_d, G_d, dx, dy, dt);
		gpuErrchk( hipPeekAtLastError() );
		gpuErrchk( hipDeviceSynchronize() );

		// enforce boundary conditions at surface points
		iterateScheme_part8<<<numBlocks, threadsPerBlock>>> (x_d, y_d, u_d, v_d, p_d, T_d, rho_d, e_d, Q_d, Q_pred_d, F_d, G_d, dx, dy, dt);
		gpuErrchk( hipPeekAtLastError() );
		gpuErrchk( hipDeviceSynchronize() );

		hipMemcpy(u, u_d, jmax*kmax*sizeof(double), hipMemcpyDeviceToHost);
		hipMemcpy(v, v_d, jmax*kmax*sizeof(double), hipMemcpyDeviceToHost);
		hipMemcpy(p, p_d, jmax*kmax*sizeof(double), hipMemcpyDeviceToHost);
		hipMemcpy(T, T_d, jmax*kmax*sizeof(double), hipMemcpyDeviceToHost);

	}


	hipMemcpy(F, F_d, 4*jmax*kmax*sizeof(double), hipMemcpyDeviceToHost);
	hipMemcpy(G, G_d, 4*jmax*kmax*sizeof(double), hipMemcpyDeviceToHost);
	hipMemcpy(Q, Q_d, 4*jmax*kmax*sizeof(double), hipMemcpyDeviceToHost);

	arrayToCSV(u, "u.csv", 1);
	arrayToCSV(v, "v.csv", 1);
	arrayToCSV(p, "p.csv", 1);
	arrayToCSV(T, "T.csv", 1);

	arrayToCSV(F, "F.csv", 4);
	arrayToCSV(G, "G.csv", 4);
	arrayToCSV(Q, "Q.csv", 4);






	free(x);
	free(y);
	free(u);
	free(v);
	free(p);
	free(T);
	free(rho);
	free(e);
	free(Q);
	free(Q_pred);
	free(F);
	free(G);

	hipFree(x_d);
	hipFree(y_d);
	hipFree(u_d);
	hipFree(v_d);
	hipFree(p_d);
	hipFree(T_d);
	hipFree(rho_d);
	hipFree(e_d);

	hipFree(Q_d);
	hipFree(Q_pred_d);
	hipFree(F_d);
	hipFree(G_d);

	printf("Finishing!\n");

	return 0;
}


	.text
	.file	"NavierStokesSolver.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z34__device_stub__iterateScheme_part1PdS_S_S_S_S_S_S_S_S_S_S_ddd # -- Begin function _Z34__device_stub__iterateScheme_part1PdS_S_S_S_S_S_S_S_S_S_S_ddd
	.type	_Z34__device_stub__iterateScheme_part1PdS_S_S_S_S_S_S_S_S_S_S_ddd,@function
_Z34__device_stub__iterateScheme_part1PdS_S_S_S_S_S_S_S_S_S_S_ddd: # @_Z34__device_stub__iterateScheme_part1PdS_S_S_S_S_S_S_S_S_S_S_ddd
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$256, %rsp                      # imm = 0x100
	.cfi_def_cfa_offset 304
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	88(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	80(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	72(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	64(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	56(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	48(%rsp), %r8
	movq	%r9, (%r8)
	leaq	40(%rsp), %r9
	movsd	%xmm0, (%r9)
	leaq	32(%rsp), %r10
	movsd	%xmm1, (%r10)
	leaq	24(%rsp), %r11
	movsd	%xmm2, (%r11)
	leaq	128(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	304(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	312(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	320(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	328(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	336(%rsp), %rax
	movq	%rax, 80(%rbx)
	leaq	344(%rsp), %rax
	movq	%rax, 88(%rbx)
	movq	%r9, 96(%rbx)
	movq	%r10, 104(%rbx)
	movq	%r11, 112(%rbx)
	leaq	112(%rsp), %r14
	leaq	96(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z19iterateScheme_part1PdS_S_S_S_S_S_S_S_S_S_S_ddd, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$272, %rsp                      # imm = 0x110
	.cfi_adjust_cfa_offset -272
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z34__device_stub__iterateScheme_part1PdS_S_S_S_S_S_S_S_S_S_S_ddd, .Lfunc_end0-_Z34__device_stub__iterateScheme_part1PdS_S_S_S_S_S_S_S_S_S_S_ddd
	.cfi_endproc
                                        # -- End function
	.globl	_Z34__device_stub__iterateScheme_part2PdS_S_S_S_S_S_S_S_S_S_S_ddd # -- Begin function _Z34__device_stub__iterateScheme_part2PdS_S_S_S_S_S_S_S_S_S_S_ddd
	.type	_Z34__device_stub__iterateScheme_part2PdS_S_S_S_S_S_S_S_S_S_S_ddd,@function
_Z34__device_stub__iterateScheme_part2PdS_S_S_S_S_S_S_S_S_S_S_ddd: # @_Z34__device_stub__iterateScheme_part2PdS_S_S_S_S_S_S_S_S_S_S_ddd
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$256, %rsp                      # imm = 0x100
	.cfi_def_cfa_offset 304
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	88(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	80(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	72(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	64(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	56(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	48(%rsp), %r8
	movq	%r9, (%r8)
	leaq	40(%rsp), %r9
	movsd	%xmm0, (%r9)
	leaq	32(%rsp), %r10
	movsd	%xmm1, (%r10)
	leaq	24(%rsp), %r11
	movsd	%xmm2, (%r11)
	leaq	128(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	304(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	312(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	320(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	328(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	336(%rsp), %rax
	movq	%rax, 80(%rbx)
	leaq	344(%rsp), %rax
	movq	%rax, 88(%rbx)
	movq	%r9, 96(%rbx)
	movq	%r10, 104(%rbx)
	movq	%r11, 112(%rbx)
	leaq	112(%rsp), %r14
	leaq	96(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z19iterateScheme_part2PdS_S_S_S_S_S_S_S_S_S_S_ddd, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$272, %rsp                      # imm = 0x110
	.cfi_adjust_cfa_offset -272
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z34__device_stub__iterateScheme_part2PdS_S_S_S_S_S_S_S_S_S_S_ddd, .Lfunc_end1-_Z34__device_stub__iterateScheme_part2PdS_S_S_S_S_S_S_S_S_S_S_ddd
	.cfi_endproc
                                        # -- End function
	.globl	_Z34__device_stub__iterateScheme_part3PdS_S_S_S_S_S_S_S_S_S_S_ddd # -- Begin function _Z34__device_stub__iterateScheme_part3PdS_S_S_S_S_S_S_S_S_S_S_ddd
	.type	_Z34__device_stub__iterateScheme_part3PdS_S_S_S_S_S_S_S_S_S_S_ddd,@function
_Z34__device_stub__iterateScheme_part3PdS_S_S_S_S_S_S_S_S_S_S_ddd: # @_Z34__device_stub__iterateScheme_part3PdS_S_S_S_S_S_S_S_S_S_S_ddd
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$256, %rsp                      # imm = 0x100
	.cfi_def_cfa_offset 304
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	88(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	80(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	72(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	64(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	56(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	48(%rsp), %r8
	movq	%r9, (%r8)
	leaq	40(%rsp), %r9
	movsd	%xmm0, (%r9)
	leaq	32(%rsp), %r10
	movsd	%xmm1, (%r10)
	leaq	24(%rsp), %r11
	movsd	%xmm2, (%r11)
	leaq	128(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	304(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	312(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	320(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	328(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	336(%rsp), %rax
	movq	%rax, 80(%rbx)
	leaq	344(%rsp), %rax
	movq	%rax, 88(%rbx)
	movq	%r9, 96(%rbx)
	movq	%r10, 104(%rbx)
	movq	%r11, 112(%rbx)
	leaq	112(%rsp), %r14
	leaq	96(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z19iterateScheme_part3PdS_S_S_S_S_S_S_S_S_S_S_ddd, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$272, %rsp                      # imm = 0x110
	.cfi_adjust_cfa_offset -272
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z34__device_stub__iterateScheme_part3PdS_S_S_S_S_S_S_S_S_S_S_ddd, .Lfunc_end2-_Z34__device_stub__iterateScheme_part3PdS_S_S_S_S_S_S_S_S_S_S_ddd
	.cfi_endproc
                                        # -- End function
	.globl	_Z34__device_stub__iterateScheme_part4PdS_S_S_S_S_S_S_S_S_S_S_ddd # -- Begin function _Z34__device_stub__iterateScheme_part4PdS_S_S_S_S_S_S_S_S_S_S_ddd
	.type	_Z34__device_stub__iterateScheme_part4PdS_S_S_S_S_S_S_S_S_S_S_ddd,@function
_Z34__device_stub__iterateScheme_part4PdS_S_S_S_S_S_S_S_S_S_S_ddd: # @_Z34__device_stub__iterateScheme_part4PdS_S_S_S_S_S_S_S_S_S_S_ddd
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$256, %rsp                      # imm = 0x100
	.cfi_def_cfa_offset 304
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	88(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	80(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	72(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	64(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	56(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	48(%rsp), %r8
	movq	%r9, (%r8)
	leaq	40(%rsp), %r9
	movsd	%xmm0, (%r9)
	leaq	32(%rsp), %r10
	movsd	%xmm1, (%r10)
	leaq	24(%rsp), %r11
	movsd	%xmm2, (%r11)
	leaq	128(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	304(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	312(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	320(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	328(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	336(%rsp), %rax
	movq	%rax, 80(%rbx)
	leaq	344(%rsp), %rax
	movq	%rax, 88(%rbx)
	movq	%r9, 96(%rbx)
	movq	%r10, 104(%rbx)
	movq	%r11, 112(%rbx)
	leaq	112(%rsp), %r14
	leaq	96(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z19iterateScheme_part4PdS_S_S_S_S_S_S_S_S_S_S_ddd, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$272, %rsp                      # imm = 0x110
	.cfi_adjust_cfa_offset -272
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	_Z34__device_stub__iterateScheme_part4PdS_S_S_S_S_S_S_S_S_S_S_ddd, .Lfunc_end3-_Z34__device_stub__iterateScheme_part4PdS_S_S_S_S_S_S_S_S_S_S_ddd
	.cfi_endproc
                                        # -- End function
	.globl	_Z34__device_stub__iterateScheme_part5PdS_S_S_S_S_S_S_S_S_S_S_ddd # -- Begin function _Z34__device_stub__iterateScheme_part5PdS_S_S_S_S_S_S_S_S_S_S_ddd
	.type	_Z34__device_stub__iterateScheme_part5PdS_S_S_S_S_S_S_S_S_S_S_ddd,@function
_Z34__device_stub__iterateScheme_part5PdS_S_S_S_S_S_S_S_S_S_S_ddd: # @_Z34__device_stub__iterateScheme_part5PdS_S_S_S_S_S_S_S_S_S_S_ddd
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$256, %rsp                      # imm = 0x100
	.cfi_def_cfa_offset 304
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	88(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	80(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	72(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	64(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	56(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	48(%rsp), %r8
	movq	%r9, (%r8)
	leaq	40(%rsp), %r9
	movsd	%xmm0, (%r9)
	leaq	32(%rsp), %r10
	movsd	%xmm1, (%r10)
	leaq	24(%rsp), %r11
	movsd	%xmm2, (%r11)
	leaq	128(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	304(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	312(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	320(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	328(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	336(%rsp), %rax
	movq	%rax, 80(%rbx)
	leaq	344(%rsp), %rax
	movq	%rax, 88(%rbx)
	movq	%r9, 96(%rbx)
	movq	%r10, 104(%rbx)
	movq	%r11, 112(%rbx)
	leaq	112(%rsp), %r14
	leaq	96(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z19iterateScheme_part5PdS_S_S_S_S_S_S_S_S_S_S_ddd, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$272, %rsp                      # imm = 0x110
	.cfi_adjust_cfa_offset -272
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end4:
	.size	_Z34__device_stub__iterateScheme_part5PdS_S_S_S_S_S_S_S_S_S_S_ddd, .Lfunc_end4-_Z34__device_stub__iterateScheme_part5PdS_S_S_S_S_S_S_S_S_S_S_ddd
	.cfi_endproc
                                        # -- End function
	.globl	_Z34__device_stub__iterateScheme_part6PdS_S_S_S_S_S_S_S_S_S_S_ddd # -- Begin function _Z34__device_stub__iterateScheme_part6PdS_S_S_S_S_S_S_S_S_S_S_ddd
	.type	_Z34__device_stub__iterateScheme_part6PdS_S_S_S_S_S_S_S_S_S_S_ddd,@function
_Z34__device_stub__iterateScheme_part6PdS_S_S_S_S_S_S_S_S_S_S_ddd: # @_Z34__device_stub__iterateScheme_part6PdS_S_S_S_S_S_S_S_S_S_S_ddd
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$256, %rsp                      # imm = 0x100
	.cfi_def_cfa_offset 304
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	88(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	80(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	72(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	64(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	56(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	48(%rsp), %r8
	movq	%r9, (%r8)
	leaq	40(%rsp), %r9
	movsd	%xmm0, (%r9)
	leaq	32(%rsp), %r10
	movsd	%xmm1, (%r10)
	leaq	24(%rsp), %r11
	movsd	%xmm2, (%r11)
	leaq	128(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	304(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	312(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	320(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	328(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	336(%rsp), %rax
	movq	%rax, 80(%rbx)
	leaq	344(%rsp), %rax
	movq	%rax, 88(%rbx)
	movq	%r9, 96(%rbx)
	movq	%r10, 104(%rbx)
	movq	%r11, 112(%rbx)
	leaq	112(%rsp), %r14
	leaq	96(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z19iterateScheme_part6PdS_S_S_S_S_S_S_S_S_S_S_ddd, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$272, %rsp                      # imm = 0x110
	.cfi_adjust_cfa_offset -272
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end5:
	.size	_Z34__device_stub__iterateScheme_part6PdS_S_S_S_S_S_S_S_S_S_S_ddd, .Lfunc_end5-_Z34__device_stub__iterateScheme_part6PdS_S_S_S_S_S_S_S_S_S_S_ddd
	.cfi_endproc
                                        # -- End function
	.globl	_Z34__device_stub__iterateScheme_part7PdS_S_S_S_S_S_S_S_S_S_S_ddd # -- Begin function _Z34__device_stub__iterateScheme_part7PdS_S_S_S_S_S_S_S_S_S_S_ddd
	.type	_Z34__device_stub__iterateScheme_part7PdS_S_S_S_S_S_S_S_S_S_S_ddd,@function
_Z34__device_stub__iterateScheme_part7PdS_S_S_S_S_S_S_S_S_S_S_ddd: # @_Z34__device_stub__iterateScheme_part7PdS_S_S_S_S_S_S_S_S_S_S_ddd
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$256, %rsp                      # imm = 0x100
	.cfi_def_cfa_offset 304
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	88(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	80(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	72(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	64(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	56(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	48(%rsp), %r8
	movq	%r9, (%r8)
	leaq	40(%rsp), %r9
	movsd	%xmm0, (%r9)
	leaq	32(%rsp), %r10
	movsd	%xmm1, (%r10)
	leaq	24(%rsp), %r11
	movsd	%xmm2, (%r11)
	leaq	128(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	304(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	312(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	320(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	328(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	336(%rsp), %rax
	movq	%rax, 80(%rbx)
	leaq	344(%rsp), %rax
	movq	%rax, 88(%rbx)
	movq	%r9, 96(%rbx)
	movq	%r10, 104(%rbx)
	movq	%r11, 112(%rbx)
	leaq	112(%rsp), %r14
	leaq	96(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z19iterateScheme_part7PdS_S_S_S_S_S_S_S_S_S_S_ddd, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$272, %rsp                      # imm = 0x110
	.cfi_adjust_cfa_offset -272
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end6:
	.size	_Z34__device_stub__iterateScheme_part7PdS_S_S_S_S_S_S_S_S_S_S_ddd, .Lfunc_end6-_Z34__device_stub__iterateScheme_part7PdS_S_S_S_S_S_S_S_S_S_S_ddd
	.cfi_endproc
                                        # -- End function
	.globl	_Z34__device_stub__iterateScheme_part8PdS_S_S_S_S_S_S_S_S_S_S_ddd # -- Begin function _Z34__device_stub__iterateScheme_part8PdS_S_S_S_S_S_S_S_S_S_S_ddd
	.type	_Z34__device_stub__iterateScheme_part8PdS_S_S_S_S_S_S_S_S_S_S_ddd,@function
_Z34__device_stub__iterateScheme_part8PdS_S_S_S_S_S_S_S_S_S_S_ddd: # @_Z34__device_stub__iterateScheme_part8PdS_S_S_S_S_S_S_S_S_S_S_ddd
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$256, %rsp                      # imm = 0x100
	.cfi_def_cfa_offset 304
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	88(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	80(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	72(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	64(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	56(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	48(%rsp), %r8
	movq	%r9, (%r8)
	leaq	40(%rsp), %r9
	movsd	%xmm0, (%r9)
	leaq	32(%rsp), %r10
	movsd	%xmm1, (%r10)
	leaq	24(%rsp), %r11
	movsd	%xmm2, (%r11)
	leaq	128(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	304(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	312(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	320(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	328(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	336(%rsp), %rax
	movq	%rax, 80(%rbx)
	leaq	344(%rsp), %rax
	movq	%rax, 88(%rbx)
	movq	%r9, 96(%rbx)
	movq	%r10, 104(%rbx)
	movq	%r11, 112(%rbx)
	leaq	112(%rsp), %r14
	leaq	96(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z19iterateScheme_part8PdS_S_S_S_S_S_S_S_S_S_S_ddd, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$272, %rsp                      # imm = 0x110
	.cfi_adjust_cfa_offset -272
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end7:
	.size	_Z34__device_stub__iterateScheme_part8PdS_S_S_S_S_S_S_S_S_S_S_ddd, .Lfunc_end7-_Z34__device_stub__iterateScheme_part8PdS_S_S_S_S_S_S_S_S_S_S_ddd
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0                          # -- Begin function _Z22BoundaryLayerThicknessv
.LCPI8_0:
	.quad	0x4014000000000000              # double 5
	.text
	.globl	_Z22BoundaryLayerThicknessv
	.type	_Z22BoundaryLayerThicknessv,@function
_Z22BoundaryLayerThicknessv:            # @_Z22BoundaryLayerThicknessv
	.cfi_startproc
# %bb.0:
	movsd	plateLength(%rip), %xmm2        # xmm2 = mem[0],zero
	mulsd	.LCPI8_0(%rip), %xmm2
	movsd	Re(%rip), %xmm0                 # xmm0 = mem[0],zero
	xorpd	%xmm1, %xmm1
	ucomisd	%xmm1, %xmm0
	jb	.LBB8_2
# %bb.1:
	sqrtsd	%xmm0, %xmm0
	jmp	.LBB8_3
.LBB8_2:                                # %call.sqrt
	pushq	%rax
	.cfi_def_cfa_offset 16
	movsd	%xmm2, (%rsp)                   # 8-byte Spill
	callq	sqrt
	movsd	(%rsp), %xmm2                   # 8-byte Reload
                                        # xmm2 = mem[0],zero
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB8_3:                                # %.split
	divsd	%xmm0, %xmm2
	movapd	%xmm2, %xmm0
	retq
.Lfunc_end8:
	.size	_Z22BoundaryLayerThicknessv, .Lfunc_end8-_Z22BoundaryLayerThicknessv
	.cfi_endproc
                                        # -- End function
	.globl	_Z9setupGridPdS_                # -- Begin function _Z9setupGridPdS_
	.type	_Z9setupGridPdS_,@function
_Z9setupGridPdS_:                       # @_Z9setupGridPdS_
	.cfi_startproc
# %bb.0:
	movl	jmax(%rip), %eax
	testl	%eax, %eax
	jle	.LBB9_3
# %bb.1:                                # %.lr.ph.preheader
	xorl	%ecx, %ecx
.LBB9_2:                                # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	xorps	%xmm0, %xmm0
	cvtsi2sd	%ecx, %xmm0
	mulsd	dx(%rip), %xmm0
	movsd	%xmm0, (%rdi,%rcx,8)
	incq	%rcx
	cmpq	%rcx, %rax
	jne	.LBB9_2
.LBB9_3:                                # %.preheader
	movl	kmax(%rip), %eax
	testl	%eax, %eax
	jle	.LBB9_6
# %bb.4:                                # %.lr.ph12.preheader
	xorl	%ecx, %ecx
.LBB9_5:                                # %.lr.ph12
                                        # =>This Inner Loop Header: Depth=1
	xorps	%xmm0, %xmm0
	cvtsi2sd	%ecx, %xmm0
	mulsd	dy(%rip), %xmm0
	movsd	%xmm0, (%rsi,%rcx,8)
	incq	%rcx
	cmpq	%rcx, %rax
	jne	.LBB9_5
.LBB9_6:                                # %._crit_edge
	retq
.Lfunc_end9:
	.size	_Z9setupGridPdS_, .Lfunc_end9-_Z9setupGridPdS_
	.cfi_endproc
                                        # -- End function
	.globl	_Z20initializePrimativesPdS_S_S_S_S_ # -- Begin function _Z20initializePrimativesPdS_S_S_S_S_
	.type	_Z20initializePrimativesPdS_S_S_S_S_,@function
_Z20initializePrimativesPdS_S_S_S_S_:   # @_Z20initializePrimativesPdS_S_S_S_S_
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%r9, -8(%rsp)                   # 8-byte Spill
	movq	%r8, -16(%rsp)                  # 8-byte Spill
	movq	%rcx, -24(%rsp)                 # 8-byte Spill
	movl	jmax(%rip), %ecx
	testl	%ecx, %ecx
	jle	.LBB10_6
# %bb.1:                                # %.preheader.lr.ph
	movl	kmax(%rip), %r10d
	movq	%r10, %r11
	shlq	$3, %r11
	xorl	%ebx, %ebx
	xorl	%r14d, %r14d
.LBB10_2:                               # %.preheader
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB10_4 Depth 2
	testl	%r10d, %r10d
	jle	.LBB10_5
# %bb.3:                                # %.lr.ph
                                        #   in Loop: Header=BB10_2 Depth=1
	movl	%ebx, %r8d
	movq	-8(%rsp), %rax                  # 8-byte Reload
	leaq	(%rax,%r8,8), %r15
	movq	-16(%rsp), %rax                 # 8-byte Reload
	leaq	(%rax,%r8,8), %r12
	movq	-24(%rsp), %rax                 # 8-byte Reload
	leaq	(%rax,%r8,8), %r13
	leaq	(%rdx,%r8,8), %rbp
	leaq	(%rsi,%r8,8), %rax
	leaq	(%rdi,%r8,8), %r9
	xorl	%r8d, %r8d
.LBB10_4:                               #   Parent Loop BB10_2 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movsd	u0(%rip), %xmm0                 # xmm0 = mem[0],zero
	movsd	%xmm0, (%r9,%r8)
	movsd	v0(%rip), %xmm0                 # xmm0 = mem[0],zero
	movsd	%xmm0, (%rax,%r8)
	movsd	p0(%rip), %xmm0                 # xmm0 = mem[0],zero
	movsd	%xmm0, (%rbp,%r8)
	movsd	T0(%rip), %xmm0                 # xmm0 = mem[0],zero
	movsd	%xmm0, (%r13,%r8)
	movsd	rho0(%rip), %xmm0               # xmm0 = mem[0],zero
	movsd	%xmm0, (%r12,%r8)
	movsd	e0(%rip), %xmm0                 # xmm0 = mem[0],zero
	movsd	%xmm0, (%r15,%r8)
	addq	$8, %r8
	cmpq	%r8, %r11
	jne	.LBB10_4
.LBB10_5:                               # %._crit_edge
                                        #   in Loop: Header=BB10_2 Depth=1
	incq	%r14
	addl	%r10d, %ebx
	cmpq	%rcx, %r14
	jne	.LBB10_2
.LBB10_6:                               # %._crit_edge25
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end10:
	.size	_Z20initializePrimativesPdS_S_S_S_S_, .Lfunc_end10-_Z20initializePrimativesPdS_S_S_S_S_
	.cfi_endproc
                                        # -- End function
	.globl	_Z18applyBC_UpperPlatePdS_S_S_  # -- Begin function _Z18applyBC_UpperPlatePdS_S_S_
	.type	_Z18applyBC_UpperPlatePdS_S_S_,@function
_Z18applyBC_UpperPlatePdS_S_S_:         # @_Z18applyBC_UpperPlatePdS_S_S_
	.cfi_startproc
# %bb.0:
	xorl	%eax, %eax
	movq	%rax, (%rdi)
	movq	%rax, (%rsi)
	movsd	p0(%rip), %xmm0                 # xmm0 = mem[0],zero
	movsd	%xmm0, (%rdx)
	movsd	T0(%rip), %xmm0                 # xmm0 = mem[0],zero
	movsd	%xmm0, (%rcx)
	movslq	kmax(%rip), %r10
	movl	%r10d, %r11d
	testq	%r10, %r10
	jle	.LBB11_3
# %bb.1:                                # %.lr.ph.preheader
	xorl	%eax, %eax
.LBB11_2:                               # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	movsd	u0(%rip), %xmm0                 # xmm0 = mem[0],zero
	movsd	%xmm0, (%rdi,%rax,8)
	movq	$0, (%rsi,%rax,8)
	movsd	p0(%rip), %xmm0                 # xmm0 = mem[0],zero
	movsd	%xmm0, (%rdx,%rax,8)
	movsd	T0(%rip), %xmm0                 # xmm0 = mem[0],zero
	movsd	%xmm0, (%rcx,%rax,8)
	incq	%rax
	cmpq	%rax, %r11
	jne	.LBB11_2
.LBB11_3:                               # %.preheader70
	movl	jmax(%rip), %r8d
	testl	%r8d, %r8d
	jle	.LBB11_6
# %bb.4:
	movl	%r10d, %eax
	movq	%r8, %r9
.LBB11_5:                               # %.lr.ph80
                                        # =>This Inner Loop Header: Depth=1
	movsd	u0(%rip), %xmm0                 # xmm0 = mem[0],zero
	cltq
	movsd	%xmm0, -8(%rdi,%rax,8)
	movq	$0, -8(%rsi,%rax,8)
	movsd	p0(%rip), %xmm0                 # xmm0 = mem[0],zero
	movsd	%xmm0, -8(%rdx,%rax,8)
	movsd	T0(%rip), %xmm0                 # xmm0 = mem[0],zero
	movsd	%xmm0, -8(%rcx,%rax,8)
	addl	%r10d, %eax
	decq	%r9
	jne	.LBB11_5
.LBB11_6:                               # %.preheader69
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%r10, -48(%rsp)                 # 8-byte Spill
	testl	%r10d, %r10d
	movq	%r11, -40(%rsp)                 # 8-byte Spill
	jle	.LBB11_9
# %bb.7:                                # %.lr.ph83
	leal	-2(%r8), %eax
	movq	-48(%rsp), %r11                 # 8-byte Reload
	imull	%r11d, %eax
	leal	-3(%r8), %r9d
	imull	%r11d, %r9d
	leal	-1(%r8), %r10d
	imull	%r11d, %r10d
	movslq	%eax, %r11
	movslq	%r9d, %rax
	movslq	%r10d, %r9
	leaq	(%rdi,%r9,8), %r10
	movq	%r10, -8(%rsp)                  # 8-byte Spill
	leaq	(%rsi,%r9,8), %r10
	movq	%r10, -16(%rsp)                 # 8-byte Spill
	leaq	(%rdx,%r9,8), %r10
	movq	%r10, -24(%rsp)                 # 8-byte Spill
	leaq	(%rcx,%r9,8), %r9
	movq	%r9, -32(%rsp)                  # 8-byte Spill
	leaq	(%rdi,%rax,8), %r15
	leaq	(%rsi,%rax,8), %r12
	leaq	(%rdx,%rax,8), %r13
	leaq	(%rcx,%rax,8), %rbp
	leaq	(%rdi,%r11,8), %rax
	leaq	(%rsi,%r11,8), %r10
	leaq	(%rdx,%r11,8), %r9
	leaq	(%rcx,%r11,8), %r11
	shlq	$3, -40(%rsp)                   # 8-byte Folded Spill
	xorl	%ebx, %ebx
.LBB11_8:                               # =>This Inner Loop Header: Depth=1
	movsd	(%rax,%rbx), %xmm0              # xmm0 = mem[0],zero
	addsd	%xmm0, %xmm0
	subsd	(%r15,%rbx), %xmm0
	movq	-8(%rsp), %r14                  # 8-byte Reload
	movsd	%xmm0, (%r14,%rbx)
	movsd	(%r10,%rbx), %xmm0              # xmm0 = mem[0],zero
	addsd	%xmm0, %xmm0
	subsd	(%r12,%rbx), %xmm0
	movq	-16(%rsp), %r14                 # 8-byte Reload
	movsd	%xmm0, (%r14,%rbx)
	movsd	(%r9,%rbx), %xmm0               # xmm0 = mem[0],zero
	addsd	%xmm0, %xmm0
	subsd	(%r13,%rbx), %xmm0
	movq	-24(%rsp), %r14                 # 8-byte Reload
	movsd	%xmm0, (%r14,%rbx)
	movsd	(%r11,%rbx), %xmm0              # xmm0 = mem[0],zero
	addsd	%xmm0, %xmm0
	subsd	(%rbp,%rbx), %xmm0
	movq	-32(%rsp), %r14                 # 8-byte Reload
	movsd	%xmm0, (%r14,%rbx)
	addq	$8, %rbx
	cmpq	%rbx, -40(%rsp)                 # 8-byte Folded Reload
	jne	.LBB11_8
.LBB11_9:                               # %.preheader
	testl	%r8d, %r8d
	movq	-48(%rsp), %r10                 # 8-byte Reload
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	.cfi_restore %rbx
	.cfi_restore %r12
	.cfi_restore %r13
	.cfi_restore %r14
	.cfi_restore %r15
	.cfi_restore %rbp
	jle	.LBB11_12
# %bb.10:                               # %.lr.ph85.preheader
	shlq	$3, %r10
	xorl	%eax, %eax
	xorl	%r9d, %r9d
.LBB11_11:                              # %.lr.ph85
                                        # =>This Inner Loop Header: Depth=1
	movq	%rax, (%rdi,%r9)
	movq	%rax, (%rsi,%r9)
	movsd	8(%rdx,%r9), %xmm0              # xmm0 = mem[0],zero
	addsd	%xmm0, %xmm0
	subsd	16(%rdx,%r9), %xmm0
	movsd	%xmm0, (%rdx,%r9)
	movsd	8(%rcx,%r9), %xmm0              # xmm0 = mem[0],zero
	movsd	%xmm0, (%rcx,%r9)
	addq	%r10, %r9
	decq	%r8
	jne	.LBB11_11
.LBB11_12:                              # %._crit_edge
	retq
.Lfunc_end11:
	.size	_Z18applyBC_UpperPlatePdS_S_S_, .Lfunc_end11-_Z18applyBC_UpperPlatePdS_S_S_
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0                          # -- Begin function _Z7calc_dtPdS_S_S_dd
.LCPI12_0:
	.quad	0xfff0000000000000              # double -Inf
.LCPI12_1:
	.quad	0x3ff8000000000000              # double 1.5
.LCPI12_2:
	.quad	0x405b800000000000              # double 110
.LCPI12_3:
	.quad	0x3ff0000000000000              # double 1
.LCPI12_4:
	.quad	0x3fe0000000000000              # double 0.5
.LCPI12_5:
	.quad	0x7ff0000000000000              # double +Inf
	.section	.rodata.cst16,"aM",@progbits,16
	.p2align	4, 0x0
.LCPI12_6:
	.quad	0x7fffffffffffffff              # double NaN
	.quad	0x7fffffffffffffff              # double NaN
	.text
	.globl	_Z7calc_dtPdS_S_S_dd
	.type	_Z7calc_dtPdS_S_S_dd,@function
_Z7calc_dtPdS_S_S_dd:                   # @_Z7calc_dtPdS_S_S_dd
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$72, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%rcx, %rbx
	movq	%rdx, %r14
	movq	%rsi, %r15
	movq	%rdi, %r12
	movl	jmax(%rip), %ecx
	testl	%ecx, %ecx
	movsd	%xmm1, 24(%rsp)                 # 8-byte Spill
	movsd	%xmm0, 16(%rsp)                 # 8-byte Spill
	jle	.LBB12_1
# %bb.2:                                # %.preheader64.preheader
	xorl	%r13d, %r13d
	movsd	.LCPI12_0(%rip), %xmm3          # xmm3 = mem[0],zero
	movl	kmax(%rip), %eax
	movsd	.LCPI12_1(%rip), %xmm4          # xmm4 = mem[0],zero
	movq	%r15, 56(%rsp)                  # 8-byte Spill
.LBB12_3:                               # %.preheader64
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB12_5 Depth 2
	testl	%eax, %eax
	jle	.LBB12_7
# %bb.4:                                # %.lr.ph.preheader
                                        #   in Loop: Header=BB12_3 Depth=1
	movsd	T0(%rip), %xmm1                 # xmm1 = mem[0],zero
	xorl	%ebp, %ebp
.LBB12_5:                               # %.lr.ph
                                        #   Parent Loop BB12_3 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movsd	%xmm3, 8(%rsp)                  # 8-byte Spill
	imull	%r13d, %eax
	movslq	%eax, %r15
	addq	%rbp, %r15
	movsd	(%r14,%r15,8), %xmm3            # xmm3 = mem[0],zero
	movsd	(%rbx,%r15,8), %xmm0            # xmm0 = mem[0],zero
	movsd	R(%rip), %xmm2                  # xmm2 = mem[0],zero
	mulsd	%xmm0, %xmm2
	divsd	%xmm2, %xmm3
	movsd	%xmm3, 32(%rsp)                 # 8-byte Spill
	movsd	mu0(%rip), %xmm2                # xmm2 = mem[0],zero
	movsd	%xmm2, (%rsp)                   # 8-byte Spill
	divsd	%xmm1, %xmm0
	movaps	%xmm4, %xmm1
	callq	pow
	movsd	.LCPI12_2(%rip), %xmm5          # xmm5 = mem[0],zero
	movsd	.LCPI12_1(%rip), %xmm4          # xmm4 = mem[0],zero
	movsd	T0(%rip), %xmm1                 # xmm1 = mem[0],zero
	mulsd	(%rsp), %xmm0                   # 8-byte Folded Reload
	movapd	%xmm1, %xmm2
	addsd	%xmm5, %xmm2
	movsd	(%rbx,%r15,8), %xmm3            # xmm3 = mem[0],zero
	mulsd	%xmm0, %xmm2
	addsd	%xmm5, %xmm3
	divsd	%xmm3, %xmm2
	movsd	gam(%rip), %xmm3                # xmm3 = mem[0],zero
	mulsd	%xmm2, %xmm3
	divsd	Pr(%rip), %xmm3
	mulsd	%xmm2, %xmm3
	divsd	32(%rsp), %xmm3                 # 8-byte Folded Reload
	maxsd	8(%rsp), %xmm3                  # 8-byte Folded Reload
	movl	kmax(%rip), %eax
	incq	%rbp
	cmpl	%eax, %ebp
	jl	.LBB12_5
# %bb.6:                                # %._crit_edge.loopexit
                                        #   in Loop: Header=BB12_3 Depth=1
	movl	jmax(%rip), %ecx
	movsd	24(%rsp), %xmm1                 # 8-byte Reload
                                        # xmm1 = mem[0],zero
	movsd	16(%rsp), %xmm0                 # 8-byte Reload
                                        # xmm0 = mem[0],zero
	movq	56(%rsp), %r15                  # 8-byte Reload
.LBB12_7:                               # %._crit_edge
                                        #   in Loop: Header=BB12_3 Depth=1
	incl	%r13d
	cmpl	%ecx, %r13d
	jl	.LBB12_3
# %bb.8:                                # %._crit_edge69.loopexit
	addsd	%xmm3, %xmm3
	movsd	%xmm3, (%rsp)                   # 8-byte Spill
	jmp	.LBB12_9
.LBB12_1:
	movsd	.LCPI12_0(%rip), %xmm2          # xmm2 = mem[0],zero
	movsd	%xmm2, (%rsp)                   # 8-byte Spill
.LBB12_9:                               # %._crit_edge69
	mulsd	%xmm0, %xmm0
	movsd	.LCPI12_3(%rip), %xmm4          # xmm4 = mem[0],zero
	movapd	%xmm4, %xmm3
	divsd	%xmm0, %xmm3
	movapd	%xmm1, %xmm2
	mulsd	%xmm1, %xmm2
	movapd	%xmm4, %xmm0
	divsd	%xmm2, %xmm0
	addsd	%xmm3, %xmm0
	movsd	.LCPI12_4(%rip), %xmm1          # xmm1 = mem[0],zero
	callq	pow
	movl	jmax(%rip), %ecx
	testl	%ecx, %ecx
	jle	.LBB12_10
# %bb.11:                               # %.preheader.lr.ph
	movapd	%xmm0, %xmm3
	mulsd	%xmm3, %xmm0
	movsd	(%rsp), %xmm2                   # 8-byte Reload
                                        # xmm2 = mem[0],zero
	mulsd	%xmm0, %xmm2
	movsd	.LCPI12_5(%rip), %xmm0          # xmm0 = mem[0],zero
	xorl	%r13d, %r13d
	movl	kmax(%rip), %eax
	movapd	.LCPI12_6(%rip), %xmm4          # xmm4 = [NaN,NaN]
	movsd	.LCPI12_4(%rip), %xmm5          # xmm5 = mem[0],zero
	movsd	%xmm2, (%rsp)                   # 8-byte Spill
	movsd	%xmm3, 64(%rsp)                 # 8-byte Spill
.LBB12_12:                              # %.preheader
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB12_14 Depth 2
	testl	%eax, %eax
	jle	.LBB12_16
# %bb.13:                               # %.lr.ph73.preheader
                                        #   in Loop: Header=BB12_12 Depth=1
	xorl	%ebp, %ebp
.LBB12_14:                              # %.lr.ph73
                                        #   Parent Loop BB12_12 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movsd	%xmm0, 8(%rsp)                  # 8-byte Spill
	imull	%r13d, %eax
	cltq
	addq	%rbp, %rax
	movsd	(%r14,%rax,8), %xmm0            # xmm0 = mem[0],zero
	movsd	R(%rip), %xmm1                  # xmm1 = mem[0],zero
	mulsd	(%rbx,%rax,8), %xmm1
	movapd	%xmm0, %xmm2
	divsd	%xmm1, %xmm2
	movsd	(%r12,%rax,8), %xmm1            # xmm1 = mem[0],zero
	andpd	%xmm4, %xmm1
	divsd	16(%rsp), %xmm1                 # 8-byte Folded Reload
	movsd	(%r15,%rax,8), %xmm3            # xmm3 = mem[0],zero
	andpd	%xmm4, %xmm3
	divsd	24(%rsp), %xmm3                 # 8-byte Folded Reload
	addsd	%xmm1, %xmm3
	movapd	%xmm3, 32(%rsp)                 # 16-byte Spill
	mulsd	gam(%rip), %xmm0
	divsd	%xmm2, %xmm0
	movapd	%xmm5, %xmm1
	callq	pow
	movsd	.LCPI12_4(%rip), %xmm5          # xmm5 = mem[0],zero
	movapd	.LCPI12_6(%rip), %xmm4          # xmm4 = [NaN,NaN]
	movsd	64(%rsp), %xmm3                 # 8-byte Reload
                                        # xmm3 = mem[0],zero
	movsd	(%rsp), %xmm2                   # 8-byte Reload
                                        # xmm2 = mem[0],zero
	movapd	%xmm0, %xmm1
	mulsd	%xmm3, %xmm1
	addsd	32(%rsp), %xmm1                 # 16-byte Folded Reload
	addsd	%xmm2, %xmm1
	movsd	.LCPI12_3(%rip), %xmm0          # xmm0 = mem[0],zero
	divsd	%xmm1, %xmm0
	mulsd	CFL(%rip), %xmm0
	minsd	8(%rsp), %xmm0                  # 8-byte Folded Reload
	movl	kmax(%rip), %eax
	incq	%rbp
	cmpl	%eax, %ebp
	jl	.LBB12_14
# %bb.15:                               # %._crit_edge74.loopexit
                                        #   in Loop: Header=BB12_12 Depth=1
	movl	jmax(%rip), %ecx
.LBB12_16:                              # %._crit_edge74
                                        #   in Loop: Header=BB12_12 Depth=1
	incl	%r13d
	cmpl	%ecx, %r13d
	jl	.LBB12_12
	jmp	.LBB12_17
.LBB12_10:
	movsd	.LCPI12_5(%rip), %xmm0          # xmm0 = mem[0],zero
.LBB12_17:                              # %._crit_edge78
	addq	$72, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end12:
	.size	_Z7calc_dtPdS_S_S_dd, .Lfunc_end12-_Z7calc_dtPdS_S_S_dd
	.cfi_endproc
                                        # -- End function
	.globl	_Z10arrayToCSVPdPci             # -- Begin function _Z10arrayToCSVPdPci
	.type	_Z10arrayToCSVPdPci,@function
_Z10arrayToCSVPdPci:                    # @_Z10arrayToCSVPdPci
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	pushq	%rax
	.cfi_def_cfa_offset 64
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%edx, %ebx
	movq	%rsi, %rax
	movq	%rdi, %r14
	movl	$.L.str, %esi
	movq	%rax, %rdi
	callq	fopen
	testl	%ebx, %ebx
	jle	.LBB13_11
# %bb.1:                                # %.preheader21.lr.ph
	movq	%rax, %r15
	movq	%rbx, %r12
	leal	-1(%rbx), %eax
	movl	%eax, 4(%rsp)                   # 4-byte Spill
	movl	jmax(%rip), %eax
	xorl	%r13d, %r13d
.LBB13_2:                               # %.preheader21
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB13_4 Depth 2
                                        #       Child Loop BB13_6 Depth 3
	testl	%eax, %eax
	jle	.LBB13_8
# %bb.3:                                # %.preheader.preheader
                                        #   in Loop: Header=BB13_2 Depth=1
	xorl	%ebp, %ebp
.LBB13_4:                               # %.preheader
                                        #   Parent Loop BB13_2 Depth=1
                                        # =>  This Loop Header: Depth=2
                                        #       Child Loop BB13_6 Depth 3
	movl	kmax(%rip), %eax
	testl	%eax, %eax
	jle	.LBB13_7
# %bb.5:                                # %.lr.ph.preheader
                                        #   in Loop: Header=BB13_4 Depth=2
	xorl	%ebx, %ebx
.LBB13_6:                               # %.lr.ph
                                        #   Parent Loop BB13_2 Depth=1
                                        #     Parent Loop BB13_4 Depth=2
                                        # =>    This Inner Loop Header: Depth=3
	movl	jmax(%rip), %ecx
	imull	%r13d, %ecx
	addl	%ebp, %ecx
	imull	%eax, %ecx
	movslq	%ecx, %rax
	addq	%rbx, %rax
	movsd	(%r14,%rax,8), %xmm0            # xmm0 = mem[0],zero
	movl	$.L.str.6, %esi
	movq	%r15, %rdi
	movb	$1, %al
	callq	fprintf
	movl	kmax(%rip), %eax
	incq	%rbx
	cmpl	%eax, %ebx
	jl	.LBB13_6
.LBB13_7:                               # %._crit_edge
                                        #   in Loop: Header=BB13_4 Depth=2
	movl	$10, %edi
	movq	%r15, %rsi
	callq	fputc@PLT
	incl	%ebp
	movl	jmax(%rip), %eax
	cmpl	%eax, %ebp
	jl	.LBB13_4
.LBB13_8:                               # %._crit_edge24
                                        #   in Loop: Header=BB13_2 Depth=1
	leal	1(%r13), %ebp
	cmpl	4(%rsp), %r13d                  # 4-byte Folded Reload
	jge	.LBB13_10
# %bb.9:                                #   in Loop: Header=BB13_2 Depth=1
	movl	$.L.str.8, %esi
	movq	%r15, %rdi
	movl	%ebp, %edx
	xorl	%eax, %eax
	callq	fprintf
	movl	jmax(%rip), %eax
.LBB13_10:                              # %._crit_edge24._crit_edge
                                        #   in Loop: Header=BB13_2 Depth=1
	movl	%ebp, %r13d
	cmpl	%r12d, %ebp
	jne	.LBB13_2
.LBB13_11:                              # %._crit_edge26
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end13:
	.size	_Z10arrayToCSVPdPci, .Lfunc_end13-_Z10arrayToCSVPdPci
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$184, %rsp
	.cfi_def_cfa_offset 240
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movslq	jmax(%rip), %rbx
	movq	%rbx, %rdi
	shlq	$3, %rdi
	callq	malloc
	movq	%rax, 144(%rsp)                 # 8-byte Spill
	movslq	kmax(%rip), %r14
	movq	%r14, %rdi
	shlq	$3, %rdi
	callq	malloc
	movq	%rax, 136(%rsp)                 # 8-byte Spill
	imull	%ebx, %r14d
	movslq	%r14d, %rax
	movq	%rax, 40(%rsp)                  # 8-byte Spill
	leaq	(,%rax,8), %rbx
	movq	%rbx, %rdi
	callq	malloc
	movq	%rax, %r14
	movq	%rbx, %rdi
	callq	malloc
	movq	%rax, %r13
	movq	%rbx, %rdi
	callq	malloc
	movq	%rax, %rbp
	movq	%rbx, %rdi
	callq	malloc
	movq	%rax, %r15
	movq	%rbx, %rdi
	callq	malloc
	movq	%rax, %r12
	movq	%rax, 128(%rsp)                 # 8-byte Spill
	movq	%rbx, %rdi
	callq	malloc
	movq	%rax, 120(%rsp)                 # 8-byte Spill
	movq	%r14, %rdi
	movq	%r13, %rsi
	movq	%rbp, %rdx
	movq	%r15, %rcx
	movq	%r12, %r8
	movq	%rax, %r9
	callq	_Z20initializePrimativesPdS_S_S_S_S_
	movq	%r14, %rdi
	movq	%r14, %r12
	movq	%r13, %rsi
	movq	%rbp, %rdx
	movq	%r15, %rcx
	callq	_Z18applyBC_UpperPlatePdS_S_S_
	movq	40(%rsp), %rax                  # 8-byte Reload
	shll	$2, %eax
	movslq	%eax, %r14
	shlq	$3, %r14
	movq	%r14, %rdi
	callq	malloc
	movq	%rax, 168(%rsp)                 # 8-byte Spill
	movq	%r14, %rdi
	callq	malloc
	movq	%rax, 112(%rsp)                 # 8-byte Spill
	movq	%r14, %rdi
	callq	malloc
	movq	%rax, 160(%rsp)                 # 8-byte Spill
	leaq	104(%rsp), %r14
	movq	%r14, %rdi
	movq	%rbx, %rsi
	callq	hipMalloc
	movslq	jmax(%rip), %rax
	movslq	kmax(%rip), %rsi
	imulq	%rax, %rsi
	shlq	$3, %rsi
	leaq	96(%rsp), %rbx
	movq	%rbx, %rdi
	callq	hipMalloc
	movslq	jmax(%rip), %rax
	movslq	kmax(%rip), %rsi
	imulq	%rax, %rsi
	shlq	$3, %rsi
	leaq	32(%rsp), %rdi
	callq	hipMalloc
	movslq	jmax(%rip), %rax
	movslq	kmax(%rip), %rsi
	imulq	%rax, %rsi
	shlq	$3, %rsi
	leaq	24(%rsp), %rdi
	callq	hipMalloc
	movslq	jmax(%rip), %rax
	movslq	kmax(%rip), %rsi
	imulq	%rax, %rsi
	shlq	$3, %rsi
	leaq	16(%rsp), %rdi
	callq	hipMalloc
	movslq	jmax(%rip), %rax
	movslq	kmax(%rip), %rsi
	imulq	%rax, %rsi
	shlq	$3, %rsi
	leaq	8(%rsp), %rdi
	callq	hipMalloc
	movslq	jmax(%rip), %rax
	movslq	kmax(%rip), %rsi
	imulq	%rax, %rsi
	shlq	$3, %rsi
	leaq	80(%rsp), %rdi
	callq	hipMalloc
	movslq	jmax(%rip), %rax
	movslq	kmax(%rip), %rsi
	imulq	%rax, %rsi
	shlq	$3, %rsi
	leaq	72(%rsp), %rdi
	callq	hipMalloc
	movslq	jmax(%rip), %rax
	movslq	kmax(%rip), %rsi
	imulq	%rax, %rsi
	shlq	$5, %rsi
	leaq	64(%rsp), %rdi
	callq	hipMalloc
	movslq	jmax(%rip), %rax
	movslq	kmax(%rip), %rsi
	imulq	%rax, %rsi
	shlq	$5, %rsi
	leaq	88(%rsp), %rdi
	callq	hipMalloc
	movslq	jmax(%rip), %rax
	movslq	kmax(%rip), %rsi
	imulq	%rax, %rsi
	shlq	$5, %rsi
	leaq	56(%rsp), %rdi
	callq	hipMalloc
	movslq	jmax(%rip), %rax
	movslq	kmax(%rip), %rsi
	imulq	%rax, %rsi
	shlq	$5, %rsi
	leaq	48(%rsp), %rdi
	callq	hipMalloc
	movq	(%r14), %rdi
	movslq	jmax(%rip), %rax
	movslq	kmax(%rip), %rdx
	imulq	%rax, %rdx
	shlq	$3, %rdx
	movl	$1, %r14d
	movq	144(%rsp), %rsi                 # 8-byte Reload
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%rbx), %rdi
	movslq	jmax(%rip), %rax
	movslq	kmax(%rip), %rdx
	imulq	%rax, %rdx
	shlq	$3, %rdx
	movq	136(%rsp), %rsi                 # 8-byte Reload
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	32(%rsp), %rax
	movq	(%rax), %rdi
	movslq	jmax(%rip), %rax
	movslq	kmax(%rip), %rdx
	imulq	%rax, %rdx
	shlq	$3, %rdx
	movq	%r12, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	24(%rsp), %rax
	movq	(%rax), %rdi
	movslq	jmax(%rip), %rax
	movslq	kmax(%rip), %rdx
	imulq	%rax, %rdx
	shlq	$3, %rdx
	movq	%r13, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	16(%rsp), %rax
	movq	(%rax), %rdi
	movslq	jmax(%rip), %rax
	movslq	kmax(%rip), %rdx
	imulq	%rax, %rdx
	shlq	$3, %rdx
	movq	%rbp, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	8(%rsp), %rax
	movq	(%rax), %rdi
	movslq	jmax(%rip), %rax
	movslq	kmax(%rip), %rdx
	imulq	%rax, %rdx
	shlq	$3, %rdx
	movq	%r15, 152(%rsp)                 # 8-byte Spill
	movq	%r15, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	80(%rsp), %rax
	movq	(%rax), %rdi
	movslq	jmax(%rip), %rax
	movslq	kmax(%rip), %rdx
	imulq	%rax, %rdx
	shlq	$3, %rdx
	movq	128(%rsp), %rsi                 # 8-byte Reload
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	72(%rsp), %rax
	movq	(%rax), %rdi
	movslq	jmax(%rip), %rax
	movslq	kmax(%rip), %rdx
	imulq	%rax, %rdx
	shlq	$3, %rdx
	movq	120(%rsp), %rsi                 # 8-byte Reload
	movl	$1, %ecx
	callq	hipMemcpy
	testl	%eax, %eax
	jne	.LBB14_53
# %bb.1:                                # %_Z9gpuAssert10hipError_tPKcib.exit
	movl	jmax(%rip), %eax
	shrl	$4, %eax
	movl	kmax(%rip), %ecx
	shrl	$4, %ecx
	incl	%ecx
	shlq	$32, %rcx
	leaq	(%rax,%rcx), %r15
	incq	%r15
	movq	152(%rsp), %rbx                 # 8-byte Reload
	movq	%rbp, 176(%rsp)                 # 8-byte Spill
.LBB14_2:                               # =>This Inner Loop Header: Depth=1
	movl	$.L.str.10, %edi
	movl	%r14d, %esi
	movl	$1000, %edx                     # imm = 0x3E8
	xorl	%eax, %eax
	callq	printf
	movsd	dx(%rip), %xmm0                 # xmm0 = mem[0],zero
	movsd	dy(%rip), %xmm1                 # xmm1 = mem[0],zero
	movq	%r13, %rsi
	movq	%r12, %r13
	movq	%r12, %rdi
	movq	%rbp, %rdx
	movq	%rsi, %rbp
	movq	%rbx, %rcx
	callq	_Z7calc_dtPdS_S_S_dd
	movsd	%xmm0, 40(%rsp)                 # 8-byte Spill
	movq	%r15, %rdi
	movl	$1, %esi
	movabsq	$68719476752, %rbx              # imm = 0x1000000010
	movq	%rbx, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB14_4
# %bb.3:                                #   in Loop: Header=BB14_2 Depth=1
	movq	104(%rsp), %rdi
	movq	96(%rsp), %rsi
	movq	32(%rsp), %rdx
	movq	24(%rsp), %rcx
	movq	16(%rsp), %r8
	movq	8(%rsp), %r9
	movsd	dx(%rip), %xmm0                 # xmm0 = mem[0],zero
	movsd	dy(%rip), %xmm1                 # xmm1 = mem[0],zero
	movsd	40(%rsp), %xmm2                 # 8-byte Reload
                                        # xmm2 = mem[0],zero
	pushq	48(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	64(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	104(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	88(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	104(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	120(%rsp)
	.cfi_adjust_cfa_offset 8
	callq	_Z34__device_stub__iterateScheme_part1PdS_S_S_S_S_S_S_S_S_S_S_ddd
	addq	$48, %rsp
	.cfi_adjust_cfa_offset -48
.LBB14_4:                               #   in Loop: Header=BB14_2 Depth=1
	callq	hipPeekAtLastError
	testl	%eax, %eax
	jne	.LBB14_5
# %bb.7:                                # %_Z9gpuAssert10hipError_tPKcib.exit130
                                        #   in Loop: Header=BB14_2 Depth=1
	callq	hipDeviceSynchronize
	testl	%eax, %eax
	jne	.LBB14_8
# %bb.9:                                # %_Z9gpuAssert10hipError_tPKcib.exit132
                                        #   in Loop: Header=BB14_2 Depth=1
	movq	%r15, %rdi
	movl	$1, %esi
	movq	%rbx, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB14_11
# %bb.10:                               #   in Loop: Header=BB14_2 Depth=1
	movq	104(%rsp), %rdi
	movq	96(%rsp), %rsi
	movq	32(%rsp), %rdx
	movq	24(%rsp), %rcx
	movq	16(%rsp), %r8
	movq	8(%rsp), %r9
	movsd	dx(%rip), %xmm0                 # xmm0 = mem[0],zero
	movsd	dy(%rip), %xmm1                 # xmm1 = mem[0],zero
	movsd	40(%rsp), %xmm2                 # 8-byte Reload
                                        # xmm2 = mem[0],zero
	pushq	48(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	64(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	104(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	88(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	104(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	120(%rsp)
	.cfi_adjust_cfa_offset 8
	callq	_Z34__device_stub__iterateScheme_part2PdS_S_S_S_S_S_S_S_S_S_S_ddd
	addq	$48, %rsp
	.cfi_adjust_cfa_offset -48
.LBB14_11:                              #   in Loop: Header=BB14_2 Depth=1
	callq	hipPeekAtLastError
	testl	%eax, %eax
	jne	.LBB14_12
# %bb.13:                               # %_Z9gpuAssert10hipError_tPKcib.exit134
                                        #   in Loop: Header=BB14_2 Depth=1
	callq	hipDeviceSynchronize
	testl	%eax, %eax
	jne	.LBB14_14
# %bb.15:                               # %_Z9gpuAssert10hipError_tPKcib.exit136
                                        #   in Loop: Header=BB14_2 Depth=1
	movq	%r15, %rdi
	movl	$1, %esi
	movq	%rbx, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB14_17
# %bb.16:                               #   in Loop: Header=BB14_2 Depth=1
	movq	104(%rsp), %rdi
	movq	96(%rsp), %rsi
	movq	32(%rsp), %rdx
	movq	24(%rsp), %rcx
	movq	16(%rsp), %r8
	movq	8(%rsp), %r9
	movsd	dx(%rip), %xmm0                 # xmm0 = mem[0],zero
	movsd	dy(%rip), %xmm1                 # xmm1 = mem[0],zero
	movsd	40(%rsp), %xmm2                 # 8-byte Reload
                                        # xmm2 = mem[0],zero
	pushq	48(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	64(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	104(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	88(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	104(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	120(%rsp)
	.cfi_adjust_cfa_offset 8
	callq	_Z34__device_stub__iterateScheme_part3PdS_S_S_S_S_S_S_S_S_S_S_ddd
	addq	$48, %rsp
	.cfi_adjust_cfa_offset -48
.LBB14_17:                              #   in Loop: Header=BB14_2 Depth=1
	callq	hipPeekAtLastError
	testl	%eax, %eax
	jne	.LBB14_18
# %bb.19:                               # %_Z9gpuAssert10hipError_tPKcib.exit138
                                        #   in Loop: Header=BB14_2 Depth=1
	callq	hipDeviceSynchronize
	testl	%eax, %eax
	jne	.LBB14_20
# %bb.21:                               # %_Z9gpuAssert10hipError_tPKcib.exit140
                                        #   in Loop: Header=BB14_2 Depth=1
	movq	%r15, %rdi
	movl	$1, %esi
	movq	%rbx, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB14_23
# %bb.22:                               #   in Loop: Header=BB14_2 Depth=1
	movq	104(%rsp), %rdi
	movq	96(%rsp), %rsi
	movq	32(%rsp), %rdx
	movq	24(%rsp), %rcx
	movq	16(%rsp), %r8
	movq	8(%rsp), %r9
	movsd	dx(%rip), %xmm0                 # xmm0 = mem[0],zero
	movsd	dy(%rip), %xmm1                 # xmm1 = mem[0],zero
	movsd	40(%rsp), %xmm2                 # 8-byte Reload
                                        # xmm2 = mem[0],zero
	pushq	48(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	64(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	104(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	88(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	104(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	120(%rsp)
	.cfi_adjust_cfa_offset 8
	callq	_Z34__device_stub__iterateScheme_part4PdS_S_S_S_S_S_S_S_S_S_S_ddd
	addq	$48, %rsp
	.cfi_adjust_cfa_offset -48
.LBB14_23:                              #   in Loop: Header=BB14_2 Depth=1
	callq	hipPeekAtLastError
	testl	%eax, %eax
	jne	.LBB14_24
# %bb.25:                               # %_Z9gpuAssert10hipError_tPKcib.exit142
                                        #   in Loop: Header=BB14_2 Depth=1
	callq	hipDeviceSynchronize
	testl	%eax, %eax
	jne	.LBB14_26
# %bb.27:                               # %_Z9gpuAssert10hipError_tPKcib.exit144
                                        #   in Loop: Header=BB14_2 Depth=1
	movq	%r15, %rdi
	movl	$1, %esi
	movq	%rbx, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB14_29
# %bb.28:                               #   in Loop: Header=BB14_2 Depth=1
	movq	104(%rsp), %rdi
	movq	96(%rsp), %rsi
	movq	32(%rsp), %rdx
	movq	24(%rsp), %rcx
	movq	16(%rsp), %r8
	movq	8(%rsp), %r9
	movsd	dx(%rip), %xmm0                 # xmm0 = mem[0],zero
	movsd	dy(%rip), %xmm1                 # xmm1 = mem[0],zero
	movsd	40(%rsp), %xmm2                 # 8-byte Reload
                                        # xmm2 = mem[0],zero
	pushq	48(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	64(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	104(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	88(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	104(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	120(%rsp)
	.cfi_adjust_cfa_offset 8
	callq	_Z34__device_stub__iterateScheme_part5PdS_S_S_S_S_S_S_S_S_S_S_ddd
	addq	$48, %rsp
	.cfi_adjust_cfa_offset -48
.LBB14_29:                              #   in Loop: Header=BB14_2 Depth=1
	callq	hipPeekAtLastError
	testl	%eax, %eax
	jne	.LBB14_30
# %bb.31:                               # %_Z9gpuAssert10hipError_tPKcib.exit146
                                        #   in Loop: Header=BB14_2 Depth=1
	callq	hipDeviceSynchronize
	testl	%eax, %eax
	jne	.LBB14_32
# %bb.33:                               # %_Z9gpuAssert10hipError_tPKcib.exit148
                                        #   in Loop: Header=BB14_2 Depth=1
	movq	%r15, %rdi
	movl	$1, %esi
	movq	%rbx, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB14_35
# %bb.34:                               #   in Loop: Header=BB14_2 Depth=1
	movq	104(%rsp), %rdi
	movq	96(%rsp), %rsi
	movq	32(%rsp), %rdx
	movq	24(%rsp), %rcx
	movq	16(%rsp), %r8
	movq	8(%rsp), %r9
	movsd	dx(%rip), %xmm0                 # xmm0 = mem[0],zero
	movsd	dy(%rip), %xmm1                 # xmm1 = mem[0],zero
	movsd	40(%rsp), %xmm2                 # 8-byte Reload
                                        # xmm2 = mem[0],zero
	pushq	48(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	64(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	104(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	88(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	104(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	120(%rsp)
	.cfi_adjust_cfa_offset 8
	callq	_Z34__device_stub__iterateScheme_part6PdS_S_S_S_S_S_S_S_S_S_S_ddd
	addq	$48, %rsp
	.cfi_adjust_cfa_offset -48
.LBB14_35:                              #   in Loop: Header=BB14_2 Depth=1
	callq	hipPeekAtLastError
	testl	%eax, %eax
	jne	.LBB14_36
# %bb.37:                               # %_Z9gpuAssert10hipError_tPKcib.exit150
                                        #   in Loop: Header=BB14_2 Depth=1
	callq	hipDeviceSynchronize
	testl	%eax, %eax
	jne	.LBB14_38
# %bb.39:                               # %_Z9gpuAssert10hipError_tPKcib.exit152
                                        #   in Loop: Header=BB14_2 Depth=1
	movq	%r15, %rdi
	movl	$1, %esi
	movq	%rbx, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB14_41
# %bb.40:                               #   in Loop: Header=BB14_2 Depth=1
	movq	104(%rsp), %rdi
	movq	96(%rsp), %rsi
	movq	32(%rsp), %rdx
	movq	24(%rsp), %rcx
	movq	16(%rsp), %r8
	movq	8(%rsp), %r9
	movsd	dx(%rip), %xmm0                 # xmm0 = mem[0],zero
	movsd	dy(%rip), %xmm1                 # xmm1 = mem[0],zero
	movsd	40(%rsp), %xmm2                 # 8-byte Reload
                                        # xmm2 = mem[0],zero
	pushq	48(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	64(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	104(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	88(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	104(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	120(%rsp)
	.cfi_adjust_cfa_offset 8
	callq	_Z34__device_stub__iterateScheme_part7PdS_S_S_S_S_S_S_S_S_S_S_ddd
	addq	$48, %rsp
	.cfi_adjust_cfa_offset -48
.LBB14_41:                              #   in Loop: Header=BB14_2 Depth=1
	callq	hipPeekAtLastError
	testl	%eax, %eax
	jne	.LBB14_42
# %bb.43:                               # %_Z9gpuAssert10hipError_tPKcib.exit154
                                        #   in Loop: Header=BB14_2 Depth=1
	callq	hipDeviceSynchronize
	testl	%eax, %eax
	jne	.LBB14_44
# %bb.45:                               # %_Z9gpuAssert10hipError_tPKcib.exit156
                                        #   in Loop: Header=BB14_2 Depth=1
	movq	%r15, %rdi
	movl	$1, %esi
	movq	%rbx, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB14_47
# %bb.46:                               #   in Loop: Header=BB14_2 Depth=1
	movq	104(%rsp), %rdi
	movq	96(%rsp), %rsi
	movq	32(%rsp), %rdx
	movq	24(%rsp), %rcx
	movq	16(%rsp), %r8
	movq	8(%rsp), %r9
	movsd	dx(%rip), %xmm0                 # xmm0 = mem[0],zero
	movsd	dy(%rip), %xmm1                 # xmm1 = mem[0],zero
	movsd	40(%rsp), %xmm2                 # 8-byte Reload
                                        # xmm2 = mem[0],zero
	pushq	48(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	64(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	104(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	88(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	104(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	120(%rsp)
	.cfi_adjust_cfa_offset 8
	callq	_Z34__device_stub__iterateScheme_part8PdS_S_S_S_S_S_S_S_S_S_S_ddd
	addq	$48, %rsp
	.cfi_adjust_cfa_offset -48
.LBB14_47:                              #   in Loop: Header=BB14_2 Depth=1
	callq	hipPeekAtLastError
	testl	%eax, %eax
	jne	.LBB14_48
# %bb.49:                               # %_Z9gpuAssert10hipError_tPKcib.exit158
                                        #   in Loop: Header=BB14_2 Depth=1
	callq	hipDeviceSynchronize
	testl	%eax, %eax
	jne	.LBB14_50
# %bb.51:                               # %_Z9gpuAssert10hipError_tPKcib.exit160
                                        #   in Loop: Header=BB14_2 Depth=1
	movq	32(%rsp), %rsi
	movslq	jmax(%rip), %rax
	movslq	kmax(%rip), %rdx
	imulq	%rax, %rdx
	shlq	$3, %rdx
	movq	%r13, %r12
	movq	%r13, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movq	24(%rsp), %rsi
	movslq	jmax(%rip), %rax
	movslq	kmax(%rip), %rdx
	imulq	%rax, %rdx
	shlq	$3, %rdx
	movq	%rbp, %r13
	movq	%rbp, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movq	16(%rsp), %rsi
	movslq	jmax(%rip), %rax
	movslq	kmax(%rip), %rdx
	imulq	%rax, %rdx
	shlq	$3, %rdx
	movq	176(%rsp), %rbp                 # 8-byte Reload
	movq	%rbp, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movq	8(%rsp), %rsi
	movslq	jmax(%rip), %rax
	movslq	kmax(%rip), %rdx
	imulq	%rax, %rdx
	shlq	$3, %rdx
	movq	152(%rsp), %rbx                 # 8-byte Reload
	movq	%rbx, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	incl	%r14d
	cmpl	$1001, %r14d                    # imm = 0x3E9
	jne	.LBB14_2
# %bb.52:
	movq	56(%rsp), %rsi
	movslq	jmax(%rip), %rax
	movslq	kmax(%rip), %rdx
	imulq	%rax, %rdx
	shlq	$5, %rdx
	movq	112(%rsp), %rdi                 # 8-byte Reload
	movl	$2, %ecx
	callq	hipMemcpy
	movq	48(%rsp), %rsi
	movslq	jmax(%rip), %rax
	movslq	kmax(%rip), %rdx
	imulq	%rax, %rdx
	shlq	$5, %rdx
	movq	160(%rsp), %r14                 # 8-byte Reload
	movq	%r14, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movq	64(%rsp), %rsi
	movslq	jmax(%rip), %rax
	movslq	kmax(%rip), %rdx
	imulq	%rax, %rdx
	shlq	$5, %rdx
	movq	168(%rsp), %r15                 # 8-byte Reload
	movq	%r15, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movl	$.L.str.11, %esi
	movq	%r12, %rdi
	movl	$1, %edx
	callq	_Z10arrayToCSVPdPci
	movl	$.L.str.12, %esi
	movq	%r13, %rdi
	movl	$1, %edx
	callq	_Z10arrayToCSVPdPci
	movl	$.L.str.13, %esi
	movq	%rbp, %rdi
	movl	$1, %edx
	callq	_Z10arrayToCSVPdPci
	movl	$.L.str.14, %esi
	movq	%rbx, %rdi
	movl	$1, %edx
	callq	_Z10arrayToCSVPdPci
	movl	$.L.str.15, %esi
	movq	112(%rsp), %rdi                 # 8-byte Reload
	movl	$4, %edx
	callq	_Z10arrayToCSVPdPci
	movl	$.L.str.16, %esi
	movq	%r14, %rdi
	movl	$4, %edx
	callq	_Z10arrayToCSVPdPci
	movl	$.L.str.17, %esi
	movq	%r15, %rdi
	movl	$4, %edx
	callq	_Z10arrayToCSVPdPci
	movq	144(%rsp), %rdi                 # 8-byte Reload
	callq	free
	movq	136(%rsp), %rdi                 # 8-byte Reload
	callq	free
	movq	%r12, %rdi
	callq	free
	movq	%r13, %rdi
	callq	free
	movq	%rbp, %rdi
	callq	free
	movq	%rbx, %rdi
	callq	free
	movq	128(%rsp), %rdi                 # 8-byte Reload
	callq	free
	movq	120(%rsp), %rdi                 # 8-byte Reload
	callq	free
	movq	%r15, %rdi
	callq	free
	movq	112(%rsp), %rdi                 # 8-byte Reload
	callq	free
	movq	%r14, %rdi
	callq	free
	movq	104(%rsp), %rdi
	callq	hipFree
	movq	96(%rsp), %rdi
	callq	hipFree
	movq	32(%rsp), %rdi
	callq	hipFree
	movq	24(%rsp), %rdi
	callq	hipFree
	movq	16(%rsp), %rdi
	callq	hipFree
	movq	8(%rsp), %rdi
	callq	hipFree
	movq	80(%rsp), %rdi
	callq	hipFree
	movq	72(%rsp), %rdi
	callq	hipFree
	movq	64(%rsp), %rdi
	callq	hipFree
	movq	88(%rsp), %rdi
	callq	hipFree
	movq	56(%rsp), %rdi
	callq	hipFree
	movq	48(%rsp), %rdi
	callq	hipFree
	movl	$.Lstr, %edi
	callq	puts@PLT
	xorl	%eax, %eax
	addq	$184, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB14_50:
	.cfi_def_cfa_offset 240
	movl	%eax, %r12d
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.19, %esi
	movl	$.L.str.9, %ecx
	movq	%rbx, %rdi
	movq	%rax, %rdx
	movl	$863, %r8d                      # imm = 0x35F
	jmp	.LBB14_6
.LBB14_48:
	movl	%eax, %r12d
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.19, %esi
	movl	$.L.str.9, %ecx
	movq	%rbx, %rdi
	movq	%rax, %rdx
	movl	$862, %r8d                      # imm = 0x35E
	jmp	.LBB14_6
.LBB14_44:
	movl	%eax, %r12d
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.19, %esi
	movl	$.L.str.9, %ecx
	movq	%rbx, %rdi
	movq	%rax, %rdx
	movl	$858, %r8d                      # imm = 0x35A
	jmp	.LBB14_6
.LBB14_42:
	movl	%eax, %r12d
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.19, %esi
	movl	$.L.str.9, %ecx
	movq	%rbx, %rdi
	movq	%rax, %rdx
	movl	$857, %r8d                      # imm = 0x359
	jmp	.LBB14_6
.LBB14_38:
	movl	%eax, %r12d
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.19, %esi
	movl	$.L.str.9, %ecx
	movq	%rbx, %rdi
	movq	%rax, %rdx
	movl	$853, %r8d                      # imm = 0x355
	jmp	.LBB14_6
.LBB14_36:
	movl	%eax, %r12d
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.19, %esi
	movl	$.L.str.9, %ecx
	movq	%rbx, %rdi
	movq	%rax, %rdx
	movl	$852, %r8d                      # imm = 0x354
	jmp	.LBB14_6
.LBB14_32:
	movl	%eax, %r12d
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.19, %esi
	movl	$.L.str.9, %ecx
	movq	%rbx, %rdi
	movq	%rax, %rdx
	movl	$848, %r8d                      # imm = 0x350
	jmp	.LBB14_6
.LBB14_30:
	movl	%eax, %r12d
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.19, %esi
	movl	$.L.str.9, %ecx
	movq	%rbx, %rdi
	movq	%rax, %rdx
	movl	$847, %r8d                      # imm = 0x34F
	jmp	.LBB14_6
.LBB14_26:
	movl	%eax, %r12d
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.19, %esi
	movl	$.L.str.9, %ecx
	movq	%rbx, %rdi
	movq	%rax, %rdx
	movl	$843, %r8d                      # imm = 0x34B
	jmp	.LBB14_6
.LBB14_24:
	movl	%eax, %r12d
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.19, %esi
	movl	$.L.str.9, %ecx
	movq	%rbx, %rdi
	movq	%rax, %rdx
	movl	$842, %r8d                      # imm = 0x34A
	jmp	.LBB14_6
.LBB14_20:
	movl	%eax, %r12d
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.19, %esi
	movl	$.L.str.9, %ecx
	movq	%rbx, %rdi
	movq	%rax, %rdx
	movl	$838, %r8d                      # imm = 0x346
	jmp	.LBB14_6
.LBB14_18:
	movl	%eax, %r12d
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.19, %esi
	movl	$.L.str.9, %ecx
	movq	%rbx, %rdi
	movq	%rax, %rdx
	movl	$837, %r8d                      # imm = 0x345
	jmp	.LBB14_6
.LBB14_14:
	movl	%eax, %r12d
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.19, %esi
	movl	$.L.str.9, %ecx
	movq	%rbx, %rdi
	movq	%rax, %rdx
	movl	$833, %r8d                      # imm = 0x341
	jmp	.LBB14_6
.LBB14_12:
	movl	%eax, %r12d
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.19, %esi
	movl	$.L.str.9, %ecx
	movq	%rbx, %rdi
	movq	%rax, %rdx
	movl	$832, %r8d                      # imm = 0x340
	jmp	.LBB14_6
.LBB14_8:
	movl	%eax, %r12d
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.19, %esi
	movl	$.L.str.9, %ecx
	movq	%rbx, %rdi
	movq	%rax, %rdx
	movl	$827, %r8d                      # imm = 0x33B
	jmp	.LBB14_6
.LBB14_5:
	movl	%eax, %r12d
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.19, %esi
	movl	$.L.str.9, %ecx
	movq	%rbx, %rdi
	movq	%rax, %rdx
	movl	$826, %r8d                      # imm = 0x33A
.LBB14_6:
	xorl	%eax, %eax
	callq	fprintf
	movl	%r12d, %edi
	callq	exit
.LBB14_53:
	movl	%eax, %ebx
	movq	stderr(%rip), %r14
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.19, %esi
	movl	$.L.str.9, %ecx
	movq	%r14, %rdi
	movq	%rax, %rdx
	movl	$806, %r8d                      # imm = 0x326
	xorl	%eax, %eax
	callq	fprintf
	movl	%ebx, %edi
	callq	exit
.Lfunc_end14:
	.size	main, .Lfunc_end14-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB15_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB15_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z19iterateScheme_part1PdS_S_S_S_S_S_S_S_S_S_S_ddd, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z19iterateScheme_part2PdS_S_S_S_S_S_S_S_S_S_S_ddd, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z19iterateScheme_part3PdS_S_S_S_S_S_S_S_S_S_S_ddd, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z19iterateScheme_part4PdS_S_S_S_S_S_S_S_S_S_S_ddd, %esi
	movl	$.L__unnamed_4, %edx
	movl	$.L__unnamed_4, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z19iterateScheme_part5PdS_S_S_S_S_S_S_S_S_S_S_ddd, %esi
	movl	$.L__unnamed_5, %edx
	movl	$.L__unnamed_5, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z19iterateScheme_part6PdS_S_S_S_S_S_S_S_S_S_S_ddd, %esi
	movl	$.L__unnamed_6, %edx
	movl	$.L__unnamed_6, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z19iterateScheme_part7PdS_S_S_S_S_S_S_S_S_S_S_ddd, %esi
	movl	$.L__unnamed_7, %edx
	movl	$.L__unnamed_7, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z19iterateScheme_part8PdS_S_S_S_S_S_S_S_S_S_S_ddd, %esi
	movl	$.L__unnamed_8, %edx
	movl	$.L__unnamed_8, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$0, 8(%rsp)
	movl	$1, (%rsp)
	movl	$jmax_d, %esi
	movl	$.L__unnamed_9, %edx
	movl	$.L__unnamed_9, %ecx
	movl	$4, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	callq	__hipRegisterVar
	movl	$0, 8(%rsp)
	movl	$1, (%rsp)
	movl	$kmax_d, %esi
	movl	$.L__unnamed_10, %edx
	movl	$.L__unnamed_10, %ecx
	movl	$4, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	callq	__hipRegisterVar
	movl	$0, 8(%rsp)
	movl	$1, (%rsp)
	movl	$plateLength_d, %esi
	movl	$.L__unnamed_11, %edx
	movl	$.L__unnamed_11, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	callq	__hipRegisterVar
	movl	$0, 8(%rsp)
	movl	$1, (%rsp)
	movl	$CFL_d, %esi
	movl	$.L__unnamed_12, %edx
	movl	$.L__unnamed_12, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	callq	__hipRegisterVar
	movl	$0, 8(%rsp)
	movl	$1, (%rsp)
	movl	$u0_d, %esi
	movl	$.L__unnamed_13, %edx
	movl	$.L__unnamed_13, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	callq	__hipRegisterVar
	movl	$0, 8(%rsp)
	movl	$1, (%rsp)
	movl	$gam_d, %esi
	movl	$.L__unnamed_14, %edx
	movl	$.L__unnamed_14, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	callq	__hipRegisterVar
	movl	$0, 8(%rsp)
	movl	$1, (%rsp)
	movl	$Pr_d, %esi
	movl	$.L__unnamed_15, %edx
	movl	$.L__unnamed_15, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	callq	__hipRegisterVar
	movl	$0, 8(%rsp)
	movl	$1, (%rsp)
	movl	$R_d, %esi
	movl	$.L__unnamed_16, %edx
	movl	$.L__unnamed_16, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	callq	__hipRegisterVar
	movl	$0, 8(%rsp)
	movl	$1, (%rsp)
	movl	$Cv_d, %esi
	movl	$.L__unnamed_17, %edx
	movl	$.L__unnamed_17, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	callq	__hipRegisterVar
	movl	$0, 8(%rsp)
	movl	$1, (%rsp)
	movl	$Cp_d, %esi
	movl	$.L__unnamed_18, %edx
	movl	$.L__unnamed_18, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	callq	__hipRegisterVar
	movl	$0, 8(%rsp)
	movl	$1, (%rsp)
	movl	$mu0_d, %esi
	movl	$.L__unnamed_19, %edx
	movl	$.L__unnamed_19, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	callq	__hipRegisterVar
	movl	$0, 8(%rsp)
	movl	$1, (%rsp)
	movl	$T0_d, %esi
	movl	$.L__unnamed_20, %edx
	movl	$.L__unnamed_20, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	callq	__hipRegisterVar
	movl	$0, 8(%rsp)
	movl	$1, (%rsp)
	movl	$p0_d, %esi
	movl	$.L__unnamed_21, %edx
	movl	$.L__unnamed_21, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	callq	__hipRegisterVar
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end15:
	.size	__hip_module_ctor, .Lfunc_end15-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB16_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB16_2:
	retq
.Lfunc_end16:
	.size	__hip_module_dtor, .Lfunc_end16-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	jmax,@object                    # @jmax
	.data
	.globl	jmax
	.p2align	2, 0x0
jmax:
	.long	70                              # 0x46
	.size	jmax, 4

	.type	kmax,@object                    # @kmax
	.globl	kmax
	.p2align	2, 0x0
kmax:
	.long	70                              # 0x46
	.size	kmax, 4

	.type	jmax_d,@object                  # @jmax_d
	.local	jmax_d
	.comm	jmax_d,4,4
	.type	kmax_d,@object                  # @kmax_d
	.local	kmax_d
	.comm	kmax_d,4,4
	.type	plateLength,@object             # @plateLength
	.globl	plateLength
	.p2align	3, 0x0
plateLength:
	.quad	0x3ee4f8b588e368f1              # double 1.0000000000000001E-5
	.size	plateLength, 8

	.type	plateLength_d,@object           # @plateLength_d
	.local	plateLength_d
	.comm	plateLength_d,8,8
	.type	CFL,@object                     # @CFL
	.globl	CFL
	.p2align	3, 0x0
CFL:
	.quad	0x3fc999999999999a              # double 0.20000000000000001
	.size	CFL, 8

	.type	CFL_d,@object                   # @CFL_d
	.local	CFL_d
	.comm	CFL_d,8,8
	.type	M0,@object                      # @M0
	.globl	M0
	.p2align	3, 0x0
M0:
	.quad	0x4010000000000000              # double 4
	.size	M0, 8

	.type	dx,@object                      # @dx
	.globl	dx
	.p2align	3, 0x0
dx:
	.quad	0x3e8373ac1715b6ac              # double 1.4492753623188408E-7
	.size	dx, 8

	.type	dy,@object                      # @dy
	.globl	dy
	.p2align	3, 0x0
dy:
	.quad	0x3e7fdc508fc5c963              # double 1.1869E-7
	.size	dy, 8

	.type	u0_d,@object                    # @u0_d
	.local	u0_d
	.comm	u0_d,8,8
	.type	gam_d,@object                   # @gam_d
	.local	gam_d
	.comm	gam_d,8,8
	.type	Pr_d,@object                    # @Pr_d
	.local	Pr_d
	.comm	Pr_d,8,8
	.type	R_d,@object                     # @R_d
	.local	R_d
	.comm	R_d,8,8
	.type	Cv_d,@object                    # @Cv_d
	.local	Cv_d
	.comm	Cv_d,8,8
	.type	Cp_d,@object                    # @Cp_d
	.local	Cp_d
	.comm	Cp_d,8,8
	.type	mu0_d,@object                   # @mu0_d
	.local	mu0_d
	.comm	mu0_d,8,8
	.type	T0_d,@object                    # @T0_d
	.local	T0_d
	.comm	T0_d,8,8
	.type	p0_d,@object                    # @p0_d
	.local	p0_d
	.comm	p0_d,8,8
	.type	a0,@object                      # @a0
	.globl	a0
	.p2align	3, 0x0
a0:
	.quad	0x4075447ae147ae14              # double 340.27999999999997
	.size	a0, 8

	.type	u0,@object                      # @u0
	.globl	u0
	.p2align	3, 0x0
u0:
	.quad	0x4095447ae147ae14              # double 1361.1199999999999
	.size	u0, 8

	.type	p0,@object                      # @p0
	.globl	p0
	.p2align	3, 0x0
p0:
	.quad	0x40f8bcd000000000              # double 101325
	.size	p0, 8

	.type	T0,@object                      # @T0
	.globl	T0
	.p2align	3, 0x0
T0:
	.quad	0x4072028f5c28f5c3              # double 288.16000000000003
	.size	T0, 8

	.type	v0,@object                      # @v0
	.bss
	.globl	v0
	.p2align	3, 0x0
v0:
	.quad	0x0000000000000000              # double 0
	.size	v0, 8

	.type	gam,@object                     # @gam
	.data
	.globl	gam
	.p2align	3, 0x0
gam:
	.quad	0x3ff6666666666666              # double 1.3999999999999999
	.size	gam, 8

	.type	Pr,@object                      # @Pr
	.globl	Pr
	.p2align	3, 0x0
Pr:
	.quad	0x3fe6b851eb851eb8              # double 0.70999999999999996
	.size	Pr, 8

	.type	R,@object                       # @R
	.globl	R
	.p2align	3, 0x0
R:
	.quad	0x4071f00000000000              # double 287
	.size	R, 8

	.type	Cv,@object                      # @Cv
	.globl	Cv
	.p2align	3, 0x0
Cv:
	.quad	0x408668cccccccccc              # double 717.09999999999991
	.size	Cv, 8

	.type	Cp,@object                      # @Cp
	.globl	Cp
	.p2align	3, 0x0
Cp:
	.quad	0x408f700000000000              # double 1006
	.size	Cp, 8

	.type	rho0,@object                    # @rho0
	.globl	rho0
	.p2align	3, 0x0
rho0:
	.quad	0x3ff39a59a943cf2b              # double 1.2251831638249751
	.size	rho0, 8

	.type	e0,@object                      # @e0
	.globl	e0
	.p2align	3, 0x0
e0:
	.quad	0x4109397c49ba5e35              # double 206639.53599999999
	.size	e0, 8

	.type	mu0,@object                     # @mu0
	.globl	mu0
	.p2align	3, 0x0
mu0:
	.quad	0x3ef2c36251142aeb              # double 1.7893999999999998E-5
	.size	mu0, 8

	.type	Re,@object                      # @Re
	.globl	Re
	.p2align	3, 0x0
Re:
	.quad	0x408d1f8e212c38cf              # double 931.94439920948378
	.size	Re, 8

	.type	_Z19iterateScheme_part1PdS_S_S_S_S_S_S_S_S_S_S_ddd,@object # @_Z19iterateScheme_part1PdS_S_S_S_S_S_S_S_S_S_S_ddd
	.section	.rodata,"a",@progbits
	.globl	_Z19iterateScheme_part1PdS_S_S_S_S_S_S_S_S_S_S_ddd
	.p2align	3, 0x0
_Z19iterateScheme_part1PdS_S_S_S_S_S_S_S_S_S_S_ddd:
	.quad	_Z34__device_stub__iterateScheme_part1PdS_S_S_S_S_S_S_S_S_S_S_ddd
	.size	_Z19iterateScheme_part1PdS_S_S_S_S_S_S_S_S_S_S_ddd, 8

	.type	_Z19iterateScheme_part2PdS_S_S_S_S_S_S_S_S_S_S_ddd,@object # @_Z19iterateScheme_part2PdS_S_S_S_S_S_S_S_S_S_S_ddd
	.globl	_Z19iterateScheme_part2PdS_S_S_S_S_S_S_S_S_S_S_ddd
	.p2align	3, 0x0
_Z19iterateScheme_part2PdS_S_S_S_S_S_S_S_S_S_S_ddd:
	.quad	_Z34__device_stub__iterateScheme_part2PdS_S_S_S_S_S_S_S_S_S_S_ddd
	.size	_Z19iterateScheme_part2PdS_S_S_S_S_S_S_S_S_S_S_ddd, 8

	.type	_Z19iterateScheme_part3PdS_S_S_S_S_S_S_S_S_S_S_ddd,@object # @_Z19iterateScheme_part3PdS_S_S_S_S_S_S_S_S_S_S_ddd
	.globl	_Z19iterateScheme_part3PdS_S_S_S_S_S_S_S_S_S_S_ddd
	.p2align	3, 0x0
_Z19iterateScheme_part3PdS_S_S_S_S_S_S_S_S_S_S_ddd:
	.quad	_Z34__device_stub__iterateScheme_part3PdS_S_S_S_S_S_S_S_S_S_S_ddd
	.size	_Z19iterateScheme_part3PdS_S_S_S_S_S_S_S_S_S_S_ddd, 8

	.type	_Z19iterateScheme_part4PdS_S_S_S_S_S_S_S_S_S_S_ddd,@object # @_Z19iterateScheme_part4PdS_S_S_S_S_S_S_S_S_S_S_ddd
	.globl	_Z19iterateScheme_part4PdS_S_S_S_S_S_S_S_S_S_S_ddd
	.p2align	3, 0x0
_Z19iterateScheme_part4PdS_S_S_S_S_S_S_S_S_S_S_ddd:
	.quad	_Z34__device_stub__iterateScheme_part4PdS_S_S_S_S_S_S_S_S_S_S_ddd
	.size	_Z19iterateScheme_part4PdS_S_S_S_S_S_S_S_S_S_S_ddd, 8

	.type	_Z19iterateScheme_part5PdS_S_S_S_S_S_S_S_S_S_S_ddd,@object # @_Z19iterateScheme_part5PdS_S_S_S_S_S_S_S_S_S_S_ddd
	.globl	_Z19iterateScheme_part5PdS_S_S_S_S_S_S_S_S_S_S_ddd
	.p2align	3, 0x0
_Z19iterateScheme_part5PdS_S_S_S_S_S_S_S_S_S_S_ddd:
	.quad	_Z34__device_stub__iterateScheme_part5PdS_S_S_S_S_S_S_S_S_S_S_ddd
	.size	_Z19iterateScheme_part5PdS_S_S_S_S_S_S_S_S_S_S_ddd, 8

	.type	_Z19iterateScheme_part6PdS_S_S_S_S_S_S_S_S_S_S_ddd,@object # @_Z19iterateScheme_part6PdS_S_S_S_S_S_S_S_S_S_S_ddd
	.globl	_Z19iterateScheme_part6PdS_S_S_S_S_S_S_S_S_S_S_ddd
	.p2align	3, 0x0
_Z19iterateScheme_part6PdS_S_S_S_S_S_S_S_S_S_S_ddd:
	.quad	_Z34__device_stub__iterateScheme_part6PdS_S_S_S_S_S_S_S_S_S_S_ddd
	.size	_Z19iterateScheme_part6PdS_S_S_S_S_S_S_S_S_S_S_ddd, 8

	.type	_Z19iterateScheme_part7PdS_S_S_S_S_S_S_S_S_S_S_ddd,@object # @_Z19iterateScheme_part7PdS_S_S_S_S_S_S_S_S_S_S_ddd
	.globl	_Z19iterateScheme_part7PdS_S_S_S_S_S_S_S_S_S_S_ddd
	.p2align	3, 0x0
_Z19iterateScheme_part7PdS_S_S_S_S_S_S_S_S_S_S_ddd:
	.quad	_Z34__device_stub__iterateScheme_part7PdS_S_S_S_S_S_S_S_S_S_S_ddd
	.size	_Z19iterateScheme_part7PdS_S_S_S_S_S_S_S_S_S_S_ddd, 8

	.type	_Z19iterateScheme_part8PdS_S_S_S_S_S_S_S_S_S_S_ddd,@object # @_Z19iterateScheme_part8PdS_S_S_S_S_S_S_S_S_S_S_ddd
	.globl	_Z19iterateScheme_part8PdS_S_S_S_S_S_S_S_S_S_S_ddd
	.p2align	3, 0x0
_Z19iterateScheme_part8PdS_S_S_S_S_S_S_S_S_S_S_ddd:
	.quad	_Z34__device_stub__iterateScheme_part8PdS_S_S_S_S_S_S_S_S_S_S_ddd
	.size	_Z19iterateScheme_part8PdS_S_S_S_S_S_S_S_S_S_S_ddd, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"w+"
	.size	.L.str, 3

	.type	.L.str.6,@object                # @.str.6
.L.str.6:
	.asciz	", %f"
	.size	.L.str.6, 5

	.type	.L.str.8,@object                # @.str.8
.L.str.8:
	.asciz	"Dimension Starting: %i\n"
	.size	.L.str.8, 24

	.type	.L.str.9,@object                # @.str.9
.L.str.9:
	.asciz	"/home/ubuntu/Datasets/stackv2/train-structured-repos-hip-sm89/mattkennedy416/NavierStokes/master/report/code/NavierStokesSolver.hip"
	.size	.L.str.9, 132

	.type	.L.str.10,@object               # @.str.10
.L.str.10:
	.asciz	"Calculating iteration %i / %i\n"
	.size	.L.str.10, 31

	.type	.L.str.11,@object               # @.str.11
.L.str.11:
	.asciz	"u.csv"
	.size	.L.str.11, 6

	.type	.L.str.12,@object               # @.str.12
.L.str.12:
	.asciz	"v.csv"
	.size	.L.str.12, 6

	.type	.L.str.13,@object               # @.str.13
.L.str.13:
	.asciz	"p.csv"
	.size	.L.str.13, 6

	.type	.L.str.14,@object               # @.str.14
.L.str.14:
	.asciz	"T.csv"
	.size	.L.str.14, 6

	.type	.L.str.15,@object               # @.str.15
.L.str.15:
	.asciz	"F.csv"
	.size	.L.str.15, 6

	.type	.L.str.16,@object               # @.str.16
.L.str.16:
	.asciz	"G.csv"
	.size	.L.str.16, 6

	.type	.L.str.17,@object               # @.str.17
.L.str.17:
	.asciz	"Q.csv"
	.size	.L.str.17, 6

	.type	.L.str.19,@object               # @.str.19
.L.str.19:
	.asciz	"GPUassert: %s %s %d\n"
	.size	.L.str.19, 21

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z19iterateScheme_part1PdS_S_S_S_S_S_S_S_S_S_S_ddd"
	.size	.L__unnamed_1, 51

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z19iterateScheme_part2PdS_S_S_S_S_S_S_S_S_S_S_ddd"
	.size	.L__unnamed_2, 51

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z19iterateScheme_part3PdS_S_S_S_S_S_S_S_S_S_S_ddd"
	.size	.L__unnamed_3, 51

	.type	.L__unnamed_4,@object           # @3
.L__unnamed_4:
	.asciz	"_Z19iterateScheme_part4PdS_S_S_S_S_S_S_S_S_S_S_ddd"
	.size	.L__unnamed_4, 51

	.type	.L__unnamed_5,@object           # @4
.L__unnamed_5:
	.asciz	"_Z19iterateScheme_part5PdS_S_S_S_S_S_S_S_S_S_S_ddd"
	.size	.L__unnamed_5, 51

	.type	.L__unnamed_6,@object           # @5
.L__unnamed_6:
	.asciz	"_Z19iterateScheme_part6PdS_S_S_S_S_S_S_S_S_S_S_ddd"
	.size	.L__unnamed_6, 51

	.type	.L__unnamed_7,@object           # @6
.L__unnamed_7:
	.asciz	"_Z19iterateScheme_part7PdS_S_S_S_S_S_S_S_S_S_S_ddd"
	.size	.L__unnamed_7, 51

	.type	.L__unnamed_8,@object           # @7
.L__unnamed_8:
	.asciz	"_Z19iterateScheme_part8PdS_S_S_S_S_S_S_S_S_S_S_ddd"
	.size	.L__unnamed_8, 51

	.type	.L__unnamed_9,@object           # @8
.L__unnamed_9:
	.asciz	"jmax_d"
	.size	.L__unnamed_9, 7

	.type	.L__unnamed_10,@object          # @9
.L__unnamed_10:
	.asciz	"kmax_d"
	.size	.L__unnamed_10, 7

	.type	.L__unnamed_11,@object          # @10
.L__unnamed_11:
	.asciz	"plateLength_d"
	.size	.L__unnamed_11, 14

	.type	.L__unnamed_12,@object          # @11
.L__unnamed_12:
	.asciz	"CFL_d"
	.size	.L__unnamed_12, 6

	.type	.L__unnamed_13,@object          # @12
.L__unnamed_13:
	.asciz	"u0_d"
	.size	.L__unnamed_13, 5

	.type	.L__unnamed_14,@object          # @13
.L__unnamed_14:
	.asciz	"gam_d"
	.size	.L__unnamed_14, 6

	.type	.L__unnamed_15,@object          # @14
.L__unnamed_15:
	.asciz	"Pr_d"
	.size	.L__unnamed_15, 5

	.type	.L__unnamed_16,@object          # @15
.L__unnamed_16:
	.asciz	"R_d"
	.size	.L__unnamed_16, 4

	.type	.L__unnamed_17,@object          # @16
.L__unnamed_17:
	.asciz	"Cv_d"
	.size	.L__unnamed_17, 5

	.type	.L__unnamed_18,@object          # @17
.L__unnamed_18:
	.asciz	"Cp_d"
	.size	.L__unnamed_18, 5

	.type	.L__unnamed_19,@object          # @18
.L__unnamed_19:
	.asciz	"mu0_d"
	.size	.L__unnamed_19, 6

	.type	.L__unnamed_20,@object          # @19
.L__unnamed_20:
	.asciz	"T0_d"
	.size	.L__unnamed_20, 5

	.type	.L__unnamed_21,@object          # @20
.L__unnamed_21:
	.asciz	"p0_d"
	.size	.L__unnamed_21, 5

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.type	.Lstr,@object                   # @str
	.section	.rodata.str1.1,"aMS",@progbits,1
.Lstr:
	.asciz	"Finishing!"
	.size	.Lstr, 11

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z34__device_stub__iterateScheme_part1PdS_S_S_S_S_S_S_S_S_S_S_ddd
	.addrsig_sym _Z34__device_stub__iterateScheme_part2PdS_S_S_S_S_S_S_S_S_S_S_ddd
	.addrsig_sym _Z34__device_stub__iterateScheme_part3PdS_S_S_S_S_S_S_S_S_S_S_ddd
	.addrsig_sym _Z34__device_stub__iterateScheme_part4PdS_S_S_S_S_S_S_S_S_S_S_ddd
	.addrsig_sym _Z34__device_stub__iterateScheme_part5PdS_S_S_S_S_S_S_S_S_S_S_ddd
	.addrsig_sym _Z34__device_stub__iterateScheme_part6PdS_S_S_S_S_S_S_S_S_S_S_ddd
	.addrsig_sym _Z34__device_stub__iterateScheme_part7PdS_S_S_S_S_S_S_S_S_S_S_ddd
	.addrsig_sym _Z34__device_stub__iterateScheme_part8PdS_S_S_S_S_S_S_S_S_S_S_ddd
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym jmax_d
	.addrsig_sym kmax_d
	.addrsig_sym plateLength_d
	.addrsig_sym CFL_d
	.addrsig_sym u0_d
	.addrsig_sym gam_d
	.addrsig_sym Pr_d
	.addrsig_sym R_d
	.addrsig_sym Cv_d
	.addrsig_sym Cp_d
	.addrsig_sym mu0_d
	.addrsig_sym T0_d
	.addrsig_sym p0_d
	.addrsig_sym _Z19iterateScheme_part1PdS_S_S_S_S_S_S_S_S_S_S_ddd
	.addrsig_sym _Z19iterateScheme_part2PdS_S_S_S_S_S_S_S_S_S_S_ddd
	.addrsig_sym _Z19iterateScheme_part3PdS_S_S_S_S_S_S_S_S_S_S_ddd
	.addrsig_sym _Z19iterateScheme_part4PdS_S_S_S_S_S_S_S_S_S_S_ddd
	.addrsig_sym _Z19iterateScheme_part5PdS_S_S_S_S_S_S_S_S_S_S_ddd
	.addrsig_sym _Z19iterateScheme_part6PdS_S_S_S_S_S_S_S_S_S_S_ddd
	.addrsig_sym _Z19iterateScheme_part7PdS_S_S_S_S_S_S_S_S_S_S_ddd
	.addrsig_sym _Z19iterateScheme_part8PdS_S_S_S_S_S_S_S_S_S_S_ddd
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.p2align	2                               ; -- Begin function _Z7calc_FGPdS_S_S_S_S_biidd
	.type	_Z7calc_FGPdS_S_S_S_S_biidd,@function
_Z7calc_FGPdS_S_S_S_S_biidd:            ; @_Z7calc_FGPdS_S_S_S_S_biidd
; %bb.0:
	s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	s_or_saveexec_b32 s0, -1
	s_clause 0x1
	scratch_store_b32 off, v40, s32
	; meta instruction
	scratch_store_b32 off, v41, s32 offset:4
	s_mov_b32 exec_lo, s0
	v_writelane_b32 v40, s34, 0
	v_writelane_b32 v40, s35, 1
	v_writelane_b32 v40, s36, 2
	v_writelane_b32 v40, s37, 3
	v_writelane_b32 v40, s38, 4
	v_writelane_b32 v40, s39, 5
	v_writelane_b32 v40, s40, 6
	v_writelane_b32 v40, s41, 7
	v_writelane_b32 v40, s42, 8
	v_writelane_b32 v40, s43, 9
	v_writelane_b32 v40, s44, 10
	v_writelane_b32 v40, s45, 11
	v_writelane_b32 v40, s46, 12
	v_writelane_b32 v40, s47, 13
	v_writelane_b32 v40, s48, 14
	v_writelane_b32 v40, s49, 15
	v_writelane_b32 v40, s50, 16
	v_writelane_b32 v40, s51, 17
	v_writelane_b32 v40, s52, 18
	v_writelane_b32 v40, s53, 19
	v_writelane_b32 v40, s54, 20
	v_writelane_b32 v40, s55, 21
	v_writelane_b32 v40, s56, 22
	v_writelane_b32 v40, s57, 23
	v_writelane_b32 v40, s58, 24
	v_writelane_b32 v40, s59, 25
	v_writelane_b32 v40, s60, 26
	v_writelane_b32 v40, s61, 27
	v_writelane_b32 v40, s62, 28
	v_writelane_b32 v40, s63, 29
	v_writelane_b32 v40, s64, 30
	v_writelane_b32 v40, s65, 31
	v_writelane_b32 v41, s66, 0
	v_writelane_b32 v41, s67, 1
	v_writelane_b32 v41, s68, 2
	v_writelane_b32 v41, s69, 3
	v_writelane_b32 v41, s70, 4
	v_writelane_b32 v41, s71, 5
	v_writelane_b32 v41, s30, 6
	v_writelane_b32 v41, s31, 7
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, kmax_d@rel32@lo+4
	s_addc_u32 s1, s1, kmax_d@rel32@hi+12
	v_dual_mov_b32 v20, v16 :: v_dual_mov_b32 v19, v15
	s_load_b32 s4, s[0:1], 0x0
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, jmax_d@rel32@lo+4
	s_addc_u32 s1, s1, jmax_d@rel32@hi+12
	v_and_b32_e32 v12, 1, v12
	s_load_b32 s5, s[0:1], 0x0
	s_mov_b32 s1, 0
                                        ; implicit-def: $vgpr33_vgpr34
                                        ; implicit-def: $vgpr52_vgpr53
                                        ; implicit-def: $vgpr50_vgpr51
	s_waitcnt lgkmcnt(0)
	v_mul_lo_u32 v35, s4, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v37, v35, v14
	v_ashrrev_i32_e32 v38, 31, v37
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[25:26], 3, v[37:38]
	v_add_co_u32 v8, vcc_lo, v8, v25
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v9, vcc_lo, v9, v26, vcc_lo
	v_add_co_u32 v15, vcc_lo, v10, v25
	v_add_co_ci_u32_e32 v16, vcc_lo, v11, v26, vcc_lo
	v_add_co_u32 v21, vcc_lo, v4, v25
	v_add_co_ci_u32_e32 v22, vcc_lo, v5, v26, vcc_lo
	v_add_co_u32 v23, vcc_lo, v6, v25
	v_add_co_ci_u32_e32 v24, vcc_lo, v7, v26, vcc_lo
	flat_load_b64 v[48:49], v[8:9]
	flat_load_b64 v[27:28], v[15:16]
	flat_load_b64 v[29:30], v[21:22]
	flat_load_b64 v[31:32], v[23:24]
	v_cmp_eq_u32_e32 vcc_lo, 1, v12
	s_xor_b32 s0, vcc_lo, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_saveexec_b32 s2, s0
	s_xor_b32 s2, exec_lo, s2
	s_cbranch_execz .LBB0_16
; %bb.1:
	s_add_i32 s6, s5, -1
	s_mov_b32 s3, exec_lo
                                        ; implicit-def: $vgpr52_vgpr53
                                        ; implicit-def: $vgpr50_vgpr51
	v_cmpx_le_i32_e64 s6, v13
	s_xor_b32 s3, exec_lo, s3
	s_cbranch_execz .LBB0_5
; %bb.2:
	v_cmp_eq_u32_e32 vcc_lo, s6, v13
                                        ; implicit-def: $vgpr50_vgpr51
	s_and_saveexec_b32 s6, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s6, exec_lo, s6
; %bb.3:
	v_add_nc_u32_e32 v12, -1, v13
	s_mov_b32 s1, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[50:51], null, v12, s4, v[14:15]
	v_ashrrev_i32_e32 v51, 31, v50
; %bb.4:                                ; %Flow153
	s_or_b32 exec_lo, exec_lo, s6
	v_dual_mov_b32 v53, v38 :: v_dual_mov_b32 v52, v37
	s_and_b32 s1, s1, exec_lo
.LBB0_5:                                ; %Flow152
	s_and_not1_saveexec_b32 s3, s3
; %bb.6:
	v_add3_u32 v52, v35, s4, v14
	v_dual_mov_b32 v51, v38 :: v_dual_mov_b32 v50, v37
	s_or_b32 s1, s1, exec_lo
	s_delay_alu instid0(VALU_DEP_2)
	v_ashrrev_i32_e32 v53, 31, v52
; %bb.7:                                ; %Flow154
	s_or_b32 exec_lo, exec_lo, s3
                                        ; implicit-def: $vgpr33_vgpr34
	s_and_saveexec_b32 s3, s1
	s_cbranch_execz .LBB0_9
; %bb.8:                                ; %.sink.split83.i
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[33:34], 3, v[52:53]
	v_lshlrev_b64 v[50:51], 3, v[50:51]
	v_add_co_u32 v33, vcc_lo, v10, v33
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v34, vcc_lo, v11, v34, vcc_lo
	v_add_co_u32 v10, vcc_lo, v10, v50
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v11, vcc_lo, v11, v51, vcc_lo
	s_clause 0x1
	flat_load_b64 v[33:34], v[33:34]
	flat_load_b64 v[10:11], v[10:11]
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f64 v[10:11], v[33:34], -v[10:11]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_scale_f64 v[33:34], null, v[19:20], v[19:20], v[10:11]
	v_rcp_f64_e32 v[50:51], v[33:34]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[52:53], -v[33:34], v[50:51], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[50:51], v[50:51], v[52:53], v[50:51]
	v_fma_f64 v[52:53], -v[33:34], v[50:51], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f64 v[50:51], v[50:51], v[52:53], v[50:51]
	v_div_scale_f64 v[52:53], vcc_lo, v[10:11], v[19:20], v[10:11]
	v_mul_f64 v[54:55], v[52:53], v[50:51]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[33:34], -v[33:34], v[54:55], v[52:53]
	v_div_fmas_f64 v[33:34], v[33:34], v[50:51], v[54:55]
	s_delay_alu instid0(VALU_DEP_1)
	v_div_fixup_f64 v[33:34], v[33:34], v[19:20], v[10:11]
.LBB0_9:
	s_or_b32 exec_lo, exec_lo, s3
	s_add_i32 s6, s4, -1
	s_mov_b32 s1, 0
	s_mov_b32 s3, exec_lo
                                        ; implicit-def: $vgpr52_vgpr53
                                        ; implicit-def: $vgpr50_vgpr51
	v_cmpx_le_i32_e64 s6, v14
	s_xor_b32 s3, exec_lo, s3
	s_cbranch_execz .LBB0_13
; %bb.10:
	v_cmp_eq_u32_e32 vcc_lo, s6, v14
                                        ; implicit-def: $vgpr50_vgpr51
	s_and_saveexec_b32 s6, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s6, exec_lo, s6
; %bb.11:
	v_add_co_u32 v50, vcc_lo, v15, -8
	v_add_co_ci_u32_e32 v51, vcc_lo, -1, v16, vcc_lo
	s_mov_b32 s1, exec_lo
; %bb.12:                               ; %Flow163
	s_or_b32 exec_lo, exec_lo, s6
	v_dual_mov_b32 v53, v16 :: v_dual_mov_b32 v52, v15
	s_and_b32 s1, s1, exec_lo
                                        ; implicit-def: $vgpr15
.LBB0_13:                               ; %Flow162
	s_and_not1_saveexec_b32 s3, s3
; %bb.14:
	v_add_co_u32 v52, vcc_lo, v15, 8
	v_add_co_ci_u32_e32 v53, vcc_lo, 0, v16, vcc_lo
	v_dual_mov_b32 v51, v16 :: v_dual_mov_b32 v50, v15
	s_or_b32 s1, s1, exec_lo
; %bb.15:                               ; %Flow164
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s1, s1, exec_lo
                                        ; implicit-def: $vgpr15_vgpr16
                                        ; implicit-def: $vgpr10_vgpr11
.LBB0_16:                               ; %Flow161
	s_and_not1_saveexec_b32 s2, s2
	s_cbranch_execz .LBB0_32
; %bb.17:
	s_mov_b32 s6, 0
	s_mov_b32 s3, exec_lo
                                        ; implicit-def: $vgpr52
                                        ; implicit-def: $vgpr50_vgpr51
	v_cmpx_gt_i32_e32 1, v13
	s_xor_b32 s3, exec_lo, s3
	s_cbranch_execz .LBB0_21
; %bb.18:
	s_mov_b32 s7, exec_lo
                                        ; implicit-def: $vgpr50_vgpr51
	v_cmpx_eq_u32_e32 0, v13
	s_xor_b32 s7, exec_lo, s7
; %bb.19:                               ; %..sink.split.i_crit_edge
	v_add_nc_u32_e32 v50, s4, v14
	s_mov_b32 s6, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_ashrrev_i32_e32 v51, 31, v50
; %bb.20:                               ; %Flow157
	s_or_b32 exec_lo, exec_lo, s7
	v_mov_b32_e32 v52, v14
	s_and_b32 s6, s6, exec_lo
.LBB0_21:                               ; %Flow156
	s_and_not1_saveexec_b32 s3, s3
; %bb.22:
	v_subrev_nc_u32_e32 v12, s4, v35
	s_or_b32 s6, s6, exec_lo
	v_dual_mov_b32 v51, v38 :: v_dual_mov_b32 v50, v37
	s_delay_alu instid0(VALU_DEP_2)
	v_add_nc_u32_e32 v52, v12, v14
; %bb.23:                               ; %Flow158
	s_or_b32 exec_lo, exec_lo, s3
                                        ; implicit-def: $vgpr33_vgpr34
	s_and_saveexec_b32 s3, s6
	s_cbranch_execz .LBB0_25
; %bb.24:                               ; %.sink.split.i
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v53, 31, v52
	v_lshlrev_b64 v[33:34], 3, v[50:51]
	v_lshlrev_b64 v[50:51], 3, v[52:53]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v33, vcc_lo, v10, v33
	v_add_co_ci_u32_e32 v34, vcc_lo, v11, v34, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v50, vcc_lo, v10, v50
	v_add_co_ci_u32_e32 v51, vcc_lo, v11, v51, vcc_lo
	s_clause 0x1
	flat_load_b64 v[33:34], v[33:34]
	flat_load_b64 v[50:51], v[50:51]
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f64 v[33:34], v[33:34], -v[50:51]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_scale_f64 v[50:51], null, v[19:20], v[19:20], v[33:34]
	v_rcp_f64_e32 v[52:53], v[50:51]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[54:55], -v[50:51], v[52:53], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[52:53], v[52:53], v[54:55], v[52:53]
	v_fma_f64 v[54:55], -v[50:51], v[52:53], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f64 v[52:53], v[52:53], v[54:55], v[52:53]
	v_div_scale_f64 v[54:55], vcc_lo, v[33:34], v[19:20], v[33:34]
	v_mul_f64 v[64:65], v[54:55], v[52:53]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[50:51], -v[50:51], v[64:65], v[54:55]
	v_div_fmas_f64 v[50:51], v[50:51], v[52:53], v[64:65]
	s_delay_alu instid0(VALU_DEP_1)
	v_div_fixup_f64 v[33:34], v[50:51], v[19:20], v[33:34]
.LBB0_25:
	s_or_b32 exec_lo, exec_lo, s3
	s_mov_b32 s3, s1
	s_mov_b32 s6, exec_lo
                                        ; implicit-def: $vgpr52_vgpr53
                                        ; implicit-def: $vgpr50_vgpr51
	v_cmpx_gt_i32_e32 1, v14
	s_xor_b32 s6, exec_lo, s6
	s_cbranch_execz .LBB0_29
; %bb.26:
	s_mov_b32 s3, s1
	s_mov_b32 s7, exec_lo
                                        ; implicit-def: $vgpr52_vgpr53
                                        ; implicit-def: $vgpr50_vgpr51
	v_cmpx_eq_u32_e32 0, v14
	s_xor_b32 s7, exec_lo, s7
; %bb.27:
	v_ashrrev_i32_e32 v36, 31, v35
	s_or_b32 s3, s1, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[15:16], 3, v[35:36]
	v_add_co_u32 v50, vcc_lo, v10, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v51, vcc_lo, v11, v16, vcc_lo
	v_add_co_u32 v52, vcc_lo, v50, 8
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v53, vcc_lo, 0, v51, vcc_lo
; %bb.28:                               ; %Flow167
	s_or_b32 exec_lo, exec_lo, s7
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_and_not1_b32 s7, s1, exec_lo
	s_and_b32 s3, s3, exec_lo
                                        ; implicit-def: $vgpr10_vgpr11
                                        ; implicit-def: $vgpr15_vgpr16
	s_or_b32 s3, s7, s3
.LBB0_29:                               ; %Flow166
	s_and_not1_saveexec_b32 s6, s6
; %bb.30:
	v_dual_mov_b32 v53, v16 :: v_dual_add_nc_u32 v50, -1, v37
	v_mov_b32_e32 v52, v15
	s_or_b32 s3, s3, exec_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v51, 31, v50
	v_lshlrev_b64 v[50:51], 3, v[50:51]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v50, vcc_lo, v10, v50
	v_add_co_ci_u32_e32 v51, vcc_lo, v11, v51, vcc_lo
; %bb.31:                               ; %Flow168
	s_or_b32 exec_lo, exec_lo, s6
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_and_not1_b32 s1, s1, exec_lo
	s_and_b32 s3, s3, exec_lo
	s_or_b32 s1, s1, s3
.LBB0_32:                               ; %Flow165
	s_or_b32 exec_lo, exec_lo, s2
                                        ; implicit-def: $vgpr10_vgpr11
	s_and_saveexec_b32 s2, s1
	s_cbranch_execz .LBB0_34
; %bb.33:                               ; %.sink.split92.i
	flat_load_b64 v[10:11], v[52:53]
	flat_load_b64 v[15:16], v[50:51]
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f64 v[10:11], v[10:11], -v[15:16]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_scale_f64 v[15:16], null, v[17:18], v[17:18], v[10:11]
	v_rcp_f64_e32 v[50:51], v[15:16]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[52:53], -v[15:16], v[50:51], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[50:51], v[50:51], v[52:53], v[50:51]
	v_fma_f64 v[52:53], -v[15:16], v[50:51], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f64 v[50:51], v[50:51], v[52:53], v[50:51]
	v_div_scale_f64 v[52:53], vcc_lo, v[10:11], v[17:18], v[10:11]
	v_mul_f64 v[54:55], v[52:53], v[50:51]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[15:16], -v[15:16], v[54:55], v[52:53]
	v_div_fmas_f64 v[15:16], v[15:16], v[50:51], v[54:55]
	s_delay_alu instid0(VALU_DEP_1)
	v_div_fixup_f64 v[10:11], v[15:16], v[17:18], v[10:11]
.LBB0_34:                               ; %_Z18heatFluxParametersPddbiiddS_.exit
	s_or_b32 exec_lo, exec_lo, s2
                                        ; implicit-def: $vgpr50_vgpr51
                                        ; implicit-def: $vgpr52_vgpr53
                                        ; implicit-def: $vgpr15_vgpr16
                                        ; implicit-def: $vgpr54_vgpr55
                                        ; implicit-def: $vgpr64
	s_and_saveexec_b32 s1, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s0, exec_lo, s1
	s_cbranch_execz .LBB0_44
; %bb.35:
	s_add_i32 s1, s5, -1
                                        ; implicit-def: $vgpr15_vgpr16
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_le_i32_e32 vcc_lo, s1, v13
	s_and_saveexec_b32 s1, vcc_lo
	s_xor_b32 s1, exec_lo, s1
; %bb.36:
	v_add_nc_u32_e32 v12, -1, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[15:16], null, s4, v12, v[14:15]
	v_ashrrev_i32_e32 v16, 31, v15
; %bb.37:                               ; %Flow145
	s_or_saveexec_b32 s1, s1
	v_dual_mov_b32 v51, v38 :: v_dual_mov_b32 v50, v37
	s_xor_b32 exec_lo, exec_lo, s1
; %bb.38:
	v_add3_u32 v50, v35, s4, v14
	v_dual_mov_b32 v15, v37 :: v_dual_mov_b32 v16, v38
	s_delay_alu instid0(VALU_DEP_2)
	v_ashrrev_i32_e32 v51, 31, v50
; %bb.39:
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[50:51], 3, v[50:51]
	v_lshlrev_b64 v[15:16], 3, v[15:16]
	s_add_i32 s1, s4, -1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v52, vcc_lo, v6, v50
	v_add_co_ci_u32_e32 v53, vcc_lo, v7, v51, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v54, vcc_lo, v6, v15
	v_add_co_ci_u32_e32 v55, vcc_lo, v7, v16, vcc_lo
	v_add_co_u32 v50, vcc_lo, v4, v50
	v_add_co_ci_u32_e32 v51, vcc_lo, v5, v51, vcc_lo
	v_add_co_u32 v15, vcc_lo, v4, v15
	v_add_co_ci_u32_e32 v16, vcc_lo, v5, v16, vcc_lo
	s_clause 0x1
	flat_load_b64 v[52:53], v[52:53]
	flat_load_b64 v[54:55], v[54:55]
	s_clause 0x1
	flat_load_b64 v[64:65], v[50:51]
	flat_load_b64 v[15:16], v[15:16]
	v_cmp_le_i32_e32 vcc_lo, s1, v14
	s_waitcnt vmcnt(2) lgkmcnt(2)
	v_add_f64 v[50:51], v[52:53], -v[54:55]
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f64 v[52:53], v[64:65], -v[15:16]
                                        ; implicit-def: $vgpr64
	s_and_saveexec_b32 s1, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s1, exec_lo, s1
; %bb.40:
	v_add_nc_u32_e32 v64, -1, v37
; %bb.41:                               ; %Flow143
	s_or_saveexec_b32 s1, s1
	v_dual_mov_b32 v15, v37 :: v_dual_mov_b32 v16, v38
	v_dual_mov_b32 v55, v22 :: v_dual_mov_b32 v54, v21
	s_xor_b32 exec_lo, exec_lo, s1
; %bb.42:
	v_dual_mov_b32 v64, v37 :: v_dual_add_nc_u32 v15, 1, v37
	v_add_co_u32 v54, vcc_lo, v21, 8
	v_add_co_ci_u32_e32 v55, vcc_lo, 0, v22, vcc_lo
	s_delay_alu instid0(VALU_DEP_3)
	v_ashrrev_i32_e32 v16, 31, v15
; %bb.43:                               ; %Flow144
	s_or_b32 exec_lo, exec_lo, s1
.LBB0_44:                               ; %Flow149
	s_or_saveexec_b32 s2, s0
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, R_d@rel32@lo+4
	s_addc_u32 s1, s1, R_d@rel32@hi+12
	s_getpc_b64 s[6:7]
	s_add_u32 s6, s6, Cv_d@rel32@lo+4
	s_addc_u32 s7, s7, Cv_d@rel32@hi+12
	s_getpc_b64 s[8:9]
	s_add_u32 s8, s8, mu0_d@rel32@lo+4
	s_addc_u32 s9, s9, mu0_d@rel32@hi+12
	s_getpc_b64 s[10:11]
	s_add_u32 s10, s10, T0_d@rel32@lo+4
	s_addc_u32 s11, s11, T0_d@rel32@hi+12
	s_getpc_b64 s[12:13]
	s_add_u32 s12, s12, Cp_d@rel32@lo+4
	s_addc_u32 s13, s13, Cp_d@rel32@hi+12
	s_getpc_b64 s[14:15]
	s_add_u32 s14, s14, Pr_d@rel32@lo+4
	s_addc_u32 s15, s15, Pr_d@rel32@hi+12
	s_xor_b32 exec_lo, exec_lo, s2
	s_cbranch_execz .LBB0_54
; %bb.45:
	s_mov_b32 s3, exec_lo
                                        ; implicit-def: $vgpr15_vgpr16
	v_cmpx_gt_i32_e32 1, v13
	s_xor_b32 s3, exec_lo, s3
; %bb.46:
	v_add_nc_u32_e32 v15, s4, v37
	s_delay_alu instid0(VALU_DEP_1)
	v_ashrrev_i32_e32 v16, 31, v15
; %bb.47:                               ; %Flow148
	s_or_saveexec_b32 s3, s3
	v_dual_mov_b32 v51, v38 :: v_dual_mov_b32 v50, v37
	s_xor_b32 exec_lo, exec_lo, s3
; %bb.48:
	v_subrev_nc_u32_e32 v12, s4, v35
	v_dual_mov_b32 v15, v37 :: v_dual_mov_b32 v16, v38
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v50, v12, v14
	v_ashrrev_i32_e32 v51, 31, v50
; %bb.49:
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[15:16], 3, v[15:16]
	v_lshlrev_b64 v[50:51], 3, v[50:51]
	s_mov_b32 s3, exec_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v52, vcc_lo, v6, v15
	v_add_co_ci_u32_e32 v53, vcc_lo, v7, v16, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v54, vcc_lo, v6, v50
	v_add_co_ci_u32_e32 v55, vcc_lo, v7, v51, vcc_lo
	v_add_co_u32 v15, vcc_lo, v4, v15
	v_add_co_ci_u32_e32 v16, vcc_lo, v5, v16, vcc_lo
	v_add_co_u32 v50, vcc_lo, v4, v50
	v_add_co_ci_u32_e32 v51, vcc_lo, v5, v51, vcc_lo
	s_clause 0x1
	flat_load_b64 v[52:53], v[52:53]
	flat_load_b64 v[54:55], v[54:55]
	s_clause 0x1
	flat_load_b64 v[15:16], v[15:16]
	flat_load_b64 v[64:65], v[50:51]
	s_waitcnt vmcnt(2) lgkmcnt(2)
	v_add_f64 v[50:51], v[52:53], -v[54:55]
                                        ; implicit-def: $vgpr54_vgpr55
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f64 v[52:53], v[15:16], -v[64:65]
                                        ; implicit-def: $vgpr15_vgpr16
	v_cmpx_gt_i32_e32 1, v14
	s_xor_b32 s3, exec_lo, s3
; %bb.50:
	v_add_nc_u32_e32 v15, 1, v37
	v_add_co_u32 v54, vcc_lo, v21, 8
	v_add_co_ci_u32_e32 v55, vcc_lo, 0, v22, vcc_lo
	s_delay_alu instid0(VALU_DEP_3)
	v_ashrrev_i32_e32 v16, 31, v15
; %bb.51:                               ; %Flow146
	s_or_saveexec_b32 s3, s3
	v_mov_b32_e32 v64, v37
	s_xor_b32 exec_lo, exec_lo, s3
; %bb.52:
	v_dual_mov_b32 v15, v37 :: v_dual_add_nc_u32 v64, -1, v37
	v_mov_b32_e32 v16, v38
	v_dual_mov_b32 v55, v22 :: v_dual_mov_b32 v54, v21
; %bb.53:                               ; %Flow147
	s_or_b32 exec_lo, exec_lo, s3
.LBB0_54:                               ; %Flow150
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s2
	v_ashrrev_i32_e32 v65, 31, v64
	v_lshlrev_b64 v[15:16], 3, v[15:16]
	s_load_b64 s[2:3], s[0:1], 0x0
	s_load_b64 s[6:7], s[6:7], 0x0
	s_load_b64 s[48:49], s[8:9], 0x0
	s_load_b64 s[50:51], s[10:11], 0x0
	s_load_b64 s[36:37], s[12:13], 0x0
	s_load_b64 s[8:9], s[14:15], 0x0
	s_mov_b32 s0, exec_lo
                                        ; implicit-def: $vgpr70_vgpr71
                                        ; implicit-def: $vgpr82_vgpr83
                                        ; implicit-def: $vgpr80_vgpr81
	v_lshlrev_b64 v[64:65], 3, v[64:65]
	v_add_co_u32 v15, vcc_lo, v6, v15
	v_add_co_ci_u32_e32 v16, vcc_lo, v7, v16, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v66, vcc_lo, v4, v64
	v_add_co_ci_u32_e32 v67, vcc_lo, v5, v65, vcc_lo
	v_add_co_u32 v68, vcc_lo, v6, v64
	v_add_co_ci_u32_e32 v69, vcc_lo, v7, v65, vcc_lo
	flat_load_b64 v[54:55], v[54:55]
	flat_load_b64 v[64:65], v[66:67]
	s_clause 0x1
	flat_load_b64 v[66:67], v[15:16]
	flat_load_b64 v[68:69], v[68:69]
                                        ; implicit-def: $vgpr15_vgpr16
	v_cmpx_ne_u32_e32 0, v13
	s_xor_b32 s0, exec_lo, s0
	s_cbranch_execz .LBB0_60
; %bb.55:
	s_add_i32 s1, s5, -1
                                        ; implicit-def: $vgpr70_vgpr71
                                        ; implicit-def: $vgpr15_vgpr16
                                        ; implicit-def: $vgpr82_vgpr83
                                        ; implicit-def: $vgpr80_vgpr81
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_ne_u32_e32 vcc_lo, s1, v13
	s_and_saveexec_b32 s1, vcc_lo
	s_xor_b32 s1, exec_lo, s1
	s_cbranch_execz .LBB0_57
; %bb.56:
	v_mad_u64_u32 v[15:16], null, s4, v13, s[4:5]
	s_lshl_b32 s10, s4, 1
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_subrev_nc_u32_e32 v12, s10, v15
	v_add_nc_u32_e32 v80, v15, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v82, v12, v14
	v_ashrrev_i32_e32 v81, 31, v80
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v83, 31, v82
	v_lshlrev_b64 v[15:16], 3, v[80:81]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[70:71], 3, v[82:83]
	v_add_co_u32 v15, vcc_lo, v6, v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v16, vcc_lo, v7, v16, vcc_lo
	v_add_co_u32 v70, vcc_lo, v6, v70
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v71, vcc_lo, v7, v71, vcc_lo
	s_clause 0x1
	flat_load_b64 v[84:85], v[15:16]
	flat_load_b64 v[70:71], v[70:71]
	v_add_f64 v[15:16], v[19:20], v[19:20]
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f64 v[70:71], v[84:85], -v[70:71]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_scale_f64 v[84:85], null, v[15:16], v[15:16], v[70:71]
	v_rcp_f64_e32 v[86:87], v[84:85]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[96:97], -v[84:85], v[86:87], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[86:87], v[86:87], v[96:97], v[86:87]
	v_fma_f64 v[96:97], -v[84:85], v[86:87], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f64 v[86:87], v[86:87], v[96:97], v[86:87]
	v_div_scale_f64 v[96:97], vcc_lo, v[70:71], v[15:16], v[70:71]
	v_mul_f64 v[98:99], v[96:97], v[86:87]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[84:85], -v[84:85], v[98:99], v[96:97]
	v_div_fmas_f64 v[84:85], v[84:85], v[86:87], v[98:99]
	s_delay_alu instid0(VALU_DEP_1)
	v_div_fixup_f64 v[70:71], v[84:85], v[15:16], v[70:71]
.LBB0_57:                               ; %Flow140
	s_and_not1_saveexec_b32 s1, s1
	s_cbranch_execz .LBB0_59
; %bb.58:
	v_add_nc_u32_e32 v12, -1, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[82:83], null, s4, v12, v[14:15]
	v_ashrrev_i32_e32 v83, 31, v82
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[15:16], 3, v[82:83]
	v_add_co_u32 v15, vcc_lo, v6, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v16, vcc_lo, v7, v16, vcc_lo
	flat_load_b64 v[15:16], v[15:16]
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f64 v[15:16], v[31:32], -v[15:16]
	v_div_scale_f64 v[70:71], null, v[19:20], v[19:20], v[15:16]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[80:81], v[70:71]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[84:85], -v[70:71], v[80:81], 1.0
	v_fma_f64 v[80:81], v[80:81], v[84:85], v[80:81]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[84:85], -v[70:71], v[80:81], 1.0
	v_fma_f64 v[80:81], v[80:81], v[84:85], v[80:81]
	v_div_scale_f64 v[84:85], vcc_lo, v[15:16], v[19:20], v[15:16]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[86:87], v[84:85], v[80:81]
	v_fma_f64 v[70:71], -v[70:71], v[86:87], v[84:85]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_fmas_f64 v[70:71], v[70:71], v[80:81], v[86:87]
	v_dual_mov_b32 v81, v38 :: v_dual_mov_b32 v80, v37
	v_div_fixup_f64 v[70:71], v[70:71], v[19:20], v[15:16]
	v_dual_mov_b32 v15, v19 :: v_dual_mov_b32 v16, v20
.LBB0_59:                               ; %Flow141
	s_or_b32 exec_lo, exec_lo, s1
.LBB0_60:                               ; %Flow142
	s_and_not1_saveexec_b32 s0, s0
	s_cbranch_execz .LBB0_62
; %bb.61:
	v_ashrrev_i32_e32 v15, 31, v14
	v_add_nc_u32_e32 v80, s4, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[82:83], 3, v[14:15]
	v_ashrrev_i32_e32 v81, 31, v80
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[70:71], 3, v[80:81]
	v_add_co_u32 v70, vcc_lo, v6, v70
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v71, vcc_lo, v7, v71, vcc_lo
	v_add_co_u32 v82, vcc_lo, v6, v82
	v_add_co_ci_u32_e32 v83, vcc_lo, v7, v83, vcc_lo
	s_clause 0x1
	flat_load_b64 v[70:71], v[70:71]
	flat_load_b64 v[82:83], v[82:83]
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f64 v[70:71], v[70:71], -v[82:83]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_scale_f64 v[82:83], null, v[19:20], v[19:20], v[70:71]
	v_rcp_f64_e32 v[84:85], v[82:83]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[86:87], -v[82:83], v[84:85], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[84:85], v[84:85], v[86:87], v[84:85]
	v_fma_f64 v[86:87], -v[82:83], v[84:85], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f64 v[84:85], v[84:85], v[86:87], v[84:85]
	v_div_scale_f64 v[86:87], vcc_lo, v[70:71], v[19:20], v[70:71]
	v_mul_f64 v[96:97], v[86:87], v[84:85]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[82:83], -v[82:83], v[96:97], v[86:87]
	v_div_fmas_f64 v[82:83], v[82:83], v[84:85], v[96:97]
	s_delay_alu instid0(VALU_DEP_1)
	v_div_fixup_f64 v[70:71], v[82:83], v[19:20], v[70:71]
	v_dual_mov_b32 v83, v15 :: v_dual_mov_b32 v82, v14
	v_dual_mov_b32 v15, v19 :: v_dual_mov_b32 v16, v20
.LBB0_62:
	s_or_b32 exec_lo, exec_lo, s0
	v_lshlrev_b64 v[80:81], 3, v[80:81]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[82:83], 3, v[82:83]
	s_mov_b32 s0, exec_lo
	v_add_co_u32 v80, vcc_lo, v4, v80
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v81, vcc_lo, v5, v81, vcc_lo
	v_add_co_u32 v82, vcc_lo, v4, v82
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v83, vcc_lo, v5, v83, vcc_lo
	s_clause 0x1
	flat_load_b64 v[84:85], v[80:81]
	flat_load_b64 v[86:87], v[82:83]
                                        ; implicit-def: $vgpr80_vgpr81
                                        ; implicit-def: $vgpr82_vgpr83
	v_cmpx_ne_u32_e32 0, v14
	s_xor_b32 s0, exec_lo, s0
	s_cbranch_execz .LBB0_68
; %bb.63:
	s_add_i32 s1, s4, -1
	v_add_nc_u32_e32 v35, -1, v37
	v_cmp_ne_u32_e32 vcc_lo, s1, v14
                                        ; implicit-def: $vgpr80_vgpr81
                                        ; implicit-def: $vgpr82_vgpr83
	s_and_saveexec_b32 s1, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s1, exec_lo, s1
	s_cbranch_execz .LBB0_65
; %bb.64:
	v_add_co_u32 v4, vcc_lo, -8, v21
	v_add_co_ci_u32_e32 v5, vcc_lo, -1, v22, vcc_lo
	v_add_f64 v[82:83], v[17:18], v[17:18]
	v_add_nc_u32_e32 v37, 1, v37
	s_clause 0x1
	flat_load_b64 v[38:39], v[21:22] offset:8
	flat_load_b64 v[4:5], v[4:5]
	v_ashrrev_i32_e32 v36, 31, v35
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f64 v[4:5], v[38:39], -v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_scale_f64 v[38:39], null, v[82:83], v[82:83], v[4:5]
	v_rcp_f64_e32 v[80:81], v[38:39]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[96:97], -v[38:39], v[80:81], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[80:81], v[80:81], v[96:97], v[80:81]
	v_fma_f64 v[96:97], -v[38:39], v[80:81], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f64 v[80:81], v[80:81], v[96:97], v[80:81]
	v_div_scale_f64 v[96:97], vcc_lo, v[4:5], v[82:83], v[4:5]
	v_mul_f64 v[98:99], v[96:97], v[80:81]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[38:39], -v[38:39], v[98:99], v[96:97]
	v_div_fmas_f64 v[38:39], v[38:39], v[80:81], v[98:99]
	s_delay_alu instid0(VALU_DEP_1)
	v_div_fixup_f64 v[80:81], v[38:39], v[82:83], v[4:5]
	v_ashrrev_i32_e32 v38, 31, v37
.LBB0_65:                               ; %Flow
	s_and_not1_saveexec_b32 s1, s1
	s_cbranch_execz .LBB0_67
; %bb.66:
	v_add_co_u32 v4, vcc_lo, -8, v21
	v_add_co_ci_u32_e32 v5, vcc_lo, -1, v22, vcc_lo
	v_ashrrev_i32_e32 v36, 31, v35
	flat_load_b64 v[4:5], v[4:5]
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f64 v[4:5], v[29:30], -v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_scale_f64 v[80:81], null, v[17:18], v[17:18], v[4:5]
	v_rcp_f64_e32 v[82:83], v[80:81]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[96:97], -v[80:81], v[82:83], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[82:83], v[82:83], v[96:97], v[82:83]
	v_fma_f64 v[96:97], -v[80:81], v[82:83], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f64 v[82:83], v[82:83], v[96:97], v[82:83]
	v_div_scale_f64 v[96:97], vcc_lo, v[4:5], v[17:18], v[4:5]
	v_mul_f64 v[98:99], v[96:97], v[82:83]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[80:81], -v[80:81], v[98:99], v[96:97]
	v_div_fmas_f64 v[80:81], v[80:81], v[82:83], v[98:99]
	v_dual_mov_b32 v83, v18 :: v_dual_mov_b32 v82, v17
	s_delay_alu instid0(VALU_DEP_2)
	v_div_fixup_f64 v[80:81], v[80:81], v[17:18], v[4:5]
.LBB0_67:                               ; %Flow138
	s_or_b32 exec_lo, exec_lo, s1
                                        ; implicit-def: $vgpr4_vgpr5
.LBB0_68:                               ; %Flow139
	s_and_not1_saveexec_b32 s0, s0
	s_cbranch_execz .LBB0_70
; %bb.69:
	v_ashrrev_i32_e32 v36, 31, v35
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[37:38], 3, v[35:36]
	v_add_co_u32 v4, vcc_lo, v4, v37
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v5, vcc_lo, v5, v38, vcc_lo
	flat_load_b128 v[80:83], v[4:5]
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f64 v[4:5], v[82:83], -v[80:81]
	v_div_scale_f64 v[37:38], null, v[17:18], v[17:18], v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[80:81], v[37:38]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[82:83], -v[37:38], v[80:81], 1.0
	v_fma_f64 v[80:81], v[80:81], v[82:83], v[80:81]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[82:83], -v[37:38], v[80:81], 1.0
	v_fma_f64 v[80:81], v[80:81], v[82:83], v[80:81]
	v_div_scale_f64 v[82:83], vcc_lo, v[4:5], v[17:18], v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[96:97], v[82:83], v[80:81]
	v_fma_f64 v[37:38], -v[37:38], v[96:97], v[82:83]
	v_dual_mov_b32 v83, v18 :: v_dual_mov_b32 v82, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f64 v[37:38], v[37:38], v[80:81], v[96:97]
	v_div_fixup_f64 v[80:81], v[37:38], v[17:18], v[4:5]
	v_add_nc_u32_e32 v37, 1, v35
	s_delay_alu instid0(VALU_DEP_1)
	v_ashrrev_i32_e32 v38, 31, v37
.LBB0_70:                               ; %_Z15shearParametersPdS_dbiiddS_.exit
	s_or_b32 exec_lo, exec_lo, s0
	s_waitcnt vmcnt(8) lgkmcnt(0)
	v_div_scale_f64 v[4:5], null, s[50:51], s[50:51], v[27:28]
	v_div_scale_f64 v[100:101], vcc_lo, v[27:28], s[50:51], v[27:28]
	s_mov_b32 s10, 0x55555555
	s_mov_b32 s11, 0x3fe55555
	s_mov_b32 s12, 0x968915a9
	s_mov_b32 s14, 0x4222de17
	s_mov_b32 s13, 0x3fba6564
	s_mov_b32 s15, 0x3fbdee67
	s_mov_b32 s16, 0x3abe935a
	s_mov_b32 s17, 0x3fbe25e4
	s_mov_b32 s18, 0x47e6c9c2
	s_mov_b32 s19, 0x3fc110ef
	s_mov_b32 s20, 0xcfa74449
	s_mov_b32 s21, 0x3fc3b13b
	s_mov_b32 s22, 0x71bf3c30
	s_mov_b32 s23, 0x3fc745d1
	s_mov_b32 s24, 0x1c7792ce
	s_mov_b32 s25, 0x3fcc71c7
	s_mov_b32 s26, 0x924920da
	s_mov_b32 s27, 0x3fd24924
	s_mov_b32 s38, 0x9999999c
	s_mov_b32 s39, 0x3fd99999
	s_mov_b32 s29, 0xbfe55555
	s_mov_b32 s28, s10
	s_mov_b32 s34, 0xd5df274d
	s_mov_b32 s35, 0x3c8543b0
	s_mov_b32 s30, 0xfefa39ef
	s_mov_b32 s31, 0x3fe62e42
	s_mov_b32 s42, 0x3b39803f
	s_mov_b32 s43, 0x3c7abc9e
	s_mov_b32 s40, 0x652b82fe
	s_mov_b32 s41, 0x3ff71547
	s_mov_b32 s45, 0xbfe62e42
	s_mov_b32 s44, s30
	s_mov_b32 s47, 0xbc7abc9e
	s_mov_b32 s46, s42
	s_delay_alu instid0(VALU_DEP_2)
	v_rcp_f64_e32 v[96:97], v[4:5]
	s_mov_b32 s52, 0xfca7ab0c
	s_mov_b32 s54, 0x6a5dcb37
	s_mov_b32 s53, 0x3e928af3
	s_mov_b32 s55, 0x3e5ade15
	s_mov_b32 s56, 0x623fde64
	s_mov_b32 s57, 0x3ec71dee
	s_mov_b32 s58, 0x7c89e6b0
	s_mov_b32 s59, 0x3efa0199
	s_mov_b32 s62, 0x14761f6e
	s_mov_b32 s63, 0x3f2a01a0
	s_mov_b32 s64, 0x1852b7b0
	s_mov_b32 s65, 0x3f56c16c
	s_mov_b32 s66, 0x11122322
	s_mov_b32 s67, 0x3f811111
	s_mov_b32 s68, 0x555502a1
	s_mov_b32 s69, 0x3fa55555
	s_mov_b32 s70, 0x55555511
	s_mov_b32 s71, 0x3fc55555
	s_mov_b32 s60, 11
	s_mov_b32 s61, 0x3fe00000
	v_lshlrev_b64 v[37:38], 3, v[37:38]
	v_lshlrev_b64 v[35:36], 3, v[35:36]
	s_waitcnt vmcnt(6)
	v_mul_f64 v[31:32], v[31:32], v[31:32]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[98:99], -v[4:5], v[96:97], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[96:97], v[96:97], v[98:99], v[96:97]
	v_fma_f64 v[98:99], -v[4:5], v[96:97], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[96:97], v[96:97], v[98:99], v[96:97]
	v_mul_f64 v[98:99], v[100:101], v[96:97]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[4:5], -v[4:5], v[98:99], v[100:101]
	v_div_fmas_f64 v[4:5], v[4:5], v[96:97], v[98:99]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f64 v[4:5], v[4:5], s[50:51], v[27:28]
	v_frexp_mant_f64_e64 v[96:97], |v[4:5]|
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_gt_f64_e32 vcc_lo, s[10:11], v[96:97]
	v_cndmask_b32_e64 v12, 0, 1, vcc_lo
	v_ldexp_f64 v[96:97], v[96:97], v12
	v_frexp_exp_i32_f64_e32 v12, v[4:5]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[98:99], v[96:97], 1.0
	v_add_f64 v[112:113], v[96:97], -1.0
	v_subrev_co_ci_u32_e32 v12, vcc_lo, 0, v12, vcc_lo
	v_cmp_eq_f64_e32 vcc_lo, 1.0, v[4:5]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[100:101], v[98:99]
	v_add_f64 v[114:115], v[98:99], -1.0
	v_add_f64 v[96:97], v[96:97], -v[114:115]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[102:103], -v[98:99], v[100:101], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[100:101], v[102:103], v[100:101], v[100:101]
	v_fma_f64 v[102:103], -v[98:99], v[100:101], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[100:101], v[102:103], v[100:101], v[100:101]
	v_mul_f64 v[102:103], v[112:113], v[100:101]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[116:117], v[98:99], v[102:103]
	v_fma_f64 v[98:99], v[102:103], v[98:99], -v[116:117]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[96:97], v[102:103], v[96:97], v[98:99]
	v_add_f64 v[98:99], v[116:117], v[96:97]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[114:115], v[112:113], -v[98:99]
	v_add_f64 v[116:117], v[98:99], -v[116:117]
	v_add_f64 v[112:113], v[112:113], -v[114:115]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[96:97], v[116:117], -v[96:97]
	v_add_f64 v[98:99], v[112:113], -v[98:99]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[96:97], v[96:97], v[98:99]
	v_add_f64 v[96:97], v[114:115], v[96:97]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[96:97], v[100:101], v[96:97]
	v_add_f64 v[98:99], v[102:103], v[96:97]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[100:101], v[98:99], -v[102:103]
	v_mul_f64 v[102:103], v[98:99], v[98:99]
	v_add_f64 v[96:97], v[96:97], -v[100:101]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[100:101], v[98:99], v[98:99], -v[102:103]
	v_add_f64 v[112:113], v[96:97], v[96:97]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[100:101], v[98:99], v[112:113], v[100:101]
	v_add_f64 v[112:113], v[102:103], v[100:101]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_fma_f64 v[114:115], v[112:113], s[14:15], s[12:13]
	v_add_f64 v[102:103], v[112:113], -v[102:103]
	v_mul_f64 v[128:129], v[98:99], v[112:113]
	v_fma_f64 v[114:115], v[112:113], v[114:115], s[16:17]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[100:101], v[100:101], -v[102:103]
	v_fma_f64 v[130:131], v[112:113], v[98:99], -v[128:129]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[114:115], v[112:113], v[114:115], s[18:19]
	v_fma_f64 v[114:115], v[112:113], v[114:115], s[20:21]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[114:115], v[112:113], v[114:115], s[22:23]
	v_fma_f64 v[114:115], v[112:113], v[114:115], s[24:25]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[114:115], v[112:113], v[114:115], s[26:27]
	v_fma_f64 v[114:115], v[112:113], v[114:115], s[38:39]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[116:117], v[112:113], v[114:115]
	v_fma_f64 v[102:103], v[112:113], v[114:115], -v[116:117]
	v_fma_f64 v[112:113], v[112:113], v[96:97], v[130:131]
	v_ldexp_f64 v[96:97], v[96:97], 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[102:103], v[100:101], v[114:115], v[102:103]
	v_fma_f64 v[100:101], v[100:101], v[98:99], v[112:113]
	v_ldexp_f64 v[98:99], v[98:99], 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[114:115], v[116:117], v[102:103]
	v_add_f64 v[116:117], v[114:115], -v[116:117]
	v_add_f64 v[118:119], v[114:115], s[10:11]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[102:103], v[102:103], -v[116:117]
	v_add_f64 v[116:117], v[118:119], s[28:29]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[102:103], v[102:103], s[34:35]
	v_add_f64 v[114:115], v[114:115], -v[116:117]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[102:103], v[102:103], v[114:115]
	v_add_f64 v[114:115], v[128:129], v[100:101]
	v_add_f64 v[112:113], v[118:119], v[102:103]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[128:129], v[114:115], -v[128:129]
	v_add_f64 v[116:117], v[118:119], -v[112:113]
	v_mul_f64 v[118:119], v[114:115], v[112:113]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[100:101], v[100:101], -v[128:129]
	v_add_f64 v[102:103], v[102:103], v[116:117]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[116:117], v[114:115], v[112:113], -v[118:119]
	v_fma_f64 v[102:103], v[114:115], v[102:103], v[116:117]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_fma_f64 v[100:101], v[100:101], v[112:113], v[102:103]
	v_cvt_f64_i32_e32 v[112:113], v12
	v_mov_b32_e32 v12, 0x3ff00000
	v_add_f64 v[102:103], v[118:119], v[100:101]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_add_f64 v[114:115], v[102:103], -v[118:119]
	v_add_f64 v[116:117], v[98:99], v[102:103]
	v_mul_f64 v[118:119], v[112:113], s[30:31]
	v_add_f64 v[100:101], v[100:101], -v[114:115]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[98:99], v[116:117], -v[98:99]
	v_fma_f64 v[114:115], v[112:113], s[30:31], -v[118:119]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[96:97], v[96:97], v[100:101]
	v_add_f64 v[98:99], v[102:103], -v[98:99]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[100:101], v[112:113], s[42:43], v[114:115]
	v_add_f64 v[96:97], v[96:97], v[98:99]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[98:99], v[118:119], v[100:101]
	v_add_f64 v[102:103], v[116:117], v[96:97]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[118:119], v[98:99], -v[118:119]
	v_add_f64 v[112:113], v[98:99], v[102:103]
	v_add_f64 v[116:117], v[102:103], -v[116:117]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[100:101], v[100:101], -v[118:119]
	v_add_f64 v[114:115], v[112:113], -v[98:99]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[96:97], v[96:97], -v[116:117]
	v_add_f64 v[128:129], v[112:113], -v[114:115]
	v_add_f64 v[102:103], v[102:103], -v[114:115]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[114:115], v[100:101], v[96:97]
	v_add_f64 v[98:99], v[98:99], -v[128:129]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[98:99], v[102:103], v[98:99]
	v_add_f64 v[102:103], v[114:115], -v[100:101]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[98:99], v[114:115], v[98:99]
	v_add_f64 v[114:115], v[114:115], -v[102:103]
	v_add_f64 v[96:97], v[96:97], -v[102:103]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[116:117], v[112:113], v[98:99]
	v_add_f64 v[100:101], v[100:101], -v[114:115]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[102:103], v[116:117], -v[112:113]
	v_add_f64 v[96:97], v[96:97], v[100:101]
	v_dual_mov_b32 v100, 0 :: v_dual_cndmask_b32 v101, 0x3ff80000, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[98:99], v[98:99], -v[102:103]
	v_add_f64 v[96:97], v[96:97], v[98:99]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[98:99], v[116:117], v[96:97]
	v_add_f64 v[102:103], v[98:99], -v[116:117]
	v_mul_f64 v[112:113], v[100:101], v[98:99]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[96:97], v[96:97], -v[102:103]
	v_fma_f64 v[98:99], v[100:101], v[98:99], -v[112:113]
	v_cmp_class_f64_e64 vcc_lo, v[112:113], 0x204
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[96:97], v[100:101], v[96:97], v[98:99]
	v_add_f64 v[98:99], v[112:113], v[96:97]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v103, v99, v113 :: v_dual_cndmask_b32 v102, v98, v112
	v_add_f64 v[98:99], v[98:99], -v[112:113]
	v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[102:103]|
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[96:97], v[96:97], -v[98:99]
	v_trunc_f64_e32 v[98:99], v[100:101]
	v_cndmask_b32_e32 v97, 0, v97, vcc_lo
	v_mul_f64 v[114:115], v[102:103], s[40:41]
	v_cmp_nlt_f64_e64 s0, 0x40900000, v[102:103]
	v_cmp_ngt_f64_e64 s1, 0xc090cc00, v[102:103]
	v_cndmask_b32_e32 v96, 0, v96, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_rndne_f64_e32 v[114:115], v[114:115]
	s_and_b32 vcc_lo, s1, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f64 v[116:117], v[114:115], s[44:45], v[102:103]
	v_cvt_i32_f64_e32 v12, v[114:115]
	v_fma_f64 v[116:117], v[114:115], s[46:47], v[116:117]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[118:119], v[116:117], s[54:55], s[52:53]
	v_fma_f64 v[118:119], v[116:117], v[118:119], s[56:57]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[118:119], v[116:117], v[118:119], s[58:59]
	v_fma_f64 v[118:119], v[116:117], v[118:119], s[62:63]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[118:119], v[116:117], v[118:119], s[64:65]
	v_fma_f64 v[118:119], v[116:117], v[118:119], s[66:67]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[118:119], v[116:117], v[118:119], s[68:69]
	v_fma_f64 v[118:119], v[116:117], v[118:119], s[70:71]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[118:119], v[116:117], v[118:119], s[60:61]
	v_fma_f64 v[118:119], v[116:117], v[118:119], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[114:115], v[116:117], v[118:119], 1.0
	v_ldexp_f64 v[112:113], v[114:115], v12
	v_mul_f64 v[114:115], v[100:101], 0.5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v12, 0x7ff00000, v113, s0
	v_trunc_f64_e32 v[102:103], v[114:115]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cndmask_b32_e32 v112, 0, v112, vcc_lo
	v_cmp_eq_f64_e32 vcc_lo, v[98:99], v[100:101]
	v_cndmask_b32_e64 v113, 0, v12, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_fma_f64 v[96:97], v[112:113], v[96:97], v[112:113]
	v_cmp_class_f64_e64 s1, v[112:113], 0x204
	v_cmp_neq_f64_e64 s0, v[102:103], v[114:115]
	v_cndmask_b32_e64 v97, v97, v113, s1
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v96, v96, v112, s1
	v_cmp_class_f64_e64 s1, v[4:5], 0x204
	v_cndmask_b32_e32 v98, 0, v96, vcc_lo
	s_and_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v39, 0x3ff00000, v5, s0
	v_cndmask_b32_e64 v12, 0, v5, s0
	v_cmp_eq_f64_e64 s0, 0, v[4:5]
	v_bfi_b32 v39, 0x7fffffff, v97, v39
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cndmask_b32_e32 v97, 0x7ff80000, v39, vcc_lo
	v_cmp_gt_f64_e32 vcc_lo, 0, v[4:5]
	v_cndmask_b32_e64 v99, 0x7ff00000, 0, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_bfi_b32 v12, 0x7fffffff, v99, v12
	v_dual_cndmask_b32 v96, v96, v98 :: v_dual_cndmask_b32 v39, v39, v97
	s_or_b32 vcc_lo, s0, s1
	v_add_f64 v[98:99], 0x405b8000, v[27:28]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v12, v39, v12, vcc_lo
	v_cndmask_b32_e64 v39, v96, 0, vcc_lo
	v_cmp_o_f64_e32 vcc_lo, v[4:5], v[4:5]
	v_add_f64 v[96:97], 0x405b8000, s[50:51]
	v_readlane_b32 s51, v40, 17
	v_readlane_b32 s50, v40, 16
	v_cndmask_b32_e32 v4, 0, v39, vcc_lo
	v_cndmask_b32_e32 v5, 0x7ff80000, v12, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_mul_f64 v[4:5], s[48:49], v[4:5]
	v_readlane_b32 s49, v40, 15
	v_readlane_b32 s48, v40, 14
	v_mul_f64 v[4:5], v[96:97], v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f64 v[96:97], null, v[98:99], v[98:99], v[4:5]
	v_div_scale_f64 v[112:113], vcc_lo, v[4:5], v[98:99], v[4:5]
	v_rcp_f64_e32 v[100:101], v[96:97]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[102:103], -v[96:97], v[100:101], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[100:101], v[100:101], v[102:103], v[100:101]
	v_fma_f64 v[102:103], -v[96:97], v[100:101], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[100:101], v[100:101], v[102:103], v[100:101]
	v_mul_f64 v[102:103], v[112:113], v[100:101]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[96:97], -v[96:97], v[102:103], v[112:113]
	v_div_fmas_f64 v[96:97], v[96:97], v[100:101], v[102:103]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_fixup_f64 v[96:97], v[96:97], v[98:99], v[4:5]
	v_mul_f64 v[4:5], s[2:3], v[27:28]
	v_mul_f64 v[98:99], v[96:97], -s[36:37]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_div_scale_f64 v[102:103], null, v[4:5], v[4:5], v[48:49]
	v_readlane_b32 s37, v40, 3
	v_readlane_b32 s36, v40, 2
	v_div_scale_f64 v[100:101], null, s[8:9], s[8:9], v[98:99]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_rcp_f64_e32 v[114:115], v[102:103]
	v_div_scale_f64 v[128:129], vcc_lo, v[98:99], s[8:9], v[98:99]
	v_rcp_f64_e32 v[112:113], v[100:101]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[118:119], -v[102:103], v[114:115], 1.0
	v_fma_f64 v[116:117], -v[100:101], v[112:113], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[114:115], v[114:115], v[118:119], v[114:115]
	v_fma_f64 v[112:113], v[112:113], v[116:117], v[112:113]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[118:119], -v[102:103], v[114:115], 1.0
	v_fma_f64 v[116:117], -v[100:101], v[112:113], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[114:115], v[114:115], v[118:119], v[114:115]
	v_fma_f64 v[112:113], v[112:113], v[116:117], v[112:113]
	v_div_scale_f64 v[116:117], s0, v[48:49], v[4:5], v[48:49]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[118:119], v[128:129], v[112:113]
	v_mul_f64 v[130:131], v[116:117], v[114:115]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[100:101], -v[100:101], v[118:119], v[128:129]
	v_fma_f64 v[102:103], -v[102:103], v[130:131], v[116:117]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_fmas_f64 v[100:101], v[100:101], v[112:113], v[118:119]
	s_mov_b32 vcc_lo, s0
	v_div_fmas_f64 v[102:103], v[102:103], v[114:115], v[130:131]
	v_add_co_u32 v37, vcc_lo, v6, v37
	v_add_co_ci_u32_e32 v38, vcc_lo, v7, v38, vcc_lo
	v_add_co_u32 v6, vcc_lo, v6, v35
	v_add_co_ci_u32_e32 v7, vcc_lo, v7, v36, vcc_lo
	v_add_co_u32 v35, vcc_lo, v0, v25
	v_add_co_ci_u32_e32 v36, vcc_lo, v1, v26, vcc_lo
	v_div_fixup_f64 v[4:5], v[102:103], v[4:5], v[48:49]
	s_clause 0x1
	flat_load_b64 v[37:38], v[37:38]
	flat_load_b64 v[102:103], v[6:7]
	v_mul_f64 v[48:49], v[4:5], v[29:30]
	v_fma_f64 v[29:30], v[29:30], v[29:30], v[31:32]
	s_waitcnt vmcnt(6)
	v_add_f64 v[31:32], v[54:55], -v[64:65]
	flat_store_b64 v[35:36], v[48:49]
	flat_load_b64 v[48:49], v[21:22]
	v_mul_f64 v[29:30], v[29:30], 0.5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_fma_f64 v[27:28], v[27:28], s[6:7], v[29:30]
	s_waitcnt vmcnt(1) lgkmcnt(2)
	v_add_f64 v[37:38], v[37:38], -v[102:103]
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_frexp_mant_f64_e64 v[6:7], |v[48:49]|
	v_cmp_gt_f64_e32 vcc_lo, s[10:11], v[6:7]
	v_cndmask_b32_e64 v12, 0, 1, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_ldexp_f64 v[6:7], v[6:7], v12
	v_frexp_exp_i32_f64_e32 v12, v[48:49]
	v_add_f64 v[35:36], v[6:7], 1.0
	v_add_f64 v[116:117], v[6:7], -1.0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_subrev_co_ci_u32_e32 v12, vcc_lo, 0, v12, vcc_lo
	v_rcp_f64_e32 v[112:113], v[35:36]
	v_add_f64 v[118:119], v[35:36], -1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_f64 v[6:7], v[6:7], -v[118:119]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[114:115], -v[35:36], v[112:113], 1.0
	v_fma_f64 v[112:113], v[114:115], v[112:113], v[112:113]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[114:115], -v[35:36], v[112:113], 1.0
	v_fma_f64 v[112:113], v[114:115], v[112:113], v[112:113]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[114:115], v[116:117], v[112:113]
	v_mul_f64 v[128:129], v[35:36], v[114:115]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[35:36], v[114:115], v[35:36], -v[128:129]
	v_fma_f64 v[6:7], v[114:115], v[6:7], v[35:36]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[35:36], v[128:129], v[6:7]
	v_add_f64 v[118:119], v[116:117], -v[35:36]
	v_add_f64 v[128:129], v[35:36], -v[128:129]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[116:117], v[116:117], -v[118:119]
	v_add_f64 v[6:7], v[128:129], -v[6:7]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[35:36], v[116:117], -v[35:36]
	v_add_f64 v[6:7], v[6:7], v[35:36]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[6:7], v[118:119], v[6:7]
	v_mul_f64 v[6:7], v[112:113], v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[35:36], v[114:115], v[6:7]
	v_add_f64 v[112:113], v[35:36], -v[114:115]
	v_mul_f64 v[114:115], v[35:36], v[35:36]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[6:7], v[6:7], -v[112:113]
	v_fma_f64 v[112:113], v[35:36], v[35:36], -v[114:115]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[116:117], v[6:7], v[6:7]
	v_fma_f64 v[112:113], v[35:36], v[116:117], v[112:113]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[116:117], v[114:115], v[112:113]
	v_fma_f64 v[118:119], v[116:117], s[14:15], s[12:13]
	v_add_f64 v[114:115], v[116:117], -v[114:115]
	v_mul_f64 v[132:133], v[35:36], v[116:117]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[118:119], v[116:117], v[118:119], s[16:17]
	v_add_f64 v[112:113], v[112:113], -v[114:115]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[118:119], v[116:117], v[118:119], s[18:19]
	v_fma_f64 v[118:119], v[116:117], v[118:119], s[20:21]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[118:119], v[116:117], v[118:119], s[22:23]
	v_fma_f64 v[118:119], v[116:117], v[118:119], s[24:25]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[118:119], v[116:117], v[118:119], s[26:27]
	v_fma_f64 v[118:119], v[116:117], v[118:119], s[38:39]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[128:129], v[116:117], v[118:119]
	v_fma_f64 v[114:115], v[116:117], v[118:119], -v[128:129]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[114:115], v[112:113], v[118:119], v[114:115]
	v_add_f64 v[118:119], v[128:129], v[114:115]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[130:131], v[118:119], s[10:11]
	v_add_f64 v[128:129], v[118:119], -v[128:129]
	v_add_f64 v[134:135], v[130:131], s[28:29]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[114:115], v[114:115], -v[128:129]
	v_fma_f64 v[128:129], v[116:117], v[35:36], -v[132:133]
	v_add_f64 v[118:119], v[118:119], -v[134:135]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[114:115], v[114:115], s[34:35]
	v_fma_f64 v[116:117], v[116:117], v[6:7], v[128:129]
	v_ldexp_f64 v[6:7], v[6:7], 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[114:115], v[114:115], v[118:119]
	v_fma_f64 v[112:113], v[112:113], v[35:36], v[116:117]
	v_ldexp_f64 v[35:36], v[35:36], 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[116:117], v[130:131], v[114:115]
	v_add_f64 v[118:119], v[132:133], v[112:113]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[128:129], v[130:131], -v[116:117]
	v_mul_f64 v[130:131], v[118:119], v[116:117]
	v_add_f64 v[132:133], v[118:119], -v[132:133]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[114:115], v[114:115], v[128:129]
	v_fma_f64 v[128:129], v[118:119], v[116:117], -v[130:131]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[112:113], v[112:113], -v[132:133]
	v_fma_f64 v[114:115], v[118:119], v[114:115], v[128:129]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f64 v[112:113], v[112:113], v[116:117], v[114:115]
	v_cvt_f64_i32_e32 v[116:117], v12
	v_add_f64 v[114:115], v[130:131], v[112:113]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f64 v[118:119], v[35:36], v[114:115]
	v_add_f64 v[128:129], v[114:115], -v[130:131]
	v_mul_f64 v[130:131], v[116:117], s[30:31]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[35:36], v[118:119], -v[35:36]
	v_add_f64 v[112:113], v[112:113], -v[128:129]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[128:129], v[116:117], s[30:31], -v[130:131]
	v_add_f64 v[35:36], v[114:115], -v[35:36]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[6:7], v[6:7], v[112:113]
	v_fma_f64 v[112:113], v[116:117], s[42:43], v[128:129]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[6:7], v[6:7], v[35:36]
	v_add_f64 v[35:36], v[130:131], v[112:113]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[114:115], v[118:119], v[6:7]
	v_add_f64 v[130:131], v[35:36], -v[130:131]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[116:117], v[35:36], v[114:115]
	v_add_f64 v[118:119], v[114:115], -v[118:119]
	v_add_f64 v[112:113], v[112:113], -v[130:131]
	v_div_scale_f64 v[130:131], null, v[82:83], v[82:83], v[37:38]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[128:129], v[116:117], -v[35:36]
	v_add_f64 v[118:119], v[6:7], -v[118:119]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[132:133], v[116:117], -v[128:129]
	v_add_f64 v[6:7], v[114:115], -v[128:129]
	v_add_f64 v[114:115], v[112:113], v[118:119]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f64 v[35:36], v[35:36], -v[132:133]
	v_rcp_f64_e32 v[132:133], v[130:131]
	v_add_f64 v[35:36], v[6:7], v[35:36]
	v_add_f64 v[6:7], v[84:85], -v[86:87]
	s_delay_alu instid0(VALU_DEP_4)
	v_add_f64 v[84:85], v[114:115], -v[112:113]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[144:145], -v[130:131], v[132:133], 1.0
	v_add_f64 v[35:36], v[114:115], v[35:36]
	v_div_scale_f64 v[86:87], null, v[15:16], v[15:16], v[6:7]
	v_add_f64 v[102:103], v[114:115], -v[84:85]
	v_add_f64 v[84:85], v[118:119], -v[84:85]
	v_div_scale_f64 v[118:119], null, v[19:20], v[19:20], v[52:53]
	v_fma_f64 v[132:133], v[132:133], v[144:145], v[132:133]
	v_add_f64 v[114:115], v[116:117], v[35:36]
	v_rcp_f64_e32 v[128:129], v[86:87]
	v_add_f64 v[102:103], v[112:113], -v[102:103]
	s_delay_alu instid0(VALU_DEP_2)
	v_add_f64 v[112:113], v[114:115], -v[116:117]
	v_div_scale_f64 v[116:117], null, v[19:20], v[19:20], v[50:51]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[134:135], -v[86:87], v[128:129], 1.0
	v_add_f64 v[84:85], v[84:85], v[102:103]
	v_add_f64 v[35:36], v[35:36], -v[112:113]
	v_rcp_f64_e32 v[112:113], v[118:119]
	v_rcp_f64_e32 v[102:103], v[116:117]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[128:129], v[128:129], v[134:135], v[128:129]
	v_add_f64 v[35:36], v[84:85], v[35:36]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[134:135], -v[118:119], v[112:113], 1.0
	v_fma_f64 v[144:145], -v[86:87], v[128:129], 1.0
	v_fma_f64 v[84:85], -v[116:117], v[102:103], 1.0
	v_add_f64 v[146:147], v[114:115], v[35:36]
	s_delay_alu instid0(VALU_DEP_4)
	v_fma_f64 v[112:113], v[112:113], v[134:135], v[112:113]
	v_fma_f64 v[134:135], -v[130:131], v[132:133], 1.0
	v_fma_f64 v[128:129], v[128:129], v[144:145], v[128:129]
	v_fma_f64 v[84:85], v[102:103], v[84:85], v[102:103]
	v_div_scale_f64 v[102:103], vcc_lo, v[6:7], v[15:16], v[6:7]
	v_add_f64 v[114:115], v[146:147], -v[114:115]
	v_add_f64 v[144:145], v[146:147], v[146:147]
	v_fma_f64 v[132:133], v[132:133], v[134:135], v[132:133]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mul_f64 v[134:135], v[102:103], v[128:129]
	v_add_f64 v[35:36], v[35:36], -v[114:115]
	s_delay_alu instid0(VALU_DEP_4)
	v_fma_f64 v[114:115], v[146:147], 2.0, -v[144:145]
	v_div_scale_f64 v[146:147], s0, v[37:38], v[82:83], v[37:38]
	v_cmp_class_f64_e64 s2, v[144:145], 0x204
	v_fma_f64 v[86:87], -v[86:87], v[134:135], v[102:103]
	v_fma_f64 v[102:103], -v[116:117], v[84:85], 1.0
	v_fma_f64 v[114:115], v[35:36], 2.0, v[114:115]
	v_mul_f64 v[148:149], v[146:147], v[132:133]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_div_fmas_f64 v[35:36], v[86:87], v[128:129], v[134:135]
	v_fma_f64 v[84:85], v[84:85], v[102:103], v[84:85]
	v_div_scale_f64 v[102:103], s1, v[50:51], v[19:20], v[50:51]
	v_fma_f64 v[86:87], -v[118:119], v[112:113], 1.0
	s_mov_b32 vcc_lo, s0
	v_fma_f64 v[130:131], -v[130:131], v[148:149], v[146:147]
	v_add_f64 v[146:147], v[144:145], v[114:115]
	v_div_fixup_f64 v[6:7], v[35:36], v[15:16], v[6:7]
	v_mul_f64 v[134:135], v[102:103], v[84:85]
	v_fma_f64 v[86:87], v[112:113], v[86:87], v[112:113]
	v_div_fmas_f64 v[128:129], v[130:131], v[132:133], v[148:149]
	v_cndmask_b32_e64 v131, v147, v145, s2
	v_cndmask_b32_e64 v130, v146, v144, s2
	v_div_scale_f64 v[132:133], s0, v[52:53], v[19:20], v[52:53]
	v_add_f64 v[144:145], v[146:147], -v[144:145]
	s_mov_b32 vcc_lo, s1
	s_delay_alu instid0(VALU_DEP_3)
	v_mul_f64 v[112:113], v[130:131], s[40:41]
	v_fma_f64 v[102:103], -v[116:117], v[134:135], v[102:103]
	v_cmp_ngt_f64_e64 s1, 0xc090cc00, v[130:131]
	v_div_fixup_f64 v[37:38], v[128:129], v[82:83], v[37:38]
	v_mul_f64 v[116:117], v[132:133], v[86:87]
	v_rndne_f64_e32 v[112:113], v[112:113]
	v_div_fmas_f64 v[84:85], v[102:103], v[84:85], v[134:135]
	s_mov_b32 vcc_lo, s0
	v_add_f64 v[102:103], v[114:115], -v[144:145]
	v_cmp_nlt_f64_e64 s0, 0x40900000, v[130:131]
	v_fma_f64 v[118:119], -v[118:119], v[116:117], v[132:133]
	v_fma_f64 v[132:133], v[112:113], s[44:45], v[130:131]
	v_cvt_i32_f64_e32 v12, v[112:113]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_div_fmas_f64 v[86:87], v[118:119], v[86:87], v[116:117]
	v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[130:131]|
	v_fma_f64 v[132:133], v[112:113], s[46:47], v[132:133]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_div_fixup_f64 v[52:53], v[86:87], v[19:20], v[52:53]
	v_dual_cndmask_b32 v83, 0, v103 :: v_dual_cndmask_b32 v82, 0, v102
	v_mul_f64 v[102:103], v[96:97], s[28:29]
	v_fma_f64 v[146:147], v[132:133], s[54:55], s[52:53]
	s_and_b32 vcc_lo, s1, s0
	v_div_fixup_f64 v[19:20], v[84:85], v[19:20], v[50:51]
	v_add_f64 v[37:38], v[52:53], v[37:38]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[146:147], v[132:133], v[146:147], s[56:57]
	v_add_f64 v[19:20], v[19:20], v[80:81]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f64 v[37:38], v[102:103], v[37:38]
	v_fma_f64 v[146:147], v[132:133], v[146:147], s[58:59]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[19:20], v[96:97], v[19:20]
	v_fma_f64 v[146:147], v[132:133], v[146:147], s[62:63]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[146:147], v[132:133], v[146:147], s[64:65]
	v_fma_f64 v[146:147], v[132:133], v[146:147], s[66:67]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[146:147], v[132:133], v[146:147], s[68:69]
	v_fma_f64 v[146:147], v[132:133], v[146:147], s[70:71]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[146:147], v[132:133], v[146:147], s[60:61]
	v_fma_f64 v[146:147], v[132:133], v[146:147], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_fma_f64 v[132:133], v[132:133], v[146:147], 1.0
	flat_load_b64 v[146:147], v[8:9]
	v_ldexp_f64 v[112:113], v[132:133], v12
	v_cndmask_b32_e64 v12, 0x7ff00000, v113, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v86, 0, v112, vcc_lo
	v_cmp_neq_f64_e64 s0, 0x7ff00000, |v[48:49]|
	v_cndmask_b32_e64 v87, 0, v12, s1
	v_cmp_neq_f64_e64 s1, 0, v[48:49]
	v_add_f64 v[48:49], v[96:97], v[96:97]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fma_f64 v[82:83], v[86:87], v[82:83], v[86:87]
	v_cmp_class_f64_e64 vcc_lo, v[86:87], 0x204
	v_fma_f64 v[37:38], v[48:49], v[52:53], v[37:38]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_dual_cndmask_b32 v12, v83, v87 :: v_dual_cndmask_b32 v39, v82, v86
	s_and_b32 vcc_lo, s1, s0
	v_and_b32_e32 v12, 0x7fffffff, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v82, 0, v39, vcc_lo
	v_cndmask_b32_e64 v12, 0x7ff00000, v12, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v83, 0, v12, s1
	v_add_nc_u32_e32 v12, s5, v13
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_fma_f64 v[52:53], v[4:5], v[82:83], v[146:147]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[82:83], null, v12, s4, v[14:15]
	v_ashrrev_i32_e32 v83, 31, v82
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[82:83], 3, v[82:83]
	v_add_co_u32 v86, vcc_lo, v0, v82
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v87, vcc_lo, v1, v83, vcc_lo
	v_add_f64 v[52:53], v[52:53], -v[37:38]
	flat_store_b64 v[86:87], v[52:53]
	flat_load_b64 v[52:53], v[21:22]
	flat_load_b64 v[86:87], v[23:24]
	s_waitcnt vmcnt(1) lgkmcnt(1)
	v_mul_f64 v[50:51], v[4:5], v[52:53]
	v_mad_u64_u32 v[52:53], null, s5, 3, v[13:14]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_subrev_nc_u32_e32 v39, s5, v52
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_fma_f64 v[12:13], v[50:51], v[86:87], -v[19:20]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[50:51], null, v39, s4, v[14:15]
	v_ashrrev_i32_e32 v51, 31, v50
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[50:51], 3, v[50:51]
	v_add_co_u32 v80, vcc_lo, v0, v50
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v81, vcc_lo, v1, v51, vcc_lo
	flat_store_b64 v[80:81], v[12:13]
	flat_load_b64 v[12:13], v[8:9]
	flat_load_b64 v[80:81], v[21:22]
	flat_load_b64 v[84:85], v[23:24]
	s_waitcnt vmcnt(2) lgkmcnt(2)
	v_fma_f64 v[12:13], v[4:5], v[27:28], v[12:13]
	s_waitcnt vmcnt(1) lgkmcnt(1)
	v_mul_f64 v[29:30], v[37:38], v[80:81]
	v_div_scale_f64 v[37:38], null, v[17:18], v[17:18], v[31:32]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fma_f64 v[12:13], v[12:13], v[80:81], -v[29:30]
	v_div_fixup_f64 v[29:30], v[100:101], s[8:9], v[98:99]
	v_rcp_f64_e32 v[54:55], v[37:38]
	s_waitcnt vmcnt(0) lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f64 v[12:13], -v[19:20], v[84:85], v[12:13]
	v_mad_u64_u32 v[19:20], null, v52, s4, v[14:15]
	v_ashrrev_i32_e32 v20, 31, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[19:20], 3, v[19:20]
	v_add_co_u32 v0, vcc_lo, v0, v19
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, v1, v20, vcc_lo
	v_add_co_u32 v25, vcc_lo, v2, v25
	v_add_co_ci_u32_e32 v26, vcc_lo, v3, v26, vcc_lo
	v_fma_f64 v[12:13], v[33:34], v[29:30], v[12:13]
	flat_store_b64 v[0:1], v[12:13]
	flat_load_b64 v[0:1], v[23:24]
	v_add_f64 v[12:13], v[66:67], -v[68:69]
	v_fma_f64 v[66:67], -v[37:38], v[54:55], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f64 v[33:34], null, v[17:18], v[17:18], v[12:13]
	v_div_scale_f64 v[68:69], vcc_lo, v[12:13], v[17:18], v[12:13]
	v_rcp_f64_e32 v[52:53], v[33:34]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[64:65], -v[33:34], v[52:53], 1.0
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_mul_f64 v[0:1], v[4:5], v[0:1]
	flat_store_b64 v[25:26], v[0:1]
	flat_load_b64 v[0:1], v[21:22]
	v_fma_f64 v[25:26], v[52:53], v[64:65], v[52:53]
	v_fma_f64 v[52:53], v[54:55], v[66:67], v[54:55]
	flat_load_b64 v[54:55], v[23:24]
	v_fma_f64 v[64:65], -v[33:34], v[25:26], 1.0
	v_fma_f64 v[66:67], -v[37:38], v[52:53], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fma_f64 v[25:26], v[25:26], v[64:65], v[25:26]
	v_div_scale_f64 v[64:65], s0, v[31:32], v[17:18], v[31:32]
	v_fma_f64 v[52:53], v[52:53], v[66:67], v[52:53]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[66:67], v[68:69], v[25:26]
	v_mul_f64 v[80:81], v[64:65], v[52:53]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[33:34], -v[33:34], v[66:67], v[68:69]
	v_fma_f64 v[37:38], -v[37:38], v[80:81], v[64:65]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_fmas_f64 v[25:26], v[33:34], v[25:26], v[66:67]
	s_mov_b32 vcc_lo, s0
	v_div_fmas_f64 v[33:34], v[37:38], v[52:53], v[80:81]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fixup_f64 v[12:13], v[25:26], v[17:18], v[12:13]
	v_div_fixup_f64 v[31:32], v[33:34], v[17:18], v[31:32]
	v_add_co_u32 v33, vcc_lo, v2, v82
	v_add_co_ci_u32_e32 v34, vcc_lo, v3, v83, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[6:7], v[12:13], v[6:7]
	v_add_f64 v[31:32], v[31:32], v[70:71]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_mul_f64 v[31:32], v[96:97], v[31:32]
	s_waitcnt vmcnt(1) lgkmcnt(1)
	v_mul_f64 v[0:1], v[4:5], v[0:1]
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_fma_f64 v[0:1], v[0:1], v[54:55], -v[31:32]
	flat_store_b64 v[33:34], v[0:1]
	flat_load_b64 v[0:1], v[23:24]
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_frexp_mant_f64_e64 v[33:34], |v[0:1]|
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_gt_f64_e32 vcc_lo, s[10:11], v[33:34]
	v_cndmask_b32_e64 v14, 0, 1, vcc_lo
	v_ldexp_f64 v[33:34], v[33:34], v14
	v_frexp_exp_i32_f64_e32 v14, v[0:1]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[37:38], v[33:34], 1.0
	v_add_f64 v[64:65], v[33:34], -1.0
	v_subrev_co_ci_u32_e32 v14, vcc_lo, 0, v14, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[52:53], v[37:38]
	v_add_f64 v[66:67], v[37:38], -1.0
	v_add_f64 v[33:34], v[33:34], -v[66:67]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[54:55], -v[37:38], v[52:53], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[52:53], v[54:55], v[52:53], v[52:53]
	v_fma_f64 v[54:55], -v[37:38], v[52:53], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[52:53], v[54:55], v[52:53], v[52:53]
	v_mul_f64 v[54:55], v[64:65], v[52:53]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[68:69], v[37:38], v[54:55]
	v_fma_f64 v[37:38], v[54:55], v[37:38], -v[68:69]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[33:34], v[54:55], v[33:34], v[37:38]
	v_add_f64 v[37:38], v[68:69], v[33:34]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[66:67], v[64:65], -v[37:38]
	v_add_f64 v[68:69], v[37:38], -v[68:69]
	v_add_f64 v[64:65], v[64:65], -v[66:67]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[33:34], v[68:69], -v[33:34]
	v_add_f64 v[37:38], v[64:65], -v[37:38]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[33:34], v[33:34], v[37:38]
	v_add_f64 v[33:34], v[66:67], v[33:34]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[33:34], v[52:53], v[33:34]
	v_add_f64 v[37:38], v[54:55], v[33:34]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[52:53], v[37:38], -v[54:55]
	v_mul_f64 v[54:55], v[37:38], v[37:38]
	v_add_f64 v[33:34], v[33:34], -v[52:53]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[52:53], v[37:38], v[37:38], -v[54:55]
	v_add_f64 v[64:65], v[33:34], v[33:34]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[52:53], v[37:38], v[64:65], v[52:53]
	v_add_f64 v[64:65], v[54:55], v[52:53]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_fma_f64 v[66:67], v[64:65], s[14:15], s[12:13]
	v_add_f64 v[54:55], v[64:65], -v[54:55]
	v_mul_f64 v[80:81], v[37:38], v[64:65]
	v_fma_f64 v[66:67], v[64:65], v[66:67], s[16:17]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[52:53], v[52:53], -v[54:55]
	v_fma_f64 v[66:67], v[64:65], v[66:67], s[18:19]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[66:67], v[64:65], v[66:67], s[20:21]
	v_fma_f64 v[66:67], v[64:65], v[66:67], s[22:23]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[66:67], v[64:65], v[66:67], s[24:25]
	v_fma_f64 v[66:67], v[64:65], v[66:67], s[26:27]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_fma_f64 v[66:67], v[64:65], v[66:67], s[38:39]
	v_readlane_b32 s39, v40, 5
	v_readlane_b32 s38, v40, 4
	v_mul_f64 v[68:69], v[64:65], v[66:67]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[54:55], v[64:65], v[66:67], -v[68:69]
	v_fma_f64 v[54:55], v[52:53], v[66:67], v[54:55]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[66:67], v[68:69], v[54:55]
	v_add_f64 v[70:71], v[66:67], s[10:11]
	v_add_f64 v[68:69], v[66:67], -v[68:69]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[82:83], v[70:71], s[28:29]
	v_add_f64 v[54:55], v[54:55], -v[68:69]
	v_fma_f64 v[68:69], v[64:65], v[37:38], -v[80:81]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[66:67], v[66:67], -v[82:83]
	v_add_f64 v[54:55], v[54:55], s[34:35]
	s_delay_alu instid0(VALU_DEP_3)
	v_fma_f64 v[64:65], v[64:65], v[33:34], v[68:69]
	v_ldexp_f64 v[33:34], v[33:34], 1
	v_readlane_b32 s35, v40, 1
	v_readlane_b32 s34, v40, 0
	v_add_f64 v[54:55], v[54:55], v[66:67]
	v_fma_f64 v[52:53], v[52:53], v[37:38], v[64:65]
	v_ldexp_f64 v[37:38], v[37:38], 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[64:65], v[70:71], v[54:55]
	v_add_f64 v[66:67], v[80:81], v[52:53]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[68:69], v[70:71], -v[64:65]
	v_mul_f64 v[70:71], v[66:67], v[64:65]
	v_add_f64 v[80:81], v[66:67], -v[80:81]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[54:55], v[54:55], v[68:69]
	v_fma_f64 v[68:69], v[66:67], v[64:65], -v[70:71]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[52:53], v[52:53], -v[80:81]
	v_fma_f64 v[54:55], v[66:67], v[54:55], v[68:69]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f64 v[52:53], v[52:53], v[64:65], v[54:55]
	v_cvt_f64_i32_e32 v[64:65], v14
	v_add_f64 v[54:55], v[70:71], v[52:53]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f64 v[66:67], v[37:38], v[54:55]
	v_add_f64 v[68:69], v[54:55], -v[70:71]
	v_mul_f64 v[70:71], v[64:65], s[30:31]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[37:38], v[66:67], -v[37:38]
	v_add_f64 v[52:53], v[52:53], -v[68:69]
	s_delay_alu instid0(VALU_DEP_3)
	v_fma_f64 v[68:69], v[64:65], s[30:31], -v[70:71]
	v_readlane_b32 s30, v41, 6
	v_readlane_b32 s31, v41, 7
	v_add_f64 v[37:38], v[54:55], -v[37:38]
	v_add_f64 v[33:34], v[33:34], v[52:53]
	v_fma_f64 v[52:53], v[64:65], s[42:43], v[68:69]
	v_readlane_b32 s43, v40, 9
	v_readlane_b32 s42, v40, 8
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[33:34], v[33:34], v[37:38]
	v_add_f64 v[37:38], v[70:71], v[52:53]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[54:55], v[66:67], v[33:34]
	v_add_f64 v[70:71], v[37:38], -v[70:71]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[64:65], v[37:38], v[54:55]
	v_add_f64 v[66:67], v[54:55], -v[66:67]
	v_add_f64 v[52:53], v[52:53], -v[70:71]
	flat_load_b64 v[70:71], v[8:9]
	v_add_f64 v[68:69], v[64:65], -v[37:38]
	v_add_f64 v[33:34], v[33:34], -v[66:67]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[80:81], v[64:65], -v[68:69]
	v_add_f64 v[54:55], v[54:55], -v[68:69]
	v_add_f64 v[66:67], v[52:53], v[33:34]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[37:38], v[37:38], -v[80:81]
	v_add_f64 v[37:38], v[54:55], v[37:38]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[54:55], v[66:67], -v[52:53]
	v_add_f64 v[37:38], v[66:67], v[37:38]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[66:67], v[66:67], -v[54:55]
	v_add_f64 v[33:34], v[33:34], -v[54:55]
	v_add_f64 v[68:69], v[64:65], v[37:38]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[52:53], v[52:53], -v[66:67]
	v_add_f64 v[54:55], v[68:69], -v[64:65]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[33:34], v[33:34], v[52:53]
	v_add_f64 v[37:38], v[37:38], -v[54:55]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[33:34], v[33:34], v[37:38]
	v_add_f64 v[37:38], v[68:69], v[33:34]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[52:53], v[37:38], -v[68:69]
	v_add_f64 v[54:55], v[37:38], v[37:38]
	v_add_f64 v[33:34], v[33:34], -v[52:53]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f64 v[37:38], v[37:38], 2.0, -v[54:55]
	v_cmp_class_f64_e64 vcc_lo, v[54:55], 0x204
	v_fma_f64 v[33:34], v[33:34], 2.0, v[37:38]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[37:38], v[54:55], v[33:34]
	v_dual_cndmask_b32 v53, v38, v55 :: v_dual_cndmask_b32 v52, v37, v54
	v_add_f64 v[37:38], v[37:38], -v[54:55]
	s_delay_alu instid0(VALU_DEP_2)
	v_mul_f64 v[64:65], v[52:53], s[40:41]
	v_cmp_nlt_f64_e64 s0, 0x40900000, v[52:53]
	v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[52:53]|
	v_cmp_ngt_f64_e64 s1, 0xc090cc00, v[52:53]
	v_readlane_b32 s41, v40, 7
	v_readlane_b32 s40, v40, 6
	v_add_f64 v[33:34], v[33:34], -v[37:38]
	v_rndne_f64_e32 v[64:65], v[64:65]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v15, 0, v34, vcc_lo
	v_fma_f64 v[66:67], v[64:65], s[44:45], v[52:53]
	v_cvt_i32_f64_e32 v14, v[64:65]
	v_readlane_b32 s45, v40, 11
	v_readlane_b32 s44, v40, 10
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_fma_f64 v[66:67], v[64:65], s[46:47], v[66:67]
	v_readlane_b32 s47, v40, 13
	v_readlane_b32 s46, v40, 12
	v_fma_f64 v[68:69], v[66:67], s[54:55], s[52:53]
	v_readlane_b32 s55, v40, 21
	v_readlane_b32 s54, v40, 20
	v_readlane_b32 s53, v40, 19
	v_readlane_b32 s52, v40, 18
	v_fma_f64 v[68:69], v[66:67], v[68:69], s[56:57]
	v_readlane_b32 s57, v40, 23
	v_readlane_b32 s56, v40, 22
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_fma_f64 v[68:69], v[66:67], v[68:69], s[58:59]
	v_readlane_b32 s59, v40, 25
	v_readlane_b32 s58, v40, 24
	v_fma_f64 v[68:69], v[66:67], v[68:69], s[62:63]
	v_readlane_b32 s63, v40, 29
	v_readlane_b32 s62, v40, 28
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_fma_f64 v[68:69], v[66:67], v[68:69], s[64:65]
	v_readlane_b32 s65, v40, 31
	v_readlane_b32 s64, v40, 30
	v_fma_f64 v[68:69], v[66:67], v[68:69], s[66:67]
	v_readlane_b32 s67, v41, 1
	v_readlane_b32 s66, v41, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_fma_f64 v[68:69], v[66:67], v[68:69], s[68:69]
	v_readlane_b32 s69, v41, 3
	v_readlane_b32 s68, v41, 2
	v_fma_f64 v[68:69], v[66:67], v[68:69], s[70:71]
	v_readlane_b32 s71, v41, 5
	v_readlane_b32 s70, v41, 4
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_fma_f64 v[68:69], v[66:67], v[68:69], s[60:61]
	v_readlane_b32 s61, v40, 27
	v_readlane_b32 s60, v40, 26
	v_fma_f64 v[68:69], v[66:67], v[68:69], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[64:65], v[66:67], v[68:69], 1.0
	v_ldexp_f64 v[54:55], v[64:65], v14
	v_cndmask_b32_e32 v14, 0, v33, vcc_lo
	s_and_b32 vcc_lo, s1, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v37, 0x7ff00000, v55, s0
	v_cndmask_b32_e32 v16, 0, v54, vcc_lo
	v_cmp_neq_f64_e64 s0, 0x7ff00000, |v[0:1]|
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v17, 0, v37, s1
	v_cmp_neq_f64_e64 s1, 0, v[0:1]
	v_mul_f64 v[0:1], v[102:103], v[6:7]
	v_fma_f64 v[14:15], v[16:17], v[14:15], v[16:17]
	v_cmp_class_f64_e64 vcc_lo, v[16:17], 0x204
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[0:1], v[48:49], v[12:13], v[0:1]
	v_dual_cndmask_b32 v15, v15, v17 :: v_dual_cndmask_b32 v6, v14, v16
	s_and_b32 vcc_lo, s1, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v6, 0, v6 :: v_dual_and_b32 v15, 0x7fffffff, v15
	v_add_co_u32 v12, vcc_lo, v2, v50
	v_add_co_ci_u32_e32 v13, vcc_lo, v3, v51, vcc_lo
	v_cndmask_b32_e64 v15, 0x7ff00000, v15, s0
	v_add_co_u32 v2, vcc_lo, v2, v19
	v_add_co_ci_u32_e32 v3, vcc_lo, v3, v20, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v7, 0, v15, s1
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_fma_f64 v[6:7], v[4:5], v[6:7], v[70:71]
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[6:7], v[6:7], -v[0:1]
	flat_store_b64 v[12:13], v[6:7]
	flat_load_b64 v[6:7], v[8:9]
	flat_load_b64 v[8:9], v[21:22]
	flat_load_b64 v[12:13], v[23:24]
	s_waitcnt vmcnt(2) lgkmcnt(2)
	v_fma_f64 v[4:5], v[4:5], v[27:28], v[6:7]
	s_waitcnt vmcnt(1) lgkmcnt(1)
	v_mul_f64 v[6:7], v[31:32], v[8:9]
	s_waitcnt vmcnt(0) lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[4:5], v[4:5], v[12:13], -v[6:7]
	v_fma_f64 v[0:1], -v[0:1], v[12:13], v[4:5]
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[0:1], v[10:11], v[29:30], v[0:1]
	flat_store_b64 v[2:3], v[0:1]
	s_or_saveexec_b32 s0, -1
	s_clause 0x1
	scratch_load_b32 v40, off, s32
	scratch_load_b32 v41, off, s32 offset:4
	s_mov_b32 exec_lo, s0
	s_waitcnt vmcnt(0) lgkmcnt(0)
	s_setpc_b64 s[30:31]
.Lfunc_end0:
	.size	_Z7calc_FGPdS_S_S_S_S_biidd, .Lfunc_end0-_Z7calc_FGPdS_S_S_S_S_biidd
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Function info:
; codeLenInByte = 11132
; NumSgprs: 74
; NumVgprs: 150
; ScratchSize: 12
; MemoryBound: 1
	.text
	.protected	_Z19iterateScheme_part1PdS_S_S_S_S_S_S_S_S_S_S_ddd ; -- Begin function _Z19iterateScheme_part1PdS_S_S_S_S_S_S_S_S_S_S_ddd
	.globl	_Z19iterateScheme_part1PdS_S_S_S_S_S_S_S_S_S_S_ddd
	.p2align	8
	.type	_Z19iterateScheme_part1PdS_S_S_S_S_S_S_S_S_S_S_ddd,@function
_Z19iterateScheme_part1PdS_S_S_S_S_S_S_S_S_S_S_ddd: ; @_Z19iterateScheme_part1PdS_S_S_S_S_S_S_S_S_S_S_ddd
; %bb.0:
	s_load_b32 s6, s[0:1], 0x84
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, jmax_d@rel32@lo+4
	s_addc_u32 s3, s3, jmax_d@rel32@hi+12
	s_getpc_b64 s[4:5]
	s_add_u32 s4, s4, kmax_d@rel32@lo+4
	s_addc_u32 s5, s5, kmax_d@rel32@hi+12
	s_load_b32 s12, s[2:3], 0x0
	s_load_b32 s3, s[4:5], 0x0
	v_and_b32_e32 v1, 0x3ff, v0
	v_bfe_u32 v0, v0, 10, 10
	s_mov_b32 s32, 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s4, s6, 0xffff
	s_lshr_b32 s2, s6, 16
	v_mad_u64_u32 v[13:14], null, s14, s4, v[1:2]
	v_mad_u64_u32 v[14:15], null, s15, s2, v[0:1]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_i32_e32 vcc_lo, s12, v13
	v_cmp_gt_i32_e64 s2, s3, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, vcc_lo, s2
	s_and_saveexec_b32 s4, s2
	s_cbranch_execz .LBB1_2
; %bb.1:
	s_load_b256 s[4:11], s[0:1], 0x10
	s_delay_alu instid0(VALU_DEP_3)
	v_mad_u64_u32 v[0:1], null, s3, v13, v[14:15]
	s_getpc_b64 s[14:15]
	s_add_u32 s14, s14, R_d@rel32@lo+4
	s_addc_u32 s15, s15, R_d@rel32@hi+12
	s_load_b64 s[20:21], s[0:1], 0x40
	s_load_b64 s[14:15], s[14:15], 0x0
	v_add_nc_u32_e32 v12, s12, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v1, 31, v0
	v_lshlrev_b64 v[0:1], 3, v[0:1]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s10, v0
	v_add_co_ci_u32_e32 v3, vcc_lo, s11, v1, vcc_lo
	v_add_co_u32 v4, vcc_lo, s8, v0
	v_add_co_ci_u32_e32 v5, vcc_lo, s9, v1, vcc_lo
	global_load_b64 v[2:3], v[2:3], off
	global_load_b64 v[4:5], v[4:5], off
	s_waitcnt vmcnt(1)
	v_mul_f64 v[6:7], s[14:15], v[2:3]
	s_getpc_b64 s[14:15]
	s_add_u32 s14, s14, Cv_d@rel32@lo+4
	s_addc_u32 s15, s15, Cv_d@rel32@hi+12
	s_load_b64 s[14:15], s[14:15], 0x0
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f64 v[8:9], null, v[6:7], v[6:7], v[4:5]
	v_div_scale_f64 v[17:18], vcc_lo, v[4:5], v[6:7], v[4:5]
	v_rcp_f64_e32 v[10:11], v[8:9]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[15:16], -v[8:9], v[10:11], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[10:11], v[10:11], v[15:16], v[10:11]
	v_fma_f64 v[15:16], -v[8:9], v[10:11], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[10:11], v[10:11], v[15:16], v[10:11]
	v_mul_f64 v[15:16], v[17:18], v[10:11]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[8:9], -v[8:9], v[15:16], v[17:18]
	v_div_fmas_f64 v[8:9], v[8:9], v[10:11], v[15:16]
	s_delay_alu instid0(VALU_DEP_1)
	v_div_fixup_f64 v[4:5], v[8:9], v[6:7], v[4:5]
	v_add_co_u32 v6, vcc_lo, s4, v0
	v_add_co_ci_u32_e32 v7, vcc_lo, s5, v1, vcc_lo
	v_add_co_u32 v8, vcc_lo, s6, v0
	v_add_co_ci_u32_e32 v9, vcc_lo, s7, v1, vcc_lo
	v_add_co_u32 v0, vcc_lo, s20, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s21, v1, vcc_lo
	global_load_b64 v[10:11], v[6:7], off
	global_load_b64 v[15:16], v[8:9], off
	global_store_b64 v[0:1], v[4:5], off
	global_load_b64 v[0:1], v[6:7], off
	s_waitcnt vmcnt(1)
	v_mad_u64_u32 v[6:7], null, v12, s3, v[14:15]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v7, 31, v6
	v_lshlrev_b64 v[6:7], 3, v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v6, vcc_lo, s20, v6
	v_add_co_ci_u32_e32 v7, vcc_lo, s21, v7, vcc_lo
	s_waitcnt vmcnt(0)
	v_mul_f64 v[0:1], v[4:5], v[0:1]
	global_store_b64 v[6:7], v[0:1], off
	global_load_b64 v[0:1], v[8:9], off
	v_mul_f64 v[6:7], v[15:16], v[15:16]
	v_mov_b32_e32 v9, s9
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f64 v[6:7], v[10:11], v[10:11], v[6:7]
	v_dual_mov_b32 v10, s10 :: v_dual_mov_b32 v11, s11
	v_mul_f64 v[6:7], v[6:7], 0.5
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_fma_f64 v[2:3], v[2:3], s[14:15], v[6:7]
	v_add_nc_u32_e32 v6, s12, v12
	v_mov_b32_e32 v12, 1
	v_add_nc_u32_e32 v8, s12, v6
	s_load_b256 s[12:19], s[0:1], 0x50
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, _Z7calc_FGPdS_S_S_S_S_biidd@rel32@lo+4
	s_addc_u32 s1, s1, _Z7calc_FGPdS_S_S_S_S_biidd@rel32@hi+12
	s_waitcnt lgkmcnt(0)
	v_dual_mov_b32 v16, s17 :: v_dual_mov_b32 v17, s18
	v_mov_b32_e32 v18, s19
	v_mul_f64 v[2:3], v[4:5], v[2:3]
	s_waitcnt vmcnt(0)
	v_mul_f64 v[0:1], v[4:5], v[0:1]
	v_mad_u64_u32 v[4:5], null, v6, s3, v[14:15]
	v_mad_u64_u32 v[6:7], null, v8, s3, v[14:15]
	v_dual_mov_b32 v8, s8 :: v_dual_mov_b32 v15, s16
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_ashrrev_i32_e32 v5, 31, v4
	v_ashrrev_i32_e32 v7, 31, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[4:5], 3, v[4:5]
	v_lshlrev_b64 v[6:7], 3, v[6:7]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v4, vcc_lo, s20, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s21, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v6, vcc_lo, s20, v6
	v_add_co_ci_u32_e32 v7, vcc_lo, s21, v7, vcc_lo
	s_clause 0x1
	global_store_b64 v[4:5], v[0:1], off
	global_store_b64 v[6:7], v[2:3], off
	v_dual_mov_b32 v5, s5 :: v_dual_mov_b32 v0, s12
	v_dual_mov_b32 v1, s13 :: v_dual_mov_b32 v2, s14
	v_dual_mov_b32 v3, s15 :: v_dual_mov_b32 v4, s4
	v_dual_mov_b32 v6, s6 :: v_dual_mov_b32 v7, s7
	s_swappc_b64 s[30:31], s[0:1]
.LBB1_2:
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z19iterateScheme_part1PdS_S_S_S_S_S_S_S_S_S_S_ddd
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 12
		.amdhsa_kernarg_size 376
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 1
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 150
		.amdhsa_next_free_sgpr 72
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z19iterateScheme_part1PdS_S_S_S_S_S_S_S_S_S_S_ddd, .Lfunc_end1-_Z19iterateScheme_part1PdS_S_S_S_S_S_S_S_S_S_S_ddd
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 844
; NumSgprs: 74
; NumVgprs: 150
; ScratchSize: 12
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 9
; VGPRBlocks: 18
; NumSGPRsForWavesPerEU: 74
; NumVGPRsForWavesPerEU: 150
; Occupancy: 9
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 1
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2align	2                               ; -- Begin function _Z15primativesFromQPdS_S_S_S_S_S_ii
	.type	_Z15primativesFromQPdS_S_S_S_S_S_ii,@function
_Z15primativesFromQPdS_S_S_S_S_S_ii:    ; @_Z15primativesFromQPdS_S_S_S_S_S_ii
; %bb.0:
	s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, kmax_d@rel32@lo+4
	s_addc_u32 s1, s1, kmax_d@rel32@hi+12
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, jmax_d@rel32@lo+4
	s_addc_u32 s3, s3, jmax_d@rel32@hi+12
	s_load_b32 s1, s[0:1], 0x0
	s_load_b32 s6, s[2:3], 0x0
	s_mov_b32 s2, 0x55555555
	s_mov_b32 s3, 0x3fe55555
	s_mov_b32 s4, 0x968915a9
	s_mov_b32 s8, 0x4222de17
	s_mov_b32 s5, 0x3fba6564
	s_mov_b32 s9, 0x3fbdee67
	s_waitcnt lgkmcnt(0)
	v_mad_u64_u32 v[16:17], null, s1, v14, v[15:16]
	v_add_nc_u32_e32 v14, s6, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v17, 31, v16
	v_lshlrev_b64 v[16:17], 3, v[16:17]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v18, vcc_lo, v0, v16
	v_add_co_ci_u32_e32 v19, vcc_lo, v1, v17, vcc_lo
	v_mad_u64_u32 v[22:23], null, v14, s1, v[15:16]
	v_add_co_u32 v2, vcc_lo, v2, v16
	flat_load_b64 v[20:21], v[18:19]
	v_add_co_ci_u32_e32 v3, vcc_lo, v3, v17, vcc_lo
	v_add_nc_u32_e32 v14, s6, v14
	v_ashrrev_i32_e32 v23, 31, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[22:23], 3, v[22:23]
	v_add_co_u32 v22, vcc_lo, v0, v22
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v23, vcc_lo, v1, v23, vcc_lo
	s_waitcnt vmcnt(0) lgkmcnt(0)
	flat_store_b64 v[2:3], v[20:21]
	flat_load_b64 v[2:3], v[22:23]
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_div_scale_f64 v[22:23], null, v[20:21], v[20:21], v[2:3]
	v_div_scale_f64 v[28:29], vcc_lo, v[2:3], v[20:21], v[2:3]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[24:25], v[22:23]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[26:27], -v[22:23], v[24:25], 1.0
	v_fma_f64 v[24:25], v[24:25], v[26:27], v[24:25]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[26:27], -v[22:23], v[24:25], 1.0
	v_fma_f64 v[24:25], v[24:25], v[26:27], v[24:25]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[26:27], v[28:29], v[24:25]
	v_fma_f64 v[22:23], -v[22:23], v[26:27], v[28:29]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_div_fmas_f64 v[22:23], v[22:23], v[24:25], v[26:27]
	v_add_co_u32 v4, vcc_lo, v4, v16
	v_add_co_ci_u32_e32 v5, vcc_lo, v5, v17, vcc_lo
	v_div_fixup_f64 v[2:3], v[22:23], v[20:21], v[2:3]
	v_mad_u64_u32 v[20:21], null, v14, s1, v[15:16]
	v_add_nc_u32_e32 v14, s6, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v21, 31, v20
	v_lshlrev_b64 v[20:21], 3, v[20:21]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v20, vcc_lo, v0, v20
	v_add_co_ci_u32_e32 v21, vcc_lo, v1, v21, vcc_lo
	flat_store_b64 v[4:5], v[2:3]
	s_clause 0x1
	flat_load_b64 v[2:3], v[20:21]
	flat_load_b64 v[20:21], v[18:19]
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_div_scale_f64 v[22:23], null, v[20:21], v[20:21], v[2:3]
	v_div_scale_f64 v[28:29], vcc_lo, v[2:3], v[20:21], v[2:3]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[24:25], v[22:23]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[26:27], -v[22:23], v[24:25], 1.0
	v_fma_f64 v[24:25], v[24:25], v[26:27], v[24:25]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[26:27], -v[22:23], v[24:25], 1.0
	v_fma_f64 v[24:25], v[24:25], v[26:27], v[24:25]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[26:27], v[28:29], v[24:25]
	v_fma_f64 v[22:23], -v[22:23], v[26:27], v[28:29]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_div_fmas_f64 v[22:23], v[22:23], v[24:25], v[26:27]
	v_add_co_u32 v6, vcc_lo, v6, v16
	v_add_co_ci_u32_e32 v7, vcc_lo, v7, v17, vcc_lo
	v_div_fixup_f64 v[2:3], v[22:23], v[20:21], v[2:3]
	flat_store_b64 v[6:7], v[2:3]
	flat_load_b64 v[4:5], v[4:5]
	v_frexp_mant_f64_e64 v[6:7], |v[2:3]|
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_gt_f64_e32 vcc_lo, s[2:3], v[6:7]
	v_cndmask_b32_e64 v22, 0, 1, vcc_lo
	v_ldexp_f64 v[6:7], v[6:7], v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_f64 v[34:35], v[6:7], -1.0
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_frexp_mant_f64_e64 v[20:21], |v[4:5]|
	v_cmp_gt_f64_e64 s0, s[2:3], v[20:21]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v22, 0, 1, s0
	v_ldexp_f64 v[20:21], v[20:21], v22
	v_add_f64 v[22:23], v[6:7], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[24:25], v[20:21], 1.0
	v_rcp_f64_e32 v[26:27], v[22:23]
	v_add_f64 v[38:39], v[22:23], -1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_rcp_f64_e32 v[28:29], v[24:25]
	v_add_f64 v[50:51], v[24:25], -1.0
	v_add_f64 v[6:7], v[6:7], -v[38:39]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[30:31], -v[22:23], v[26:27], 1.0
	v_fma_f64 v[32:33], -v[24:25], v[28:29], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[26:27], v[30:31], v[26:27], v[26:27]
	v_fma_f64 v[28:29], v[32:33], v[28:29], v[28:29]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[30:31], -v[22:23], v[26:27], 1.0
	v_fma_f64 v[32:33], -v[24:25], v[28:29], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_fma_f64 v[26:27], v[30:31], v[26:27], v[26:27]
	v_add_f64 v[30:31], v[20:21], -1.0
	v_add_f64 v[20:21], v[20:21], -v[50:51]
	v_fma_f64 v[28:29], v[32:33], v[28:29], v[28:29]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[32:33], v[34:35], v[26:27]
	v_mul_f64 v[36:37], v[30:31], v[28:29]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[48:49], v[22:23], v[32:33]
	v_mul_f64 v[52:53], v[24:25], v[36:37]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[22:23], v[32:33], v[22:23], -v[48:49]
	v_fma_f64 v[24:25], v[36:37], v[24:25], -v[52:53]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[6:7], v[32:33], v[6:7], v[22:23]
	v_fma_f64 v[20:21], v[36:37], v[20:21], v[24:25]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[22:23], v[48:49], v[6:7]
	v_add_f64 v[24:25], v[52:53], v[20:21]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[38:39], v[34:35], -v[22:23]
	v_add_f64 v[48:49], v[22:23], -v[48:49]
	v_add_f64 v[50:51], v[30:31], -v[24:25]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f64 v[34:35], v[34:35], -v[38:39]
	v_add_f64 v[52:53], v[24:25], -v[52:53]
	v_add_f64 v[6:7], v[48:49], -v[6:7]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[30:31], v[30:31], -v[50:51]
	v_add_f64 v[22:23], v[34:35], -v[22:23]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[20:21], v[52:53], -v[20:21]
	v_add_f64 v[24:25], v[30:31], -v[24:25]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[6:7], v[6:7], v[22:23]
	v_add_f64 v[20:21], v[20:21], v[24:25]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[6:7], v[38:39], v[6:7]
	v_add_f64 v[20:21], v[50:51], v[20:21]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[6:7], v[26:27], v[6:7]
	v_mul_f64 v[20:21], v[28:29], v[20:21]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[22:23], v[32:33], v[6:7]
	v_add_f64 v[24:25], v[36:37], v[20:21]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[26:27], v[22:23], -v[32:33]
	v_mul_f64 v[30:31], v[22:23], v[22:23]
	v_add_f64 v[28:29], v[24:25], -v[36:37]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[6:7], v[6:7], -v[26:27]
	v_mul_f64 v[26:27], v[24:25], v[24:25]
	v_add_f64 v[20:21], v[20:21], -v[28:29]
	v_fma_f64 v[28:29], v[22:23], v[22:23], -v[30:31]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[32:33], v[6:7], v[6:7]
	v_fma_f64 v[34:35], v[24:25], v[24:25], -v[26:27]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[36:37], v[20:21], v[20:21]
	v_fma_f64 v[28:29], v[22:23], v[32:33], v[28:29]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[32:33], v[24:25], v[36:37], v[34:35]
	v_add_f64 v[34:35], v[30:31], v[28:29]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[36:37], v[26:27], v[32:33]
	v_fma_f64 v[38:39], v[34:35], s[8:9], s[4:5]
	v_add_f64 v[30:31], v[34:35], -v[30:31]
	v_mul_f64 v[64:65], v[22:23], v[34:35]
	s_delay_alu instid0(VALU_DEP_4)
	v_fma_f64 v[48:49], v[36:37], s[8:9], s[4:5]
	s_mov_b32 s4, 0x3abe935a
	s_mov_b32 s5, 0x3fbe25e4
	v_add_f64 v[26:27], v[36:37], -v[26:27]
	v_fma_f64 v[38:39], v[34:35], v[38:39], s[4:5]
	v_add_f64 v[28:29], v[28:29], -v[30:31]
	v_mul_f64 v[68:69], v[24:25], v[36:37]
	s_mov_b32 s8, 0x652b82fe
	s_mov_b32 s9, 0x3ff71547
	v_fma_f64 v[48:49], v[36:37], v[48:49], s[4:5]
	s_mov_b32 s4, 0x47e6c9c2
	s_mov_b32 s5, 0x3fc110ef
	v_add_f64 v[26:27], v[32:33], -v[26:27]
	v_fma_f64 v[38:39], v[34:35], v[38:39], s[4:5]
	s_delay_alu instid0(VALU_DEP_3)
	v_fma_f64 v[48:49], v[36:37], v[48:49], s[4:5]
	s_mov_b32 s4, 0xcfa74449
	s_mov_b32 s5, 0x3fc3b13b
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[38:39], v[34:35], v[38:39], s[4:5]
	s_delay_alu instid0(VALU_DEP_2)
	v_fma_f64 v[48:49], v[36:37], v[48:49], s[4:5]
	s_mov_b32 s4, 0x71bf3c30
	s_mov_b32 s5, 0x3fc745d1
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[38:39], v[34:35], v[38:39], s[4:5]
	s_delay_alu instid0(VALU_DEP_2)
	v_fma_f64 v[48:49], v[36:37], v[48:49], s[4:5]
	s_mov_b32 s4, 0x1c7792ce
	s_mov_b32 s5, 0x3fcc71c7
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[38:39], v[34:35], v[38:39], s[4:5]
	s_delay_alu instid0(VALU_DEP_2)
	v_fma_f64 v[48:49], v[36:37], v[48:49], s[4:5]
	s_mov_b32 s4, 0x924920da
	s_mov_b32 s5, 0x3fd24924
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[38:39], v[34:35], v[38:39], s[4:5]
	s_delay_alu instid0(VALU_DEP_2)
	v_fma_f64 v[48:49], v[36:37], v[48:49], s[4:5]
	s_mov_b32 s4, 0x9999999c
	s_mov_b32 s5, 0x3fd99999
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[38:39], v[34:35], v[38:39], s[4:5]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_fma_f64 v[48:49], v[36:37], v[48:49], s[4:5]
	s_mov_b32 s4, 0x3b39803f
	s_mov_b32 s5, 0x3c7abc9e
	v_mul_f64 v[50:51], v[34:35], v[38:39]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[52:53], v[36:37], v[48:49]
	v_fma_f64 v[30:31], v[34:35], v[38:39], -v[50:51]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[32:33], v[36:37], v[48:49], -v[52:53]
	v_fma_f64 v[30:31], v[28:29], v[38:39], v[30:31]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[32:33], v[26:27], v[48:49], v[32:33]
	v_add_f64 v[38:39], v[50:51], v[30:31]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[48:49], v[52:53], v[32:33]
	v_add_f64 v[54:55], v[38:39], s[2:3]
	v_add_f64 v[50:51], v[38:39], -v[50:51]
	s_delay_alu instid0(VALU_DEP_3)
	v_add_f64 v[66:67], v[48:49], s[2:3]
	v_add_f64 v[52:53], v[48:49], -v[52:53]
	s_mov_b32 s3, 0xbfe55555
	s_delay_alu instid0(VALU_DEP_4) | instid1(SALU_CYCLE_1)
	v_add_f64 v[70:71], v[54:55], s[2:3]
	s_delay_alu instid0(VALU_DEP_4)
	v_add_f64 v[30:31], v[30:31], -v[50:51]
	v_fma_f64 v[50:51], v[34:35], v[22:23], -v[64:65]
	v_add_f64 v[80:81], v[66:67], s[2:3]
	v_add_f64 v[32:33], v[32:33], -v[52:53]
	v_fma_f64 v[52:53], v[36:37], v[24:25], -v[68:69]
	s_mov_b32 s2, 0xd5df274d
	s_mov_b32 s3, 0x3c8543b0
	v_add_f64 v[38:39], v[38:39], -v[70:71]
	v_add_f64 v[30:31], v[30:31], s[2:3]
	v_fma_f64 v[34:35], v[34:35], v[6:7], v[50:51]
	v_ldexp_f64 v[6:7], v[6:7], 1
	v_add_f64 v[48:49], v[48:49], -v[80:81]
	v_add_f64 v[32:33], v[32:33], s[2:3]
	v_fma_f64 v[36:37], v[36:37], v[20:21], v[52:53]
	s_mov_b32 s2, 0xfefa39ef
	s_mov_b32 s3, 0x3fe62e42
	v_ldexp_f64 v[20:21], v[20:21], 1
	v_add_f64 v[30:31], v[30:31], v[38:39]
	v_fma_f64 v[28:29], v[28:29], v[22:23], v[34:35]
	v_ldexp_f64 v[22:23], v[22:23], 1
	v_add_f64 v[32:33], v[32:33], v[48:49]
	v_fma_f64 v[26:27], v[26:27], v[24:25], v[36:37]
	v_ldexp_f64 v[24:25], v[24:25], 1
	v_add_f64 v[34:35], v[54:55], v[30:31]
	v_add_f64 v[36:37], v[64:65], v[28:29]
	v_add_f64 v[38:39], v[66:67], v[32:33]
	v_add_f64 v[48:49], v[68:69], v[26:27]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[50:51], v[54:55], -v[34:35]
	v_mul_f64 v[52:53], v[36:37], v[34:35]
	v_add_f64 v[64:65], v[36:37], -v[64:65]
	v_add_f64 v[54:55], v[66:67], -v[38:39]
	v_mul_f64 v[66:67], v[48:49], v[38:39]
	v_add_f64 v[68:69], v[48:49], -v[68:69]
	v_add_f64 v[30:31], v[30:31], v[50:51]
	v_fma_f64 v[50:51], v[36:37], v[34:35], -v[52:53]
	v_add_f64 v[28:29], v[28:29], -v[64:65]
	v_add_f64 v[32:33], v[32:33], v[54:55]
	v_fma_f64 v[54:55], v[48:49], v[38:39], -v[66:67]
	v_add_f64 v[26:27], v[26:27], -v[68:69]
	v_fma_f64 v[30:31], v[36:37], v[30:31], v[50:51]
	v_frexp_exp_i32_f64_e32 v36, v[4:5]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[32:33], v[48:49], v[32:33], v[54:55]
	v_fma_f64 v[28:29], v[28:29], v[34:35], v[30:31]
	v_frexp_exp_i32_f64_e32 v34, v[2:3]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[26:27], v[26:27], v[38:39], v[32:33]
	v_add_f64 v[30:31], v[52:53], v[28:29]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_co_ci_u32_e32 v34, vcc_lo, 0, v34, vcc_lo
	v_subrev_co_ci_u32_e64 v48, vcc_lo, 0, v36, s0
	v_cvt_f64_i32_e32 v[34:35], v34
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_4)
	v_cvt_f64_i32_e32 v[48:49], v48
	v_add_f64 v[32:33], v[66:67], v[26:27]
	v_add_f64 v[36:37], v[22:23], v[30:31]
	v_add_f64 v[38:39], v[30:31], -v[52:53]
	v_mul_f64 v[54:55], v[34:35], s[2:3]
	v_add_f64 v[50:51], v[24:25], v[32:33]
	v_add_f64 v[52:53], v[32:33], -v[66:67]
	v_add_f64 v[22:23], v[36:37], -v[22:23]
	v_add_f64 v[28:29], v[28:29], -v[38:39]
	v_mul_f64 v[38:39], v[48:49], s[2:3]
	v_add_f64 v[24:25], v[50:51], -v[24:25]
	v_add_f64 v[26:27], v[26:27], -v[52:53]
	v_fma_f64 v[52:53], v[34:35], s[2:3], -v[54:55]
	v_add_f64 v[22:23], v[30:31], -v[22:23]
	v_add_f64 v[6:7], v[6:7], v[28:29]
	v_fma_f64 v[28:29], v[48:49], s[2:3], -v[38:39]
	s_mov_b32 s3, 0xbfe62e42
	v_add_f64 v[24:25], v[32:33], -v[24:25]
	v_add_f64 v[20:21], v[20:21], v[26:27]
	v_fma_f64 v[26:27], v[34:35], s[4:5], v[52:53]
	v_add_f64 v[6:7], v[6:7], v[22:23]
	v_fma_f64 v[22:23], v[48:49], s[4:5], v[28:29]
	s_mov_b32 s5, 0xbc7abc9e
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[20:21], v[20:21], v[24:25]
	v_add_f64 v[24:25], v[54:55], v[26:27]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[28:29], v[36:37], v[6:7]
	v_add_f64 v[30:31], v[38:39], v[22:23]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[32:33], v[50:51], v[20:21]
	v_add_f64 v[54:55], v[24:25], -v[54:55]
	s_delay_alu instid0(VALU_DEP_4)
	v_add_f64 v[34:35], v[24:25], v[28:29]
	v_add_f64 v[36:37], v[28:29], -v[36:37]
	v_add_f64 v[38:39], v[30:31], -v[38:39]
	v_add_f64 v[48:49], v[30:31], v[32:33]
	v_add_f64 v[50:51], v[32:33], -v[50:51]
	v_add_f64 v[26:27], v[26:27], -v[54:55]
	v_add_f64 v[52:53], v[34:35], -v[24:25]
	v_add_f64 v[6:7], v[6:7], -v[36:37]
	v_add_f64 v[22:23], v[22:23], -v[38:39]
	v_add_f64 v[64:65], v[48:49], -v[30:31]
	v_add_f64 v[20:21], v[20:21], -v[50:51]
	v_add_f64 v[66:67], v[34:35], -v[52:53]
	v_add_f64 v[28:29], v[28:29], -v[52:53]
	v_add_f64 v[36:37], v[26:27], v[6:7]
	v_add_f64 v[68:69], v[48:49], -v[64:65]
	v_add_f64 v[32:33], v[32:33], -v[64:65]
	v_add_f64 v[24:25], v[24:25], -v[66:67]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[30:31], v[30:31], -v[68:69]
	v_add_f64 v[24:25], v[28:29], v[24:25]
	v_add_f64 v[28:29], v[22:23], v[20:21]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f64 v[30:31], v[32:33], v[30:31]
	v_add_f64 v[32:33], v[36:37], -v[26:27]
	v_add_f64 v[24:25], v[36:37], v[24:25]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[38:39], v[28:29], -v[22:23]
	v_add_f64 v[30:31], v[28:29], v[30:31]
	s_delay_alu instid0(VALU_DEP_4)
	v_add_f64 v[36:37], v[36:37], -v[32:33]
	v_add_f64 v[6:7], v[6:7], -v[32:33]
	v_add_f64 v[50:51], v[34:35], v[24:25]
	v_add_f64 v[28:29], v[28:29], -v[38:39]
	v_add_f64 v[20:21], v[20:21], -v[38:39]
	v_mad_u64_u32 v[38:39], null, v14, s1, v[15:16]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v39, 31, v38
	v_lshlrev_b64 v[14:15], 3, v[38:39]
	v_add_f64 v[52:53], v[48:49], v[30:31]
	v_add_f64 v[26:27], v[26:27], -v[36:37]
	v_add_f64 v[32:33], v[50:51], -v[34:35]
	v_add_f64 v[22:23], v[22:23], -v[28:29]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[28:29], v[52:53], -v[48:49]
	v_add_f64 v[6:7], v[6:7], v[26:27]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[24:25], v[24:25], -v[32:33]
	v_add_f64 v[20:21], v[20:21], v[22:23]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[22:23], v[30:31], -v[28:29]
	v_add_f64 v[6:7], v[6:7], v[24:25]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[20:21], v[20:21], v[22:23]
	v_add_f64 v[22:23], v[50:51], v[6:7]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[24:25], v[52:53], v[20:21]
	v_add_f64 v[26:27], v[22:23], -v[50:51]
	v_add_f64 v[28:29], v[22:23], v[22:23]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f64 v[30:31], v[24:25], -v[52:53]
	v_add_f64 v[32:33], v[24:25], v[24:25]
	v_add_f64 v[6:7], v[6:7], -v[26:27]
	s_delay_alu instid0(VALU_DEP_4)
	v_fma_f64 v[22:23], v[22:23], 2.0, -v[28:29]
	v_cmp_class_f64_e64 vcc_lo, v[28:29], 0x204
	v_add_f64 v[20:21], v[20:21], -v[30:31]
	v_fma_f64 v[24:25], v[24:25], 2.0, -v[32:33]
	v_cmp_class_f64_e64 s0, v[32:33], 0x204
	v_fma_f64 v[6:7], v[6:7], 2.0, v[22:23]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[20:21], v[20:21], 2.0, v[24:25]
	v_add_f64 v[22:23], v[28:29], v[6:7]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[24:25], v[32:33], v[20:21]
	v_dual_cndmask_b32 v27, v23, v29 :: v_dual_cndmask_b32 v26, v22, v28
	v_add_co_u32 v0, vcc_lo, v0, v14
	v_add_co_ci_u32_e32 v1, vcc_lo, v1, v15, vcc_lo
	s_delay_alu instid0(VALU_DEP_3)
	v_mul_f64 v[30:31], v[26:27], s[8:9]
	s_clause 0x1
	flat_load_b64 v[0:1], v[0:1]
	flat_load_b64 v[48:49], v[18:19]
	v_add_f64 v[22:23], v[22:23], -v[28:29]
	v_cndmask_b32_e64 v35, v25, v33, s0
	v_cndmask_b32_e64 v34, v24, v32, s0
	s_mov_b32 s0, 0xfca7ab0c
	s_mov_b32 s1, 0x3e928af3
	v_add_f64 v[24:25], v[24:25], -v[32:33]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_mul_f64 v[36:37], v[34:35], s[8:9]
	v_rndne_f64_e32 v[30:31], v[30:31]
	v_add_f64 v[6:7], v[6:7], -v[22:23]
	v_add_f64 v[20:21], v[20:21], -v[24:25]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_rndne_f64_e32 v[36:37], v[36:37]
	v_fma_f64 v[38:39], v[30:31], s[2:3], v[26:27]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_fma_f64 v[14:15], v[36:37], s[2:3], v[34:35]
	s_mov_b32 s2, 0x6a5dcb37
	s_mov_b32 s3, 0x3e5ade15
	v_fma_f64 v[38:39], v[30:31], s[4:5], v[38:39]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_fma_f64 v[14:15], v[36:37], s[4:5], v[14:15]
	v_cmp_nlt_f64_e64 s4, 0x40900000, v[34:35]
	v_cmp_ngt_f64_e64 s5, 0xc090cc00, v[34:35]
	v_fma_f64 v[50:51], v[38:39], s[2:3], s[0:1]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
	v_fma_f64 v[52:53], v[14:15], s[2:3], s[0:1]
	s_mov_b32 s0, 0x623fde64
	s_mov_b32 s1, 0x3ec71dee
	v_cmp_nlt_f64_e64 s2, 0x40900000, v[26:27]
	v_cmp_ngt_f64_e64 s3, 0xc090cc00, v[26:27]
	v_fma_f64 v[50:51], v[38:39], v[50:51], s[0:1]
	s_delay_alu instid0(VALU_DEP_4)
	v_fma_f64 v[52:53], v[14:15], v[52:53], s[0:1]
	s_mov_b32 s0, 0x7c89e6b0
	s_mov_b32 s1, 0x3efa0199
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[50:51], v[38:39], v[50:51], s[0:1]
	s_delay_alu instid0(VALU_DEP_2)
	v_fma_f64 v[52:53], v[14:15], v[52:53], s[0:1]
	s_mov_b32 s0, 0x14761f6e
	s_mov_b32 s1, 0x3f2a01a0
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[50:51], v[38:39], v[50:51], s[0:1]
	s_delay_alu instid0(VALU_DEP_2)
	v_fma_f64 v[52:53], v[14:15], v[52:53], s[0:1]
	s_mov_b32 s0, 0x1852b7b0
	s_mov_b32 s1, 0x3f56c16c
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[50:51], v[38:39], v[50:51], s[0:1]
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_div_scale_f64 v[54:55], null, v[48:49], v[48:49], v[0:1]
	s_delay_alu instid0(VALU_DEP_3)
	v_fma_f64 v[52:53], v[14:15], v[52:53], s[0:1]
	s_mov_b32 s0, 0x11122322
	s_mov_b32 s1, 0x3f811111
	s_delay_alu instid0(VALU_DEP_3) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[50:51], v[38:39], v[50:51], s[0:1]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rcp_f64_e32 v[64:65], v[54:55]
	v_fma_f64 v[52:53], v[14:15], v[52:53], s[0:1]
	s_mov_b32 s0, 0x555502a1
	s_mov_b32 s1, 0x3fa55555
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[50:51], v[38:39], v[50:51], s[0:1]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[66:67], -v[54:55], v[64:65], 1.0
	v_fma_f64 v[52:53], v[14:15], v[52:53], s[0:1]
	s_mov_b32 s0, 0x55555511
	s_mov_b32 s1, 0x3fc55555
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[50:51], v[38:39], v[50:51], s[0:1]
	v_fma_f64 v[64:65], v[64:65], v[66:67], v[64:65]
	v_cvt_i32_f64_e32 v66, v[30:31]
	s_delay_alu instid0(VALU_DEP_4)
	v_fma_f64 v[52:53], v[14:15], v[52:53], s[0:1]
	s_mov_b32 s0, 11
	s_mov_b32 s1, 0x3fe00000
	s_delay_alu instid0(VALU_DEP_4) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[50:51], v[38:39], v[50:51], s[0:1]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_fma_f64 v[52:53], v[14:15], v[52:53], s[0:1]
	v_cmp_neq_f64_e64 s0, 0x7ff00000, |v[26:27]|
	v_cmp_neq_f64_e64 s1, 0x7ff00000, |v[34:35]|
	v_fma_f64 v[50:51], v[38:39], v[50:51], 1.0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[52:53], v[14:15], v[52:53], 1.0
	v_cndmask_b32_e64 v7, 0, v7, s0
	v_cndmask_b32_e64 v6, 0, v6, s0
	s_and_b32 s0, s3, s2
	v_cndmask_b32_e64 v21, 0, v21, s1
	v_fma_f64 v[30:31], v[38:39], v[50:51], 1.0
	v_cvt_i32_f64_e32 v38, v[36:37]
	v_fma_f64 v[36:37], -v[54:55], v[64:65], 1.0
	v_cndmask_b32_e64 v20, 0, v20, s1
	v_fma_f64 v[14:15], v[14:15], v[52:53], 1.0
	v_ldexp_f64 v[28:29], v[30:31], v66
	v_div_scale_f64 v[30:31], vcc_lo, v[0:1], v[48:49], v[0:1]
	v_fma_f64 v[32:33], v[64:65], v[36:37], v[64:65]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_ldexp_f64 v[14:15], v[14:15], v38
	v_cndmask_b32_e64 v24, 0x7ff00000, v29, s2
	v_cmp_neq_f64_e64 s2, 0x7ff00000, |v[2:3]|
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f64 v[22:23], v[30:31], v[32:33]
	v_cndmask_b32_e64 v25, 0, v24, s3
	v_cndmask_b32_e64 v24, 0, v28, s0
	s_and_b32 s0, s5, s4
	v_cmp_neq_f64_e64 s3, 0, v[2:3]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_4)
	v_fma_f64 v[6:7], v[24:25], v[6:7], v[24:25]
	v_cndmask_b32_e64 v15, 0x7ff00000, v15, s4
	v_cndmask_b32_e64 v14, 0, v14, s0
	v_cmp_class_f64_e64 s0, v[24:25], 0x204
	v_cmp_neq_f64_e64 s4, 0x7ff00000, |v[4:5]|
	v_cndmask_b32_e64 v15, 0, v15, s5
	v_cmp_neq_f64_e64 s5, 0, v[4:5]
	v_fma_f64 v[26:27], -v[54:55], v[22:23], v[30:31]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_fma_f64 v[20:21], v[14:15], v[20:21], v[14:15]
	v_cmp_class_f64_e64 s1, v[14:15], 0x204
	v_cndmask_b32_e64 v7, v7, v25, s0
	v_cndmask_b32_e64 v4, v6, v24, s0
	v_and_b32_e32 v7, 0x7fffffff, v7
	v_div_fmas_f64 v[2:3], v[26:27], v[32:33], v[22:23]
	s_and_b32 vcc_lo, s3, s2
	v_cndmask_b32_e64 v15, v21, v15, s1
	s_delay_alu instid0(VALU_DEP_3)
	v_cndmask_b32_e64 v7, 0x7ff00000, v7, s2
	v_cndmask_b32_e64 v6, v20, v14, s1
	v_cndmask_b32_e32 v4, 0, v4, vcc_lo
	s_and_b32 vcc_lo, s5, s4
	v_and_b32_e32 v15, 0x7fffffff, v15
	v_cndmask_b32_e64 v5, 0, v7, s3
	v_cndmask_b32_e32 v6, 0, v6, vcc_lo
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, Cv_d@rel32@lo+4
	s_addc_u32 s1, s1, Cv_d@rel32@hi+12
	v_cndmask_b32_e64 v15, 0x7ff00000, v15, s4
	s_load_b64 s[0:1], s[0:1], 0x0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v7, 0, v15, s5
	v_div_fixup_f64 v[0:1], v[2:3], v[48:49], v[0:1]
	v_add_f64 v[2:3], v[4:5], v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f64 v[0:1], v[2:3], -0.5, v[0:1]
	s_waitcnt lgkmcnt(0)
	v_div_scale_f64 v[2:3], null, s[0:1], s[0:1], v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[4:5], v[2:3]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0
	v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0
	v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5]
	v_div_scale_f64 v[6:7], vcc_lo, v[0:1], s[0:1], v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[14:15], v[6:7], v[4:5]
	v_fma_f64 v[2:3], -v[2:3], v[14:15], v[6:7]
	s_delay_alu instid0(VALU_DEP_1)
	v_div_fmas_f64 v[2:3], v[2:3], v[4:5], v[14:15]
	v_add_co_u32 v4, vcc_lo, v12, v16
	v_add_co_ci_u32_e32 v5, vcc_lo, v13, v17, vcc_lo
	v_add_co_u32 v6, vcc_lo, v10, v16
	v_add_co_ci_u32_e32 v7, vcc_lo, v11, v17, vcc_lo
	v_div_fixup_f64 v[2:3], v[2:3], s[0:1], v[0:1]
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, R_d@rel32@lo+4
	s_addc_u32 s1, s1, R_d@rel32@hi+12
	flat_store_b64 v[4:5], v[0:1]
	flat_store_b64 v[6:7], v[2:3]
	flat_load_b64 v[0:1], v[18:19]
	s_load_b64 s[0:1], s[0:1], 0x0
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_mul_f64 v[0:1], v[0:1], s[0:1]
	s_delay_alu instid0(VALU_DEP_1)
	v_mul_f64 v[0:1], v[0:1], v[2:3]
	v_add_co_u32 v2, vcc_lo, v8, v16
	v_add_co_ci_u32_e32 v3, vcc_lo, v9, v17, vcc_lo
	flat_store_b64 v[2:3], v[0:1]
	s_waitcnt lgkmcnt(0)
	s_setpc_b64 s[30:31]
.Lfunc_end2:
	.size	_Z15primativesFromQPdS_S_S_S_S_S_ii, .Lfunc_end2-_Z15primativesFromQPdS_S_S_S_S_S_ii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Function info:
; codeLenInByte = 4240
; NumSgprs: 34
; NumVgprs: 82
; ScratchSize: 0
; MemoryBound: 0
	.text
	.protected	_Z19iterateScheme_part2PdS_S_S_S_S_S_S_S_S_S_S_ddd ; -- Begin function _Z19iterateScheme_part2PdS_S_S_S_S_S_S_S_S_S_S_ddd
	.globl	_Z19iterateScheme_part2PdS_S_S_S_S_S_S_S_S_S_S_ddd
	.p2align	8
	.type	_Z19iterateScheme_part2PdS_S_S_S_S_S_S_S_S_S_S_ddd,@function
_Z19iterateScheme_part2PdS_S_S_S_S_S_S_S_S_S_S_ddd: ; @_Z19iterateScheme_part2PdS_S_S_S_S_S_S_S_S_S_S_ddd
; %bb.0:
	s_load_b32 s4, s[0:1], 0x84
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, jmax_d@rel32@lo+4
	s_addc_u32 s3, s3, jmax_d@rel32@hi+12
	s_getpc_b64 s[6:7]
	s_add_u32 s6, s6, kmax_d@rel32@lo+4
	s_addc_u32 s7, s7, kmax_d@rel32@hi+12
	s_load_b32 s5, s[2:3], 0x0
	s_load_b32 s6, s[6:7], 0x0
	v_and_b32_e32 v1, 0x3ff, v0
	v_bfe_u32 v0, v0, 10, 10
	s_mov_b32 s32, 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s3, s4, 0xffff
	s_lshr_b32 s2, s4, 16
	v_mad_u64_u32 v[14:15], null, s14, s3, v[1:2]
	v_mad_u64_u32 v[15:16], null, s15, s2, v[0:1]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_i32_e32 vcc_lo, s5, v14
	v_cmp_gt_i32_e64 s2, s6, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, vcc_lo, s2
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB3_5
; %bb.1:
	s_load_b512 s[8:23], s[0:1], 0x10
	v_cmp_ne_u32_e32 vcc_lo, 0, v14
	s_add_i32 s3, s5, -1
	v_cmp_ne_u32_e64 s2, 0, v15
	v_cmp_ne_u32_e64 s3, s3, v14
	s_add_i32 s4, s6, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_ne_u32_e64 s4, s4, v15
	s_and_b32 s2, vcc_lo, s2
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, s2, s3
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, s2, s4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s4, s2
	s_cbranch_execz .LBB3_4
; %bb.2:                                ; %.preheader.i
	s_clause 0x1
	s_load_b256 s[24:31], s[0:1], 0x50
	s_load_b64 s[2:3], s[0:1], 0x70
	v_mul_lo_u32 v0, s6, v14
	s_mul_i32 s1, s6, s5
	s_mov_b32 s5, 4
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_mov_b32 v2, v15 :: v_dual_add_nc_u32 v1, s6, v0
.LBB3_3:                                ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
	v_add_nc_u32_e32 v3, v1, v2
	v_add_nc_u32_e32 v5, v0, v2
	v_add_nc_u32_e32 v2, s1, v2
	s_add_i32 s5, s5, -1
	s_cmp_lg_u32 s5, 0
	v_ashrrev_i32_e32 v4, 31, v3
	v_ashrrev_i32_e32 v6, 31, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[3:4], 3, v[3:4]
	v_lshlrev_b64 v[7:8], 3, v[5:6]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v3, vcc_lo, s24, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s25, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v5, vcc_lo, s24, v7
	v_add_co_ci_u32_e32 v6, vcc_lo, s25, v8, vcc_lo
	v_add_co_u32 v9, vcc_lo, s26, v7
	v_add_co_ci_u32_e32 v10, vcc_lo, s27, v8, vcc_lo
	s_clause 0x1
	global_load_b64 v[11:12], v[3:4], off
	global_load_b64 v[16:17], v[5:6], off
	global_load_b128 v[3:6], v[9:10], off
	v_add_co_u32 v24, vcc_lo, s20, v7
	v_add_co_ci_u32_e32 v25, vcc_lo, s21, v8, vcc_lo
	global_load_b64 v[24:25], v[24:25], off
	s_waitcnt vmcnt(2)
	v_add_f64 v[9:10], v[11:12], -v[16:17]
	s_waitcnt vmcnt(1)
	v_add_f64 v[3:4], v[5:6], -v[3:4]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_scale_f64 v[5:6], null, s[28:29], s[28:29], v[9:10]
	v_div_scale_f64 v[11:12], null, s[30:31], s[30:31], v[3:4]
	v_div_scale_f64 v[26:27], vcc_lo, v[9:10], s[28:29], v[9:10]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rcp_f64_e32 v[16:17], v[5:6]
	v_rcp_f64_e32 v[18:19], v[11:12]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[20:21], -v[5:6], v[16:17], 1.0
	v_fma_f64 v[22:23], -v[11:12], v[18:19], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[16:17], v[16:17], v[20:21], v[16:17]
	v_fma_f64 v[18:19], v[18:19], v[22:23], v[18:19]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[20:21], -v[5:6], v[16:17], 1.0
	v_fma_f64 v[22:23], -v[11:12], v[18:19], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fma_f64 v[16:17], v[16:17], v[20:21], v[16:17]
	v_div_scale_f64 v[20:21], s0, v[3:4], s[30:31], v[3:4]
	v_fma_f64 v[18:19], v[18:19], v[22:23], v[18:19]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[22:23], v[26:27], v[16:17]
	v_mul_f64 v[28:29], v[20:21], v[18:19]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[5:6], -v[5:6], v[22:23], v[26:27]
	v_fma_f64 v[11:12], -v[11:12], v[28:29], v[20:21]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_fmas_f64 v[5:6], v[5:6], v[16:17], v[22:23]
	s_mov_b32 vcc_lo, s0
	v_div_fmas_f64 v[11:12], v[11:12], v[18:19], v[28:29]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fixup_f64 v[5:6], v[5:6], s[28:29], v[9:10]
	v_div_fixup_f64 v[3:4], v[11:12], s[30:31], v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_add_f64 v[3:4], v[5:6], v[3:4]
	v_add_co_u32 v5, vcc_lo, s22, v7
	v_add_co_ci_u32_e32 v6, vcc_lo, s23, v8, vcc_lo
	s_waitcnt vmcnt(0)
	v_fma_f64 v[3:4], -v[3:4], s[2:3], v[24:25]
	global_store_b64 v[5:6], v[3:4], off
	s_cbranch_scc1 .LBB3_3
.LBB3_4:                                ; %Flow79
	s_or_b32 exec_lo, exec_lo, s4
	s_waitcnt lgkmcnt(0)
	v_dual_mov_b32 v0, s22 :: v_dual_mov_b32 v1, s23
	v_dual_mov_b32 v2, s16 :: v_dual_mov_b32 v3, s17
	v_dual_mov_b32 v4, s8 :: v_dual_mov_b32 v5, s9
	v_dual_mov_b32 v6, s10 :: v_dual_mov_b32 v7, s11
	v_dual_mov_b32 v8, s12 :: v_dual_mov_b32 v9, s13
	v_dual_mov_b32 v10, s14 :: v_dual_mov_b32 v11, s15
	v_dual_mov_b32 v12, s18 :: v_dual_mov_b32 v13, s19
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, _Z15primativesFromQPdS_S_S_S_S_S_ii@rel32@lo+4
	s_addc_u32 s1, s1, _Z15primativesFromQPdS_S_S_S_S_S_ii@rel32@hi+12
	s_delay_alu instid0(SALU_CYCLE_1)
	s_swappc_b64 s[30:31], s[0:1]
.LBB3_5:
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z19iterateScheme_part2PdS_S_S_S_S_S_S_S_S_S_S_ddd
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 376
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 82
		.amdhsa_next_free_sgpr 33
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end3:
	.size	_Z19iterateScheme_part2PdS_S_S_S_S_S_S_S_S_S_S_ddd, .Lfunc_end3-_Z19iterateScheme_part2PdS_S_S_S_S_S_S_S_S_S_S_ddd
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 804
; NumSgprs: 35
; NumVgprs: 82
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 4
; VGPRBlocks: 10
; NumSGPRsForWavesPerEU: 35
; NumVGPRsForWavesPerEU: 82
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z19iterateScheme_part3PdS_S_S_S_S_S_S_S_S_S_S_ddd ; -- Begin function _Z19iterateScheme_part3PdS_S_S_S_S_S_S_S_S_S_S_ddd
	.globl	_Z19iterateScheme_part3PdS_S_S_S_S_S_S_S_S_S_S_ddd
	.p2align	8
	.type	_Z19iterateScheme_part3PdS_S_S_S_S_S_S_S_S_S_S_ddd,@function
_Z19iterateScheme_part3PdS_S_S_S_S_S_S_S_S_S_S_ddd: ; @_Z19iterateScheme_part3PdS_S_S_S_S_S_S_S_S_S_S_ddd
; %bb.0:
	s_load_b32 s6, s[0:1], 0x84
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, jmax_d@rel32@lo+4
	s_addc_u32 s3, s3, jmax_d@rel32@hi+12
	s_getpc_b64 s[4:5]
	s_add_u32 s4, s4, kmax_d@rel32@lo+4
	s_addc_u32 s5, s5, kmax_d@rel32@hi+12
	s_load_b32 s3, s[2:3], 0x0
	s_load_b32 s12, s[4:5], 0x0
	v_and_b32_e32 v1, 0x3ff, v0
	v_bfe_u32 v0, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s2, s6, 16
	s_and_b32 s4, s6, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[4:5], null, s14, s4, v[1:2]
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	v_cmp_gt_i32_e32 vcc_lo, s3, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_gt_i32_e64 s2, s12, v1
	s_and_b32 s2, vcc_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s4, s2
	s_cbranch_execz .LBB4_13
; %bb.1:
	s_load_b256 s[4:11], s[0:1], 0x10
	v_mul_lo_u32 v5, s12, v4
	v_or_b32_e32 v2, v1, v4
	s_mov_b32 s0, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_ne_u32_e32 vcc_lo, 0, v2
                                        ; implicit-def: $vgpr2_vgpr3
	v_add_nc_u32_e32 v0, v5, v1
	s_and_saveexec_b32 s1, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s1, exec_lo, s1
	s_cbranch_execz .LBB4_9
; %bb.2:
	s_add_i32 s0, s12, -1
	v_cmp_ne_u32_e32 vcc_lo, 0, v4
	v_cmp_ne_u32_e64 s0, s0, v1
	s_mov_b32 s2, 0
                                        ; implicit-def: $vgpr2_vgpr3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, vcc_lo, s0
	s_and_saveexec_b32 s13, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s0, exec_lo, s13
	s_cbranch_execz .LBB4_6
; %bb.3:
	s_add_i32 s3, s3, -1
                                        ; implicit-def: $vgpr2_vgpr3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_eq_u32_e32 vcc_lo, s3, v4
	s_and_saveexec_b32 s3, vcc_lo
	s_xor_b32 s3, exec_lo, s3
	s_cbranch_execz .LBB4_5
; %bb.4:
	v_subrev_nc_u32_e32 v2, s12, v5
	s_mov_b32 s2, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v3, s12, v2
	v_add_nc_u32_e32 v2, v2, v1
	v_add_nc_u32_e32 v4, v3, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_ashrrev_i32_e32 v3, 31, v2
	v_ashrrev_i32_e32 v1, 31, v0
	v_ashrrev_i32_e32 v5, 31, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[2:3], 3, v[2:3]
	v_lshlrev_b64 v[4:5], 3, v[4:5]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v6, vcc_lo, s4, v2
	v_add_co_ci_u32_e32 v7, vcc_lo, s5, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v8, vcc_lo, s4, v4
	v_add_co_ci_u32_e32 v9, vcc_lo, s5, v5, vcc_lo
	s_clause 0x1
	global_load_b64 v[6:7], v[6:7], off
	global_load_b64 v[8:9], v[8:9], off
	s_waitcnt vmcnt(0)
	v_fma_f64 v[6:7], v[6:7], 2.0, -v[8:9]
	v_lshlrev_b64 v[8:9], 3, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v10, vcc_lo, s4, v8
	v_add_co_ci_u32_e32 v11, vcc_lo, s5, v9, vcc_lo
	v_add_co_u32 v12, vcc_lo, s6, v2
	v_add_co_ci_u32_e32 v13, vcc_lo, s7, v3, vcc_lo
	v_add_co_u32 v14, vcc_lo, s6, v4
	v_add_co_ci_u32_e32 v15, vcc_lo, s7, v5, vcc_lo
	global_store_b64 v[10:11], v[6:7], off
	s_clause 0x1
	global_load_b64 v[6:7], v[12:13], off
	global_load_b64 v[10:11], v[14:15], off
	s_waitcnt vmcnt(0)
	v_fma_f64 v[6:7], v[6:7], 2.0, -v[10:11]
	v_add_co_u32 v10, vcc_lo, s6, v8
	v_add_co_ci_u32_e32 v11, vcc_lo, s7, v9, vcc_lo
	v_add_co_u32 v12, vcc_lo, s8, v2
	v_add_co_ci_u32_e32 v13, vcc_lo, s9, v3, vcc_lo
	v_add_co_u32 v14, vcc_lo, s8, v4
	v_add_co_ci_u32_e32 v15, vcc_lo, s9, v5, vcc_lo
	v_add_co_u32 v8, vcc_lo, s8, v8
	v_add_co_ci_u32_e32 v9, vcc_lo, s9, v9, vcc_lo
	v_add_co_u32 v2, vcc_lo, s10, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s11, v3, vcc_lo
	v_add_co_u32 v4, vcc_lo, s10, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s11, v5, vcc_lo
	global_store_b64 v[10:11], v[6:7], off
	s_clause 0x1
	global_load_b64 v[6:7], v[12:13], off
	global_load_b64 v[10:11], v[14:15], off
	s_waitcnt vmcnt(0)
	v_fma_f64 v[6:7], v[6:7], 2.0, -v[10:11]
	global_store_b64 v[8:9], v[6:7], off
	s_clause 0x1
	global_load_b64 v[2:3], v[2:3], off
	global_load_b64 v[4:5], v[4:5], off
	s_waitcnt vmcnt(0)
	v_fma_f64 v[2:3], v[2:3], 2.0, -v[4:5]
.LBB4_5:                                ; %Flow35
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s2, s2, exec_lo
.LBB4_6:                                ; %Flow34
	s_and_not1_saveexec_b32 s0, s0
	s_cbranch_execz .LBB4_8
; %bb.7:
	s_getpc_b64 s[12:13]
	s_add_u32 s12, s12, u0_d@rel32@lo+4
	s_addc_u32 s13, s13, u0_d@rel32@hi+12
	s_getpc_b64 s[14:15]
	s_add_u32 s14, s14, p0_d@rel32@lo+4
	s_addc_u32 s15, s15, p0_d@rel32@hi+12
	s_load_b64 s[12:13], s[12:13], 0x0
	s_getpc_b64 s[16:17]
	s_add_u32 s16, s16, T0_d@rel32@lo+4
	s_addc_u32 s17, s17, T0_d@rel32@hi+12
	s_load_b64 s[14:15], s[14:15], 0x0
	s_load_b64 s[16:17], s[16:17], 0x0
	v_ashrrev_i32_e32 v1, 31, v0
	v_mov_b32_e32 v4, 0
	s_or_b32 s2, s2, exec_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 3, v[0:1]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v6, vcc_lo, s4, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v7, vcc_lo, s5, v3, vcc_lo
	v_add_co_u32 v8, vcc_lo, s6, v2
	v_add_co_ci_u32_e32 v9, vcc_lo, s7, v3, vcc_lo
	v_dual_mov_b32 v10, s12 :: v_dual_mov_b32 v11, s13
	v_add_co_u32 v12, vcc_lo, s8, v2
	v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v14, s14
	v_add_co_ci_u32_e32 v13, vcc_lo, s9, v3, vcc_lo
	v_dual_mov_b32 v15, s15 :: v_dual_mov_b32 v2, s16
	v_mov_b32_e32 v3, s17
	global_store_b64 v[6:7], v[10:11], off
	global_store_b64 v[8:9], v[4:5], off
	global_store_b64 v[12:13], v[14:15], off
.LBB4_8:                                ; %Flow36
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s0, s2, exec_lo
.LBB4_9:                                ; %Flow
	s_and_not1_saveexec_b32 s1, s1
	s_cbranch_execz .LBB4_11
; %bb.10:
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, p0_d@rel32@lo+4
	s_addc_u32 s3, s3, p0_d@rel32@hi+12
	s_getpc_b64 s[12:13]
	s_add_u32 s12, s12, T0_d@rel32@lo+4
	s_addc_u32 s13, s13, T0_d@rel32@hi+12
	v_ashrrev_i32_e32 v1, 31, v0
	s_load_b64 s[2:3], s[2:3], 0x0
	s_load_b64 s[12:13], s[12:13], 0x0
	s_mov_b32 s14, 0
	s_or_b32 s0, s0, exec_lo
	s_mov_b32 s15, s14
	v_lshlrev_b64 v[2:3], 3, v[0:1]
	v_dual_mov_b32 v6, s14 :: v_dual_mov_b32 v7, s15
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v4, vcc_lo, s4, v2
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
	v_add_co_u32 v8, vcc_lo, s6, v2
	v_add_co_ci_u32_e32 v9, vcc_lo, s7, v3, vcc_lo
	v_add_co_u32 v10, vcc_lo, s8, v2
	v_add_co_ci_u32_e32 v11, vcc_lo, s9, v3, vcc_lo
	v_dual_mov_b32 v13, s3 :: v_dual_mov_b32 v12, s2
	v_dual_mov_b32 v2, s12 :: v_dual_mov_b32 v3, s13
	global_store_b64 v[4:5], v[6:7], off
	global_store_b64 v[8:9], v[6:7], off
	global_store_b64 v[10:11], v[12:13], off
.LBB4_11:                               ; %Flow37
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB4_13
; %bb.12:                               ; %.sink.split.i
	v_lshlrev_b64 v[0:1], 3, v[0:1]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s10, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s11, v1, vcc_lo
	global_store_b64 v[0:1], v[2:3], off
.LBB4_13:                               ; %_Z20enforceBC_nonSurfacePdS_S_S_ii.exit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z19iterateScheme_part3PdS_S_S_S_S_S_S_S_S_S_S_ddd
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 376
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 16
		.amdhsa_next_free_sgpr 18
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end4:
	.size	_Z19iterateScheme_part3PdS_S_S_S_S_S_S_S_S_S_S_ddd, .Lfunc_end4-_Z19iterateScheme_part3PdS_S_S_S_S_S_S_S_S_S_S_ddd
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1116
; NumSgprs: 20
; NumVgprs: 16
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 20
; NumVGPRsForWavesPerEU: 16
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z19iterateScheme_part4PdS_S_S_S_S_S_S_S_S_S_S_ddd ; -- Begin function _Z19iterateScheme_part4PdS_S_S_S_S_S_S_S_S_S_S_ddd
	.globl	_Z19iterateScheme_part4PdS_S_S_S_S_S_S_S_S_S_S_ddd
	.p2align	8
	.type	_Z19iterateScheme_part4PdS_S_S_S_S_S_S_S_S_S_S_ddd,@function
_Z19iterateScheme_part4PdS_S_S_S_S_S_S_S_S_S_S_ddd: ; @_Z19iterateScheme_part4PdS_S_S_S_S_S_S_S_S_S_S_ddd
; %bb.0:
	s_load_b32 s6, s[0:1], 0x84
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, jmax_d@rel32@lo+4
	s_addc_u32 s3, s3, jmax_d@rel32@hi+12
	s_getpc_b64 s[4:5]
	s_add_u32 s4, s4, kmax_d@rel32@lo+4
	s_addc_u32 s5, s5, kmax_d@rel32@hi+12
	s_load_b32 s2, s[2:3], 0x0
	s_load_b32 s5, s[4:5], 0x0
	v_and_b32_e32 v2, 0x3ff, v0
	v_bfe_u32 v3, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_and_b32 s4, s6, 0xffff
	s_lshr_b32 s3, s6, 16
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[0:1], null, s14, s4, v[2:3]
	v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
	v_cmp_gt_i32_e32 vcc_lo, s2, v0
	v_cmp_lt_i32_e64 s4, 0, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cmp_gt_i32_e64 s2, s5, v1
	v_cmp_eq_u32_e64 s3, 0, v1
	s_and_b32 s6, vcc_lo, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_and_b32 s3, s4, s3
	s_mov_b32 s2, 0
	s_and_b32 s3, s6, s3
	s_and_saveexec_b32 s4, s3
	s_cbranch_execz .LBB5_2
; %bb.1:
	s_load_b256 s[8:15], s[0:1], 0x10
	v_mul_lo_u32 v0, s5, v0
	s_mov_b32 s3, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v1, 31, v0
	v_lshlrev_b64 v[4:5], 3, v[0:1]
	v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v2, vcc_lo, s8, v4
	v_add_co_ci_u32_e32 v3, vcc_lo, s9, v5, vcc_lo
	v_add_co_u32 v6, vcc_lo, s10, v4
	v_add_co_ci_u32_e32 v7, vcc_lo, s11, v5, vcc_lo
	v_add_co_u32 v8, vcc_lo, s12, v4
	v_add_co_ci_u32_e32 v9, vcc_lo, s13, v5, vcc_lo
	global_store_b64 v[2:3], v[0:1], off
	global_store_b64 v[6:7], v[0:1], off
	global_load_b128 v[0:3], v[8:9], off offset:8
	s_waitcnt vmcnt(0)
	v_fma_f64 v[0:1], v[0:1], 2.0, -v[2:3]
	v_add_co_u32 v2, vcc_lo, s14, v4
	v_add_co_ci_u32_e32 v3, vcc_lo, s15, v5, vcc_lo
	global_store_b64 v[8:9], v[0:1], off
	global_load_b64 v[0:1], v[2:3], off offset:8
	s_waitcnt vmcnt(0)
	global_store_b64 v[2:3], v[0:1], off
.LBB5_2:                                ; %_Z17enforceBC_surfacePdS_S_S_ii.exit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z19iterateScheme_part4PdS_S_S_S_S_S_S_S_S_S_S_ddd
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 376
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 10
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end5:
	.size	_Z19iterateScheme_part4PdS_S_S_S_S_S_S_S_S_S_S_ddd, .Lfunc_end5-_Z19iterateScheme_part4PdS_S_S_S_S_S_S_S_S_S_S_ddd
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 352
; NumSgprs: 18
; NumVgprs: 10
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 10
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z19iterateScheme_part5PdS_S_S_S_S_S_S_S_S_S_S_ddd ; -- Begin function _Z19iterateScheme_part5PdS_S_S_S_S_S_S_S_S_S_S_ddd
	.globl	_Z19iterateScheme_part5PdS_S_S_S_S_S_S_S_S_S_S_ddd
	.p2align	8
	.type	_Z19iterateScheme_part5PdS_S_S_S_S_S_S_S_S_S_S_ddd,@function
_Z19iterateScheme_part5PdS_S_S_S_S_S_S_S_S_S_S_ddd: ; @_Z19iterateScheme_part5PdS_S_S_S_S_S_S_S_S_S_S_ddd
; %bb.0:
	s_load_b32 s6, s[0:1], 0x84
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, jmax_d@rel32@lo+4
	s_addc_u32 s3, s3, jmax_d@rel32@hi+12
	s_getpc_b64 s[4:5]
	s_add_u32 s4, s4, kmax_d@rel32@lo+4
	s_addc_u32 s5, s5, kmax_d@rel32@hi+12
	s_load_b32 s2, s[2:3], 0x0
	s_load_b32 s3, s[4:5], 0x0
	v_and_b32_e32 v1, 0x3ff, v0
	v_bfe_u32 v0, v0, 10, 10
	s_mov_b32 s32, 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s5, s6, 0xffff
	s_lshr_b32 s4, s6, 16
	v_mad_u64_u32 v[13:14], null, s14, s5, v[1:2]
	v_mad_u64_u32 v[14:15], null, s15, s4, v[0:1]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_i32_e32 vcc_lo, s2, v13
	v_cmp_gt_i32_e64 s2, s3, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, vcc_lo, s2
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB6_2
; %bb.1:
	s_clause 0x1
	s_load_b256 s[4:11], s[0:1], 0x50
	s_load_b256 s[12:19], s[0:1], 0x10
	v_mov_b32_e32 v12, 0
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, _Z7calc_FGPdS_S_S_S_S_biidd@rel32@lo+4
	s_addc_u32 s1, s1, _Z7calc_FGPdS_S_S_S_S_biidd@rel32@hi+12
	s_waitcnt lgkmcnt(0)
	v_dual_mov_b32 v1, s5 :: v_dual_mov_b32 v0, s4
	v_dual_mov_b32 v3, s7 :: v_dual_mov_b32 v2, s6
	v_dual_mov_b32 v5, s13 :: v_dual_mov_b32 v4, s12
	v_dual_mov_b32 v7, s15 :: v_dual_mov_b32 v6, s14
	v_dual_mov_b32 v9, s17 :: v_dual_mov_b32 v8, s16
	v_dual_mov_b32 v11, s19 :: v_dual_mov_b32 v10, s18
	v_dual_mov_b32 v15, s8 :: v_dual_mov_b32 v16, s9
	v_dual_mov_b32 v17, s10 :: v_dual_mov_b32 v18, s11
	s_swappc_b64 s[30:31], s[0:1]
.LBB6_2:
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z19iterateScheme_part5PdS_S_S_S_S_S_S_S_S_S_S_ddd
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 12
		.amdhsa_kernarg_size 376
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 1
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 150
		.amdhsa_next_free_sgpr 72
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end6:
	.size	_Z19iterateScheme_part5PdS_S_S_S_S_S_S_S_S_S_S_ddd, .Lfunc_end6-_Z19iterateScheme_part5PdS_S_S_S_S_S_S_S_S_S_S_ddd
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 268
; NumSgprs: 74
; NumVgprs: 150
; ScratchSize: 12
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 9
; VGPRBlocks: 18
; NumSGPRsForWavesPerEU: 74
; NumVGPRsForWavesPerEU: 150
; Occupancy: 9
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 1
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z19iterateScheme_part6PdS_S_S_S_S_S_S_S_S_S_S_ddd ; -- Begin function _Z19iterateScheme_part6PdS_S_S_S_S_S_S_S_S_S_S_ddd
	.globl	_Z19iterateScheme_part6PdS_S_S_S_S_S_S_S_S_S_S_ddd
	.p2align	8
	.type	_Z19iterateScheme_part6PdS_S_S_S_S_S_S_S_S_S_S_ddd,@function
_Z19iterateScheme_part6PdS_S_S_S_S_S_S_S_S_S_S_ddd: ; @_Z19iterateScheme_part6PdS_S_S_S_S_S_S_S_S_S_S_ddd
; %bb.0:
	s_load_b32 s4, s[0:1], 0x84
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, jmax_d@rel32@lo+4
	s_addc_u32 s3, s3, jmax_d@rel32@hi+12
	s_getpc_b64 s[6:7]
	s_add_u32 s6, s6, kmax_d@rel32@lo+4
	s_addc_u32 s7, s7, kmax_d@rel32@hi+12
	s_load_b32 s5, s[2:3], 0x0
	s_load_b32 s6, s[6:7], 0x0
	v_and_b32_e32 v1, 0x3ff, v0
	v_bfe_u32 v0, v0, 10, 10
	s_mov_b32 s32, 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s3, s4, 0xffff
	s_lshr_b32 s2, s4, 16
	v_mad_u64_u32 v[14:15], null, s14, s3, v[1:2]
	v_mad_u64_u32 v[15:16], null, s15, s2, v[0:1]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_i32_e32 vcc_lo, s5, v14
	v_cmp_gt_i32_e64 s2, s6, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, vcc_lo, s2
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB7_5
; %bb.1:
	s_load_b512 s[8:23], s[0:1], 0x10
	v_cmp_ne_u32_e32 vcc_lo, 0, v14
	s_add_i32 s3, s5, -1
	v_cmp_ne_u32_e64 s2, 0, v15
	v_cmp_ne_u32_e64 s3, s3, v14
	s_add_i32 s4, s6, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_ne_u32_e64 s4, s4, v15
	s_and_b32 s2, vcc_lo, s2
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, s2, s3
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, s2, s4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s4, s2
	s_cbranch_execz .LBB7_4
; %bb.2:                                ; %.preheader.i
	s_clause 0x1
	s_load_b256 s[24:31], s[0:1], 0x50
	s_load_b64 s[2:3], s[0:1], 0x70
	v_add_nc_u32_e32 v0, -1, v14
	v_mul_lo_u32 v1, s6, v14
	v_mov_b32_e32 v2, v15
	s_mul_i32 s1, s6, s5
	s_mov_b32 s5, 4
	v_mul_lo_u32 v0, s6, v0
.LBB7_3:                                ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v3, v1, v2
	v_add_nc_u32_e32 v5, v0, v2
	v_add_nc_u32_e32 v2, s1, v2
	s_add_i32 s5, s5, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	s_cmp_lg_u32 s5, 0
	v_ashrrev_i32_e32 v4, 31, v3
	v_ashrrev_i32_e32 v6, 31, v5
	v_lshlrev_b64 v[7:8], 3, v[3:4]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[3:4], 3, v[5:6]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v5, vcc_lo, s24, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v6, vcc_lo, s25, v8, vcc_lo
	v_add_co_u32 v3, vcc_lo, s24, v3
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v4, vcc_lo, s25, v4, vcc_lo
	v_add_co_u32 v9, vcc_lo, s26, v7
	v_add_co_ci_u32_e32 v10, vcc_lo, s27, v8, vcc_lo
	s_clause 0x1
	global_load_b64 v[11:12], v[5:6], off
	global_load_b64 v[16:17], v[3:4], off
	global_load_b128 v[3:6], v[9:10], off offset:-8
	v_add_co_u32 v20, vcc_lo, s20, v7
	v_add_co_ci_u32_e32 v21, vcc_lo, s21, v8, vcc_lo
	v_add_co_u32 v7, vcc_lo, s22, v7
	v_add_co_ci_u32_e32 v8, vcc_lo, s23, v8, vcc_lo
	global_load_b64 v[22:23], v[20:21], off
	global_load_b64 v[7:8], v[7:8], off
	s_waitcnt vmcnt(3)
	v_add_f64 v[9:10], v[11:12], -v[16:17]
	s_waitcnt vmcnt(2)
	v_add_f64 v[3:4], v[5:6], -v[3:4]
	s_waitcnt vmcnt(0)
	v_add_f64 v[7:8], v[22:23], v[7:8]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_div_scale_f64 v[5:6], null, s[28:29], s[28:29], v[9:10]
	v_div_scale_f64 v[11:12], null, s[30:31], s[30:31], v[3:4]
	v_div_scale_f64 v[28:29], vcc_lo, v[9:10], s[28:29], v[9:10]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rcp_f64_e32 v[16:17], v[5:6]
	v_rcp_f64_e32 v[18:19], v[11:12]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[24:25], -v[5:6], v[16:17], 1.0
	v_fma_f64 v[26:27], -v[11:12], v[18:19], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[16:17], v[16:17], v[24:25], v[16:17]
	v_fma_f64 v[18:19], v[18:19], v[26:27], v[18:19]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[24:25], -v[5:6], v[16:17], 1.0
	v_fma_f64 v[26:27], -v[11:12], v[18:19], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fma_f64 v[16:17], v[16:17], v[24:25], v[16:17]
	v_div_scale_f64 v[24:25], s0, v[3:4], s[30:31], v[3:4]
	v_fma_f64 v[18:19], v[18:19], v[26:27], v[18:19]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[26:27], v[28:29], v[16:17]
	v_mul_f64 v[30:31], v[24:25], v[18:19]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[5:6], -v[5:6], v[26:27], v[28:29]
	v_fma_f64 v[11:12], -v[11:12], v[30:31], v[24:25]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_fmas_f64 v[5:6], v[5:6], v[16:17], v[26:27]
	s_mov_b32 vcc_lo, s0
	v_div_fmas_f64 v[11:12], v[11:12], v[18:19], v[30:31]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fixup_f64 v[5:6], v[5:6], s[28:29], v[9:10]
	v_div_fixup_f64 v[3:4], v[11:12], s[30:31], v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[3:4], v[5:6], v[3:4]
	v_fma_f64 v[3:4], -v[3:4], s[2:3], v[7:8]
	s_delay_alu instid0(VALU_DEP_1)
	v_mul_f64 v[3:4], v[3:4], 0.5
	global_store_b64 v[20:21], v[3:4], off
	s_cbranch_scc1 .LBB7_3
.LBB7_4:                                ; %Flow79
	s_or_b32 exec_lo, exec_lo, s4
	s_waitcnt lgkmcnt(0)
	v_dual_mov_b32 v0, s20 :: v_dual_mov_b32 v1, s21
	v_dual_mov_b32 v2, s16 :: v_dual_mov_b32 v3, s17
	v_dual_mov_b32 v4, s8 :: v_dual_mov_b32 v5, s9
	v_dual_mov_b32 v6, s10 :: v_dual_mov_b32 v7, s11
	v_dual_mov_b32 v8, s12 :: v_dual_mov_b32 v9, s13
	v_dual_mov_b32 v10, s14 :: v_dual_mov_b32 v11, s15
	v_dual_mov_b32 v12, s18 :: v_dual_mov_b32 v13, s19
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, _Z15primativesFromQPdS_S_S_S_S_S_ii@rel32@lo+4
	s_addc_u32 s1, s1, _Z15primativesFromQPdS_S_S_S_S_S_ii@rel32@hi+12
	s_delay_alu instid0(SALU_CYCLE_1)
	s_swappc_b64 s[30:31], s[0:1]
.LBB7_5:
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z19iterateScheme_part6PdS_S_S_S_S_S_S_S_S_S_S_ddd
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 376
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 82
		.amdhsa_next_free_sgpr 33
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end7:
	.size	_Z19iterateScheme_part6PdS_S_S_S_S_S_S_S_S_S_S_ddd, .Lfunc_end7-_Z19iterateScheme_part6PdS_S_S_S_S_S_S_S_S_S_S_ddd
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 840
; NumSgprs: 35
; NumVgprs: 82
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 4
; VGPRBlocks: 10
; NumSGPRsForWavesPerEU: 35
; NumVGPRsForWavesPerEU: 82
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z19iterateScheme_part7PdS_S_S_S_S_S_S_S_S_S_S_ddd ; -- Begin function _Z19iterateScheme_part7PdS_S_S_S_S_S_S_S_S_S_S_ddd
	.globl	_Z19iterateScheme_part7PdS_S_S_S_S_S_S_S_S_S_S_ddd
	.p2align	8
	.type	_Z19iterateScheme_part7PdS_S_S_S_S_S_S_S_S_S_S_ddd,@function
_Z19iterateScheme_part7PdS_S_S_S_S_S_S_S_S_S_S_ddd: ; @_Z19iterateScheme_part7PdS_S_S_S_S_S_S_S_S_S_S_ddd
; %bb.0:
	s_load_b32 s6, s[0:1], 0x84
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, jmax_d@rel32@lo+4
	s_addc_u32 s3, s3, jmax_d@rel32@hi+12
	s_getpc_b64 s[4:5]
	s_add_u32 s4, s4, kmax_d@rel32@lo+4
	s_addc_u32 s5, s5, kmax_d@rel32@hi+12
	s_load_b32 s3, s[2:3], 0x0
	s_load_b32 s12, s[4:5], 0x0
	v_and_b32_e32 v1, 0x3ff, v0
	v_bfe_u32 v0, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s2, s6, 16
	s_and_b32 s4, s6, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[4:5], null, s14, s4, v[1:2]
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	v_cmp_gt_i32_e32 vcc_lo, s3, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_gt_i32_e64 s2, s12, v1
	s_and_b32 s2, vcc_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s4, s2
	s_cbranch_execz .LBB8_13
; %bb.1:
	s_load_b256 s[4:11], s[0:1], 0x10
	v_mul_lo_u32 v5, s12, v4
	v_or_b32_e32 v2, v1, v4
	s_mov_b32 s0, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_ne_u32_e32 vcc_lo, 0, v2
                                        ; implicit-def: $vgpr2_vgpr3
	v_add_nc_u32_e32 v0, v5, v1
	s_and_saveexec_b32 s1, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s1, exec_lo, s1
	s_cbranch_execz .LBB8_9
; %bb.2:
	s_add_i32 s0, s12, -1
	v_cmp_ne_u32_e32 vcc_lo, 0, v4
	v_cmp_ne_u32_e64 s0, s0, v1
	s_mov_b32 s2, 0
                                        ; implicit-def: $vgpr2_vgpr3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, vcc_lo, s0
	s_and_saveexec_b32 s13, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s0, exec_lo, s13
	s_cbranch_execz .LBB8_6
; %bb.3:
	s_add_i32 s3, s3, -1
                                        ; implicit-def: $vgpr2_vgpr3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_eq_u32_e32 vcc_lo, s3, v4
	s_and_saveexec_b32 s3, vcc_lo
	s_xor_b32 s3, exec_lo, s3
	s_cbranch_execz .LBB8_5
; %bb.4:
	v_subrev_nc_u32_e32 v2, s12, v5
	s_mov_b32 s2, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v3, s12, v2
	v_add_nc_u32_e32 v2, v2, v1
	v_add_nc_u32_e32 v4, v3, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_ashrrev_i32_e32 v3, 31, v2
	v_ashrrev_i32_e32 v1, 31, v0
	v_ashrrev_i32_e32 v5, 31, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[2:3], 3, v[2:3]
	v_lshlrev_b64 v[4:5], 3, v[4:5]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v6, vcc_lo, s4, v2
	v_add_co_ci_u32_e32 v7, vcc_lo, s5, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v8, vcc_lo, s4, v4
	v_add_co_ci_u32_e32 v9, vcc_lo, s5, v5, vcc_lo
	s_clause 0x1
	global_load_b64 v[6:7], v[6:7], off
	global_load_b64 v[8:9], v[8:9], off
	s_waitcnt vmcnt(0)
	v_fma_f64 v[6:7], v[6:7], 2.0, -v[8:9]
	v_lshlrev_b64 v[8:9], 3, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v10, vcc_lo, s4, v8
	v_add_co_ci_u32_e32 v11, vcc_lo, s5, v9, vcc_lo
	v_add_co_u32 v12, vcc_lo, s6, v2
	v_add_co_ci_u32_e32 v13, vcc_lo, s7, v3, vcc_lo
	v_add_co_u32 v14, vcc_lo, s6, v4
	v_add_co_ci_u32_e32 v15, vcc_lo, s7, v5, vcc_lo
	global_store_b64 v[10:11], v[6:7], off
	s_clause 0x1
	global_load_b64 v[6:7], v[12:13], off
	global_load_b64 v[10:11], v[14:15], off
	s_waitcnt vmcnt(0)
	v_fma_f64 v[6:7], v[6:7], 2.0, -v[10:11]
	v_add_co_u32 v10, vcc_lo, s6, v8
	v_add_co_ci_u32_e32 v11, vcc_lo, s7, v9, vcc_lo
	v_add_co_u32 v12, vcc_lo, s8, v2
	v_add_co_ci_u32_e32 v13, vcc_lo, s9, v3, vcc_lo
	v_add_co_u32 v14, vcc_lo, s8, v4
	v_add_co_ci_u32_e32 v15, vcc_lo, s9, v5, vcc_lo
	v_add_co_u32 v8, vcc_lo, s8, v8
	v_add_co_ci_u32_e32 v9, vcc_lo, s9, v9, vcc_lo
	v_add_co_u32 v2, vcc_lo, s10, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s11, v3, vcc_lo
	v_add_co_u32 v4, vcc_lo, s10, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s11, v5, vcc_lo
	global_store_b64 v[10:11], v[6:7], off
	s_clause 0x1
	global_load_b64 v[6:7], v[12:13], off
	global_load_b64 v[10:11], v[14:15], off
	s_waitcnt vmcnt(0)
	v_fma_f64 v[6:7], v[6:7], 2.0, -v[10:11]
	global_store_b64 v[8:9], v[6:7], off
	s_clause 0x1
	global_load_b64 v[2:3], v[2:3], off
	global_load_b64 v[4:5], v[4:5], off
	s_waitcnt vmcnt(0)
	v_fma_f64 v[2:3], v[2:3], 2.0, -v[4:5]
.LBB8_5:                                ; %Flow35
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s2, s2, exec_lo
.LBB8_6:                                ; %Flow34
	s_and_not1_saveexec_b32 s0, s0
	s_cbranch_execz .LBB8_8
; %bb.7:
	s_getpc_b64 s[12:13]
	s_add_u32 s12, s12, u0_d@rel32@lo+4
	s_addc_u32 s13, s13, u0_d@rel32@hi+12
	s_getpc_b64 s[14:15]
	s_add_u32 s14, s14, p0_d@rel32@lo+4
	s_addc_u32 s15, s15, p0_d@rel32@hi+12
	s_load_b64 s[12:13], s[12:13], 0x0
	s_getpc_b64 s[16:17]
	s_add_u32 s16, s16, T0_d@rel32@lo+4
	s_addc_u32 s17, s17, T0_d@rel32@hi+12
	s_load_b64 s[14:15], s[14:15], 0x0
	s_load_b64 s[16:17], s[16:17], 0x0
	v_ashrrev_i32_e32 v1, 31, v0
	v_mov_b32_e32 v4, 0
	s_or_b32 s2, s2, exec_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 3, v[0:1]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v6, vcc_lo, s4, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v7, vcc_lo, s5, v3, vcc_lo
	v_add_co_u32 v8, vcc_lo, s6, v2
	v_add_co_ci_u32_e32 v9, vcc_lo, s7, v3, vcc_lo
	v_dual_mov_b32 v10, s12 :: v_dual_mov_b32 v11, s13
	v_add_co_u32 v12, vcc_lo, s8, v2
	v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v14, s14
	v_add_co_ci_u32_e32 v13, vcc_lo, s9, v3, vcc_lo
	v_dual_mov_b32 v15, s15 :: v_dual_mov_b32 v2, s16
	v_mov_b32_e32 v3, s17
	global_store_b64 v[6:7], v[10:11], off
	global_store_b64 v[8:9], v[4:5], off
	global_store_b64 v[12:13], v[14:15], off
.LBB8_8:                                ; %Flow36
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s0, s2, exec_lo
.LBB8_9:                                ; %Flow
	s_and_not1_saveexec_b32 s1, s1
	s_cbranch_execz .LBB8_11
; %bb.10:
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, p0_d@rel32@lo+4
	s_addc_u32 s3, s3, p0_d@rel32@hi+12
	s_getpc_b64 s[12:13]
	s_add_u32 s12, s12, T0_d@rel32@lo+4
	s_addc_u32 s13, s13, T0_d@rel32@hi+12
	v_ashrrev_i32_e32 v1, 31, v0
	s_load_b64 s[2:3], s[2:3], 0x0
	s_load_b64 s[12:13], s[12:13], 0x0
	s_mov_b32 s14, 0
	s_or_b32 s0, s0, exec_lo
	s_mov_b32 s15, s14
	v_lshlrev_b64 v[2:3], 3, v[0:1]
	v_dual_mov_b32 v6, s14 :: v_dual_mov_b32 v7, s15
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v4, vcc_lo, s4, v2
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
	v_add_co_u32 v8, vcc_lo, s6, v2
	v_add_co_ci_u32_e32 v9, vcc_lo, s7, v3, vcc_lo
	v_add_co_u32 v10, vcc_lo, s8, v2
	v_add_co_ci_u32_e32 v11, vcc_lo, s9, v3, vcc_lo
	v_dual_mov_b32 v13, s3 :: v_dual_mov_b32 v12, s2
	v_dual_mov_b32 v2, s12 :: v_dual_mov_b32 v3, s13
	global_store_b64 v[4:5], v[6:7], off
	global_store_b64 v[8:9], v[6:7], off
	global_store_b64 v[10:11], v[12:13], off
.LBB8_11:                               ; %Flow37
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB8_13
; %bb.12:                               ; %.sink.split.i
	v_lshlrev_b64 v[0:1], 3, v[0:1]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s10, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s11, v1, vcc_lo
	global_store_b64 v[0:1], v[2:3], off
.LBB8_13:                               ; %_Z20enforceBC_nonSurfacePdS_S_S_ii.exit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z19iterateScheme_part7PdS_S_S_S_S_S_S_S_S_S_S_ddd
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 376
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 16
		.amdhsa_next_free_sgpr 18
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end8:
	.size	_Z19iterateScheme_part7PdS_S_S_S_S_S_S_S_S_S_S_ddd, .Lfunc_end8-_Z19iterateScheme_part7PdS_S_S_S_S_S_S_S_S_S_S_ddd
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1116
; NumSgprs: 20
; NumVgprs: 16
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 20
; NumVGPRsForWavesPerEU: 16
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z19iterateScheme_part8PdS_S_S_S_S_S_S_S_S_S_S_ddd ; -- Begin function _Z19iterateScheme_part8PdS_S_S_S_S_S_S_S_S_S_S_ddd
	.globl	_Z19iterateScheme_part8PdS_S_S_S_S_S_S_S_S_S_S_ddd
	.p2align	8
	.type	_Z19iterateScheme_part8PdS_S_S_S_S_S_S_S_S_S_S_ddd,@function
_Z19iterateScheme_part8PdS_S_S_S_S_S_S_S_S_S_S_ddd: ; @_Z19iterateScheme_part8PdS_S_S_S_S_S_S_S_S_S_S_ddd
; %bb.0:
	s_load_b32 s6, s[0:1], 0x84
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, jmax_d@rel32@lo+4
	s_addc_u32 s3, s3, jmax_d@rel32@hi+12
	s_getpc_b64 s[4:5]
	s_add_u32 s4, s4, kmax_d@rel32@lo+4
	s_addc_u32 s5, s5, kmax_d@rel32@hi+12
	s_load_b32 s2, s[2:3], 0x0
	s_load_b32 s5, s[4:5], 0x0
	v_and_b32_e32 v2, 0x3ff, v0
	v_bfe_u32 v3, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_and_b32 s4, s6, 0xffff
	s_lshr_b32 s3, s6, 16
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[0:1], null, s14, s4, v[2:3]
	v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
	v_cmp_gt_i32_e32 vcc_lo, s2, v0
	v_cmp_lt_i32_e64 s4, 0, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cmp_gt_i32_e64 s2, s5, v1
	v_cmp_eq_u32_e64 s3, 0, v1
	s_and_b32 s6, vcc_lo, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_and_b32 s3, s4, s3
	s_mov_b32 s2, 0
	s_and_b32 s3, s6, s3
	s_and_saveexec_b32 s4, s3
	s_cbranch_execz .LBB9_2
; %bb.1:
	s_load_b256 s[8:15], s[0:1], 0x10
	v_mul_lo_u32 v0, s5, v0
	s_mov_b32 s3, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v1, 31, v0
	v_lshlrev_b64 v[4:5], 3, v[0:1]
	v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v2, vcc_lo, s8, v4
	v_add_co_ci_u32_e32 v3, vcc_lo, s9, v5, vcc_lo
	v_add_co_u32 v6, vcc_lo, s10, v4
	v_add_co_ci_u32_e32 v7, vcc_lo, s11, v5, vcc_lo
	v_add_co_u32 v8, vcc_lo, s12, v4
	v_add_co_ci_u32_e32 v9, vcc_lo, s13, v5, vcc_lo
	global_store_b64 v[2:3], v[0:1], off
	global_store_b64 v[6:7], v[0:1], off
	global_load_b128 v[0:3], v[8:9], off offset:8
	s_waitcnt vmcnt(0)
	v_fma_f64 v[0:1], v[0:1], 2.0, -v[2:3]
	v_add_co_u32 v2, vcc_lo, s14, v4
	v_add_co_ci_u32_e32 v3, vcc_lo, s15, v5, vcc_lo
	global_store_b64 v[8:9], v[0:1], off
	global_load_b64 v[0:1], v[2:3], off offset:8
	s_waitcnt vmcnt(0)
	global_store_b64 v[2:3], v[0:1], off
.LBB9_2:                                ; %_Z17enforceBC_surfacePdS_S_S_ii.exit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z19iterateScheme_part8PdS_S_S_S_S_S_S_S_S_S_S_ddd
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 376
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 10
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end9:
	.size	_Z19iterateScheme_part8PdS_S_S_S_S_S_S_S_S_S_S_ddd, .Lfunc_end9-_Z19iterateScheme_part8PdS_S_S_S_S_S_S_S_S_S_S_ddd
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 352
; NumSgprs: 18
; NumVgprs: 10
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 10
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.protected	jmax_d                  ; @jmax_d
	.type	jmax_d,@object
	.data
	.globl	jmax_d
	.p2align	2, 0x0
jmax_d:
	.long	70                              ; 0x46
	.size	jmax_d, 4

	.protected	kmax_d                  ; @kmax_d
	.type	kmax_d,@object
	.globl	kmax_d
	.p2align	2, 0x0
kmax_d:
	.long	70                              ; 0x46
	.size	kmax_d, 4

	.protected	plateLength_d           ; @plateLength_d
	.type	plateLength_d,@object
	.globl	plateLength_d
	.p2align	3, 0x0
plateLength_d:
	.quad	0x3ee4f8b588e368f1              ; double 1.0000000000000001E-5
	.size	plateLength_d, 8

	.protected	CFL_d                   ; @CFL_d
	.type	CFL_d,@object
	.globl	CFL_d
	.p2align	3, 0x0
CFL_d:
	.quad	0x3fc999999999999a              ; double 0.20000000000000001
	.size	CFL_d, 8

	.protected	u0_d                    ; @u0_d
	.type	u0_d,@object
	.globl	u0_d
	.p2align	3, 0x0
u0_d:
	.quad	0x4095447ae147ae14              ; double 1361.1199999999999
	.size	u0_d, 8

	.protected	gam_d                   ; @gam_d
	.type	gam_d,@object
	.globl	gam_d
	.p2align	3, 0x0
gam_d:
	.quad	0x3ff6666666666666              ; double 1.3999999999999999
	.size	gam_d, 8

	.protected	Pr_d                    ; @Pr_d
	.type	Pr_d,@object
	.globl	Pr_d
	.p2align	3, 0x0
Pr_d:
	.quad	0x3fe6b851eb851eb8              ; double 0.70999999999999996
	.size	Pr_d, 8

	.protected	R_d                     ; @R_d
	.type	R_d,@object
	.globl	R_d
	.p2align	3, 0x0
R_d:
	.quad	0x4071f00000000000              ; double 287
	.size	R_d, 8

	.protected	Cv_d                    ; @Cv_d
	.type	Cv_d,@object
	.globl	Cv_d
	.p2align	3, 0x0
Cv_d:
	.quad	0x408668cccccccccc              ; double 717.09999999999991
	.size	Cv_d, 8

	.protected	Cp_d                    ; @Cp_d
	.type	Cp_d,@object
	.globl	Cp_d
	.p2align	3, 0x0
Cp_d:
	.quad	0x408f700000000000              ; double 1006
	.size	Cp_d, 8

	.protected	mu0_d                   ; @mu0_d
	.type	mu0_d,@object
	.globl	mu0_d
	.p2align	3, 0x0
mu0_d:
	.quad	0x3ef2c36251142aeb              ; double 1.7893999999999998E-5
	.size	mu0_d, 8

	.protected	T0_d                    ; @T0_d
	.type	T0_d,@object
	.globl	T0_d
	.p2align	3, 0x0
T0_d:
	.quad	0x4072028f5c28f5c3              ; double 288.16000000000003
	.size	T0_d, 8

	.protected	p0_d                    ; @p0_d
	.type	p0_d,@object
	.globl	p0_d
	.p2align	3, 0x0
p0_d:
	.quad	0x40f8bcd000000000              ; double 101325
	.size	p0_d, 8

	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym jmax_d
	.addrsig_sym kmax_d
	.addrsig_sym u0_d
	.addrsig_sym Pr_d
	.addrsig_sym R_d
	.addrsig_sym Cv_d
	.addrsig_sym Cp_d
	.addrsig_sym mu0_d
	.addrsig_sym T0_d
	.addrsig_sym p0_d
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         48
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         56
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         64
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         72
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         80
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         88
        .size:           8
        .value_kind:     global_buffer
      - .offset:         96
        .size:           8
        .value_kind:     by_value
      - .offset:         104
        .size:           8
        .value_kind:     by_value
      - .offset:         112
        .size:           8
        .value_kind:     by_value
      - .offset:         120
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         124
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         128
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         132
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         134
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         136
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         138
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         140
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         142
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         160
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         168
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         176
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         184
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 376
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z19iterateScheme_part1PdS_S_S_S_S_S_S_S_S_S_S_ddd
    .private_segment_fixed_size: 12
    .sgpr_count:     74
    .sgpr_spill_count: 0
    .symbol:         _Z19iterateScheme_part1PdS_S_S_S_S_S_S_S_S_S_S_ddd.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     150
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         48
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         56
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         64
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         72
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         80
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         88
        .size:           8
        .value_kind:     global_buffer
      - .offset:         96
        .size:           8
        .value_kind:     by_value
      - .offset:         104
        .size:           8
        .value_kind:     by_value
      - .offset:         112
        .size:           8
        .value_kind:     by_value
      - .offset:         120
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         124
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         128
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         132
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         134
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         136
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         138
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         140
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         142
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         160
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         168
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         176
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         184
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 376
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z19iterateScheme_part2PdS_S_S_S_S_S_S_S_S_S_S_ddd
    .private_segment_fixed_size: 0
    .sgpr_count:     35
    .sgpr_spill_count: 0
    .symbol:         _Z19iterateScheme_part2PdS_S_S_S_S_S_S_S_S_S_S_ddd.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     82
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
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