#include <stdio.h>
#include <stdlib.h>
#include <cuda.h>
#include <math.h>
#include <limits.h>
#include <float.h>
#include <iostream>
#include <sys/time.h>

#define G 6.67408E-11 //Gravitational constant 

#define lvl 9		//depth of quad tree till which we'll divide plane

using namespace std;

struct vect		//Structure for 2D coordinate
{
	float x; //X coordinate
	float y; //Y coordinate
};

struct node		//Structure for each node of the quad tree

{
	vect body; //centre of mass of bodies in current node
	float mass; //total mass of bodies in current node
	int child[4]; //children indices in nodes array
	int l,r; //index limit in body array of bodies in current node
	vect min, max; //min and max X and Y coordinates of bodies belonging to current node
};

//Function to calculate Gravitational force between two bodies
__device__ vect gravity (vect a, vect b, float m1, float m2)
{
	float res=G*m1*m2;

	float r=(a.y-b.y)*(a.y-b.y)+(a.x-b.x)*(a.x-b.x);

	if (r>0)	res/=r;

	vect vec;

	vec.y=a.y-b.y;
	vec.x=a.x-b.x;

	r=sqrt(r);

	if (r>0)	vec.y/=r, vec.x/=r;

	vec.y*=res;
	vec.x*=res;

	return vec;
}

//part1 for kernel1 to find min-max among the n bodies 
//Will find min and max of X and Y coordinates for each thread lock
//Uses reduction technique
__global__ void findMinMax(vect * body, vect * min, vect * max, int n)
{
	__shared__ vect min_cache[32];
	__shared__ vect max_cache[32];

	int index=threadIdx.x+blockDim.x*blockIdx.x;

	float xmin=FLT_MAX, ymin=FLT_MAX;
	float xmax=FLT_MIN, ymax=FLT_MIN;

	while (index<n) //takes care if total number greater than total threads in kernel
	{
		xmin=fmin(xmin, body[index].x);
		ymin=fmin(ymin, body[index].y);
		xmax=fmax(xmax, body[index].x);
		ymax=fmax(ymax, body[index].y);

		index+=(blockDim.x*gridDim.x); //incrementing index by total number of threads in kernel, to take care if total number more than total threads in kernel
	}

	int tid=threadIdx.x;

	min_cache[tid].x=xmin;
	min_cache[tid].y=ymin;

	max_cache[tid].x=xmax;
	max_cache[tid].y=ymax;

	int active=blockDim.x>>1;

	do
	{
		__syncthreads();

		if (tid<active) //reduction
		{
			min_cache[tid].x=fmin(min_cache[tid].x, min_cache[tid+active].x);
			min_cache[tid].y=fmin(min_cache[tid].y, min_cache[tid+active].y);

			max_cache[tid].x=fmax(max_cache[tid].x, max_cache[tid+active].x);
			max_cache[tid].y=fmax(max_cache[tid].y, max_cache[tid+active].y);
		}

		active>>=1;
	}while (active>0);

	if (tid==0)	min[blockIdx.x]=min_cache[0], max[blockIdx.x]=max_cache[0];
}

//part2 for kernel1 to find min-max among the n bodies 
//Will find global min and max of X and Y coordinates from local min and max of above kernel

__global__ void findMMinMax(vect * mmin, vect *mmax, vect * min, vect * max, int n)
{
	__shared__ vect min_cache[32];
	__shared__ vect max_cache[32];

	int index=threadIdx.x+blockDim.x*blockIdx.x;

	float xmin=FLT_MAX, ymin=FLT_MAX;
	float xmax=FLT_MIN, ymax=FLT_MIN;

	while (index<n) //takes care if total number greater than total threads in kernel
	{
		xmin=fmin(xmin, min[index].x);
		ymin=fmin(ymin, min[index].y);
		xmax=fmax(xmax, max[index].x);
		ymax=fmax(ymax, max[index].y);

		index+=(blockDim.x*gridDim.x);
	}

	int tid=threadIdx.x;

	min_cache[tid].x=xmin;
	min_cache[tid].y=ymin;

	max_cache[tid].x=xmax;
	max_cache[tid].y=ymax;

	int active=blockDim.x>>1;

	do
	{
		__syncthreads();

		if (tid<active) //reduction
		{
			min_cache[tid].x=fmin(min_cache[tid].x, min_cache[tid+active].x);
			min_cache[tid].y=fmin(min_cache[tid].y, min_cache[tid+active].y);

			max_cache[tid].x=fmax(max_cache[tid].x, max_cache[tid+active].x);
			max_cache[tid].y=fmax(max_cache[tid].y, max_cache[tid+active].y);
		}

		active>>=1;
	}while (active>0);

	if (tid==0)	mmin[blockIdx.x]=min_cache[0], mmax[blockIdx.x]=max_cache[0];
}

//This function will construct particular level of the tree.
//Each node will be divided further into four new nodes and bodies in the array will be swapped so that bodies belonging to same node remain together in the array

//This will work as kernel 2
__global__ void construct(vect *body, float *mass, node *nodes, int level, int tot)
{
	int index=blockDim.x*blockIdx.x+threadIdx.x;
	
	int tid=index*4;

	int total = 1<<(2*level); //total nodes in current level

	int offset=((1<<(2*level))-1)/3; //total nodes in tree upto previous level
	int off=offset+total; //total nodes in tree upto current level

	while (index<total) //'while' loop will take care if total number more than total threads in kernel
	{
		index+=offset; //actual index in nodes array

		node nd=nodes[index];

		if (nodes[index].l<=nodes[index].r)
		{
			float xl=nd.min.x, xr=nd.max.x;
			float yl=nd.min.y, yr=nd.max.y;

			float xmid=xl+(xr-xl)/2;
			float ymid=yl+(yr-yl)/2;

			float l=nd.l, r=nd.r;

			node child[4];

			for (int i=0;i<4;i++)	
			{
				child[i].min.x=child[i].min.y=FLT_MAX, child[i].max.x=child[i].max.y=FLT_MIN;
					
				for (int j=0;j<4;j++)	child[i].child[j]=-1;
			}

			int i=l-1;

			float m=0, x=0, y=0, mm=0, xx=0, yy=0;
			
			for (int j=l;j<=r;j++) //swapping of bodies belonging to current node based on x-coordinates creating two children

			{
				if (body[j].x<=xmid)
				{
					i++;
					
					vect temp=body[i];
					body[i]=body[j];
					body[j]=temp;

					float t=mass[i];
					mass[i]=mass[j];
					mass[j]=t;
				}

			}

			child[2].l=l, child[2].r=i;
			child[3].l=i+1, child[3].r=r;

			for (int k=2;k<=3;k++)
			{
				m=mm=x=xx=y=yy=0;

				l=child[k].l, r=child[k].r;

				i=l-1;

				int cnt=0;

				for (int j=l;j<=r;j++) //swapping of bodies in two children created previously based on y-coordinates, each creating two new children

				{
					x+=body[j].x;
					y+=body[j].y;
					m+=mass[j];

					if (body[j].y<=ymid)
					{
						xx+=body[j].x, yy+=body[j].y, mm+=mass[j];
						cnt++;
						i++;
						
						vect temp=body[i];
						body[i]=body[j];
						body[j]=temp;

						float t=mass[i];
						mass[i]=mass[j];
						mass[j]=t;
					}
				}
				
				if(cnt>0)	child[k].mass=mm, child[k].body.x=xx/cnt, child[k].body.y=yy/cnt;

				child[k].l=l, child[k].r=i;

				mm=m-mm, xx=x-xx, yy=y-yy, cnt=r-l+1-cnt;
				
				if(cnt>0)	child[k-2].mass=mm, child[k-2].body.x=xx/cnt, child[k-2].body.y=yy/cnt;

				child[k-2].l=i+1, child[k-2].r=r;
			}			

			for (int i=0;i<4;i++)	
			{
				if (i%2)	child[i].min.x=xmid, child[i].max.x=xr;
				else	child[i].min.x=xl, child[i].max.x=xmid;
				
				if (i<2)	child[i].min.y=ymid, child[i].max.y=yr;
				else	child[i].min.y=yl, child[i].max.y=ymid;

				if (off+tid+i<tot)	nodes[off+tid+i]=child[i];
				nd.child[i]=off+tid+i;
			}	
		}
		else
		{
			for (int i=0;i<4;i++)
			{
				if (off+tid+i<tot)
				{	
					nodes[off+tid+i].l=0;
					nodes[off+tid+i].r=-1;
				}

				nd.child[i]=off+tid+i;
			}
		}

		nodes[index]=nd;

		index-=offset;
		
		index+=(blockDim.x*gridDim.x); //will take care if total number more than total threads by incrementing index by total threads.
	}
}

//This is kernel 3
//This function calculates force on bodies

__global__ void calculate(vect *body, float *mass, node *nodes, vect *force, int n, float theta)
{
	int index=blockDim.x*blockIdx.x+threadIdx.x;

	int l=((1<<(2*(lvl-1)))-1)/3; //total nodes in tree upto max depth


	while (index<n) //'while' loop takes care if total number more than total threads in kernel
	{
		int st[4*(lvl)]; //using array as stack
		int curr=0; //variable showing current top index

		st[curr]=0;

		vect bd=body[index];

		while (curr>=0) //for each body do DFS until reached leaf

		{
			int t=st[curr];
			curr--;

			node nd=nodes[t];

			float s=fmax(nd.max.x-nd.min.x, nd.max.y-nd.min.y);

			float x=bd.x-nd.body.x, y=bd.y-nd.body.y;

			float dist=sqrt(x*x+y*y);

			float val=FLT_MAX;

			if (dist>0)	val=s/dist;

			if (val<theta)	//Barnes-Hutt approximation
			{
				vect frc=gravity(nd.body, bd, nd.mass, mass[index]);

				force[index].x+=frc.x;
				force[index].y+=frc.y;
			}
			else
			{
				if (t>=l) //if reached leaf
				{
					vect frc=gravity(nd.body, bd, nd.mass, mass[index]);

					force[index].x+=frc.x;
					force[index].y+=frc.y;

					continue;
				}

				for (int i=0;i<4;i++)
				{
					int temp=nd.child[i];

					if (temp==-1 || nodes[temp].l>nodes[temp].r)	continue;
					
					st[++curr]=temp;
				}
			}
		}

		index+=(blockDim.x*gridDim.x); //will take care if total number more than total threads by incrementing index by total number of threads in kernel
	}
}

float maxx(float a, float b)
{
	return (a<b?b:a);
}

float minn(float a, float b)
{
	return (a<b?a:b);
}

int main()
{
	int n;
	printf("n : ");
	scanf("%d", &n);

	vect body[n];

	float mass[n];

	float m=0, x=0, y=0;

	for (int i=0;i<n;i++)	
	{
		body[i].x=rand()%1000000;
		body[i].y=rand()%1000000;
		mass[i]=rand()%1000000;

		m+=mass[i], x+=body[i].x, y+=body[i].y;
	}	

	x/=n, y/=n; //centre of mass of the whole system

	vect force[n];
	vect *min;
	vect *max;

	for (int i=0;i<n;i++)	force[i].x=force[i].y=0;

	vect *dforce;
	vect *dbody;
	float *dmass;

	int s=sizeof(vect)*n;
	int sz=sizeof(float)*n;

	cudaMalloc(&dbody, s);
	cudaMalloc(&dmass, sz);

	cudaMalloc(&dforce, s);
	cudaMemset(dforce, 0, s);

	cudaMalloc(&min, s);
	cudaMalloc(&max, s);

	cudaMemcpy(dbody, body, s, cudaMemcpyHostToDevice);
	cudaMemcpy(dmass, mass, sz, cudaMemcpyHostToDevice);

	int val=32;

	int block = val;

	int grid = val;

	cudaEvent_t start, stop;
	
	cudaEventCreate(&start);
	cudaEventCreate(&stop);
	
	cudaEventRecord(start);

	//This is kernel 1 which devided into 2 parts
	//bassically it find minimum and maximum from
	//the n bodies
	findMinMax<<<grid, block>>>(dbody, min, max, n);
	
	findMMinMax<<<1, block>>>(min, max, min, max, val);

	cudaEventRecord(stop);
	cudaEventSynchronize(stop);

	//milliseconds find the total kernal time in GPU
	float milliseconds = 0;
	cudaEventElapsedTime(&milliseconds, start, stop);

	vect gmin;
	vect gmax;

	cudaMemcpy(&gmin, min, sizeof(vect), cudaMemcpyDeviceToHost);
	cudaMemcpy(&gmax, max, sizeof(vect), cudaMemcpyDeviceToHost);

	int curr=1;

	int tot=1<<(2*lvl);
	tot=(tot-1)/3;

	node h_nodes[tot];

	for (int i=0;i<tot;i++)
	{
		for (int j=0;j<4;j++)	h_nodes[i].child[j]=-1;
	}

	vect temp;
	temp.x=x, temp.y=y;

	h_nodes[0].body=temp, h_nodes[0].mass=m, h_nodes[0].l=0, h_nodes[0].r=n-1, h_nodes[0].min=gmin, h_nodes[0].max=gmax;

	node *d_nodes;
	cudaMalloc(&d_nodes, sizeof(node)*tot);
	cudaMemcpy(d_nodes, h_nodes, sizeof(node)*tot, cudaMemcpyHostToDevice);

	float t;

	for (int i=0;i<lvl-1;i++) //creation of tree level by level. Each thread is assigned a node in current level.
	{
		block = 1024;
		grid=ceil((1.0*curr)/block);

		grid = minn(grid, 20);

		cudaEventRecord(start);
		construct<<<grid, block>>>(dbody, dmass, d_nodes, i, tot);
		cudaEventRecord(stop);
		cudaEventSynchronize(stop);

		cudaEventElapsedTime(&t, start, stop);

		milliseconds+=t;

		curr*=4;
	}

	cudaMemcpy(h_nodes, d_nodes, sizeof(node)*tot, cudaMemcpyDeviceToHost);

	float theta;

	printf("theta : ");
	scanf("%f", &theta);

	grid=minn(20, ceil((1.0*n)/block));

	printf("%d\n", grid);

	cudaEventRecord(start);
	calculate<<<grid, block>>>(dbody, dmass, d_nodes, dforce, n, theta);  //Each thread is assigned a body
	cudaEventRecord(stop);
	cudaEventSynchronize(stop);

	cudaEventElapsedTime(&t, start, stop);

	milliseconds+=t;

	cudaMemcpy(force, dforce, s, cudaMemcpyDeviceToHost);
	cudaMemcpy(body, dbody, s, cudaMemcpyDeviceToHost);
	cudaMemcpy(mass, dmass, sz, cudaMemcpyDeviceToHost);

	x=0, y=0;

	for(int i=0;i<n;i++)
	{
		printf("force %d : x %f y %f m %f : %.15f %.15f\n", i, body[i].x, body[i].y, mass[i], force[i].x, force[i].y);
		x+=force[i].x, y+=force[i].y;
	}

	printf("gpu time : %f\n", milliseconds);

	printf("x %f y %f\n", x, y);
}


	.file	"tmpxft_002d673b_00000000-6_main1.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3641:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3641:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z7gravity4vectS_ff
	.type	_Z7gravity4vectS_ff, @function
_Z7gravity4vectS_ff:
.LFB3635:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE3635:
	.size	_Z7gravity4vectS_ff, .-_Z7gravity4vectS_ff
	.globl	_Z4maxxff
	.type	_Z4maxxff, @function
_Z4maxxff:
.LFB3636:
	.cfi_startproc
	endbr64
	maxss	%xmm0, %xmm1
	movaps	%xmm1, %xmm0
	ret
	.cfi_endproc
.LFE3636:
	.size	_Z4maxxff, .-_Z4maxxff
	.globl	_Z4minnff
	.type	_Z4minnff, @function
_Z4minnff:
.LFB3637:
	.cfi_startproc
	endbr64
	minss	%xmm1, %xmm0
	ret
	.cfi_endproc
.LFE3637:
	.size	_Z4minnff, .-_Z4minnff
	.globl	_Z41__device_stub__Z10findMinMaxP4vectS0_S0_iP4vectS0_S0_i
	.type	_Z41__device_stub__Z10findMinMaxP4vectS0_S0_iP4vectS0_S0_i, @function
_Z41__device_stub__Z10findMinMaxP4vectS0_S0_iP4vectS0_S0_i:
.LFB3663:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 4(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L12
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z10findMinMaxP4vectS0_S0_i(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L12:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L14
	call	__stack_chk_fail@PLT
.L14:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3663:
	.size	_Z41__device_stub__Z10findMinMaxP4vectS0_S0_iP4vectS0_S0_i, .-_Z41__device_stub__Z10findMinMaxP4vectS0_S0_iP4vectS0_S0_i
	.globl	_Z10findMinMaxP4vectS0_S0_i
	.type	_Z10findMinMaxP4vectS0_S0_i, @function
_Z10findMinMaxP4vectS0_S0_i:
.LFB3664:
	.cfi_startproc
	endbr64
	jmp	_Z41__device_stub__Z10findMinMaxP4vectS0_S0_iP4vectS0_S0_i
	.cfi_endproc
.LFE3664:
	.size	_Z10findMinMaxP4vectS0_S0_i, .-_Z10findMinMaxP4vectS0_S0_i
	.globl	_Z45__device_stub__Z11findMMinMaxP4vectS0_S0_S0_iP4vectS0_S0_S0_i
	.type	_Z45__device_stub__Z11findMMinMaxP4vectS0_S0_S0_iP4vectS0_S0_S0_i, @function
_Z45__device_stub__Z11findMMinMaxP4vectS0_S0_S0_iP4vectS0_S0_S0_i:
.LFB3665:
	.cfi_startproc
	endbr64
	subq	$168, %rsp
	.cfi_def_cfa_offset 176
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	48(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	56(%rsp), %rcx
	movl	%r8d, 12(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 152(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 112(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 144(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L18
	pushq	56(%rsp)
	.cfi_def_cfa_offset 184
	leaq	_Z11findMMinMaxP4vectS0_S0_S0_i(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 192
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 184
	popq	%rdx
	.cfi_def_cfa_offset 176
.L18:
	movq	152(%rsp), %rax
	subq	%fs:40, %rax
	je	.L20
	call	__stack_chk_fail@PLT
.L20:
	addq	$168, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3665:
	.size	_Z45__device_stub__Z11findMMinMaxP4vectS0_S0_S0_iP4vectS0_S0_S0_i, .-_Z45__device_stub__Z11findMMinMaxP4vectS0_S0_S0_iP4vectS0_S0_S0_i
	.globl	_Z11findMMinMaxP4vectS0_S0_S0_i
	.type	_Z11findMMinMaxP4vectS0_S0_S0_i, @function
_Z11findMMinMaxP4vectS0_S0_S0_i:
.LFB3666:
	.cfi_startproc
	endbr64
	jmp	_Z45__device_stub__Z11findMMinMaxP4vectS0_S0_S0_iP4vectS0_S0_S0_i
	.cfi_endproc
.LFE3666:
	.size	_Z11findMMinMaxP4vectS0_S0_S0_i, .-_Z11findMMinMaxP4vectS0_S0_S0_i
	.globl	_Z42__device_stub__Z9constructP4vectPfP4nodeiiP4vectPfP4nodeii
	.type	_Z42__device_stub__Z9constructP4vectPfP4nodeiiP4vectPfP4nodeii, @function
_Z42__device_stub__Z9constructP4vectPfP4nodeiiP4vectPfP4nodeii:
.LFB3667:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	32(%rsp), %rdx
	movl	%ecx, 4(%rsp)
	leaq	40(%rsp), %rcx
	movl	%r8d, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L23
	pushq	40(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z9constructP4vectPfP4nodeii(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 176
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L23:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L25
	call	__stack_chk_fail@PLT
.L25:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3667:
	.size	_Z42__device_stub__Z9constructP4vectPfP4nodeiiP4vectPfP4nodeii, .-_Z42__device_stub__Z9constructP4vectPfP4nodeiiP4vectPfP4nodeii
	.globl	_Z9constructP4vectPfP4nodeii
	.type	_Z9constructP4vectPfP4nodeii, @function
_Z9constructP4vectPfP4nodeii:
.LFB3668:
	.cfi_startproc
	endbr64
	jmp	_Z42__device_stub__Z9constructP4vectPfP4nodeiiP4vectPfP4nodeii
	.cfi_endproc
.LFE3668:
	.size	_Z9constructP4vectPfP4nodeii, .-_Z9constructP4vectPfP4nodeii
	.globl	_Z45__device_stub__Z9calculateP4vectPfP4nodeS0_ifP4vectPfP4nodeS0_if
	.type	_Z45__device_stub__Z9calculateP4vectPfP4nodeS0_ifP4vectPfP4nodeS0_if, @function
_Z45__device_stub__Z9calculateP4vectPfP4nodeS0_ifP4vectPfP4nodeS0_if:
.LFB3669:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	56(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	64(%rsp), %rcx
	movl	%r8d, 12(%rsp)
	movss	%xmm0, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L28
	pushq	64(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z9calculateP4vectPfP4nodeS0_if(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 208
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L28:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L30
	call	__stack_chk_fail@PLT
.L30:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3669:
	.size	_Z45__device_stub__Z9calculateP4vectPfP4nodeS0_ifP4vectPfP4nodeS0_if, .-_Z45__device_stub__Z9calculateP4vectPfP4nodeS0_ifP4vectPfP4nodeS0_if
	.globl	_Z9calculateP4vectPfP4nodeS0_if
	.type	_Z9calculateP4vectPfP4nodeS0_if, @function
_Z9calculateP4vectPfP4nodeS0_if:
.LFB3670:
	.cfi_startproc
	endbr64
	jmp	_Z45__device_stub__Z9calculateP4vectPfP4nodeS0_ifP4vectPfP4nodeS0_if
	.cfi_endproc
.LFE3670:
	.size	_Z9calculateP4vectPfP4nodeS0_if, .-_Z9calculateP4vectPfP4nodeS0_if
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC2:
	.string	"n : "
.LC3:
	.string	"%d"
.LC5:
	.string	"theta : "
.LC6:
	.string	"%f"
.LC7:
	.string	"%d\n"
.LC8:
	.string	"force %d : x %f y %f m %f : %.15f %.15f\n"
.LC9:
	.string	"gpu time : %f\n"
.LC10:
	.string	"x %f y %f\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB3638:
	.cfi_startproc
	endbr64
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	leaq	.LC2(%rip), %rsi
	movl	$2, %edi
	movq	%rsp, %rbp
	.cfi_def_cfa_register 6
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$168, %rsp
	.cfi_offset 15, -24
	.cfi_offset 14, -32
	.cfi_offset 13, -40
	.cfi_offset 12, -48
	.cfi_offset 3, -56
	movq	%fs:40, %rax
	movq	%rax, -56(%rbp)
	xorl	%eax, %eax
	call	__printf_chk@PLT
	leaq	-176(%rbp), %rsi
	leaq	.LC3(%rip), %rdi
	xorl	%eax, %eax
	call	__isoc23_scanf@PLT
	movslq	-176(%rbp), %rcx
	movq	%rsp, %rsi
	leaq	15(,%rcx,8), %rdx
	movq	%rdx, %rax
	andq	$-4096, %rdx
	andq	$-16, %rax
	subq	%rdx, %rsi
.L34:
	cmpq	%rsi, %rsp
	je	.L35
	subq	$4096, %rsp
	orq	$0, 4088(%rsp)
	jmp	.L34
.L35:
	andl	$4095, %eax
	subq	%rax, %rsp
	testq	%rax, %rax
	je	.L36
	orq	$0, -8(%rsp,%rax)
.L36:
	leaq	15(,%rcx,4), %rdx
	movq	%rsp, %rcx
	movq	%rsp, %rbx
	movq	%rdx, %rax
	andq	$-4096, %rdx
	andq	$-16, %rax
	subq	%rdx, %rcx
.L37:
	cmpq	%rcx, %rsp
	je	.L38
	subq	$4096, %rsp
	orq	$0, 4088(%rsp)
	jmp	.L37
.L38:
	andl	$4095, %eax
	subq	%rax, %rsp
	testq	%rax, %rax
	je	.L39
	orq	$0, -8(%rsp,%rax)
.L39:
	movq	%rsp, -192(%rbp)
	xorps	%xmm0, %xmm0
	xorl	%r12d, %r12d
	movl	$1000000, %r15d
	movaps	%xmm0, %xmm1
	movss	%xmm0, -208(%rbp)
.L40:
	movl	-176(%rbp), %r13d
	cmpl	%r12d, %r13d
	jle	.L77
	movss	%xmm0, -200(%rbp)
	movss	%xmm1, -184(%rbp)
	call	rand@PLT
	cltd
	idivl	%r15d
	cvtsi2ssl	%edx, %xmm2
	movss	%xmm2, (%rbx,%r12,8)
	call	rand@PLT
	cltd
	idivl	%r15d
	cvtsi2ssl	%edx, %xmm2
	movss	%xmm2, 4(%rbx,%r12,8)
	call	rand@PLT
	movss	-184(%rbp), %xmm1
	movss	-200(%rbp), %xmm0
	cltd
	addss	(%rbx,%r12,8), %xmm1
	addss	4(%rbx,%r12,8), %xmm0
	idivl	%r15d
	movq	-192(%rbp), %rax
	cvtsi2ssl	%edx, %xmm2
	movss	%xmm2, (%rax,%r12,4)
	addss	-208(%rbp), %xmm2
	incq	%r12
	movss	%xmm2, -208(%rbp)
	jmp	.L40
.L77:
	cvtsi2ssl	%r13d, %xmm2
	movslq	%r13d, %rax
	movq	%rsp, %rcx
	leaq	15(,%rax,8), %rdx
	movq	%rdx, %rax
	andq	$-4096, %rdx
	andq	$-16, %rax
	subq	%rdx, %rcx
	divss	%xmm2, %xmm1
	divss	%xmm2, %xmm0
	movd	%xmm1, %r15d
	movd	%xmm0, %r14d
.L42:
	cmpq	%rcx, %rsp
	je	.L43
	subq	$4096, %rsp
	orq	$0, 4088(%rsp)
	jmp	.L42
.L43:
	andl	$4095, %eax
	subq	%rax, %rsp
	testq	%rax, %rax
	je	.L44
	orq	$0, -8(%rsp,%rax)
.L44:
	movq	%rsp, %r12
	xorl	%eax, %eax
.L45:
	cmpl	%eax, %r13d
	jle	.L78
	movl	$0x00000000, 4(%r12,%rax,8)
	movl	$0x00000000, (%r12,%rax,8)
	incq	%rax
	jmp	.L45
.L78:
	leal	0(,%r13,8), %eax
	leaq	-136(%rbp), %rdi
	sall	$2, %r13d
	cltq
	movq	%rax, %rsi
	movq	%rax, -184(%rbp)
	call	cudaMalloc@PLT
	movslq	%r13d, %rax
	leaq	-128(%rbp), %rdi
	movq	%rax, %rsi
	movq	%rax, -200(%rbp)
	call	cudaMalloc@PLT
	movq	-184(%rbp), %rsi
	leaq	-144(%rbp), %rdi
	call	cudaMalloc@PLT
	movq	-184(%rbp), %rdx
	movq	-144(%rbp), %rdi
	xorl	%esi, %esi
	call	cudaMemset@PLT
	movq	-184(%rbp), %rsi
	leaq	-160(%rbp), %rdi
	call	cudaMalloc@PLT
	movq	-184(%rbp), %rsi
	leaq	-152(%rbp), %rdi
	call	cudaMalloc@PLT
	movq	-184(%rbp), %rdx
	movl	$1, %ecx
	movq	%rbx, %rsi
	movq	-136(%rbp), %rdi
	call	cudaMemcpy@PLT
	movq	-200(%rbp), %rdx
	movq	-128(%rbp), %rdi
	movl	$1, %ecx
	movq	-192(%rbp), %rsi
	call	cudaMemcpy@PLT
	leaq	-120(%rbp), %rdi
	call	cudaEventCreate@PLT
	leaq	-112(%rbp), %rdi
	call	cudaEventCreate@PLT
	movq	-120(%rbp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movl	$134217729, %edi
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	salq	$5, %rdi
	movl	$1, %ecx
	movl	$1, %esi
	movl	$1, -60(%rbp)
	movq	%rdi, %rdx
	movq	%rdi, -68(%rbp)
	movq	%rdi, -80(%rbp)
	movl	$1, -72(%rbp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L47
	movl	-176(%rbp), %ecx
	movq	-152(%rbp), %rdx
	movq	-160(%rbp), %rsi
	movq	-136(%rbp), %rdi
	call	_Z41__device_stub__Z10findMinMaxP4vectS0_S0_iP4vectS0_S0_i
.L47:
	movl	$134217729, %edx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$1, %ecx
	salq	$5, %rdx
	movl	$1, %esi
	movabsq	$4294967297, %rdi
	movl	$1, -60(%rbp)
	movq	%rdx, -68(%rbp)
	movq	%rdi, -80(%rbp)
	movl	$1, -72(%rbp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L48
	movq	-152(%rbp), %rsi
	movq	-160(%rbp), %rdi
	movl	$32, %r8d
	movq	%rsi, %rcx
	movq	%rdi, %rdx
	call	_Z45__device_stub__Z11findMMinMaxP4vectS0_S0_S0_iP4vectS0_S0_S0_i
.L48:
	movq	-112(%rbp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movq	-112(%rbp), %rdi
	call	cudaEventSynchronize@PLT
	movq	-112(%rbp), %rdx
	movq	-120(%rbp), %rsi
	leaq	-172(%rbp), %rdi
	movl	$0x00000000, -172(%rbp)
	call	cudaEventElapsedTime@PLT
	movq	-160(%rbp), %rsi
	leaq	-96(%rbp), %rdi
	movl	$2, %ecx
	movl	$8, %edx
	call	cudaMemcpy@PLT
	movq	-152(%rbp), %rsi
	leaq	-88(%rbp), %rdi
	movl	$2, %ecx
	movl	$8, %edx
	call	cudaMemcpy@PLT
	leaq	-4542464(%rsp), %rax
.L49:
	cmpq	%rax, %rsp
	je	.L50
	subq	$4096, %rsp
	orq	$0, 4088(%rsp)
	jmp	.L49
.L50:
	subq	$1360, %rsp
	orq	$0, 1352(%rsp)
	leaq	3(%rsp), %r13
	movq	%r13, %rax
	andq	$-4, %r13
	shrq	$2, %rax
	leaq	12(%r13), %rdx
	leaq	4543824(%r13), %rcx
.L52:
	movl	$-1, (%rdx)
	addq	$52, %rdx
	movl	$-1, -48(%rdx)
	movl	$-1, -44(%rdx)
	movl	$-1, -40(%rdx)
	cmpq	%rcx, %rdx
	jne	.L52
	movl	-176(%rbp), %ecx
	xorl	%edx, %edx
	movss	-208(%rbp), %xmm3
	movl	%r15d, 0(,%rax,4)
	movl	%edx, 28(,%rax,4)
	leaq	-104(%rbp), %rdi
	movl	$4543812, %esi
	movl	$1, %r15d
	leal	-1(%rcx), %edx
	movl	%r14d, 4(,%rax,4)
	xorl	%r14d, %r14d
	movl	%edx, 32(,%rax,4)
	movq	-96(%rbp), %rdx
	movss	%xmm3, 8(,%rax,4)
	movq	%rdx, 36(,%rax,4)
	movq	-88(%rbp), %rdx
	movq	%rdx, 44(,%rax,4)
	call	cudaMalloc@PLT
	movq	-104(%rbp), %rdi
	movl	$1, %ecx
	movq	%r13, %rsi
	movl	$4543812, %edx
	call	cudaMemcpy@PLT
.L56:
	cvtsi2sdl	%r15d, %xmm0
	mulsd	.LC4(%rip), %xmm0
	call	ceil@PLT
	movq	-120(%rbp), %rdi
	xorl	%esi, %esi
	cvttsd2sil	%xmm0, %eax
	cvtsi2ssl	%eax, %xmm0
	minss	.LC1(%rip), %xmm0
	movss	%xmm0, -208(%rbp)
	call	cudaEventRecord@PLT
	movl	$4194305, %edx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	salq	$10, %rdx
	movss	-208(%rbp), %xmm0
	movl	$1, %ecx
	movl	$1, -60(%rbp)
	movq	%rdx, -68(%rbp)
	cvttss2sil	%xmm0, %eax
	movl	%eax, -80(%rbp)
	movabsq	$4294967297, %rax
	movq	%rax, -76(%rbp)
	movq	-80(%rbp), %rdi
	movl	-72(%rbp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L55
	movq	-104(%rbp), %rdx
	movq	-128(%rbp), %rsi
	movl	$87381, %r8d
	movl	%r14d, %ecx
	movq	-136(%rbp), %rdi
	call	_Z42__device_stub__Z9constructP4vectPfP4nodeiiP4vectPfP4nodeii
.L55:
	movq	-112(%rbp), %rdi
	xorl	%esi, %esi
	incl	%r14d
	sall	$2, %r15d
	call	cudaEventRecord@PLT
	movq	-112(%rbp), %rdi
	call	cudaEventSynchronize@PLT
	leaq	-168(%rbp), %rax
	movq	-112(%rbp), %rdx
	movq	-120(%rbp), %rsi
	movq	%rax, %rdi
	movq	%rax, -208(%rbp)
	call	cudaEventElapsedTime@PLT
	movss	-172(%rbp), %xmm0
	addss	-168(%rbp), %xmm0
	movss	%xmm0, -172(%rbp)
	cmpl	$8, %r14d
	jne	.L56
	movq	-104(%rbp), %rsi
	movl	$2, %ecx
	movl	$4543812, %edx
	movq	%r13, %rdi
	call	cudaMemcpy@PLT
	leaq	.LC5(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	leaq	-164(%rbp), %rsi
	leaq	.LC6(%rip), %rdi
	xorl	%eax, %eax
	call	__isoc23_scanf@PLT
	cvtsi2sdl	-176(%rbp), %xmm0
	mulsd	.LC4(%rip), %xmm0
	call	ceil@PLT
	cvtsd2ss	%xmm0, %xmm0
	comiss	.LC1(%rip), %xmm0
	jbe	.L57
	movss	.LC1(%rip), %xmm0
.L57:
	cvttss2sil	%xmm0, %r13d
	leaq	.LC7(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	movl	%r13d, %edx
	call	__printf_chk@PLT
	movq	-120(%rbp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movl	%r13d, -80(%rbp)
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movabsq	$4294967297, %rax
	movl	$4194305, %edx
	movl	$1, %ecx
	movl	$1, -60(%rbp)
	movq	%rax, -76(%rbp)
	movq	-80(%rbp), %rdi
	salq	$10, %rdx
	movl	-72(%rbp), %esi
	movq	%rdx, -68(%rbp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L59
	movss	-164(%rbp), %xmm0
	movl	-176(%rbp), %r8d
	movq	-144(%rbp), %rcx
	movq	-104(%rbp), %rdx
	movq	-128(%rbp), %rsi
	movq	-136(%rbp), %rdi
	call	_Z45__device_stub__Z9calculateP4vectPfP4nodeS0_ifP4vectPfP4nodeS0_if
.L59:
	movq	-112(%rbp), %rdi
	xorl	%esi, %esi
	xorl	%r13d, %r13d
	leaq	.LC8(%rip), %r14
	call	cudaEventRecord@PLT
	movq	-112(%rbp), %rdi
	call	cudaEventSynchronize@PLT
	movq	-112(%rbp), %rdx
	movq	-120(%rbp), %rsi
	movq	-208(%rbp), %rdi
	call	cudaEventElapsedTime@PLT
	movss	-172(%rbp), %xmm0
	movl	$2, %ecx
	movq	%r12, %rdi
	addss	-168(%rbp), %xmm0
	movq	-184(%rbp), %rdx
	movq	-144(%rbp), %rsi
	movss	%xmm0, -172(%rbp)
	call	cudaMemcpy@PLT
	movq	-184(%rbp), %rdx
	movl	$2, %ecx
	movq	%rbx, %rdi
	movq	-136(%rbp), %rsi
	call	cudaMemcpy@PLT
	movq	-200(%rbp), %rdx
	movq	-128(%rbp), %rsi
	movl	$2, %ecx
	movq	-192(%rbp), %rdi
	call	cudaMemcpy@PLT
	xorps	%xmm5, %xmm5
	movd	%xmm5, %r15d
.L60:
	cmpl	%r13d, -176(%rbp)
	movl	%r13d, %edx
	movss	%xmm5, -184(%rbp)
	jle	.L79
	movq	-192(%rbp), %rax
	movq	%r14, %rsi
	movl	$2, %edi
	cvtss2sd	(%rbx,%r13,8), %xmm0
	cvtss2sd	4(%r12,%r13,8), %xmm4
	cvtss2sd	(%r12,%r13,8), %xmm3
	cvtss2sd	4(%rbx,%r13,8), %xmm1
	cvtss2sd	(%rax,%r13,4), %xmm2
	movb	$5, %al
	call	__printf_chk@PLT
	movd	%r15d, %xmm6
	addss	(%r12,%r13,8), %xmm6
	movss	-184(%rbp), %xmm5
	addss	4(%r12,%r13,8), %xmm5
	incq	%r13
	movd	%xmm6, %r15d
	jmp	.L60
.L79:
	leaq	.LC9(%rip), %rsi
	movl	$2, %edi
	movb	$1, %al
	cvtss2sd	-172(%rbp), %xmm0
	call	__printf_chk@PLT
	movss	-184(%rbp), %xmm5
	movd	%r15d, %xmm4
	movb	$2, %al
	leaq	.LC10(%rip), %rsi
	movl	$2, %edi
	cvtss2sd	%xmm4, %xmm0
	cvtss2sd	%xmm5, %xmm1
	call	__printf_chk@PLT
	movq	-56(%rbp), %rax
	subq	%fs:40, %rax
	je	.L62
	call	__stack_chk_fail@PLT
.L62:
	leaq	-40(%rbp), %rsp
	xorl	%eax, %eax
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE3638:
	.size	main, .-main
	.section	.rodata.str1.1
.LC11:
	.string	"_Z9calculateP4vectPfP4nodeS0_if"
.LC12:
	.string	"_Z9constructP4vectPfP4nodeii"
.LC13:
	.string	"_Z11findMMinMaxP4vectS0_S0_S0_i"
.LC14:
	.string	"_Z10findMinMaxP4vectS0_S0_i"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3672:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC11(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z9calculateP4vectPfP4nodeS0_if(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC12(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z9constructP4vectPfP4nodeii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC13(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z11findMMinMaxP4vectS0_S0_S0_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC14(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z10findMinMaxP4vectS0_S0_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3672:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst4,"aM",@progbits,4
	.align 4
.LC1:
	.long	1101004800
	.section	.rodata.cst8,"aM",@progbits,8
	.align 8
.LC4:
	.long	0
	.long	1062207488
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#include <math.h>
#include <limits.h>
#include <float.h>
#include <iostream>
#include <sys/time.h>

#define G 6.67408E-11 //Gravitational constant 

#define lvl 9		//depth of quad tree till which we'll divide plane

using namespace std;

struct vect		//Structure for 2D coordinate
{
	float x; //X coordinate
	float y; //Y coordinate
};

struct node		//Structure for each node of the quad tree

{
	vect body; //centre of mass of bodies in current node
	float mass; //total mass of bodies in current node
	int child[4]; //children indices in nodes array
	int l,r; //index limit in body array of bodies in current node
	vect min, max; //min and max X and Y coordinates of bodies belonging to current node
};

//Function to calculate Gravitational force between two bodies
__device__ vect gravity (vect a, vect b, float m1, float m2)
{
	float res=G*m1*m2;

	float r=(a.y-b.y)*(a.y-b.y)+(a.x-b.x)*(a.x-b.x);

	if (r>0)	res/=r;

	vect vec;

	vec.y=a.y-b.y;
	vec.x=a.x-b.x;

	r=sqrt(r);

	if (r>0)	vec.y/=r, vec.x/=r;

	vec.y*=res;
	vec.x*=res;

	return vec;
}

//part1 for kernel1 to find min-max among the n bodies 
//Will find min and max of X and Y coordinates for each thread lock
//Uses reduction technique
__global__ void findMinMax(vect * body, vect * min, vect * max, int n)
{
	__shared__ vect min_cache[32];
	__shared__ vect max_cache[32];

	int index=threadIdx.x+blockDim.x*blockIdx.x;

	float xmin=FLT_MAX, ymin=FLT_MAX;
	float xmax=FLT_MIN, ymax=FLT_MIN;

	while (index<n) //takes care if total number greater than total threads in kernel
	{
		xmin=fmin(xmin, body[index].x);
		ymin=fmin(ymin, body[index].y);
		xmax=fmax(xmax, body[index].x);
		ymax=fmax(ymax, body[index].y);

		index+=(blockDim.x*gridDim.x); //incrementing index by total number of threads in kernel, to take care if total number more than total threads in kernel
	}

	int tid=threadIdx.x;

	min_cache[tid].x=xmin;
	min_cache[tid].y=ymin;

	max_cache[tid].x=xmax;
	max_cache[tid].y=ymax;

	int active=blockDim.x>>1;

	do
	{
		__syncthreads();

		if (tid<active) //reduction
		{
			min_cache[tid].x=fmin(min_cache[tid].x, min_cache[tid+active].x);
			min_cache[tid].y=fmin(min_cache[tid].y, min_cache[tid+active].y);

			max_cache[tid].x=fmax(max_cache[tid].x, max_cache[tid+active].x);
			max_cache[tid].y=fmax(max_cache[tid].y, max_cache[tid+active].y);
		}

		active>>=1;
	}while (active>0);

	if (tid==0)	min[blockIdx.x]=min_cache[0], max[blockIdx.x]=max_cache[0];
}

//part2 for kernel1 to find min-max among the n bodies 
//Will find global min and max of X and Y coordinates from local min and max of above kernel

__global__ void findMMinMax(vect * mmin, vect *mmax, vect * min, vect * max, int n)
{
	__shared__ vect min_cache[32];
	__shared__ vect max_cache[32];

	int index=threadIdx.x+blockDim.x*blockIdx.x;

	float xmin=FLT_MAX, ymin=FLT_MAX;
	float xmax=FLT_MIN, ymax=FLT_MIN;

	while (index<n) //takes care if total number greater than total threads in kernel
	{
		xmin=fmin(xmin, min[index].x);
		ymin=fmin(ymin, min[index].y);
		xmax=fmax(xmax, max[index].x);
		ymax=fmax(ymax, max[index].y);

		index+=(blockDim.x*gridDim.x);
	}

	int tid=threadIdx.x;

	min_cache[tid].x=xmin;
	min_cache[tid].y=ymin;

	max_cache[tid].x=xmax;
	max_cache[tid].y=ymax;

	int active=blockDim.x>>1;

	do
	{
		__syncthreads();

		if (tid<active) //reduction
		{
			min_cache[tid].x=fmin(min_cache[tid].x, min_cache[tid+active].x);
			min_cache[tid].y=fmin(min_cache[tid].y, min_cache[tid+active].y);

			max_cache[tid].x=fmax(max_cache[tid].x, max_cache[tid+active].x);
			max_cache[tid].y=fmax(max_cache[tid].y, max_cache[tid+active].y);
		}

		active>>=1;
	}while (active>0);

	if (tid==0)	mmin[blockIdx.x]=min_cache[0], mmax[blockIdx.x]=max_cache[0];
}

//This function will construct particular level of the tree.
//Each node will be divided further into four new nodes and bodies in the array will be swapped so that bodies belonging to same node remain together in the array

//This will work as kernel 2
__global__ void construct(vect *body, float *mass, node *nodes, int level, int tot)
{
	int index=blockDim.x*blockIdx.x+threadIdx.x;
	
	int tid=index*4;

	int total = 1<<(2*level); //total nodes in current level

	int offset=((1<<(2*level))-1)/3; //total nodes in tree upto previous level
	int off=offset+total; //total nodes in tree upto current level

	while (index<total) //'while' loop will take care if total number more than total threads in kernel
	{
		index+=offset; //actual index in nodes array

		node nd=nodes[index];

		if (nodes[index].l<=nodes[index].r)
		{
			float xl=nd.min.x, xr=nd.max.x;
			float yl=nd.min.y, yr=nd.max.y;

			float xmid=xl+(xr-xl)/2;
			float ymid=yl+(yr-yl)/2;

			float l=nd.l, r=nd.r;

			node child[4];

			for (int i=0;i<4;i++)	
			{
				child[i].min.x=child[i].min.y=FLT_MAX, child[i].max.x=child[i].max.y=FLT_MIN;
					
				for (int j=0;j<4;j++)	child[i].child[j]=-1;
			}

			int i=l-1;

			float m=0, x=0, y=0, mm=0, xx=0, yy=0;
			
			for (int j=l;j<=r;j++) //swapping of bodies belonging to current node based on x-coordinates creating two children

			{
				if (body[j].x<=xmid)
				{
					i++;
					
					vect temp=body[i];
					body[i]=body[j];
					body[j]=temp;

					float t=mass[i];
					mass[i]=mass[j];
					mass[j]=t;
				}

			}

			child[2].l=l, child[2].r=i;
			child[3].l=i+1, child[3].r=r;

			for (int k=2;k<=3;k++)
			{
				m=mm=x=xx=y=yy=0;

				l=child[k].l, r=child[k].r;

				i=l-1;

				int cnt=0;

				for (int j=l;j<=r;j++) //swapping of bodies in two children created previously based on y-coordinates, each creating two new children

				{
					x+=body[j].x;
					y+=body[j].y;
					m+=mass[j];

					if (body[j].y<=ymid)
					{
						xx+=body[j].x, yy+=body[j].y, mm+=mass[j];
						cnt++;
						i++;
						
						vect temp=body[i];
						body[i]=body[j];
						body[j]=temp;

						float t=mass[i];
						mass[i]=mass[j];
						mass[j]=t;
					}
				}
				
				if(cnt>0)	child[k].mass=mm, child[k].body.x=xx/cnt, child[k].body.y=yy/cnt;

				child[k].l=l, child[k].r=i;

				mm=m-mm, xx=x-xx, yy=y-yy, cnt=r-l+1-cnt;
				
				if(cnt>0)	child[k-2].mass=mm, child[k-2].body.x=xx/cnt, child[k-2].body.y=yy/cnt;

				child[k-2].l=i+1, child[k-2].r=r;
			}			

			for (int i=0;i<4;i++)	
			{
				if (i%2)	child[i].min.x=xmid, child[i].max.x=xr;
				else	child[i].min.x=xl, child[i].max.x=xmid;
				
				if (i<2)	child[i].min.y=ymid, child[i].max.y=yr;
				else	child[i].min.y=yl, child[i].max.y=ymid;

				if (off+tid+i<tot)	nodes[off+tid+i]=child[i];
				nd.child[i]=off+tid+i;
			}	
		}
		else
		{
			for (int i=0;i<4;i++)
			{
				if (off+tid+i<tot)
				{	
					nodes[off+tid+i].l=0;
					nodes[off+tid+i].r=-1;
				}

				nd.child[i]=off+tid+i;
			}
		}

		nodes[index]=nd;

		index-=offset;
		
		index+=(blockDim.x*gridDim.x); //will take care if total number more than total threads by incrementing index by total threads.
	}
}

//This is kernel 3
//This function calculates force on bodies

__global__ void calculate(vect *body, float *mass, node *nodes, vect *force, int n, float theta)
{
	int index=blockDim.x*blockIdx.x+threadIdx.x;

	int l=((1<<(2*(lvl-1)))-1)/3; //total nodes in tree upto max depth


	while (index<n) //'while' loop takes care if total number more than total threads in kernel
	{
		int st[4*(lvl)]; //using array as stack
		int curr=0; //variable showing current top index

		st[curr]=0;

		vect bd=body[index];

		while (curr>=0) //for each body do DFS until reached leaf

		{
			int t=st[curr];
			curr--;

			node nd=nodes[t];

			float s=fmax(nd.max.x-nd.min.x, nd.max.y-nd.min.y);

			float x=bd.x-nd.body.x, y=bd.y-nd.body.y;

			float dist=sqrt(x*x+y*y);

			float val=FLT_MAX;

			if (dist>0)	val=s/dist;

			if (val<theta)	//Barnes-Hutt approximation
			{
				vect frc=gravity(nd.body, bd, nd.mass, mass[index]);

				force[index].x+=frc.x;
				force[index].y+=frc.y;
			}
			else
			{
				if (t>=l) //if reached leaf
				{
					vect frc=gravity(nd.body, bd, nd.mass, mass[index]);

					force[index].x+=frc.x;
					force[index].y+=frc.y;

					continue;
				}

				for (int i=0;i<4;i++)
				{
					int temp=nd.child[i];

					if (temp==-1 || nodes[temp].l>nodes[temp].r)	continue;
					
					st[++curr]=temp;
				}
			}
		}

		index+=(blockDim.x*gridDim.x); //will take care if total number more than total threads by incrementing index by total number of threads in kernel
	}
}

float maxx(float a, float b)
{
	return (a<b?b:a);
}

float minn(float a, float b)
{
	return (a<b?a:b);
}

int main()
{
	int n;
	printf("n : ");
	scanf("%d", &n);

	vect body[n];

	float mass[n];

	float m=0, x=0, y=0;

	for (int i=0;i<n;i++)	
	{
		body[i].x=rand()%1000000;
		body[i].y=rand()%1000000;
		mass[i]=rand()%1000000;

		m+=mass[i], x+=body[i].x, y+=body[i].y;
	}	

	x/=n, y/=n; //centre of mass of the whole system

	vect force[n];
	vect *min;
	vect *max;

	for (int i=0;i<n;i++)	force[i].x=force[i].y=0;

	vect *dforce;
	vect *dbody;
	float *dmass;

	int s=sizeof(vect)*n;
	int sz=sizeof(float)*n;

	hipMalloc(&dbody, s);
	hipMalloc(&dmass, sz);

	hipMalloc(&dforce, s);
	hipMemset(dforce, 0, s);

	hipMalloc(&min, s);
	hipMalloc(&max, s);

	hipMemcpy(dbody, body, s, hipMemcpyHostToDevice);
	hipMemcpy(dmass, mass, sz, hipMemcpyHostToDevice);

	int val=32;

	int block = val;

	int grid = val;

	hipEvent_t start, stop;
	
	hipEventCreate(&start);
	hipEventCreate(&stop);
	
	hipEventRecord(start);

	//This is kernel 1 which devided into 2 parts
	//bassically it find minimum and maximum from
	//the n bodies
	findMinMax<<<grid, block>>>(dbody, min, max, n);
	
	findMMinMax<<<1, block>>>(min, max, min, max, val);

	hipEventRecord(stop);
	hipEventSynchronize(stop);

	//milliseconds find the total kernal time in GPU
	float milliseconds = 0;
	hipEventElapsedTime(&milliseconds, start, stop);

	vect gmin;
	vect gmax;

	hipMemcpy(&gmin, min, sizeof(vect), hipMemcpyDeviceToHost);
	hipMemcpy(&gmax, max, sizeof(vect), hipMemcpyDeviceToHost);

	int curr=1;

	int tot=1<<(2*lvl);
	tot=(tot-1)/3;

	node h_nodes[tot];

	for (int i=0;i<tot;i++)
	{
		for (int j=0;j<4;j++)	h_nodes[i].child[j]=-1;
	}

	vect temp;
	temp.x=x, temp.y=y;

	h_nodes[0].body=temp, h_nodes[0].mass=m, h_nodes[0].l=0, h_nodes[0].r=n-1, h_nodes[0].min=gmin, h_nodes[0].max=gmax;

	node *d_nodes;
	hipMalloc(&d_nodes, sizeof(node)*tot);
	hipMemcpy(d_nodes, h_nodes, sizeof(node)*tot, hipMemcpyHostToDevice);

	float t;

	for (int i=0;i<lvl-1;i++) //creation of tree level by level. Each thread is assigned a node in current level.
	{
		block = 1024;
		grid=ceil((1.0*curr)/block);

		grid = minn(grid, 20);

		hipEventRecord(start);
		construct<<<grid, block>>>(dbody, dmass, d_nodes, i, tot);
		hipEventRecord(stop);
		hipEventSynchronize(stop);

		hipEventElapsedTime(&t, start, stop);

		milliseconds+=t;

		curr*=4;
	}

	hipMemcpy(h_nodes, d_nodes, sizeof(node)*tot, hipMemcpyDeviceToHost);

	float theta;

	printf("theta : ");
	scanf("%f", &theta);

	grid=minn(20, ceil((1.0*n)/block));

	printf("%d\n", grid);

	hipEventRecord(start);
	calculate<<<grid, block>>>(dbody, dmass, d_nodes, dforce, n, theta);  //Each thread is assigned a body
	hipEventRecord(stop);
	hipEventSynchronize(stop);

	hipEventElapsedTime(&t, start, stop);

	milliseconds+=t;

	hipMemcpy(force, dforce, s, hipMemcpyDeviceToHost);
	hipMemcpy(body, dbody, s, hipMemcpyDeviceToHost);
	hipMemcpy(mass, dmass, sz, hipMemcpyDeviceToHost);

	x=0, y=0;

	for(int i=0;i<n;i++)
	{
		printf("force %d : x %f y %f m %f : %.15f %.15f\n", i, body[i].x, body[i].y, mass[i], force[i].x, force[i].y);
		x+=force[i].x, y+=force[i].y;
	}

	printf("gpu time : %f\n", milliseconds);

	printf("x %f y %f\n", x, y);
}


	.text
	.file	"main1.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z25__device_stub__findMinMaxP4vectS0_S0_i # -- Begin function _Z25__device_stub__findMinMaxP4vectS0_S0_i
	.type	_Z25__device_stub__findMinMaxP4vectS0_S0_i,@function
_Z25__device_stub__findMinMaxP4vectS0_S0_i: # @_Z25__device_stub__findMinMaxP4vectS0_S0_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	4(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z10findMinMaxP4vectS0_S0_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z25__device_stub__findMinMaxP4vectS0_S0_i, .Lfunc_end0-_Z25__device_stub__findMinMaxP4vectS0_S0_i
	.cfi_endproc
                                        # -- End function
	.globl	_Z26__device_stub__findMMinMaxP4vectS0_S0_S0_i # -- Begin function _Z26__device_stub__findMMinMaxP4vectS0_S0_S0_i
	.type	_Z26__device_stub__findMMinMaxP4vectS0_S0_S0_i,@function
_Z26__device_stub__findMMinMaxP4vectS0_S0_S0_i: # @_Z26__device_stub__findMMinMaxP4vectS0_S0_S0_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	12(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z11findMMinMaxP4vectS0_S0_S0_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z26__device_stub__findMMinMaxP4vectS0_S0_S0_i, .Lfunc_end1-_Z26__device_stub__findMMinMaxP4vectS0_S0_S0_i
	.cfi_endproc
                                        # -- End function
	.globl	_Z24__device_stub__constructP4vectPfP4nodeii # -- Begin function _Z24__device_stub__constructP4vectPfP4nodeii
	.type	_Z24__device_stub__constructP4vectPfP4nodeii,@function
_Z24__device_stub__constructP4vectPfP4nodeii: # @_Z24__device_stub__constructP4vectPfP4nodeii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	4(%rsp), %rdx
	movl	%ecx, (%rdx)
	movq	%rsp, %rcx
	movl	%r8d, (%rcx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z9constructP4vectPfP4nodeii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z24__device_stub__constructP4vectPfP4nodeii, .Lfunc_end2-_Z24__device_stub__constructP4vectPfP4nodeii
	.cfi_endproc
                                        # -- End function
	.globl	_Z24__device_stub__calculateP4vectPfP4nodeS0_if # -- Begin function _Z24__device_stub__calculateP4vectPfP4nodeS0_if
	.type	_Z24__device_stub__calculateP4vectPfP4nodeS0_if,@function
_Z24__device_stub__calculateP4vectPfP4nodeS0_if: # @_Z24__device_stub__calculateP4vectPfP4nodeS0_if
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	12(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	8(%rsp), %r8
	movss	%xmm0, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z9calculateP4vectPfP4nodeS0_if, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	_Z24__device_stub__calculateP4vectPfP4nodeS0_if, .Lfunc_end3-_Z24__device_stub__calculateP4vectPfP4nodeS0_if
	.cfi_endproc
                                        # -- End function
	.globl	_Z4maxxff                       # -- Begin function _Z4maxxff
	.type	_Z4maxxff,@function
_Z4maxxff:                              # @_Z4maxxff
	.cfi_startproc
# %bb.0:
	maxss	%xmm0, %xmm1
	movaps	%xmm1, %xmm0
	retq
.Lfunc_end4:
	.size	_Z4maxxff, .Lfunc_end4-_Z4maxxff
	.cfi_endproc
                                        # -- End function
	.globl	_Z4minnff                       # -- Begin function _Z4minnff
	.type	_Z4minnff,@function
_Z4minnff:                              # @_Z4minnff
	.cfi_startproc
# %bb.0:
	minss	%xmm1, %xmm0
	retq
.Lfunc_end5:
	.size	_Z4minnff, .Lfunc_end5-_Z4minnff
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0                          # -- Begin function main
.LCPI6_0:
	.quad	0x3f50000000000000              # double 9.765625E-4
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0
.LCPI6_1:
	.long	0x41a00000                      # float 20
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$184, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	$.L.str, %edi
	xorl	%eax, %eax
	callq	printf
	leaq	-44(%rbp), %rbx
	movl	$.L.str.1, %edi
	movq	%rbx, %rsi
	xorl	%eax, %eax
	callq	__isoc23_scanf
	movq	%rsp, -200(%rbp)                # 8-byte Spill
	movl	(%rbx), %eax
	movq	%rsp, %r15
	leaq	15(,%rax,8), %rax
	andq	$-16, %rax
	subq	%rax, %r15
	movq	%r15, %rsp
	movl	(%rbx), %ebx
	movq	%rsp, %r13
	leaq	15(,%rbx,4), %rax
	andq	$-16, %rax
	subq	%rax, %r13
	movq	%r13, %rsp
	testl	%ebx, %ebx
	jle	.LBB6_5
# %bb.1:                                # %.lr.ph.preheader
	xorps	%xmm1, %xmm1
	xorl	%r14d, %r14d
	xorps	%xmm3, %xmm3
	xorps	%xmm2, %xmm2
.LBB6_2:                                # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	movss	%xmm3, -76(%rbp)                # 4-byte Spill
	movss	%xmm2, -56(%rbp)                # 4-byte Spill
	movss	%xmm1, -64(%rbp)                # 4-byte Spill
	callq	rand
	cltq
	imulq	$1125899907, %rax, %rcx         # imm = 0x431BDE83
	movq	%rcx, %rdx
	shrq	$63, %rdx
	sarq	$50, %rcx
	addl	%edx, %ecx
	imull	$1000000, %ecx, %ecx            # imm = 0xF4240
	subl	%ecx, %eax
	xorps	%xmm0, %xmm0
	cvtsi2ss	%eax, %xmm0
	movss	%xmm0, -128(%rbp)               # 4-byte Spill
	movss	%xmm0, (%r15,%r14,8)
	callq	rand
	cltq
	imulq	$1125899907, %rax, %rcx         # imm = 0x431BDE83
	movq	%rcx, %rdx
	shrq	$63, %rdx
	sarq	$50, %rcx
	addl	%edx, %ecx
	imull	$1000000, %ecx, %ecx            # imm = 0xF4240
	subl	%ecx, %eax
	xorps	%xmm0, %xmm0
	cvtsi2ss	%eax, %xmm0
	movss	%xmm0, -120(%rbp)               # 4-byte Spill
	movss	%xmm0, 4(%r15,%r14,8)
	callq	rand
	movss	-76(%rbp), %xmm3                # 4-byte Reload
                                        # xmm3 = mem[0],zero,zero,zero
	movss	-56(%rbp), %xmm2                # 4-byte Reload
                                        # xmm2 = mem[0],zero,zero,zero
	movss	-64(%rbp), %xmm1                # 4-byte Reload
                                        # xmm1 = mem[0],zero,zero,zero
	cltq
	imulq	$1125899907, %rax, %rcx         # imm = 0x431BDE83
	movq	%rcx, %rdx
	shrq	$63, %rdx
	sarq	$50, %rcx
	addl	%edx, %ecx
	imull	$1000000, %ecx, %ecx            # imm = 0xF4240
	subl	%ecx, %eax
	xorps	%xmm0, %xmm0
	cvtsi2ss	%eax, %xmm0
	movss	%xmm0, (%r13,%r14,4)
	addss	%xmm0, %xmm1
	addss	-128(%rbp), %xmm3               # 4-byte Folded Reload
	addss	-120(%rbp), %xmm2               # 4-byte Folded Reload
	incq	%r14
	movslq	-44(%rbp), %rbx
	cmpq	%rbx, %r14
	jl	.LBB6_2
# %bb.3:                                # %._crit_edge
	movss	%xmm1, -64(%rbp)                # 4-byte Spill
	xorps	%xmm0, %xmm0
	cvtsi2ss	%ebx, %xmm0
	movl	%ebx, %edx
	divss	%xmm0, %xmm3
	movss	%xmm3, -76(%rbp)                # 4-byte Spill
	divss	%xmm0, %xmm2
	movss	%xmm2, -56(%rbp)                # 4-byte Spill
	movq	%rsp, %rdi
	leaq	15(,%rdx,8), %rax
	andq	$-16, %rax
	subq	%rax, %rdi
	movq	%rdi, %rsp
	testl	%ebx, %ebx
	movq	%rdi, -168(%rbp)                # 8-byte Spill
	jle	.LBB6_6
# %bb.4:                                # %.lr.ph138.preheader
	shlq	$3, %rdx
	xorl	%esi, %esi
	callq	memset@PLT
	jmp	.LBB6_6
.LBB6_5:                                # %._crit_edge.thread
	cvtsi2ss	%ebx, %xmm0
	xorps	%xmm1, %xmm1
	movss	%xmm1, -64(%rbp)                # 4-byte Spill
	divss	%xmm0, %xmm1
	movq	%rsp, %rcx
	leaq	15(,%rbx,8), %rax
	andq	$-16, %rax
	subq	%rax, %rcx
	movq	%rcx, -168(%rbp)                # 8-byte Spill
	movq	%rcx, %rsp
	movss	%xmm1, -56(%rbp)                # 4-byte Spill
	movss	%xmm1, -76(%rbp)                # 4-byte Spill
.LBB6_6:                                # %._crit_edge139
	leal	(,%rbx,8), %eax
	shll	$2, %ebx
	movslq	%eax, %r14
	leaq	-96(%rbp), %rdi
	movq	%r14, %rsi
	callq	hipMalloc
	movslq	%ebx, %rbx
	leaq	-112(%rbp), %rdi
	movq	%rbx, %rsi
	callq	hipMalloc
	leaq	-176(%rbp), %r12
	movq	%r12, %rdi
	movq	%r14, %rsi
	callq	hipMalloc
	movq	(%r12), %rdi
	xorl	%esi, %esi
	movq	%r14, %rdx
	callq	hipMemset
	leaq	-152(%rbp), %rdi
	movq	%r14, %rsi
	callq	hipMalloc
	leaq	-144(%rbp), %rdi
	movq	%r14, %rsi
	callq	hipMalloc
	leaq	-96(%rbp), %rax
	movq	(%rax), %rdi
	movq	%r15, %rsi
	movq	%r14, -184(%rbp)                # 8-byte Spill
	movq	%r14, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	-112(%rbp), %rax
	movq	(%rax), %rdi
	movq	%r13, %rsi
	movq	%rbx, -192(%rbp)                # 8-byte Spill
	movq	%rbx, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	-88(%rbp), %rbx
	movq	%rbx, %rdi
	callq	hipEventCreate
	leaq	-72(%rbp), %rdi
	callq	hipEventCreate
	movq	(%rbx), %rdi
	movabsq	$4294967328, %rbx               # imm = 0x100000020
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	%rbx, %rdi
	movl	$1, %esi
	movq	%rbx, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB6_8
# %bb.7:
	movq	-96(%rbp), %rdi
	movq	-152(%rbp), %rsi
	movq	-144(%rbp), %rdx
	movl	-44(%rbp), %ecx
	callq	_Z25__device_stub__findMinMaxP4vectS0_S0_i
.LBB6_8:
	leaq	-31(%rbx), %rdi
	movl	$1, %esi
	movq	%rbx, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB6_10
# %bb.9:
	movq	-152(%rbp), %rdi
	movq	-144(%rbp), %rcx
	movq	%rcx, %rsi
	movq	%rdi, %rdx
	movl	$32, %r8d
	callq	_Z26__device_stub__findMMinMaxP4vectS0_S0_S0_i
.LBB6_10:
	movq	%r13, -120(%rbp)                # 8-byte Spill
	movq	%r15, -128(%rbp)                # 8-byte Spill
	movq	-72(%rbp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	-72(%rbp), %rdi
	callq	hipEventSynchronize
	leaq	-48(%rbp), %rdi
	movl	$0, (%rdi)
	movq	-88(%rbp), %rsi
	movq	-72(%rbp), %rdx
	callq	hipEventElapsedTime
	movq	-152(%rbp), %rsi
	leaq	-216(%rbp), %rdi
	movl	$8, %edx
	movl	$2, %ecx
	callq	hipMemcpy
	movq	-144(%rbp), %rsi
	leaq	-208(%rbp), %rdi
	movl	$8, %edx
	movl	$2, %ecx
	callq	hipMemcpy
	movq	%rsp, %r12
	addq	$-4543824, %r12                 # imm = 0xFFBAAAB0
	movq	%r12, %rsp
	movl	$12, %eax
	pcmpeqd	%xmm0, %xmm0
.LBB6_11:                               # %.preheader
                                        # =>This Inner Loop Header: Depth=1
	movdqu	%xmm0, (%r12,%rax)
	addq	$52, %rax
	cmpq	$4543824, %rax                  # imm = 0x455550
	jne	.LBB6_11
# %bb.12:
	movss	-76(%rbp), %xmm0                # 4-byte Reload
                                        # xmm0 = mem[0],zero,zero,zero
	movss	%xmm0, (%r12)
	movss	-56(%rbp), %xmm0                # 4-byte Reload
                                        # xmm0 = mem[0],zero,zero,zero
	movss	%xmm0, 4(%r12)
	movss	-64(%rbp), %xmm0                # 4-byte Reload
                                        # xmm0 = mem[0],zero,zero,zero
	movss	%xmm0, 8(%r12)
	movl	$0, 28(%r12)
	movl	-44(%rbp), %eax
	decl	%eax
	movl	%eax, 32(%r12)
	movq	-216(%rbp), %rax
	movq	%rax, 36(%r12)
	movq	-208(%rbp), %rax
	movq	%rax, 44(%r12)
	leaq	-136(%rbp), %rbx
	movl	$4543812, %esi                  # imm = 0x455544
	movq	%rbx, %rdi
	callq	hipMalloc
	movq	(%rbx), %rdi
	movl	$1, %ebx
	movl	$4543812, %edx                  # imm = 0x455544
	movq	%r12, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	xorl	%r14d, %r14d
	movabsq	$4294967328, %rax               # imm = 0x100000020
	leaq	992(%rax), %r13
.LBB6_13:                               # =>This Inner Loop Header: Depth=1
	xorps	%xmm0, %xmm0
	cvtsi2sd	%ebx, %xmm0
	mulsd	.LCPI6_0(%rip), %xmm0
	callq	ceil@PLT
	cvttpd2dq	%xmm0, %xmm0
	cvtdq2ps	%xmm0, %xmm0
	minss	.LCPI6_1(%rip), %xmm0
	cvttss2si	%xmm0, %r15d
	movq	-88(%rbp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movabsq	$4294967328, %rax               # imm = 0x100000020
	leaq	(%rax,%r15), %rdi
	addq	$-32, %rdi
	movl	$1, %esi
	movq	%r13, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB6_15
# %bb.14:                               #   in Loop: Header=BB6_13 Depth=1
	movq	-96(%rbp), %rdi
	movq	-112(%rbp), %rsi
	movq	-136(%rbp), %rdx
	movl	%r14d, %ecx
	movl	$87381, %r8d                    # imm = 0x15555
	callq	_Z24__device_stub__constructP4vectPfP4nodeii
.LBB6_15:                               #   in Loop: Header=BB6_13 Depth=1
	movq	-72(%rbp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	-72(%rbp), %rdi
	callq	hipEventSynchronize
	movq	-88(%rbp), %rsi
	movq	-72(%rbp), %rdx
	leaq	-100(%rbp), %rdi
	callq	hipEventElapsedTime
	movss	-100(%rbp), %xmm0               # xmm0 = mem[0],zero,zero,zero
	addss	-48(%rbp), %xmm0
	movss	%xmm0, -48(%rbp)
	shll	$2, %ebx
	incl	%r14d
	cmpl	$8, %r14d
	jne	.LBB6_13
# %bb.16:
	movq	-136(%rbp), %rsi
	movl	$4543812, %edx                  # imm = 0x455544
	movq	%r12, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movl	$.L.str.2, %edi
	xorl	%eax, %eax
	callq	printf
	leaq	-156(%rbp), %rsi
	movl	$.L.str.3, %edi
	xorl	%eax, %eax
	callq	__isoc23_scanf
	xorps	%xmm0, %xmm0
	cvtsi2sdl	-44(%rbp), %xmm0
	mulsd	.LCPI6_0(%rip), %xmm0
	callq	ceil@PLT
	cvtsd2ss	%xmm0, %xmm0
	movss	.LCPI6_1(%rip), %xmm1           # xmm1 = mem[0],zero,zero,zero
	minss	%xmm0, %xmm1
	cvttss2si	%xmm1, %ebx
	movl	$.L.str.4, %edi
	movl	%ebx, %esi
	xorl	%eax, %eax
	callq	printf
	movq	-88(%rbp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movabsq	$4294967328, %rax               # imm = 0x100000020
	leaq	(%rax,%rbx), %rdi
	addq	$-32, %rdi
	movl	$1, %esi
	movq	%r13, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB6_18
# %bb.17:
	movq	-96(%rbp), %rdi
	movq	-112(%rbp), %rsi
	movq	-136(%rbp), %rdx
	movq	-176(%rbp), %rcx
	movl	-44(%rbp), %r8d
	movss	-156(%rbp), %xmm0               # xmm0 = mem[0],zero,zero,zero
	callq	_Z24__device_stub__calculateP4vectPfP4nodeS0_if
.LBB6_18:
	movq	-72(%rbp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	-72(%rbp), %rdi
	callq	hipEventSynchronize
	movq	-88(%rbp), %rsi
	movq	-72(%rbp), %rdx
	leaq	-100(%rbp), %rbx
	movq	%rbx, %rdi
	callq	hipEventElapsedTime
	movss	(%rbx), %xmm0                   # xmm0 = mem[0],zero,zero,zero
	addss	-48(%rbp), %xmm0
	movss	%xmm0, -48(%rbp)
	movq	-176(%rbp), %rsi
	movq	-168(%rbp), %r12                # 8-byte Reload
	movq	%r12, %rdi
	movq	-184(%rbp), %rbx                # 8-byte Reload
	movq	%rbx, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	movq	-96(%rbp), %rsi
	movq	-128(%rbp), %r14                # 8-byte Reload
	movq	%r14, %rdi
	movq	%rbx, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	movq	-112(%rbp), %rsi
	movq	-120(%rbp), %r15                # 8-byte Reload
	movq	%r15, %rdi
	movq	-192(%rbp), %rdx                # 8-byte Reload
	movl	$2, %ecx
	callq	hipMemcpy
	cmpl	$0, -44(%rbp)
	jle	.LBB6_19
# %bb.22:                               # %.lr.ph148.preheader
	xorps	%xmm0, %xmm0
	xorl	%ebx, %ebx
	xorps	%xmm1, %xmm1
.LBB6_23:                               # %.lr.ph148
                                        # =>This Inner Loop Header: Depth=1
	movss	%xmm1, -56(%rbp)                # 4-byte Spill
	movss	%xmm0, -64(%rbp)                # 4-byte Spill
	xorps	%xmm0, %xmm0
	cvtss2sd	(%r14,%rbx,8), %xmm0
	xorps	%xmm1, %xmm1
	cvtss2sd	4(%r14,%rbx,8), %xmm1
	xorps	%xmm2, %xmm2
	cvtss2sd	(%r15,%rbx,4), %xmm2
	xorps	%xmm3, %xmm3
	cvtss2sd	(%r12,%rbx,8), %xmm3
	xorps	%xmm4, %xmm4
	cvtss2sd	4(%r12,%rbx,8), %xmm4
	movl	$.L.str.5, %edi
	movl	%ebx, %esi
	movb	$5, %al
	callq	printf
	movss	-56(%rbp), %xmm1                # 4-byte Reload
                                        # xmm1 = mem[0],zero,zero,zero
	movss	-64(%rbp), %xmm0                # 4-byte Reload
                                        # xmm0 = mem[0],zero,zero,zero
	addss	(%r12,%rbx,8), %xmm0
	addss	4(%r12,%rbx,8), %xmm1
	incq	%rbx
	movslq	-44(%rbp), %rax
	cmpq	%rax, %rbx
	jl	.LBB6_23
# %bb.20:                               # %._crit_edge149.loopexit
	cvtss2sd	%xmm0, %xmm0
	movsd	%xmm0, -56(%rbp)                # 8-byte Spill
	xorps	%xmm0, %xmm0
	cvtss2sd	%xmm1, %xmm0
	movsd	%xmm0, -64(%rbp)                # 8-byte Spill
	jmp	.LBB6_21
.LBB6_19:
	xorps	%xmm0, %xmm0
	movsd	%xmm0, -64(%rbp)                # 8-byte Spill
	movsd	%xmm0, -56(%rbp)                # 8-byte Spill
.LBB6_21:                               # %._crit_edge149
	xorps	%xmm0, %xmm0
	cvtss2sd	-48(%rbp), %xmm0
	movl	$.L.str.6, %edi
	movb	$1, %al
	callq	printf
	movl	$.L.str.7, %edi
	movsd	-56(%rbp), %xmm0                # 8-byte Reload
                                        # xmm0 = mem[0],zero
	movsd	-64(%rbp), %xmm1                # 8-byte Reload
                                        # xmm1 = mem[0],zero
	movb	$2, %al
	callq	printf
	movq	-200(%rbp), %rsp                # 8-byte Reload
	xorl	%eax, %eax
	leaq	-40(%rbp), %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	.cfi_def_cfa %rsp, 8
	retq
.Lfunc_end6:
	.size	main, .Lfunc_end6-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB7_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB7_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z10findMinMaxP4vectS0_S0_i, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z11findMMinMaxP4vectS0_S0_S0_i, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z9constructP4vectPfP4nodeii, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z9calculateP4vectPfP4nodeS0_if, %esi
	movl	$.L__unnamed_4, %edx
	movl	$.L__unnamed_4, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end7:
	.size	__hip_module_ctor, .Lfunc_end7-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB8_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB8_2:
	retq
.Lfunc_end8:
	.size	__hip_module_dtor, .Lfunc_end8-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z10findMinMaxP4vectS0_S0_i,@object # @_Z10findMinMaxP4vectS0_S0_i
	.section	.rodata,"a",@progbits
	.globl	_Z10findMinMaxP4vectS0_S0_i
	.p2align	3, 0x0
_Z10findMinMaxP4vectS0_S0_i:
	.quad	_Z25__device_stub__findMinMaxP4vectS0_S0_i
	.size	_Z10findMinMaxP4vectS0_S0_i, 8

	.type	_Z11findMMinMaxP4vectS0_S0_S0_i,@object # @_Z11findMMinMaxP4vectS0_S0_S0_i
	.globl	_Z11findMMinMaxP4vectS0_S0_S0_i
	.p2align	3, 0x0
_Z11findMMinMaxP4vectS0_S0_S0_i:
	.quad	_Z26__device_stub__findMMinMaxP4vectS0_S0_S0_i
	.size	_Z11findMMinMaxP4vectS0_S0_S0_i, 8

	.type	_Z9constructP4vectPfP4nodeii,@object # @_Z9constructP4vectPfP4nodeii
	.globl	_Z9constructP4vectPfP4nodeii
	.p2align	3, 0x0
_Z9constructP4vectPfP4nodeii:
	.quad	_Z24__device_stub__constructP4vectPfP4nodeii
	.size	_Z9constructP4vectPfP4nodeii, 8

	.type	_Z9calculateP4vectPfP4nodeS0_if,@object # @_Z9calculateP4vectPfP4nodeS0_if
	.globl	_Z9calculateP4vectPfP4nodeS0_if
	.p2align	3, 0x0
_Z9calculateP4vectPfP4nodeS0_if:
	.quad	_Z24__device_stub__calculateP4vectPfP4nodeS0_if
	.size	_Z9calculateP4vectPfP4nodeS0_if, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"n : "
	.size	.L.str, 5

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"%d"
	.size	.L.str.1, 3

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"theta : "
	.size	.L.str.2, 9

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"%f"
	.size	.L.str.3, 3

	.type	.L.str.4,@object                # @.str.4
.L.str.4:
	.asciz	"%d\n"
	.size	.L.str.4, 4

	.type	.L.str.5,@object                # @.str.5
.L.str.5:
	.asciz	"force %d : x %f y %f m %f : %.15f %.15f\n"
	.size	.L.str.5, 41

	.type	.L.str.6,@object                # @.str.6
.L.str.6:
	.asciz	"gpu time : %f\n"
	.size	.L.str.6, 15

	.type	.L.str.7,@object                # @.str.7
.L.str.7:
	.asciz	"x %f y %f\n"
	.size	.L.str.7, 11

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z10findMinMaxP4vectS0_S0_i"
	.size	.L__unnamed_1, 28

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z11findMMinMaxP4vectS0_S0_S0_i"
	.size	.L__unnamed_2, 32

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z9constructP4vectPfP4nodeii"
	.size	.L__unnamed_3, 29

	.type	.L__unnamed_4,@object           # @3
.L__unnamed_4:
	.asciz	"_Z9calculateP4vectPfP4nodeS0_if"
	.size	.L__unnamed_4, 32

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z25__device_stub__findMinMaxP4vectS0_S0_i
	.addrsig_sym _Z26__device_stub__findMMinMaxP4vectS0_S0_S0_i
	.addrsig_sym _Z24__device_stub__constructP4vectPfP4nodeii
	.addrsig_sym _Z24__device_stub__calculateP4vectPfP4nodeS0_if
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z10findMinMaxP4vectS0_S0_i
	.addrsig_sym _Z11findMMinMaxP4vectS0_S0_S0_i
	.addrsig_sym _Z9constructP4vectPfP4nodeii
	.addrsig_sym _Z9calculateP4vectPfP4nodeS0_if
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z10findMinMaxP4vectS0_S0_i ; -- Begin function _Z10findMinMaxP4vectS0_S0_i
	.globl	_Z10findMinMaxP4vectS0_S0_i
	.p2align	8
	.type	_Z10findMinMaxP4vectS0_S0_i,@function
_Z10findMinMaxP4vectS0_S0_i:            ; @_Z10findMinMaxP4vectS0_S0_i
; %bb.0:
	s_clause 0x3
	s_load_b32 s3, s[0:1], 0x2c
	s_load_b32 s10, s[0:1], 0x18
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b64 s[8:9], s[0:1], 0x10
	s_add_u32 s0, s0, 32
	s_mov_b32 s2, s15
	s_addc_u32 s1, s1, 0
	v_mov_b32_e32 v2, 0x800000
	v_dual_mov_b32 v4, 0x7f7fffff :: v_dual_mov_b32 v3, 0x7f7fffff
	s_mov_b32 s11, exec_lo
	s_waitcnt lgkmcnt(0)
	s_and_b32 s3, s3, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[5:6], null, s2, s3, v[0:1]
	v_mov_b32_e32 v1, 0x800000
	v_cmpx_gt_i32_e64 s10, v5
	s_cbranch_execz .LBB0_4
; %bb.1:                                ; %.lr.ph
	s_load_b32 s1, s[0:1], 0x0
	v_dual_mov_b32 v2, 0x800000 :: v_dual_mov_b32 v1, 0x800000
	v_dual_mov_b32 v4, 0x7f7fffff :: v_dual_mov_b32 v3, 0x7f7fffff
	s_mov_b32 s0, 0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s1, s1, s3
.LBB0_2:                                ; =>This Inner Loop Header: Depth=1
	v_ashrrev_i32_e32 v6, 31, v5
	v_dual_max_f32 v3, v3, v3 :: v_dual_max_f32 v4, v4, v4
	v_dual_max_f32 v1, v1, v1 :: v_dual_max_f32 v2, v2, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[6:7], 3, v[5:6]
	v_add_co_u32 v6, vcc_lo, s4, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
	global_load_b64 v[6:7], v[6:7], off
	s_waitcnt vmcnt(0)
	v_dual_max_f32 v6, v6, v6 :: v_dual_add_nc_u32 v5, s1, v5
	v_max_f32_e32 v7, v7, v7
	v_cmp_le_i32_e32 vcc_lo, s10, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_dual_min_f32 v3, v3, v6 :: v_dual_min_f32 v4, v4, v7
	v_dual_max_f32 v1, v1, v6 :: v_dual_max_f32 v2, v2, v7
	s_or_b32 s0, vcc_lo, s0
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB0_2
; %bb.3:                                ; %Flow
	s_or_b32 exec_lo, exec_lo, s0
.LBB0_4:                                ; %Flow91
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_or_b32 exec_lo, exec_lo, s11
	v_lshlrev_b32_e32 v5, 3, v0
	v_add_nc_u32_e32 v6, 0x100, v5
	ds_store_2addr_b64 v5, v[1:2], v[3:4] offset1:32
.LBB0_5:                                ; =>This Inner Loop Header: Depth=1
	s_lshr_b32 s0, s3, 1
	s_mov_b32 s1, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e64 s0, v0
	s_cbranch_execz .LBB0_7
; %bb.6:                                ;   in Loop: Header=BB0_5 Depth=1
	s_lshl_b32 s4, s0, 3
	s_delay_alu instid0(SALU_CYCLE_1)
	v_add_nc_u32_e32 v3, s4, v6
	v_add_nc_u32_e32 v7, s4, v5
	ds_load_b64 v[1:2], v6
	ds_load_b64 v[3:4], v3
	ds_load_b64 v[7:8], v7
	ds_load_b64 v[9:10], v5
	s_waitcnt lgkmcnt(3)
	v_dual_max_f32 v2, v2, v2 :: v_dual_max_f32 v1, v1, v1
	s_waitcnt lgkmcnt(1)
	v_dual_max_f32 v8, v8, v8 :: v_dual_max_f32 v3, v3, v3
	s_waitcnt lgkmcnt(0)
	v_max_f32_e32 v10, v10, v10
	v_dual_max_f32 v4, v4, v4 :: v_dual_max_f32 v7, v7, v7
	v_max_f32_e32 v9, v9, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_min_f32 v1, v1, v3 :: v_dual_min_f32 v2, v2, v4
	v_dual_max_f32 v4, v10, v8 :: v_dual_max_f32 v3, v9, v7
	ds_store_b64 v6, v[1:2]
	ds_store_b64 v5, v[3:4]
.LBB0_7:                                ;   in Loop: Header=BB0_5 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_cmp_gt_u32 s3, 3
	s_mov_b32 s3, s0
	s_cbranch_scc1 .LBB0_5
; %bb.8:
	s_mov_b32 s3, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB0_10
; %bb.9:
	v_mov_b32_e32 v4, 0
	s_lshl_b64 s[0:1], s[2:3], 3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s2, s8, s0
	s_addc_u32 s3, s9, s1
	ds_load_2addr_b64 v[0:3], v4 offset1:32
	s_add_u32 s0, s6, s0
	s_addc_u32 s1, s7, s1
	s_waitcnt lgkmcnt(0)
	s_clause 0x1
	global_store_b64 v4, v[2:3], s[0:1]
	global_store_b64 v4, v[0:1], s[2:3]
.LBB0_10:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z10findMinMaxP4vectS0_S0_i
		.amdhsa_group_segment_fixed_size 512
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 11
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z10findMinMaxP4vectS0_S0_i, .Lfunc_end0-_Z10findMinMaxP4vectS0_S0_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 568
; NumSgprs: 18
; NumVgprs: 11
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 512 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 11
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z11findMMinMaxP4vectS0_S0_S0_i ; -- Begin function _Z11findMMinMaxP4vectS0_S0_S0_i
	.globl	_Z11findMMinMaxP4vectS0_S0_S0_i
	.p2align	8
	.type	_Z11findMMinMaxP4vectS0_S0_S0_i,@function
_Z11findMMinMaxP4vectS0_S0_S0_i:        ; @_Z11findMMinMaxP4vectS0_S0_S0_i
; %bb.0:
	s_clause 0x2
	s_load_b32 s3, s[0:1], 0x34
	s_load_b32 s12, s[0:1], 0x20
	s_load_b256 s[4:11], s[0:1], 0x0
	s_add_u32 s0, s0, 40
	s_mov_b32 s2, s15
	s_addc_u32 s1, s1, 0
	v_mov_b32_e32 v2, 0x800000
	v_dual_mov_b32 v4, 0x7f7fffff :: v_dual_mov_b32 v3, 0x7f7fffff
	s_mov_b32 s13, exec_lo
	s_waitcnt lgkmcnt(0)
	s_and_b32 s3, s3, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[5:6], null, s2, s3, v[0:1]
	v_mov_b32_e32 v1, 0x800000
	v_cmpx_gt_i32_e64 s12, v5
	s_cbranch_execz .LBB1_4
; %bb.1:                                ; %.lr.ph
	s_load_b32 s1, s[0:1], 0x0
	v_dual_mov_b32 v2, 0x800000 :: v_dual_mov_b32 v1, 0x800000
	v_dual_mov_b32 v4, 0x7f7fffff :: v_dual_mov_b32 v3, 0x7f7fffff
	s_mov_b32 s0, 0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s1, s1, s3
.LBB1_2:                                ; =>This Inner Loop Header: Depth=1
	v_ashrrev_i32_e32 v6, 31, v5
	v_dual_max_f32 v3, v3, v3 :: v_dual_max_f32 v4, v4, v4
	v_dual_max_f32 v1, v1, v1 :: v_dual_max_f32 v2, v2, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[6:7], 3, v[5:6]
	v_add_co_u32 v8, vcc_lo, s8, v6
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v9, vcc_lo, s9, v7, vcc_lo
	v_add_co_u32 v6, vcc_lo, s10, v6
	v_add_co_ci_u32_e32 v7, vcc_lo, s11, v7, vcc_lo
	global_load_b64 v[8:9], v[8:9], off
	global_load_b64 v[6:7], v[6:7], off
	s_waitcnt vmcnt(1)
	v_dual_max_f32 v8, v8, v8 :: v_dual_add_nc_u32 v5, s1, v5
	s_waitcnt vmcnt(0)
	v_dual_max_f32 v9, v9, v9 :: v_dual_max_f32 v6, v6, v6
	v_max_f32_e32 v7, v7, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_le_i32_e32 vcc_lo, s12, v5
	v_dual_min_f32 v4, v4, v9 :: v_dual_min_f32 v3, v3, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_dual_max_f32 v2, v2, v7 :: v_dual_max_f32 v1, v1, v6
	s_or_b32 s0, vcc_lo, s0
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB1_2
; %bb.3:                                ; %Flow
	s_or_b32 exec_lo, exec_lo, s0
.LBB1_4:                                ; %Flow95
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_or_b32 exec_lo, exec_lo, s13
	v_lshlrev_b32_e32 v5, 3, v0
	v_add_nc_u32_e32 v6, 0x100, v5
	ds_store_2addr_b64 v5, v[1:2], v[3:4] offset1:32
.LBB1_5:                                ; =>This Inner Loop Header: Depth=1
	s_lshr_b32 s0, s3, 1
	s_mov_b32 s1, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e64 s0, v0
	s_cbranch_execz .LBB1_7
; %bb.6:                                ;   in Loop: Header=BB1_5 Depth=1
	s_lshl_b32 s8, s0, 3
	s_delay_alu instid0(SALU_CYCLE_1)
	v_add_nc_u32_e32 v3, s8, v6
	v_add_nc_u32_e32 v7, s8, v5
	ds_load_b64 v[1:2], v6
	ds_load_b64 v[3:4], v3
	ds_load_b64 v[7:8], v7
	ds_load_b64 v[9:10], v5
	s_waitcnt lgkmcnt(3)
	v_dual_max_f32 v2, v2, v2 :: v_dual_max_f32 v1, v1, v1
	s_waitcnt lgkmcnt(1)
	v_dual_max_f32 v8, v8, v8 :: v_dual_max_f32 v3, v3, v3
	s_waitcnt lgkmcnt(0)
	v_max_f32_e32 v10, v10, v10
	v_dual_max_f32 v4, v4, v4 :: v_dual_max_f32 v7, v7, v7
	v_max_f32_e32 v9, v9, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_min_f32 v1, v1, v3 :: v_dual_min_f32 v2, v2, v4
	v_dual_max_f32 v4, v10, v8 :: v_dual_max_f32 v3, v9, v7
	ds_store_b64 v6, v[1:2]
	ds_store_b64 v5, v[3:4]
.LBB1_7:                                ;   in Loop: Header=BB1_5 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_cmp_gt_u32 s3, 3
	s_mov_b32 s3, s0
	s_cbranch_scc1 .LBB1_5
; %bb.8:
	s_mov_b32 s3, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB1_10
; %bb.9:
	v_mov_b32_e32 v4, 0
	s_lshl_b64 s[0:1], s[2:3], 3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s2, s6, s0
	s_addc_u32 s3, s7, s1
	ds_load_2addr_b64 v[0:3], v4 offset1:32
	s_add_u32 s0, s4, s0
	s_addc_u32 s1, s5, s1
	s_waitcnt lgkmcnt(0)
	s_clause 0x1
	global_store_b64 v4, v[2:3], s[0:1]
	global_store_b64 v4, v[0:1], s[2:3]
.LBB1_10:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z11findMMinMaxP4vectS0_S0_S0_i
		.amdhsa_group_segment_fixed_size 512
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 11
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z11findMMinMaxP4vectS0_S0_S0_i, .Lfunc_end1-_Z11findMMinMaxP4vectS0_S0_S0_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 596
; NumSgprs: 18
; NumVgprs: 11
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 512 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 11
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z9constructP4vectPfP4nodeii ; -- Begin function _Z9constructP4vectPfP4nodeii
	.globl	_Z9constructP4vectPfP4nodeii
	.p2align	8
	.type	_Z9constructP4vectPfP4nodeii,@function
_Z9constructP4vectPfP4nodeii:           ; @_Z9constructP4vectPfP4nodeii
; %bb.0:
	s_clause 0x1
	s_load_b32 s6, s[2:3], 0x2c
	s_load_b64 s[8:9], s[2:3], 0x18
	v_and_b32_e32 v1, 0x3ff, v0
	s_add_u32 s4, s2, 32
	s_addc_u32 s5, s3, 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s11, s6, 0xffff
	s_lshl_b32 s6, s8, 1
	v_mad_u64_u32 v[8:9], null, s15, s11, v[1:2]
	s_lshl_b32 s10, 1, s6
	s_mov_b32 s6, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e64 s10, v8
	s_cbranch_execz .LBB2_37
; %bb.1:                                ; %.lr.ph260
	s_load_b64 s[0:1], s[0:1], 0x4
	s_load_b32 s8, s[4:5], 0x0
	v_bfe_u32 v2, v0, 10, 10
	s_load_b128 s[4:7], s[2:3], 0x0
	v_bfe_u32 v3, v0, 20, 10
	s_load_b64 s[2:3], s[2:3], 0x10
	v_dual_mov_b32 v0, 0x7f7fffff :: v_dual_mov_b32 v9, 0
	v_mov_b32_e32 v4, -1
	s_mov_b32 s18, 0
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s0, s0, 16
	v_mul_u32_u24_e32 v2, s1, v2
	s_mul_i32 s0, s0, s1
	s_mul_i32 s11, s8, s11
	v_mul_lo_u32 v1, s0, v1
	s_add_i32 s0, s10, -1
	s_mov_b32 s8, 16
	s_mul_hi_i32 s1, s0, 0x55555556
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshr_b32 s0, s1, 31
	s_add_i32 s1, s1, s0
	s_delay_alu instid0(VALU_DEP_1)
	v_add3_u32 v1, v1, v2, v3
	s_add_i32 s0, s1, s10
	s_add_u32 s12, s4, 8
	s_addc_u32 s13, s5, 0
	v_mov_b32_e32 v2, 0x800000
	v_mul_lo_u32 v25, v1, 52
	v_mov_b32_e32 v24, 16
	v_lshl_add_u32 v26, v8, 2, s0
	s_add_u32 s14, s6, 4
	s_addc_u32 s15, s7, 0
	s_add_u32 s16, s4, 4
	s_addc_u32 s17, s5, 0
	s_delay_alu instid0(VALU_DEP_3)
	v_add_nc_u32_e32 v27, 12, v25
.LBB2_2:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB2_4 Depth 2
                                        ;     Child Loop BB2_7 Depth 2
                                        ;     Child Loop BB2_12 Depth 2
                                        ;       Child Loop BB2_14 Depth 3
                                        ;     Child Loop BB2_28 Depth 2
                                        ;     Child Loop BB2_33 Depth 2
	v_add_nc_u32_e32 v1, s1, v8
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_mad_i64_i32 v[11:12], null, v1, 52, s[2:3]
	s_clause 0x4
	global_load_b128 v[13:16], v[11:12], off offset:32
	global_load_b64 v[5:6], v[11:12], off offset:28
	global_load_b128 v[17:20], v[11:12], off offset:16
	global_load_b128 v[28:31], v[11:12], off
	global_load_b32 v1, v[11:12], off offset:48
	s_waitcnt vmcnt(4)
	ds_store_2addr_b32 v25, v13, v14 offset0:8 offset1:9
	s_waitcnt vmcnt(2)
	ds_store_2addr_b32 v25, v19, v20 offset0:6 offset1:7
	ds_store_2addr_b32 v25, v17, v18 offset0:4 offset1:5
	s_waitcnt vmcnt(1)
	ds_store_2addr_b32 v25, v30, v31 offset0:2 offset1:3
	ds_store_2addr_b32 v25, v28, v29 offset1:1
	ds_store_2addr_b32 v25, v15, v16 offset0:10 offset1:11
	s_waitcnt vmcnt(0)
	ds_store_b32 v25, v1 offset:48
	v_cmpx_le_i32_e64 v5, v6
	s_xor_b32 s19, exec_lo, s0
	s_cbranch_execz .LBB2_31
; %bb.3:                                ;   in Loop: Header=BB2_2 Depth=1
	ds_load_2addr_b32 v[13:14], v25 offset0:11 offset1:12
	ds_load_2addr_b32 v[15:16], v25 offset0:9 offset1:10
	ds_load_2addr_b32 v[17:18], v25 offset0:7 offset1:8
	s_mov_b32 s0, 0
.LBB2_4:                                ;   Parent Loop BB2_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_add_nc_u32_e64 v10, s0, 16
	v_mov_b32_e32 v1, v0
	v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v6, v4
	v_mov_b32_e32 v5, v4
	v_add_nc_u32_e32 v19, 36, v10
	v_dual_mov_b32 v7, v4 :: v_dual_add_nc_u32 v10, 12, v10
	s_add_i32 s0, s0, 52
	s_clause 0x1
	scratch_store_b128 v19, v[0:3], off
	scratch_store_b128 v10, v[4:7], off
	s_cmpk_eq_i32 s0, 0xd0
	s_cbranch_scc0 .LBB2_4
; %bb.5:                                ;   in Loop: Header=BB2_2 Depth=1
	s_waitcnt lgkmcnt(0)
	v_cvt_f32_i32_e32 v1, v17
	v_sub_f32_e32 v6, v13, v15
	v_cvt_f32_i32_e32 v3, v18
	s_mov_b32 s20, exec_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_add_f32_e32 v7, -1.0, v1
	v_cvt_i32_f32_e32 v5, v1
	v_fma_f32 v1, 0.5, v6, v15
	v_cvt_i32_f32_e32 v17, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f32_i32_e32 v10, v5
	v_cmpx_le_f32_e32 v10, v3
	s_cbranch_execz .LBB2_11
; %bb.6:                                ; %.lr.ph.preheader
                                        ;   in Loop: Header=BB2_2 Depth=1
	v_ashrrev_i32_e32 v6, 31, v5
	v_add_nc_u32_e32 v10, 1, v5
	s_mov_b32 s21, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[18:19], 3, v[5:6]
	v_lshlrev_b64 v[20:21], 2, v[5:6]
	v_add_co_u32 v6, vcc_lo, s4, v18
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v7, vcc_lo, s5, v19, vcc_lo
	v_add_co_u32 v19, vcc_lo, s6, v20
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v20, vcc_lo, s7, v21, vcc_lo
.LBB2_7:                                ; %.lr.ph
                                        ;   Parent Loop BB2_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	global_load_b32 v18, v[6:7], off
	s_mov_b32 s0, exec_lo
	s_waitcnt vmcnt(0)
	v_cmpx_le_f32_e32 v18, v1
	s_cbranch_execz .LBB2_9
; %bb.8:                                ;   in Loop: Header=BB2_7 Depth=2
	v_ashrrev_i32_e32 v18, 31, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[21:22], 3, v[17:18]
	v_lshlrev_b64 v[32:33], 2, v[17:18]
	v_add_nc_u32_e32 v17, 1, v17
	v_add_co_u32 v21, vcc_lo, s12, v21
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_ci_u32_e32 v22, vcc_lo, s13, v22, vcc_lo
	v_add_co_u32 v32, vcc_lo, s14, v32
	global_load_b64 v[28:29], v[6:7], off
	global_load_b64 v[30:31], v[21:22], off
	v_add_co_ci_u32_e32 v33, vcc_lo, s15, v33, vcc_lo
	s_waitcnt vmcnt(1)
	global_store_b64 v[21:22], v[28:29], off
	s_waitcnt vmcnt(0)
	global_store_b64 v[6:7], v[30:31], off
	global_load_b32 v18, v[19:20], off
	global_load_b32 v21, v[32:33], off
	s_waitcnt vmcnt(1)
	global_store_b32 v[32:33], v18, off
	s_waitcnt vmcnt(0)
	global_store_b32 v[19:20], v21, off
.LBB2_9:                                ;   in Loop: Header=BB2_7 Depth=2
	s_or_b32 exec_lo, exec_lo, s0
	v_cvt_f32_i32_e32 v18, v10
	v_add_co_u32 v6, vcc_lo, v6, 8
	v_add_co_ci_u32_e32 v7, vcc_lo, 0, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_nle_f32_e32 vcc_lo, v18, v3
	v_add_co_u32 v19, s0, v19, 4
	v_add_co_ci_u32_e64 v20, s0, 0, v20, s0
	v_add_nc_u32_e32 v10, 1, v10
	s_or_b32 s21, vcc_lo, s21
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s21
	s_cbranch_execnz .LBB2_7
; %bb.10:                               ; %Flow367
                                        ;   in Loop: Header=BB2_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s21
.LBB2_11:                               ; %Flow368
                                        ;   in Loop: Header=BB2_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_3)
	s_or_b32 exec_lo, exec_lo, s20
	v_dual_sub_f32 v7, v14, v16 :: v_dual_mov_b32 v6, v17
	v_cvt_i32_f32_e32 v18, v3
	v_add_nc_u32_e32 v17, 1, v17
	s_mov_b32 s20, 2
	v_fma_f32 v3, 0.5, v7, v16
	s_clause 0x1
	scratch_store_b64 off, v[5:6], off offset:148
	scratch_store_b64 off, v[17:18], off offset:200
.LBB2_12:                               ;   Parent Loop BB2_2 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB2_14 Depth 3
	s_mul_i32 s21, s20, 52
	v_dual_mov_b32 v34, 0 :: v_dual_mov_b32 v29, 0
	s_add_i32 s0, s21, 16
	v_dual_mov_b32 v31, 0 :: v_dual_mov_b32 v30, 0
	scratch_load_b64 v[5:6], off, s0 offset:28
	v_mov_b32_e32 v7, 0
	v_mov_b32_e32 v33, 0
	s_mov_b32 s22, exec_lo
	v_mov_b32_e32 v28, 0
	s_waitcnt vmcnt(0)
	v_cvt_f32_i32_e32 v32, v5
	v_cvt_f32_i32_e32 v10, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cvt_i32_f32_e32 v19, v32
	v_add_f32_e32 v5, -1.0, v32
	v_cvt_f32_i32_e32 v6, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_i32_f32_e32 v17, v5
	v_cmpx_le_f32_e32 v6, v10
	s_cbranch_execz .LBB2_18
; %bb.13:                               ; %.lr.ph245.preheader
                                        ;   in Loop: Header=BB2_12 Depth=2
	v_ashrrev_i32_e32 v20, 31, v19
	v_dual_mov_b32 v34, 0 :: v_dual_add_nc_u32 v35, 1, v19
	v_dual_mov_b32 v29, 0 :: v_dual_mov_b32 v30, 0
	s_delay_alu instid0(VALU_DEP_3)
	v_lshlrev_b64 v[5:6], 3, v[19:20]
	v_lshlrev_b64 v[20:21], 2, v[19:20]
	v_dual_mov_b32 v31, 0 :: v_dual_mov_b32 v28, 0
	v_mov_b32_e32 v7, 0
	v_mov_b32_e32 v33, 0
	v_add_co_u32 v5, vcc_lo, s16, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, s17, v6, vcc_lo
	v_add_co_u32 v20, vcc_lo, s6, v20
	v_add_co_ci_u32_e32 v21, vcc_lo, s7, v21, vcc_lo
	s_mov_b32 s23, 0
.LBB2_14:                               ; %.lr.ph245
                                        ;   Parent Loop BB2_2 Depth=1
                                        ;     Parent Loop BB2_12 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	global_load_b64 v[22:23], v[5:6], off offset:-4
	global_load_b32 v36, v[20:21], off
	s_mov_b32 s0, exec_lo
	s_waitcnt vmcnt(1)
	v_cmpx_le_f32_e32 v23, v3
	s_cbranch_execz .LBB2_16
; %bb.15:                               ;   in Loop: Header=BB2_14 Depth=3
	v_ashrrev_i32_e32 v18, 31, v17
	v_add_f32_e32 v31, v31, v22
	v_dual_add_f32 v29, v29, v23 :: v_dual_add_nc_u32 v34, 1, v34
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v7, v7, v36
	v_lshlrev_b64 v[37:38], 3, v[17:18]
	v_lshlrev_b64 v[43:44], 2, v[17:18]
	v_add_nc_u32_e32 v17, 1, v17
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v37, vcc_lo, s12, v37
	v_add_co_ci_u32_e32 v38, vcc_lo, s13, v38, vcc_lo
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_u32 v43, vcc_lo, s14, v43
	global_load_b64 v[39:40], v[5:6], off offset:-4
	global_load_b64 v[41:42], v[37:38], off
	v_add_co_ci_u32_e32 v44, vcc_lo, s15, v44, vcc_lo
	s_waitcnt vmcnt(1)
	global_store_b64 v[37:38], v[39:40], off
	s_waitcnt vmcnt(0)
	global_store_b64 v[5:6], v[41:42], off offset:-4
	global_load_b32 v18, v[20:21], off
	global_load_b32 v37, v[43:44], off
	s_waitcnt vmcnt(1)
	global_store_b32 v[43:44], v18, off
	s_waitcnt vmcnt(0)
	global_store_b32 v[20:21], v37, off
.LBB2_16:                               ;   in Loop: Header=BB2_14 Depth=3
	s_or_b32 exec_lo, exec_lo, s0
	v_cvt_f32_i32_e32 v18, v35
	v_add_co_u32 v5, s0, v5, 8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v6, s0, 0, v6, s0
	v_cmp_nle_f32_e32 vcc_lo, v18, v10
	v_add_co_u32 v20, s0, v20, 4
	v_dual_add_f32 v33, v33, v22 :: v_dual_add_f32 v30, v30, v23
	s_waitcnt vmcnt(0)
	v_dual_add_f32 v28, v28, v36 :: v_dual_add_nc_u32 v35, 1, v35
	v_add_co_ci_u32_e64 v21, s0, 0, v21, s0
	s_or_b32 s23, vcc_lo, s23
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s23
	s_cbranch_execnz .LBB2_14
; %bb.17:                               ; %Flow365
                                        ;   in Loop: Header=BB2_12 Depth=2
	s_or_b32 exec_lo, exec_lo, s23
.LBB2_18:                               ; %Flow366
                                        ;   in Loop: Header=BB2_12 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	s_or_b32 exec_lo, exec_lo, s22
	v_add_nc_u32_e64 v18, s21, 16
	v_cvt_f32_i32_e32 v20, v34
	s_mov_b32 s0, exec_lo
	v_add_nc_u32_e32 v21, 28, v18
	v_cmpx_gt_i32_e32 1, v34
	s_xor_b32 s0, exec_lo, s0
; %bb.19:                               ; %._crit_edge246._crit_edge
                                        ;   in Loop: Header=BB2_12 Depth=2
	v_cvt_f32_i32_e32 v20, v34
; %bb.20:                               ; %Flow364
                                        ;   in Loop: Header=BB2_12 Depth=2
	s_and_not1_saveexec_b32 s21, s0
	s_cbranch_execz .LBB2_22
; %bb.21:                               ;   in Loop: Header=BB2_12 Depth=2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_div_scale_f32 v5, null, v20, v20, v31
	v_div_scale_f32 v6, null, v20, v20, v29
	v_div_scale_f32 v36, vcc_lo, v31, v20, v31
	v_rcp_f32_e32 v22, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v23, v6
	s_waitcnt_depctr 0xfff
	v_fma_f32 v34, -v5, v22, 1.0
	v_fma_f32 v35, -v6, v23, 1.0
	v_dual_fmac_f32 v22, v34, v22 :: v_dual_fmac_f32 v23, v35, v23
	v_div_scale_f32 v34, s0, v29, v20, v29
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v35, v36, v22
	v_mul_f32_e32 v37, v34, v23
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v38, -v5, v35, v36
	v_fma_f32 v39, -v6, v37, v34
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v35, v38, v22
	v_fmac_f32_e32 v37, v39, v23
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v5, -v5, v35, v36
	v_fma_f32 v6, -v6, v37, v34
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_fmas_f32 v5, v5, v22, v35
	s_mov_b32 vcc_lo, s0
	v_div_fmas_f32 v6, v6, v23, v37
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fixup_f32 v5, v5, v20, v31
	v_div_fixup_f32 v6, v6, v20, v29
	scratch_store_b96 v18, v[5:7], off
.LBB2_22:                               ;   in Loop: Header=BB2_12 Depth=2
	s_or_b32 exec_lo, exec_lo, s21
	v_sub_f32_e32 v5, v10, v32
	s_mov_b32 s21, exec_lo
                                        ; implicit-def: $sgpr0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v5, 1.0, v5
	v_sub_f32_e32 v5, v5, v20
	v_mov_b32_e32 v20, v17
	s_delay_alu instid0(VALU_DEP_2)
	v_cvt_i32_f32_e32 v5, v5
	scratch_store_b64 v21, v[19:20], off
	v_cmpx_gt_i32_e32 1, v5
	s_xor_b32 s21, exec_lo, s21
; %bb.23:                               ; %._crit_edge270
                                        ;   in Loop: Header=BB2_12 Depth=2
	s_add_i32 s0, s20, -2
                                        ; implicit-def: $vgpr30
                                        ; implicit-def: $vgpr29
                                        ; implicit-def: $vgpr33
                                        ; implicit-def: $vgpr31
                                        ; implicit-def: $vgpr28
                                        ; implicit-def: $vgpr7
                                        ; implicit-def: $vgpr5
                                        ; implicit-def: $vgpr18
; %bb.24:                               ; %Flow
                                        ;   in Loop: Header=BB2_12 Depth=2
	s_or_saveexec_b32 s21, s21
	v_mov_b32_e32 v6, s0
	s_xor_b32 exec_lo, exec_lo, s21
	s_cbranch_execz .LBB2_26
; %bb.25:                               ;   in Loop: Header=BB2_12 Depth=2
	v_sub_f32_e32 v6, v33, v31
	v_cvt_f32_i32_e32 v5, v5
	v_sub_f32_e32 v20, v30, v29
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_scale_f32 v19, null, v5, v5, v6
	v_div_scale_f32 v21, null, v5, v5, v20
	v_div_scale_f32 v31, vcc_lo, v6, v5, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rcp_f32_e32 v22, v19
	v_rcp_f32_e32 v23, v21
	s_waitcnt_depctr 0xfff
	v_fma_f32 v29, -v19, v22, 1.0
	v_fma_f32 v30, -v21, v23, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_fmac_f32 v22, v29, v22 :: v_dual_fmac_f32 v23, v30, v23
	v_div_scale_f32 v29, s0, v20, v5, v20
	v_mul_f32_e32 v30, v31, v22
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v32, v29, v23
	v_fma_f32 v33, -v19, v30, v31
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v34, -v21, v32, v29
	v_fmac_f32_e32 v30, v33, v22
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v32, v34, v23
	v_fma_f32 v19, -v19, v30, v31
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v21, -v21, v32, v29
	v_div_fmas_f32 v19, v19, v22, v30
	s_mov_b32 vcc_lo, s0
	s_add_i32 s0, s20, -2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_div_fmas_f32 v22, v21, v23, v32
	v_sub_f32_e32 v21, v28, v7
	v_div_fixup_f32 v19, v19, v5, v6
	v_mov_b32_e32 v6, s0
	v_div_fixup_f32 v20, v22, v5, v20
	scratch_store_b96 v18, v[19:21], off offset:-104
.LBB2_26:                               ;   in Loop: Header=BB2_12 Depth=2
	s_or_b32 exec_lo, exec_lo, s21
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[18:19], null, v6, 52, s[8:9]
	v_add_nc_u32_e32 v5, 1, v17
	v_cvt_i32_f32_e32 v6, v10
	s_add_i32 s20, s20, 1
	s_cmp_lg_u32 s20, 4
	scratch_store_b64 v18, v[5:6], off offset:28
	s_cbranch_scc1 .LBB2_12
; %bb.27:                               ; %.preheader230.preheader
                                        ;   in Loop: Header=BB2_2 Depth=1
	v_mov_b32_e32 v5, v27
	s_mov_b32 s0, 0
	s_mov_b32 s20, 0
.LBB2_28:                               ; %.preheader230
                                        ;   Parent Loop BB2_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_readfirstlane_b32 s21, v24
	s_bitcmp0_b32 s20, 0
	v_add_nc_u32_e32 v6, s20, v26
	s_cselect_b32 vcc_lo, -1, 0
	v_cndmask_b32_e32 v17, v1, v15, vcc_lo
	s_add_i32 s21, s21, s0
	v_cndmask_b32_e32 v19, v13, v1, vcc_lo
	s_add_i32 s22, s21, 36
	s_cmp_lt_u32 s20, 2
	s_cselect_b32 vcc_lo, -1, 0
	v_cndmask_b32_e32 v18, v16, v3, vcc_lo
	v_cndmask_b32_e32 v20, v3, v14, vcc_lo
	scratch_store_b128 off, v[17:20], s22
	s_mov_b32 s22, exec_lo
	v_cmpx_gt_i32_e64 s9, v6
	s_cbranch_execz .LBB2_30
; %bb.29:                               ;   in Loop: Header=BB2_28 Depth=2
	s_add_i32 s23, s21, 48
	s_add_i32 s24, s21, 32
	scratch_load_b32 v7, off, s23
	s_add_i32 s23, s21, 16
	s_clause 0x2
	scratch_load_b128 v[17:20], off, s24
	scratch_load_b128 v[28:31], off, s21
	scratch_load_b128 v[32:35], off, s23
	v_mad_i64_i32 v[21:22], null, v6, 52, s[2:3]
	s_waitcnt vmcnt(3)
	global_store_b32 v[21:22], v7, off offset:48
	s_waitcnt vmcnt(2)
	global_store_b128 v[21:22], v[17:20], off offset:32
	s_waitcnt vmcnt(1)
	global_store_b128 v[21:22], v[28:31], off
	s_waitcnt vmcnt(0)
	global_store_b128 v[21:22], v[32:35], off offset:16
.LBB2_30:                               ;   in Loop: Header=BB2_28 Depth=2
	s_or_b32 exec_lo, exec_lo, s22
	ds_store_b32 v5, v6
	v_add_nc_u32_e32 v5, 4, v5
	s_add_i32 s0, s0, 52
	s_add_i32 s20, s20, 1
	s_cmpk_eq_i32 s0, 0xd0
	s_cbranch_scc0 .LBB2_28
.LBB2_31:                               ; %Flow370
                                        ;   in Loop: Header=BB2_2 Depth=1
	s_and_not1_saveexec_b32 s0, s19
	s_cbranch_execz .LBB2_36
; %bb.32:                               ; %.preheader.preheader
                                        ;   in Loop: Header=BB2_2 Depth=1
	v_mov_b32_e32 v1, v26
	s_mov_b32 s19, 0
.LBB2_33:                               ; %.preheader
                                        ;   Parent Loop BB2_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_mov_b32 s20, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e64 s9, v1
	s_cbranch_execz .LBB2_35
; %bb.34:                               ;   in Loop: Header=BB2_33 Depth=2
	v_mad_i64_i32 v[5:6], null, v1, 52, s[2:3]
	v_mov_b32_e32 v10, v4
	global_store_b64 v[5:6], v[9:10], off offset:28
.LBB2_35:                               ;   in Loop: Header=BB2_33 Depth=2
	s_or_b32 exec_lo, exec_lo, s20
	v_add_nc_u32_e32 v3, s19, v27
	s_add_i32 s19, s19, 4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u32 s19, 16
	ds_store_b32 v3, v1
	v_add_nc_u32_e32 v1, 1, v1
	s_cbranch_scc1 .LBB2_33
.LBB2_36:                               ; %Flow371
                                        ;   in Loop: Header=BB2_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v1, v25 offset:48
	ds_load_2addr_b32 v[15:16], v25 offset0:10 offset1:11
	ds_load_2addr_b32 v[13:14], v25 offset0:8 offset1:9
	ds_load_2addr_b32 v[19:20], v25 offset0:6 offset1:7
	ds_load_2addr_b32 v[17:18], v25 offset0:4 offset1:5
	ds_load_2addr_b32 v[30:31], v25 offset0:2 offset1:3
	ds_load_2addr_b32 v[28:29], v25 offset1:1
	v_add_nc_u32_e32 v8, s11, v8
	s_waitcnt lgkmcnt(6)
	global_store_b32 v[11:12], v1, off offset:48
	s_waitcnt lgkmcnt(4)
	global_store_b128 v[11:12], v[13:16], off offset:32
	s_waitcnt lgkmcnt(2)
	global_store_b128 v[11:12], v[17:20], off offset:16
	s_waitcnt lgkmcnt(0)
	global_store_b128 v[11:12], v[28:31], off
	v_cmp_le_i32_e32 vcc_lo, s10, v8
	s_or_b32 s18, vcc_lo, s18
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s18
	s_cbranch_execnz .LBB2_2
.LBB2_37:                               ; %._crit_edge261
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z9constructP4vectPfP4nodeii
		.amdhsa_group_segment_fixed_size 53248
		.amdhsa_private_segment_fixed_size 224
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 1
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 1
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 45
		.amdhsa_next_free_sgpr 25
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_Z9constructP4vectPfP4nodeii, .Lfunc_end2-_Z9constructP4vectPfP4nodeii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 2416
; NumSgprs: 27
; NumVgprs: 45
; ScratchSize: 224
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 53248 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 5
; NumSGPRsForWavesPerEU: 27
; NumVGPRsForWavesPerEU: 45
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 1
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.text
	.protected	_Z9calculateP4vectPfP4nodeS0_if ; -- Begin function _Z9calculateP4vectPfP4nodeS0_if
	.globl	_Z9calculateP4vectPfP4nodeS0_if
	.p2align	8
	.type	_Z9calculateP4vectPfP4nodeS0_if,@function
_Z9calculateP4vectPfP4nodeS0_if:        ; @_Z9calculateP4vectPfP4nodeS0_if
; %bb.0:
	s_clause 0x1
	s_load_b32 s6, s[2:3], 0x34
	s_load_b64 s[12:13], s[2:3], 0x20
	v_and_b32_e32 v1, 0x3ff, v0
	s_add_u32 s4, s2, 40
	s_addc_u32 s5, s3, 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s14, s6, 0xffff
	s_mov_b32 s6, exec_lo
	v_mad_u64_u32 v[4:5], null, s15, s14, v[1:2]
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e64 s12, v4
	s_cbranch_execz .LBB3_25
; %bb.1:                                ; %.lr.ph
	s_load_b64 s[0:1], s[0:1], 0x4
	v_bfe_u32 v2, v0, 10, 10
	v_bfe_u32 v0, v0, 20, 10
	v_or_b32_e64 v13, 16, 4
	v_mov_b32_e32 v15, 0
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s0, s0, 16
	v_mul_u32_u24_e32 v2, s1, v2
	s_mul_i32 s0, s0, s1
	s_load_b32 s1, s[4:5], 0x0
	s_load_b256 s[4:11], s[2:3], 0x0
	v_mul_lo_u32 v1, s0, v1
	s_mov_b32 s2, 0x5e37fa03
	s_mov_b32 s3, 0x3dd25877
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v0, v1, v2, v0
	v_mul_lo_u32 v12, v0, 52
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s1, s1, s14
	s_mov_b32 s14, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_add_nc_u32_e32 v14, 12, v12
.LBB3_2:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB3_3 Depth 2
                                        ;       Child Loop BB3_6 Depth 3
	v_ashrrev_i32_e32 v5, 31, v4
	v_mov_b32_e32 v16, 0
	s_mov_b32 s15, 0
	scratch_store_b32 off, v15, off offset:16
	v_lshlrev_b64 v[0:1], 3, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s4, v0
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
	global_load_b64 v[6:7], v[2:3], off
	v_lshlrev_b64 v[2:3], 2, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v8, vcc_lo, s6, v2
	v_add_co_ci_u32_e32 v9, vcc_lo, s7, v3, vcc_lo
	v_add_co_u32 v10, vcc_lo, s10, v0
	v_add_co_ci_u32_e32 v11, vcc_lo, s11, v1, vcc_lo
.LBB3_3:                                ;   Parent Loop BB3_2 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB3_6 Depth 3
	v_lshl_add_u32 v0, v16, 2, 16
	s_mov_b32 s17, 0
	scratch_load_b32 v17, v0, off
	s_waitcnt vmcnt(0)
	v_mad_i64_i32 v[22:23], null, v17, 52, s[8:9]
	s_clause 0x3
	global_load_b128 v[0:3], v[22:23], off
	global_load_b128 v[18:21], v[22:23], off offset:32
	global_load_b32 v5, v[22:23], off offset:48
	global_load_b128 v[22:25], v[22:23], off offset:16
	s_waitcnt vmcnt(3)
	v_dual_sub_f32 v26, v7, v1 :: v_dual_sub_f32 v27, v6, v0
	s_waitcnt vmcnt(2)
	ds_store_2addr_b32 v12, v18, v19 offset0:8 offset1:9
	ds_store_2addr_b32 v12, v20, v21 offset0:10 offset1:11
	s_waitcnt vmcnt(1)
	ds_store_b32 v12, v5 offset:48
	ds_load_2addr_b32 v[18:19], v12 offset0:11 offset1:12
	ds_load_2addr_b32 v[20:21], v12 offset0:9 offset1:10
	v_mul_f32_e32 v26, v26, v26
	ds_store_2addr_b32 v12, v2, v3 offset0:2 offset1:3
	ds_store_2addr_b32 v12, v0, v1 offset1:1
	s_waitcnt vmcnt(0)
	ds_store_2addr_b32 v12, v24, v25 offset0:6 offset1:7
	ds_store_2addr_b32 v12, v22, v23 offset0:4 offset1:5
	v_fmac_f32_e32 v26, v27, v27
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v27, 0x4f800000, v26
	v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v26
	s_waitcnt lgkmcnt(4)
	v_sub_f32_e32 v18, v18, v20
	v_dual_cndmask_b32 v26, v26, v27 :: v_dual_sub_f32 v19, v19, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sqrt_f32_e32 v27, v26
	v_max_f32_e32 v18, v18, v19
	s_waitcnt_depctr 0xfff
	v_add_nc_u32_e32 v28, -1, v27
	v_add_nc_u32_e32 v5, 1, v27
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v29, -v28, v27, v26
	v_fma_f32 v30, -v5, v27, v26
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_ge_f32_e64 s0, 0, v29
	v_cndmask_b32_e64 v27, v27, v28, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_f32_e64 s0, 0, v30
	v_cndmask_b32_e64 v5, v27, v5, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v27, 0x37800000, v5
	v_cndmask_b32_e32 v5, v5, v27, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v26, 0x260
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v5, v5, v26, vcc_lo
	v_div_scale_f32 v19, null, v5, v5, v18
	v_div_scale_f32 v26, vcc_lo, v18, v5, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v20, v19
	s_waitcnt_depctr 0xfff
	v_fma_f32 v21, -v19, v20, 1.0
	v_fmac_f32_e32 v20, v21, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v21, v26, v20
	v_fma_f32 v27, -v19, v21, v26
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v21, v27, v20
	v_fma_f32 v19, -v19, v21, v26
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_fmas_f32 v19, v19, v20, v21
	v_cmp_lt_f32_e32 vcc_lo, 0, v5
	v_div_fixup_f32 v18, v19, v5, v18
	v_add_nc_u32_e32 v5, -1, v16
                                        ; implicit-def: $vgpr19
                                        ; implicit-def: $vgpr16
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v18, 0x7f7fffff, v18, vcc_lo
	v_cmp_ngt_f32_e32 vcc_lo, s13, v18
                                        ; implicit-def: $vgpr18
	s_and_saveexec_b32 s0, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s16, exec_lo, s0
	s_cbranch_execz .LBB3_17
; %bb.4:                                ;   in Loop: Header=BB3_3 Depth=2
	s_mov_b32 s0, exec_lo
                                        ; implicit-def: $vgpr16
	v_cmpx_gt_i32_e32 0x5555, v17
	s_xor_b32 s0, exec_lo, s0
	s_cbranch_execz .LBB3_12
; %bb.5:                                ; %.preheader.preheader
                                        ;   in Loop: Header=BB3_3 Depth=2
	v_mov_b32_e32 v16, v5
.LBB3_6:                                ; %.preheader
                                        ;   Parent Loop BB3_2 Depth=1
                                        ;     Parent Loop BB3_3 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	v_add_nc_u32_e32 v0, s17, v14
	s_mov_b32 s18, exec_lo
	ds_load_b32 v0, v0
	s_waitcnt lgkmcnt(0)
	v_cmpx_ne_u32_e32 -1, v0
	s_cbranch_execz .LBB3_10
; %bb.7:                                ;   in Loop: Header=BB3_6 Depth=3
	v_mad_i64_i32 v[1:2], null, v0, 52, s[8:9]
	s_mov_b32 s19, exec_lo
	global_load_b64 v[1:2], v[1:2], off offset:28
	s_waitcnt vmcnt(0)
	v_cmpx_le_i32_e64 v1, v2
	s_cbranch_execz .LBB3_9
; %bb.8:                                ;   in Loop: Header=BB3_6 Depth=3
	v_add_nc_u32_e32 v1, 1, v16
	v_lshl_add_u32 v2, v16, 2, v13
	s_delay_alu instid0(VALU_DEP_2)
	v_mov_b32_e32 v16, v1
	scratch_store_b32 v2, v0, off
.LBB3_9:                                ; %Flow
                                        ;   in Loop: Header=BB3_6 Depth=3
	s_or_b32 exec_lo, exec_lo, s19
.LBB3_10:                               ;   in Loop: Header=BB3_6 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s18
	s_add_i32 s17, s17, 4
	s_cmp_eq_u32 s17, 16
	s_cbranch_scc0 .LBB3_6
; %bb.11:                               ; %Flow115
                                        ;   in Loop: Header=BB3_3 Depth=2
                                        ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3
.LBB3_12:                               ; %Flow118
                                        ;   in Loop: Header=BB3_3 Depth=2
	s_or_saveexec_b32 s17, s0
	s_mov_b32 s0, 0
                                        ; implicit-def: $vgpr18
                                        ; implicit-def: $vgpr19
	s_xor_b32 exec_lo, exec_lo, s17
	s_cbranch_execz .LBB3_16
; %bb.13:                               ;   in Loop: Header=BB3_3 Depth=2
	global_load_b32 v3, v[8:9], off
	v_dual_sub_f32 v1, v1, v7 :: v_dual_sub_f32 v0, v0, v6
	s_mov_b32 s18, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v2, v1, v1
	v_fmac_f32_e32 v2, v0, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v16, 0x4f800000, v2
	v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v2
	v_cndmask_b32_e32 v17, v2, v16, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_sqrt_f32_e32 v16, v17
	s_waitcnt_depctr 0xfff
	v_add_nc_u32_e32 v18, -1, v16
	v_add_nc_u32_e32 v19, 1, v16
	v_fma_f32 v20, -v18, v16, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v21, -v19, v16, v17
	v_cmp_ge_f32_e64 s0, 0, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v16, v16, v18, s0
	v_cmp_lt_f32_e64 s0, 0, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v18, v16, v19, s0
	ds_load_b32 v16, v12 offset:8
	v_mul_f32_e32 v19, 0x37800000, v18
	v_cndmask_b32_e32 v18, v18, v19, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v17, 0x260
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v17, v18, v17, vcc_lo
	v_cmpx_lt_f32_e32 0, v17
	s_cbranch_execz .LBB3_15
; %bb.14:                               ;   in Loop: Header=BB3_3 Depth=2
	v_div_scale_f32 v18, null, v17, v17, v1
	v_div_scale_f32 v19, null, v17, v17, v0
	v_div_scale_f32 v24, vcc_lo, v1, v17, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rcp_f32_e32 v20, v18
	v_rcp_f32_e32 v21, v19
	s_waitcnt_depctr 0xfff
	v_fma_f32 v22, -v18, v20, 1.0
	v_fma_f32 v23, -v19, v21, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_fmac_f32 v20, v22, v20 :: v_dual_fmac_f32 v21, v23, v21
	v_div_scale_f32 v22, s0, v0, v17, v0
	v_mul_f32_e32 v23, v24, v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v25, v22, v21
	v_fma_f32 v26, -v18, v23, v24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v27, -v19, v25, v22
	v_fmac_f32_e32 v23, v26, v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v25, v27, v21
	v_fma_f32 v18, -v18, v23, v24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v19, -v19, v25, v22
	v_div_fmas_f32 v18, v18, v20, v23
	s_mov_b32 vcc_lo, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fmas_f32 v19, v19, v21, v25
	v_div_fixup_f32 v1, v18, v17, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_div_fixup_f32 v0, v19, v17, v0
.LBB3_15:                               ; %_Z7gravity4vectS_ff.exit76
                                        ;   in Loop: Header=BB3_3 Depth=2
	s_or_b32 exec_lo, exec_lo, s18
	s_waitcnt lgkmcnt(0)
	v_cvt_f64_f32_e32 v[16:17], v16
	s_waitcnt vmcnt(0)
	v_cvt_f64_f32_e32 v[18:19], v3
	v_cmp_lt_f32_e32 vcc_lo, 0, v2
	s_mov_b32 s0, exec_lo
	v_cndmask_b32_e32 v2, 1.0, v2, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[16:17], v[16:17], s[2:3]
	v_mul_f64 v[16:17], v[16:17], v[18:19]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f32_f64_e32 v3, v[16:17]
	v_div_scale_f32 v16, null, v2, v2, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v17, v16
	s_waitcnt_depctr 0xfff
	v_fma_f32 v18, -v16, v17, 1.0
	v_fmac_f32_e32 v17, v18, v17
	v_div_scale_f32 v19, vcc_lo, v3, v2, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v18, v19, v17
	v_fma_f32 v20, -v16, v18, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v18, v20, v17
	v_fma_f32 v16, -v16, v18, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v16, v16, v17, v18
	v_div_fixup_f32 v2, v16, v2, v3
                                        ; implicit-def: $vgpr16
	s_delay_alu instid0(VALU_DEP_1)
	v_mul_f32_e32 v19, v2, v0
	v_mul_f32_e32 v18, v2, v1
.LBB3_16:                               ; %Flow119
                                        ;   in Loop: Header=BB3_3 Depth=2
	s_or_b32 exec_lo, exec_lo, s17
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s17, s0, exec_lo
                                        ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3
.LBB3_17:                               ; %Flow117
                                        ;   in Loop: Header=BB3_3 Depth=2
	s_and_not1_saveexec_b32 s16, s16
	s_cbranch_execz .LBB3_21
; %bb.18:                               ;   in Loop: Header=BB3_3 Depth=2
	global_load_b32 v3, v[8:9], off
	v_dual_sub_f32 v1, v1, v7 :: v_dual_sub_f32 v0, v0, v6
	s_mov_b32 s18, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v2, v1, v1
	v_fmac_f32_e32 v2, v0, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v16, 0x4f800000, v2
	v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v2
	v_cndmask_b32_e32 v17, v2, v16, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_sqrt_f32_e32 v16, v17
	s_waitcnt_depctr 0xfff
	v_add_nc_u32_e32 v18, -1, v16
	v_add_nc_u32_e32 v19, 1, v16
	v_fma_f32 v20, -v18, v16, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v21, -v19, v16, v17
	v_cmp_ge_f32_e64 s0, 0, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v16, v16, v18, s0
	v_cmp_lt_f32_e64 s0, 0, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v18, v16, v19, s0
	ds_load_b32 v16, v12 offset:8
	v_mul_f32_e32 v19, 0x37800000, v18
	v_cndmask_b32_e32 v18, v18, v19, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v17, 0x260
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v17, v18, v17, vcc_lo
	v_cmpx_lt_f32_e32 0, v17
	s_cbranch_execz .LBB3_20
; %bb.19:                               ;   in Loop: Header=BB3_3 Depth=2
	v_div_scale_f32 v18, null, v17, v17, v1
	v_div_scale_f32 v19, null, v17, v17, v0
	v_div_scale_f32 v24, vcc_lo, v1, v17, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rcp_f32_e32 v20, v18
	v_rcp_f32_e32 v21, v19
	s_waitcnt_depctr 0xfff
	v_fma_f32 v22, -v18, v20, 1.0
	v_fma_f32 v23, -v19, v21, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_fmac_f32 v20, v22, v20 :: v_dual_fmac_f32 v21, v23, v21
	v_div_scale_f32 v22, s0, v0, v17, v0
	v_mul_f32_e32 v23, v24, v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v25, v22, v21
	v_fma_f32 v26, -v18, v23, v24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v27, -v19, v25, v22
	v_fmac_f32_e32 v23, v26, v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v25, v27, v21
	v_fma_f32 v18, -v18, v23, v24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v19, -v19, v25, v22
	v_div_fmas_f32 v18, v18, v20, v23
	s_mov_b32 vcc_lo, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fmas_f32 v19, v19, v21, v25
	v_div_fixup_f32 v1, v18, v17, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_div_fixup_f32 v0, v19, v17, v0
.LBB3_20:                               ; %_Z7gravity4vectS_ff.exit
                                        ;   in Loop: Header=BB3_3 Depth=2
	s_or_b32 exec_lo, exec_lo, s18
	s_waitcnt lgkmcnt(0)
	v_cvt_f64_f32_e32 v[16:17], v16
	s_waitcnt vmcnt(0)
	v_cvt_f64_f32_e32 v[18:19], v3
	v_cmp_lt_f32_e32 vcc_lo, 0, v2
	s_or_b32 s17, s17, exec_lo
	v_cndmask_b32_e32 v2, 1.0, v2, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[16:17], v[16:17], s[2:3]
	v_mul_f64 v[16:17], v[16:17], v[18:19]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f32_f64_e32 v3, v[16:17]
	v_div_scale_f32 v16, null, v2, v2, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v17, v16
	s_waitcnt_depctr 0xfff
	v_fma_f32 v18, -v16, v17, 1.0
	v_fmac_f32_e32 v17, v18, v17
	v_div_scale_f32 v19, vcc_lo, v3, v2, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v18, v19, v17
	v_fma_f32 v20, -v16, v18, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v18, v20, v17
	v_fma_f32 v16, -v16, v18, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v16, v16, v17, v18
	v_div_fixup_f32 v2, v16, v2, v3
                                        ; implicit-def: $vgpr16
	s_delay_alu instid0(VALU_DEP_1)
	v_mul_f32_e32 v19, v2, v0
	v_mul_f32_e32 v18, v2, v1
.LBB3_21:                               ; %Flow120
                                        ;   in Loop: Header=BB3_3 Depth=2
	s_or_b32 exec_lo, exec_lo, s16
	s_and_saveexec_b32 s0, s17
	s_cbranch_execz .LBB3_23
; %bb.22:                               ; %.loopexit.sink.split
                                        ;   in Loop: Header=BB3_3 Depth=2
	global_load_b64 v[0:1], v[10:11], off
	v_mov_b32_e32 v16, v5
	s_waitcnt vmcnt(0)
	v_dual_add_f32 v0, v19, v0 :: v_dual_add_f32 v1, v18, v1
	global_store_b64 v[10:11], v[0:1], off
.LBB3_23:                               ; %.loopexit
                                        ;   in Loop: Header=BB3_3 Depth=2
	s_or_b32 exec_lo, exec_lo, s0
	v_cmp_gt_i32_e32 vcc_lo, 0, v16
	s_or_b32 s15, vcc_lo, s15
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s15
	s_cbranch_execnz .LBB3_3
; %bb.24:                               ;   in Loop: Header=BB3_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s15
	v_add_nc_u32_e32 v4, s1, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_le_i32_e32 vcc_lo, s12, v4
	s_or_b32 s14, vcc_lo, s14
	s_and_not1_b32 exec_lo, exec_lo, s14
	s_cbranch_execnz .LBB3_2
.LBB3_25:                               ; %._crit_edge
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z9calculateP4vectPfP4nodeS0_if
		.amdhsa_group_segment_fixed_size 53248
		.amdhsa_private_segment_fixed_size 160
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 1
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 1
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 31
		.amdhsa_next_free_sgpr 20
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end3:
	.size	_Z9calculateP4vectPfP4nodeS0_if, .Lfunc_end3-_Z9calculateP4vectPfP4nodeS0_if
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 2096
; NumSgprs: 22
; NumVgprs: 31
; ScratchSize: 160
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 53248 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 3
; NumSGPRsForWavesPerEU: 22
; NumVGPRsForWavesPerEU: 31
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 1
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 512
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z10findMinMaxP4vectS0_S0_i
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z10findMinMaxP4vectS0_S0_i.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     11
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         44
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         52
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         54
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         56
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         58
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         60
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         62
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         104
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 512
    .kernarg_segment_align: 8
    .kernarg_segment_size: 296
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z11findMMinMaxP4vectS0_S0_S0_i
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z11findMMinMaxP4vectS0_S0_S0_i.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     11
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
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    .group_segment_fixed_size: 53248
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
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      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z9constructP4vectPfP4nodeii
    .private_segment_fixed_size: 224
    .sgpr_count:     27
    .sgpr_spill_count: 0
    .symbol:         _Z9constructP4vectPfP4nodeii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     45
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
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        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
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        .size:           8
        .value_kind:     global_buffer
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        .value_kind:     hidden_block_count_x
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    .language:       OpenCL C
    .language_version:
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    .name:           _Z9calculateP4vectPfP4nodeS0_if
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    .sgpr_spill_count: 0
    .symbol:         _Z9calculateP4vectPfP4nodeS0_if.kd
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amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
