#include "includes.h"
__global__ void idwt_per_X_1(float *d_dst, float *src_A, float *src_D, int rows, int cols, int next_cols, int filt_len, int halo) {

extern __shared__ float s_Data[];

//Offset to the left halo edge
const int baseX = ((blockIdx.x * I_X_RESULT_STEPS) - halo) * I_X_BLOCKDIM_X + threadIdx.x; // even if the last pixel of cols+l2-1 takes a new block, rows can be maintained
const int baseY = blockIdx.y * I_X_BLOCKDIM_Y + threadIdx.y;

const int baseX1 = blockIdx.x * I_X_RESULT_STEPS * 2 * I_X_BLOCKDIM_X + 2 * threadIdx.x;

if (baseY < rows) {

src_A += baseY * cols + baseX;
src_D += baseY * cols + baseX;
d_dst += baseY * next_cols + baseX1;//To compensate the halo

int l2 = filt_len / 2;

//Loading data to shared memory
#pragma unroll
for (int i = 0; i < halo; i++)
{
s_Data[(threadIdx.y*(I_X_RESULT_STEPS + 2 * halo)*I_X_BLOCKDIM_X) + threadIdx.x + i * I_X_BLOCKDIM_X] = (baseX + i * I_X_BLOCKDIM_X >= 0) ? src_A[i * I_X_BLOCKDIM_X] : src_A[i * I_X_BLOCKDIM_X + cols];
s_Data[((threadIdx.y + I_X_BLOCKDIM_Y)*(I_X_RESULT_STEPS + 2 * halo)*I_X_BLOCKDIM_X) + threadIdx.x + i * I_X_BLOCKDIM_X] = (baseX + i * I_X_BLOCKDIM_X >= 0) ? src_D[i * I_X_BLOCKDIM_X] : src_D[i * I_X_BLOCKDIM_X + cols];
}

// main data and Load right halo
#pragma unroll

for (int i = halo; i < halo + I_X_RESULT_STEPS + halo; i++)
{

s_Data[(threadIdx.y*(I_X_RESULT_STEPS + 2 * halo)*I_X_BLOCKDIM_X) + threadIdx.x + i * I_X_BLOCKDIM_X] = ((baseX + i * I_X_BLOCKDIM_X) < cols) ? src_A[i * I_X_BLOCKDIM_X] : src_A[i * I_X_BLOCKDIM_X - cols];
s_Data[((threadIdx.y + I_X_BLOCKDIM_Y)*(I_X_RESULT_STEPS + 2 * halo)*I_X_BLOCKDIM_X) + threadIdx.x + i * I_X_BLOCKDIM_X] = ((baseX + i * I_X_BLOCKDIM_X) < cols) ? src_D[i * I_X_BLOCKDIM_X] : src_D[i * I_X_BLOCKDIM_X - cols];

}

//Compute and store results
__syncthreads();

#pragma unroll
for (int i = halo; i < halo + I_X_RESULT_STEPS; i++)
{
int pos_x = (baseX1 + 2 * (i - halo) * I_X_BLOCKDIM_X);

if ((pos_x + 1) < (2 * cols + filt_len - 2)) {

float temp_1 = 0, temp_2 = 0;

for (int l = 0; l < l2; ++l)
{
int t = 2 * l;

temp_1 += c_lpr[t] * s_Data[(threadIdx.y*(I_X_RESULT_STEPS + 2 * halo)*I_X_BLOCKDIM_X) + threadIdx.x + i * I_X_BLOCKDIM_X - l]
+ c_hpr[t] * s_Data[((threadIdx.y + I_X_BLOCKDIM_Y)*(I_X_RESULT_STEPS + 2 * halo)*I_X_BLOCKDIM_X) + threadIdx.x + i * I_X_BLOCKDIM_X - l];
temp_2 += c_lpr[t + 1] * s_Data[(threadIdx.y*(I_X_RESULT_STEPS + 2 * halo)*I_X_BLOCKDIM_X) + threadIdx.x + i * I_X_BLOCKDIM_X - l]
+ c_hpr[t + 1] * s_Data[((threadIdx.y + I_X_BLOCKDIM_Y)*(I_X_RESULT_STEPS + 2 * halo)*I_X_BLOCKDIM_X) + threadIdx.x + i * I_X_BLOCKDIM_X - l];
}

if ((pos_x >= l2 - 1) && (pos_x < (next_cols + l2 - 1))) d_dst[2 * (i - halo) * I_X_BLOCKDIM_X - l2 + 1] = temp_1;
if ((pos_x + 1 >= l2 - 1) && (pos_x + 1 < (next_cols + l2 - 1))) d_dst[2 * (i - halo) * I_X_BLOCKDIM_X - l2 + 2] = temp_2;
}

}
}
}
	.file	"tmpxft_00244a60_00000000-6_idwt_per_X_1.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2010:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2010:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z41__device_stub__Z12idwt_per_X_1PfS_S_iiiiiPfS_S_iiiii
	.type	_Z41__device_stub__Z12idwt_per_X_1PfS_S_iiiiiPfS_S_iiiii, @function
_Z41__device_stub__Z12idwt_per_X_1PfS_S_iiiiiPfS_S_iiiii:
.LFB2032:
	.cfi_startproc
	endbr64
	subq	$200, %rsp
	.cfi_def_cfa_offset 208
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	56(%rsp), %rdx
	movl	%ecx, 20(%rsp)
	leaq	64(%rsp), %rcx
	movl	%r8d, 16(%rsp)
	movl	%r9d, 12(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 184(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	208(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	216(%rsp), %rax
	movq	%rax, 176(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	64(%rsp)
	.cfi_def_cfa_offset 216
	leaq	_Z12idwt_per_X_1PfS_S_iiiii(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 224
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 216
	popq	%rdx
	.cfi_def_cfa_offset 208
.L2:
	movq	184(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$200, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2032:
	.size	_Z41__device_stub__Z12idwt_per_X_1PfS_S_iiiiiPfS_S_iiiii, .-_Z41__device_stub__Z12idwt_per_X_1PfS_S_iiiiiPfS_S_iiiii
	.globl	_Z12idwt_per_X_1PfS_S_iiiii
	.type	_Z12idwt_per_X_1PfS_S_iiiii, @function
_Z12idwt_per_X_1PfS_S_iiiii:
.LFB2033:
	.cfi_startproc
	endbr64
	jmp	_Z41__device_stub__Z12idwt_per_X_1PfS_S_iiiiiPfS_S_iiiii
	.cfi_endproc
.LFE2033:
	.size	_Z12idwt_per_X_1PfS_S_iiiii, .-_Z12idwt_per_X_1PfS_S_iiiii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z12idwt_per_X_1PfS_S_iiiii"
.LC1:
	.string	"c_lpr"
.LC2:
	.string	"c_hpr"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2035:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z12idwt_per_X_1PfS_S_iiiii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC1(%rip), %rdx
	movl	$8, %r9d
	leaq	_ZL5c_lpr(%rip), %rsi
	pushq	$1
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC2(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL5c_hpr(%rip), %rsi
	call	__cudaRegisterVar@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2035:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.local	_ZL5c_hpr
	.comm	_ZL5c_hpr,8,8
	.local	_ZL5c_lpr
	.comm	_ZL5c_lpr,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void idwt_per_X_1(float *d_dst, float *src_A, float *src_D, int rows, int cols, int next_cols, int filt_len, int halo) {

extern __shared__ float s_Data[];

//Offset to the left halo edge
const int baseX = ((blockIdx.x * I_X_RESULT_STEPS) - halo) * I_X_BLOCKDIM_X + threadIdx.x; // even if the last pixel of cols+l2-1 takes a new block, rows can be maintained
const int baseY = blockIdx.y * I_X_BLOCKDIM_Y + threadIdx.y;

const int baseX1 = blockIdx.x * I_X_RESULT_STEPS * 2 * I_X_BLOCKDIM_X + 2 * threadIdx.x;

if (baseY < rows) {

src_A += baseY * cols + baseX;
src_D += baseY * cols + baseX;
d_dst += baseY * next_cols + baseX1;//To compensate the halo

int l2 = filt_len / 2;

//Loading data to shared memory
#pragma unroll
for (int i = 0; i < halo; i++)
{
s_Data[(threadIdx.y*(I_X_RESULT_STEPS + 2 * halo)*I_X_BLOCKDIM_X) + threadIdx.x + i * I_X_BLOCKDIM_X] = (baseX + i * I_X_BLOCKDIM_X >= 0) ? src_A[i * I_X_BLOCKDIM_X] : src_A[i * I_X_BLOCKDIM_X + cols];
s_Data[((threadIdx.y + I_X_BLOCKDIM_Y)*(I_X_RESULT_STEPS + 2 * halo)*I_X_BLOCKDIM_X) + threadIdx.x + i * I_X_BLOCKDIM_X] = (baseX + i * I_X_BLOCKDIM_X >= 0) ? src_D[i * I_X_BLOCKDIM_X] : src_D[i * I_X_BLOCKDIM_X + cols];
}

// main data and Load right halo
#pragma unroll

for (int i = halo; i < halo + I_X_RESULT_STEPS + halo; i++)
{

s_Data[(threadIdx.y*(I_X_RESULT_STEPS + 2 * halo)*I_X_BLOCKDIM_X) + threadIdx.x + i * I_X_BLOCKDIM_X] = ((baseX + i * I_X_BLOCKDIM_X) < cols) ? src_A[i * I_X_BLOCKDIM_X] : src_A[i * I_X_BLOCKDIM_X - cols];
s_Data[((threadIdx.y + I_X_BLOCKDIM_Y)*(I_X_RESULT_STEPS + 2 * halo)*I_X_BLOCKDIM_X) + threadIdx.x + i * I_X_BLOCKDIM_X] = ((baseX + i * I_X_BLOCKDIM_X) < cols) ? src_D[i * I_X_BLOCKDIM_X] : src_D[i * I_X_BLOCKDIM_X - cols];

}

//Compute and store results
__syncthreads();

#pragma unroll
for (int i = halo; i < halo + I_X_RESULT_STEPS; i++)
{
int pos_x = (baseX1 + 2 * (i - halo) * I_X_BLOCKDIM_X);

if ((pos_x + 1) < (2 * cols + filt_len - 2)) {

float temp_1 = 0, temp_2 = 0;

for (int l = 0; l < l2; ++l)
{
int t = 2 * l;

temp_1 += c_lpr[t] * s_Data[(threadIdx.y*(I_X_RESULT_STEPS + 2 * halo)*I_X_BLOCKDIM_X) + threadIdx.x + i * I_X_BLOCKDIM_X - l]
+ c_hpr[t] * s_Data[((threadIdx.y + I_X_BLOCKDIM_Y)*(I_X_RESULT_STEPS + 2 * halo)*I_X_BLOCKDIM_X) + threadIdx.x + i * I_X_BLOCKDIM_X - l];
temp_2 += c_lpr[t + 1] * s_Data[(threadIdx.y*(I_X_RESULT_STEPS + 2 * halo)*I_X_BLOCKDIM_X) + threadIdx.x + i * I_X_BLOCKDIM_X - l]
+ c_hpr[t + 1] * s_Data[((threadIdx.y + I_X_BLOCKDIM_Y)*(I_X_RESULT_STEPS + 2 * halo)*I_X_BLOCKDIM_X) + threadIdx.x + i * I_X_BLOCKDIM_X - l];
}

if ((pos_x >= l2 - 1) && (pos_x < (next_cols + l2 - 1))) d_dst[2 * (i - halo) * I_X_BLOCKDIM_X - l2 + 1] = temp_1;
if ((pos_x + 1 >= l2 - 1) && (pos_x + 1 < (next_cols + l2 - 1))) d_dst[2 * (i - halo) * I_X_BLOCKDIM_X - l2 + 2] = temp_2;
}

}
}
}
	.text
	.file	"idwt_per_X_1.hip"
	.globl	_Z27__device_stub__idwt_per_X_1PfS_S_iiiii # -- Begin function _Z27__device_stub__idwt_per_X_1PfS_S_iiiii
	.type	_Z27__device_stub__idwt_per_X_1PfS_S_iiiii,@function
_Z27__device_stub__idwt_per_X_1PfS_S_iiiii: # @_Z27__device_stub__idwt_per_X_1PfS_S_iiiii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	20(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	16(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	12(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	216(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z12idwt_per_X_1PfS_S_iiiii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z27__device_stub__idwt_per_X_1PfS_S_iiiii, .Lfunc_end0-_Z27__device_stub__idwt_per_X_1PfS_S_iiiii
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	subq	$32, %rsp
	.cfi_adjust_cfa_offset 32
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z12idwt_per_X_1PfS_S_iiiii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	addq	$32, %rsp
	.cfi_adjust_cfa_offset -32
	movl	$c_lpr, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$c_hpr, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$__hip_module_dtor, %edi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	c_lpr,@object                   # @c_lpr
	.local	c_lpr
	.comm	c_lpr,8,8
	.type	c_hpr,@object                   # @c_hpr
	.local	c_hpr
	.comm	c_hpr,8,8
	.type	_Z12idwt_per_X_1PfS_S_iiiii,@object # @_Z12idwt_per_X_1PfS_S_iiiii
	.section	.rodata,"a",@progbits
	.globl	_Z12idwt_per_X_1PfS_S_iiiii
	.p2align	3, 0x0
_Z12idwt_per_X_1PfS_S_iiiii:
	.quad	_Z27__device_stub__idwt_per_X_1PfS_S_iiiii
	.size	_Z12idwt_per_X_1PfS_S_iiiii, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z12idwt_per_X_1PfS_S_iiiii"
	.size	.L__unnamed_1, 28

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"c_lpr"
	.size	.L__unnamed_2, 6

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"c_hpr"
	.size	.L__unnamed_3, 6

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z27__device_stub__idwt_per_X_1PfS_S_iiiii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym c_lpr
	.addrsig_sym c_hpr
	.addrsig_sym _Z12idwt_per_X_1PfS_S_iiiii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z12idwt_per_X_1PfS_S_iiiii ; -- Begin function _Z12idwt_per_X_1PfS_S_iiiii
	.globl	_Z12idwt_per_X_1PfS_S_iiiii
	.p2align	8
	.type	_Z12idwt_per_X_1PfS_S_iiiii,@function
_Z12idwt_per_X_1PfS_S_iiiii:            ; @_Z12idwt_per_X_1PfS_S_iiiii
; %bb.0:
	s_load_b128 s[4:7], s[0:1], 0x18
	v_bfe_u32 v2, v0, 10, 10
	s_mov_b32 s2, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshl_add_u32 v4, s15, 2, v2
	s_waitcnt lgkmcnt(0)
	v_cmpx_gt_i32_e64 s4, v4
	s_cbranch_execz .LBB0_17
; %bb.1:
	s_clause 0x1
	s_load_b32 s12, s[0:1], 0x28
	s_load_b128 s[8:11], s[0:1], 0x0
	v_and_b32_e32 v1, 0x3ff, v0
	s_mul_i32 s2, s14, 3
	s_load_b64 s[0:1], s[0:1], 0x10
	s_waitcnt lgkmcnt(0)
	s_sub_i32 s2, s2, s12
	s_cmp_lt_i32 s12, 1
	v_lshl_add_u32 v0, s2, 5, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[5:6], null, v4, s5, v[0:1]
	v_ashrrev_i32_e32 v6, 31, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[8:9], 2, v[5:6]
	v_lshlrev_b32_e32 v5, 2, v1
	v_add_co_u32 v6, vcc_lo, s10, v8
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v7, vcc_lo, s11, v9, vcc_lo
	v_add_co_u32 v8, vcc_lo, s0, v8
	v_add_co_ci_u32_e32 v9, vcc_lo, s1, v9, vcc_lo
	s_cbranch_scc1 .LBB0_4
; %bb.2:                                ; %.lr.ph
	s_lshl_b32 s0, s12, 1
	s_lshl_b32 s2, s12, 10
	s_add_i32 s0, s0, 3
	s_mov_b32 s3, s5
	v_mul_lo_u32 v3, v2, s0
	s_mov_b64 s[0:1], 0
	s_mov_b32 s4, s12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b32_e32 v3, 7, v3
	v_add3_u32 v3, v3, v5, 0
.LBB0_3:                                ; =>This Inner Loop Header: Depth=1
	s_add_i32 s10, s3, s0
	s_add_i32 s4, s4, -1
	s_ashr_i32 s11, s10, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_mov_b32 v11, s11 :: v_dual_add_nc_u32 v10, s0, v0
	v_mov_b32_e32 v12, s10
	v_cmp_gt_i32_e32 vcc_lo, 0, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v11, s1, v11, vcc_lo
	v_cndmask_b32_e32 v10, s0, v12, vcc_lo
	s_add_u32 s0, s0, 32
	s_addc_u32 s1, s1, 0
	s_cmp_eq_u32 s4, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[10:11], 2, v[10:11]
	v_add_co_u32 v12, vcc_lo, v6, v10
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v13, vcc_lo, v7, v11, vcc_lo
	v_add_co_u32 v10, vcc_lo, v8, v10
	v_add_co_ci_u32_e32 v11, vcc_lo, v9, v11, vcc_lo
	global_load_b32 v12, v[12:13], off
	global_load_b32 v10, v[10:11], off
	v_add_nc_u32_e32 v11, s2, v3
	s_waitcnt vmcnt(1)
	ds_store_b32 v3, v12
	s_waitcnt vmcnt(0)
	ds_store_b32 v11, v10 offset:1536
	v_add_nc_u32_e32 v3, 0x80, v3
	s_cbranch_scc0 .LBB0_3
.LBB0_4:                                ; %.preheader135
	s_add_i32 s10, s12, 3
	s_mul_i32 s0, s12, 0x480
	s_add_i32 s1, s10, s12
	s_cmp_lt_i32 s12, -2
	v_mul_lo_u32 v0, v2, s1
	s_delay_alu instid0(VALU_DEP_1)
	v_lshlrev_b32_e32 v11, 5, v0
	v_lshlrev_b32_e32 v10, 7, v0
	s_cbranch_scc1 .LBB0_7
; %bb.5:                                ; %.lr.ph138.preheader
	s_lshl_b32 s2, s12, 5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_add3_u32 v0, v10, s0, v5
	v_add3_u32 v12, v1, v11, s2
	v_mad_u64_u32 v[2:3], null, 0x60, s14, v[1:2]
	s_mov_b32 s3, s12
	v_add3_u32 v0, v0, 0, 0x600
	s_delay_alu instid0(VALU_DEP_3)
	v_lshl_add_u32 v3, v12, 2, 0
.LBB0_6:                                ; %.lr.ph138
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_cmp_le_i32_e32 vcc_lo, s5, v2
	v_add_nc_u32_e32 v2, 32, v2
	s_add_i32 s3, s3, 1
	v_cndmask_b32_e64 v12, 0, s5, vcc_lo
	v_sub_nc_u32_e32 v12, s2, v12
	s_add_i32 s2, s2, 32
	s_cmp_ge_i32 s3, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v13, 31, v12
	v_lshlrev_b64 v[12:13], 2, v[12:13]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v14, vcc_lo, v6, v12
	v_add_co_ci_u32_e32 v15, vcc_lo, v7, v13, vcc_lo
	v_add_co_u32 v12, vcc_lo, v8, v12
	v_add_co_ci_u32_e32 v13, vcc_lo, v9, v13, vcc_lo
	global_load_b32 v14, v[14:15], off
	global_load_b32 v12, v[12:13], off
	s_waitcnt vmcnt(1)
	ds_store_b32 v3, v14
	s_waitcnt vmcnt(0)
	ds_store_b32 v0, v12
	v_add_nc_u32_e32 v0, 0x80, v0
	v_add_nc_u32_e32 v3, 0x80, v3
	s_cbranch_scc0 .LBB0_6
.LBB0_7:                                ; %._crit_edge
	s_mulk_i32 s14, 0xc0
	s_lshr_b32 s1, s7, 31
	v_lshl_add_u32 v0, v1, 1, s14
	s_lshl_b32 s2, s5, 1
	s_add_i32 s1, s7, s1
	s_add_i32 s13, s2, s7
	s_ashr_i32 s11, s1, 1
	v_mad_u64_u32 v[2:3], null, v4, s6, v[0:1]
	s_add_i32 s13, s13, -2
	s_cmp_gt_i32 s7, 1
	v_add3_u32 v8, v10, s0, v5
	s_cselect_b32 s14, -1, 0
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, c_lpr@rel32@lo+4
	s_addc_u32 s3, s3, c_lpr@rel32@hi+12
	s_getpc_b64 s[4:5]
	s_add_u32 s4, s4, c_hpr@rel32@lo+4
	s_addc_u32 s5, s5, c_hpr@rel32@hi+12
	v_ashrrev_i32_e32 v3, 31, v2
	s_load_b64 s[2:3], s[2:3], 0x0
	s_load_b64 s[4:5], s[4:5], 0x0
	s_lshl_b32 s1, s12, 5
	s_add_i32 s15, s11, -1
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	v_add3_u32 v7, v1, v11, s1
	s_add_i32 s16, s15, s6
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_add_co_u32 v4, vcc_lo, s8, v2
	v_add_co_ci_u32_e32 v6, vcc_lo, s9, v3, vcc_lo
	v_lshl_add_u32 v5, v7, 2, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v1, vcc_lo, v4, 4
	v_add_co_ci_u32_e32 v2, vcc_lo, 0, v6, vcc_lo
	v_add_co_u32 v3, vcc_lo, v4, 8
	v_add_co_ci_u32_e32 v4, vcc_lo, 0, v6, vcc_lo
	v_add3_u32 v6, v8, 0, 0x600
	s_add_u32 s2, s2, 4
	v_mov_b32_e32 v7, 0
	s_addc_u32 s3, s3, 0
	s_add_u32 s4, s4, 4
	s_addc_u32 s5, s5, 0
	s_mov_b32 s8, s12
.LBB0_8:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_11 Depth 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_sub_i32 s0, s8, s12
	s_mov_b32 s9, exec_lo
	s_lshl_b32 s17, s0, 6
	v_add_nc_u32_e32 v10, s17, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or_b32_e32 v9, 1, v10
	v_cmpx_gt_i32_e64 s13, v9
	s_cbranch_execz .LBB0_16
; %bb.9:                                ; %.preheader
                                        ;   in Loop: Header=BB0_8 Depth=1
	v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v11, 0
	s_and_not1_b32 vcc_lo, exec_lo, s14
	s_cbranch_vccnz .LBB0_12
; %bb.10:                               ; %.lr.ph143
                                        ;   in Loop: Header=BB0_8 Depth=1
	v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v13, v5
	v_dual_mov_b32 v12, v6 :: v_dual_mov_b32 v11, 0
	s_mov_b64 s[0:1], s[4:5]
	s_mov_b64 s[6:7], s[2:3]
	s_mov_b32 s18, s11
.LBB0_11:                               ;   Parent Loop BB0_8 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_clause 0x1
	global_load_b64 v[14:15], v7, s[0:1] offset:-4
	global_load_b64 v[16:17], v7, s[6:7] offset:-4
	ds_load_b32 v18, v12
	ds_load_b32 v19, v13
	s_add_i32 s18, s18, -1
	s_add_u32 s6, s6, 8
	s_addc_u32 s7, s7, 0
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	s_cmp_eq_u32 s18, 0
	v_add_nc_u32_e32 v13, -4, v13
	v_add_nc_u32_e32 v12, -4, v12
	s_waitcnt vmcnt(1) lgkmcnt(1)
	v_mul_f32_e32 v14, v14, v18
	v_mul_f32_e32 v15, v18, v15
	s_waitcnt vmcnt(0) lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v14, v16, v19 :: v_dual_fmac_f32 v15, v19, v17
	v_dual_add_f32 v11, v11, v14 :: v_dual_add_f32 v8, v8, v15
	s_cbranch_scc0 .LBB0_11
.LBB0_12:                               ; %Flow232
                                        ;   in Loop: Header=BB0_8 Depth=1
	v_cmp_le_i32_e32 vcc_lo, s15, v10
	v_cmp_gt_i32_e64 s0, s16, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s1, vcc_lo, s0
	s_and_saveexec_b32 s0, s1
	s_cbranch_execz .LBB0_14
; %bb.13:                               ;   in Loop: Header=BB0_8 Depth=1
	s_sub_i32 s6, s17, s11
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_ashr_i32 s7, s6, 31
	s_lshl_b64 s[6:7], s[6:7], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	v_add_co_u32 v12, vcc_lo, v1, s6
	v_add_co_ci_u32_e32 v13, vcc_lo, s7, v2, vcc_lo
	global_store_b32 v[12:13], v11, off
.LBB0_14:                               ;   in Loop: Header=BB0_8 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	v_cmp_le_i32_e32 vcc_lo, s15, v9
	v_cmp_gt_i32_e64 s0, s16, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, vcc_lo, s0
	s_and_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB0_16
; %bb.15:                               ;   in Loop: Header=BB0_8 Depth=1
	s_sub_i32 s0, s17, s11
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_ashr_i32 s1, s0, 31
	s_lshl_b64 s[0:1], s[0:1], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	v_add_co_u32 v9, vcc_lo, v3, s0
	v_add_co_ci_u32_e32 v10, vcc_lo, s1, v4, vcc_lo
	global_store_b32 v[9:10], v8, off
.LBB0_16:                               ; %Flow233
                                        ;   in Loop: Header=BB0_8 Depth=1
	s_or_b32 exec_lo, exec_lo, s9
	v_add_nc_u32_e32 v5, 0x80, v5
	v_add_nc_u32_e32 v6, 0x80, v6
	s_add_i32 s8, s8, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lt_i32 s8, s10
	s_cbranch_scc1 .LBB0_8
.LBB0_17:                               ; %.loopexit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z12idwt_per_X_1PfS_S_iiiii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 44
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 20
		.amdhsa_next_free_sgpr 19
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z12idwt_per_X_1PfS_S_iiiii, .Lfunc_end0-_Z12idwt_per_X_1PfS_S_iiiii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1248
; NumSgprs: 21
; NumVgprs: 20
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 21
; NumVGPRsForWavesPerEU: 20
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.protected	c_lpr                   ; @c_lpr
	.type	c_lpr,@object
	.section	.bss,"aw",@nobits
	.globl	c_lpr
	.p2align	3, 0x0
c_lpr:
	.quad	0
	.size	c_lpr, 8

	.protected	c_hpr                   ; @c_hpr
	.type	c_hpr,@object
	.globl	c_hpr
	.p2align	3, 0x0
c_hpr:
	.quad	0
	.size	c_hpr, 8

	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym c_lpr
	.addrsig_sym c_hpr
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         36
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     by_value
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 44
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z12idwt_per_X_1PfS_S_iiiii
    .private_segment_fixed_size: 0
    .sgpr_count:     21
    .sgpr_spill_count: 0
    .symbol:         _Z12idwt_per_X_1PfS_S_iiiii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     20
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
