#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <time.h>

// Interleaved addressing with divergent branching
__global__ void reduce_kernel0(int *d_out, int *d_in)
{
    extern __shared__ int s_data[];

    // thread ID inside the block
    unsigned int tid = threadIdx.x;
    // global ID across all blocks
    unsigned int gid = blockIdx.x * blockDim.x + threadIdx.x;

    // Copy elements from global memoery into per-block shared memory
    s_data[tid] = d_in[gid];
    // Ensure all elements have been copied into shared memory
    __syncthreads();

    // s = 1, 2, 4, 8, ..... blockDim.x / 2
    for (unsigned int s = 1; s < blockDim.x; s <<= 1) {
        if (tid % (s << 1) == 0) {
            s_data[tid] += s_data[tid + s];
        }
        // Ensure all threads in the block finish add in this round
        __syncthreads();
    }

    // write the reduction sum back to the global memory
    if (tid == 0) {
        d_out[blockIdx.x] = s_data[0];
    }
}

// Interleaved addressing with bank conflicts
__global__ void reduce_kernel1(int *d_out, int *d_in)
{
    extern __shared__ int s_data[];

    // thread ID inside the block
    unsigned int tid = threadIdx.x;
    // global ID across all blocks
    unsigned int gid = blockIdx.x * blockDim.x + threadIdx.x;

    // Copy elements from global memoery into per-block shared memory
    s_data[tid] = d_in[gid];
    // Ensure all elements have been copied into shared memory
    __syncthreads();    

    // s = 1, 2, 4, 8, ..... blockDim.x / 2
    for (unsigned int s = 1; s < blockDim.x; s <<= 1) {
        int index = tid * s * 2;

        if (index + s < blockDim.x) {
            s_data[index] += s_data[index + s];
        }

        // Ensure all threads in the block finish add in this round
        __syncthreads();
    }

    if (tid == 0) {
        d_out[blockIdx.x] = s_data[0];
    }
}

// Sequential addressing
__global__ void reduce_kernel2(int *d_out, int *d_in)
{
    extern __shared__ int s_data[];

    // thread ID inside the block
    unsigned int tid = threadIdx.x;
    // global ID across all blocks
    unsigned int gid = blockIdx.x * blockDim.x + threadIdx.x;

    // Copy elements from global memoery into per-block shared memory
    s_data[tid] = d_in[gid];
    // Ensure all elements have been copied into shared memory
    __syncthreads();    

    // s = blockDim.x / 2, ....., 8, 4, 2, 1
    for (unsigned int s = (blockDim.x >> 1); s >= 1; s >>= 1) {
        if (tid < s) {
            s_data[tid] += s_data[tid + s];
        }
        // Ensure all threads in the block finish add in this round
        __syncthreads();
    }

    if (tid == 0) {
        d_out[blockIdx.x] = s_data[0];
    }
}

// First add during global load
__global__ void reduce_kernel3(int *d_out, int *d_in)
{
    extern __shared__ int s_data[];

    // thread ID inside the block
    unsigned int tid = threadIdx.x;
    // global ID across all blocks
    unsigned int gid = blockIdx.x * blockDim.x * 2 + threadIdx.x;

    // perform first level of reduction,
    // reading from global memory, writing to shared memory
    s_data[tid] = d_in[gid] + d_in[gid + blockDim.x];
    // Ensure all elements have been copied into shared memory
    __syncthreads();    

    // s = blockDim.x / 2, ....., 8, 4, 2, 1
    for (unsigned int s = (blockDim.x >> 1); s >= 1; s >>= 1) {
        if (tid < s) {
            s_data[tid] += s_data[tid + s];
        }
        // Ensure all threads in the block finish add in this round
        __syncthreads();
    }

    if (tid == 0) {
        d_out[blockIdx.x] = s_data[0];
    }    
}

inline bool is_power_of_2(int n)
{
    return ((n & (n - 1)) == 0);
}


// input: array (in host memory), array size, expected result, kernel function ID and iterations 
void reduce(int *h_in, int array_size, int expected_result, int kernel_id, int iters)
{
    // # of threads per block. It should be the power of two
    int threads = 1 << 10;
    // # of blocks in total. 
    int blocks = 1;
    // GPU memory pointers
    int *d_in, *d_intermediate, *d_out;
    // final result in host memory
    int h_out;

    if (!h_in || array_size <= 0 || !is_power_of_2(array_size))
        goto out;

    if (array_size > threads)
        blocks = array_size / threads;
    
    // allocate GPU memory
    if (cudaMalloc((void**) &d_in, array_size * sizeof(int)) != cudaSuccess
     || cudaMalloc((void**) &d_intermediate, blocks * sizeof(int)) != cudaSuccess
     || cudaMalloc((void**) &d_out, sizeof(int)) != cudaSuccess)
        goto out;
    

    // copy the input array from the host memory to the GPU memory
    cudaMemcpy(d_in, h_in, array_size * sizeof(int), cudaMemcpyHostToDevice);

    // run many times
    for (int i = 0; i < iters; i++) {
        switch (kernel_id) {
            // Interleaved addressing with divergent branching 
            case 0: 
                // first stage reduce
                reduce_kernel0<<<blocks, threads, threads * sizeof(int)>>>(d_intermediate, d_in);
                // second stage reduce    
                reduce_kernel0<<<1, blocks, blocks * sizeof(int)>>>(d_out, d_intermediate);
                break;
            // Interleaved addressing with bank conflicts
            case 1:
                reduce_kernel1<<<blocks, threads, threads * sizeof(int)>>>(d_intermediate, d_in);
                reduce_kernel1<<<1, blocks, blocks * sizeof(int)>>>(d_out, d_intermediate);
                break;  
            // Sequential addressing              
            case 2:
                reduce_kernel2<<<blocks, threads, threads * sizeof(int)>>>(d_intermediate, d_in);
                reduce_kernel2<<<1, blocks, blocks * sizeof(int)>>>(d_out, d_intermediate);
                break;
            // First add during global load
            case 3:
                reduce_kernel3<<<blocks, threads / 2 , threads / 2 * sizeof(int)>>>(d_intermediate, d_in);
                reduce_kernel3<<<1, blocks / 2, blocks / 2 * sizeof(int)>>>(d_out, d_intermediate);  
                break;              
            default:
                printf("Invalid kernel function ID %d\n", kernel_id);   
                goto out;      
        }
    }

    // copy the result from the GPU memory to the host memory
    cudaMemcpy(&h_out, d_out, sizeof(int), cudaMemcpyDeviceToHost);

    if (h_out != expected_result) {
        printf("Wrong result: %d (expected) %d (actual)\n", expected_result, h_out);
    }

out:
    // free GPU memory
    cudaFree(d_in);
    cudaFree(d_intermediate);
    cudaFree(d_out);
}

// generate a random integer in [min, max]
inline int random_range(int min, int max)
{
    if (min > max)
        return 0;
    else
        return min + rand() / (RAND_MAX / (max - min + 1) + 1);
}

int main(int argc, char **argv) 
{
    if (argc != 3) {
        printf("%s [kernel ID] [iterations]\n", argv[0]);
        exit(EXIT_FAILURE);
    }

    int kernel_id = atoi(argv[1]);
    int iters = atoi(argv[2]);
    if (iters <= 0 || kernel_id < 0) {
        printf("Invalid input\n");
        exit(EXIT_FAILURE);
    }

    const int ARRAY_SIZE = 1 << 20;
    int h_in[ARRAY_SIZE];
    int sum = 0;
    
    // initialize random number generator
    srand(time(NULL));
    int min = 0, max = 10;

    for (int i = 0; i < ARRAY_SIZE; i++) {
        // generate a random int in a range
        h_in[i] = random_range(min, max);
        sum += h_in[i];
    }

    cudaEvent_t start, stop;
    cudaEventCreate(&start);
    cudaEventCreate(&stop);
    
    cudaEventRecord(start, 0);
    reduce(h_in, ARRAY_SIZE, sum, kernel_id, iters);
    cudaEventRecord(stop, 0);
    cudaEventSynchronize(stop);

    float elapsed_time;
    cudaEventElapsedTime(&elapsed_time, start, stop);    
    elapsed_time /= iters;      

    printf("Average time elapsed: %f ms\n", elapsed_time);

    return 0;
}
	.file	"tmpxft_0029ae62_00000000-6_reduce.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2033:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2033:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z36__device_stub__Z14reduce_kernel0PiS_PiS_
	.type	_Z36__device_stub__Z14reduce_kernel0PiS_PiS_, @function
_Z36__device_stub__Z14reduce_kernel0PiS_PiS_:
.LFB2055:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 8(%rsp)
	leaq	32(%rsp), %rcx
	leaq	24(%rsp), %rdx
	movq	%rsi, (%rsp)
	leaq	40(%rsp), %rdi
	leaq	52(%rsp), %rsi
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 48(%rsp)
	movq	%rax, 88(%rsp)
	movq	%rsp, %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	32(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z14reduce_kernel0PiS_(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 144
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	104(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L2:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2055:
	.size	_Z36__device_stub__Z14reduce_kernel0PiS_PiS_, .-_Z36__device_stub__Z14reduce_kernel0PiS_PiS_
	.globl	_Z14reduce_kernel0PiS_
	.type	_Z14reduce_kernel0PiS_, @function
_Z14reduce_kernel0PiS_:
.LFB2056:
	.cfi_startproc
	endbr64
	jmp	_Z36__device_stub__Z14reduce_kernel0PiS_PiS_
	.cfi_endproc
.LFE2056:
	.size	_Z14reduce_kernel0PiS_, .-_Z14reduce_kernel0PiS_
	.globl	_Z36__device_stub__Z14reduce_kernel1PiS_PiS_
	.type	_Z36__device_stub__Z14reduce_kernel1PiS_PiS_, @function
_Z36__device_stub__Z14reduce_kernel1PiS_PiS_:
.LFB2057:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 8(%rsp)
	leaq	32(%rsp), %rcx
	leaq	24(%rsp), %rdx
	movq	%rsi, (%rsp)
	leaq	40(%rsp), %rdi
	leaq	52(%rsp), %rsi
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 48(%rsp)
	movq	%rax, 88(%rsp)
	movq	%rsp, %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L8
	pushq	32(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z14reduce_kernel1PiS_(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 144
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	104(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L8:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L10
	call	__stack_chk_fail@PLT
.L10:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2057:
	.size	_Z36__device_stub__Z14reduce_kernel1PiS_PiS_, .-_Z36__device_stub__Z14reduce_kernel1PiS_PiS_
	.globl	_Z14reduce_kernel1PiS_
	.type	_Z14reduce_kernel1PiS_, @function
_Z14reduce_kernel1PiS_:
.LFB2058:
	.cfi_startproc
	endbr64
	jmp	_Z36__device_stub__Z14reduce_kernel1PiS_PiS_
	.cfi_endproc
.LFE2058:
	.size	_Z14reduce_kernel1PiS_, .-_Z14reduce_kernel1PiS_
	.globl	_Z36__device_stub__Z14reduce_kernel2PiS_PiS_
	.type	_Z36__device_stub__Z14reduce_kernel2PiS_PiS_, @function
_Z36__device_stub__Z14reduce_kernel2PiS_PiS_:
.LFB2059:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 8(%rsp)
	leaq	32(%rsp), %rcx
	leaq	24(%rsp), %rdx
	movq	%rsi, (%rsp)
	leaq	40(%rsp), %rdi
	leaq	52(%rsp), %rsi
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 48(%rsp)
	movq	%rax, 88(%rsp)
	movq	%rsp, %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L13
	pushq	32(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z14reduce_kernel2PiS_(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 144
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	104(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L13:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L15
	call	__stack_chk_fail@PLT
.L15:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2059:
	.size	_Z36__device_stub__Z14reduce_kernel2PiS_PiS_, .-_Z36__device_stub__Z14reduce_kernel2PiS_PiS_
	.globl	_Z14reduce_kernel2PiS_
	.type	_Z14reduce_kernel2PiS_, @function
_Z14reduce_kernel2PiS_:
.LFB2060:
	.cfi_startproc
	endbr64
	jmp	_Z36__device_stub__Z14reduce_kernel2PiS_PiS_
	.cfi_endproc
.LFE2060:
	.size	_Z14reduce_kernel2PiS_, .-_Z14reduce_kernel2PiS_
	.globl	_Z36__device_stub__Z14reduce_kernel3PiS_PiS_
	.type	_Z36__device_stub__Z14reduce_kernel3PiS_PiS_, @function
_Z36__device_stub__Z14reduce_kernel3PiS_PiS_:
.LFB2061:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 8(%rsp)
	leaq	32(%rsp), %rcx
	leaq	24(%rsp), %rdx
	movq	%rsi, (%rsp)
	leaq	40(%rsp), %rdi
	leaq	52(%rsp), %rsi
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 48(%rsp)
	movq	%rax, 88(%rsp)
	movq	%rsp, %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L18
	pushq	32(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z14reduce_kernel3PiS_(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 144
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	104(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L18:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L20
	call	__stack_chk_fail@PLT
.L20:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2061:
	.size	_Z36__device_stub__Z14reduce_kernel3PiS_PiS_, .-_Z36__device_stub__Z14reduce_kernel3PiS_PiS_
	.globl	_Z14reduce_kernel3PiS_
	.type	_Z14reduce_kernel3PiS_, @function
_Z14reduce_kernel3PiS_:
.LFB2062:
	.cfi_startproc
	endbr64
	jmp	_Z36__device_stub__Z14reduce_kernel3PiS_PiS_
	.cfi_endproc
.LFE2062:
	.size	_Z14reduce_kernel3PiS_, .-_Z14reduce_kernel3PiS_
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"Invalid kernel function ID %d\n"
.LC1:
	.string	"Wrong result: %d (expected) %d (actual)\n"
	.text
	.globl	_Z6reducePiiiii
	.type	_Z6reducePiiiii, @function
_Z6reducePiiiii:
.LFB2028:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$88, %rsp
	.cfi_def_cfa_offset 144
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	xorl	%eax, %eax
	testq	%rdi, %rdi
	je	.L26
	testl	%esi, %esi
	jle	.L26
	leal	-1(%rsi), %r12d
	andl	%esi, %r12d
	jne	.L26
	movq	%rdi, %r14
	movl	%edx, %r13d
	movl	%ecx, %ebp
	movl	%r8d, %r15d
	movl	$1, %ebx
	cmpl	$1024, %esi
	jle	.L28
	movl	%esi, %ebx
	sarl	$10, %ebx
.L28:
	movslq	%esi, %rsi
	leaq	24(%rsp), %rdi
	leaq	0(,%rsi,4), %rax
	movq	%rax, %rsi
	movq	%rax, 8(%rsp)
	call	cudaMalloc@PLT
	testl	%eax, %eax
	jne	.L26
	movslq	%ebx, %rax
	leaq	32(%rsp), %rdi
	salq	$2, %rax
	movq	%rax, %rsi
	movq	%rax, (%rsp)
	call	cudaMalloc@PLT
	testl	%eax, %eax
	jne	.L26
	leaq	40(%rsp), %rdi
	movl	$4, %esi
	call	cudaMalloc@PLT
	testl	%eax, %eax
	jne	.L26
	movq	8(%rsp), %rdx
	movq	24(%rsp), %rdi
	movl	$1, %ecx
	movq	%r14, %rsi
	call	cudaMemcpy@PLT
.L29:
	cmpl	%r15d, %r12d
	jge	.L49
	cmpl	$2, %ebp
	je	.L30
	jg	.L31
	testl	%ebp, %ebp
	je	.L32
	cmpl	$1, %ebp
	je	.L33
	jmp	.L34
.L31:
	cmpl	$3, %ebp
	je	.L35
	jmp	.L34
.L32:
	movl	%ebx, 48(%rsp)
	movl	$4194305, %edx
	xorl	%r9d, %r9d
	movl	$1, %ecx
	movabsq	$4294967297, %rax
	salq	$10, %rdx
	movl	$4096, %r8d
	movl	$1, 68(%rsp)
	movq	%rax, 52(%rsp)
	movq	48(%rsp), %rdi
	movl	56(%rsp), %esi
	movq	%rdx, 60(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L36
	movq	24(%rsp), %rsi
	movq	32(%rsp), %rdi
	call	_Z36__device_stub__Z14reduce_kernel0PiS_PiS_
.L36:
	movl	%ebx, 60(%rsp)
	movq	(%rsp), %r8
	xorl	%r9d, %r9d
	movl	$1, %esi
	movabsq	$4294967297, %rdi
	movl	$1, 56(%rsp)
	movq	%rdi, 64(%rsp)
	movl	68(%rsp), %ecx
	movq	60(%rsp), %rdx
	movq	%rdi, 48(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L38
	movq	32(%rsp), %rsi
	movq	40(%rsp), %rdi
	call	_Z36__device_stub__Z14reduce_kernel0PiS_PiS_
	jmp	.L38
.L33:
	movl	%ebx, 48(%rsp)
	movl	$4194305, %edx
	xorl	%r9d, %r9d
	movl	$1, %ecx
	movabsq	$4294967297, %rax
	salq	$10, %rdx
	movl	$4096, %r8d
	movl	$1, 68(%rsp)
	movq	%rax, 52(%rsp)
	movq	48(%rsp), %rdi
	movl	56(%rsp), %esi
	movq	%rdx, 60(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L39
	movq	24(%rsp), %rsi
	movq	32(%rsp), %rdi
	call	_Z36__device_stub__Z14reduce_kernel1PiS_PiS_
.L39:
	movl	%ebx, 60(%rsp)
	movq	(%rsp), %r8
	xorl	%r9d, %r9d
	movl	$1, %esi
	movabsq	$4294967297, %rdi
	movl	$1, 56(%rsp)
	movq	%rdi, 64(%rsp)
	movl	68(%rsp), %ecx
	movq	60(%rsp), %rdx
	movq	%rdi, 48(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L38
	movq	32(%rsp), %rsi
	movq	40(%rsp), %rdi
	call	_Z36__device_stub__Z14reduce_kernel1PiS_PiS_
	jmp	.L38
.L30:
	movl	%ebx, 48(%rsp)
	movl	$4194305, %edx
	xorl	%r9d, %r9d
	movl	$1, %ecx
	movabsq	$4294967297, %rax
	salq	$10, %rdx
	movl	$4096, %r8d
	movl	$1, 68(%rsp)
	movq	%rax, 52(%rsp)
	movq	48(%rsp), %rdi
	movl	56(%rsp), %esi
	movq	%rdx, 60(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L41
	movq	24(%rsp), %rsi
	movq	32(%rsp), %rdi
	call	_Z36__device_stub__Z14reduce_kernel2PiS_PiS_
.L41:
	movl	%ebx, 60(%rsp)
	movq	(%rsp), %r8
	xorl	%r9d, %r9d
	movl	$1, %esi
	movabsq	$4294967297, %rdi
	movl	$1, 56(%rsp)
	movq	%rdi, 64(%rsp)
	movl	68(%rsp), %ecx
	movq	60(%rsp), %rdx
	movq	%rdi, 48(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L38
	movq	32(%rsp), %rsi
	movq	40(%rsp), %rdi
	call	_Z36__device_stub__Z14reduce_kernel2PiS_PiS_
	jmp	.L38
.L35:
	movl	%ebx, 48(%rsp)
	movl	$8388609, %edx
	xorl	%r9d, %r9d
	movl	$1, %ecx
	movabsq	$4294967297, %rax
	salq	$9, %rdx
	movl	$2048, %r8d
	movl	$1, 68(%rsp)
	movq	%rax, 52(%rsp)
	movq	48(%rsp), %rdi
	movl	56(%rsp), %esi
	movq	%rdx, 60(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L43
	movq	24(%rsp), %rsi
	movq	32(%rsp), %rdi
	call	_Z36__device_stub__Z14reduce_kernel3PiS_PiS_
.L43:
	movl	%ebx, %eax
	xorl	%r9d, %r9d
	movabsq	$4294967297, %rdi
	movl	$1, %esi
	sarl	%eax
	movq	%rdi, 64(%rsp)
	movl	68(%rsp), %ecx
	movl	%eax, 60(%rsp)
	cltq
	movq	60(%rsp), %rdx
	leaq	0(,%rax,4), %r8
	movq	%rdi, 48(%rsp)
	movl	$1, 56(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L38
	movq	32(%rsp), %rsi
	movq	40(%rsp), %rdi
	call	_Z36__device_stub__Z14reduce_kernel3PiS_PiS_
	jmp	.L38
.L34:
	movl	%ebp, %edx
	leaq	.LC0(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	jmp	.L26
.L38:
	incl	%r12d
	jmp	.L29
.L49:
	movq	40(%rsp), %rsi
	movl	$2, %ecx
	leaq	60(%rsp), %rdi
	movl	$4, %edx
	call	cudaMemcpy@PLT
	movl	60(%rsp), %ecx
	cmpl	%r13d, %ecx
	je	.L26
	movl	%r13d, %edx
	leaq	.LC1(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
.L26:
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	movq	32(%rsp), %rdi
	call	cudaFree@PLT
	movq	40(%rsp), %rdi
	call	cudaFree@PLT
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L46
	call	__stack_chk_fail@PLT
.L46:
	addq	$88, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2028:
	.size	_Z6reducePiiiii, .-_Z6reducePiiiii
	.section	.rodata.str1.1
.LC2:
	.string	"%s [kernel ID] [iterations]\n"
.LC3:
	.string	"Invalid input\n"
.LC4:
	.string	"Average time elapsed: %f ms\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2030:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	leaq	-4194304(%rsp), %r11
	.cfi_def_cfa 11, 4194360
.LPSRL0:
	subq	$4096, %rsp
	orq	$0, (%rsp)
	cmpq	%r11, %rsp
	jne	.LPSRL0
	.cfi_def_cfa_register 7
	subq	$40, %rsp
	.cfi_def_cfa_offset 4194400
	movq	%fs:40, %rax
	movq	%rax, 4194328(%rsp)
	xorl	%eax, %eax
	movq	%rsi, %rbx
	cmpl	$3, %edi
	je	.L51
	movq	(%rsi), %rdx
	movl	$2, %edi
	leaq	.LC2(%rip), %rsi
	call	__printf_chk@PLT
	jmp	.L59
.L51:
	movq	8(%rsi), %rdi
	call	atoi@PLT
	movq	16(%rbx), %rdi
	movl	%eax, %ebp
	call	atoi@PLT
	movl	%eax, %ebx
	testl	%eax, %eax
	jle	.L56
	testl	%ebp, %ebp
	jns	.L52
.L56:
	leaq	.LC3(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
.L59:
	movl	$1, %edi
	call	exit@PLT
.L52:
	xorl	%edi, %edi
	xorl	%r14d, %r14d
	xorl	%r12d, %r12d
	movl	$195225787, %r13d
	call	time@PLT
	movl	%eax, %edi
	call	srand@PLT
.L54:
	call	rand@PLT
	leaq	24(%rsp), %r15
	cltd
	idivl	%r13d
	movl	%eax, (%r15,%r14,4)
	incq	%r14
	addl	%eax, %r12d
	cmpq	$1048576, %r14
	jne	.L54
	leaq	8(%rsp), %rdi
	call	cudaEventCreate@PLT
	leaq	16(%rsp), %rdi
	call	cudaEventCreate@PLT
	movq	8(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movl	%ebx, %r8d
	movl	%ebp, %ecx
	movl	%r12d, %edx
	movl	$1048576, %esi
	movq	%r15, %rdi
	call	_Z6reducePiiiii
	movq	16(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movq	16(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movq	8(%rsp), %rsi
	movq	16(%rsp), %rdx
	leaq	4(%rsp), %rdi
	call	cudaEventElapsedTime@PLT
	cvtsi2ssl	%ebx, %xmm1
	movl	$2, %edi
	movb	$1, %al
	movss	4(%rsp), %xmm0
	leaq	.LC4(%rip), %rsi
	divss	%xmm1, %xmm0
	movss	%xmm0, 4(%rsp)
	cvtss2sd	%xmm0, %xmm0
	call	__printf_chk@PLT
	movq	4194328(%rsp), %rax
	subq	%fs:40, %rax
	je	.L55
	call	__stack_chk_fail@PLT
.L55:
	addq	$4194344, %rsp
	.cfi_def_cfa_offset 56
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2030:
	.size	main, .-main
	.section	.rodata.str1.1
.LC5:
	.string	"_Z14reduce_kernel3PiS_"
.LC6:
	.string	"_Z14reduce_kernel2PiS_"
.LC7:
	.string	"_Z14reduce_kernel1PiS_"
.LC8:
	.string	"_Z14reduce_kernel0PiS_"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2064:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC5(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z14reduce_kernel3PiS_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC6(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z14reduce_kernel2PiS_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC7(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z14reduce_kernel1PiS_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC8(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z14reduce_kernel0PiS_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2064:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <time.h>

// Interleaved addressing with divergent branching
__global__ void reduce_kernel0(int *d_out, int *d_in)
{
    extern __shared__ int s_data[];

    // thread ID inside the block
    unsigned int tid = threadIdx.x;
    // global ID across all blocks
    unsigned int gid = blockIdx.x * blockDim.x + threadIdx.x;

    // Copy elements from global memoery into per-block shared memory
    s_data[tid] = d_in[gid];
    // Ensure all elements have been copied into shared memory
    __syncthreads();

    // s = 1, 2, 4, 8, ..... blockDim.x / 2
    for (unsigned int s = 1; s < blockDim.x; s <<= 1) {
        if (tid % (s << 1) == 0) {
            s_data[tid] += s_data[tid + s];
        }
        // Ensure all threads in the block finish add in this round
        __syncthreads();
    }

    // write the reduction sum back to the global memory
    if (tid == 0) {
        d_out[blockIdx.x] = s_data[0];
    }
}

// Interleaved addressing with bank conflicts
__global__ void reduce_kernel1(int *d_out, int *d_in)
{
    extern __shared__ int s_data[];

    // thread ID inside the block
    unsigned int tid = threadIdx.x;
    // global ID across all blocks
    unsigned int gid = blockIdx.x * blockDim.x + threadIdx.x;

    // Copy elements from global memoery into per-block shared memory
    s_data[tid] = d_in[gid];
    // Ensure all elements have been copied into shared memory
    __syncthreads();    

    // s = 1, 2, 4, 8, ..... blockDim.x / 2
    for (unsigned int s = 1; s < blockDim.x; s <<= 1) {
        int index = tid * s * 2;

        if (index + s < blockDim.x) {
            s_data[index] += s_data[index + s];
        }

        // Ensure all threads in the block finish add in this round
        __syncthreads();
    }

    if (tid == 0) {
        d_out[blockIdx.x] = s_data[0];
    }
}

// Sequential addressing
__global__ void reduce_kernel2(int *d_out, int *d_in)
{
    extern __shared__ int s_data[];

    // thread ID inside the block
    unsigned int tid = threadIdx.x;
    // global ID across all blocks
    unsigned int gid = blockIdx.x * blockDim.x + threadIdx.x;

    // Copy elements from global memoery into per-block shared memory
    s_data[tid] = d_in[gid];
    // Ensure all elements have been copied into shared memory
    __syncthreads();    

    // s = blockDim.x / 2, ....., 8, 4, 2, 1
    for (unsigned int s = (blockDim.x >> 1); s >= 1; s >>= 1) {
        if (tid < s) {
            s_data[tid] += s_data[tid + s];
        }
        // Ensure all threads in the block finish add in this round
        __syncthreads();
    }

    if (tid == 0) {
        d_out[blockIdx.x] = s_data[0];
    }
}

// First add during global load
__global__ void reduce_kernel3(int *d_out, int *d_in)
{
    extern __shared__ int s_data[];

    // thread ID inside the block
    unsigned int tid = threadIdx.x;
    // global ID across all blocks
    unsigned int gid = blockIdx.x * blockDim.x * 2 + threadIdx.x;

    // perform first level of reduction,
    // reading from global memory, writing to shared memory
    s_data[tid] = d_in[gid] + d_in[gid + blockDim.x];
    // Ensure all elements have been copied into shared memory
    __syncthreads();    

    // s = blockDim.x / 2, ....., 8, 4, 2, 1
    for (unsigned int s = (blockDim.x >> 1); s >= 1; s >>= 1) {
        if (tid < s) {
            s_data[tid] += s_data[tid + s];
        }
        // Ensure all threads in the block finish add in this round
        __syncthreads();
    }

    if (tid == 0) {
        d_out[blockIdx.x] = s_data[0];
    }    
}

inline bool is_power_of_2(int n)
{
    return ((n & (n - 1)) == 0);
}


// input: array (in host memory), array size, expected result, kernel function ID and iterations 
void reduce(int *h_in, int array_size, int expected_result, int kernel_id, int iters)
{
    // # of threads per block. It should be the power of two
    int threads = 1 << 10;
    // # of blocks in total. 
    int blocks = 1;
    // GPU memory pointers
    int *d_in, *d_intermediate, *d_out;
    // final result in host memory
    int h_out;

    if (!h_in || array_size <= 0 || !is_power_of_2(array_size))
        goto out;

    if (array_size > threads)
        blocks = array_size / threads;
    
    // allocate GPU memory
    if (hipMalloc((void**) &d_in, array_size * sizeof(int)) != hipSuccess
     || hipMalloc((void**) &d_intermediate, blocks * sizeof(int)) != hipSuccess
     || hipMalloc((void**) &d_out, sizeof(int)) != hipSuccess)
        goto out;
    

    // copy the input array from the host memory to the GPU memory
    hipMemcpy(d_in, h_in, array_size * sizeof(int), hipMemcpyHostToDevice);

    // run many times
    for (int i = 0; i < iters; i++) {
        switch (kernel_id) {
            // Interleaved addressing with divergent branching 
            case 0: 
                // first stage reduce
                reduce_kernel0<<<blocks, threads, threads * sizeof(int)>>>(d_intermediate, d_in);
                // second stage reduce    
                reduce_kernel0<<<1, blocks, blocks * sizeof(int)>>>(d_out, d_intermediate);
                break;
            // Interleaved addressing with bank conflicts
            case 1:
                reduce_kernel1<<<blocks, threads, threads * sizeof(int)>>>(d_intermediate, d_in);
                reduce_kernel1<<<1, blocks, blocks * sizeof(int)>>>(d_out, d_intermediate);
                break;  
            // Sequential addressing              
            case 2:
                reduce_kernel2<<<blocks, threads, threads * sizeof(int)>>>(d_intermediate, d_in);
                reduce_kernel2<<<1, blocks, blocks * sizeof(int)>>>(d_out, d_intermediate);
                break;
            // First add during global load
            case 3:
                reduce_kernel3<<<blocks, threads / 2 , threads / 2 * sizeof(int)>>>(d_intermediate, d_in);
                reduce_kernel3<<<1, blocks / 2, blocks / 2 * sizeof(int)>>>(d_out, d_intermediate);  
                break;              
            default:
                printf("Invalid kernel function ID %d\n", kernel_id);   
                goto out;      
        }
    }

    // copy the result from the GPU memory to the host memory
    hipMemcpy(&h_out, d_out, sizeof(int), hipMemcpyDeviceToHost);

    if (h_out != expected_result) {
        printf("Wrong result: %d (expected) %d (actual)\n", expected_result, h_out);
    }

out:
    // free GPU memory
    hipFree(d_in);
    hipFree(d_intermediate);
    hipFree(d_out);
}

// generate a random integer in [min, max]
inline int random_range(int min, int max)
{
    if (min > max)
        return 0;
    else
        return min + rand() / (RAND_MAX / (max - min + 1) + 1);
}

int main(int argc, char **argv) 
{
    if (argc != 3) {
        printf("%s [kernel ID] [iterations]\n", argv[0]);
        exit(EXIT_FAILURE);
    }

    int kernel_id = atoi(argv[1]);
    int iters = atoi(argv[2]);
    if (iters <= 0 || kernel_id < 0) {
        printf("Invalid input\n");
        exit(EXIT_FAILURE);
    }

    const int ARRAY_SIZE = 1 << 20;
    int h_in[ARRAY_SIZE];
    int sum = 0;
    
    // initialize random number generator
    srand(time(NULL));
    int min = 0, max = 10;

    for (int i = 0; i < ARRAY_SIZE; i++) {
        // generate a random int in a range
        h_in[i] = random_range(min, max);
        sum += h_in[i];
    }

    hipEvent_t start, stop;
    hipEventCreate(&start);
    hipEventCreate(&stop);
    
    hipEventRecord(start, 0);
    reduce(h_in, ARRAY_SIZE, sum, kernel_id, iters);
    hipEventRecord(stop, 0);
    hipEventSynchronize(stop);

    float elapsed_time;
    hipEventElapsedTime(&elapsed_time, start, stop);    
    elapsed_time /= iters;      

    printf("Average time elapsed: %f ms\n", elapsed_time);

    return 0;
}
	.text
	.file	"reduce.hip"
	.globl	_Z29__device_stub__reduce_kernel0PiS_ # -- Begin function _Z29__device_stub__reduce_kernel0PiS_
	.type	_Z29__device_stub__reduce_kernel0PiS_,@function
_Z29__device_stub__reduce_kernel0PiS_:  # @_Z29__device_stub__reduce_kernel0PiS_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	16(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z14reduce_kernel0PiS_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z29__device_stub__reduce_kernel0PiS_, .Lfunc_end0-_Z29__device_stub__reduce_kernel0PiS_
	.cfi_endproc
                                        # -- End function
	.globl	_Z29__device_stub__reduce_kernel1PiS_ # -- Begin function _Z29__device_stub__reduce_kernel1PiS_
	.type	_Z29__device_stub__reduce_kernel1PiS_,@function
_Z29__device_stub__reduce_kernel1PiS_:  # @_Z29__device_stub__reduce_kernel1PiS_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	16(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z14reduce_kernel1PiS_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z29__device_stub__reduce_kernel1PiS_, .Lfunc_end1-_Z29__device_stub__reduce_kernel1PiS_
	.cfi_endproc
                                        # -- End function
	.globl	_Z29__device_stub__reduce_kernel2PiS_ # -- Begin function _Z29__device_stub__reduce_kernel2PiS_
	.type	_Z29__device_stub__reduce_kernel2PiS_,@function
_Z29__device_stub__reduce_kernel2PiS_:  # @_Z29__device_stub__reduce_kernel2PiS_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	16(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z14reduce_kernel2PiS_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z29__device_stub__reduce_kernel2PiS_, .Lfunc_end2-_Z29__device_stub__reduce_kernel2PiS_
	.cfi_endproc
                                        # -- End function
	.globl	_Z29__device_stub__reduce_kernel3PiS_ # -- Begin function _Z29__device_stub__reduce_kernel3PiS_
	.type	_Z29__device_stub__reduce_kernel3PiS_,@function
_Z29__device_stub__reduce_kernel3PiS_:  # @_Z29__device_stub__reduce_kernel3PiS_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	16(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z14reduce_kernel3PiS_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	_Z29__device_stub__reduce_kernel3PiS_, .Lfunc_end3-_Z29__device_stub__reduce_kernel3PiS_
	.cfi_endproc
                                        # -- End function
	.globl	_Z6reducePiiiii                 # -- Begin function _Z6reducePiiiii
	.type	_Z6reducePiiiii,@function
_Z6reducePiiiii:                        # @_Z6reducePiiiii
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$72, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	testq	%rdi, %rdi
	je	.LBB4_31
# %bb.1:
	testl	%esi, %esi
	jle	.LBB4_31
# %bb.2:
	movl	%ecx, %ebp
	movl	%edx, %ebx
	movl	%esi, %eax
	shrl	%eax
	andl	$1431655765, %eax               # imm = 0x55555555
	movl	%esi, %ecx
	subl	%eax, %ecx
	movl	$858993459, %eax                # imm = 0x33333333
	movl	%ecx, %edx
	andl	%eax, %edx
	shrl	$2, %ecx
	andl	%eax, %ecx
	addl	%edx, %ecx
	movl	%ecx, %eax
	shrl	$4, %eax
	addl	%ecx, %eax
	andl	$252645135, %eax                # imm = 0xF0F0F0F
	imull	$16843009, %eax, %eax           # imm = 0x1010101
	shrl	$24, %eax
	cmpl	$1, %eax
	ja	.LBB4_31
# %bb.3:
	movl	%r8d, %r14d
	movq	%rdi, %r12
	movl	%esi, %eax
	shrl	$10, %eax
	cmpl	$1025, %esi                     # imm = 0x401
	movl	$1, %r15d
	cmovael	%eax, %r15d
	movl	%esi, %r13d
	shlq	$2, %r13
	leaq	24(%rsp), %rdi
	movq	%r13, %rsi
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB4_31
# %bb.4:
	leal	(,%r15,4), %esi
	leaq	8(%rsp), %rdi
	movq	%rsi, 32(%rsp)                  # 8-byte Spill
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB4_31
# %bb.5:
	leaq	16(%rsp), %rdi
	movl	$4, %esi
	callq	hipMalloc
	testl	%eax, %eax
	je	.LBB4_6
.LBB4_31:
	movq	24(%rsp), %rdi
	callq	hipFree
	movq	8(%rsp), %rdi
	callq	hipFree
	movq	16(%rsp), %rdi
	callq	hipFree
	addq	$72, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB4_6:
	.cfi_def_cfa_offset 128
	movq	24(%rsp), %rdi
	movq	%r12, %rsi
	movq	%r13, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	testl	%r14d, %r14d
	jle	.LBB4_29
# %bb.7:                                # %.lr.ph
	cmpl	$3, %ebp
	ja	.LBB4_32
# %bb.8:                                # %.lr.ph.split.preheader
	movabsq	$4294967297, %rcx               # imm = 0x100000001
	movl	%r15d, %eax
	leaq	(%rax,%rcx), %r13
	decq	%r13
	shrl	%r15d
	leal	(,%r15,4), %eax
	movq	%rax, 56(%rsp)                  # 8-byte Spill
	leaq	(%r15,%rcx), %rax
	decq	%rax
	movq	%rax, 48(%rsp)                  # 8-byte Spill
	movq	%rcx, %r15
	leaq	1023(%rcx), %r12
	leaq	511(%rcx), %rax
	movq	%rax, 40(%rsp)                  # 8-byte Spill
.LBB4_9:                                # %.lr.ph.split
                                        # =>This Inner Loop Header: Depth=1
	cmpl	$2, %ebp
	je	.LBB4_20
# %bb.10:                               # %.lr.ph.split
                                        #   in Loop: Header=BB4_9 Depth=1
	cmpl	$1, %ebp
	je	.LBB4_16
# %bb.11:                               # %.lr.ph.split
                                        #   in Loop: Header=BB4_9 Depth=1
	testl	%ebp, %ebp
	jne	.LBB4_24
# %bb.12:                               #   in Loop: Header=BB4_9 Depth=1
	movl	$4096, %r8d                     # imm = 0x1000
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB4_14
# %bb.13:                               #   in Loop: Header=BB4_9 Depth=1
	movq	8(%rsp), %rdi
	movq	24(%rsp), %rsi
	callq	_Z29__device_stub__reduce_kernel0PiS_
.LBB4_14:                               #   in Loop: Header=BB4_9 Depth=1
	movq	%r15, %rdi
	movl	$1, %esi
	movq	%r13, %rdx
	movl	$1, %ecx
	movq	32(%rsp), %r8                   # 8-byte Reload
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB4_28
# %bb.15:                               #   in Loop: Header=BB4_9 Depth=1
	movq	16(%rsp), %rdi
	movq	8(%rsp), %rsi
	callq	_Z29__device_stub__reduce_kernel0PiS_
	jmp	.LBB4_28
.LBB4_16:                               #   in Loop: Header=BB4_9 Depth=1
	movl	$4096, %r8d                     # imm = 0x1000
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB4_18
# %bb.17:                               #   in Loop: Header=BB4_9 Depth=1
	movq	8(%rsp), %rdi
	movq	24(%rsp), %rsi
	callq	_Z29__device_stub__reduce_kernel1PiS_
.LBB4_18:                               #   in Loop: Header=BB4_9 Depth=1
	movq	%r15, %rdi
	movl	$1, %esi
	movq	%r13, %rdx
	movl	$1, %ecx
	movq	32(%rsp), %r8                   # 8-byte Reload
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB4_28
# %bb.19:                               #   in Loop: Header=BB4_9 Depth=1
	movq	16(%rsp), %rdi
	movq	8(%rsp), %rsi
	callq	_Z29__device_stub__reduce_kernel1PiS_
	jmp	.LBB4_28
.LBB4_20:                               #   in Loop: Header=BB4_9 Depth=1
	movl	$4096, %r8d                     # imm = 0x1000
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB4_22
# %bb.21:                               #   in Loop: Header=BB4_9 Depth=1
	movq	8(%rsp), %rdi
	movq	24(%rsp), %rsi
	callq	_Z29__device_stub__reduce_kernel2PiS_
.LBB4_22:                               #   in Loop: Header=BB4_9 Depth=1
	movq	%r15, %rdi
	movl	$1, %esi
	movq	%r13, %rdx
	movl	$1, %ecx
	movq	32(%rsp), %r8                   # 8-byte Reload
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB4_28
# %bb.23:                               #   in Loop: Header=BB4_9 Depth=1
	movq	16(%rsp), %rdi
	movq	8(%rsp), %rsi
	callq	_Z29__device_stub__reduce_kernel2PiS_
	jmp	.LBB4_28
.LBB4_24:                               #   in Loop: Header=BB4_9 Depth=1
	movl	$2048, %r8d                     # imm = 0x800
	movq	%r13, %rdi
	movl	$1, %esi
	movq	40(%rsp), %rdx                  # 8-byte Reload
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB4_26
# %bb.25:                               #   in Loop: Header=BB4_9 Depth=1
	movq	8(%rsp), %rdi
	movq	24(%rsp), %rsi
	callq	_Z29__device_stub__reduce_kernel3PiS_
.LBB4_26:                               #   in Loop: Header=BB4_9 Depth=1
	movq	%r15, %rdi
	movl	$1, %esi
	movq	48(%rsp), %rdx                  # 8-byte Reload
	movl	$1, %ecx
	movq	56(%rsp), %r8                   # 8-byte Reload
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB4_28
# %bb.27:                               #   in Loop: Header=BB4_9 Depth=1
	movq	16(%rsp), %rdi
	movq	8(%rsp), %rsi
	callq	_Z29__device_stub__reduce_kernel3PiS_
.LBB4_28:                               #   in Loop: Header=BB4_9 Depth=1
	decl	%r14d
	jne	.LBB4_9
.LBB4_29:                               # %._crit_edge
	movq	16(%rsp), %rsi
	leaq	68(%rsp), %r14
	movl	$4, %edx
	movq	%r14, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movl	(%r14), %edx
	cmpl	%ebx, %edx
	je	.LBB4_31
# %bb.30:
	movl	$.L.str.1, %edi
	movl	%ebx, %esi
	xorl	%eax, %eax
	callq	printf
	jmp	.LBB4_31
.LBB4_32:
	movl	$.L.str, %edi
	movl	%ebp, %esi
	xorl	%eax, %eax
	callq	printf
	jmp	.LBB4_31
.Lfunc_end4:
	.size	_Z6reducePiiiii, .Lfunc_end4-_Z6reducePiiiii
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$4194336, %rsp                  # imm = 0x400020
	.cfi_def_cfa_offset 4194384
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%rsi, %rbx
	cmpl	$3, %edi
	jne	.LBB5_6
# %bb.1:
	movq	8(%rbx), %rdi
	callq	atoi
	movl	%eax, %ebp
	movq	16(%rbx), %rdi
	callq	atoi
	testl	%eax, %eax
	jle	.LBB5_7
# %bb.2:
	testl	%ebp, %ebp
	js	.LBB5_7
# %bb.3:
	movl	%eax, %ebx
	xorl	%r15d, %r15d
	xorl	%edi, %edi
	callq	time
	movl	%eax, %edi
	callq	srand
	xorl	%r14d, %r14d
.LBB5_4:                                # =>This Inner Loop Header: Depth=1
	callq	rand
	cltq
	imulq	$738197501, %rax, %rax          # imm = 0x2BFFFFFD
	movq	%rax, %rcx
	shrq	$63, %rcx
	sarq	$57, %rax
	addl	%ecx, %eax
	movl	%eax, 32(%rsp,%r15,4)
	addl	%eax, %r14d
	incq	%r15
	cmpq	$1048576, %r15                  # imm = 0x100000
	jne	.LBB5_4
# %bb.5:
	leaq	24(%rsp), %r15
	movq	%r15, %rdi
	callq	hipEventCreate
	leaq	16(%rsp), %r12
	movq	%r12, %rdi
	callq	hipEventCreate
	movq	(%r15), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	leaq	32(%rsp), %rdi
	movl	$1048576, %esi                  # imm = 0x100000
	movl	%r14d, %edx
	movl	%ebp, %ecx
	movl	%ebx, %r8d
	callq	_Z6reducePiiiii
	movq	(%r12), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	(%r12), %rdi
	callq	hipEventSynchronize
	movq	(%r15), %rsi
	movq	(%r12), %rdx
	leaq	12(%rsp), %r14
	movq	%r14, %rdi
	callq	hipEventElapsedTime
	cvtsi2ss	%ebx, %xmm0
	movss	(%r14), %xmm1                   # xmm1 = mem[0],zero,zero,zero
	divss	%xmm0, %xmm1
	movss	%xmm1, (%r14)
	xorps	%xmm0, %xmm0
	cvtss2sd	%xmm1, %xmm0
	movl	$.L.str.4, %edi
	movb	$1, %al
	callq	printf
	xorl	%eax, %eax
	addq	$4194336, %rsp                  # imm = 0x400020
	.cfi_def_cfa_offset 48
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB5_6:
	.cfi_def_cfa_offset 4194384
	movq	(%rbx), %rsi
	movl	$.L.str.2, %edi
	xorl	%eax, %eax
	callq	printf
	jmp	.LBB5_8
.LBB5_7:
	movl	$.Lstr, %edi
	callq	puts@PLT
.LBB5_8:
	movl	$1, %edi
	callq	exit
.Lfunc_end5:
	.size	main, .Lfunc_end5-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB6_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB6_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z14reduce_kernel0PiS_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z14reduce_kernel1PiS_, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z14reduce_kernel2PiS_, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z14reduce_kernel3PiS_, %esi
	movl	$.L__unnamed_4, %edx
	movl	$.L__unnamed_4, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end6:
	.size	__hip_module_ctor, .Lfunc_end6-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB7_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB7_2:
	retq
.Lfunc_end7:
	.size	__hip_module_dtor, .Lfunc_end7-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z14reduce_kernel0PiS_,@object  # @_Z14reduce_kernel0PiS_
	.section	.rodata,"a",@progbits
	.globl	_Z14reduce_kernel0PiS_
	.p2align	3, 0x0
_Z14reduce_kernel0PiS_:
	.quad	_Z29__device_stub__reduce_kernel0PiS_
	.size	_Z14reduce_kernel0PiS_, 8

	.type	_Z14reduce_kernel1PiS_,@object  # @_Z14reduce_kernel1PiS_
	.globl	_Z14reduce_kernel1PiS_
	.p2align	3, 0x0
_Z14reduce_kernel1PiS_:
	.quad	_Z29__device_stub__reduce_kernel1PiS_
	.size	_Z14reduce_kernel1PiS_, 8

	.type	_Z14reduce_kernel2PiS_,@object  # @_Z14reduce_kernel2PiS_
	.globl	_Z14reduce_kernel2PiS_
	.p2align	3, 0x0
_Z14reduce_kernel2PiS_:
	.quad	_Z29__device_stub__reduce_kernel2PiS_
	.size	_Z14reduce_kernel2PiS_, 8

	.type	_Z14reduce_kernel3PiS_,@object  # @_Z14reduce_kernel3PiS_
	.globl	_Z14reduce_kernel3PiS_
	.p2align	3, 0x0
_Z14reduce_kernel3PiS_:
	.quad	_Z29__device_stub__reduce_kernel3PiS_
	.size	_Z14reduce_kernel3PiS_, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"Invalid kernel function ID %d\n"
	.size	.L.str, 31

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"Wrong result: %d (expected) %d (actual)\n"
	.size	.L.str.1, 41

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"%s [kernel ID] [iterations]\n"
	.size	.L.str.2, 29

	.type	.L.str.4,@object                # @.str.4
.L.str.4:
	.asciz	"Average time elapsed: %f ms\n"
	.size	.L.str.4, 29

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z14reduce_kernel0PiS_"
	.size	.L__unnamed_1, 23

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z14reduce_kernel1PiS_"
	.size	.L__unnamed_2, 23

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z14reduce_kernel2PiS_"
	.size	.L__unnamed_3, 23

	.type	.L__unnamed_4,@object           # @3
.L__unnamed_4:
	.asciz	"_Z14reduce_kernel3PiS_"
	.size	.L__unnamed_4, 23

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.type	.Lstr,@object                   # @str
	.section	.rodata.str1.1,"aMS",@progbits,1
.Lstr:
	.asciz	"Invalid input"
	.size	.Lstr, 14

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z29__device_stub__reduce_kernel0PiS_
	.addrsig_sym _Z29__device_stub__reduce_kernel1PiS_
	.addrsig_sym _Z29__device_stub__reduce_kernel2PiS_
	.addrsig_sym _Z29__device_stub__reduce_kernel3PiS_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z14reduce_kernel0PiS_
	.addrsig_sym _Z14reduce_kernel1PiS_
	.addrsig_sym _Z14reduce_kernel2PiS_
	.addrsig_sym _Z14reduce_kernel3PiS_
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z14reduce_kernel0PiS_  ; -- Begin function _Z14reduce_kernel0PiS_
	.globl	_Z14reduce_kernel0PiS_
	.p2align	8
	.type	_Z14reduce_kernel0PiS_,@function
_Z14reduce_kernel0PiS_:                 ; @_Z14reduce_kernel0PiS_
; %bb.0:
	s_clause 0x1
	s_load_b32 s5, s[0:1], 0x1c
	s_load_b128 s[0:3], s[0:1], 0x0
	s_mov_b32 s4, s15
	s_waitcnt lgkmcnt(0)
	s_and_b32 s5, s5, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s4, s5, v[0:1]
	v_mov_b32_e32 v2, 0
	s_cmp_lt_u32 s5, 2
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s2, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
	global_load_b32 v2, v[1:2], off
	v_lshl_add_u32 v1, v0, 2, 0
	s_waitcnt vmcnt(0)
	ds_store_b32 v1, v2
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB0_5
; %bb.1:                                ; %.lr.ph.preheader
	s_mov_b32 s3, 1
.LBB0_2:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b32 s2, s3, 1
	s_add_i32 s6, s2, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v2, s6, v0
	s_mov_b32 s6, exec_lo
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB0_4
; %bb.3:                                ;   in Loop: Header=BB0_2 Depth=1
	v_lshl_add_u32 v2, s3, 2, v1
	ds_load_b32 v2, v2
	ds_load_b32 v3, v1
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v2, v3, v2
	ds_store_b32 v1, v2
.LBB0_4:                                ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s6
	s_cmp_ge_u32 s2, s5
	s_mov_b32 s3, s2
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc0 .LBB0_2
.LBB0_5:                                ; %._crit_edge
	s_mov_b32 s2, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB0_7
; %bb.6:
	v_mov_b32_e32 v0, 0
	s_mov_b32 s5, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[2:3], s[4:5], 2
	s_add_u32 s0, s0, s2
	ds_load_b32 v1, v0
	s_addc_u32 s1, s1, s3
	s_waitcnt lgkmcnt(0)
	global_store_b32 v0, v1, s[0:1]
.LBB0_7:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z14reduce_kernel0PiS_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 4
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z14reduce_kernel0PiS_, .Lfunc_end0-_Z14reduce_kernel0PiS_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 304
; NumSgprs: 18
; NumVgprs: 4
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 4
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z14reduce_kernel1PiS_  ; -- Begin function _Z14reduce_kernel1PiS_
	.globl	_Z14reduce_kernel1PiS_
	.p2align	8
	.type	_Z14reduce_kernel1PiS_,@function
_Z14reduce_kernel1PiS_:                 ; @_Z14reduce_kernel1PiS_
; %bb.0:
	s_clause 0x1
	s_load_b32 s5, s[0:1], 0x1c
	s_load_b128 s[0:3], s[0:1], 0x0
	s_mov_b32 s4, s15
	s_waitcnt lgkmcnt(0)
	s_and_b32 s5, s5, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s4, s5, v[0:1]
	v_mov_b32_e32 v2, 0
	s_cmp_lt_u32 s5, 2
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s2, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
	global_load_b32 v1, v[1:2], off
	v_lshl_add_u32 v2, v0, 2, 0
	s_waitcnt vmcnt(0)
	ds_store_b32 v2, v1
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB1_5
; %bb.1:                                ; %.lr.ph
	v_lshlrev_b32_e32 v1, 1, v0
	s_mov_b32 s2, 1
.LBB1_2:                                ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mul_lo_u32 v2, v1, s2
	s_mov_b32 s3, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v3, s2, v2
	v_cmpx_gt_u32_e64 s5, v3
	s_cbranch_execz .LBB1_4
; %bb.3:                                ;   in Loop: Header=BB1_2 Depth=1
	v_lshl_add_u32 v2, v2, 2, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_lshl_add_u32 v3, s2, 2, v2
	ds_load_b32 v3, v3
	ds_load_b32 v4, v2
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v3, v4, v3
	ds_store_b32 v2, v3
.LBB1_4:                                ;   in Loop: Header=BB1_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s3
	s_lshl_b32 s2, s2, 1
	s_waitcnt lgkmcnt(0)
	s_cmp_ge_u32 s2, s5
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc0 .LBB1_2
.LBB1_5:                                ; %._crit_edge
	s_mov_b32 s2, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB1_7
; %bb.6:
	v_mov_b32_e32 v0, 0
	s_mov_b32 s5, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[2:3], s[4:5], 2
	s_add_u32 s0, s0, s2
	ds_load_b32 v1, v0
	s_addc_u32 s1, s1, s3
	s_waitcnt lgkmcnt(0)
	global_store_b32 v0, v1, s[0:1]
.LBB1_7:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z14reduce_kernel1PiS_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 5
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z14reduce_kernel1PiS_, .Lfunc_end1-_Z14reduce_kernel1PiS_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 324
; NumSgprs: 18
; NumVgprs: 5
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 5
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z14reduce_kernel2PiS_  ; -- Begin function _Z14reduce_kernel2PiS_
	.globl	_Z14reduce_kernel2PiS_
	.p2align	8
	.type	_Z14reduce_kernel2PiS_,@function
_Z14reduce_kernel2PiS_:                 ; @_Z14reduce_kernel2PiS_
; %bb.0:
	s_clause 0x1
	s_load_b32 s5, s[0:1], 0x1c
	s_load_b128 s[0:3], s[0:1], 0x0
	s_mov_b32 s4, s15
	s_waitcnt lgkmcnt(0)
	s_and_b32 s5, s5, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s4, s5, v[0:1]
	v_mov_b32_e32 v2, 0
	s_cmp_lt_u32 s5, 2
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s2, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
	global_load_b32 v2, v[1:2], off
	v_lshl_add_u32 v1, v0, 2, 0
	s_waitcnt vmcnt(0)
	ds_store_b32 v1, v2
	s_waitcnt lgkmcnt(0)
	s_barrier
.LBB2_1:                                ; =>This Inner Loop Header: Depth=1
	buffer_gl0_inv
	s_cbranch_scc1 .LBB2_5
; %bb.2:                                ; %.lr.ph
                                        ;   in Loop: Header=BB2_1 Depth=1
	s_lshr_b32 s2, s5, 1
	s_mov_b32 s3, exec_lo
	v_cmpx_gt_u32_e64 s2, v0
	s_cbranch_execz .LBB2_4
; %bb.3:                                ;   in Loop: Header=BB2_1 Depth=1
	v_lshl_add_u32 v2, s2, 2, v1
	ds_load_b32 v2, v2
	ds_load_b32 v3, v1
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v2, v3, v2
	ds_store_b32 v1, v2
.LBB2_4:                                ;   in Loop: Header=BB2_1 Depth=1
	s_or_b32 exec_lo, exec_lo, s3
	s_waitcnt lgkmcnt(0)
	s_barrier
	s_cmp_lt_u32 s5, 4
	s_mov_b32 s5, s2
	s_branch .LBB2_1
.LBB2_5:                                ; %._crit_edge
	s_mov_b32 s2, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB2_7
; %bb.6:
	v_mov_b32_e32 v0, 0
	s_mov_b32 s5, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[2:3], s[4:5], 2
	s_add_u32 s0, s0, s2
	ds_load_b32 v1, v0
	s_addc_u32 s1, s1, s3
	s_waitcnt lgkmcnt(0)
	global_store_b32 v0, v1, s[0:1]
.LBB2_7:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z14reduce_kernel2PiS_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 4
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_Z14reduce_kernel2PiS_, .Lfunc_end2-_Z14reduce_kernel2PiS_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 280
; NumSgprs: 18
; NumVgprs: 4
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 4
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z14reduce_kernel3PiS_  ; -- Begin function _Z14reduce_kernel3PiS_
	.globl	_Z14reduce_kernel3PiS_
	.p2align	8
	.type	_Z14reduce_kernel3PiS_,@function
_Z14reduce_kernel3PiS_:                 ; @_Z14reduce_kernel3PiS_
; %bb.0:
	s_clause 0x1
	s_load_b32 s5, s[0:1], 0x1c
	s_load_b128 s[0:3], s[0:1], 0x0
	s_mov_b32 s4, s15
	s_waitcnt lgkmcnt(0)
	s_and_b32 s5, s5, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	s_mul_i32 s6, s15, s5
	s_cmp_lt_u32 s5, 2
	v_lshl_add_u32 v1, s6, 1, v0
	v_mov_b32_e32 v2, 0
	v_lshlrev_b64 v[3:4], 2, v[1:2]
	v_add_nc_u32_e32 v1, s5, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v3, vcc_lo, s2, v3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
	v_add_co_u32 v1, vcc_lo, s2, v1
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
	s_clause 0x1
	global_load_b32 v3, v[3:4], off
	global_load_b32 v2, v[1:2], off
	v_lshl_add_u32 v1, v0, 2, 0
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v2, v2, v3
	ds_store_b32 v1, v2
	s_waitcnt lgkmcnt(0)
	s_barrier
.LBB3_1:                                ; =>This Inner Loop Header: Depth=1
	buffer_gl0_inv
	s_cbranch_scc1 .LBB3_5
; %bb.2:                                ; %.lr.ph
                                        ;   in Loop: Header=BB3_1 Depth=1
	s_lshr_b32 s2, s5, 1
	s_mov_b32 s3, exec_lo
	v_cmpx_gt_u32_e64 s2, v0
	s_cbranch_execz .LBB3_4
; %bb.3:                                ;   in Loop: Header=BB3_1 Depth=1
	v_lshl_add_u32 v2, s2, 2, v1
	ds_load_b32 v2, v2
	ds_load_b32 v3, v1
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v2, v3, v2
	ds_store_b32 v1, v2
.LBB3_4:                                ;   in Loop: Header=BB3_1 Depth=1
	s_or_b32 exec_lo, exec_lo, s3
	s_waitcnt lgkmcnt(0)
	s_barrier
	s_cmp_lt_u32 s5, 4
	s_mov_b32 s5, s2
	s_branch .LBB3_1
.LBB3_5:                                ; %._crit_edge
	s_mov_b32 s2, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB3_7
; %bb.6:
	v_mov_b32_e32 v0, 0
	s_mov_b32 s5, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[2:3], s[4:5], 2
	s_add_u32 s0, s0, s2
	ds_load_b32 v1, v0
	s_addc_u32 s1, s1, s3
	s_waitcnt lgkmcnt(0)
	global_store_b32 v0, v1, s[0:1]
.LBB3_7:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z14reduce_kernel3PiS_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 5
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end3:
	.size	_Z14reduce_kernel3PiS_, .Lfunc_end3-_Z14reduce_kernel3PiS_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 332
; NumSgprs: 18
; NumVgprs: 5
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 5
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         20
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         28
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         30
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         32
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         34
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         36
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         38
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         56
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         80
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         136
        .size:           4
        .value_kind:     hidden_dynamic_lds_size
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 272
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z14reduce_kernel0PiS_
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z14reduce_kernel0PiS_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     4
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         20
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         28
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         30
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         32
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         34
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         36
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         38
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         56
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         80
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         136
        .size:           4
        .value_kind:     hidden_dynamic_lds_size
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 272
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z14reduce_kernel1PiS_
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z14reduce_kernel1PiS_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     5
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         20
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         28
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         30
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         32
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         34
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         36
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         38
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         56
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         80
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         136
        .size:           4
        .value_kind:     hidden_dynamic_lds_size
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 272
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z14reduce_kernel2PiS_
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z14reduce_kernel2PiS_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     4
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         20
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         28
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         30
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         32
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         34
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         36
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         38
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         56
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         80
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         136
        .size:           4
        .value_kind:     hidden_dynamic_lds_size
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 272
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z14reduce_kernel3PiS_
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z14reduce_kernel3PiS_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     5
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
