/******************************************************************************************/
///功能：图片缩小两倍
/*  函数名                         线程块大小       耗费时间
 *  kernel_halfsize1              [32,4,1]      639.142us
 *  kernel_halfsizebyshare1       [32,4,1]      654.107us
 *  kernel_halfsize               [32,8,1]      639.56us
 *  kernel_halfsizebyshare        [32,4,1]      687.768us
 */
/******************************************************************************************/

#include <cuda_runtime.h>
#include <cstdio>
#include <iostream>
/**
 * @property    图像缩放
 * @func        将图像缩小为原图两倍　 像素点为(2*y,2*x)(2*y,2*x+1)(2*y+1,2*x)(2*y+1,2*x+1)的平均值
 *                                 若最后一行或最后一列为奇数列．则越界部分再取最后一行或最后一列
 * @param_out   out_image          放大后的图像首地址
 * @param_in    in_image           待放大图像首地址
 * @param_in    weight             输入图像的宽度
 * @param_in    height             输入图像的高度
 * @param_in    channels           输入图像的颜色通道数
 * 调用示例：
 * halfsize_by_cuda(&out_image->at(0),&img->at(0),img->width(),img->height(),img->channels());
 */
void halfsize_by_cuda(float * const out_image,float const  * const in_image, int const weight,int const height,int const channels);
/**********************************************************************************************************************************/
__global__ void kernel_halfsizebyshare1(float *out,float *in,int const ow,int const oh,int const iw,int const ih,int const ic)
{
    extern __shared__ float data[];
    int out_x=threadIdx.x+blockIdx.x*blockDim.x*ic*2;//输出的x维起始索引
    int out_y=threadIdx.y+blockIdx.y*blockDim.y;//输出的y位索引
    int stride=iw*ic;//输入图像的行索引的最大值

    int in_x0=blockIdx.x*blockDim.x*2*ic*2;//输入图像x维的第一起始点
    int in_y0=blockIdx.y*blockDim.y*2;//输入图像y维的第一起始点
    int in_x1=in_x0+blockDim.x*ic*2;//输入图像x维的第二起始点
    int in_y1=in_y0+blockDim.y;//输入图像y维的第二起始点

    int share_x=blockDim.x*4;//共享块内x维最大像素点个数
    for (int c = 0; c < ic*2; ++c)
    {
        int fact_x_s=threadIdx.x+blockDim.x*c;//共享内存内第一个x的索引
        int x_s=fact_x_s+blockDim.x*ic*2;//共享内存内第二个x的索引
        int y_s0=threadIdx.y*share_x*ic;//共享内存内第一个y的索引
        int y_s1=y_s0+blockDim.y*share_x*ic;//共享内存内第二个y的索引
        int fact_iw=fact_x_s%ic+stride-ic;

        int x0=min(in_x0+fact_x_s,fact_iw);
        int x1=min(in_x1+fact_x_s,fact_iw);
        int y0=min(in_y0+threadIdx.y,ih-1)*stride;
        int y1=min(in_y1+threadIdx.y,ih-1)*stride;
        data[y_s0+fact_x_s]=in[y0+x0];
        data[y_s0+x_s]=in[y0+x1];
        data[y_s1+fact_x_s]=in[y1+x0];
        data[y_s1+x_s]=in[y1+x1];
    }
    __syncthreads();
    for (int c = 0; c <ic*2 ; ++c) {
        int fact_x=out_x+blockDim.x*c;

        if(out_y<oh&&fact_x<ow*ic)
        {
            int fact_x_s=threadIdx.x+blockDim.x*c;
            int srow1=threadIdx.y*2*share_x*ic;
            int srow2=srow1+share_x*ic;
            int scol1=(fact_x_s / ic) * 2 * ic + fact_x_s % ic;
            int scol2=scol1 + ic;
            int index[4] = {srow1 + scol1,
                            srow1 + scol2,
                            srow2 + scol1,
                            srow2 + scol2};
            int out_idx = out_y * ow*ic + fact_x;
            out[out_idx] = 0.25f * (data[index[0]] + data[index[1]] + data[index[2]] + data[index[3]]);
        }
    }
}
__global__ void kernel_halfsize(float *out,float *in,int const ow,int const oh,int const iw,int const ih,int const ic)
{
    int out_x=threadIdx.x+blockIdx.x*blockDim.x*ic;
    int out_y=threadIdx.y+blockIdx.y*blockDim.y;
    int stride=iw*ic;

    for(int c=0;c<ic;c++)
    {
        int fact_x=out_x+blockDim.x*c;
        if(out_y<oh&&fact_x<ow*ic) {
            int irow1 = out_y * 2 * stride;
            int irow2 = irow1 + stride * (out_y * 2 + 1 < ih);
            int icol1 = (fact_x / ic) * 2 * ic + fact_x % ic;
            int icol2 = min((icol1 + ic), (iw * ic - ic + fact_x % ic));
            int index[4] = {irow1 + icol1,
                            irow1 + icol2,
                            irow2 + icol1,
                            irow2 + icol2};
            int out_idx = out_y * ow*ic + fact_x;
            out[out_idx] = 0.25f * (in[index[0]] + in[index[1]] + in[index[2]] + in[index[3]]);
        }

    }
}
__global__ void kernel_halfsize1(float *out,float *in,int const ow,int const oh,int const iw,int const ih,int const ic)
{
    //若需要展开ic*3重循环只需修改out_x=threadIdx.x+blockIdx.x*blockDim.x*ic*3;以及for(int c=0;c<ic*3;c++)即可，同时应修改网格大小
    int out_x=threadIdx.x+blockIdx.x*blockDim.x*ic*2;
    int out_y=threadIdx.y+blockIdx.y*blockDim.y;
    int stride=iw*ic;

    for(int c=0;c<ic*2;c++)
    {
        int fact_x=out_x+blockDim.x*c;
        if(out_y<oh&&fact_x<ow*ic) {
            int irow1 = out_y * 2 * stride;
            int irow2 = irow1 + stride * (out_y * 2 + 1 < ih);
            int icol1 = (fact_x / ic) * 2 * ic + fact_x % ic;
            int icol2 = min((icol1 + ic), (iw * ic - ic + fact_x % ic));
            int index[4] = {irow1 + icol1,
                            irow1 + icol2,
                            irow2 + icol1,
                            irow2 + icol2};
            int out_idx = out_y * ow*ic + fact_x;
            out[out_idx] = 0.25f * (in[index[0]] + in[index[1]] + in[index[2]] + in[index[3]]);
        }

    }
}
__global__ void kernel_halfsizebyshare(float *out,float *in,int const ow,int const oh,int const iw,int const ih,int const ic)
{
    extern __shared__ float data[];
    int out_x=threadIdx.x+blockIdx.x*blockDim.x*ic;//输出的x维起始索引
    int out_y=threadIdx.y+blockIdx.y*blockDim.y;//输出的y位索引
    int stride=iw*ic;//输入图像的行索引的最大值

    int in_x0=blockIdx.x*blockDim.x*2*ic;//输入图像x维的起始点
    int in_y0=blockIdx.y*blockDim.y*2;//输入图像y维的起始点
    int in_x1=in_x0+blockDim.x*ic;
    int in_y1=in_y0+blockDim.y;

    int share_x=blockDim.x*2;//共享块内x维最大像素点个数
    for (int c = 0; c < ic; ++c)
    {
        int fact_x_s=threadIdx.x+blockDim.x*c;
        int x_s=fact_x_s+blockDim.x*ic;
        int y_s0=threadIdx.y*share_x*ic;
        int y_s1=y_s0+blockDim.y*share_x*ic;
        int fact_iw=fact_x_s%ic+stride-ic;
        int x0=min(in_x0+fact_x_s,fact_iw);
        int x1=min(in_x1+fact_x_s,fact_iw);
        int y0=min(in_y0+threadIdx.y,ih-1)*stride;
        int y1=min(in_y1+threadIdx.y,ih-1)*stride;
        data[y_s0+fact_x_s]=in[y0+x0];
        data[y_s0+x_s]=in[y0+x1];
        data[y_s1+fact_x_s]=in[y1+x0];
        data[y_s1+x_s]=in[y1+x1];
    }
    __syncthreads();
    for (int c = 0; c <ic ; ++c)
    {
        int fact_x=out_x+blockDim.x*c;

        if(out_y<oh&&fact_x<ow*ic)
        {
            int fact_x_s=threadIdx.x+blockDim.x*c;
            int srow1=threadIdx.y*2*share_x*ic;
            int srow2=srow1+share_x*ic;
            int scol1=(fact_x_s / ic) * 2 * ic + fact_x_s % ic;
            int scol2=scol1 + ic;
            int index[4] = {srow1 + scol1,
                            srow1 + scol2,
                            srow2 + scol1,
                            srow2 + scol2};
            int out_idx = out_y * ow*ic + fact_x;
            out[out_idx] = 0.25f * (data[index[0]] + data[index[1]] + data[index[2]] + data[index[3]]);
        }
    }
}

void halfsize_by_cuda(float * const out_image,float const  * const in_image, int const weight,int const height,int const channels)
{
    int ow=(weight+1)>>1;
    int oh=(height+1)>>1;
    int const size_in=weight*height;
    int const size_out=ow*oh;
    int const bytes_in=size_in*channels* sizeof(float);
    int const bytes_out=size_out*channels* sizeof(float);

    float *d_in=NULL;
    float *d_out=NULL;
    cudaMalloc((void**)&d_in,bytes_in);
    cudaMalloc((void**)&d_out,bytes_out);

    int const  x=32;
    int const  y=4;
    int const   share_x=x*4;
    int const   share_y=y*2;
    dim3 block (x,y,1);
    dim3 grid ((ow-1+x*2)/(x*2),(oh-1+y)/y,1);
    cudaMemcpy(d_in,in_image,bytes_in,cudaMemcpyHostToDevice);
    kernel_halfsizebyshare1<<<grid,block,share_x*share_y*channels* sizeof(float)>>>(d_out,d_in,ow,oh,weight,height,channels);
    cudaMemcpy(out_image,d_out,bytes_out,cudaMemcpyDeviceToHost);
    cudaFree(d_in);
    cudaFree(d_out);
}


	.file	"tmpxft_003280e3_00000000-6_halfsize.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3638:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3638:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z50__device_stub__Z23kernel_halfsizebyshare1PfS_iiiiiPfS_iiiii
	.type	_Z50__device_stub__Z23kernel_halfsizebyshare1PfS_iiiiiPfS_iiiii, @function
_Z50__device_stub__Z23kernel_halfsizebyshare1PfS_iiiiiPfS_iiiii:
.LFB3660:
	.cfi_startproc
	endbr64
	subq	$168, %rsp
	.cfi_def_cfa_offset 176
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	32(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	40(%rsp), %rcx
	movl	%r8d, 4(%rsp)
	movl	%r9d, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 152(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 128(%rsp)
	movq	%rsp, %rax
	movq	%rax, 136(%rsp)
	leaq	176(%rsp), %rax
	movq	%rax, 144(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	40(%rsp)
	.cfi_def_cfa_offset 184
	leaq	_Z23kernel_halfsizebyshare1PfS_iiiii(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 192
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 184
	popq	%rdx
	.cfi_def_cfa_offset 176
.L2:
	movq	152(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$168, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3660:
	.size	_Z50__device_stub__Z23kernel_halfsizebyshare1PfS_iiiiiPfS_iiiii, .-_Z50__device_stub__Z23kernel_halfsizebyshare1PfS_iiiiiPfS_iiiii
	.globl	_Z23kernel_halfsizebyshare1PfS_iiiii
	.type	_Z23kernel_halfsizebyshare1PfS_iiiii, @function
_Z23kernel_halfsizebyshare1PfS_iiiii:
.LFB3661:
	.cfi_startproc
	endbr64
	jmp	_Z50__device_stub__Z23kernel_halfsizebyshare1PfS_iiiiiPfS_iiiii
	.cfi_endproc
.LFE3661:
	.size	_Z23kernel_halfsizebyshare1PfS_iiiii, .-_Z23kernel_halfsizebyshare1PfS_iiiii
	.globl	_Z16halfsize_by_cudaPfPKfiii
	.type	_Z16halfsize_by_cudaPfPKfiii, @function
_Z16halfsize_by_cudaPfPKfiii:
.LFB3635:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movl	%edx, %r15d
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	leal	1(%rcx), %r14d
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	leal	1(%rdx), %r13d
	sarl	%r14d
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	sarl	%r13d
	movl	%r8d, %r12d
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movl	%edx, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	imull	%ecx, %ebp
	movl	%r13d, %ebx
	imull	%r14d, %ebx
	imull	%r8d, %ebp
	subq	$88, %rsp
	.cfi_def_cfa_offset 144
	imull	%r12d, %ebx
	movq	%rdi, 8(%rsp)
	leaq	32(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	xorl	%esi, %esi
	sall	$2, %ebp
	movslq	%ebp, %rbp
	sall	$2, %ebx
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	xorl	%eax, %eax
	movslq	%ebx, %rbx
	movq	%rsi, 32(%rsp)
	movq	%rsi, 40(%rsp)
	movq	%rbp, %rsi
	movl	%ecx, 28(%rsp)
	call	cudaMalloc@PLT
	leaq	40(%rsp), %rdi
	movq	%rbx, %rsi
	call	cudaMalloc@PLT
	movl	$536870913, %eax
	movl	$64, %ecx
	movq	16(%rsp), %rsi
	salq	$5, %rax
	movq	32(%rsp), %rdi
	movl	$1, 56(%rsp)
	movq	%rax, 48(%rsp)
	leal	63(%r13), %eax
	cltd
	movl	$1, 68(%rsp)
	idivl	%ecx
	movl	$4, %ecx
	movl	%eax, 60(%rsp)
	leal	3(%r14), %eax
	cltd
	idivl	%ecx
	movl	$1, %ecx
	movq	%rbp, %rdx
	movl	%eax, 64(%rsp)
	call	cudaMemcpy@PLT
	movl	%r12d, %eax
	movl	56(%rsp), %ecx
	movl	68(%rsp), %esi
	sall	$10, %eax
	movq	48(%rsp), %rdx
	movq	60(%rsp), %rdi
	xorl	%r9d, %r9d
	cltq
	leaq	0(,%rax,4), %r8
	call	__cudaPushCallConfiguration@PLT
	movl	28(%rsp), %r11d
	testl	%eax, %eax
	jne	.L9
	pushq	%rax
	.cfi_def_cfa_offset 152
	movl	%r14d, %ecx
	movl	%r13d, %edx
	movl	%r11d, %r9d
	pushq	%r12
	.cfi_def_cfa_offset 160
	movq	48(%rsp), %rsi
	movl	%r15d, %r8d
	movq	56(%rsp), %rdi
	call	_Z50__device_stub__Z23kernel_halfsizebyshare1PfS_iiiiiPfS_iiiii
	popq	%rdx
	.cfi_def_cfa_offset 152
	popq	%rcx
	.cfi_def_cfa_offset 144
.L9:
	movq	40(%rsp), %rsi
	movq	8(%rsp), %rdi
	movl	$2, %ecx
	movq	%rbx, %rdx
	call	cudaMemcpy@PLT
	movq	32(%rsp), %rdi
	call	cudaFree@PLT
	movq	40(%rsp), %rdi
	call	cudaFree@PLT
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L10
	call	__stack_chk_fail@PLT
.L10:
	addq	$88, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3635:
	.size	_Z16halfsize_by_cudaPfPKfiii, .-_Z16halfsize_by_cudaPfPKfiii
	.globl	_Z42__device_stub__Z15kernel_halfsizePfS_iiiiiPfS_iiiii
	.type	_Z42__device_stub__Z15kernel_halfsizePfS_iiiiiPfS_iiiii, @function
_Z42__device_stub__Z15kernel_halfsizePfS_iiiiiPfS_iiiii:
.LFB3662:
	.cfi_startproc
	endbr64
	subq	$168, %rsp
	.cfi_def_cfa_offset 176
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	32(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	40(%rsp), %rcx
	movl	%r8d, 4(%rsp)
	movl	%r9d, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 152(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 128(%rsp)
	movq	%rsp, %rax
	movq	%rax, 136(%rsp)
	leaq	176(%rsp), %rax
	movq	%rax, 144(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L12
	pushq	40(%rsp)
	.cfi_def_cfa_offset 184
	leaq	_Z15kernel_halfsizePfS_iiiii(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 192
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 184
	popq	%rdx
	.cfi_def_cfa_offset 176
.L12:
	movq	152(%rsp), %rax
	subq	%fs:40, %rax
	je	.L14
	call	__stack_chk_fail@PLT
.L14:
	addq	$168, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3662:
	.size	_Z42__device_stub__Z15kernel_halfsizePfS_iiiiiPfS_iiiii, .-_Z42__device_stub__Z15kernel_halfsizePfS_iiiiiPfS_iiiii
	.globl	_Z15kernel_halfsizePfS_iiiii
	.type	_Z15kernel_halfsizePfS_iiiii, @function
_Z15kernel_halfsizePfS_iiiii:
.LFB3663:
	.cfi_startproc
	endbr64
	jmp	_Z42__device_stub__Z15kernel_halfsizePfS_iiiiiPfS_iiiii
	.cfi_endproc
.LFE3663:
	.size	_Z15kernel_halfsizePfS_iiiii, .-_Z15kernel_halfsizePfS_iiiii
	.globl	_Z43__device_stub__Z16kernel_halfsize1PfS_iiiiiPfS_iiiii
	.type	_Z43__device_stub__Z16kernel_halfsize1PfS_iiiiiPfS_iiiii, @function
_Z43__device_stub__Z16kernel_halfsize1PfS_iiiiiPfS_iiiii:
.LFB3664:
	.cfi_startproc
	endbr64
	subq	$168, %rsp
	.cfi_def_cfa_offset 176
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	32(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	40(%rsp), %rcx
	movl	%r8d, 4(%rsp)
	movl	%r9d, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 152(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 128(%rsp)
	movq	%rsp, %rax
	movq	%rax, 136(%rsp)
	leaq	176(%rsp), %rax
	movq	%rax, 144(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L17
	pushq	40(%rsp)
	.cfi_def_cfa_offset 184
	leaq	_Z16kernel_halfsize1PfS_iiiii(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 192
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 184
	popq	%rdx
	.cfi_def_cfa_offset 176
.L17:
	movq	152(%rsp), %rax
	subq	%fs:40, %rax
	je	.L19
	call	__stack_chk_fail@PLT
.L19:
	addq	$168, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3664:
	.size	_Z43__device_stub__Z16kernel_halfsize1PfS_iiiiiPfS_iiiii, .-_Z43__device_stub__Z16kernel_halfsize1PfS_iiiiiPfS_iiiii
	.globl	_Z16kernel_halfsize1PfS_iiiii
	.type	_Z16kernel_halfsize1PfS_iiiii, @function
_Z16kernel_halfsize1PfS_iiiii:
.LFB3665:
	.cfi_startproc
	endbr64
	jmp	_Z43__device_stub__Z16kernel_halfsize1PfS_iiiiiPfS_iiiii
	.cfi_endproc
.LFE3665:
	.size	_Z16kernel_halfsize1PfS_iiiii, .-_Z16kernel_halfsize1PfS_iiiii
	.globl	_Z49__device_stub__Z22kernel_halfsizebysharePfS_iiiiiPfS_iiiii
	.type	_Z49__device_stub__Z22kernel_halfsizebysharePfS_iiiiiPfS_iiiii, @function
_Z49__device_stub__Z22kernel_halfsizebysharePfS_iiiiiPfS_iiiii:
.LFB3666:
	.cfi_startproc
	endbr64
	subq	$168, %rsp
	.cfi_def_cfa_offset 176
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	32(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	40(%rsp), %rcx
	movl	%r8d, 4(%rsp)
	movl	%r9d, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 152(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 128(%rsp)
	movq	%rsp, %rax
	movq	%rax, 136(%rsp)
	leaq	176(%rsp), %rax
	movq	%rax, 144(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L22
	pushq	40(%rsp)
	.cfi_def_cfa_offset 184
	leaq	_Z22kernel_halfsizebysharePfS_iiiii(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 192
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 184
	popq	%rdx
	.cfi_def_cfa_offset 176
.L22:
	movq	152(%rsp), %rax
	subq	%fs:40, %rax
	je	.L24
	call	__stack_chk_fail@PLT
.L24:
	addq	$168, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3666:
	.size	_Z49__device_stub__Z22kernel_halfsizebysharePfS_iiiiiPfS_iiiii, .-_Z49__device_stub__Z22kernel_halfsizebysharePfS_iiiiiPfS_iiiii
	.globl	_Z22kernel_halfsizebysharePfS_iiiii
	.type	_Z22kernel_halfsizebysharePfS_iiiii, @function
_Z22kernel_halfsizebysharePfS_iiiii:
.LFB3667:
	.cfi_startproc
	endbr64
	jmp	_Z49__device_stub__Z22kernel_halfsizebysharePfS_iiiiiPfS_iiiii
	.cfi_endproc
.LFE3667:
	.size	_Z22kernel_halfsizebysharePfS_iiiii, .-_Z22kernel_halfsizebysharePfS_iiiii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z22kernel_halfsizebysharePfS_iiiii"
.LC1:
	.string	"_Z16kernel_halfsize1PfS_iiiii"
.LC2:
	.string	"_Z15kernel_halfsizePfS_iiiii"
.LC3:
	.string	"_Z23kernel_halfsizebyshare1PfS_iiiii"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3669:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z22kernel_halfsizebysharePfS_iiiii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC1(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z16kernel_halfsize1PfS_iiiii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC2(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z15kernel_halfsizePfS_iiiii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC3(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z23kernel_halfsizebyshare1PfS_iiiii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3669:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

/******************************************************************************************/
///功能：图片缩小两倍
/*  函数名                         线程块大小       耗费时间
 *  kernel_halfsize1              [32,4,1]      639.142us
 *  kernel_halfsizebyshare1       [32,4,1]      654.107us
 *  kernel_halfsize               [32,8,1]      639.56us
 *  kernel_halfsizebyshare        [32,4,1]      687.768us
 */
/******************************************************************************************/

#include <hip/hip_runtime.h>
#include <cstdio>
#include <iostream>
/**
 * @property    图像缩放
 * @func        将图像缩小为原图两倍　 像素点为(2*y,2*x)(2*y,2*x+1)(2*y+1,2*x)(2*y+1,2*x+1)的平均值
 *                                 若最后一行或最后一列为奇数列．则越界部分再取最后一行或最后一列
 * @param_out   out_image          放大后的图像首地址
 * @param_in    in_image           待放大图像首地址
 * @param_in    weight             输入图像的宽度
 * @param_in    height             输入图像的高度
 * @param_in    channels           输入图像的颜色通道数
 * 调用示例：
 * halfsize_by_cuda(&out_image->at(0),&img->at(0),img->width(),img->height(),img->channels());
 */
void halfsize_by_cuda(float * const out_image,float const  * const in_image, int const weight,int const height,int const channels);
/**********************************************************************************************************************************/
__global__ void kernel_halfsizebyshare1(float *out,float *in,int const ow,int const oh,int const iw,int const ih,int const ic)
{
    extern __shared__ float data[];
    int out_x=threadIdx.x+blockIdx.x*blockDim.x*ic*2;//输出的x维起始索引
    int out_y=threadIdx.y+blockIdx.y*blockDim.y;//输出的y位索引
    int stride=iw*ic;//输入图像的行索引的最大值

    int in_x0=blockIdx.x*blockDim.x*2*ic*2;//输入图像x维的第一起始点
    int in_y0=blockIdx.y*blockDim.y*2;//输入图像y维的第一起始点
    int in_x1=in_x0+blockDim.x*ic*2;//输入图像x维的第二起始点
    int in_y1=in_y0+blockDim.y;//输入图像y维的第二起始点

    int share_x=blockDim.x*4;//共享块内x维最大像素点个数
    for (int c = 0; c < ic*2; ++c)
    {
        int fact_x_s=threadIdx.x+blockDim.x*c;//共享内存内第一个x的索引
        int x_s=fact_x_s+blockDim.x*ic*2;//共享内存内第二个x的索引
        int y_s0=threadIdx.y*share_x*ic;//共享内存内第一个y的索引
        int y_s1=y_s0+blockDim.y*share_x*ic;//共享内存内第二个y的索引
        int fact_iw=fact_x_s%ic+stride-ic;

        int x0=min(in_x0+fact_x_s,fact_iw);
        int x1=min(in_x1+fact_x_s,fact_iw);
        int y0=min(in_y0+threadIdx.y,ih-1)*stride;
        int y1=min(in_y1+threadIdx.y,ih-1)*stride;
        data[y_s0+fact_x_s]=in[y0+x0];
        data[y_s0+x_s]=in[y0+x1];
        data[y_s1+fact_x_s]=in[y1+x0];
        data[y_s1+x_s]=in[y1+x1];
    }
    __syncthreads();
    for (int c = 0; c <ic*2 ; ++c) {
        int fact_x=out_x+blockDim.x*c;

        if(out_y<oh&&fact_x<ow*ic)
        {
            int fact_x_s=threadIdx.x+blockDim.x*c;
            int srow1=threadIdx.y*2*share_x*ic;
            int srow2=srow1+share_x*ic;
            int scol1=(fact_x_s / ic) * 2 * ic + fact_x_s % ic;
            int scol2=scol1 + ic;
            int index[4] = {srow1 + scol1,
                            srow1 + scol2,
                            srow2 + scol1,
                            srow2 + scol2};
            int out_idx = out_y * ow*ic + fact_x;
            out[out_idx] = 0.25f * (data[index[0]] + data[index[1]] + data[index[2]] + data[index[3]]);
        }
    }
}
__global__ void kernel_halfsize(float *out,float *in,int const ow,int const oh,int const iw,int const ih,int const ic)
{
    int out_x=threadIdx.x+blockIdx.x*blockDim.x*ic;
    int out_y=threadIdx.y+blockIdx.y*blockDim.y;
    int stride=iw*ic;

    for(int c=0;c<ic;c++)
    {
        int fact_x=out_x+blockDim.x*c;
        if(out_y<oh&&fact_x<ow*ic) {
            int irow1 = out_y * 2 * stride;
            int irow2 = irow1 + stride * (out_y * 2 + 1 < ih);
            int icol1 = (fact_x / ic) * 2 * ic + fact_x % ic;
            int icol2 = min((icol1 + ic), (iw * ic - ic + fact_x % ic));
            int index[4] = {irow1 + icol1,
                            irow1 + icol2,
                            irow2 + icol1,
                            irow2 + icol2};
            int out_idx = out_y * ow*ic + fact_x;
            out[out_idx] = 0.25f * (in[index[0]] + in[index[1]] + in[index[2]] + in[index[3]]);
        }

    }
}
__global__ void kernel_halfsize1(float *out,float *in,int const ow,int const oh,int const iw,int const ih,int const ic)
{
    //若需要展开ic*3重循环只需修改out_x=threadIdx.x+blockIdx.x*blockDim.x*ic*3;以及for(int c=0;c<ic*3;c++)即可，同时应修改网格大小
    int out_x=threadIdx.x+blockIdx.x*blockDim.x*ic*2;
    int out_y=threadIdx.y+blockIdx.y*blockDim.y;
    int stride=iw*ic;

    for(int c=0;c<ic*2;c++)
    {
        int fact_x=out_x+blockDim.x*c;
        if(out_y<oh&&fact_x<ow*ic) {
            int irow1 = out_y * 2 * stride;
            int irow2 = irow1 + stride * (out_y * 2 + 1 < ih);
            int icol1 = (fact_x / ic) * 2 * ic + fact_x % ic;
            int icol2 = min((icol1 + ic), (iw * ic - ic + fact_x % ic));
            int index[4] = {irow1 + icol1,
                            irow1 + icol2,
                            irow2 + icol1,
                            irow2 + icol2};
            int out_idx = out_y * ow*ic + fact_x;
            out[out_idx] = 0.25f * (in[index[0]] + in[index[1]] + in[index[2]] + in[index[3]]);
        }

    }
}
__global__ void kernel_halfsizebyshare(float *out,float *in,int const ow,int const oh,int const iw,int const ih,int const ic)
{
    extern __shared__ float data[];
    int out_x=threadIdx.x+blockIdx.x*blockDim.x*ic;//输出的x维起始索引
    int out_y=threadIdx.y+blockIdx.y*blockDim.y;//输出的y位索引
    int stride=iw*ic;//输入图像的行索引的最大值

    int in_x0=blockIdx.x*blockDim.x*2*ic;//输入图像x维的起始点
    int in_y0=blockIdx.y*blockDim.y*2;//输入图像y维的起始点
    int in_x1=in_x0+blockDim.x*ic;
    int in_y1=in_y0+blockDim.y;

    int share_x=blockDim.x*2;//共享块内x维最大像素点个数
    for (int c = 0; c < ic; ++c)
    {
        int fact_x_s=threadIdx.x+blockDim.x*c;
        int x_s=fact_x_s+blockDim.x*ic;
        int y_s0=threadIdx.y*share_x*ic;
        int y_s1=y_s0+blockDim.y*share_x*ic;
        int fact_iw=fact_x_s%ic+stride-ic;
        int x0=min(in_x0+fact_x_s,fact_iw);
        int x1=min(in_x1+fact_x_s,fact_iw);
        int y0=min(in_y0+threadIdx.y,ih-1)*stride;
        int y1=min(in_y1+threadIdx.y,ih-1)*stride;
        data[y_s0+fact_x_s]=in[y0+x0];
        data[y_s0+x_s]=in[y0+x1];
        data[y_s1+fact_x_s]=in[y1+x0];
        data[y_s1+x_s]=in[y1+x1];
    }
    __syncthreads();
    for (int c = 0; c <ic ; ++c)
    {
        int fact_x=out_x+blockDim.x*c;

        if(out_y<oh&&fact_x<ow*ic)
        {
            int fact_x_s=threadIdx.x+blockDim.x*c;
            int srow1=threadIdx.y*2*share_x*ic;
            int srow2=srow1+share_x*ic;
            int scol1=(fact_x_s / ic) * 2 * ic + fact_x_s % ic;
            int scol2=scol1 + ic;
            int index[4] = {srow1 + scol1,
                            srow1 + scol2,
                            srow2 + scol1,
                            srow2 + scol2};
            int out_idx = out_y * ow*ic + fact_x;
            out[out_idx] = 0.25f * (data[index[0]] + data[index[1]] + data[index[2]] + data[index[3]]);
        }
    }
}

void halfsize_by_cuda(float * const out_image,float const  * const in_image, int const weight,int const height,int const channels)
{
    int ow=(weight+1)>>1;
    int oh=(height+1)>>1;
    int const size_in=weight*height;
    int const size_out=ow*oh;
    int const bytes_in=size_in*channels* sizeof(float);
    int const bytes_out=size_out*channels* sizeof(float);

    float *d_in=NULL;
    float *d_out=NULL;
    hipMalloc((void**)&d_in,bytes_in);
    hipMalloc((void**)&d_out,bytes_out);

    int const  x=32;
    int const  y=4;
    int const   share_x=x*4;
    int const   share_y=y*2;
    dim3 block (x,y,1);
    dim3 grid ((ow-1+x*2)/(x*2),(oh-1+y)/y,1);
    hipMemcpy(d_in,in_image,bytes_in,hipMemcpyHostToDevice);
    kernel_halfsizebyshare1<<<grid,block,share_x*share_y*channels* sizeof(float)>>>(d_out,d_in,ow,oh,weight,height,channels);
    hipMemcpy(out_image,d_out,bytes_out,hipMemcpyDeviceToHost);
    hipFree(d_in);
    hipFree(d_out);
}


	.text
	.file	"halfsize.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z38__device_stub__kernel_halfsizebyshare1PfS_iiiii # -- Begin function _Z38__device_stub__kernel_halfsizebyshare1PfS_iiiii
	.type	_Z38__device_stub__kernel_halfsizebyshare1PfS_iiiii,@function
_Z38__device_stub__kernel_halfsizebyshare1PfS_iiiii: # @_Z38__device_stub__kernel_halfsizebyshare1PfS_iiiii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	4(%rsp), %rcx
	movl	%r8d, (%rcx)
	movq	%rsp, %r8
	movl	%r9d, (%r8)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	192(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z23kernel_halfsizebyshare1PfS_iiiii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z38__device_stub__kernel_halfsizebyshare1PfS_iiiii, .Lfunc_end0-_Z38__device_stub__kernel_halfsizebyshare1PfS_iiiii
	.cfi_endproc
                                        # -- End function
	.globl	_Z30__device_stub__kernel_halfsizePfS_iiiii # -- Begin function _Z30__device_stub__kernel_halfsizePfS_iiiii
	.type	_Z30__device_stub__kernel_halfsizePfS_iiiii,@function
_Z30__device_stub__kernel_halfsizePfS_iiiii: # @_Z30__device_stub__kernel_halfsizePfS_iiiii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	4(%rsp), %rcx
	movl	%r8d, (%rcx)
	movq	%rsp, %r8
	movl	%r9d, (%r8)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	192(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z15kernel_halfsizePfS_iiiii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z30__device_stub__kernel_halfsizePfS_iiiii, .Lfunc_end1-_Z30__device_stub__kernel_halfsizePfS_iiiii
	.cfi_endproc
                                        # -- End function
	.globl	_Z31__device_stub__kernel_halfsize1PfS_iiiii # -- Begin function _Z31__device_stub__kernel_halfsize1PfS_iiiii
	.type	_Z31__device_stub__kernel_halfsize1PfS_iiiii,@function
_Z31__device_stub__kernel_halfsize1PfS_iiiii: # @_Z31__device_stub__kernel_halfsize1PfS_iiiii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	4(%rsp), %rcx
	movl	%r8d, (%rcx)
	movq	%rsp, %r8
	movl	%r9d, (%r8)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	192(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z16kernel_halfsize1PfS_iiiii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z31__device_stub__kernel_halfsize1PfS_iiiii, .Lfunc_end2-_Z31__device_stub__kernel_halfsize1PfS_iiiii
	.cfi_endproc
                                        # -- End function
	.globl	_Z37__device_stub__kernel_halfsizebysharePfS_iiiii # -- Begin function _Z37__device_stub__kernel_halfsizebysharePfS_iiiii
	.type	_Z37__device_stub__kernel_halfsizebysharePfS_iiiii,@function
_Z37__device_stub__kernel_halfsizebysharePfS_iiiii: # @_Z37__device_stub__kernel_halfsizebysharePfS_iiiii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	4(%rsp), %rcx
	movl	%r8d, (%rcx)
	movq	%rsp, %r8
	movl	%r9d, (%r8)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	192(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z22kernel_halfsizebysharePfS_iiiii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	_Z37__device_stub__kernel_halfsizebysharePfS_iiiii, .Lfunc_end3-_Z37__device_stub__kernel_halfsizebysharePfS_iiiii
	.cfi_endproc
                                        # -- End function
	.globl	_Z16halfsize_by_cudaPfPKfiii    # -- Begin function _Z16halfsize_by_cudaPfPKfiii
	.type	_Z16halfsize_by_cudaPfPKfiii,@function
_Z16halfsize_by_cudaPfPKfiii:           # @_Z16halfsize_by_cudaPfPKfiii
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$56, %rsp
	.cfi_def_cfa_offset 112
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%r8d, %ebp
                                        # kill: def $ecx killed $ecx def $rcx
                                        # kill: def $edx killed $edx def $rdx
	movq	%rsi, 40(%rsp)                  # 8-byte Spill
	movq	%rdi, 48(%rsp)                  # 8-byte Spill
	leal	1(%rdx), %r12d
	sarl	%r12d
	leal	1(%rcx), %r13d
	sarl	%r13d
	movq	%rdx, 24(%rsp)                  # 8-byte Spill
	movl	%edx, %eax
	movq	%rcx, 32(%rsp)                  # 8-byte Spill
	imull	%ecx, %eax
	imull	%r8d, %eax
	shll	$2, %eax
	movl	%r12d, %r15d
	imull	%r8d, %r15d
	imull	%r13d, %r15d
	shll	$2, %r15d
	xorl	%ecx, %ecx
	leaq	16(%rsp), %rdi
	movq	%rcx, (%rdi)
	leaq	8(%rsp), %rbx
	movq	%rcx, (%rbx)
	movslq	%eax, %r14
	movq	%r14, %rsi
	callq	hipMalloc
	movslq	%r15d, %r15
	movq	%rbx, %rdi
	movq	%r15, %rsi
	callq	hipMalloc
	leal	63(%r12), %eax
	leal	126(%r12), %ecx
	testl	%eax, %eax
	cmovnsl	%eax, %ecx
	sarl	$6, %ecx
	leal	3(%r13), %eax
	leal	6(%r13), %ebx
	testl	%eax, %eax
	cmovnsl	%eax, %ebx
	sarl	$2, %ebx
	shlq	$32, %rbx
	orq	%rcx, %rbx
	leaq	16(%rsp), %rax
	movq	(%rax), %rdi
	movq	40(%rsp), %rsi                  # 8-byte Reload
	movq	%r14, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	movl	%ebp, %eax
	shll	$10, %eax
	movslq	%eax, %r8
	shlq	$2, %r8
	movabsq	$17179869216, %rdx              # imm = 0x400000020
	movq	%rbx, %rdi
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB4_2
# %bb.1:
	movq	8(%rsp), %rdi
	movq	16(%rsp), %rsi
	movl	%ebp, (%rsp)
	movl	%r12d, %edx
	movl	%r13d, %ecx
	movq	24(%rsp), %r8                   # 8-byte Reload
                                        # kill: def $r8d killed $r8d killed $r8
	movq	32(%rsp), %r9                   # 8-byte Reload
                                        # kill: def $r9d killed $r9d killed $r9
	callq	_Z38__device_stub__kernel_halfsizebyshare1PfS_iiiii
.LBB4_2:
	movq	8(%rsp), %rsi
	movq	48(%rsp), %rdi                  # 8-byte Reload
	movq	%r15, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	movq	16(%rsp), %rdi
	callq	hipFree
	movq	8(%rsp), %rdi
	callq	hipFree
	addq	$56, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end4:
	.size	_Z16halfsize_by_cudaPfPKfiii, .Lfunc_end4-_Z16halfsize_by_cudaPfPKfiii
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB5_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB5_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z23kernel_halfsizebyshare1PfS_iiiii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z15kernel_halfsizePfS_iiiii, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z16kernel_halfsize1PfS_iiiii, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z22kernel_halfsizebysharePfS_iiiii, %esi
	movl	$.L__unnamed_4, %edx
	movl	$.L__unnamed_4, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end5:
	.size	__hip_module_ctor, .Lfunc_end5-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB6_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB6_2:
	retq
.Lfunc_end6:
	.size	__hip_module_dtor, .Lfunc_end6-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z23kernel_halfsizebyshare1PfS_iiiii,@object # @_Z23kernel_halfsizebyshare1PfS_iiiii
	.section	.rodata,"a",@progbits
	.globl	_Z23kernel_halfsizebyshare1PfS_iiiii
	.p2align	3, 0x0
_Z23kernel_halfsizebyshare1PfS_iiiii:
	.quad	_Z38__device_stub__kernel_halfsizebyshare1PfS_iiiii
	.size	_Z23kernel_halfsizebyshare1PfS_iiiii, 8

	.type	_Z15kernel_halfsizePfS_iiiii,@object # @_Z15kernel_halfsizePfS_iiiii
	.globl	_Z15kernel_halfsizePfS_iiiii
	.p2align	3, 0x0
_Z15kernel_halfsizePfS_iiiii:
	.quad	_Z30__device_stub__kernel_halfsizePfS_iiiii
	.size	_Z15kernel_halfsizePfS_iiiii, 8

	.type	_Z16kernel_halfsize1PfS_iiiii,@object # @_Z16kernel_halfsize1PfS_iiiii
	.globl	_Z16kernel_halfsize1PfS_iiiii
	.p2align	3, 0x0
_Z16kernel_halfsize1PfS_iiiii:
	.quad	_Z31__device_stub__kernel_halfsize1PfS_iiiii
	.size	_Z16kernel_halfsize1PfS_iiiii, 8

	.type	_Z22kernel_halfsizebysharePfS_iiiii,@object # @_Z22kernel_halfsizebysharePfS_iiiii
	.globl	_Z22kernel_halfsizebysharePfS_iiiii
	.p2align	3, 0x0
_Z22kernel_halfsizebysharePfS_iiiii:
	.quad	_Z37__device_stub__kernel_halfsizebysharePfS_iiiii
	.size	_Z22kernel_halfsizebysharePfS_iiiii, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z23kernel_halfsizebyshare1PfS_iiiii"
	.size	.L__unnamed_1, 37

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z15kernel_halfsizePfS_iiiii"
	.size	.L__unnamed_2, 29

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z16kernel_halfsize1PfS_iiiii"
	.size	.L__unnamed_3, 30

	.type	.L__unnamed_4,@object           # @3
.L__unnamed_4:
	.asciz	"_Z22kernel_halfsizebysharePfS_iiiii"
	.size	.L__unnamed_4, 36

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z38__device_stub__kernel_halfsizebyshare1PfS_iiiii
	.addrsig_sym _Z30__device_stub__kernel_halfsizePfS_iiiii
	.addrsig_sym _Z31__device_stub__kernel_halfsize1PfS_iiiii
	.addrsig_sym _Z37__device_stub__kernel_halfsizebysharePfS_iiiii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z23kernel_halfsizebyshare1PfS_iiiii
	.addrsig_sym _Z15kernel_halfsizePfS_iiiii
	.addrsig_sym _Z16kernel_halfsize1PfS_iiiii
	.addrsig_sym _Z22kernel_halfsizebysharePfS_iiiii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z23kernel_halfsizebyshare1PfS_iiiii ; -- Begin function _Z23kernel_halfsizebyshare1PfS_iiiii
	.globl	_Z23kernel_halfsizebyshare1PfS_iiiii
	.p2align	8
	.type	_Z23kernel_halfsizebyshare1PfS_iiiii,@function
_Z23kernel_halfsizebyshare1PfS_iiiii:   ; @_Z23kernel_halfsizebyshare1PfS_iiiii
; %bb.0:
	s_clause 0x2
	s_load_b32 s3, s[0:1], 0x34
	s_load_b32 s2, s[0:1], 0x20
	s_load_b256 s[4:11], s[0:1], 0x0
	v_and_b32_e32 v1, 0x3ff, v0
	v_bfe_u32 v0, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s16, s3, 16
	s_and_b32 s1, s3, 0xffff
	s_mul_i32 s15, s15, s16
	s_mul_i32 s14, s14, s1
	s_lshl_b32 s3, s2, 1
	s_lshl_b32 s12, s1, 2
	s_lshl_b32 s0, s14, 1
	v_add_nc_u32_e32 v2, s15, v0
	s_cmp_gt_i32 s2, 0
	s_cselect_b32 s13, -1, 0
	s_cmp_lt_i32 s2, 1
	s_cbranch_scc1 .LBB0_3
; %bb.1:                                ; %.lr.ph
	v_add_nc_u32_e32 v11, s16, v0
	v_add_nc_u32_e32 v3, s15, v2
	s_add_i32 s11, s11, -1
	s_mul_i32 s16, s2, s10
	v_cvt_f64_i32_e32 v[5:6], s11
	v_lshl_add_u32 v7, s15, 1, v11
	v_cvt_f64_u32_e32 v[3:4], v3
	v_cvt_f64_i32_e32 v[9:10], s16
	s_ashr_i32 s10, s2, 31
	s_add_i32 s15, s0, s1
	v_cvt_f64_u32_e32 v[7:8], v7
	s_add_i32 s11, s2, s10
	s_mul_i32 s15, s3, s15
	s_xor_b32 s10, s11, s10
	s_sub_i32 s16, s16, s2
	s_sub_i32 s11, 0, s10
	s_max_i32 s17, s3, 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_min_f64 v[3:4], v[3:4], v[5:6]
	v_min_f64 v[5:6], v[7:8], v[5:6]
	v_cvt_f32_u32_e32 v7, s10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_rcp_iflag_f32_e32 v7, v7
	v_mul_f64 v[3:4], v[3:4], v[9:10]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_mul_f64 v[5:6], v[5:6], v[9:10]
	v_mul_lo_u32 v9, v0, s2
	v_mul_lo_u32 v10, s2, v11
	v_mul_lo_u32 v9, v9, s1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v10, v10, s1
	v_lshlrev_b32_e32 v9, 4, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b32_e32 v10, 4, v10
	v_cvt_i32_f64_e32 v3, v[3:4]
	v_cvt_i32_f64_e32 v4, v[5:6]
	v_lshl_or_b32 v6, v0, 2, 2
	v_mul_lo_u32 v6, s2, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v6, v6, s1
	v_mul_f32_e32 v5, 0x4f7ffffe, v7
	v_lshl_or_b32 v7, v11, 2, 2
	v_mul_lo_u32 v7, s2, v7
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_lshlrev_b32_e32 v6, 2, v6
	v_cvt_u32_f32_e32 v5, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mul_lo_u32 v8, s11, v5
	v_mul_lo_u32 v11, v7, s1
	v_lshl_add_u32 v7, v1, 2, 0
	s_mul_i32 s11, s3, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v8, v5, v8
	v_add_nc_u32_e32 v5, v5, v8
	s_delay_alu instid0(VALU_DEP_4)
	v_dual_mov_b32 v11, v1 :: v_dual_lshlrev_b32 v8, 2, v11
.LBB0_2:                                ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_ashrrev_i32_e32 v12, 31, v11
	v_add_nc_u32_e32 v13, s11, v11
	s_add_i32 s17, s17, -1
	s_cmp_eq_u32 s17, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v15, v11, v12
	v_xor_b32_e32 v15, v15, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v16, v15, v5
	v_mul_lo_u32 v16, v16, s10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v15, v15, v16
	v_subrev_nc_u32_e32 v16, s10, v15
	v_cmp_le_u32_e32 vcc_lo, s10, v15
	v_add_nc_u32_e32 v14, s15, v11
	v_add_nc_u32_e32 v11, s1, v11
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v15, v15, v16, vcc_lo
	v_subrev_nc_u32_e32 v16, s10, v15
	v_cmp_le_u32_e32 vcc_lo, s10, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v15, v15, v16, vcc_lo
	v_xor_b32_e32 v15, v15, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v12, v15, v12
	v_add_nc_u32_e32 v12, s16, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_min_i32_e32 v13, v13, v12
	v_min_i32_e32 v15, v14, v12
	v_add_nc_u32_e32 v12, v13, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v14, v15, v3
	v_add_nc_u32_e32 v16, v13, v4
	v_add_nc_u32_e32 v18, v15, v4
	v_ashrrev_i32_e32 v13, 31, v12
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_ashrrev_i32_e32 v15, 31, v14
	v_ashrrev_i32_e32 v17, 31, v16
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_ashrrev_i32_e32 v19, 31, v18
	v_lshlrev_b64 v[12:13], 2, v[12:13]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_lshlrev_b64 v[14:15], 2, v[14:15]
	v_lshlrev_b64 v[16:17], 2, v[16:17]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_lshlrev_b64 v[18:19], 2, v[18:19]
	v_add_co_u32 v12, vcc_lo, s6, v12
	v_add_co_ci_u32_e32 v13, vcc_lo, s7, v13, vcc_lo
	v_add_co_u32 v14, vcc_lo, s6, v14
	v_add_co_ci_u32_e32 v15, vcc_lo, s7, v15, vcc_lo
	v_add_co_u32 v16, vcc_lo, s6, v16
	v_add_co_ci_u32_e32 v17, vcc_lo, s7, v17, vcc_lo
	v_add_co_u32 v18, vcc_lo, s6, v18
	v_add_co_ci_u32_e32 v19, vcc_lo, s7, v19, vcc_lo
	s_clause 0x3
	global_load_b32 v12, v[12:13], off
	global_load_b32 v13, v[14:15], off
	global_load_b32 v14, v[16:17], off
	global_load_b32 v15, v[18:19], off
	v_add_nc_u32_e32 v16, v7, v9
	v_add_nc_u32_e32 v17, v7, v6
	v_add_nc_u32_e32 v18, v7, v10
	v_add_nc_u32_e32 v19, v7, v8
	v_add_nc_u32_e32 v7, s12, v7
	s_waitcnt vmcnt(3)
	ds_store_b32 v16, v12
	s_waitcnt vmcnt(2)
	ds_store_b32 v17, v13
	s_waitcnt vmcnt(1)
	ds_store_b32 v18, v14
	s_waitcnt vmcnt(0)
	ds_store_b32 v19, v15
	s_cbranch_scc0 .LBB0_2
.LBB0_3:                                ; %._crit_edge
	s_and_not1_b32 vcc_lo, exec_lo, s13
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_vccnz .LBB0_8
; %bb.4:                                ; %.lr.ph111
	s_ashr_i32 s6, s2, 31
	v_mad_u64_u32 v[4:5], null, s8, v2, s[0:1]
	s_add_i32 s7, s2, s6
	v_cmp_gt_i32_e32 vcc_lo, s9, v2
	s_xor_b32 s7, s7, s6
	s_mul_i32 s9, s3, s14
	v_cvt_f32_u32_e32 v3, s7
	s_sub_i32 s10, 0, s7
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v4, s2, v4
	s_mul_i32 s8, s2, s8
	v_lshlrev_b32_e32 v0, 1, v0
	v_rcp_iflag_f32_e32 v3, v3
	v_mul_u32_u24_e32 v5, s12, v0
	v_mad_u32_u24 v7, s12, v0, s12
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v0, v5, s2
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v3, 0x4f7ffffe, v3
	v_cvt_u32_f32_e32 v6, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v3, s10, v6
	s_max_i32 s10, s3, 1
	v_mul_hi_u32 v8, v6, v3
	v_mul_lo_u32 v3, v7, s2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_nc_u32_e32 v2, v6, v8
.LBB0_5:                                ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v5, s9, v1
	v_cmp_gt_i32_e64 s0, s8, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, vcc_lo, s0
	s_and_saveexec_b32 s11, s0
	s_cbranch_execz .LBB0_7
; %bb.6:                                ;   in Loop: Header=BB0_5 Depth=1
	v_ashrrev_i32_e32 v5, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v6, v1, v5
	v_xor_b32_e32 v6, v6, v5
	v_xor_b32_e32 v5, s6, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v7, v6, v2
	v_mul_lo_u32 v8, v7, s7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v6, v6, v8
	v_add_nc_u32_e32 v8, 1, v7
	v_subrev_nc_u32_e32 v9, s7, v6
	v_cmp_le_u32_e64 s0, s7, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v7, v7, v8, s0
	v_cndmask_b32_e64 v6, v6, v9, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v8, 1, v7
	v_cmp_le_u32_e64 s0, s7, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v6, v7, v8, s0
	v_xor_b32_e32 v6, v6, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v8, v6, v5
	v_mul_lo_u32 v5, v8, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v5, v1, v5
	v_mad_u64_u32 v[6:7], null, s3, v8, v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v5, s2, v6
	v_add_nc_u32_e32 v7, v6, v0
	v_add_nc_u32_e32 v6, v6, v3
	v_add_nc_u32_e32 v8, v5, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_lshl_add_u32 v7, v7, 2, 0
	v_add_nc_u32_e32 v5, v5, v3
	v_lshl_add_u32 v6, v6, 2, 0
	s_delay_alu instid0(VALU_DEP_4)
	v_lshl_add_u32 v8, v8, 2, 0
	ds_load_b32 v7, v7
	ds_load_b32 v8, v8
	v_lshl_add_u32 v5, v5, 2, 0
	ds_load_b32 v6, v6
	ds_load_b32 v9, v5
	v_add_nc_u32_e32 v5, v4, v1
	s_waitcnt lgkmcnt(2)
	v_add_f32_e32 v7, v7, v8
	s_waitcnt lgkmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_add_f32_e32 v7, v7, v6
	v_ashrrev_i32_e32 v6, 31, v5
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v7, v7, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[5:6], 2, v[5:6]
	v_mul_f32_e32 v7, 0x3e800000, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v5, s0, s4, v5
	v_add_co_ci_u32_e64 v6, s0, s5, v6, s0
	global_store_b32 v[5:6], v7, off
.LBB0_7:                                ;   in Loop: Header=BB0_5 Depth=1
	s_or_b32 exec_lo, exec_lo, s11
	v_add_nc_u32_e32 v1, s1, v1
	s_add_i32 s10, s10, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s10, 0
	s_cbranch_scc0 .LBB0_5
.LBB0_8:                                ; %._crit_edge112
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z23kernel_halfsizebyshare1PfS_iiiii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 20
		.amdhsa_next_free_sgpr 18
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z23kernel_halfsizebyshare1PfS_iiiii, .Lfunc_end0-_Z23kernel_halfsizebyshare1PfS_iiiii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1332
; NumSgprs: 20
; NumVgprs: 20
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 20
; NumVGPRsForWavesPerEU: 20
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z15kernel_halfsizePfS_iiiii ; -- Begin function _Z15kernel_halfsizePfS_iiiii
	.globl	_Z15kernel_halfsizePfS_iiiii
	.p2align	8
	.type	_Z15kernel_halfsizePfS_iiiii,@function
_Z15kernel_halfsizePfS_iiiii:           ; @_Z15kernel_halfsizePfS_iiiii
; %bb.0:
	s_load_b32 s2, s[0:1], 0x20
	s_waitcnt lgkmcnt(0)
	s_cmp_lt_i32 s2, 1
	s_cbranch_scc1 .LBB1_5
; %bb.1:                                ; %.lr.ph
	s_load_b32 s13, s[0:1], 0x34
	s_ashr_i32 s3, s2, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s4, s2, s3
	s_xor_b32 s12, s4, s3
	s_load_b256 s[4:11], s[0:1], 0x0
	v_cvt_f32_u32_e32 v1, s12
	s_delay_alu instid0(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v2, v1
	v_bfe_u32 v1, v0, 10, 10
	v_and_b32_e32 v0, 0x3ff, v0
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s0, s13, 16
	s_and_b32 s1, s13, 0xffff
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v4, 0x4f7ffffe, v2
	v_mad_u64_u32 v[2:3], null, s15, s0, v[1:2]
	s_sub_i32 s0, 0, s12
	s_mul_i32 s10, s2, s10
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cvt_u32_f32_e32 v5, v4
	s_mov_b32 s13, s2
	v_lshlrev_b32_e32 v1, 1, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_mul_lo_u32 v6, s0, v5
	s_mul_i32 s0, s14, s1
	v_mad_u64_u32 v[3:4], null, s8, v2, s[0:1]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_or_b32_e32 v7, 1, v1
	v_mul_lo_u32 v1, v1, s10
	s_mul_i32 s8, s2, s8
	v_mul_hi_u32 v4, v5, v6
	s_delay_alu instid0(VALU_DEP_3)
	v_cmp_gt_i32_e32 vcc_lo, s11, v7
	s_mul_i32 s11, s0, s2
	v_cndmask_b32_e64 v6, 0, s10, vcc_lo
	v_cmp_gt_i32_e32 vcc_lo, s9, v2
	v_mul_lo_u32 v2, s2, v3
	v_add_nc_u32_e32 v4, v5, v4
	s_lshl_b32 s9, s2, 1
	v_add_nc_u32_e32 v3, v6, v1
	s_sub_i32 s10, s10, s2
.LBB1_2:                                ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v5, s11, v0
	v_cmp_gt_i32_e64 s0, s8, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, vcc_lo, s0
	s_and_saveexec_b32 s14, s0
	s_cbranch_execz .LBB1_4
; %bb.3:                                ;   in Loop: Header=BB1_2 Depth=1
	v_ashrrev_i32_e32 v6, 31, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v7, v5, v6
	v_xor_b32_e32 v7, v7, v6
	v_xor_b32_e32 v6, s3, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v8, v7, v4
	v_mul_lo_u32 v9, v8, s12
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v7, v7, v9
	v_add_nc_u32_e32 v9, 1, v8
	v_subrev_nc_u32_e32 v10, s12, v7
	v_cmp_le_u32_e64 s0, s12, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v8, v8, v9, s0
	v_cndmask_b32_e64 v7, v7, v10, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v9, 1, v8
	v_cmp_le_u32_e64 s0, s12, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v7, v8, v9, s0
	v_xor_b32_e32 v7, v7, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v8, v7, v6
	v_mul_lo_u32 v6, v8, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v5, v5, v6
	v_mad_u64_u32 v[6:7], null, s9, v8, v[5:6]
	v_add_nc_u32_e32 v5, s10, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v7, s2, v6
	v_min_i32_e32 v10, v7, v5
	v_add_nc_u32_e32 v5, v6, v1
	v_add_nc_u32_e32 v7, v6, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v9, v10, v1
	v_ashrrev_i32_e32 v6, 31, v5
	v_add_nc_u32_e32 v11, v10, v3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_ashrrev_i32_e32 v8, 31, v7
	v_ashrrev_i32_e32 v10, 31, v9
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_lshlrev_b64 v[5:6], 2, v[5:6]
	v_ashrrev_i32_e32 v12, 31, v11
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_lshlrev_b64 v[7:8], 2, v[7:8]
	v_lshlrev_b64 v[9:10], 2, v[9:10]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v5, s0, s6, v5
	v_add_co_ci_u32_e64 v6, s0, s7, v6, s0
	v_lshlrev_b64 v[11:12], 2, v[11:12]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v9, s0, s6, v9
	v_add_co_ci_u32_e64 v10, s0, s7, v10, s0
	v_add_co_u32 v7, s0, s6, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e64 v8, s0, s7, v8, s0
	s_clause 0x1
	global_load_b32 v13, v[5:6], off
	global_load_b32 v9, v[9:10], off
	v_add_co_u32 v5, s0, s6, v11
	v_add_co_ci_u32_e64 v6, s0, s7, v12, s0
	s_clause 0x1
	global_load_b32 v7, v[7:8], off
	global_load_b32 v8, v[5:6], off
	s_waitcnt vmcnt(2)
	v_dual_add_f32 v6, v13, v9 :: v_dual_add_nc_u32 v5, v2, v0
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v7, v6, v7
	v_ashrrev_i32_e32 v6, 31, v5
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v7, v7, v8
	v_lshlrev_b64 v[5:6], 2, v[5:6]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v7, 0x3e800000, v7
	v_add_co_u32 v5, s0, s4, v5
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v6, s0, s5, v6, s0
	global_store_b32 v[5:6], v7, off
.LBB1_4:                                ;   in Loop: Header=BB1_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s14
	v_add_nc_u32_e32 v0, s1, v0
	s_add_i32 s13, s13, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s13, 0
	s_cbranch_scc0 .LBB1_2
.LBB1_5:                                ; %._crit_edge
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z15kernel_halfsizePfS_iiiii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 14
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z15kernel_halfsizePfS_iiiii, .Lfunc_end1-_Z15kernel_halfsizePfS_iiiii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 756
; NumSgprs: 18
; NumVgprs: 14
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 14
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z16kernel_halfsize1PfS_iiiii ; -- Begin function _Z16kernel_halfsize1PfS_iiiii
	.globl	_Z16kernel_halfsize1PfS_iiiii
	.p2align	8
	.type	_Z16kernel_halfsize1PfS_iiiii,@function
_Z16kernel_halfsize1PfS_iiiii:          ; @_Z16kernel_halfsize1PfS_iiiii
; %bb.0:
	s_load_b32 s2, s[0:1], 0x20
	s_waitcnt lgkmcnt(0)
	s_cmp_lt_i32 s2, 1
	s_cbranch_scc1 .LBB2_5
; %bb.1:                                ; %.lr.ph
	s_load_b32 s13, s[0:1], 0x34
	s_ashr_i32 s3, s2, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s4, s2, s3
	s_xor_b32 s12, s4, s3
	s_load_b256 s[4:11], s[0:1], 0x0
	v_cvt_f32_u32_e32 v1, s12
	s_delay_alu instid0(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v2, v1
	v_bfe_u32 v1, v0, 10, 10
	v_and_b32_e32 v0, 0x3ff, v0
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s0, s13, 16
	s_and_b32 s1, s13, 0xffff
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v4, 0x4f7ffffe, v2
	v_mad_u64_u32 v[2:3], null, s15, s0, v[1:2]
	s_sub_i32 s0, 0, s12
	s_mul_i32 s13, s14, s1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_u32_f32_e32 v4, v4
	v_lshlrev_b32_e32 v1, 1, v2
	v_mul_lo_u32 v3, s8, v2
	s_delay_alu instid0(VALU_DEP_3)
	v_mul_lo_u32 v5, s0, v4
	s_mul_i32 s0, s2, s10
	s_lshl_b32 s10, s2, 1
	v_or_b32_e32 v6, 1, v1
	v_mul_lo_u32 v1, v1, s0
	s_mul_i32 s8, s2, s8
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshl_add_u32 v3, s13, 1, v3
	v_cmp_gt_i32_e32 vcc_lo, s11, v6
	v_mul_hi_u32 v5, v4, v5
	s_mul_i32 s13, s13, s2
	s_max_i32 s11, s10, 1
	s_lshl_b32 s13, s13, 1
	v_cndmask_b32_e64 v6, 0, s0, vcc_lo
	v_cmp_gt_i32_e32 vcc_lo, s9, v2
	v_mul_lo_u32 v2, s2, v3
	s_sub_i32 s9, s0, s2
	v_add_nc_u32_e32 v4, v4, v5
	v_add_nc_u32_e32 v3, v6, v1
.LBB2_2:                                ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v5, s13, v0
	v_cmp_gt_i32_e64 s0, s8, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, vcc_lo, s0
	s_and_saveexec_b32 s14, s0
	s_cbranch_execz .LBB2_4
; %bb.3:                                ;   in Loop: Header=BB2_2 Depth=1
	v_ashrrev_i32_e32 v6, 31, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v7, v5, v6
	v_xor_b32_e32 v7, v7, v6
	v_xor_b32_e32 v6, s3, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v8, v7, v4
	v_mul_lo_u32 v9, v8, s12
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v7, v7, v9
	v_add_nc_u32_e32 v9, 1, v8
	v_subrev_nc_u32_e32 v10, s12, v7
	v_cmp_le_u32_e64 s0, s12, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v8, v8, v9, s0
	v_cndmask_b32_e64 v7, v7, v10, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v9, 1, v8
	v_cmp_le_u32_e64 s0, s12, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v7, v8, v9, s0
	v_xor_b32_e32 v7, v7, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v8, v7, v6
	v_mul_lo_u32 v6, v8, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v5, v5, v6
	v_mad_u64_u32 v[6:7], null, s10, v8, v[5:6]
	v_add_nc_u32_e32 v5, s9, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v7, s2, v6
	v_min_i32_e32 v10, v7, v5
	v_add_nc_u32_e32 v5, v6, v1
	v_add_nc_u32_e32 v7, v6, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v9, v10, v1
	v_ashrrev_i32_e32 v6, 31, v5
	v_add_nc_u32_e32 v11, v10, v3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_ashrrev_i32_e32 v8, 31, v7
	v_ashrrev_i32_e32 v10, 31, v9
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_lshlrev_b64 v[5:6], 2, v[5:6]
	v_ashrrev_i32_e32 v12, 31, v11
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_lshlrev_b64 v[7:8], 2, v[7:8]
	v_lshlrev_b64 v[9:10], 2, v[9:10]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v5, s0, s6, v5
	v_add_co_ci_u32_e64 v6, s0, s7, v6, s0
	v_lshlrev_b64 v[11:12], 2, v[11:12]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v9, s0, s6, v9
	v_add_co_ci_u32_e64 v10, s0, s7, v10, s0
	v_add_co_u32 v7, s0, s6, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e64 v8, s0, s7, v8, s0
	s_clause 0x1
	global_load_b32 v13, v[5:6], off
	global_load_b32 v9, v[9:10], off
	v_add_co_u32 v5, s0, s6, v11
	v_add_co_ci_u32_e64 v6, s0, s7, v12, s0
	s_clause 0x1
	global_load_b32 v7, v[7:8], off
	global_load_b32 v8, v[5:6], off
	s_waitcnt vmcnt(2)
	v_dual_add_f32 v6, v13, v9 :: v_dual_add_nc_u32 v5, v2, v0
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v7, v6, v7
	v_ashrrev_i32_e32 v6, 31, v5
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v7, v7, v8
	v_lshlrev_b64 v[5:6], 2, v[5:6]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v7, 0x3e800000, v7
	v_add_co_u32 v5, s0, s4, v5
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v6, s0, s5, v6, s0
	global_store_b32 v[5:6], v7, off
.LBB2_4:                                ;   in Loop: Header=BB2_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s14
	v_add_nc_u32_e32 v0, s1, v0
	s_add_i32 s11, s11, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s11, 0
	s_cbranch_scc0 .LBB2_2
.LBB2_5:                                ; %._crit_edge
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z16kernel_halfsize1PfS_iiiii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 14
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_Z16kernel_halfsize1PfS_iiiii, .Lfunc_end2-_Z16kernel_halfsize1PfS_iiiii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 764
; NumSgprs: 18
; NumVgprs: 14
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 14
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z22kernel_halfsizebysharePfS_iiiii ; -- Begin function _Z22kernel_halfsizebysharePfS_iiiii
	.globl	_Z22kernel_halfsizebysharePfS_iiiii
	.p2align	8
	.type	_Z22kernel_halfsizebysharePfS_iiiii,@function
_Z22kernel_halfsizebysharePfS_iiiii:    ; @_Z22kernel_halfsizebysharePfS_iiiii
; %bb.0:
	s_clause 0x2
	s_load_b32 s3, s[0:1], 0x34
	s_load_b32 s2, s[0:1], 0x20
	s_load_b256 s[4:11], s[0:1], 0x0
	v_bfe_u32 v2, v0, 10, 10
	v_and_b32_e32 v1, 0x3ff, v0
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s12, s3, 16
	s_and_b32 s1, s3, 0xffff
	s_mul_i32 s15, s15, s12
	s_cmp_gt_i32 s2, 0
	v_add_nc_u32_e32 v0, s15, v2
	s_cselect_b32 s3, -1, 0
	s_cmp_lt_i32 s2, 1
	s_mul_i32 s0, s14, s1
	s_cbranch_scc1 .LBB3_3
; %bb.1:                                ; %.lr.ph
	v_add_nc_u32_e32 v11, s12, v2
	v_add_nc_u32_e32 v3, s15, v0
	s_add_i32 s11, s11, -1
	s_mul_i32 s13, s2, s10
	v_cvt_f64_i32_e32 v[5:6], s11
	v_lshl_add_u32 v7, s15, 1, v11
	v_cvt_f64_u32_e32 v[3:4], v3
	v_cvt_f64_i32_e32 v[9:10], s13
	s_ashr_i32 s10, s2, 31
	s_sub_i32 s13, s13, s2
	v_cvt_f64_u32_e32 v[7:8], v7
	s_add_i32 s11, s2, s10
	s_lshl_b32 s14, s1, 2
	s_xor_b32 s10, s11, s10
	s_mov_b32 s15, s2
	s_sub_i32 s11, 0, s10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_min_f64 v[3:4], v[3:4], v[5:6]
	v_min_f64 v[5:6], v[7:8], v[5:6]
	v_cvt_f32_u32_e32 v7, s10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_rcp_iflag_f32_e32 v7, v7
	v_mul_f64 v[3:4], v[3:4], v[9:10]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[5:6], v[5:6], v[9:10]
	v_cvt_i32_f64_e32 v3, v[3:4]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cvt_i32_f64_e32 v4, v[5:6]
	v_mul_lo_u32 v6, v2, s2
	v_lshl_add_u32 v9, v6, 1, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(TRANS32_DEP_1)
	v_mul_lo_u32 v9, v9, s1
	v_mul_f32_e32 v5, 0x4f7ffffe, v7
	v_mul_lo_u32 v7, s2, v11
	v_mul_lo_u32 v11, v6, s1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_lshlrev_b32_e32 v6, 2, v9
	v_cvt_u32_f32_e32 v5, v5
	s_delay_alu instid0(VALU_DEP_4)
	v_lshl_add_u32 v10, v7, 1, s2
	v_mul_lo_u32 v12, v7, s1
	v_lshl_add_u32 v7, v1, 2, 0
	v_lshlrev_b32_e32 v9, 3, v11
	v_mul_lo_u32 v8, s11, v5
	v_mul_lo_u32 v10, v10, s1
	s_lshl_b32 s11, s0, 1
	v_mov_b32_e32 v11, v1
	s_add_i32 s12, s11, s1
	s_mul_i32 s11, s11, s2
	s_mul_i32 s12, s12, s2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v8, v5, v8
	v_add_nc_u32_e32 v5, v5, v8
	v_lshlrev_b32_e32 v8, 2, v10
	v_lshlrev_b32_e32 v10, 3, v12
.LBB3_2:                                ; =>This Inner Loop Header: Depth=1
	v_ashrrev_i32_e32 v12, 31, v11
	v_add_nc_u32_e32 v13, s11, v11
	s_add_i32 s15, s15, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	s_cmp_eq_u32 s15, 0
	v_add_nc_u32_e32 v15, v11, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v15, v15, v12
	v_mul_hi_u32 v16, v15, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v16, v16, s10
	v_sub_nc_u32_e32 v15, v15, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_subrev_nc_u32_e32 v16, s10, v15
	v_cmp_le_u32_e32 vcc_lo, s10, v15
	v_add_nc_u32_e32 v14, s12, v11
	v_add_nc_u32_e32 v11, s1, v11
	v_cndmask_b32_e32 v15, v15, v16, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v16, s10, v15
	v_cmp_le_u32_e32 vcc_lo, s10, v15
	v_cndmask_b32_e32 v15, v15, v16, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v15, v15, v12
	v_sub_nc_u32_e32 v12, v15, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v12, s13, v12
	v_min_i32_e32 v13, v13, v12
	v_min_i32_e32 v15, v14, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v12, v13, v3
	v_add_nc_u32_e32 v14, v15, v3
	v_add_nc_u32_e32 v16, v13, v4
	v_add_nc_u32_e32 v18, v15, v4
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_ashrrev_i32_e32 v13, 31, v12
	v_ashrrev_i32_e32 v15, 31, v14
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_ashrrev_i32_e32 v17, 31, v16
	v_ashrrev_i32_e32 v19, 31, v18
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_lshlrev_b64 v[12:13], 2, v[12:13]
	v_lshlrev_b64 v[14:15], 2, v[14:15]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_lshlrev_b64 v[16:17], 2, v[16:17]
	v_lshlrev_b64 v[18:19], 2, v[18:19]
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_u32 v12, vcc_lo, s6, v12
	v_add_co_ci_u32_e32 v13, vcc_lo, s7, v13, vcc_lo
	v_add_co_u32 v14, vcc_lo, s6, v14
	v_add_co_ci_u32_e32 v15, vcc_lo, s7, v15, vcc_lo
	v_add_co_u32 v16, vcc_lo, s6, v16
	v_add_co_ci_u32_e32 v17, vcc_lo, s7, v17, vcc_lo
	v_add_co_u32 v18, vcc_lo, s6, v18
	v_add_co_ci_u32_e32 v19, vcc_lo, s7, v19, vcc_lo
	s_clause 0x3
	global_load_b32 v12, v[12:13], off
	global_load_b32 v13, v[14:15], off
	global_load_b32 v14, v[16:17], off
	global_load_b32 v15, v[18:19], off
	v_add_nc_u32_e32 v16, v7, v9
	v_add_nc_u32_e32 v17, v7, v6
	v_add_nc_u32_e32 v18, v7, v10
	v_add_nc_u32_e32 v19, v7, v8
	v_add_nc_u32_e32 v7, s14, v7
	s_waitcnt vmcnt(3)
	ds_store_b32 v16, v12
	s_waitcnt vmcnt(2)
	ds_store_b32 v17, v13
	s_waitcnt vmcnt(1)
	ds_store_b32 v18, v14
	s_waitcnt vmcnt(0)
	ds_store_b32 v19, v15
	s_cbranch_scc0 .LBB3_2
.LBB3_3:                                ; %._crit_edge
	s_and_not1_b32 vcc_lo, exec_lo, s3
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_vccnz .LBB3_8
; %bb.4:                                ; %.lr.ph111
	s_ashr_i32 s3, s2, 31
	v_mad_u64_u32 v[4:5], null, s8, v0, s[0:1]
	s_add_i32 s6, s2, s3
	v_cmp_gt_i32_e32 vcc_lo, s9, v0
	s_xor_b32 s6, s6, s3
	s_mul_i32 s8, s2, s8
	v_cvt_f32_u32_e32 v3, s6
	s_sub_i32 s7, 0, s6
	s_delay_alu instid0(VALU_DEP_3)
	v_mul_lo_u32 v4, s2, v4
	s_lshl_b32 s9, s2, 1
	s_mov_b32 s10, s2
	v_rcp_iflag_f32_e32 v3, v3
	s_waitcnt_depctr 0xfff
	v_dual_mul_f32 v3, 0x4f7ffffe, v3 :: v_dual_lshlrev_b32 v2, 1, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v6, v3
	v_mul_lo_u32 v3, s7, v6
	s_lshl_b32 s7, s1, 1
	s_delay_alu instid0(VALU_DEP_3) | instid1(SALU_CYCLE_1)
	v_mul_u32_u24_e32 v5, s7, v2
	v_mad_u32_u24 v7, s7, v2, s7
	s_mul_i32 s7, s0, s2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mul_lo_u32 v2, v5, s2
	v_mul_hi_u32 v8, v6, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v3, v7, s2
	v_add_nc_u32_e32 v0, v6, v8
.LBB3_5:                                ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v5, s7, v1
	v_cmp_gt_i32_e64 s0, s8, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, vcc_lo, s0
	s_and_saveexec_b32 s11, s0
	s_cbranch_execz .LBB3_7
; %bb.6:                                ;   in Loop: Header=BB3_5 Depth=1
	v_ashrrev_i32_e32 v5, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v6, v1, v5
	v_xor_b32_e32 v6, v6, v5
	v_xor_b32_e32 v5, s3, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v7, v6, v0
	v_mul_lo_u32 v8, v7, s6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v6, v6, v8
	v_add_nc_u32_e32 v8, 1, v7
	v_subrev_nc_u32_e32 v9, s6, v6
	v_cmp_le_u32_e64 s0, s6, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v7, v7, v8, s0
	v_cndmask_b32_e64 v6, v6, v9, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v8, 1, v7
	v_cmp_le_u32_e64 s0, s6, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v6, v7, v8, s0
	v_xor_b32_e32 v6, v6, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v8, v6, v5
	v_mul_lo_u32 v5, v8, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v5, v1, v5
	v_mad_u64_u32 v[6:7], null, s9, v8, v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v5, s2, v6
	v_add_nc_u32_e32 v7, v6, v2
	v_add_nc_u32_e32 v6, v6, v3
	v_add_nc_u32_e32 v8, v5, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_lshl_add_u32 v7, v7, 2, 0
	v_add_nc_u32_e32 v5, v5, v3
	v_lshl_add_u32 v6, v6, 2, 0
	s_delay_alu instid0(VALU_DEP_4)
	v_lshl_add_u32 v8, v8, 2, 0
	ds_load_b32 v7, v7
	ds_load_b32 v8, v8
	v_lshl_add_u32 v5, v5, 2, 0
	ds_load_b32 v6, v6
	ds_load_b32 v9, v5
	v_add_nc_u32_e32 v5, v4, v1
	s_waitcnt lgkmcnt(2)
	v_add_f32_e32 v7, v7, v8
	s_waitcnt lgkmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_add_f32_e32 v7, v7, v6
	v_ashrrev_i32_e32 v6, 31, v5
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v7, v7, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[5:6], 2, v[5:6]
	v_mul_f32_e32 v7, 0x3e800000, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v5, s0, s4, v5
	v_add_co_ci_u32_e64 v6, s0, s5, v6, s0
	global_store_b32 v[5:6], v7, off
.LBB3_7:                                ;   in Loop: Header=BB3_5 Depth=1
	s_or_b32 exec_lo, exec_lo, s11
	v_add_nc_u32_e32 v1, s1, v1
	s_add_i32 s10, s10, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s10, 0
	s_cbranch_scc0 .LBB3_5
.LBB3_8:                                ; %._crit_edge112
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z22kernel_halfsizebysharePfS_iiiii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 20
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end3:
	.size	_Z22kernel_halfsizebysharePfS_iiiii, .Lfunc_end3-_Z22kernel_halfsizebysharePfS_iiiii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1316
; NumSgprs: 18
; NumVgprs: 20
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 20
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
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    .language:       OpenCL C
    .language_version:
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      - 0
    .max_flat_workgroup_size: 1024
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    .symbol:         _Z23kernel_halfsizebyshare1PfS_iiiii.kd
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    .name:           _Z15kernel_halfsizePfS_iiiii
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    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z15kernel_halfsizePfS_iiiii.kd
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    .vgpr_spill_count: 0
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    .name:           _Z22kernel_halfsizebysharePfS_iiiii
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amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
