#include "init.cuh"

void init_params()
{
    srand((unsigned)time(NULL));

    for(int i=0;i<CONV_W_NUM;i++)
    {
        for(int j=0;j<CONV_W_SIZE;j++)
        for(int k=0;k<CONV_W_SIZE;k++)
            conv_w[i][j][k]=get_rand(CONV_W_SIZE*CONV_W_SIZE);
        conv_b[i]=get_rand(CONV_W_SIZE*CONV_W_SIZE);
    }

    for(int i=0;i<FC1_SIZE;i++)
    {
        for(int j=0;j<CONV_W_NUM;j++)
        for(int k=0;k<POOL_SIZE;k++)
        for(int l=0;l<POOL_SIZE;l++)
            fc1_w[i][j][k][l]=get_rand(POOL_SIZE*POOL_SIZE*CONV_W_NUM);
        fc1_b[i]=get_rand(POOL_SIZE*POOL_SIZE*CONV_W_NUM);
    }

    for(int i=0;i<FC2_SIZE;i++)
    {
        for(int j=0;j<FC1_SIZE;j++)
            fc2_w[i][j]=get_rand(FC1_SIZE);
        fc2_b[i]=get_rand(FC1_SIZE);
    }
}
	.file	"tmpxft_00298527_00000000-6_init.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL20__nv_init_managed_rtv, @function
_ZL20__nv_init_managed_rtv:
.LFB1:
	.cfi_startproc
	movb	_ZL22__nv_inited_managed_rt(%rip), %al
	testb	%al, %al
	jne	.L4
	pushq	%rax
	.cfi_def_cfa_offset 16
	movq	_ZL32__nv_fatbinhandle_for_managed_rt(%rip), %rdi
	call	__cudaInitModule@PLT
	movb	%al, _ZL22__nv_inited_managed_rt(%rip)
	popq	%rdx
	.cfi_def_cfa_offset 8
	ret
.L4:
	movb	%al, _ZL22__nv_inited_managed_rt(%rip)
	ret
	.cfi_endproc
.LFE1:
	.size	_ZL20__nv_init_managed_rtv, .-_ZL20__nv_init_managed_rtv
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2030:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z11init_paramsv
	.type	_Z11init_paramsv, @function
_Z11init_paramsv:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	xorl	%edi, %edi
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	xorl	%ebx, %ebx
	subq	$24, %rsp
	.cfi_def_cfa_offset 80
	call	time@PLT
	movl	%eax, %edi
	call	srand@PLT
.L10:
	xorl	%ebp, %ebp
	movslq	%ebx, %r13
.L16:
	imulq	$25, %r13, %r14
	movslq	%ebp, %rax
	xorl	%r12d, %r12d
	leaq	(%rax,%rax,4), %rax
	addq	%rax, %r14
.L12:
	movss	.LC0(%rip), %xmm0
	call	_Z8get_randf@PLT
	cmpb	$0, _ZL22__nv_inited_managed_rt(%rip)
	jne	.L11
	movss	%xmm0, (%rsp)
	call	_ZL20__nv_init_managed_rtv
	movss	(%rsp), %xmm0
.L11:
	movslq	%r12d, %rax
	movq	_ZL6conv_w(%rip), %rdx
	incl	%r12d
	addq	%r14, %rax
	movss	%xmm0, (%rdx,%rax,4)
	cmpl	$5, %r12d
	jne	.L12
	incl	%ebp
	cmpl	$5, %ebp
	jne	.L16
	movss	.LC0(%rip), %xmm0
	call	_Z8get_randf@PLT
	cmpb	$0, _ZL22__nv_inited_managed_rt(%rip)
	jne	.L14
	movss	%xmm0, (%rsp)
	call	_ZL20__nv_init_managed_rtv
	movss	(%rsp), %xmm0
.L14:
	movq	_ZL6conv_b(%rip), %rax
	incl	%ebx
	movss	%xmm0, (%rax,%r13,4)
	cmpl	$6, %ebx
	jne	.L10
	xorl	%ebp, %ebp
.L15:
	xorl	%r12d, %r12d
	movslq	%ebp, %r15
.L24:
	movslq	%r12d, %rax
	imulq	$864, %r15, %rdx
	xorl	%r13d, %r13d
	imulq	$144, %rax, %rax
	addq	%rdx, %rax
	movq	%rax, (%rsp)
.L21:
	movslq	%r13d, %rbx
	movq	(%rsp), %rax
	xorl	%r14d, %r14d
	imulq	$12, %rbx, %rbx
	addq	%rax, %rbx
.L18:
	movss	.LC1(%rip), %xmm0
	call	_Z8get_randf@PLT
	cmpb	$0, _ZL22__nv_inited_managed_rt(%rip)
	jne	.L17
	movss	%xmm0, 12(%rsp)
	call	_ZL20__nv_init_managed_rtv
	movss	12(%rsp), %xmm0
.L17:
	movslq	%r14d, %rax
	movq	_ZL5fc1_w(%rip), %rdx
	incl	%r14d
	addq	%rbx, %rax
	movss	%xmm0, (%rdx,%rax,4)
	cmpl	$12, %r14d
	jne	.L18
	incl	%r13d
	cmpl	$12, %r13d
	jne	.L21
	incl	%r12d
	cmpl	$6, %r12d
	jne	.L24
	movss	.LC1(%rip), %xmm0
	call	_Z8get_randf@PLT
	cmpb	$0, _ZL22__nv_inited_managed_rt(%rip)
	jne	.L22
	movss	%xmm0, (%rsp)
	call	_ZL20__nv_init_managed_rtv
	movss	(%rsp), %xmm0
.L22:
	movq	_ZL5fc1_b(%rip), %rax
	incl	%ebp
	movss	%xmm0, (%rax,%r15,4)
	cmpl	$45, %ebp
	jne	.L15
	xorl	%ebx, %ebx
.L23:
	xorl	%ebp, %ebp
	movslq	%ebx, %r12
.L26:
	movss	.LC2(%rip), %xmm0
	call	_Z8get_randf@PLT
	cmpb	$0, _ZL22__nv_inited_managed_rt(%rip)
	jne	.L25
	movss	%xmm0, (%rsp)
	call	_ZL20__nv_init_managed_rtv
	movss	(%rsp), %xmm0
.L25:
	imulq	$45, %r12, %rax
	movslq	%ebp, %rdx
	incl	%ebp
	addq	%rdx, %rax
	movq	_ZL5fc2_w(%rip), %rdx
	movss	%xmm0, (%rdx,%rax,4)
	cmpl	$45, %ebp
	jne	.L26
	movss	.LC2(%rip), %xmm0
	call	_Z8get_randf@PLT
	cmpb	$0, _ZL22__nv_inited_managed_rt(%rip)
	jne	.L27
	movss	%xmm0, (%rsp)
	call	_ZL20__nv_init_managed_rtv
	movss	(%rsp), %xmm0
.L27:
	movq	_ZL5fc2_b(%rip), %rax
	incl	%ebx
	movss	%xmm0, (%rax,%r12,4)
	cmpl	$10, %ebx
	jne	.L23
	addq	$24, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2027:
	.size	_Z11init_paramsv, .-_Z11init_paramsv
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC3:
	.string	"alpha"
.LC4:
	.string	"correct_cnt"
.LC5:
	.string	"avg_error"
.LC6:
	.string	"train_image"
.LC7:
	.string	"train_label"
.LC8:
	.string	"test_image"
.LC9:
	.string	"test_label"
.LC10:
	.string	"conv_w"
.LC11:
	.string	"conv_b"
.LC12:
	.string	"fc1_b"
.LC13:
	.string	"fc1_w"
.LC14:
	.string	"fc2_b"
.LC15:
	.string	"fc2_w"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2053:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC3(%rip), %rdx
	movl	$4, %r9d
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	movq	%rax, %rdi
	movl	$1, %r8d
	leaq	_ZL5alpha(%rip), %rsi
	movq	%rax, %rbx
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	movq	%rax, _ZL32__nv_fatbinhandle_for_managed_rt(%rip)
	call	__cudaRegisterManagedVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC4(%rip), %rdx
	movq	%rbx, %rdi
	movl	$4, %r9d
	movq	%rdx, %rcx
	movl	$1, %r8d
	leaq	_ZL11correct_cnt(%rip), %rsi
	call	__cudaRegisterManagedVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC5(%rip), %rdx
	movq	%rbx, %rdi
	movl	$4, %r9d
	movq	%rdx, %rcx
	movl	$1, %r8d
	leaq	_ZL9avg_error(%rip), %rsi
	call	__cudaRegisterManagedVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	popq	%r8
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC6(%rip), %rdx
	movq	%rbx, %rdi
	movl	$188160000, %r9d
	movq	%rdx, %rcx
	movl	$1, %r8d
	leaq	_ZL11train_image(%rip), %rsi
	call	__cudaRegisterManagedVar@PLT
	popq	%r9
	.cfi_def_cfa_offset 24
	popq	%r10
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC7(%rip), %rdx
	movq	%rbx, %rdi
	movl	$240000, %r9d
	movq	%rdx, %rcx
	movl	$1, %r8d
	leaq	_ZL11train_label(%rip), %rsi
	call	__cudaRegisterManagedVar@PLT
	popq	%r11
	.cfi_def_cfa_offset 24
	popq	%rax
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC8(%rip), %rdx
	movq	%rbx, %rdi
	movl	$31360000, %r9d
	movq	%rdx, %rcx
	movl	$1, %r8d
	leaq	_ZL10test_image(%rip), %rsi
	call	__cudaRegisterManagedVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC9(%rip), %rdx
	movq	%rbx, %rdi
	movl	$40000, %r9d
	movq	%rdx, %rcx
	movl	$1, %r8d
	leaq	_ZL10test_label(%rip), %rsi
	call	__cudaRegisterManagedVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC10(%rip), %rdx
	movq	%rbx, %rdi
	movl	$600, %r9d
	movq	%rdx, %rcx
	movl	$1, %r8d
	leaq	_ZL6conv_w(%rip), %rsi
	call	__cudaRegisterManagedVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	popq	%r8
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC11(%rip), %rdx
	movq	%rbx, %rdi
	movl	$24, %r9d
	movq	%rdx, %rcx
	movl	$1, %r8d
	leaq	_ZL6conv_b(%rip), %rsi
	call	__cudaRegisterManagedVar@PLT
	popq	%r9
	.cfi_def_cfa_offset 24
	popq	%r10
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC12(%rip), %rdx
	movq	%rbx, %rdi
	movl	$180, %r9d
	movq	%rdx, %rcx
	movl	$1, %r8d
	leaq	_ZL5fc1_b(%rip), %rsi
	call	__cudaRegisterManagedVar@PLT
	popq	%r11
	.cfi_def_cfa_offset 24
	popq	%rax
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC13(%rip), %rdx
	movq	%rbx, %rdi
	movl	$155520, %r9d
	movq	%rdx, %rcx
	movl	$1, %r8d
	leaq	_ZL5fc1_w(%rip), %rsi
	call	__cudaRegisterManagedVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC14(%rip), %rdx
	movq	%rbx, %rdi
	movl	$40, %r9d
	movq	%rdx, %rcx
	movl	$1, %r8d
	leaq	_ZL5fc2_b(%rip), %rsi
	call	__cudaRegisterManagedVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC15(%rip), %rdx
	movq	%rbx, %rdi
	movl	$1800, %r9d
	movl	$1, %r8d
	movq	%rdx, %rcx
	leaq	_ZL5fc2_w(%rip), %rsi
	call	__cudaRegisterManagedVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	popq	%r8
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2053:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	__nv_managed_data__,"aw"
	.align 8
	.type	_ZL5fc2_w, @object
	.size	_ZL5fc2_w, 8
_ZL5fc2_w:
	.zero	8
	.align 8
	.type	_ZL5fc2_b, @object
	.size	_ZL5fc2_b, 8
_ZL5fc2_b:
	.zero	8
	.align 8
	.type	_ZL5fc1_w, @object
	.size	_ZL5fc1_w, 8
_ZL5fc1_w:
	.zero	8
	.align 8
	.type	_ZL5fc1_b, @object
	.size	_ZL5fc1_b, 8
_ZL5fc1_b:
	.zero	8
	.align 8
	.type	_ZL6conv_b, @object
	.size	_ZL6conv_b, 8
_ZL6conv_b:
	.zero	8
	.align 8
	.type	_ZL6conv_w, @object
	.size	_ZL6conv_w, 8
_ZL6conv_w:
	.zero	8
	.align 8
	.type	_ZL10test_label, @object
	.size	_ZL10test_label, 8
_ZL10test_label:
	.zero	8
	.align 8
	.type	_ZL10test_image, @object
	.size	_ZL10test_image, 8
_ZL10test_image:
	.zero	8
	.align 8
	.type	_ZL11train_label, @object
	.size	_ZL11train_label, 8
_ZL11train_label:
	.zero	8
	.align 8
	.type	_ZL11train_image, @object
	.size	_ZL11train_image, 8
_ZL11train_image:
	.zero	8
	.align 8
	.type	_ZL9avg_error, @object
	.size	_ZL9avg_error, 8
_ZL9avg_error:
	.zero	8
	.align 8
	.type	_ZL11correct_cnt, @object
	.size	_ZL11correct_cnt, 8
_ZL11correct_cnt:
	.zero	8
	.align 8
	.type	_ZL5alpha, @object
	.size	_ZL5alpha, 8
_ZL5alpha:
	.zero	8
	.local	_ZL32__nv_fatbinhandle_for_managed_rt
	.comm	_ZL32__nv_fatbinhandle_for_managed_rt,8,8
	.local	_ZL22__nv_inited_managed_rt
	.comm	_ZL22__nv_inited_managed_rt,1,1
	.section	.rodata.cst4,"aM",@progbits,4
	.align 4
.LC0:
	.long	1103626240
	.align 4
.LC1:
	.long	1146617856
	.align 4
.LC2:
	.long	1110704128
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#ifndef _INIT_H_
#define _INIT_H_

#include "utils.cuh"
#include "global.cuh"

void init_params();

#endif
	.text
	.file	"init.hip"
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_

	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.amdgpu_metadata
---
amdhsa.kernels:  []
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
