#include<iostream>
#include<ctime>
using namespace std;
#define O3
template<unsigned int BlockSize>
__global__ void add(int*a,int*b,unsigned int n) {
  unsigned int tid = threadIdx.x;
  unsigned int idx = threadIdx.x + blockIdx.x * blockDim.x * 8;
  int *idata = a + blockIdx.x * blockDim.x*8;
  if(idx + 7*blockDim.x < n) {
    a[idx] *= a[idx + blockDim.x];
    a[idx] *= a[idx + 2*blockDim.x];
    a[idx] *= a[idx + 3*blockDim.x];
    a[idx] *= a[idx + 4*blockDim.x];
    a[idx] *= a[idx + 5*blockDim.x];
    a[idx] *= a[idx + 6*blockDim.x];
    a[idx] *= a[idx + 7*blockDim.x];
  }
  //if(idx  + blockDim.x < n) a[idx] += a[idx + blockDim.x];
  __syncthreads();
  if(BlockSize >= 1024 && tid < 512) {
    idata[tid] *= idata[tid + 512];
  }
  __syncthreads();
  if(BlockSize >= 512 && tid < 256) {
    idata[tid] *= idata[tid + 256];
  }
  __syncthreads();
  if(BlockSize >= 256 && tid < 128) {
    idata[tid] *= idata[tid + 128];
  }
  __syncthreads();
  if(BlockSize >= 128 && tid < 64) {
    idata[tid] *= idata[tid + 64];
  }
  __syncthreads();
  if(tid < 32) {
    volatile int *vmem = idata;
    vmem[tid] *= vmem[tid + 32];
    vmem[tid] *= vmem[tid + 16];
    vmem[tid] *= vmem[tid + 8];
    vmem[tid] *= vmem[tid + 4];
    vmem[tid] *= vmem[tid + 2];
    vmem[tid] *= vmem[tid + 1];
  }
  if (tid == 0) {b[blockIdx.x] = idata[0];}
}
int main(int argc,char*argv[]) {
  int SIZE = 512;
  int N = 1<<20;
  dim3 block(SIZE,1);
  dim3 grid((block.x + N - 1)/block.x, 1);
  int a[N];
  auto init = [&](auto* a,unsigned int size) -> void{
    for(int i = 0;i < size;i++) {
      a[i] = 1;
    }
  };
  int *a_dev, *ans_dev,ans[grid.x];
  init(a, N);
  cudaMalloc((int**)(&a_dev),sizeof(int)*N);
  cudaMalloc((int**)(&ans_dev),sizeof(int)*grid.x);
  cudaMemcpy(a_dev, a, sizeof(int)*N, cudaMemcpyHostToDevice);
  cudaDeviceSynchronize();
  switch(SIZE){
    case 512:
      clock_t start,end;
      start = clock();
      add<512><<<grid.x/8, block>>>(a_dev, ans_dev, N);
      cudaDeviceSynchronize();
      end = clock();
      cout<<"GPU time : "<<end - start<<"ms"<<endl;
      break;
  }
  clock_t start,end;
  start = clock();
  for(int i = 1;i < N;i++) {
    a[0] += a[i];
  }
  cout<<a[0]<<endl;
  end = clock();
  cout<<"CPU time : "<<end - start<<"ms"<<endl;
  cudaMemcpy (&ans, ans_dev, sizeof(int)*grid.x, cudaMemcpyDeviceToHost);
  cudaDeviceSynchronize();
  int ret = 0;
  for (int i = 0;i < grid.x;i++) {
    ret += ans[i];
  }
  cout<<ret<<endl;
  return 0;
} 

	.file	"tmpxft_00360f2a_00000000-6_5.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3641:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3641:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.type	_ZL35__device_stub__Z3addILj512EEvPiS0_jPiS_j, @function
_ZL35__device_stub__Z3addILj512EEvPiS0_jPiS_j:
.LFB3663:
	.cfi_startproc
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z3addILj512EEvPiS0_j(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L2:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3663:
	.size	_ZL35__device_stub__Z3addILj512EEvPiS0_jPiS_j, .-_ZL35__device_stub__Z3addILj512EEvPiS0_jPiS_j
	.section	.text._Z3addILj512EEvPiS0_j,"axG",@progbits,_Z3addILj512EEvPiS0_j,comdat
	.weak	_Z3addILj512EEvPiS0_j
	.type	_Z3addILj512EEvPiS0_j, @function
_Z3addILj512EEvPiS0_j:
.LFB3968:
	.cfi_startproc
	endbr64
	jmp	_ZL35__device_stub__Z3addILj512EEvPiS0_jPiS_j
	.cfi_endproc
.LFE3968:
	.size	_Z3addILj512EEvPiS0_j, .-_Z3addILj512EEvPiS0_j
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"GPU time : "
.LC1:
	.string	"ms"
.LC2:
	.string	"CPU time : "
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB3637:
	.cfi_startproc
	endbr64
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register 6
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$56, %rsp
	.cfi_offset 15, -24
	.cfi_offset 14, -32
	.cfi_offset 13, -40
	.cfi_offset 12, -48
	.cfi_offset 3, -56
	movq	%fs:40, %rax
	movq	%rax, -56(%rbp)
	xorl	%eax, %eax
	movl	$1, -76(%rbp)
	leaq	-4194304(%rsp), %rax
	movl	$1, -72(%rbp)
.L9:
	cmpq	%rax, %rsp
	je	.L10
	subq	$4096, %rsp
	orq	$0, 4088(%rsp)
	jmp	.L9
.L10:
	leaq	3(%rsp), %rbx
	leaq	-8192(%rsp), %rax
	movq	%rbx, %r15
	andq	$-4, %rbx
	shrq	$2, %r15
.L12:
	cmpq	%rax, %rsp
	je	.L13
	subq	$4096, %rsp
	orq	$0, 4088(%rsp)
	jmp	.L12
.L13:
	xorl	%eax, %eax
	movq	%rsp, %r14
.L15:
	movl	$1, (%rbx,%rax,4)
	incq	%rax
	cmpq	$1048576, %rax
	jne	.L15
	leaq	-96(%rbp), %rdi
	movl	$4194304, %esi
	call	cudaMalloc@PLT
	leaq	-88(%rbp), %rdi
	movl	$8192, %esi
	call	cudaMalloc@PLT
	movq	-96(%rbp), %rdi
	movl	$1, %ecx
	movq	%rbx, %rsi
	movl	$4194304, %edx
	call	cudaMemcpy@PLT
	call	cudaDeviceSynchronize@PLT
	call	clock@PLT
	movl	$16777217, %edi
	movl	-72(%rbp), %ecx
	xorl	%r9d, %r9d
	salq	$8, %rdi
	xorl	%r8d, %r8d
	movl	$1, %esi
	movq	%rax, %r13
	movl	$512, -80(%rbp)
	movq	-80(%rbp), %rdx
	movq	%rdi, -68(%rbp)
	movl	$1, -60(%rbp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L16
	movq	-88(%rbp), %rsi
	movq	-96(%rbp), %rdi
	movl	$1048576, %edx
	call	_ZL35__device_stub__Z3addILj512EEvPiS0_jPiS_j
.L16:
	call	cudaDeviceSynchronize@PLT
	call	clock@PLT
	leaq	.LC0(%rip), %rsi
	leaq	_ZSt4cout(%rip), %rdi
	movq	%rax, %r12
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%r12, %rsi
	leaq	.LC1(%rip), %r12
	subq	%r13, %rsi
	movq	%rax, %rdi
	call	_ZNSo9_M_insertIlEERSoT_@PLT
	movq	%r12, %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%rax, %rdi
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
	call	clock@PLT
	movl	0(,%r15,4), %esi
	movq	%rax, %r13
	movl	$1, %eax
.L17:
	addl	(%rbx,%rax,4), %esi
	incq	%rax
	cmpq	$1048576, %rax
	jne	.L17
	movl	%esi, 0(,%r15,4)
	leaq	_ZSt4cout(%rip), %rdi
	call	_ZNSolsEi@PLT
	movq	%rax, %rdi
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
	call	clock@PLT
	leaq	.LC2(%rip), %rsi
	leaq	_ZSt4cout(%rip), %rdi
	movq	%rax, %rbx
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	subq	%r13, %rbx
	movq	%rax, %rdi
	movq	%rbx, %rsi
	call	_ZNSo9_M_insertIlEERSoT_@PLT
	movq	%r12, %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%rax, %rdi
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
	movq	-88(%rbp), %rsi
	movl	$2, %ecx
	movq	%r14, %rdi
	movl	$8192, %edx
	call	cudaMemcpy@PLT
	call	cudaDeviceSynchronize@PLT
	xorl	%eax, %eax
	xorl	%esi, %esi
.L18:
	addl	(%r14,%rax,4), %esi
	incq	%rax
	cmpq	$2048, %rax
	jne	.L18
	leaq	_ZSt4cout(%rip), %rdi
	call	_ZNSolsEi@PLT
	movq	%rax, %rdi
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
	movq	-56(%rbp), %rax
	subq	%fs:40, %rax
	je	.L19
	call	__stack_chk_fail@PLT
.L19:
	leaq	-40(%rbp), %rsp
	xorl	%eax, %eax
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE3637:
	.size	main, .-main
	.section	.rodata.str1.1
.LC3:
	.string	"_Z3addILj512EEvPiS0_j"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3666:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC3(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z3addILj512EEvPiS0_j(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3666:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include<iostream>
#include<ctime>
using namespace std;
#define O3
template<unsigned int BlockSize>
__global__ void add(int*a,int*b,unsigned int n) {
  unsigned int tid = threadIdx.x;
  unsigned int idx = threadIdx.x + blockIdx.x * blockDim.x * 8;
  int *idata = a + blockIdx.x * blockDim.x*8;
  if(idx + 7*blockDim.x < n) {
    a[idx] *= a[idx + blockDim.x];
    a[idx] *= a[idx + 2*blockDim.x];
    a[idx] *= a[idx + 3*blockDim.x];
    a[idx] *= a[idx + 4*blockDim.x];
    a[idx] *= a[idx + 5*blockDim.x];
    a[idx] *= a[idx + 6*blockDim.x];
    a[idx] *= a[idx + 7*blockDim.x];
  }
  //if(idx  + blockDim.x < n) a[idx] += a[idx + blockDim.x];
  __syncthreads();
  if(BlockSize >= 1024 && tid < 512) {
    idata[tid] *= idata[tid + 512];
  }
  __syncthreads();
  if(BlockSize >= 512 && tid < 256) {
    idata[tid] *= idata[tid + 256];
  }
  __syncthreads();
  if(BlockSize >= 256 && tid < 128) {
    idata[tid] *= idata[tid + 128];
  }
  __syncthreads();
  if(BlockSize >= 128 && tid < 64) {
    idata[tid] *= idata[tid + 64];
  }
  __syncthreads();
  if(tid < 32) {
    volatile int *vmem = idata;
    vmem[tid] *= vmem[tid + 32];
    vmem[tid] *= vmem[tid + 16];
    vmem[tid] *= vmem[tid + 8];
    vmem[tid] *= vmem[tid + 4];
    vmem[tid] *= vmem[tid + 2];
    vmem[tid] *= vmem[tid + 1];
  }
  if (tid == 0) {b[blockIdx.x] = idata[0];}
}
int main(int argc,char*argv[]) {
  int SIZE = 512;
  int N = 1<<20;
  dim3 block(SIZE,1);
  dim3 grid((block.x + N - 1)/block.x, 1);
  int a[N];
  auto init = [&](auto* a,unsigned int size) -> void{
    for(int i = 0;i < size;i++) {
      a[i] = 1;
    }
  };
  int *a_dev, *ans_dev,ans[grid.x];
  init(a, N);
  hipMalloc((int**)(&a_dev),sizeof(int)*N);
  hipMalloc((int**)(&ans_dev),sizeof(int)*grid.x);
  hipMemcpy(a_dev, a, sizeof(int)*N, hipMemcpyHostToDevice);
  hipDeviceSynchronize();
  switch(SIZE){
    case 512:
      clock_t start,end;
      start = clock();
      add<512><<<grid.x/8, block>>>(a_dev, ans_dev, N);
      hipDeviceSynchronize();
      end = clock();
      cout<<"GPU time : "<<end - start<<"ms"<<endl;
      break;
  }
  clock_t start,end;
  start = clock();
  for(int i = 1;i < N;i++) {
    a[0] += a[i];
  }
  cout<<a[0]<<endl;
  end = clock();
  cout<<"CPU time : "<<end - start<<"ms"<<endl;
  hipMemcpy (&ans, ans_dev, sizeof(int)*grid.x, hipMemcpyDeviceToHost);
  hipDeviceSynchronize();
  int ret = 0;
  for (int i = 0;i < grid.x;i++) {
    ret += ans[i];
  }
  cout<<ret<<endl;
  return 0;
} 

	.text
	.file	"5.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%r14
	.cfi_def_cfa_offset 16
	pushq	%rbx
	.cfi_def_cfa_offset 24
	subq	$4202520, %rsp                  # imm = 0x402018
	.cfi_def_cfa_offset 4202544
	.cfi_offset %rbx, -24
	.cfi_offset %r14, -16
	xorl	%eax, %eax
.LBB0_1:                                # =>This Inner Loop Header: Depth=1
	movl	$1, 8208(%rsp,%rax,4)
	incq	%rax
	cmpq	$1048576, %rax                  # imm = 0x100000
	jne	.LBB0_1
# %bb.2:                                # %_ZZ4mainENKUlPT_jE_clIiEEvS0_j.exit
	leaq	8(%rsp), %rbx
	movl	$4194304, %esi                  # imm = 0x400000
	movq	%rbx, %rdi
	callq	hipMalloc
	movq	%rsp, %rdi
	movl	$8192, %esi                     # imm = 0x2000
	callq	hipMalloc
	movq	(%rbx), %rdi
	leaq	8208(%rsp), %rsi
	movl	$4194304, %edx                  # imm = 0x400000
	movl	$1, %ecx
	callq	hipMemcpy
	callq	hipDeviceSynchronize
	callq	clock
	movq	%rax, %rbx
	movabsq	$4294967552, %rdi               # imm = 0x100000100
	leaq	256(%rdi), %rdx
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB0_4
# %bb.3:
	movq	8(%rsp), %rdi
	movq	(%rsp), %rsi
	movl	$1048576, %edx                  # imm = 0x100000
	callq	_Z18__device_stub__addILj512EEvPiS0_j
.LBB0_4:
	callq	hipDeviceSynchronize
	callq	clock
	movq	%rax, %r14
	movl	$_ZSt4cout, %edi
	movl	$.L.str, %esi
	movl	$11, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	subq	%rbx, %r14
	movl	$_ZSt4cout, %edi
	movq	%r14, %rsi
	callq	_ZNSo9_M_insertIlEERSoT_
	movq	%rax, %rbx
	movl	$.L.str.1, %esi
	movl	$2, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	(%rbx), %rax
	movq	-24(%rax), %rdi
	addq	%rbx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%rbx, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	callq	clock
	movq	%rax, %rbx
	movl	$1, %eax
	movl	8208(%rsp), %esi
.LBB0_5:                                # =>This Inner Loop Header: Depth=1
	addl	8208(%rsp,%rax,4), %esi
	incq	%rax
	cmpq	$1048576, %rax                  # imm = 0x100000
	jne	.LBB0_5
# %bb.6:
	movl	%esi, 8208(%rsp)
	movl	$_ZSt4cout, %edi
	callq	_ZNSolsEi
	movq	%rax, %r14
	movq	(%rax), %rax
	movq	-24(%rax), %rdi
	addq	%r14, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%r14, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	callq	clock
	movq	%rax, %r14
	movl	$_ZSt4cout, %edi
	movl	$.L.str.2, %esi
	movl	$11, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	subq	%rbx, %r14
	movl	$_ZSt4cout, %edi
	movq	%r14, %rsi
	callq	_ZNSo9_M_insertIlEERSoT_
	movq	%rax, %rbx
	movl	$.L.str.1, %esi
	movl	$2, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	(%rbx), %rax
	movq	-24(%rax), %rdi
	addq	%rbx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%rbx, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movq	(%rsp), %rsi
	leaq	16(%rsp), %rdi
	movl	$8192, %edx                     # imm = 0x2000
	movl	$2, %ecx
	callq	hipMemcpy
	callq	hipDeviceSynchronize
	xorl	%eax, %eax
	xorl	%esi, %esi
.LBB0_7:                                # =>This Inner Loop Header: Depth=1
	addl	16(%rsp,%rax,4), %esi
	incq	%rax
	cmpq	$2048, %rax                     # imm = 0x800
	jne	.LBB0_7
# %bb.8:
	movl	$_ZSt4cout, %edi
	callq	_ZNSolsEi
	movq	%rax, %rbx
	movq	(%rax), %rax
	movq	-24(%rax), %rdi
	addq	%rbx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%rbx, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	xorl	%eax, %eax
	addq	$4202520, %rsp                  # imm = 0x402018
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	main, .Lfunc_end0-main
	.cfi_endproc
                                        # -- End function
	.section	.text._Z18__device_stub__addILj512EEvPiS0_j,"axG",@progbits,_Z18__device_stub__addILj512EEvPiS0_j,comdat
	.weak	_Z18__device_stub__addILj512EEvPiS0_j # -- Begin function _Z18__device_stub__addILj512EEvPiS0_j
	.type	_Z18__device_stub__addILj512EEvPiS0_j,@function
_Z18__device_stub__addILj512EEvPiS0_j:  # @_Z18__device_stub__addILj512EEvPiS0_j
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z3addILj512EEvPiS0_j, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z18__device_stub__addILj512EEvPiS0_j, .Lfunc_end1-_Z18__device_stub__addILj512EEvPiS0_j
	.cfi_endproc
                                        # -- End function
	.text
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z3addILj512EEvPiS0_j, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z3addILj512EEvPiS0_j,@object   # @_Z3addILj512EEvPiS0_j
	.section	.rodata._Z3addILj512EEvPiS0_j,"aG",@progbits,_Z3addILj512EEvPiS0_j,comdat
	.weak	_Z3addILj512EEvPiS0_j
	.p2align	3, 0x0
_Z3addILj512EEvPiS0_j:
	.quad	_Z18__device_stub__addILj512EEvPiS0_j
	.size	_Z3addILj512EEvPiS0_j, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"GPU time : "
	.size	.L.str, 12

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"ms"
	.size	.L.str.1, 3

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"CPU time : "
	.size	.L.str.2, 12

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z3addILj512EEvPiS0_j"
	.size	.L__unnamed_1, 22

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z18__device_stub__addILj512EEvPiS0_j
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z3addILj512EEvPiS0_j
	.addrsig_sym _ZSt4cout
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.section	.text._Z3addILj512EEvPiS0_j,"axG",@progbits,_Z3addILj512EEvPiS0_j,comdat
	.protected	_Z3addILj512EEvPiS0_j   ; -- Begin function _Z3addILj512EEvPiS0_j
	.globl	_Z3addILj512EEvPiS0_j
	.p2align	8
	.type	_Z3addILj512EEvPiS0_j,@function
_Z3addILj512EEvPiS0_j:                  ; @_Z3addILj512EEvPiS0_j
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x24
	s_load_b32 s5, s[0:1], 0x10
	s_mov_b32 s4, s15
	s_waitcnt lgkmcnt(0)
	s_and_b32 s7, s2, 0xffff
	s_load_b128 s[0:3], s[0:1], 0x0
	s_mul_i32 s6, s15, s7
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b32 s6, s6, 3
	v_add_nc_u32_e32 v3, s6, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s7, 7, v[3:4]
	v_cmp_gt_u32_e32 vcc_lo, s5, v1
	s_and_saveexec_b32 s5, vcc_lo
	s_cbranch_execz .LBB0_2
; %bb.1:
	v_dual_mov_b32 v6, 0 :: v_dual_add_nc_u32 v5, s7, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v4, v6
	v_lshlrev_b64 v[7:8], 2, v[5:6]
	v_add_nc_u32_e32 v5, s7, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[2:3], 2, v[3:4]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v7, vcc_lo, s0, v7
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v8, vcc_lo, s1, v8, vcc_lo
	v_add_co_u32 v9, vcc_lo, s0, v2
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v10, vcc_lo, s1, v3, vcc_lo
	v_lshlrev_b64 v[2:3], 2, v[5:6]
	v_add_nc_u32_e32 v5, s7, v5
	s_clause 0x1
	global_load_b32 v4, v[7:8], off
	global_load_b32 v7, v[9:10], off
	v_add_co_u32 v2, vcc_lo, s0, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
	s_waitcnt vmcnt(0)
	v_mul_lo_u32 v4, v7, v4
	global_store_b32 v[9:10], v4, off
	global_load_b32 v7, v[2:3], off
	v_lshlrev_b64 v[2:3], 2, v[5:6]
	v_add_nc_u32_e32 v5, s7, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v2, vcc_lo, s0, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
	s_waitcnt vmcnt(0)
	v_mul_lo_u32 v4, v7, v4
	global_store_b32 v[9:10], v4, off
	global_load_b32 v7, v[2:3], off
	v_lshlrev_b64 v[2:3], 2, v[5:6]
	v_add_nc_u32_e32 v5, s7, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v2, vcc_lo, s0, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
	s_waitcnt vmcnt(0)
	v_mul_lo_u32 v4, v7, v4
	global_store_b32 v[9:10], v4, off
	global_load_b32 v7, v[2:3], off
	v_lshlrev_b64 v[2:3], 2, v[5:6]
	v_add_nc_u32_e32 v5, s7, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v2, vcc_lo, s0, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
	s_waitcnt vmcnt(0)
	v_mul_lo_u32 v4, v7, v4
	global_store_b32 v[9:10], v4, off
	global_load_b32 v7, v[2:3], off
	v_lshlrev_b64 v[2:3], 2, v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s0, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
	s_waitcnt vmcnt(0)
	v_mul_lo_u32 v4, v7, v4
	global_store_b32 v[9:10], v4, off
	global_load_b32 v3, v[2:3], off
	v_mov_b32_e32 v2, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	s_waitcnt vmcnt(0)
	v_mul_lo_u32 v3, v3, v4
	global_store_b32 v[9:10], v3, off
	global_load_b32 v1, v[1:2], off
	s_waitcnt vmcnt(0)
	v_mul_lo_u32 v1, v1, v3
	global_store_b32 v[9:10], v1, off
.LBB0_2:
	s_or_b32 exec_lo, exec_lo, s5
	s_mov_b32 s7, 0
	v_lshlrev_b32_e32 v1, 2, v0
	s_lshl_b64 s[6:7], s[6:7], 2
	s_mov_b32 s5, exec_lo
	s_waitcnt lgkmcnt(0)
	s_add_u32 s0, s0, s6
	s_addc_u32 s1, s1, s7
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 0x100, v0
	s_cbranch_execz .LBB0_4
; %bb.3:
	v_or_b32_e32 v2, 0x400, v1
	s_clause 0x1
	global_load_b32 v2, v2, s[0:1]
	global_load_b32 v3, v1, s[0:1]
	s_waitcnt vmcnt(0)
	v_mul_lo_u32 v2, v3, v2
	global_store_b32 v1, v2, s[0:1]
.LBB0_4:
	s_or_b32 exec_lo, exec_lo, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s5, exec_lo
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 0x80, v0
	s_cbranch_execz .LBB0_6
; %bb.5:
	v_or_b32_e32 v2, 0x200, v1
	s_clause 0x1
	global_load_b32 v2, v2, s[0:1]
	global_load_b32 v3, v1, s[0:1]
	s_waitcnt vmcnt(0)
	v_mul_lo_u32 v2, v3, v2
	global_store_b32 v1, v2, s[0:1]
.LBB0_6:
	s_or_b32 exec_lo, exec_lo, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s5, exec_lo
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 64, v0
	s_cbranch_execz .LBB0_8
; %bb.7:
	v_or_b32_e32 v2, 0x100, v1
	s_clause 0x1
	global_load_b32 v2, v2, s[0:1]
	global_load_b32 v3, v1, s[0:1]
	s_waitcnt vmcnt(0)
	v_mul_lo_u32 v2, v3, v2
	global_store_b32 v1, v2, s[0:1]
.LBB0_8:
	s_or_b32 exec_lo, exec_lo, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s5, exec_lo
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v0
	s_cbranch_execz .LBB0_10
; %bb.9:
	v_or_b32_e32 v2, 0x80, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v2, s6, s0, v2
	v_add_co_ci_u32_e64 v3, null, s1, 0, s6
	v_add_co_u32 v4, s6, s0, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v5, null, s1, 0, s6
	flat_load_b32 v1, v[2:3] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v2, v[4:5] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_mul_lo_u32 v1, v2, v1
	flat_store_b32 v[4:5], v1 dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b32 v1, v[4:5] offset:64 glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v2, v[4:5] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_mul_lo_u32 v1, v2, v1
	flat_store_b32 v[4:5], v1 dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b32 v1, v[4:5] offset:32 glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v2, v[4:5] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_mul_lo_u32 v1, v2, v1
	flat_store_b32 v[4:5], v1 dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b32 v1, v[4:5] offset:16 glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v2, v[4:5] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_mul_lo_u32 v1, v2, v1
	flat_store_b32 v[4:5], v1 dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b32 v1, v[4:5] offset:8 glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v2, v[4:5] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_mul_lo_u32 v1, v2, v1
	flat_store_b32 v[4:5], v1 dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b32 v1, v[4:5] offset:4 glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v2, v[4:5] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_mul_lo_u32 v1, v2, v1
	flat_store_b32 v[4:5], v1 dlc
	s_waitcnt_vscnt null, 0x0
.LBB0_10:
	s_or_b32 exec_lo, exec_lo, s5
	s_mov_b32 s5, 0
	s_mov_b32 s6, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB0_12
; %bb.11:
	v_mov_b32_e32 v0, 0
	global_load_b32 v1, v0, s[0:1]
	s_lshl_b64 s[0:1], s[4:5], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s0, s2, s0
	s_addc_u32 s1, s3, s1
	s_waitcnt vmcnt(0)
	global_store_b32 v0, v1, s[0:1]
.LBB0_12:
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z3addILj512EEvPiS0_j
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 11
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z3addILj512EEvPiS0_j,"axG",@progbits,_Z3addILj512EEvPiS0_j,comdat
.Lfunc_end0:
	.size	_Z3addILj512EEvPiS0_j, .Lfunc_end0-_Z3addILj512EEvPiS0_j
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1236
; NumSgprs: 18
; NumVgprs: 11
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 11
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z3addILj512EEvPiS0_j
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z3addILj512EEvPiS0_j.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     11
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
