#include <sys/types.h>
#include <sys/stat.h>
#include <fcntl.h>
#include <stdio.h>
#include <errno.h>
#include <unistd.h>
#include <stdlib.h>
#include <arpa/inet.h>
#include <math.h>
#include "cs_cuda.h"
#include "cs_dbg.h"
#include "cs_helper.h"
#include "cs_motion_detect.h"

// #define CUDA_DBG
// #define CUDA_DBG1

#define NUM_OF_HVT_INDEX	3

__global__ void d_do_motion_detection ( int *fdp, int *tdp, int tbl_size, 
	int record_size, // do include the 3 indexes
	int cx, int cxy_size,
	int mx, int mxy_size )
{
	int t_idx = blockIdx.x * blockDim.x + threadIdx.x;
	int ot_idx, i, j, from, no_idx_size, *dp, h, v, t, tt, hh, vv ;

	ot_idx = t_idx ;
	while ( t_idx < tbl_size )
	{
		no_idx_size = record_size - NUM_OF_HVT_INDEX ;

		i = t_idx / no_idx_size ;
		dp = tdp + ( i * record_size ) ;
		t = *dp++ ;
		v = *dp++ ;
		h = *dp++ ;

		t_idx %= no_idx_size ;

		tt = t_idx / mxy_size ; // which block
		j = t_idx % mxy_size ;
		hh = j % mx ;	// which h
		vv = j / mx ;	// which v

		from = ( t + tt )  * cxy_size + ( v + vv ) * cx + h + hh ;

		dp[ t_idx ] = fdp[ from ] ; 
		// dp[ t_idx ] = from ; 

		ot_idx += CUDA_MAX_THREADS ;
		t_idx = ot_idx ;
	}		
}

// do: 1 block at a time ... 
// block : the result of do_motion_idx <- edge-detection <- L-selection
// cube : the cube that is going to be moved by all h/v/t units
int
h_do_motion_detection ( int *fromp, int *top,
	int tbl_size,		// overall input size ... excludes the 3 indexes
	int record_size,	// includes the 3 indexes
	int blk_x, int blk_xy,	
	int cube_x, int cube_xy )
{
	int nThreadsPerBlock = CUDA_MAX_THREADS_P_BLK ;
	int nBlocks ; // = ( tbl_size + ( nThreadsPerBlock - 1 ))/nThreadsPerBlock ;

#ifdef CUDA_DBG1 
	fprintf(stderr, "%s: f %p t %p tblsize %d rec %d blk %d %d cube %d %d\n",
		__func__, fromp, top, tbl_size, record_size,
		blk_x, blk_xy, cube_x, cube_xy ) ;
#endif 

	if (( tbl_size % cube_xy ) || (( record_size - NUM_OF_HVT_INDEX ) % cube_xy ))
	{
		fprintf(stderr, "%s: error size %d cube %d rec %d\n", __func__,
			tbl_size, cube_xy, record_size ) ;
		return ( 0 ) ;
	}

	h_block_adj ( tbl_size, nThreadsPerBlock, &nBlocks ) ;

	d_do_motion_detection <<< nBlocks, nThreadsPerBlock >>> (
		fromp, top, tbl_size, record_size, blk_x, blk_xy,
		cube_x, cube_xy ) ;

	cudaThreadSynchronize() ;

#ifdef CUDA_OBS 
	dbg_p_d_data_i("motion_detect", top, tbl_size ) ; 
#endif 
	return ( 1 ) ;
}

// 3 indexes + real data length == record_length

__global__ void d_do_motion_idx ( int *dp, int tbl_size, int record_length,
	int h_loop, int t_loop, int hv_size ) 
{
	int *odp, t_idx = blockIdx.x * blockDim.x + threadIdx.x;
	int j ;

	odp = dp ;
	while ( t_idx < tbl_size )
	{
		dp = odp ;

		dp += t_idx * record_length ;

		*dp++ = t_idx / hv_size ;	// tmporal

		j = t_idx % hv_size ;
	
		*dp++ = j / h_loop ;	// vertical
		*dp = j % h_loop ;	// horizontal

		t_idx += CUDA_MAX_THREADS ;
	}   
} 

int
h_do_motion_idx ( int *dp, int total_size, int record_length,
	int h_loop, int v_loop, int t_loop, int *orig_idx )
{
	int nThreadsPerBlock = CUDA_MAX_THREADS_P_BLK ;
	int nBlocks, loopcnt ;

	record_length += NUM_OF_HVT_INDEX ; // 3 indexes .. t/v/h in the beginning ...

	loopcnt = v_loop * h_loop * t_loop ;

	if (( record_length * loopcnt ) > total_size )
	{
		fprintf( stderr, "%s: size needed %d got %d\n",
			__func__, record_length * loopcnt, total_size ) ;
		return ( 0 ) ;
	}

	// nBlocks= ( loopcnt + ( nThreadsPerBlock - 1 ))/nThreadsPerBlock ;

	h_block_adj ( loopcnt, nThreadsPerBlock, &nBlocks ) ;

	d_do_motion_idx <<< nBlocks, nThreadsPerBlock >>> (
		dp, loopcnt, record_length, h_loop, t_loop, h_loop * v_loop ) ;

	cudaThreadSynchronize() ;

	*orig_idx = ( v_loop / 2 ) * h_loop + ( h_loop / 2 ) ;

	return ( 1 ) ;
}

// step one is to get y0-yk

__global__ void d_do_l1_norm_step1 ( int *dp, int tbl_size, int record_length,
	int *op, int orig )
{
	int t_idx = blockIdx.x * blockDim.x + threadIdx.x;
	int *odp, i, j ;

	odp = dp ;
	while ( t_idx < tbl_size )
	{
		dp = odp ;

		j = t_idx / record_length ;

		if ( j != orig )
		{
			i = t_idx % record_length ;

			op += i ;
			dp = dp + j * ( record_length + NUM_OF_HVT_INDEX ) + 
				NUM_OF_HVT_INDEX + i ;

			*dp -= *op ;

			if ( *dp < 0 )
				*dp = -*dp ;	// save a step ... no need to abs()
		}

		t_idx += CUDA_MAX_THREADS ;
	}   
}

// total and record_size does not have the NUM_OF_HVT_INDEX elements
void
h_do_l1_norm_step1( int *dp, int total, int record_size, int orig )
{
	int nThreadsPerBlock = CUDA_MAX_THREADS_P_BLK ;
	int nBlocks ; // = ( total + ( nThreadsPerBlock - 1 ))/nThreadsPerBlock ;
	int *op ;

	op = dp + orig * ( record_size + NUM_OF_HVT_INDEX ) + NUM_OF_HVT_INDEX ;

	h_block_adj ( total, nThreadsPerBlock, &nBlocks ) ;

	d_do_l1_norm_step1 <<< nBlocks, nThreadsPerBlock >>> (
		dp, total, record_size, op, orig ) ;

	cudaThreadSynchronize() ;
}

// step two is to get L1-norm(sum)
// all row, should be after the abs() is done
// tbl_size is the number of elements for this addition operation
// record_length includes the NUM_OF_HVT_INDEX
// dp starts with valid data, see caller

__global__ void d_do_l1_norm_step2 ( int *dp, int tbl_size, int record_length,
	int start, int cnt )
{
	int t_idx = blockIdx.x * blockDim.x + threadIdx.x;
	int *odp, *tp, j ;

	odp = dp ;
	while ( t_idx < tbl_size )
	{
		dp = odp ;

		j = t_idx / cnt ;

		tp = dp + j * record_length ;
		dp = tp + start ;

		j = t_idx % cnt ;

		tp[ j ] += dp [ j ] ;

		t_idx += CUDA_MAX_THREADS ;
	}   
}

// step 1.1 should be to do the abs() 
// step 2 is to do the sum
// record_size does not have the NUM_OF_HVT_INDEX elements
// total is the overall number of data elements, no NUM_OF_HVT_INDEX
int
h_do_l1_norm_step2( int *dp, int total, int record_size )
{
	int nThreadsPerBlock = CUDA_MAX_THREADS_P_BLK ;
	int nBlocks, i, start, row, cnt ;

	start = max_log2( record_size ) ;
	if ( start != record_size )
		start = max_log2(( start / 2 ) - 1 ) ;
	else
		start >>= 1 ;
	
	cnt = record_size - start ;
	row = total / record_size ;

	if ( total % record_size )
	{
		fprintf( stderr, "h_do_l1_norm_step2: error size %d %d \n", total, record_size ) ;
		return ( 0 ) ;
	}

	while ( cnt > 0 ) 
	{
		i = row * cnt ;

		printf("row %d cnt %d i %d start %d\n", row, cnt, i, start ) ;
		
		// nBlocks= ( i + ( nThreadsPerBlock - 1 ))/nThreadsPerBlock ;

		h_block_adj ( i, nThreadsPerBlock, &nBlocks ) ;

		d_do_l1_norm_step2 <<< nBlocks, nThreadsPerBlock >>> (
			dp + NUM_OF_HVT_INDEX, i, record_size + NUM_OF_HVT_INDEX,
			start, cnt ) ;

		cudaThreadSynchronize() ;

		start >>= 1 ;
		cnt = start ;
	}
	return ( 1 ) ;
}

#define MAX_L1_NORM			1000

// step 3 is to get 1-|y0-yk|/|y0| 
// row_size is the number of rows ... 
// record_length includes the NUM_OF_HVT_INDEX
// dp starts with valid data, see caller

__global__ void d_do_l1_norm_step3 ( int *dp, int row_size, int record_length,
	int *op )
{
	int *odp, t_idx = blockIdx.x * blockDim.x + threadIdx.x;

	odp = dp ;
	while ( t_idx < row_size )
	{
		dp = odp ;

		dp += t_idx * record_length ;

		// skip the orig
		if ( dp != op ) 
			*dp = MAX_L1_NORM - ( MAX_L1_NORM * ( *dp )) / (*op) ;

		t_idx += CUDA_MAX_THREADS ;
	}   
}

// record_size does not have the NUM_OF_HVT_INDEX elements
// total is the overall number of data elements, no NUM_OF_HVT_INDEX
int
h_do_l1_norm_step3( int *dp, int total, int record_size, int orig )
{
	int nThreadsPerBlock = CUDA_MAX_THREADS_P_BLK ;
	int i, nBlocks ;

	if ( total % record_size )
	{
		fprintf( stderr, "h_do_l1_norm_step3: error size %d %d \n", total, record_size ) ;
		return ( 0 ) ;
	}

	i = total / record_size ;

	// nBlocks= ( i + ( nThreadsPerBlock - 1 ))/nThreadsPerBlock ;

	h_block_adj ( i, nThreadsPerBlock, &nBlocks ) ;

	d_do_l1_norm_step3 <<< nBlocks, nThreadsPerBlock >>> (
		dp + NUM_OF_HVT_INDEX, i, record_size + NUM_OF_HVT_INDEX,
		dp + orig * ( record_size + NUM_OF_HVT_INDEX ) + NUM_OF_HVT_INDEX ) ;

	cudaThreadSynchronize() ;

	return ( 1 ) ;
}

// to find the min
// row_size is the number of rows for this addition operation
// record_length includes the NUM_OF_HVT_INDEX
// dp starts with idx 0 of NUM_OF_HVT_INDEX, see caller

__global__ void d_do_l1_norm_step4 ( int *dp, int cnt, int record_length,
	int start )
{
	int t_idx = blockIdx.x * blockDim.x + threadIdx.x;
	int *odp, *tp ;

	odp = dp ;
	while ( t_idx < cnt )
	{
		dp = odp ;

		tp = dp + t_idx * record_length ;
		dp = tp + start * record_length ;

		if ( *dp >= 0 )
		{
			if ( *dp < *tp )
			{
				*tp-- = *dp-- ;	// value
				*tp-- = *dp-- ;	// h
				*tp-- = *dp-- ;	// v
				*tp-- = *dp ;	// t
			}
		}

		t_idx += CUDA_MAX_THREADS ;
	}   
}

// step 4 is find the min 
// record_size does not have the NUM_OF_HVT_INDEX elements
// total is the overall number of data elements, no NUM_OF_HVT_INDEX
int
h_do_l1_norm_step4( int *dp, int total, int record_size, int orig,
	int *v )
{
	int nThreadsPerBlock = CUDA_MAX_THREADS_P_BLK ;
	int nBlocks, i, start, row, cnt ;
	int a[4] ;

	if ( total % record_size )
	{
		fprintf( stderr, "%s: error size %d %d \n", __func__, total,
			record_size ) ;
		return ( 0 ) ;
	}

	row = total / record_size ;

	if ( orig >= row )
	{
		fprintf( stderr, "%s: error orig %d row %d \n", __func__,
			orig, row ) ;
		return ( 0 ) ;
	}

	start = MAX_L1_NORM + 1 ;

	if (( i = cudaMemcpy( dp + orig * ( record_size + NUM_OF_HVT_INDEX ) +
		NUM_OF_HVT_INDEX, &start, sizeof( int ), cudaMemcpyHostToDevice))
		!= cudaSuccess )
	{
		printf("%s: download orig : %d\n", __func__, i ) ;
		return ( 0 ) ; 
	}

	start = max_log2( row ) ;
	if ( start != row )
		start = max_log2(( start / 2 ) - 1 ) ;
	else
		start >>= 1 ;
	
	cnt = row - start ;

	while ( cnt > 0 ) 
	{
		printf("row %d cnt %d start %d\n", row, cnt, start ) ;
		
		// nBlocks= ( cnt + ( nThreadsPerBlock - 1 ))/nThreadsPerBlock ;

		h_block_adj ( cnt, nThreadsPerBlock, &nBlocks ) ;

		d_do_l1_norm_step4 <<< nBlocks, nThreadsPerBlock >>> (
			dp + NUM_OF_HVT_INDEX, cnt, record_size + NUM_OF_HVT_INDEX,
			start ) ;

		cudaThreadSynchronize() ;

		start >>= 1 ;
		cnt = start ;
	}

	if (( i = cudaMemcpy( a, dp, 4 * sizeof( int ), cudaMemcpyDeviceToHost ))
		!= cudaSuccess )
	{
		printf("%s: upload orig : %d\n", __func__, i ) ;
		return ( 0 ) ; 
	}

	*v++ = a[0] ;
	*v++ = a[1] ;
	*v++ = a[2] ;
	*v++ = a[3] ;

	return ( 1 ) ;
}

	.file	"tmpxft_0032339b_00000000-6_cs_motion_detect.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2054:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2054:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z49__device_stub__Z21d_do_motion_detectionPiS_iiiiiiPiS_iiiiii
	.type	_Z49__device_stub__Z21d_do_motion_detectionPiS_iiiiiiPiS_iiiiii, @function
_Z49__device_stub__Z21d_do_motion_detectionPiS_iiiiiiPiS_iiiiii:
.LFB2076:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	48(%rsp), %rcx
	movl	%r8d, 4(%rsp)
	movl	%r9d, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 136(%rsp)
	movq	%rsp, %rax
	movq	%rax, 144(%rsp)
	leaq	192(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	200(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	48(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z21d_do_motion_detectionPiS_iiiiii(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 208
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L2:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2076:
	.size	_Z49__device_stub__Z21d_do_motion_detectionPiS_iiiiiiPiS_iiiiii, .-_Z49__device_stub__Z21d_do_motion_detectionPiS_iiiiiiPiS_iiiiii
	.globl	_Z21d_do_motion_detectionPiS_iiiiii
	.type	_Z21d_do_motion_detectionPiS_iiiiii, @function
_Z21d_do_motion_detectionPiS_iiiiii:
.LFB2077:
	.cfi_startproc
	endbr64
	jmp	_Z49__device_stub__Z21d_do_motion_detectionPiS_iiiiiiPiS_iiiiii
	.cfi_endproc
.LFE2077:
	.size	_Z21d_do_motion_detectionPiS_iiiiii, .-_Z21d_do_motion_detectionPiS_iiiiii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"h_do_motion_detection"
.LC1:
	.string	"%s: error size %d cube %d rec %d\n"
	.text
	.globl	_Z21h_do_motion_detectionPiS_iiiiii
	.type	_Z21h_do_motion_detectionPiS_iiiiii, @function
_Z21h_do_motion_detectionPiS_iiiiii:
.LFB2046:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movl	%ecx, %ebx
	subq	$72, %rsp
	.cfi_def_cfa_offset 128
	movl	%edx, 12(%rsp)
	movl	136(%rsp), %ebp
	movq	%fs:40, %rax
	movq	%rax, 56(%rsp)
	movl	%edx, %eax
	cltd
	idivl	%ebp
	testl	%edx, %edx
	jne	.L9
	leal	-3(%rcx), %eax
	cltd
	idivl	%ebp
	testl	%edx, %edx
	je	.L10
.L9:
	pushq	%rcx
	.cfi_def_cfa_offset 136
	movq	stderr(%rip), %rdi
	movl	$2, %esi
	movl	%ebp, %r9d
	pushq	%rbx
	.cfi_def_cfa_offset 144
	movl	28(%rsp), %r8d
	leaq	.LC0(%rip), %rcx
	xorl	%eax, %eax
	leaq	.LC1(%rip), %rdx
	call	__fprintf_chk@PLT
	popq	%rsi
	.cfi_def_cfa_offset 136
	xorl	%eax, %eax
	popq	%rdi
	.cfi_def_cfa_offset 128
	jmp	.L8
.L10:
	movq	%rdi, %r12
	movl	12(%rsp), %edi
	leaq	28(%rsp), %rdx
	movq	%rsi, %r13
	movl	$512, %esi
	movl	%r8d, %r14d
	movl	%r9d, %r15d
	call	_Z11h_block_adjiiPi@PLT
	movl	28(%rsp), %eax
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$8388609, %edx
	movl	$1, %ecx
	movl	%eax, 32(%rsp)
	salq	$9, %rdx
	movabsq	$4294967297, %rax
	movq	%rax, 36(%rsp)
	movq	32(%rsp), %rdi
	movl	40(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L12
	pushq	%rbp
	.cfi_def_cfa_offset 136
	movl	136(%rsp), %eax
	movl	%r15d, %r9d
	movl	%r14d, %r8d
	movl	%ebx, %ecx
	movq	%r13, %rsi
	movq	%r12, %rdi
	pushq	%rax
	.cfi_def_cfa_offset 144
	movl	28(%rsp), %edx
	call	_Z49__device_stub__Z21d_do_motion_detectionPiS_iiiiiiPiS_iiiiii
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L12:
	call	cudaThreadSynchronize@PLT
	movl	$1, %eax
.L8:
	movq	56(%rsp), %rdx
	subq	%fs:40, %rdx
	je	.L13
	call	__stack_chk_fail@PLT
.L13:
	addq	$72, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2046:
	.size	_Z21h_do_motion_detectionPiS_iiiiii, .-_Z21h_do_motion_detectionPiS_iiiiii
	.globl	_Z40__device_stub__Z15d_do_motion_idxPiiiiiiPiiiiii
	.type	_Z40__device_stub__Z15d_do_motion_idxPiiiiiiPiiiiii, @function
_Z40__device_stub__Z15d_do_motion_idxPiiiiiiPiiiiii:
.LFB2078:
	.cfi_startproc
	endbr64
	subq	$168, %rsp
	.cfi_def_cfa_offset 176
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movl	%esi, 20(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 16(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 12(%rsp)
	leaq	48(%rsp), %rcx
	movl	%r8d, 8(%rsp)
	movl	%r9d, 4(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 152(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 144(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L15
	pushq	48(%rsp)
	.cfi_def_cfa_offset 184
	leaq	_Z15d_do_motion_idxPiiiiii(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 192
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 184
	popq	%rdx
	.cfi_def_cfa_offset 176
.L15:
	movq	152(%rsp), %rax
	subq	%fs:40, %rax
	je	.L17
	call	__stack_chk_fail@PLT
.L17:
	addq	$168, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2078:
	.size	_Z40__device_stub__Z15d_do_motion_idxPiiiiiiPiiiiii, .-_Z40__device_stub__Z15d_do_motion_idxPiiiiiiPiiiiii
	.globl	_Z15d_do_motion_idxPiiiiii
	.type	_Z15d_do_motion_idxPiiiiii, @function
_Z15d_do_motion_idxPiiiiii:
.LFB2079:
	.cfi_startproc
	endbr64
	jmp	_Z40__device_stub__Z15d_do_motion_idxPiiiiiiPiiiiii
	.cfi_endproc
.LFE2079:
	.size	_Z15d_do_motion_idxPiiiiii, .-_Z15d_do_motion_idxPiiiiii
	.section	.rodata.str1.1
.LC2:
	.string	"h_do_motion_idx"
.LC3:
	.string	"%s: size needed %d got %d\n"
	.text
	.globl	_Z15h_do_motion_idxPiiiiiiS_
	.type	_Z15h_do_motion_idxPiiiiiiS_, @function
_Z15h_do_motion_idxPiiiiiiS_:
.LFB2047:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movl	%r8d, %r13d
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	imull	%ecx, %r13d
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movl	%r8d, %ebx
	movl	%r13d, %r15d
	imull	%r9d, %r15d
	subq	$72, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 8(%rsp)
	movq	128(%rsp), %r12
	movq	%fs:40, %rax
	movq	%rax, 56(%rsp)
	xorl	%eax, %eax
	leal	3(%rdx), %eax
	movl	%eax, %r8d
	movl	%eax, 4(%rsp)
	imull	%r15d, %r8d
	cmpl	%esi, %r8d
	jle	.L21
	movq	stderr(%rip), %rdi
	movl	%esi, %r9d
	xorl	%eax, %eax
	movl	$2, %esi
	leaq	.LC2(%rip), %rcx
	leaq	.LC3(%rip), %rdx
	call	__fprintf_chk@PLT
	xorl	%eax, %eax
	jmp	.L20
.L21:
	leaq	28(%rsp), %rdx
	movl	$512, %esi
	movl	%r15d, %edi
	movl	%ecx, %ebp
	movl	%r9d, %r14d
	call	_Z11h_block_adjiiPi@PLT
	movl	28(%rsp), %eax
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$8388609, %edx
	movl	$1, %ecx
	movl	%eax, 32(%rsp)
	salq	$9, %rdx
	movabsq	$4294967297, %rax
	movq	%rax, 36(%rsp)
	movq	32(%rsp), %rdi
	movl	40(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L23
	movl	4(%rsp), %edx
	movq	8(%rsp), %rdi
	movl	%r13d, %r9d
	movl	%r14d, %r8d
	movl	%ebp, %ecx
	movl	%r15d, %esi
	call	_Z40__device_stub__Z15d_do_motion_idxPiiiiiiPiiiiii
.L23:
	call	cudaThreadSynchronize@PLT
	movl	%ebx, %eax
	movl	$2, %ecx
	cltd
	idivl	%ecx
	movl	%eax, %ebx
	movl	%ebp, %eax
	cltd
	imull	%ebp, %ebx
	idivl	%ecx
	addl	%ebx, %eax
	movl	%eax, (%r12)
	movl	$1, %eax
.L20:
	movq	56(%rsp), %rdx
	subq	%fs:40, %rdx
	je	.L24
	call	__stack_chk_fail@PLT
.L24:
	addq	$72, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2047:
	.size	_Z15h_do_motion_idxPiiiiiiS_, .-_Z15h_do_motion_idxPiiiiiiS_
	.globl	_Z43__device_stub__Z18d_do_l1_norm_step1PiiiS_iPiiiS_i
	.type	_Z43__device_stub__Z18d_do_l1_norm_step1PiiiS_iPiiiS_i, @function
_Z43__device_stub__Z18d_do_l1_norm_step1PiiiS_iPiiiS_i:
.LFB2080:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rdi
	movl	%esi, 20(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 16(%rsp)
	leaq	32(%rsp), %rdx
	movq	%rcx, 8(%rsp)
	leaq	40(%rsp), %rcx
	movl	%r8d, 4(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L26
	pushq	40(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z18d_do_l1_norm_step1PiiiS_i(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 176
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L26:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L28
	call	__stack_chk_fail@PLT
.L28:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2080:
	.size	_Z43__device_stub__Z18d_do_l1_norm_step1PiiiS_iPiiiS_i, .-_Z43__device_stub__Z18d_do_l1_norm_step1PiiiS_iPiiiS_i
	.globl	_Z18d_do_l1_norm_step1PiiiS_i
	.type	_Z18d_do_l1_norm_step1PiiiS_i, @function
_Z18d_do_l1_norm_step1PiiiS_i:
.LFB2081:
	.cfi_startproc
	endbr64
	jmp	_Z43__device_stub__Z18d_do_l1_norm_step1PiiiS_iPiiiS_i
	.cfi_endproc
.LFE2081:
	.size	_Z18d_do_l1_norm_step1PiiiS_i, .-_Z18d_do_l1_norm_step1PiiiS_i
	.globl	_Z18h_do_l1_norm_step1Piiii
	.type	_Z18h_do_l1_norm_step1Piiii, @function
_Z18h_do_l1_norm_step1Piiii:
.LFB2048:
	.cfi_startproc
	endbr64
	pushq	%r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	movl	%ecx, %r13d
	pushq	%r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	movl	%edx, %r12d
	pushq	%rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	movl	%esi, %ebp
	movl	$512, %esi
	pushq	%rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	movq	%rdi, %rbx
	movl	%ebp, %edi
	subq	$56, %rsp
	.cfi_def_cfa_offset 96
	movq	%fs:40, %rax
	movq	%rax, 40(%rsp)
	xorl	%eax, %eax
	leaq	12(%rsp), %rdx
	call	_Z11h_block_adjiiPi@PLT
	movl	12(%rsp), %eax
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$8388609, %edx
	movl	$1, %ecx
	movl	%eax, 16(%rsp)
	salq	$9, %rdx
	movabsq	$4294967297, %rax
	movq	%rax, 20(%rsp)
	movq	16(%rsp), %rdi
	movl	24(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L32
	leal	3(%r12), %eax
	movl	%r13d, %r8d
	movl	%r12d, %edx
	movl	%ebp, %esi
	imull	%r13d, %eax
	movq	%rbx, %rdi
	cltq
	leaq	12(%rbx,%rax,4), %rcx
	call	_Z43__device_stub__Z18d_do_l1_norm_step1PiiiS_iPiiiS_i
.L32:
	call	cudaThreadSynchronize@PLT
	movq	40(%rsp), %rax
	subq	%fs:40, %rax
	je	.L33
	call	__stack_chk_fail@PLT
.L33:
	addq	$56, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2048:
	.size	_Z18h_do_l1_norm_step1Piiii, .-_Z18h_do_l1_norm_step1Piiii
	.globl	_Z42__device_stub__Z18d_do_l1_norm_step2PiiiiiPiiiii
	.type	_Z42__device_stub__Z18d_do_l1_norm_step2PiiiiiPiiiii, @function
_Z42__device_stub__Z18d_do_l1_norm_step2PiiiiiPiiiii:
.LFB2082:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rdi
	movl	%esi, 20(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 16(%rsp)
	leaq	32(%rsp), %rdx
	movl	%ecx, 12(%rsp)
	leaq	40(%rsp), %rcx
	movl	%r8d, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L35
	pushq	40(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z18d_do_l1_norm_step2Piiiii(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 176
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L35:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L37
	call	__stack_chk_fail@PLT
.L37:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2082:
	.size	_Z42__device_stub__Z18d_do_l1_norm_step2PiiiiiPiiiii, .-_Z42__device_stub__Z18d_do_l1_norm_step2PiiiiiPiiiii
	.globl	_Z18d_do_l1_norm_step2Piiiii
	.type	_Z18d_do_l1_norm_step2Piiiii, @function
_Z18d_do_l1_norm_step2Piiiii:
.LFB2083:
	.cfi_startproc
	endbr64
	jmp	_Z42__device_stub__Z18d_do_l1_norm_step2PiiiiiPiiiii
	.cfi_endproc
.LFE2083:
	.size	_Z18d_do_l1_norm_step2Piiiii, .-_Z18d_do_l1_norm_step2Piiiii
	.section	.rodata.str1.1
.LC4:
	.string	"h_do_l1_norm_step2: error size %d %d \n"
.LC5:
	.string	"row %d cnt %d i %d start %d\n"
	.text
	.globl	_Z18h_do_l1_norm_step2Piii
	.type	_Z18h_do_l1_norm_step2Piii, @function
_Z18h_do_l1_norm_step2Piii:
.LFB2049:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movq	%rdi, %r13
	movl	%edx, %edi
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movl	%esi, %r12d
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movl	%edx, %ebx
	movl	%ebx, %ebp
	sarl	%ebp
	subq	$72, %rsp
	.cfi_def_cfa_offset 128
	movq	%fs:40, %rax
	movq	%rax, 56(%rsp)
	xorl	%eax, %eax
	call	_Z8max_log2i@PLT
	cmpl	%eax, %ebx
	je	.L42
	movl	$2, %ecx
	cltd
	idivl	%ecx
	leal	-1(%rax), %edi
	call	_Z8max_log2i@PLT
	movl	%eax, %ebp
.L42:
	movl	%r12d, %eax
	movl	%ebx, %r14d
	leaq	.LC5(%rip), %r15
	cltd
	subl	%ebp, %r14d
	idivl	%ebx
	movl	%eax, 12(%rsp)
	testl	%edx, %edx
	je	.L43
	movq	stderr(%rip), %rdi
	movl	%ebx, %r8d
	movl	%r12d, %ecx
	xorl	%eax, %eax
	leaq	.LC4(%rip), %rdx
	movl	$2, %esi
	call	__fprintf_chk@PLT
	xorl	%eax, %eax
	jmp	.L40
.L46:
	movl	12(%rsp), %r12d
	movl	12(%rsp), %edx
	movl	%ebp, %r9d
	movl	%r14d, %ecx
	movq	%r15, %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	imull	%r14d, %r12d
	movl	%r12d, %r8d
	call	__printf_chk@PLT
	leaq	28(%rsp), %rdx
	movl	$512, %esi
	movl	%r12d, %edi
	call	_Z11h_block_adjiiPi@PLT
	movl	28(%rsp), %eax
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$8388609, %edx
	movl	$1, %ecx
	movl	%eax, 32(%rsp)
	salq	$9, %rdx
	movabsq	$4294967297, %rax
	movq	%rax, 36(%rsp)
	movq	32(%rsp), %rdi
	movl	40(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L45
	leal	3(%rbx), %edx
	leaq	12(%r13), %rdi
	movl	%r14d, %r8d
	movl	%ebp, %ecx
	movl	%r12d, %esi
	call	_Z42__device_stub__Z18d_do_l1_norm_step2PiiiiiPiiiii
.L45:
	call	cudaThreadSynchronize@PLT
	sarl	%ebp
	movl	%ebp, %r14d
.L43:
	testl	%r14d, %r14d
	jg	.L46
	movl	$1, %eax
.L40:
	movq	56(%rsp), %rdx
	subq	%fs:40, %rdx
	je	.L47
	call	__stack_chk_fail@PLT
.L47:
	addq	$72, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2049:
	.size	_Z18h_do_l1_norm_step2Piii, .-_Z18h_do_l1_norm_step2Piii
	.globl	_Z42__device_stub__Z18d_do_l1_norm_step3PiiiS_PiiiS_
	.type	_Z42__device_stub__Z18d_do_l1_norm_step3PiiiS_PiiiS_, @function
_Z42__device_stub__Z18d_do_l1_norm_step3PiiiS_PiiiS_:
.LFB2084:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movl	%esi, 20(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 16(%rsp)
	leaq	40(%rsp), %rdx
	movq	%rcx, 8(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L51
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z18d_do_l1_norm_step3PiiiS_(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L51:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L53
	call	__stack_chk_fail@PLT
.L53:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2084:
	.size	_Z42__device_stub__Z18d_do_l1_norm_step3PiiiS_PiiiS_, .-_Z42__device_stub__Z18d_do_l1_norm_step3PiiiS_PiiiS_
	.globl	_Z18d_do_l1_norm_step3PiiiS_
	.type	_Z18d_do_l1_norm_step3PiiiS_, @function
_Z18d_do_l1_norm_step3PiiiS_:
.LFB2085:
	.cfi_startproc
	endbr64
	jmp	_Z42__device_stub__Z18d_do_l1_norm_step3PiiiS_PiiiS_
	.cfi_endproc
.LFE2085:
	.size	_Z18d_do_l1_norm_step3PiiiS_, .-_Z18d_do_l1_norm_step3PiiiS_
	.section	.rodata.str1.1
.LC6:
	.string	"h_do_l1_norm_step3: error size %d %d \n"
	.text
	.globl	_Z18h_do_l1_norm_step3Piiii
	.type	_Z18h_do_l1_norm_step3Piiii, @function
_Z18h_do_l1_norm_step3Piiii:
.LFB2050:
	.cfi_startproc
	endbr64
	pushq	%r14
	.cfi_def_cfa_offset 16
	.cfi_offset 14, -16
	pushq	%r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	pushq	%rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	movl	%edx, %ebx
	subq	$56, %rsp
	.cfi_def_cfa_offset 96
	movq	%fs:40, %rax
	movq	%rax, 40(%rsp)
	movl	%esi, %eax
	cltd
	idivl	%ebx
	testl	%edx, %edx
	je	.L57
	movq	stderr(%rip), %rdi
	movl	%esi, %ecx
	movl	%ebx, %r8d
	xorl	%eax, %eax
	leaq	.LC6(%rip), %rdx
	movl	$2, %esi
	call	__fprintf_chk@PLT
	xorl	%eax, %eax
	jmp	.L56
.L57:
	leaq	12(%rsp), %rdx
	movl	$512, %esi
	movq	%rdi, %r12
	movl	%eax, %edi
	movl	%ecx, %ebp
	movl	%eax, %r14d
	call	_Z11h_block_adjiiPi@PLT
	movl	12(%rsp), %eax
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$8388609, %edx
	movl	$1, %ecx
	movl	%eax, 16(%rsp)
	salq	$9, %rdx
	movabsq	$4294967297, %rax
	movq	%rax, 20(%rsp)
	movq	16(%rsp), %rdi
	movl	24(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L59
	leal	3(%rbx), %edx
	leaq	12(%r12), %rdi
	movl	%r14d, %esi
	imull	%edx, %ebp
	movslq	%ebp, %rbp
	leaq	12(%r12,%rbp,4), %rcx
	call	_Z42__device_stub__Z18d_do_l1_norm_step3PiiiS_PiiiS_
.L59:
	call	cudaThreadSynchronize@PLT
	movl	$1, %eax
.L56:
	movq	40(%rsp), %rdx
	subq	%fs:40, %rdx
	je	.L60
	call	__stack_chk_fail@PLT
.L60:
	addq	$56, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2050:
	.size	_Z18h_do_l1_norm_step3Piiii, .-_Z18h_do_l1_norm_step3Piiii
	.globl	_Z41__device_stub__Z18d_do_l1_norm_step4PiiiiPiiii
	.type	_Z41__device_stub__Z18d_do_l1_norm_step4PiiiiPiiii, @function
_Z41__device_stub__Z18d_do_l1_norm_step4PiiiiPiiii:
.LFB2086:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movl	%esi, 20(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 16(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 12(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L62
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z18d_do_l1_norm_step4Piiii(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L62:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L64
	call	__stack_chk_fail@PLT
.L64:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2086:
	.size	_Z41__device_stub__Z18d_do_l1_norm_step4PiiiiPiiii, .-_Z41__device_stub__Z18d_do_l1_norm_step4PiiiiPiiii
	.globl	_Z18d_do_l1_norm_step4Piiii
	.type	_Z18d_do_l1_norm_step4Piiii, @function
_Z18d_do_l1_norm_step4Piiii:
.LFB2087:
	.cfi_startproc
	endbr64
	jmp	_Z41__device_stub__Z18d_do_l1_norm_step4PiiiiPiiii
	.cfi_endproc
.LFE2087:
	.size	_Z18d_do_l1_norm_step4Piiii, .-_Z18d_do_l1_norm_step4Piiii
	.section	.rodata.str1.1
.LC7:
	.string	"h_do_l1_norm_step4"
.LC8:
	.string	"%s: error size %d %d \n"
.LC9:
	.string	"%s: error orig %d row %d \n"
.LC10:
	.string	"%s: download orig : %d\n"
.LC11:
	.string	"row %d cnt %d start %d\n"
.LC12:
	.string	"%s: upload orig : %d\n"
	.text
	.globl	_Z18h_do_l1_norm_step4PiiiiS_
	.type	_Z18h_do_l1_norm_step4PiiiiS_, @function
_Z18h_do_l1_norm_step4PiiiiS_:
.LFB2051:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movl	%edx, %r9d
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$72, %rsp
	.cfi_def_cfa_offset 128
	movq	%fs:40, %rax
	movq	%rax, 56(%rsp)
	movl	%esi, %eax
	cltd
	idivl	%r9d
	testl	%edx, %edx
	je	.L68
	movl	%esi, %r8d
	leaq	.LC7(%rip), %rcx
	leaq	.LC8(%rip), %rdx
	jmp	.L81
.L68:
	movl	%eax, %ebp
	cmpl	%ecx, %eax
	jg	.L70
	movl	%ecx, %r8d
	movl	%eax, %r9d
	leaq	.LC7(%rip), %rcx
	leaq	.LC9(%rip), %rdx
.L81:
	movq	stderr(%rip), %rdi
	movl	$2, %esi
	xorl	%eax, %eax
	call	__fprintf_chk@PLT
.L69:
	xorl	%eax, %eax
	jmp	.L67
.L70:
	leal	3(%r9), %ebx
	leaq	12(%rsp), %rsi
	movq	%rdi, %r12
	movq	%r8, %r13
	imull	%ebx, %ecx
	movl	$4, %edx
	movl	$1001, 12(%rsp)
	movslq	%ecx, %rcx
	leaq	12(%rdi,%rcx,4), %rdi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	leaq	.LC7(%rip), %rdx
	leaq	.LC10(%rip), %rsi
	movl	%eax, %ecx
	testl	%eax, %eax
	jne	.L82
	movl	%ebp, %edi
	call	_Z8max_log2i@PLT
	movl	%ebp, %r8d
	movl	%eax, 12(%rsp)
	sarl	%r8d
	cmpl	%eax, %ebp
	je	.L74
	movl	$2, %ecx
	cltd
	idivl	%ecx
	leal	-1(%rax), %edi
	call	_Z8max_log2i@PLT
	movl	%eax, %r8d
.L74:
	movl	%ebp, %r14d
	leaq	.LC11(%rip), %r15
	subl	%r8d, %r14d
.L75:
	movl	%r8d, 12(%rsp)
	testl	%r14d, %r14d
	jle	.L83
	movl	%r14d, %ecx
	movl	%ebp, %edx
	movq	%r15, %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	leaq	8(%rsp), %rdx
	movl	$512, %esi
	movl	%r14d, %edi
	call	_Z11h_block_adjiiPi@PLT
	movl	8(%rsp), %eax
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$8388609, %edx
	movl	$1, %ecx
	movl	%eax, 16(%rsp)
	salq	$9, %rdx
	movabsq	$4294967297, %rax
	movq	%rax, 20(%rsp)
	movq	16(%rsp), %rdi
	movl	24(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L76
	movl	12(%rsp), %ecx
	leaq	12(%r12), %rdi
	movl	%ebx, %edx
	movl	%r14d, %esi
	call	_Z41__device_stub__Z18d_do_l1_norm_step4PiiiiPiiii
.L76:
	call	cudaThreadSynchronize@PLT
	movl	12(%rsp), %r14d
	sarl	%r14d
	movl	%r14d, %r8d
	jmp	.L75
.L83:
	movl	$2, %ecx
	leaq	40(%rsp), %rdi
	movl	$16, %edx
	movq	%r12, %rsi
	call	cudaMemcpy@PLT
	movl	%eax, %ecx
	testl	%eax, %eax
	je	.L78
	leaq	.LC7(%rip), %rdx
	leaq	.LC12(%rip), %rsi
.L82:
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	jmp	.L69
.L78:
	movq	40(%rsp), %rax
	movq	%rax, 0(%r13)
	movq	48(%rsp), %rax
	movq	%rax, 8(%r13)
	movl	$1, %eax
.L67:
	movq	56(%rsp), %rdx
	subq	%fs:40, %rdx
	je	.L79
	call	__stack_chk_fail@PLT
.L79:
	addq	$72, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2051:
	.size	_Z18h_do_l1_norm_step4PiiiiS_, .-_Z18h_do_l1_norm_step4PiiiiS_
	.section	.rodata.str1.1
.LC13:
	.string	"_Z18d_do_l1_norm_step4Piiii"
.LC14:
	.string	"_Z18d_do_l1_norm_step3PiiiS_"
.LC15:
	.string	"_Z18d_do_l1_norm_step2Piiiii"
.LC16:
	.string	"_Z18d_do_l1_norm_step1PiiiS_i"
.LC17:
	.string	"_Z15d_do_motion_idxPiiiiii"
.LC18:
	.string	"_Z21d_do_motion_detectionPiS_iiiiii"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2089:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC13(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z18d_do_l1_norm_step4Piiii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC14(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z18d_do_l1_norm_step3PiiiS_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC15(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z18d_do_l1_norm_step2Piiiii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC16(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z18d_do_l1_norm_step1PiiiS_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC17(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z15d_do_motion_idxPiiiiii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC18(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z21d_do_motion_detectionPiS_iiiiii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2089:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include <sys/types.h>
#include <sys/stat.h>
#include <fcntl.h>
#include <stdio.h>
#include <errno.h>
#include <unistd.h>
#include <stdlib.h>
#include <arpa/inet.h>
#include <math.h>
#include "cs_cuda.h"
#include "cs_dbg.h"
#include "cs_helper.h"
#include "cs_motion_detect.h"

// #define CUDA_DBG
// #define CUDA_DBG1

#define NUM_OF_HVT_INDEX	3

__global__ void d_do_motion_detection ( int *fdp, int *tdp, int tbl_size, 
	int record_size, // do include the 3 indexes
	int cx, int cxy_size,
	int mx, int mxy_size )
{
	int t_idx = blockIdx.x * blockDim.x + threadIdx.x;
	int ot_idx, i, j, from, no_idx_size, *dp, h, v, t, tt, hh, vv ;

	ot_idx = t_idx ;
	while ( t_idx < tbl_size )
	{
		no_idx_size = record_size - NUM_OF_HVT_INDEX ;

		i = t_idx / no_idx_size ;
		dp = tdp + ( i * record_size ) ;
		t = *dp++ ;
		v = *dp++ ;
		h = *dp++ ;

		t_idx %= no_idx_size ;

		tt = t_idx / mxy_size ; // which block
		j = t_idx % mxy_size ;
		hh = j % mx ;	// which h
		vv = j / mx ;	// which v

		from = ( t + tt )  * cxy_size + ( v + vv ) * cx + h + hh ;

		dp[ t_idx ] = fdp[ from ] ; 
		// dp[ t_idx ] = from ; 

		ot_idx += CUDA_MAX_THREADS ;
		t_idx = ot_idx ;
	}		
}

// do: 1 block at a time ... 
// block : the result of do_motion_idx <- edge-detection <- L-selection
// cube : the cube that is going to be moved by all h/v/t units
int
h_do_motion_detection ( int *fromp, int *top,
	int tbl_size,		// overall input size ... excludes the 3 indexes
	int record_size,	// includes the 3 indexes
	int blk_x, int blk_xy,	
	int cube_x, int cube_xy )
{
	int nThreadsPerBlock = CUDA_MAX_THREADS_P_BLK ;
	int nBlocks ; // = ( tbl_size + ( nThreadsPerBlock - 1 ))/nThreadsPerBlock ;

#ifdef CUDA_DBG1 
	fprintf(stderr, "%s: f %p t %p tblsize %d rec %d blk %d %d cube %d %d\n",
		__func__, fromp, top, tbl_size, record_size,
		blk_x, blk_xy, cube_x, cube_xy ) ;
#endif 

	if (( tbl_size % cube_xy ) || (( record_size - NUM_OF_HVT_INDEX ) % cube_xy ))
	{
		fprintf(stderr, "%s: error size %d cube %d rec %d\n", __func__,
			tbl_size, cube_xy, record_size ) ;
		return ( 0 ) ;
	}

	h_block_adj ( tbl_size, nThreadsPerBlock, &nBlocks ) ;

	d_do_motion_detection <<< nBlocks, nThreadsPerBlock >>> (
		fromp, top, tbl_size, record_size, blk_x, blk_xy,
		cube_x, cube_xy ) ;

	hipDeviceSynchronize() ;

#ifdef CUDA_OBS 
	dbg_p_d_data_i("motion_detect", top, tbl_size ) ; 
#endif 
	return ( 1 ) ;
}

// 3 indexes + real data length == record_length

__global__ void d_do_motion_idx ( int *dp, int tbl_size, int record_length,
	int h_loop, int t_loop, int hv_size ) 
{
	int *odp, t_idx = blockIdx.x * blockDim.x + threadIdx.x;
	int j ;

	odp = dp ;
	while ( t_idx < tbl_size )
	{
		dp = odp ;

		dp += t_idx * record_length ;

		*dp++ = t_idx / hv_size ;	// tmporal

		j = t_idx % hv_size ;
	
		*dp++ = j / h_loop ;	// vertical
		*dp = j % h_loop ;	// horizontal

		t_idx += CUDA_MAX_THREADS ;
	}   
} 

int
h_do_motion_idx ( int *dp, int total_size, int record_length,
	int h_loop, int v_loop, int t_loop, int *orig_idx )
{
	int nThreadsPerBlock = CUDA_MAX_THREADS_P_BLK ;
	int nBlocks, loopcnt ;

	record_length += NUM_OF_HVT_INDEX ; // 3 indexes .. t/v/h in the beginning ...

	loopcnt = v_loop * h_loop * t_loop ;

	if (( record_length * loopcnt ) > total_size )
	{
		fprintf( stderr, "%s: size needed %d got %d\n",
			__func__, record_length * loopcnt, total_size ) ;
		return ( 0 ) ;
	}

	// nBlocks= ( loopcnt + ( nThreadsPerBlock - 1 ))/nThreadsPerBlock ;

	h_block_adj ( loopcnt, nThreadsPerBlock, &nBlocks ) ;

	d_do_motion_idx <<< nBlocks, nThreadsPerBlock >>> (
		dp, loopcnt, record_length, h_loop, t_loop, h_loop * v_loop ) ;

	hipDeviceSynchronize() ;

	*orig_idx = ( v_loop / 2 ) * h_loop + ( h_loop / 2 ) ;

	return ( 1 ) ;
}

// step one is to get y0-yk

__global__ void d_do_l1_norm_step1 ( int *dp, int tbl_size, int record_length,
	int *op, int orig )
{
	int t_idx = blockIdx.x * blockDim.x + threadIdx.x;
	int *odp, i, j ;

	odp = dp ;
	while ( t_idx < tbl_size )
	{
		dp = odp ;

		j = t_idx / record_length ;

		if ( j != orig )
		{
			i = t_idx % record_length ;

			op += i ;
			dp = dp + j * ( record_length + NUM_OF_HVT_INDEX ) + 
				NUM_OF_HVT_INDEX + i ;

			*dp -= *op ;

			if ( *dp < 0 )
				*dp = -*dp ;	// save a step ... no need to abs()
		}

		t_idx += CUDA_MAX_THREADS ;
	}   
}

// total and record_size does not have the NUM_OF_HVT_INDEX elements
void
h_do_l1_norm_step1( int *dp, int total, int record_size, int orig )
{
	int nThreadsPerBlock = CUDA_MAX_THREADS_P_BLK ;
	int nBlocks ; // = ( total + ( nThreadsPerBlock - 1 ))/nThreadsPerBlock ;
	int *op ;

	op = dp + orig * ( record_size + NUM_OF_HVT_INDEX ) + NUM_OF_HVT_INDEX ;

	h_block_adj ( total, nThreadsPerBlock, &nBlocks ) ;

	d_do_l1_norm_step1 <<< nBlocks, nThreadsPerBlock >>> (
		dp, total, record_size, op, orig ) ;

	hipDeviceSynchronize() ;
}

// step two is to get L1-norm(sum)
// all row, should be after the abs() is done
// tbl_size is the number of elements for this addition operation
// record_length includes the NUM_OF_HVT_INDEX
// dp starts with valid data, see caller

__global__ void d_do_l1_norm_step2 ( int *dp, int tbl_size, int record_length,
	int start, int cnt )
{
	int t_idx = blockIdx.x * blockDim.x + threadIdx.x;
	int *odp, *tp, j ;

	odp = dp ;
	while ( t_idx < tbl_size )
	{
		dp = odp ;

		j = t_idx / cnt ;

		tp = dp + j * record_length ;
		dp = tp + start ;

		j = t_idx % cnt ;

		tp[ j ] += dp [ j ] ;

		t_idx += CUDA_MAX_THREADS ;
	}   
}

// step 1.1 should be to do the abs() 
// step 2 is to do the sum
// record_size does not have the NUM_OF_HVT_INDEX elements
// total is the overall number of data elements, no NUM_OF_HVT_INDEX
int
h_do_l1_norm_step2( int *dp, int total, int record_size )
{
	int nThreadsPerBlock = CUDA_MAX_THREADS_P_BLK ;
	int nBlocks, i, start, row, cnt ;

	start = max_log2( record_size ) ;
	if ( start != record_size )
		start = max_log2(( start / 2 ) - 1 ) ;
	else
		start >>= 1 ;
	
	cnt = record_size - start ;
	row = total / record_size ;

	if ( total % record_size )
	{
		fprintf( stderr, "h_do_l1_norm_step2: error size %d %d \n", total, record_size ) ;
		return ( 0 ) ;
	}

	while ( cnt > 0 ) 
	{
		i = row * cnt ;

		printf("row %d cnt %d i %d start %d\n", row, cnt, i, start ) ;
		
		// nBlocks= ( i + ( nThreadsPerBlock - 1 ))/nThreadsPerBlock ;

		h_block_adj ( i, nThreadsPerBlock, &nBlocks ) ;

		d_do_l1_norm_step2 <<< nBlocks, nThreadsPerBlock >>> (
			dp + NUM_OF_HVT_INDEX, i, record_size + NUM_OF_HVT_INDEX,
			start, cnt ) ;

		hipDeviceSynchronize() ;

		start >>= 1 ;
		cnt = start ;
	}
	return ( 1 ) ;
}

#define MAX_L1_NORM			1000

// step 3 is to get 1-|y0-yk|/|y0| 
// row_size is the number of rows ... 
// record_length includes the NUM_OF_HVT_INDEX
// dp starts with valid data, see caller

__global__ void d_do_l1_norm_step3 ( int *dp, int row_size, int record_length,
	int *op )
{
	int *odp, t_idx = blockIdx.x * blockDim.x + threadIdx.x;

	odp = dp ;
	while ( t_idx < row_size )
	{
		dp = odp ;

		dp += t_idx * record_length ;

		// skip the orig
		if ( dp != op ) 
			*dp = MAX_L1_NORM - ( MAX_L1_NORM * ( *dp )) / (*op) ;

		t_idx += CUDA_MAX_THREADS ;
	}   
}

// record_size does not have the NUM_OF_HVT_INDEX elements
// total is the overall number of data elements, no NUM_OF_HVT_INDEX
int
h_do_l1_norm_step3( int *dp, int total, int record_size, int orig )
{
	int nThreadsPerBlock = CUDA_MAX_THREADS_P_BLK ;
	int i, nBlocks ;

	if ( total % record_size )
	{
		fprintf( stderr, "h_do_l1_norm_step3: error size %d %d \n", total, record_size ) ;
		return ( 0 ) ;
	}

	i = total / record_size ;

	// nBlocks= ( i + ( nThreadsPerBlock - 1 ))/nThreadsPerBlock ;

	h_block_adj ( i, nThreadsPerBlock, &nBlocks ) ;

	d_do_l1_norm_step3 <<< nBlocks, nThreadsPerBlock >>> (
		dp + NUM_OF_HVT_INDEX, i, record_size + NUM_OF_HVT_INDEX,
		dp + orig * ( record_size + NUM_OF_HVT_INDEX ) + NUM_OF_HVT_INDEX ) ;

	hipDeviceSynchronize() ;

	return ( 1 ) ;
}

// to find the min
// row_size is the number of rows for this addition operation
// record_length includes the NUM_OF_HVT_INDEX
// dp starts with idx 0 of NUM_OF_HVT_INDEX, see caller

__global__ void d_do_l1_norm_step4 ( int *dp, int cnt, int record_length,
	int start )
{
	int t_idx = blockIdx.x * blockDim.x + threadIdx.x;
	int *odp, *tp ;

	odp = dp ;
	while ( t_idx < cnt )
	{
		dp = odp ;

		tp = dp + t_idx * record_length ;
		dp = tp + start * record_length ;

		if ( *dp >= 0 )
		{
			if ( *dp < *tp )
			{
				*tp-- = *dp-- ;	// value
				*tp-- = *dp-- ;	// h
				*tp-- = *dp-- ;	// v
				*tp-- = *dp ;	// t
			}
		}

		t_idx += CUDA_MAX_THREADS ;
	}   
}

// step 4 is find the min 
// record_size does not have the NUM_OF_HVT_INDEX elements
// total is the overall number of data elements, no NUM_OF_HVT_INDEX
int
h_do_l1_norm_step4( int *dp, int total, int record_size, int orig,
	int *v )
{
	int nThreadsPerBlock = CUDA_MAX_THREADS_P_BLK ;
	int nBlocks, i, start, row, cnt ;
	int a[4] ;

	if ( total % record_size )
	{
		fprintf( stderr, "%s: error size %d %d \n", __func__, total,
			record_size ) ;
		return ( 0 ) ;
	}

	row = total / record_size ;

	if ( orig >= row )
	{
		fprintf( stderr, "%s: error orig %d row %d \n", __func__,
			orig, row ) ;
		return ( 0 ) ;
	}

	start = MAX_L1_NORM + 1 ;

	if (( i = hipMemcpy( dp + orig * ( record_size + NUM_OF_HVT_INDEX ) +
		NUM_OF_HVT_INDEX, &start, sizeof( int ), hipMemcpyHostToDevice))
		!= hipSuccess )
	{
		printf("%s: download orig : %d\n", __func__, i ) ;
		return ( 0 ) ; 
	}

	start = max_log2( row ) ;
	if ( start != row )
		start = max_log2(( start / 2 ) - 1 ) ;
	else
		start >>= 1 ;
	
	cnt = row - start ;

	while ( cnt > 0 ) 
	{
		printf("row %d cnt %d start %d\n", row, cnt, start ) ;
		
		// nBlocks= ( cnt + ( nThreadsPerBlock - 1 ))/nThreadsPerBlock ;

		h_block_adj ( cnt, nThreadsPerBlock, &nBlocks ) ;

		d_do_l1_norm_step4 <<< nBlocks, nThreadsPerBlock >>> (
			dp + NUM_OF_HVT_INDEX, cnt, record_size + NUM_OF_HVT_INDEX,
			start ) ;

		hipDeviceSynchronize() ;

		start >>= 1 ;
		cnt = start ;
	}

	if (( i = hipMemcpy( a, dp, 4 * sizeof( int ), hipMemcpyDeviceToHost ))
		!= hipSuccess )
	{
		printf("%s: upload orig : %d\n", __func__, i ) ;
		return ( 0 ) ; 
	}

	*v++ = a[0] ;
	*v++ = a[1] ;
	*v++ = a[2] ;
	*v++ = a[3] ;

	return ( 1 ) ;
}

	.text
	.file	"cs_motion_detect.hip"
	.globl	_Z36__device_stub__d_do_motion_detectionPiS_iiiiii # -- Begin function _Z36__device_stub__d_do_motion_detectionPiS_iiiiii
	.type	_Z36__device_stub__d_do_motion_detectionPiS_iiiiii,@function
_Z36__device_stub__d_do_motion_detectionPiS_iiiiii: # @_Z36__device_stub__d_do_motion_detectionPiS_iiiiii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	4(%rsp), %rcx
	movl	%r8d, (%rcx)
	movq	%rsp, %r8
	movl	%r9d, (%r8)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	192(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	200(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z21d_do_motion_detectionPiS_iiiiii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z36__device_stub__d_do_motion_detectionPiS_iiiiii, .Lfunc_end0-_Z36__device_stub__d_do_motion_detectionPiS_iiiiii
	.cfi_endproc
                                        # -- End function
	.globl	_Z21h_do_motion_detectionPiS_iiiiii # -- Begin function _Z21h_do_motion_detectionPiS_iiiiii
	.type	_Z21h_do_motion_detectionPiS_iiiiii,@function
_Z21h_do_motion_detectionPiS_iiiiii:    # @_Z21h_do_motion_detectionPiS_iiiiii
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	pushq	%rax
	.cfi_def_cfa_offset 64
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%ecx, %ebx
	movl	%edx, %ebp
	movl	72(%rsp), %r10d
	movl	%edx, %eax
	cltd
	idivl	%r10d
	testl	%edx, %edx
	jne	.LBB1_2
# %bb.1:
	leal	-3(%rbx), %eax
	cltd
	idivl	%r10d
	testl	%edx, %edx
	jne	.LBB1_2
# %bb.3:
	movq	%rdi, %r13
	movq	%rsi, %r14
	movl	%r8d, %r15d
	movl	%r9d, (%rsp)                    # 4-byte Spill
	leaq	4(%rsp), %r12
	movl	%ebp, %edi
	movl	$512, %esi                      # imm = 0x200
	movq	%r12, %rdx
	callq	_Z11h_block_adjiiPi
	movl	(%r12), %edi
	btsq	$32, %rdi
	movabsq	$4294967296, %rdx               # imm = 0x100000000
	orq	$512, %rdx                      # imm = 0x200
	movl	$1, %r12d
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_5
# %bb.4:
	movl	64(%rsp), %eax
	movq	%r13, %rdi
	movq	%r14, %rsi
	movl	%ebp, %edx
	movl	%ebx, %ecx
	movl	%r15d, %r8d
	movl	(%rsp), %r9d                    # 4-byte Reload
	movl	72(%rsp), %r10d
	pushq	%r10
	.cfi_adjust_cfa_offset 8
	pushq	%rax
	.cfi_adjust_cfa_offset 8
	callq	_Z36__device_stub__d_do_motion_detectionPiS_iiiiii
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
.LBB1_5:
	callq	hipDeviceSynchronize
.LBB1_6:
	movl	%r12d, %eax
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB1_2:
	.cfi_def_cfa_offset 64
	movq	stderr(%rip), %rdi
	xorl	%r12d, %r12d
	movl	$.L.str, %esi
	movl	$.L__func__._Z21h_do_motion_detectionPiS_iiiiii, %edx
	movl	%ebp, %ecx
	movl	%r10d, %r8d
	movl	%ebx, %r9d
	xorl	%eax, %eax
	callq	fprintf
	jmp	.LBB1_6
.Lfunc_end1:
	.size	_Z21h_do_motion_detectionPiS_iiiiii, .Lfunc_end1-_Z21h_do_motion_detectionPiS_iiiiii
	.cfi_endproc
                                        # -- End function
	.globl	_Z30__device_stub__d_do_motion_idxPiiiiii # -- Begin function _Z30__device_stub__d_do_motion_idxPiiiiii
	.type	_Z30__device_stub__d_do_motion_idxPiiiiii,@function
_Z30__device_stub__d_do_motion_idxPiiiiii: # @_Z30__device_stub__d_do_motion_idxPiiiiii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	20(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	16(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	12(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	8(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	4(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z15d_do_motion_idxPiiiiii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z30__device_stub__d_do_motion_idxPiiiiii, .Lfunc_end2-_Z30__device_stub__d_do_motion_idxPiiiiii
	.cfi_endproc
                                        # -- End function
	.globl	_Z15h_do_motion_idxPiiiiiiS_    # -- Begin function _Z15h_do_motion_idxPiiiiiiS_
	.type	_Z15h_do_motion_idxPiiiiiiS_,@function
_Z15h_do_motion_idxPiiiiiiS_:           # @_Z15h_do_motion_idxPiiiiiiS_
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$24, %rsp
	.cfi_def_cfa_offset 80
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%r8d, %r14d
	movl	%ecx, %ebx
	movl	%edx, %r12d
	addl	$3, %r12d
	movl	%r8d, %ebp
	imull	%ecx, %ebp
	movl	%ebp, %r13d
	imull	%r9d, %r13d
	movl	%r13d, %ecx
	imull	%r12d, %ecx
	cmpl	%esi, %ecx
	jg	.LBB3_1
# %bb.2:
	movq	%rdi, 8(%rsp)                   # 8-byte Spill
	movl	%r9d, 4(%rsp)                   # 4-byte Spill
	leaq	20(%rsp), %r15
	movl	%r13d, %edi
	movl	$512, %esi                      # imm = 0x200
	movq	%r15, %rdx
	callq	_Z11h_block_adjiiPi
	movl	(%r15), %edi
	btsq	$32, %rdi
	movabsq	$4294967296, %rdx               # imm = 0x100000000
	orq	$512, %rdx                      # imm = 0x200
	movl	$1, %r15d
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB3_4
# %bb.3:
	movq	8(%rsp), %rdi                   # 8-byte Reload
	movl	%r13d, %esi
	movl	%r12d, %edx
	movl	%ebx, %ecx
	movl	4(%rsp), %r8d                   # 4-byte Reload
	movl	%ebp, %r9d
	callq	_Z30__device_stub__d_do_motion_idxPiiiiii
.LBB3_4:
	callq	hipDeviceSynchronize
	movl	%r14d, %eax
	shrl	$31, %eax
	addl	%r14d, %eax
	sarl	%eax
	imull	%ebx, %eax
	movl	%ebx, %ecx
	shrl	$31, %ecx
	addl	%ebx, %ecx
	sarl	%ecx
	addl	%eax, %ecx
	movq	80(%rsp), %rax
	movl	%ecx, (%rax)
.LBB3_5:
	movl	%r15d, %eax
	addq	$24, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB3_1:
	.cfi_def_cfa_offset 80
	movl	%esi, %r8d
	movq	stderr(%rip), %rdi
	xorl	%r15d, %r15d
	movl	$.L.str.1, %esi
	movl	$.L__func__._Z15h_do_motion_idxPiiiiiiS_, %edx
	xorl	%eax, %eax
	callq	fprintf
	jmp	.LBB3_5
.Lfunc_end3:
	.size	_Z15h_do_motion_idxPiiiiiiS_, .Lfunc_end3-_Z15h_do_motion_idxPiiiiiiS_
	.cfi_endproc
                                        # -- End function
	.globl	_Z33__device_stub__d_do_l1_norm_step1PiiiS_i # -- Begin function _Z33__device_stub__d_do_l1_norm_step1PiiiS_i
	.type	_Z33__device_stub__d_do_l1_norm_step1PiiiS_i,@function
_Z33__device_stub__d_do_l1_norm_step1PiiiS_i: # @_Z33__device_stub__d_do_l1_norm_step1PiiiS_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	12(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	8(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	4(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z18d_do_l1_norm_step1PiiiS_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end4:
	.size	_Z33__device_stub__d_do_l1_norm_step1PiiiS_i, .Lfunc_end4-_Z33__device_stub__d_do_l1_norm_step1PiiiS_i
	.cfi_endproc
                                        # -- End function
	.globl	_Z18h_do_l1_norm_step1Piiii     # -- Begin function _Z18h_do_l1_norm_step1Piiii
	.type	_Z18h_do_l1_norm_step1Piiii,@function
_Z18h_do_l1_norm_step1Piiii:            # @_Z18h_do_l1_norm_step1Piiii
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$16, %rsp
	.cfi_def_cfa_offset 64
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%ecx, %ebx
	movl	%edx, %r14d
	movl	%esi, %ebp
	movq	%rdi, %r15
	leaq	12(%rsp), %r12
	movl	%esi, %edi
	movl	$512, %esi                      # imm = 0x200
	movq	%r12, %rdx
	callq	_Z11h_block_adjiiPi
	movl	(%r12), %edi
	btsq	$32, %rdi
	movabsq	$4294967296, %rdx               # imm = 0x100000000
	orq	$512, %rdx                      # imm = 0x200
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB5_2
# %bb.1:
	leal	3(%r14), %eax
	imull	%ebx, %eax
	cltq
	leaq	(%r15,%rax,4), %rcx
	addq	$12, %rcx
	movq	%r15, %rdi
	movl	%ebp, %esi
	movl	%r14d, %edx
	movl	%ebx, %r8d
	callq	_Z33__device_stub__d_do_l1_norm_step1PiiiS_i
.LBB5_2:
	callq	hipDeviceSynchronize
	addq	$16, %rsp
	.cfi_def_cfa_offset 48
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end5:
	.size	_Z18h_do_l1_norm_step1Piiii, .Lfunc_end5-_Z18h_do_l1_norm_step1Piiii
	.cfi_endproc
                                        # -- End function
	.globl	_Z33__device_stub__d_do_l1_norm_step2Piiiii # -- Begin function _Z33__device_stub__d_do_l1_norm_step2Piiiii
	.type	_Z33__device_stub__d_do_l1_norm_step2Piiiii,@function
_Z33__device_stub__d_do_l1_norm_step2Piiiii: # @_Z33__device_stub__d_do_l1_norm_step2Piiiii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	20(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	16(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	12(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	8(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z18d_do_l1_norm_step2Piiiii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end6:
	.size	_Z33__device_stub__d_do_l1_norm_step2Piiiii, .Lfunc_end6-_Z33__device_stub__d_do_l1_norm_step2Piiiii
	.cfi_endproc
                                        # -- End function
	.globl	_Z18h_do_l1_norm_step2Piii      # -- Begin function _Z18h_do_l1_norm_step2Piii
	.type	_Z18h_do_l1_norm_step2Piii,@function
_Z18h_do_l1_norm_step2Piii:             # @_Z18h_do_l1_norm_step2Piii
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$24, %rsp
	.cfi_def_cfa_offset 80
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%edx, %r12d
	movl	%esi, %r14d
	movq	%rdi, 16(%rsp)                  # 8-byte Spill
	movl	%edx, %edi
	callq	_Z8max_log2i
	cmpl	%r12d, %eax
	jne	.LBB7_1
# %bb.2:
	movl	%r12d, %ebp
	sarl	%ebp
	jmp	.LBB7_3
.LBB7_1:
	movl	%eax, %edi
	shrl	$31, %edi
	addl	%eax, %edi
	sarl	%edi
	decl	%edi
	callq	_Z8max_log2i
	movl	%eax, %ebp
.LBB7_3:
	movl	%r14d, %eax
	cltd
	idivl	%r12d
	testl	%edx, %edx
	jne	.LBB7_11
# %bb.4:                                # %.preheader
	movl	%r12d, %ebx
	subl	%ebp, %ebx
	testl	%ebx, %ebx
	jle	.LBB7_9
# %bb.5:                                # %.lr.ph
	movl	%eax, %r15d
	movabsq	$4294967296, %rax               # imm = 0x100000000
	addq	$12, 16(%rsp)                   # 8-byte Folded Spill
	addl	$3, %r12d
	movl	%r12d, 8(%rsp)                  # 4-byte Spill
	movq	%rax, %r13
	leaq	512(%rax), %r14
.LBB7_6:                                # =>This Inner Loop Header: Depth=1
	movl	%ebx, %r12d
	imull	%r15d, %r12d
	movl	$.L.str.3, %edi
	movl	%r15d, %esi
	movl	%ebx, %edx
	movl	%r12d, %ecx
	movl	%ebp, %r8d
	xorl	%eax, %eax
	callq	printf
	movl	%r12d, %edi
	movl	$512, %esi                      # imm = 0x200
	leaq	12(%rsp), %rdx
	callq	_Z11h_block_adjiiPi
	movl	12(%rsp), %edi
	orq	%r13, %rdi
	movl	$1, %esi
	movq	%r14, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB7_8
# %bb.7:                                #   in Loop: Header=BB7_6 Depth=1
	movq	16(%rsp), %rdi                  # 8-byte Reload
	movl	%r12d, %esi
	movl	8(%rsp), %edx                   # 4-byte Reload
	movl	%ebp, %ecx
	movl	%ebx, %r8d
	callq	_Z33__device_stub__d_do_l1_norm_step2Piiiii
.LBB7_8:                                #   in Loop: Header=BB7_6 Depth=1
	callq	hipDeviceSynchronize
	sarl	%ebp
	movl	%ebp, %ebx
	testl	%ebp, %ebp
	jg	.LBB7_6
.LBB7_9:
	movl	$1, %ebx
.LBB7_10:                               # %.loopexit
	movl	%ebx, %eax
	addq	$24, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB7_11:
	.cfi_def_cfa_offset 80
	movq	stderr(%rip), %rdi
	xorl	%ebx, %ebx
	movl	$.L.str.2, %esi
	movl	%r14d, %edx
	movl	%r12d, %ecx
	xorl	%eax, %eax
	callq	fprintf
	jmp	.LBB7_10
.Lfunc_end7:
	.size	_Z18h_do_l1_norm_step2Piii, .Lfunc_end7-_Z18h_do_l1_norm_step2Piii
	.cfi_endproc
                                        # -- End function
	.globl	_Z33__device_stub__d_do_l1_norm_step3PiiiS_ # -- Begin function _Z33__device_stub__d_do_l1_norm_step3PiiiS_
	.type	_Z33__device_stub__d_do_l1_norm_step3PiiiS_,@function
_Z33__device_stub__d_do_l1_norm_step3PiiiS_: # @_Z33__device_stub__d_do_l1_norm_step3PiiiS_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	12(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	8(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z18d_do_l1_norm_step3PiiiS_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end8:
	.size	_Z33__device_stub__d_do_l1_norm_step3PiiiS_, .Lfunc_end8-_Z33__device_stub__d_do_l1_norm_step3PiiiS_
	.cfi_endproc
                                        # -- End function
	.globl	_Z18h_do_l1_norm_step3Piiii     # -- Begin function _Z18h_do_l1_norm_step3Piiii
	.type	_Z18h_do_l1_norm_step3Piiii,@function
_Z18h_do_l1_norm_step3Piiii:            # @_Z18h_do_l1_norm_step3Piiii
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$16, %rsp
	.cfi_def_cfa_offset 64
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%edx, %ebx
	movl	%esi, %eax
	cltd
	idivl	%ebx
	testl	%edx, %edx
	jne	.LBB9_1
# %bb.2:
	movl	%ecx, %ebp
	movq	%rdi, %r14
	movl	%eax, %r15d
	leaq	12(%rsp), %r12
	movl	%eax, %edi
	movl	$512, %esi                      # imm = 0x200
	movq	%r12, %rdx
	callq	_Z11h_block_adjiiPi
	movl	(%r12), %edi
	btsq	$32, %rdi
	movabsq	$4294967296, %rdx               # imm = 0x100000000
	orq	$512, %rdx                      # imm = 0x200
	movl	$1, %r12d
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB9_4
# %bb.3:
	addl	$3, %ebx
	imull	%ebx, %ebp
	movslq	%ebp, %rax
	leaq	(%r14,%rax,4), %rcx
	addq	$12, %rcx
	addq	$12, %r14
	movq	%r14, %rdi
	movl	%r15d, %esi
	movl	%ebx, %edx
	callq	_Z33__device_stub__d_do_l1_norm_step3PiiiS_
.LBB9_4:
	callq	hipDeviceSynchronize
.LBB9_5:
	movl	%r12d, %eax
	addq	$16, %rsp
	.cfi_def_cfa_offset 48
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB9_1:
	.cfi_def_cfa_offset 64
	movl	%esi, %ecx
	movq	stderr(%rip), %rdi
	xorl	%r12d, %r12d
	movl	$.L.str.4, %esi
	movl	%ecx, %edx
	movl	%ebx, %ecx
	xorl	%eax, %eax
	callq	fprintf
	jmp	.LBB9_5
.Lfunc_end9:
	.size	_Z18h_do_l1_norm_step3Piiii, .Lfunc_end9-_Z18h_do_l1_norm_step3Piiii
	.cfi_endproc
                                        # -- End function
	.globl	_Z33__device_stub__d_do_l1_norm_step4Piiii # -- Begin function _Z33__device_stub__d_do_l1_norm_step4Piiii
	.type	_Z33__device_stub__d_do_l1_norm_step4Piiii,@function
_Z33__device_stub__d_do_l1_norm_step4Piiii: # @_Z33__device_stub__d_do_l1_norm_step4Piiii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	20(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	16(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	12(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z18d_do_l1_norm_step4Piiii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end10:
	.size	_Z33__device_stub__d_do_l1_norm_step4Piiii, .Lfunc_end10-_Z33__device_stub__d_do_l1_norm_step4Piiii
	.cfi_endproc
                                        # -- End function
	.globl	_Z18h_do_l1_norm_step4PiiiiS_   # -- Begin function _Z18h_do_l1_norm_step4PiiiiS_
	.type	_Z18h_do_l1_norm_step4PiiiiS_,@function
_Z18h_do_l1_norm_step4PiiiiS_:          # @_Z18h_do_l1_norm_step4PiiiiS_
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$56, %rsp
	.cfi_def_cfa_offset 112
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%edx, %ebp
	movl	%esi, %eax
	cltd
	idivl	%ebp
	testl	%edx, %edx
	jne	.LBB11_1
# %bb.2:
	movl	%eax, %r12d
	movl	%eax, %r15d
	cmpl	%ecx, %eax
	jle	.LBB11_3
# %bb.5:
	movq	%r8, %rbx
	movq	%rdi, %r14
	movq	%rsp, %rsi
	movl	$1001, (%rsi)                   # imm = 0x3E9
	addl	$3, %ebp
	imull	%ebp, %ecx
	movslq	%ecx, %rax
	leaq	(%rdi,%rax,4), %rdi
	addq	$12, %rdi
	movl	$4, %edx
	movl	$1, %ecx
	callq	hipMemcpy
	testl	%eax, %eax
	je	.LBB11_8
# %bb.6:
	xorl	%ebx, %ebx
	movl	$.L.str.7, %edi
	jmp	.LBB11_7
.LBB11_8:
	movq	%rbx, 40(%rsp)                  # 8-byte Spill
	movl	%r15d, %edi
	callq	_Z8max_log2i
	movl	%eax, (%rsp)
	cmpl	%r12d, %eax
	movq	%r14, 8(%rsp)                   # 8-byte Spill
	jne	.LBB11_9
# %bb.10:
	movl	%r12d, %ecx
	sarl	%ecx
	jmp	.LBB11_11
.LBB11_9:
	movl	%eax, %edi
	shrl	$31, %edi
	addl	%eax, %edi
	sarl	%edi
	decl	%edi
	callq	_Z8max_log2i
	movl	%eax, %ecx
.LBB11_11:
	movl	%ecx, (%rsp)
	subl	%ecx, %r12d
	jle	.LBB11_16
# %bb.12:                               # %.lr.ph
	movabsq	$4294967296, %r13               # imm = 0x100000000
	movq	8(%rsp), %rax                   # 8-byte Reload
	addq	$12, %rax
	movq	%rax, 48(%rsp)                  # 8-byte Spill
	leaq	4(%rsp), %rbx
	leaq	512(%r13), %r14
.LBB11_13:                              # =>This Inner Loop Header: Depth=1
	movl	$.L.str.8, %edi
	movl	%r15d, %esi
	movl	%r12d, %edx
	xorl	%eax, %eax
	callq	printf
	movl	%r12d, %edi
	movl	$512, %esi                      # imm = 0x200
	movq	%rbx, %rdx
	callq	_Z11h_block_adjiiPi
	movl	4(%rsp), %edi
	orq	%r13, %rdi
	movl	$1, %esi
	movq	%r14, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB11_15
# %bb.14:                               #   in Loop: Header=BB11_13 Depth=1
	movl	(%rsp), %ecx
	movq	48(%rsp), %rdi                  # 8-byte Reload
	movl	%r12d, %esi
	movl	%ebp, %edx
	callq	_Z33__device_stub__d_do_l1_norm_step4Piiii
.LBB11_15:                              #   in Loop: Header=BB11_13 Depth=1
	callq	hipDeviceSynchronize
	movl	(%rsp), %ecx
	sarl	%ecx
	movl	%ecx, (%rsp)
	movl	%ecx, %r12d
	testl	%ecx, %ecx
	jg	.LBB11_13
.LBB11_16:                              # %._crit_edge
	leaq	16(%rsp), %rdi
	movl	$16, %edx
	movq	8(%rsp), %rsi                   # 8-byte Reload
	movl	$2, %ecx
	callq	hipMemcpy
	testl	%eax, %eax
	je	.LBB11_18
# %bb.17:
	xorl	%ebx, %ebx
	movl	$.L.str.9, %edi
.LBB11_7:
	movl	$.L__func__._Z18h_do_l1_norm_step4PiiiiS_, %esi
	movl	%eax, %edx
	xorl	%eax, %eax
	callq	printf
.LBB11_19:
	movl	%ebx, %eax
	addq	$56, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB11_18:
	.cfi_def_cfa_offset 112
	movl	16(%rsp), %eax
	movq	40(%rsp), %rcx                  # 8-byte Reload
	movl	%eax, (%rcx)
	movl	20(%rsp), %eax
	movl	%eax, 4(%rcx)
	movl	24(%rsp), %eax
	movl	%eax, 8(%rcx)
	movl	28(%rsp), %eax
	movl	%eax, 12(%rcx)
	movl	$1, %ebx
	jmp	.LBB11_19
.LBB11_1:
	movl	%esi, %r8d
	movq	stderr(%rip), %rdi
	xorl	%ebx, %ebx
	movl	$.L.str.5, %esi
	movl	$.L__func__._Z18h_do_l1_norm_step4PiiiiS_, %edx
	movl	%r8d, %ecx
	movl	%ebp, %r8d
	jmp	.LBB11_4
.LBB11_3:
	movq	stderr(%rip), %rdi
	xorl	%ebx, %ebx
	movl	$.L.str.6, %esi
	movl	$.L__func__._Z18h_do_l1_norm_step4PiiiiS_, %edx
	movl	%r15d, %r8d
.LBB11_4:
	xorl	%eax, %eax
	callq	fprintf
	jmp	.LBB11_19
.Lfunc_end11:
	.size	_Z18h_do_l1_norm_step4PiiiiS_, .Lfunc_end11-_Z18h_do_l1_norm_step4PiiiiS_
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB12_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB12_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z21d_do_motion_detectionPiS_iiiiii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z15d_do_motion_idxPiiiiii, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z18d_do_l1_norm_step1PiiiS_i, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z18d_do_l1_norm_step2Piiiii, %esi
	movl	$.L__unnamed_4, %edx
	movl	$.L__unnamed_4, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z18d_do_l1_norm_step3PiiiS_, %esi
	movl	$.L__unnamed_5, %edx
	movl	$.L__unnamed_5, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z18d_do_l1_norm_step4Piiii, %esi
	movl	$.L__unnamed_6, %edx
	movl	$.L__unnamed_6, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end12:
	.size	__hip_module_ctor, .Lfunc_end12-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB13_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB13_2:
	retq
.Lfunc_end13:
	.size	__hip_module_dtor, .Lfunc_end13-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z21d_do_motion_detectionPiS_iiiiii,@object # @_Z21d_do_motion_detectionPiS_iiiiii
	.section	.rodata,"a",@progbits
	.globl	_Z21d_do_motion_detectionPiS_iiiiii
	.p2align	3, 0x0
_Z21d_do_motion_detectionPiS_iiiiii:
	.quad	_Z36__device_stub__d_do_motion_detectionPiS_iiiiii
	.size	_Z21d_do_motion_detectionPiS_iiiiii, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"%s: error size %d cube %d rec %d\n"
	.size	.L.str, 34

	.type	.L__func__._Z21h_do_motion_detectionPiS_iiiiii,@object # @__func__._Z21h_do_motion_detectionPiS_iiiiii
.L__func__._Z21h_do_motion_detectionPiS_iiiiii:
	.asciz	"h_do_motion_detection"
	.size	.L__func__._Z21h_do_motion_detectionPiS_iiiiii, 22

	.type	_Z15d_do_motion_idxPiiiiii,@object # @_Z15d_do_motion_idxPiiiiii
	.section	.rodata,"a",@progbits
	.globl	_Z15d_do_motion_idxPiiiiii
	.p2align	3, 0x0
_Z15d_do_motion_idxPiiiiii:
	.quad	_Z30__device_stub__d_do_motion_idxPiiiiii
	.size	_Z15d_do_motion_idxPiiiiii, 8

	.type	.L.str.1,@object                # @.str.1
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str.1:
	.asciz	"%s: size needed %d got %d\n"
	.size	.L.str.1, 27

	.type	.L__func__._Z15h_do_motion_idxPiiiiiiS_,@object # @__func__._Z15h_do_motion_idxPiiiiiiS_
.L__func__._Z15h_do_motion_idxPiiiiiiS_:
	.asciz	"h_do_motion_idx"
	.size	.L__func__._Z15h_do_motion_idxPiiiiiiS_, 16

	.type	_Z18d_do_l1_norm_step1PiiiS_i,@object # @_Z18d_do_l1_norm_step1PiiiS_i
	.section	.rodata,"a",@progbits
	.globl	_Z18d_do_l1_norm_step1PiiiS_i
	.p2align	3, 0x0
_Z18d_do_l1_norm_step1PiiiS_i:
	.quad	_Z33__device_stub__d_do_l1_norm_step1PiiiS_i
	.size	_Z18d_do_l1_norm_step1PiiiS_i, 8

	.type	_Z18d_do_l1_norm_step2Piiiii,@object # @_Z18d_do_l1_norm_step2Piiiii
	.globl	_Z18d_do_l1_norm_step2Piiiii
	.p2align	3, 0x0
_Z18d_do_l1_norm_step2Piiiii:
	.quad	_Z33__device_stub__d_do_l1_norm_step2Piiiii
	.size	_Z18d_do_l1_norm_step2Piiiii, 8

	.type	.L.str.2,@object                # @.str.2
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str.2:
	.asciz	"h_do_l1_norm_step2: error size %d %d \n"
	.size	.L.str.2, 39

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"row %d cnt %d i %d start %d\n"
	.size	.L.str.3, 29

	.type	_Z18d_do_l1_norm_step3PiiiS_,@object # @_Z18d_do_l1_norm_step3PiiiS_
	.section	.rodata,"a",@progbits
	.globl	_Z18d_do_l1_norm_step3PiiiS_
	.p2align	3, 0x0
_Z18d_do_l1_norm_step3PiiiS_:
	.quad	_Z33__device_stub__d_do_l1_norm_step3PiiiS_
	.size	_Z18d_do_l1_norm_step3PiiiS_, 8

	.type	.L.str.4,@object                # @.str.4
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str.4:
	.asciz	"h_do_l1_norm_step3: error size %d %d \n"
	.size	.L.str.4, 39

	.type	_Z18d_do_l1_norm_step4Piiii,@object # @_Z18d_do_l1_norm_step4Piiii
	.section	.rodata,"a",@progbits
	.globl	_Z18d_do_l1_norm_step4Piiii
	.p2align	3, 0x0
_Z18d_do_l1_norm_step4Piiii:
	.quad	_Z33__device_stub__d_do_l1_norm_step4Piiii
	.size	_Z18d_do_l1_norm_step4Piiii, 8

	.type	.L.str.5,@object                # @.str.5
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str.5:
	.asciz	"%s: error size %d %d \n"
	.size	.L.str.5, 23

	.type	.L__func__._Z18h_do_l1_norm_step4PiiiiS_,@object # @__func__._Z18h_do_l1_norm_step4PiiiiS_
.L__func__._Z18h_do_l1_norm_step4PiiiiS_:
	.asciz	"h_do_l1_norm_step4"
	.size	.L__func__._Z18h_do_l1_norm_step4PiiiiS_, 19

	.type	.L.str.6,@object                # @.str.6
.L.str.6:
	.asciz	"%s: error orig %d row %d \n"
	.size	.L.str.6, 27

	.type	.L.str.7,@object                # @.str.7
.L.str.7:
	.asciz	"%s: download orig : %d\n"
	.size	.L.str.7, 24

	.type	.L.str.8,@object                # @.str.8
.L.str.8:
	.asciz	"row %d cnt %d start %d\n"
	.size	.L.str.8, 24

	.type	.L.str.9,@object                # @.str.9
.L.str.9:
	.asciz	"%s: upload orig : %d\n"
	.size	.L.str.9, 22

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z21d_do_motion_detectionPiS_iiiiii"
	.size	.L__unnamed_1, 36

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z15d_do_motion_idxPiiiiii"
	.size	.L__unnamed_2, 27

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z18d_do_l1_norm_step1PiiiS_i"
	.size	.L__unnamed_3, 30

	.type	.L__unnamed_4,@object           # @3
.L__unnamed_4:
	.asciz	"_Z18d_do_l1_norm_step2Piiiii"
	.size	.L__unnamed_4, 29

	.type	.L__unnamed_5,@object           # @4
.L__unnamed_5:
	.asciz	"_Z18d_do_l1_norm_step3PiiiS_"
	.size	.L__unnamed_5, 29

	.type	.L__unnamed_6,@object           # @5
.L__unnamed_6:
	.asciz	"_Z18d_do_l1_norm_step4Piiii"
	.size	.L__unnamed_6, 28

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z36__device_stub__d_do_motion_detectionPiS_iiiiii
	.addrsig_sym _Z30__device_stub__d_do_motion_idxPiiiiii
	.addrsig_sym _Z33__device_stub__d_do_l1_norm_step1PiiiS_i
	.addrsig_sym _Z33__device_stub__d_do_l1_norm_step2Piiiii
	.addrsig_sym _Z33__device_stub__d_do_l1_norm_step3PiiiS_
	.addrsig_sym _Z33__device_stub__d_do_l1_norm_step4Piiii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z21d_do_motion_detectionPiS_iiiiii
	.addrsig_sym _Z15d_do_motion_idxPiiiiii
	.addrsig_sym _Z18d_do_l1_norm_step1PiiiS_i
	.addrsig_sym _Z18d_do_l1_norm_step2Piiiii
	.addrsig_sym _Z18d_do_l1_norm_step3PiiiS_
	.addrsig_sym _Z18d_do_l1_norm_step4Piiii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z21d_do_motion_detectionPiS_iiiiii ; -- Begin function _Z21d_do_motion_detectionPiS_iiiiii
	.globl	_Z21d_do_motion_detectionPiS_iiiiii
	.p2align	8
	.type	_Z21d_do_motion_detectionPiS_iiiiii,@function
_Z21d_do_motion_detectionPiS_iiiiii:    ; @_Z21d_do_motion_detectionPiS_iiiiii
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x34
	s_load_b128 s[4:7], s[0:1], 0x10
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_i32_e64 s4, v1
	s_cbranch_execz .LBB0_3
; %bb.1:                                ; %.lr.ph
	s_load_b64 s[2:3], s[0:1], 0x20
	s_add_i32 s12, s5, -3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_ashr_i32 s13, s12, 31
	s_add_i32 s8, s12, s13
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	s_xor_b32 s14, s8, s13
	s_load_b128 s[8:11], s[0:1], 0x0
	v_cvt_f32_u32_e32 v0, s14
	v_rcp_iflag_f32_e32 v0, v0
	s_waitcnt lgkmcnt(0)
	s_ashr_i32 s1, s3, 31
	s_ashr_i32 s15, s2, 31
	s_add_i32 s0, s3, s1
	s_add_i32 s17, s2, s15
	s_xor_b32 s16, s0, s1
	s_xor_b32 s17, s17, s15
	v_cvt_f32_u32_e32 v2, s16
	v_cvt_f32_u32_e32 v3, s17
	s_sub_i32 s0, 0, s14
	s_sub_i32 s18, 0, s16
	s_sub_i32 s19, 0, s17
	v_rcp_iflag_f32_e32 v2, v2
	v_rcp_iflag_f32_e32 v3, v3
	v_mul_f32_e32 v0, 0x4f7ffffe, v0
	s_sub_i32 s3, 0, s3
	s_waitcnt_depctr 0xfff
	v_dual_mul_f32 v2, 0x4f7ffffe, v2 :: v_dual_mul_f32 v3, 0x4f7ffffe, v3
	v_cvt_u32_f32_e32 v0, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cvt_u32_f32_e32 v2, v2
	v_cvt_u32_f32_e32 v3, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_lo_u32 v4, s0, v0
	v_mul_lo_u32 v5, s18, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_mul_lo_u32 v6, s19, v3
	s_mov_b32 s18, 0
	s_sub_i32 s19, 3, s5
	v_mul_hi_u32 v4, v0, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_hi_u32 v5, v2, v5
	v_mul_hi_u32 v6, v3, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v0, v0, v4
	v_add_nc_u32_e32 v2, v2, v5
	s_delay_alu instid0(VALU_DEP_3)
	v_add_nc_u32_e32 v3, v3, v6
.LBB0_2:                                ; =>This Inner Loop Header: Depth=1
	v_ashrrev_i32_e32 v4, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v5, v1, v4
	v_xor_b32_e32 v6, s13, v4
	v_xor_b32_e32 v4, v5, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v5, v4, v0
	v_mul_lo_u32 v7, v5, s14
	v_add_nc_u32_e32 v8, 1, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v4, v4, v7
	v_subrev_nc_u32_e32 v7, s14, v4
	v_cmp_le_u32_e32 vcc_lo, s14, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_cndmask_b32 v5, v5, v8 :: v_dual_cndmask_b32 v4, v4, v7
	v_add_nc_u32_e32 v7, 1, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_le_u32_e32 vcc_lo, s14, v4
	v_cndmask_b32_e32 v4, v5, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v4, v4, v6
	v_sub_nc_u32_e32 v11, v4, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_mul_lo_u32 v4, v11, s5
	v_mad_u64_u32 v[9:10], null, s19, v11, v[1:2]
	v_mul_lo_u32 v11, v11, s12
	v_ashrrev_i32_e32 v5, 31, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v10, 31, v9
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v11, v10, v11
	v_xor_b32_e32 v12, s1, v10
	v_add_nc_u32_e32 v11, v1, v11
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v7, vcc_lo, s10, v4
	v_add_co_ci_u32_e32 v8, vcc_lo, s11, v5, vcc_lo
	v_xor_b32_e32 v11, v11, v10
	v_add_nc_u32_e32 v1, 0x1fffe00, v1
	global_load_b96 v[4:6], v[7:8], off
	v_mul_hi_u32 v13, v11, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v14, v13, s16
	v_add_nc_u32_e32 v15, 1, v13
	v_sub_nc_u32_e32 v11, v11, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_subrev_nc_u32_e32 v14, s16, v11
	v_cmp_le_u32_e32 vcc_lo, s16, v11
	v_cndmask_b32_e32 v13, v13, v15, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_cndmask_b32 v11, v11, v14 :: v_dual_add_nc_u32 v14, 1, v13
	v_cmp_le_u32_e32 vcc_lo, s16, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v11, v13, v14, vcc_lo
	v_xor_b32_e32 v11, v11, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v13, v11, v12
	v_mad_u64_u32 v[11:12], null, s3, v13, v[9:10]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v12, 31, v11
	v_add_nc_u32_e32 v14, v11, v12
	v_xor_b32_e32 v15, s15, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v12, v14, v12
	v_mul_hi_u32 v14, v12, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v16, v14, s17
	v_add_nc_u32_e32 v17, 1, v14
	v_sub_nc_u32_e32 v12, v12, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_subrev_nc_u32_e32 v16, s17, v12
	v_cmp_le_u32_e32 vcc_lo, s17, v12
	v_cndmask_b32_e32 v14, v14, v17, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v12, v12, v16, vcc_lo
	v_add_nc_u32_e32 v16, 1, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_le_u32_e32 vcc_lo, s17, v12
	v_cndmask_b32_e32 v12, v14, v16, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v12, v12, v15
	v_sub_nc_u32_e32 v12, v12, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_3)
	v_mul_lo_u32 v14, v12, s2
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v5, v12, v5
	v_add_nc_u32_e32 v12, v13, v4
	v_mov_b32_e32 v4, v6
	v_mul_lo_u32 v13, v5, s6
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[5:6], null, v12, s7, v[4:5]
	v_sub_nc_u32_e32 v4, v11, v14
	v_add3_u32 v4, v5, v4, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v5, 31, v4
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, s8, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s9, v5, vcc_lo
	v_cmp_le_i32_e32 vcc_lo, s4, v1
	global_load_b32 v6, v[4:5], off
	v_lshlrev_b64 v[4:5], 2, v[9:10]
	s_or_b32 s18, vcc_lo, s18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v4, s0, v7, v4
	v_add_co_ci_u32_e64 v5, s0, v8, v5, s0
	s_waitcnt vmcnt(0)
	global_store_b32 v[4:5], v6, off offset:12
	s_and_not1_b32 exec_lo, exec_lo, s18
	s_cbranch_execnz .LBB0_2
.LBB0_3:                                ; %._crit_edge
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z21d_do_motion_detectionPiS_iiiiii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 18
		.amdhsa_next_free_sgpr 20
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z21d_do_motion_detectionPiS_iiiiii, .Lfunc_end0-_Z21d_do_motion_detectionPiS_iiiiii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 856
; NumSgprs: 22
; NumVgprs: 18
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 22
; NumVGPRsForWavesPerEU: 18
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z15d_do_motion_idxPiiiiii ; -- Begin function _Z15d_do_motion_idxPiiiiii
	.globl	_Z15d_do_motion_idxPiiiiii
	.p2align	8
	.type	_Z15d_do_motion_idxPiiiiii,@function
_Z15d_do_motion_idxPiiiiii:             ; @_Z15d_do_motion_idxPiiiiii
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x2c
	s_load_b128 s[4:7], s[0:1], 0x8
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_i32_e64 s4, v1
	s_cbranch_execz .LBB1_3
; %bb.1:                                ; %.lr.ph.preheader
	s_load_b32 s7, s[0:1], 0x18
	s_ashr_i32 s9, s6, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_add_i32 s3, s6, s9
	s_sub_i32 s6, 0, s6
	s_xor_b32 s11, s3, s9
	v_cvt_f32_u32_e32 v2, s11
	s_sub_i32 s3, 0, s11
	s_delay_alu instid0(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v2, v2
	s_waitcnt lgkmcnt(0)
	s_ashr_i32 s8, s7, 31
	s_sub_i32 s12, 0, s7
	s_add_i32 s2, s7, s8
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v2, 0x4f7ffffe, v2
	s_xor_b32 s10, s2, s8
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cvt_f32_u32_e32 v0, s10
	s_sub_i32 s2, 0, s10
	v_cvt_u32_f32_e32 v3, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v0, v0
	v_mul_lo_u32 v4, s3, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v4, v3, v4
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v0, 0x4f7ffffe, v0
	v_cvt_u32_f32_e32 v0, v0
	v_add_nc_u32_e32 v4, v3, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v2, s2, v0
	s_load_b64 s[2:3], s[0:1], 0x0
	s_mov_b32 s1, 0
	v_mul_hi_u32 v5, v0, v2
	v_mul_lo_u32 v2, v1, s5
	s_mul_i32 s5, s5, 0x1fffe00
	s_delay_alu instid0(VALU_DEP_2)
	v_add_nc_u32_e32 v0, v0, v5
.LBB1_2:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	v_ashrrev_i32_e32 v3, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v5, v1, v3
	v_xor_b32_e32 v6, s8, v3
	v_xor_b32_e32 v3, v5, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v5, v3, v0
	v_mul_lo_u32 v7, v5, s10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v3, v3, v7
	v_subrev_nc_u32_e32 v7, s10, v3
	v_cmp_le_u32_e32 vcc_lo, s10, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_cndmask_b32 v3, v3, v7 :: v_dual_add_nc_u32 v8, 1, v5
	v_cndmask_b32_e32 v5, v5, v8, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_le_u32_e32 vcc_lo, s10, v3
	v_add_nc_u32_e32 v7, 1, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v3, v5, v7, vcc_lo
	v_xor_b32_e32 v3, v3, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v5, v3, v6
	v_mad_u64_u32 v[7:8], null, s12, v5, v[1:2]
	v_mul_lo_u32 v3, v5, s7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v6, 31, v7
	v_sub_nc_u32_e32 v3, v6, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v3, v1, v3
	v_add_nc_u32_e32 v1, 0x1fffe00, v1
	v_xor_b32_e32 v3, v3, v6
	v_xor_b32_e32 v6, s9, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_le_i32_e64 s0, s4, v1
	v_mul_hi_u32 v8, v3, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_or_b32 s1, s0, s1
	v_add_nc_u32_e32 v10, 1, v8
	v_mul_lo_u32 v9, v8, s11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v3, v3, v9
	v_subrev_nc_u32_e32 v9, s11, v3
	v_cmp_le_u32_e32 vcc_lo, s11, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_cndmask_b32 v8, v8, v10 :: v_dual_cndmask_b32 v3, v3, v9
	v_add_nc_u32_e32 v9, 1, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cmp_le_u32_e32 vcc_lo, s11, v3
	v_ashrrev_i32_e32 v3, 31, v2
	v_cndmask_b32_e32 v8, v8, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v8, v8, v6
	v_sub_nc_u32_e32 v6, v8, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[8:9], null, s6, v6, v[7:8]
	v_lshlrev_b64 v[9:10], 2, v[2:3]
	v_add_nc_u32_e32 v2, s5, v2
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v9, vcc_lo, s2, v9
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v10, vcc_lo, s3, v10, vcc_lo
	v_mov_b32_e32 v7, v8
	global_store_b96 v[9:10], v[5:7], off
	s_and_not1_b32 exec_lo, exec_lo, s1
	s_cbranch_execnz .LBB1_2
.LBB1_3:                                ; %._crit_edge
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z15d_do_motion_idxPiiiiii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 11
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z15d_do_motion_idxPiiiiii, .Lfunc_end1-_Z15d_do_motion_idxPiiiiii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 588
; NumSgprs: 18
; NumVgprs: 11
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 11
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z18d_do_l1_norm_step1PiiiS_i ; -- Begin function _Z18d_do_l1_norm_step1PiiiS_i
	.globl	_Z18d_do_l1_norm_step1PiiiS_i
	.p2align	8
	.type	_Z18d_do_l1_norm_step1PiiiS_i,@function
_Z18d_do_l1_norm_step1PiiiS_i:          ; @_Z18d_do_l1_norm_step1PiiiS_i
; %bb.0:
	s_clause 0x1
	s_load_b32 s4, s[0:1], 0x2c
	s_load_b64 s[2:3], s[0:1], 0x8
	s_waitcnt lgkmcnt(0)
	s_and_b32 s4, s4, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
	s_mov_b32 s4, exec_lo
	v_cmpx_gt_i32_e64 s2, v1
	s_cbranch_execz .LBB2_7
; %bb.1:                                ; %.lr.ph
	s_ashr_i32 s6, s3, 31
	s_load_b64 s[8:9], s[0:1], 0x10
	s_add_i32 s4, s3, s6
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b32 s7, s4, s6
	v_cvt_f32_u32_e32 v0, s7
	s_sub_i32 s4, 0, s7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v0, v0
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v0, 0x4f7ffffe, v0
	v_cvt_u32_f32_e32 v0, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v2, s4, v0
	s_clause 0x1
	s_load_b64 s[4:5], s[0:1], 0x0
	s_load_b32 s0, s[0:1], 0x18
	s_mov_b32 s1, 0
	v_mul_hi_u32 v2, v0, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_add_nc_u32_e32 v0, v0, v2
	s_waitcnt lgkmcnt(0)
	v_dual_mov_b32 v2, s8 :: v_dual_mov_b32 v3, s9
	s_sub_i32 s8, 0, s3
.LBB2_2:                                ; =>This Inner Loop Header: Depth=1
	v_ashrrev_i32_e32 v4, 31, v1
	s_mov_b32 s9, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v5, v1, v4
	v_xor_b32_e32 v5, v5, v4
	v_xor_b32_e32 v4, s6, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v6, v5, v0
	v_mul_lo_u32 v7, v6, s7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v5, v5, v7
	v_add_nc_u32_e32 v7, 1, v6
	v_subrev_nc_u32_e32 v8, s7, v5
	v_cmp_le_u32_e32 vcc_lo, s7, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_cndmask_b32 v6, v6, v7 :: v_dual_cndmask_b32 v5, v5, v8
	v_add_nc_u32_e32 v7, 1, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_le_u32_e32 vcc_lo, s7, v5
	v_cndmask_b32_e32 v5, v6, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v5, v5, v4
	v_sub_nc_u32_e32 v4, v5, v4
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_ne_u32_e64 s0, v4
	s_cbranch_execz .LBB2_6
; %bb.3:                                ;   in Loop: Header=BB2_2 Depth=1
	v_lshl_add_u32 v5, v4, 1, v4
	v_mad_u64_u32 v[8:9], null, s8, v4, v[1:2]
	s_mov_b32 s10, exec_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[6:7], null, v4, s3, v[5:6]
	v_ashrrev_i32_e32 v9, 31, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v7, 31, v6
	v_lshlrev_b64 v[4:5], 2, v[6:7]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[6:7], 2, v[8:9]
	v_add_co_u32 v4, vcc_lo, s4, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
	v_add_co_u32 v2, vcc_lo, v2, v6
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_ci_u32_e32 v3, vcc_lo, v3, v7, vcc_lo
	v_add_co_u32 v4, vcc_lo, v4, v6
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v5, vcc_lo, v5, v7, vcc_lo
	global_load_b32 v6, v[2:3], off
	global_load_b32 v7, v[4:5], off offset:12
	s_waitcnt vmcnt(0)
	v_sub_nc_u32_e32 v6, v7, v6
	global_store_b32 v[4:5], v6, off offset:12
	v_cmpx_gt_i32_e32 0, v6
	s_cbranch_execz .LBB2_5
; %bb.4:                                ;   in Loop: Header=BB2_2 Depth=1
	v_sub_nc_u32_e32 v6, 0, v6
	global_store_b32 v[4:5], v6, off offset:12
.LBB2_5:                                ; %Flow
                                        ;   in Loop: Header=BB2_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
.LBB2_6:                                ;   in Loop: Header=BB2_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_or_b32 exec_lo, exec_lo, s9
	v_add_nc_u32_e32 v1, 0x1fffe00, v1
	v_cmp_le_i32_e32 vcc_lo, s2, v1
	s_or_b32 s1, vcc_lo, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s1
	s_cbranch_execnz .LBB2_2
.LBB2_7:                                ; %._crit_edge
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z18d_do_l1_norm_step1PiiiS_i
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 10
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_Z18d_do_l1_norm_step1PiiiS_i, .Lfunc_end2-_Z18d_do_l1_norm_step1PiiiS_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 520
; NumSgprs: 18
; NumVgprs: 10
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 10
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z18d_do_l1_norm_step2Piiiii ; -- Begin function _Z18d_do_l1_norm_step2Piiiii
	.globl	_Z18d_do_l1_norm_step2Piiiii
	.p2align	8
	.type	_Z18d_do_l1_norm_step2Piiiii,@function
_Z18d_do_l1_norm_step2Piiiii:           ; @_Z18d_do_l1_norm_step2Piiiii
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x24
	s_load_b128 s[4:7], s[0:1], 0x8
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_i32_e64 s4, v1
	s_cbranch_execz .LBB3_3
; %bb.1:                                ; %.lr.ph
	s_ashr_i32 s8, s7, 31
	s_load_b64 s[0:1], s[0:1], 0x0
	s_add_i32 s2, s7, s8
	s_ashr_i32 s3, s6, 31
	s_xor_b32 s9, s2, s8
	s_sub_i32 s7, 0, s7
	v_cvt_f32_u32_e32 v0, s9
	s_sub_i32 s2, 0, s9
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v0, v0
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v0, 0x4f7ffffe, v0
	v_cvt_u32_f32_e32 v0, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v2, s2, v0
	s_mov_b32 s2, s6
	s_mov_b32 s6, 0
	s_lshl_b64 s[2:3], s[2:3], 2
	v_mul_hi_u32 v2, v0, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_add_nc_u32_e32 v0, v0, v2
.LBB3_2:                                ; =>This Inner Loop Header: Depth=1
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v3, v1, v2
	v_xor_b32_e32 v3, v3, v2
	v_xor_b32_e32 v2, s8, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v4, v3, v0
	v_mul_lo_u32 v5, v4, s9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v3, v3, v5
	v_subrev_nc_u32_e32 v5, s9, v3
	v_cmp_le_u32_e32 vcc_lo, s9, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_cndmask_b32 v3, v3, v5 :: v_dual_add_nc_u32 v6, 1, v4
	v_cndmask_b32_e32 v4, v4, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_le_u32_e32 vcc_lo, s9, v3
	v_add_nc_u32_e32 v5, 1, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v3, v4, v5, vcc_lo
	v_xor_b32_e32 v3, v3, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v3, v3, v2
	v_mul_lo_u32 v2, v3, s5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[4:5], null, s7, v3, v[1:2]
	v_ashrrev_i32_e32 v3, 31, v2
	v_add_nc_u32_e32 v1, 0x1fffe00, v1
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v5, 31, v4
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v2, vcc_lo, s0, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, v2, v4
	v_add_co_ci_u32_e32 v3, vcc_lo, v3, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, v2, s2
	v_add_co_ci_u32_e32 v5, vcc_lo, s3, v3, vcc_lo
	s_clause 0x1
	global_load_b32 v4, v[4:5], off
	global_load_b32 v5, v[2:3], off
	v_cmp_le_i32_e32 vcc_lo, s4, v1
	s_or_b32 s6, vcc_lo, s6
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v4, v5, v4
	global_store_b32 v[2:3], v4, off
	s_and_not1_b32 exec_lo, exec_lo, s6
	s_cbranch_execnz .LBB3_2
.LBB3_3:                                ; %._crit_edge
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z18d_do_l1_norm_step2Piiiii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 7
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end3:
	.size	_Z18d_do_l1_norm_step2Piiiii, .Lfunc_end3-_Z18d_do_l1_norm_step2Piiiii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 436
; NumSgprs: 18
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z18d_do_l1_norm_step3PiiiS_ ; -- Begin function _Z18d_do_l1_norm_step3PiiiS_
	.globl	_Z18d_do_l1_norm_step3PiiiS_
	.p2align	8
	.type	_Z18d_do_l1_norm_step3PiiiS_,@function
_Z18d_do_l1_norm_step3PiiiS_:           ; @_Z18d_do_l1_norm_step3PiiiS_
; %bb.0:
	s_clause 0x1
	s_load_b32 s4, s[0:1], 0x24
	s_load_b64 s[2:3], s[0:1], 0x8
	s_waitcnt lgkmcnt(0)
	s_and_b32 s4, s4, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
	s_mov_b32 s4, exec_lo
	v_cmpx_gt_i32_e64 s2, v1
	s_cbranch_execz .LBB4_5
; %bb.1:                                ; %.lr.ph.preheader
	s_clause 0x1
	s_load_b64 s[4:5], s[0:1], 0x0
	s_load_b64 s[0:1], s[0:1], 0x10
	v_mul_lo_u32 v2, s3, v1
	v_mov_b32_e32 v0, 0
	s_mul_i32 s3, s3, 0x1fffe00
	s_mov_b32 s6, 0
.LBB4_2:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	s_mov_b32 s7, exec_lo
	v_lshlrev_b64 v[3:4], 2, v[2:3]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, s4, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_ne_u64_e64 s[0:1], v[3:4]
	s_cbranch_execz .LBB4_4
; %bb.3:                                ;   in Loop: Header=BB4_2 Depth=1
	global_load_b32 v5, v0, s[0:1]
	global_load_b32 v6, v[3:4], off
	s_waitcnt vmcnt(1)
	v_ashrrev_i32_e32 v7, 31, v5
	s_waitcnt vmcnt(0)
	v_mul_lo_u32 v6, 0x3e8, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v5, v5, v7
	v_ashrrev_i32_e32 v10, 31, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v5, v5, v7
	v_add_nc_u32_e32 v6, v6, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_cvt_f32_u32_e32 v8, v5
	v_sub_nc_u32_e32 v9, 0, v5
	v_xor_b32_e32 v7, v10, v7
	v_xor_b32_e32 v6, v6, v10
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v8, v8
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v8, 0x4f7ffffe, v8
	v_cvt_u32_f32_e32 v8, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v9, v9, v8
	v_mul_hi_u32 v9, v8, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v8, v8, v9
	v_mul_hi_u32 v8, v6, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v9, v8, v5
	v_sub_nc_u32_e32 v6, v6, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v11, v6, v5
	v_cmp_ge_u32_e32 vcc_lo, v6, v5
	v_dual_cndmask_b32 v6, v6, v11 :: v_dual_add_nc_u32 v9, 1, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v8, v8, v9, vcc_lo
	v_cmp_ge_u32_e32 vcc_lo, v6, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v9, 1, v8
	v_cndmask_b32_e32 v5, v8, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v5, v5, v7
	v_sub_nc_u32_e32 v5, v7, v5
	s_delay_alu instid0(VALU_DEP_1)
	v_add_nc_u32_e32 v5, 0x3e8, v5
	global_store_b32 v[3:4], v5, off
.LBB4_4:                                ;   in Loop: Header=BB4_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s7
	v_add_nc_u32_e32 v1, 0x1fffe00, v1
	v_add_nc_u32_e32 v2, s3, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_le_i32_e32 vcc_lo, s2, v1
	s_or_b32 s6, vcc_lo, s6
	s_and_not1_b32 exec_lo, exec_lo, s6
	s_cbranch_execnz .LBB4_2
.LBB4_5:                                ; %._crit_edge
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z18d_do_l1_norm_step3PiiiS_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 12
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end4:
	.size	_Z18d_do_l1_norm_step3PiiiS_, .Lfunc_end4-_Z18d_do_l1_norm_step3PiiiS_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 444
; NumSgprs: 18
; NumVgprs: 12
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 12
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z18d_do_l1_norm_step4Piiii ; -- Begin function _Z18d_do_l1_norm_step4Piiii
	.globl	_Z18d_do_l1_norm_step4Piiii
	.p2align	8
	.type	_Z18d_do_l1_norm_step4Piiii,@function
_Z18d_do_l1_norm_step4Piiii:            ; @_Z18d_do_l1_norm_step4Piiii
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x24
	s_load_b128 s[4:7], s[0:1], 0x8
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_i32_e64 s4, v1
	s_cbranch_execz .LBB5_6
; %bb.1:                                ; %.lr.ph
	s_load_b64 s[0:1], s[0:1], 0x0
	v_mul_lo_u32 v2, s5, v1
	s_mul_i32 s2, s6, s5
	s_mul_i32 s5, s5, 0x1fffe00
	s_ashr_i32 s3, s2, 31
	s_mov_b32 s6, 0
	s_lshl_b64 s[2:3], s[2:3], 2
.LBB5_2:                                ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	s_mov_b32 s7, exec_lo
	v_lshlrev_b64 v[3:4], 2, v[2:3]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, s0, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v5, vcc_lo, v3, s2
	v_add_co_ci_u32_e32 v6, vcc_lo, s3, v4, vcc_lo
	global_load_b32 v0, v[5:6], off
	s_waitcnt vmcnt(0)
	v_cmpx_lt_i32_e32 -1, v0
	s_cbranch_execz .LBB5_5
; %bb.3:                                ;   in Loop: Header=BB5_2 Depth=1
	global_load_b32 v7, v[3:4], off
	s_waitcnt vmcnt(0)
	v_cmp_lt_i32_e32 vcc_lo, v0, v7
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB5_5
; %bb.4:                                ;   in Loop: Header=BB5_2 Depth=1
	global_store_b32 v[3:4], v0, off
	global_load_b32 v0, v[5:6], off offset:-4
	s_waitcnt vmcnt(0)
	global_store_b32 v[3:4], v0, off offset:-4
	global_load_b32 v0, v[5:6], off offset:-8
	s_waitcnt vmcnt(0)
	global_store_b32 v[3:4], v0, off offset:-8
	global_load_b32 v0, v[5:6], off offset:-12
	s_waitcnt vmcnt(0)
	global_store_b32 v[3:4], v0, off offset:-12
.LBB5_5:                                ;   in Loop: Header=BB5_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s7
	v_add_nc_u32_e32 v1, 0x1fffe00, v1
	v_add_nc_u32_e32 v2, s5, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_le_i32_e32 vcc_lo, s4, v1
	s_or_b32 s6, vcc_lo, s6
	s_and_not1_b32 exec_lo, exec_lo, s6
	s_cbranch_execnz .LBB5_2
.LBB5_6:                                ; %._crit_edge
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z18d_do_l1_norm_step4Piiii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 8
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end5:
	.size	_Z18d_do_l1_norm_step4Piiii, .Lfunc_end5-_Z18d_do_l1_norm_step4Piiii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 316
; NumSgprs: 18
; NumVgprs: 8
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 8
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         36
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         44
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         52
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         54
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         56
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         58
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         60
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         62
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         104
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        .value_kind:     hidden_grid_dims
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...

	.end_amdgpu_metadata
