__device__ int get(int x, int y,int width){
  return y * width +x;
}

__device__ int normeValue(int x, int width){
	if(x < 0) //-1
		return width - 1;
	if(x == width)
		return 0;
	return x;
}

__device__ int* neighborsIndexes(int i, int j, int width, int height){
	int dir[8];
	dir[0] = get(normeValue(i+1,width), j, width);
	dir[1] = get(normeValue(i+1,width), normeValue(j+1,height),width);
	dir[2] = get(i, normeValue(j+1,height),width);
	dir[3] = get(normeValue(i-1,width), normeValue(j+1,height),width);
	dir[4] = get(normeValue(i-1,width), j, width);
	dir[5] = get(normeValue(i-1,width), normeValue(j-1,height),width);
	dir[6] = get(i, normeValue(j-1,height),width);
	dir[7] = get(normeValue(i+1,width), normeValue(j-1,height),width);
	return dir;
}

/*
__device__ float getTotalUpdateFromNeighbors(float* tmp, int i, int j, int width, int height){
		int index = get(i,j,width) * 8;
       return 
        tmp[get(normeValue(iPlusOne,width), j, width)] +
        tmp[get(normeValue(iPlusOne,width), normeValue(jPlusOne,height),width)] +
	tmp[get(i, normeValue(jPlusOne,height),width)] +
        tmp[get(normeValue(iMinusOne,width), normeValue(jPlusOne,height),width)] +
        tmp[get(normeValue(iMinusOne,width), j, width)] +
        tmp[get(normeValue(iMinusOne,width), normeValue(jMinusOne,height),width)] +
        tmp[get(i, normeValue(jMinusOne,height),width)] +
        tmp[get(normeValue(iPlusOne,width), normeValue(jMinusOne,height),width)];
}
*/


extern "C"
__global__ void FIELD_MAX_DIR(int width, int height, float *values, int* patchMax)
{
        int i = blockIdx.x * blockDim.x + threadIdx.x;
        int j = blockIdx.y * blockDim.y + threadIdx.y;
        
       if (i < width && j < height ){
    		int k = get(i,j,width);
    		int maxIndex = 0;
    		int* neighbors = neighborsIndexes(i,j,width,height);
    		float max = values[neighbors[0]];
    		for(int u=1 ; u < 8 ; u++){
    			float current = values[neighbors[u]];
    			if(max < current){
    				max = current;
    				maxIndex = u;
    			}
    		}
    		patchMax[k] = maxIndex * 45;
    	}
}
 
//with fields
extern "C"
__global__ void FIELD_MAX_DIR2(int width, int height, float *values, int* patchMax
					 )
{
        int i = blockIdx.x * blockDim.x + threadIdx.x;
        int j = blockIdx.y * blockDim.y + threadIdx.y;
        
       if (i < width && j < height ){
    	int k = get(i,j,width);
    	
		float max = values[get(normeValue(i + 1, width), j, width)];
		int maxDir = 0;

		float current = values[get(normeValue(i + 1, width), normeValue(j + 1, height), width)];
		if (current > max) {
			max = current;
			maxDir = 45;
		}

		current = values[get(i, normeValue(j + 1, height), width)];
		if (current > max) {
			max = current;
			maxDir = 90;
		}

		current = values[get(normeValue(i - 1, width), normeValue(j + 1, height), width)];
		if (current > max) {
			max = current;
			maxDir = 135;
		}

		current = values[get(normeValue(i - 1, width), j, width)];
		if (current > max) {
			max = current;
			maxDir = 180;
		}

		current = values[get(normeValue(i - 1, width), normeValue(j - 1, height), width)];
		if (current > max) {
			max = current;
			maxDir = 225;
		}

		current = values[get(i, normeValue(j - 1, height), width)];
		if (current > max) {
			max = current;
			maxDir = 270;
		}

		current = values[get(normeValue(i + 1, width), normeValue(j - 1, height), width)];
		if (current > max) {
			max = current;
			maxDir = 315;
		}

	   patchMax[k] = maxDir;
	   }
	   
}

//with fields
extern "C"
__global__ void DIFFUSION_UPDATE_THEN_EVAPORATION_THEN_FIELDMAXDIRV2( int width, int height, float *values, float* tmp, float evapCoef, int* patchMax)
{
        int i = blockIdx.x * blockDim.x + threadIdx.x;
        int j = blockIdx.y * blockDim.y + threadIdx.y;
        
       if (i < width && j < height ){
    	
		float max = tmp[get(normeValue(i + 1, width), j, width)];
		float total = max;
		int maxDir = 0;

		float current = tmp[get(normeValue(i + 1, width), normeValue(j + 1, height), width)];
		total += current;
		if (current > max) {
			max = current;
			maxDir = 45;
		}

		current = tmp[get(i, normeValue(j + 1, height), width)];
		total += current;
		if (current > max) {
			max = current;
			maxDir = 90;
		}

		current = tmp[get(normeValue(i - 1, width), normeValue(j + 1, height), width)];
		total += current;
		if (current > max) {
			max = current;
			maxDir = 135;
		}

		current = tmp[get(normeValue(i - 1, width), j, width)];
		total += current;
		if (current > max) {
			max = current;
			maxDir = 180;
		}

		current = tmp[get(normeValue(i - 1, width), normeValue(j - 1, height), width)];
		total += current;
		if (current > max) {
			max = current;
			maxDir = 225;
		}

		current = tmp[get(i, normeValue(j - 1, height), width)];
		total += current;
		if (current > max) {
			max = current;
			maxDir = 270;
		}

		current = tmp[get(normeValue(i + 1, width), normeValue(j - 1, height), width)];
		total += current;
		if (current > max) {
			max = current;
			maxDir = 315;
		}

		int k = get(i,j,width);
	   	patchMax[k] = maxDir;
		total += values[k];
	    values[k] = total - total * evapCoef;
	   }
	   
}

//with fields
extern "C"
__global__ void DIFFUSION_UPDATE_THEN_EVAPORATION_THEN_FIELDMAXDIRV3( int width, int height, float *values, float* tmp, float evapCoef, int* patchMax)
{
        int i = blockIdx.x * blockDim.x + threadIdx.x;
        int j = blockIdx.y * blockDim.y + threadIdx.y;
        
        
       if (i < width && j < height ){
    	
		int iPlusOne = i + 1;
		int jPlusOne = j + 1;
	 	int iMinusOne = i - 1;
	 	int jMinusOne = j - 1;

		float max = tmp[get(normeValue(iPlusOne, width), j, width)];
		float total = max;
		int maxDir = 0;

		float current = tmp[get(normeValue(iPlusOne, width), normeValue(jPlusOne, height), width)];
		total += current;
		if (current > max) {
			max = current;
			maxDir = 45;
		}

		current = tmp[get(i, normeValue(jPlusOne, height), width)];
		total += current;
		if (current > max) {
			max = current;
			maxDir = 90;
		}

		current = tmp[get(normeValue(iMinusOne, width), normeValue(jPlusOne, height), width)];
		total += current;
		if (current > max) {
			max = current;
			maxDir = 135;
		}

		current = tmp[get(normeValue(iMinusOne, width), j, width)];
		total += current;
		if (current > max) {
			max = current;
			maxDir = 180;
		}

		current = tmp[get(normeValue(iMinusOne, width), normeValue(jMinusOne, height), width)];
		total += current;
		if (current > max) {
			max = current;
			maxDir = 225;
		}

		current = tmp[get(i, normeValue(jMinusOne, height), width)];
		total += current;
		if (current > max) {
			max = current;
			maxDir = 270;
		}

		current = tmp[get(normeValue(iPlusOne, width), normeValue(jMinusOne, height), width)];
		total += current;
		if (current > max) {
			max = current;
			maxDir = 315;
		}

		int k = get(i,j,width);
	   	patchMax[k] = maxDir;
		total += values[k];
	    values[k] = total - total * evapCoef;
	   }
	   
}

extern "C"
__global__ void DIFFUSION_UPDATE_THEN_EVAPORATION_THEN_FIELDMAXDIR( int width, int height, float *values, float* tmp, float evapCoef, int* patchMax)
{
	int i = blockIdx.x * blockDim.x + threadIdx.x;
	int j = blockIdx.y * blockDim.y + threadIdx.y;
	
       if (i < width && j < height ){//TODO + alone
		int k = get(i,j,width);
		int* neighbors = neighborsIndexes(i,j,width,height);
		int maxIndex = 0;
		float total = tmp[neighbors[0]];
		float max = total;
		for(int u=1 ; u < 8 ; u++){
			float current = tmp[neighbors[u]];
			total += current;
			if(max < current){
				max = current;
				maxIndex = u;
			}
		}
		patchMax[k] = maxIndex * 45;
		total += values[k];
	    	values[k] = total - total * evapCoef;
    	}
}

	.file	"tmpxft_002d7a05_00000000-6_DiffusionEvaporationGradients_2D.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2013:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2013:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z3getiii
	.type	_Z3getiii, @function
_Z3getiii:
.LFB2008:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2008:
	.size	_Z3getiii, .-_Z3getiii
	.globl	_Z10normeValueii
	.type	_Z10normeValueii, @function
_Z10normeValueii:
.LFB2009:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2009:
	.size	_Z10normeValueii, .-_Z10normeValueii
	.globl	_Z16neighborsIndexesiiii
	.type	_Z16neighborsIndexesiiii, @function
_Z16neighborsIndexesiiii:
.LFB2010:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2010:
	.size	_Z16neighborsIndexesiiii, .-_Z16neighborsIndexesiiii
	.globl	_Z37__device_stub__Z13FIELD_MAX_DIRiiPfPiiiPfPi
	.type	_Z37__device_stub__Z13FIELD_MAX_DIRiiPfPiiiPfPi, @function
_Z37__device_stub__Z13FIELD_MAX_DIRiiPfPiiiPfPi:
.LFB2035:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movl	%edi, 28(%rsp)
	leaq	56(%rsp), %rdi
	movl	%esi, 24(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 16(%rsp)
	leaq	40(%rsp), %rdx
	movq	%rcx, 8(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	28(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L8
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	FIELD_MAX_DIR(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L8:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L10
	call	__stack_chk_fail@PLT
.L10:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2035:
	.size	_Z37__device_stub__Z13FIELD_MAX_DIRiiPfPiiiPfPi, .-_Z37__device_stub__Z13FIELD_MAX_DIRiiPfPiiiPfPi
	.globl	FIELD_MAX_DIR
	.type	FIELD_MAX_DIR, @function
FIELD_MAX_DIR:
.LFB2036:
	.cfi_startproc
	endbr64
	jmp	_Z37__device_stub__Z13FIELD_MAX_DIRiiPfPiiiPfPi
	.cfi_endproc
.LFE2036:
	.size	FIELD_MAX_DIR, .-FIELD_MAX_DIR
	.globl	_Z38__device_stub__Z14FIELD_MAX_DIR2iiPfPiiiPfPi
	.type	_Z38__device_stub__Z14FIELD_MAX_DIR2iiPfPiiiPfPi, @function
_Z38__device_stub__Z14FIELD_MAX_DIR2iiPfPiiiPfPi:
.LFB2037:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movl	%edi, 28(%rsp)
	leaq	56(%rsp), %rdi
	movl	%esi, 24(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 16(%rsp)
	leaq	40(%rsp), %rdx
	movq	%rcx, 8(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	28(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L14
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	FIELD_MAX_DIR2(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L14:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L16
	call	__stack_chk_fail@PLT
.L16:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2037:
	.size	_Z38__device_stub__Z14FIELD_MAX_DIR2iiPfPiiiPfPi, .-_Z38__device_stub__Z14FIELD_MAX_DIR2iiPfPiiiPfPi
	.globl	FIELD_MAX_DIR2
	.type	FIELD_MAX_DIR2, @function
FIELD_MAX_DIR2:
.LFB2038:
	.cfi_startproc
	endbr64
	jmp	_Z38__device_stub__Z14FIELD_MAX_DIR2iiPfPiiiPfPi
	.cfi_endproc
.LFE2038:
	.size	FIELD_MAX_DIR2, .-FIELD_MAX_DIR2
	.globl	_Z79__device_stub__Z52DIFFUSION_UPDATE_THEN_EVAPORATION_THEN_FIELDMAXDIRV2iiPfS_fPiiiPfS_fPi
	.type	_Z79__device_stub__Z52DIFFUSION_UPDATE_THEN_EVAPORATION_THEN_FIELDMAXDIRV2iiPfS_fPiiiPfS_fPi, @function
_Z79__device_stub__Z52DIFFUSION_UPDATE_THEN_EVAPORATION_THEN_FIELDMAXDIRV2iiPfS_fPiiiPfS_fPi:
.LFB2039:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movl	%edi, 44(%rsp)
	leaq	72(%rsp), %rdi
	movl	%esi, 40(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 32(%rsp)
	leaq	56(%rsp), %rdx
	movq	%rcx, 24(%rsp)
	leaq	64(%rsp), %rcx
	movq	%r8, 8(%rsp)
	movss	%xmm0, 20(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	44(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L19
	pushq	64(%rsp)
	.cfi_def_cfa_offset 200
	leaq	DIFFUSION_UPDATE_THEN_EVAPORATION_THEN_FIELDMAXDIRV2(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 208
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L19:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L21
	call	__stack_chk_fail@PLT
.L21:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2039:
	.size	_Z79__device_stub__Z52DIFFUSION_UPDATE_THEN_EVAPORATION_THEN_FIELDMAXDIRV2iiPfS_fPiiiPfS_fPi, .-_Z79__device_stub__Z52DIFFUSION_UPDATE_THEN_EVAPORATION_THEN_FIELDMAXDIRV2iiPfS_fPiiiPfS_fPi
	.globl	DIFFUSION_UPDATE_THEN_EVAPORATION_THEN_FIELDMAXDIRV2
	.type	DIFFUSION_UPDATE_THEN_EVAPORATION_THEN_FIELDMAXDIRV2, @function
DIFFUSION_UPDATE_THEN_EVAPORATION_THEN_FIELDMAXDIRV2:
.LFB2040:
	.cfi_startproc
	endbr64
	jmp	_Z79__device_stub__Z52DIFFUSION_UPDATE_THEN_EVAPORATION_THEN_FIELDMAXDIRV2iiPfS_fPiiiPfS_fPi
	.cfi_endproc
.LFE2040:
	.size	DIFFUSION_UPDATE_THEN_EVAPORATION_THEN_FIELDMAXDIRV2, .-DIFFUSION_UPDATE_THEN_EVAPORATION_THEN_FIELDMAXDIRV2
	.globl	_Z79__device_stub__Z52DIFFUSION_UPDATE_THEN_EVAPORATION_THEN_FIELDMAXDIRV3iiPfS_fPiiiPfS_fPi
	.type	_Z79__device_stub__Z52DIFFUSION_UPDATE_THEN_EVAPORATION_THEN_FIELDMAXDIRV3iiPfS_fPiiiPfS_fPi, @function
_Z79__device_stub__Z52DIFFUSION_UPDATE_THEN_EVAPORATION_THEN_FIELDMAXDIRV3iiPfS_fPiiiPfS_fPi:
.LFB2041:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movl	%edi, 44(%rsp)
	leaq	72(%rsp), %rdi
	movl	%esi, 40(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 32(%rsp)
	leaq	56(%rsp), %rdx
	movq	%rcx, 24(%rsp)
	leaq	64(%rsp), %rcx
	movq	%r8, 8(%rsp)
	movss	%xmm0, 20(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	44(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L24
	pushq	64(%rsp)
	.cfi_def_cfa_offset 200
	leaq	DIFFUSION_UPDATE_THEN_EVAPORATION_THEN_FIELDMAXDIRV3(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 208
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L24:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L26
	call	__stack_chk_fail@PLT
.L26:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2041:
	.size	_Z79__device_stub__Z52DIFFUSION_UPDATE_THEN_EVAPORATION_THEN_FIELDMAXDIRV3iiPfS_fPiiiPfS_fPi, .-_Z79__device_stub__Z52DIFFUSION_UPDATE_THEN_EVAPORATION_THEN_FIELDMAXDIRV3iiPfS_fPiiiPfS_fPi
	.globl	DIFFUSION_UPDATE_THEN_EVAPORATION_THEN_FIELDMAXDIRV3
	.type	DIFFUSION_UPDATE_THEN_EVAPORATION_THEN_FIELDMAXDIRV3, @function
DIFFUSION_UPDATE_THEN_EVAPORATION_THEN_FIELDMAXDIRV3:
.LFB2042:
	.cfi_startproc
	endbr64
	jmp	_Z79__device_stub__Z52DIFFUSION_UPDATE_THEN_EVAPORATION_THEN_FIELDMAXDIRV3iiPfS_fPiiiPfS_fPi
	.cfi_endproc
.LFE2042:
	.size	DIFFUSION_UPDATE_THEN_EVAPORATION_THEN_FIELDMAXDIRV3, .-DIFFUSION_UPDATE_THEN_EVAPORATION_THEN_FIELDMAXDIRV3
	.globl	_Z77__device_stub__Z50DIFFUSION_UPDATE_THEN_EVAPORATION_THEN_FIELDMAXDIRiiPfS_fPiiiPfS_fPi
	.type	_Z77__device_stub__Z50DIFFUSION_UPDATE_THEN_EVAPORATION_THEN_FIELDMAXDIRiiPfS_fPiiiPfS_fPi, @function
_Z77__device_stub__Z50DIFFUSION_UPDATE_THEN_EVAPORATION_THEN_FIELDMAXDIRiiPfS_fPiiiPfS_fPi:
.LFB2043:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movl	%edi, 44(%rsp)
	leaq	72(%rsp), %rdi
	movl	%esi, 40(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 32(%rsp)
	leaq	56(%rsp), %rdx
	movq	%rcx, 24(%rsp)
	leaq	64(%rsp), %rcx
	movq	%r8, 8(%rsp)
	movss	%xmm0, 20(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	44(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L29
	pushq	64(%rsp)
	.cfi_def_cfa_offset 200
	leaq	DIFFUSION_UPDATE_THEN_EVAPORATION_THEN_FIELDMAXDIR(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 208
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L29:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L31
	call	__stack_chk_fail@PLT
.L31:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2043:
	.size	_Z77__device_stub__Z50DIFFUSION_UPDATE_THEN_EVAPORATION_THEN_FIELDMAXDIRiiPfS_fPiiiPfS_fPi, .-_Z77__device_stub__Z50DIFFUSION_UPDATE_THEN_EVAPORATION_THEN_FIELDMAXDIRiiPfS_fPiiiPfS_fPi
	.globl	DIFFUSION_UPDATE_THEN_EVAPORATION_THEN_FIELDMAXDIR
	.type	DIFFUSION_UPDATE_THEN_EVAPORATION_THEN_FIELDMAXDIR, @function
DIFFUSION_UPDATE_THEN_EVAPORATION_THEN_FIELDMAXDIR:
.LFB2044:
	.cfi_startproc
	endbr64
	jmp	_Z77__device_stub__Z50DIFFUSION_UPDATE_THEN_EVAPORATION_THEN_FIELDMAXDIRiiPfS_fPiiiPfS_fPi
	.cfi_endproc
.LFE2044:
	.size	DIFFUSION_UPDATE_THEN_EVAPORATION_THEN_FIELDMAXDIR, .-DIFFUSION_UPDATE_THEN_EVAPORATION_THEN_FIELDMAXDIR
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"DIFFUSION_UPDATE_THEN_EVAPORATION_THEN_FIELDMAXDIR"
.LC1:
	.string	"DIFFUSION_UPDATE_THEN_EVAPORATION_THEN_FIELDMAXDIRV3"
.LC2:
	.string	"DIFFUSION_UPDATE_THEN_EVAPORATION_THEN_FIELDMAXDIRV2"
.LC3:
	.string	"FIELD_MAX_DIR2"
.LC4:
	.string	"FIELD_MAX_DIR"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2046:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	DIFFUSION_UPDATE_THEN_EVAPORATION_THEN_FIELDMAXDIR(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC1(%rip), %rdx
	orl	$-1, %r8d
	leaq	DIFFUSION_UPDATE_THEN_EVAPORATION_THEN_FIELDMAXDIRV3(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC2(%rip), %rdx
	orl	$-1, %r8d
	leaq	DIFFUSION_UPDATE_THEN_EVAPORATION_THEN_FIELDMAXDIRV2(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC3(%rip), %rdx
	orl	$-1, %r8d
	leaq	FIELD_MAX_DIR2(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC4(%rip), %rdx
	orl	$-1, %r8d
	leaq	FIELD_MAX_DIR(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2046:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
__device__ int get(int x, int y,int width){
  return y * width +x;
}

__device__ int normeValue(int x, int width){
	if(x < 0) //-1
		return width - 1;
	if(x == width)
		return 0;
	return x;
}

__device__ int* neighborsIndexes(int i, int j, int width, int height){
	int dir[8];
	dir[0] = get(normeValue(i+1,width), j, width);
	dir[1] = get(normeValue(i+1,width), normeValue(j+1,height),width);
	dir[2] = get(i, normeValue(j+1,height),width);
	dir[3] = get(normeValue(i-1,width), normeValue(j+1,height),width);
	dir[4] = get(normeValue(i-1,width), j, width);
	dir[5] = get(normeValue(i-1,width), normeValue(j-1,height),width);
	dir[6] = get(i, normeValue(j-1,height),width);
	dir[7] = get(normeValue(i+1,width), normeValue(j-1,height),width);
	return dir;
}

/*
__device__ float getTotalUpdateFromNeighbors(float* tmp, int i, int j, int width, int height){
		int index = get(i,j,width) * 8;
       return 
        tmp[get(normeValue(iPlusOne,width), j, width)] +
        tmp[get(normeValue(iPlusOne,width), normeValue(jPlusOne,height),width)] +
	tmp[get(i, normeValue(jPlusOne,height),width)] +
        tmp[get(normeValue(iMinusOne,width), normeValue(jPlusOne,height),width)] +
        tmp[get(normeValue(iMinusOne,width), j, width)] +
        tmp[get(normeValue(iMinusOne,width), normeValue(jMinusOne,height),width)] +
        tmp[get(i, normeValue(jMinusOne,height),width)] +
        tmp[get(normeValue(iPlusOne,width), normeValue(jMinusOne,height),width)];
}
*/


extern "C"
__global__ void FIELD_MAX_DIR(int width, int height, float *values, int* patchMax)
{
        int i = blockIdx.x * blockDim.x + threadIdx.x;
        int j = blockIdx.y * blockDim.y + threadIdx.y;
        
       if (i < width && j < height ){
    		int k = get(i,j,width);
    		int maxIndex = 0;
    		int* neighbors = neighborsIndexes(i,j,width,height);
    		float max = values[neighbors[0]];
    		for(int u=1 ; u < 8 ; u++){
    			float current = values[neighbors[u]];
    			if(max < current){
    				max = current;
    				maxIndex = u;
    			}
    		}
    		patchMax[k] = maxIndex * 45;
    	}
}
 
//with fields
extern "C"
__global__ void FIELD_MAX_DIR2(int width, int height, float *values, int* patchMax
					 )
{
        int i = blockIdx.x * blockDim.x + threadIdx.x;
        int j = blockIdx.y * blockDim.y + threadIdx.y;
        
       if (i < width && j < height ){
    	int k = get(i,j,width);
    	
		float max = values[get(normeValue(i + 1, width), j, width)];
		int maxDir = 0;

		float current = values[get(normeValue(i + 1, width), normeValue(j + 1, height), width)];
		if (current > max) {
			max = current;
			maxDir = 45;
		}

		current = values[get(i, normeValue(j + 1, height), width)];
		if (current > max) {
			max = current;
			maxDir = 90;
		}

		current = values[get(normeValue(i - 1, width), normeValue(j + 1, height), width)];
		if (current > max) {
			max = current;
			maxDir = 135;
		}

		current = values[get(normeValue(i - 1, width), j, width)];
		if (current > max) {
			max = current;
			maxDir = 180;
		}

		current = values[get(normeValue(i - 1, width), normeValue(j - 1, height), width)];
		if (current > max) {
			max = current;
			maxDir = 225;
		}

		current = values[get(i, normeValue(j - 1, height), width)];
		if (current > max) {
			max = current;
			maxDir = 270;
		}

		current = values[get(normeValue(i + 1, width), normeValue(j - 1, height), width)];
		if (current > max) {
			max = current;
			maxDir = 315;
		}

	   patchMax[k] = maxDir;
	   }
	   
}

//with fields
extern "C"
__global__ void DIFFUSION_UPDATE_THEN_EVAPORATION_THEN_FIELDMAXDIRV2( int width, int height, float *values, float* tmp, float evapCoef, int* patchMax)
{
        int i = blockIdx.x * blockDim.x + threadIdx.x;
        int j = blockIdx.y * blockDim.y + threadIdx.y;
        
       if (i < width && j < height ){
    	
		float max = tmp[get(normeValue(i + 1, width), j, width)];
		float total = max;
		int maxDir = 0;

		float current = tmp[get(normeValue(i + 1, width), normeValue(j + 1, height), width)];
		total += current;
		if (current > max) {
			max = current;
			maxDir = 45;
		}

		current = tmp[get(i, normeValue(j + 1, height), width)];
		total += current;
		if (current > max) {
			max = current;
			maxDir = 90;
		}

		current = tmp[get(normeValue(i - 1, width), normeValue(j + 1, height), width)];
		total += current;
		if (current > max) {
			max = current;
			maxDir = 135;
		}

		current = tmp[get(normeValue(i - 1, width), j, width)];
		total += current;
		if (current > max) {
			max = current;
			maxDir = 180;
		}

		current = tmp[get(normeValue(i - 1, width), normeValue(j - 1, height), width)];
		total += current;
		if (current > max) {
			max = current;
			maxDir = 225;
		}

		current = tmp[get(i, normeValue(j - 1, height), width)];
		total += current;
		if (current > max) {
			max = current;
			maxDir = 270;
		}

		current = tmp[get(normeValue(i + 1, width), normeValue(j - 1, height), width)];
		total += current;
		if (current > max) {
			max = current;
			maxDir = 315;
		}

		int k = get(i,j,width);
	   	patchMax[k] = maxDir;
		total += values[k];
	    values[k] = total - total * evapCoef;
	   }
	   
}

//with fields
extern "C"
__global__ void DIFFUSION_UPDATE_THEN_EVAPORATION_THEN_FIELDMAXDIRV3( int width, int height, float *values, float* tmp, float evapCoef, int* patchMax)
{
        int i = blockIdx.x * blockDim.x + threadIdx.x;
        int j = blockIdx.y * blockDim.y + threadIdx.y;
        
        
       if (i < width && j < height ){
    	
		int iPlusOne = i + 1;
		int jPlusOne = j + 1;
	 	int iMinusOne = i - 1;
	 	int jMinusOne = j - 1;

		float max = tmp[get(normeValue(iPlusOne, width), j, width)];
		float total = max;
		int maxDir = 0;

		float current = tmp[get(normeValue(iPlusOne, width), normeValue(jPlusOne, height), width)];
		total += current;
		if (current > max) {
			max = current;
			maxDir = 45;
		}

		current = tmp[get(i, normeValue(jPlusOne, height), width)];
		total += current;
		if (current > max) {
			max = current;
			maxDir = 90;
		}

		current = tmp[get(normeValue(iMinusOne, width), normeValue(jPlusOne, height), width)];
		total += current;
		if (current > max) {
			max = current;
			maxDir = 135;
		}

		current = tmp[get(normeValue(iMinusOne, width), j, width)];
		total += current;
		if (current > max) {
			max = current;
			maxDir = 180;
		}

		current = tmp[get(normeValue(iMinusOne, width), normeValue(jMinusOne, height), width)];
		total += current;
		if (current > max) {
			max = current;
			maxDir = 225;
		}

		current = tmp[get(i, normeValue(jMinusOne, height), width)];
		total += current;
		if (current > max) {
			max = current;
			maxDir = 270;
		}

		current = tmp[get(normeValue(iPlusOne, width), normeValue(jMinusOne, height), width)];
		total += current;
		if (current > max) {
			max = current;
			maxDir = 315;
		}

		int k = get(i,j,width);
	   	patchMax[k] = maxDir;
		total += values[k];
	    values[k] = total - total * evapCoef;
	   }
	   
}

extern "C"
__global__ void DIFFUSION_UPDATE_THEN_EVAPORATION_THEN_FIELDMAXDIR( int width, int height, float *values, float* tmp, float evapCoef, int* patchMax)
{
	int i = blockIdx.x * blockDim.x + threadIdx.x;
	int j = blockIdx.y * blockDim.y + threadIdx.y;
	
       if (i < width && j < height ){//TODO + alone
		int k = get(i,j,width);
		int* neighbors = neighborsIndexes(i,j,width,height);
		int maxIndex = 0;
		float total = tmp[neighbors[0]];
		float max = total;
		for(int u=1 ; u < 8 ; u++){
			float current = tmp[neighbors[u]];
			total += current;
			if(max < current){
				max = current;
				maxIndex = u;
			}
		}
		patchMax[k] = maxIndex * 45;
		total += values[k];
	    	values[k] = total - total * evapCoef;
    	}
}

	.text
	.file	"DiffusionEvaporationGradients_2D.hip"
	.globl	__device_stub__FIELD_MAX_DIR    # -- Begin function __device_stub__FIELD_MAX_DIR
	.type	__device_stub__FIELD_MAX_DIR,@function
__device_stub__FIELD_MAX_DIR:           # @__device_stub__FIELD_MAX_DIR
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	12(%rsp), %rax
	movl	%edi, (%rax)
	leaq	8(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$FIELD_MAX_DIR, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	__device_stub__FIELD_MAX_DIR, .Lfunc_end0-__device_stub__FIELD_MAX_DIR
	.cfi_endproc
                                        # -- End function
	.globl	__device_stub__FIELD_MAX_DIR2   # -- Begin function __device_stub__FIELD_MAX_DIR2
	.type	__device_stub__FIELD_MAX_DIR2,@function
__device_stub__FIELD_MAX_DIR2:          # @__device_stub__FIELD_MAX_DIR2
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	12(%rsp), %rax
	movl	%edi, (%rax)
	leaq	8(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$FIELD_MAX_DIR2, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	__device_stub__FIELD_MAX_DIR2, .Lfunc_end1-__device_stub__FIELD_MAX_DIR2
	.cfi_endproc
                                        # -- End function
	.globl	__device_stub__DIFFUSION_UPDATE_THEN_EVAPORATION_THEN_FIELDMAXDIRV2 # -- Begin function __device_stub__DIFFUSION_UPDATE_THEN_EVAPORATION_THEN_FIELDMAXDIRV2
	.type	__device_stub__DIFFUSION_UPDATE_THEN_EVAPORATION_THEN_FIELDMAXDIRV2,@function
__device_stub__DIFFUSION_UPDATE_THEN_EVAPORATION_THEN_FIELDMAXDIRV2: # @__device_stub__DIFFUSION_UPDATE_THEN_EVAPORATION_THEN_FIELDMAXDIRV2
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	20(%rsp), %rax
	movl	%edi, (%rax)
	leaq	16(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	56(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	48(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	12(%rsp), %rcx
	movss	%xmm0, (%rcx)
	leaq	40(%rsp), %r9
	movq	%r8, (%r9)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r9, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$DIFFUSION_UPDATE_THEN_EVAPORATION_THEN_FIELDMAXDIRV2, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	__device_stub__DIFFUSION_UPDATE_THEN_EVAPORATION_THEN_FIELDMAXDIRV2, .Lfunc_end2-__device_stub__DIFFUSION_UPDATE_THEN_EVAPORATION_THEN_FIELDMAXDIRV2
	.cfi_endproc
                                        # -- End function
	.globl	__device_stub__DIFFUSION_UPDATE_THEN_EVAPORATION_THEN_FIELDMAXDIRV3 # -- Begin function __device_stub__DIFFUSION_UPDATE_THEN_EVAPORATION_THEN_FIELDMAXDIRV3
	.type	__device_stub__DIFFUSION_UPDATE_THEN_EVAPORATION_THEN_FIELDMAXDIRV3,@function
__device_stub__DIFFUSION_UPDATE_THEN_EVAPORATION_THEN_FIELDMAXDIRV3: # @__device_stub__DIFFUSION_UPDATE_THEN_EVAPORATION_THEN_FIELDMAXDIRV3
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	20(%rsp), %rax
	movl	%edi, (%rax)
	leaq	16(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	56(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	48(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	12(%rsp), %rcx
	movss	%xmm0, (%rcx)
	leaq	40(%rsp), %r9
	movq	%r8, (%r9)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r9, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$DIFFUSION_UPDATE_THEN_EVAPORATION_THEN_FIELDMAXDIRV3, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	__device_stub__DIFFUSION_UPDATE_THEN_EVAPORATION_THEN_FIELDMAXDIRV3, .Lfunc_end3-__device_stub__DIFFUSION_UPDATE_THEN_EVAPORATION_THEN_FIELDMAXDIRV3
	.cfi_endproc
                                        # -- End function
	.globl	__device_stub__DIFFUSION_UPDATE_THEN_EVAPORATION_THEN_FIELDMAXDIR # -- Begin function __device_stub__DIFFUSION_UPDATE_THEN_EVAPORATION_THEN_FIELDMAXDIR
	.type	__device_stub__DIFFUSION_UPDATE_THEN_EVAPORATION_THEN_FIELDMAXDIR,@function
__device_stub__DIFFUSION_UPDATE_THEN_EVAPORATION_THEN_FIELDMAXDIR: # @__device_stub__DIFFUSION_UPDATE_THEN_EVAPORATION_THEN_FIELDMAXDIR
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	20(%rsp), %rax
	movl	%edi, (%rax)
	leaq	16(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	56(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	48(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	12(%rsp), %rcx
	movss	%xmm0, (%rcx)
	leaq	40(%rsp), %r9
	movq	%r8, (%r9)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r9, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$DIFFUSION_UPDATE_THEN_EVAPORATION_THEN_FIELDMAXDIR, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end4:
	.size	__device_stub__DIFFUSION_UPDATE_THEN_EVAPORATION_THEN_FIELDMAXDIR, .Lfunc_end4-__device_stub__DIFFUSION_UPDATE_THEN_EVAPORATION_THEN_FIELDMAXDIR
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB5_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB5_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$FIELD_MAX_DIR, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$FIELD_MAX_DIR2, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$DIFFUSION_UPDATE_THEN_EVAPORATION_THEN_FIELDMAXDIRV2, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$DIFFUSION_UPDATE_THEN_EVAPORATION_THEN_FIELDMAXDIRV3, %esi
	movl	$.L__unnamed_4, %edx
	movl	$.L__unnamed_4, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$DIFFUSION_UPDATE_THEN_EVAPORATION_THEN_FIELDMAXDIR, %esi
	movl	$.L__unnamed_5, %edx
	movl	$.L__unnamed_5, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end5:
	.size	__hip_module_ctor, .Lfunc_end5-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB6_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB6_2:
	retq
.Lfunc_end6:
	.size	__hip_module_dtor, .Lfunc_end6-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	FIELD_MAX_DIR,@object           # @FIELD_MAX_DIR
	.section	.rodata,"a",@progbits
	.globl	FIELD_MAX_DIR
	.p2align	3, 0x0
FIELD_MAX_DIR:
	.quad	__device_stub__FIELD_MAX_DIR
	.size	FIELD_MAX_DIR, 8

	.type	FIELD_MAX_DIR2,@object          # @FIELD_MAX_DIR2
	.globl	FIELD_MAX_DIR2
	.p2align	3, 0x0
FIELD_MAX_DIR2:
	.quad	__device_stub__FIELD_MAX_DIR2
	.size	FIELD_MAX_DIR2, 8

	.type	DIFFUSION_UPDATE_THEN_EVAPORATION_THEN_FIELDMAXDIRV2,@object # @DIFFUSION_UPDATE_THEN_EVAPORATION_THEN_FIELDMAXDIRV2
	.globl	DIFFUSION_UPDATE_THEN_EVAPORATION_THEN_FIELDMAXDIRV2
	.p2align	3, 0x0
DIFFUSION_UPDATE_THEN_EVAPORATION_THEN_FIELDMAXDIRV2:
	.quad	__device_stub__DIFFUSION_UPDATE_THEN_EVAPORATION_THEN_FIELDMAXDIRV2
	.size	DIFFUSION_UPDATE_THEN_EVAPORATION_THEN_FIELDMAXDIRV2, 8

	.type	DIFFUSION_UPDATE_THEN_EVAPORATION_THEN_FIELDMAXDIRV3,@object # @DIFFUSION_UPDATE_THEN_EVAPORATION_THEN_FIELDMAXDIRV3
	.globl	DIFFUSION_UPDATE_THEN_EVAPORATION_THEN_FIELDMAXDIRV3
	.p2align	3, 0x0
DIFFUSION_UPDATE_THEN_EVAPORATION_THEN_FIELDMAXDIRV3:
	.quad	__device_stub__DIFFUSION_UPDATE_THEN_EVAPORATION_THEN_FIELDMAXDIRV3
	.size	DIFFUSION_UPDATE_THEN_EVAPORATION_THEN_FIELDMAXDIRV3, 8

	.type	DIFFUSION_UPDATE_THEN_EVAPORATION_THEN_FIELDMAXDIR,@object # @DIFFUSION_UPDATE_THEN_EVAPORATION_THEN_FIELDMAXDIR
	.globl	DIFFUSION_UPDATE_THEN_EVAPORATION_THEN_FIELDMAXDIR
	.p2align	3, 0x0
DIFFUSION_UPDATE_THEN_EVAPORATION_THEN_FIELDMAXDIR:
	.quad	__device_stub__DIFFUSION_UPDATE_THEN_EVAPORATION_THEN_FIELDMAXDIR
	.size	DIFFUSION_UPDATE_THEN_EVAPORATION_THEN_FIELDMAXDIR, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"FIELD_MAX_DIR"
	.size	.L__unnamed_1, 14

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"FIELD_MAX_DIR2"
	.size	.L__unnamed_2, 15

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"DIFFUSION_UPDATE_THEN_EVAPORATION_THEN_FIELDMAXDIRV2"
	.size	.L__unnamed_3, 53

	.type	.L__unnamed_4,@object           # @3
.L__unnamed_4:
	.asciz	"DIFFUSION_UPDATE_THEN_EVAPORATION_THEN_FIELDMAXDIRV3"
	.size	.L__unnamed_4, 53

	.type	.L__unnamed_5,@object           # @4
.L__unnamed_5:
	.asciz	"DIFFUSION_UPDATE_THEN_EVAPORATION_THEN_FIELDMAXDIR"
	.size	.L__unnamed_5, 51

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __device_stub__FIELD_MAX_DIR
	.addrsig_sym __device_stub__FIELD_MAX_DIR2
	.addrsig_sym __device_stub__DIFFUSION_UPDATE_THEN_EVAPORATION_THEN_FIELDMAXDIRV2
	.addrsig_sym __device_stub__DIFFUSION_UPDATE_THEN_EVAPORATION_THEN_FIELDMAXDIRV3
	.addrsig_sym __device_stub__DIFFUSION_UPDATE_THEN_EVAPORATION_THEN_FIELDMAXDIR
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym FIELD_MAX_DIR
	.addrsig_sym FIELD_MAX_DIR2
	.addrsig_sym DIFFUSION_UPDATE_THEN_EVAPORATION_THEN_FIELDMAXDIRV2
	.addrsig_sym DIFFUSION_UPDATE_THEN_EVAPORATION_THEN_FIELDMAXDIRV3
	.addrsig_sym DIFFUSION_UPDATE_THEN_EVAPORATION_THEN_FIELDMAXDIR
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	FIELD_MAX_DIR           ; -- Begin function FIELD_MAX_DIR
	.globl	FIELD_MAX_DIR
	.p2align	8
	.type	FIELD_MAX_DIR,@function
FIELD_MAX_DIR:                          ; @FIELD_MAX_DIR
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x24
	s_load_b64 s[4:5], s[0:1], 0x0
	v_and_b32_e32 v2, 0x3ff, v0
	v_bfe_u32 v3, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s2, 16
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[0:1], null, s14, s2, v[2:3]
	v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_i32_e32 vcc_lo, s4, v0
	v_cmp_gt_i32_e64 s2, s5, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, vcc_lo, s2
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_2
; %bb.1:
	s_load_b64 s[0:1], s[0:1], 0x10
	v_mad_u64_u32 v[2:3], null, v1, s4, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[0:1], 2, v[2:3]
	v_mov_b32_e32 v2, 0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v0, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	global_store_b32 v[0:1], v2, off
.LBB0_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel FIELD_MAX_DIR
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 5
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	FIELD_MAX_DIR, .Lfunc_end0-FIELD_MAX_DIR
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 180
; NumSgprs: 18
; NumVgprs: 5
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 5
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	FIELD_MAX_DIR2          ; -- Begin function FIELD_MAX_DIR2
	.globl	FIELD_MAX_DIR2
	.p2align	8
	.type	FIELD_MAX_DIR2,@function
FIELD_MAX_DIR2:                         ; @FIELD_MAX_DIR2
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x24
	s_load_b64 s[4:5], s[0:1], 0x0
	v_and_b32_e32 v2, 0x3ff, v0
	v_bfe_u32 v3, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s2, 16
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[0:1], null, s14, s2, v[2:3]
	v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_i32_e32 vcc_lo, s4, v0
	v_cmp_gt_i32_e64 s2, s5, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, vcc_lo, s2
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB1_2
; %bb.1:
	v_add_nc_u32_e32 v3, 1, v0
	v_add_nc_u32_e32 v2, 1, v1
	s_add_i32 s7, s5, -1
	s_add_i32 s6, s4, -1
	v_mul_lo_u32 v14, v1, s4
	s_load_b128 s[0:3], s[0:1], 0x8
	v_cmp_ne_u32_e32 vcc_lo, s5, v2
	v_cndmask_b32_e32 v2, 0, v2, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, s4, v3
	v_cndmask_b32_e32 v3, 0, v3, vcc_lo
	v_cmp_gt_i32_e32 vcc_lo, -1, v1
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v2, v2, s7, vcc_lo
	v_cmp_gt_i32_e32 vcc_lo, -1, v0
	v_mul_lo_u32 v7, v2, s4
	v_cndmask_b32_e64 v15, v3, s6, vcc_lo
	v_add_nc_u32_e32 v3, -1, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v2, v15, v14
	v_cmp_ne_u32_e32 vcc_lo, s4, v3
	v_add_nc_u32_e32 v4, -1, v1
	v_dual_cndmask_b32 v5, 0, v3 :: v_dual_add_nc_u32 v6, v7, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_4)
	v_cmp_ne_u32_e32 vcc_lo, s5, v4
	v_ashrrev_i32_e32 v3, 31, v2
	v_cndmask_b32_e32 v8, 0, v4, vcc_lo
	v_add_nc_u32_e32 v4, v7, v15
	v_cmp_gt_i32_e32 vcc_lo, 1, v0
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	v_cndmask_b32_e64 v11, v5, s6, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_ashrrev_i32_e32 v5, 31, v4
	v_cmp_gt_i32_e32 vcc_lo, 1, v1
	v_add_nc_u32_e32 v1, v7, v11
	s_delay_alu instid0(VALU_DEP_3)
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	v_cndmask_b32_e64 v10, v8, s7, vcc_lo
	v_ashrrev_i32_e32 v7, 31, v6
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v8, vcc_lo, s0, v2
	v_add_co_ci_u32_e32 v9, vcc_lo, s1, v3, vcc_lo
	v_ashrrev_i32_e32 v2, 31, v1
	v_add_co_u32 v3, vcc_lo, s0, v4
	v_lshlrev_b64 v[6:7], 2, v[6:7]
	v_add_co_ci_u32_e32 v4, vcc_lo, s1, v5, vcc_lo
	v_mul_lo_u32 v16, v10, s4
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_clause 0x1
	global_load_b32 v9, v[8:9], off
	global_load_b32 v17, v[3:4], off
	v_add_nc_u32_e32 v10, v11, v14
	v_add_co_u32 v5, vcc_lo, s0, v6
	v_add_co_ci_u32_e32 v6, vcc_lo, s1, v7, vcc_lo
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_nc_u32_e32 v12, v16, v11
	v_ashrrev_i32_e32 v11, 31, v10
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	v_add_nc_u32_e32 v7, v16, v15
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_ashrrev_i32_e32 v13, 31, v12
	v_lshlrev_b64 v[3:4], 2, v[10:11]
	s_clause 0x1
	global_load_b32 v10, v[5:6], off
	global_load_b32 v11, v[1:2], off
	v_add_nc_u32_e32 v5, v16, v0
	v_ashrrev_i32_e32 v8, 31, v7
	v_lshlrev_b64 v[1:2], 2, v[12:13]
	v_add_nc_u32_e32 v0, v14, v0
	v_add_co_u32 v3, vcc_lo, s0, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	s_clause 0x1
	global_load_b32 v12, v[3:4], off
	global_load_b32 v13, v[1:2], off
	v_ashrrev_i32_e32 v6, 31, v5
	v_lshlrev_b64 v[3:4], 2, v[7:8]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[5:6], 2, v[5:6]
	v_add_co_u32 v1, vcc_lo, s0, v5
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v6, vcc_lo
	global_load_b32 v5, v[1:2], off
	v_add_co_u32 v1, vcc_lo, s0, v3
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v4, vcc_lo
	global_load_b32 v2, v[1:2], off
	s_waitcnt vmcnt(6)
	v_cmp_gt_f32_e32 vcc_lo, v17, v9
	v_cndmask_b32_e32 v1, v9, v17, vcc_lo
	v_cndmask_b32_e64 v3, 0, 45, vcc_lo
	s_waitcnt vmcnt(5)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cmp_gt_f32_e32 vcc_lo, v10, v1
	v_cndmask_b32_e32 v1, v1, v10, vcc_lo
	v_cndmask_b32_e64 v3, v3, 0x5a, vcc_lo
	s_waitcnt vmcnt(4)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cmp_gt_f32_e32 vcc_lo, v11, v1
	v_cndmask_b32_e32 v1, v1, v11, vcc_lo
	v_cndmask_b32_e64 v3, v3, 0x87, vcc_lo
	s_waitcnt vmcnt(3)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cmp_gt_f32_e32 vcc_lo, v12, v1
	v_cndmask_b32_e32 v1, v1, v12, vcc_lo
	v_cndmask_b32_e64 v3, v3, 0xb4, vcc_lo
	s_waitcnt vmcnt(2)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cmp_gt_f32_e32 vcc_lo, v13, v1
	v_cndmask_b32_e32 v4, v1, v13, vcc_lo
	v_cndmask_b32_e64 v3, v3, 0xe1, vcc_lo
	v_ashrrev_i32_e32 v1, 31, v0
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_f32_e32 vcc_lo, v5, v4
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	v_cndmask_b32_e32 v4, v4, v5, vcc_lo
	v_cndmask_b32_e64 v3, v3, 0x10e, vcc_lo
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_ngt_f32_e32 vcc_lo, v2, v4
	v_cndmask_b32_e32 v2, 0x13b, v3, vcc_lo
	v_add_co_u32 v0, vcc_lo, s2, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
	global_store_b32 v[0:1], v2, off
.LBB1_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel FIELD_MAX_DIR2
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 18
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	FIELD_MAX_DIR2, .Lfunc_end1-FIELD_MAX_DIR2
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 808
; NumSgprs: 18
; NumVgprs: 18
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 18
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	DIFFUSION_UPDATE_THEN_EVAPORATION_THEN_FIELDMAXDIRV2 ; -- Begin function DIFFUSION_UPDATE_THEN_EVAPORATION_THEN_FIELDMAXDIRV2
	.globl	DIFFUSION_UPDATE_THEN_EVAPORATION_THEN_FIELDMAXDIRV2
	.p2align	8
	.type	DIFFUSION_UPDATE_THEN_EVAPORATION_THEN_FIELDMAXDIRV2,@function
DIFFUSION_UPDATE_THEN_EVAPORATION_THEN_FIELDMAXDIRV2: ; @DIFFUSION_UPDATE_THEN_EVAPORATION_THEN_FIELDMAXDIRV2
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x34
	s_load_b64 s[8:9], s[0:1], 0x0
	v_and_b32_e32 v2, 0x3ff, v0
	v_bfe_u32 v3, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s2, 16
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[0:1], null, s14, s2, v[2:3]
	v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_i32_e32 vcc_lo, s8, v0
	v_cmp_gt_i32_e64 s2, s9, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, vcc_lo, s2
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB2_2
; %bb.1:
	v_add_nc_u32_e32 v3, 1, v0
	v_add_nc_u32_e32 v2, 1, v1
	s_add_i32 s2, s9, -1
	s_add_i32 s3, s8, -1
	v_mul_lo_u32 v10, v1, s8
	s_clause 0x1
	s_load_b128 s[4:7], s[0:1], 0x8
	s_load_b32 s10, s[0:1], 0x18
	v_cmp_ne_u32_e32 vcc_lo, s9, v2
	v_add_nc_u32_e32 v8, -1, v1
	s_load_b64 s[0:1], s[0:1], 0x20
	v_cndmask_b32_e32 v2, 0, v2, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, s8, v3
	v_cndmask_b32_e32 v3, 0, v3, vcc_lo
	v_cmp_gt_i32_e32 vcc_lo, -1, v1
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v2, v2, s2, vcc_lo
	v_cmp_gt_i32_e32 vcc_lo, -1, v0
	v_mul_lo_u32 v7, v2, s8
	v_cndmask_b32_e64 v11, v3, s3, vcc_lo
	v_add_nc_u32_e32 v3, -1, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_ne_u32_e32 vcc_lo, s8, v3
	v_add_nc_u32_e32 v2, v11, v10
	v_dual_cndmask_b32 v5, 0, v3 :: v_dual_add_nc_u32 v6, v7, v0
	v_cmp_gt_i32_e32 vcc_lo, 1, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_ashrrev_i32_e32 v3, 31, v2
	v_cndmask_b32_e64 v12, v5, s3, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, s9, v8
	v_add_nc_u32_e32 v4, v7, v11
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	v_cndmask_b32_e32 v9, 0, v8, vcc_lo
	v_ashrrev_i32_e32 v5, 31, v4
	v_add_nc_u32_e32 v8, v7, v12
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s6, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	v_ashrrev_i32_e32 v7, 31, v6
	v_add_co_u32 v4, vcc_lo, s6, v4
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v5, vcc_lo, s7, v5, vcc_lo
	s_clause 0x1
	global_load_b32 v13, v[2:3], off
	global_load_b32 v14, v[4:5], off
	v_cmp_gt_i32_e32 vcc_lo, 1, v1
	v_lshlrev_b64 v[6:7], 2, v[6:7]
	v_add_nc_u32_e32 v3, v12, v10
	v_cndmask_b32_e64 v1, v9, s2, vcc_lo
	v_ashrrev_i32_e32 v9, 31, v8
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_co_u32 v5, vcc_lo, s6, v6
	v_add_co_ci_u32_e32 v6, vcc_lo, s7, v7, vcc_lo
	v_mul_lo_u32 v15, v1, s8
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[1:2], 2, v[8:9]
	v_ashrrev_i32_e32 v4, 31, v3
	v_add_co_u32 v1, vcc_lo, s6, v1
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
	v_add_nc_u32_e32 v7, v15, v12
	s_clause 0x1
	global_load_b32 v9, v[5:6], off
	global_load_b32 v12, v[1:2], off
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	v_add_nc_u32_e32 v5, v15, v0
	v_ashrrev_i32_e32 v8, 31, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, s6, v3
	v_lshlrev_b64 v[1:2], 2, v[7:8]
	v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
	v_add_nc_u32_e32 v7, v15, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v1, vcc_lo, s6, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
	s_clause 0x1
	global_load_b32 v11, v[3:4], off
	global_load_b32 v15, v[1:2], off
	v_add_nc_u32_e32 v3, v10, v0
	v_ashrrev_i32_e32 v8, 31, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v4, 31, v3
	v_lshlrev_b64 v[1:2], 2, v[7:8]
	s_waitcnt vmcnt(4)
	v_add_f32_e32 v10, v13, v14
	v_ashrrev_i32_e32 v6, 31, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[5:6], 2, v[5:6]
	v_add_co_u32 v5, vcc_lo, s6, v5
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v6, vcc_lo, s7, v6, vcc_lo
	v_add_co_u32 v0, vcc_lo, s6, v1
	v_add_co_ci_u32_e32 v1, vcc_lo, s7, v2, vcc_lo
	v_lshlrev_b64 v[2:3], 2, v[3:4]
	s_clause 0x1
	global_load_b32 v4, v[5:6], off
	global_load_b32 v5, v[0:1], off
	v_add_co_u32 v0, vcc_lo, s4, v2
	v_add_co_ci_u32_e32 v1, vcc_lo, s5, v3, vcc_lo
	v_cmp_gt_f32_e32 vcc_lo, v14, v13
	global_load_b32 v6, v[0:1], off
	v_cndmask_b32_e32 v8, v13, v14, vcc_lo
	v_cndmask_b32_e64 v7, 0, 45, vcc_lo
	s_waitcnt vmcnt(6)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cmp_gt_f32_e32 vcc_lo, v9, v8
	v_cndmask_b32_e32 v8, v8, v9, vcc_lo
	v_cndmask_b32_e64 v7, v7, 0x5a, vcc_lo
	v_add_f32_e32 v9, v10, v9
	s_waitcnt vmcnt(5)
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_f32_e32 vcc_lo, v12, v8
	v_add_f32_e32 v9, v9, v12
	v_cndmask_b32_e32 v8, v8, v12, vcc_lo
	v_cndmask_b32_e64 v7, v7, 0x87, vcc_lo
	s_waitcnt vmcnt(4)
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v9, v9, v11
	v_cmp_gt_f32_e32 vcc_lo, v11, v8
	v_cndmask_b32_e32 v8, v8, v11, vcc_lo
	v_cndmask_b32_e64 v7, v7, 0xb4, vcc_lo
	s_waitcnt vmcnt(3)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cmp_gt_f32_e32 vcc_lo, v15, v8
	v_cndmask_b32_e32 v8, v8, v15, vcc_lo
	v_cndmask_b32_e64 v7, v7, 0xe1, vcc_lo
	s_waitcnt vmcnt(2)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cmp_gt_f32_e32 vcc_lo, v4, v8
	v_add_f32_e32 v9, v9, v15
	v_cndmask_b32_e64 v7, v7, 0x10e, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f32_e32 v9, v9, v4
	s_waitcnt vmcnt(1)
	v_dual_add_f32 v9, v9, v5 :: v_dual_cndmask_b32 v4, v8, v4
	v_add_co_u32 v2, vcc_lo, s0, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_cmp_ngt_f32_e32 vcc_lo, v5, v4
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v6, v9, v6
	v_cndmask_b32_e32 v4, 0x13b, v7, vcc_lo
	v_fma_f32 v5, -v6, s10, v6
	global_store_b32 v[2:3], v4, off
	global_store_b32 v[0:1], v5, off
.LBB2_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel DIFFUSION_UPDATE_THEN_EVAPORATION_THEN_FIELDMAXDIRV2
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 16
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	DIFFUSION_UPDATE_THEN_EVAPORATION_THEN_FIELDMAXDIRV2, .Lfunc_end2-DIFFUSION_UPDATE_THEN_EVAPORATION_THEN_FIELDMAXDIRV2
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 928
; NumSgprs: 18
; NumVgprs: 16
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 16
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	DIFFUSION_UPDATE_THEN_EVAPORATION_THEN_FIELDMAXDIRV3 ; -- Begin function DIFFUSION_UPDATE_THEN_EVAPORATION_THEN_FIELDMAXDIRV3
	.globl	DIFFUSION_UPDATE_THEN_EVAPORATION_THEN_FIELDMAXDIRV3
	.p2align	8
	.type	DIFFUSION_UPDATE_THEN_EVAPORATION_THEN_FIELDMAXDIRV3,@function
DIFFUSION_UPDATE_THEN_EVAPORATION_THEN_FIELDMAXDIRV3: ; @DIFFUSION_UPDATE_THEN_EVAPORATION_THEN_FIELDMAXDIRV3
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x34
	s_load_b64 s[8:9], s[0:1], 0x0
	v_and_b32_e32 v2, 0x3ff, v0
	v_bfe_u32 v3, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s2, 16
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[0:1], null, s14, s2, v[2:3]
	v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_i32_e32 vcc_lo, s8, v0
	v_cmp_gt_i32_e64 s2, s9, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, vcc_lo, s2
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB3_2
; %bb.1:
	v_add_nc_u32_e32 v3, 1, v0
	v_add_nc_u32_e32 v2, 1, v1
	s_add_i32 s2, s9, -1
	s_add_i32 s3, s8, -1
	v_mul_lo_u32 v10, v1, s8
	s_clause 0x1
	s_load_b128 s[4:7], s[0:1], 0x8
	s_load_b32 s10, s[0:1], 0x18
	v_cmp_ne_u32_e32 vcc_lo, s9, v2
	v_add_nc_u32_e32 v8, -1, v1
	s_load_b64 s[0:1], s[0:1], 0x20
	v_cndmask_b32_e32 v2, 0, v2, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, s8, v3
	v_cndmask_b32_e32 v3, 0, v3, vcc_lo
	v_cmp_gt_i32_e32 vcc_lo, -1, v1
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v2, v2, s2, vcc_lo
	v_cmp_gt_i32_e32 vcc_lo, -1, v0
	v_mul_lo_u32 v7, v2, s8
	v_cndmask_b32_e64 v11, v3, s3, vcc_lo
	v_add_nc_u32_e32 v3, -1, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_ne_u32_e32 vcc_lo, s8, v3
	v_add_nc_u32_e32 v2, v11, v10
	v_dual_cndmask_b32 v5, 0, v3 :: v_dual_add_nc_u32 v6, v7, v0
	v_cmp_gt_i32_e32 vcc_lo, 1, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_ashrrev_i32_e32 v3, 31, v2
	v_cndmask_b32_e64 v12, v5, s3, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, s9, v8
	v_add_nc_u32_e32 v4, v7, v11
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	v_cndmask_b32_e32 v9, 0, v8, vcc_lo
	v_ashrrev_i32_e32 v5, 31, v4
	v_add_nc_u32_e32 v8, v7, v12
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s6, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	v_ashrrev_i32_e32 v7, 31, v6
	v_add_co_u32 v4, vcc_lo, s6, v4
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v5, vcc_lo, s7, v5, vcc_lo
	s_clause 0x1
	global_load_b32 v13, v[2:3], off
	global_load_b32 v14, v[4:5], off
	v_cmp_gt_i32_e32 vcc_lo, 1, v1
	v_lshlrev_b64 v[6:7], 2, v[6:7]
	v_add_nc_u32_e32 v3, v12, v10
	v_cndmask_b32_e64 v1, v9, s2, vcc_lo
	v_ashrrev_i32_e32 v9, 31, v8
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_co_u32 v5, vcc_lo, s6, v6
	v_add_co_ci_u32_e32 v6, vcc_lo, s7, v7, vcc_lo
	v_mul_lo_u32 v15, v1, s8
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[1:2], 2, v[8:9]
	v_ashrrev_i32_e32 v4, 31, v3
	v_add_co_u32 v1, vcc_lo, s6, v1
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
	v_add_nc_u32_e32 v7, v15, v12
	s_clause 0x1
	global_load_b32 v9, v[5:6], off
	global_load_b32 v12, v[1:2], off
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	v_add_nc_u32_e32 v5, v15, v0
	v_ashrrev_i32_e32 v8, 31, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, s6, v3
	v_lshlrev_b64 v[1:2], 2, v[7:8]
	v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
	v_add_nc_u32_e32 v7, v15, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v1, vcc_lo, s6, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
	s_clause 0x1
	global_load_b32 v11, v[3:4], off
	global_load_b32 v15, v[1:2], off
	v_add_nc_u32_e32 v3, v10, v0
	v_ashrrev_i32_e32 v8, 31, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v4, 31, v3
	v_lshlrev_b64 v[1:2], 2, v[7:8]
	s_waitcnt vmcnt(4)
	v_add_f32_e32 v10, v13, v14
	v_ashrrev_i32_e32 v6, 31, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[5:6], 2, v[5:6]
	v_add_co_u32 v5, vcc_lo, s6, v5
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v6, vcc_lo, s7, v6, vcc_lo
	v_add_co_u32 v0, vcc_lo, s6, v1
	v_add_co_ci_u32_e32 v1, vcc_lo, s7, v2, vcc_lo
	v_lshlrev_b64 v[2:3], 2, v[3:4]
	s_clause 0x1
	global_load_b32 v4, v[5:6], off
	global_load_b32 v5, v[0:1], off
	v_add_co_u32 v0, vcc_lo, s4, v2
	v_add_co_ci_u32_e32 v1, vcc_lo, s5, v3, vcc_lo
	v_cmp_gt_f32_e32 vcc_lo, v14, v13
	global_load_b32 v6, v[0:1], off
	v_cndmask_b32_e32 v8, v13, v14, vcc_lo
	v_cndmask_b32_e64 v7, 0, 45, vcc_lo
	s_waitcnt vmcnt(6)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cmp_gt_f32_e32 vcc_lo, v9, v8
	v_cndmask_b32_e32 v8, v8, v9, vcc_lo
	v_cndmask_b32_e64 v7, v7, 0x5a, vcc_lo
	v_add_f32_e32 v9, v10, v9
	s_waitcnt vmcnt(5)
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_f32_e32 vcc_lo, v12, v8
	v_add_f32_e32 v9, v9, v12
	v_cndmask_b32_e32 v8, v8, v12, vcc_lo
	v_cndmask_b32_e64 v7, v7, 0x87, vcc_lo
	s_waitcnt vmcnt(4)
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v9, v9, v11
	v_cmp_gt_f32_e32 vcc_lo, v11, v8
	v_cndmask_b32_e32 v8, v8, v11, vcc_lo
	v_cndmask_b32_e64 v7, v7, 0xb4, vcc_lo
	s_waitcnt vmcnt(3)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cmp_gt_f32_e32 vcc_lo, v15, v8
	v_cndmask_b32_e32 v8, v8, v15, vcc_lo
	v_cndmask_b32_e64 v7, v7, 0xe1, vcc_lo
	s_waitcnt vmcnt(2)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cmp_gt_f32_e32 vcc_lo, v4, v8
	v_add_f32_e32 v9, v9, v15
	v_cndmask_b32_e64 v7, v7, 0x10e, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f32_e32 v9, v9, v4
	s_waitcnt vmcnt(1)
	v_dual_add_f32 v9, v9, v5 :: v_dual_cndmask_b32 v4, v8, v4
	v_add_co_u32 v2, vcc_lo, s0, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_cmp_ngt_f32_e32 vcc_lo, v5, v4
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v6, v9, v6
	v_cndmask_b32_e32 v4, 0x13b, v7, vcc_lo
	v_fma_f32 v5, -v6, s10, v6
	global_store_b32 v[2:3], v4, off
	global_store_b32 v[0:1], v5, off
.LBB3_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel DIFFUSION_UPDATE_THEN_EVAPORATION_THEN_FIELDMAXDIRV3
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 16
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end3:
	.size	DIFFUSION_UPDATE_THEN_EVAPORATION_THEN_FIELDMAXDIRV3, .Lfunc_end3-DIFFUSION_UPDATE_THEN_EVAPORATION_THEN_FIELDMAXDIRV3
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 928
; NumSgprs: 18
; NumVgprs: 16
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 16
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	DIFFUSION_UPDATE_THEN_EVAPORATION_THEN_FIELDMAXDIR ; -- Begin function DIFFUSION_UPDATE_THEN_EVAPORATION_THEN_FIELDMAXDIR
	.globl	DIFFUSION_UPDATE_THEN_EVAPORATION_THEN_FIELDMAXDIR
	.p2align	8
	.type	DIFFUSION_UPDATE_THEN_EVAPORATION_THEN_FIELDMAXDIR,@function
DIFFUSION_UPDATE_THEN_EVAPORATION_THEN_FIELDMAXDIR: ; @DIFFUSION_UPDATE_THEN_EVAPORATION_THEN_FIELDMAXDIR
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x34
	s_load_b64 s[4:5], s[0:1], 0x0
	v_and_b32_e32 v2, 0x3ff, v0
	v_bfe_u32 v3, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s2, 16
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[0:1], null, s14, s2, v[2:3]
	v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_i32_e32 vcc_lo, s4, v0
	v_cmp_gt_i32_e64 s2, s5, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, vcc_lo, s2
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB4_2
; %bb.1:
	s_clause 0x1
	s_load_b128 s[8:11], s[0:1], 0x8
	s_load_b32 s2, s[0:1], 0x18
	v_mad_u64_u32 v[2:3], null, v1, s4, v[0:1]
	s_load_b64 s[0:1], s[0:1], 0x20
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[0:1], 2, v[2:3]
	s_waitcnt lgkmcnt(0)
	s_load_b32 s3, s[10:11], 0x0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s8, v0
	v_add_co_ci_u32_e32 v3, vcc_lo, s9, v1, vcc_lo
	v_add_co_u32 v0, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	global_load_b32 v4, v[2:3], off
	s_waitcnt lgkmcnt(0)
	v_fma_f32 v5, s3, 2.0, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v5, s3, v5
	v_add_f32_e32 v5, s3, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v5, s3, v5
	v_add_f32_e32 v5, s3, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f32_e32 v5, s3, v5
	s_waitcnt vmcnt(0)
	v_dual_add_f32 v4, v5, v4 :: v_dual_mov_b32 v5, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f32 v4, -v4, s2, v4
	global_store_b32 v[0:1], v5, off
	global_store_b32 v[2:3], v4, off
.LBB4_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel DIFFUSION_UPDATE_THEN_EVAPORATION_THEN_FIELDMAXDIR
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 6
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end4:
	.size	DIFFUSION_UPDATE_THEN_EVAPORATION_THEN_FIELDMAXDIR, .Lfunc_end4-DIFFUSION_UPDATE_THEN_EVAPORATION_THEN_FIELDMAXDIR
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 300
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
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        .size:           4
        .value_kind:     by_value
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        .size:           4
        .value_kind:     by_value
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        .size:           2
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        .size:           2
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        .size:           8
        .value_kind:     hidden_global_offset_x
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        .size:           8
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        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           FIELD_MAX_DIR
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         FIELD_MAX_DIR.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     5
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .offset:         0
        .size:           4
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        .size:           4
        .value_kind:     by_value
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        .size:           8
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        .size:           8
        .value_kind:     hidden_global_offset_z
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        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
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      - 0
    .max_flat_workgroup_size: 1024
    .name:           FIELD_MAX_DIR2
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         FIELD_MAX_DIR2.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     18
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
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    .private_segment_fixed_size: 0
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    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     16
    .vgpr_spill_count: 0
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    .language:       OpenCL C
    .language_version:
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      - 0
    .max_flat_workgroup_size: 1024
    .name:           DIFFUSION_UPDATE_THEN_EVAPORATION_THEN_FIELDMAXDIR
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         DIFFUSION_UPDATE_THEN_EVAPORATION_THEN_FIELDMAXDIR.kd
    .uniform_work_group_size: 1
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    .vgpr_count:     6
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
