#define BLOCK_WIDTH 32
//#define BLOCK_HEIGHT 32
#define BLOCK_HEIGHT 16
#define TILE_WIDTH 96
//#define TILE_HEIGHT 96
#define TILE_HEIGHT 48
#define SMALL_TILE_WIDTH 64
//#define SMALL_TILE_HEIGHT 64
#define SMALL_TILE_HEIGHT 32

__global__ void superResolutionKernel(float* o_arr1d, float* i_arr1d, int rows, int cols) {
    
    __shared__ float tile[TILE_HEIGHT][TILE_WIDTH];
    __shared__ float buf[SMALL_TILE_HEIGHT][TILE_WIDTH]; // buffer for down/up sampling
    __shared__ float small_tile[SMALL_TILE_HEIGHT][SMALL_TILE_WIDTH];

    int tx = threadIdx.x;
    int ty = threadIdx.y;

    for(int offset_y = 0; offset_y < TILE_HEIGHT; offset_y += BLOCK_HEIGHT) {
        for(int offset_x = 0; offset_x < TILE_WIDTH; offset_x += BLOCK_WIDTH) {
            int xidx = blockIdx.x * TILE_WIDTH + offset_x + tx;
            int yidx = blockIdx.y * TILE_HEIGHT + offset_y + ty;
            tile[offset_y + ty][offset_x + tx] = i_arr1d[yidx * cols + xidx];
        }
    }
    __syncthreads();

    // col downsample: (TILE_HEIGHT, TILE_WIDTH) -> (SMALL_TILE_HEIGHT, TILE_WIDTH)
    for(int offset_x = 0; offset_x < TILE_WIDTH; offset_x += BLOCK_WIDTH) {
        buf[2*ty][offset_x + tx] = -0.022 * tile[3*ty][offset_x + tx] + 0.974 * tile[3*ty+1][offset_x + tx] + 0.227 * tile[3*ty+2][offset_x + tx];
        buf[2*ty+1][offset_x + tx] = 0.227 * tile[3*ty][offset_x + tx] + 0.974 * tile[3*ty+1][offset_x + tx] + -0.022 * tile[3*ty+2][offset_x + tx];
    }
    __syncthreads();

    // row downsample: (SMALL_TILE_HEIGHT, TILE_WIDTH) -> (SMALL_TILE_HEIGHT, SMALL_TILE_WIDTH)
    for(int offset_y = 0; offset_y < SMALL_TILE_HEIGHT; offset_y += BLOCK_HEIGHT) {
        small_tile[offset_y + ty][2*tx] = -0.022 * buf[offset_y + ty][3*tx] + 0.974 * buf[offset_y + ty][3*tx+1] + 0.227 * buf[offset_y + ty][3*tx+2];
        small_tile[offset_y + ty][2*tx+1] = 0.227 * buf[offset_y + ty][3*tx] + 0.974 * buf[offset_y + ty][3*tx+1] + -0.022 * buf[offset_y + ty][3*tx+2];
    }
    __syncthreads();

    // row upsample: (SMALL_TILE_HEIGHT, SMALL_TILE_WIDTH) -> (SMALL_TILE_HEIGHT, TILE_WIDTH)
    for(int offset_y = 0; offset_y < SMALL_TILE_HEIGHT; offset_y += BLOCK_HEIGHT) {
        // 3*tx
        if(tx == 0)
            buf[offset_y + ty][0] = 0.927 * small_tile[offset_y + ty][0] + -0.047 * small_tile[offset_y + ty][1];
        else
            buf[offset_y + ty][3*tx] = 0.119 * small_tile[offset_y + ty][2*tx-1] + 0.927 * small_tile[offset_y + ty][2*tx]
                + -0.047 * small_tile[offset_y + ty][2*tx+1];
        // 3*tx+2
        if(tx == BLOCK_WIDTH-1)
            buf[offset_y + ty][TILE_WIDTH-1] = -0.047 * small_tile[offset_y + ty][SMALL_TILE_WIDTH-2] + 0.927 * small_tile[offset_y + ty][SMALL_TILE_WIDTH-1];
        else
            buf[offset_y + ty][3*tx+2] = -0.047 * small_tile[offset_y + ty][2*tx] + 0.927 * small_tile[offset_y + ty][2*tx+1]
                + 0.119 * small_tile[offset_y + ty][2*tx+2];
        // 3*tx+1
        if(tx == 0)
            buf[offset_y + ty][1] = 0.6 * small_tile[offset_y + ty][0] + 0.6 * small_tile[offset_y + ty][1] + -0.1 * small_tile[offset_y + ty][2];
        else if(tx == BLOCK_WIDTH-1)
            buf[offset_y + ty][TILE_WIDTH-2] = -0.1 * small_tile[offset_y + ty][SMALL_TILE_WIDTH-3] + 0.6 * small_tile[offset_y + ty][SMALL_TILE_WIDTH-2] 
                + 0.6 * small_tile[offset_y + ty][SMALL_TILE_WIDTH-1];
        else
            buf[offset_y + ty][3*tx+1] = -0.1 * small_tile[offset_y + ty][2*tx-1] + 0.6 * small_tile[offset_y + ty][2*tx]
                + 0.6 * small_tile[offset_y + ty][2*tx+1] + -0.1 * small_tile[offset_y + ty][2*tx+2];
    }
    __syncthreads();

    // col upsample: (SMALL_TILE_HEIGHT, TILE_WIDTH) -> (TILE_HEIGHT, TILE_WIDTH)
    for(int offset_x = 0; offset_x < TILE_WIDTH; offset_x += BLOCK_WIDTH) {
        int xidx = blockIdx.x * TILE_WIDTH + offset_x + tx;
        // 3*ty
        if(ty == 0) {
            int yidx = blockIdx.y * TILE_HEIGHT;
            o_arr1d[yidx * cols + xidx] = 0.927 * buf[0][offset_x + tx] + -0.047 * buf[1][offset_x + tx];
        
        }
        else {
            int yidx = blockIdx.y * TILE_HEIGHT + 3*ty;
            o_arr1d[yidx * cols + xidx] = 0.119 * buf[2*tx-1][offset_x + tx] + 0.927 * buf[2*tx][offset_x + tx]
                + -0.047 * buf[2*tx+1][offset_x + tx];
        }
        // 3*ty+2
        if(ty == BLOCK_HEIGHT-1) {
            int yidx = blockIdx.y * TILE_HEIGHT + TILE_HEIGHT-1;
            o_arr1d[yidx * cols + xidx] = -0.047 * buf[SMALL_TILE_HEIGHT-2][offset_x + tx] + 0.927 * buf[SMALL_TILE_HEIGHT-1][offset_x + tx];
        }
        else {
            int yidx = blockIdx.y * TILE_HEIGHT + 3*ty+2;
            o_arr1d[yidx * cols + xidx] = -0.047 * buf[2*ty][offset_x + tx] + 0.927 * buf[2*ty+1][offset_x + tx]
                + 0.119 * small_tile[2*ty+2][offset_x + tx];
        }
        // 3*ty+1
        if(ty == 0) {
            int yidx = blockIdx.y * TILE_HEIGHT + 1;
            o_arr1d[yidx * cols + xidx] = 0.6 * buf[0][offset_x + tx] + 0.6 * buf[1][offset_x + tx] + -0.1 * buf[2][offset_x + tx];
        }
        else if(ty == BLOCK_HEIGHT-1) {
            int yidx = blockIdx.y * TILE_HEIGHT + TILE_HEIGHT-2;
            o_arr1d[yidx * cols + xidx] = -0.1 * buf[SMALL_TILE_HEIGHT-3][offset_x + tx] + 0.6 * buf[SMALL_TILE_HEIGHT-2][offset_x + tx] 
                + 0.6 * buf[SMALL_TILE_HEIGHT-1][offset_x + tx];
        }
        else {
            int yidx = blockIdx.y * TILE_HEIGHT + 3*ty+1;
            o_arr1d[yidx * cols + xidx] = -0.1 * buf[2*ty-1][offset_x + tx] + 0.6 * buf[2*ty][offset_x + tx]
                + 0.6 * buf[2*ty+1][offset_x + tx] + -0.1 * buf[2*ty+2][offset_x + tx];
        }
    }


}

	.file	"tmpxft_0026e349_00000000-6_kernel.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2010:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2010:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z45__device_stub__Z21superResolutionKernelPfS_iiPfS_ii
	.type	_Z45__device_stub__Z21superResolutionKernelPfS_iiPfS_ii, @function
_Z45__device_stub__Z21superResolutionKernelPfS_iiPfS_ii:
.LFB2032:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z21superResolutionKernelPfS_ii(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L2:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2032:
	.size	_Z45__device_stub__Z21superResolutionKernelPfS_iiPfS_ii, .-_Z45__device_stub__Z21superResolutionKernelPfS_iiPfS_ii
	.globl	_Z21superResolutionKernelPfS_ii
	.type	_Z21superResolutionKernelPfS_ii, @function
_Z21superResolutionKernelPfS_ii:
.LFB2033:
	.cfi_startproc
	endbr64
	jmp	_Z45__device_stub__Z21superResolutionKernelPfS_iiPfS_ii
	.cfi_endproc
.LFE2033:
	.size	_Z21superResolutionKernelPfS_ii, .-_Z21superResolutionKernelPfS_ii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z21superResolutionKernelPfS_ii"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2035:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z21superResolutionKernelPfS_ii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2035:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#define BLOCK_WIDTH 32
//#define BLOCK_HEIGHT 32
#define BLOCK_HEIGHT 16
#define TILE_WIDTH 96
//#define TILE_HEIGHT 96
#define TILE_HEIGHT 48
#define SMALL_TILE_WIDTH 64
//#define SMALL_TILE_HEIGHT 64
#define SMALL_TILE_HEIGHT 32

__global__ void superResolutionKernel(float* o_arr1d, float* i_arr1d, int rows, int cols) {
    
    __shared__ float tile[TILE_HEIGHT][TILE_WIDTH];
    __shared__ float buf[SMALL_TILE_HEIGHT][TILE_WIDTH]; // buffer for down/up sampling
    __shared__ float small_tile[SMALL_TILE_HEIGHT][SMALL_TILE_WIDTH];

    int tx = threadIdx.x;
    int ty = threadIdx.y;

    for(int offset_y = 0; offset_y < TILE_HEIGHT; offset_y += BLOCK_HEIGHT) {
        for(int offset_x = 0; offset_x < TILE_WIDTH; offset_x += BLOCK_WIDTH) {
            int xidx = blockIdx.x * TILE_WIDTH + offset_x + tx;
            int yidx = blockIdx.y * TILE_HEIGHT + offset_y + ty;
            tile[offset_y + ty][offset_x + tx] = i_arr1d[yidx * cols + xidx];
        }
    }
    __syncthreads();

    // col downsample: (TILE_HEIGHT, TILE_WIDTH) -> (SMALL_TILE_HEIGHT, TILE_WIDTH)
    for(int offset_x = 0; offset_x < TILE_WIDTH; offset_x += BLOCK_WIDTH) {
        buf[2*ty][offset_x + tx] = -0.022 * tile[3*ty][offset_x + tx] + 0.974 * tile[3*ty+1][offset_x + tx] + 0.227 * tile[3*ty+2][offset_x + tx];
        buf[2*ty+1][offset_x + tx] = 0.227 * tile[3*ty][offset_x + tx] + 0.974 * tile[3*ty+1][offset_x + tx] + -0.022 * tile[3*ty+2][offset_x + tx];
    }
    __syncthreads();

    // row downsample: (SMALL_TILE_HEIGHT, TILE_WIDTH) -> (SMALL_TILE_HEIGHT, SMALL_TILE_WIDTH)
    for(int offset_y = 0; offset_y < SMALL_TILE_HEIGHT; offset_y += BLOCK_HEIGHT) {
        small_tile[offset_y + ty][2*tx] = -0.022 * buf[offset_y + ty][3*tx] + 0.974 * buf[offset_y + ty][3*tx+1] + 0.227 * buf[offset_y + ty][3*tx+2];
        small_tile[offset_y + ty][2*tx+1] = 0.227 * buf[offset_y + ty][3*tx] + 0.974 * buf[offset_y + ty][3*tx+1] + -0.022 * buf[offset_y + ty][3*tx+2];
    }
    __syncthreads();

    // row upsample: (SMALL_TILE_HEIGHT, SMALL_TILE_WIDTH) -> (SMALL_TILE_HEIGHT, TILE_WIDTH)
    for(int offset_y = 0; offset_y < SMALL_TILE_HEIGHT; offset_y += BLOCK_HEIGHT) {
        // 3*tx
        if(tx == 0)
            buf[offset_y + ty][0] = 0.927 * small_tile[offset_y + ty][0] + -0.047 * small_tile[offset_y + ty][1];
        else
            buf[offset_y + ty][3*tx] = 0.119 * small_tile[offset_y + ty][2*tx-1] + 0.927 * small_tile[offset_y + ty][2*tx]
                + -0.047 * small_tile[offset_y + ty][2*tx+1];
        // 3*tx+2
        if(tx == BLOCK_WIDTH-1)
            buf[offset_y + ty][TILE_WIDTH-1] = -0.047 * small_tile[offset_y + ty][SMALL_TILE_WIDTH-2] + 0.927 * small_tile[offset_y + ty][SMALL_TILE_WIDTH-1];
        else
            buf[offset_y + ty][3*tx+2] = -0.047 * small_tile[offset_y + ty][2*tx] + 0.927 * small_tile[offset_y + ty][2*tx+1]
                + 0.119 * small_tile[offset_y + ty][2*tx+2];
        // 3*tx+1
        if(tx == 0)
            buf[offset_y + ty][1] = 0.6 * small_tile[offset_y + ty][0] + 0.6 * small_tile[offset_y + ty][1] + -0.1 * small_tile[offset_y + ty][2];
        else if(tx == BLOCK_WIDTH-1)
            buf[offset_y + ty][TILE_WIDTH-2] = -0.1 * small_tile[offset_y + ty][SMALL_TILE_WIDTH-3] + 0.6 * small_tile[offset_y + ty][SMALL_TILE_WIDTH-2] 
                + 0.6 * small_tile[offset_y + ty][SMALL_TILE_WIDTH-1];
        else
            buf[offset_y + ty][3*tx+1] = -0.1 * small_tile[offset_y + ty][2*tx-1] + 0.6 * small_tile[offset_y + ty][2*tx]
                + 0.6 * small_tile[offset_y + ty][2*tx+1] + -0.1 * small_tile[offset_y + ty][2*tx+2];
    }
    __syncthreads();

    // col upsample: (SMALL_TILE_HEIGHT, TILE_WIDTH) -> (TILE_HEIGHT, TILE_WIDTH)
    for(int offset_x = 0; offset_x < TILE_WIDTH; offset_x += BLOCK_WIDTH) {
        int xidx = blockIdx.x * TILE_WIDTH + offset_x + tx;
        // 3*ty
        if(ty == 0) {
            int yidx = blockIdx.y * TILE_HEIGHT;
            o_arr1d[yidx * cols + xidx] = 0.927 * buf[0][offset_x + tx] + -0.047 * buf[1][offset_x + tx];
        
        }
        else {
            int yidx = blockIdx.y * TILE_HEIGHT + 3*ty;
            o_arr1d[yidx * cols + xidx] = 0.119 * buf[2*tx-1][offset_x + tx] + 0.927 * buf[2*tx][offset_x + tx]
                + -0.047 * buf[2*tx+1][offset_x + tx];
        }
        // 3*ty+2
        if(ty == BLOCK_HEIGHT-1) {
            int yidx = blockIdx.y * TILE_HEIGHT + TILE_HEIGHT-1;
            o_arr1d[yidx * cols + xidx] = -0.047 * buf[SMALL_TILE_HEIGHT-2][offset_x + tx] + 0.927 * buf[SMALL_TILE_HEIGHT-1][offset_x + tx];
        }
        else {
            int yidx = blockIdx.y * TILE_HEIGHT + 3*ty+2;
            o_arr1d[yidx * cols + xidx] = -0.047 * buf[2*ty][offset_x + tx] + 0.927 * buf[2*ty+1][offset_x + tx]
                + 0.119 * small_tile[2*ty+2][offset_x + tx];
        }
        // 3*ty+1
        if(ty == 0) {
            int yidx = blockIdx.y * TILE_HEIGHT + 1;
            o_arr1d[yidx * cols + xidx] = 0.6 * buf[0][offset_x + tx] + 0.6 * buf[1][offset_x + tx] + -0.1 * buf[2][offset_x + tx];
        }
        else if(ty == BLOCK_HEIGHT-1) {
            int yidx = blockIdx.y * TILE_HEIGHT + TILE_HEIGHT-2;
            o_arr1d[yidx * cols + xidx] = -0.1 * buf[SMALL_TILE_HEIGHT-3][offset_x + tx] + 0.6 * buf[SMALL_TILE_HEIGHT-2][offset_x + tx] 
                + 0.6 * buf[SMALL_TILE_HEIGHT-1][offset_x + tx];
        }
        else {
            int yidx = blockIdx.y * TILE_HEIGHT + 3*ty+1;
            o_arr1d[yidx * cols + xidx] = -0.1 * buf[2*ty-1][offset_x + tx] + 0.6 * buf[2*ty][offset_x + tx]
                + 0.6 * buf[2*ty+1][offset_x + tx] + -0.1 * buf[2*ty+2][offset_x + tx];
        }
    }


}

	.text
	.file	"kernel.hip"
	.globl	_Z36__device_stub__superResolutionKernelPfS_ii # -- Begin function _Z36__device_stub__superResolutionKernelPfS_ii
	.type	_Z36__device_stub__superResolutionKernelPfS_ii,@function
_Z36__device_stub__superResolutionKernelPfS_ii: # @_Z36__device_stub__superResolutionKernelPfS_ii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z21superResolutionKernelPfS_ii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z36__device_stub__superResolutionKernelPfS_ii, .Lfunc_end0-_Z36__device_stub__superResolutionKernelPfS_ii
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z21superResolutionKernelPfS_ii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z21superResolutionKernelPfS_ii,@object # @_Z21superResolutionKernelPfS_ii
	.section	.rodata,"a",@progbits
	.globl	_Z21superResolutionKernelPfS_ii
	.p2align	3, 0x0
_Z21superResolutionKernelPfS_ii:
	.quad	_Z36__device_stub__superResolutionKernelPfS_ii
	.size	_Z21superResolutionKernelPfS_ii, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z21superResolutionKernelPfS_ii"
	.size	.L__unnamed_1, 32

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z36__device_stub__superResolutionKernelPfS_ii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z21superResolutionKernelPfS_ii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z21superResolutionKernelPfS_ii ; -- Begin function _Z21superResolutionKernelPfS_ii
	.globl	_Z21superResolutionKernelPfS_ii
	.p2align	8
	.type	_Z21superResolutionKernelPfS_ii,@function
_Z21superResolutionKernelPfS_ii:        ; @_Z21superResolutionKernelPfS_ii
; %bb.0:
	s_clause 0x1
	s_load_b32 s16, s[0:1], 0x14
	s_load_b128 s[4:7], s[0:1], 0x0
	v_bfe_u32 v2, v0, 10, 10
	s_mul_i32 s15, s15, 48
	v_and_b32_e32 v3, 0x3ff, v0
	s_mulk_i32 s14, 0x60
	s_mov_b32 s1, 0
	v_add_nc_u32_e32 v1, s15, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b32_e32 v4, 2, v3
	v_mad_u32_u24 v0, 0x180, v2, v4
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v1, s16, v1
	s_lshl_b32 s0, s16, 4
	v_add3_u32 v1, v3, v1, s14
.LBB0_1:                                ; %.preheader
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_2 Depth 2
	v_mov_b32_e32 v5, v0
	s_movk_i32 s2, 0xffe0
.LBB0_2:                                ;   Parent Loop BB0_1 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_i32 s2, s2, 32
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	v_add_nc_u32_e32 v6, s2, v1
	s_cmp_gt_u32 s2, 63
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v7, 31, v6
	v_lshlrev_b64 v[6:7], 2, v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v6, vcc_lo, s6, v6
	v_add_co_ci_u32_e32 v7, vcc_lo, s7, v7, vcc_lo
	global_load_b32 v6, v[6:7], off
	s_waitcnt vmcnt(0)
	ds_store_b32 v5, v6
	v_add_nc_u32_e32 v5, 0x80, v5
	s_cbranch_scc0 .LBB0_2
; %bb.3:                                ;   in Loop: Header=BB0_1 Depth=1
	v_add_nc_u32_e32 v0, 0x1800, v0
	v_add_nc_u32_e32 v1, s0, v1
	s_add_i32 s2, s1, 16
	s_cmp_gt_u32 s1, 31
	s_mov_b32 s1, s2
	s_cbranch_scc0 .LBB0_1
; %bb.4:
	v_mad_u32_u24 v5, 0x300, v2, v4
	v_mul_u32_u24_e32 v6, 3, v2
	s_mov_b32 s0, 0xc49ba5e
	s_mov_b32 s2, 0x20c49ba
	s_mov_b32 s6, 0x4189375
	v_add_nc_u32_e32 v0, 0x4800, v5
	v_mad_u32_u24 v1, 0x180, v6, v4
	s_mov_b32 s1, 0x3fef2b02
	s_mov_b32 s3, 0xbf96872b
	s_mov_b32 s7, 0x3fcd0e56
	s_movk_i32 s8, 0xffe0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
.LBB0_5:                                ; =>This Inner Loop Header: Depth=1
	ds_load_2addr_b32 v[7:8], v1 offset1:96
	s_add_i32 s8, s8, 32
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	s_cmp_gt_u32 s8, 63
	s_waitcnt lgkmcnt(0)
	v_cvt_f64_f32_e32 v[8:9], v8
	v_cvt_f64_f32_e32 v[10:11], v7
	v_mul_f64 v[7:8], v[8:9], s[0:1]
	ds_load_b32 v9, v1 offset:768
	v_add_nc_u32_e32 v1, 0x80, v1
	s_waitcnt lgkmcnt(0)
	v_cvt_f64_f32_e32 v[12:13], v9
	v_fma_f64 v[14:15], v[10:11], s[2:3], v[7:8]
	v_fma_f64 v[7:8], v[10:11], s[6:7], v[7:8]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[9:10], v[12:13], s[6:7], v[14:15]
	v_fma_f64 v[7:8], v[12:13], s[2:3], v[7:8]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_f32_f64_e32 v9, v[9:10]
	v_cvt_f32_f64_e32 v7, v[7:8]
	ds_store_2addr_b32 v0, v9, v7 offset1:96
	v_add_nc_u32_e32 v0, 0x80, v0
	s_cbranch_scc0 .LBB0_5
; %bb.6:
	v_lshlrev_b32_e32 v8, 1, v3
	v_mul_u32_u24_e32 v7, 3, v3
	s_mov_b32 s0, 0xc49ba5e
	s_mov_b32 s2, 0x20c49ba
	s_mov_b32 s6, 0x4189375
	v_lshlrev_b32_e32 v9, 2, v8
	s_mov_b32 s1, 0x3fef2b02
	s_mov_b32 s3, 0xbf96872b
	s_mov_b32 s7, 0x3fcd0e56
	s_mov_b32 s9, 0
	s_mov_b32 s8, -1
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
.LBB0_7:                                ; =>This Inner Loop Header: Depth=1
	v_add_nc_u32_e32 v16, s9, v2
	s_mov_b32 s9, 16
	s_and_not1_b32 vcc_lo, exec_lo, s8
	s_mov_b32 s8, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v0, 0x180, v16
	v_lshl_add_u32 v10, v7, 2, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_add_nc_u32_e32 v0, 0x4800, v10
	ds_load_2addr_b32 v[0:1], v0 offset1:1
	ds_load_b32 v12, v10 offset:18440
	s_waitcnt lgkmcnt(1)
	v_cvt_f64_f32_e32 v[10:11], v1
	v_cvt_f64_f32_e32 v[0:1], v0
	s_waitcnt lgkmcnt(0)
	v_cvt_f64_f32_e32 v[12:13], v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[10:11], v[10:11], s[0:1]
	v_fma_f64 v[14:15], v[0:1], s[2:3], v[10:11]
	v_fma_f64 v[0:1], v[0:1], s[6:7], v[10:11]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[10:11], v[12:13], s[6:7], v[14:15]
	v_fma_f64 v[0:1], v[12:13], s[2:3], v[0:1]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_f32_f64_e32 v10, v[10:11]
	v_cvt_f32_f64_e32 v11, v[0:1]
	v_lshl_add_u32 v0, v16, 8, v9
	ds_store_b64 v0, v[10:11] offset:30720
	s_cbranch_vccz .LBB0_7
; %bb.8:
	v_add_nc_u32_e32 v10, 2, v7
	v_cmp_ne_u32_e64 s0, 0, v3
	v_cmp_ne_u32_e64 s1, 31, v3
	v_add_nc_u32_e32 v11, -1, v8
	s_mov_b32 s2, 0xe76c8b44
	s_mov_b32 s6, 0xb4395810
	s_mov_b32 s8, 0x4dd2f1aa
	s_mov_b32 s10, 0x9999999a
	s_mov_b32 s12, 0x33333333
	s_mov_b32 s3, 0x3feda9fb
	s_mov_b32 s7, 0x3fbe76c8
	s_mov_b32 s9, 0xbfa81062
	s_mov_b32 s11, 0xbfb99999
	s_mov_b32 s13, 0x3fe33333
	s_mov_b32 s18, 0
	s_mov_b32 s17, -1
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
.LBB0_9:                                ; =>This Inner Loop Header: Depth=1
	v_add_nc_u32_e32 v13, s18, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_mul_lo_u32 v12, 0x180, v13
	s_and_saveexec_b32 s18, s0
	s_xor_b32 s18, exec_lo, s18
	s_cbranch_execz .LBB0_11
; %bb.10:                               ;   in Loop: Header=BB0_9 Depth=1
	v_lshl_add_u32 v14, v13, 8, 0x7800
	s_delay_alu instid0(VALU_DEP_1)
	v_lshl_add_u32 v0, v11, 2, v14
	v_lshl_add_u32 v14, v8, 2, v14
	ds_load_2addr_b32 v[0:1], v0 offset1:1
	ds_load_b32 v16, v14 offset:4
	s_waitcnt lgkmcnt(1)
	v_cvt_f64_f32_e32 v[14:15], v1
	v_cvt_f64_f32_e32 v[0:1], v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[14:15], v[14:15], s[2:3]
	v_fma_f64 v[0:1], v[0:1], s[6:7], v[14:15]
	s_waitcnt lgkmcnt(0)
	v_cvt_f64_f32_e32 v[14:15], v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[0:1], v[14:15], s[8:9], v[0:1]
	v_cvt_f32_f64_e32 v0, v[0:1]
	v_lshl_add_u32 v1, v7, 2, v12
	ds_store_b32 v1, v0 offset:18432
.LBB0_11:                               ; %Flow358
                                        ;   in Loop: Header=BB0_9 Depth=1
	s_or_saveexec_b32 s18, s18
	v_lshlrev_b32_e32 v14, 8, v13
	s_xor_b32 exec_lo, exec_lo, s18
	s_cbranch_execz .LBB0_13
; %bb.12:                               ;   in Loop: Header=BB0_9 Depth=1
	ds_load_b64 v[0:1], v14 offset:30720
	s_waitcnt lgkmcnt(0)
	v_cvt_f64_f32_e32 v[15:16], v1
	v_cvt_f64_f32_e32 v[0:1], v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[15:16], v[15:16], s[8:9]
	v_fma_f64 v[0:1], v[0:1], s[2:3], v[15:16]
	s_delay_alu instid0(VALU_DEP_1)
	v_cvt_f32_f64_e32 v0, v[0:1]
	ds_store_b32 v12, v0 offset:18432
.LBB0_13:                               ;   in Loop: Header=BB0_9 Depth=1
	s_or_b32 exec_lo, exec_lo, s18
                                        ; implicit-def: $vgpr0_vgpr1
	s_and_saveexec_b32 s18, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s18, exec_lo, s18
	s_cbranch_execz .LBB0_15
; %bb.14:                               ;   in Loop: Header=BB0_9 Depth=1
	v_lshl_add_u32 v15, v13, 8, v9
	ds_load_b64 v[0:1], v15 offset:30720
	ds_load_b32 v17, v15 offset:30728
	s_waitcnt lgkmcnt(1)
	v_cvt_f64_f32_e32 v[15:16], v0
	v_cvt_f64_f32_e32 v[0:1], v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[15:16], v[15:16], s[8:9]
	v_fma_f64 v[0:1], v[0:1], s[2:3], v[15:16]
	s_waitcnt lgkmcnt(0)
	v_cvt_f64_f32_e32 v[15:16], v17
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[0:1], v[15:16], s[6:7], v[0:1]
.LBB0_15:                               ; %Flow357
                                        ;   in Loop: Header=BB0_9 Depth=1
	s_or_saveexec_b32 s18, s18
	v_mov_b32_e32 v15, v10
	s_xor_b32 exec_lo, exec_lo, s18
	s_cbranch_execz .LBB0_17
; %bb.16:                               ;   in Loop: Header=BB0_9 Depth=1
	ds_load_b64 v[0:1], v14 offset:30968
	s_waitcnt lgkmcnt(0)
	v_cvt_f64_f32_e32 v[15:16], v0
	v_cvt_f64_f32_e32 v[0:1], v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[15:16], v[15:16], s[8:9]
	v_fma_f64 v[0:1], v[0:1], s[2:3], v[15:16]
	v_mov_b32_e32 v15, 0x5f
.LBB0_17:                               ;   in Loop: Header=BB0_9 Depth=1
	s_or_b32 exec_lo, exec_lo, s18
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_f32_f64_e32 v0, v[0:1]
	v_lshl_add_u32 v1, v15, 2, v12
	ds_store_b32 v1, v0 offset:18432
	s_and_saveexec_b32 s18, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s18, exec_lo, s18
	s_cbranch_execz .LBB0_23
; %bb.18:                               ;   in Loop: Header=BB0_9 Depth=1
	s_and_saveexec_b32 s19, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s19, exec_lo, s19
	s_cbranch_execz .LBB0_20
; %bb.19:                               ;   in Loop: Header=BB0_9 Depth=1
	v_lshl_add_u32 v13, v13, 8, 0x7800
	s_delay_alu instid0(VALU_DEP_1)
	v_lshl_add_u32 v0, v11, 2, v13
	v_lshl_add_u32 v13, v8, 2, v13
	ds_load_2addr_b32 v[0:1], v0 offset1:1
	ds_load_2addr_b32 v[13:14], v13 offset0:1 offset1:2
	s_waitcnt lgkmcnt(1)
	v_cvt_f64_f32_e32 v[15:16], v0
	v_cvt_f64_f32_e32 v[0:1], v1
	s_waitcnt lgkmcnt(0)
	v_cvt_f64_f32_e32 v[17:18], v13
	v_cvt_f64_f32_e32 v[13:14], v14
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[15:16], v[15:16], s[10:11]
	v_fma_f64 v[0:1], v[0:1], s[12:13], v[15:16]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[0:1], v[17:18], s[12:13], v[0:1]
	v_fma_f64 v[0:1], v[13:14], s[10:11], v[0:1]
                                        ; implicit-def: $vgpr14
	s_delay_alu instid0(VALU_DEP_1)
	v_cvt_f32_f64_e32 v0, v[0:1]
	v_lshl_add_u32 v1, v7, 2, v12
                                        ; implicit-def: $vgpr12
	ds_store_b32 v1, v0 offset:18436
.LBB0_20:                               ; %Flow353
                                        ;   in Loop: Header=BB0_9 Depth=1
	s_and_not1_saveexec_b32 s19, s19
	s_cbranch_execz .LBB0_22
; %bb.21:                               ;   in Loop: Header=BB0_9 Depth=1
	v_add_nc_u32_e32 v0, 0x78f4, v14
	ds_load_2addr_b32 v[0:1], v0 offset1:1
	ds_load_b32 v15, v14 offset:30972
	s_waitcnt lgkmcnt(1)
	v_cvt_f64_f32_e32 v[13:14], v0
	v_cvt_f64_f32_e32 v[0:1], v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[13:14], v[13:14], s[10:11]
	v_fma_f64 v[0:1], v[0:1], s[12:13], v[13:14]
	s_waitcnt lgkmcnt(0)
	v_cvt_f64_f32_e32 v[13:14], v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[0:1], v[13:14], s[12:13], v[0:1]
	v_cvt_f32_f64_e32 v0, v[0:1]
	ds_store_b32 v12, v0 offset:18808
.LBB0_22:                               ; %Flow354
                                        ;   in Loop: Header=BB0_9 Depth=1
	s_or_b32 exec_lo, exec_lo, s19
                                        ; implicit-def: $vgpr14
                                        ; implicit-def: $vgpr12
.LBB0_23:                               ; %Flow356
                                        ;   in Loop: Header=BB0_9 Depth=1
	s_and_not1_saveexec_b32 s18, s18
	s_cbranch_execz .LBB0_25
; %bb.24:                               ;   in Loop: Header=BB0_9 Depth=1
	ds_load_b96 v[13:15], v14 offset:30720
	s_waitcnt lgkmcnt(0)
	v_cvt_f64_f32_e32 v[0:1], v14
	v_cvt_f64_f32_e32 v[13:14], v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[0:1], v[0:1], s[12:13]
	v_fma_f64 v[0:1], v[13:14], s[12:13], v[0:1]
	v_cvt_f64_f32_e32 v[13:14], v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[0:1], v[13:14], s[10:11], v[0:1]
	v_cvt_f32_f64_e32 v0, v[0:1]
	ds_store_b32 v12, v0 offset:18436
.LBB0_25:                               ;   in Loop: Header=BB0_9 Depth=1
	s_or_b32 exec_lo, exec_lo, s18
	s_xor_b32 s17, s17, -1
	s_mov_b32 s18, 16
	s_and_b32 vcc_lo, exec_lo, s17
	s_mov_b32 s17, 0
	s_cbranch_vccz .LBB0_9
; %bb.26:
	v_add_nc_u32_e32 v6, s15, v6
	v_cmp_ne_u32_e32 vcc_lo, 0, v2
	v_cmp_ne_u32_e64 s0, 15, v2
	v_lshl_add_u32 v9, v2, 9, v4
	v_mul_u32_u24_e32 v10, 0x304, v3
	v_add_nc_u32_e32 v7, 2, v6
	v_add_nc_u32_e32 v8, 1, v6
	v_add_nc_u32_e32 v11, s14, v3
	s_mov_b32 s2, 0xe76c8b44
	s_mov_b32 s6, 0xb4395810
	s_mov_b32 s8, 0x4dd2f1aa
	s_mov_b32 s10, 0x9999999a
	s_mov_b32 s12, 0x33333333
	s_add_i32 s18, s15, 47
	s_mov_b32 s3, 0x3feda9fb
	s_mov_b32 s7, 0x3fbe76c8
	s_mov_b32 s9, 0xbfa81062
	s_mov_b32 s11, 0xbfb99999
	s_mov_b32 s13, 0x3fe33333
	s_add_i32 s14, s15, 46
	s_or_b32 s19, s15, 1
	s_mov_b32 s20, 0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
.LBB0_27:                               ; =>This Inner Loop Header: Depth=1
                                        ; implicit-def: $vgpr0_vgpr1
                                        ; implicit-def: $vgpr2
	s_and_saveexec_b32 s1, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s1, exec_lo, s1
	s_cbranch_execz .LBB0_29
; %bb.28:                               ;   in Loop: Header=BB0_27 Depth=1
	v_add_nc_u32_e32 v14, s17, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v0, 0x4600, v14
	ds_load_2addr_b32 v[0:1], v0 offset0:32 offset1:128
	s_waitcnt lgkmcnt(0)
	v_cvt_f64_f32_e32 v[1:2], v1
	v_cvt_f64_f32_e32 v[12:13], v0
	v_mul_f64 v[0:1], v[1:2], s[2:3]
	v_add_nc_u32_e32 v2, 0x4980, v14
	s_delay_alu instid0(VALU_DEP_2)
	v_fma_f64 v[0:1], v[12:13], s[6:7], v[0:1]
.LBB0_29:                               ; %Flow352
                                        ;   in Loop: Header=BB0_27 Depth=1
	s_or_saveexec_b32 s1, s1
	v_dual_mov_b32 v13, v6 :: v_dual_add_nc_u32 v12, s17, v4
	s_xor_b32 exec_lo, exec_lo, s1
	s_cbranch_execz .LBB0_31
; %bb.30:                               ;   in Loop: Header=BB0_27 Depth=1
	ds_load_b32 v0, v12 offset:18432
	v_dual_mov_b32 v13, s15 :: v_dual_add_nc_u32 v2, s20, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_lshl_add_u32 v2, v2, 2, 0x4980
	s_waitcnt lgkmcnt(0)
	v_cvt_f64_f32_e32 v[0:1], v0
	v_mul_f64 v[0:1], v[0:1], s[2:3]
.LBB0_31:                               ;   in Loop: Header=BB0_27 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	ds_load_b32 v2, v2
	s_waitcnt lgkmcnt(0)
	v_cvt_f64_f32_e32 v[14:15], v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[0:1], v[14:15], s[8:9], v[0:1]
	v_cvt_f32_f64_e32 v14, v[0:1]
	v_add_nc_u32_e32 v0, s20, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, v13, s16, v[0:1]
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, s1, s4, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_add_co_ci_u32_e64 v2, s1, s5, v2, s1
	global_store_b32 v[1:2], v14, off
                                        ; implicit-def: $vgpr1_vgpr2
	s_and_saveexec_b32 s1, s0
	s_xor_b32 s1, exec_lo, s1
	s_cbranch_execz .LBB0_33
; %bb.32:                               ;   in Loop: Header=BB0_27 Depth=1
	v_add_nc_u32_e32 v1, s17, v5
	v_add_nc_u32_e32 v15, s17, v9
	s_delay_alu instid0(VALU_DEP_2)
	v_add_nc_u32_e32 v1, 0x4800, v1
	ds_load_b32 v15, v15 offset:31232
	ds_load_2addr_b32 v[1:2], v1 offset1:96
	s_waitcnt lgkmcnt(0)
	v_cvt_f64_f32_e32 v[13:14], v1
	v_cvt_f64_f32_e32 v[1:2], v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[13:14], v[13:14], s[8:9]
	v_fma_f64 v[1:2], v[1:2], s[2:3], v[13:14]
	v_cvt_f64_f32_e32 v[13:14], v15
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[1:2], v[13:14], s[6:7], v[1:2]
.LBB0_33:                               ; %Flow351
                                        ;   in Loop: Header=BB0_27 Depth=1
	s_or_saveexec_b32 s1, s1
	v_mov_b32_e32 v13, v7
	s_xor_b32 exec_lo, exec_lo, s1
	s_cbranch_execz .LBB0_35
; %bb.34:                               ;   in Loop: Header=BB0_27 Depth=1
	v_add_nc_u32_e32 v1, 0x7400, v12
	ds_load_2addr_b32 v[1:2], v1 offset0:64 offset1:160
	s_waitcnt lgkmcnt(0)
	v_cvt_f64_f32_e32 v[13:14], v1
	v_cvt_f64_f32_e32 v[1:2], v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[13:14], v[13:14], s[8:9]
	v_fma_f64 v[1:2], v[1:2], s[2:3], v[13:14]
	v_mov_b32_e32 v13, s18
.LBB0_35:                               ;   in Loop: Header=BB0_27 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_f32_f64_e32 v14, v[1:2]
	v_mad_u64_u32 v[1:2], null, v13, s16, v[0:1]
                                        ; implicit-def: $vgpr13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v2, 31, v1
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v1, s1, s4, v1
	v_add_co_ci_u32_e64 v2, s1, s5, v2, s1
	global_store_b32 v[1:2], v14, off
                                        ; implicit-def: $vgpr1_vgpr2
	s_and_saveexec_b32 s1, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s1, exec_lo, s1
	s_cbranch_execz .LBB0_41
; %bb.36:                               ;   in Loop: Header=BB0_27 Depth=1
                                        ; implicit-def: $vgpr1_vgpr2
	s_and_saveexec_b32 s21, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s21, exec_lo, s21
	s_cbranch_execz .LBB0_38
; %bb.37:                               ;   in Loop: Header=BB0_27 Depth=1
	v_add_nc_u32_e32 v14, s17, v5
	s_delay_alu instid0(VALU_DEP_1)
	v_add_nc_u32_e32 v1, 0x4600, v14
	v_add_nc_u32_e32 v14, 0x4800, v14
	ds_load_2addr_b32 v[1:2], v1 offset0:32 offset1:128
	ds_load_2addr_b32 v[14:15], v14 offset0:96 offset1:192
	s_waitcnt lgkmcnt(1)
	v_cvt_f64_f32_e32 v[12:13], v1
	v_cvt_f64_f32_e32 v[1:2], v2
	s_waitcnt lgkmcnt(0)
	v_cvt_f64_f32_e32 v[16:17], v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[12:13], v[12:13], s[10:11]
	v_fma_f64 v[1:2], v[1:2], s[12:13], v[12:13]
	v_cvt_f64_f32_e32 v[12:13], v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[1:2], v[16:17], s[12:13], v[1:2]
	v_fma_f64 v[1:2], v[12:13], s[10:11], v[1:2]
                                        ; implicit-def: $vgpr12
.LBB0_38:                               ; %Flow
                                        ;   in Loop: Header=BB0_27 Depth=1
	s_or_saveexec_b32 s21, s21
	v_mov_b32_e32 v13, v8
	s_xor_b32 exec_lo, exec_lo, s21
	s_cbranch_execz .LBB0_40
; %bb.39:                               ;   in Loop: Header=BB0_27 Depth=1
	v_add_nc_u32_e32 v1, 0x7200, v12
	ds_load_b32 v12, v12 offset:30336
	ds_load_2addr_b32 v[1:2], v1 offset0:96 offset1:192
	s_waitcnt lgkmcnt(0)
	v_cvt_f64_f32_e32 v[13:14], v1
	v_cvt_f64_f32_e32 v[1:2], v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[13:14], v[13:14], s[10:11]
	v_fma_f64 v[1:2], v[1:2], s[12:13], v[13:14]
	v_cvt_f64_f32_e32 v[12:13], v12
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[1:2], v[12:13], s[12:13], v[1:2]
	v_mov_b32_e32 v13, s14
.LBB0_40:                               ; %Flow348
                                        ;   in Loop: Header=BB0_27 Depth=1
	s_or_b32 exec_lo, exec_lo, s21
                                        ; implicit-def: $vgpr12
.LBB0_41:                               ; %Flow350
                                        ;   in Loop: Header=BB0_27 Depth=1
	s_and_not1_saveexec_b32 s1, s1
	s_cbranch_execz .LBB0_43
; %bb.42:                               ;   in Loop: Header=BB0_27 Depth=1
	v_add_nc_u32_e32 v1, 0x4800, v12
	ds_load_b32 v12, v12 offset:19200
	ds_load_2addr_b32 v[1:2], v1 offset1:96
	s_waitcnt lgkmcnt(0)
	v_cvt_f64_f32_e32 v[13:14], v2
	v_cvt_f64_f32_e32 v[1:2], v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[13:14], v[13:14], s[12:13]
	v_fma_f64 v[1:2], v[1:2], s[12:13], v[13:14]
	v_cvt_f64_f32_e32 v[12:13], v12
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[1:2], v[12:13], s[10:11], v[1:2]
	v_mov_b32_e32 v13, s19
.LBB0_43:                               ;   in Loop: Header=BB0_27 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_f32_f64_e32 v12, v[1:2]
	v_mad_u64_u32 v[1:2], null, v13, s16, v[0:1]
	s_addk_i32 s17, 0x80
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v2, 31, v1
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v0, s1, s4, v0
	v_add_co_ci_u32_e64 v1, s1, s5, v1, s1
	s_add_i32 s1, s20, 32
	s_cmp_gt_u32 s20, 63
	s_mov_b32 s20, s1
	global_store_b32 v[0:1], v12, off
	s_cbranch_scc0 .LBB0_27
; %bb.44:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z21superResolutionKernelPfS_ii
		.amdhsa_group_segment_fixed_size 38912
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 24
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 19
		.amdhsa_next_free_sgpr 22
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z21superResolutionKernelPfS_ii, .Lfunc_end0-_Z21superResolutionKernelPfS_ii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 2656
; NumSgprs: 24
; NumVgprs: 19
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 38912 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 24
; NumVGPRsForWavesPerEU: 19
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
    .group_segment_fixed_size: 38912
    .kernarg_segment_align: 8
    .kernarg_segment_size: 24
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z21superResolutionKernelPfS_ii
    .private_segment_fixed_size: 0
    .sgpr_count:     24
    .sgpr_spill_count: 0
    .symbol:         _Z21superResolutionKernelPfS_ii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     19
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
