#include<stdio.h>
#include<cstdlib>
#include<iostream>
#include<cuda.h>

__global__ void Betweenness(int* R,int* C,int s,int* d,int* sigma,int n,float* delta)
{  //printf("dfmk");

    int idx = threadIdx.x;
	int w,v;
    for(v=idx; v<n; v+=blockDim.x)
    {
      if(v == s)
      {
        d[v] = 0;
        sigma[v] = 1;
      }
      else
      {
        d[v] = INT_MAX;
        sigma[v] = 0;
      }
		delta[v]=0;
    }
    __shared__ int current_depth;
    __shared__ bool done;

    if(idx == 0)
    {  
      done = false;
      current_depth = 0;
    }
    __syncthreads();

    //Calculate the number of shortest paths and the 
    // distance from s (the root) to each vertex
    while(!done)
    {
      __syncthreads();
      done = true;
      __syncthreads();

      for(v=idx; v<n; v+=blockDim.x) //For each vertex...
      {
        if(d[v] == current_depth)
        {
          for(int r=R[v]; r<R[v+1]; r++) //For each neighbor of v
          {
            int w = C[r];
            if(d[w] == INT_MAX)
            {
              d[w] = d[v] + 1;
              done = false;
            }
            if(d[w] == (d[v] + 1))
            {
              atomicAdd(&sigma[w],sigma[v]);
            }
          }
        }
      }
      __syncthreads();
      
      if(idx == 0){
        current_depth++;
      }
    }
	__syncthreads();
	for(v=idx;v<n;v+=blockDim.x)
	{
		float ds = 0;
		for(int r=R[v]; r<R[v+1]; r++)
		{
			w=C[r];
			if(d[w]+1==d[v]){
				ds=ds+(float)sigma[v]*(1+delta[w])/sigma[w];
				printf("%d ",(float)sigma[v]*(1+delta[w])/sigma[w]);}
		}
		delta[v]=ds;
	}
	__syncthreads();
}

	.file	"tmpxft_003b675f_00000000-6_pavan.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3637:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3637:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z41__device_stub__Z11BetweennessPiS_iS_S_iPfPiS_iS_S_iPf
	.type	_Z41__device_stub__Z11BetweennessPiS_iS_S_iPfPiS_iS_S_iPf, @function
_Z41__device_stub__Z11BetweennessPiS_iS_S_iPfPiS_iS_S_iPf:
.LFB3659:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	192(%rsp), %rax
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movl	%edx, 28(%rsp)
	leaq	48(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	56(%rsp), %rcx
	movq	%r8, 8(%rsp)
	movl	%r9d, 24(%rsp)
	movq	%rax, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 112(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	28(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 152(%rsp)
	movq	%rsp, %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	56(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z11BetweennessPiS_iS_S_iPf(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 208
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L2:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3659:
	.size	_Z41__device_stub__Z11BetweennessPiS_iS_S_iPfPiS_iS_S_iPf, .-_Z41__device_stub__Z11BetweennessPiS_iS_S_iPfPiS_iS_S_iPf
	.globl	_Z11BetweennessPiS_iS_S_iPf
	.type	_Z11BetweennessPiS_iS_S_iPf, @function
_Z11BetweennessPiS_iS_S_iPf:
.LFB3660:
	.cfi_startproc
	endbr64
	jmp	_Z41__device_stub__Z11BetweennessPiS_iS_S_iPfPiS_iS_S_iPf
	.cfi_endproc
.LFE3660:
	.size	_Z11BetweennessPiS_iS_S_iPf, .-_Z11BetweennessPiS_iS_S_iPf
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z11BetweennessPiS_iS_S_iPf"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3662:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z11BetweennessPiS_iS_S_iPf(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3662:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include<stdio.h>
#include<cstdlib>
#include<iostream>
#include<hip/hip_runtime.h>

__global__ void Betweenness(int* R,int* C,int s,int* d,int* sigma,int n,float* delta)
{  //printf("dfmk");

    int idx = threadIdx.x;
	int w,v;
    for(v=idx; v<n; v+=blockDim.x)
    {
      if(v == s)
      {
        d[v] = 0;
        sigma[v] = 1;
      }
      else
      {
        d[v] = INT_MAX;
        sigma[v] = 0;
      }
		delta[v]=0;
    }
    __shared__ int current_depth;
    __shared__ bool done;

    if(idx == 0)
    {  
      done = false;
      current_depth = 0;
    }
    __syncthreads();

    //Calculate the number of shortest paths and the 
    // distance from s (the root) to each vertex
    while(!done)
    {
      __syncthreads();
      done = true;
      __syncthreads();

      for(v=idx; v<n; v+=blockDim.x) //For each vertex...
      {
        if(d[v] == current_depth)
        {
          for(int r=R[v]; r<R[v+1]; r++) //For each neighbor of v
          {
            int w = C[r];
            if(d[w] == INT_MAX)
            {
              d[w] = d[v] + 1;
              done = false;
            }
            if(d[w] == (d[v] + 1))
            {
              atomicAdd(&sigma[w],sigma[v]);
            }
          }
        }
      }
      __syncthreads();
      
      if(idx == 0){
        current_depth++;
      }
    }
	__syncthreads();
	for(v=idx;v<n;v+=blockDim.x)
	{
		float ds = 0;
		for(int r=R[v]; r<R[v+1]; r++)
		{
			w=C[r];
			if(d[w]+1==d[v]){
				ds=ds+(float)sigma[v]*(1+delta[w])/sigma[w];
				printf("%d ",(float)sigma[v]*(1+delta[w])/sigma[w]);}
		}
		delta[v]=ds;
	}
	__syncthreads();
}

	.text
	.file	"pavan.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z26__device_stub__BetweennessPiS_iS_S_iPf # -- Begin function _Z26__device_stub__BetweennessPiS_iS_S_iPf
	.type	_Z26__device_stub__BetweennessPiS_iS_S_iPf,@function
_Z26__device_stub__BetweennessPiS_iS_S_iPf: # @_Z26__device_stub__BetweennessPiS_iS_S_iPf
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	40(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	32(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	8(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z11BetweennessPiS_iS_S_iPf, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z26__device_stub__BetweennessPiS_iS_S_iPf, .Lfunc_end0-_Z26__device_stub__BetweennessPiS_iS_S_iPf
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z11BetweennessPiS_iS_S_iPf, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z11BetweennessPiS_iS_S_iPf,@object # @_Z11BetweennessPiS_iS_S_iPf
	.section	.rodata,"a",@progbits
	.globl	_Z11BetweennessPiS_iS_S_iPf
	.p2align	3, 0x0
_Z11BetweennessPiS_iS_S_iPf:
	.quad	_Z26__device_stub__BetweennessPiS_iS_S_iPf
	.size	_Z11BetweennessPiS_iS_S_iPf, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z11BetweennessPiS_iS_S_iPf"
	.size	.L__unnamed_1, 28

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z26__device_stub__BetweennessPiS_iS_S_iPf
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z11BetweennessPiS_iS_S_iPf
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z11BetweennessPiS_iS_S_iPf ; -- Begin function _Z11BetweennessPiS_iS_S_iPf
	.globl	_Z11BetweennessPiS_iS_S_iPf
	.p2align	8
	.type	_Z11BetweennessPiS_iS_S_iPf,@function
_Z11BetweennessPiS_iS_S_iPf:            ; @_Z11BetweennessPiS_iS_S_iPf
; %bb.0:
	s_clause 0x2
	s_load_b32 s28, s[0:1], 0x28
	s_load_b128 s[8:11], s[0:1], 0x18
	s_load_b64 s[16:17], s[0:1], 0x30
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_i32_e64 s2, s28, v0
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s14, s2
	s_cbranch_execz .LBB0_7
; %bb.1:                                ; %.lr.ph
	s_clause 0x1
	s_load_b32 s4, s[0:1], 0x10
	s_load_b32 s3, s[0:1], 0x44
	v_bfrev_b32_e32 v3, -2
	v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v5, 1
	v_mov_b32_e32 v1, v0
	s_mov_b32 s15, 0
	s_waitcnt lgkmcnt(0)
	s_ashr_i32 s5, s4, 31
	s_delay_alu instid0(SALU_CYCLE_1)
	s_lshl_b64 s[12:13], s[4:5], 2
	s_and_b32 s5, s3, 0xffff
	s_add_u32 s6, s8, s12
	s_addc_u32 s7, s9, s13
	s_add_u32 s12, s10, s12
	s_addc_u32 s13, s11, s13
.LBB0_2:                                ; =>This Inner Loop Header: Depth=1
	v_ashrrev_i32_e32 v2, 31, v1
	s_mov_b32 s3, exec_lo
	v_cmpx_ne_u32_e64 s4, v1
	s_xor_b32 s3, exec_lo, s3
	s_cbranch_execz .LBB0_4
; %bb.3:                                ;   in Loop: Header=BB0_2 Depth=1
	v_lshlrev_b64 v[6:7], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v8, vcc_lo, s8, v6
	v_add_co_ci_u32_e32 v9, vcc_lo, s9, v7, vcc_lo
	v_add_co_u32 v6, vcc_lo, s10, v6
	v_add_co_ci_u32_e32 v7, vcc_lo, s11, v7, vcc_lo
	global_store_b32 v[8:9], v3, off
	global_store_b32 v[6:7], v4, off
.LBB0_4:                                ; %Flow470
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_and_not1_saveexec_b32 s3, s3
; %bb.5:                                ;   in Loop: Header=BB0_2 Depth=1
	s_clause 0x1
	global_store_b32 v4, v4, s[6:7]
	global_store_b32 v4, v5, s[12:13]
; %bb.6:                                ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s3
	v_lshlrev_b64 v[6:7], 2, v[1:2]
	v_add_nc_u32_e32 v1, s5, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_le_i32_e32 vcc_lo, s28, v1
	v_add_co_u32 v6, s3, s16, v6
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v7, s3, s17, v7, s3
	s_or_b32 s15, vcc_lo, s15
	global_store_b32 v[6:7], v4, off
	s_and_not1_b32 exec_lo, exec_lo, s15
	s_cbranch_execnz .LBB0_2
.LBB0_7:                                ; %Flow473
	s_or_b32 exec_lo, exec_lo, s14
	v_cmp_eq_u32_e64 s3, 0, v0
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s4, s3
	s_cbranch_execz .LBB0_9
; %bb.8:
	v_mov_b32_e32 v1, 0
	ds_store_b8 v1, v1 offset:4
	ds_store_b32 v1, v1
.LBB0_9:
	s_or_b32 exec_lo, exec_lo, s4
	v_mov_b32_e32 v15, 0
	s_waitcnt lgkmcnt(0)
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_load_b128 s[12:15], s[0:1], 0x0
	ds_load_u8 v1, v15 offset:4
	s_waitcnt lgkmcnt(0)
	v_cmp_ne_u16_e32 vcc_lo, 0, v1
	s_cbranch_vccnz .LBB0_25
; %bb.10:                               ; %.lr.ph122
	v_mov_b32_e32 v16, 1
	s_add_u32 s6, s0, 56
	s_addc_u32 s7, s1, 0
.LBB0_11:                               ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_13 Depth 2
                                        ;       Child Loop BB0_16 Depth 3
	s_barrier
	buffer_gl0_inv
	ds_store_b8 v15, v16 offset:4
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s5, s2
	s_cbranch_execz .LBB0_22
; %bb.12:                               ; %.lr.ph118
                                        ;   in Loop: Header=BB0_11 Depth=1
	s_load_b32 s4, s[6:7], 0xc
	ds_load_b32 v17, v15
	v_mov_b32_e32 v1, v0
	s_mov_b32 s19, 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s18, s4, 0xffff
.LBB0_13:                               ;   Parent Loop BB0_11 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB0_16 Depth 3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v2, 31, v1
	s_mov_b32 s20, exec_lo
	v_lshlrev_b64 v[8:9], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s8, v8
	v_add_co_ci_u32_e32 v3, vcc_lo, s9, v9, vcc_lo
	global_load_b32 v4, v[2:3], off
	s_waitcnt vmcnt(0)
	v_cmpx_eq_u32_e64 v4, v17
	s_cbranch_execz .LBB0_21
; %bb.14:                               ;   in Loop: Header=BB0_13 Depth=2
	v_add_co_u32 v4, vcc_lo, s12, v8
	v_add_co_ci_u32_e32 v5, vcc_lo, s13, v9, vcc_lo
	global_load_b64 v[6:7], v[4:5], off
	s_waitcnt vmcnt(0)
	v_cmp_lt_i32_e32 vcc_lo, v6, v7
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_21
; %bb.15:                               ; %.lr.ph115
                                        ;   in Loop: Header=BB0_13 Depth=2
	v_ashrrev_i32_e32 v7, 31, v6
	s_mov_b32 s21, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[10:11], 2, v[6:7]
	v_add_co_u32 v7, vcc_lo, s10, v8
	v_add_co_ci_u32_e32 v8, vcc_lo, s11, v9, vcc_lo
	v_add_co_u32 v9, vcc_lo, s14, v10
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v10, vcc_lo, s15, v11, vcc_lo
.LBB0_16:                               ;   Parent Loop BB0_11 Depth=1
                                        ;     Parent Loop BB0_13 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	global_load_b32 v11, v[9:10], off
	s_mov_b32 s4, exec_lo
	s_waitcnt vmcnt(0)
	v_ashrrev_i32_e32 v12, 31, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[11:12], 2, v[11:12]
	v_add_co_u32 v13, vcc_lo, s8, v11
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v14, vcc_lo, s9, v12, vcc_lo
	s_clause 0x1
	global_load_b32 v18, v[13:14], off
	global_load_b32 v19, v[2:3], off
	s_waitcnt vmcnt(1)
	v_cmpx_eq_u32_e32 0x7fffffff, v18
	s_cbranch_execz .LBB0_18
; %bb.17:                               ;   in Loop: Header=BB0_16 Depth=3
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v18, 1, v19
	ds_store_b8 v15, v15 offset:4
	global_store_b32 v[13:14], v18, off
	global_load_b32 v19, v[2:3], off
.LBB0_18:                               ;   in Loop: Header=BB0_16 Depth=3
	s_or_b32 exec_lo, exec_lo, s4
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v13, 1, v19
	s_mov_b32 s4, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e64 v18, v13
	s_cbranch_execz .LBB0_20
; %bb.19:                               ;   in Loop: Header=BB0_16 Depth=3
	global_load_b32 v13, v[7:8], off
	v_add_co_u32 v11, vcc_lo, s10, v11
	v_add_co_ci_u32_e32 v12, vcc_lo, s11, v12, vcc_lo
	s_waitcnt vmcnt(0)
	global_atomic_add_u32 v[11:12], v13, off
.LBB0_20:                               ;   in Loop: Header=BB0_16 Depth=3
	s_or_b32 exec_lo, exec_lo, s4
	global_load_b32 v11, v[4:5], off offset:4
	v_add_nc_u32_e32 v6, 1, v6
	v_add_co_u32 v9, s4, v9, 4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v10, s4, 0, v10, s4
	s_waitcnt vmcnt(0)
	v_cmp_ge_i32_e32 vcc_lo, v6, v11
	s_or_b32 s21, vcc_lo, s21
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s21
	s_cbranch_execnz .LBB0_16
.LBB0_21:                               ; %.loopexit
                                        ;   in Loop: Header=BB0_13 Depth=2
	s_or_b32 exec_lo, exec_lo, s20
	v_add_nc_u32_e32 v1, s18, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_le_i32_e32 vcc_lo, s28, v1
	s_or_b32 s19, vcc_lo, s19
	s_and_not1_b32 exec_lo, exec_lo, s19
	s_cbranch_execnz .LBB0_13
.LBB0_22:                               ; %Flow465
                                        ;   in Loop: Header=BB0_11 Depth=1
	s_or_b32 exec_lo, exec_lo, s5
	s_waitcnt lgkmcnt(0)
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s4, s3
	s_cbranch_execz .LBB0_24
; %bb.23:                               ;   in Loop: Header=BB0_11 Depth=1
	ds_load_b32 v1, v15
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v1, 1, v1
	ds_store_b32 v15, v1
.LBB0_24:                               ;   in Loop: Header=BB0_11 Depth=1
	s_or_b32 exec_lo, exec_lo, s4
	ds_load_u8 v1, v15 offset:4
	s_waitcnt lgkmcnt(0)
	v_cmp_eq_u16_e32 vcc_lo, 0, v1
	s_cbranch_vccnz .LBB0_11
.LBB0_25:                               ; %._crit_edge123
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s29, s2
	s_cbranch_execz .LBB0_206
; %bb.26:                               ; %.lr.ph131
	v_mbcnt_lo_u32_b32 v41, -1, 0
	v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v7, 2
	v_mov_b32_e32 v8, 1
	v_mov_b32_e32 v2, 33
	s_add_u32 s2, s0, 56
	s_addc_u32 s3, s1, 0
	s_mov_b32 s4, 0
	s_mov_b32 s30, 0
.LBB0_27:                               ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_29 Depth 2
                                        ;       Child Loop BB0_33 Depth 3
                                        ;       Child Loop BB0_41 Depth 3
                                        ;       Child Loop BB0_47 Depth 3
                                        ;       Child Loop BB0_56 Depth 3
                                        ;       Child Loop BB0_59 Depth 3
                                        ;         Child Loop BB0_62 Depth 4
                                        ;         Child Loop BB0_70 Depth 4
                                        ;         Child Loop BB0_78 Depth 4
                                        ;         Child Loop BB0_86 Depth 4
                                        ;         Child Loop BB0_94 Depth 4
                                        ;         Child Loop BB0_102 Depth 4
                                        ;         Child Loop BB0_110 Depth 4
                                        ;         Child Loop BB0_118 Depth 4
                                        ;         Child Loop BB0_126 Depth 4
                                        ;         Child Loop BB0_132 Depth 4
                                        ;         Child Loop BB0_141 Depth 4
                                        ;       Child Loop BB0_149 Depth 3
                                        ;       Child Loop BB0_157 Depth 3
                                        ;       Child Loop BB0_163 Depth 3
                                        ;       Child Loop BB0_172 Depth 3
                                        ;       Child Loop BB0_177 Depth 3
                                        ;       Child Loop BB0_185 Depth 3
                                        ;       Child Loop BB0_191 Depth 3
                                        ;       Child Loop BB0_200 Depth 3
	v_ashrrev_i32_e32 v1, 31, v0
	s_mov_b32 s31, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[31:32], 2, v[0:1]
	v_mov_b32_e32 v1, v4
	v_add_co_u32 v33, vcc_lo, s12, v31
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v34, vcc_lo, s13, v32, vcc_lo
	global_load_b64 v[35:36], v[33:34], off
	s_waitcnt vmcnt(0)
	v_cmpx_lt_i32_e64 v35, v36
	s_cbranch_execz .LBB0_204
; %bb.28:                               ; %.lr.ph127
                                        ;   in Loop: Header=BB0_27 Depth=1
	v_add_co_u32 v37, vcc_lo, s8, v31
	v_add_co_ci_u32_e32 v38, vcc_lo, s9, v32, vcc_lo
	v_add_co_u32 v39, vcc_lo, s10, v31
	v_add_co_ci_u32_e32 v40, vcc_lo, s11, v32, vcc_lo
	v_mov_b32_e32 v1, 0
	s_mov_b32 s33, 0
.LBB0_29:                               ;   Parent Loop BB0_27 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB0_33 Depth 3
                                        ;       Child Loop BB0_41 Depth 3
                                        ;       Child Loop BB0_47 Depth 3
                                        ;       Child Loop BB0_56 Depth 3
                                        ;       Child Loop BB0_59 Depth 3
                                        ;         Child Loop BB0_62 Depth 4
                                        ;         Child Loop BB0_70 Depth 4
                                        ;         Child Loop BB0_78 Depth 4
                                        ;         Child Loop BB0_86 Depth 4
                                        ;         Child Loop BB0_94 Depth 4
                                        ;         Child Loop BB0_102 Depth 4
                                        ;         Child Loop BB0_110 Depth 4
                                        ;         Child Loop BB0_118 Depth 4
                                        ;         Child Loop BB0_126 Depth 4
                                        ;         Child Loop BB0_132 Depth 4
                                        ;         Child Loop BB0_141 Depth 4
                                        ;       Child Loop BB0_149 Depth 3
                                        ;       Child Loop BB0_157 Depth 3
                                        ;       Child Loop BB0_163 Depth 3
                                        ;       Child Loop BB0_172 Depth 3
                                        ;       Child Loop BB0_177 Depth 3
                                        ;       Child Loop BB0_185 Depth 3
                                        ;       Child Loop BB0_191 Depth 3
                                        ;       Child Loop BB0_200 Depth 3
	v_ashrrev_i32_e32 v36, 31, v35
	s_mov_b32 s34, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[5:6], 2, v[35:36]
	v_add_co_u32 v5, vcc_lo, s14, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v6, vcc_lo, s15, v6, vcc_lo
	global_load_b32 v5, v[5:6], off
	s_waitcnt vmcnt(0)
	v_ashrrev_i32_e32 v6, 31, v5
	v_lshlrev_b64 v[5:6], 2, v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v9, vcc_lo, s8, v5
	v_add_co_ci_u32_e32 v10, vcc_lo, s9, v6, vcc_lo
	s_clause 0x1
	global_load_b32 v3, v[9:10], off
	global_load_b32 v9, v[37:38], off
	s_waitcnt vmcnt(1)
	v_add_nc_u32_e32 v3, 1, v3
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e64 v3, v9
	s_cbranch_execz .LBB0_202
; %bb.30:                               ;   in Loop: Header=BB0_29 Depth=2
	v_add_co_u32 v9, vcc_lo, s16, v5
	v_add_co_ci_u32_e32 v10, vcc_lo, s17, v6, vcc_lo
	v_add_co_u32 v5, vcc_lo, s10, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, s11, v6, vcc_lo
	global_load_b32 v36, v[39:40], off
	global_load_b32 v42, v[9:10], off
	global_load_b32 v43, v[5:6], off
	s_load_b64 s[18:19], s[2:3], 0x50
	v_mov_b32_e32 v3, v41
	v_mov_b32_e32 v5, 0
	v_mov_b32_e32 v6, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s0, v3
	v_cmp_eq_u32_e64 s0, s0, v3
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_36
; %bb.31:                               ;   in Loop: Header=BB0_29 Depth=2
	s_waitcnt lgkmcnt(0)
	global_load_b64 v[11:12], v4, s[18:19] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[5:6], v4, s[18:19] offset:40
	global_load_b64 v[9:10], v4, s[18:19]
	s_mov_b32 s5, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v6, v6, v12
	v_and_b32_e32 v5, v5, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v6, v6, 24
	v_mul_hi_u32 v13, v5, 24
	v_mul_lo_u32 v5, v5, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v6, v13, v6
	s_waitcnt vmcnt(0)
	v_add_co_u32 v5, vcc_lo, v9, v5
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v6, vcc_lo, v10, v6, vcc_lo
	global_load_b64 v[9:10], v[5:6], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[5:6], v4, v[9:12], s[18:19] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[5:6], v[11:12]
	s_cbranch_execz .LBB0_35
; %bb.32:                               ; %.preheader3.i.i.i.preheader
                                        ;   in Loop: Header=BB0_29 Depth=2
	s_mov_b32 s6, 0
.LBB0_33:                               ; %.preheader3.i.i.i
                                        ;   Parent Loop BB0_27 Depth=1
                                        ;     Parent Loop BB0_29 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[9:10], v4, s[18:19] offset:40
	global_load_b64 v[13:14], v4, s[18:19]
	v_dual_mov_b32 v12, v6 :: v_dual_mov_b32 v11, v5
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v9, v9, v11
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[5:6], null, v9, 24, v[13:14]
	v_and_b32_e32 v13, v10, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[9:10], null, v13, 24, v[6:7]
	v_mov_b32_e32 v6, v9
	global_load_b64 v[9:10], v[5:6], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[5:6], v4, v[9:12], s[18:19] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[5:6], v[11:12]
	s_or_b32 s6, vcc_lo, s6
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s6
	s_cbranch_execnz .LBB0_33
; %bb.34:                               ; %Flow450
                                        ;   in Loop: Header=BB0_29 Depth=2
	s_or_b32 exec_lo, exec_lo, s6
.LBB0_35:                               ; %Flow452
                                        ;   in Loop: Header=BB0_29 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s5
.LBB0_36:                               ; %.loopexit4.i.i.i
                                        ;   in Loop: Header=BB0_29 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_waitcnt lgkmcnt(0)
	s_clause 0x1
	global_load_b64 v[13:14], v4, s[18:19] offset:40
	global_load_b128 v[9:12], v4, s[18:19]
	v_readfirstlane_b32 s20, v5
	v_readfirstlane_b32 s21, v6
	s_mov_b32 s5, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s6, v13
	v_readfirstlane_b32 s7, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[6:7], s[20:21], s[6:7]
	s_mul_i32 s1, s7, 24
	s_mul_hi_u32 s22, s6, 24
	s_mul_i32 s23, s6, 24
	s_and_saveexec_b32 s24, s0
	s_cbranch_execz .LBB0_38
; %bb.37:                               ;   in Loop: Header=BB0_29 Depth=2
	v_dual_mov_b32 v5, s5 :: v_dual_mov_b32 v6, v4
	s_add_i32 s5, s22, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v13, vcc_lo, v9, s23
	v_add_co_ci_u32_e32 v14, vcc_lo, s5, v10, vcc_lo
	global_store_b128 v[13:14], v[5:8], off offset:8
.LBB0_38:                               ;   in Loop: Header=BB0_29 Depth=2
	s_or_b32 exec_lo, exec_lo, s24
	s_lshl_b64 s[6:7], s[6:7], 12
	v_lshlrev_b64 v[5:6], 6, v[3:4]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v3, vcc_lo, v11, s6
	v_add_co_ci_u32_e32 v11, vcc_lo, s7, v12, vcc_lo
	s_mov_b32 s7, s4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v15, vcc_lo, v3, v5
	s_mov_b32 s5, s4
	s_mov_b32 s6, s4
	v_add_co_ci_u32_e32 v16, vcc_lo, v11, v6, vcc_lo
	v_dual_mov_b32 v3, v4 :: v_dual_mov_b32 v14, s7
	v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v12, s5
	v_mov_b32_e32 v13, s6
	v_mov_b32_e32 v11, s4
	s_clause 0x3
	global_store_b128 v[15:16], v[2:5], off
	global_store_b128 v[15:16], v[11:14], off offset:16
	global_store_b128 v[15:16], v[11:14], off offset:32
	global_store_b128 v[15:16], v[11:14], off offset:48
	s_and_saveexec_b32 s5, s0
	s_cbranch_execz .LBB0_46
; %bb.39:                               ;   in Loop: Header=BB0_29 Depth=2
	s_clause 0x1
	global_load_b64 v[19:20], v4, s[18:19] offset:32 glc
	global_load_b64 v[5:6], v4, s[18:19] offset:40
	v_mov_b32_e32 v17, s20
	s_mov_b32 s6, exec_lo
	s_waitcnt vmcnt(0)
	v_dual_mov_b32 v18, s21 :: v_dual_and_b32 v3, s21, v6
	v_and_b32_e32 v5, s20, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v3, v3, 24
	v_mul_hi_u32 v6, v5, 24
	v_mul_lo_u32 v5, v5, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v3, v6, v3
	v_add_co_u32 v5, vcc_lo, v9, v5
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v6, vcc_lo, v10, v3, vcc_lo
	global_store_b64 v[5:6], v[19:20], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[13:14], v4, v[17:20], s[18:19] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[13:14], v[19:20]
	s_cbranch_execz .LBB0_42
; %bb.40:                               ; %.preheader1.i.i.i.preheader
                                        ;   in Loop: Header=BB0_29 Depth=2
	s_mov_b32 s7, 0
.LBB0_41:                               ; %.preheader1.i.i.i
                                        ;   Parent Loop BB0_27 Depth=1
                                        ;     Parent Loop BB0_29 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	v_dual_mov_b32 v11, s20 :: v_dual_mov_b32 v12, s21
	s_sleep 1
	global_store_b64 v[5:6], v[13:14], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[11:12], v4, v[11:14], s[18:19] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[11:12], v[13:14]
	v_dual_mov_b32 v14, v12 :: v_dual_mov_b32 v13, v11
	s_or_b32 s7, vcc_lo, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s7
	s_cbranch_execnz .LBB0_41
.LBB0_42:                               ; %Flow448
                                        ;   in Loop: Header=BB0_29 Depth=2
	s_or_b32 exec_lo, exec_lo, s6
	global_load_b64 v[5:6], v4, s[18:19] offset:16
	s_mov_b32 s7, exec_lo
	s_mov_b32 s6, exec_lo
	v_mbcnt_lo_u32_b32 v3, s7, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v3
	s_cbranch_execz .LBB0_44
; %bb.43:                               ;   in Loop: Header=BB0_29 Depth=2
	s_bcnt1_i32_b32 s7, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v3, s7
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[5:6], v[3:4], off offset:8
.LBB0_44:                               ;   in Loop: Header=BB0_29 Depth=2
	s_or_b32 exec_lo, exec_lo, s6
	s_waitcnt vmcnt(0)
	global_load_b64 v[11:12], v[5:6], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[11:12]
	s_cbranch_vccnz .LBB0_46
; %bb.45:                               ;   in Loop: Header=BB0_29 Depth=2
	global_load_b32 v3, v[5:6], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s6, v3
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[11:12], v[3:4], off
	s_and_b32 m0, s6, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_46:                               ; %Flow449
                                        ;   in Loop: Header=BB0_29 Depth=2
	s_or_b32 exec_lo, exec_lo, s5
	s_add_i32 s22, s22, s1
	v_add_co_u32 v3, vcc_lo, v9, s23
	v_add_co_ci_u32_e32 v6, vcc_lo, s22, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v5, vcc_lo, v3, 20
	v_add_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
.LBB0_47:                               ;   Parent Loop BB0_27 Depth=1
                                        ;     Parent Loop BB0_29 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	v_mov_b32_e32 v3, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_49
; %bb.48:                               ;   in Loop: Header=BB0_47 Depth=3
	global_load_b32 v3, v[5:6], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v3, 1, v3
.LBB0_49:                               ;   in Loop: Header=BB0_47 Depth=3
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v3
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB0_51
; %bb.50:                               ;   in Loop: Header=BB0_47 Depth=3
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB0_52
.LBB0_51:                               ;   in Loop: Header=BB0_47 Depth=3
	s_mov_b32 s1, -1
.LBB0_52:                               ; %Flow443
                                        ;   in Loop: Header=BB0_47 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB0_47
; %bb.53:                               ;   in Loop: Header=BB0_29 Depth=2
	global_load_b64 v[9:10], v[15:16], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_57
; %bb.54:                               ;   in Loop: Header=BB0_29 Depth=2
	s_clause 0x2
	global_load_b64 v[5:6], v4, s[18:19] offset:40
	global_load_b64 v[15:16], v4, s[18:19] offset:24 glc
	global_load_b64 v[13:14], v4, s[18:19]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v3, vcc_lo, v5, 1
	v_add_co_ci_u32_e32 v17, vcc_lo, 0, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v11, vcc_lo, v3, s20
	v_add_co_ci_u32_e32 v12, vcc_lo, s21, v17, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[11:12]
	v_dual_cndmask_b32 v12, v12, v17 :: v_dual_cndmask_b32 v11, v11, v3
	v_and_b32_e32 v3, v12, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v5, v11, v5
	v_mul_lo_u32 v3, v3, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v6, v5, 24
	v_mul_lo_u32 v5, v5, 24
	v_add_nc_u32_e32 v3, v6, v3
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v5, vcc_lo, v13, v5
	v_mov_b32_e32 v13, v15
	v_add_co_ci_u32_e32 v6, vcc_lo, v14, v3, vcc_lo
	v_mov_b32_e32 v14, v16
	global_store_b64 v[5:6], v[15:16], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[13:14], v4, v[11:14], s[18:19] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[13:14], v[15:16]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_57
; %bb.55:                               ; %.preheader.i.i.i.preheader
                                        ;   in Loop: Header=BB0_29 Depth=2
	s_mov_b32 s0, 0
.LBB0_56:                               ; %.preheader.i.i.i
                                        ;   Parent Loop BB0_27 Depth=1
                                        ;     Parent Loop BB0_29 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_sleep 1
	global_store_b64 v[5:6], v[13:14], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[15:16], v4, v[11:14], s[18:19] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[15:16], v[13:14]
	v_dual_mov_b32 v13, v15 :: v_dual_mov_b32 v14, v16
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB0_56
.LBB0_57:                               ; %__ockl_printf_begin.exit
                                        ;   in Loop: Header=BB0_29 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	s_getpc_b64 s[6:7]
	s_add_u32 s6, s6, .str@rel32@lo+4
	s_addc_u32 s7, s7, .str@rel32@hi+12
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u64 s[6:7], 0
	s_cbranch_scc0 .LBB0_144
; %bb.58:                               ;   in Loop: Header=BB0_29 Depth=2
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v44, 2, v9
	v_dual_mov_b32 v12, v10 :: v_dual_and_b32 v11, -3, v9
	s_mov_b64 s[20:21], 4
.LBB0_59:                               ;   Parent Loop BB0_27 Depth=1
                                        ;     Parent Loop BB0_29 Depth=2
                                        ; =>    This Loop Header: Depth=3
                                        ;         Child Loop BB0_62 Depth 4
                                        ;         Child Loop BB0_70 Depth 4
                                        ;         Child Loop BB0_78 Depth 4
                                        ;         Child Loop BB0_86 Depth 4
                                        ;         Child Loop BB0_94 Depth 4
                                        ;         Child Loop BB0_102 Depth 4
                                        ;         Child Loop BB0_110 Depth 4
                                        ;         Child Loop BB0_118 Depth 4
                                        ;         Child Loop BB0_126 Depth 4
                                        ;         Child Loop BB0_132 Depth 4
                                        ;         Child Loop BB0_141 Depth 4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_u64_e64 s0, s[20:21], 56
	s_and_b32 s0, s0, exec_lo
	s_cselect_b32 s22, s20, 56
	s_cselect_b32 s23, s21, 0
	s_cmp_gt_u32 s22, 7
	s_cbranch_scc1 .LBB0_64
; %bb.60:                               ;   in Loop: Header=BB0_59 Depth=3
	s_waitcnt vmcnt(0)
	v_mov_b32_e32 v13, 0
	v_mov_b32_e32 v14, 0
	s_cmp_eq_u32 s22, 0
	s_cbranch_scc1 .LBB0_63
; %bb.61:                               ; %.preheader31.i.preheader
                                        ;   in Loop: Header=BB0_59 Depth=3
	s_lshl_b64 s[0:1], s[22:23], 3
	s_mov_b64 s[24:25], 0
	s_mov_b64 s[26:27], s[6:7]
.LBB0_62:                               ; %.preheader31.i
                                        ;   Parent Loop BB0_27 Depth=1
                                        ;     Parent Loop BB0_29 Depth=2
                                        ;       Parent Loop BB0_59 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	global_load_u8 v3, v4, s[26:27]
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v3, 0xffff, v3
	s_delay_alu instid0(VALU_DEP_1)
	v_lshlrev_b64 v[5:6], s24, v[3:4]
	s_add_u32 s24, s24, 8
	s_addc_u32 s25, s25, 0
	s_add_u32 s26, s26, 1
	s_addc_u32 s27, s27, 0
	s_cmp_lg_u32 s0, s24
	v_or_b32_e32 v13, v5, v13
	v_or_b32_e32 v14, v6, v14
	s_cbranch_scc1 .LBB0_62
.LBB0_63:                               ; %Flow419
                                        ;   in Loop: Header=BB0_59 Depth=3
	s_mov_b32 s0, 0
	s_mov_b32 s5, 0
	s_branch .LBB0_65
.LBB0_64:                               ;   in Loop: Header=BB0_59 Depth=3
	s_mov_b32 s0, -1
                                        ; implicit-def: $vgpr13_vgpr14
                                        ; implicit-def: $sgpr5
.LBB0_65:                               ; %Flow421
                                        ;   in Loop: Header=BB0_59 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s0
	s_mov_b64 s[0:1], s[6:7]
	s_cbranch_vccnz .LBB0_67
; %bb.66:                               ;   in Loop: Header=BB0_59 Depth=3
	global_load_b64 v[13:14], v4, s[6:7]
	s_add_i32 s5, s22, -8
	s_add_u32 s0, s6, 8
	s_addc_u32 s1, s7, 0
.LBB0_67:                               ; %.loopexit32.i
                                        ;   in Loop: Header=BB0_59 Depth=3
	s_cmp_gt_u32 s5, 7
	s_cbranch_scc1 .LBB0_72
; %bb.68:                               ;   in Loop: Header=BB0_59 Depth=3
	v_mov_b32_e32 v15, 0
	v_mov_b32_e32 v16, 0
	s_cmp_eq_u32 s5, 0
	s_cbranch_scc1 .LBB0_71
; %bb.69:                               ; %.preheader29.i.preheader
                                        ;   in Loop: Header=BB0_59 Depth=3
	s_mov_b64 s[24:25], 0
	s_mov_b64 s[26:27], 0
.LBB0_70:                               ; %.preheader29.i
                                        ;   Parent Loop BB0_27 Depth=1
                                        ;     Parent Loop BB0_29 Depth=2
                                        ;       Parent Loop BB0_59 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s36, s0, s26
	s_addc_u32 s37, s1, s27
	s_add_u32 s26, s26, 1
	global_load_u8 v3, v4, s[36:37]
	s_addc_u32 s27, s27, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v3, 0xffff, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[5:6], s24, v[3:4]
	s_add_u32 s24, s24, 8
	s_addc_u32 s25, s25, 0
	s_cmp_lg_u32 s5, s26
	v_or_b32_e32 v15, v5, v15
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v16, v6, v16
	s_cbranch_scc1 .LBB0_70
.LBB0_71:                               ; %Flow414
                                        ;   in Loop: Header=BB0_59 Depth=3
	s_mov_b32 s24, 0
	s_mov_b32 s35, 0
	s_branch .LBB0_73
.LBB0_72:                               ;   in Loop: Header=BB0_59 Depth=3
	s_mov_b32 s24, -1
                                        ; implicit-def: $vgpr15_vgpr16
                                        ; implicit-def: $sgpr35
.LBB0_73:                               ; %Flow416
                                        ;   in Loop: Header=BB0_59 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s24
	s_cbranch_vccnz .LBB0_75
; %bb.74:                               ;   in Loop: Header=BB0_59 Depth=3
	global_load_b64 v[15:16], v4, s[0:1]
	s_add_i32 s35, s5, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB0_75:                               ; %.loopexit30.i
                                        ;   in Loop: Header=BB0_59 Depth=3
	s_cmp_gt_u32 s35, 7
	s_cbranch_scc1 .LBB0_80
; %bb.76:                               ;   in Loop: Header=BB0_59 Depth=3
	v_mov_b32_e32 v17, 0
	v_mov_b32_e32 v18, 0
	s_cmp_eq_u32 s35, 0
	s_cbranch_scc1 .LBB0_79
; %bb.77:                               ; %.preheader27.i.preheader
                                        ;   in Loop: Header=BB0_59 Depth=3
	s_mov_b64 s[24:25], 0
	s_mov_b64 s[26:27], 0
.LBB0_78:                               ; %.preheader27.i
                                        ;   Parent Loop BB0_27 Depth=1
                                        ;     Parent Loop BB0_29 Depth=2
                                        ;       Parent Loop BB0_59 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s36, s0, s26
	s_addc_u32 s37, s1, s27
	s_add_u32 s26, s26, 1
	global_load_u8 v3, v4, s[36:37]
	s_addc_u32 s27, s27, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v3, 0xffff, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[5:6], s24, v[3:4]
	s_add_u32 s24, s24, 8
	s_addc_u32 s25, s25, 0
	s_cmp_lg_u32 s35, s26
	v_or_b32_e32 v17, v5, v17
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v18, v6, v18
	s_cbranch_scc1 .LBB0_78
.LBB0_79:                               ; %Flow409
                                        ;   in Loop: Header=BB0_59 Depth=3
	s_mov_b32 s24, 0
	s_mov_b32 s5, 0
	s_branch .LBB0_81
.LBB0_80:                               ;   in Loop: Header=BB0_59 Depth=3
	s_mov_b32 s24, -1
                                        ; implicit-def: $sgpr5
.LBB0_81:                               ; %Flow411
                                        ;   in Loop: Header=BB0_59 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s24
	s_cbranch_vccnz .LBB0_83
; %bb.82:                               ;   in Loop: Header=BB0_59 Depth=3
	global_load_b64 v[17:18], v4, s[0:1]
	s_add_i32 s5, s35, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB0_83:                               ; %.loopexit28.i
                                        ;   in Loop: Header=BB0_59 Depth=3
	s_cmp_gt_u32 s5, 7
	s_cbranch_scc1 .LBB0_88
; %bb.84:                               ;   in Loop: Header=BB0_59 Depth=3
	v_mov_b32_e32 v19, 0
	v_mov_b32_e32 v20, 0
	s_cmp_eq_u32 s5, 0
	s_cbranch_scc1 .LBB0_87
; %bb.85:                               ; %.preheader25.i.preheader
                                        ;   in Loop: Header=BB0_59 Depth=3
	s_mov_b64 s[24:25], 0
	s_mov_b64 s[26:27], 0
.LBB0_86:                               ; %.preheader25.i
                                        ;   Parent Loop BB0_27 Depth=1
                                        ;     Parent Loop BB0_29 Depth=2
                                        ;       Parent Loop BB0_59 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s36, s0, s26
	s_addc_u32 s37, s1, s27
	s_add_u32 s26, s26, 1
	global_load_u8 v3, v4, s[36:37]
	s_addc_u32 s27, s27, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v3, 0xffff, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[5:6], s24, v[3:4]
	s_add_u32 s24, s24, 8
	s_addc_u32 s25, s25, 0
	s_cmp_lg_u32 s5, s26
	v_or_b32_e32 v19, v5, v19
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v20, v6, v20
	s_cbranch_scc1 .LBB0_86
.LBB0_87:                               ; %Flow404
                                        ;   in Loop: Header=BB0_59 Depth=3
	s_mov_b32 s24, 0
	s_mov_b32 s35, 0
	s_branch .LBB0_89
.LBB0_88:                               ;   in Loop: Header=BB0_59 Depth=3
	s_mov_b32 s24, -1
                                        ; implicit-def: $vgpr19_vgpr20
                                        ; implicit-def: $sgpr35
.LBB0_89:                               ; %Flow406
                                        ;   in Loop: Header=BB0_59 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s24
	s_cbranch_vccnz .LBB0_91
; %bb.90:                               ;   in Loop: Header=BB0_59 Depth=3
	global_load_b64 v[19:20], v4, s[0:1]
	s_add_i32 s35, s5, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB0_91:                               ; %.loopexit26.i
                                        ;   in Loop: Header=BB0_59 Depth=3
	s_cmp_gt_u32 s35, 7
	s_cbranch_scc1 .LBB0_96
; %bb.92:                               ;   in Loop: Header=BB0_59 Depth=3
	v_mov_b32_e32 v21, 0
	v_mov_b32_e32 v22, 0
	s_cmp_eq_u32 s35, 0
	s_cbranch_scc1 .LBB0_95
; %bb.93:                               ; %.preheader23.i.preheader
                                        ;   in Loop: Header=BB0_59 Depth=3
	s_mov_b64 s[24:25], 0
	s_mov_b64 s[26:27], 0
.LBB0_94:                               ; %.preheader23.i
                                        ;   Parent Loop BB0_27 Depth=1
                                        ;     Parent Loop BB0_29 Depth=2
                                        ;       Parent Loop BB0_59 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s36, s0, s26
	s_addc_u32 s37, s1, s27
	s_add_u32 s26, s26, 1
	global_load_u8 v3, v4, s[36:37]
	s_addc_u32 s27, s27, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v3, 0xffff, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[5:6], s24, v[3:4]
	s_add_u32 s24, s24, 8
	s_addc_u32 s25, s25, 0
	s_cmp_lg_u32 s35, s26
	v_or_b32_e32 v21, v5, v21
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v22, v6, v22
	s_cbranch_scc1 .LBB0_94
.LBB0_95:                               ; %Flow399
                                        ;   in Loop: Header=BB0_59 Depth=3
	s_mov_b32 s24, 0
	s_mov_b32 s5, 0
	s_branch .LBB0_97
.LBB0_96:                               ;   in Loop: Header=BB0_59 Depth=3
	s_mov_b32 s24, -1
                                        ; implicit-def: $sgpr5
.LBB0_97:                               ; %Flow401
                                        ;   in Loop: Header=BB0_59 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s24
	s_cbranch_vccnz .LBB0_99
; %bb.98:                               ;   in Loop: Header=BB0_59 Depth=3
	global_load_b64 v[21:22], v4, s[0:1]
	s_add_i32 s5, s35, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB0_99:                               ; %.loopexit24.i
                                        ;   in Loop: Header=BB0_59 Depth=3
	s_cmp_gt_u32 s5, 7
	s_cbranch_scc1 .LBB0_104
; %bb.100:                              ;   in Loop: Header=BB0_59 Depth=3
	v_mov_b32_e32 v23, 0
	v_mov_b32_e32 v24, 0
	s_cmp_eq_u32 s5, 0
	s_cbranch_scc1 .LBB0_103
; %bb.101:                              ; %.preheader21.i.preheader
                                        ;   in Loop: Header=BB0_59 Depth=3
	s_mov_b64 s[24:25], 0
	s_mov_b64 s[26:27], 0
.LBB0_102:                              ; %.preheader21.i
                                        ;   Parent Loop BB0_27 Depth=1
                                        ;     Parent Loop BB0_29 Depth=2
                                        ;       Parent Loop BB0_59 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s36, s0, s26
	s_addc_u32 s37, s1, s27
	s_add_u32 s26, s26, 1
	global_load_u8 v3, v4, s[36:37]
	s_addc_u32 s27, s27, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v3, 0xffff, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[5:6], s24, v[3:4]
	s_add_u32 s24, s24, 8
	s_addc_u32 s25, s25, 0
	s_cmp_lg_u32 s5, s26
	v_or_b32_e32 v23, v5, v23
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v24, v6, v24
	s_cbranch_scc1 .LBB0_102
.LBB0_103:                              ; %Flow394
                                        ;   in Loop: Header=BB0_59 Depth=3
	s_mov_b32 s24, 0
	s_mov_b32 s35, 0
	s_branch .LBB0_105
.LBB0_104:                              ;   in Loop: Header=BB0_59 Depth=3
	s_mov_b32 s24, -1
                                        ; implicit-def: $vgpr23_vgpr24
                                        ; implicit-def: $sgpr35
.LBB0_105:                              ; %Flow396
                                        ;   in Loop: Header=BB0_59 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s24
	s_cbranch_vccnz .LBB0_107
; %bb.106:                              ;   in Loop: Header=BB0_59 Depth=3
	global_load_b64 v[23:24], v4, s[0:1]
	s_add_i32 s35, s5, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB0_107:                              ; %.loopexit22.i
                                        ;   in Loop: Header=BB0_59 Depth=3
	s_cmp_gt_u32 s35, 7
	s_cbranch_scc1 .LBB0_112
; %bb.108:                              ;   in Loop: Header=BB0_59 Depth=3
	v_mov_b32_e32 v25, 0
	v_mov_b32_e32 v26, 0
	s_cmp_eq_u32 s35, 0
	s_cbranch_scc1 .LBB0_111
; %bb.109:                              ; %.preheader.i.preheader
                                        ;   in Loop: Header=BB0_59 Depth=3
	s_mov_b64 s[24:25], 0
	s_mov_b64 s[26:27], s[0:1]
.LBB0_110:                              ; %.preheader.i
                                        ;   Parent Loop BB0_27 Depth=1
                                        ;     Parent Loop BB0_29 Depth=2
                                        ;       Parent Loop BB0_59 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	global_load_u8 v3, v4, s[26:27]
	s_add_i32 s35, s35, -1
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v3, 0xffff, v3
	s_delay_alu instid0(VALU_DEP_1)
	v_lshlrev_b64 v[5:6], s24, v[3:4]
	s_add_u32 s24, s24, 8
	s_addc_u32 s25, s25, 0
	s_add_u32 s26, s26, 1
	s_addc_u32 s27, s27, 0
	s_cmp_lg_u32 s35, 0
	v_or_b32_e32 v25, v5, v25
	v_or_b32_e32 v26, v6, v26
	s_cbranch_scc1 .LBB0_110
.LBB0_111:                              ; %Flow389
                                        ;   in Loop: Header=BB0_59 Depth=3
	s_mov_b32 s5, 0
	s_branch .LBB0_113
.LBB0_112:                              ;   in Loop: Header=BB0_59 Depth=3
	s_mov_b32 s5, -1
.LBB0_113:                              ; %Flow391
                                        ;   in Loop: Header=BB0_59 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s5
	s_cbranch_vccnz .LBB0_115
; %bb.114:                              ;   in Loop: Header=BB0_59 Depth=3
	global_load_b64 v[25:26], v4, s[0:1]
.LBB0_115:                              ; %.loopexit.i
                                        ;   in Loop: Header=BB0_59 Depth=3
	v_mov_b32_e32 v3, v41
	v_mov_b32_e32 v5, 0
	v_mov_b32_e32 v6, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s0, v3
	v_cmp_eq_u32_e64 s0, s0, v3
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_121
; %bb.116:                              ;   in Loop: Header=BB0_59 Depth=3
	global_load_b64 v[29:30], v4, s[18:19] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[5:6], v4, s[18:19] offset:40
	global_load_b64 v[27:28], v4, s[18:19]
	s_mov_b32 s5, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v6, v6, v30
	v_and_b32_e32 v5, v5, v29
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v6, v6, 24
	v_mul_hi_u32 v45, v5, 24
	v_mul_lo_u32 v5, v5, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v6, v45, v6
	s_waitcnt vmcnt(0)
	v_add_co_u32 v5, vcc_lo, v27, v5
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v6, vcc_lo, v28, v6, vcc_lo
	global_load_b64 v[27:28], v[5:6], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[5:6], v4, v[27:30], s[18:19] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[5:6], v[29:30]
	s_cbranch_execz .LBB0_120
; %bb.117:                              ; %.preheader3.i.i19.i.preheader
                                        ;   in Loop: Header=BB0_59 Depth=3
	s_mov_b32 s24, 0
.LBB0_118:                              ; %.preheader3.i.i19.i
                                        ;   Parent Loop BB0_27 Depth=1
                                        ;     Parent Loop BB0_29 Depth=2
                                        ;       Parent Loop BB0_59 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[27:28], v4, s[18:19] offset:40
	global_load_b64 v[45:46], v4, s[18:19]
	v_dual_mov_b32 v30, v6 :: v_dual_mov_b32 v29, v5
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v27, v27, v29
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[5:6], null, v27, 24, v[45:46]
	v_and_b32_e32 v45, v28, v30
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[27:28], null, v45, 24, v[6:7]
	v_mov_b32_e32 v6, v27
	global_load_b64 v[27:28], v[5:6], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[5:6], v4, v[27:30], s[18:19] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[5:6], v[29:30]
	s_or_b32 s24, vcc_lo, s24
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s24
	s_cbranch_execnz .LBB0_118
; %bb.119:                              ; %Flow384
                                        ;   in Loop: Header=BB0_59 Depth=3
	s_or_b32 exec_lo, exec_lo, s24
.LBB0_120:                              ; %Flow386
                                        ;   in Loop: Header=BB0_59 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s5
.LBB0_121:                              ; %.loopexit4.i.i14.i
                                        ;   in Loop: Header=BB0_59 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_clause 0x1
	global_load_b64 v[45:46], v4, s[18:19] offset:40
	global_load_b128 v[27:30], v4, s[18:19]
	v_readfirstlane_b32 s24, v5
	v_readfirstlane_b32 s25, v6
	s_mov_b32 s36, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s26, v45
	v_readfirstlane_b32 s27, v46
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[26:27], s[24:25], s[26:27]
	s_mul_i32 s1, s27, 24
	s_mul_hi_u32 s5, s26, 24
	s_mul_i32 s35, s26, 24
	s_and_saveexec_b32 s37, s0
	s_cbranch_execz .LBB0_123
; %bb.122:                              ;   in Loop: Header=BB0_59 Depth=3
	v_dual_mov_b32 v5, s36 :: v_dual_mov_b32 v6, v4
	s_add_i32 s36, s5, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v45, vcc_lo, v27, s35
	v_add_co_ci_u32_e32 v46, vcc_lo, s36, v28, vcc_lo
	global_store_b128 v[45:46], v[5:8], off offset:8
.LBB0_123:                              ;   in Loop: Header=BB0_59 Depth=3
	s_or_b32 exec_lo, exec_lo, s37
	v_cmp_gt_u64_e64 vcc_lo, s[20:21], 56
	v_or_b32_e32 v5, 0, v12
	v_or_b32_e32 v6, v11, v44
	s_lshl_b64 s[26:27], s[26:27], 12
	s_lshl_b32 s36, s22, 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_add_i32 s36, s36, 28
	v_dual_cndmask_b32 v12, v5, v12 :: v_dual_cndmask_b32 v11, v6, v11
	v_lshlrev_b64 v[5:6], 6, v[3:4]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v3, vcc_lo, v29, s26
	v_add_co_ci_u32_e32 v29, vcc_lo, s27, v30, vcc_lo
	s_and_b32 s36, s36, 0x1e0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v5, vcc_lo, v3, v5
	v_and_or_b32 v11, 0xffffff1f, v11, s36
	v_add_co_ci_u32_e32 v6, vcc_lo, v29, v6, vcc_lo
	s_clause 0x3
	global_store_b128 v[5:6], v[11:14], off
	global_store_b128 v[5:6], v[15:18], off offset:16
	global_store_b128 v[5:6], v[19:22], off offset:32
	global_store_b128 v[5:6], v[23:26], off offset:48
	s_and_saveexec_b32 s26, s0
	s_cbranch_execz .LBB0_131
; %bb.124:                              ;   in Loop: Header=BB0_59 Depth=3
	s_clause 0x1
	global_load_b64 v[19:20], v4, s[18:19] offset:32 glc
	global_load_b64 v[11:12], v4, s[18:19] offset:40
	v_dual_mov_b32 v17, s24 :: v_dual_mov_b32 v18, s25
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s36, v11
	v_readfirstlane_b32 s37, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[36:37], s[36:37], s[24:25]
	s_mul_i32 s27, s37, 24
	s_mul_hi_u32 s37, s36, 24
	s_mul_i32 s36, s36, 24
	s_add_i32 s37, s37, s27
	v_add_co_u32 v15, vcc_lo, v27, s36
	v_add_co_ci_u32_e32 v16, vcc_lo, s37, v28, vcc_lo
	s_mov_b32 s27, exec_lo
	global_store_b64 v[15:16], v[19:20], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[13:14], v4, v[17:20], s[18:19] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[13:14], v[19:20]
	s_cbranch_execz .LBB0_127
; %bb.125:                              ; %.preheader1.i.i17.i.preheader
                                        ;   in Loop: Header=BB0_59 Depth=3
	s_mov_b32 s36, 0
.LBB0_126:                              ; %.preheader1.i.i17.i
                                        ;   Parent Loop BB0_27 Depth=1
                                        ;     Parent Loop BB0_29 Depth=2
                                        ;       Parent Loop BB0_59 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	v_dual_mov_b32 v11, s24 :: v_dual_mov_b32 v12, s25
	s_sleep 1
	global_store_b64 v[15:16], v[13:14], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[11:12], v4, v[11:14], s[18:19] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[11:12], v[13:14]
	v_dual_mov_b32 v14, v12 :: v_dual_mov_b32 v13, v11
	s_or_b32 s36, vcc_lo, s36
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s36
	s_cbranch_execnz .LBB0_126
.LBB0_127:                              ; %Flow382
                                        ;   in Loop: Header=BB0_59 Depth=3
	s_or_b32 exec_lo, exec_lo, s27
	global_load_b64 v[11:12], v4, s[18:19] offset:16
	s_mov_b32 s36, exec_lo
	s_mov_b32 s27, exec_lo
	v_mbcnt_lo_u32_b32 v3, s36, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v3
	s_cbranch_execz .LBB0_129
; %bb.128:                              ;   in Loop: Header=BB0_59 Depth=3
	s_bcnt1_i32_b32 s36, s36
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v3, s36
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[11:12], v[3:4], off offset:8
.LBB0_129:                              ;   in Loop: Header=BB0_59 Depth=3
	s_or_b32 exec_lo, exec_lo, s27
	s_waitcnt vmcnt(0)
	global_load_b64 v[13:14], v[11:12], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[13:14]
	s_cbranch_vccnz .LBB0_131
; %bb.130:                              ;   in Loop: Header=BB0_59 Depth=3
	global_load_b32 v3, v[11:12], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s27, v3
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[13:14], v[3:4], off
	s_and_b32 m0, s27, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_131:                              ; %Flow383
                                        ;   in Loop: Header=BB0_59 Depth=3
	s_or_b32 exec_lo, exec_lo, s26
	s_add_i32 s5, s5, s1
	v_add_co_u32 v3, vcc_lo, v27, s35
	v_add_co_ci_u32_e32 v12, vcc_lo, s5, v28, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v11, vcc_lo, v3, 20
	v_add_co_ci_u32_e32 v12, vcc_lo, 0, v12, vcc_lo
.LBB0_132:                              ;   Parent Loop BB0_27 Depth=1
                                        ;     Parent Loop BB0_29 Depth=2
                                        ;       Parent Loop BB0_59 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	v_mov_b32_e32 v3, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_134
; %bb.133:                              ;   in Loop: Header=BB0_132 Depth=4
	global_load_b32 v3, v[11:12], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v3, 1, v3
.LBB0_134:                              ;   in Loop: Header=BB0_132 Depth=4
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v3
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB0_136
; %bb.135:                              ;   in Loop: Header=BB0_132 Depth=4
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB0_137
.LBB0_136:                              ;   in Loop: Header=BB0_132 Depth=4
	s_mov_b32 s1, -1
.LBB0_137:                              ; %Flow377
                                        ;   in Loop: Header=BB0_132 Depth=4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB0_132
; %bb.138:                              ;   in Loop: Header=BB0_59 Depth=3
	global_load_b128 v[11:14], v[5:6], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_142
; %bb.139:                              ;   in Loop: Header=BB0_59 Depth=3
	s_clause 0x2
	global_load_b64 v[5:6], v4, s[18:19] offset:40
	global_load_b64 v[17:18], v4, s[18:19] offset:24 glc
	global_load_b64 v[15:16], v4, s[18:19]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v3, vcc_lo, v5, 1
	v_add_co_ci_u32_e32 v19, vcc_lo, 0, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v13, vcc_lo, v3, s24
	v_add_co_ci_u32_e32 v14, vcc_lo, s25, v19, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[13:14]
	v_cndmask_b32_e32 v13, v13, v3, vcc_lo
	v_dual_cndmask_b32 v14, v14, v19 :: v_dual_and_b32 v5, v13, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v3, v14, v6
	v_mul_hi_u32 v6, v5, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v3, v3, 24
	v_mul_lo_u32 v5, v5, 24
	v_add_nc_u32_e32 v3, v6, v3
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v5, vcc_lo, v15, v5
	v_mov_b32_e32 v15, v17
	v_add_co_ci_u32_e32 v6, vcc_lo, v16, v3, vcc_lo
	v_mov_b32_e32 v16, v18
	global_store_b64 v[5:6], v[17:18], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[15:16], v4, v[13:16], s[18:19] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[15:16], v[17:18]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_142
; %bb.140:                              ; %.preheader.i.i16.i.preheader
                                        ;   in Loop: Header=BB0_59 Depth=3
	s_mov_b32 s0, 0
.LBB0_141:                              ; %.preheader.i.i16.i
                                        ;   Parent Loop BB0_27 Depth=1
                                        ;     Parent Loop BB0_29 Depth=2
                                        ;       Parent Loop BB0_59 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	s_sleep 1
	global_store_b64 v[5:6], v[15:16], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[17:18], v4, v[13:16], s[18:19] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[17:18], v[15:16]
	v_dual_mov_b32 v15, v17 :: v_dual_mov_b32 v16, v18
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB0_141
.LBB0_142:                              ; %__ockl_hostcall_preview.exit20.i
                                        ;   in Loop: Header=BB0_59 Depth=3
	s_or_b32 exec_lo, exec_lo, s1
	s_sub_u32 s20, s20, s22
	s_subb_u32 s21, s21, s23
	s_add_u32 s6, s6, s22
	s_addc_u32 s7, s7, s23
	s_cmp_lg_u64 s[20:21], 0
	s_cbranch_scc1 .LBB0_59
; %bb.143:                              ; %Flow422
                                        ;   in Loop: Header=BB0_29 Depth=2
	s_mov_b32 s0, 0
	s_branch .LBB0_145
.LBB0_144:                              ;   in Loop: Header=BB0_29 Depth=2
	s_mov_b32 s0, -1
                                        ; implicit-def: $vgpr11_vgpr12
.LBB0_145:                              ; %Flow437
                                        ;   in Loop: Header=BB0_29 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccz .LBB0_174
; %bb.146:                              ;   in Loop: Header=BB0_29 Depth=2
	v_mov_b32_e32 v3, v41
	v_mov_b32_e32 v5, 0
	v_mov_b32_e32 v6, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s0, v3
	v_cmp_eq_u32_e64 s0, s0, v3
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_152
; %bb.147:                              ;   in Loop: Header=BB0_29 Depth=2
	global_load_b64 v[13:14], v4, s[18:19] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[5:6], v4, s[18:19] offset:40
	global_load_b64 v[11:12], v4, s[18:19]
	s_mov_b32 s5, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v6, v6, v14
	v_and_b32_e32 v5, v5, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v6, v6, 24
	v_mul_hi_u32 v15, v5, 24
	v_mul_lo_u32 v5, v5, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v6, v15, v6
	s_waitcnt vmcnt(0)
	v_add_co_u32 v5, vcc_lo, v11, v5
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v6, vcc_lo, v12, v6, vcc_lo
	global_load_b64 v[11:12], v[5:6], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[5:6], v4, v[11:14], s[18:19] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[5:6], v[13:14]
	s_cbranch_execz .LBB0_151
; %bb.148:                              ; %.preheader3.i.i.i92.preheader
                                        ;   in Loop: Header=BB0_29 Depth=2
	s_mov_b32 s6, 0
.LBB0_149:                              ; %.preheader3.i.i.i92
                                        ;   Parent Loop BB0_27 Depth=1
                                        ;     Parent Loop BB0_29 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[11:12], v4, s[18:19] offset:40
	global_load_b64 v[15:16], v4, s[18:19]
	v_dual_mov_b32 v14, v6 :: v_dual_mov_b32 v13, v5
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v11, v11, v13
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[5:6], null, v11, 24, v[15:16]
	v_and_b32_e32 v15, v12, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[11:12], null, v15, 24, v[6:7]
	v_mov_b32_e32 v6, v11
	global_load_b64 v[11:12], v[5:6], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[5:6], v4, v[11:14], s[18:19] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[5:6], v[13:14]
	s_or_b32 s6, vcc_lo, s6
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s6
	s_cbranch_execnz .LBB0_149
; %bb.150:                              ; %Flow434
                                        ;   in Loop: Header=BB0_29 Depth=2
	s_or_b32 exec_lo, exec_lo, s6
.LBB0_151:                              ; %Flow436
                                        ;   in Loop: Header=BB0_29 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s5
.LBB0_152:                              ; %.loopexit4.i.i.i87
                                        ;   in Loop: Header=BB0_29 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_clause 0x1
	global_load_b64 v[11:12], v4, s[18:19] offset:40
	global_load_b128 v[13:16], v4, s[18:19]
	v_readfirstlane_b32 s20, v5
	v_readfirstlane_b32 s21, v6
	s_mov_b32 s5, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s6, v11
	v_readfirstlane_b32 s7, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[6:7], s[20:21], s[6:7]
	s_mul_i32 s1, s7, 24
	s_mul_hi_u32 s22, s6, 24
	s_mul_i32 s23, s6, 24
	s_and_saveexec_b32 s24, s0
	s_cbranch_execz .LBB0_154
; %bb.153:                              ;   in Loop: Header=BB0_29 Depth=2
	v_dual_mov_b32 v5, s5 :: v_dual_mov_b32 v6, v4
	s_add_i32 s5, s22, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v11, vcc_lo, v13, s23
	v_add_co_ci_u32_e32 v12, vcc_lo, s5, v14, vcc_lo
	global_store_b128 v[11:12], v[5:8], off offset:8
.LBB0_154:                              ;   in Loop: Header=BB0_29 Depth=2
	s_or_b32 exec_lo, exec_lo, s24
	s_lshl_b64 s[6:7], s[6:7], 12
	v_lshlrev_b64 v[5:6], 6, v[3:4]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v3, vcc_lo, v15, s6
	v_add_co_ci_u32_e32 v11, vcc_lo, s7, v16, vcc_lo
	s_mov_b32 s7, s4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v5, vcc_lo, v3, v5
	s_mov_b32 s5, s4
	s_mov_b32 s6, s4
	v_and_or_b32 v9, 0xffffff1f, v9, 32
	v_add_co_ci_u32_e32 v6, vcc_lo, v11, v6, vcc_lo
	v_dual_mov_b32 v11, v4 :: v_dual_mov_b32 v18, s7
	v_dual_mov_b32 v12, v4 :: v_dual_mov_b32 v17, s6
	v_dual_mov_b32 v16, s5 :: v_dual_mov_b32 v15, s4
	s_clause 0x3
	global_store_b128 v[5:6], v[9:12], off
	global_store_b128 v[5:6], v[15:18], off offset:16
	global_store_b128 v[5:6], v[15:18], off offset:32
	global_store_b128 v[5:6], v[15:18], off offset:48
	s_and_saveexec_b32 s5, s0
	s_cbranch_execz .LBB0_162
; %bb.155:                              ;   in Loop: Header=BB0_29 Depth=2
	s_clause 0x1
	global_load_b64 v[19:20], v4, s[18:19] offset:32 glc
	global_load_b64 v[9:10], v4, s[18:19] offset:40
	v_dual_mov_b32 v17, s20 :: v_dual_mov_b32 v18, s21
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s6, v9
	v_readfirstlane_b32 s7, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[6:7], s[6:7], s[20:21]
	s_mul_i32 s7, s7, 24
	s_mul_hi_u32 s24, s6, 24
	s_mul_i32 s6, s6, 24
	s_add_i32 s24, s24, s7
	v_add_co_u32 v15, vcc_lo, v13, s6
	v_add_co_ci_u32_e32 v16, vcc_lo, s24, v14, vcc_lo
	s_mov_b32 s6, exec_lo
	global_store_b64 v[15:16], v[19:20], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[11:12], v4, v[17:20], s[18:19] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[11:12], v[19:20]
	s_cbranch_execz .LBB0_158
; %bb.156:                              ; %.preheader1.i.i.i90.preheader
                                        ;   in Loop: Header=BB0_29 Depth=2
	s_mov_b32 s7, 0
.LBB0_157:                              ; %.preheader1.i.i.i90
                                        ;   Parent Loop BB0_27 Depth=1
                                        ;     Parent Loop BB0_29 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	v_dual_mov_b32 v9, s20 :: v_dual_mov_b32 v10, s21
	s_sleep 1
	global_store_b64 v[15:16], v[11:12], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[9:10], v4, v[9:12], s[18:19] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[9:10], v[11:12]
	v_dual_mov_b32 v12, v10 :: v_dual_mov_b32 v11, v9
	s_or_b32 s7, vcc_lo, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s7
	s_cbranch_execnz .LBB0_157
.LBB0_158:                              ; %Flow432
                                        ;   in Loop: Header=BB0_29 Depth=2
	s_or_b32 exec_lo, exec_lo, s6
	global_load_b64 v[9:10], v4, s[18:19] offset:16
	s_mov_b32 s7, exec_lo
	s_mov_b32 s6, exec_lo
	v_mbcnt_lo_u32_b32 v3, s7, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v3
	s_cbranch_execz .LBB0_160
; %bb.159:                              ;   in Loop: Header=BB0_29 Depth=2
	s_bcnt1_i32_b32 s7, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v3, s7
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[9:10], v[3:4], off offset:8
.LBB0_160:                              ;   in Loop: Header=BB0_29 Depth=2
	s_or_b32 exec_lo, exec_lo, s6
	s_waitcnt vmcnt(0)
	global_load_b64 v[11:12], v[9:10], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[11:12]
	s_cbranch_vccnz .LBB0_162
; %bb.161:                              ;   in Loop: Header=BB0_29 Depth=2
	global_load_b32 v3, v[9:10], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s6, v3
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[11:12], v[3:4], off
	s_and_b32 m0, s6, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_162:                              ; %Flow433
                                        ;   in Loop: Header=BB0_29 Depth=2
	s_or_b32 exec_lo, exec_lo, s5
	s_add_i32 s22, s22, s1
	v_add_co_u32 v3, vcc_lo, v13, s23
	v_add_co_ci_u32_e32 v10, vcc_lo, s22, v14, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v9, vcc_lo, v3, 20
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v10, vcc_lo
.LBB0_163:                              ;   Parent Loop BB0_27 Depth=1
                                        ;     Parent Loop BB0_29 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	v_mov_b32_e32 v3, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_165
; %bb.164:                              ;   in Loop: Header=BB0_163 Depth=3
	global_load_b32 v3, v[9:10], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v3, 1, v3
.LBB0_165:                              ;   in Loop: Header=BB0_163 Depth=3
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v3
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB0_167
; %bb.166:                              ;   in Loop: Header=BB0_163 Depth=3
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB0_168
.LBB0_167:                              ;   in Loop: Header=BB0_163 Depth=3
	s_mov_b32 s1, -1
.LBB0_168:                              ; %Flow427
                                        ;   in Loop: Header=BB0_163 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB0_163
; %bb.169:                              ;   in Loop: Header=BB0_29 Depth=2
	global_load_b128 v[11:14], v[5:6], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_173
; %bb.170:                              ;   in Loop: Header=BB0_29 Depth=2
	s_clause 0x2
	global_load_b64 v[5:6], v4, s[18:19] offset:40
	global_load_b64 v[9:10], v4, s[18:19] offset:24 glc
	global_load_b64 v[15:16], v4, s[18:19]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v3, vcc_lo, v5, 1
	v_add_co_ci_u32_e32 v17, vcc_lo, 0, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v13, vcc_lo, v3, s20
	v_add_co_ci_u32_e32 v14, vcc_lo, s21, v17, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[13:14]
	v_dual_cndmask_b32 v14, v14, v17 :: v_dual_cndmask_b32 v13, v13, v3
	v_and_b32_e32 v3, v14, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v5, v13, v5
	v_mul_lo_u32 v3, v3, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v6, v5, 24
	v_mul_lo_u32 v5, v5, 24
	v_add_nc_u32_e32 v3, v6, v3
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v5, vcc_lo, v15, v5
	v_mov_b32_e32 v15, v9
	v_add_co_ci_u32_e32 v6, vcc_lo, v16, v3, vcc_lo
	v_mov_b32_e32 v16, v10
	global_store_b64 v[5:6], v[9:10], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[15:16], v4, v[13:16], s[18:19] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[15:16], v[9:10]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_173
; %bb.171:                              ; %.preheader.i.i.i89.preheader
                                        ;   in Loop: Header=BB0_29 Depth=2
	s_mov_b32 s0, 0
.LBB0_172:                              ; %.preheader.i.i.i89
                                        ;   Parent Loop BB0_27 Depth=1
                                        ;     Parent Loop BB0_29 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_sleep 1
	global_store_b64 v[5:6], v[15:16], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[9:10], v4, v[13:16], s[18:19] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[9:10], v[15:16]
	v_dual_mov_b32 v16, v10 :: v_dual_mov_b32 v15, v9
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB0_172
.LBB0_173:                              ; %__ockl_hostcall_preview.exit.i
                                        ;   in Loop: Header=BB0_29 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
.LBB0_174:                              ; %__ockl_printf_append_string_n.exit
                                        ;   in Loop: Header=BB0_29 Depth=2
	v_mov_b32_e32 v3, v41
	v_mov_b32_e32 v5, 0
	v_mov_b32_e32 v6, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s0, v3
	v_cmp_eq_u32_e64 s0, s0, v3
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_180
; %bb.175:                              ;   in Loop: Header=BB0_29 Depth=2
	global_load_b64 v[15:16], v4, s[18:19] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[5:6], v4, s[18:19] offset:40
	global_load_b64 v[9:10], v4, s[18:19]
	s_mov_b32 s5, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v6, v6, v16
	v_and_b32_e32 v5, v5, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v6, v6, 24
	v_mul_hi_u32 v13, v5, 24
	v_mul_lo_u32 v5, v5, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v6, v13, v6
	s_waitcnt vmcnt(0)
	v_add_co_u32 v5, vcc_lo, v9, v5
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v6, vcc_lo, v10, v6, vcc_lo
	global_load_b64 v[13:14], v[5:6], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[5:6], v4, v[13:16], s[18:19] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[5:6], v[15:16]
	s_cbranch_execz .LBB0_179
; %bb.176:                              ; %.preheader3.i.i.i99.preheader
                                        ;   in Loop: Header=BB0_29 Depth=2
	s_mov_b32 s6, 0
.LBB0_177:                              ; %.preheader3.i.i.i99
                                        ;   Parent Loop BB0_27 Depth=1
                                        ;     Parent Loop BB0_29 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[9:10], v4, s[18:19] offset:40
	global_load_b64 v[13:14], v4, s[18:19]
	v_dual_mov_b32 v16, v6 :: v_dual_mov_b32 v15, v5
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v9, v9, v15
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[5:6], null, v9, 24, v[13:14]
	v_and_b32_e32 v13, v10, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[9:10], null, v13, 24, v[6:7]
	v_mov_b32_e32 v6, v9
	global_load_b64 v[13:14], v[5:6], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[5:6], v4, v[13:16], s[18:19] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[5:6], v[15:16]
	s_or_b32 s6, vcc_lo, s6
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s6
	s_cbranch_execnz .LBB0_177
; %bb.178:                              ; %Flow370
                                        ;   in Loop: Header=BB0_29 Depth=2
	s_or_b32 exec_lo, exec_lo, s6
.LBB0_179:                              ; %Flow372
                                        ;   in Loop: Header=BB0_29 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s5
.LBB0_180:                              ; %.loopexit4.i.i.i93
                                        ;   in Loop: Header=BB0_29 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_clause 0x1
	global_load_b64 v[9:10], v4, s[18:19] offset:40
	global_load_b128 v[15:18], v4, s[18:19]
	v_readfirstlane_b32 s20, v5
	v_readfirstlane_b32 s21, v6
	s_mov_b32 s5, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s6, v9
	v_readfirstlane_b32 s7, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[6:7], s[20:21], s[6:7]
	s_mul_i32 s1, s7, 24
	s_mul_hi_u32 s22, s6, 24
	s_mul_i32 s23, s6, 24
	s_and_saveexec_b32 s24, s0
	s_cbranch_execz .LBB0_182
; %bb.181:                              ;   in Loop: Header=BB0_29 Depth=2
	v_dual_mov_b32 v5, s5 :: v_dual_mov_b32 v6, v4
	s_add_i32 s5, s22, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v9, vcc_lo, v15, s23
	v_add_co_ci_u32_e32 v10, vcc_lo, s5, v16, vcc_lo
	global_store_b128 v[9:10], v[5:8], off offset:8
.LBB0_182:                              ;   in Loop: Header=BB0_29 Depth=2
	s_or_b32 exec_lo, exec_lo, s24
	v_cvt_f32_i32_e32 v5, v36
	s_lshl_b64 s[24:25], s[6:7], 12
	s_mov_b32 s5, s4
	s_mov_b32 s6, s4
	s_mov_b32 s7, s4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_dual_add_f32 v6, 1.0, v42 :: v_dual_mov_b32 v23, s7
	v_cvt_f32_i32_e32 v9, v43
	v_and_or_b32 v11, 0xffffff1d, v11, 34
	v_mov_b32_e32 v21, s5
	v_dual_mul_f32 v5, v6, v5 :: v_dual_mov_b32 v22, s6
	v_mov_b32_e32 v20, s4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_scale_f32 v6, null, v9, v9, v5
	v_rcp_f32_e32 v10, v6
	s_waitcnt_depctr 0xfff
	v_fma_f32 v13, -v6, v10, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v10, v13, v10
	v_div_scale_f32 v14, vcc_lo, v5, v9, v5
	v_mul_f32_e32 v13, v14, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v19, -v6, v13, v14
	v_fmac_f32_e32 v13, v19, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v6, -v6, v13, v14
	v_div_fmas_f32 v6, v6, v10, v13
	s_delay_alu instid0(VALU_DEP_1)
	v_div_fixup_f32 v19, v6, v9, v5
	v_lshlrev_b64 v[5:6], 6, v[3:4]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v3, vcc_lo, v17, s24
	v_add_co_ci_u32_e32 v9, vcc_lo, s25, v18, vcc_lo
	v_cvt_f64_f32_e32 v[13:14], v19
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v5, vcc_lo, v3, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, v9, v6, vcc_lo
	s_clause 0x3
	global_store_b128 v[5:6], v[11:14], off
	global_store_b128 v[5:6], v[20:23], off offset:16
	global_store_b128 v[5:6], v[20:23], off offset:32
	global_store_b128 v[5:6], v[20:23], off offset:48
	s_and_saveexec_b32 s5, s0
	s_cbranch_execz .LBB0_190
; %bb.183:                              ;   in Loop: Header=BB0_29 Depth=2
	s_clause 0x1
	global_load_b64 v[13:14], v4, s[18:19] offset:32 glc
	global_load_b64 v[5:6], v4, s[18:19] offset:40
	v_dual_mov_b32 v11, s20 :: v_dual_mov_b32 v12, s21
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s6, v5
	v_readfirstlane_b32 s7, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[6:7], s[6:7], s[20:21]
	s_mul_i32 s7, s7, 24
	s_mul_hi_u32 s24, s6, 24
	s_mul_i32 s6, s6, 24
	s_add_i32 s24, s24, s7
	v_add_co_u32 v5, vcc_lo, v15, s6
	v_add_co_ci_u32_e32 v6, vcc_lo, s24, v16, vcc_lo
	s_mov_b32 s6, exec_lo
	global_store_b64 v[5:6], v[13:14], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[11:12], v4, v[11:14], s[18:19] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[11:12], v[13:14]
	s_cbranch_execz .LBB0_186
; %bb.184:                              ; %.preheader1.i.i.i97.preheader
                                        ;   in Loop: Header=BB0_29 Depth=2
	s_mov_b32 s7, 0
.LBB0_185:                              ; %.preheader1.i.i.i97
                                        ;   Parent Loop BB0_27 Depth=1
                                        ;     Parent Loop BB0_29 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	v_dual_mov_b32 v9, s20 :: v_dual_mov_b32 v10, s21
	s_sleep 1
	global_store_b64 v[5:6], v[11:12], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[9:10], v4, v[9:12], s[18:19] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[9:10], v[11:12]
	v_dual_mov_b32 v12, v10 :: v_dual_mov_b32 v11, v9
	s_or_b32 s7, vcc_lo, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s7
	s_cbranch_execnz .LBB0_185
.LBB0_186:                              ; %Flow368
                                        ;   in Loop: Header=BB0_29 Depth=2
	s_or_b32 exec_lo, exec_lo, s6
	global_load_b64 v[5:6], v4, s[18:19] offset:16
	s_mov_b32 s7, exec_lo
	s_mov_b32 s6, exec_lo
	v_mbcnt_lo_u32_b32 v3, s7, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v3
	s_cbranch_execz .LBB0_188
; %bb.187:                              ;   in Loop: Header=BB0_29 Depth=2
	s_bcnt1_i32_b32 s7, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v3, s7
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[5:6], v[3:4], off offset:8
.LBB0_188:                              ;   in Loop: Header=BB0_29 Depth=2
	s_or_b32 exec_lo, exec_lo, s6
	s_waitcnt vmcnt(0)
	global_load_b64 v[9:10], v[5:6], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[9:10]
	s_cbranch_vccnz .LBB0_190
; %bb.189:                              ;   in Loop: Header=BB0_29 Depth=2
	global_load_b32 v3, v[5:6], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s6, v3
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[9:10], v[3:4], off
	s_and_b32 m0, s6, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_190:                              ; %Flow369
                                        ;   in Loop: Header=BB0_29 Depth=2
	s_or_b32 exec_lo, exec_lo, s5
	s_add_i32 s22, s22, s1
	v_add_co_u32 v3, vcc_lo, v15, s23
	v_add_co_ci_u32_e32 v6, vcc_lo, s22, v16, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v5, vcc_lo, v3, 20
	v_add_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
.LBB0_191:                              ;   Parent Loop BB0_27 Depth=1
                                        ;     Parent Loop BB0_29 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	v_mov_b32_e32 v3, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_193
; %bb.192:                              ;   in Loop: Header=BB0_191 Depth=3
	global_load_b32 v3, v[5:6], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v3, 1, v3
.LBB0_193:                              ;   in Loop: Header=BB0_191 Depth=3
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v3
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB0_195
; %bb.194:                              ;   in Loop: Header=BB0_191 Depth=3
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB0_196
.LBB0_195:                              ;   in Loop: Header=BB0_191 Depth=3
	s_mov_b32 s1, -1
.LBB0_196:                              ; %Flow363
                                        ;   in Loop: Header=BB0_191 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB0_191
; %bb.197:                              ;   in Loop: Header=BB0_29 Depth=2
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_201
; %bb.198:                              ;   in Loop: Header=BB0_29 Depth=2
	s_clause 0x2
	global_load_b64 v[5:6], v4, s[18:19] offset:40
	global_load_b64 v[13:14], v4, s[18:19] offset:24 glc
	global_load_b64 v[11:12], v4, s[18:19]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v3, vcc_lo, v5, 1
	v_add_co_ci_u32_e32 v15, vcc_lo, 0, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v9, vcc_lo, v3, s20
	v_add_co_ci_u32_e32 v10, vcc_lo, s21, v15, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[9:10]
	v_cndmask_b32_e32 v9, v9, v3, vcc_lo
	v_dual_cndmask_b32 v10, v10, v15 :: v_dual_and_b32 v5, v9, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v3, v10, v6
	v_mul_hi_u32 v6, v5, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v3, v3, 24
	v_mul_lo_u32 v5, v5, 24
	v_add_nc_u32_e32 v3, v6, v3
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v5, vcc_lo, v11, v5
	v_mov_b32_e32 v11, v13
	v_add_co_ci_u32_e32 v6, vcc_lo, v12, v3, vcc_lo
	v_mov_b32_e32 v12, v14
	global_store_b64 v[5:6], v[13:14], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[11:12], v4, v[9:12], s[18:19] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[11:12], v[13:14]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_201
; %bb.199:                              ; %.preheader.i.i.i96.preheader
                                        ;   in Loop: Header=BB0_29 Depth=2
	s_mov_b32 s0, 0
.LBB0_200:                              ; %.preheader.i.i.i96
                                        ;   Parent Loop BB0_27 Depth=1
                                        ;     Parent Loop BB0_29 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_sleep 1
	global_store_b64 v[5:6], v[11:12], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[13:14], v4, v[9:12], s[18:19] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[13:14], v[11:12]
	v_dual_mov_b32 v11, v13 :: v_dual_mov_b32 v12, v14
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB0_200
.LBB0_201:                              ; %Flow361
                                        ;   in Loop: Header=BB0_29 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	v_add_f32_e32 v1, v1, v19
.LBB0_202:                              ; %Flow453
                                        ;   in Loop: Header=BB0_29 Depth=2
	s_or_b32 exec_lo, exec_lo, s34
	global_load_b32 v3, v[33:34], off offset:4
	v_add_nc_u32_e32 v35, 1, v35
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_ge_i32_e32 vcc_lo, v35, v3
	s_or_b32 s33, vcc_lo, s33
	s_and_not1_b32 exec_lo, exec_lo, s33
	s_cbranch_execnz .LBB0_29
; %bb.203:                              ; %Flow455
                                        ;   in Loop: Header=BB0_27 Depth=1
	s_or_b32 exec_lo, exec_lo, s33
.LBB0_204:                              ; %Flow456
                                        ;   in Loop: Header=BB0_27 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s31
; %bb.205:                              ; %._crit_edge128
                                        ;   in Loop: Header=BB0_27 Depth=1
	v_add_co_u32 v5, vcc_lo, s16, v31
	v_add_co_ci_u32_e32 v6, vcc_lo, s17, v32, vcc_lo
	global_store_b32 v[5:6], v1, off
	s_load_b32 s0, s[2:3], 0xc
	s_waitcnt lgkmcnt(0)
	s_and_b32 s0, s0, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v0, s0, v0
	v_cmp_le_i32_e32 vcc_lo, s28, v0
	s_or_b32 s30, vcc_lo, s30
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s30
	s_cbranch_execnz .LBB0_27
.LBB0_206:                              ; %Flow459
	s_or_b32 exec_lo, exec_lo, s29
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z11BetweennessPiS_iS_S_iPf
		.amdhsa_group_segment_fixed_size 8
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 312
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 47
		.amdhsa_next_free_sgpr 38
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z11BetweennessPiS_iS_S_iPf, .Lfunc_end0-_Z11BetweennessPiS_iS_S_iPf
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 8112
; NumSgprs: 40
; NumVgprs: 47
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 8 bytes/workgroup (compile time only)
; SGPRBlocks: 4
; VGPRBlocks: 5
; NumSGPRsForWavesPerEU: 40
; NumVGPRsForWavesPerEU: 47
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	.str,@object                    ; @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.str:
	.asciz	"%d "
	.size	.str, 4

	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .offset:         40
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         48
        .size:           8
        .value_kind:     global_buffer
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         60
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         64
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         68
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         70
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         72
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         74
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         76
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         78
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         112
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         120
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         136
        .size:           8
        .value_kind:     hidden_hostcall_buffer
    .group_segment_fixed_size: 8
    .kernarg_segment_align: 8
    .kernarg_segment_size: 312
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z11BetweennessPiS_iS_S_iPf
    .private_segment_fixed_size: 0
    .sgpr_count:     40
    .sgpr_spill_count: 0
    .symbol:         _Z11BetweennessPiS_iS_S_iPf.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     47
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
