#include <stdio.h>
#include <stdlib.h>
#include <cuda_runtime.h>

#define WINDOW_WIDTH 9
#define WINDOW_HEIGHT 7
#define IMAGE_WIDTH 1280
#define IMAGE_HEIGHT 720

#define BLOCK_SIZE 128
#define LINES_PER_BLOCK 16

__global__ static void censusTransform(int width, int height, int * ret)
{
    int half_kw = WINDOW_WIDTH /2;
    int half_kh = WINDOW_HEIGHT /2 ;

    int tid = threadIdx.x;
    int x0 = blockIdx.x * (BLOCK_SIZE - WINDOW_WIDTH + 1) - half_kw;
    int y0 = blockIdx.y * LINES_PER_BLOCK;

    printf("block Dim (%d %d) (%d %d) \n", blockDim.x, blockDim.y, blockIdx.x, blockIdx.y);
    //printf("block id (%d %d) \n", blockIdx.x, blockIdx.y);
    for (int i = 0; i < WINDOW_HEIGHT; ++i) {
        int x = x0 + tid;
	int y = y0 - half_kh + i;
        int value = 0;
	
        if (0 <= x && x < IMAGE_WIDTH && 0 <= y && y < IMAGE_HEIGHT) {
	    value = x+y*IMAGE_WIDTH;
	    ret[i] = value / IMAGE_WIDTH;
	    ret[WINDOW_HEIGHT + i] = value % IMAGE_WIDTH;
            //printf("row %d  col %d \n", value / IMAGE_WIDTH, value % IMAGE_WIDTH);
        }



    }
    __syncthreads();
}

void censusDemo(void)
{
    printf("censusDemo +++++\n");
    int * ret = 0;
    int host_ret[WINDOW_HEIGHT*2] = {0};
    
    cudaMalloc((void**) &ret, sizeof(int)*WINDOW_HEIGHT*2);
    
    int width_per_block = BLOCK_SIZE - WINDOW_WIDTH + 1;
    int height_per_block = LINES_PER_BLOCK;
    dim3 grid((IMAGE_WIDTH + width_per_block - 1) / width_per_block, (IMAGE_HEIGHT + height_per_block - 1) / height_per_block);
    //dim3 grid(1,1);
    dim3 block(BLOCK_SIZE);

    censusTransform<<<grid,block>>>(IMAGE_WIDTH, IMAGE_HEIGHT, ret);

    cudaMemcpy(host_ret, ret, sizeof(int)*WINDOW_HEIGHT*2, cudaMemcpyDeviceToHost);
    for (int i = 0; i < WINDOW_HEIGHT; i++) {
        printf("(%d  %d)", host_ret[i], host_ret[WINDOW_HEIGHT+i]);

    }

    cudaFree(ret);

}

	.file	"tmpxft_00374550_00000000-6_censusDemo.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2030:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.type	_ZL37__device_stub__Z15censusTransformiiPiiiPi, @function
_ZL37__device_stub__Z15censusTransformiiPiiiPi:
.LFB2052:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movl	%edi, 12(%rsp)
	leaq	24(%rsp), %rcx
	leaq	32(%rsp), %rdi
	movl	%esi, 8(%rsp)
	leaq	44(%rsp), %rsi
	movq	%rdx, (%rsp)
	leaq	16(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	12(%rsp), %rax
	movl	$1, 40(%rsp)
	movq	%rax, 80(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 88(%rsp)
	movq	%rsp, %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 32(%rsp)
	movq	%rax, 44(%rsp)
	movl	$1, 52(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	24(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_ZL15censusTransformiiPi(%rip), %rdi
	pushq	24(%rsp)
	.cfi_def_cfa_offset 144
	movq	60(%rsp), %rcx
	movl	68(%rsp), %r8d
	movq	48(%rsp), %rsi
	movl	56(%rsp), %edx
	leaq	96(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L2:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2052:
	.size	_ZL37__device_stub__Z15censusTransformiiPiiiPi, .-_ZL37__device_stub__Z15censusTransformiiPiiiPi
	.type	_ZL15censusTransformiiPi, @function
_ZL15censusTransformiiPi:
.LFB2053:
	.cfi_startproc
	endbr64
	jmp	_ZL37__device_stub__Z15censusTransformiiPiiiPi
	.cfi_endproc
.LFE2053:
	.size	_ZL15censusTransformiiPi, .-_ZL15censusTransformiiPi
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"censusDemo +++++\n"
.LC1:
	.string	"(%d  %d)"
	.text
	.globl	_Z10censusDemov
	.type	_Z10censusDemov, @function
_Z10censusDemov:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%r12
	.cfi_def_cfa_offset 16
	.cfi_offset 12, -16
	leaq	.LC0(%rip), %rsi
	movl	$2, %edi
	pushq	%rbp
	.cfi_def_cfa_offset 24
	.cfi_offset 6, -24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset 3, -32
	subq	$96, %rsp
	.cfi_def_cfa_offset 128
	movq	%fs:40, %rax
	movq	%rax, 88(%rsp)
	xorl	%eax, %eax
	leaq	32(%rsp), %rbx
	call	__printf_chk@PLT
	xorl	%eax, %eax
	leaq	32(%rsp), %rdi
	movl	$14, %ecx
	movq	%rax, (%rsp)
	xorl	%eax, %eax
	movl	$56, %esi
	rep stosl
	movq	%rsp, %rdi
	call	cudaMalloc@PLT
	movl	$33554433, %edx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	salq	$7, %rdx
	movl	$1, %ecx
	movabsq	$193273528331, %rdi
	movl	$1, %esi
	movq	%rdi, 8(%rsp)
	movl	$1, 16(%rsp)
	movq	%rdx, 20(%rsp)
	movl	$1, 28(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L9
	movq	(%rsp), %rdx
	movl	$720, %esi
	movl	$1280, %edi
	call	_ZL37__device_stub__Z15censusTransformiiPiiiPi
.L9:
	movq	(%rsp), %rsi
	movl	$2, %ecx
	movl	$56, %edx
	movq	%rbx, %rdi
	leaq	60(%rsp), %rbp
	leaq	.LC1(%rip), %r12
	call	cudaMemcpy@PLT
.L10:
	movl	28(%rbx), %ecx
	movl	(%rbx), %edx
	movq	%r12, %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	addq	$4, %rbx
	call	__printf_chk@PLT
	cmpq	%rbp, %rbx
	jne	.L10
	movq	(%rsp), %rdi
	call	cudaFree@PLT
	movq	88(%rsp), %rax
	subq	%fs:40, %rax
	je	.L11
	call	__stack_chk_fail@PLT
.L11:
	addq	$96, %rsp
	.cfi_def_cfa_offset 32
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2027:
	.size	_Z10censusDemov, .-_Z10censusDemov
	.section	.rodata.str1.1
.LC2:
	.string	"_Z15censusTransformiiPi"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC2(%rip), %rdx
	movq	%rax, %rdi
	leaq	_ZL15censusTransformiiPi(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2055:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>

#define WINDOW_WIDTH 9
#define WINDOW_HEIGHT 7
#define IMAGE_WIDTH 1280
#define IMAGE_HEIGHT 720

#define BLOCK_SIZE 128
#define LINES_PER_BLOCK 16

__global__ static void censusTransform(int width, int height, int * ret)
{
    int half_kw = WINDOW_WIDTH /2;
    int half_kh = WINDOW_HEIGHT /2 ;

    int tid = threadIdx.x;
    int x0 = blockIdx.x * (BLOCK_SIZE - WINDOW_WIDTH + 1) - half_kw;
    int y0 = blockIdx.y * LINES_PER_BLOCK;

    printf("block Dim (%d %d) (%d %d) \n", blockDim.x, blockDim.y, blockIdx.x, blockIdx.y);
    //printf("block id (%d %d) \n", blockIdx.x, blockIdx.y);
    for (int i = 0; i < WINDOW_HEIGHT; ++i) {
        int x = x0 + tid;
	int y = y0 - half_kh + i;
        int value = 0;
	
        if (0 <= x && x < IMAGE_WIDTH && 0 <= y && y < IMAGE_HEIGHT) {
	    value = x+y*IMAGE_WIDTH;
	    ret[i] = value / IMAGE_WIDTH;
	    ret[WINDOW_HEIGHT + i] = value % IMAGE_WIDTH;
            //printf("row %d  col %d \n", value / IMAGE_WIDTH, value % IMAGE_WIDTH);
        }



    }
    __syncthreads();
}

void censusDemo(void)
{
    printf("censusDemo +++++\n");
    int * ret = 0;
    int host_ret[WINDOW_HEIGHT*2] = {0};
    
    hipMalloc((void**) &ret, sizeof(int)*WINDOW_HEIGHT*2);
    
    int width_per_block = BLOCK_SIZE - WINDOW_WIDTH + 1;
    int height_per_block = LINES_PER_BLOCK;
    dim3 grid((IMAGE_WIDTH + width_per_block - 1) / width_per_block, (IMAGE_HEIGHT + height_per_block - 1) / height_per_block);
    //dim3 grid(1,1);
    dim3 block(BLOCK_SIZE);

    censusTransform<<<grid,block>>>(IMAGE_WIDTH, IMAGE_HEIGHT, ret);

    hipMemcpy(host_ret, ret, sizeof(int)*WINDOW_HEIGHT*2, hipMemcpyDeviceToHost);
    for (int i = 0; i < WINDOW_HEIGHT; i++) {
        printf("(%d  %d)", host_ret[i], host_ret[WINDOW_HEIGHT+i]);

    }

    hipFree(ret);

}

	.text
	.file	"censusDemo.hip"
	.globl	_Z10censusDemov                 # -- Begin function _Z10censusDemov
	.type	_Z10censusDemov,@function
_Z10censusDemov:                        # @_Z10censusDemov
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$80, %rsp
	.cfi_def_cfa_offset 96
	.cfi_offset %rbx, -16
	movl	$.Lstr, %edi
	callq	puts@PLT
	xorl	%eax, %eax
	leaq	8(%rsp), %rdi
	movq	%rax, (%rdi)
	movq	%rax, 64(%rsp)
	xorps	%xmm0, %xmm0
	movaps	%xmm0, 48(%rsp)
	movaps	%xmm0, 32(%rsp)
	movaps	%xmm0, 16(%rsp)
	movl	$56, %esi
	callq	hipMalloc
	movabsq	$193273528331, %rdi             # imm = 0x2D0000000B
	movabsq	$4294967424, %rdx               # imm = 0x100000080
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB0_2
# %bb.1:
	movq	8(%rsp), %rdx
	movl	$1280, %edi                     # imm = 0x500
	movl	$720, %esi                      # imm = 0x2D0
	callq	_ZL30__device_stub__censusTransformiiPi
.LBB0_2:
	movq	8(%rsp), %rsi
	leaq	16(%rsp), %rdi
	movl	$56, %edx
	movl	$2, %ecx
	callq	hipMemcpy
	xorl	%ebx, %ebx
.LBB0_3:                                # =>This Inner Loop Header: Depth=1
	movl	16(%rsp,%rbx,4), %esi
	movl	44(%rsp,%rbx,4), %edx
	movl	$.L.str.1, %edi
	xorl	%eax, %eax
	callq	printf
	incq	%rbx
	cmpq	$7, %rbx
	jne	.LBB0_3
# %bb.4:
	movq	8(%rsp), %rdi
	callq	hipFree
	addq	$80, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z10censusDemov, .Lfunc_end0-_Z10censusDemov
	.cfi_endproc
                                        # -- End function
	.type	_ZL30__device_stub__censusTransformiiPi,@function # -- Begin function _ZL30__device_stub__censusTransformiiPi
_ZL30__device_stub__censusTransformiiPi: # @_ZL30__device_stub__censusTransformiiPi
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$96, %rsp
	.cfi_def_cfa_offset 144
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	4(%rsp), %rax
	movl	%edi, (%rax)
	movq	%rsp, %rcx
	movl	%esi, (%rcx)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_ZL15censusTransformiiPi, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$112, %rsp
	.cfi_adjust_cfa_offset -112
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_ZL30__device_stub__censusTransformiiPi, .Lfunc_end1-_ZL30__device_stub__censusTransformiiPi
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_ZL15censusTransformiiPi, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_ZL15censusTransformiiPi,@object # @_ZL15censusTransformiiPi
	.section	.rodata,"a",@progbits
	.p2align	3, 0x0
_ZL15censusTransformiiPi:
	.quad	_ZL30__device_stub__censusTransformiiPi
	.size	_ZL15censusTransformiiPi, 8

	.type	.L.str.1,@object                # @.str.1
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str.1:
	.asciz	"(%d  %d)"
	.size	.L.str.1, 9

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_ZL15censusTransformiiPi"
	.size	.L__unnamed_1, 25

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.type	.Lstr,@object                   # @str
	.section	.rodata.str1.1,"aMS",@progbits,1
.Lstr:
	.asciz	"censusDemo +++++"
	.size	.Lstr, 17

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _ZL30__device_stub__censusTransformiiPi
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _ZL15censusTransformiiPi
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.section	.text._ZL15censusTransformiiPi,"axG",@progbits,_ZL15censusTransformiiPi,comdat
	.globl	_ZL15censusTransformiiPi        ; -- Begin function _ZL15censusTransformiiPi
	.p2align	8
	.type	_ZL15censusTransformiiPi,@function
_ZL15censusTransformiiPi:               ; @_ZL15censusTransformiiPi
; %bb.0:
	s_clause 0x1
	s_load_b32 s18, s[0:1], 0x1c
	s_load_b64 s[4:5], s[0:1], 0x60
	v_mbcnt_lo_u32_b32 v3, -1, 0
	v_mov_b32_e32 v1, 0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v8, v3
	;;#ASMSTART
	;;#ASMEND
	v_readfirstlane_b32 s2, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_eq_u32_e64 s2, s2, v8
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_6
; %bb.1:
	v_mov_b32_e32 v4, 0
	s_mov_b32 s6, exec_lo
	s_waitcnt lgkmcnt(0)
	global_load_b64 v[11:12], v4, s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[1:2], v4, s[4:5] offset:40
	global_load_b64 v[5:6], v4, s[4:5]
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v1, v1, v11
	v_and_b32_e32 v2, v2, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v7, v1, 24
	v_mul_lo_u32 v2, v2, 24
	v_mul_lo_u32 v1, v1, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v2, v7, v2
	s_waitcnt vmcnt(0)
	v_add_co_u32 v1, vcc_lo, v5, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, v6, v2, vcc_lo
	global_load_b64 v[9:10], v[1:2], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[1:2], v4, v[9:12], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[1:2], v[11:12]
	s_cbranch_execz .LBB0_5
; %bb.2:                                ; %.preheader3.i.i.i.preheader
	s_mov_b32 s7, 0
.LBB0_3:                                ; %.preheader3.i.i.i
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[5:6], v4, s[4:5] offset:40
	global_load_b64 v[9:10], v4, s[4:5]
	v_dual_mov_b32 v12, v2 :: v_dual_mov_b32 v11, v1
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v5, v5, v11
	v_and_b32_e32 v7, v6, v12
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, v5, 24, v[9:10]
	v_mad_u64_u32 v[5:6], null, v7, 24, v[2:3]
	s_delay_alu instid0(VALU_DEP_1)
	v_mov_b32_e32 v2, v5
	global_load_b64 v[9:10], v[1:2], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[1:2], v4, v[9:12], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[1:2], v[11:12]
	s_or_b32 s7, vcc_lo, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s7
	s_cbranch_execnz .LBB0_3
; %bb.4:                                ; %Flow500
	s_or_b32 exec_lo, exec_lo, s7
.LBB0_5:                                ; %Flow502
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s6
.LBB0_6:                                ; %.loopexit4.i.i.i
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s3
	v_mov_b32_e32 v9, 0
	v_readfirstlane_b32 s6, v1
	v_readfirstlane_b32 s7, v2
	s_mov_b32 s12, exec_lo
	s_waitcnt lgkmcnt(0)
	s_clause 0x1
	global_load_b64 v[10:11], v9, s[4:5] offset:40
	global_load_b128 v[4:7], v9, s[4:5]
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s8, v10
	v_readfirstlane_b32 s9, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[8:9], s[6:7], s[8:9]
	s_mul_i32 s3, s9, 24
	s_mul_hi_u32 s10, s8, 24
	s_mul_i32 s11, s8, 24
	s_and_saveexec_b32 s13, s2
	s_cbranch_execz .LBB0_8
; %bb.7:
	v_dual_mov_b32 v10, s12 :: v_dual_mov_b32 v11, v9
	s_add_i32 s12, s10, s3
	s_waitcnt vmcnt(0)
	v_add_co_u32 v1, vcc_lo, v4, s11
	v_add_co_ci_u32_e32 v2, vcc_lo, s12, v5, vcc_lo
	v_dual_mov_b32 v12, 2 :: v_dual_mov_b32 v13, 1
	global_store_b128 v[1:2], v[10:13], off offset:8
.LBB0_8:
	s_or_b32 exec_lo, exec_lo, s13
	s_lshl_b64 s[8:9], s[8:9], 12
	v_lshlrev_b64 v[1:2], 6, v[8:9]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v6, vcc_lo, v6, s8
	v_add_co_ci_u32_e32 v7, vcc_lo, s9, v7, vcc_lo
	s_mov_b32 s20, 0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, v6, v1
	s_mov_b32 s21, s20
	s_mov_b32 s22, s20
	s_mov_b32 s23, s20
	v_add_co_ci_u32_e32 v2, vcc_lo, v7, v2, vcc_lo
	v_dual_mov_b32 v8, 33 :: v_dual_mov_b32 v11, v9
	v_mov_b32_e32 v10, v9
	v_dual_mov_b32 v12, s20 :: v_dual_mov_b32 v15, s23
	v_dual_mov_b32 v13, s21 :: v_dual_mov_b32 v14, s22
	s_clause 0x3
	global_store_b128 v[1:2], v[8:11], off
	global_store_b128 v[1:2], v[12:15], off offset:16
	global_store_b128 v[1:2], v[12:15], off offset:32
	global_store_b128 v[1:2], v[12:15], off offset:48
	s_and_saveexec_b32 s8, s2
	s_cbranch_execz .LBB0_16
; %bb.9:
	v_mov_b32_e32 v12, 0
	s_mov_b32 s9, exec_lo
	s_clause 0x1
	global_load_b64 v[15:16], v12, s[4:5] offset:32 glc
	global_load_b64 v[6:7], v12, s[4:5] offset:40
	v_dual_mov_b32 v13, s6 :: v_dual_mov_b32 v14, s7
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v7, s7, v7
	v_and_b32_e32 v6, s6, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v7, v7, 24
	v_mul_hi_u32 v8, v6, 24
	v_mul_lo_u32 v6, v6, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v7, v8, v7
	v_add_co_u32 v10, vcc_lo, v4, v6
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v11, vcc_lo, v5, v7, vcc_lo
	global_store_b64 v[10:11], v[15:16], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[8:9], v12, v[13:16], s[4:5] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[8:9], v[15:16]
	s_cbranch_execz .LBB0_12
; %bb.10:                               ; %.preheader1.i.i.i.preheader
	s_mov_b32 s12, 0
.LBB0_11:                               ; %.preheader1.i.i.i
                                        ; =>This Inner Loop Header: Depth=1
	v_dual_mov_b32 v6, s6 :: v_dual_mov_b32 v7, s7
	s_sleep 1
	global_store_b64 v[10:11], v[8:9], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[6:7], v12, v[6:9], s[4:5] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[8:9]
	v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6
	s_or_b32 s12, vcc_lo, s12
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s12
	s_cbranch_execnz .LBB0_11
.LBB0_12:                               ; %Flow498
	s_or_b32 exec_lo, exec_lo, s9
	v_mov_b32_e32 v9, 0
	s_mov_b32 s12, exec_lo
	s_mov_b32 s9, exec_lo
	v_mbcnt_lo_u32_b32 v8, s12, 0
	global_load_b64 v[6:7], v9, s[4:5] offset:16
	v_cmpx_eq_u32_e32 0, v8
	s_cbranch_execz .LBB0_14
; %bb.13:
	s_bcnt1_i32_b32 s12, s12
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v8, s12
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[6:7], v[8:9], off offset:8
.LBB0_14:
	s_or_b32 exec_lo, exec_lo, s9
	s_waitcnt vmcnt(0)
	global_load_b64 v[8:9], v[6:7], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[8:9]
	s_cbranch_vccnz .LBB0_16
; %bb.15:
	global_load_b32 v6, v[6:7], off offset:24
	v_mov_b32_e32 v7, 0
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s9, v6
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[8:9], v[6:7], off
	s_and_b32 m0, s9, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_16:                               ; %Flow499
	s_or_b32 exec_lo, exec_lo, s8
	s_add_i32 s10, s10, s3
	v_add_co_u32 v4, vcc_lo, v4, s11
	v_add_co_ci_u32_e32 v5, vcc_lo, s10, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, v4, 20
	v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
.LBB0_17:                               ; =>This Inner Loop Header: Depth=1
	v_mov_b32_e32 v6, 1
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_19
; %bb.18:                               ;   in Loop: Header=BB0_17 Depth=1
	global_load_b32 v6, v[4:5], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v6, 1, v6
.LBB0_19:                               ;   in Loop: Header=BB0_17 Depth=1
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s3, v6
	s_cmp_eq_u32 s3, 0
	s_cbranch_scc1 .LBB0_21
; %bb.20:                               ;   in Loop: Header=BB0_17 Depth=1
	s_mov_b32 s3, 0
	s_sleep 1
	s_branch .LBB0_22
.LBB0_21:                               ;   in Loop: Header=BB0_17 Depth=1
	s_mov_b32 s3, -1
.LBB0_22:                               ; %Flow493
                                        ;   in Loop: Header=BB0_17 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s3
	s_cbranch_vccnz .LBB0_17
; %bb.23:
	global_load_b64 v[4:5], v[1:2], off
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_27
; %bb.24:
	v_mov_b32_e32 v10, 0
	s_clause 0x2
	global_load_b64 v[1:2], v10, s[4:5] offset:40
	global_load_b64 v[11:12], v10, s[4:5] offset:24 glc
	global_load_b64 v[8:9], v10, s[4:5]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v13, vcc_lo, v1, 1
	v_add_co_ci_u32_e32 v14, vcc_lo, 0, v2, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v6, vcc_lo, v13, s6
	v_add_co_ci_u32_e32 v7, vcc_lo, s7, v14, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[6:7]
	v_dual_cndmask_b32 v7, v7, v14 :: v_dual_cndmask_b32 v6, v6, v13
	v_and_b32_e32 v2, v7, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v1, v6, v1
	v_mul_lo_u32 v2, v2, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v13, v1, 24
	v_mul_lo_u32 v1, v1, 24
	v_add_nc_u32_e32 v2, v13, v2
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v1, vcc_lo, v8, v1
	v_mov_b32_e32 v8, v11
	v_add_co_ci_u32_e32 v2, vcc_lo, v9, v2, vcc_lo
	v_mov_b32_e32 v9, v12
	global_store_b64 v[1:2], v[11:12], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[8:9], v10, v[6:9], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[8:9], v[11:12]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_27
; %bb.25:                               ; %.preheader.i.i.i.preheader
	s_mov_b32 s2, 0
.LBB0_26:                               ; %.preheader.i.i.i
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	global_store_b64 v[1:2], v[8:9], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[11:12], v10, v[6:9], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[11:12], v[8:9]
	v_dual_mov_b32 v8, v11 :: v_dual_mov_b32 v9, v12
	s_or_b32 s2, vcc_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s2
	s_cbranch_execnz .LBB0_26
.LBB0_27:                               ; %__ockl_printf_begin.exit
	s_or_b32 exec_lo, exec_lo, s3
	s_getpc_b64 s[6:7]
	s_add_u32 s6, s6, .str@rel32@lo+4
	s_addc_u32 s7, s7, .str@rel32@hi+12
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u64 s[6:7], 0
	s_cbranch_scc0 .LBB0_113
; %bb.28:
	s_waitcnt vmcnt(0)
	v_dual_mov_b32 v7, v5 :: v_dual_and_b32 v32, 2, v4
	v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v11, 1
	v_and_b32_e32 v6, -3, v4
	v_mov_b32_e32 v10, 2
	s_mov_b64 s[8:9], 28
.LBB0_29:                               ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_32 Depth 2
                                        ;     Child Loop BB0_39 Depth 2
                                        ;     Child Loop BB0_47 Depth 2
                                        ;     Child Loop BB0_55 Depth 2
                                        ;     Child Loop BB0_63 Depth 2
                                        ;     Child Loop BB0_71 Depth 2
                                        ;     Child Loop BB0_79 Depth 2
                                        ;     Child Loop BB0_87 Depth 2
                                        ;     Child Loop BB0_95 Depth 2
                                        ;     Child Loop BB0_101 Depth 2
                                        ;     Child Loop BB0_110 Depth 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_u64_e64 s2, s[8:9], 56
                                        ; implicit-def: $vgpr14_vgpr15
                                        ; implicit-def: $sgpr20
	s_and_b32 s2, s2, exec_lo
	s_cselect_b32 s10, s8, 56
	s_cselect_b32 s11, s9, 0
	s_cmp_gt_u32 s10, 7
	s_mov_b32 s2, -1
	s_cbranch_scc1 .LBB0_34
; %bb.30:                               ;   in Loop: Header=BB0_29 Depth=1
	v_mov_b32_e32 v14, 0
	v_mov_b32_e32 v15, 0
	s_cmp_eq_u32 s10, 0
	s_cbranch_scc1 .LBB0_33
; %bb.31:                               ; %.preheader31.i.preheader
                                        ;   in Loop: Header=BB0_29 Depth=1
	s_lshl_b64 s[2:3], s[10:11], 3
	s_mov_b64 s[12:13], 0
	s_mov_b64 s[16:17], s[6:7]
.LBB0_32:                               ; %.preheader31.i
                                        ;   Parent Loop BB0_29 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	global_load_u8 v1, v2, s[16:17]
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v1, 0xffff, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_lshlrev_b64 v[8:9], s12, v[1:2]
	s_add_u32 s12, s12, 8
	s_addc_u32 s13, s13, 0
	s_add_u32 s16, s16, 1
	s_addc_u32 s17, s17, 0
	s_cmp_lg_u32 s2, s12
	v_or_b32_e32 v14, v8, v14
	v_or_b32_e32 v15, v9, v15
	s_cbranch_scc1 .LBB0_32
.LBB0_33:                               ; %Flow469
                                        ;   in Loop: Header=BB0_29 Depth=1
	s_mov_b32 s2, 0
	s_mov_b32 s20, 0
.LBB0_34:                               ; %Flow471
                                        ;   in Loop: Header=BB0_29 Depth=1
	s_and_not1_b32 vcc_lo, exec_lo, s2
	s_mov_b64 s[2:3], s[6:7]
	s_cbranch_vccnz .LBB0_36
; %bb.35:                               ;   in Loop: Header=BB0_29 Depth=1
	global_load_b64 v[14:15], v2, s[6:7]
	s_add_i32 s20, s10, -8
	s_add_u32 s2, s6, 8
	s_addc_u32 s3, s7, 0
.LBB0_36:                               ; %.loopexit32.i
                                        ;   in Loop: Header=BB0_29 Depth=1
	s_cmp_gt_u32 s20, 7
	s_cbranch_scc1 .LBB0_41
; %bb.37:                               ;   in Loop: Header=BB0_29 Depth=1
	v_mov_b32_e32 v16, 0
	v_mov_b32_e32 v17, 0
	s_cmp_eq_u32 s20, 0
	s_cbranch_scc1 .LBB0_40
; %bb.38:                               ; %.preheader29.i.preheader
                                        ;   in Loop: Header=BB0_29 Depth=1
	s_mov_b64 s[12:13], 0
	s_mov_b64 s[16:17], 0
.LBB0_39:                               ; %.preheader29.i
                                        ;   Parent Loop BB0_29 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s22, s2, s16
	s_addc_u32 s23, s3, s17
	s_add_u32 s16, s16, 1
	global_load_u8 v1, v2, s[22:23]
	s_addc_u32 s17, s17, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v1, 0xffff, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[8:9], s12, v[1:2]
	s_add_u32 s12, s12, 8
	s_addc_u32 s13, s13, 0
	s_cmp_lg_u32 s20, s16
	v_or_b32_e32 v16, v8, v16
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v17, v9, v17
	s_cbranch_scc1 .LBB0_39
.LBB0_40:                               ; %Flow464
                                        ;   in Loop: Header=BB0_29 Depth=1
	s_mov_b32 s12, 0
	s_mov_b32 s19, 0
	s_branch .LBB0_42
.LBB0_41:                               ;   in Loop: Header=BB0_29 Depth=1
	s_mov_b32 s12, -1
                                        ; implicit-def: $vgpr16_vgpr17
                                        ; implicit-def: $sgpr19
.LBB0_42:                               ; %Flow466
                                        ;   in Loop: Header=BB0_29 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s12
	s_cbranch_vccnz .LBB0_44
; %bb.43:                               ;   in Loop: Header=BB0_29 Depth=1
	global_load_b64 v[16:17], v2, s[2:3]
	s_add_i32 s19, s20, -8
	s_add_u32 s2, s2, 8
	s_addc_u32 s3, s3, 0
.LBB0_44:                               ; %.loopexit30.i
                                        ;   in Loop: Header=BB0_29 Depth=1
	s_cmp_gt_u32 s19, 7
	s_cbranch_scc1 .LBB0_49
; %bb.45:                               ;   in Loop: Header=BB0_29 Depth=1
	v_mov_b32_e32 v18, 0
	v_mov_b32_e32 v19, 0
	s_cmp_eq_u32 s19, 0
	s_cbranch_scc1 .LBB0_48
; %bb.46:                               ; %.preheader27.i.preheader
                                        ;   in Loop: Header=BB0_29 Depth=1
	s_mov_b64 s[12:13], 0
	s_mov_b64 s[16:17], 0
.LBB0_47:                               ; %.preheader27.i
                                        ;   Parent Loop BB0_29 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s20, s2, s16
	s_addc_u32 s21, s3, s17
	s_add_u32 s16, s16, 1
	global_load_u8 v1, v2, s[20:21]
	s_addc_u32 s17, s17, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v1, 0xffff, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[8:9], s12, v[1:2]
	s_add_u32 s12, s12, 8
	s_addc_u32 s13, s13, 0
	s_cmp_lg_u32 s19, s16
	v_or_b32_e32 v18, v8, v18
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v19, v9, v19
	s_cbranch_scc1 .LBB0_47
.LBB0_48:                               ; %Flow459
                                        ;   in Loop: Header=BB0_29 Depth=1
	s_mov_b32 s12, 0
	s_mov_b32 s20, 0
	s_branch .LBB0_50
.LBB0_49:                               ;   in Loop: Header=BB0_29 Depth=1
	s_mov_b32 s12, -1
                                        ; implicit-def: $sgpr20
.LBB0_50:                               ; %Flow461
                                        ;   in Loop: Header=BB0_29 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s12
	s_cbranch_vccnz .LBB0_52
; %bb.51:                               ;   in Loop: Header=BB0_29 Depth=1
	global_load_b64 v[18:19], v2, s[2:3]
	s_add_i32 s20, s19, -8
	s_add_u32 s2, s2, 8
	s_addc_u32 s3, s3, 0
.LBB0_52:                               ; %.loopexit28.i
                                        ;   in Loop: Header=BB0_29 Depth=1
	s_cmp_gt_u32 s20, 7
	s_cbranch_scc1 .LBB0_57
; %bb.53:                               ;   in Loop: Header=BB0_29 Depth=1
	v_mov_b32_e32 v20, 0
	v_mov_b32_e32 v21, 0
	s_cmp_eq_u32 s20, 0
	s_cbranch_scc1 .LBB0_56
; %bb.54:                               ; %.preheader25.i.preheader
                                        ;   in Loop: Header=BB0_29 Depth=1
	s_mov_b64 s[12:13], 0
	s_mov_b64 s[16:17], 0
.LBB0_55:                               ; %.preheader25.i
                                        ;   Parent Loop BB0_29 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s22, s2, s16
	s_addc_u32 s23, s3, s17
	s_add_u32 s16, s16, 1
	global_load_u8 v1, v2, s[22:23]
	s_addc_u32 s17, s17, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v1, 0xffff, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[8:9], s12, v[1:2]
	s_add_u32 s12, s12, 8
	s_addc_u32 s13, s13, 0
	s_cmp_lg_u32 s20, s16
	v_or_b32_e32 v20, v8, v20
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v21, v9, v21
	s_cbranch_scc1 .LBB0_55
.LBB0_56:                               ; %Flow454
                                        ;   in Loop: Header=BB0_29 Depth=1
	s_mov_b32 s12, 0
	s_mov_b32 s19, 0
	s_branch .LBB0_58
.LBB0_57:                               ;   in Loop: Header=BB0_29 Depth=1
	s_mov_b32 s12, -1
                                        ; implicit-def: $vgpr20_vgpr21
                                        ; implicit-def: $sgpr19
.LBB0_58:                               ; %Flow456
                                        ;   in Loop: Header=BB0_29 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s12
	s_cbranch_vccnz .LBB0_60
; %bb.59:                               ;   in Loop: Header=BB0_29 Depth=1
	global_load_b64 v[20:21], v2, s[2:3]
	s_add_i32 s19, s20, -8
	s_add_u32 s2, s2, 8
	s_addc_u32 s3, s3, 0
.LBB0_60:                               ; %.loopexit26.i
                                        ;   in Loop: Header=BB0_29 Depth=1
	s_cmp_gt_u32 s19, 7
	s_cbranch_scc1 .LBB0_65
; %bb.61:                               ;   in Loop: Header=BB0_29 Depth=1
	v_mov_b32_e32 v22, 0
	v_mov_b32_e32 v23, 0
	s_cmp_eq_u32 s19, 0
	s_cbranch_scc1 .LBB0_64
; %bb.62:                               ; %.preheader23.i.preheader
                                        ;   in Loop: Header=BB0_29 Depth=1
	s_mov_b64 s[12:13], 0
	s_mov_b64 s[16:17], 0
.LBB0_63:                               ; %.preheader23.i
                                        ;   Parent Loop BB0_29 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s20, s2, s16
	s_addc_u32 s21, s3, s17
	s_add_u32 s16, s16, 1
	global_load_u8 v1, v2, s[20:21]
	s_addc_u32 s17, s17, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v1, 0xffff, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[8:9], s12, v[1:2]
	s_add_u32 s12, s12, 8
	s_addc_u32 s13, s13, 0
	s_cmp_lg_u32 s19, s16
	v_or_b32_e32 v22, v8, v22
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v23, v9, v23
	s_cbranch_scc1 .LBB0_63
.LBB0_64:                               ; %Flow449
                                        ;   in Loop: Header=BB0_29 Depth=1
	s_mov_b32 s12, 0
	s_mov_b32 s20, 0
	s_branch .LBB0_66
.LBB0_65:                               ;   in Loop: Header=BB0_29 Depth=1
	s_mov_b32 s12, -1
                                        ; implicit-def: $sgpr20
.LBB0_66:                               ; %Flow451
                                        ;   in Loop: Header=BB0_29 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s12
	s_cbranch_vccnz .LBB0_68
; %bb.67:                               ;   in Loop: Header=BB0_29 Depth=1
	global_load_b64 v[22:23], v2, s[2:3]
	s_add_i32 s20, s19, -8
	s_add_u32 s2, s2, 8
	s_addc_u32 s3, s3, 0
.LBB0_68:                               ; %.loopexit24.i
                                        ;   in Loop: Header=BB0_29 Depth=1
	s_cmp_gt_u32 s20, 7
	s_cbranch_scc1 .LBB0_73
; %bb.69:                               ;   in Loop: Header=BB0_29 Depth=1
	v_mov_b32_e32 v24, 0
	v_mov_b32_e32 v25, 0
	s_cmp_eq_u32 s20, 0
	s_cbranch_scc1 .LBB0_72
; %bb.70:                               ; %.preheader21.i.preheader
                                        ;   in Loop: Header=BB0_29 Depth=1
	s_mov_b64 s[12:13], 0
	s_mov_b64 s[16:17], 0
.LBB0_71:                               ; %.preheader21.i
                                        ;   Parent Loop BB0_29 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s22, s2, s16
	s_addc_u32 s23, s3, s17
	s_add_u32 s16, s16, 1
	global_load_u8 v1, v2, s[22:23]
	s_addc_u32 s17, s17, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v1, 0xffff, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[8:9], s12, v[1:2]
	s_add_u32 s12, s12, 8
	s_addc_u32 s13, s13, 0
	s_cmp_lg_u32 s20, s16
	v_or_b32_e32 v24, v8, v24
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v25, v9, v25
	s_cbranch_scc1 .LBB0_71
.LBB0_72:                               ; %Flow444
                                        ;   in Loop: Header=BB0_29 Depth=1
	s_mov_b32 s12, 0
	s_mov_b32 s19, 0
	s_branch .LBB0_74
.LBB0_73:                               ;   in Loop: Header=BB0_29 Depth=1
	s_mov_b32 s12, -1
                                        ; implicit-def: $vgpr24_vgpr25
                                        ; implicit-def: $sgpr19
.LBB0_74:                               ; %Flow446
                                        ;   in Loop: Header=BB0_29 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s12
	s_cbranch_vccnz .LBB0_76
; %bb.75:                               ;   in Loop: Header=BB0_29 Depth=1
	global_load_b64 v[24:25], v2, s[2:3]
	s_add_i32 s19, s20, -8
	s_add_u32 s2, s2, 8
	s_addc_u32 s3, s3, 0
.LBB0_76:                               ; %.loopexit22.i
                                        ;   in Loop: Header=BB0_29 Depth=1
	s_cmp_gt_u32 s19, 7
	s_cbranch_scc1 .LBB0_81
; %bb.77:                               ;   in Loop: Header=BB0_29 Depth=1
	v_mov_b32_e32 v26, 0
	v_mov_b32_e32 v27, 0
	s_cmp_eq_u32 s19, 0
	s_cbranch_scc1 .LBB0_80
; %bb.78:                               ; %.preheader.i.preheader
                                        ;   in Loop: Header=BB0_29 Depth=1
	s_mov_b64 s[12:13], 0
	s_mov_b64 s[16:17], s[2:3]
.LBB0_79:                               ; %.preheader.i
                                        ;   Parent Loop BB0_29 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	global_load_u8 v1, v2, s[16:17]
	s_add_i32 s19, s19, -1
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v1, 0xffff, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_lshlrev_b64 v[8:9], s12, v[1:2]
	s_add_u32 s12, s12, 8
	s_addc_u32 s13, s13, 0
	s_add_u32 s16, s16, 1
	s_addc_u32 s17, s17, 0
	s_cmp_lg_u32 s19, 0
	v_or_b32_e32 v26, v8, v26
	v_or_b32_e32 v27, v9, v27
	s_cbranch_scc1 .LBB0_79
.LBB0_80:                               ; %Flow439
                                        ;   in Loop: Header=BB0_29 Depth=1
	s_mov_b32 s12, 0
	s_branch .LBB0_82
.LBB0_81:                               ;   in Loop: Header=BB0_29 Depth=1
	s_mov_b32 s12, -1
.LBB0_82:                               ; %Flow441
                                        ;   in Loop: Header=BB0_29 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s12
	s_cbranch_vccnz .LBB0_84
; %bb.83:                               ;   in Loop: Header=BB0_29 Depth=1
	global_load_b64 v[26:27], v2, s[2:3]
.LBB0_84:                               ; %.loopexit.i
                                        ;   in Loop: Header=BB0_29 Depth=1
	s_waitcnt vmcnt(0)
	v_dual_mov_b32 v1, v3 :: v_dual_mov_b32 v8, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s2, v1
	v_mov_b32_e32 v9, 0
	v_cmp_eq_u32_e64 s2, s2, v1
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_90
; %bb.85:                               ;   in Loop: Header=BB0_29 Depth=1
	global_load_b64 v[30:31], v2, s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[8:9], v2, s[4:5] offset:40
	global_load_b64 v[12:13], v2, s[4:5]
	s_mov_b32 s12, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v9, v9, v31
	v_and_b32_e32 v8, v8, v30
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v9, v9, 24
	v_mul_hi_u32 v28, v8, 24
	v_mul_lo_u32 v8, v8, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v9, v28, v9
	s_waitcnt vmcnt(0)
	v_add_co_u32 v8, vcc_lo, v12, v8
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v9, vcc_lo, v13, v9, vcc_lo
	global_load_b64 v[28:29], v[8:9], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[8:9], v2, v[28:31], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[8:9], v[30:31]
	s_cbranch_execz .LBB0_89
; %bb.86:                               ; %.preheader3.i.i19.i.preheader
                                        ;   in Loop: Header=BB0_29 Depth=1
	s_mov_b32 s13, 0
.LBB0_87:                               ; %.preheader3.i.i19.i
                                        ;   Parent Loop BB0_29 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[12:13], v2, s[4:5] offset:40
	global_load_b64 v[28:29], v2, s[4:5]
	v_dual_mov_b32 v31, v9 :: v_dual_mov_b32 v30, v8
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v12, v12, v30
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[8:9], null, v12, 24, v[28:29]
	v_and_b32_e32 v28, v13, v31
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[12:13], null, v28, 24, v[9:10]
	v_mov_b32_e32 v9, v12
	global_load_b64 v[28:29], v[8:9], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[8:9], v2, v[28:31], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[30:31]
	s_or_b32 s13, vcc_lo, s13
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s13
	s_cbranch_execnz .LBB0_87
; %bb.88:                               ; %Flow434
                                        ;   in Loop: Header=BB0_29 Depth=1
	s_or_b32 exec_lo, exec_lo, s13
.LBB0_89:                               ; %Flow436
                                        ;   in Loop: Header=BB0_29 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s12
.LBB0_90:                               ; %.loopexit4.i.i14.i
                                        ;   in Loop: Header=BB0_29 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s3
	s_clause 0x1
	global_load_b64 v[12:13], v2, s[4:5] offset:40
	global_load_b128 v[28:31], v2, s[4:5]
	v_readfirstlane_b32 s12, v8
	v_readfirstlane_b32 s13, v9
	s_mov_b32 s21, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s16, v12
	v_readfirstlane_b32 s17, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[16:17], s[12:13], s[16:17]
	s_mul_i32 s3, s17, 24
	s_mul_hi_u32 s19, s16, 24
	s_mul_i32 s20, s16, 24
	s_and_saveexec_b32 s22, s2
	s_cbranch_execz .LBB0_92
; %bb.91:                               ;   in Loop: Header=BB0_29 Depth=1
	v_dual_mov_b32 v8, s21 :: v_dual_mov_b32 v9, v2
	s_add_i32 s21, s19, s3
	s_waitcnt vmcnt(0)
	v_add_co_u32 v12, vcc_lo, v28, s20
	v_add_co_ci_u32_e32 v13, vcc_lo, s21, v29, vcc_lo
	global_store_b128 v[12:13], v[8:11], off offset:8
.LBB0_92:                               ;   in Loop: Header=BB0_29 Depth=1
	s_or_b32 exec_lo, exec_lo, s22
	v_cmp_gt_u64_e64 vcc_lo, s[8:9], 56
	v_or_b32_e32 v8, 0, v7
	v_or_b32_e32 v9, v6, v32
	s_lshl_b64 s[16:17], s[16:17], 12
	s_lshl_b32 s21, s10, 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_add_i32 s21, s21, 28
	v_dual_cndmask_b32 v13, v8, v7 :: v_dual_cndmask_b32 v8, v9, v6
	v_lshlrev_b64 v[6:7], 6, v[1:2]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v1, vcc_lo, v30, s16
	v_add_co_ci_u32_e32 v9, vcc_lo, s17, v31, vcc_lo
	s_and_b32 s21, s21, 0x1e0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v30, vcc_lo, v1, v6
	v_and_or_b32 v12, 0xffffff1f, v8, s21
	v_add_co_ci_u32_e32 v31, vcc_lo, v9, v7, vcc_lo
	s_clause 0x3
	global_store_b128 v[30:31], v[12:15], off
	global_store_b128 v[30:31], v[16:19], off offset:16
	global_store_b128 v[30:31], v[20:23], off offset:32
	global_store_b128 v[30:31], v[24:27], off offset:48
	s_and_saveexec_b32 s16, s2
	s_cbranch_execz .LBB0_100
; %bb.93:                               ;   in Loop: Header=BB0_29 Depth=1
	s_clause 0x1
	global_load_b64 v[16:17], v2, s[4:5] offset:32 glc
	global_load_b64 v[6:7], v2, s[4:5] offset:40
	v_dual_mov_b32 v14, s12 :: v_dual_mov_b32 v15, s13
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s22, v6
	v_readfirstlane_b32 s23, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[22:23], s[22:23], s[12:13]
	s_mul_i32 s17, s23, 24
	s_mul_hi_u32 s21, s22, 24
	s_mul_i32 s22, s22, 24
	s_add_i32 s21, s21, s17
	v_add_co_u32 v12, vcc_lo, v28, s22
	v_add_co_ci_u32_e32 v13, vcc_lo, s21, v29, vcc_lo
	s_mov_b32 s17, exec_lo
	global_store_b64 v[12:13], v[16:17], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[8:9], v2, v[14:17], s[4:5] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[8:9], v[16:17]
	s_cbranch_execz .LBB0_96
; %bb.94:                               ; %.preheader1.i.i17.i.preheader
                                        ;   in Loop: Header=BB0_29 Depth=1
	s_mov_b32 s21, 0
.LBB0_95:                               ; %.preheader1.i.i17.i
                                        ;   Parent Loop BB0_29 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_dual_mov_b32 v6, s12 :: v_dual_mov_b32 v7, s13
	s_sleep 1
	global_store_b64 v[12:13], v[8:9], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[6:7], v2, v[6:9], s[4:5] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[8:9]
	v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6
	s_or_b32 s21, vcc_lo, s21
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s21
	s_cbranch_execnz .LBB0_95
.LBB0_96:                               ; %Flow432
                                        ;   in Loop: Header=BB0_29 Depth=1
	s_or_b32 exec_lo, exec_lo, s17
	global_load_b64 v[6:7], v2, s[4:5] offset:16
	s_mov_b32 s21, exec_lo
	s_mov_b32 s17, exec_lo
	v_mbcnt_lo_u32_b32 v1, s21, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v1
	s_cbranch_execz .LBB0_98
; %bb.97:                               ;   in Loop: Header=BB0_29 Depth=1
	s_bcnt1_i32_b32 s21, s21
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v1, s21
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[6:7], v[1:2], off offset:8
.LBB0_98:                               ;   in Loop: Header=BB0_29 Depth=1
	s_or_b32 exec_lo, exec_lo, s17
	s_waitcnt vmcnt(0)
	global_load_b64 v[8:9], v[6:7], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[8:9]
	s_cbranch_vccnz .LBB0_100
; %bb.99:                               ;   in Loop: Header=BB0_29 Depth=1
	global_load_b32 v1, v[6:7], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s17, v1
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[8:9], v[1:2], off
	s_and_b32 m0, s17, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_100:                              ; %Flow433
                                        ;   in Loop: Header=BB0_29 Depth=1
	s_or_b32 exec_lo, exec_lo, s16
	s_add_i32 s19, s19, s3
	v_add_co_u32 v1, vcc_lo, v28, s20
	v_add_co_ci_u32_e32 v7, vcc_lo, s19, v29, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v6, vcc_lo, v1, 20
	v_add_co_ci_u32_e32 v7, vcc_lo, 0, v7, vcc_lo
.LBB0_101:                              ;   Parent Loop BB0_29 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_mov_b32_e32 v1, 1
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_103
; %bb.102:                              ;   in Loop: Header=BB0_101 Depth=2
	global_load_b32 v1, v[6:7], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v1, 1, v1
.LBB0_103:                              ;   in Loop: Header=BB0_101 Depth=2
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s3, v1
	s_cmp_eq_u32 s3, 0
	s_cbranch_scc1 .LBB0_105
; %bb.104:                              ;   in Loop: Header=BB0_101 Depth=2
	s_mov_b32 s3, 0
	s_sleep 1
	s_branch .LBB0_106
.LBB0_105:                              ;   in Loop: Header=BB0_101 Depth=2
	s_mov_b32 s3, -1
.LBB0_106:                              ; %Flow427
                                        ;   in Loop: Header=BB0_101 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s3
	s_cbranch_vccnz .LBB0_101
; %bb.107:                              ;   in Loop: Header=BB0_29 Depth=1
	global_load_b128 v[6:9], v[30:31], off
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_111
; %bb.108:                              ;   in Loop: Header=BB0_29 Depth=1
	s_clause 0x2
	global_load_b64 v[8:9], v2, s[4:5] offset:40
	global_load_b64 v[16:17], v2, s[4:5] offset:24 glc
	global_load_b64 v[14:15], v2, s[4:5]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v1, vcc_lo, v8, 1
	v_add_co_ci_u32_e32 v18, vcc_lo, 0, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v12, vcc_lo, v1, s12
	v_add_co_ci_u32_e32 v13, vcc_lo, s13, v18, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[12:13]
	v_dual_cndmask_b32 v13, v13, v18 :: v_dual_cndmask_b32 v12, v12, v1
	v_and_b32_e32 v1, v13, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v8, v12, v8
	v_mul_hi_u32 v9, v8, 24
	v_mul_lo_u32 v8, v8, 24
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_u32 v8, vcc_lo, v14, v8
	v_mov_b32_e32 v14, v16
	v_mul_lo_u32 v1, v1, 24
	v_add_nc_u32_e32 v1, v9, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e32 v9, vcc_lo, v15, v1, vcc_lo
	v_mov_b32_e32 v15, v17
	global_store_b64 v[8:9], v[16:17], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[14:15], v2, v[12:15], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[14:15], v[16:17]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_111
; %bb.109:                              ; %.preheader.i.i16.i.preheader
                                        ;   in Loop: Header=BB0_29 Depth=1
	s_mov_b32 s2, 0
.LBB0_110:                              ; %.preheader.i.i16.i
                                        ;   Parent Loop BB0_29 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	global_store_b64 v[8:9], v[14:15], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[16:17], v2, v[12:15], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[16:17], v[14:15]
	v_dual_mov_b32 v14, v16 :: v_dual_mov_b32 v15, v17
	s_or_b32 s2, vcc_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s2
	s_cbranch_execnz .LBB0_110
.LBB0_111:                              ; %__ockl_hostcall_preview.exit20.i
                                        ;   in Loop: Header=BB0_29 Depth=1
	s_or_b32 exec_lo, exec_lo, s3
	s_sub_u32 s8, s8, s10
	s_subb_u32 s9, s9, s11
	s_add_u32 s6, s6, s10
	s_addc_u32 s7, s7, s11
	s_cmp_lg_u64 s[8:9], 0
	s_cbranch_scc1 .LBB0_29
; %bb.112:                              ; %Flow472
	s_mov_b32 s2, 0
	s_branch .LBB0_114
.LBB0_113:
	s_mov_b32 s2, -1
                                        ; implicit-def: $vgpr6_vgpr7
.LBB0_114:                              ; %Flow487
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s2
	s_cbranch_vccz .LBB0_143
; %bb.115:
	s_waitcnt vmcnt(0)
	v_dual_mov_b32 v6, v3 :: v_dual_mov_b32 v1, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s2, v6
	v_mov_b32_e32 v2, 0
	v_cmp_eq_u32_e64 s2, s2, v6
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_121
; %bb.116:
	v_mov_b32_e32 v7, 0
	s_mov_b32 s6, exec_lo
	global_load_b64 v[10:11], v7, s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[1:2], v7, s[4:5] offset:40
	global_load_b64 v[8:9], v7, s[4:5]
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v2, v2, v11
	v_and_b32_e32 v1, v1, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v2, v2, 24
	v_mul_hi_u32 v12, v1, 24
	v_mul_lo_u32 v1, v1, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v2, v12, v2
	s_waitcnt vmcnt(0)
	v_add_co_u32 v1, vcc_lo, v8, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, v9, v2, vcc_lo
	global_load_b64 v[8:9], v[1:2], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[1:2], v7, v[8:11], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[1:2], v[10:11]
	s_cbranch_execz .LBB0_120
; %bb.117:                              ; %.preheader3.i.i.i33.preheader
	s_mov_b32 s7, 0
.LBB0_118:                              ; %.preheader3.i.i.i33
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[8:9], v7, s[4:5] offset:40
	global_load_b64 v[12:13], v7, s[4:5]
	v_dual_mov_b32 v11, v2 :: v_dual_mov_b32 v10, v1
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v8, v8, v10
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[1:2], null, v8, 24, v[12:13]
	v_and_b32_e32 v12, v9, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[8:9], null, v12, 24, v[2:3]
	v_mov_b32_e32 v2, v8
	global_load_b64 v[8:9], v[1:2], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[1:2], v7, v[8:11], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[1:2], v[10:11]
	s_or_b32 s7, vcc_lo, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s7
	s_cbranch_execnz .LBB0_118
; %bb.119:                              ; %Flow484
	s_or_b32 exec_lo, exec_lo, s7
.LBB0_120:                              ; %Flow486
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s6
.LBB0_121:                              ; %.loopexit4.i.i.i28
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s3
	v_mov_b32_e32 v7, 0
	v_readfirstlane_b32 s6, v1
	v_readfirstlane_b32 s7, v2
	s_mov_b32 s12, exec_lo
	s_clause 0x1
	global_load_b64 v[12:13], v7, s[4:5] offset:40
	global_load_b128 v[8:11], v7, s[4:5]
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s8, v12
	v_readfirstlane_b32 s9, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[8:9], s[6:7], s[8:9]
	s_mul_i32 s3, s9, 24
	s_mul_hi_u32 s10, s8, 24
	s_mul_i32 s11, s8, 24
	s_and_saveexec_b32 s13, s2
	s_cbranch_execz .LBB0_123
; %bb.122:
	v_dual_mov_b32 v12, s12 :: v_dual_mov_b32 v13, v7
	s_add_i32 s12, s10, s3
	s_waitcnt vmcnt(0)
	v_add_co_u32 v1, vcc_lo, v8, s11
	v_add_co_ci_u32_e32 v2, vcc_lo, s12, v9, vcc_lo
	v_dual_mov_b32 v14, 2 :: v_dual_mov_b32 v15, 1
	global_store_b128 v[1:2], v[12:15], off offset:8
.LBB0_123:
	s_or_b32 exec_lo, exec_lo, s13
	s_lshl_b64 s[8:9], s[8:9], 12
	v_lshlrev_b64 v[1:2], 6, v[6:7]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v6, vcc_lo, v10, s8
	v_add_co_ci_u32_e32 v10, vcc_lo, s9, v11, vcc_lo
	s_mov_b32 s20, 0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, v6, v1
	s_mov_b32 s21, s20
	s_mov_b32 s22, s20
	s_mov_b32 s23, s20
	v_and_or_b32 v4, 0xffffff1f, v4, 32
	v_add_co_ci_u32_e32 v2, vcc_lo, v10, v2, vcc_lo
	v_mov_b32_e32 v6, v7
	v_dual_mov_b32 v10, s20 :: v_dual_mov_b32 v13, s23
	v_dual_mov_b32 v11, s21 :: v_dual_mov_b32 v12, s22
	s_clause 0x3
	global_store_b128 v[1:2], v[4:7], off
	global_store_b128 v[1:2], v[10:13], off offset:16
	global_store_b128 v[1:2], v[10:13], off offset:32
	global_store_b128 v[1:2], v[10:13], off offset:48
	s_and_saveexec_b32 s8, s2
	s_cbranch_execz .LBB0_131
; %bb.124:
	v_dual_mov_b32 v12, 0 :: v_dual_mov_b32 v13, s6
	v_mov_b32_e32 v14, s7
	s_clause 0x1
	global_load_b64 v[15:16], v12, s[4:5] offset:32 glc
	global_load_b64 v[4:5], v12, s[4:5] offset:40
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s12, v4
	v_readfirstlane_b32 s13, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[12:13], s[12:13], s[6:7]
	s_mul_i32 s9, s13, 24
	s_mul_hi_u32 s13, s12, 24
	s_mul_i32 s12, s12, 24
	s_add_i32 s13, s13, s9
	v_add_co_u32 v10, vcc_lo, v8, s12
	v_add_co_ci_u32_e32 v11, vcc_lo, s13, v9, vcc_lo
	s_mov_b32 s9, exec_lo
	global_store_b64 v[10:11], v[15:16], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[6:7], v12, v[13:16], s[4:5] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[6:7], v[15:16]
	s_cbranch_execz .LBB0_127
; %bb.125:                              ; %.preheader1.i.i.i31.preheader
	s_mov_b32 s12, 0
.LBB0_126:                              ; %.preheader1.i.i.i31
                                        ; =>This Inner Loop Header: Depth=1
	v_dual_mov_b32 v4, s6 :: v_dual_mov_b32 v5, s7
	s_sleep 1
	global_store_b64 v[10:11], v[6:7], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[4:5], v12, v[4:7], s[4:5] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
	v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
	s_or_b32 s12, vcc_lo, s12
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s12
	s_cbranch_execnz .LBB0_126
.LBB0_127:                              ; %Flow482
	s_or_b32 exec_lo, exec_lo, s9
	v_mov_b32_e32 v7, 0
	s_mov_b32 s12, exec_lo
	s_mov_b32 s9, exec_lo
	v_mbcnt_lo_u32_b32 v6, s12, 0
	global_load_b64 v[4:5], v7, s[4:5] offset:16
	v_cmpx_eq_u32_e32 0, v6
	s_cbranch_execz .LBB0_129
; %bb.128:
	s_bcnt1_i32_b32 s12, s12
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v6, s12
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[4:5], v[6:7], off offset:8
.LBB0_129:
	s_or_b32 exec_lo, exec_lo, s9
	s_waitcnt vmcnt(0)
	global_load_b64 v[6:7], v[4:5], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[6:7]
	s_cbranch_vccnz .LBB0_131
; %bb.130:
	global_load_b32 v4, v[4:5], off offset:24
	v_mov_b32_e32 v5, 0
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s9, v4
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[6:7], v[4:5], off
	s_and_b32 m0, s9, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_131:                              ; %Flow483
	s_or_b32 exec_lo, exec_lo, s8
	s_add_i32 s10, s10, s3
	v_add_co_u32 v4, vcc_lo, v8, s11
	v_add_co_ci_u32_e32 v5, vcc_lo, s10, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, v4, 20
	v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
.LBB0_132:                              ; =>This Inner Loop Header: Depth=1
	v_mov_b32_e32 v6, 1
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_134
; %bb.133:                              ;   in Loop: Header=BB0_132 Depth=1
	global_load_b32 v6, v[4:5], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v6, 1, v6
.LBB0_134:                              ;   in Loop: Header=BB0_132 Depth=1
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s3, v6
	s_cmp_eq_u32 s3, 0
	s_cbranch_scc1 .LBB0_136
; %bb.135:                              ;   in Loop: Header=BB0_132 Depth=1
	s_mov_b32 s3, 0
	s_sleep 1
	s_branch .LBB0_137
.LBB0_136:                              ;   in Loop: Header=BB0_132 Depth=1
	s_mov_b32 s3, -1
.LBB0_137:                              ; %Flow477
                                        ;   in Loop: Header=BB0_132 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s3
	s_cbranch_vccnz .LBB0_132
; %bb.138:
	global_load_b128 v[6:9], v[1:2], off
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_142
; %bb.139:
	v_mov_b32_e32 v4, 0
	s_clause 0x2
	global_load_b64 v[1:2], v4, s[4:5] offset:40
	global_load_b64 v[12:13], v4, s[4:5] offset:24 glc
	global_load_b64 v[10:11], v4, s[4:5]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v5, vcc_lo, v1, 1
	v_add_co_ci_u32_e32 v14, vcc_lo, 0, v2, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v8, vcc_lo, v5, s6
	v_add_co_ci_u32_e32 v9, vcc_lo, s7, v14, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[8:9]
	v_dual_cndmask_b32 v9, v9, v14 :: v_dual_cndmask_b32 v8, v8, v5
	v_and_b32_e32 v2, v9, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v1, v8, v1
	v_mul_lo_u32 v2, v2, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v5, v1, 24
	v_mul_lo_u32 v1, v1, 24
	v_add_nc_u32_e32 v2, v5, v2
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v1, vcc_lo, v10, v1
	v_mov_b32_e32 v10, v12
	v_add_co_ci_u32_e32 v2, vcc_lo, v11, v2, vcc_lo
	v_mov_b32_e32 v11, v13
	global_store_b64 v[1:2], v[12:13], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[10:11], v4, v[8:11], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[10:11], v[12:13]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_142
; %bb.140:                              ; %.preheader.i.i.i30.preheader
	s_mov_b32 s2, 0
.LBB0_141:                              ; %.preheader.i.i.i30
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	global_store_b64 v[1:2], v[10:11], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[12:13], v4, v[8:11], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[12:13], v[10:11]
	v_dual_mov_b32 v10, v12 :: v_dual_mov_b32 v11, v13
	s_or_b32 s2, vcc_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s2
	s_cbranch_execnz .LBB0_141
.LBB0_142:                              ; %__ockl_hostcall_preview.exit.i
	s_or_b32 exec_lo, exec_lo, s3
.LBB0_143:                              ; %__ockl_printf_append_string_n.exit
	s_waitcnt vmcnt(0)
	v_dual_mov_b32 v8, v3 :: v_dual_mov_b32 v1, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s2, v8
	v_mov_b32_e32 v2, 0
	v_cmp_eq_u32_e64 s2, s2, v8
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_149
; %bb.144:
	v_mov_b32_e32 v4, 0
	s_mov_b32 s6, exec_lo
	global_load_b64 v[11:12], v4, s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[1:2], v4, s[4:5] offset:40
	global_load_b64 v[9:10], v4, s[4:5]
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v1, v1, v11
	v_and_b32_e32 v2, v2, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v5, v1, 24
	v_mul_lo_u32 v2, v2, 24
	v_mul_lo_u32 v1, v1, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v2, v5, v2
	s_waitcnt vmcnt(0)
	v_add_co_u32 v1, vcc_lo, v9, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, v10, v2, vcc_lo
	global_load_b64 v[9:10], v[1:2], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[1:2], v4, v[9:12], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[1:2], v[11:12]
	s_cbranch_execz .LBB0_148
; %bb.145:                              ; %.preheader3.i.i.i40.preheader
	s_mov_b32 s7, 0
.LBB0_146:                              ; %.preheader3.i.i.i40
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[9:10], v4, s[4:5] offset:40
	global_load_b64 v[13:14], v4, s[4:5]
	v_dual_mov_b32 v12, v2 :: v_dual_mov_b32 v11, v1
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v5, v9, v11
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[1:2], null, v5, 24, v[13:14]
	v_and_b32_e32 v5, v10, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[9:10], null, v5, 24, v[2:3]
	v_mov_b32_e32 v2, v9
	global_load_b64 v[9:10], v[1:2], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[1:2], v4, v[9:12], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[1:2], v[11:12]
	s_or_b32 s7, vcc_lo, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s7
	s_cbranch_execnz .LBB0_146
; %bb.147:                              ; %Flow420
	s_or_b32 exec_lo, exec_lo, s7
.LBB0_148:                              ; %Flow422
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s6
.LBB0_149:                              ; %.loopexit4.i.i.i34
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s3
	v_mov_b32_e32 v9, 0
	v_readfirstlane_b32 s6, v1
	v_readfirstlane_b32 s7, v2
	s_mov_b32 s12, exec_lo
	s_clause 0x1
	global_load_b64 v[4:5], v9, s[4:5] offset:40
	global_load_b128 v[10:13], v9, s[4:5]
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s8, v4
	v_readfirstlane_b32 s9, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[8:9], s[6:7], s[8:9]
	s_mul_i32 s3, s9, 24
	s_mul_hi_u32 s10, s8, 24
	s_mul_i32 s11, s8, 24
	s_and_saveexec_b32 s13, s2
	s_cbranch_execz .LBB0_151
; %bb.150:
	v_dual_mov_b32 v14, s12 :: v_dual_mov_b32 v15, v9
	s_add_i32 s12, s10, s3
	s_waitcnt vmcnt(0)
	v_add_co_u32 v1, vcc_lo, v10, s11
	v_add_co_ci_u32_e32 v2, vcc_lo, s12, v11, vcc_lo
	v_dual_mov_b32 v16, 2 :: v_dual_mov_b32 v17, 1
	global_store_b128 v[1:2], v[14:17], off offset:8
.LBB0_151:
	s_or_b32 exec_lo, exec_lo, s13
	s_lshl_b64 s[8:9], s[8:9], 12
	v_lshlrev_b64 v[1:2], 6, v[8:9]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v4, vcc_lo, v12, s8
	v_add_co_ci_u32_e32 v5, vcc_lo, s9, v13, vcc_lo
	s_mov_b32 s20, 0
	s_and_b32 s8, s18, 0xffff
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, v4, v1
	s_mov_b32 s21, s20
	s_mov_b32 s22, s20
	s_mov_b32 s23, s20
	v_and_or_b32 v6, 0xffffff1f, v6, 32
	v_add_co_ci_u32_e32 v2, vcc_lo, v5, v2, vcc_lo
	v_mov_b32_e32 v8, s8
	v_dual_mov_b32 v12, s20 :: v_dual_mov_b32 v15, s23
	v_dual_mov_b32 v13, s21 :: v_dual_mov_b32 v14, s22
	s_clause 0x3
	global_store_b128 v[1:2], v[6:9], off
	global_store_b128 v[1:2], v[12:15], off offset:16
	global_store_b128 v[1:2], v[12:15], off offset:32
	global_store_b128 v[1:2], v[12:15], off offset:48
	s_and_saveexec_b32 s8, s2
	s_cbranch_execz .LBB0_159
; %bb.152:
	v_dual_mov_b32 v12, 0 :: v_dual_mov_b32 v13, s6
	v_mov_b32_e32 v14, s7
	s_clause 0x1
	global_load_b64 v[15:16], v12, s[4:5] offset:32 glc
	global_load_b64 v[4:5], v12, s[4:5] offset:40
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s12, v4
	v_readfirstlane_b32 s13, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[12:13], s[12:13], s[6:7]
	s_mul_i32 s9, s13, 24
	s_mul_hi_u32 s13, s12, 24
	s_mul_i32 s12, s12, 24
	s_add_i32 s13, s13, s9
	v_add_co_u32 v8, vcc_lo, v10, s12
	v_add_co_ci_u32_e32 v9, vcc_lo, s13, v11, vcc_lo
	s_mov_b32 s9, exec_lo
	global_store_b64 v[8:9], v[15:16], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[6:7], v12, v[13:16], s[4:5] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[6:7], v[15:16]
	s_cbranch_execz .LBB0_155
; %bb.153:                              ; %.preheader1.i.i.i38.preheader
	s_mov_b32 s12, 0
.LBB0_154:                              ; %.preheader1.i.i.i38
                                        ; =>This Inner Loop Header: Depth=1
	v_dual_mov_b32 v4, s6 :: v_dual_mov_b32 v5, s7
	s_sleep 1
	global_store_b64 v[8:9], v[6:7], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[4:5], v12, v[4:7], s[4:5] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
	v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
	s_or_b32 s12, vcc_lo, s12
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s12
	s_cbranch_execnz .LBB0_154
.LBB0_155:                              ; %Flow418
	s_or_b32 exec_lo, exec_lo, s9
	v_mov_b32_e32 v7, 0
	s_mov_b32 s12, exec_lo
	s_mov_b32 s9, exec_lo
	v_mbcnt_lo_u32_b32 v6, s12, 0
	global_load_b64 v[4:5], v7, s[4:5] offset:16
	v_cmpx_eq_u32_e32 0, v6
	s_cbranch_execz .LBB0_157
; %bb.156:
	s_bcnt1_i32_b32 s12, s12
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v6, s12
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[4:5], v[6:7], off offset:8
.LBB0_157:
	s_or_b32 exec_lo, exec_lo, s9
	s_waitcnt vmcnt(0)
	global_load_b64 v[6:7], v[4:5], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[6:7]
	s_cbranch_vccnz .LBB0_159
; %bb.158:
	global_load_b32 v4, v[4:5], off offset:24
	v_mov_b32_e32 v5, 0
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s9, v4
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[6:7], v[4:5], off
	s_and_b32 m0, s9, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_159:                              ; %Flow419
	s_or_b32 exec_lo, exec_lo, s8
	s_add_i32 s10, s10, s3
	v_add_co_u32 v4, vcc_lo, v10, s11
	v_add_co_ci_u32_e32 v5, vcc_lo, s10, v11, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, v4, 20
	v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
.LBB0_160:                              ; =>This Inner Loop Header: Depth=1
	v_mov_b32_e32 v6, 1
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_162
; %bb.161:                              ;   in Loop: Header=BB0_160 Depth=1
	global_load_b32 v6, v[4:5], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v6, 1, v6
.LBB0_162:                              ;   in Loop: Header=BB0_160 Depth=1
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s3, v6
	s_cmp_eq_u32 s3, 0
	s_cbranch_scc1 .LBB0_164
; %bb.163:                              ;   in Loop: Header=BB0_160 Depth=1
	s_mov_b32 s3, 0
	s_sleep 1
	s_branch .LBB0_165
.LBB0_164:                              ;   in Loop: Header=BB0_160 Depth=1
	s_mov_b32 s3, -1
.LBB0_165:                              ; %Flow413
                                        ;   in Loop: Header=BB0_160 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s3
	s_cbranch_vccnz .LBB0_160
; %bb.166:
	global_load_b64 v[4:5], v[1:2], off
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_170
; %bb.167:
	v_mov_b32_e32 v10, 0
	s_clause 0x2
	global_load_b64 v[1:2], v10, s[4:5] offset:40
	global_load_b64 v[11:12], v10, s[4:5] offset:24 glc
	global_load_b64 v[8:9], v10, s[4:5]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v13, vcc_lo, v1, 1
	v_add_co_ci_u32_e32 v14, vcc_lo, 0, v2, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v6, vcc_lo, v13, s6
	v_add_co_ci_u32_e32 v7, vcc_lo, s7, v14, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[6:7]
	v_dual_cndmask_b32 v7, v7, v14 :: v_dual_cndmask_b32 v6, v6, v13
	v_and_b32_e32 v2, v7, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v1, v6, v1
	v_mul_lo_u32 v2, v2, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v13, v1, 24
	v_mul_lo_u32 v1, v1, 24
	v_add_nc_u32_e32 v2, v13, v2
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v1, vcc_lo, v8, v1
	v_mov_b32_e32 v8, v11
	v_add_co_ci_u32_e32 v2, vcc_lo, v9, v2, vcc_lo
	v_mov_b32_e32 v9, v12
	global_store_b64 v[1:2], v[11:12], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[8:9], v10, v[6:9], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[8:9], v[11:12]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_170
; %bb.168:                              ; %.preheader.i.i.i37.preheader
	s_mov_b32 s2, 0
.LBB0_169:                              ; %.preheader.i.i.i37
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	global_store_b64 v[1:2], v[8:9], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[11:12], v10, v[6:9], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[11:12], v[8:9]
	v_dual_mov_b32 v8, v11 :: v_dual_mov_b32 v9, v12
	s_or_b32 s2, vcc_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s2
	s_cbranch_execnz .LBB0_169
.LBB0_170:                              ; %__ockl_printf_append_args.exit
	s_or_b32 exec_lo, exec_lo, s3
	v_dual_mov_b32 v6, v3 :: v_dual_mov_b32 v1, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s2, v6
	v_mov_b32_e32 v2, 0
	v_cmp_eq_u32_e64 s2, s2, v6
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_176
; %bb.171:
	v_mov_b32_e32 v7, 0
	s_mov_b32 s6, exec_lo
	global_load_b64 v[10:11], v7, s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[1:2], v7, s[4:5] offset:40
	global_load_b64 v[8:9], v7, s[4:5]
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v2, v2, v11
	v_and_b32_e32 v1, v1, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v2, v2, 24
	v_mul_hi_u32 v12, v1, 24
	v_mul_lo_u32 v1, v1, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v2, v12, v2
	s_waitcnt vmcnt(0)
	v_add_co_u32 v1, vcc_lo, v8, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, v9, v2, vcc_lo
	global_load_b64 v[8:9], v[1:2], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[1:2], v7, v[8:11], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[1:2], v[10:11]
	s_cbranch_execz .LBB0_175
; %bb.172:                              ; %.preheader3.i.i.i47.preheader
	s_mov_b32 s7, 0
.LBB0_173:                              ; %.preheader3.i.i.i47
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[8:9], v7, s[4:5] offset:40
	global_load_b64 v[12:13], v7, s[4:5]
	v_dual_mov_b32 v11, v2 :: v_dual_mov_b32 v10, v1
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v8, v8, v10
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[1:2], null, v8, 24, v[12:13]
	v_and_b32_e32 v12, v9, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[8:9], null, v12, 24, v[2:3]
	v_mov_b32_e32 v2, v8
	global_load_b64 v[8:9], v[1:2], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[1:2], v7, v[8:11], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[1:2], v[10:11]
	s_or_b32 s7, vcc_lo, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s7
	s_cbranch_execnz .LBB0_173
; %bb.174:                              ; %Flow406
	s_or_b32 exec_lo, exec_lo, s7
.LBB0_175:                              ; %Flow408
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s6
.LBB0_176:                              ; %.loopexit4.i.i.i41
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s3
	v_mov_b32_e32 v7, 0
	v_readfirstlane_b32 s6, v1
	v_readfirstlane_b32 s7, v2
	s_mov_b32 s12, exec_lo
	s_clause 0x1
	global_load_b64 v[12:13], v7, s[4:5] offset:40
	global_load_b128 v[8:11], v7, s[4:5]
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s8, v12
	v_readfirstlane_b32 s9, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[8:9], s[6:7], s[8:9]
	s_mul_i32 s3, s9, 24
	s_mul_hi_u32 s10, s8, 24
	s_mul_i32 s11, s8, 24
	s_and_saveexec_b32 s13, s2
	s_cbranch_execz .LBB0_178
; %bb.177:
	v_dual_mov_b32 v12, s12 :: v_dual_mov_b32 v13, v7
	s_add_i32 s12, s10, s3
	s_waitcnt vmcnt(0)
	v_add_co_u32 v1, vcc_lo, v8, s11
	v_add_co_ci_u32_e32 v2, vcc_lo, s12, v9, vcc_lo
	v_dual_mov_b32 v14, 2 :: v_dual_mov_b32 v15, 1
	global_store_b128 v[1:2], v[12:15], off offset:8
.LBB0_178:
	s_or_b32 exec_lo, exec_lo, s13
	s_lshl_b64 s[8:9], s[8:9], 12
	v_lshlrev_b64 v[1:2], 6, v[6:7]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v6, vcc_lo, v10, s8
	v_add_co_ci_u32_e32 v10, vcc_lo, s9, v11, vcc_lo
	s_mov_b32 s16, 0
	s_lshr_b32 s8, s18, 16
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, v6, v1
	s_mov_b32 s17, s16
	s_mov_b32 s18, s16
	s_mov_b32 s19, s16
	v_and_or_b32 v4, 0xffffff1f, v4, 32
	v_add_co_ci_u32_e32 v2, vcc_lo, v10, v2, vcc_lo
	v_mov_b32_e32 v6, s8
	v_dual_mov_b32 v10, s16 :: v_dual_mov_b32 v13, s19
	v_dual_mov_b32 v11, s17 :: v_dual_mov_b32 v12, s18
	s_clause 0x3
	global_store_b128 v[1:2], v[4:7], off
	global_store_b128 v[1:2], v[10:13], off offset:16
	global_store_b128 v[1:2], v[10:13], off offset:32
	global_store_b128 v[1:2], v[10:13], off offset:48
	s_and_saveexec_b32 s8, s2
	s_cbranch_execz .LBB0_186
; %bb.179:
	v_dual_mov_b32 v12, 0 :: v_dual_mov_b32 v13, s6
	v_mov_b32_e32 v14, s7
	s_clause 0x1
	global_load_b64 v[15:16], v12, s[4:5] offset:32 glc
	global_load_b64 v[4:5], v12, s[4:5] offset:40
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s12, v4
	v_readfirstlane_b32 s13, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[12:13], s[12:13], s[6:7]
	s_mul_i32 s9, s13, 24
	s_mul_hi_u32 s13, s12, 24
	s_mul_i32 s12, s12, 24
	s_add_i32 s13, s13, s9
	v_add_co_u32 v10, vcc_lo, v8, s12
	v_add_co_ci_u32_e32 v11, vcc_lo, s13, v9, vcc_lo
	s_mov_b32 s9, exec_lo
	global_store_b64 v[10:11], v[15:16], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[6:7], v12, v[13:16], s[4:5] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[6:7], v[15:16]
	s_cbranch_execz .LBB0_182
; %bb.180:                              ; %.preheader1.i.i.i45.preheader
	s_mov_b32 s12, 0
.LBB0_181:                              ; %.preheader1.i.i.i45
                                        ; =>This Inner Loop Header: Depth=1
	v_dual_mov_b32 v4, s6 :: v_dual_mov_b32 v5, s7
	s_sleep 1
	global_store_b64 v[10:11], v[6:7], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[4:5], v12, v[4:7], s[4:5] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
	v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
	s_or_b32 s12, vcc_lo, s12
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s12
	s_cbranch_execnz .LBB0_181
.LBB0_182:                              ; %Flow404
	s_or_b32 exec_lo, exec_lo, s9
	v_mov_b32_e32 v7, 0
	s_mov_b32 s12, exec_lo
	s_mov_b32 s9, exec_lo
	v_mbcnt_lo_u32_b32 v6, s12, 0
	global_load_b64 v[4:5], v7, s[4:5] offset:16
	v_cmpx_eq_u32_e32 0, v6
	s_cbranch_execz .LBB0_184
; %bb.183:
	s_bcnt1_i32_b32 s12, s12
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v6, s12
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[4:5], v[6:7], off offset:8
.LBB0_184:
	s_or_b32 exec_lo, exec_lo, s9
	s_waitcnt vmcnt(0)
	global_load_b64 v[6:7], v[4:5], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[6:7]
	s_cbranch_vccnz .LBB0_186
; %bb.185:
	global_load_b32 v4, v[4:5], off offset:24
	v_mov_b32_e32 v5, 0
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s9, v4
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[6:7], v[4:5], off
	s_and_b32 m0, s9, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_186:                              ; %Flow405
	s_or_b32 exec_lo, exec_lo, s8
	s_add_i32 s10, s10, s3
	v_add_co_u32 v4, vcc_lo, v8, s11
	v_add_co_ci_u32_e32 v5, vcc_lo, s10, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, v4, 20
	v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
.LBB0_187:                              ; =>This Inner Loop Header: Depth=1
	v_mov_b32_e32 v6, 1
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_189
; %bb.188:                              ;   in Loop: Header=BB0_187 Depth=1
	global_load_b32 v6, v[4:5], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v6, 1, v6
.LBB0_189:                              ;   in Loop: Header=BB0_187 Depth=1
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s3, v6
	s_cmp_eq_u32 s3, 0
	s_cbranch_scc1 .LBB0_191
; %bb.190:                              ;   in Loop: Header=BB0_187 Depth=1
	s_mov_b32 s3, 0
	s_sleep 1
	s_branch .LBB0_192
.LBB0_191:                              ;   in Loop: Header=BB0_187 Depth=1
	s_mov_b32 s3, -1
.LBB0_192:                              ; %Flow399
                                        ;   in Loop: Header=BB0_187 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s3
	s_cbranch_vccnz .LBB0_187
; %bb.193:
	global_load_b64 v[4:5], v[1:2], off
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_197
; %bb.194:
	v_mov_b32_e32 v10, 0
	s_clause 0x2
	global_load_b64 v[1:2], v10, s[4:5] offset:40
	global_load_b64 v[11:12], v10, s[4:5] offset:24 glc
	global_load_b64 v[8:9], v10, s[4:5]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v13, vcc_lo, v1, 1
	v_add_co_ci_u32_e32 v14, vcc_lo, 0, v2, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v6, vcc_lo, v13, s6
	v_add_co_ci_u32_e32 v7, vcc_lo, s7, v14, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[6:7]
	v_dual_cndmask_b32 v7, v7, v14 :: v_dual_cndmask_b32 v6, v6, v13
	v_and_b32_e32 v2, v7, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v1, v6, v1
	v_mul_lo_u32 v2, v2, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v13, v1, 24
	v_mul_lo_u32 v1, v1, 24
	v_add_nc_u32_e32 v2, v13, v2
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v1, vcc_lo, v8, v1
	v_mov_b32_e32 v8, v11
	v_add_co_ci_u32_e32 v2, vcc_lo, v9, v2, vcc_lo
	v_mov_b32_e32 v9, v12
	global_store_b64 v[1:2], v[11:12], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[8:9], v10, v[6:9], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[8:9], v[11:12]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_197
; %bb.195:                              ; %.preheader.i.i.i44.preheader
	s_mov_b32 s2, 0
.LBB0_196:                              ; %.preheader.i.i.i44
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	global_store_b64 v[1:2], v[8:9], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[11:12], v10, v[6:9], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[11:12], v[8:9]
	v_dual_mov_b32 v8, v11 :: v_dual_mov_b32 v9, v12
	s_or_b32 s2, vcc_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s2
	s_cbranch_execnz .LBB0_196
.LBB0_197:                              ; %__ockl_printf_append_args.exit48
	s_or_b32 exec_lo, exec_lo, s3
	v_dual_mov_b32 v6, v3 :: v_dual_mov_b32 v1, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s2, v6
	v_mov_b32_e32 v2, 0
	v_cmp_eq_u32_e64 s2, s2, v6
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_203
; %bb.198:
	v_mov_b32_e32 v7, 0
	s_mov_b32 s6, exec_lo
	global_load_b64 v[10:11], v7, s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[1:2], v7, s[4:5] offset:40
	global_load_b64 v[8:9], v7, s[4:5]
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v2, v2, v11
	v_and_b32_e32 v1, v1, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v2, v2, 24
	v_mul_hi_u32 v12, v1, 24
	v_mul_lo_u32 v1, v1, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v2, v12, v2
	s_waitcnt vmcnt(0)
	v_add_co_u32 v1, vcc_lo, v8, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, v9, v2, vcc_lo
	global_load_b64 v[8:9], v[1:2], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[1:2], v7, v[8:11], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[1:2], v[10:11]
	s_cbranch_execz .LBB0_202
; %bb.199:                              ; %.preheader3.i.i.i55.preheader
	s_mov_b32 s7, 0
.LBB0_200:                              ; %.preheader3.i.i.i55
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[8:9], v7, s[4:5] offset:40
	global_load_b64 v[12:13], v7, s[4:5]
	v_dual_mov_b32 v11, v2 :: v_dual_mov_b32 v10, v1
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v8, v8, v10
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[1:2], null, v8, 24, v[12:13]
	v_and_b32_e32 v12, v9, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[8:9], null, v12, 24, v[2:3]
	v_mov_b32_e32 v2, v8
	global_load_b64 v[8:9], v[1:2], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[1:2], v7, v[8:11], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[1:2], v[10:11]
	s_or_b32 s7, vcc_lo, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s7
	s_cbranch_execnz .LBB0_200
; %bb.201:                              ; %Flow392
	s_or_b32 exec_lo, exec_lo, s7
.LBB0_202:                              ; %Flow394
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s6
.LBB0_203:                              ; %.loopexit4.i.i.i49
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s3
	v_mov_b32_e32 v7, 0
	v_readfirstlane_b32 s6, v1
	v_readfirstlane_b32 s7, v2
	s_mov_b32 s12, exec_lo
	s_clause 0x1
	global_load_b64 v[12:13], v7, s[4:5] offset:40
	global_load_b128 v[8:11], v7, s[4:5]
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s8, v12
	v_readfirstlane_b32 s9, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[8:9], s[6:7], s[8:9]
	s_mul_i32 s3, s9, 24
	s_mul_hi_u32 s10, s8, 24
	s_mul_i32 s11, s8, 24
	s_and_saveexec_b32 s13, s2
	s_cbranch_execz .LBB0_205
; %bb.204:
	v_dual_mov_b32 v12, s12 :: v_dual_mov_b32 v13, v7
	s_add_i32 s12, s10, s3
	s_waitcnt vmcnt(0)
	v_add_co_u32 v1, vcc_lo, v8, s11
	v_add_co_ci_u32_e32 v2, vcc_lo, s12, v9, vcc_lo
	v_dual_mov_b32 v14, 2 :: v_dual_mov_b32 v15, 1
	global_store_b128 v[1:2], v[12:15], off offset:8
.LBB0_205:
	s_or_b32 exec_lo, exec_lo, s13
	s_lshl_b64 s[8:9], s[8:9], 12
	v_lshlrev_b64 v[1:2], 6, v[6:7]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v6, vcc_lo, v10, s8
	v_add_co_ci_u32_e32 v10, vcc_lo, s9, v11, vcc_lo
	s_mov_b32 s16, 0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, v6, v1
	s_mov_b32 s17, s16
	s_mov_b32 s18, s16
	s_mov_b32 s19, s16
	v_and_or_b32 v4, 0xffffff1f, v4, 32
	v_add_co_ci_u32_e32 v2, vcc_lo, v10, v2, vcc_lo
	v_mov_b32_e32 v6, s14
	v_dual_mov_b32 v10, s16 :: v_dual_mov_b32 v13, s19
	v_dual_mov_b32 v11, s17 :: v_dual_mov_b32 v12, s18
	s_clause 0x3
	global_store_b128 v[1:2], v[4:7], off
	global_store_b128 v[1:2], v[10:13], off offset:16
	global_store_b128 v[1:2], v[10:13], off offset:32
	global_store_b128 v[1:2], v[10:13], off offset:48
	s_and_saveexec_b32 s8, s2
	s_cbranch_execz .LBB0_213
; %bb.206:
	v_dual_mov_b32 v12, 0 :: v_dual_mov_b32 v13, s6
	v_mov_b32_e32 v14, s7
	s_clause 0x1
	global_load_b64 v[15:16], v12, s[4:5] offset:32 glc
	global_load_b64 v[4:5], v12, s[4:5] offset:40
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s12, v4
	v_readfirstlane_b32 s13, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[12:13], s[12:13], s[6:7]
	s_mul_i32 s9, s13, 24
	s_mul_hi_u32 s13, s12, 24
	s_mul_i32 s12, s12, 24
	s_add_i32 s13, s13, s9
	v_add_co_u32 v10, vcc_lo, v8, s12
	v_add_co_ci_u32_e32 v11, vcc_lo, s13, v9, vcc_lo
	s_mov_b32 s9, exec_lo
	global_store_b64 v[10:11], v[15:16], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[6:7], v12, v[13:16], s[4:5] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[6:7], v[15:16]
	s_cbranch_execz .LBB0_209
; %bb.207:                              ; %.preheader1.i.i.i53.preheader
	s_mov_b32 s12, 0
.LBB0_208:                              ; %.preheader1.i.i.i53
                                        ; =>This Inner Loop Header: Depth=1
	v_dual_mov_b32 v4, s6 :: v_dual_mov_b32 v5, s7
	s_sleep 1
	global_store_b64 v[10:11], v[6:7], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[4:5], v12, v[4:7], s[4:5] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
	v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
	s_or_b32 s12, vcc_lo, s12
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s12
	s_cbranch_execnz .LBB0_208
.LBB0_209:                              ; %Flow390
	s_or_b32 exec_lo, exec_lo, s9
	v_mov_b32_e32 v7, 0
	s_mov_b32 s12, exec_lo
	s_mov_b32 s9, exec_lo
	v_mbcnt_lo_u32_b32 v6, s12, 0
	global_load_b64 v[4:5], v7, s[4:5] offset:16
	v_cmpx_eq_u32_e32 0, v6
	s_cbranch_execz .LBB0_211
; %bb.210:
	s_bcnt1_i32_b32 s12, s12
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v6, s12
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[4:5], v[6:7], off offset:8
.LBB0_211:
	s_or_b32 exec_lo, exec_lo, s9
	s_waitcnt vmcnt(0)
	global_load_b64 v[6:7], v[4:5], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[6:7]
	s_cbranch_vccnz .LBB0_213
; %bb.212:
	global_load_b32 v4, v[4:5], off offset:24
	v_mov_b32_e32 v5, 0
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s9, v4
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[6:7], v[4:5], off
	s_and_b32 m0, s9, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_213:                              ; %Flow391
	s_or_b32 exec_lo, exec_lo, s8
	s_add_i32 s10, s10, s3
	v_add_co_u32 v4, vcc_lo, v8, s11
	v_add_co_ci_u32_e32 v5, vcc_lo, s10, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, v4, 20
	v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
.LBB0_214:                              ; =>This Inner Loop Header: Depth=1
	v_mov_b32_e32 v6, 1
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_216
; %bb.215:                              ;   in Loop: Header=BB0_214 Depth=1
	global_load_b32 v6, v[4:5], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v6, 1, v6
.LBB0_216:                              ;   in Loop: Header=BB0_214 Depth=1
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s3, v6
	s_cmp_eq_u32 s3, 0
	s_cbranch_scc1 .LBB0_218
; %bb.217:                              ;   in Loop: Header=BB0_214 Depth=1
	s_mov_b32 s3, 0
	s_sleep 1
	s_branch .LBB0_219
.LBB0_218:                              ;   in Loop: Header=BB0_214 Depth=1
	s_mov_b32 s3, -1
.LBB0_219:                              ; %Flow385
                                        ;   in Loop: Header=BB0_214 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s3
	s_cbranch_vccnz .LBB0_214
; %bb.220:
	global_load_b64 v[1:2], v[1:2], off
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_224
; %bb.221:
	v_mov_b32_e32 v10, 0
	s_clause 0x2
	global_load_b64 v[6:7], v10, s[4:5] offset:40
	global_load_b64 v[11:12], v10, s[4:5] offset:24 glc
	global_load_b64 v[8:9], v10, s[4:5]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v13, vcc_lo, v6, 1
	v_add_co_ci_u32_e32 v14, vcc_lo, 0, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, v13, s6
	v_add_co_ci_u32_e32 v5, vcc_lo, s7, v14, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
	v_dual_cndmask_b32 v5, v5, v14 :: v_dual_cndmask_b32 v4, v4, v13
	v_and_b32_e32 v7, v5, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v6, v4, v6
	v_mul_lo_u32 v7, v7, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v13, v6, 24
	v_mul_lo_u32 v6, v6, 24
	v_add_nc_u32_e32 v7, v13, v7
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v8, vcc_lo, v8, v6
	v_mov_b32_e32 v6, v11
	v_add_co_ci_u32_e32 v9, vcc_lo, v9, v7, vcc_lo
	v_mov_b32_e32 v7, v12
	global_store_b64 v[8:9], v[11:12], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[6:7], v10, v[4:7], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[6:7], v[11:12]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_224
; %bb.222:                              ; %.preheader.i.i.i52.preheader
	s_mov_b32 s2, 0
.LBB0_223:                              ; %.preheader.i.i.i52
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	global_store_b64 v[8:9], v[6:7], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[11:12], v10, v[4:7], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[11:12], v[6:7]
	v_dual_mov_b32 v6, v11 :: v_dual_mov_b32 v7, v12
	s_or_b32 s2, vcc_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s2
	s_cbranch_execnz .LBB0_223
.LBB0_224:                              ; %__ockl_printf_append_args.exit56
	s_or_b32 exec_lo, exec_lo, s3
	;;#ASMSTART
	;;#ASMEND
	v_readfirstlane_b32 s2, v3
	v_mov_b32_e32 v9, 0
	v_mov_b32_e32 v10, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_eq_u32_e64 s2, s2, v3
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_230
; %bb.225:
	v_mov_b32_e32 v4, 0
	s_mov_b32 s6, exec_lo
	global_load_b64 v[7:8], v4, s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[5:6], v4, s[4:5] offset:40
	global_load_b64 v[9:10], v4, s[4:5]
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v5, v5, v7
	v_and_b32_e32 v6, v6, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v11, v5, 24
	v_mul_lo_u32 v6, v6, 24
	v_mul_lo_u32 v5, v5, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v6, v11, v6
	s_waitcnt vmcnt(0)
	v_add_co_u32 v5, vcc_lo, v9, v5
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v6, vcc_lo, v10, v6, vcc_lo
	global_load_b64 v[5:6], v[5:6], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[9:10], v4, v[5:8], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[9:10], v[7:8]
	s_cbranch_execz .LBB0_229
; %bb.226:                              ; %.preheader3.i.i.i63.preheader
	s_mov_b32 s7, 0
.LBB0_227:                              ; %.preheader3.i.i.i63
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[5:6], v4, s[4:5] offset:40
	global_load_b64 v[11:12], v4, s[4:5]
	v_dual_mov_b32 v7, v9 :: v_dual_mov_b32 v8, v10
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v5, v5, v7
	v_and_b32_e32 v6, v6, v8
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[9:10], null, v5, 24, v[11:12]
	v_mov_b32_e32 v5, v10
	s_delay_alu instid0(VALU_DEP_1)
	v_mad_u64_u32 v[10:11], null, v6, 24, v[5:6]
	global_load_b64 v[5:6], v[9:10], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[9:10], v4, v[5:8], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[9:10], v[7:8]
	s_or_b32 s7, vcc_lo, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s7
	s_cbranch_execnz .LBB0_227
; %bb.228:                              ; %Flow378
	s_or_b32 exec_lo, exec_lo, s7
.LBB0_229:                              ; %Flow380
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s6
.LBB0_230:                              ; %.loopexit4.i.i.i57
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s3
	v_mov_b32_e32 v4, 0
	v_readfirstlane_b32 s6, v9
	v_readfirstlane_b32 s7, v10
	s_mov_b32 s12, exec_lo
	s_clause 0x1
	global_load_b64 v[11:12], v4, s[4:5] offset:40
	global_load_b128 v[5:8], v4, s[4:5]
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s8, v11
	v_readfirstlane_b32 s9, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[8:9], s[6:7], s[8:9]
	s_mul_i32 s3, s9, 24
	s_mul_hi_u32 s10, s8, 24
	s_mul_i32 s11, s8, 24
	s_and_saveexec_b32 s13, s2
	s_cbranch_execz .LBB0_232
; %bb.231:
	v_dual_mov_b32 v9, s12 :: v_dual_mov_b32 v10, v4
	s_add_i32 s12, s10, s3
	s_waitcnt vmcnt(0)
	v_add_co_u32 v13, vcc_lo, v5, s11
	v_add_co_ci_u32_e32 v14, vcc_lo, s12, v6, vcc_lo
	v_dual_mov_b32 v11, 2 :: v_dual_mov_b32 v12, 1
	global_store_b128 v[13:14], v[9:12], off offset:8
.LBB0_232:
	s_or_b32 exec_lo, exec_lo, s13
	s_lshl_b64 s[8:9], s[8:9], 12
	v_lshlrev_b64 v[9:10], 6, v[3:4]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v3, vcc_lo, v7, s8
	v_add_co_ci_u32_e32 v7, vcc_lo, s9, v8, vcc_lo
	s_mov_b32 s16, 0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v11, vcc_lo, v3, v9
	s_mov_b32 s17, s16
	s_mov_b32 s18, s16
	s_mov_b32 s19, s16
	v_and_or_b32 v1, 0xffffff1d, v1, 34
	v_add_co_ci_u32_e32 v12, vcc_lo, v7, v10, vcc_lo
	v_mov_b32_e32 v3, s15
	v_dual_mov_b32 v7, s16 :: v_dual_mov_b32 v10, s19
	v_dual_mov_b32 v8, s17 :: v_dual_mov_b32 v9, s18
	s_clause 0x3
	global_store_b128 v[11:12], v[1:4], off
	global_store_b128 v[11:12], v[7:10], off offset:16
	global_store_b128 v[11:12], v[7:10], off offset:32
	global_store_b128 v[11:12], v[7:10], off offset:48
	s_and_saveexec_b32 s8, s2
	s_cbranch_execz .LBB0_240
; %bb.233:
	v_dual_mov_b32 v9, 0 :: v_dual_mov_b32 v10, s6
	v_mov_b32_e32 v11, s7
	s_clause 0x1
	global_load_b64 v[12:13], v9, s[4:5] offset:32 glc
	global_load_b64 v[1:2], v9, s[4:5] offset:40
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s12, v1
	v_readfirstlane_b32 s13, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[12:13], s[12:13], s[6:7]
	s_mul_i32 s9, s13, 24
	s_mul_hi_u32 s13, s12, 24
	s_mul_i32 s12, s12, 24
	s_add_i32 s13, s13, s9
	v_add_co_u32 v7, vcc_lo, v5, s12
	v_add_co_ci_u32_e32 v8, vcc_lo, s13, v6, vcc_lo
	s_mov_b32 s9, exec_lo
	global_store_b64 v[7:8], v[12:13], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[3:4], v9, v[10:13], s[4:5] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[3:4], v[12:13]
	s_cbranch_execz .LBB0_236
; %bb.234:                              ; %.preheader1.i.i.i61.preheader
	s_mov_b32 s12, 0
.LBB0_235:                              ; %.preheader1.i.i.i61
                                        ; =>This Inner Loop Header: Depth=1
	v_dual_mov_b32 v1, s6 :: v_dual_mov_b32 v2, s7
	s_sleep 1
	global_store_b64 v[7:8], v[3:4], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[1:2], v9, v[1:4], s[4:5] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[1:2], v[3:4]
	v_dual_mov_b32 v4, v2 :: v_dual_mov_b32 v3, v1
	s_or_b32 s12, vcc_lo, s12
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s12
	s_cbranch_execnz .LBB0_235
.LBB0_236:                              ; %Flow376
	s_or_b32 exec_lo, exec_lo, s9
	v_mov_b32_e32 v4, 0
	s_mov_b32 s12, exec_lo
	s_mov_b32 s9, exec_lo
	v_mbcnt_lo_u32_b32 v3, s12, 0
	global_load_b64 v[1:2], v4, s[4:5] offset:16
	v_cmpx_eq_u32_e32 0, v3
	s_cbranch_execz .LBB0_238
; %bb.237:
	s_bcnt1_i32_b32 s12, s12
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v3, s12
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[1:2], v[3:4], off offset:8
.LBB0_238:
	s_or_b32 exec_lo, exec_lo, s9
	s_waitcnt vmcnt(0)
	global_load_b64 v[3:4], v[1:2], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[3:4]
	s_cbranch_vccnz .LBB0_240
; %bb.239:
	global_load_b32 v1, v[1:2], off offset:24
	v_mov_b32_e32 v2, 0
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s9, v1
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[3:4], v[1:2], off
	s_and_b32 m0, s9, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_240:                              ; %Flow377
	s_or_b32 exec_lo, exec_lo, s8
	s_add_i32 s10, s10, s3
	v_add_co_u32 v1, vcc_lo, v5, s11
	v_add_co_ci_u32_e32 v2, vcc_lo, s10, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, v1, 20
	v_add_co_ci_u32_e32 v2, vcc_lo, 0, v2, vcc_lo
.LBB0_241:                              ; =>This Inner Loop Header: Depth=1
	v_mov_b32_e32 v3, 1
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_243
; %bb.242:                              ;   in Loop: Header=BB0_241 Depth=1
	global_load_b32 v3, v[1:2], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v3, 1, v3
.LBB0_243:                              ;   in Loop: Header=BB0_241 Depth=1
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s3, v3
	s_cmp_eq_u32 s3, 0
	s_cbranch_scc1 .LBB0_245
; %bb.244:                              ;   in Loop: Header=BB0_241 Depth=1
	s_mov_b32 s3, 0
	s_sleep 1
	s_branch .LBB0_246
.LBB0_245:                              ;   in Loop: Header=BB0_241 Depth=1
	s_mov_b32 s3, -1
.LBB0_246:                              ; %Flow371
                                        ;   in Loop: Header=BB0_241 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s3
	s_cbranch_vccnz .LBB0_241
; %bb.247:
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_251
; %bb.248:
	v_mov_b32_e32 v7, 0
	s_clause 0x2
	global_load_b64 v[3:4], v7, s[4:5] offset:40
	global_load_b64 v[8:9], v7, s[4:5] offset:24 glc
	global_load_b64 v[5:6], v7, s[4:5]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v10, vcc_lo, v3, 1
	v_add_co_ci_u32_e32 v11, vcc_lo, 0, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, v10, s6
	v_add_co_ci_u32_e32 v2, vcc_lo, s7, v11, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[1:2]
	v_dual_cndmask_b32 v2, v2, v11 :: v_dual_cndmask_b32 v1, v1, v10
	v_and_b32_e32 v4, v2, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v3, v1, v3
	v_mul_lo_u32 v4, v4, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v10, v3, 24
	v_mul_lo_u32 v3, v3, 24
	v_add_nc_u32_e32 v4, v10, v4
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v5, vcc_lo, v5, v3
	v_mov_b32_e32 v3, v8
	v_add_co_ci_u32_e32 v6, vcc_lo, v6, v4, vcc_lo
	v_mov_b32_e32 v4, v9
	global_store_b64 v[5:6], v[8:9], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[3:4], v7, v[1:4], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[3:4], v[8:9]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_251
; %bb.249:                              ; %.preheader.i.i.i60.preheader
	s_mov_b32 s2, 0
.LBB0_250:                              ; %.preheader.i.i.i60
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	global_store_b64 v[5:6], v[3:4], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[8:9], v7, v[1:4], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[3:4]
	v_dual_mov_b32 v3, v8 :: v_dual_mov_b32 v4, v9
	s_or_b32 s2, vcc_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s2
	s_cbranch_execnz .LBB0_250
.LBB0_251:                              ; %__ockl_printf_append_args.exit64
	s_or_b32 exec_lo, exec_lo, s3
	s_load_b64 s[0:1], s[0:1], 0x8
	s_mul_i32 s3, s14, 0x78
	s_mul_i32 s4, s15, 0x5000
	v_add3_u32 v2, v0, s3, -4
	s_add_i32 s3, s3, s4
	v_mov_b32_e32 v1, 0
	v_add3_u32 v0, s3, v0, 0xfffff0fc
	s_lshl_b32 s2, s15, 4
	v_cmp_gt_u32_e32 vcc_lo, 0x500, v2
	s_mov_b32 s3, -3
	s_waitcnt lgkmcnt(0)
	s_add_u32 s0, s0, 28
	s_addc_u32 s1, s1, 0
.LBB0_252:                              ; =>This Inner Loop Header: Depth=1
	s_add_i32 s4, s2, s3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_cmp_gt_i32 s4, -1
	s_cselect_b32 s5, -1, 0
	s_and_b32 s5, vcc_lo, s5
	s_cmpk_lt_i32 s4, 0x2d0
	s_cselect_b32 s4, -1, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s5, s5, s4
	s_and_saveexec_b32 s4, s5
; %bb.253:                              ;   in Loop: Header=BB0_252 Depth=1
	v_mul_hi_u32 v2, 0xcccccccd, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshrrev_b32_e32 v2, 10, v2
	v_mul_u32_u24_e32 v3, 0x500, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_sub_nc_u32_e32 v3, v0, v3
	s_clause 0x1
	global_store_b32 v1, v2, s[0:1] offset:-28
	global_store_b32 v1, v3, s[0:1]
; %bb.254:                              ;   in Loop: Header=BB0_252 Depth=1
	s_or_b32 exec_lo, exec_lo, s4
	s_add_i32 s3, s3, 1
	v_add_nc_u32_e32 v0, 0x500, v0
	s_add_u32 s0, s0, 4
	s_addc_u32 s1, s1, 0
	s_cmp_eq_u32 s3, 4
	s_cbranch_scc0 .LBB0_252
; %bb.255:
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _ZL15censusTransformiiPi
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 33
		.amdhsa_next_free_sgpr 24
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._ZL15censusTransformiiPi,"axG",@progbits,_ZL15censusTransformiiPi,comdat
.Lfunc_end0:
	.size	_ZL15censusTransformiiPi, .Lfunc_end0-_ZL15censusTransformiiPi
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 10976
; NumSgprs: 26
; NumVgprs: 33
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 4
; NumSGPRsForWavesPerEU: 26
; NumVGPRsForWavesPerEU: 33
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	.str,@object                    ; @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.str:
	.asciz	"block Dim (%d %d) (%d %d) \n"
	.size	.str, 28

	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     by_value
      - .offset:         4
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         20
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         28
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         30
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         32
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         34
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         36
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         38
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         56
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         80
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         96
        .size:           8
        .value_kind:     hidden_hostcall_buffer
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 272
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _ZL15censusTransformiiPi
    .private_segment_fixed_size: 0
    .sgpr_count:     26
    .sgpr_spill_count: 0
    .symbol:         _ZL15censusTransformiiPi.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     33
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
