#include <stdio.h>
#include <math.h>
#include <stdlib.h>
#include <time.h>

#include <cuda.h>
#include <curand.h>

#define CUDA_CALL(x) do { if((x)!=cudaSuccess) { \
    printf("Error at %s:%d\n",__FILE__,__LINE__);\
    return EXIT_FAILURE;}} while(0)
    
#define DEPTH 5 // no of layers
#define BREADTH 1000 // nodes per layer
#define RATE 0.0001 // learning rate

#define NDIM(a,b) ((a)*BREADTH+(b)) 
#define WDIM(a,b,c) ((a)*BREADTH*BREADTH+(b)*BREADTH+(c))

float *W, *R; // [DEPTH-1][BREADTH][BREADTH] W_kij : weight of edge b/w jth and ith node from kth layer and k+1th layer resp. 
float *N; // [DEPTH][BREADTH] N_ki : jth node in kth layer
float *Y, *pY; // [BREADTH] expected and predicted output vectors
float *U, *V; // [BREADTH] vectors for backpropagation chain-rule

float Yh[BREADTH], Dh[BREADTH]; // host arrays: expected and predicted output
int count = 0;

#define f(x) (tanhf((x))) // activation function
#define df(y) (1 - (y) * (y)) // derivative of activation function in y terms


__global__ void predict_N( float *N) { // feedforward pass algorithm
    int tid = blockIdx.x * blockDim.x + threadIdx.x;
    int stride = gridDim.x * blockDim.x;
    int i;
     // erase all nodes except first layer
    for ( i = tid + BREADTH ; i < BREADTH * DEPTH ; i += stride )
        N[i] = 0;
}


__global__ void predict_WN( float *N, float *W, float *R, int k) { // feedforward pass algorithm
    int tid = blockIdx.x * blockDim.x + threadIdx.x;
    int stride = gridDim.x * blockDim.x;
    int h;

    // matrix-vector multiplication W*N b/w k-1th and kth layer
    int wIndex = k * BREADTH * BREADTH; 
    int nIndex = k * BREADTH; 
    for ( h = tid ; h < BREADTH * BREADTH ; h += stride ) {
        int j = h % BREADTH;
        R[h] = W[wIndex + h] * N[nIndex + j];
    }
}

__global__ void predict_Ri( float *R, int n, int j) { // feedforward pass algorithm
    int tid = blockIdx.x * blockDim.x + threadIdx.x;
    int stride = gridDim.x * blockDim.x;

    int i;
    for ( i = tid % BREADTH ; i < BREADTH ; i += stride ) {

        int itid = tid / BREADTH;
        int istride = stride / BREADTH;
        istride += (istride == 0);

        int rIndex = i * BREADTH;
        
        for ( int h = 2 * j * itid; h < j * (n - 1); h += 2 * j * istride)
            R[rIndex + h] += R[rIndex + h + j];
    }
}

__global__ void predict_Nk( float *N, float *R, int k) { // feedforward pass algorithm
    int tid = blockIdx.x * blockDim.x + threadIdx.x;
    int stride = gridDim.x * blockDim.x;

    int i;    
    for ( i = tid; i < BREADTH; i += stride )
        N[NDIM(k,i)] = f( R[NDIM(i,0)]);
}

__global__ void predict_Yp( float *N, float *pY) { // feedforward pass algorithm
    int tid = blockIdx.x * blockDim.x + threadIdx.x;
    int stride = gridDim.x * blockDim.x;

    int i;    
    for ( i = tid; i < BREADTH; i += stride )
        pY[i] = N[NDIM(DEPTH-1,i)];
}


__global__ void train_V( float *N, float *Y, float *V) {    

    int tid = blockIdx.x * blockDim.x + threadIdx.x;
    int stride = gridDim.x * blockDim.x;
    
    int q = DEPTH - 2;

    // caching chain-rule calculation in vector to aid in backpropagation
    for ( int i = tid; i < BREADTH; i += stride ) {
        V[i] = (N[NDIM(q+1,i)] - Y[i]) * df( N[NDIM(q+1,i)]);
    }
}

__global__ void train_Wf( float *N, float *W, float *V) {    

    int tid = blockIdx.x * blockDim.x + threadIdx.x;
    int stride = gridDim.x * blockDim.x;
    
    int q = DEPTH - 2, h;

    // update weights of outer layer
    for ( h = tid; h < BREADTH * BREADTH; h += stride ) {
        int i = h / BREADTH;
        int j = h % BREADTH;
        W[WDIM(q,i,j)] -= (float)RATE * V[i] * N[NDIM(q,j)];
    }
}

__global__ void train_WN( float *N, float *W, float *A, float *R, int k) { // feedforward pass algorithm
    int tid = blockIdx.x * blockDim.x + threadIdx.x;
    int stride = gridDim.x * blockDim.x;
    int h;

    // matrix-vector multiplication W*N b/w k-1th and kth layer
    int wIndex = k * BREADTH * BREADTH; 
    int nIndex = k * BREADTH; 
    for ( h = tid ; h < BREADTH * BREADTH ; h += stride ) {
        int j = h % BREADTH;
        int i = h / BREADTH;
        R[NDIM(j,i)] = A[i] * W[wIndex + h] * df( N[nIndex + j]);
    }
}

__global__ void train_B( float *R, float *B) { // feedforward pass algorithm
    int tid = blockIdx.x * blockDim.x + threadIdx.x;
    int stride = gridDim.x * blockDim.x;

    int i;    
    for ( i = tid; i < BREADTH; i += stride )
        B[i] = R[NDIM(i,0)];
}

__global__ void train_Wh( float *N, float *W, float *A, int k) { // feedforward pass algorithm
    int tid = blockIdx.x * blockDim.x + threadIdx.x;
    int stride = gridDim.x * blockDim.x;
    int h;

    // matrix-vector multiplication W*N b/w k-1th and kth layer
    int wIndex = k * BREADTH * BREADTH; 
    int nIndex = k * BREADTH; 
    for ( h = tid ; h < BREADTH * BREADTH ; h += stride ) {
        int j = h % BREADTH;
        int i = h / BREADTH;
        W[wIndex + h] -= (float)RATE * A[i] * N[nIndex + j];
    }
}


void train() {

    train_V<<<128, 32>>>( N, Y, V);
    cudaDeviceSynchronize();

    train_Wf<<<128, 32>>>( N, W, V);
    cudaDeviceSynchronize();
    
    int q = DEPTH - 2;

    float *A = &V[0], *B = &U[0];
    float *temp;

    // updating weights of hidden layers (backpropagation)
    for ( int k = q - 1; k >= 0; k-- ) {      

        // chain-rule expansion by multiplying with next layer's weight matrix and 
        // derivative of activation function on the same layer's nodes
        train_WN<<<128, 32>>>( N, W, A, R, k+1);
        cudaDeviceSynchronize();

        int j = 1;
        int n = BREADTH;
        while ( n > 1) {
            predict_Ri<<<128, 32>>>( R, n, j);
            cudaDeviceSynchronize();

            j *= 2;
            n = (n+1)/2;
        }

        train_B<<<128, 32>>>( R, B);
        cudaDeviceSynchronize();

        temp = B;        B = A;        A = temp;

        // adjust weights by gradient descent
        train_Wh<<<128, 32>>>( N, W, A, k);
        cudaDeviceSynchronize();
    }
}


__global__ void normalize( float *W, float *N, float *Y) {    

    int tid = blockIdx.x * blockDim.x + threadIdx.x;
    int stride = gridDim.x * blockDim.x;
    int i, w = (DEPTH-1) * BREADTH * BREADTH;

    for ( i = tid; i < w; i+= stride)
        W[i] = 1/ (float)BREADTH;

    for ( i = tid; i < BREADTH; i+= stride)
        N[i] = i/ (float)BREADTH;

    for ( i = tid; i < BREADTH; i+= stride)
        Y[i] = i/ (float)BREADTH;
}

void initialize() {
    int w = (DEPTH-1) * BREADTH * BREADTH;

    // device memory allocation of global arrays
    cudaMalloc( (void**)(&W), sizeof(float) * w);
    cudaMalloc( (void**)(&R), sizeof(float) * BREADTH * BREADTH);
    cudaMalloc( (void**)(&N), sizeof(float) * DEPTH * BREADTH);
    cudaMalloc( (void**)(&Y), sizeof(float) * BREADTH);
    cudaMalloc( (void**)(&pY), sizeof(float) * BREADTH);
    cudaMalloc( (void**)(&U), sizeof(float) * BREADTH);
    cudaMalloc( (void**)(&V), sizeof(float) * BREADTH);

    /*
    // random number generator
    curandGenerator_t gen;

    // Create pseudo-random number generator 
    curandCreateGenerator(&gen, CURAND_RNG_PSEUDO_DEFAULT);

    // Set seed 
    curandSetPseudoRandomGeneratorSeed(gen, time(0));

    // Generate floats on device
    curandGenerateUniform(gen, W, w);
    curandGenerateUniform(gen, N, BREADTH * DEPTH);
    curandGenerateUniform(gen, Y, BREADTH);

    curandDestroyGenerator(gen);
    */
    
    normalize<<<128, 32>>>(W, N, Y);
    cudaDeviceSynchronize();
}

void calculateError() {
    float err = 0, dY;

    // dY : difference b/w expected and predicted output, and
    // err : sum of squares of dY

    for ( int i = 0 ; i < BREADTH ; i++ ) {
        dY = (Dh[i] - Yh[i]);
        err += dY * dY;
    }
    printf("ITERATION : %d\tLOSS : %f\t", count, err);
}

void freeResources() {
    cudaFree(Y);
    cudaFree(N);
    cudaFree(W);
    cudaFree(pY);
    cudaFree(U);
    cudaFree(V);
    cudaFree(R);
}

void predict() {

    predict_N<<<128, 32>>>(N);
    cudaDeviceSynchronize();
    
    for ( int k = 1; k < DEPTH ; k++ ) {
        predict_WN<<<128, 32>>>( N, W, R, k-1);
        cudaDeviceSynchronize();

        int j = 1;
        int n = BREADTH;
        while ( n > 1) {
            predict_Ri<<<128, 32>>>( R, n, j);
            cudaDeviceSynchronize();

            j *= 2;
            n = (n+1)/2;
        }

        predict_Nk<<<128, 32>>>( N, R, k);
        cudaDeviceSynchronize();
    }
    predict_Yp<<<128, 32>>>( N, pY);
    cudaDeviceSynchronize();
}

int main() {

    initialize();

    for ( count = 0; count < 4; count++) {

        clock_t begin, end;
        begin = clock();

        predict();
        train();

        end = clock();
        float CpuTime = (float)(end - begin) / CLOCKS_PER_SEC;

        CUDA_CALL(cudaMemcpy(Yh, Y, BREADTH * sizeof(float), cudaMemcpyDeviceToHost));
        CUDA_CALL(cudaMemcpy(Dh, pY, BREADTH * sizeof(float), cudaMemcpyDeviceToHost));

        calculateError();
        printf("TIME: %f\n", CpuTime);
    }

    freeResources();

    return 0;
}

	.file	"tmpxft_0033daa5_00000000-6_deep.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2035:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2035:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC1:
	.string	"ITERATION : %d\tLOSS : %f\t"
	.text
	.globl	_Z14calculateErrorv
	.type	_Z14calculateErrorv, @function
_Z14calculateErrorv:
.LFB2029:
	.cfi_startproc
	endbr64
	xorl	%eax, %eax
	xorps	%xmm0, %xmm0
	leaq	Dh(%rip), %rcx
	leaq	Yh(%rip), %rdx
.L3:
	movss	(%rcx,%rax), %xmm1
	subss	(%rdx,%rax), %xmm1
	addq	$4, %rax
	mulss	%xmm1, %xmm1
	addss	%xmm1, %xmm0
	cmpq	$4000, %rax
	jne	.L3
	movl	count(%rip), %edx
	leaq	.LC1(%rip), %rsi
	movl	$2, %edi
	movb	$1, %al
	cvtss2sd	%xmm0, %xmm0
	jmp	__printf_chk@PLT
	.cfi_endproc
.LFE2029:
	.size	_Z14calculateErrorv, .-_Z14calculateErrorv
	.globl	_Z13freeResourcesv
	.type	_Z13freeResourcesv, @function
_Z13freeResourcesv:
.LFB2030:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	movq	Y(%rip), %rdi
	call	cudaFree@PLT
	movq	N(%rip), %rdi
	call	cudaFree@PLT
	movq	W(%rip), %rdi
	call	cudaFree@PLT
	movq	pY(%rip), %rdi
	call	cudaFree@PLT
	movq	U(%rip), %rdi
	call	cudaFree@PLT
	movq	V(%rip), %rdi
	call	cudaFree@PLT
	movq	R(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	cudaFree@PLT
	.cfi_endproc
.LFE2030:
	.size	_Z13freeResourcesv, .-_Z13freeResourcesv
	.globl	_Z28__device_stub__Z9predict_NPfPf
	.type	_Z28__device_stub__Z9predict_NPfPf, @function
_Z28__device_stub__Z9predict_NPfPf:
.LFB2057:
	.cfi_startproc
	endbr64
	subq	$104, %rsp
	.cfi_def_cfa_offset 112
	movq	%rdi, 8(%rsp)
	leaq	24(%rsp), %rcx
	leaq	16(%rsp), %rdx
	leaq	44(%rsp), %rsi
	leaq	32(%rsp), %rdi
	movq	%fs:40, %rax
	movq	%rax, 88(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 40(%rsp)
	movq	%rax, 80(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 32(%rsp)
	movq	%rax, 44(%rsp)
	movl	$1, 52(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L8
	pushq	24(%rsp)
	.cfi_def_cfa_offset 120
	leaq	_Z9predict_NPf(%rip), %rdi
	pushq	24(%rsp)
	.cfi_def_cfa_offset 128
	movq	60(%rsp), %rcx
	movl	68(%rsp), %r8d
	movq	48(%rsp), %rsi
	movl	56(%rsp), %edx
	leaq	96(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 120
	popq	%rdx
	.cfi_def_cfa_offset 112
.L8:
	movq	88(%rsp), %rax
	subq	%fs:40, %rax
	je	.L10
	call	__stack_chk_fail@PLT
.L10:
	addq	$104, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2057:
	.size	_Z28__device_stub__Z9predict_NPfPf, .-_Z28__device_stub__Z9predict_NPfPf
	.globl	_Z9predict_NPf
	.type	_Z9predict_NPf, @function
_Z9predict_NPf:
.LFB2058:
	.cfi_startproc
	endbr64
	jmp	_Z28__device_stub__Z9predict_NPfPf
	.cfi_endproc
.LFE2058:
	.size	_Z9predict_NPf, .-_Z9predict_NPf
	.globl	_Z35__device_stub__Z10predict_WNPfS_S_iPfS_S_i
	.type	_Z35__device_stub__Z10predict_WNPfS_S_iPfS_S_i, @function
_Z35__device_stub__Z10predict_WNPfS_S_iPfS_S_i:
.LFB2059:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 4(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L13
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z10predict_WNPfS_S_i(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L13:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L15
	call	__stack_chk_fail@PLT
.L15:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2059:
	.size	_Z35__device_stub__Z10predict_WNPfS_S_iPfS_S_i, .-_Z35__device_stub__Z10predict_WNPfS_S_iPfS_S_i
	.globl	_Z10predict_WNPfS_S_i
	.type	_Z10predict_WNPfS_S_i, @function
_Z10predict_WNPfS_S_i:
.LFB2060:
	.cfi_startproc
	endbr64
	jmp	_Z35__device_stub__Z10predict_WNPfS_S_iPfS_S_i
	.cfi_endproc
.LFE2060:
	.size	_Z10predict_WNPfS_S_i, .-_Z10predict_WNPfS_S_i
	.globl	_Z32__device_stub__Z10predict_RiPfiiPfii
	.type	_Z32__device_stub__Z10predict_RiPfiiPfii, @function
_Z32__device_stub__Z10predict_RiPfiiPfii:
.LFB2061:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 8(%rsp)
	leaq	24(%rsp), %rcx
	leaq	32(%rsp), %rdi
	movl	%esi, 4(%rsp)
	leaq	44(%rsp), %rsi
	movl	%edx, (%rsp)
	leaq	16(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 40(%rsp)
	movq	%rax, 80(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 88(%rsp)
	movq	%rsp, %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 32(%rsp)
	movq	%rax, 44(%rsp)
	movl	$1, 52(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L18
	pushq	24(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z10predict_RiPfii(%rip), %rdi
	pushq	24(%rsp)
	.cfi_def_cfa_offset 144
	movq	60(%rsp), %rcx
	movl	68(%rsp), %r8d
	movq	48(%rsp), %rsi
	movl	56(%rsp), %edx
	leaq	96(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L18:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L20
	call	__stack_chk_fail@PLT
.L20:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2061:
	.size	_Z32__device_stub__Z10predict_RiPfiiPfii, .-_Z32__device_stub__Z10predict_RiPfiiPfii
	.globl	_Z10predict_RiPfii
	.type	_Z10predict_RiPfii, @function
_Z10predict_RiPfii:
.LFB2062:
	.cfi_startproc
	endbr64
	jmp	_Z32__device_stub__Z10predict_RiPfiiPfii
	.cfi_endproc
.LFE2062:
	.size	_Z10predict_RiPfii, .-_Z10predict_RiPfii
	.globl	_Z33__device_stub__Z10predict_NkPfS_iPfS_i
	.type	_Z33__device_stub__Z10predict_NkPfS_iPfS_i, @function
_Z33__device_stub__Z10predict_NkPfS_iPfS_i:
.LFB2063:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L23
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z10predict_NkPfS_i(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L23:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L25
	call	__stack_chk_fail@PLT
.L25:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2063:
	.size	_Z33__device_stub__Z10predict_NkPfS_iPfS_i, .-_Z33__device_stub__Z10predict_NkPfS_iPfS_i
	.globl	_Z10predict_NkPfS_i
	.type	_Z10predict_NkPfS_i, @function
_Z10predict_NkPfS_i:
.LFB2064:
	.cfi_startproc
	endbr64
	jmp	_Z33__device_stub__Z10predict_NkPfS_iPfS_i
	.cfi_endproc
.LFE2064:
	.size	_Z10predict_NkPfS_i, .-_Z10predict_NkPfS_i
	.globl	_Z32__device_stub__Z10predict_YpPfS_PfS_
	.type	_Z32__device_stub__Z10predict_YpPfS_PfS_, @function
_Z32__device_stub__Z10predict_YpPfS_PfS_:
.LFB2065:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 8(%rsp)
	leaq	32(%rsp), %rcx
	leaq	24(%rsp), %rdx
	movq	%rsi, (%rsp)
	leaq	40(%rsp), %rdi
	leaq	52(%rsp), %rsi
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 48(%rsp)
	movq	%rax, 88(%rsp)
	movq	%rsp, %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L28
	pushq	32(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z10predict_YpPfS_(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 144
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	104(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L28:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L30
	call	__stack_chk_fail@PLT
.L30:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2065:
	.size	_Z32__device_stub__Z10predict_YpPfS_PfS_, .-_Z32__device_stub__Z10predict_YpPfS_PfS_
	.globl	_Z10predict_YpPfS_
	.type	_Z10predict_YpPfS_, @function
_Z10predict_YpPfS_:
.LFB2066:
	.cfi_startproc
	endbr64
	jmp	_Z32__device_stub__Z10predict_YpPfS_PfS_
	.cfi_endproc
.LFE2066:
	.size	_Z10predict_YpPfS_, .-_Z10predict_YpPfS_
	.globl	_Z7predictv
	.type	_Z7predictv, @function
_Z7predictv:
.LFB2031:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movl	$134217729, %edx
	movl	$33554433, %edi
	xorl	%r9d, %r9d
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	salq	$5, %rdx
	salq	$7, %rdi
	xorl	%r8d, %r8d
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movl	$1, %ecx
	movl	$1, %esi
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$40, %rsp
	.cfi_def_cfa_offset 96
	movq	%rdx, 20(%rsp)
	movl	$1, 28(%rsp)
	movq	%rdi, 8(%rsp)
	movl	$1, 16(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L34
	movq	N(%rip), %rdi
	call	_Z28__device_stub__Z9predict_NPfPf
.L34:
	movl	$134217729, %ebx
	movl	$33554433, %ebp
	movl	$1, %r12d
	call	cudaDeviceSynchronize@PLT
	salq	$5, %rbx
	salq	$7, %rbp
.L39:
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	%rbx, %rdx
	movl	$1, %ecx
	movq	%rbp, %rdi
	movl	$1, %esi
	movq	%rbx, 20(%rsp)
	movl	$1, 28(%rsp)
	movq	%rbp, 8(%rsp)
	movl	$1, 16(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L35
	movq	R(%rip), %rdx
	movq	W(%rip), %rsi
	leal	-1(%r12), %ecx
	movq	N(%rip), %rdi
	call	_Z35__device_stub__Z10predict_WNPfS_S_iPfS_S_i
.L35:
	call	cudaDeviceSynchronize@PLT
	movl	$10, %r14d
	movl	$1000, %r13d
	movl	$1, %r15d
.L37:
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	%rbx, %rdx
	movl	$1, %ecx
	movq	%rbp, %rdi
	movl	$1, %esi
	movq	%rbx, 20(%rsp)
	movl	$1, 28(%rsp)
	movq	%rbp, 8(%rsp)
	movl	$1, 16(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L36
	movq	R(%rip), %rdi
	movl	%r15d, %edx
	movl	%r13d, %esi
	call	_Z32__device_stub__Z10predict_RiPfiiPfii
.L36:
	call	cudaDeviceSynchronize@PLT
	incl	%r13d
	addl	%r15d, %r15d
	sarl	%r13d
	decl	%r14d
	jne	.L37
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	%rbx, %rdx
	movl	$1, %ecx
	movq	%rbp, %rdi
	movl	$1, %esi
	movq	%rbx, 20(%rsp)
	movl	$1, 28(%rsp)
	movq	%rbp, 8(%rsp)
	movl	$1, 16(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L38
	movq	R(%rip), %rsi
	movq	N(%rip), %rdi
	movl	%r12d, %edx
	call	_Z33__device_stub__Z10predict_NkPfS_iPfS_i
.L38:
	call	cudaDeviceSynchronize@PLT
	incl	%r12d
	cmpl	$5, %r12d
	jne	.L39
	movl	$134217729, %edx
	movl	$33554433, %edi
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	salq	$5, %rdx
	salq	$7, %rdi
	movl	$1, %ecx
	movl	$1, %esi
	movq	%rdx, 20(%rsp)
	movl	$1, 28(%rsp)
	movq	%rdi, 8(%rsp)
	movl	$1, 16(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L40
	movq	pY(%rip), %rsi
	movq	N(%rip), %rdi
	call	_Z32__device_stub__Z10predict_YpPfS_PfS_
.L40:
	addq	$40, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	cudaDeviceSynchronize@PLT
	.cfi_endproc
.LFE2031:
	.size	_Z7predictv, .-_Z7predictv
	.globl	_Z30__device_stub__Z7train_VPfS_S_PfS_S_
	.type	_Z30__device_stub__Z7train_VPfS_S_PfS_S_, @function
_Z30__device_stub__Z7train_VPfS_S_PfS_S_:
.LFB2067:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L44
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z7train_VPfS_S_(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L44:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L46
	call	__stack_chk_fail@PLT
.L46:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2067:
	.size	_Z30__device_stub__Z7train_VPfS_S_PfS_S_, .-_Z30__device_stub__Z7train_VPfS_S_PfS_S_
	.globl	_Z7train_VPfS_S_
	.type	_Z7train_VPfS_S_, @function
_Z7train_VPfS_S_:
.LFB2068:
	.cfi_startproc
	endbr64
	jmp	_Z30__device_stub__Z7train_VPfS_S_PfS_S_
	.cfi_endproc
.LFE2068:
	.size	_Z7train_VPfS_S_, .-_Z7train_VPfS_S_
	.globl	_Z31__device_stub__Z8train_WfPfS_S_PfS_S_
	.type	_Z31__device_stub__Z8train_WfPfS_S_PfS_S_, @function
_Z31__device_stub__Z8train_WfPfS_S_PfS_S_:
.LFB2069:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L49
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z8train_WfPfS_S_(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L49:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L51
	call	__stack_chk_fail@PLT
.L51:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2069:
	.size	_Z31__device_stub__Z8train_WfPfS_S_PfS_S_, .-_Z31__device_stub__Z8train_WfPfS_S_PfS_S_
	.globl	_Z8train_WfPfS_S_
	.type	_Z8train_WfPfS_S_, @function
_Z8train_WfPfS_S_:
.LFB2070:
	.cfi_startproc
	endbr64
	jmp	_Z31__device_stub__Z8train_WfPfS_S_PfS_S_
	.cfi_endproc
.LFE2070:
	.size	_Z8train_WfPfS_S_, .-_Z8train_WfPfS_S_
	.globl	_Z34__device_stub__Z8train_WNPfS_S_S_iPfS_S_S_i
	.type	_Z34__device_stub__Z8train_WNPfS_S_S_iPfS_S_S_i, @function
_Z34__device_stub__Z8train_WNPfS_S_S_iPfS_S_S_i:
.LFB2071:
	.cfi_startproc
	endbr64
	subq	$168, %rsp
	.cfi_def_cfa_offset 176
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	48(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	56(%rsp), %rcx
	movl	%r8d, 12(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 152(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 112(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 144(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L54
	pushq	56(%rsp)
	.cfi_def_cfa_offset 184
	leaq	_Z8train_WNPfS_S_S_i(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 192
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 184
	popq	%rdx
	.cfi_def_cfa_offset 176
.L54:
	movq	152(%rsp), %rax
	subq	%fs:40, %rax
	je	.L56
	call	__stack_chk_fail@PLT
.L56:
	addq	$168, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2071:
	.size	_Z34__device_stub__Z8train_WNPfS_S_S_iPfS_S_S_i, .-_Z34__device_stub__Z8train_WNPfS_S_S_iPfS_S_S_i
	.globl	_Z8train_WNPfS_S_S_i
	.type	_Z8train_WNPfS_S_S_i, @function
_Z8train_WNPfS_S_S_i:
.LFB2072:
	.cfi_startproc
	endbr64
	jmp	_Z34__device_stub__Z8train_WNPfS_S_S_iPfS_S_S_i
	.cfi_endproc
.LFE2072:
	.size	_Z8train_WNPfS_S_S_i, .-_Z8train_WNPfS_S_S_i
	.globl	_Z28__device_stub__Z7train_BPfS_PfS_
	.type	_Z28__device_stub__Z7train_BPfS_PfS_, @function
_Z28__device_stub__Z7train_BPfS_PfS_:
.LFB2073:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 8(%rsp)
	leaq	32(%rsp), %rcx
	leaq	24(%rsp), %rdx
	movq	%rsi, (%rsp)
	leaq	40(%rsp), %rdi
	leaq	52(%rsp), %rsi
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 48(%rsp)
	movq	%rax, 88(%rsp)
	movq	%rsp, %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L59
	pushq	32(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7train_BPfS_(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 144
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	104(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L59:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L61
	call	__stack_chk_fail@PLT
.L61:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2073:
	.size	_Z28__device_stub__Z7train_BPfS_PfS_, .-_Z28__device_stub__Z7train_BPfS_PfS_
	.globl	_Z7train_BPfS_
	.type	_Z7train_BPfS_, @function
_Z7train_BPfS_:
.LFB2074:
	.cfi_startproc
	endbr64
	jmp	_Z28__device_stub__Z7train_BPfS_PfS_
	.cfi_endproc
.LFE2074:
	.size	_Z7train_BPfS_, .-_Z7train_BPfS_
	.globl	_Z32__device_stub__Z8train_WhPfS_S_iPfS_S_i
	.type	_Z32__device_stub__Z8train_WhPfS_S_iPfS_S_i, @function
_Z32__device_stub__Z8train_WhPfS_S_iPfS_S_i:
.LFB2075:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 4(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L64
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z8train_WhPfS_S_i(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L64:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L66
	call	__stack_chk_fail@PLT
.L66:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2075:
	.size	_Z32__device_stub__Z8train_WhPfS_S_iPfS_S_i, .-_Z32__device_stub__Z8train_WhPfS_S_iPfS_S_i
	.globl	_Z8train_WhPfS_S_i
	.type	_Z8train_WhPfS_S_i, @function
_Z8train_WhPfS_S_i:
.LFB2076:
	.cfi_startproc
	endbr64
	jmp	_Z32__device_stub__Z8train_WhPfS_S_iPfS_S_i
	.cfi_endproc
.LFE2076:
	.size	_Z8train_WhPfS_S_i, .-_Z8train_WhPfS_S_i
	.globl	_Z5trainv
	.type	_Z5trainv, @function
_Z5trainv:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movl	$134217729, %edx
	movl	$33554433, %edi
	xorl	%r9d, %r9d
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	salq	$5, %rdx
	salq	$7, %rdi
	xorl	%r8d, %r8d
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movl	$1, %ecx
	movl	$1, %esi
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$56, %rsp
	.cfi_def_cfa_offset 112
	movq	%rdx, 36(%rsp)
	movl	$1, 44(%rsp)
	movq	%rdi, 24(%rsp)
	movl	$1, 32(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L70
	movq	V(%rip), %rdx
	movq	Y(%rip), %rsi
	movq	N(%rip), %rdi
	call	_Z30__device_stub__Z7train_VPfS_S_PfS_S_
.L70:
	call	cudaDeviceSynchronize@PLT
	movl	$134217729, %edx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$33554433, %edi
	salq	$5, %rdx
	movl	$1, %ecx
	movl	$1, %esi
	salq	$7, %rdi
	movq	%rdx, 36(%rsp)
	movl	$1, 44(%rsp)
	movq	%rdi, 24(%rsp)
	movl	$1, 32(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L71
	movq	V(%rip), %rdx
	movq	W(%rip), %rsi
	movq	N(%rip), %rdi
	call	_Z31__device_stub__Z8train_WfPfS_S_PfS_S_
.L71:
	call	cudaDeviceSynchronize@PLT
	movl	$134217729, %ebx
	movl	$33554433, %ebp
	movq	V(%rip), %r15
	movq	U(%rip), %r14
	movl	$2, %r12d
	salq	$5, %rbx
	salq	$7, %rbp
.L77:
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	%rbx, %rdx
	movl	$1, %ecx
	movq	%rbp, %rdi
	movl	$1, %esi
	movq	%rbx, 36(%rsp)
	movl	$1, 44(%rsp)
	movq	%rbp, 24(%rsp)
	movl	$1, 32(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L72
	movq	R(%rip), %rcx
	movq	W(%rip), %rsi
	leal	1(%r12), %r8d
	movq	%r15, %rdx
	movq	N(%rip), %rdi
	call	_Z34__device_stub__Z8train_WNPfS_S_S_iPfS_S_S_i
.L72:
	call	cudaDeviceSynchronize@PLT
	movl	$10, 12(%rsp)
	movl	$1000, %r13d
	movl	$1, 8(%rsp)
.L74:
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	%rbx, %rdx
	movl	$1, %ecx
	movq	%rbp, %rdi
	movl	$1, %esi
	movq	%rbx, 36(%rsp)
	movl	$1, 44(%rsp)
	movq	%rbp, 24(%rsp)
	movl	$1, 32(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L73
	movl	8(%rsp), %edx
	movq	R(%rip), %rdi
	movl	%r13d, %esi
	call	_Z32__device_stub__Z10predict_RiPfiiPfii
.L73:
	call	cudaDeviceSynchronize@PLT
	incl	%r13d
	sall	8(%rsp)
	sarl	%r13d
	decl	12(%rsp)
	jne	.L74
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	%rbx, %rdx
	movl	$1, %ecx
	movq	%rbp, %rdi
	movl	$1, %esi
	movq	%rbx, 36(%rsp)
	movl	$1, 44(%rsp)
	movq	%rbp, 24(%rsp)
	movl	$1, 32(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L75
	movq	R(%rip), %rdi
	movq	%r14, %rsi
	call	_Z28__device_stub__Z7train_BPfS_PfS_
.L75:
	call	cudaDeviceSynchronize@PLT
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	%rbx, %rdx
	movl	$1, %ecx
	movq	%rbp, %rdi
	movl	$1, %esi
	movq	%rbx, 36(%rsp)
	movl	$1, 44(%rsp)
	movq	%rbp, 24(%rsp)
	movl	$1, 32(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L76
	movq	W(%rip), %rsi
	movq	N(%rip), %rdi
	movl	%r12d, %ecx
	movq	%r14, %rdx
	call	_Z32__device_stub__Z8train_WhPfS_S_iPfS_S_i
.L76:
	call	cudaDeviceSynchronize@PLT
	decl	%r12d
	movq	%r14, %rax
	movq	%r15, %r14
	cmpl	$-1, %r12d
	je	.L81
	movq	%rax, %r15
	jmp	.L77
.L81:
	addq	$56, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2027:
	.size	_Z5trainv, .-_Z5trainv
	.globl	_Z32__device_stub__Z9normalizePfS_S_PfS_S_
	.type	_Z32__device_stub__Z9normalizePfS_S_PfS_S_, @function
_Z32__device_stub__Z9normalizePfS_S_PfS_S_:
.LFB2077:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L82
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z9normalizePfS_S_(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L82:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L84
	call	__stack_chk_fail@PLT
.L84:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2077:
	.size	_Z32__device_stub__Z9normalizePfS_S_PfS_S_, .-_Z32__device_stub__Z9normalizePfS_S_PfS_S_
	.globl	_Z9normalizePfS_S_
	.type	_Z9normalizePfS_S_, @function
_Z9normalizePfS_S_:
.LFB2078:
	.cfi_startproc
	endbr64
	jmp	_Z32__device_stub__Z9normalizePfS_S_PfS_S_
	.cfi_endproc
.LFE2078:
	.size	_Z9normalizePfS_S_, .-_Z9normalizePfS_S_
	.globl	_Z10initializev
	.type	_Z10initializev, @function
_Z10initializev:
.LFB2028:
	.cfi_startproc
	endbr64
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movl	$16000000, %esi
	leaq	W(%rip), %rdi
	call	cudaMalloc@PLT
	movl	$4000000, %esi
	leaq	R(%rip), %rdi
	call	cudaMalloc@PLT
	movl	$20000, %esi
	leaq	N(%rip), %rdi
	call	cudaMalloc@PLT
	movl	$4000, %esi
	leaq	Y(%rip), %rdi
	call	cudaMalloc@PLT
	movl	$4000, %esi
	leaq	pY(%rip), %rdi
	call	cudaMalloc@PLT
	movl	$4000, %esi
	leaq	U(%rip), %rdi
	call	cudaMalloc@PLT
	movl	$4000, %esi
	leaq	V(%rip), %rdi
	call	cudaMalloc@PLT
	movl	$134217729, %edx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$33554433, %edi
	salq	$5, %rdx
	movl	$1, %ecx
	movl	$1, %esi
	salq	$7, %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L88
	movq	Y(%rip), %rdx
	movq	N(%rip), %rsi
	movq	W(%rip), %rdi
	call	_Z32__device_stub__Z9normalizePfS_S_PfS_S_
.L88:
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	cudaDeviceSynchronize@PLT
	.cfi_endproc
.LFE2028:
	.size	_Z10initializev, .-_Z10initializev
	.section	.rodata.str1.1
.LC3:
	.string	"/home/ubuntu/Datasets/stackv2/train-structured/ShamsArfeen/Deep-Learning-with-CUDA/main/deep.cu"
.LC4:
	.string	"Error at %s:%d\n"
.LC5:
	.string	"TIME: %f\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2032:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	call	_Z10initializev
	xorl	%eax, %eax
.L91:
	movl	%eax, count(%rip)
	cmpl	$3, %eax
	jg	.L99
	call	clock@PLT
	movq	%rax, %rbx
	call	_Z7predictv
	call	_Z5trainv
	call	clock@PLT
	movl	$2, %ecx
	movq	Y(%rip), %rsi
	movl	$4000, %edx
	subq	%rbx, %rax
	leaq	Yh(%rip), %rdi
	cvtsi2ssq	%rax, %xmm0
	divss	.LC2(%rip), %xmm0
	movd	%xmm0, %ebx
	call	cudaMemcpy@PLT
	testl	%eax, %eax
	je	.L92
	movl	$318, %ecx
	jmp	.L98
.L92:
	movq	pY(%rip), %rsi
	movl	$2, %ecx
	movl	$4000, %edx
	leaq	Dh(%rip), %rdi
	call	cudaMemcpy@PLT
	testl	%eax, %eax
	je	.L94
	movl	$319, %ecx
.L98:
	leaq	.LC3(%rip), %rdx
	leaq	.LC4(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movl	$1, %eax
	jmp	.L90
.L94:
	call	_Z14calculateErrorv
	movd	%ebx, %xmm1
	movl	$2, %edi
	movb	$1, %al
	leaq	.LC5(%rip), %rsi
	cvtss2sd	%xmm1, %xmm0
	call	__printf_chk@PLT
	movl	count(%rip), %eax
	incl	%eax
	jmp	.L91
.L99:
	call	_Z13freeResourcesv
	xorl	%eax, %eax
.L90:
	popq	%rbx
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2032:
	.size	main, .-main
	.section	.rodata.str1.1
.LC6:
	.string	"_Z9normalizePfS_S_"
.LC7:
	.string	"_Z8train_WhPfS_S_i"
.LC8:
	.string	"_Z7train_BPfS_"
.LC9:
	.string	"_Z8train_WNPfS_S_S_i"
.LC10:
	.string	"_Z8train_WfPfS_S_"
.LC11:
	.string	"_Z7train_VPfS_S_"
.LC12:
	.string	"_Z10predict_YpPfS_"
.LC13:
	.string	"_Z10predict_NkPfS_i"
.LC14:
	.string	"_Z10predict_RiPfii"
.LC15:
	.string	"_Z10predict_WNPfS_S_i"
.LC16:
	.string	"_Z9predict_NPf"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2080:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC6(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z9normalizePfS_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC7(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z8train_WhPfS_S_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC8(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z7train_BPfS_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC9(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z8train_WNPfS_S_S_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC10(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z8train_WfPfS_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC11(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z7train_VPfS_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC12(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z10predict_YpPfS_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC13(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z10predict_NkPfS_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	leaq	.LC14(%rip), %rdx
	pushq	$0
	.cfi_def_cfa_offset 24
	movq	%rdx, %rcx
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	_Z10predict_RiPfii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC15(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z10predict_WNPfS_S_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC16(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z9predict_NPf(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2080:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.globl	count
	.bss
	.align 4
	.type	count, @object
	.size	count, 4
count:
	.zero	4
	.globl	Dh
	.align 32
	.type	Dh, @object
	.size	Dh, 4000
Dh:
	.zero	4000
	.globl	Yh
	.align 32
	.type	Yh, @object
	.size	Yh, 4000
Yh:
	.zero	4000
	.globl	V
	.align 8
	.type	V, @object
	.size	V, 8
V:
	.zero	8
	.globl	U
	.align 8
	.type	U, @object
	.size	U, 8
U:
	.zero	8
	.globl	pY
	.align 8
	.type	pY, @object
	.size	pY, 8
pY:
	.zero	8
	.globl	Y
	.align 8
	.type	Y, @object
	.size	Y, 8
Y:
	.zero	8
	.globl	N
	.align 8
	.type	N, @object
	.size	N, 8
N:
	.zero	8
	.globl	R
	.align 8
	.type	R, @object
	.size	R, 8
R:
	.zero	8
	.globl	W
	.align 8
	.type	W, @object
	.size	W, 8
W:
	.zero	8
	.section	.rodata.cst4,"aM",@progbits,4
	.align 4
.LC2:
	.long	1232348160
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <stdio.h>
#include <math.h>
#include <stdlib.h>
#include <time.h>

#include <hip/hip_runtime.h>
#include <hiprand/hiprand.h>

#define CUDA_CALL(x) do { if((x)!=hipSuccess) { \
    printf("Error at %s:%d\n",__FILE__,__LINE__);\
    return EXIT_FAILURE;}} while(0)
    
#define DEPTH 5 // no of layers
#define BREADTH 1000 // nodes per layer
#define RATE 0.0001 // learning rate

#define NDIM(a,b) ((a)*BREADTH+(b)) 
#define WDIM(a,b,c) ((a)*BREADTH*BREADTH+(b)*BREADTH+(c))

float *W, *R; // [DEPTH-1][BREADTH][BREADTH] W_kij : weight of edge b/w jth and ith node from kth layer and k+1th layer resp. 
float *N; // [DEPTH][BREADTH] N_ki : jth node in kth layer
float *Y, *pY; // [BREADTH] expected and predicted output vectors
float *U, *V; // [BREADTH] vectors for backpropagation chain-rule

float Yh[BREADTH], Dh[BREADTH]; // host arrays: expected and predicted output
int count = 0;

#define f(x) (tanhf((x))) // activation function
#define df(y) (1 - (y) * (y)) // derivative of activation function in y terms


__global__ void predict_N( float *N) { // feedforward pass algorithm
    int tid = blockIdx.x * blockDim.x + threadIdx.x;
    int stride = gridDim.x * blockDim.x;
    int i;
     // erase all nodes except first layer
    for ( i = tid + BREADTH ; i < BREADTH * DEPTH ; i += stride )
        N[i] = 0;
}


__global__ void predict_WN( float *N, float *W, float *R, int k) { // feedforward pass algorithm
    int tid = blockIdx.x * blockDim.x + threadIdx.x;
    int stride = gridDim.x * blockDim.x;
    int h;

    // matrix-vector multiplication W*N b/w k-1th and kth layer
    int wIndex = k * BREADTH * BREADTH; 
    int nIndex = k * BREADTH; 
    for ( h = tid ; h < BREADTH * BREADTH ; h += stride ) {
        int j = h % BREADTH;
        R[h] = W[wIndex + h] * N[nIndex + j];
    }
}

__global__ void predict_Ri( float *R, int n, int j) { // feedforward pass algorithm
    int tid = blockIdx.x * blockDim.x + threadIdx.x;
    int stride = gridDim.x * blockDim.x;

    int i;
    for ( i = tid % BREADTH ; i < BREADTH ; i += stride ) {

        int itid = tid / BREADTH;
        int istride = stride / BREADTH;
        istride += (istride == 0);

        int rIndex = i * BREADTH;
        
        for ( int h = 2 * j * itid; h < j * (n - 1); h += 2 * j * istride)
            R[rIndex + h] += R[rIndex + h + j];
    }
}

__global__ void predict_Nk( float *N, float *R, int k) { // feedforward pass algorithm
    int tid = blockIdx.x * blockDim.x + threadIdx.x;
    int stride = gridDim.x * blockDim.x;

    int i;    
    for ( i = tid; i < BREADTH; i += stride )
        N[NDIM(k,i)] = f( R[NDIM(i,0)]);
}

__global__ void predict_Yp( float *N, float *pY) { // feedforward pass algorithm
    int tid = blockIdx.x * blockDim.x + threadIdx.x;
    int stride = gridDim.x * blockDim.x;

    int i;    
    for ( i = tid; i < BREADTH; i += stride )
        pY[i] = N[NDIM(DEPTH-1,i)];
}


__global__ void train_V( float *N, float *Y, float *V) {    

    int tid = blockIdx.x * blockDim.x + threadIdx.x;
    int stride = gridDim.x * blockDim.x;
    
    int q = DEPTH - 2;

    // caching chain-rule calculation in vector to aid in backpropagation
    for ( int i = tid; i < BREADTH; i += stride ) {
        V[i] = (N[NDIM(q+1,i)] - Y[i]) * df( N[NDIM(q+1,i)]);
    }
}

__global__ void train_Wf( float *N, float *W, float *V) {    

    int tid = blockIdx.x * blockDim.x + threadIdx.x;
    int stride = gridDim.x * blockDim.x;
    
    int q = DEPTH - 2, h;

    // update weights of outer layer
    for ( h = tid; h < BREADTH * BREADTH; h += stride ) {
        int i = h / BREADTH;
        int j = h % BREADTH;
        W[WDIM(q,i,j)] -= (float)RATE * V[i] * N[NDIM(q,j)];
    }
}

__global__ void train_WN( float *N, float *W, float *A, float *R, int k) { // feedforward pass algorithm
    int tid = blockIdx.x * blockDim.x + threadIdx.x;
    int stride = gridDim.x * blockDim.x;
    int h;

    // matrix-vector multiplication W*N b/w k-1th and kth layer
    int wIndex = k * BREADTH * BREADTH; 
    int nIndex = k * BREADTH; 
    for ( h = tid ; h < BREADTH * BREADTH ; h += stride ) {
        int j = h % BREADTH;
        int i = h / BREADTH;
        R[NDIM(j,i)] = A[i] * W[wIndex + h] * df( N[nIndex + j]);
    }
}

__global__ void train_B( float *R, float *B) { // feedforward pass algorithm
    int tid = blockIdx.x * blockDim.x + threadIdx.x;
    int stride = gridDim.x * blockDim.x;

    int i;    
    for ( i = tid; i < BREADTH; i += stride )
        B[i] = R[NDIM(i,0)];
}

__global__ void train_Wh( float *N, float *W, float *A, int k) { // feedforward pass algorithm
    int tid = blockIdx.x * blockDim.x + threadIdx.x;
    int stride = gridDim.x * blockDim.x;
    int h;

    // matrix-vector multiplication W*N b/w k-1th and kth layer
    int wIndex = k * BREADTH * BREADTH; 
    int nIndex = k * BREADTH; 
    for ( h = tid ; h < BREADTH * BREADTH ; h += stride ) {
        int j = h % BREADTH;
        int i = h / BREADTH;
        W[wIndex + h] -= (float)RATE * A[i] * N[nIndex + j];
    }
}


void train() {

    train_V<<<128, 32>>>( N, Y, V);
    hipDeviceSynchronize();

    train_Wf<<<128, 32>>>( N, W, V);
    hipDeviceSynchronize();
    
    int q = DEPTH - 2;

    float *A = &V[0], *B = &U[0];
    float *temp;

    // updating weights of hidden layers (backpropagation)
    for ( int k = q - 1; k >= 0; k-- ) {      

        // chain-rule expansion by multiplying with next layer's weight matrix and 
        // derivative of activation function on the same layer's nodes
        train_WN<<<128, 32>>>( N, W, A, R, k+1);
        hipDeviceSynchronize();

        int j = 1;
        int n = BREADTH;
        while ( n > 1) {
            predict_Ri<<<128, 32>>>( R, n, j);
            hipDeviceSynchronize();

            j *= 2;
            n = (n+1)/2;
        }

        train_B<<<128, 32>>>( R, B);
        hipDeviceSynchronize();

        temp = B;        B = A;        A = temp;

        // adjust weights by gradient descent
        train_Wh<<<128, 32>>>( N, W, A, k);
        hipDeviceSynchronize();
    }
}


__global__ void normalize( float *W, float *N, float *Y) {    

    int tid = blockIdx.x * blockDim.x + threadIdx.x;
    int stride = gridDim.x * blockDim.x;
    int i, w = (DEPTH-1) * BREADTH * BREADTH;

    for ( i = tid; i < w; i+= stride)
        W[i] = 1/ (float)BREADTH;

    for ( i = tid; i < BREADTH; i+= stride)
        N[i] = i/ (float)BREADTH;

    for ( i = tid; i < BREADTH; i+= stride)
        Y[i] = i/ (float)BREADTH;
}

void initialize() {
    int w = (DEPTH-1) * BREADTH * BREADTH;

    // device memory allocation of global arrays
    hipMalloc( (void**)(&W), sizeof(float) * w);
    hipMalloc( (void**)(&R), sizeof(float) * BREADTH * BREADTH);
    hipMalloc( (void**)(&N), sizeof(float) * DEPTH * BREADTH);
    hipMalloc( (void**)(&Y), sizeof(float) * BREADTH);
    hipMalloc( (void**)(&pY), sizeof(float) * BREADTH);
    hipMalloc( (void**)(&U), sizeof(float) * BREADTH);
    hipMalloc( (void**)(&V), sizeof(float) * BREADTH);

    /*
    // random number generator
    curandGenerator_t gen;

    // Create pseudo-random number generator 
    curandCreateGenerator(&gen, CURAND_RNG_PSEUDO_DEFAULT);

    // Set seed 
    curandSetPseudoRandomGeneratorSeed(gen, time(0));

    // Generate floats on device
    curandGenerateUniform(gen, W, w);
    curandGenerateUniform(gen, N, BREADTH * DEPTH);
    curandGenerateUniform(gen, Y, BREADTH);

    curandDestroyGenerator(gen);
    */
    
    normalize<<<128, 32>>>(W, N, Y);
    hipDeviceSynchronize();
}

void calculateError() {
    float err = 0, dY;

    // dY : difference b/w expected and predicted output, and
    // err : sum of squares of dY

    for ( int i = 0 ; i < BREADTH ; i++ ) {
        dY = (Dh[i] - Yh[i]);
        err += dY * dY;
    }
    printf("ITERATION : %d\tLOSS : %f\t", count, err);
}

void freeResources() {
    hipFree(Y);
    hipFree(N);
    hipFree(W);
    hipFree(pY);
    hipFree(U);
    hipFree(V);
    hipFree(R);
}

void predict() {

    predict_N<<<128, 32>>>(N);
    hipDeviceSynchronize();
    
    for ( int k = 1; k < DEPTH ; k++ ) {
        predict_WN<<<128, 32>>>( N, W, R, k-1);
        hipDeviceSynchronize();

        int j = 1;
        int n = BREADTH;
        while ( n > 1) {
            predict_Ri<<<128, 32>>>( R, n, j);
            hipDeviceSynchronize();

            j *= 2;
            n = (n+1)/2;
        }

        predict_Nk<<<128, 32>>>( N, R, k);
        hipDeviceSynchronize();
    }
    predict_Yp<<<128, 32>>>( N, pY);
    hipDeviceSynchronize();
}

int main() {

    initialize();

    for ( count = 0; count < 4; count++) {

        clock_t begin, end;
        begin = clock();

        predict();
        train();

        end = clock();
        float CpuTime = (float)(end - begin) / CLOCKS_PER_SEC;

        CUDA_CALL(hipMemcpy(Yh, Y, BREADTH * sizeof(float), hipMemcpyDeviceToHost));
        CUDA_CALL(hipMemcpy(Dh, pY, BREADTH * sizeof(float), hipMemcpyDeviceToHost));

        calculateError();
        printf("TIME: %f\n", CpuTime);
    }

    freeResources();

    return 0;
}

	.text
	.file	"deep.hip"
	.globl	_Z24__device_stub__predict_NPf  # -- Begin function _Z24__device_stub__predict_NPf
	.type	_Z24__device_stub__predict_NPf,@function
_Z24__device_stub__predict_NPf:         # @_Z24__device_stub__predict_NPf
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$64, %rsp
	.cfi_def_cfa_offset 112
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	movq	%rsp, %rbx
	movq	%rax, (%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z9predict_NPf, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$80, %rsp
	.cfi_adjust_cfa_offset -80
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z24__device_stub__predict_NPf, .Lfunc_end0-_Z24__device_stub__predict_NPf
	.cfi_endproc
                                        # -- End function
	.globl	_Z25__device_stub__predict_WNPfS_S_i # -- Begin function _Z25__device_stub__predict_WNPfS_S_i
	.type	_Z25__device_stub__predict_WNPfS_S_i,@function
_Z25__device_stub__predict_WNPfS_S_i:   # @_Z25__device_stub__predict_WNPfS_S_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	4(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z10predict_WNPfS_S_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z25__device_stub__predict_WNPfS_S_i, .Lfunc_end1-_Z25__device_stub__predict_WNPfS_S_i
	.cfi_endproc
                                        # -- End function
	.globl	_Z25__device_stub__predict_RiPfii # -- Begin function _Z25__device_stub__predict_RiPfii
	.type	_Z25__device_stub__predict_RiPfii,@function
_Z25__device_stub__predict_RiPfii:      # @_Z25__device_stub__predict_RiPfii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$96, %rsp
	.cfi_def_cfa_offset 144
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	4(%rsp), %rcx
	movl	%esi, (%rcx)
	movq	%rsp, %rsi
	movl	%edx, (%rsi)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z10predict_RiPfii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$112, %rsp
	.cfi_adjust_cfa_offset -112
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z25__device_stub__predict_RiPfii, .Lfunc_end2-_Z25__device_stub__predict_RiPfii
	.cfi_endproc
                                        # -- End function
	.globl	_Z25__device_stub__predict_NkPfS_i # -- Begin function _Z25__device_stub__predict_NkPfS_i
	.type	_Z25__device_stub__predict_NkPfS_i,@function
_Z25__device_stub__predict_NkPfS_i:     # @_Z25__device_stub__predict_NkPfS_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z10predict_NkPfS_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	_Z25__device_stub__predict_NkPfS_i, .Lfunc_end3-_Z25__device_stub__predict_NkPfS_i
	.cfi_endproc
                                        # -- End function
	.globl	_Z25__device_stub__predict_YpPfS_ # -- Begin function _Z25__device_stub__predict_YpPfS_
	.type	_Z25__device_stub__predict_YpPfS_,@function
_Z25__device_stub__predict_YpPfS_:      # @_Z25__device_stub__predict_YpPfS_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	16(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z10predict_YpPfS_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end4:
	.size	_Z25__device_stub__predict_YpPfS_, .Lfunc_end4-_Z25__device_stub__predict_YpPfS_
	.cfi_endproc
                                        # -- End function
	.globl	_Z22__device_stub__train_VPfS_S_ # -- Begin function _Z22__device_stub__train_VPfS_S_
	.type	_Z22__device_stub__train_VPfS_S_,@function
_Z22__device_stub__train_VPfS_S_:       # @_Z22__device_stub__train_VPfS_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7train_VPfS_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end5:
	.size	_Z22__device_stub__train_VPfS_S_, .Lfunc_end5-_Z22__device_stub__train_VPfS_S_
	.cfi_endproc
                                        # -- End function
	.globl	_Z23__device_stub__train_WfPfS_S_ # -- Begin function _Z23__device_stub__train_WfPfS_S_
	.type	_Z23__device_stub__train_WfPfS_S_,@function
_Z23__device_stub__train_WfPfS_S_:      # @_Z23__device_stub__train_WfPfS_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z8train_WfPfS_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end6:
	.size	_Z23__device_stub__train_WfPfS_S_, .Lfunc_end6-_Z23__device_stub__train_WfPfS_S_
	.cfi_endproc
                                        # -- End function
	.globl	_Z23__device_stub__train_WNPfS_S_S_i # -- Begin function _Z23__device_stub__train_WNPfS_S_S_i
	.type	_Z23__device_stub__train_WNPfS_S_S_i,@function
_Z23__device_stub__train_WNPfS_S_S_i:   # @_Z23__device_stub__train_WNPfS_S_S_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	12(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z8train_WNPfS_S_S_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end7:
	.size	_Z23__device_stub__train_WNPfS_S_S_i, .Lfunc_end7-_Z23__device_stub__train_WNPfS_S_S_i
	.cfi_endproc
                                        # -- End function
	.globl	_Z22__device_stub__train_BPfS_  # -- Begin function _Z22__device_stub__train_BPfS_
	.type	_Z22__device_stub__train_BPfS_,@function
_Z22__device_stub__train_BPfS_:         # @_Z22__device_stub__train_BPfS_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	16(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7train_BPfS_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end8:
	.size	_Z22__device_stub__train_BPfS_, .Lfunc_end8-_Z22__device_stub__train_BPfS_
	.cfi_endproc
                                        # -- End function
	.globl	_Z23__device_stub__train_WhPfS_S_i # -- Begin function _Z23__device_stub__train_WhPfS_S_i
	.type	_Z23__device_stub__train_WhPfS_S_i,@function
_Z23__device_stub__train_WhPfS_S_i:     # @_Z23__device_stub__train_WhPfS_S_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	4(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z8train_WhPfS_S_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end9:
	.size	_Z23__device_stub__train_WhPfS_S_i, .Lfunc_end9-_Z23__device_stub__train_WhPfS_S_i
	.cfi_endproc
                                        # -- End function
	.globl	_Z5trainv                       # -- Begin function _Z5trainv
	.type	_Z5trainv,@function
_Z5trainv:                              # @_Z5trainv
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	pushq	%rax
	.cfi_def_cfa_offset 64
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movabsq	$4294967328, %rbx               # imm = 0x100000020
	leaq	96(%rbx), %r14
	movq	%r14, %rdi
	movl	$1, %esi
	movq	%rbx, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB10_2
# %bb.1:
	movq	N(%rip), %rdi
	movq	Y(%rip), %rsi
	movq	V(%rip), %rdx
	callq	_Z22__device_stub__train_VPfS_S_
.LBB10_2:
	callq	hipDeviceSynchronize
	movq	%r14, %rdi
	movl	$1, %esi
	movq	%rbx, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB10_4
# %bb.3:
	movq	N(%rip), %rdi
	movq	W(%rip), %rsi
	movq	V(%rip), %rdx
	callq	_Z23__device_stub__train_WfPfS_S_
.LBB10_4:
	callq	hipDeviceSynchronize
	movq	V(%rip), %rax
	movl	$2, %r15d
	movq	U(%rip), %r12
.LBB10_5:                               # =>This Loop Header: Depth=1
                                        #     Child Loop BB10_8 Depth 2
	movq	%rax, %r13
	movq	%r14, %rdi
	movl	$1, %esi
	movq	%rbx, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB10_7
# %bb.6:                                #   in Loop: Header=BB10_5 Depth=1
	movq	N(%rip), %rdi
	movq	W(%rip), %rsi
	movq	R(%rip), %rcx
	leal	1(%r15), %r8d
	movq	%r13, %rdx
	callq	_Z23__device_stub__train_WNPfS_S_S_i
.LBB10_7:                               #   in Loop: Header=BB10_5 Depth=1
	movq	%r13, (%rsp)                    # 8-byte Spill
	callq	hipDeviceSynchronize
	movl	$1000, %r13d                    # imm = 0x3E8
	movl	$1, %ebp
.LBB10_8:                               #   Parent Loop BB10_5 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movq	%r14, %rdi
	movl	$1, %esi
	movq	%rbx, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB10_10
# %bb.9:                                #   in Loop: Header=BB10_8 Depth=2
	movq	R(%rip), %rdi
	movl	%r13d, %esi
	movl	%ebp, %edx
	callq	_Z25__device_stub__predict_RiPfii
.LBB10_10:                              #   in Loop: Header=BB10_8 Depth=2
	callq	hipDeviceSynchronize
	addl	%ebp, %ebp
	leal	1(%r13), %eax
	shrl	%eax
	cmpl	$2, %r13d
	movl	%eax, %r13d
	ja	.LBB10_8
# %bb.11:                               #   in Loop: Header=BB10_5 Depth=1
	movq	%r14, %rdi
	movl	$1, %esi
	movq	%rbx, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB10_13
# %bb.12:                               #   in Loop: Header=BB10_5 Depth=1
	movq	R(%rip), %rdi
	movq	%r12, %rsi
	callq	_Z22__device_stub__train_BPfS_
.LBB10_13:                              #   in Loop: Header=BB10_5 Depth=1
	callq	hipDeviceSynchronize
	movq	%r14, %rdi
	movl	$1, %esi
	movq	%rbx, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	movq	(%rsp), %r13                    # 8-byte Reload
	jne	.LBB10_15
# %bb.14:                               #   in Loop: Header=BB10_5 Depth=1
	movq	N(%rip), %rdi
	movq	W(%rip), %rsi
	movq	%r12, %rdx
	movl	%r15d, %ecx
	callq	_Z23__device_stub__train_WhPfS_S_i
.LBB10_15:                              #   in Loop: Header=BB10_5 Depth=1
	callq	hipDeviceSynchronize
	movq	%r12, %rax
	movq	%r13, %r12
	subl	$1, %r15d
	jae	.LBB10_5
# %bb.16:
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end10:
	.size	_Z5trainv, .Lfunc_end10-_Z5trainv
	.cfi_endproc
                                        # -- End function
	.globl	_Z24__device_stub__normalizePfS_S_ # -- Begin function _Z24__device_stub__normalizePfS_S_
	.type	_Z24__device_stub__normalizePfS_S_,@function
_Z24__device_stub__normalizePfS_S_:     # @_Z24__device_stub__normalizePfS_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z9normalizePfS_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end11:
	.size	_Z24__device_stub__normalizePfS_S_, .Lfunc_end11-_Z24__device_stub__normalizePfS_S_
	.cfi_endproc
                                        # -- End function
	.globl	_Z10initializev                 # -- Begin function _Z10initializev
	.type	_Z10initializev,@function
_Z10initializev:                        # @_Z10initializev
	.cfi_startproc
# %bb.0:
	pushq	%rax
	.cfi_def_cfa_offset 16
	movl	$W, %edi
	movl	$16000000, %esi                 # imm = 0xF42400
	callq	hipMalloc
	movl	$R, %edi
	movl	$4000000, %esi                  # imm = 0x3D0900
	callq	hipMalloc
	movl	$N, %edi
	movl	$20000, %esi                    # imm = 0x4E20
	callq	hipMalloc
	movl	$Y, %edi
	movl	$4000, %esi                     # imm = 0xFA0
	callq	hipMalloc
	movl	$pY, %edi
	movl	$4000, %esi                     # imm = 0xFA0
	callq	hipMalloc
	movl	$U, %edi
	movl	$4000, %esi                     # imm = 0xFA0
	callq	hipMalloc
	movl	$V, %edi
	movl	$4000, %esi                     # imm = 0xFA0
	callq	hipMalloc
	movabsq	$4294967328, %rdx               # imm = 0x100000020
	leaq	96(%rdx), %rdi
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB12_2
# %bb.1:
	movq	W(%rip), %rdi
	movq	N(%rip), %rsi
	movq	Y(%rip), %rdx
	callq	_Z24__device_stub__normalizePfS_S_
.LBB12_2:
	popq	%rax
	.cfi_def_cfa_offset 8
	jmp	hipDeviceSynchronize            # TAILCALL
.Lfunc_end12:
	.size	_Z10initializev, .Lfunc_end12-_Z10initializev
	.cfi_endproc
                                        # -- End function
	.globl	_Z14calculateErrorv             # -- Begin function _Z14calculateErrorv
	.type	_Z14calculateErrorv,@function
_Z14calculateErrorv:                    # @_Z14calculateErrorv
	.cfi_startproc
# %bb.0:
	xorps	%xmm0, %xmm0
	movq	$-4000, %rax                    # imm = 0xF060
.LBB13_1:                               # =>This Inner Loop Header: Depth=1
	movss	Dh+4000(%rax), %xmm1            # xmm1 = mem[0],zero,zero,zero
	subss	Yh+4000(%rax), %xmm1
	mulss	%xmm1, %xmm1
	addss	%xmm1, %xmm0
	addq	$4, %rax
	jne	.LBB13_1
# %bb.2:
	movl	count(%rip), %esi
	cvtss2sd	%xmm0, %xmm0
	movl	$.L.str, %edi
	movb	$1, %al
	jmp	printf                          # TAILCALL
.Lfunc_end13:
	.size	_Z14calculateErrorv, .Lfunc_end13-_Z14calculateErrorv
	.cfi_endproc
                                        # -- End function
	.globl	_Z13freeResourcesv              # -- Begin function _Z13freeResourcesv
	.type	_Z13freeResourcesv,@function
_Z13freeResourcesv:                     # @_Z13freeResourcesv
	.cfi_startproc
# %bb.0:
	pushq	%rax
	.cfi_def_cfa_offset 16
	movq	Y(%rip), %rdi
	callq	hipFree
	movq	N(%rip), %rdi
	callq	hipFree
	movq	W(%rip), %rdi
	callq	hipFree
	movq	pY(%rip), %rdi
	callq	hipFree
	movq	U(%rip), %rdi
	callq	hipFree
	movq	V(%rip), %rdi
	callq	hipFree
	movq	R(%rip), %rdi
	popq	%rax
	.cfi_def_cfa_offset 8
	jmp	hipFree                         # TAILCALL
.Lfunc_end14:
	.size	_Z13freeResourcesv, .Lfunc_end14-_Z13freeResourcesv
	.cfi_endproc
                                        # -- End function
	.globl	_Z7predictv                     # -- Begin function _Z7predictv
	.type	_Z7predictv,@function
_Z7predictv:                            # @_Z7predictv
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movabsq	$4294967328, %rbx               # imm = 0x100000020
	leaq	96(%rbx), %r14
	movl	$1, %r15d
	movq	%r14, %rdi
	movl	$1, %esi
	movq	%rbx, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB15_2
# %bb.1:
	movq	N(%rip), %rdi
	callq	_Z24__device_stub__predict_NPf
.LBB15_2:
	callq	hipDeviceSynchronize
.LBB15_3:                               # =>This Loop Header: Depth=1
                                        #     Child Loop BB15_6 Depth 2
	movq	%r14, %rdi
	movl	$1, %esi
	movq	%rbx, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB15_5
# %bb.4:                                #   in Loop: Header=BB15_3 Depth=1
	movq	N(%rip), %rdi
	movq	W(%rip), %rsi
	movq	R(%rip), %rdx
	leal	-1(%r15), %ecx
	callq	_Z25__device_stub__predict_WNPfS_S_i
.LBB15_5:                               #   in Loop: Header=BB15_3 Depth=1
	callq	hipDeviceSynchronize
	movl	$1000, %r12d                    # imm = 0x3E8
	movl	$1, %ebp
.LBB15_6:                               #   Parent Loop BB15_3 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movq	%r14, %rdi
	movl	$1, %esi
	movq	%rbx, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB15_8
# %bb.7:                                #   in Loop: Header=BB15_6 Depth=2
	movq	R(%rip), %rdi
	movl	%r12d, %esi
	movl	%ebp, %edx
	callq	_Z25__device_stub__predict_RiPfii
.LBB15_8:                               #   in Loop: Header=BB15_6 Depth=2
	callq	hipDeviceSynchronize
	addl	%ebp, %ebp
	leal	1(%r12), %eax
	shrl	%eax
	cmpl	$2, %r12d
	movl	%eax, %r12d
	ja	.LBB15_6
# %bb.9:                                #   in Loop: Header=BB15_3 Depth=1
	movq	%r14, %rdi
	movl	$1, %esi
	movq	%rbx, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB15_11
# %bb.10:                               #   in Loop: Header=BB15_3 Depth=1
	movq	N(%rip), %rdi
	movq	R(%rip), %rsi
	movl	%r15d, %edx
	callq	_Z25__device_stub__predict_NkPfS_i
.LBB15_11:                              #   in Loop: Header=BB15_3 Depth=1
	callq	hipDeviceSynchronize
	incl	%r15d
	cmpl	$5, %r15d
	jne	.LBB15_3
# %bb.12:
	movq	%r14, %rdi
	movl	$1, %esi
	movq	%rbx, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB15_14
# %bb.13:
	movq	N(%rip), %rdi
	movq	pY(%rip), %rsi
	callq	_Z25__device_stub__predict_YpPfS_
.LBB15_14:
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	hipDeviceSynchronize            # TAILCALL
.Lfunc_end15:
	.size	_Z7predictv, .Lfunc_end15-_Z7predictv
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0                          # -- Begin function main
.LCPI16_0:
	.long	0x49742400                      # float 1.0E+6
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$16, %rsp
	.cfi_def_cfa_offset 32
	.cfi_offset %rbx, -16
	callq	_Z10initializev
	movl	$0, count(%rip)
.LBB16_1:                               # =>This Inner Loop Header: Depth=1
	callq	clock
	movq	%rax, %rbx
	callq	_Z7predictv
	callq	_Z5trainv
	callq	clock
	subq	%rbx, %rax
	xorps	%xmm0, %xmm0
	cvtsi2ss	%rax, %xmm0
	divss	.LCPI16_0(%rip), %xmm0
	movss	%xmm0, 12(%rsp)                 # 4-byte Spill
	movq	Y(%rip), %rsi
	movl	$Yh, %edi
	movl	$4000, %edx                     # imm = 0xFA0
	movl	$2, %ecx
	callq	hipMemcpy
	testl	%eax, %eax
	jne	.LBB16_2
# %bb.4:                                #   in Loop: Header=BB16_1 Depth=1
	movq	pY(%rip), %rsi
	movl	$Dh, %edi
	movl	$4000, %edx                     # imm = 0xFA0
	movl	$2, %ecx
	callq	hipMemcpy
	testl	%eax, %eax
	jne	.LBB16_5
# %bb.6:                                #   in Loop: Header=BB16_1 Depth=1
	callq	_Z14calculateErrorv
	xorps	%xmm0, %xmm0
	cvtss2sd	12(%rsp), %xmm0                 # 4-byte Folded Reload
	movl	$.L.str.3, %edi
	movb	$1, %al
	callq	printf
	movl	count(%rip), %eax
	leal	1(%rax), %ecx
	movl	%ecx, count(%rip)
	cmpl	$3, %eax
	jl	.LBB16_1
# %bb.7:
	callq	_Z13freeResourcesv
	xorl	%eax, %eax
	jmp	.LBB16_8
.LBB16_2:
	movl	$.L.str.1, %edi
	movl	$.L.str.2, %esi
	movl	$318, %edx                      # imm = 0x13E
	jmp	.LBB16_3
.LBB16_5:
	movl	$.L.str.1, %edi
	movl	$.L.str.2, %esi
	movl	$319, %edx                      # imm = 0x13F
.LBB16_3:                               # %.thread
	xorl	%eax, %eax
	callq	printf
	movl	$1, %eax
.LBB16_8:                               # %.thread
	addq	$16, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end16:
	.size	main, .Lfunc_end16-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB17_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB17_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z9predict_NPf, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z10predict_WNPfS_S_i, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z10predict_RiPfii, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z10predict_NkPfS_i, %esi
	movl	$.L__unnamed_4, %edx
	movl	$.L__unnamed_4, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z10predict_YpPfS_, %esi
	movl	$.L__unnamed_5, %edx
	movl	$.L__unnamed_5, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z7train_VPfS_S_, %esi
	movl	$.L__unnamed_6, %edx
	movl	$.L__unnamed_6, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z8train_WfPfS_S_, %esi
	movl	$.L__unnamed_7, %edx
	movl	$.L__unnamed_7, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z8train_WNPfS_S_S_i, %esi
	movl	$.L__unnamed_8, %edx
	movl	$.L__unnamed_8, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z7train_BPfS_, %esi
	movl	$.L__unnamed_9, %edx
	movl	$.L__unnamed_9, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z8train_WhPfS_S_i, %esi
	movl	$.L__unnamed_10, %edx
	movl	$.L__unnamed_10, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z9normalizePfS_S_, %esi
	movl	$.L__unnamed_11, %edx
	movl	$.L__unnamed_11, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end17:
	.size	__hip_module_ctor, .Lfunc_end17-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB18_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB18_2:
	retq
.Lfunc_end18:
	.size	__hip_module_dtor, .Lfunc_end18-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	W,@object                       # @W
	.bss
	.globl	W
	.p2align	3, 0x0
W:
	.quad	0
	.size	W, 8

	.type	R,@object                       # @R
	.globl	R
	.p2align	3, 0x0
R:
	.quad	0
	.size	R, 8

	.type	N,@object                       # @N
	.globl	N
	.p2align	3, 0x0
N:
	.quad	0
	.size	N, 8

	.type	Y,@object                       # @Y
	.globl	Y
	.p2align	3, 0x0
Y:
	.quad	0
	.size	Y, 8

	.type	pY,@object                      # @pY
	.globl	pY
	.p2align	3, 0x0
pY:
	.quad	0
	.size	pY, 8

	.type	U,@object                       # @U
	.globl	U
	.p2align	3, 0x0
U:
	.quad	0
	.size	U, 8

	.type	V,@object                       # @V
	.globl	V
	.p2align	3, 0x0
V:
	.quad	0
	.size	V, 8

	.type	Yh,@object                      # @Yh
	.globl	Yh
	.p2align	4, 0x0
Yh:
	.zero	4000
	.size	Yh, 4000

	.type	Dh,@object                      # @Dh
	.globl	Dh
	.p2align	4, 0x0
Dh:
	.zero	4000
	.size	Dh, 4000

	.type	count,@object                   # @count
	.globl	count
	.p2align	2, 0x0
count:
	.long	0                               # 0x0
	.size	count, 4

	.type	_Z9predict_NPf,@object          # @_Z9predict_NPf
	.section	.rodata,"a",@progbits
	.globl	_Z9predict_NPf
	.p2align	3, 0x0
_Z9predict_NPf:
	.quad	_Z24__device_stub__predict_NPf
	.size	_Z9predict_NPf, 8

	.type	_Z10predict_WNPfS_S_i,@object   # @_Z10predict_WNPfS_S_i
	.globl	_Z10predict_WNPfS_S_i
	.p2align	3, 0x0
_Z10predict_WNPfS_S_i:
	.quad	_Z25__device_stub__predict_WNPfS_S_i
	.size	_Z10predict_WNPfS_S_i, 8

	.type	_Z10predict_RiPfii,@object      # @_Z10predict_RiPfii
	.globl	_Z10predict_RiPfii
	.p2align	3, 0x0
_Z10predict_RiPfii:
	.quad	_Z25__device_stub__predict_RiPfii
	.size	_Z10predict_RiPfii, 8

	.type	_Z10predict_NkPfS_i,@object     # @_Z10predict_NkPfS_i
	.globl	_Z10predict_NkPfS_i
	.p2align	3, 0x0
_Z10predict_NkPfS_i:
	.quad	_Z25__device_stub__predict_NkPfS_i
	.size	_Z10predict_NkPfS_i, 8

	.type	_Z10predict_YpPfS_,@object      # @_Z10predict_YpPfS_
	.globl	_Z10predict_YpPfS_
	.p2align	3, 0x0
_Z10predict_YpPfS_:
	.quad	_Z25__device_stub__predict_YpPfS_
	.size	_Z10predict_YpPfS_, 8

	.type	_Z7train_VPfS_S_,@object        # @_Z7train_VPfS_S_
	.globl	_Z7train_VPfS_S_
	.p2align	3, 0x0
_Z7train_VPfS_S_:
	.quad	_Z22__device_stub__train_VPfS_S_
	.size	_Z7train_VPfS_S_, 8

	.type	_Z8train_WfPfS_S_,@object       # @_Z8train_WfPfS_S_
	.globl	_Z8train_WfPfS_S_
	.p2align	3, 0x0
_Z8train_WfPfS_S_:
	.quad	_Z23__device_stub__train_WfPfS_S_
	.size	_Z8train_WfPfS_S_, 8

	.type	_Z8train_WNPfS_S_S_i,@object    # @_Z8train_WNPfS_S_S_i
	.globl	_Z8train_WNPfS_S_S_i
	.p2align	3, 0x0
_Z8train_WNPfS_S_S_i:
	.quad	_Z23__device_stub__train_WNPfS_S_S_i
	.size	_Z8train_WNPfS_S_S_i, 8

	.type	_Z7train_BPfS_,@object          # @_Z7train_BPfS_
	.globl	_Z7train_BPfS_
	.p2align	3, 0x0
_Z7train_BPfS_:
	.quad	_Z22__device_stub__train_BPfS_
	.size	_Z7train_BPfS_, 8

	.type	_Z8train_WhPfS_S_i,@object      # @_Z8train_WhPfS_S_i
	.globl	_Z8train_WhPfS_S_i
	.p2align	3, 0x0
_Z8train_WhPfS_S_i:
	.quad	_Z23__device_stub__train_WhPfS_S_i
	.size	_Z8train_WhPfS_S_i, 8

	.type	_Z9normalizePfS_S_,@object      # @_Z9normalizePfS_S_
	.globl	_Z9normalizePfS_S_
	.p2align	3, 0x0
_Z9normalizePfS_S_:
	.quad	_Z24__device_stub__normalizePfS_S_
	.size	_Z9normalizePfS_S_, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"ITERATION : %d\tLOSS : %f\t"
	.size	.L.str, 26

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"Error at %s:%d\n"
	.size	.L.str.1, 16

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"/home/ubuntu/Datasets/stackv2/train-structured-repos-hip-sm89/ShamsArfeen/Deep-Learning-with-CUDA/main/deep.hip"
	.size	.L.str.2, 112

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"TIME: %f\n"
	.size	.L.str.3, 10

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z9predict_NPf"
	.size	.L__unnamed_1, 15

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z10predict_WNPfS_S_i"
	.size	.L__unnamed_2, 22

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z10predict_RiPfii"
	.size	.L__unnamed_3, 19

	.type	.L__unnamed_4,@object           # @3
.L__unnamed_4:
	.asciz	"_Z10predict_NkPfS_i"
	.size	.L__unnamed_4, 20

	.type	.L__unnamed_5,@object           # @4
.L__unnamed_5:
	.asciz	"_Z10predict_YpPfS_"
	.size	.L__unnamed_5, 19

	.type	.L__unnamed_6,@object           # @5
.L__unnamed_6:
	.asciz	"_Z7train_VPfS_S_"
	.size	.L__unnamed_6, 17

	.type	.L__unnamed_7,@object           # @6
.L__unnamed_7:
	.asciz	"_Z8train_WfPfS_S_"
	.size	.L__unnamed_7, 18

	.type	.L__unnamed_8,@object           # @7
.L__unnamed_8:
	.asciz	"_Z8train_WNPfS_S_S_i"
	.size	.L__unnamed_8, 21

	.type	.L__unnamed_9,@object           # @8
.L__unnamed_9:
	.asciz	"_Z7train_BPfS_"
	.size	.L__unnamed_9, 15

	.type	.L__unnamed_10,@object          # @9
.L__unnamed_10:
	.asciz	"_Z8train_WhPfS_S_i"
	.size	.L__unnamed_10, 19

	.type	.L__unnamed_11,@object          # @10
.L__unnamed_11:
	.asciz	"_Z9normalizePfS_S_"
	.size	.L__unnamed_11, 19

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z24__device_stub__predict_NPf
	.addrsig_sym _Z25__device_stub__predict_WNPfS_S_i
	.addrsig_sym _Z25__device_stub__predict_RiPfii
	.addrsig_sym _Z25__device_stub__predict_NkPfS_i
	.addrsig_sym _Z25__device_stub__predict_YpPfS_
	.addrsig_sym _Z22__device_stub__train_VPfS_S_
	.addrsig_sym _Z23__device_stub__train_WfPfS_S_
	.addrsig_sym _Z23__device_stub__train_WNPfS_S_S_i
	.addrsig_sym _Z22__device_stub__train_BPfS_
	.addrsig_sym _Z23__device_stub__train_WhPfS_S_i
	.addrsig_sym _Z24__device_stub__normalizePfS_S_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym W
	.addrsig_sym R
	.addrsig_sym N
	.addrsig_sym Y
	.addrsig_sym pY
	.addrsig_sym U
	.addrsig_sym V
	.addrsig_sym Yh
	.addrsig_sym Dh
	.addrsig_sym _Z9predict_NPf
	.addrsig_sym _Z10predict_WNPfS_S_i
	.addrsig_sym _Z10predict_RiPfii
	.addrsig_sym _Z10predict_NkPfS_i
	.addrsig_sym _Z10predict_YpPfS_
	.addrsig_sym _Z7train_VPfS_S_
	.addrsig_sym _Z8train_WfPfS_S_
	.addrsig_sym _Z8train_WNPfS_S_S_i
	.addrsig_sym _Z7train_BPfS_
	.addrsig_sym _Z8train_WhPfS_S_i
	.addrsig_sym _Z9normalizePfS_S_
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z9predict_NPf          ; -- Begin function _Z9predict_NPf
	.globl	_Z9predict_NPf
	.p2align	8
	.type	_Z9predict_NPf,@function
_Z9predict_NPf:                         ; @_Z9predict_NPf
; %bb.0:
	s_load_b32 s4, s[0:1], 0x14
	s_add_u32 s2, s0, 8
	s_addc_u32 s3, s1, 0
	s_mov_b32 s5, exec_lo
	s_waitcnt lgkmcnt(0)
	s_and_b32 s4, s4, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s15, s15, s4
	v_add3_u32 v0, v0, s15, 0x3e8
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e32 0x1388, v0
	s_cbranch_execz .LBB0_3
; %bb.1:                                ; %.lr.ph.preheader
	s_load_b32 s2, s[2:3], 0x0
	s_load_b64 s[0:1], s[0:1], 0x0
	v_ashrrev_i32_e32 v1, 31, v0
	v_mov_b32_e32 v3, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[0:1]
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s2, s2, s4
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	s_ashr_i32 s3, s2, 31
	s_mov_b32 s1, 0
	s_lshl_b64 s[4:5], s[2:3], 2
.LBB0_2:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	v_add_nc_u32_e32 v0, s2, v0
	global_store_b32 v[1:2], v3, off
	v_add_co_u32 v1, s0, v1, s4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_add_co_ci_u32_e64 v2, s0, s5, v2, s0
	v_cmp_lt_i32_e32 vcc_lo, 0x1387, v0
	s_or_b32 s1, vcc_lo, s1
	s_and_not1_b32 exec_lo, exec_lo, s1
	s_cbranch_execnz .LBB0_2
.LBB0_3:                                ; %._crit_edge
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z9predict_NPf
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 264
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 4
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z9predict_NPf, .Lfunc_end0-_Z9predict_NPf
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 204
; NumSgprs: 18
; NumVgprs: 4
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 4
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z10predict_WNPfS_S_i   ; -- Begin function _Z10predict_WNPfS_S_i
	.globl	_Z10predict_WNPfS_S_i
	.p2align	8
	.type	_Z10predict_WNPfS_S_i,@function
_Z10predict_WNPfS_S_i:                  ; @_Z10predict_WNPfS_S_i
; %bb.0:
	s_load_b32 s4, s[0:1], 0x2c
	s_add_u32 s2, s0, 32
	s_addc_u32 s3, s1, 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s8, s4, 0xffff
	s_mov_b32 s4, exec_lo
	v_mad_u64_u32 v[1:2], null, s15, s8, v[0:1]
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e32 0xf4240, v1
	s_cbranch_execz .LBB1_3
; %bb.1:                                ; %.lr.ph.preheader
	s_load_b32 s9, s[0:1], 0x18
	s_load_b32 s2, s[2:3], 0x0
	s_load_b64 s[10:11], s[0:1], 0x10
	v_ashrrev_i32_e32 v2, 31, v1
	s_load_b128 s[4:7], s[0:1], 0x0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[5:6], 2, v[1:2]
	s_waitcnt lgkmcnt(0)
	v_mad_u64_u32 v[3:4], null, 0xf4240, s9, v[1:2]
	v_add_co_u32 v0, vcc_lo, s10, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v2, vcc_lo, s11, v6, vcc_lo
	s_mul_i32 s2, s2, s8
	s_mul_i32 s1, s9, 0x3e8
	v_ashrrev_i32_e32 v4, 31, v3
	s_ashr_i32 s3, s2, 31
	s_mov_b64 s[8:9], 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	v_add_co_u32 v3, vcc_lo, s6, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
	s_lshl_b64 s[6:7], s[2:3], 2
	s_mov_b32 s3, 0
.LBB1_2:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	v_mul_hi_i32 v5, 0x10624dd3, v1
	v_add_co_u32 v7, vcc_lo, v3, s8
	v_add_co_ci_u32_e32 v8, vcc_lo, s9, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshrrev_b32_e32 v6, 31, v5
	v_ashrrev_i32_e32 v5, 6, v5
	v_add_nc_u32_e32 v5, v5, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v5, 0x3e8, v5
	v_sub_nc_u32_e32 v5, v1, v5
	v_add_nc_u32_e32 v1, s2, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v5, s1, v5
	v_cmp_lt_i32_e64 s0, 0xf423f, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v6, 31, v5
	v_lshlrev_b64 v[5:6], 2, v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v5, vcc_lo, s4, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
	global_load_b32 v7, v[7:8], off
	global_load_b32 v8, v[5:6], off
	v_add_co_u32 v5, vcc_lo, v0, s8
	v_add_co_ci_u32_e32 v6, vcc_lo, s9, v2, vcc_lo
	s_add_u32 s8, s8, s6
	s_addc_u32 s9, s9, s7
	s_or_b32 s3, s0, s3
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v7, v7, v8
	global_store_b32 v[5:6], v7, off
	s_and_not1_b32 exec_lo, exec_lo, s3
	s_cbranch_execnz .LBB1_2
.LBB1_3:                                ; %._crit_edge
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z10predict_WNPfS_S_i
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 9
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z10predict_WNPfS_S_i, .Lfunc_end1-_Z10predict_WNPfS_S_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 388
; NumSgprs: 18
; NumVgprs: 9
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 9
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z10predict_RiPfii      ; -- Begin function _Z10predict_RiPfii
	.globl	_Z10predict_RiPfii
	.p2align	8
	.type	_Z10predict_RiPfii,@function
_Z10predict_RiPfii:                     ; @_Z10predict_RiPfii
; %bb.0:
	s_clause 0x2
	s_load_b32 s2, s[0:1], 0x1c
	s_load_b32 s3, s[0:1], 0x10
	s_load_b128 s[4:7], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mul_i32 s1, s3, s2
	s_mul_hi_i32 s0, s1, 0x10624dd3
	s_add_i32 s3, s1, 0x3e7
	s_lshr_b32 s2, s0, 31
	s_ashr_i32 s0, s0, 6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
	v_mul_hi_i32 v0, 0x10624dd3, v1
	s_cmpk_lt_u32 s3, 0x7cf
	s_mul_i32 s11, s1, 0x3e8
	s_cselect_b32 s3, -1, 0
	s_cmp_lg_u32 s3, 0
	s_addc_u32 s0, s0, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
	v_lshrrev_b32_e32 v2, 31, v0
	v_ashrrev_i32_e32 v0, 6, v0
	s_lshl_b32 s2, s7, 1
	s_add_i32 s10, s6, -1
	s_mul_i32 s10, s10, s7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v0, v0, v2
	v_mul_lo_u32 v2, v0, s7
	v_mul_i32_i24_e32 v3, 0x3e8, v0
	v_mul_lo_u32 v8, v0, s2
	v_mul_lo_u32 v0, 0x3e8, v1
	s_mul_i32 s2, s0, s2
	s_delay_alu instid0(VALU_DEP_3)
	v_mul_lo_u32 v4, 0x3e8, v3
	v_sub_nc_u32_e32 v9, v1, v3
	v_lshlrev_b32_e32 v2, 1, v2
	s_ashr_i32 s3, s2, 31
	v_cmp_gt_i32_e32 vcc_lo, s10, v8
	v_add_nc_u32_e32 v1, v8, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_add3_u32 v2, v2, s7, v0
	s_lshl_b64 s[6:7], s[2:3], 2
	s_mov_b32 s3, 0
	v_sub_nc_u32_e32 v0, v1, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_sub_nc_u32_e32 v2, v2, v4
.LBB2_1:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB2_3 Depth 2
	s_and_saveexec_b32 s12, vcc_lo
	s_cbranch_execz .LBB2_4
; %bb.2:                                ; %.lr.ph.preheader
                                        ;   in Loop: Header=BB2_1 Depth=1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v1, 31, v0
	v_ashrrev_i32_e32 v3, 31, v2
	s_mov_b32 s13, 0
	s_mov_b64 s[8:9], s[4:5]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[4:5], 2, v[0:1]
	v_lshlrev_b64 v[6:7], 2, v[2:3]
	v_mov_b32_e32 v1, v8
.LBB2_3:                                ; %.lr.ph
                                        ;   Parent Loop BB2_1 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v10, s0, s8, v6
	v_add_co_ci_u32_e64 v11, s0, s9, v7, s0
	v_add_co_u32 v12, s0, s8, v4
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v13, s0, s9, v5, s0
	v_add_nc_u32_e32 v1, s2, v1
	s_clause 0x1
	global_load_b32 v3, v[10:11], off
	global_load_b32 v10, v[12:13], off
	s_add_u32 s8, s8, s6
	s_addc_u32 s9, s9, s7
	v_cmp_le_i32_e64 s0, s10, v1
	s_delay_alu instid0(VALU_DEP_1)
	s_or_b32 s13, s0, s13
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v3, v3, v10
	global_store_b32 v[12:13], v3, off
	s_and_not1_b32 exec_lo, exec_lo, s13
	s_cbranch_execnz .LBB2_3
.LBB2_4:                                ; %Flow39
                                        ;   in Loop: Header=BB2_1 Depth=1
	s_or_b32 exec_lo, exec_lo, s12
	v_add_nc_u32_e32 v9, s1, v9
	v_add_nc_u32_e32 v0, s11, v0
	v_add_nc_u32_e32 v2, s11, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_i32_e64 s0, 0x3e7, v9
	s_or_b32 s3, s0, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s3
	s_cbranch_execnz .LBB2_1
; %bb.5:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z10predict_RiPfii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 14
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_Z10predict_RiPfii, .Lfunc_end2-_Z10predict_RiPfii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 484
; NumSgprs: 18
; NumVgprs: 14
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 14
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z10predict_NkPfS_i     ; -- Begin function _Z10predict_NkPfS_i
	.globl	_Z10predict_NkPfS_i
	.p2align	8
	.type	_Z10predict_NkPfS_i,@function
_Z10predict_NkPfS_i:                    ; @_Z10predict_NkPfS_i
; %bb.0:
	s_load_b32 s4, s[0:1], 0x24
	s_add_u32 s2, s0, 24
	s_addc_u32 s3, s1, 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s8, s4, 0xffff
	s_mov_b32 s4, exec_lo
	v_mad_u64_u32 v[1:2], null, s15, s8, v[0:1]
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e32 0x3e8, v1
	s_cbranch_execz .LBB3_7
; %bb.1:                                ; %.lr.ph
	s_load_b32 s2, s[2:3], 0x0
	s_clause 0x1
	s_load_b32 s3, s[0:1], 0x10
	s_load_b128 s[4:7], s[0:1], 0x0
	v_mul_lo_u32 v2, 0x3e8, v1
	s_mov_b32 s1, 0
	s_mov_b32 s9, 0xbbbac73d
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s2, s2, s8
	s_mulk_i32 s3, 0x3e8
	s_mul_i32 s8, s2, 0x3e8
.LBB3_2:                                ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[3:4], 2, v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, s6, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
	global_load_b32 v0, v[3:4], off
                                        ; implicit-def: $vgpr3
	s_waitcnt vmcnt(0)
	v_cmp_ngt_f32_e64 s0, 0x3f200000, |v0|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_saveexec_b32 s10, s0
	s_xor_b32 s0, exec_lo, s10
	s_cbranch_execz .LBB3_4
; %bb.3:                                ;   in Loop: Header=BB3_2 Depth=1
	v_add_f32_e64 v3, |v0|, |v0|
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v4, 0x3fb8aa3b, v3
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v3
	v_rndne_f32_e32 v5, v4
	v_fma_f32 v6, 0x3fb8aa3b, v3, -v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v4, v4, v5
	v_fmac_f32_e32 v6, 0x32a5705f, v3
	v_cvt_i32_f32_e32 v5, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v4, v4, v6
	v_exp_f32_e32 v4, v4
	s_waitcnt_depctr 0xfff
	v_ldexp_f32 v4, v4, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v4, 0, v4, vcc_lo
	v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v3
	v_cndmask_b32_e32 v3, 0x7f800000, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v3, 1.0, v3
	v_rcp_f32_e32 v3, v3
	s_waitcnt_depctr 0xfff
	v_fma_f32 v3, v3, -2.0, 1.0
.LBB3_4:                                ; %Flow
                                        ;   in Loop: Header=BB3_2 Depth=1
	s_and_not1_saveexec_b32 s0, s0
; %bb.5:                                ;   in Loop: Header=BB3_2 Depth=1
	v_mul_f32_e32 v3, v0, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmaak_f32 v4, s9, v3, 0x3ca908c9
	v_fmaak_f32 v4, v3, v4, 0xbd5c1c4e
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmaak_f32 v4, v3, v4, 0x3e088382
	v_fmaak_f32 v4, v3, v4, 0xbeaaaa99
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e64 v4, |v0|, v4
	v_fma_f32 v3, v3, v4, |v0|
; %bb.6:                                ; %_ZL5tanhff.exit
                                        ;   in Loop: Header=BB3_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	v_add_nc_u32_e32 v4, s3, v1
	v_add_nc_u32_e32 v1, s2, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_bfi_b32 v0, 0x7fffffff, v3, v0
	v_add_nc_u32_e32 v2, s8, v2
	v_ashrrev_i32_e32 v5, 31, v4
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_lt_i32_e32 vcc_lo, 0x3e7, v1
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	s_or_b32 s1, vcc_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v3, s0, s4, v4
	v_add_co_ci_u32_e64 v4, s0, s5, v5, s0
	global_store_b32 v[3:4], v0, off
	s_and_not1_b32 exec_lo, exec_lo, s1
	s_cbranch_execnz .LBB3_2
.LBB3_7:                                ; %._crit_edge
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z10predict_NkPfS_i
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 7
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end3:
	.size	_Z10predict_NkPfS_i, .Lfunc_end3-_Z10predict_NkPfS_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 512
; NumSgprs: 18
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z10predict_YpPfS_      ; -- Begin function _Z10predict_YpPfS_
	.globl	_Z10predict_YpPfS_
	.p2align	8
	.type	_Z10predict_YpPfS_,@function
_Z10predict_YpPfS_:                     ; @_Z10predict_YpPfS_
; %bb.0:
	s_load_b32 s4, s[0:1], 0x1c
	s_add_u32 s2, s0, 16
	s_addc_u32 s3, s1, 0
	s_mov_b32 s5, exec_lo
	s_waitcnt lgkmcnt(0)
	s_and_b32 s4, s4, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
	v_cmpx_gt_i32_e32 0x3e8, v1
	s_cbranch_execz .LBB4_3
; %bb.1:                                ; %.lr.ph.preheader
	s_load_b32 s5, s[2:3], 0x0
	s_load_b128 s[0:3], s[0:1], 0x0
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[1:2]
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s4, s5, s4
	s_add_u32 s8, s0, 0x3e80
	s_addc_u32 s1, s1, 0
	s_ashr_i32 s5, s4, 31
	s_delay_alu instid0(SALU_CYCLE_1)
	s_lshl_b64 s[6:7], s[4:5], 2
	s_mov_b32 s5, 0
.LBB4_2:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	v_add_co_u32 v4, vcc_lo, s8, v2
	v_add_co_ci_u32_e32 v5, vcc_lo, s1, v3, vcc_lo
	v_add_nc_u32_e32 v1, s4, v1
	global_load_b32 v0, v[4:5], off
	v_add_co_u32 v4, vcc_lo, s2, v2
	v_add_co_ci_u32_e32 v5, vcc_lo, s3, v3, vcc_lo
	v_cmp_lt_i32_e32 vcc_lo, 0x3e7, v1
	v_add_co_u32 v2, s0, v2, s6
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v3, s0, s7, v3, s0
	s_or_b32 s5, vcc_lo, s5
	s_waitcnt vmcnt(0)
	global_store_b32 v[4:5], v0, off
	s_and_not1_b32 exec_lo, exec_lo, s5
	s_cbranch_execnz .LBB4_2
.LBB4_3:                                ; %._crit_edge
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z10predict_YpPfS_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 6
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end4:
	.size	_Z10predict_YpPfS_, .Lfunc_end4-_Z10predict_YpPfS_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 224
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z7train_VPfS_S_        ; -- Begin function _Z7train_VPfS_S_
	.globl	_Z7train_VPfS_S_
	.p2align	8
	.type	_Z7train_VPfS_S_,@function
_Z7train_VPfS_S_:                       ; @_Z7train_VPfS_S_
; %bb.0:
	s_load_b32 s4, s[0:1], 0x24
	s_add_u32 s2, s0, 24
	s_addc_u32 s3, s1, 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s8, s4, 0xffff
	s_mov_b32 s4, exec_lo
	v_mad_u64_u32 v[1:2], null, s15, s8, v[0:1]
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e32 0x3e8, v1
	s_cbranch_execz .LBB5_3
; %bb.1:                                ; %.lr.ph.preheader
	s_load_b32 s9, s[2:3], 0x0
	s_clause 0x1
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b64 s[2:3], s[0:1], 0x10
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[1:2]
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s8, s9, s8
	s_add_u32 s1, s4, 0x3e80
	s_addc_u32 s10, s5, 0
	s_ashr_i32 s9, s8, 31
	s_delay_alu instid0(SALU_CYCLE_1)
	s_lshl_b64 s[4:5], s[8:9], 2
	s_mov_b32 s9, 0
.LBB5_2:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	v_add_co_u32 v4, vcc_lo, s1, v2
	v_add_co_ci_u32_e32 v5, vcc_lo, s10, v3, vcc_lo
	v_add_co_u32 v6, vcc_lo, s6, v2
	v_add_co_ci_u32_e32 v7, vcc_lo, s7, v3, vcc_lo
	global_load_b32 v0, v[4:5], off
	global_load_b32 v6, v[6:7], off
	v_add_nc_u32_e32 v1, s8, v1
	v_add_co_u32 v4, vcc_lo, s2, v2
	v_add_co_ci_u32_e32 v5, vcc_lo, s3, v3, vcc_lo
	v_add_co_u32 v2, vcc_lo, v2, s4
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
	s_waitcnt vmcnt(0)
	v_sub_f32_e32 v6, v0, v6
	v_fma_f32 v0, -v0, v0, 1.0
	v_cmp_lt_i32_e64 s0, 0x3e7, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v0, v6, v0
	s_or_b32 s9, s0, s9
	global_store_b32 v[4:5], v0, off
	s_and_not1_b32 exec_lo, exec_lo, s9
	s_cbranch_execnz .LBB5_2
.LBB5_3:                                ; %Flow30
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7train_VPfS_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 8
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end5:
	.size	_Z7train_VPfS_S_, .Lfunc_end5-_Z7train_VPfS_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 272
; NumSgprs: 18
; NumVgprs: 8
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 8
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z8train_WfPfS_S_       ; -- Begin function _Z8train_WfPfS_S_
	.globl	_Z8train_WfPfS_S_
	.p2align	8
	.type	_Z8train_WfPfS_S_,@function
_Z8train_WfPfS_S_:                      ; @_Z8train_WfPfS_S_
; %bb.0:
	s_load_b32 s4, s[0:1], 0x24
	s_add_u32 s2, s0, 24
	s_addc_u32 s3, s1, 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s8, s4, 0xffff
	s_mov_b32 s4, exec_lo
	v_mad_u64_u32 v[1:2], null, s15, s8, v[0:1]
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e32 0xf4240, v1
	s_cbranch_execz .LBB6_3
; %bb.1:                                ; %.lr.ph.preheader
	s_load_b32 s2, s[2:3], 0x0
	s_clause 0x1
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b64 s[0:1], s[0:1], 0x10
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s2, s2, s8
	s_add_u32 s3, s4, 0x2ee0
	s_addc_u32 s4, s5, 0
	s_mov_b32 s5, 0
.LBB6_2:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	v_mul_hi_i32 v0, 0x10624dd3, v1
	v_add_nc_u32_e32 v2, 0x2dc6c0, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshrrev_b32_e32 v4, 31, v0
	v_ashrrev_i32_e32 v0, 6, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	v_add_nc_u32_e32 v4, v0, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s6, v2
	v_mul_i32_i24_e32 v0, 0x3e8, v4
	v_ashrrev_i32_e32 v5, 31, v4
	v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v6, v1, v0
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v7, 31, v6
	v_add_co_u32 v4, vcc_lo, s0, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
	v_lshlrev_b64 v[6:7], 2, v[6:7]
	global_load_b32 v0, v[4:5], off
	v_add_nc_u32_e32 v1, s2, v1
	v_add_co_u32 v4, vcc_lo, s3, v6
	v_add_co_ci_u32_e32 v5, vcc_lo, s4, v7, vcc_lo
	global_load_b32 v6, v[2:3], off
	global_load_b32 v4, v[4:5], off
	s_waitcnt vmcnt(2)
	v_mul_f32_e32 v0, 0xb8d1b717, v0
	v_cmp_lt_i32_e32 vcc_lo, 0xf423f, v1
	s_or_b32 s5, vcc_lo, s5
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2)
	v_fmac_f32_e32 v6, v0, v4
	global_store_b32 v[2:3], v6, off
	s_and_not1_b32 exec_lo, exec_lo, s5
	s_cbranch_execnz .LBB6_2
.LBB6_3:                                ; %._crit_edge
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z8train_WfPfS_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 8
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end6:
	.size	_Z8train_WfPfS_S_, .Lfunc_end6-_Z8train_WfPfS_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 340
; NumSgprs: 18
; NumVgprs: 8
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 8
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z8train_WNPfS_S_S_i    ; -- Begin function _Z8train_WNPfS_S_S_i
	.globl	_Z8train_WNPfS_S_S_i
	.p2align	8
	.type	_Z8train_WNPfS_S_S_i,@function
_Z8train_WNPfS_S_S_i:                   ; @_Z8train_WNPfS_S_S_i
; %bb.0:
	s_load_b32 s4, s[0:1], 0x34
	s_add_u32 s2, s0, 40
	s_addc_u32 s3, s1, 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s12, s4, 0xffff
	s_mov_b32 s4, exec_lo
	v_mad_u64_u32 v[1:2], null, s15, s12, v[0:1]
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e32 0xf4240, v1
	s_cbranch_execz .LBB7_3
; %bb.1:                                ; %.lr.ph.preheader
	s_load_b32 s2, s[2:3], 0x0
	s_clause 0x1
	s_load_b32 s3, s[0:1], 0x20
	s_load_b256 s[4:11], s[0:1], 0x0
	v_mul_lo_u32 v0, 0x3e8, v1
	s_mov_b32 s13, 0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s1, s2, s12
	s_mul_i32 s2, s3, 0x3e8
	s_mul_i32 s3, s3, 0xf4240
	s_mul_i32 s12, s1, 0x3e8
.LBB7_2:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	v_mul_hi_i32 v4, 0x10624dd3, v1
	v_add_nc_u32_e32 v2, s3, v1
	v_add_nc_u32_e32 v6, s2, v1
	v_add_nc_u32_e32 v1, s1, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshrrev_b32_e32 v5, 31, v4
	v_ashrrev_i32_e32 v4, 6, v4
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v4, v4, v5
	v_add_co_u32 v2, vcc_lo, s6, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_mul_i32_i24_e32 v10, 0x3e8, v4
	v_ashrrev_i32_e32 v5, 31, v4
	v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
	v_sub_nc_u32_e32 v6, v6, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[8:9], 2, v[4:5]
	v_ashrrev_i32_e32 v7, 31, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v5, vcc_lo, s8, v8
	v_lshlrev_b64 v[7:8], 2, v[6:7]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v6, vcc_lo, s9, v9, vcc_lo
	v_add_co_u32 v7, vcc_lo, s4, v7
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v8, vcc_lo, s5, v8, vcc_lo
	global_load_b32 v9, v[2:3], off
	global_load_b32 v5, v[5:6], off
	global_load_b32 v6, v[7:8], off
	v_mul_lo_u32 v2, 0x3e8, v10
	v_cmp_lt_i32_e32 vcc_lo, 0xf423f, v1
	s_or_b32 s13, vcc_lo, s13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v2, v4, v2
	v_add_nc_u32_e32 v2, v0, v2
	v_add_nc_u32_e32 v0, s12, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v2, s0, s10, v2
	v_add_co_ci_u32_e64 v3, s0, s11, v3, s0
	s_waitcnt vmcnt(1)
	v_mul_f32_e32 v4, v5, v9
	s_waitcnt vmcnt(0)
	v_fma_f32 v5, -v6, v6, 1.0
	s_delay_alu instid0(VALU_DEP_1)
	v_mul_f32_e32 v4, v4, v5
	global_store_b32 v[2:3], v4, off
	s_and_not1_b32 exec_lo, exec_lo, s13
	s_cbranch_execnz .LBB7_2
.LBB7_3:                                ; %._crit_edge
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z8train_WNPfS_S_S_i
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 11
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end7:
	.size	_Z8train_WNPfS_S_S_i, .Lfunc_end7-_Z8train_WNPfS_S_S_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 436
; NumSgprs: 18
; NumVgprs: 11
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 11
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z7train_BPfS_          ; -- Begin function _Z7train_BPfS_
	.globl	_Z7train_BPfS_
	.p2align	8
	.type	_Z7train_BPfS_,@function
_Z7train_BPfS_:                         ; @_Z7train_BPfS_
; %bb.0:
	s_load_b32 s4, s[0:1], 0x1c
	s_add_u32 s2, s0, 16
	s_addc_u32 s3, s1, 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s8, s4, 0xffff
	s_mov_b32 s4, exec_lo
	v_mad_u64_u32 v[1:2], null, s15, s8, v[0:1]
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e32 0x3e8, v1
	s_cbranch_execz .LBB8_3
; %bb.1:                                ; %.lr.ph.preheader
	s_load_b32 s2, s[2:3], 0x0
	s_load_b128 s[4:7], s[0:1], 0x0
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[4:5], 2, v[1:2]
	v_mul_lo_u32 v2, 0x3e8, v1
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s2, s2, s8
	v_add_co_u32 v4, vcc_lo, s6, v4
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v5, vcc_lo, s7, v5, vcc_lo
	s_ashr_i32 s3, s2, 31
	s_mul_i32 s1, s2, 0x3e8
	s_lshl_b64 s[6:7], s[2:3], 2
	s_mov_b32 s3, 0
.LBB8_2:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	v_ashrrev_i32_e32 v3, 31, v2
	v_add_nc_u32_e32 v1, s2, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[6:7], 2, v[2:3]
	v_add_nc_u32_e32 v2, s1, v2
	v_add_co_u32 v6, vcc_lo, s4, v6
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
	v_cmp_lt_i32_e32 vcc_lo, 0x3e7, v1
	global_load_b32 v0, v[6:7], off
	s_or_b32 s3, vcc_lo, s3
	s_waitcnt vmcnt(0)
	global_store_b32 v[4:5], v0, off
	v_add_co_u32 v4, s0, v4, s6
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v5, s0, s7, v5, s0
	s_and_not1_b32 exec_lo, exec_lo, s3
	s_cbranch_execnz .LBB8_2
.LBB8_3:                                ; %._crit_edge
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7train_BPfS_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 8
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end8:
	.size	_Z7train_BPfS_, .Lfunc_end8-_Z7train_BPfS_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 256
; NumSgprs: 18
; NumVgprs: 8
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 8
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z8train_WhPfS_S_i      ; -- Begin function _Z8train_WhPfS_S_i
	.globl	_Z8train_WhPfS_S_i
	.p2align	8
	.type	_Z8train_WhPfS_S_i,@function
_Z8train_WhPfS_S_i:                     ; @_Z8train_WhPfS_S_i
; %bb.0:
	s_load_b32 s4, s[0:1], 0x2c
	s_add_u32 s2, s0, 32
	s_addc_u32 s3, s1, 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s8, s4, 0xffff
	s_mov_b32 s4, exec_lo
	v_mad_u64_u32 v[1:2], null, s15, s8, v[0:1]
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e32 0xf4240, v1
	s_cbranch_execz .LBB9_3
; %bb.1:                                ; %.lr.ph.preheader
	s_load_b32 s2, s[2:3], 0x0
	s_clause 0x2
	s_load_b32 s9, s[0:1], 0x18
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b64 s[0:1], s[0:1], 0x10
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s2, s2, s8
	s_mul_i32 s3, s9, 0x3e8
	s_mul_i32 s8, s9, 0xf4240
	s_mov_b32 s9, 0
.LBB9_2:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	v_mul_hi_i32 v0, 0x10624dd3, v1
	v_add_nc_u32_e32 v2, s8, v1
	v_add_nc_u32_e32 v6, s3, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshrrev_b32_e32 v4, 31, v0
	v_ashrrev_i32_e32 v0, 6, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	v_add_nc_u32_e32 v4, v0, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s6, v2
	v_mul_i32_i24_e32 v0, 0x3e8, v4
	v_ashrrev_i32_e32 v5, 31, v4
	v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v6, v6, v0
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v7, 31, v6
	v_add_co_u32 v4, vcc_lo, s0, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
	v_lshlrev_b64 v[6:7], 2, v[6:7]
	global_load_b32 v0, v[4:5], off
	v_add_nc_u32_e32 v1, s2, v1
	v_add_co_u32 v4, vcc_lo, s4, v6
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v7, vcc_lo
	global_load_b32 v6, v[2:3], off
	global_load_b32 v4, v[4:5], off
	s_waitcnt vmcnt(2)
	v_mul_f32_e32 v0, 0xb8d1b717, v0
	v_cmp_lt_i32_e32 vcc_lo, 0xf423f, v1
	s_or_b32 s9, vcc_lo, s9
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2)
	v_fmac_f32_e32 v6, v0, v4
	global_store_b32 v[2:3], v6, off
	s_and_not1_b32 exec_lo, exec_lo, s9
	s_cbranch_execnz .LBB9_2
.LBB9_3:                                ; %._crit_edge
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z8train_WhPfS_S_i
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 8
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end9:
	.size	_Z8train_WhPfS_S_i, .Lfunc_end9-_Z8train_WhPfS_S_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 352
; NumSgprs: 18
; NumVgprs: 8
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 8
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z9normalizePfS_S_      ; -- Begin function _Z9normalizePfS_S_
	.globl	_Z9normalizePfS_S_
	.p2align	8
	.type	_Z9normalizePfS_S_,@function
_Z9normalizePfS_S_:                     ; @_Z9normalizePfS_S_
; %bb.0:
	s_clause 0x3
	s_load_b32 s2, s[0:1], 0x24
	s_load_b32 s3, s[0:1], 0x18
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b64 s[8:9], s[0:1], 0x10
	s_mov_b32 s1, exec_lo
	s_waitcnt lgkmcnt(0)
	s_and_b32 s0, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s0, v[0:1]
	s_mul_i32 s2, s3, s0
	v_ashrrev_i32_e32 v2, 31, v1
	v_cmpx_gt_i32_e32 0x3d0900, v1
	s_cbranch_execz .LBB10_3
; %bb.1:                                ; %.lr.ph.preheader
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[3:4], 2, v[1:2]
	v_dual_mov_b32 v0, 0x3a83126f :: v_dual_mov_b32 v5, v1
	s_ashr_i32 s3, s2, 31
	v_add_co_u32 v3, vcc_lo, s4, v3
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
	s_lshl_b64 s[4:5], s[2:3], 2
	s_mov_b32 s3, 0
.LBB10_2:                               ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	v_add_nc_u32_e32 v5, s2, v5
	global_store_b32 v[3:4], v0, off
	v_add_co_u32 v3, s0, v3, s4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_add_co_ci_u32_e64 v4, s0, s5, v4, s0
	v_cmp_lt_i32_e32 vcc_lo, 0x3d08ff, v5
	s_or_b32 s3, vcc_lo, s3
	s_and_not1_b32 exec_lo, exec_lo, s3
	s_cbranch_execnz .LBB10_2
.LBB10_3:                               ; %Flow46
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_i32_e32 0x3e8, v1
	s_cbranch_execz .LBB10_8
; %bb.4:                                ; %.lr.ph26.preheader
	v_lshlrev_b64 v[2:3], 2, v[1:2]
	v_mov_b32_e32 v0, v1
	s_ashr_i32 s3, s2, 31
	s_mov_b32 s1, 0
	s_lshl_b64 s[4:5], s[2:3], 2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, s6, v2
	v_add_co_ci_u32_e32 v5, vcc_lo, s7, v3, vcc_lo
.LBB10_5:                               ; %.lr.ph26
                                        ; =>This Inner Loop Header: Depth=1
	v_cvt_f32_i32_e32 v6, v0
	v_add_nc_u32_e32 v0, s2, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_div_scale_f32 v7, null, 0x447a0000, 0x447a0000, v6
	v_div_scale_f32 v9, vcc_lo, v6, 0x447a0000, v6
	v_cmp_lt_i32_e64 s0, 0x3e7, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v8, v7
	s_or_b32 s1, s0, s1
	s_waitcnt_depctr 0xfff
	v_fma_f32 v10, -v7, v8, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v8, v10, v8
	v_mul_f32_e32 v10, v9, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v11, -v7, v10, v9
	v_fmac_f32_e32 v10, v11, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v7, -v7, v10, v9
	v_div_fmas_f32 v7, v7, v8, v10
	s_delay_alu instid0(VALU_DEP_1)
	v_div_fixup_f32 v6, v7, 0x447a0000, v6
	global_store_b32 v[4:5], v6, off
	v_add_co_u32 v4, vcc_lo, v4, s4
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
	s_and_not1_b32 exec_lo, exec_lo, s1
	s_cbranch_execnz .LBB10_5
; %bb.6:                                ; %.preheader
	s_or_b32 exec_lo, exec_lo, s1
	v_add_co_u32 v2, vcc_lo, s8, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
	s_mov_b32 s1, 0
.LBB10_7:                               ; %.lr.ph28
                                        ; =>This Inner Loop Header: Depth=1
	v_cvt_f32_i32_e32 v0, v1
	v_add_nc_u32_e32 v1, s2, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_div_scale_f32 v4, null, 0x447a0000, 0x447a0000, v0
	v_div_scale_f32 v6, vcc_lo, v0, 0x447a0000, v0
	v_cmp_lt_i32_e64 s0, 0x3e7, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v5, v4
	s_or_b32 s1, s0, s1
	s_waitcnt_depctr 0xfff
	v_fma_f32 v7, -v4, v5, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v5, v7, v5
	v_mul_f32_e32 v7, v6, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v8, -v4, v7, v6
	v_fmac_f32_e32 v7, v8, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v4, -v4, v7, v6
	v_div_fmas_f32 v4, v4, v5, v7
	s_delay_alu instid0(VALU_DEP_1)
	v_div_fixup_f32 v0, v4, 0x447a0000, v0
	global_store_b32 v[2:3], v0, off
	v_add_co_u32 v2, vcc_lo, v2, s4
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
	s_and_not1_b32 exec_lo, exec_lo, s1
	s_cbranch_execnz .LBB10_7
.LBB10_8:                               ; %._crit_edge
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z9normalizePfS_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 12
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end10:
	.size	_Z9normalizePfS_S_, .Lfunc_end10-_Z9normalizePfS_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 612
; NumSgprs: 18
; NumVgprs: 12
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 12
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
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        .value_kind:     hidden_grid_dims
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    .kernarg_segment_align: 8
    .kernarg_segment_size: 264
    .language:       OpenCL C
    .language_version:
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      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z9predict_NPf
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z9predict_NPf.kd
    .uniform_work_group_size: 1
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    .vgpr_count:     4
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
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    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
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      - 0
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    .symbol:         _Z10predict_WNPfS_S_i.kd
    .uniform_work_group_size: 1
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    .vgpr_count:     9
    .vgpr_spill_count: 0
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    .language_version:
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amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
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  - 2
...

	.end_amdgpu_metadata
