/**
 * Programmation GPU 
 * Universit Pierre et Marie Curie
 * Calcul de convolution sur une image.
 */

/**
 * V0
 *
 */

#include <cuda.h>
#include <stdio.h>

extern "C" double my_gettimeofday();

/** 
 * Controle des erreurs CUDA et debugging. 
 */

#ifdef CUDA_DEBUG
#define CUDA_SYNC_ERROR() {						\
    cudaError_t sync_error;						\
    cudaDeviceSynchronize();						\
    sync_error = cudaGetLastError();					\
    if(sync_error != cudaSuccess) {					\
      fprintf(stderr, "[CUDA SYNC ERROR at %s:%d -> %s]\n",		\
	      __FILE__ , __LINE__, cudaGetErrorString(sync_error));	\
      exit(EXIT_FAILURE);						\
    }									\
  }
#else /* #ifdef CUDA_DEBUG */
#define CUDA_SYNC_ERROR()
#endif /* #ifdef CUDA_DEBUG */

#define CUDA_ERROR(cuda_call) {					\
    cudaError_t error = cuda_call;				\
    if(error != cudaSuccess){					\
      fprintf(stderr, "[CUDA ERROR at %s:%d -> %s]\n",		\
	      __FILE__ , __LINE__, cudaGetErrorString(error));	\
      exit(EXIT_FAILURE);					\
    }								\
    CUDA_SYNC_ERROR();						\
  }



/**
 * Retourne le quotient entier superieur ou egal a "a/b". 
 * D'apres : CUDA SDK 4.1 
 */

static int iDivUp(int a, int b){
  return ((a % b != 0) ? (a / b + 1) : (a / b));
}

__global__ void convolKernel(float* d_buf, float* d_buf_aux, int nbl, int nbc){

	  int j = blockDim.x*blockIdx.x + threadIdx.x;
	  int i = blockDim.y*blockIdx.y + threadIdx.y;

	  if (i<nbl && j<nbc)
	  {

	  //Copie depuis convol.c
	  //=====================
	  /*** filtre moyenneur CONVOL_MOYENNE2 (filtre moyenneur avec
	     * un poid central plus fort):
	     * Rq: pour les bords, moyenne avec uniquement les cases presentes */
	  float denominateur = 0.0f;
	  float numerateur = 0.0f;
	  float poids_central;
 	  if (i<nbl-1){
	     numerateur += d_buf[(i+1)*nbc+j]; ++denominateur;
	     if (j>0){     numerateur += d_buf[(i+1)*nbc+j-1]; ++denominateur; }
	     if (j<nbc-1){ numerateur += d_buf[(i+1)*nbc+j+1]; ++denominateur; }
	  }
	  if (j>0){     numerateur += d_buf[(i)*nbc+j-1]; ++denominateur; }
	  if (j<nbc-1){ numerateur += d_buf[(i)*nbc+j+1]; ++denominateur; }
	  if (i>0){
	       numerateur +=  d_buf[(i-1)*nbc+j]; ++denominateur;
	       if (j>0){     numerateur += d_buf[(i-1)*nbc+j-1]; ++denominateur; }
	       if (j<nbc-1){ numerateur += d_buf[(i-1)*nbc+j+1]; ++denominateur; }
	  }

	 poids_central = denominateur*0.5f; /* poids central = 50% autres poids */
	 numerateur   += poids_central*d_buf[(i)*nbc+j];
	 denominateur += poids_central;

	d_buf_aux[i*nbc+j] = numerateur/denominateur;
	}
}					   


/**
 * Effectue 'nbiter' convolutions sur GPU et retourne
 * le pointeur vers le buffer contenant la derniere convolution. 
 */

extern "C"
float *gpu_multiples_convolutions(float buf[], 
				  float buf_aux[], 
				  int nbl, 
				  int nbc,
				  int nbiter, 
				  int nbThreadsParBloc){
  
  /*** TODO ***/;
  float *d_buf, *d_buf_aux;
  int grilleX, grilleY;
  int taille_alloc = nbc * nbl * sizeof(float);

  cudaMalloc((void **) &d_buf, taille_alloc);
  cudaMalloc((void **) &d_buf_aux, taille_alloc);

  cudaMemcpy(d_buf, buf, taille_alloc, cudaMemcpyHostToDevice);
  cudaMemcpy(d_buf_aux, buf_aux, taille_alloc, cudaMemcpyHostToDevice);

  grilleX = ceil((float)nbc/(float)nbThreadsParBloc);
  grilleY = ceil((float)nbl/(float)nbThreadsParBloc);
  dim3 threads_par_bloc(nbThreadsParBloc, nbThreadsParBloc);
  dim3 taille_grille(grilleX, grilleY);

  int i;
  for(i=0; i<nbiter; i++){
 	convolKernel<<<taille_grille, threads_par_bloc>>>(d_buf, d_buf_aux, nbl, nbc);
  	cudaMemcpy(d_buf, d_buf_aux, taille_alloc, cudaMemcpyDeviceToDevice);
 }

 cudaMemcpy(buf, d_buf, taille_alloc, cudaMemcpyDeviceToHost);
 return buf;			  
}

	.file	"tmpxft_002a49f6_00000000-6_gpu_convol_v0.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2031:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z36__device_stub__Z12convolKernelPfS_iiPfS_ii
	.type	_Z36__device_stub__Z12convolKernelPfS_iiPfS_ii, @function
_Z36__device_stub__Z12convolKernelPfS_iiPfS_ii:
.LFB2053:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z12convolKernelPfS_ii(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L2:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2053:
	.size	_Z36__device_stub__Z12convolKernelPfS_iiPfS_ii, .-_Z36__device_stub__Z12convolKernelPfS_iiPfS_ii
	.globl	_Z12convolKernelPfS_ii
	.type	_Z12convolKernelPfS_ii, @function
_Z12convolKernelPfS_ii:
.LFB2054:
	.cfi_startproc
	endbr64
	jmp	_Z36__device_stub__Z12convolKernelPfS_iiPfS_ii
	.cfi_endproc
.LFE2054:
	.size	_Z12convolKernelPfS_ii, .-_Z12convolKernelPfS_ii
	.globl	gpu_multiples_convolutions
	.type	gpu_multiples_convolutions, @function
gpu_multiples_convolutions:
.LFB2028:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movq	%rsi, %r15
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	movl	%r8d, %r14d
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movl	%ecx, %r13d
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movl	%edx, %r12d
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movl	%r9d, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movl	%ecx, %ebx
	imull	%edx, %ebx
	subq	$72, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, (%rsp)
	sall	$2, %ebx
	leaq	16(%rsp), %rdi
	movslq	%ebx, %rbx
	movq	%rbx, %rsi
	movq	%fs:40, %rax
	movq	%rax, 56(%rsp)
	xorl	%eax, %eax
	call	cudaMalloc@PLT
	leaq	24(%rsp), %rdi
	movq	%rbx, %rsi
	call	cudaMalloc@PLT
	movq	(%rsp), %rsi
	movq	16(%rsp), %rdi
	movq	%rbx, %rdx
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	movq	24(%rsp), %rdi
	movq	%r15, %rsi
	movq	%rbx, %rdx
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	cvtsi2ssl	%ebp, %xmm1
	cvtsi2ssl	%r13d, %xmm0
	movss	%xmm1, 12(%rsp)
	divss	%xmm1, %xmm0
	call	ceilf@PLT
	movss	12(%rsp), %xmm1
	movd	%xmm0, %r15d
	cvtsi2ssl	%r12d, %xmm0
	divss	%xmm1, %xmm0
	call	ceilf@PLT
	movd	%r15d, %xmm2
	xorl	%r15d, %r15d
	movl	%ebp, 32(%rsp)
	cvttss2sil	%xmm2, %eax
	movl	%ebp, 36(%rsp)
	movl	$1, 40(%rsp)
	movl	$1, 52(%rsp)
	movl	%eax, 44(%rsp)
	cvttss2sil	%xmm0, %eax
	movl	%eax, 48(%rsp)
.L9:
	cmpl	%r14d, %r15d
	jge	.L14
	movl	40(%rsp), %ecx
	movq	32(%rsp), %rdx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	44(%rsp), %rdi
	movl	52(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L10
	movq	24(%rsp), %rsi
	movq	16(%rsp), %rdi
	movl	%r13d, %ecx
	movl	%r12d, %edx
	call	_Z36__device_stub__Z12convolKernelPfS_iiPfS_ii
.L10:
	movq	24(%rsp), %rsi
	movq	16(%rsp), %rdi
	movq	%rbx, %rdx
	incl	%r15d
	movl	$3, %ecx
	call	cudaMemcpy@PLT
	jmp	.L9
.L14:
	movq	16(%rsp), %rsi
	movq	(%rsp), %rdi
	movl	$2, %ecx
	movq	%rbx, %rdx
	call	cudaMemcpy@PLT
	movq	56(%rsp), %rax
	subq	%fs:40, %rax
	je	.L12
	call	__stack_chk_fail@PLT
.L12:
	movq	(%rsp), %rax
	addq	$72, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2028:
	.size	gpu_multiples_convolutions, .-gpu_multiples_convolutions
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z12convolKernelPfS_ii"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2056:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z12convolKernelPfS_ii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2056:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

/**
 * Programmation GPU 
 * Universit Pierre et Marie Curie
 * Calcul de convolution sur une image.
 */

/**
 * V0
 *
 */

#include <hip/hip_runtime.h>
#include <stdio.h>

extern "C" double my_gettimeofday();

/** 
 * Controle des erreurs CUDA et debugging. 
 */

#ifdef CUDA_DEBUG
#define CUDA_SYNC_ERROR() {						\
    hipError_t sync_error;						\
    hipDeviceSynchronize();						\
    sync_error = hipGetLastError();					\
    if(sync_error != hipSuccess) {					\
      fprintf(stderr, "[CUDA SYNC ERROR at %s:%d -> %s]\n",		\
	      __FILE__ , __LINE__, hipGetErrorString(sync_error));	\
      exit(EXIT_FAILURE);						\
    }									\
  }
#else /* #ifdef CUDA_DEBUG */
#define CUDA_SYNC_ERROR()
#endif /* #ifdef CUDA_DEBUG */

#define CUDA_ERROR(cuda_call) {					\
    hipError_t error = cuda_call;				\
    if(error != hipSuccess){					\
      fprintf(stderr, "[CUDA ERROR at %s:%d -> %s]\n",		\
	      __FILE__ , __LINE__, hipGetErrorString(error));	\
      exit(EXIT_FAILURE);					\
    }								\
    CUDA_SYNC_ERROR();						\
  }



/**
 * Retourne le quotient entier superieur ou egal a "a/b". 
 * D'apres : CUDA SDK 4.1 
 */

static int iDivUp(int a, int b){
  return ((a % b != 0) ? (a / b + 1) : (a / b));
}

__global__ void convolKernel(float* d_buf, float* d_buf_aux, int nbl, int nbc){

	  int j = blockDim.x*blockIdx.x + threadIdx.x;
	  int i = blockDim.y*blockIdx.y + threadIdx.y;

	  if (i<nbl && j<nbc)
	  {

	  //Copie depuis convol.c
	  //=====================
	  /*** filtre moyenneur CONVOL_MOYENNE2 (filtre moyenneur avec
	     * un poid central plus fort):
	     * Rq: pour les bords, moyenne avec uniquement les cases presentes */
	  float denominateur = 0.0f;
	  float numerateur = 0.0f;
	  float poids_central;
 	  if (i<nbl-1){
	     numerateur += d_buf[(i+1)*nbc+j]; ++denominateur;
	     if (j>0){     numerateur += d_buf[(i+1)*nbc+j-1]; ++denominateur; }
	     if (j<nbc-1){ numerateur += d_buf[(i+1)*nbc+j+1]; ++denominateur; }
	  }
	  if (j>0){     numerateur += d_buf[(i)*nbc+j-1]; ++denominateur; }
	  if (j<nbc-1){ numerateur += d_buf[(i)*nbc+j+1]; ++denominateur; }
	  if (i>0){
	       numerateur +=  d_buf[(i-1)*nbc+j]; ++denominateur;
	       if (j>0){     numerateur += d_buf[(i-1)*nbc+j-1]; ++denominateur; }
	       if (j<nbc-1){ numerateur += d_buf[(i-1)*nbc+j+1]; ++denominateur; }
	  }

	 poids_central = denominateur*0.5f; /* poids central = 50% autres poids */
	 numerateur   += poids_central*d_buf[(i)*nbc+j];
	 denominateur += poids_central;

	d_buf_aux[i*nbc+j] = numerateur/denominateur;
	}
}					   


/**
 * Effectue 'nbiter' convolutions sur GPU et retourne
 * le pointeur vers le buffer contenant la derniere convolution. 
 */

extern "C"
float *gpu_multiples_convolutions(float buf[], 
				  float buf_aux[], 
				  int nbl, 
				  int nbc,
				  int nbiter, 
				  int nbThreadsParBloc){
  
  /*** TODO ***/;
  float *d_buf, *d_buf_aux;
  int grilleX, grilleY;
  int taille_alloc = nbc * nbl * sizeof(float);

  hipMalloc((void **) &d_buf, taille_alloc);
  hipMalloc((void **) &d_buf_aux, taille_alloc);

  hipMemcpy(d_buf, buf, taille_alloc, hipMemcpyHostToDevice);
  hipMemcpy(d_buf_aux, buf_aux, taille_alloc, hipMemcpyHostToDevice);

  grilleX = ceil((float)nbc/(float)nbThreadsParBloc);
  grilleY = ceil((float)nbl/(float)nbThreadsParBloc);
  dim3 threads_par_bloc(nbThreadsParBloc, nbThreadsParBloc);
  dim3 taille_grille(grilleX, grilleY);

  int i;
  for(i=0; i<nbiter; i++){
 	convolKernel<<<taille_grille, threads_par_bloc>>>(d_buf, d_buf_aux, nbl, nbc);
  	hipMemcpy(d_buf, d_buf_aux, taille_alloc, hipMemcpyDeviceToDevice);
 }

 hipMemcpy(buf, d_buf, taille_alloc, hipMemcpyDeviceToHost);
 return buf;			  
}

	.text
	.file	"gpu_convol_v0.hip"
	.globl	_Z27__device_stub__convolKernelPfS_ii # -- Begin function _Z27__device_stub__convolKernelPfS_ii
	.type	_Z27__device_stub__convolKernelPfS_ii,@function
_Z27__device_stub__convolKernelPfS_ii:  # @_Z27__device_stub__convolKernelPfS_ii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z12convolKernelPfS_ii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z27__device_stub__convolKernelPfS_ii, .Lfunc_end0-_Z27__device_stub__convolKernelPfS_ii
	.cfi_endproc
                                        # -- End function
	.globl	gpu_multiples_convolutions      # -- Begin function gpu_multiples_convolutions
	.type	gpu_multiples_convolutions,@function
gpu_multiples_convolutions:             # @gpu_multiples_convolutions
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$40, %rsp
	.cfi_def_cfa_offset 96
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%r9d, 28(%rsp)                  # 4-byte Spill
	movl	%r8d, %ebp
	movl	%ecx, %r14d
	movl	%edx, %r15d
	movq	%rsi, (%rsp)                    # 8-byte Spill
	movq	%rdi, %rbx
	movl	%edx, %eax
	imull	%ecx, %eax
	shll	$2, %eax
	movslq	%eax, %r12
	leaq	16(%rsp), %r13
	movq	%r13, %rdi
	movq	%r12, %rsi
	callq	hipMalloc
	leaq	8(%rsp), %rdi
	movq	%r12, %rsi
	callq	hipMalloc
	movq	(%r13), %rdi
	movl	28(%rsp), %r13d                 # 4-byte Reload
	movq	%rbx, 32(%rsp)                  # 8-byte Spill
	movq	%rbx, %rsi
	movq	%r12, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	8(%rsp), %rax
	movq	(%rax), %rdi
	movq	(%rsp), %rsi                    # 8-byte Reload
	movq	%r12, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	cvtsi2ss	%r14d, %xmm0
	cvtsi2ss	%r13d, %xmm1
	movss	%xmm1, (%rsp)                   # 4-byte Spill
	divss	%xmm1, %xmm0
	callq	ceilf@PLT
	movss	%xmm0, 24(%rsp)                 # 4-byte Spill
	xorps	%xmm0, %xmm0
	cvtsi2ss	%r15d, %xmm0
	divss	(%rsp), %xmm0                   # 4-byte Folded Reload
	callq	ceilf@PLT
	testl	%ebp, %ebp
	jle	.LBB1_5
# %bb.1:                                # %.lr.ph.preheader
	cvttss2si	24(%rsp), %eax          # 4-byte Folded Reload
	cvttss2si	%xmm0, %ebx
	movl	%r13d, %ecx
	movq	%rcx, %r13
	shlq	$32, %r13
	orq	%rcx, %r13
	shlq	$32, %rbx
	orq	%rax, %rbx
.LBB1_2:                                # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	movq	%rbx, %rdi
	movl	$1, %esi
	movq	%r13, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_4
# %bb.3:                                #   in Loop: Header=BB1_2 Depth=1
	movq	16(%rsp), %rdi
	movq	8(%rsp), %rsi
	movl	%r15d, %edx
	movl	%r14d, %ecx
	callq	_Z27__device_stub__convolKernelPfS_ii
.LBB1_4:                                #   in Loop: Header=BB1_2 Depth=1
	movq	16(%rsp), %rdi
	movq	8(%rsp), %rsi
	movq	%r12, %rdx
	movl	$3, %ecx
	callq	hipMemcpy
	decl	%ebp
	jne	.LBB1_2
.LBB1_5:                                # %._crit_edge
	movq	16(%rsp), %rsi
	movq	32(%rsp), %rbx                  # 8-byte Reload
	movq	%rbx, %rdi
	movq	%r12, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	movq	%rbx, %rax
	addq	$40, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	gpu_multiples_convolutions, .Lfunc_end1-gpu_multiples_convolutions
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z12convolKernelPfS_ii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z12convolKernelPfS_ii,@object  # @_Z12convolKernelPfS_ii
	.section	.rodata,"a",@progbits
	.globl	_Z12convolKernelPfS_ii
	.p2align	3, 0x0
_Z12convolKernelPfS_ii:
	.quad	_Z27__device_stub__convolKernelPfS_ii
	.size	_Z12convolKernelPfS_ii, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z12convolKernelPfS_ii"
	.size	.L__unnamed_1, 23

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z27__device_stub__convolKernelPfS_ii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z12convolKernelPfS_ii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z12convolKernelPfS_ii  ; -- Begin function _Z12convolKernelPfS_ii
	.globl	_Z12convolKernelPfS_ii
	.p2align	8
	.type	_Z12convolKernelPfS_ii,@function
_Z12convolKernelPfS_ii:                 ; @_Z12convolKernelPfS_ii
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x24
	s_load_b64 s[8:9], s[0:1], 0x10
	v_bfe_u32 v2, v0, 10, 10
	v_and_b32_e32 v3, 0x3ff, v0
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s2, 16
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[0:1], null, s15, s3, v[2:3]
	v_mad_u64_u32 v[1:2], null, s14, s2, v[3:4]
	v_cmp_gt_i32_e32 vcc_lo, s8, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_gt_i32_e64 s2, s9, v1
	s_and_b32 s2, s2, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_18
; %bb.1:
	s_load_b128 s[4:7], s[0:1], 0x0
	s_add_i32 s0, s8, -1
	v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, 0
	v_cmp_gt_i32_e32 vcc_lo, s0, v0
	s_and_saveexec_b32 s0, vcc_lo
	s_cbranch_execz .LBB0_7
; %bb.2:
	v_mul_lo_u32 v2, s9, v0
	s_mov_b32 s1, exec_lo
	v_mov_b32_e32 v5, 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v2, v2, s9, v1
	v_ashrrev_i32_e32 v3, 31, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v2, vcc_lo, s4, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
	global_load_b32 v4, v[2:3], off
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v4, 0, v4
	v_cmpx_lt_i32_e32 0, v1
	s_cbranch_execz .LBB0_4
; %bb.3:
	global_load_b32 v5, v[2:3], off offset:-4
	s_waitcnt vmcnt(0)
	v_dual_add_f32 v4, v4, v5 :: v_dual_mov_b32 v5, 2.0
.LBB0_4:
	s_or_b32 exec_lo, exec_lo, s1
	s_add_i32 s1, s9, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	v_cmp_gt_i32_e32 vcc_lo, s1, v1
	s_and_saveexec_b32 s1, vcc_lo
	s_cbranch_execz .LBB0_6
; %bb.5:
	global_load_b32 v2, v[2:3], off offset:4
	s_waitcnt vmcnt(0)
	v_dual_add_f32 v5, 1.0, v5 :: v_dual_add_f32 v4, v4, v2
.LBB0_6:                                ; %Flow105
	s_or_b32 exec_lo, exec_lo, s1
.LBB0_7:                                ; %Flow106
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s0
	v_cmp_lt_i32_e32 vcc_lo, 0, v1
	s_and_saveexec_b32 s1, vcc_lo
	s_cbranch_execz .LBB0_9
; %bb.8:
	v_mad_u64_u32 v[2:3], null, v0, s9, v[1:2]
	v_add_f32_e32 v5, 1.0, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v2, s0, s4, v2
	v_add_co_ci_u32_e64 v3, s0, s5, v3, s0
	global_load_b32 v2, v[2:3], off offset:-4
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v4, v4, v2
.LBB0_9:
	s_or_b32 exec_lo, exec_lo, s1
	s_add_i32 s0, s9, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_gt_i32_e64 s0, s0, v1
	s_and_saveexec_b32 s2, s0
	s_cbranch_execz .LBB0_11
; %bb.10:
	v_mad_u64_u32 v[2:3], null, v0, s9, v[1:2]
	v_add_f32_e32 v5, 1.0, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v2, s1, s4, v2
	v_add_co_ci_u32_e64 v3, s1, s5, v3, s1
	global_load_b32 v2, v[2:3], off offset:4
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v4, v4, v2
.LBB0_11:
	s_or_b32 exec_lo, exec_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s2, exec_lo
	v_cmpx_lt_i32_e32 0, v0
	s_cbranch_execz .LBB0_17
; %bb.12:
	v_dual_add_f32 v5, 1.0, v5 :: v_dual_add_nc_u32 v6, -1, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[2:3], null, v6, s9, v[1:2]
	v_ashrrev_i32_e32 v3, 31, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v2, s1, s4, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v3, s1, s5, v3, s1
	global_load_b32 v6, v[2:3], off
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v4, v4, v6
	s_and_saveexec_b32 s1, vcc_lo
	s_cbranch_execz .LBB0_14
; %bb.13:
	global_load_b32 v6, v[2:3], off offset:-4
	s_waitcnt vmcnt(0)
	v_dual_add_f32 v5, 1.0, v5 :: v_dual_add_f32 v4, v4, v6
.LBB0_14:
	s_or_b32 exec_lo, exec_lo, s1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_16
; %bb.15:
	global_load_b32 v2, v[2:3], off offset:4
	s_waitcnt vmcnt(0)
	v_dual_add_f32 v5, 1.0, v5 :: v_dual_add_f32 v4, v4, v2
.LBB0_16:                               ; %Flow
	s_or_b32 exec_lo, exec_lo, s1
.LBB0_17:                               ; %Flow104
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_or_b32 exec_lo, exec_lo, s2
	v_mad_u64_u32 v[2:3], null, v0, s9, v[1:2]
	v_ashrrev_i32_e32 v3, 31, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[2:3]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v2, vcc_lo, s4, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
	global_load_b32 v2, v[2:3], off
	v_mul_f32_e32 v3, 0.5, v5
	s_waitcnt vmcnt(0)
	v_dual_fmac_f32 v5, 0.5, v5 :: v_dual_fmac_f32 v4, v3, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f32 v2, null, v5, v5, v4
	v_div_scale_f32 v7, vcc_lo, v4, v5, v4
	v_rcp_f32_e32 v3, v2
	s_waitcnt_depctr 0xfff
	v_fma_f32 v6, -v2, v3, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v3, v6, v3
	v_mul_f32_e32 v6, v7, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v8, -v2, v6, v7
	v_fmac_f32_e32 v6, v8, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v2, -v2, v6, v7
	v_div_fmas_f32 v2, v2, v3, v6
	v_add_co_u32 v0, vcc_lo, s6, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_3)
	v_div_fixup_f32 v2, v2, v5, v4
	global_store_b32 v[0:1], v2, off
.LBB0_18:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z12convolKernelPfS_ii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 9
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z12convolKernelPfS_ii, .Lfunc_end0-_Z12convolKernelPfS_ii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 840
; NumSgprs: 18
; NumVgprs: 9
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 9
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z12convolKernelPfS_ii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z12convolKernelPfS_ii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     9
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
