#include <iostream>
#include <cuda.h>

using namespace std;

__global__ void matmul_kernel(const float* A, const float* B, float* C, unsigned int n) {

	int blocksize = blockDim.x;
	extern __shared__ float shared_arr[];
	float *As = shared_arr;
	float *Bs = (float*)&As[blocksize*blocksize];

	int bx = blockIdx.x;
	int by = blockIdx.y;
	int tx = threadIdx.x;
	int ty = threadIdx.y;
	int aBegin = by * blocksize * n;
	int aEnd = aBegin + n-1;
	int aStep = blocksize;
	int arow = aBegin/n + ty;
	int bBegin = bx * blocksize;
	int bStep = n * blocksize;
	int bcol = bBegin + tx;
	int c = n * blocksize * by + blocksize * bx;
	float Csub = 0;

	for (int a = aBegin, b = bBegin;a <= aEnd;a += aStep, b += bStep) {
		As[blocksize*ty + tx] = ((arow < n) && (a + tx <= aEnd))? A[a + n * ty + tx] : 0;
		Bs[blocksize*ty + tx] = ((bcol < n) && (a + tx <= aEnd))? B[b + n * ty + tx] : 0; 
		//Using aEnd condition for zero padding B matrix since column and row dimension of A and B respectively needs to be the same
		__syncthreads();
		for (int k = 0; k < blocksize; ++k)
			Csub += As[blocksize*ty + k] * Bs[blocksize*k + tx];
           	__syncthreads();
	}
	if((by*blocksize + ty < n) && (bx*blocksize + tx < n)) {
		C[c + n * ty + tx] = Csub;
	}
}

__host__ void matmul(const float* A, const float* B, float* C, unsigned int n, unsigned int block_dim) {
	dim3 dimBlock(block_dim, block_dim);
	dim3 dimGrid( (n + block_dim-1)/block_dim , (n + block_dim-1)/block_dim );
	size_t shared_array_size = (2*block_dim*block_dim)*sizeof(float);
	
	matmul_kernel<<<dimGrid, dimBlock, shared_array_size>>>(A, B, C, n);
	cudaDeviceSynchronize();
}

	.file	"tmpxft_00366b2c_00000000-6_matmul.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3638:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3638:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z40__device_stub__Z13matmul_kernelPKfS0_PfjPKfS0_Pfj
	.type	_Z40__device_stub__Z13matmul_kernelPKfS0_PfjPKfS0_Pfj, @function
_Z40__device_stub__Z13matmul_kernelPKfS0_PfjPKfS0_Pfj:
.LFB3660:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 4(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z13matmul_kernelPKfS0_Pfj(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L2:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3660:
	.size	_Z40__device_stub__Z13matmul_kernelPKfS0_PfjPKfS0_Pfj, .-_Z40__device_stub__Z13matmul_kernelPKfS0_PfjPKfS0_Pfj
	.globl	_Z13matmul_kernelPKfS0_Pfj
	.type	_Z13matmul_kernelPKfS0_Pfj, @function
_Z13matmul_kernelPKfS0_Pfj:
.LFB3661:
	.cfi_startproc
	endbr64
	jmp	_Z40__device_stub__Z13matmul_kernelPKfS0_PfjPKfS0_Pfj
	.cfi_endproc
.LFE3661:
	.size	_Z13matmul_kernelPKfS0_Pfj, .-_Z13matmul_kernelPKfS0_Pfj
	.globl	_Z6matmulPKfS0_Pfjj
	.type	_Z6matmulPKfS0_Pfjj, @function
_Z6matmulPKfS0_Pfjj:
.LFB3635:
	.cfi_startproc
	endbr64
	pushq	%r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	leal	-1(%rcx,%r8), %eax
	movl	%ecx, %r13d
	xorl	%r9d, %r9d
	pushq	%r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	movq	%rdx, %r12
	xorl	%edx, %edx
	movl	$1, %ecx
	divl	%r8d
	pushq	%rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	subq	$40, %rsp
	.cfi_def_cfa_offset 80
	movq	%rdi, %rbx
	movq	%rsi, %rbp
	movl	$1, %esi
	movl	%r8d, 8(%rsp)
	movl	%r8d, 12(%rsp)
	imull	%r8d, %r8d
	movq	8(%rsp), %rdx
	addl	%r8d, %r8d
	leaq	0(,%r8,4), %r8
	movl	%eax, 20(%rsp)
	movl	%eax, 24(%rsp)
	movq	20(%rsp), %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L9
	movl	%r13d, %ecx
	movq	%r12, %rdx
	movq	%rbp, %rsi
	movq	%rbx, %rdi
	call	_Z40__device_stub__Z13matmul_kernelPKfS0_PfjPKfS0_Pfj
.L9:
	addq	$40, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	cudaDeviceSynchronize@PLT
	.cfi_endproc
.LFE3635:
	.size	_Z6matmulPKfS0_Pfjj, .-_Z6matmulPKfS0_Pfjj
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z13matmul_kernelPKfS0_Pfj"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3663:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z13matmul_kernelPKfS0_Pfj(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3663:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <iostream>
#include <hip/hip_runtime.h>

using namespace std;

__global__ void matmul_kernel(const float* A, const float* B, float* C, unsigned int n) {

	int blocksize = blockDim.x;
	extern __shared__ float shared_arr[];
	float *As = shared_arr;
	float *Bs = (float*)&As[blocksize*blocksize];

	int bx = blockIdx.x;
	int by = blockIdx.y;
	int tx = threadIdx.x;
	int ty = threadIdx.y;
	int aBegin = by * blocksize * n;
	int aEnd = aBegin + n-1;
	int aStep = blocksize;
	int arow = aBegin/n + ty;
	int bBegin = bx * blocksize;
	int bStep = n * blocksize;
	int bcol = bBegin + tx;
	int c = n * blocksize * by + blocksize * bx;
	float Csub = 0;

	for (int a = aBegin, b = bBegin;a <= aEnd;a += aStep, b += bStep) {
		As[blocksize*ty + tx] = ((arow < n) && (a + tx <= aEnd))? A[a + n * ty + tx] : 0;
		Bs[blocksize*ty + tx] = ((bcol < n) && (a + tx <= aEnd))? B[b + n * ty + tx] : 0; 
		//Using aEnd condition for zero padding B matrix since column and row dimension of A and B respectively needs to be the same
		__syncthreads();
		for (int k = 0; k < blocksize; ++k)
			Csub += As[blocksize*ty + k] * Bs[blocksize*k + tx];
           	__syncthreads();
	}
	if((by*blocksize + ty < n) && (bx*blocksize + tx < n)) {
		C[c + n * ty + tx] = Csub;
	}
}

__host__ void matmul(const float* A, const float* B, float* C, unsigned int n, unsigned int block_dim) {
	dim3 dimBlock(block_dim, block_dim);
	dim3 dimGrid( (n + block_dim-1)/block_dim , (n + block_dim-1)/block_dim );
	size_t shared_array_size = (2*block_dim*block_dim)*sizeof(float);
	
	matmul_kernel<<<dimGrid, dimBlock, shared_array_size>>>(A, B, C, n);
	hipDeviceSynchronize();
}

	.text
	.file	"matmul.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z28__device_stub__matmul_kernelPKfS0_Pfj # -- Begin function _Z28__device_stub__matmul_kernelPKfS0_Pfj
	.type	_Z28__device_stub__matmul_kernelPKfS0_Pfj,@function
_Z28__device_stub__matmul_kernelPKfS0_Pfj: # @_Z28__device_stub__matmul_kernelPKfS0_Pfj
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	4(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z13matmul_kernelPKfS0_Pfj, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z28__device_stub__matmul_kernelPKfS0_Pfj, .Lfunc_end0-_Z28__device_stub__matmul_kernelPKfS0_Pfj
	.cfi_endproc
                                        # -- End function
	.globl	_Z6matmulPKfS0_Pfjj             # -- Begin function _Z6matmulPKfS0_Pfjj
	.type	_Z6matmulPKfS0_Pfjj,@function
_Z6matmulPKfS0_Pfjj:                    # @_Z6matmulPKfS0_Pfjj
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r12
	.cfi_def_cfa_offset 32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	pushq	%rax
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -40
	.cfi_offset %r12, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
                                        # kill: def $r8d killed $r8d def $r8
	movl	%ecx, %ebx
	movq	%rdx, %r14
	movq	%rsi, %r15
	movq	%rdi, %r12
	movl	%r8d, %eax
	movq	%rax, %rcx
	shlq	$32, %rcx
	orq	%rax, %rcx
	leal	(%rbx,%r8), %eax
	decl	%eax
	xorl	%edx, %edx
	divl	%r8d
                                        # kill: def $eax killed $eax def $rax
	movq	%rax, %rdi
	shlq	$32, %rdi
	orq	%rax, %rdi
	imull	%r8d, %r8d
	addl	%r8d, %r8d
	shlq	$2, %r8
	movl	$1, %esi
	movq	%rcx, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_2
# %bb.1:
	movq	%r12, %rdi
	movq	%r15, %rsi
	movq	%r14, %rdx
	movl	%ebx, %ecx
	callq	_Z28__device_stub__matmul_kernelPKfS0_Pfj
.LBB1_2:
	addq	$8, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	hipDeviceSynchronize            # TAILCALL
.Lfunc_end1:
	.size	_Z6matmulPKfS0_Pfjj, .Lfunc_end1-_Z6matmulPKfS0_Pfjj
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z13matmul_kernelPKfS0_Pfj, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z13matmul_kernelPKfS0_Pfj,@object # @_Z13matmul_kernelPKfS0_Pfj
	.section	.rodata,"a",@progbits
	.globl	_Z13matmul_kernelPKfS0_Pfj
	.p2align	3, 0x0
_Z13matmul_kernelPKfS0_Pfj:
	.quad	_Z28__device_stub__matmul_kernelPKfS0_Pfj
	.size	_Z13matmul_kernelPKfS0_Pfj, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z13matmul_kernelPKfS0_Pfj"
	.size	.L__unnamed_1, 27

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z28__device_stub__matmul_kernelPKfS0_Pfj
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z13matmul_kernelPKfS0_Pfj
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z13matmul_kernelPKfS0_Pfj ; -- Begin function _Z13matmul_kernelPKfS0_Pfj
	.globl	_Z13matmul_kernelPKfS0_Pfj
	.p2align	8
	.type	_Z13matmul_kernelPKfS0_Pfj,@function
_Z13matmul_kernelPKfS0_Pfj:             ; @_Z13matmul_kernelPKfS0_Pfj
; %bb.0:
	s_clause 0x3
	s_load_b32 s2, s[0:1], 0x2c
	s_load_b32 s3, s[0:1], 0x18
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b64 s[8:9], s[0:1], 0x10
	v_dual_mov_b32 v6, 0 :: v_dual_and_b32 v1, 0x3ff, v0
	v_bfe_u32 v0, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_and_b32 s12, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mul_i32 s10, s15, s12
	s_mul_i32 s14, s14, s12
	s_mul_i32 s13, s10, s3
	v_add_nc_u32_e32 v5, s14, v1
	s_add_i32 s16, s3, s13
	s_mul_i32 s11, s12, s3
	s_add_i32 s16, s16, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_gt_i32 s13, s16
	s_cbranch_scc1 .LBB0_10
; %bb.1:                                ; %.lr.ph106
	v_cvt_f32_u32_e32 v2, s3
	s_sub_i32 s1, 0, s3
	s_mul_i32 s2, s12, s12
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v2, v2
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v2, 0x4f7ffffe, v2
	v_cvt_u32_f32_e32 v2, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_readfirstlane_b32 s0, v2
	v_mad_u64_u32 v[2:3], null, v0, s3, v[1:2]
	v_mul_u32_u24_e32 v3, s12, v0
	s_mul_i32 s1, s1, s0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_mul_hi_u32 s1, s0, s1
	v_add_lshl_u32 v6, v3, v1, 2
	s_add_i32 s1, s0, s1
	v_lshl_add_u32 v7, v3, 2, 0
	s_mul_hi_u32 s1, s13, s1
	v_cmp_le_u32_e64 s0, s3, v5
	s_mul_i32 s17, s1, s3
	s_add_i32 s18, s1, 1
	s_sub_i32 s17, s13, s17
	v_add_nc_u32_e32 v8, 0, v6
	s_sub_i32 s19, s17, s3
	s_cmp_ge_u32 s17, s3
	s_cselect_b32 s1, s18, s1
	s_cselect_b32 s17, s19, s17
	s_add_i32 s18, s1, 1
	s_cmp_ge_u32 s17, s3
	s_cselect_b32 s1, s18, s1
	s_lshl_b32 s2, s2, 2
	v_add_nc_u32_e32 v3, s1, v0
	s_add_i32 s1, s2, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_mov_b32 v4, 0 :: v_dual_add_nc_u32 v9, s1, v6
	v_lshl_add_u32 v10, v1, 2, s1
	v_cmp_le_u32_e64 s1, s3, v3
	v_mov_b32_e32 v6, 0
	s_cmp_lg_u32 s12, 0
	s_cselect_b32 s17, -1, 0
	s_lshl_b32 s18, s12, 2
.LBB0_2:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_8 Depth 2
	v_add_nc_u32_e32 v3, s13, v1
	v_mov_b32_e32 v11, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_lt_i32_e32 vcc_lo, s16, v3
	s_or_b32 s2, s1, vcc_lo
	s_xor_b32 s2, s2, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s19, s2
	s_cbranch_execz .LBB0_4
; %bb.3:                                ;   in Loop: Header=BB0_2 Depth=1
	v_add_nc_u32_e32 v3, s13, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[11:12], 2, v[3:4]
	v_add_co_u32 v11, s2, s4, v11
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v12, s2, s5, v12, s2
	global_load_b32 v11, v[11:12], off
.LBB0_4:                                ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s19
	v_mov_b32_e32 v3, 0
	s_or_b32 s2, s0, vcc_lo
	s_waitcnt vmcnt(0)
	ds_store_b32 v8, v11
	s_xor_b32 s19, s2, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s2, s19
	s_cbranch_execz .LBB0_6
; %bb.5:                                ;   in Loop: Header=BB0_2 Depth=1
	v_add_nc_u32_e32 v3, s14, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[11:12], 2, v[3:4]
	v_add_co_u32 v11, vcc_lo, s6, v11
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v12, vcc_lo, s7, v12, vcc_lo
	global_load_b32 v3, v[11:12], off
.LBB0_6:                                ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s17
	s_waitcnt vmcnt(0)
	ds_store_b32 v9, v3
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_vccnz .LBB0_9
; %bb.7:                                ; %.lr.ph.preheader
                                        ;   in Loop: Header=BB0_2 Depth=1
	v_mov_b32_e32 v3, v10
	s_mov_b32 s2, 0
.LBB0_8:                                ; %.lr.ph
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	v_add_nc_u32_e32 v11, s2, v7
	s_add_i32 s2, s2, 4
	ds_load_b32 v12, v3
	ds_load_b32 v11, v11
	v_add_nc_u32_e32 v3, s18, v3
	s_cmp_eq_u32 s18, s2
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v6, v11, v12
	s_cbranch_scc0 .LBB0_8
.LBB0_9:                                ; %._crit_edge
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_add_i32 s13, s13, s12
	s_add_i32 s14, s14, s11
	s_cmp_gt_i32 s13, s16
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc0 .LBB0_2
.LBB0_10:                               ; %Flow124
	v_add_nc_u32_e32 v1, s10, v0
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_max_u32_e32 v1, v1, v5
	v_cmpx_gt_u32_e64 s3, v1
	s_cbranch_execz .LBB0_12
; %bb.11:
	v_mul_lo_u32 v0, v0, s3
	s_mul_i32 s11, s11, s15
	v_mov_b32_e32 v1, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v0, v5, v0, s11
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s8, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s9, v1, vcc_lo
	global_store_b32 v[0:1], v6, off
.LBB0_12:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z13matmul_kernelPKfS0_Pfj
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 13
		.amdhsa_next_free_sgpr 20
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z13matmul_kernelPKfS0_Pfj, .Lfunc_end0-_Z13matmul_kernelPKfS0_Pfj
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 700
; NumSgprs: 22
; NumVgprs: 13
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 22
; NumVGPRsForWavesPerEU: 13
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         152
        .size:           4
        .value_kind:     hidden_dynamic_lds_size
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z13matmul_kernelPKfS0_Pfj
    .private_segment_fixed_size: 0
    .sgpr_count:     22
    .sgpr_spill_count: 0
    .symbol:         _Z13matmul_kernelPKfS0_Pfj.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     13
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
