#include "includes.h"

// ERROR CHECKING MACROS //////////////////////////////////////////////////////

__global__ void mteKernel(int noPaths, int nYears, int noPatches, float timeStep, float* rgr, float* brownians, float* jumpSizes, float* jumps, float* speciesParams, float *initPops, float* caps, float*mmm, int* rowIdx, int* elemsPerCol, float* pathPops, float* eps) {
// Global index for finding the thread number
int ii = blockIdx.x*blockDim.x + threadIdx.x;

// Only perform matrix multiplication sequentially for now. Later, if
// so desired, we can use dynamic parallelism because the card in the
// machine has CUDA compute capability 3.5
if (ii < noPaths) {
//extern __shared__ float s[];

// Initialise the prevailing population vector
for (int jj = 0; jj < noPatches; jj++) {
pathPops[(ii*2)*noPatches+jj] = initPops[jj];
}

float grMean = speciesParams[0];

for (int jj = 0; jj < nYears; jj++) {
// Movement and mortality. This component is very slow without
// using shared memory. As we do not know the size of the patches
// at compile time, we need to be careful how much shared memory we
// allocate. For safety, we assume that we will have less than
// 64KB worth of patch data in the mmm matrix. Using single
// precision floating point numbers, this means that we can only
// have up to 8,000 patches. As this number is extremely large, we
// set a limit outside this routine to have at most 300 patches.
for (int kk = 0; kk < noPatches; kk++) {
pathPops[(ii*2+1)*noPatches+kk] = 0.0;
}

int iterator = 0;
for (int kk = 0; kk < noPatches; kk++) {
for (int ll = 0; ll < elemsPerCol[kk]; ll++) {
pathPops[(ii*2+1)*noPatches+kk] += pathPops[(ii*2)*
noPatches+rowIdx[iterator]]*mmm[iterator];
iterator++;
}
}

// UPDATE: NEED TO IMPLEMENT SHARED MEMORY AS WELL

// DEPRECATED - TO BE DELETED AT LATER STAGE
// Load the correct slice of the mmm matrix for each
// destination patch. Use the thread index as a helper to do
// this. Wait for all information to be loaded in before
// proceeding. We need to tile the mmm matrix here to obtain
// a sufficient speed up.

//            for (int kk = 0; kk < noTiles; kk++) {
//                int currDim = tileDim;

//                if (threadIdx.x < noPatches) {
//                    // First, allocate the memory for this tile
//                    if (kk == noTiles-1) {
//                        currDim = (int)(noTiles*tileDim == noPatches) ?
//                                (int)tileDim : (int)(noPatches - kk*tileDim);
//                    }

//                    for (int ll = 0; ll < currDim; ll++) {
//                        s[ll*noPatches + threadIdx.x] = mmm[kk*noPatches*
//                                tileDim + ll*noPatches + threadIdx.x];
//                    }
//                }
//                __syncthreads();

//                // Now increment the populations for this path
//                for (int kk = 0; kk < currDim; kk++) {
//                    for (int ll = 0; ll < noPatches; ll++) {
//                        pathPops[(ii*2+1)*noPatches+kk] += pathPops[(ii*2)*
//                                noPatches+ll]*s[kk*noPatches + ll];
//                    }
//                }
//            }

//            for (int kk = 0; kk < noPatches; kk++) {
//                for (int ll = 0; ll < noPatches; ll++) {
////                    pathPops[(ii*2+1)*noPatches+kk] += pathPops[(ii*2)*
////                            noPatches+ll]*s[ll];
//                    pathPops[(ii*2+1)*noPatches+kk] += pathPops[(ii*2)*
//                            noPatches+ll]*mmm[kk*noPatches+ll];
//                }
//            }

//            matrixMultiplicationKernel<<<noBlocks,noThreadsPerBlock>>>(pathPops
//                    + (ii*2)*noPatches, mmm, pathPops + (ii*2+1)*noPatches, 1,
//                    noPatches, noPatches);
//            cudaDeviceSynchronize();
//            __syncthreads();

// Natural birth and death

// Adjust the global growth rate mean for this species at this
// time step for this path.
float jump = (jumps[ii*nYears + jj] < speciesParams[6]) ? 1.0f :
0.0f;
float meanP = speciesParams[1];
float reversion = speciesParams[4];

float brownian = brownians[ii*nYears + jj]*speciesParams[2];
float jumpSize = jumpSizes[ii*nYears + jj]*pow(speciesParams[5],2)
- pow(speciesParams[5],2)/2;

grMean = grMean + reversion*(meanP - grMean)*timeStep + grMean
*brownian + (exp(jumpSize) - 1)*grMean*jump;

for (int kk = 0; kk < noPatches; kk++) {
float gr = speciesParams[7]*rgr[ii*(nYears*noPatches) + jj*
noPatches + kk]*grMean + grMean;
pathPops[(ii*2)*noPatches+kk] = pathPops[(ii*2+1)*noPatches+kk]
*(1.0f + gr*(caps[kk]-pathPops[(ii*2+1)*noPatches+kk])/
caps[kk]);
}
}

eps[ii] = 0.0f;
for (int jj = 0; jj < noPatches; jj++) {
eps[ii] += pathPops[(ii*2+1)*noPatches+jj];
}
}
}
	.file	"tmpxft_002a9478_00000000-6_mteKernel.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2010:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2010:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z55__device_stub__Z9mteKerneliiifPfS_S_S_S_S_S_S_PiS0_S_S_iiifPfS_S_S_S_S_S_S_PiS0_S_S_
	.type	_Z55__device_stub__Z9mteKerneliiifPfS_S_S_S_S_S_S_PiS0_S_S_iiifPfS_S_S_S_S_S_S_PiS0_S_S_, @function
_Z55__device_stub__Z9mteKerneliiifPfS_S_S_S_S_S_S_PiS0_S_S_iiifPfS_S_S_S_S_S_S_PiS0_S_S_:
.LFB2032:
	.cfi_startproc
	endbr64
	subq	$328, %rsp
	.cfi_def_cfa_offset 336
	movq	336(%rsp), %rax
	movl	%edi, 108(%rsp)
	leaq	136(%rsp), %rdi
	movl	%esi, 104(%rsp)
	leaq	148(%rsp), %rsi
	movq	%rax, 64(%rsp)
	movq	344(%rsp), %rax
	movl	%edx, 100(%rsp)
	leaq	120(%rsp), %rdx
	movq	%rax, 56(%rsp)
	movq	352(%rsp), %rax
	movq	%rcx, 88(%rsp)
	leaq	128(%rsp), %rcx
	movq	%rax, 48(%rsp)
	movq	360(%rsp), %rax
	movq	%r8, 80(%rsp)
	movq	%rax, 40(%rsp)
	movq	368(%rsp), %rax
	movq	%r9, 72(%rsp)
	movq	%rax, 32(%rsp)
	movq	376(%rsp), %rax
	movss	%xmm0, 96(%rsp)
	movq	%rax, 24(%rsp)
	movq	384(%rsp), %rax
	movq	%rax, 16(%rsp)
	movq	392(%rsp), %rax
	movq	%rax, 8(%rsp)
	movq	400(%rsp), %rax
	movq	%rax, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 312(%rsp)
	xorl	%eax, %eax
	leaq	108(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	104(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	100(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	96(%rsp), %rax
	movq	%rax, 208(%rsp)
	leaq	88(%rsp), %rax
	movq	%rax, 216(%rsp)
	leaq	80(%rsp), %rax
	movq	%rax, 224(%rsp)
	leaq	72(%rsp), %rax
	movq	%rax, 232(%rsp)
	leaq	64(%rsp), %rax
	movq	%rax, 240(%rsp)
	leaq	56(%rsp), %rax
	movq	%rax, 248(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 256(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 264(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 272(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 280(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 288(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 296(%rsp)
	movq	%rsp, %rax
	movq	%rax, 304(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 136(%rsp)
	movl	$1, 144(%rsp)
	movq	%rax, 148(%rsp)
	movl	$1, 156(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	128(%rsp)
	.cfi_def_cfa_offset 344
	leaq	_Z9mteKerneliiifPfS_S_S_S_S_S_S_PiS0_S_S_(%rip), %rdi
	pushq	128(%rsp)
	.cfi_def_cfa_offset 352
	movq	164(%rsp), %rcx
	movl	172(%rsp), %r8d
	movq	152(%rsp), %rsi
	movl	160(%rsp), %edx
	leaq	200(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 344
	popq	%rdx
	.cfi_def_cfa_offset 336
.L2:
	movq	312(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$328, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2032:
	.size	_Z55__device_stub__Z9mteKerneliiifPfS_S_S_S_S_S_S_PiS0_S_S_iiifPfS_S_S_S_S_S_S_PiS0_S_S_, .-_Z55__device_stub__Z9mteKerneliiifPfS_S_S_S_S_S_S_PiS0_S_S_iiifPfS_S_S_S_S_S_S_PiS0_S_S_
	.globl	_Z9mteKerneliiifPfS_S_S_S_S_S_S_PiS0_S_S_
	.type	_Z9mteKerneliiifPfS_S_S_S_S_S_S_PiS0_S_S_, @function
_Z9mteKerneliiifPfS_S_S_S_S_S_S_PiS0_S_S_:
.LFB2033:
	.cfi_startproc
	endbr64
	jmp	_Z55__device_stub__Z9mteKerneliiifPfS_S_S_S_S_S_S_PiS0_S_S_iiifPfS_S_S_S_S_S_S_PiS0_S_S_
	.cfi_endproc
.LFE2033:
	.size	_Z9mteKerneliiifPfS_S_S_S_S_S_S_PiS0_S_S_, .-_Z9mteKerneliiifPfS_S_S_S_S_S_S_PiS0_S_S_
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z9mteKerneliiifPfS_S_S_S_S_S_S_PiS0_S_S_"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2035:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z9mteKerneliiifPfS_S_S_S_S_S_S_PiS0_S_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2035:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include "includes.h"

// ERROR CHECKING MACROS //////////////////////////////////////////////////////

__global__ void mteKernel(int noPaths, int nYears, int noPatches, float timeStep, float* rgr, float* brownians, float* jumpSizes, float* jumps, float* speciesParams, float *initPops, float* caps, float*mmm, int* rowIdx, int* elemsPerCol, float* pathPops, float* eps) {
// Global index for finding the thread number
int ii = blockIdx.x*blockDim.x + threadIdx.x;

// Only perform matrix multiplication sequentially for now. Later, if
// so desired, we can use dynamic parallelism because the card in the
// machine has CUDA compute capability 3.5
if (ii < noPaths) {
//extern __shared__ float s[];

// Initialise the prevailing population vector
for (int jj = 0; jj < noPatches; jj++) {
pathPops[(ii*2)*noPatches+jj] = initPops[jj];
}

float grMean = speciesParams[0];

for (int jj = 0; jj < nYears; jj++) {
// Movement and mortality. This component is very slow without
// using shared memory. As we do not know the size of the patches
// at compile time, we need to be careful how much shared memory we
// allocate. For safety, we assume that we will have less than
// 64KB worth of patch data in the mmm matrix. Using single
// precision floating point numbers, this means that we can only
// have up to 8,000 patches. As this number is extremely large, we
// set a limit outside this routine to have at most 300 patches.
for (int kk = 0; kk < noPatches; kk++) {
pathPops[(ii*2+1)*noPatches+kk] = 0.0;
}

int iterator = 0;
for (int kk = 0; kk < noPatches; kk++) {
for (int ll = 0; ll < elemsPerCol[kk]; ll++) {
pathPops[(ii*2+1)*noPatches+kk] += pathPops[(ii*2)*
noPatches+rowIdx[iterator]]*mmm[iterator];
iterator++;
}
}

// UPDATE: NEED TO IMPLEMENT SHARED MEMORY AS WELL

// DEPRECATED - TO BE DELETED AT LATER STAGE
// Load the correct slice of the mmm matrix for each
// destination patch. Use the thread index as a helper to do
// this. Wait for all information to be loaded in before
// proceeding. We need to tile the mmm matrix here to obtain
// a sufficient speed up.

//            for (int kk = 0; kk < noTiles; kk++) {
//                int currDim = tileDim;

//                if (threadIdx.x < noPatches) {
//                    // First, allocate the memory for this tile
//                    if (kk == noTiles-1) {
//                        currDim = (int)(noTiles*tileDim == noPatches) ?
//                                (int)tileDim : (int)(noPatches - kk*tileDim);
//                    }

//                    for (int ll = 0; ll < currDim; ll++) {
//                        s[ll*noPatches + threadIdx.x] = mmm[kk*noPatches*
//                                tileDim + ll*noPatches + threadIdx.x];
//                    }
//                }
//                __syncthreads();

//                // Now increment the populations for this path
//                for (int kk = 0; kk < currDim; kk++) {
//                    for (int ll = 0; ll < noPatches; ll++) {
//                        pathPops[(ii*2+1)*noPatches+kk] += pathPops[(ii*2)*
//                                noPatches+ll]*s[kk*noPatches + ll];
//                    }
//                }
//            }

//            for (int kk = 0; kk < noPatches; kk++) {
//                for (int ll = 0; ll < noPatches; ll++) {
////                    pathPops[(ii*2+1)*noPatches+kk] += pathPops[(ii*2)*
////                            noPatches+ll]*s[ll];
//                    pathPops[(ii*2+1)*noPatches+kk] += pathPops[(ii*2)*
//                            noPatches+ll]*mmm[kk*noPatches+ll];
//                }
//            }

//            matrixMultiplicationKernel<<<noBlocks,noThreadsPerBlock>>>(pathPops
//                    + (ii*2)*noPatches, mmm, pathPops + (ii*2+1)*noPatches, 1,
//                    noPatches, noPatches);
//            cudaDeviceSynchronize();
//            __syncthreads();

// Natural birth and death

// Adjust the global growth rate mean for this species at this
// time step for this path.
float jump = (jumps[ii*nYears + jj] < speciesParams[6]) ? 1.0f :
0.0f;
float meanP = speciesParams[1];
float reversion = speciesParams[4];

float brownian = brownians[ii*nYears + jj]*speciesParams[2];
float jumpSize = jumpSizes[ii*nYears + jj]*pow(speciesParams[5],2)
- pow(speciesParams[5],2)/2;

grMean = grMean + reversion*(meanP - grMean)*timeStep + grMean
*brownian + (exp(jumpSize) - 1)*grMean*jump;

for (int kk = 0; kk < noPatches; kk++) {
float gr = speciesParams[7]*rgr[ii*(nYears*noPatches) + jj*
noPatches + kk]*grMean + grMean;
pathPops[(ii*2)*noPatches+kk] = pathPops[(ii*2+1)*noPatches+kk]
*(1.0f + gr*(caps[kk]-pathPops[(ii*2+1)*noPatches+kk])/
caps[kk]);
}
}

eps[ii] = 0.0f;
for (int jj = 0; jj < noPatches; jj++) {
eps[ii] += pathPops[(ii*2+1)*noPatches+jj];
}
}
}
	.text
	.file	"mteKernel.hip"
	.globl	_Z24__device_stub__mteKerneliiifPfS_S_S_S_S_S_S_PiS0_S_S_ # -- Begin function _Z24__device_stub__mteKerneliiifPfS_S_S_S_S_S_S_PiS0_S_S_
	.type	_Z24__device_stub__mteKerneliiifPfS_S_S_S_S_S_S_PiS0_S_S_,@function
_Z24__device_stub__mteKerneliiifPfS_S_S_S_S_S_S_PiS0_S_S_: # @_Z24__device_stub__mteKerneliiifPfS_S_S_S_S_S_S_PiS0_S_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$224, %rsp
	.cfi_def_cfa_offset 272
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	20(%rsp), %rax
	movl	%edi, (%rax)
	leaq	16(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movss	%xmm0, (%rdx)
	leaq	56(%rsp), %r10
	movq	%rcx, (%r10)
	leaq	48(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	40(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%r10, 32(%rbx)
	movq	%rcx, 40(%rbx)
	movq	%r8, 48(%rbx)
	leaq	272(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	280(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	288(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	296(%rsp), %rax
	movq	%rax, 80(%rbx)
	leaq	304(%rsp), %rax
	movq	%rax, 88(%rbx)
	leaq	312(%rsp), %rax
	movq	%rax, 96(%rbx)
	leaq	320(%rsp), %rax
	movq	%rax, 104(%rbx)
	leaq	328(%rsp), %rax
	movq	%rax, 112(%rbx)
	leaq	336(%rsp), %rax
	movq	%rax, 120(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z9mteKerneliiifPfS_S_S_S_S_S_S_PiS0_S_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$240, %rsp
	.cfi_adjust_cfa_offset -240
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z24__device_stub__mteKerneliiifPfS_S_S_S_S_S_S_PiS0_S_S_, .Lfunc_end0-_Z24__device_stub__mteKerneliiifPfS_S_S_S_S_S_S_PiS0_S_S_
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z9mteKerneliiifPfS_S_S_S_S_S_S_PiS0_S_S_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z9mteKerneliiifPfS_S_S_S_S_S_S_PiS0_S_S_,@object # @_Z9mteKerneliiifPfS_S_S_S_S_S_S_PiS0_S_S_
	.section	.rodata,"a",@progbits
	.globl	_Z9mteKerneliiifPfS_S_S_S_S_S_S_PiS0_S_S_
	.p2align	3, 0x0
_Z9mteKerneliiifPfS_S_S_S_S_S_S_PiS0_S_S_:
	.quad	_Z24__device_stub__mteKerneliiifPfS_S_S_S_S_S_S_PiS0_S_S_
	.size	_Z9mteKerneliiifPfS_S_S_S_S_S_S_PiS0_S_S_, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z9mteKerneliiifPfS_S_S_S_S_S_S_PiS0_S_S_"
	.size	.L__unnamed_1, 42

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z24__device_stub__mteKerneliiifPfS_S_S_S_S_S_S_PiS0_S_S_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z9mteKerneliiifPfS_S_S_S_S_S_S_PiS0_S_S_
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z9mteKerneliiifPfS_S_S_S_S_S_S_PiS0_S_S_ ; -- Begin function _Z9mteKerneliiifPfS_S_S_S_S_S_S_PiS0_S_S_
	.globl	_Z9mteKerneliiifPfS_S_S_S_S_S_S_PiS0_S_S_
	.p2align	8
	.type	_Z9mteKerneliiifPfS_S_S_S_S_S_S_PiS0_S_S_,@function
_Z9mteKerneliiifPfS_S_S_S_S_S_S_PiS0_S_S_: ; @_Z9mteKerneliiifPfS_S_S_S_S_S_S_PiS0_S_S_
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x7c
	s_load_b128 s[28:31], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_i32_e64 s28, v1
	s_cbranch_execz .LBB0_20
; %bb.1:                                ; %.preheader135
	s_clause 0x1
	s_load_b512 s[4:19], s[0:1], 0x10
	s_load_b256 s[20:27], s[0:1], 0x50
	s_cmp_gt_i32 s30, 0
	s_cselect_b32 s28, -1, 0
	s_cmp_lt_i32 s30, 1
	s_cbranch_scc1 .LBB0_4
; %bb.2:                                ; %.lr.ph
	v_mul_lo_u32 v0, s30, v1
	s_mov_b32 s0, s30
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b32_e32 v2, 1, v0
	v_mov_b32_e32 v0, 0
	v_ashrrev_i32_e32 v3, 31, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v2, vcc_lo, s24, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s25, v3, vcc_lo
.LBB0_3:                                ; =>This Inner Loop Header: Depth=1
	global_load_b32 v4, v0, s[14:15]
	s_add_i32 s0, s0, -1
	s_add_u32 s14, s14, 4
	s_addc_u32 s15, s15, 0
	s_cmp_eq_u32 s0, 0
	s_waitcnt vmcnt(0)
	global_store_b32 v[2:3], v4, off
	v_add_co_u32 v2, vcc_lo, v2, 4
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
	s_cbranch_scc0 .LBB0_3
.LBB0_4:                                ; %._crit_edge
	v_cndmask_b32_e64 v0, 0, 1, s28
	s_cmp_lt_i32 s29, 1
	s_cbranch_scc1 .LBB0_17
; %bb.5:                                ; %.preheader134.lr.ph
	v_mov_b32_e32 v15, 0
	v_lshlrev_b32_e32 v3, 1, v1
	s_mul_i32 s0, s30, s29
	s_mov_b32 s1, 0
	v_mul_lo_u32 v17, s0, v1
	s_waitcnt lgkmcnt(0)
	global_load_b32 v16, v15, s[12:13]
	v_or_b32_e32 v2, 1, v3
	v_mul_lo_u32 v4, v3, s30
	s_mov_b32 s14, 0x3e76c4e1
	s_mov_b32 s15, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v2, v2, s30
	v_ashrrev_i32_e32 v5, 31, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[8:9], 2, v[4:5]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[6:7], 2, v[2:3]
	v_mul_lo_u32 v3, v1, s29
	v_add_co_u32 v5, vcc_lo, s24, v6
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v6, vcc_lo, s25, v7, vcc_lo
	v_add_co_u32 v7, vcc_lo, s24, v8
	v_add_co_ci_u32_e32 v8, vcc_lo, s25, v9, vcc_lo
.LBB0_6:                                ; %.preheader134
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_7 Depth 2
                                        ;     Child Loop BB0_9 Depth 2
                                        ;       Child Loop BB0_11 Depth 3
                                        ;     Child Loop BB0_15 Depth 2
	s_delay_alu instid0(VALU_DEP_3)
	v_dual_mov_b32 v10, v6 :: v_dual_mov_b32 v9, v5
	s_and_not1_b32 vcc_lo, exec_lo, s28
	s_mov_b32 s0, s30
	s_cbranch_vccnz .LBB0_14
.LBB0_7:                                ; %.lr.ph138
                                        ;   Parent Loop BB0_6 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	global_store_b32 v[9:10], v15, off
	v_add_co_u32 v9, vcc_lo, v9, 4
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v10, vcc_lo
	s_add_i32 s0, s0, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s0, 0
	s_cbranch_scc0 .LBB0_7
; %bb.8:                                ; %.preheader133
                                        ;   in Loop: Header=BB0_6 Depth=1
	s_mov_b32 s2, 0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, s2
.LBB0_9:                                ; %.preheader
                                        ;   Parent Loop BB0_6 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB0_11 Depth 3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[34:35], s[0:1], 2
	s_add_u32 s34, s22, s34
	s_addc_u32 s35, s23, s35
	s_load_b32 s33, s[34:35], 0x0
	s_waitcnt lgkmcnt(0)
	s_cmp_lt_i32 s33, 1
	s_cbranch_scc1 .LBB0_13
; %bb.10:                               ; %.lr.ph141
                                        ;   in Loop: Header=BB0_9 Depth=2
	v_add_nc_u32_e32 v9, s0, v2
	s_add_i32 s34, s2, s33
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v10, 31, v9
	v_lshlrev_b64 v[9:10], 2, v[9:10]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v9, vcc_lo, s24, v9
	v_add_co_ci_u32_e32 v10, vcc_lo, s25, v10, vcc_lo
	global_load_b32 v11, v[9:10], off
.LBB0_11:                               ;   Parent Loop BB0_6 Depth=1
                                        ;     Parent Loop BB0_9 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_ashr_i32 s3, s2, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[36:37], s[2:3], 2
	s_add_u32 s38, s20, s36
	s_addc_u32 s39, s21, s37
	s_add_u32 s36, s18, s36
	s_load_b32 s3, s[38:39], 0x0
	s_addc_u32 s37, s19, s37
	s_add_i32 s33, s33, -1
	s_add_i32 s2, s2, 1
	s_cmp_eq_u32 s33, 0
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v12, s3, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v13, 31, v12
	v_lshlrev_b64 v[12:13], 2, v[12:13]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v12, vcc_lo, s24, v12
	v_add_co_ci_u32_e32 v13, vcc_lo, s25, v13, vcc_lo
	global_load_b32 v12, v[12:13], off
	global_load_b32 v13, v15, s[36:37]
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v11, v12, v13
	global_store_b32 v[9:10], v11, off
	s_cbranch_scc0 .LBB0_11
; %bb.12:                               ;   in Loop: Header=BB0_9 Depth=2
	s_mov_b32 s2, s34
.LBB0_13:                               ; %._crit_edge142
                                        ;   in Loop: Header=BB0_9 Depth=2
	s_add_i32 s0, s0, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s0, s30
	s_cbranch_scc0 .LBB0_9
.LBB0_14:                               ; %._crit_edge145
                                        ;   in Loop: Header=BB0_6 Depth=1
	s_clause 0x1
	global_load_b96 v[9:11], v15, s[12:13] offset:16
	global_load_b64 v[12:13], v15, s[12:13] offset:4
	s_mov_b64 s[2:3], s[16:17]
	s_waitcnt vmcnt(1)
	v_frexp_mant_f32_e64 v14, |v10|
	s_waitcnt vmcnt(0)
	v_sub_f32_e32 v12, v12, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_f32_e32 vcc_lo, 0x3f2aaaab, v14
	v_mul_f32_e32 v9, v9, v12
	v_cndmask_b32_e64 v18, 0, 1, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v9, s31, v9, v16
	v_ldexp_f32 v14, v14, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f32_e32 v18, 1.0, v14
	v_add_f32_e32 v20, -1.0, v14
	v_rcp_f32_e32 v22, v18
	v_add_f32_e32 v19, -1.0, v18
	s_waitcnt_depctr 0xfff
	v_dual_sub_f32 v14, v14, v19 :: v_dual_mul_f32 v23, v20, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v21, v18, v23
	v_fma_f32 v24, v23, v18, -v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v24, v23, v14
	v_add_f32_e32 v14, v21, v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v25, v20, v14 :: v_dual_add_nc_u32 v18, s15, v3
	v_sub_f32_e32 v21, v14, v21
	v_ashrrev_i32_e32 v19, 31, v18
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v20, v20, v25
	v_sub_f32_e32 v24, v21, v24
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[18:19], 2, v[18:19]
	v_sub_f32_e32 v14, v20, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v20, s0, s8, v18
	v_add_f32_e32 v14, v24, v14
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e64 v21, s0, s9, v19, s0
	v_add_f32_e32 v14, v25, v14
	global_load_b32 v24, v[20:21], off
	v_mul_f32_e32 v14, v22, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v22, v23, v14
	v_sub_f32_e32 v20, v22, v23
	v_mul_f32_e32 v23, v22, v22
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v14, v14, v20
	v_fma_f32 v25, v22, v22, -v23
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v20, v14, v14
	v_fmac_f32_e32 v25, v22, v20
	v_add_co_u32 v20, s0, s6, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v21, s0, s7, v19, s0
	v_add_f32_e32 v26, v23, v25
	v_add_co_u32 v18, s0, s10, v18
	global_load_b32 v20, v[20:21], off
	v_add_co_ci_u32_e64 v19, s0, s11, v19, s0
	v_fmaak_f32 v21, s14, v26, 0x3e91f4c4
	v_cmp_neq_f32_e64 s0, 0x7f800000, |v10|
	global_load_b32 v18, v[18:19], off
	v_sub_f32_e32 v19, v26, v23
	v_fmaak_f32 v21, v26, v21, 0x3ecccdef
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v19, v25, v19
	v_mul_f32_e32 v23, v26, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v25, v26, v21, -v23
	v_fmac_f32_e32 v25, v19, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v21, v23, v25
	v_sub_f32_e32 v23, v21, v23
	v_add_f32_e32 v27, 0x3f2aaaaa, v21
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v23, v25, v23 :: v_dual_mul_f32 v28, v22, v26
	v_add_f32_e32 v25, 0xbf2aaaaa, v27
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v23, 0x31739010, v23
	v_fma_f32 v29, v26, v22, -v28
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v21, v21, v25
	v_fmac_f32_e32 v29, v26, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f32_e32 v21, v23, v21
	v_ldexp_f32 v14, v14, 1
	v_fmac_f32_e32 v29, v19, v22
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v19, v27, v21
	v_add_f32_e32 v23, v28, v29
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v25, v27, v19
	v_mul_f32_e32 v26, v23, v19
	v_sub_f32_e32 v27, v23, v28
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v21, v21, v25
	v_fma_f32 v25, v23, v19, -v26
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v27, v29, v27
	v_fmac_f32_e32 v25, v23, v21
	v_frexp_exp_i32_f32_e32 v21, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v25, v27, v19
	v_subrev_co_ci_u32_e32 v19, vcc_lo, 0, v21, vcc_lo
	v_ldexp_f32 v21, v22, 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v22, v26, v25
	v_cvt_f32_i32_e32 v19, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v23, v21, v22
	v_dual_sub_f32 v26, v22, v26 :: v_dual_mul_f32 v27, 0x3f317218, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v21, v23, v21
	v_sub_f32_e32 v25, v25, v26
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v26, 0x3f317218, v19, -v27
	v_sub_f32_e32 v21, v22, v21
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v14, v14, v25
	v_fmac_f32_e32 v26, 0xb102e308, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v14, v14, v21 :: v_dual_add_f32 v19, v27, v26
	v_add_f32_e32 v21, v23, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v27, v19, v27
	v_dual_add_f32 v22, v19, v21 :: v_dual_sub_f32 v23, v21, v23
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v26, v26, v27
	v_sub_f32_e32 v25, v22, v19
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v14, v14, v23
	v_sub_f32_e32 v28, v22, v25
	v_sub_f32_e32 v21, v21, v25
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v23, v26, v14
	v_sub_f32_e32 v19, v19, v28
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v19, v21, v19
	v_sub_f32_e32 v21, v23, v26
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v19, v23, v19
	v_sub_f32_e32 v23, v23, v21
	v_sub_f32_e32 v14, v14, v21
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v25, v22, v19
	v_dual_sub_f32 v21, v26, v23 :: v_dual_sub_f32 v22, v25, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v14, v14, v21 :: v_dual_sub_f32 v19, v19, v22
	v_add_f32_e32 v14, v14, v19
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v19, v25, v14 :: v_dual_mul_f32 v12, v20, v13
	v_sub_f32_e32 v21, v19, v25
	v_add_f32_e32 v22, v19, v19
	v_mul_f32_e32 v23, 0, v19
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_fmac_f32 v9, v16, v12 :: v_dual_sub_f32 v14, v14, v21
	v_fma_f32 v19, v19, 2.0, -v22
	v_cmp_class_f32_e64 vcc_lo, v22, 0x204
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v23, 2.0, v14
	v_add_f32_e32 v14, v19, v23
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v19, v22, v14
	v_cndmask_b32_e32 v21, v19, v22, vcc_lo
	v_sub_f32_e32 v19, v19, v22
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_eq_f32_e32 vcc_lo, 0x42b17218, v21
	v_sub_f32_e32 v14, v14, v19
	v_cndmask_b32_e64 v23, 0, 0x37000000, vcc_lo
	v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v21|
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v25, v21, v23 :: v_dual_cndmask_b32 v14, 0, v14
	v_mul_f32_e32 v26, 0x3fb8aa3b, v25
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v25
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v14, v23, v14
	v_fma_f32 v27, 0x3fb8aa3b, v25, -v26
	v_rndne_f32_e32 v28, v26
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_fmac_f32 v27, 0x32a5705f, v25 :: v_dual_sub_f32 v26, v26, v28
	v_cvt_i32_f32_e32 v22, v28
	v_add_f32_e32 v26, v26, v27
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_exp_f32_e32 v26, v26
	s_waitcnt_depctr 0xfff
	v_ldexp_f32 v19, v26, v22
	v_cndmask_b32_e32 v19, 0, v19, vcc_lo
	v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v25
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v19, 0x7f800000, v19, vcc_lo
	v_fma_f32 v14, v19, v14, v19
	v_cmp_eq_f32_e32 vcc_lo, 0x7f800000, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v14, v14, v19, vcc_lo
	v_cmp_neq_f32_e32 vcc_lo, 0, v10
	v_cndmask_b32_e64 v14, 0x7f800000, |v14|, s0
	s_mov_b32 s0, s30
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v10, 0, v14, vcc_lo
	v_mul_f32_e32 v14, -0.5, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v14, v24, v10
	v_mul_f32_e32 v10, 0x3fb8aa3b, v14
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f32 v19, 0x3fb8aa3b, v14, -v10
	v_rndne_f32_e32 v21, v10
	v_dual_fmac_f32 v19, 0x32a5705f, v14 :: v_dual_sub_f32 v10, v10, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f32_e32 v10, v10, v19
	v_cvt_i32_f32_e32 v19, v21
	v_exp_f32_e32 v10, v10
	s_waitcnt_depctr 0xfff
	v_ldexp_f32 v10, v10, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v10, 0, v10, vcc_lo
	v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v14
	v_cndmask_b32_e32 v10, 0x7f800000, v10, vcc_lo
	s_waitcnt vmcnt(0)
	v_cmp_lt_f32_e32 vcc_lo, v18, v11
	v_dual_mov_b32 v12, v6 :: v_dual_mov_b32 v11, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_add_f32_e32 v10, -1.0, v10
	v_cndmask_b32_e64 v13, 0, 1.0, vcc_lo
	s_and_not1_b32 vcc_lo, exec_lo, s28
	v_mul_f32_e32 v10, v16, v10
	v_mov_b32_e32 v16, v9
	v_mov_b32_e32 v9, v17
	s_delay_alu instid0(VALU_DEP_2)
	v_fmac_f32_e32 v16, v13, v10
	v_dual_mov_b32 v14, v8 :: v_dual_mov_b32 v13, v7
	s_cbranch_vccnz .LBB0_16
.LBB0_15:                               ;   Parent Loop BB0_6 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(VALU_DEP_3)
	v_ashrrev_i32_e32 v10, 31, v9
	global_load_b32 v20, v15, s[12:13] offset:28
	global_load_b32 v21, v[11:12], off
	s_add_i32 s0, s0, -1
	v_lshlrev_b64 v[18:19], 2, v[9:10]
	v_add_nc_u32_e32 v9, 1, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v18, vcc_lo, s4, v18
	v_add_co_ci_u32_e32 v19, vcc_lo, s5, v19, vcc_lo
	global_load_b32 v10, v[18:19], off
	global_load_b32 v18, v15, s[2:3]
	v_add_co_u32 v11, vcc_lo, v11, 4
	v_add_co_ci_u32_e32 v12, vcc_lo, 0, v12, vcc_lo
	s_add_u32 s2, s2, 4
	s_addc_u32 s3, s3, 0
	s_cmp_eq_u32 s0, 0
	s_waitcnt vmcnt(0)
	v_dual_mul_f32 v10, v20, v10 :: v_dual_sub_f32 v19, v18, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v10, v16, v10, v16
	v_mul_f32_e32 v10, v10, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f32 v19, null, v18, v18, v10
	v_div_scale_f32 v22, vcc_lo, v10, v18, v10
	v_rcp_f32_e32 v20, v19
	s_waitcnt_depctr 0xfff
	v_fma_f32 v23, -v19, v20, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v20, v23, v20
	v_mul_f32_e32 v23, v22, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v24, -v19, v23, v22
	v_fmac_f32_e32 v23, v24, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v19, -v19, v23, v22
	v_div_fmas_f32 v19, v19, v20, v23
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f32 v10, v19, v18, v10
	v_add_f32_e32 v10, 1.0, v10
	s_delay_alu instid0(VALU_DEP_1)
	v_mul_f32_e32 v10, v21, v10
	global_store_b32 v[13:14], v10, off
	v_add_co_u32 v13, vcc_lo, v13, 4
	v_add_co_ci_u32_e32 v14, vcc_lo, 0, v14, vcc_lo
	s_cbranch_scc0 .LBB0_15
.LBB0_16:                               ; %._crit_edge149
                                        ;   in Loop: Header=BB0_6 Depth=1
	v_add_nc_u32_e32 v17, s30, v17
	s_add_i32 s15, s15, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s15, s29
	s_cbranch_scc0 .LBB0_6
.LBB0_17:                               ; %._crit_edge152
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cmp_ne_u32_e32 vcc_lo, 1, v0
	v_mov_b32_e32 v4, 0
	v_lshlrev_b64 v[2:3], 2, v[1:2]
	s_and_b32 vcc_lo, exec_lo, vcc_lo
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v2, s0, s26, v2
	v_add_co_ci_u32_e64 v3, s0, s27, v3, s0
	global_store_b32 v[2:3], v4, off
	s_cbranch_vccnz .LBB0_20
; %bb.18:                               ; %.lr.ph155
	v_lshl_or_b32 v0, v1, 1, 1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v0, v0, s30
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	v_add_co_u32 v0, vcc_lo, s24, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s25, v1, vcc_lo
.LBB0_19:                               ; =>This Inner Loop Header: Depth=1
	global_load_b32 v5, v[0:1], off
	v_add_co_u32 v0, vcc_lo, v0, 4
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
	s_add_i32 s30, s30, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u32 s30, 0
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v4, v5, v4
	global_store_b32 v[2:3], v4, off
	s_cbranch_scc1 .LBB0_19
.LBB0_20:                               ; %.loopexit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z9mteKerneliiifPfS_S_S_S_S_S_S_PiS0_S_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 368
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 30
		.amdhsa_next_free_sgpr 40
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z9mteKerneliiifPfS_S_S_S_S_S_S_PiS0_S_S_, .Lfunc_end0-_Z9mteKerneliiifPfS_S_S_S_S_S_S_PiS0_S_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 2384
; NumSgprs: 42
; NumVgprs: 30
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 5
; VGPRBlocks: 3
; NumSGPRsForWavesPerEU: 42
; NumVGPRsForWavesPerEU: 30
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     by_value
      - .offset:         4
        .size:           4
        .value_kind:     by_value
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .offset:         12
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         48
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         56
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         64
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         72
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         80
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         88
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         96
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         104
        .size:           8
        .value_kind:     global_buffer
      - .offset:         112
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         116
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         120
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         124
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         126
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         128
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         130
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         132
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         134
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         152
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         160
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         168
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         176
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 368
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z9mteKerneliiifPfS_S_S_S_S_S_S_PiS0_S_S_
    .private_segment_fixed_size: 0
    .sgpr_count:     42
    .sgpr_spill_count: 0
    .symbol:         _Z9mteKerneliiifPfS_S_S_S_S_S_S_PiS0_S_S_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     30
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
