// #CSCS CUDA Training 
//
// #Example 4.2 - dot product with atomics - generic version with custom mutex
//
// #Author: Ugo Varetto
//
// #Goal: compute the dot product of two vectors performing all the computation on the GPU 
//
// #Rationale: shows how to perform the dot product of two vectors as a parallel reduction
//             with all the computation on the GPU; last step is done through synchronized
//             access to a shared variable. Spinlock implemented through atomicCAS.              
// 
// #Solution: store scalar products in local cache and iterate over cache elements
//            performing incremental sums; perform last reduction on GPU through custom atomicAddF(float*...)
//
// #Code: 1) compute launch grid configuration
//        2) allocate data on host(cpu) and device(gpu)
//        3) initialize data directly on GPU
//        4) launch kernel
//        5) report errors 
//        6) read data back 
//        7) free memory 
//             
// #Compilation: 
//               [correct] nvcc -arch=sm_13 4_3_parallel-dot-product-atomics-portable.cu -o dot-product-atomics
//               [wrong]   nvcc -DNO_SYNC -arch=sm_13 4_3_parallel-dot-product-atomics-portable.cu -o dot-product-atomics 
//
// #Execution: ./dot-product-atomics
//
// #Note: kernel invocations ( foo<<<...>>>(...) ) are *always* asynchronous and a call to 
//        cudaThreadSynchronize() is required to wait for the end of kernel execution from
//        a host thread; in case of synchronous copy operations like cudaMemcpy(...,cudaDeviceToHost)
//        kernel execution is guaranteed to be terminated before data are copied
//
// #Note: also check cudaMemset, cudaErrorString, cudaGetLastError usage
//
// #Note: as of CUDA 3.2 it seems that kernels do not stall anymore when invoking
//        __syncthreads from within an if block dependent on the thread id;
//       #see http://forums.nvidia.com/index.php?showtopic=178284
//


//#include <cuda_runtime.h> // automatically added by nvcc
#include <vector>
#include <iostream>


typedef float real_t;

const size_t BLOCK_SIZE = 16;

// lock mutex: atomicCAS sets variable to third argument if
// variable value is equal to second argument and returns previous value.
// In this case we spin in the while loop until the mutex is set to 1 i.e.
// until its return value is != 0 and exit the loop only after the mutex has
// been acquired i.e. has been set to 1 after the mutex has been released i.e.
// set to zero.
__device__ void lock( int* mutex ) {
    while( atomicCAS( mutex, 0, 1 ) != 0 );
}

// set mutex to zero; note that we do not need to use an atomic op here;
// it is however preferred to access the same memory accessed by atomic functions
// only with atomic functions for consistency reasons: atomic transations and
// regular memory access follow different paths on the GPU; it might *appear* that
// the unlock doesn't look in sync with the lock, although the final result will be correct.
__device__ void unlock( int* mutex ) {
    atomicExch( mutex, 0 );
}

// custom implementation of atomic add for floating point variables
__device__ void atomicAddF( real_t* pv, real_t v, int* mutex ) {
    lock( mutex );
    *pv += v;
    unlock( mutex );
}

// dot product entirely executed on the GPU; last reduction step is executed by serializing
// access to the output variable through a mutex
__global__ void full_dot( const real_t* v1, const real_t* v2, real_t* out, int N, int* mutex ) {
    __shared__ real_t cache[ BLOCK_SIZE ];
    int i = blockIdx.x * blockDim.x + threadIdx.x;
    cache[ threadIdx.x ] = 0.f;
    while( i < N ) {
        cache[ threadIdx.x ] += v1[ i ] * v2[ i ];
        i += gridDim.x * blockDim.x;
    }
    __syncthreads(); // required because later on the current thread is accessing
                     // data written by another thread    
    i = BLOCK_SIZE / 2;
    while( i > 0 ) {
        if( threadIdx.x < i ) cache[ threadIdx.x ] += cache[ threadIdx.x + i ];
        __syncthreads();
        i /= 2; //not sure bitwise operations are actually faster
    }
#ifndef NO_SYNC // serialized access to shared data; 
    if( threadIdx.x == 0 ) atomicAddF( out, cache[ 0 ], mutex );
#else // no sync, what most likely happens is:
      // 1) all threads read 0
      // 2) all threads write concurrently 16 (local block dot product)
    if( threadIdx.x == 0 ) *out += cache[ 0 ];
#endif                
    
}

// cpu implementation of dot product
real_t dot( const real_t* v1, const real_t* v2, int N ) {
    real_t s = 0;
    for( int i = 0; i != N; ++i ) {
        s += v1[ i ] * v2[ i ];
    }
    return s;
}

// initialization function run on the GPU
__global__ void init_vector( real_t* v, int N ) {
    int i = blockIdx.x * blockDim.x + threadIdx.x;
    while( i < N ) {
        v[ i ] = 1.0f;//real_t( i ) / 1000000.f;
        i += gridDim.x * blockDim.x;
    } 
}


//------------------------------------------------------------------------------
int main(int argc, char** argv ) {
    
    const size_t ARRAY_SIZE = 1024;//1024 * 1024; //1Mi elements
    const int BLOCKS = 64;//512;
    const int THREADS_PER_BLOCK = BLOCK_SIZE;//256; // total threads = 512 x 256 = 128ki threads;                                   
    const size_t SIZE = ARRAY_SIZE * sizeof( real_t );
    
    // device storage
    real_t* dev_v1 = 0;  // vector 1
    real_t* dev_v2 = 0;  // vector 2
    real_t* dev_out = 0; // result
    int* dev_mutex = 0;
    cudaMalloc( &dev_v1,  SIZE );
    cudaMalloc( &dev_v2,  SIZE );
    cudaMalloc( &dev_out, sizeof( real_t ) );
    cudaMalloc( &dev_mutex, sizeof( int ) );

    // host storage
    std::vector< real_t > host_v1( ARRAY_SIZE );
    std::vector< real_t > host_v2( ARRAY_SIZE );
    real_t host_out = 0.f;

    // initialize vector 1 with kernel; much faster than using for loops on the cpu
    init_vector<<< 1024, 256  >>>( dev_v1, ARRAY_SIZE );
    cudaMemcpy( &host_v1[ 0 ], dev_v1, SIZE, cudaMemcpyDeviceToHost );
    // initialize vector 2 with kernel; much faster than using for loops on the cpu
    init_vector<<< 1024, 256  >>>( dev_v2, ARRAY_SIZE );
    cudaMemcpy( &host_v2[ 0 ], dev_v2, SIZE, cudaMemcpyDeviceToHost );
    
    // initialize result on GPU: note the use of cudaMemset, alternatives are to run a kernel
    // or copy from CPU
    cudaMemset( dev_out, 0, sizeof( real_t ) );
    cudaMemset( dev_mutex, 0, sizeof( int ) );    

    // execute kernel
    full_dot<<<BLOCKS, THREADS_PER_BLOCK>>>( dev_v1, dev_v2, dev_out, ARRAY_SIZE, dev_mutex );
    std::cout << cudaGetErrorString( cudaGetLastError() ) << std::endl;
             
    // copy output data from device(gpu) to host(cpu)
    cudaMemcpy( &host_out, dev_out, sizeof( real_t ), cudaMemcpyDeviceToHost );

    // print dot product by summing up the partially reduced vectors
    std::cout << "GPU: " << host_out << std::endl;    

    // print dot product on cpu
    std::cout << "CPU: " << dot( &host_v1[ 0 ], &host_v2[ 0 ], ARRAY_SIZE ) << std::endl;

    // free memory
    cudaFree( dev_v1 );
    cudaFree( dev_v2 );
    cudaFree( dev_out );

    return 0;
}

	.file	"tmpxft_0034f31c_00000000-6_004_2_parallel-dot-product-atomics-portable.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4005:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE4005:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z4lockPi
	.type	_Z4lockPi, @function
_Z4lockPi:
.LFB3998:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE3998:
	.size	_Z4lockPi, .-_Z4lockPi
	.globl	_Z6unlockPi
	.type	_Z6unlockPi, @function
_Z6unlockPi:
.LFB4738:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	pushq	%rax
	.cfi_def_cfa_offset 16
	call	_Z4lockPi
	.cfi_endproc
.LFE4738:
	.size	_Z6unlockPi, .-_Z6unlockPi
	.globl	_Z10atomicAddFPffPi
	.type	_Z10atomicAddFPffPi, @function
_Z10atomicAddFPffPi:
.LFB4000:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE4000:
	.size	_Z10atomicAddFPffPi, .-_Z10atomicAddFPffPi
	.globl	_Z3dotPKfS0_i
	.type	_Z3dotPKfS0_i, @function
_Z3dotPKfS0_i:
.LFB4001:
	.cfi_startproc
	endbr64
	xorl	%eax, %eax
	xorps	%xmm0, %xmm0
.L9:
	cmpl	%eax, %edx
	je	.L12
	movss	(%rdi,%rax,4), %xmm1
	mulss	(%rsi,%rax,4), %xmm1
	incq	%rax
	addss	%xmm1, %xmm0
	jmp	.L9
.L12:
	ret
	.cfi_endproc
.LFE4001:
	.size	_Z3dotPKfS0_i, .-_Z3dotPKfS0_i
	.globl	_Z36__device_stub__Z8full_dotPKfS0_PfiPiPKfS0_PfiPi
	.type	_Z36__device_stub__Z8full_dotPKfS0_PfiPiPKfS0_PfiPi, @function
_Z36__device_stub__Z8full_dotPKfS0_PfiPiPKfS0_PfiPi:
.LFB4027:
	.cfi_startproc
	endbr64
	subq	$168, %rsp
	.cfi_def_cfa_offset 176
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	48(%rsp), %rdx
	movl	%ecx, 20(%rsp)
	leaq	56(%rsp), %rcx
	movq	%r8, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 152(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 112(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 144(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L13
	pushq	56(%rsp)
	.cfi_def_cfa_offset 184
	leaq	_Z8full_dotPKfS0_PfiPi(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 192
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 184
	popq	%rdx
	.cfi_def_cfa_offset 176
.L13:
	movq	152(%rsp), %rax
	subq	%fs:40, %rax
	je	.L15
	call	__stack_chk_fail@PLT
.L15:
	addq	$168, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4027:
	.size	_Z36__device_stub__Z8full_dotPKfS0_PfiPiPKfS0_PfiPi, .-_Z36__device_stub__Z8full_dotPKfS0_PfiPiPKfS0_PfiPi
	.globl	_Z8full_dotPKfS0_PfiPi
	.type	_Z8full_dotPKfS0_PfiPi, @function
_Z8full_dotPKfS0_PfiPi:
.LFB4028:
	.cfi_startproc
	endbr64
	jmp	_Z36__device_stub__Z8full_dotPKfS0_PfiPiPKfS0_PfiPi
	.cfi_endproc
.LFE4028:
	.size	_Z8full_dotPKfS0_PfiPi, .-_Z8full_dotPKfS0_PfiPi
	.globl	_Z32__device_stub__Z11init_vectorPfiPfi
	.type	_Z32__device_stub__Z11init_vectorPfiPfi, @function
_Z32__device_stub__Z11init_vectorPfiPfi:
.LFB4029:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 8(%rsp)
	leaq	32(%rsp), %rcx
	leaq	24(%rsp), %rdx
	movl	%esi, 4(%rsp)
	leaq	40(%rsp), %rdi
	leaq	52(%rsp), %rsi
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 48(%rsp)
	movq	%rax, 88(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L18
	pushq	32(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z11init_vectorPfi(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 144
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	104(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L18:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L20
	call	__stack_chk_fail@PLT
.L20:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4029:
	.size	_Z32__device_stub__Z11init_vectorPfiPfi, .-_Z32__device_stub__Z11init_vectorPfiPfi
	.globl	_Z11init_vectorPfi
	.type	_Z11init_vectorPfi, @function
_Z11init_vectorPfi:
.LFB4030:
	.cfi_startproc
	endbr64
	jmp	_Z32__device_stub__Z11init_vectorPfiPfi
	.cfi_endproc
.LFE4030:
	.size	_Z11init_vectorPfi, .-_Z11init_vectorPfi
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC1:
	.string	"_Z11init_vectorPfi"
.LC2:
	.string	"_Z8full_dotPKfS0_PfiPi"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4032:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC1(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z11init_vectorPfi(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC2(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z8full_dotPKfS0_PfiPi(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE4032:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.text._ZNSt6vectorIfSaIfEED2Ev,"axG",@progbits,_ZNSt6vectorIfSaIfEED5Ev,comdat
	.align 2
	.weak	_ZNSt6vectorIfSaIfEED2Ev
	.type	_ZNSt6vectorIfSaIfEED2Ev, @function
_ZNSt6vectorIfSaIfEED2Ev:
.LFB4344:
	.cfi_startproc
	endbr64
	movq	(%rdi), %rax
	testq	%rax, %rax
	je	.L25
	movq	16(%rdi), %rsi
	movq	%rax, %rdi
	subq	%rax, %rsi
	jmp	_ZdlPvm@PLT
.L25:
	ret
	.cfi_endproc
.LFE4344:
	.size	_ZNSt6vectorIfSaIfEED2Ev, .-_ZNSt6vectorIfSaIfEED2Ev
	.weak	_ZNSt6vectorIfSaIfEED1Ev
	.set	_ZNSt6vectorIfSaIfEED1Ev,_ZNSt6vectorIfSaIfEED2Ev
	.section	.rodata.str1.1
.LC3:
	.string	"GPU: "
.LC4:
	.string	"CPU: "
	.section	.text.startup
	.globl	main
	.type	main, @function
main:
.LFB4002:
	.cfi_startproc
	.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
	.cfi_lsda 0x1b,.LLSDA4002
	endbr64
	pushq	%r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	xorl	%edx, %edx
	movl	$4096, %esi
	pushq	%r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	pushq	%rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	subq	$136, %rsp
	.cfi_def_cfa_offset 176
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	16(%rsp), %rdi
	movq	%rdx, 16(%rsp)
	movq	%rdx, 24(%rsp)
	movq	%rdx, 32(%rsp)
	movq	%rdx, 40(%rsp)
.LEHB0:
	call	cudaMalloc@PLT
	leaq	24(%rsp), %rdi
	movl	$4096, %esi
	call	cudaMalloc@PLT
	leaq	32(%rsp), %rdi
	movl	$4, %esi
	call	cudaMalloc@PLT
	leaq	40(%rsp), %rdi
	movl	$4, %esi
	call	cudaMalloc@PLT
	movl	$4096, %edi
	call	_Znwm@PLT
.LEHE0:
	leaq	4096(%rax), %rdx
	movq	%rax, 72(%rsp)
	movq	%rax, %rbx
	movq	%rdx, 88(%rsp)
	movl	$0x00000000, (%rax)
	xorl	%eax, %eax
.L28:
	addq	$4, %rax
	cmpq	$4096, %rax
	je	.L43
	movl	$0x00000000, (%rbx,%rax)
	jmp	.L28
.L43:
	xorl	%eax, %eax
	movl	$4096, %edi
	movq	%rdx, 80(%rsp)
	movq	%rax, 104(%rsp)
	movq	%rax, 112(%rsp)
.LEHB1:
	call	_Znwm@PLT
.LEHE1:
	leaq	4096(%rax), %rdx
	movq	%rax, 96(%rsp)
	movq	%rax, %rbp
	movq	%rdx, 112(%rsp)
	movl	$0x00000000, (%rax)
	xorl	%eax, %eax
.L30:
	addq	$4, %rax
	cmpq	$4096, %rax
	je	.L44
	movl	$0x00000000, 0(%rbp,%rax)
	jmp	.L30
.L44:
	movq	%rdx, 104(%rsp)
	movl	$4194305, %edi
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$16777217, %edx
	salq	$10, %rdi
	movl	$1, %ecx
	movl	$1, %esi
	salq	$8, %rdx
	movq	%rdi, 48(%rsp)
	leaq	96(%rsp), %r12
	movl	$0x00000000, 12(%rsp)
	movq	%rdx, 60(%rsp)
	movl	$1, 68(%rsp)
	movl	$1, 56(%rsp)
.LEHB2:
	call	__cudaPushCallConfiguration@PLT
	movq	16(%rsp), %rdi
	testl	%eax, %eax
	jne	.L32
	movl	$1024, %esi
	call	_Z32__device_stub__Z11init_vectorPfiPfi
.L32:
	movq	16(%rsp), %rsi
	movl	$2, %ecx
	movl	$4096, %edx
	movq	%rbx, %rdi
	call	cudaMemcpy@PLT
	movl	$16777217, %edx
	movl	$4194305, %edi
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	salq	$8, %rdx
	salq	$10, %rdi
	movl	$1, %ecx
	movl	$1, %esi
	movq	%rdx, 60(%rsp)
	movl	$1, 68(%rsp)
	movq	%rdi, 48(%rsp)
	movl	$1, 56(%rsp)
	call	__cudaPushCallConfiguration@PLT
	movq	24(%rsp), %rdi
	testl	%eax, %eax
	jne	.L33
	movl	$1024, %esi
	call	_Z32__device_stub__Z11init_vectorPfiPfi
.L33:
	movq	24(%rsp), %rsi
	movl	$2, %ecx
	movl	$4096, %edx
	movq	%rbp, %rdi
	call	cudaMemcpy@PLT
	movq	32(%rsp), %rdi
	movl	$4, %edx
	xorl	%esi, %esi
	call	cudaMemset@PLT
	movq	40(%rsp), %rdi
	movl	$4, %edx
	xorl	%esi, %esi
	call	cudaMemset@PLT
	movl	$268435457, %edx
	movl	$67108865, %edi
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	salq	$4, %rdx
	salq	$6, %rdi
	movl	$1, %ecx
	movl	$1, %esi
	movq	%rdx, 60(%rsp)
	movl	$1, 68(%rsp)
	movq	%rdi, 48(%rsp)
	movl	$1, 56(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L34
	movq	40(%rsp), %r8
	movq	32(%rsp), %rdx
	movl	$1024, %ecx
	movq	24(%rsp), %rsi
	movq	16(%rsp), %rdi
	call	_Z36__device_stub__Z8full_dotPKfS0_PfiPiPKfS0_PfiPi
.L34:
	call	cudaGetLastError@PLT
	movl	%eax, %edi
	call	cudaGetErrorString@PLT
	leaq	_ZSt4cout(%rip), %r13
	movq	%rax, %rsi
	movq	%r13, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%rax, %rdi
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
	movq	32(%rsp), %rsi
	leaq	12(%rsp), %rdi
	movl	$2, %ecx
	movl	$4, %edx
	call	cudaMemcpy@PLT
	leaq	.LC3(%rip), %rsi
	movq	%r13, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%rax, %rdi
	cvtss2sd	12(%rsp), %xmm0
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	movq	%rax, %rdi
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
	leaq	.LC4(%rip), %rsi
	movq	%r13, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%rax, %rcx
	movq	%rbx, %rdi
	movl	$1024, %edx
	movq	%rbp, %rsi
	call	_Z3dotPKfS0_i
	movq	%rcx, %rdi
	cvtss2sd	%xmm0, %xmm0
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	movq	%rax, %rdi
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
	movq	16(%rsp), %rdi
	call	cudaFree@PLT
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	movq	32(%rsp), %rdi
	call	cudaFree@PLT
.LEHE2:
	movq	%r12, %rdi
	call	_ZNSt6vectorIfSaIfEED1Ev
	leaq	72(%rsp), %rdi
	call	_ZNSt6vectorIfSaIfEED1Ev
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L38
	jmp	.L41
.L40:
	endbr64
	movq	%rax, %rbx
.L35:
	movq	%r12, %rdi
	call	_ZNSt6vectorIfSaIfEED1Ev
	jmp	.L36
.L39:
	endbr64
	movq	%rax, %rbx
.L36:
	leaq	72(%rsp), %rdi
	call	_ZNSt6vectorIfSaIfEED1Ev
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	jne	.L41
	movq	%rbx, %rdi
.LEHB3:
	call	_Unwind_Resume@PLT
.LEHE3:
.L41:
	call	__stack_chk_fail@PLT
.L38:
	addq	$136, %rsp
	.cfi_def_cfa_offset 40
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4002:
	.globl	__gxx_personality_v0
	.section	.gcc_except_table,"a",@progbits
.LLSDA4002:
	.byte	0xff
	.byte	0xff
	.byte	0x1
	.uleb128 .LLSDACSE4002-.LLSDACSB4002
.LLSDACSB4002:
	.uleb128 .LEHB0-.LFB4002
	.uleb128 .LEHE0-.LEHB0
	.uleb128 0
	.uleb128 0
	.uleb128 .LEHB1-.LFB4002
	.uleb128 .LEHE1-.LEHB1
	.uleb128 .L39-.LFB4002
	.uleb128 0
	.uleb128 .LEHB2-.LFB4002
	.uleb128 .LEHE2-.LEHB2
	.uleb128 .L40-.LFB4002
	.uleb128 0
	.uleb128 .LEHB3-.LFB4002
	.uleb128 .LEHE3-.LEHB3
	.uleb128 0
	.uleb128 0
.LLSDACSE4002:
	.section	.text.startup
	.size	main, .-main
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.hidden	DW.ref.__gxx_personality_v0
	.weak	DW.ref.__gxx_personality_v0
	.section	.data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
	.align 8
	.type	DW.ref.__gxx_personality_v0, @object
	.size	DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
	.quad	__gxx_personality_v0
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

// #CSCS CUDA Training 
//
// #Example 4.2 - dot product with atomics - generic version with custom mutex
//
// #Author: Ugo Varetto
//
// #Goal: compute the dot product of two vectors performing all the computation on the GPU 
//
// #Rationale: shows how to perform the dot product of two vectors as a parallel reduction
//             with all the computation on the GPU; last step is done through synchronized
//             access to a shared variable. Spinlock implemented through atomicCAS.              
// 
// #Solution: store scalar products in local cache and iterate over cache elements
//            performing incremental sums; perform last reduction on GPU through custom atomicAddF(float*...)
//
// #Code: 1) compute launch grid configuration
//        2) allocate data on host(cpu) and device(gpu)
//        3) initialize data directly on GPU
//        4) launch kernel
//        5) report errors 
//        6) read data back 
//        7) free memory 
//             
// #Compilation: 
//               [correct] nvcc -arch=sm_13 4_3_parallel-dot-product-atomics-portable.cu -o dot-product-atomics
//               [wrong]   nvcc -DNO_SYNC -arch=sm_13 4_3_parallel-dot-product-atomics-portable.cu -o dot-product-atomics 
//
// #Execution: ./dot-product-atomics
//
// #Note: kernel invocations ( foo<<<...>>>(...) ) are *always* asynchronous and a call to 
//        cudaThreadSynchronize() is required to wait for the end of kernel execution from
//        a host thread; in case of synchronous copy operations like cudaMemcpy(...,cudaDeviceToHost)
//        kernel execution is guaranteed to be terminated before data are copied
//
// #Note: also check cudaMemset, cudaErrorString, cudaGetLastError usage
//
// #Note: as of CUDA 3.2 it seems that kernels do not stall anymore when invoking
//        __syncthreads from within an if block dependent on the thread id;
//       #see http://forums.nvidia.com/index.php?showtopic=178284
//


//#include <cuda_runtime.h> // automatically added by nvcc

#include <hip/hip_runtime.h>
#include <vector>
#include <iostream>


typedef float real_t;

const size_t BLOCK_SIZE = 16;

// lock mutex: atomicCAS sets variable to third argument if
// variable value is equal to second argument and returns previous value.
// In this case we spin in the while loop until the mutex is set to 1 i.e.
// until its return value is != 0 and exit the loop only after the mutex has
// been acquired i.e. has been set to 1 after the mutex has been released i.e.
// set to zero.
__device__ void lock( int* mutex ) {
    while( atomicCAS( mutex, 0, 1 ) != 0 );
}

// set mutex to zero; note that we do not need to use an atomic op here;
// it is however preferred to access the same memory accessed by atomic functions
// only with atomic functions for consistency reasons: atomic transations and
// regular memory access follow different paths on the GPU; it might *appear* that
// the unlock doesn't look in sync with the lock, although the final result will be correct.
__device__ void unlock( int* mutex ) {
    atomicExch( mutex, 0 );
}

// custom implementation of atomic add for floating point variables
__device__ void atomicAddF( real_t* pv, real_t v, int* mutex ) {
    lock( mutex );
    *pv += v;
    unlock( mutex );
}

// dot product entirely executed on the GPU; last reduction step is executed by serializing
// access to the output variable through a mutex
__global__ void full_dot( const real_t* v1, const real_t* v2, real_t* out, int N, int* mutex ) {
    __shared__ real_t cache[ BLOCK_SIZE ];
    int i = blockIdx.x * blockDim.x + threadIdx.x;
    cache[ threadIdx.x ] = 0.f;
    while( i < N ) {
        cache[ threadIdx.x ] += v1[ i ] * v2[ i ];
        i += gridDim.x * blockDim.x;
    }
    __syncthreads(); // required because later on the current thread is accessing
                     // data written by another thread    
    i = BLOCK_SIZE / 2;
    while( i > 0 ) {
        if( threadIdx.x < i ) cache[ threadIdx.x ] += cache[ threadIdx.x + i ];
        __syncthreads();
        i /= 2; //not sure bitwise operations are actually faster
    }
#ifndef NO_SYNC // serialized access to shared data; 
    if( threadIdx.x == 0 ) atomicAddF( out, cache[ 0 ], mutex );
#else // no sync, what most likely happens is:
      // 1) all threads read 0
      // 2) all threads write concurrently 16 (local block dot product)
    if( threadIdx.x == 0 ) *out += cache[ 0 ];
#endif                
    
}

// cpu implementation of dot product
real_t dot( const real_t* v1, const real_t* v2, int N ) {
    real_t s = 0;
    for( int i = 0; i != N; ++i ) {
        s += v1[ i ] * v2[ i ];
    }
    return s;
}

// initialization function run on the GPU
__global__ void init_vector( real_t* v, int N ) {
    int i = blockIdx.x * blockDim.x + threadIdx.x;
    while( i < N ) {
        v[ i ] = 1.0f;//real_t( i ) / 1000000.f;
        i += gridDim.x * blockDim.x;
    } 
}


//------------------------------------------------------------------------------
int main(int argc, char** argv ) {
    
    const size_t ARRAY_SIZE = 1024;//1024 * 1024; //1Mi elements
    const int BLOCKS = 64;//512;
    const int THREADS_PER_BLOCK = BLOCK_SIZE;//256; // total threads = 512 x 256 = 128ki threads;                                   
    const size_t SIZE = ARRAY_SIZE * sizeof( real_t );
    
    // device storage
    real_t* dev_v1 = 0;  // vector 1
    real_t* dev_v2 = 0;  // vector 2
    real_t* dev_out = 0; // result
    int* dev_mutex = 0;
    hipMalloc( &dev_v1,  SIZE );
    hipMalloc( &dev_v2,  SIZE );
    hipMalloc( &dev_out, sizeof( real_t ) );
    hipMalloc( &dev_mutex, sizeof( int ) );

    // host storage
    std::vector< real_t > host_v1( ARRAY_SIZE );
    std::vector< real_t > host_v2( ARRAY_SIZE );
    real_t host_out = 0.f;

    // initialize vector 1 with kernel; much faster than using for loops on the cpu
    init_vector<<< 1024, 256  >>>( dev_v1, ARRAY_SIZE );
    hipMemcpy( &host_v1[ 0 ], dev_v1, SIZE, hipMemcpyDeviceToHost );
    // initialize vector 2 with kernel; much faster than using for loops on the cpu
    init_vector<<< 1024, 256  >>>( dev_v2, ARRAY_SIZE );
    hipMemcpy( &host_v2[ 0 ], dev_v2, SIZE, hipMemcpyDeviceToHost );
    
    // initialize result on GPU: note the use of cudaMemset, alternatives are to run a kernel
    // or copy from CPU
    hipMemset( dev_out, 0, sizeof( real_t ) );
    hipMemset( dev_mutex, 0, sizeof( int ) );    

    // execute kernel
    full_dot<<<BLOCKS, THREADS_PER_BLOCK>>>( dev_v1, dev_v2, dev_out, ARRAY_SIZE, dev_mutex );
    std::cout << hipGetErrorString( hipGetLastError() ) << std::endl;
             
    // copy output data from device(gpu) to host(cpu)
    hipMemcpy( &host_out, dev_out, sizeof( real_t ), hipMemcpyDeviceToHost );

    // print dot product by summing up the partially reduced vectors
    std::cout << "GPU: " << host_out << std::endl;    

    // print dot product on cpu
    std::cout << "CPU: " << dot( &host_v1[ 0 ], &host_v2[ 0 ], ARRAY_SIZE ) << std::endl;

    // free memory
    hipFree( dev_v1 );
    hipFree( dev_v2 );
    hipFree( dev_out );

    return 0;
}

	.text
	.file	"004_2_parallel-dot-product-atomics-portable.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z23__device_stub__full_dotPKfS0_PfiPi # -- Begin function _Z23__device_stub__full_dotPKfS0_PfiPi
	.type	_Z23__device_stub__full_dotPKfS0_PfiPi,@function
_Z23__device_stub__full_dotPKfS0_PfiPi: # @_Z23__device_stub__full_dotPKfS0_PfiPi
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	12(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	32(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z8full_dotPKfS0_PfiPi, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z23__device_stub__full_dotPKfS0_PfiPi, .Lfunc_end0-_Z23__device_stub__full_dotPKfS0_PfiPi
	.cfi_endproc
                                        # -- End function
	.globl	_Z3dotPKfS0_i                   # -- Begin function _Z3dotPKfS0_i
	.type	_Z3dotPKfS0_i,@function
_Z3dotPKfS0_i:                          # @_Z3dotPKfS0_i
	.cfi_startproc
# %bb.0:
	testl	%edx, %edx
	je	.LBB1_1
# %bb.3:                                # %.lr.ph.preheader
	movl	%edx, %eax
	xorps	%xmm0, %xmm0
	xorl	%ecx, %ecx
.LBB1_4:                                # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	movss	(%rdi,%rcx,4), %xmm1            # xmm1 = mem[0],zero,zero,zero
	mulss	(%rsi,%rcx,4), %xmm1
	addss	%xmm1, %xmm0
	incq	%rcx
	cmpq	%rcx, %rax
	jne	.LBB1_4
# %bb.2:                                # %._crit_edge
	retq
.LBB1_1:
	xorps	%xmm0, %xmm0
	retq
.Lfunc_end1:
	.size	_Z3dotPKfS0_i, .Lfunc_end1-_Z3dotPKfS0_i
	.cfi_endproc
                                        # -- End function
	.globl	_Z26__device_stub__init_vectorPfi # -- Begin function _Z26__device_stub__init_vectorPfi
	.type	_Z26__device_stub__init_vectorPfi,@function
_Z26__device_stub__init_vectorPfi:      # @_Z26__device_stub__init_vectorPfi
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	4(%rsp), %rcx
	movl	%esi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z11init_vectorPfi, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z26__device_stub__init_vectorPfi, .Lfunc_end2-_Z26__device_stub__init_vectorPfi
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
.Lfunc_begin0:
	.cfi_startproc
	.cfi_personality 3, __gxx_personality_v0
	.cfi_lsda 3, .Lexception0
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	subq	$48, %rsp
	.cfi_def_cfa_offset 80
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	xorl	%eax, %eax
	leaq	32(%rsp), %rdi
	movq	%rax, (%rdi)
	leaq	24(%rsp), %rbx
	movq	%rax, (%rbx)
	leaq	16(%rsp), %r14
	movq	%rax, (%r14)
	leaq	40(%rsp), %r15
	movq	%rax, (%r15)
	movl	$4096, %esi                     # imm = 0x1000
	callq	hipMalloc
	movl	$4096, %esi                     # imm = 0x1000
	movq	%rbx, %rdi
	callq	hipMalloc
	movl	$4, %esi
	movq	%r14, %rdi
	callq	hipMalloc
	movl	$4, %esi
	movq	%r15, %rdi
	callq	hipMalloc
	movl	$4096, %edi                     # imm = 0x1000
	callq	_Znwm
	movq	%rax, %rbx
	movl	$4096, %edx                     # imm = 0x1000
	movq	%rax, %rdi
	xorl	%esi, %esi
	callq	memset@PLT
.Ltmp0:
	movl	$4096, %edi                     # imm = 0x1000
	callq	_Znwm
.Ltmp1:
# %bb.1:
	movq	%rax, %r14
	movl	$4096, %edx                     # imm = 0x1000
	movq	%rax, %rdi
	xorl	%esi, %esi
	callq	memset@PLT
	movl	$0, 12(%rsp)
.Ltmp3:
	movabsq	$4294968320, %rdi               # imm = 0x100000400
	movabsq	$4294967552, %rdx               # imm = 0x100000100
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
.Ltmp4:
# %bb.2:
	testl	%eax, %eax
	jne	.LBB3_4
# %bb.3:
	movq	32(%rsp), %rdi
.Ltmp5:
	movl	$1024, %esi                     # imm = 0x400
	callq	_Z26__device_stub__init_vectorPfi
.Ltmp6:
.LBB3_4:
	movq	32(%rsp), %rsi
.Ltmp7:
	movl	$4096, %edx                     # imm = 0x1000
	movq	%rbx, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
.Ltmp8:
# %bb.5:
.Ltmp9:
	movabsq	$4294968320, %rdi               # imm = 0x100000400
	movabsq	$4294967552, %rdx               # imm = 0x100000100
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
.Ltmp10:
# %bb.6:
	testl	%eax, %eax
	jne	.LBB3_8
# %bb.7:
	movq	24(%rsp), %rdi
.Ltmp11:
	movl	$1024, %esi                     # imm = 0x400
	callq	_Z26__device_stub__init_vectorPfi
.Ltmp12:
.LBB3_8:
	movq	24(%rsp), %rsi
.Ltmp13:
	movl	$4096, %edx                     # imm = 0x1000
	movq	%r14, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
.Ltmp14:
# %bb.9:
	movq	16(%rsp), %rdi
.Ltmp15:
	movl	$4, %edx
	xorl	%esi, %esi
	callq	hipMemset
.Ltmp16:
# %bb.10:
	movq	40(%rsp), %rdi
.Ltmp17:
	movl	$4, %edx
	xorl	%esi, %esi
	callq	hipMemset
.Ltmp18:
# %bb.11:
.Ltmp19:
	movabsq	$4294967360, %rdi               # imm = 0x100000040
	movabsq	$4294967312, %rdx               # imm = 0x100000010
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
.Ltmp20:
# %bb.12:
	testl	%eax, %eax
	jne	.LBB3_14
# %bb.13:
	movq	32(%rsp), %rdi
	movq	24(%rsp), %rsi
	movq	16(%rsp), %rdx
	movq	40(%rsp), %r8
.Ltmp21:
	movl	$1024, %ecx                     # imm = 0x400
	callq	_Z23__device_stub__full_dotPKfS0_PfiPi
.Ltmp22:
.LBB3_14:
.Ltmp23:
	callq	hipGetLastError
.Ltmp24:
# %bb.15:
.Ltmp25:
	movl	%eax, %edi
	callq	hipGetErrorString
.Ltmp26:
# %bb.16:
	movq	%rax, %r15
	testq	%rax, %rax
	je	.LBB3_17
# %bb.18:
	movq	%r15, %rdi
	callq	strlen
.Ltmp27:
	movl	$_ZSt4cout, %edi
	movq	%r15, %rsi
	movq	%rax, %rdx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp28:
	jmp	.LBB3_19
.LBB3_17:
	movq	_ZSt4cout(%rip), %rax
	movq	-24(%rax), %rax
	leaq	_ZSt4cout(%rax), %rdi
	movl	32(%rdi), %esi
	orl	$1, %esi
.Ltmp29:
	callq	_ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.Ltmp30:
.LBB3_19:                               # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
	movq	_ZSt4cout(%rip), %rax
	movl	$_ZSt4cout, %edi
	addq	-24(%rax), %rdi
.Ltmp31:
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
.Ltmp32:
# %bb.20:                               # %.noexc42
.Ltmp33:
	movsbl	%al, %esi
	movl	$_ZSt4cout, %edi
	callq	_ZNSo3putEc
.Ltmp34:
# %bb.21:                               # %.noexc43
.Ltmp35:
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
.Ltmp36:
# %bb.22:                               # %_ZNSolsEPFRSoS_E.exit
	movq	16(%rsp), %rsi
.Ltmp37:
	leaq	12(%rsp), %rdi
	movl	$4, %edx
	movl	$2, %ecx
	callq	hipMemcpy
.Ltmp38:
# %bb.23:
.Ltmp39:
	movl	$_ZSt4cout, %edi
	movl	$.L.str, %esi
	movl	$5, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp40:
# %bb.24:                               # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit22
	cvtss2sd	12(%rsp), %xmm0
.Ltmp41:
	movl	$_ZSt4cout, %edi
	callq	_ZNSo9_M_insertIdEERSoT_
.Ltmp42:
# %bb.25:                               # %_ZNSolsEf.exit
	movq	%rax, %r15
	movq	(%rax), %rax
	movq	-24(%rax), %rdi
	addq	%r15, %rdi
.Ltmp43:
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
.Ltmp44:
# %bb.26:                               # %.noexc45
.Ltmp45:
	movsbl	%al, %esi
	movq	%r15, %rdi
	callq	_ZNSo3putEc
.Ltmp46:
# %bb.27:                               # %.noexc46
.Ltmp47:
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
.Ltmp48:
# %bb.28:                               # %_ZNSolsEPFRSoS_E.exit25
.Ltmp49:
	movl	$_ZSt4cout, %edi
	movl	$.L.str.1, %esi
	movl	$5, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp50:
# %bb.29:                               # %.lr.ph.i.preheader
	xorps	%xmm0, %xmm0
	xorl	%eax, %eax
.LBB3_30:                               # %.lr.ph.i
                                        # =>This Inner Loop Header: Depth=1
	movss	(%rbx,%rax,4), %xmm1            # xmm1 = mem[0],zero,zero,zero
	mulss	(%r14,%rax,4), %xmm1
	addss	%xmm1, %xmm0
	incq	%rax
	cmpq	$1024, %rax                     # imm = 0x400
	jne	.LBB3_30
# %bb.31:                               # %_Z3dotPKfS0_i.exit
	cvtss2sd	%xmm0, %xmm0
.Ltmp51:
	movl	$_ZSt4cout, %edi
	callq	_ZNSo9_M_insertIdEERSoT_
.Ltmp52:
# %bb.32:                               # %_ZNSolsEf.exit30
	movq	%rax, %r15
	movq	(%rax), %rax
	movq	-24(%rax), %rdi
	addq	%r15, %rdi
.Ltmp53:
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
.Ltmp54:
# %bb.33:                               # %.noexc49
.Ltmp55:
	movsbl	%al, %esi
	movq	%r15, %rdi
	callq	_ZNSo3putEc
.Ltmp56:
# %bb.34:                               # %.noexc50
.Ltmp57:
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
.Ltmp58:
# %bb.35:                               # %_ZNSolsEPFRSoS_E.exit32
	movq	32(%rsp), %rdi
.Ltmp59:
	callq	hipFree
.Ltmp60:
# %bb.36:
	movq	24(%rsp), %rdi
.Ltmp61:
	callq	hipFree
.Ltmp62:
# %bb.37:
	movq	16(%rsp), %rdi
.Ltmp63:
	callq	hipFree
.Ltmp64:
# %bb.38:                               # %_ZNSt6vectorIfSaIfEED2Ev.exit36
	movq	%r14, %rdi
	callq	_ZdlPv
	movq	%rbx, %rdi
	callq	_ZdlPv
	xorl	%eax, %eax
	addq	$48, %rsp
	.cfi_def_cfa_offset 32
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.LBB3_39:
	.cfi_def_cfa_offset 80
.Ltmp2:
	movq	%rax, %r15
	jmp	.LBB3_40
.LBB3_41:                               # %_ZNSt6vectorIfSaIfEED2Ev.exit
.Ltmp65:
	movq	%rax, %r15
	movq	%r14, %rdi
	callq	_ZdlPv
.LBB3_40:                               # %_ZNSt6vectorIfSaIfEED2Ev.exit38
	movq	%rbx, %rdi
	callq	_ZdlPv
	movq	%r15, %rdi
	callq	_Unwind_Resume@PLT
.Lfunc_end3:
	.size	main, .Lfunc_end3-main
	.cfi_endproc
	.section	.gcc_except_table,"a",@progbits
	.p2align	2, 0x0
GCC_except_table3:
.Lexception0:
	.byte	255                             # @LPStart Encoding = omit
	.byte	255                             # @TType Encoding = omit
	.byte	1                               # Call site Encoding = uleb128
	.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
	.uleb128 .Lfunc_begin0-.Lfunc_begin0    # >> Call Site 1 <<
	.uleb128 .Ltmp0-.Lfunc_begin0           #   Call between .Lfunc_begin0 and .Ltmp0
	.byte	0                               #     has no landing pad
	.byte	0                               #   On action: cleanup
	.uleb128 .Ltmp0-.Lfunc_begin0           # >> Call Site 2 <<
	.uleb128 .Ltmp1-.Ltmp0                  #   Call between .Ltmp0 and .Ltmp1
	.uleb128 .Ltmp2-.Lfunc_begin0           #     jumps to .Ltmp2
	.byte	0                               #   On action: cleanup
	.uleb128 .Ltmp1-.Lfunc_begin0           # >> Call Site 3 <<
	.uleb128 .Ltmp3-.Ltmp1                  #   Call between .Ltmp1 and .Ltmp3
	.byte	0                               #     has no landing pad
	.byte	0                               #   On action: cleanup
	.uleb128 .Ltmp3-.Lfunc_begin0           # >> Call Site 4 <<
	.uleb128 .Ltmp64-.Ltmp3                 #   Call between .Ltmp3 and .Ltmp64
	.uleb128 .Ltmp65-.Lfunc_begin0          #     jumps to .Ltmp65
	.byte	0                               #   On action: cleanup
	.uleb128 .Ltmp64-.Lfunc_begin0          # >> Call Site 5 <<
	.uleb128 .Lfunc_end3-.Ltmp64            #   Call between .Ltmp64 and .Lfunc_end3
	.byte	0                               #     has no landing pad
	.byte	0                               #   On action: cleanup
.Lcst_end0:
	.p2align	2, 0x0
                                        # -- End function
	.text
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB4_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB4_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z8full_dotPKfS0_PfiPi, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z11init_vectorPfi, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end4:
	.size	__hip_module_ctor, .Lfunc_end4-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB5_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB5_2:
	retq
.Lfunc_end5:
	.size	__hip_module_dtor, .Lfunc_end5-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z8full_dotPKfS0_PfiPi,@object  # @_Z8full_dotPKfS0_PfiPi
	.section	.rodata,"a",@progbits
	.globl	_Z8full_dotPKfS0_PfiPi
	.p2align	3, 0x0
_Z8full_dotPKfS0_PfiPi:
	.quad	_Z23__device_stub__full_dotPKfS0_PfiPi
	.size	_Z8full_dotPKfS0_PfiPi, 8

	.type	_Z11init_vectorPfi,@object      # @_Z11init_vectorPfi
	.globl	_Z11init_vectorPfi
	.p2align	3, 0x0
_Z11init_vectorPfi:
	.quad	_Z26__device_stub__init_vectorPfi
	.size	_Z11init_vectorPfi, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"GPU: "
	.size	.L.str, 6

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"CPU: "
	.size	.L.str.1, 6

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z8full_dotPKfS0_PfiPi"
	.size	.L__unnamed_1, 23

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z11init_vectorPfi"
	.size	.L__unnamed_2, 19

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z23__device_stub__full_dotPKfS0_PfiPi
	.addrsig_sym _Z26__device_stub__init_vectorPfi
	.addrsig_sym __gxx_personality_v0
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Unwind_Resume
	.addrsig_sym _Z8full_dotPKfS0_PfiPi
	.addrsig_sym _Z11init_vectorPfi
	.addrsig_sym _ZSt4cout
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z8full_dotPKfS0_PfiPi  ; -- Begin function _Z8full_dotPKfS0_PfiPi
	.globl	_Z8full_dotPKfS0_PfiPi
	.p2align	8
	.type	_Z8full_dotPKfS0_PfiPi,@function
_Z8full_dotPKfS0_PfiPi:                 ; @_Z8full_dotPKfS0_PfiPi
; %bb.0:
	s_clause 0x3
	s_load_b32 s11, s[0:1], 0x34
	s_load_b32 s10, s[0:1], 0x18
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b64 s[2:3], s[0:1], 0x10
	s_add_u32 s8, s0, 40
	s_addc_u32 s9, s1, 0
	v_dual_mov_b32 v4, 0 :: v_dual_lshlrev_b32 v3, 2, v0
	ds_store_b32 v3, v4
	s_waitcnt lgkmcnt(0)
	s_and_b32 s12, s11, 0xffff
	s_mov_b32 s11, exec_lo
	v_mad_u64_u32 v[1:2], null, s15, s12, v[0:1]
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e64 s10, v1
	s_cbranch_execz .LBB0_4
; %bb.1:                                ; %.lr.ph
	s_load_b32 s9, s[8:9], 0x0
	s_mov_b32 s8, 0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s9, s9, s12
.LBB0_2:                                ; =>This Inner Loop Header: Depth=1
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[5:6], 2, v[1:2]
	v_add_nc_u32_e32 v1, s9, v1
	v_add_co_u32 v7, vcc_lo, s4, v5
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v8, vcc_lo, s5, v6, vcc_lo
	v_add_co_u32 v5, vcc_lo, s6, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, s7, v6, vcc_lo
	v_cmp_le_i32_e32 vcc_lo, s10, v1
	global_load_b32 v2, v[7:8], off
	global_load_b32 v5, v[5:6], off
	s_or_b32 s8, vcc_lo, s8
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v4, v2, v5
	s_and_not1_b32 exec_lo, exec_lo, s8
	s_cbranch_execnz .LBB0_2
; %bb.3:                                ; %._crit_edge
	s_or_b32 exec_lo, exec_lo, s8
	ds_store_b32 v3, v4
.LBB0_4:                                ; %Flow30
	s_or_b32 exec_lo, exec_lo, s11
	s_mov_b32 s4, 8
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
.LBB0_5:                                ; =>This Inner Loop Header: Depth=1
	s_mov_b32 s5, exec_lo
	v_cmpx_gt_u32_e64 s4, v0
	s_cbranch_execz .LBB0_7
; %bb.6:                                ;   in Loop: Header=BB0_5 Depth=1
	v_lshl_add_u32 v1, s4, 2, v3
	ds_load_b32 v1, v1
	ds_load_b32 v2, v3
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v1, v1, v2
	ds_store_b32 v3, v1
.LBB0_7:                                ;   in Loop: Header=BB0_5 Depth=1
	s_or_b32 exec_lo, exec_lo, s5
	s_lshr_b32 s5, s4, 1
	s_cmp_gt_u32 s4, 1
	s_mov_b32 s4, s5
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB0_5
; %bb.8:
	s_mov_b32 s4, 0
	s_mov_b32 s5, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB0_12
; %bb.9:
	v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, 1
	s_load_b64 s[0:1], s[0:1], 0x20
	ds_load_b32 v2, v1
.LBB0_10:                               ; =>This Inner Loop Header: Depth=1
	s_waitcnt lgkmcnt(0)
	global_atomic_cmpswap_b32 v3, v1, v[0:1], s[0:1] glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u32_e32 vcc_lo, 0, v3
	s_or_b32 s4, vcc_lo, s4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s4
	s_cbranch_execnz .LBB0_10
; %bb.11:                               ; %_Z10atomicAddFPffPi.exit
	s_or_b32 exec_lo, exec_lo, s4
	v_mov_b32_e32 v0, 0
	global_load_b32 v1, v0, s[2:3]
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v1, v2, v1
	global_store_b32 v0, v1, s[2:3]
	global_atomic_swap_b32 v0, v0, s[0:1]
.LBB0_12:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z8full_dotPKfS0_PfiPi
		.amdhsa_group_segment_fixed_size 64
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 9
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z8full_dotPKfS0_PfiPi, .Lfunc_end0-_Z8full_dotPKfS0_PfiPi
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 464
; NumSgprs: 18
; NumVgprs: 9
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 64 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 9
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z11init_vectorPfi      ; -- Begin function _Z11init_vectorPfi
	.globl	_Z11init_vectorPfi
	.p2align	8
	.type	_Z11init_vectorPfi,@function
_Z11init_vectorPfi:                     ; @_Z11init_vectorPfi
; %bb.0:
	s_clause 0x1
	s_load_b32 s5, s[0:1], 0x1c
	s_load_b32 s4, s[0:1], 0x8
	s_add_u32 s2, s0, 16
	s_addc_u32 s3, s1, 0
	s_mov_b32 s6, exec_lo
	s_waitcnt lgkmcnt(0)
	s_and_b32 s5, s5, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s5, v[0:1]
	v_cmpx_gt_i32_e64 s4, v1
	s_cbranch_execz .LBB1_3
; %bb.1:                                ; %.lr.ph
	s_load_b32 s6, s[2:3], 0x0
	s_load_b64 s[2:3], s[0:1], 0x0
	v_mov_b32_e32 v0, 1.0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s1, s6, s5
	s_mov_b32 s5, 0
.LBB1_2:                                ; =>This Inner Loop Header: Depth=1
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[1:2]
	v_add_nc_u32_e32 v1, s1, v1
	v_cmp_le_i32_e32 vcc_lo, s4, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v2, s0, s2, v2
	v_add_co_ci_u32_e64 v3, s0, s3, v3, s0
	s_or_b32 s5, vcc_lo, s5
	global_store_b32 v[2:3], v0, off
	s_and_not1_b32 exec_lo, exec_lo, s5
	s_cbranch_execnz .LBB1_2
.LBB1_3:                                ; %._crit_edge
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z11init_vectorPfi
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 4
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z11init_vectorPfi, .Lfunc_end1-_Z11init_vectorPfi
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 176
; NumSgprs: 18
; NumVgprs: 4
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 4
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         44
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         52
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         54
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         56
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         58
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         60
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         62
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         104
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 64
    .kernarg_segment_align: 8
    .kernarg_segment_size: 296
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z8full_dotPKfS0_PfiPi
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z8full_dotPKfS0_PfiPi.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     9
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .offset:         16
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         20
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         28
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         30
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         32
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         34
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         36
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         38
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         56
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         80
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 272
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z11init_vectorPfi
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z11init_vectorPfi.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     4
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
