extern "C" {

    #define MAX_AREA_SIZE 7
    #define MEDIAN_BUFFER_SIZE (MAX_AREA_SIZE * MAX_AREA_SIZE + 1)


    __device__ void quickSort(unsigned char *arr, int left, int right) {
        int i = left, j = right;
        int tmp;
        int pivot = arr[(left + right) / 2];

        /* partition */
        while (i <= j) {
            while (arr[i] < pivot)
                i++;
            while (arr[j] > pivot)
                j--;
            if (i <= j) {
                tmp = arr[i];
                arr[i] = arr[j];
                arr[j] = tmp;
                i++;
                j--;
            }
        };

        /* recursion */
        if (left < j)
            quickSort(arr, left, j);
        if (i < right)
            quickSort(arr, i, right);
    }
    
    __global__ void adaptive_median_filter_kernel(unsigned char *imageData, unsigned char *filteredImageData, int width,int height,
        unsigned char *medianBuffer)
    {
        int x = blockIdx.x * blockDim.x + threadIdx.x;
        int y = blockIdx.y * blockDim.y + threadIdx.y;
        //int width = gridDim.x;
        //int height = gridDim.y;

        bool processed = false;

        int pixelOffset = y * width + x;

        unsigned int pixel = imageData[pixelOffset];

       
        int n = 3;

        unsigned char *median = medianBuffer + ((y * width) + x) * MEDIAN_BUFFER_SIZE;

        //thrust::device_vector<unsigned char> median(MAX_AREA_SIZE * MAX_AREA_SIZE + 1, 255);

        //std::array<unsigned char, MAX_AREA_SIZE * MAX_AREA_SIZE + 1> median;

        while (!processed) {
           
            double zMin = 255;
           
            double zMax = 0;
           
            double zMed = 0;

            
            int sDelta = (n - 1) / 2;

            int processedPixelCount = 0;

            
            for (int sx = x - sDelta; sx <= x + sDelta; sx++) {
                for (int sy = y - sDelta; sy <= y + sDelta; sy++) {
                    if (sx < 0 || sy < 0 || sx >= width || sy >= height) {
                        continue;
                    }

                    unsigned int currentPixel = imageData[sy * width + sx];

                    if (currentPixel < zMin) {
                        zMin = currentPixel;
                    }

                    if (currentPixel > zMax) {
                        zMax = currentPixel;
                    }

                    median[processedPixelCount] = currentPixel;

                    processedPixelCount++;
                }
            }

            quickSort(median, 0, processedPixelCount);

            zMed = median[processedPixelCount / 2];

            double a1 = zMed - zMin;
            double a2 = zMed - zMax;

            if (a1 > 0 && a2 < 0) {
                double b1 = pixel - zMin;
                double b2 = pixel - zMax;

                if (b1 > 0 && b2 < 0) {
                    filteredImageData[pixelOffset] = pixel;
                }
                else {
                    filteredImageData[pixelOffset] = zMed;
                }

                processed = true;
            }
            else {
                n += 2;
                if (n > 7) {
                    filteredImageData[pixelOffset] = zMed;
                    processed = true;
                }
            }
        }
    }

}
	.file	"tmpxft_0031decb_00000000-6_29-adaptive-median-filter.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2011:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2011:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	quickSort
	.type	quickSort, @function
quickSort:
.LFB2008:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2008:
	.size	quickSort, .-quickSort
	.globl	_Z55__device_stub__Z29adaptive_median_filter_kernelPhS_iiS_PhS_iiS_
	.type	_Z55__device_stub__Z29adaptive_median_filter_kernelPhS_iiS_PhS_iiS_, @function
_Z55__device_stub__Z29adaptive_median_filter_kernelPhS_iiS_PhS_iiS_:
.LFB2033:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	32(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	40(%rsp), %rcx
	movq	%r8, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L4
	pushq	40(%rsp)
	.cfi_def_cfa_offset 168
	leaq	adaptive_median_filter_kernel(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 176
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L4:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L6
	call	__stack_chk_fail@PLT
.L6:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2033:
	.size	_Z55__device_stub__Z29adaptive_median_filter_kernelPhS_iiS_PhS_iiS_, .-_Z55__device_stub__Z29adaptive_median_filter_kernelPhS_iiS_PhS_iiS_
	.globl	adaptive_median_filter_kernel
	.type	adaptive_median_filter_kernel, @function
adaptive_median_filter_kernel:
.LFB2034:
	.cfi_startproc
	endbr64
	jmp	_Z55__device_stub__Z29adaptive_median_filter_kernelPhS_iiS_PhS_iiS_
	.cfi_endproc
.LFE2034:
	.size	adaptive_median_filter_kernel, .-adaptive_median_filter_kernel
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"adaptive_median_filter_kernel"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2036:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	adaptive_median_filter_kernel(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2036:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
extern "C" {

    #define MAX_AREA_SIZE 7
    #define MEDIAN_BUFFER_SIZE (MAX_AREA_SIZE * MAX_AREA_SIZE + 1)


    __device__ void quickSort(unsigned char *arr, int left, int right) {
        int i = left, j = right;
        int tmp;
        int pivot = arr[(left + right) / 2];

        /* partition */
        while (i <= j) {
            while (arr[i] < pivot)
                i++;
            while (arr[j] > pivot)
                j--;
            if (i <= j) {
                tmp = arr[i];
                arr[i] = arr[j];
                arr[j] = tmp;
                i++;
                j--;
            }
        };

        /* recursion */
        if (left < j)
            quickSort(arr, left, j);
        if (i < right)
            quickSort(arr, i, right);
    }
    
    __global__ void adaptive_median_filter_kernel(unsigned char *imageData, unsigned char *filteredImageData, int width,int height,
        unsigned char *medianBuffer)
    {
        int x = blockIdx.x * blockDim.x + threadIdx.x;
        int y = blockIdx.y * blockDim.y + threadIdx.y;
        //int width = gridDim.x;
        //int height = gridDim.y;

        bool processed = false;

        int pixelOffset = y * width + x;

        unsigned int pixel = imageData[pixelOffset];

       
        int n = 3;

        unsigned char *median = medianBuffer + ((y * width) + x) * MEDIAN_BUFFER_SIZE;

        //thrust::device_vector<unsigned char> median(MAX_AREA_SIZE * MAX_AREA_SIZE + 1, 255);

        //std::array<unsigned char, MAX_AREA_SIZE * MAX_AREA_SIZE + 1> median;

        while (!processed) {
           
            double zMin = 255;
           
            double zMax = 0;
           
            double zMed = 0;

            
            int sDelta = (n - 1) / 2;

            int processedPixelCount = 0;

            
            for (int sx = x - sDelta; sx <= x + sDelta; sx++) {
                for (int sy = y - sDelta; sy <= y + sDelta; sy++) {
                    if (sx < 0 || sy < 0 || sx >= width || sy >= height) {
                        continue;
                    }

                    unsigned int currentPixel = imageData[sy * width + sx];

                    if (currentPixel < zMin) {
                        zMin = currentPixel;
                    }

                    if (currentPixel > zMax) {
                        zMax = currentPixel;
                    }

                    median[processedPixelCount] = currentPixel;

                    processedPixelCount++;
                }
            }

            quickSort(median, 0, processedPixelCount);

            zMed = median[processedPixelCount / 2];

            double a1 = zMed - zMin;
            double a2 = zMed - zMax;

            if (a1 > 0 && a2 < 0) {
                double b1 = pixel - zMin;
                double b2 = pixel - zMax;

                if (b1 > 0 && b2 < 0) {
                    filteredImageData[pixelOffset] = pixel;
                }
                else {
                    filteredImageData[pixelOffset] = zMed;
                }

                processed = true;
            }
            else {
                n += 2;
                if (n > 7) {
                    filteredImageData[pixelOffset] = zMed;
                    processed = true;
                }
            }
        }
    }

}
	.text
	.file	"29-adaptive-median-filter.hip"
	.globl	__device_stub__adaptive_median_filter_kernel # -- Begin function __device_stub__adaptive_median_filter_kernel
	.type	__device_stub__adaptive_median_filter_kernel,@function
__device_stub__adaptive_median_filter_kernel: # @__device_stub__adaptive_median_filter_kernel
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	4(%rsp), %rsi
	movl	%edx, (%rsi)
	movq	%rsp, %rdx
	movl	%ecx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$adaptive_median_filter_kernel, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	__device_stub__adaptive_median_filter_kernel, .Lfunc_end0-__device_stub__adaptive_median_filter_kernel
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$adaptive_median_filter_kernel, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	adaptive_median_filter_kernel,@object # @adaptive_median_filter_kernel
	.section	.rodata,"a",@progbits
	.globl	adaptive_median_filter_kernel
	.p2align	3, 0x0
adaptive_median_filter_kernel:
	.quad	__device_stub__adaptive_median_filter_kernel
	.size	adaptive_median_filter_kernel, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"adaptive_median_filter_kernel"
	.size	.L__unnamed_1, 30

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __device_stub__adaptive_median_filter_kernel
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym adaptive_median_filter_kernel
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.p2align	2                               ; -- Begin function quickSort
	.type	quickSort,@function
quickSort:                              ; @quickSort
; %bb.0:
	s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	s_mov_b32 s0, s33
	s_mov_b32 s33, s32
	s_or_saveexec_b32 s1, -1
	scratch_store_b32 off, v46, s33 offset:24 ; 4-byte Folded Spill
	s_mov_b32 exec_lo, s1
	v_writelane_b32 v46, s0, 4
	s_add_i32 s32, s32, 32
	s_clause 0x5
	scratch_store_b32 off, v40, s33 offset:20
	; meta instruction
	scratch_store_b32 off, v41, s33 offset:16
	; meta instruction
	scratch_store_b32 off, v42, s33 offset:12
	; meta instruction
	scratch_store_b32 off, v43, s33 offset:8
	; meta instruction
	scratch_store_b32 off, v44, s33 offset:4
	; meta instruction
	scratch_store_b32 off, v45, s33
	v_writelane_b32 v46, s34, 0
	v_writelane_b32 v46, s35, 1
	v_writelane_b32 v46, s30, 2
	v_writelane_b32 v46, s31, 3
	v_dual_mov_b32 v42, v0 :: v_dual_mov_b32 v45, v2
	v_dual_mov_b32 v40, v3 :: v_dual_mov_b32 v41, v1
	s_mov_b32 s34, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v43, vcc_lo, v42, -1
	v_add_co_ci_u32_e32 v44, vcc_lo, -1, v41, vcc_lo
.LBB0_1:                                ; %tailrecurse
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_3 Depth 2
                                        ;       Child Loop BB0_4 Depth 3
                                        ;       Child Loop BB0_6 Depth 3
	s_delay_alu instid0(VALU_DEP_3)
	v_mov_b32_e32 v3, v40
	s_mov_b32 s1, exec_lo
	v_cmpx_le_i32_e64 v2, v40
	s_cbranch_execz .LBB0_11
; %bb.2:                                ; %.preheader45.preheader
                                        ;   in Loop: Header=BB0_1 Depth=1
	v_dual_mov_b32 v3, v40 :: v_dual_add_nc_u32 v0, v2, v40
	s_mov_b32 s2, 0
	v_mov_b32_e32 v45, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshrrev_b32_e32 v1, 31, v0
	v_add_nc_u32_e32 v0, v0, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v0, 1, v0
	v_ashrrev_i32_e32 v1, 31, v0
	v_add_co_u32 v0, vcc_lo, v42, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, v41, v1, vcc_lo
	flat_load_u8 v0, v[0:1]
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_and_b32_e32 v6, 0xff, v0
.LBB0_3:                                ; %.preheader45
                                        ;   Parent Loop BB0_1 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB0_4 Depth 3
                                        ;       Child Loop BB0_6 Depth 3
	v_ashrrev_i32_e32 v1, 31, v45
	v_add_co_u32 v0, vcc_lo, v43, v45
	v_mov_b32_e32 v7, v45
	s_mov_b32 s3, 0
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v1, vcc_lo, v44, v1, vcc_lo
.LBB0_4:                                ;   Parent Loop BB0_1 Depth=1
                                        ;     Parent Loop BB0_3 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	flat_load_u8 v8, v[0:1] offset:1
	v_mov_b32_e32 v45, v7
	v_add_co_u32 v0, vcc_lo, v0, 1
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v7, 1, v45
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_cmp_ge_u16_e64 s0, v8, v6
	s_or_b32 s3, s0, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s3
	s_cbranch_execnz .LBB0_4
; %bb.5:                                ; %.preheader.preheader
                                        ;   in Loop: Header=BB0_3 Depth=2
	s_or_b32 exec_lo, exec_lo, s3
	v_ashrrev_i32_e32 v5, 31, v3
	v_add_co_u32 v4, vcc_lo, v42, v3
	v_mov_b32_e32 v10, v3
	s_mov_b32 s3, 0
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v5, vcc_lo, v41, v5, vcc_lo
.LBB0_6:                                ; %.preheader
                                        ;   Parent Loop BB0_1 Depth=1
                                        ;     Parent Loop BB0_3 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	flat_load_u8 v9, v[4:5]
	v_mov_b32_e32 v3, v10
	v_add_co_u32 v4, vcc_lo, v4, -1
	v_add_co_ci_u32_e32 v5, vcc_lo, -1, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v10, -1, v3
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_cmp_le_u16_e64 s0, v9, v6
	s_or_b32 s3, s0, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s3
	s_cbranch_execnz .LBB0_6
; %bb.7:                                ;   in Loop: Header=BB0_3 Depth=2
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_le_i32_e64 v45, v3
	s_cbranch_execz .LBB0_9
; %bb.8:                                ;   in Loop: Header=BB0_3 Depth=2
	v_mov_b32_e32 v3, v10
	v_mov_b32_e32 v45, v7
	flat_store_b8 v[0:1], v9
	flat_store_b8 v[4:5], v8 offset:1
.LBB0_9:                                ;   in Loop: Header=BB0_3 Depth=2
	s_or_b32 exec_lo, exec_lo, s0
	v_cmp_gt_i32_e32 vcc_lo, v45, v3
	s_or_b32 s2, vcc_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s2
	s_cbranch_execnz .LBB0_3
; %bb.10:                               ; %Flow
                                        ;   in Loop: Header=BB0_1 Depth=1
	s_or_b32 exec_lo, exec_lo, s2
.LBB0_11:                               ; %Flow88
                                        ;   in Loop: Header=BB0_1 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_mov_b32 s35, exec_lo
	v_cmpx_gt_i32_e64 v3, v2
	s_cbranch_execz .LBB0_13
; %bb.12:                               ;   in Loop: Header=BB0_1 Depth=1
	v_dual_mov_b32 v0, v42 :: v_dual_mov_b32 v1, v41
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, quickSort@rel32@lo+4
	s_addc_u32 s1, s1, quickSort@rel32@hi+12
	s_delay_alu instid0(SALU_CYCLE_1)
	s_swappc_b64 s[30:31], s[0:1]
.LBB0_13:                               ;   in Loop: Header=BB0_1 Depth=1
	s_or_b32 exec_lo, exec_lo, s35
	v_cmp_ge_i32_e32 vcc_lo, v45, v40
	v_mov_b32_e32 v2, v45
	s_or_b32 s34, vcc_lo, s34
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s34
	s_cbranch_execnz .LBB0_1
; %bb.14:
	s_or_b32 exec_lo, exec_lo, s34
	s_clause 0x5
	scratch_load_b32 v45, off, s33
	scratch_load_b32 v44, off, s33 offset:4
	scratch_load_b32 v43, off, s33 offset:8
	scratch_load_b32 v42, off, s33 offset:12
	scratch_load_b32 v41, off, s33 offset:16
	scratch_load_b32 v40, off, s33 offset:20
	v_readlane_b32 s30, v46, 2
	v_readlane_b32 s31, v46, 3
	v_readlane_b32 s35, v46, 1
	v_readlane_b32 s34, v46, 0
	v_readlane_b32 s0, v46, 4
	s_or_saveexec_b32 s1, -1
	scratch_load_b32 v46, off, s33 offset:24 ; 4-byte Folded Reload
	s_mov_b32 exec_lo, s1
	s_addk_i32 s32, 0xffe0
	s_mov_b32 s33, s0
	s_waitcnt vmcnt(0) lgkmcnt(0)
	s_setpc_b64 s[30:31]
.Lfunc_end0:
	.size	quickSort, .Lfunc_end0-quickSort
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Function info:
; codeLenInByte = 732
; NumSgprs: 38
; NumVgprs: 47
; ScratchSize: 32
; MemoryBound: 0
	.text
	.protected	adaptive_median_filter_kernel ; -- Begin function adaptive_median_filter_kernel
	.globl	adaptive_median_filter_kernel
	.p2align	8
	.type	adaptive_median_filter_kernel,@function
adaptive_median_filter_kernel:          ; @adaptive_median_filter_kernel
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x2c
	s_load_b256 s[36:43], s[0:1], 0x0
	v_and_b32_e32 v1, 0x3ff, v0
	v_bfe_u32 v0, v0, 10, 10
	v_mov_b32_e32 v47, 3
	s_mov_b32 s32, 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s1, s2, 0xffff
	s_lshr_b32 s0, s2, 16
	v_mad_u64_u32 v[43:44], null, s14, s1, v[1:2]
	v_mad_u64_u32 v[44:45], null, s15, s0, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[0:1], null, v44, s40, v[43:44]
	v_ashrrev_i32_e32 v3, 31, v0
	v_add_co_u32 v1, vcc_lo, s36, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v2, vcc_lo, s37, v3, vcc_lo
	global_load_u8 v45, v[1:2], off
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v1, 0xffff, v45
	v_cvt_f64_u32_e32 v[56:57], v1
	v_mul_lo_u32 v1, v0, 50
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v2, 31, v1
	v_add_co_u32 v40, vcc_lo, s42, v1
	v_add_co_ci_u32_e32 v41, vcc_lo, s43, v2, vcc_lo
	v_add_co_u32 v58, vcc_lo, s38, v0
	v_add_co_ci_u32_e32 v59, vcc_lo, s39, v3, vcc_lo
	s_mov_b32 s38, 0
.LBB1_1:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB1_3 Depth 2
                                        ;       Child Loop BB1_5 Depth 3
	v_add_nc_u32_e32 v0, -1, v47
	v_mov_b32_e32 v60, 0
	v_dual_mov_b32 v61, 0x406fe000 :: v_dual_mov_b32 v62, 0
	v_mov_b32_e32 v42, 0
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshrrev_b32_e32 v1, 31, v0
	s_mov_b32 s4, exec_lo
	v_dual_mov_b32 v63, 0 :: v_dual_add_nc_u32 v0, v0, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v4, 1, v0
	v_sub_nc_u32_e32 v0, v43, v4
	v_add_nc_u32_e32 v2, v4, v43
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_le_i32_e64 v0, v2
	s_cbranch_execz .LBB1_11
; %bb.2:                                ; %.lr.ph114
                                        ;   in Loop: Header=BB1_1 Depth=1
	v_sub_nc_u32_e32 v1, v44, v4
	v_mov_b32_e32 v60, 0
	v_mov_b32_e32 v62, 0
	v_dual_mov_b32 v63, 0 :: v_dual_add_nc_u32 v2, 1, v2
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[5:6], null, s40, v1, v[43:44]
	v_dual_mov_b32 v61, 0x406fe000 :: v_dual_add_nc_u32 v6, v4, v44
	v_lshl_or_b32 v3, v4, 1, 1
	v_mov_b32_e32 v42, 0
	s_mov_b32 s5, 0
	v_cmp_le_i32_e32 vcc_lo, v1, v6
	v_sub_nc_u32_e32 v4, v5, v4
.LBB1_3:                                ;   Parent Loop BB1_1 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB1_5 Depth 3
	s_and_saveexec_b32 s6, vcc_lo
	s_cbranch_execz .LBB1_9
; %bb.4:                                ; %.lr.ph
                                        ;   in Loop: Header=BB1_3 Depth=2
	v_cmp_gt_i32_e64 s0, s40, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v6, v3
	v_mov_b32_e32 v7, v1
	s_mov_b32 s7, 0
.LBB1_5:                                ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_3 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_or_b32_e32 v8, v7, v0
	v_cmp_gt_i32_e64 s2, s41, v7
	v_cmp_lt_i32_e64 s1, -1, v8
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 s1, s0, s1
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	s_and_b32 s1, s2, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s8, s1
	s_cbranch_execz .LBB1_7
; %bb.6:                                ;   in Loop: Header=BB1_5 Depth=3
	v_ashrrev_i32_e32 v9, 31, v5
	v_add_co_u32 v8, s1, s36, v5
	v_ashrrev_i32_e32 v11, 31, v42
	v_add_co_u32 v10, s3, v40, v42
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v9, s1, s37, v9, s1
	v_add_co_ci_u32_e64 v11, s3, v41, v11, s3
	v_add_nc_u32_e32 v42, 1, v42
	global_load_u8 v12, v[8:9], off
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v8, 0xffff, v12
	global_store_b8 v[10:11], v12, off
	v_cvt_f64_u32_e32 v[8:9], v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cmp_gt_f64_e64 s1, v[60:61], v[8:9]
	v_cmp_lt_f64_e64 s2, v[62:63], v[8:9]
	v_cndmask_b32_e64 v61, v61, v9, s1
	s_delay_alu instid0(VALU_DEP_2)
	v_cndmask_b32_e64 v63, v63, v9, s2
	v_cndmask_b32_e64 v60, v60, v8, s1
	v_cndmask_b32_e64 v62, v62, v8, s2
.LBB1_7:                                ;   in Loop: Header=BB1_5 Depth=3
	s_or_b32 exec_lo, exec_lo, s8
	v_add_nc_u32_e32 v6, -1, v6
	v_add_nc_u32_e32 v7, 1, v7
	v_add_nc_u32_e32 v5, s40, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_eq_u32_e64 s1, 0, v6
	s_or_b32 s7, s1, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s7
	s_cbranch_execnz .LBB1_5
; %bb.8:                                ; %Flow174
                                        ;   in Loop: Header=BB1_3 Depth=2
	s_or_b32 exec_lo, exec_lo, s7
.LBB1_9:                                ; %Flow175
                                        ;   in Loop: Header=BB1_3 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	s_or_b32 exec_lo, exec_lo, s6
	v_add_nc_u32_e32 v0, 1, v0
	v_add_nc_u32_e32 v4, 1, v4
	v_cmp_eq_u32_e64 s0, v0, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s5, s0, s5
	s_and_not1_b32 exec_lo, exec_lo, s5
	s_cbranch_execnz .LBB1_3
; %bb.10:                               ; %Flow176
                                        ;   in Loop: Header=BB1_1 Depth=1
	s_or_b32 exec_lo, exec_lo, s5
.LBB1_11:                               ; %Flow177
                                        ;   in Loop: Header=BB1_1 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s4
	v_dual_mov_b32 v0, v40 :: v_dual_mov_b32 v1, v41
	v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v3, v42
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, quickSort@rel32@lo+4
	s_addc_u32 s1, s1, quickSort@rel32@hi+12
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	s_swappc_b64 s[30:31], s[0:1]
	v_lshrrev_b32_e32 v0, 31, v42
	s_mov_b32 s2, 0
                                        ; implicit-def: $sgpr1
	v_add_nc_u32_e32 v0, v42, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v0, 1, v0
	v_ashrrev_i32_e32 v1, 31, v0
	v_add_co_u32 v0, vcc_lo, v40, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v1, vcc_lo, v41, v1, vcc_lo
	global_load_u8 v0, v[0:1], off
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v1, 0xffff, v0
	v_cvt_f64_u32_e32 v[1:2], v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[3:4], v[1:2], -v[60:61]
	v_add_f64 v[1:2], v[1:2], -v[62:63]
	v_cmp_nlt_f64_e32 vcc_lo, 0, v[3:4]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_ngt_f64_e64 s0, 0, v[1:2]
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_saveexec_b32 s3, s0
	s_xor_b32 s0, exec_lo, s3
; %bb.12:                               ;   in Loop: Header=BB1_1 Depth=1
	v_add_nc_u32_e32 v1, 2, v47
	v_cmp_lt_i32_e32 vcc_lo, 5, v47
	s_mov_b32 s1, 0
                                        ; implicit-def: $vgpr60_vgpr61
                                        ; implicit-def: $vgpr62_vgpr63
	s_delay_alu instid0(VALU_DEP_2)
	v_mov_b32_e32 v47, v1
	s_and_b32 s2, vcc_lo, exec_lo
; %bb.13:                               ; %Flow
                                        ;   in Loop: Header=BB1_1 Depth=1
	s_and_not1_saveexec_b32 s3, s0
; %bb.14:                               ;   in Loop: Header=BB1_1 Depth=1
	v_add_f64 v[1:2], v[56:57], -v[60:61]
	v_add_f64 v[3:4], v[56:57], -v[62:63]
	s_or_b32 s2, s2, exec_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_lt_f64_e32 vcc_lo, 0, v[1:2]
	v_cmp_gt_f64_e64 s0, 0, v[3:4]
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 vcc_lo, vcc_lo, s0
	v_cndmask_b32_e32 v0, v0, v45, vcc_lo
; %bb.15:                               ; %Flow173
                                        ;   in Loop: Header=BB1_1 Depth=1
	s_or_b32 exec_lo, exec_lo, s3
	s_and_saveexec_b32 s0, s2
	s_cbranch_execz .LBB1_17
; %bb.16:                               ; %.sink.split
                                        ;   in Loop: Header=BB1_1 Depth=1
	s_or_b32 s1, s1, exec_lo
	global_store_b8 v[58:59], v0, off
.LBB1_17:                               ;   in Loop: Header=BB1_1 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, exec_lo, s1
	s_or_b32 s38, s0, s38
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s38
	s_cbranch_execnz .LBB1_1
; %bb.18:
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel adaptive_median_filter_kernel
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 32
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 1
		.amdhsa_enable_private_segment 1
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 64
		.amdhsa_next_free_sgpr 44
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	adaptive_median_filter_kernel, .Lfunc_end1-adaptive_median_filter_kernel
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 936
; NumSgprs: 46
; NumVgprs: 64
; ScratchSize: 32
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 5
; VGPRBlocks: 7
; NumSGPRsForWavesPerEU: 46
; NumVGPRsForWavesPerEU: 64
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 1
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           adaptive_median_filter_kernel
    .private_segment_fixed_size: 32
    .sgpr_count:     46
    .sgpr_spill_count: 0
    .symbol:         adaptive_median_filter_kernel.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: true
    .vgpr_count:     64
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
