//Copyright (c) 2018 ETH Zurich, Lukas Cavigelli
#include <math.h>
#include <cuda_runtime.h>
#include <cuda_fp16.h>

using namespace std;
typedef __half half;


   __global__ void changeDetection_1x1_kernel(
                                         const half* __restrict__ input,
                                         half* __restrict__ inputState,
                                         bool* __restrict__ changeMap,
                                         const int width, const int height, const int nInputPlane,
                                         const float diffThreshold_float,
                                         const bool updateInputState) {

    // compute pixel index
    int pxlInpIdx = blockIdx.x * blockDim.x + threadIdx.x;
    if(pxlInpIdx >= height * width) return;

    //check for changes at the pixel location; any feature map can trigger a change
	half diffThreshold = __float2half(diffThreshold_float);
    bool change = false;
    for (int i = 0; i < nInputPlane; ++i) {
      int idx = i*(height*width) + pxlInpIdx; // !! this expression might need the long datatype for high res
	  half diff = __hsub(inputState[idx], input[idx]);
      change |= __hgt(diff, diffThreshold) | __hlt(diff, __hneg(diffThreshold));
    }

    if(!change) return; // no need to mark outputs/proceed, if not changed

    // mark pixels in the support of the changed pixel for updating
    changeMap[pxlInpIdx] = true;

    //update prevInput if with copyChanges/feedback
    if(updateInputState) { // implicit (&& change), otherwise already returned
      for (int i = 0; i < nInputPlane; ++i) {
        int idx = i*(height*width) + pxlInpIdx; // !! this expression might need the long datatype for high res                                                           
        inputState[idx] = input[idx];
      }
    }
  }
  
  __global__ void changeDetection_kernel(
                                         const half* __restrict__ input,
                                         half* __restrict__ inputState,
                                         bool* __restrict__ changeMap,
                                         const int width, const int height, const int nInputPlane,
                                         const int kHHalf, const int kWHalf, const float diffThreshold_float,
                                         const bool updateInputState) {

    // compute pixel index
    int pxlInpIdx = blockIdx.x * blockDim.x + threadIdx.x;
    if(pxlInpIdx >= height * width) return;

    //check for changes at the pixel location; any feature map can trigger a change
	half diffThreshold = __float2half(diffThreshold_float);
    bool change = false;
    for (int i = 0; i < nInputPlane; ++i) {
      int idx = i*(height*width) + pxlInpIdx; // !! this expression might need the long datatype for high res
	  half diff = __hsub(inputState[idx], input[idx]);
      change |= __hgt(diff, diffThreshold) | __hlt(diff, __hneg(diffThreshold));
    }

    if(!change) return; // no need to mark outputs/proceed, if not changed

    // mark pixels in the support of the changed pixel for updating
    int xIn = pxlInpIdx % width;
    int yIn = pxlInpIdx / width;
    for (int k = -kHHalf; k <= kHHalf; ++k) {
      int yOut = yIn + k;
      for (int l = -kWHalf; l <= kWHalf; ++l) {
        int xOut = xIn + l;
        if(yOut>=0 && yOut<height && xOut>=0 && xOut<width) {
          changeMap[yOut*width + xOut] = true;
        }
      }
    }

    //update prevInput if with copyChanges/feedback
    if(updateInputState) { // implicit (&& change), otherwise already returned
      for (int i = 0; i < nInputPlane; ++i) {
        int idx = i*(height*width) + pxlInpIdx; // !! this expression might need the long datatype for high res                                                           
        inputState[idx] = input[idx];
      }
    }
  }

extern "C" {
  void changeDetection(int gridz, int gridy, int gridx, int blockz, int blocky, int blockx,
                       const half* __restrict__ input,
                       half* __restrict__ oldinput,
                       bool* __restrict__ changeMap,
                       const int width, const int height, const int nInputPlane,
                       const int kHHalf, const int kWHalf, const float diffThreshold,
                       const bool updateInputState) {
    dim3 grid(gridx, gridy, gridz);
    dim3 block(blockx, blocky, blockz);
    
    if(kHHalf == 0 and kWHalf == 0) {      
      changeDetection_1x1_kernel<<<grid, block>>>(input, oldinput, changeMap, width, height,
                                                  nInputPlane, diffThreshold, updateInputState);
    } else {
      changeDetection_kernel<<<grid, block>>>(input, oldinput, changeMap, width, height, 
                                              nInputPlane, kHHalf, kWHalf, diffThreshold, updateInputState);
    }
  }
  __global__ void changePropagation_kernel(const bool* __restrict__ changeMatrixIn,
                                           bool* __restrict__ changeMatrixOut,
                                           const int width, const int height,
                                           const int kHHalf, const int kWHalf) {

    // compute pixel index
    int pxlInpIdx = blockIdx.x * blockDim.x + threadIdx.x;
    if(pxlInpIdx >= height * width) return;

    //check if any pixel in the input range has changed
    bool change = false;
    int xOut = pxlInpIdx % width;
    int yOut = pxlInpIdx / width;
    for (int k = -kHHalf; k <= kHHalf; ++k) {
      int yIn = yOut + k;
      for (int l = -kWHalf; l <= kWHalf; ++l) {
        int xIn = xOut + l;
        if(yIn>=0 && yIn<height && xIn>=0 && xIn<width) {
          change = change || changeMatrixIn[yIn*width + xIn];
        }
      }
    }
    changeMatrixOut[yOut*width + xOut] = change;
  }

  void changePropagation(int gridz, int gridy, int gridx, int blockz, int blocky, int blockx,
                         const bool* __restrict__ changeMatrixIn,
                         bool* __restrict__ changeMatrixOut,
                         const int width, const int height,
                         const int kHHalf, const int kWHalf) {
    dim3 grid(gridx, gridy, gridz);
    dim3 block(blockx, blocky, blockz);
    
    changePropagation_kernel<<<grid, block>>>(changeMatrixIn, changeMatrixOut, 
                                              width, height, kHHalf, kWHalf);
  }

  __global__ void genXMatrix_kernel(
                                    half* columns,
                                    const half* __restrict__ input,
                                    const int* __restrict__ changeList,
                                    const int kW, const int kH,
                                    const int nInputPlane, const int width, const int height,
                                    const int numChanges) {

    const int kx = threadIdx.x;
    const int ky = threadIdx.z;
    const	int changeIdx = blockIdx.x * blockDim.y + threadIdx.y;

    if(changeIdx < numChanges) {
      int pos = changeList[changeIdx];
      int ix = pos % width + kx - (kW-1)/2;
      int iy = pos / width + ky - (kH-1)/2;
      half *dst = columns + changeIdx*(kW*kH*nInputPlane) + ky*kW+kx;

      const bool isInImage = ix>=0 && ix < width && iy>=0 && iy< height;
      for (int i = 0; i < nInputPlane; ++i) {
        dst[i*kH*kW] = isInImage ? input[(i*height + iy) * width + ix] : __float2half(0.0f);
      }
    }
  }

  void genXMatrix(int gridz, int gridy, int gridx, int blockz, int blocky, int blockx,
                  half* columns,
                  const half* __restrict__ input,
                  const int* __restrict__ changeList,
                  const int kW, const int kH,
                  const int nInputPlane, const int width, const int height,
                  const int numChanges) {
    dim3 grid(gridx, gridy, gridz);
    dim3 block(blockx, blocky, blockz);
    genXMatrix_kernel<<<grid, block>>>(columns, input, changeList, kW, kH, nInputPlane, width, height, numChanges);
  }

  __global__ void updateOutput_kernel(const half* __restrict__ columnsOut,
                                      half* output, const int* __restrict__ changeList,
                                      const int numOutputPixel, const int numChanges, const int nOutputPlane, const bool relu) {

    int count = blockIdx.x * blockDim.x + threadIdx.x;

    if(count < numChanges*nOutputPlane) {
      int outpPlane = count / numChanges;
      int changeNr =  count % numChanges;
      int pxl = changeList[changeNr];
      half v = columnsOut[count];
      v = relu && __hle(v, __float2half(0.0f)) ? __float2half(0.0f) : v;
      output[outpPlane*numOutputPixel + pxl] = v;
    }
  }

  void updateOutput(int gridz, int gridy, int gridx, int blockz, int blocky, int blockx,
                    half *columnsOut, half *output, int* changeList, 
                    int numOutputPixel, int numChanges, int nOutputPlane, bool relu) {
    dim3 grid(gridx, gridy, gridz);
    dim3 block(blockx, blocky, blockz);
    updateOutput_kernel<<<grid, block>>>(columnsOut, output, changeList, numOutputPixel, numChanges, nOutputPlane, relu);
  }

  __global__ void maxPool2d_kernel(const half* __restrict__ input,
                                   half* __restrict__ output, 
                                   const int* __restrict__ changeIndexes,
                                   const int numChanges, 
                                   const int numCh, const int iheight, const int iwidth,
                                   const int oheight, const int owidth,
                                   const int stridey, const int stridex) {

    int tid = blockIdx.x * blockDim.x + threadIdx.x;
    if(tid >= numChanges)
      return;
    int pxIdx = changeIndexes[tid];
    int y = pxIdx / iwidth, x = pxIdx % iwidth;
    int yo = y / stridey, xo = x / stridex;

    for(int ch = 0; ch < numCh; ch++) {
      half v = __float2half(-INFINITY);
      for(int j = 0; j < stridey; j++) {
        for(int i = 0; i < stridex; i++) {
          int yi = yo*stridey + j, xi = xo*stridex + i;
          if(yi < iheight && xi < iwidth) {
			half iVal = input[(ch*iheight + yi)*iwidth + xi];
			if (__hgt(iVal, v))
				v = iVal;
          }
        }
      }
      output[(ch*oheight + yo)*owidth + xo] = v;
    }
    
  }

  void maxPool2d(int gridx, int blockx,
                 half *input, half *output, int* changeIndexes, int numChanges, 
                 int numCh, int iheight, int iwidth,
                 int oheight, int owidth,
                 int stridey, int stridex) {
                 
    //determine grid and block size based on number of changes
    dim3 grid(gridx);
    dim3 block(blockx);
    maxPool2d_kernel<<<grid, block>>>(input, output, changeIndexes, numChanges, 
                                      numCh, iheight, iwidth, oheight, owidth, stridey, stridex);
  }

}

	.file	"tmpxft_0029a3ca_00000000-6_cbconv2d_cg_half_backend.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2389:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2389:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z63__device_stub__Z26changeDetection_1x1_kernelPK6__halfPS_PbiiifbPK6__halfPS_Pbiiifb
	.type	_Z63__device_stub__Z26changeDetection_1x1_kernelPK6__halfPS_PbiiifbPK6__halfPS_Pbiiifb, @function
_Z63__device_stub__Z26changeDetection_1x1_kernelPK6__halfPS_PbiiifbPK6__halfPS_Pbiiifb:
.LFB2411:
	.cfi_startproc
	endbr64
	subq	$200, %rsp
	.cfi_def_cfa_offset 208
	movl	208(%rsp), %eax
	movl	%ecx, 28(%rsp)
	leaq	64(%rsp), %rcx
	movl	%r8d, 24(%rsp)
	movl	%r9d, 20(%rsp)
	movb	%al, 12(%rsp)
	movss	%xmm0, 16(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 184(%rsp)
	xorl	%eax, %eax
	leaq	32(%rsp), %rax
	movq	%rdi, 32(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rax, 120(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	28(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	12(%rsp), %rax
	movq	%rsi, 40(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 48(%rsp)
	leaq	56(%rsp), %rdx
	movq	%rax, 176(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movl	$1, 80(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	64(%rsp)
	.cfi_def_cfa_offset 216
	leaq	_Z26changeDetection_1x1_kernelPK6__halfPS_Pbiiifb(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 224
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 216
	popq	%rdx
	.cfi_def_cfa_offset 208
.L2:
	movq	184(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$200, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2411:
	.size	_Z63__device_stub__Z26changeDetection_1x1_kernelPK6__halfPS_PbiiifbPK6__halfPS_Pbiiifb, .-_Z63__device_stub__Z26changeDetection_1x1_kernelPK6__halfPS_PbiiifbPK6__halfPS_Pbiiifb
	.globl	_Z26changeDetection_1x1_kernelPK6__halfPS_Pbiiifb
	.type	_Z26changeDetection_1x1_kernelPK6__halfPS_Pbiiifb, @function
_Z26changeDetection_1x1_kernelPK6__halfPS_Pbiiifb:
.LFB2412:
	.cfi_startproc
	endbr64
	movzbl	8(%rsp), %eax
	movl	%eax, 8(%rsp)
	jmp	_Z63__device_stub__Z26changeDetection_1x1_kernelPK6__halfPS_PbiiifbPK6__halfPS_Pbiiifb
	.cfi_endproc
.LFE2412:
	.size	_Z26changeDetection_1x1_kernelPK6__halfPS_Pbiiifb, .-_Z26changeDetection_1x1_kernelPK6__halfPS_Pbiiifb
	.globl	_Z61__device_stub__Z22changeDetection_kernelPK6__halfPS_PbiiiiifbPK6__halfPS_Pbiiiiifb
	.type	_Z61__device_stub__Z22changeDetection_kernelPK6__halfPS_PbiiiiifbPK6__halfPS_Pbiiiiifb, @function
_Z61__device_stub__Z22changeDetection_kernelPK6__halfPS_PbiiiiifbPK6__halfPS_Pbiiiiifb:
.LFB2413:
	.cfi_startproc
	endbr64
	subq	$216, %rsp
	.cfi_def_cfa_offset 224
	movl	240(%rsp), %eax
	movl	%ecx, 28(%rsp)
	leaq	64(%rsp), %rcx
	movl	%r8d, 24(%rsp)
	movl	%r9d, 20(%rsp)
	movb	%al, 12(%rsp)
	movss	%xmm0, 16(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 200(%rsp)
	xorl	%eax, %eax
	leaq	32(%rsp), %rax
	movq	%rdi, 32(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rax, 120(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	28(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	224(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	232(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	12(%rsp), %rax
	movq	%rsi, 40(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 48(%rsp)
	leaq	56(%rsp), %rdx
	movq	%rax, 192(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movl	$1, 80(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L8
	pushq	64(%rsp)
	.cfi_def_cfa_offset 232
	leaq	_Z22changeDetection_kernelPK6__halfPS_Pbiiiiifb(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 240
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 232
	popq	%rdx
	.cfi_def_cfa_offset 224
.L8:
	movq	200(%rsp), %rax
	subq	%fs:40, %rax
	je	.L10
	call	__stack_chk_fail@PLT
.L10:
	addq	$216, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2413:
	.size	_Z61__device_stub__Z22changeDetection_kernelPK6__halfPS_PbiiiiifbPK6__halfPS_Pbiiiiifb, .-_Z61__device_stub__Z22changeDetection_kernelPK6__halfPS_PbiiiiifbPK6__halfPS_Pbiiiiifb
	.globl	_Z22changeDetection_kernelPK6__halfPS_Pbiiiiifb
	.type	_Z22changeDetection_kernelPK6__halfPS_Pbiiiiifb, @function
_Z22changeDetection_kernelPK6__halfPS_Pbiiiiifb:
.LFB2414:
	.cfi_startproc
	endbr64
	movzbl	24(%rsp), %eax
	movl	%eax, 24(%rsp)
	jmp	_Z61__device_stub__Z22changeDetection_kernelPK6__halfPS_PbiiiiifbPK6__halfPS_Pbiiiiifb
	.cfi_endproc
.LFE2414:
	.size	_Z22changeDetection_kernelPK6__halfPS_Pbiiiiifb, .-_Z22changeDetection_kernelPK6__halfPS_Pbiiiiifb
	.globl	changeDetection
	.type	changeDetection, @function
changeDetection:
.LFB2382:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movl	%edi, %eax
	movl	%ecx, %ecx
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$72, %rsp
	.cfi_def_cfa_offset 128
	movq	128(%rsp), %rbx
	movl	176(%rsp), %ebp
	movl	%esi, 44(%rsp)
	movl	184(%rsp), %r12d
	movq	144(%rsp), %rdi
	movl	%r9d, 52(%rsp)
	xorl	%r9d, %r9d
	movq	%rbx, (%rsp)
	movl	%ebp, %esi
	movq	136(%rsp), %rbx
	movl	%r8d, 56(%rsp)
	xorl	%r8d, %r8d
	orl	%r12d, %esi
	movl	152(%rsp), %r13d
	movq	%rbx, 8(%rsp)
	movl	160(%rsp), %r14d
	movl	%eax, %esi
	movl	%edx, 40(%rsp)
	movl	168(%rsp), %r15d
	movq	%rdi, 16(%rsp)
	movl	192(%rsp), %ebx
	movq	52(%rsp), %rdx
	movss	%xmm0, 28(%rsp)
	movq	40(%rsp), %rdi
	jne	.L14
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L13
	movzbl	%bl, %ebx
	movss	28(%rsp), %xmm0
	movq	(%rsp), %rdi
	movl	%r15d, %r9d
	movq	16(%rsp), %rdx
	movq	8(%rsp), %rsi
	movl	%r14d, %r8d
	movl	%r13d, %ecx
	movl	%ebx, 128(%rsp)
	addq	$72, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	_Z63__device_stub__Z26changeDetection_1x1_kernelPK6__halfPS_PbiiifbPK6__halfPS_Pbiiifb
.L14:
	.cfi_restore_state
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L13
	movzbl	%bl, %ebx
	movss	28(%rsp), %xmm0
	movq	(%rsp), %rdi
	movl	%r15d, %r9d
	movq	16(%rsp), %rdx
	movq	8(%rsp), %rsi
	movl	%r14d, %r8d
	movl	%r13d, %ecx
	movl	%ebx, 144(%rsp)
	movl	%r12d, 136(%rsp)
	movl	%ebp, 128(%rsp)
	addq	$72, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	_Z61__device_stub__Z22changeDetection_kernelPK6__halfPS_PbiiiiifbPK6__halfPS_Pbiiiiifb
.L13:
	.cfi_restore_state
	addq	$72, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2382:
	.size	changeDetection, .-changeDetection
	.globl	_Z51__device_stub__Z24changePropagation_kernelPKbPbiiiiPKbPbiiii
	.type	_Z51__device_stub__Z24changePropagation_kernelPKbPbiiiiPKbPbiiii, @function
_Z51__device_stub__Z24changePropagation_kernelPKbPbiiiiPKbPbiiii:
.LFB2415:
	.cfi_startproc
	endbr64
	subq	$168, %rsp
	.cfi_def_cfa_offset 176
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	48(%rsp), %rcx
	movl	%r8d, 4(%rsp)
	movl	%r9d, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 152(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rax, 104(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 136(%rsp)
	movq	%rsp, %rax
	movq	%rsi, 32(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rax, 144(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movl	$1, 64(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L19
	pushq	48(%rsp)
	.cfi_def_cfa_offset 184
	leaq	changePropagation_kernel(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 192
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 184
	popq	%rdx
	.cfi_def_cfa_offset 176
.L19:
	movq	152(%rsp), %rax
	subq	%fs:40, %rax
	je	.L21
	call	__stack_chk_fail@PLT
.L21:
	addq	$168, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2415:
	.size	_Z51__device_stub__Z24changePropagation_kernelPKbPbiiiiPKbPbiiii, .-_Z51__device_stub__Z24changePropagation_kernelPKbPbiiiiPKbPbiiii
	.globl	changePropagation_kernel
	.type	changePropagation_kernel, @function
changePropagation_kernel:
.LFB2416:
	.cfi_startproc
	endbr64
	jmp	_Z51__device_stub__Z24changePropagation_kernelPKbPbiiiiPKbPbiiii
	.cfi_endproc
.LFE2416:
	.size	changePropagation_kernel, .-changePropagation_kernel
	.globl	changePropagation
	.type	changePropagation, @function
changePropagation:
.LFB2383:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movl	%edi, %eax
	movl	%ecx, %ecx
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$40, %rsp
	.cfi_def_cfa_offset 96
	movl	%edx, 8(%rsp)
	movq	96(%rsp), %rbx
	movq	104(%rsp), %rbp
	movl	112(%rsp), %r12d
	movl	%esi, 12(%rsp)
	movl	%eax, %esi
	movq	8(%rsp), %rdi
	movl	120(%rsp), %r13d
	movl	%r9d, 20(%rsp)
	xorl	%r9d, %r9d
	movl	%r8d, 24(%rsp)
	movq	20(%rsp), %rdx
	xorl	%r8d, %r8d
	movl	128(%rsp), %r14d
	movl	136(%rsp), %r15d
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L24
	addq	$40, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 56
	movl	%r15d, %r9d
	movl	%r14d, %r8d
	movl	%r13d, %ecx
	movl	%r12d, %edx
	movq	%rbp, %rsi
	movq	%rbx, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	_Z51__device_stub__Z24changePropagation_kernelPKbPbiiiiPKbPbiiii
.L24:
	.cfi_restore_state
	addq	$40, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2383:
	.size	changePropagation, .-changePropagation
	.globl	_Z56__device_stub__Z17genXMatrix_kernelP6__halfPKS_PKiiiiiiiP6__halfPKS_PKiiiiiii
	.type	_Z56__device_stub__Z17genXMatrix_kernelP6__halfPKS_PKiiiiiiiP6__halfPKS_PKiiiiiii, @function
_Z56__device_stub__Z17genXMatrix_kernelP6__halfPKS_PKiiiiiiiP6__halfPKS_PKiiiiiii:
.LFB2417:
	.cfi_startproc
	endbr64
	subq	$200, %rsp
	.cfi_def_cfa_offset 208
	movq	%rdi, 24(%rsp)
	leaq	64(%rsp), %rdi
	movl	%ecx, 20(%rsp)
	leaq	56(%rsp), %rcx
	movl	%r8d, 16(%rsp)
	movl	%r9d, 12(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 184(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rax, 112(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	208(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	216(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	224(%rsp), %rax
	movq	%rdx, 40(%rsp)
	leaq	48(%rsp), %rdx
	movq	%rax, 176(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movl	$1, 72(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L27
	pushq	56(%rsp)
	.cfi_def_cfa_offset 216
	leaq	genXMatrix_kernel(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 224
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 216
	popq	%rdx
	.cfi_def_cfa_offset 208
.L27:
	movq	184(%rsp), %rax
	subq	%fs:40, %rax
	je	.L29
	call	__stack_chk_fail@PLT
.L29:
	addq	$200, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2417:
	.size	_Z56__device_stub__Z17genXMatrix_kernelP6__halfPKS_PKiiiiiiiP6__halfPKS_PKiiiiiii, .-_Z56__device_stub__Z17genXMatrix_kernelP6__halfPKS_PKiiiiiiiP6__halfPKS_PKiiiiiii
	.globl	genXMatrix_kernel
	.type	genXMatrix_kernel, @function
genXMatrix_kernel:
.LFB2418:
	.cfi_startproc
	endbr64
	jmp	_Z56__device_stub__Z17genXMatrix_kernelP6__halfPKS_PKiiiiiiiP6__halfPKS_PKiiiiiii
	.cfi_endproc
.LFE2418:
	.size	genXMatrix_kernel, .-genXMatrix_kernel
	.globl	genXMatrix
	.type	genXMatrix, @function
genXMatrix:
.LFB2384:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movl	%edi, %eax
	movl	%ecx, %ecx
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$72, %rsp
	.cfi_def_cfa_offset 128
	movq	128(%rsp), %rbx
	movq	144(%rsp), %rdi
	movl	%edx, 40(%rsp)
	movl	%esi, 44(%rsp)
	movl	%eax, %esi
	movl	152(%rsp), %r12d
	movl	%r9d, 52(%rsp)
	xorl	%r9d, %r9d
	movl	160(%rsp), %r13d
	movl	%r8d, 56(%rsp)
	movq	52(%rsp), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, 8(%rsp)
	movq	136(%rsp), %rbx
	movq	%rdi, 24(%rsp)
	movq	40(%rsp), %rdi
	movq	%rbx, 16(%rsp)
	movl	168(%rsp), %r14d
	movl	176(%rsp), %r15d
	movl	184(%rsp), %ebx
	movl	192(%rsp), %ebp
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L32
	movl	%ebp, 144(%rsp)
	movl	%r14d, %r9d
	movl	%r13d, %r8d
	movl	%r12d, %ecx
	movl	%ebx, 136(%rsp)
	movq	24(%rsp), %rdx
	movl	%r15d, 128(%rsp)
	movq	16(%rsp), %rsi
	movq	8(%rsp), %rdi
	addq	$72, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	_Z56__device_stub__Z17genXMatrix_kernelP6__halfPKS_PKiiiiiiiP6__halfPKS_PKiiiiiii
.L32:
	.cfi_restore_state
	addq	$72, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2384:
	.size	genXMatrix, .-genXMatrix
	.globl	_Z56__device_stub__Z19updateOutput_kernelPK6__halfPS_PKiiiibPK6__halfPS_PKiiiib
	.type	_Z56__device_stub__Z19updateOutput_kernelPK6__halfPS_PKiiiibPK6__halfPS_PKiiiib, @function
_Z56__device_stub__Z19updateOutput_kernelPK6__halfPS_PKiiiibPK6__halfPS_PKiiiib:
.LFB2419:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movl	192(%rsp), %eax
	movq	%rsi, 24(%rsp)
	leaq	76(%rsp), %rsi
	movl	%ecx, 20(%rsp)
	leaq	56(%rsp), %rcx
	movl	%r8d, 16(%rsp)
	movl	%r9d, 12(%rsp)
	movb	%al, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	32(%rsp), %rax
	movq	%rdi, 32(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rax, 112(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	8(%rsp), %rax
	movq	%rdx, 40(%rsp)
	leaq	48(%rsp), %rdx
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movl	$1, 72(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L35
	pushq	56(%rsp)
	.cfi_def_cfa_offset 200
	leaq	updateOutput_kernel(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 208
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L35:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L37
	call	__stack_chk_fail@PLT
.L37:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2419:
	.size	_Z56__device_stub__Z19updateOutput_kernelPK6__halfPS_PKiiiibPK6__halfPS_PKiiiib, .-_Z56__device_stub__Z19updateOutput_kernelPK6__halfPS_PKiiiibPK6__halfPS_PKiiiib
	.globl	updateOutput_kernel
	.type	updateOutput_kernel, @function
updateOutput_kernel:
.LFB2420:
	.cfi_startproc
	endbr64
	movzbl	8(%rsp), %eax
	movl	%eax, 8(%rsp)
	jmp	_Z56__device_stub__Z19updateOutput_kernelPK6__halfPS_PKiiiibPK6__halfPS_PKiiiib
	.cfi_endproc
.LFE2420:
	.size	updateOutput_kernel, .-updateOutput_kernel
	.globl	updateOutput
	.type	updateOutput, @function
updateOutput:
.LFB2385:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movl	%edi, %eax
	movl	%ecx, %ecx
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$56, %rsp
	.cfi_def_cfa_offset 112
	movl	%edx, 24(%rsp)
	movq	112(%rsp), %rbx
	movl	%esi, 28(%rsp)
	movq	24(%rsp), %rdi
	movl	%eax, %esi
	movl	%r9d, 36(%rsp)
	xorl	%r9d, %r9d
	movq	120(%rsp), %rbp
	movl	%r8d, 40(%rsp)
	movq	36(%rsp), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, 8(%rsp)
	movq	128(%rsp), %r12
	movl	136(%rsp), %r13d
	movl	144(%rsp), %r14d
	movl	152(%rsp), %r15d
	movl	160(%rsp), %ebx
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L40
	movzbl	%bl, %ebx
	movq	8(%rsp), %rdi
	movl	%r15d, %r9d
	movl	%r14d, %r8d
	movl	%ebx, 112(%rsp)
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 56
	movl	%r13d, %ecx
	movq	%r12, %rdx
	popq	%rbx
	.cfi_def_cfa_offset 48
	movq	%rbp, %rsi
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	_Z56__device_stub__Z19updateOutput_kernelPK6__halfPS_PKiiiibPK6__halfPS_PKiiiib
.L40:
	.cfi_restore_state
	addq	$56, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2385:
	.size	updateOutput, .-updateOutput
	.globl	_Z57__device_stub__Z16maxPool2d_kernelPK6__halfPS_PKiiiiiiiiiPK6__halfPS_PKiiiiiiiii
	.type	_Z57__device_stub__Z16maxPool2d_kernelPK6__halfPS_PKiiiiiiiiiPK6__halfPS_PKiiiiiiiii, @function
_Z57__device_stub__Z16maxPool2d_kernelPK6__halfPS_PKiiiiiiiiiPK6__halfPS_PKiiiiiiiii:
.LFB2421:
	.cfi_startproc
	endbr64
	subq	$216, %rsp
	.cfi_def_cfa_offset 224
	movl	%ecx, 12(%rsp)
	leaq	56(%rsp), %rcx
	movl	%r8d, 8(%rsp)
	movl	%r9d, 4(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 200(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movq	%rdi, 24(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rax, 112(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	224(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	232(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	240(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	248(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	256(%rsp), %rax
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 40(%rsp)
	leaq	48(%rsp), %rdx
	movq	%rax, 192(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movl	$1, 72(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L43
	pushq	56(%rsp)
	.cfi_def_cfa_offset 232
	leaq	maxPool2d_kernel(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 240
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 232
	popq	%rdx
	.cfi_def_cfa_offset 224
.L43:
	movq	200(%rsp), %rax
	subq	%fs:40, %rax
	je	.L45
	call	__stack_chk_fail@PLT
.L45:
	addq	$216, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2421:
	.size	_Z57__device_stub__Z16maxPool2d_kernelPK6__halfPS_PKiiiiiiiiiPK6__halfPS_PKiiiiiiiii, .-_Z57__device_stub__Z16maxPool2d_kernelPK6__halfPS_PKiiiiiiiiiPK6__halfPS_PKiiiiiiiii
	.globl	maxPool2d_kernel
	.type	maxPool2d_kernel, @function
maxPool2d_kernel:
.LFB2422:
	.cfi_startproc
	endbr64
	jmp	_Z57__device_stub__Z16maxPool2d_kernelPK6__halfPS_PKiiiiiiiiiPK6__halfPS_PKiiiiiiiii
	.cfi_endproc
.LFE2422:
	.size	maxPool2d_kernel, .-maxPool2d_kernel
	.globl	maxPool2d
	.type	maxPool2d, @function
maxPool2d:
.LFB2386:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$72, %rsp
	.cfi_def_cfa_offset 128
	movl	128(%rsp), %eax
	movl	%esi, 52(%rsp)
	movq	%rdx, (%rsp)
	movl	136(%rsp), %r12d
	movl	%eax, 28(%rsp)
	movl	144(%rsp), %r13d
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movl	152(%rsp), %r14d
	movq	%rcx, 8(%rsp)
	movl	160(%rsp), %r15d
	movq	%r8, 16(%rsp)
	movl	168(%rsp), %ebx
	xorl	%r8d, %r8d
	movl	176(%rsp), %ebp
	movl	60(%rsp), %ecx
	movl	%r9d, 24(%rsp)
	xorl	%r9d, %r9d
	movl	%edi, 40(%rsp)
	movq	52(%rsp), %rdx
	movq	%rax, 44(%rsp)
	movq	40(%rsp), %rdi
	movl	48(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L48
	movl	%ebp, 160(%rsp)
	movl	28(%rsp), %r8d
	movl	%r12d, %r9d
	movl	%ebx, 152(%rsp)
	movl	24(%rsp), %ecx
	movl	%r15d, 144(%rsp)
	movq	16(%rsp), %rdx
	movl	%r14d, 136(%rsp)
	movq	8(%rsp), %rsi
	movl	%r13d, 128(%rsp)
	movq	(%rsp), %rdi
	addq	$72, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	_Z57__device_stub__Z16maxPool2d_kernelPK6__halfPS_PKiiiiiiiiiPK6__halfPS_PKiiiiiiiii
.L48:
	.cfi_restore_state
	addq	$72, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2386:
	.size	maxPool2d, .-maxPool2d
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"maxPool2d_kernel"
.LC1:
	.string	"updateOutput_kernel"
.LC2:
	.string	"genXMatrix_kernel"
.LC3:
	.string	"changePropagation_kernel"
.LC4:
	.string	"_Z22changeDetection_kernelPK6__halfPS_Pbiiiiifb"
.LC5:
	.string	"_Z26changeDetection_1x1_kernelPK6__halfPS_Pbiiifb"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2424:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	maxPool2d_kernel(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC1(%rip), %rdx
	orl	$-1, %r8d
	leaq	updateOutput_kernel(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC2(%rip), %rdx
	orl	$-1, %r8d
	leaq	genXMatrix_kernel(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC3(%rip), %rdx
	orl	$-1, %r8d
	leaq	changePropagation_kernel(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC4(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z22changeDetection_kernelPK6__halfPS_Pbiiiiifb(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC5(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z26changeDetection_1x1_kernelPK6__halfPS_Pbiiifb(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2424:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

//Copyright (c) 2018 ETH Zurich, Lukas Cavigelli
#include <math.h>
#include <hip/hip_runtime.h>
#include <hip/hip_fp16.h>

using namespace std;
typedef __half half;


   __global__ void changeDetection_1x1_kernel(
                                         const half* __restrict__ input,
                                         half* __restrict__ inputState,
                                         bool* __restrict__ changeMap,
                                         const int width, const int height, const int nInputPlane,
                                         const float diffThreshold_float,
                                         const bool updateInputState) {

    // compute pixel index
    int pxlInpIdx = blockIdx.x * blockDim.x + threadIdx.x;
    if(pxlInpIdx >= height * width) return;

    //check for changes at the pixel location; any feature map can trigger a change
	half diffThreshold = __float2half(diffThreshold_float);
    bool change = false;
    for (int i = 0; i < nInputPlane; ++i) {
      int idx = i*(height*width) + pxlInpIdx; // !! this expression might need the long datatype for high res
	  half diff = __hsub(inputState[idx], input[idx]);
      change |= __hgt(diff, diffThreshold) | __hlt(diff, __hneg(diffThreshold));
    }

    if(!change) return; // no need to mark outputs/proceed, if not changed

    // mark pixels in the support of the changed pixel for updating
    changeMap[pxlInpIdx] = true;

    //update prevInput if with copyChanges/feedback
    if(updateInputState) { // implicit (&& change), otherwise already returned
      for (int i = 0; i < nInputPlane; ++i) {
        int idx = i*(height*width) + pxlInpIdx; // !! this expression might need the long datatype for high res                                                           
        inputState[idx] = input[idx];
      }
    }
  }
  
  __global__ void changeDetection_kernel(
                                         const half* __restrict__ input,
                                         half* __restrict__ inputState,
                                         bool* __restrict__ changeMap,
                                         const int width, const int height, const int nInputPlane,
                                         const int kHHalf, const int kWHalf, const float diffThreshold_float,
                                         const bool updateInputState) {

    // compute pixel index
    int pxlInpIdx = blockIdx.x * blockDim.x + threadIdx.x;
    if(pxlInpIdx >= height * width) return;

    //check for changes at the pixel location; any feature map can trigger a change
	half diffThreshold = __float2half(diffThreshold_float);
    bool change = false;
    for (int i = 0; i < nInputPlane; ++i) {
      int idx = i*(height*width) + pxlInpIdx; // !! this expression might need the long datatype for high res
	  half diff = __hsub(inputState[idx], input[idx]);
      change |= __hgt(diff, diffThreshold) | __hlt(diff, __hneg(diffThreshold));
    }

    if(!change) return; // no need to mark outputs/proceed, if not changed

    // mark pixels in the support of the changed pixel for updating
    int xIn = pxlInpIdx % width;
    int yIn = pxlInpIdx / width;
    for (int k = -kHHalf; k <= kHHalf; ++k) {
      int yOut = yIn + k;
      for (int l = -kWHalf; l <= kWHalf; ++l) {
        int xOut = xIn + l;
        if(yOut>=0 && yOut<height && xOut>=0 && xOut<width) {
          changeMap[yOut*width + xOut] = true;
        }
      }
    }

    //update prevInput if with copyChanges/feedback
    if(updateInputState) { // implicit (&& change), otherwise already returned
      for (int i = 0; i < nInputPlane; ++i) {
        int idx = i*(height*width) + pxlInpIdx; // !! this expression might need the long datatype for high res                                                           
        inputState[idx] = input[idx];
      }
    }
  }

extern "C" {
  void changeDetection(int gridz, int gridy, int gridx, int blockz, int blocky, int blockx,
                       const half* __restrict__ input,
                       half* __restrict__ oldinput,
                       bool* __restrict__ changeMap,
                       const int width, const int height, const int nInputPlane,
                       const int kHHalf, const int kWHalf, const float diffThreshold,
                       const bool updateInputState) {
    dim3 grid(gridx, gridy, gridz);
    dim3 block(blockx, blocky, blockz);
    
    if(kHHalf == 0 and kWHalf == 0) {      
      changeDetection_1x1_kernel<<<grid, block>>>(input, oldinput, changeMap, width, height,
                                                  nInputPlane, diffThreshold, updateInputState);
    } else {
      changeDetection_kernel<<<grid, block>>>(input, oldinput, changeMap, width, height, 
                                              nInputPlane, kHHalf, kWHalf, diffThreshold, updateInputState);
    }
  }
  __global__ void changePropagation_kernel(const bool* __restrict__ changeMatrixIn,
                                           bool* __restrict__ changeMatrixOut,
                                           const int width, const int height,
                                           const int kHHalf, const int kWHalf) {

    // compute pixel index
    int pxlInpIdx = blockIdx.x * blockDim.x + threadIdx.x;
    if(pxlInpIdx >= height * width) return;

    //check if any pixel in the input range has changed
    bool change = false;
    int xOut = pxlInpIdx % width;
    int yOut = pxlInpIdx / width;
    for (int k = -kHHalf; k <= kHHalf; ++k) {
      int yIn = yOut + k;
      for (int l = -kWHalf; l <= kWHalf; ++l) {
        int xIn = xOut + l;
        if(yIn>=0 && yIn<height && xIn>=0 && xIn<width) {
          change = change || changeMatrixIn[yIn*width + xIn];
        }
      }
    }
    changeMatrixOut[yOut*width + xOut] = change;
  }

  void changePropagation(int gridz, int gridy, int gridx, int blockz, int blocky, int blockx,
                         const bool* __restrict__ changeMatrixIn,
                         bool* __restrict__ changeMatrixOut,
                         const int width, const int height,
                         const int kHHalf, const int kWHalf) {
    dim3 grid(gridx, gridy, gridz);
    dim3 block(blockx, blocky, blockz);
    
    changePropagation_kernel<<<grid, block>>>(changeMatrixIn, changeMatrixOut, 
                                              width, height, kHHalf, kWHalf);
  }

  __global__ void genXMatrix_kernel(
                                    half* columns,
                                    const half* __restrict__ input,
                                    const int* __restrict__ changeList,
                                    const int kW, const int kH,
                                    const int nInputPlane, const int width, const int height,
                                    const int numChanges) {

    const int kx = threadIdx.x;
    const int ky = threadIdx.z;
    const	int changeIdx = blockIdx.x * blockDim.y + threadIdx.y;

    if(changeIdx < numChanges) {
      int pos = changeList[changeIdx];
      int ix = pos % width + kx - (kW-1)/2;
      int iy = pos / width + ky - (kH-1)/2;
      half *dst = columns + changeIdx*(kW*kH*nInputPlane) + ky*kW+kx;

      const bool isInImage = ix>=0 && ix < width && iy>=0 && iy< height;
      for (int i = 0; i < nInputPlane; ++i) {
        dst[i*kH*kW] = isInImage ? input[(i*height + iy) * width + ix] : __float2half(0.0f);
      }
    }
  }

  void genXMatrix(int gridz, int gridy, int gridx, int blockz, int blocky, int blockx,
                  half* columns,
                  const half* __restrict__ input,
                  const int* __restrict__ changeList,
                  const int kW, const int kH,
                  const int nInputPlane, const int width, const int height,
                  const int numChanges) {
    dim3 grid(gridx, gridy, gridz);
    dim3 block(blockx, blocky, blockz);
    genXMatrix_kernel<<<grid, block>>>(columns, input, changeList, kW, kH, nInputPlane, width, height, numChanges);
  }

  __global__ void updateOutput_kernel(const half* __restrict__ columnsOut,
                                      half* output, const int* __restrict__ changeList,
                                      const int numOutputPixel, const int numChanges, const int nOutputPlane, const bool relu) {

    int count = blockIdx.x * blockDim.x + threadIdx.x;

    if(count < numChanges*nOutputPlane) {
      int outpPlane = count / numChanges;
      int changeNr =  count % numChanges;
      int pxl = changeList[changeNr];
      half v = columnsOut[count];
      v = relu && __hle(v, __float2half(0.0f)) ? __float2half(0.0f) : v;
      output[outpPlane*numOutputPixel + pxl] = v;
    }
  }

  void updateOutput(int gridz, int gridy, int gridx, int blockz, int blocky, int blockx,
                    half *columnsOut, half *output, int* changeList, 
                    int numOutputPixel, int numChanges, int nOutputPlane, bool relu) {
    dim3 grid(gridx, gridy, gridz);
    dim3 block(blockx, blocky, blockz);
    updateOutput_kernel<<<grid, block>>>(columnsOut, output, changeList, numOutputPixel, numChanges, nOutputPlane, relu);
  }

  __global__ void maxPool2d_kernel(const half* __restrict__ input,
                                   half* __restrict__ output, 
                                   const int* __restrict__ changeIndexes,
                                   const int numChanges, 
                                   const int numCh, const int iheight, const int iwidth,
                                   const int oheight, const int owidth,
                                   const int stridey, const int stridex) {

    int tid = blockIdx.x * blockDim.x + threadIdx.x;
    if(tid >= numChanges)
      return;
    int pxIdx = changeIndexes[tid];
    int y = pxIdx / iwidth, x = pxIdx % iwidth;
    int yo = y / stridey, xo = x / stridex;

    for(int ch = 0; ch < numCh; ch++) {
      half v = __float2half(-INFINITY);
      for(int j = 0; j < stridey; j++) {
        for(int i = 0; i < stridex; i++) {
          int yi = yo*stridey + j, xi = xo*stridex + i;
          if(yi < iheight && xi < iwidth) {
			half iVal = input[(ch*iheight + yi)*iwidth + xi];
			if (__hgt(iVal, v))
				v = iVal;
          }
        }
      }
      output[(ch*oheight + yo)*owidth + xo] = v;
    }
    
  }

  void maxPool2d(int gridx, int blockx,
                 half *input, half *output, int* changeIndexes, int numChanges, 
                 int numCh, int iheight, int iwidth,
                 int oheight, int owidth,
                 int stridey, int stridex) {
                 
    //determine grid and block size based on number of changes
    dim3 grid(gridx);
    dim3 block(blockx);
    maxPool2d_kernel<<<grid, block>>>(input, output, changeIndexes, numChanges, 
                                      numCh, iheight, iwidth, oheight, owidth, stridey, stridex);
  }

}

	.text
	.file	"cbconv2d_cg_half_backend.hip"
	.globl	_Z41__device_stub__changeDetection_1x1_kernelPK6__halfPS_Pbiiifb # -- Begin function _Z41__device_stub__changeDetection_1x1_kernelPK6__halfPS_Pbiiifb
	.type	_Z41__device_stub__changeDetection_1x1_kernelPK6__halfPS_Pbiiifb,@function
_Z41__device_stub__changeDetection_1x1_kernelPK6__halfPS_Pbiiifb: # @_Z41__device_stub__changeDetection_1x1_kernelPK6__halfPS_Pbiiifb
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movb	208(%rsp), %al
	leaq	56(%rsp), %r10
	movq	%rdi, (%r10)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	20(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	16(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	12(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	8(%rsp), %r9
	movss	%xmm0, (%r9)
	leaq	7(%rsp), %r11
	movb	%al, (%r11)
	leaq	96(%rsp), %rbx
	movq	%r10, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	movq	%r9, 48(%rbx)
	movq	%r11, 56(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z26changeDetection_1x1_kernelPK6__halfPS_Pbiiifb, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z41__device_stub__changeDetection_1x1_kernelPK6__halfPS_Pbiiifb, .Lfunc_end0-_Z41__device_stub__changeDetection_1x1_kernelPK6__halfPS_Pbiiifb
	.cfi_endproc
                                        # -- End function
	.globl	_Z37__device_stub__changeDetection_kernelPK6__halfPS_Pbiiiiifb # -- Begin function _Z37__device_stub__changeDetection_kernelPK6__halfPS_Pbiiiiifb
	.type	_Z37__device_stub__changeDetection_kernelPK6__halfPS_Pbiiiiifb,@function
_Z37__device_stub__changeDetection_kernelPK6__halfPS_Pbiiiiifb: # @_Z37__device_stub__changeDetection_kernelPK6__halfPS_Pbiiiiifb
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$176, %rsp
	.cfi_def_cfa_offset 224
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movb	240(%rsp), %al
	leaq	56(%rsp), %r10
	movq	%rdi, (%r10)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	20(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	16(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	12(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	8(%rsp), %r9
	movss	%xmm0, (%r9)
	leaq	7(%rsp), %r11
	movb	%al, (%r11)
	leaq	96(%rsp), %rbx
	movq	%r10, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	224(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	232(%rsp), %rax
	movq	%rax, 56(%rbx)
	movq	%r9, 64(%rbx)
	movq	%r11, 72(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z22changeDetection_kernelPK6__halfPS_Pbiiiiifb, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$192, %rsp
	.cfi_adjust_cfa_offset -192
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z37__device_stub__changeDetection_kernelPK6__halfPS_Pbiiiiifb, .Lfunc_end1-_Z37__device_stub__changeDetection_kernelPK6__halfPS_Pbiiiiifb
	.cfi_endproc
                                        # -- End function
	.globl	changeDetection                 # -- Begin function changeDetection
	.type	changeDetection,@function
changeDetection:                        # @changeDetection
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	pushq	%rax
	.cfi_def_cfa_offset 64
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movss	%xmm0, 4(%rsp)                  # 4-byte Spill
                                        # kill: def $r8d killed $r8d def $r8
                                        # kill: def $esi killed $esi def $rsi
	movl	%edi, %eax
	movb	128(%rsp), %r14b
	movl	120(%rsp), %ebp
	movl	112(%rsp), %ebx
	movq	80(%rsp), %r15
	movq	72(%rsp), %r12
	movq	64(%rsp), %r13
	movl	%edx, %edi
	shlq	$32, %rsi
	orq	%rsi, %rdi
	movl	%r9d, %edx
	shlq	$32, %r8
	orq	%r8, %rdx
	movl	%eax, %esi
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	movl	%ebp, %ecx
	orl	%ebx, %ecx
	je	.LBB2_1
# %bb.3:
	testl	%eax, %eax
	jne	.LBB2_5
# %bb.4:
	subq	$8, %rsp
	.cfi_adjust_cfa_offset 8
	movzbl	%r14b, %eax
	movq	%r13, %rdi
	movq	%r12, %rsi
	movq	%r15, %rdx
	movl	96(%rsp), %ecx
	movl	104(%rsp), %r8d
	movl	112(%rsp), %r9d
	movss	12(%rsp), %xmm0                 # 4-byte Reload
                                        # xmm0 = mem[0],zero,zero,zero
	pushq	%rax
	.cfi_adjust_cfa_offset 8
	pushq	%rbp
	.cfi_adjust_cfa_offset 8
	pushq	%rbx
	.cfi_adjust_cfa_offset 8
	callq	_Z37__device_stub__changeDetection_kernelPK6__halfPS_Pbiiiiifb
	addq	$40, %rsp
	.cfi_adjust_cfa_offset -40
	jmp	.LBB2_6
.LBB2_1:
	.cfi_def_cfa_offset 64
	testl	%eax, %eax
	je	.LBB2_2
.LBB2_5:
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
.LBB2_6:
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB2_2:
	.cfi_def_cfa_offset 64
	subq	$8, %rsp
	.cfi_adjust_cfa_offset 8
	movzbl	%r14b, %eax
	movq	%r13, %rdi
	movq	%r12, %rsi
	movq	%r15, %rdx
	movl	96(%rsp), %ecx
	movl	104(%rsp), %r8d
	movl	112(%rsp), %r9d
	movss	12(%rsp), %xmm0                 # 4-byte Reload
                                        # xmm0 = mem[0],zero,zero,zero
	pushq	%rax
	.cfi_adjust_cfa_offset 8
	callq	_Z41__device_stub__changeDetection_1x1_kernelPK6__halfPS_Pbiiifb
	addq	$24, %rsp
	.cfi_adjust_cfa_offset -24
	jmp	.LBB2_6
.Lfunc_end2:
	.size	changeDetection, .Lfunc_end2-changeDetection
	.cfi_endproc
                                        # -- End function
	.globl	__device_stub__changePropagation_kernel # -- Begin function __device_stub__changePropagation_kernel
	.type	__device_stub__changePropagation_kernel,@function
__device_stub__changePropagation_kernel: # @__device_stub__changePropagation_kernel
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	4(%rsp), %rcx
	movl	%r8d, (%rcx)
	movq	%rsp, %r8
	movl	%r9d, (%r8)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$changePropagation_kernel, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	__device_stub__changePropagation_kernel, .Lfunc_end3-__device_stub__changePropagation_kernel
	.cfi_endproc
                                        # -- End function
	.globl	changePropagation               # -- Begin function changePropagation
	.type	changePropagation,@function
changePropagation:                      # @changePropagation
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	pushq	%rax
	.cfi_def_cfa_offset 64
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
                                        # kill: def $r8d killed $r8d def $r8
                                        # kill: def $esi killed $esi def $rsi
	movl	%edi, %eax
	movl	104(%rsp), %ebx
	movl	96(%rsp), %ebp
	movl	88(%rsp), %r14d
	movl	80(%rsp), %r15d
	movq	72(%rsp), %r12
	movq	64(%rsp), %r13
	movl	%edx, %edi
	shlq	$32, %rsi
	orq	%rsi, %rdi
	movl	%r9d, %edx
	shlq	$32, %r8
	orq	%r8, %rdx
	movl	%eax, %esi
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	je	.LBB4_2
# %bb.1:
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB4_2:
	.cfi_def_cfa_offset 64
	movq	%r13, %rdi
	movq	%r12, %rsi
	movl	%r15d, %edx
	movl	%r14d, %ecx
	movl	%ebp, %r8d
	movl	%ebx, %r9d
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	__device_stub__changePropagation_kernel # TAILCALL
.Lfunc_end4:
	.size	changePropagation, .Lfunc_end4-changePropagation
	.cfi_endproc
                                        # -- End function
	.globl	__device_stub__genXMatrix_kernel # -- Begin function __device_stub__genXMatrix_kernel
	.type	__device_stub__genXMatrix_kernel,@function
__device_stub__genXMatrix_kernel:       # @__device_stub__genXMatrix_kernel
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$176, %rsp
	.cfi_def_cfa_offset 224
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	20(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	16(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	12(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	224(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	232(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	240(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$genXMatrix_kernel, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$192, %rsp
	.cfi_adjust_cfa_offset -192
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end5:
	.size	__device_stub__genXMatrix_kernel, .Lfunc_end5-__device_stub__genXMatrix_kernel
	.cfi_endproc
                                        # -- End function
	.globl	genXMatrix                      # -- Begin function genXMatrix
	.type	genXMatrix,@function
genXMatrix:                             # @genXMatrix
	.cfi_startproc
# %bb.0:
	pushq	%rax
	.cfi_def_cfa_offset 16
                                        # kill: def $r8d killed $r8d def $r8
                                        # kill: def $esi killed $esi def $rsi
	movl	%edi, %eax
	movl	%edx, %edi
	shlq	$32, %rsi
	orq	%rsi, %rdi
	movl	%r9d, %edx
	shlq	$32, %r8
	orq	%r8, %rdx
	movl	%eax, %esi
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB6_2
# %bb.1:
	movl	80(%rsp), %eax
	movl	72(%rsp), %r10d
	movl	64(%rsp), %r11d
	movl	56(%rsp), %r9d
	movl	48(%rsp), %r8d
	movl	40(%rsp), %ecx
	movq	32(%rsp), %rdx
	movq	24(%rsp), %rsi
	movq	16(%rsp), %rdi
	subq	$8, %rsp
	.cfi_adjust_cfa_offset 8
	pushq	%rax
	.cfi_adjust_cfa_offset 8
	pushq	%r10
	.cfi_adjust_cfa_offset 8
	pushq	%r11
	.cfi_adjust_cfa_offset 8
	callq	__device_stub__genXMatrix_kernel
	addq	$32, %rsp
	.cfi_adjust_cfa_offset -32
.LBB6_2:
	popq	%rax
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end6:
	.size	genXMatrix, .Lfunc_end6-genXMatrix
	.cfi_endproc
                                        # -- End function
	.globl	__device_stub__updateOutput_kernel # -- Begin function __device_stub__updateOutput_kernel
	.type	__device_stub__updateOutput_kernel,@function
__device_stub__updateOutput_kernel:     # @__device_stub__updateOutput_kernel
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movb	208(%rsp), %al
	leaq	56(%rsp), %r10
	movq	%rdi, (%r10)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	20(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	16(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	12(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	11(%rsp), %r9
	movb	%al, (%r9)
	leaq	96(%rsp), %rbx
	movq	%r10, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	movq	%r9, 48(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$updateOutput_kernel, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end7:
	.size	__device_stub__updateOutput_kernel, .Lfunc_end7-__device_stub__updateOutput_kernel
	.cfi_endproc
                                        # -- End function
	.globl	updateOutput                    # -- Begin function updateOutput
	.type	updateOutput,@function
updateOutput:                           # @updateOutput
	.cfi_startproc
# %bb.0:
	pushq	%rax
	.cfi_def_cfa_offset 16
                                        # kill: def $r8d killed $r8d def $r8
                                        # kill: def $esi killed $esi def $rsi
	movl	%edi, %eax
	movl	%edx, %edi
	shlq	$32, %rsi
	orq	%rsi, %rdi
	movl	%r9d, %edx
	shlq	$32, %r8
	orq	%r8, %rdx
	movl	%eax, %esi
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB8_2
# %bb.1:
	movl	56(%rsp), %r9d
	movl	48(%rsp), %r8d
	movl	40(%rsp), %ecx
	movq	32(%rsp), %rdx
	movq	24(%rsp), %rsi
	movq	16(%rsp), %rdi
	movzbl	64(%rsp), %eax
	movl	%eax, (%rsp)
	callq	__device_stub__updateOutput_kernel
.LBB8_2:
	popq	%rax
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end8:
	.size	updateOutput, .Lfunc_end8-updateOutput
	.cfi_endproc
                                        # -- End function
	.globl	__device_stub__maxPool2d_kernel # -- Begin function __device_stub__maxPool2d_kernel
	.type	__device_stub__maxPool2d_kernel,@function
__device_stub__maxPool2d_kernel:        # @__device_stub__maxPool2d_kernel
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$192, %rsp
	.cfi_def_cfa_offset 240
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	20(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	16(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	12(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	240(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	248(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	256(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	264(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	272(%rsp), %rax
	movq	%rax, 80(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$maxPool2d_kernel, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$208, %rsp
	.cfi_adjust_cfa_offset -208
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end9:
	.size	__device_stub__maxPool2d_kernel, .Lfunc_end9-__device_stub__maxPool2d_kernel
	.cfi_endproc
                                        # -- End function
	.globl	maxPool2d                       # -- Begin function maxPool2d
	.type	maxPool2d,@function
maxPool2d:                              # @maxPool2d
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	pushq	%rax
	.cfi_def_cfa_offset 64
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%r9d, %ebx
	movq	%r8, %r14
	movq	%rcx, %r15
	movq	%rdx, %r12
	movl	%edi, %edi
	btsq	$32, %rdi
	movl	%esi, %edx
	btsq	$32, %rdx
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	je	.LBB10_1
# %bb.2:
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	jmp	.LBB10_3
.LBB10_1:
	.cfi_def_cfa_offset 64
	movl	112(%rsp), %eax
	movl	104(%rsp), %r10d
	movl	96(%rsp), %r11d
	movl	88(%rsp), %r13d
	movl	80(%rsp), %ebp
	movl	72(%rsp), %r9d
	movl	64(%rsp), %r8d
	subq	$8, %rsp
	.cfi_adjust_cfa_offset 8
	movq	%r12, %rdi
	movq	%r15, %rsi
	movq	%r14, %rdx
	movl	%ebx, %ecx
	pushq	%rax
	.cfi_adjust_cfa_offset 8
	pushq	%r10
	.cfi_adjust_cfa_offset 8
	pushq	%r11
	.cfi_adjust_cfa_offset 8
	pushq	%r13
	.cfi_adjust_cfa_offset 8
	pushq	%rbp
	.cfi_adjust_cfa_offset 8
	callq	__device_stub__maxPool2d_kernel
	addq	$56, %rsp
	.cfi_adjust_cfa_offset -56
.LBB10_3:
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end10:
	.size	maxPool2d, .Lfunc_end10-maxPool2d
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB11_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB11_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z26changeDetection_1x1_kernelPK6__halfPS_Pbiiifb, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z22changeDetection_kernelPK6__halfPS_Pbiiiiifb, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$changePropagation_kernel, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$genXMatrix_kernel, %esi
	movl	$.L__unnamed_4, %edx
	movl	$.L__unnamed_4, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$updateOutput_kernel, %esi
	movl	$.L__unnamed_5, %edx
	movl	$.L__unnamed_5, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$maxPool2d_kernel, %esi
	movl	$.L__unnamed_6, %edx
	movl	$.L__unnamed_6, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end11:
	.size	__hip_module_ctor, .Lfunc_end11-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB12_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB12_2:
	retq
.Lfunc_end12:
	.size	__hip_module_dtor, .Lfunc_end12-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z26changeDetection_1x1_kernelPK6__halfPS_Pbiiifb,@object # @_Z26changeDetection_1x1_kernelPK6__halfPS_Pbiiifb
	.section	.rodata,"a",@progbits
	.globl	_Z26changeDetection_1x1_kernelPK6__halfPS_Pbiiifb
	.p2align	3, 0x0
_Z26changeDetection_1x1_kernelPK6__halfPS_Pbiiifb:
	.quad	_Z41__device_stub__changeDetection_1x1_kernelPK6__halfPS_Pbiiifb
	.size	_Z26changeDetection_1x1_kernelPK6__halfPS_Pbiiifb, 8

	.type	_Z22changeDetection_kernelPK6__halfPS_Pbiiiiifb,@object # @_Z22changeDetection_kernelPK6__halfPS_Pbiiiiifb
	.globl	_Z22changeDetection_kernelPK6__halfPS_Pbiiiiifb
	.p2align	3, 0x0
_Z22changeDetection_kernelPK6__halfPS_Pbiiiiifb:
	.quad	_Z37__device_stub__changeDetection_kernelPK6__halfPS_Pbiiiiifb
	.size	_Z22changeDetection_kernelPK6__halfPS_Pbiiiiifb, 8

	.type	changePropagation_kernel,@object # @changePropagation_kernel
	.globl	changePropagation_kernel
	.p2align	3, 0x0
changePropagation_kernel:
	.quad	__device_stub__changePropagation_kernel
	.size	changePropagation_kernel, 8

	.type	genXMatrix_kernel,@object       # @genXMatrix_kernel
	.globl	genXMatrix_kernel
	.p2align	3, 0x0
genXMatrix_kernel:
	.quad	__device_stub__genXMatrix_kernel
	.size	genXMatrix_kernel, 8

	.type	updateOutput_kernel,@object     # @updateOutput_kernel
	.globl	updateOutput_kernel
	.p2align	3, 0x0
updateOutput_kernel:
	.quad	__device_stub__updateOutput_kernel
	.size	updateOutput_kernel, 8

	.type	maxPool2d_kernel,@object        # @maxPool2d_kernel
	.globl	maxPool2d_kernel
	.p2align	3, 0x0
maxPool2d_kernel:
	.quad	__device_stub__maxPool2d_kernel
	.size	maxPool2d_kernel, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z26changeDetection_1x1_kernelPK6__halfPS_Pbiiifb"
	.size	.L__unnamed_1, 50

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z22changeDetection_kernelPK6__halfPS_Pbiiiiifb"
	.size	.L__unnamed_2, 48

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"changePropagation_kernel"
	.size	.L__unnamed_3, 25

	.type	.L__unnamed_4,@object           # @3
.L__unnamed_4:
	.asciz	"genXMatrix_kernel"
	.size	.L__unnamed_4, 18

	.type	.L__unnamed_5,@object           # @4
.L__unnamed_5:
	.asciz	"updateOutput_kernel"
	.size	.L__unnamed_5, 20

	.type	.L__unnamed_6,@object           # @5
.L__unnamed_6:
	.asciz	"maxPool2d_kernel"
	.size	.L__unnamed_6, 17

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z41__device_stub__changeDetection_1x1_kernelPK6__halfPS_Pbiiifb
	.addrsig_sym _Z37__device_stub__changeDetection_kernelPK6__halfPS_Pbiiiiifb
	.addrsig_sym __device_stub__changePropagation_kernel
	.addrsig_sym __device_stub__genXMatrix_kernel
	.addrsig_sym __device_stub__updateOutput_kernel
	.addrsig_sym __device_stub__maxPool2d_kernel
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z26changeDetection_1x1_kernelPK6__halfPS_Pbiiifb
	.addrsig_sym _Z22changeDetection_kernelPK6__halfPS_Pbiiiiifb
	.addrsig_sym changePropagation_kernel
	.addrsig_sym genXMatrix_kernel
	.addrsig_sym updateOutput_kernel
	.addrsig_sym maxPool2d_kernel
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z26changeDetection_1x1_kernelPK6__halfPS_Pbiiifb ; -- Begin function _Z26changeDetection_1x1_kernelPK6__halfPS_Pbiiifb
	.globl	_Z26changeDetection_1x1_kernelPK6__halfPS_Pbiiifb
	.p2align	8
	.type	_Z26changeDetection_1x1_kernelPK6__halfPS_Pbiiifb,@function
_Z26changeDetection_1x1_kernelPK6__halfPS_Pbiiifb: ; @_Z26changeDetection_1x1_kernelPK6__halfPS_Pbiiifb
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x3c
	s_load_b128 s[4:7], s[0:1], 0x18
	s_mov_b32 s3, exec_lo
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mul_i32 s2, s5, s4
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_cmpx_gt_i32_e64 s2, v1
	s_cbranch_execz .LBB0_7
; %bb.1:
	s_load_b32 s3, s[0:1], 0x28
	s_cmp_lt_i32 s6, 1
	s_cbranch_scc1 .LBB0_7
; %bb.2:                                ; %.lr.ph
	s_clause 0x1
	s_load_b128 s[8:11], s[0:1], 0x0
	s_load_b64 s[0:1], s[0:1], 0x10
	v_cvt_f16_f32_e32 v0, s7
	v_mov_b32_e32 v2, v1
	s_mov_b32 s4, 0
	s_mov_b32 s5, s6
                                        ; implicit-def: $sgpr7
.LBB0_3:                                ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	s_and_not1_b32 s7, s7, exec_lo
	s_add_i32 s5, s5, -1
	v_lshlrev_b64 v[3:4], 1, v[2:3]
	v_add_nc_u32_e32 v2, s2, v2
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v5, vcc_lo, s10, v3
	v_add_co_ci_u32_e32 v6, vcc_lo, s11, v4, vcc_lo
	v_add_co_u32 v3, vcc_lo, s8, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s9, v4, vcc_lo
	global_load_u16 v5, v[5:6], off
	global_load_u16 v3, v[3:4], off
	s_waitcnt vmcnt(0)
	v_sub_f16_e32 v3, v5, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_gt_f16_e32 vcc_lo, v3, v0
	v_cmp_lt_f16_e64 s12, v3, -v0
	s_or_b32 s12, vcc_lo, s12
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s4, s4, s12
	s_and_b32 s12, s4, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s7, s7, s12
	s_cmp_eq_u32 s5, 0
	s_cbranch_scc0 .LBB0_3
; %bb.4:                                ; %._crit_edge
	s_and_b32 exec_lo, exec_lo, s7
	s_cbranch_execz .LBB0_7
; %bb.5:
	v_ashrrev_i32_e32 v0, 31, v1
	v_add_co_u32 v2, vcc_lo, s0, v1
	s_bitcmp0_b32 s3, 0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v0, vcc_lo
	v_mov_b32_e32 v0, 1
	global_store_b8 v[2:3], v0, off
	s_cbranch_scc1 .LBB0_7
.LBB0_6:                                ; %.lr.ph53
                                        ; =>This Inner Loop Header: Depth=1
	v_ashrrev_i32_e32 v2, 31, v1
	s_add_i32 s6, s6, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_cmp_lg_u32 s6, 0
	v_lshlrev_b64 v[2:3], 1, v[1:2]
	v_add_nc_u32_e32 v1, s2, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v4, vcc_lo, s8, v2
	v_add_co_ci_u32_e32 v5, vcc_lo, s9, v3, vcc_lo
	v_add_co_u32 v2, vcc_lo, s10, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s11, v3, vcc_lo
	global_load_u16 v0, v[4:5], off
	s_waitcnt vmcnt(0)
	global_store_b16 v[2:3], v0, off
	s_cbranch_scc1 .LBB0_6
.LBB0_7:                                ; %.loopexit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z26changeDetection_1x1_kernelPK6__halfPS_Pbiiifb
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 304
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 7
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z26changeDetection_1x1_kernelPK6__halfPS_Pbiiifb, .Lfunc_end0-_Z26changeDetection_1x1_kernelPK6__halfPS_Pbiiifb
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 392
; NumSgprs: 18
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z22changeDetection_kernelPK6__halfPS_Pbiiiiifb ; -- Begin function _Z22changeDetection_kernelPK6__halfPS_Pbiiiiifb
	.globl	_Z22changeDetection_kernelPK6__halfPS_Pbiiiiifb
	.p2align	8
	.type	_Z22changeDetection_kernelPK6__halfPS_Pbiiiiifb,@function
_Z22changeDetection_kernelPK6__halfPS_Pbiiiiifb: ; @_Z22changeDetection_kernelPK6__halfPS_Pbiiiiifb
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x44
	s_load_b128 s[8:11], s[0:1], 0x18
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_mul_i32 s3, s9, s8
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e64 s3, v1
	s_cbranch_execz .LBB1_16
; %bb.1:
	s_load_b128 s[12:15], s[0:1], 0x28
	s_cmp_lt_i32 s10, 1
	s_cbranch_scc1 .LBB1_16
; %bb.2:                                ; %.lr.ph
	s_clause 0x1
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b64 s[16:17], s[0:1], 0x10
	s_waitcnt lgkmcnt(0)
	v_cvt_f16_f32_e32 v0, s13
	v_mov_b32_e32 v2, v1
	s_mov_b32 s0, 0
	s_mov_b32 s1, s10
                                        ; implicit-def: $sgpr2
.LBB1_3:                                ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	s_and_not1_b32 s2, s2, exec_lo
	s_add_i32 s1, s1, -1
	v_lshlrev_b64 v[3:4], 1, v[2:3]
	v_add_nc_u32_e32 v2, s3, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v5, vcc_lo, s6, v3
	v_add_co_ci_u32_e32 v6, vcc_lo, s7, v4, vcc_lo
	v_add_co_u32 v3, vcc_lo, s4, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
	global_load_u16 v5, v[5:6], off
	global_load_u16 v3, v[3:4], off
	s_waitcnt vmcnt(0)
	v_sub_f16_e32 v3, v5, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_gt_f16_e32 vcc_lo, v3, v0
	v_cmp_lt_f16_e64 s13, v3, -v0
	s_or_b32 s13, vcc_lo, s13
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s0, s0, s13
	s_and_b32 s13, s0, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s2, s2, s13
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc0 .LBB1_3
; %bb.4:                                ; %._crit_edge
	s_and_b32 exec_lo, exec_lo, s2
	s_cbranch_execz .LBB1_16
; %bb.5:
	s_cmp_lt_i32 s11, 0
	s_cbranch_scc1 .LBB1_13
; %bb.6:                                ; %.lr.ph93
	s_ashr_i32 s0, s8, 31
	v_ashrrev_i32_e32 v3, 31, v1
	s_add_i32 s1, s8, s0
	s_sub_i32 s13, 0, s11
	s_xor_b32 s1, s1, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v4, v1, v3
	v_cvt_f32_u32_e32 v0, s1
	s_sub_i32 s2, 0, s1
	s_cmp_gt_i32 s12, -1
	v_xor_b32_e32 v4, v4, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_rcp_iflag_f32_e32 v0, v0
	v_xor_b32_e32 v3, s0, v3
	s_mul_i32 s0, s11, s8
	s_cselect_b32 s15, -1, 0
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v0, 0x4f7ffffe, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v0, v0
	v_mul_lo_u32 v2, s2, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v2, v0, v2
	v_add_nc_u32_e32 v0, v0, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v0, v4, v0
	v_mul_lo_u32 v2, v0, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v2, v4, v2
	v_add_nc_u32_e32 v4, 1, v0
	v_subrev_nc_u32_e32 v5, s1, v2
	v_cmp_le_u32_e32 vcc_lo, s1, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v0, v0, v4, vcc_lo
	v_cndmask_b32_e32 v2, v2, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v4, 1, v0
	v_cmp_le_u32_e32 vcc_lo, s1, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v0, v0, v4, vcc_lo
	v_xor_b32_e32 v0, v0, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v0, v0, v3
	v_subrev_nc_u32_e32 v3, s0, v1
	s_lshl_b32 s0, s12, 1
	v_mul_lo_u32 v2, v0, s8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v4, v1, v2
	v_subrev_nc_u32_e32 v2, s12, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_subrev_nc_u32_e32 v3, s12, v4
	v_mov_b32_e32 v4, 1
	s_or_b32 s12, s0, 1
.LBB1_7:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB1_9 Depth 2
	s_and_not1_b32 vcc_lo, exec_lo, s15
	s_cbranch_vccnz .LBB1_12
; %bb.8:                                ; %.lr.ph88
                                        ;   in Loop: Header=BB1_7 Depth=1
	v_dual_mov_b32 v5, v2 :: v_dual_add_nc_u32 v6, s13, v0
	s_mov_b32 s18, s12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_lt_i32_e32 vcc_lo, -1, v6
	v_cmp_gt_i32_e64 s0, s9, v6
	v_mov_b32_e32 v6, v3
.LBB1_9:                                ;   Parent Loop BB1_7 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cmp_lt_i32_e64 s1, -1, v6
	v_cmp_gt_i32_e64 s2, s8, v6
	s_and_b32 s1, s0, s1
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	s_and_b32 s1, s1, s2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s1, vcc_lo, s1
	s_and_saveexec_b32 s2, s1
	s_cbranch_execz .LBB1_11
; %bb.10:                               ;   in Loop: Header=BB1_9 Depth=2
	v_ashrrev_i32_e32 v8, 31, v5
	v_add_co_u32 v7, s1, s16, v5
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v8, s1, s17, v8, s1
	global_store_b8 v[7:8], v4, off
.LBB1_11:                               ;   in Loop: Header=BB1_9 Depth=2
	s_or_b32 exec_lo, exec_lo, s2
	v_add_nc_u32_e32 v6, 1, v6
	v_add_nc_u32_e32 v5, 1, v5
	s_add_i32 s18, s18, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s18, 0
	s_cbranch_scc0 .LBB1_9
.LBB1_12:                               ; %._crit_edge89
                                        ;   in Loop: Header=BB1_7 Depth=1
	v_add_nc_u32_e32 v2, s8, v2
	s_add_i32 s0, s13, 1
	s_cmp_eq_u32 s13, s11
	s_mov_b32 s13, s0
	s_cbranch_scc0 .LBB1_7
.LBB1_13:                               ; %._crit_edge94
	s_bitcmp0_b32 s14, 0
	s_cbranch_scc1 .LBB1_16
; %bb.14:                               ; %.lr.ph96.preheader
	s_max_i32 s0, s10, 1
.LBB1_15:                               ; %.lr.ph96
                                        ; =>This Inner Loop Header: Depth=1
	v_ashrrev_i32_e32 v2, 31, v1
	s_add_i32 s0, s0, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_cmp_lg_u32 s0, 0
	v_lshlrev_b64 v[2:3], 1, v[1:2]
	v_add_nc_u32_e32 v1, s3, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v4, vcc_lo, s4, v2
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
	v_add_co_u32 v2, vcc_lo, s6, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
	global_load_u16 v0, v[4:5], off
	s_waitcnt vmcnt(0)
	global_store_b16 v[2:3], v0, off
	s_cbranch_scc1 .LBB1_15
.LBB1_16:                               ; %.loopexit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z22changeDetection_kernelPK6__halfPS_Pbiiiiifb
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 312
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 9
		.amdhsa_next_free_sgpr 19
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z22changeDetection_kernelPK6__halfPS_Pbiiiiifb, .Lfunc_end1-_Z22changeDetection_kernelPK6__halfPS_Pbiiiiifb
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 772
; NumSgprs: 21
; NumVgprs: 9
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 21
; NumVGPRsForWavesPerEU: 9
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	changePropagation_kernel ; -- Begin function changePropagation_kernel
	.globl	changePropagation_kernel
	.p2align	8
	.type	changePropagation_kernel,@function
changePropagation_kernel:               ; @changePropagation_kernel
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x2c
	s_load_b128 s[4:7], s[0:1], 0x10
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mul_i32 s2, s5, s4
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_cmp_gt_i32_e32 vcc_lo, s2, v1
	s_and_saveexec_b32 s2, vcc_lo
	s_cbranch_execz .LBB2_14
; %bb.1:
	s_load_b64 s[8:9], s[0:1], 0x8
	v_ashrrev_i32_e32 v0, 31, v1
	s_cmp_lt_i32 s6, 0
	s_mov_b32 s13, 0
	s_cbranch_scc1 .LBB2_13
; %bb.2:                                ; %.lr.ph61
	s_ashr_i32 s2, s4, 31
	v_add_nc_u32_e32 v4, v1, v0
	s_add_i32 s3, s4, s2
	s_sub_i32 s12, 0, s6
	s_xor_b32 s3, s3, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v4, v4, v0
	v_cvt_f32_u32_e32 v2, s3
	s_sub_i32 s10, 0, s3
	s_cmp_gt_i32 s7, -1
	v_rcp_iflag_f32_e32 v2, v2
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v2, 0x4f7ffffe, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v2, v2
	v_mul_lo_u32 v3, s10, v2
	s_load_b64 s[10:11], s[0:1], 0x0
	s_mul_i32 s0, s6, s4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v3, v2, v3
	v_add_nc_u32_e32 v2, v2, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v2, v4, v2
	v_mul_lo_u32 v3, v2, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v3, v4, v3
	v_add_nc_u32_e32 v4, 1, v2
	v_subrev_nc_u32_e32 v5, s3, v3
	v_cmp_le_u32_e32 vcc_lo, s3, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v3, v3, v5 :: v_dual_cndmask_b32 v2, v2, v4
	v_xor_b32_e32 v5, s2, v0
	v_cmp_le_u32_e32 vcc_lo, s3, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v4, 1, v2
	s_cselect_b32 s3, -1, 0
	v_cndmask_b32_e32 v2, v2, v4, vcc_lo
	v_subrev_nc_u32_e32 v4, s0, v1
	s_lshl_b32 s0, s7, 1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v2, v2, v5
	v_sub_nc_u32_e32 v2, v2, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v3, v2, s4
	v_sub_nc_u32_e32 v5, v1, v3
	v_subrev_nc_u32_e32 v3, s7, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_subrev_nc_u32_e32 v4, s7, v5
	s_or_b32 s7, s0, 1
.LBB2_3:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB2_5 Depth 2
	s_and_not1_b32 s0, s13, exec_lo
	s_and_b32 s1, s13, exec_lo
	s_and_not1_b32 vcc_lo, exec_lo, s3
	s_or_b32 s14, s0, s1
	s_cbranch_vccnz .LBB2_11
; %bb.4:                                ; %.lr.ph
                                        ;   in Loop: Header=BB2_3 Depth=1
	v_dual_mov_b32 v5, v3 :: v_dual_add_nc_u32 v6, s12, v2
	s_mov_b32 s15, s7
                                        ; implicit-def: $sgpr16
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_lt_i32_e32 vcc_lo, -1, v6
	v_cmp_le_i32_e64 s0, s5, v6
	v_mov_b32_e32 v6, v4
.LBB2_5:                                ;   Parent Loop BB2_3 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_and_not1_b32 s1, s16, exec_lo
	s_and_b32 s2, s13, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s16, s1, s2
	s_and_saveexec_b32 s17, vcc_lo
	s_cbranch_execz .LBB2_9
; %bb.6:                                ;   in Loop: Header=BB2_5 Depth=2
	v_cmp_gt_i32_e64 s1, 0, v6
	v_cmp_le_i32_e64 s2, s4, v6
	s_delay_alu instid0(VALU_DEP_2)
	s_or_b32 s1, s0, s1
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	s_or_b32 s1, s1, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s2, s1, s13
	s_xor_b32 s1, s1, -1
	s_xor_b32 s18, s2, -1
	s_or_b32 s2, s1, s13
	s_and_saveexec_b32 s13, s18
	s_cbranch_execz .LBB2_8
; %bb.7:                                ;   in Loop: Header=BB2_5 Depth=2
	v_ashrrev_i32_e32 v8, 31, v5
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v7, s1, s10, v5
	s_and_not1_b32 s2, s2, exec_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e64 v8, s1, s11, v8, s1
	global_load_u8 v7, v[7:8], off
	s_waitcnt vmcnt(0)
	v_cmp_ne_u16_e64 s1, 0, v7
	s_and_b32 s1, s1, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s2, s2, s1
.LBB2_8:                                ; %Flow
                                        ;   in Loop: Header=BB2_5 Depth=2
	s_or_b32 exec_lo, exec_lo, s13
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_and_not1_b32 s1, s16, exec_lo
	s_and_b32 s2, s2, exec_lo
                                        ; implicit-def: $sgpr13
	s_or_b32 s16, s1, s2
.LBB2_9:                                ;   in Loop: Header=BB2_5 Depth=2
	s_or_b32 exec_lo, exec_lo, s17
	v_add_nc_u32_e32 v6, 1, v6
	s_and_not1_b32 s2, s13, exec_lo
	s_and_b32 s1, s16, exec_lo
	v_add_nc_u32_e32 v5, 1, v5
	s_add_i32 s15, s15, -1
	s_or_b32 s13, s2, s1
	s_cmp_eq_u32 s15, 0
	s_cbranch_scc0 .LBB2_5
; %bb.10:                               ; %Flow81
                                        ;   in Loop: Header=BB2_3 Depth=1
	s_and_not1_b32 s0, s14, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s13, s0, s1
	s_branch .LBB2_12
.LBB2_11:                               ;   in Loop: Header=BB2_3 Depth=1
	s_mov_b32 s13, s14
.LBB2_12:                               ; %._crit_edge
                                        ;   in Loop: Header=BB2_3 Depth=1
	v_add_nc_u32_e32 v3, s4, v3
	s_add_i32 s0, s12, 1
	s_cmp_eq_u32 s12, s6
	s_mov_b32 s12, s0
	s_cbranch_scc0 .LBB2_3
.LBB2_13:                               ; %Flow84
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v1, vcc_lo, s8, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s9, v0, vcc_lo
	v_cndmask_b32_e64 v0, 0, 1, s13
	global_store_b8 v[1:2], v0, off
.LBB2_14:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel changePropagation_kernel
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 9
		.amdhsa_next_free_sgpr 19
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	changePropagation_kernel, .Lfunc_end2-changePropagation_kernel
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 656
; NumSgprs: 21
; NumVgprs: 9
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 21
; NumVGPRsForWavesPerEU: 9
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	genXMatrix_kernel       ; -- Begin function genXMatrix_kernel
	.globl	genXMatrix_kernel
	.p2align	8
	.type	genXMatrix_kernel,@function
genXMatrix_kernel:                      ; @genXMatrix_kernel
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x3c
	s_load_b64 s[12:13], s[0:1], 0x28
	v_bfe_u32 v3, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s2, s2, 16
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
	s_mov_b32 s2, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e64 s13, v1
	s_cbranch_execz .LBB3_6
; %bb.1:
	s_load_b128 s[4:7], s[0:1], 0x18
	s_waitcnt lgkmcnt(0)
	s_cmp_lt_i32 s6, 1
	s_cbranch_scc1 .LBB3_6
; %bb.2:                                ; %.lr.ph.preheader
	s_load_b64 s[2:3], s[0:1], 0x10
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[1:2]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v2, vcc_lo, s2, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
	s_ashr_i32 s2, s7, 31
	s_add_i32 s3, s7, s2
	global_load_b32 v4, v[2:3], off
	s_xor_b32 s3, s3, s2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cvt_f32_u32_e32 v2, s3
	s_sub_i32 s8, 0, s3
	v_rcp_iflag_f32_e32 v2, v2
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v2, 0x4f7ffffe, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v2, v2
	v_mul_lo_u32 v3, s8, v2
	s_load_b128 s[8:11], s[0:1], 0x0
	s_add_i32 s0, s4, -1
	s_add_i32 s1, s5, -1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v3, v2, v3
	v_add_nc_u32_e32 v2, v2, v3
	s_waitcnt vmcnt(0)
	v_ashrrev_i32_e32 v5, 31, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v6, v4, v5
	v_xor_b32_e32 v3, v6, v5
	v_xor_b32_e32 v5, s2, v5
	s_lshr_b32 s2, s0, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	s_add_i32 s0, s0, s2
	v_mul_hi_u32 v2, v3, v2
	s_ashr_i32 s0, s0, 1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v6, v2, s3
	v_sub_nc_u32_e32 v3, v3, v6
	v_add_nc_u32_e32 v6, 1, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v7, s3, v3
	v_cmp_le_u32_e32 vcc_lo, s3, v3
	v_dual_cndmask_b32 v3, v3, v7 :: v_dual_cndmask_b32 v2, v2, v6
	v_and_b32_e32 v7, 0x3ff, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_le_u32_e32 vcc_lo, s3, v3
	v_add_nc_u32_e32 v6, 1, v2
	s_mul_i32 s3, s5, s4
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_lshlrev_b32_e32 v8, 1, v7
	v_subrev_nc_u32_e32 v10, s0, v7
	v_dual_cndmask_b32 v2, v2, v6 :: v_dual_add_nc_u32 v7, v4, v7
	s_mul_i32 s5, s3, s6
	v_bfe_u32 v6, v0, 20, 10
	v_mul_lo_u32 v0, s5, v1
	s_lshr_b32 s5, s1, 31
	v_xor_b32_e32 v3, v2, v5
	s_add_i32 s1, s1, s5
	v_mul_lo_u32 v2, v6, s4
	s_ashr_i32 s1, s1, 1
	s_mul_i32 s4, s12, s7
	v_sub_nc_u32_e32 v5, v3, v5
	v_ashrrev_i32_e32 v1, 31, v0
	v_subrev_nc_u32_e32 v6, s1, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_mul_lo_u32 v9, v5, s7
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[0:1], 1, v[0:1]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v5, v6, v5
	v_lshlrev_b64 v[2:3], 1, v[2:3]
	v_sub_nc_u32_e32 v9, v4, v9
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_add_co_u32 v0, vcc_lo, s8, v0
	v_subrev_nc_u32_e32 v4, s0, v7
	v_add_co_ci_u32_e32 v1, vcc_lo, s9, v1, vcc_lo
	v_add_nc_u32_e32 v7, v10, v9
	v_add_co_u32 v2, vcc_lo, v0, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v3, vcc_lo, v1, v3, vcc_lo
	v_or_b32_e32 v9, v7, v5
	v_cmp_gt_i32_e32 vcc_lo, s12, v5
	v_cmp_gt_i32_e64 s0, s7, v7
	v_mad_u64_u32 v[0:1], null, s7, v6, v[4:5]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_lt_i32_e64 s1, -1, v9
	v_add_co_u32 v2, s2, v2, v8
	v_add_co_ci_u32_e64 v3, s2, 0, v3, s2
	s_and_b32 s2, s0, vcc_lo
	s_mov_b32 s0, 0
	s_and_b32 s2, s2, s1
.LBB3_3:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	v_mov_b32_e32 v1, 0
	s_and_saveexec_b32 s1, s2
	s_cbranch_execz .LBB3_5
; %bb.4:                                ;   in Loop: Header=BB3_3 Depth=1
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 1, v[0:1]
	v_add_co_u32 v4, vcc_lo, s10, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s11, v5, vcc_lo
	global_load_u16 v1, v[4:5], off
.LBB3_5:                                ;   in Loop: Header=BB3_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_ashr_i32 s1, s0, 31
	v_add_nc_u32_e32 v0, s4, v0
	s_lshl_b64 s[8:9], s[0:1], 1
	s_add_i32 s6, s6, -1
	v_add_co_u32 v4, vcc_lo, v2, s8
	v_add_co_ci_u32_e32 v5, vcc_lo, s9, v3, vcc_lo
	s_add_i32 s0, s0, s3
	s_cmp_lg_u32 s6, 0
	s_waitcnt vmcnt(0)
	global_store_b16 v[4:5], v1, off
	s_cbranch_scc1 .LBB3_3
.LBB3_6:                                ; %.loopexit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel genXMatrix_kernel
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 304
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 11
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end3:
	.size	genXMatrix_kernel, .Lfunc_end3-genXMatrix_kernel
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 692
; NumSgprs: 18
; NumVgprs: 11
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 11
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.text
	.protected	updateOutput_kernel     ; -- Begin function updateOutput_kernel
	.globl	updateOutput_kernel
	.p2align	8
	.type	updateOutput_kernel,@function
updateOutput_kernel:                    ; @updateOutput_kernel
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x34
	s_load_b128 s[4:7], s[0:1], 0x18
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mul_i32 s2, s6, s5
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_cmp_gt_i32_e32 vcc_lo, s2, v1
	s_and_saveexec_b32 s2, vcc_lo
	s_cbranch_execz .LBB4_2
; %bb.1:
	s_bitcmp1_b32 s7, 0
	v_ashrrev_i32_e32 v2, 31, v1
	s_cselect_b32 s8, -1, 0
	s_ashr_i32 s2, s5, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_add_i32 s3, s5, s2
	v_add_nc_u32_e32 v4, v1, v2
	s_xor_b32 s3, s3, s2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cvt_f32_u32_e32 v0, s3
	s_sub_i32 s6, 0, s3
	v_xor_b32_e32 v4, v4, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v0, v0
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v0, 0x4f7ffffe, v0
	v_cvt_u32_f32_e32 v0, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v3, s6, v0
	s_load_b64 s[6:7], s[0:1], 0x10
	v_mul_hi_u32 v3, v0, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v0, v0, v3
	v_mul_hi_u32 v0, v4, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v3, v0, s3
	v_sub_nc_u32_e32 v3, v4, v3
	v_add_nc_u32_e32 v4, 1, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v5, s3, v3
	v_cmp_le_u32_e32 vcc_lo, s3, v3
	v_dual_cndmask_b32 v3, v3, v5 :: v_dual_cndmask_b32 v0, v0, v4
	v_xor_b32_e32 v5, s2, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_le_u32_e32 vcc_lo, s3, v3
	v_add_nc_u32_e32 v4, 1, v0
	s_load_b128 s[0:3], s[0:1], 0x0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v0, v0, v4, vcc_lo
	v_xor_b32_e32 v0, v0, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v5, v0, v5
	v_mul_lo_u32 v0, v5, s5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v3, v1, v0
	v_lshlrev_b64 v[0:1], 1, v[1:2]
	v_ashrrev_i32_e32 v4, 31, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v3, vcc_lo, s6, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
	v_add_co_u32 v0, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	global_load_b32 v2, v[3:4], off
	global_load_u16 v3, v[0:1], off
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[0:1], null, v5, s4, v[2:3]
	v_cmp_ge_f16_e32 vcc_lo, 0, v3
	s_and_b32 s0, s8, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v1, 31, v0
	v_cndmask_b32_e64 v2, v3, 0, s0
	v_lshlrev_b64 v[0:1], 1, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s2, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
	global_store_b16 v[0:1], v2, off
.LBB4_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel updateOutput_kernel
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 6
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end4:
	.size	updateOutput_kernel, .Lfunc_end4-updateOutput_kernel
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 432
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	maxPool2d_kernel        ; -- Begin function maxPool2d_kernel
	.globl	maxPool2d_kernel
	.p2align	8
	.type	maxPool2d_kernel,@function
maxPool2d_kernel:                       ; @maxPool2d_kernel
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x44
	s_load_b256 s[4:11], s[0:1], 0x18
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_i32_e64 s4, v1
	s_cbranch_execz .LBB5_12
; %bb.1:
	s_cmp_lt_i32 s5, 1
	s_cbranch_scc1 .LBB5_12
; %bb.2:                                ; %.preheader58.lr.ph
	s_load_b64 s[2:3], s[0:1], 0x10
	v_ashrrev_i32_e32 v2, 31, v1
	s_ashr_i32 s13, s11, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_add_i32 s14, s11, s13
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	s_xor_b32 s14, s14, s13
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cvt_f32_u32_e32 v6, s14
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v0, vcc_lo, s2, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
	s_ashr_i32 s2, s7, 31
	s_add_i32 s3, s7, s2
	global_load_b32 v0, v[0:1], off
	s_xor_b32 s3, s3, s2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cvt_f32_u32_e32 v1, s3
	s_sub_i32 s4, 0, s3
	v_rcp_iflag_f32_e32 v1, v1
	s_waitcnt vmcnt(0)
	v_ashrrev_i32_e32 v3, 31, v0
	s_waitcnt_depctr 0xfff
	v_dual_mul_f32 v1, 0x4f7ffffe, v1 :: v_dual_add_nc_u32 v4, v0, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v1, v1
	v_mul_lo_u32 v2, s4, v1
	s_ashr_i32 s4, s10, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s12, s10, s4
	s_xor_b32 s12, s12, s4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v2, v1, v2
	v_add_nc_u32_e32 v1, v1, v2
	v_xor_b32_e32 v2, v4, v3
	v_xor_b32_e32 v3, s2, v3
	s_sub_i32 s2, 0, s12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v1, v2, v1
	v_mul_lo_u32 v4, v1, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v2, v2, v4
	v_add_nc_u32_e32 v4, 1, v1
	v_subrev_nc_u32_e32 v5, s3, v2
	v_cmp_le_u32_e32 vcc_lo, s3, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v2, v2, v5 :: v_dual_cndmask_b32 v1, v1, v4
	v_cvt_f32_u32_e32 v4, s12
	v_cmp_le_u32_e32 vcc_lo, s3, v2
	v_rcp_iflag_f32_e32 v2, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
	v_rcp_iflag_f32_e32 v4, v4
	s_mov_b32 s3, 0
	s_waitcnt_depctr 0xfff
	v_dual_mul_f32 v2, 0x4f7ffffe, v2 :: v_dual_add_nc_u32 v5, 1, v1
	v_mul_f32_e32 v4, 0x4f7ffffe, v4
	v_cvt_u32_f32_e32 v2, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v1, v1, v5, vcc_lo
	v_xor_b32_e32 v1, v1, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v1, v1, v3
	v_cvt_u32_f32_e32 v3, v4
	v_mul_lo_u32 v4, v1, s7
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_mul_lo_u32 v5, s2, v3
	s_sub_i32 s2, 0, s14
	s_cmp_gt_i32 s10, 0
	v_mul_lo_u32 v6, s2, v2
	v_sub_nc_u32_e32 v0, v0, v4
	v_ashrrev_i32_e32 v4, 31, v1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mul_hi_u32 v5, v3, v5
	v_mul_hi_u32 v6, v2, v6
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v7, 31, v0
	v_add_nc_u32_e32 v0, v0, v7
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v3, v3, v5
	v_add_nc_u32_e32 v2, v2, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v0, v0, v7
	v_xor_b32_e32 v7, s13, v7
	v_mul_hi_u32 v2, v0, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v6, v2, s14
	v_sub_nc_u32_e32 v0, v0, v6
	v_add_nc_u32_e32 v6, 1, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cmp_le_u32_e64 s2, s14, v0
	v_subrev_nc_u32_e32 v8, s14, v0
	v_cndmask_b32_e64 v2, v2, v6, s2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v0, v0, v8, s2
	v_add_nc_u32_e32 v6, 1, v2
	v_add_nc_u32_e32 v1, v1, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v1, v1, v4
	v_xor_b32_e32 v4, s4, v4
	s_mul_i32 s4, s7, s6
	v_mul_hi_u32 v3, v1, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v5, v3, s12
	v_sub_nc_u32_e32 v1, v1, v5
	v_add_nc_u32_e32 v5, 1, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_le_u32_e32 vcc_lo, s12, v1
	v_cndmask_b32_e32 v3, v3, v5, vcc_lo
	v_subrev_nc_u32_e32 v5, s12, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v1, v1, v5, vcc_lo
	v_add_nc_u32_e32 v5, 1, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_le_u32_e32 vcc_lo, s12, v1
	v_cndmask_b32_e32 v1, v3, v5, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s14, v0
	s_load_b128 s[12:15], s[0:1], 0x0
	s_mul_i32 s0, s10, s7
	s_cselect_b32 s1, -1, 0
	v_xor_b32_e32 v1, v1, v4
	v_cndmask_b32_e32 v0, v2, v6, vcc_lo
	s_cmp_gt_i32 s11, 0
	s_cselect_b32 s2, -1, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v2, v0, v7
	v_sub_nc_u32_e32 v0, v1, v4
	v_sub_nc_u32_e32 v1, v2, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_lo_u32 v2, v0, s10
	v_mul_lo_u32 v4, s0, v0
	v_mul_lo_u32 v3, v1, s11
.LBB5_3:                                ; %.preheader58
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB5_5 Depth 2
                                        ;       Child Loop BB5_7 Depth 3
	v_mov_b32_e32 v5, 0xfffffc00
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB5_11
; %bb.4:                                ; %.preheader.lr.ph
                                        ;   in Loop: Header=BB5_3 Depth=1
	s_delay_alu instid0(VALU_DEP_3)
	v_mov_b32_e32 v6, v4
	s_mov_b32 s16, 0
.LBB5_5:                                ; %.preheader
                                        ;   Parent Loop BB5_3 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB5_7 Depth 3
	s_and_not1_b32 vcc_lo, exec_lo, s2
	s_cbranch_vccnz .LBB5_10
; %bb.6:                                ; %.lr.ph
                                        ;   in Loop: Header=BB5_5 Depth=2
	v_add_nc_u32_e32 v7, s16, v2
	s_mov_b32 s17, s11
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_i32_e32 vcc_lo, s6, v7
	v_mov_b32_e32 v7, v3
.LBB5_7:                                ;   Parent Loop BB5_3 Depth=1
                                        ;     Parent Loop BB5_5 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_gt_i32_e64 s0, s7, v7
	s_and_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s18, s0
	s_cbranch_execz .LBB5_9
; %bb.8:                                ;   in Loop: Header=BB5_7 Depth=3
	v_add_nc_u32_e32 v8, v6, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v9, 31, v8
	v_lshlrev_b64 v[8:9], 1, v[8:9]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v8, s0, s12, v8
	v_add_co_ci_u32_e64 v9, s0, s13, v9, s0
	global_load_u16 v8, v[8:9], off
	s_waitcnt vmcnt(0)
	v_cmp_gt_f16_e64 s0, v8, v5
	s_delay_alu instid0(VALU_DEP_1)
	v_cndmask_b32_e64 v5, v5, v8, s0
.LBB5_9:                                ;   in Loop: Header=BB5_7 Depth=3
	s_or_b32 exec_lo, exec_lo, s18
	v_add_nc_u32_e32 v7, 1, v7
	s_add_i32 s17, s17, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s17, 0
	s_cbranch_scc0 .LBB5_7
.LBB5_10:                               ; %._crit_edge
                                        ;   in Loop: Header=BB5_5 Depth=2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_add_nc_u32_e32 v6, s7, v6
	s_add_i32 s16, s16, 1
	s_cmp_eq_u32 s16, s10
	s_cbranch_scc0 .LBB5_5
.LBB5_11:                               ; %._crit_edge63
                                        ;   in Loop: Header=BB5_3 Depth=1
	v_mad_u64_u32 v[6:7], null, s3, s8, v[0:1]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_add_nc_u32_e32 v4, s4, v4
	s_add_i32 s3, s3, 1
	s_cmp_eq_u32 s3, s5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[7:8], null, v6, s9, v[1:2]
	v_ashrrev_i32_e32 v8, 31, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[6:7], 1, v[7:8]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v6, vcc_lo, s14, v6
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v7, vcc_lo, s15, v7, vcc_lo
	global_store_b16 v[6:7], v5, off
	s_cbranch_scc0 .LBB5_3
.LBB5_12:                               ; %.loopexit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel maxPool2d_kernel
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 312
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 10
		.amdhsa_next_free_sgpr 19
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end5:
	.size	maxPool2d_kernel, .Lfunc_end5-maxPool2d_kernel
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1016
; NumSgprs: 21
; NumVgprs: 10
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 21
; NumVGPRsForWavesPerEU: 10
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
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amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
