#include <stdio.h>

__global__ void Kernel1 (int nz, int nip, int *d_nprox, float *d_arr)
{
  int ipn, ik, isn, k;

  ipn = blockIdx.x;
  k = threadIdx.x;

  //  if (k == 0)
  //    printf ("Kernel1: nprox[%d]=%d\n", ipn, d_nprox[ipn]);

  ik = ipn*nz + k;
  d_arr[ik] = 0.;
  for (isn = 0; isn < d_nprox[ipn]; isn++) {
    d_arr[ik] += 1.;
  }
  //  printf ("Kernel1: k=%d ik=%d d_arr=%f\n", k, ik, d_arr[ik]);
}

__host__ int main ()
{
  const int nz = 192;    // number of vertical points (threading)
  const int nip = 10242; // number of horizontal points (blocking)

  int k;                 // vertical index
  int ik;                // loop index collapses ipn and k
  int ipn;               // loop index over nip
  int isn;               // loop index over nprox
  int nprox[nip];        // mimics nprox in NIM
  int *d_nprox;          // nprox on device

  float refarr[nip*nz];  // reference array on CPU containing correct results
  float outarr[nip*nz];  // output array from GPU containing test results
  float *d_arr;

  dim3 cuda_threads1(nz);   // nz threads
  dim3 cuda_grids1(nip);    // nip blocks

  for (ipn = 0; ipn < nip; ++ipn) {
    nprox[ipn] = (ipn%6) + 1;
    for (k = 0; k < nz; ++k) {
      ik = ipn*nz + k;
      refarr[ik] = 0.;
      for (isn = 0; isn < nprox[ipn]; isn++) {
	refarr[ik] += 1.;
      }
    }
  }

  // Allocate space on device
  cudaMalloc ((void **) &d_arr,   nz*nip*sizeof(float));
  cudaMalloc ((void **) &d_nprox, nip*sizeof(int));

  // Set up nprox array for device
  cudaMemcpy (d_nprox, nprox, nip*sizeof(int), cudaMemcpyHostToDevice);

  Kernel1<<< cuda_grids1, cuda_threads1 >>>(nz, nip, d_nprox, d_arr);
  cudaThreadSynchronize ();

  // Copy results back to host
  cudaMemcpy (outarr, d_arr, nz*nip*sizeof(float), cudaMemcpyDeviceToHost);

  // Check results
  for (ipn = 0; ipn < nip; ++ipn) {
    for (k = 0; k < nz; ++k) {
      ik = ipn*nz + k;
      if (outarr[ik] != refarr[ik]) {
	printf ("ik=%d outarr=%f refarr=%f\n", ik, outarr[ik], refarr[ik]);
	return -1;
      }
    }
  }
  return 0;
}

	.file	"tmpxft_002988c2_00000000-6_nprox.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2030:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z30__device_stub__Z7Kernel1iiPiPfiiPiPf
	.type	_Z30__device_stub__Z7Kernel1iiPiPfiiPiPf, @function
_Z30__device_stub__Z7Kernel1iiPiPfiiPiPf:
.LFB2052:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movl	%edi, 28(%rsp)
	leaq	56(%rsp), %rdi
	movl	%esi, 24(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 16(%rsp)
	leaq	40(%rsp), %rdx
	movq	%rcx, 8(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	28(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z7Kernel1iiPiPf(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L2:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2052:
	.size	_Z30__device_stub__Z7Kernel1iiPiPfiiPiPf, .-_Z30__device_stub__Z7Kernel1iiPiPfiiPiPf
	.globl	_Z7Kernel1iiPiPf
	.type	_Z7Kernel1iiPiPf, @function
_Z7Kernel1iiPiPf:
.LFB2053:
	.cfi_startproc
	endbr64
	jmp	_Z30__device_stub__Z7Kernel1iiPiPfiiPiPf
	.cfi_endproc
.LFE2053:
	.size	_Z7Kernel1iiPiPf, .-_Z7Kernel1iiPiPf
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC2:
	.string	"ik=%d outarr=%f refarr=%f\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	pushq	%rbx
	.cfi_def_cfa_offset 24
	.cfi_offset 3, -24
	leaq	-15769600(%rsp), %r11
	.cfi_def_cfa 11, 15769624
.LPSRL0:
	subq	$4096, %rsp
	orq	$0, (%rsp)
	cmpq	%r11, %rsp
	jne	.LPSRL0
	.cfi_def_cfa_register 7
	subq	$3144, %rsp
	.cfi_def_cfa_offset 15772768
	movss	.LC1(%rip), %xmm1
	xorl	%ecx, %ecx
	movl	$6, %r8d
	movq	%fs:40, %rax
	movq	%rax, 15772728(%rsp)
	movabsq	$4294967488, %rax
	movl	$1, 32(%rsp)
	leaq	41016(%rsp), %rsi
	leaq	48(%rsp), %rbp
	movl	$1, 44(%rsp)
	movq	%rsi, %rbx
	movq	%rax, 24(%rsp)
	addq	$10050, %rax
	movq	%rax, 36(%rsp)
.L11:
	movl	%ecx, %eax
	cltd
	idivl	%r8d
	leal	1(%rdx), %eax
	movl	%eax, 0(%rbp,%rcx,4)
	xorl	%eax, %eax
.L10:
	xorps	%xmm0, %xmm0
	xorl	%edi, %edi
.L9:
	movl	%edi, %r9d
	addss	%xmm1, %xmm0
	incl	%edi
	cmpl	%r9d, %edx
	jne	.L9
	movss	%xmm0, (%rsi,%rax,4)
	incq	%rax
	cmpq	$192, %rax
	jne	.L10
	incq	%rcx
	addq	$768, %rsi
	cmpq	$10242, %rcx
	jne	.L11
	leaq	16(%rsp), %rdi
	movl	$7865856, %esi
	call	cudaMalloc@PLT
	leaq	8(%rsp), %rdi
	movl	$40968, %esi
	call	cudaMalloc@PLT
	movq	8(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbp, %rsi
	movl	$40968, %edx
	call	cudaMemcpy@PLT
	movl	32(%rsp), %ecx
	movl	44(%rsp), %esi
	xorl	%r9d, %r9d
	movq	24(%rsp), %rdx
	movq	36(%rsp), %rdi
	xorl	%r8d, %r8d
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L12
	movq	16(%rsp), %rcx
	movq	8(%rsp), %rdx
	movl	$10242, %esi
	movl	$192, %edi
	call	_Z30__device_stub__Z7Kernel1iiPiPfiiPiPf
.L12:
	call	cudaThreadSynchronize@PLT
	movq	16(%rsp), %rsi
	movl	$2, %ecx
	leaq	7906872(%rsp), %rbp
	movl	$7865856, %edx
	movq	%rbp, %rdi
	call	cudaMemcpy@PLT
	xorl	%esi, %esi
	xorl	%ecx, %ecx
.L13:
	movq	%rcx, %rax
	xorl	%edx, %edx
.L17:
	movss	0(%rbp,%rax), %xmm0
	movss	(%rbx,%rax), %xmm1
	ucomiss	%xmm1, %xmm0
	jp	.L20
	je	.L14
.L20:
	addl	%esi, %edx
	movl	$2, %edi
	movb	$2, %al
	cvtss2sd	%xmm0, %xmm0
	leaq	.LC2(%rip), %rsi
	cvtss2sd	%xmm1, %xmm1
	call	__printf_chk@PLT
	orl	$-1, %eax
	jmp	.L8
.L14:
	incl	%edx
	addq	$4, %rax
	cmpl	$192, %edx
	jne	.L17
	addq	$768, %rcx
	addl	$192, %esi
	cmpq	$7865856, %rcx
	jne	.L13
	xorl	%eax, %eax
.L8:
	movq	15772728(%rsp), %rdx
	subq	%fs:40, %rdx
	je	.L18
	call	__stack_chk_fail@PLT
.L18:
	addq	$15772744, %rsp
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2027:
	.size	main, .-main
	.section	.rodata.str1.1
.LC3:
	.string	"_Z7Kernel1iiPiPf"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC3(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z7Kernel1iiPiPf(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2055:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst4,"aM",@progbits,4
	.align 4
.LC1:
	.long	1065353216
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include <stdio.h>

__global__ void Kernel1 (int nz, int nip, int *d_nprox, float *d_arr)
{
  int ipn, ik, isn, k;

  ipn = blockIdx.x;
  k = threadIdx.x;

  //  if (k == 0)
  //    printf ("Kernel1: nprox[%d]=%d\n", ipn, d_nprox[ipn]);

  ik = ipn*nz + k;
  d_arr[ik] = 0.;
  for (isn = 0; isn < d_nprox[ipn]; isn++) {
    d_arr[ik] += 1.;
  }
  //  printf ("Kernel1: k=%d ik=%d d_arr=%f\n", k, ik, d_arr[ik]);
}

__host__ int main ()
{
  const int nz = 192;    // number of vertical points (threading)
  const int nip = 10242; // number of horizontal points (blocking)

  int k;                 // vertical index
  int ik;                // loop index collapses ipn and k
  int ipn;               // loop index over nip
  int isn;               // loop index over nprox
  int nprox[nip];        // mimics nprox in NIM
  int *d_nprox;          // nprox on device

  float refarr[nip*nz];  // reference array on CPU containing correct results
  float outarr[nip*nz];  // output array from GPU containing test results
  float *d_arr;

  dim3 cuda_threads1(nz);   // nz threads
  dim3 cuda_grids1(nip);    // nip blocks

  for (ipn = 0; ipn < nip; ++ipn) {
    nprox[ipn] = (ipn%6) + 1;
    for (k = 0; k < nz; ++k) {
      ik = ipn*nz + k;
      refarr[ik] = 0.;
      for (isn = 0; isn < nprox[ipn]; isn++) {
	refarr[ik] += 1.;
      }
    }
  }

  // Allocate space on device
  hipMalloc ((void **) &d_arr,   nz*nip*sizeof(float));
  hipMalloc ((void **) &d_nprox, nip*sizeof(int));

  // Set up nprox array for device
  hipMemcpy (d_nprox, nprox, nip*sizeof(int), hipMemcpyHostToDevice);

  Kernel1<<< cuda_grids1, cuda_threads1 >>>(nz, nip, d_nprox, d_arr);
  hipDeviceSynchronize ();

  // Copy results back to host
  hipMemcpy (outarr, d_arr, nz*nip*sizeof(float), hipMemcpyDeviceToHost);

  // Check results
  for (ipn = 0; ipn < nip; ++ipn) {
    for (k = 0; k < nz; ++k) {
      ik = ipn*nz + k;
      if (outarr[ik] != refarr[ik]) {
	printf ("ik=%d outarr=%f refarr=%f\n", ik, outarr[ik], refarr[ik]);
	return -1;
      }
    }
  }
  return 0;
}

	.text
	.file	"nprox.hip"
	.globl	_Z22__device_stub__Kernel1iiPiPf # -- Begin function _Z22__device_stub__Kernel1iiPiPf
	.type	_Z22__device_stub__Kernel1iiPiPf,@function
_Z22__device_stub__Kernel1iiPiPf:       # @_Z22__device_stub__Kernel1iiPiPf
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	12(%rsp), %rax
	movl	%edi, (%rax)
	leaq	8(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7Kernel1iiPiPf, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z22__device_stub__Kernel1iiPiPf, .Lfunc_end0-_Z22__device_stub__Kernel1iiPiPf
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0                          # -- Begin function main
.LCPI1_0:
	.long	0x3f800000                      # float 1
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$15772704, %rsp                 # imm = 0xF0AC20
	.cfi_def_cfa_offset 15772720
	.cfi_offset %rbx, -16
	movw	$1, %ax
	xorl	%ecx, %ecx
	movl	$65535, %edx                    # imm = 0xFFFF
	movss	.LCPI1_0(%rip), %xmm0           # xmm0 = mem[0],zero,zero,zero
.LBB1_1:                                # =>This Loop Header: Depth=1
                                        #     Child Loop BB1_2 Depth 2
                                        #       Child Loop BB1_3 Depth 3
	movl	%ecx, %esi
	andl	%edx, %esi
	imull	$43691, %esi, %esi              # imm = 0xAAAB
	shrl	$17, %esi
	andl	$-2, %esi
	leal	(%rsi,%rsi,2), %edi
	movl	%eax, %esi
	subl	%edi, %esi
	andl	%edx, %esi
	cmpl	$1, %esi
	adcl	$0, %esi
	movl	%ecx, %r8d
	subl	%edi, %r8d
	incl	%r8d
	andl	%edx, %r8d
	movl	%r8d, 16(%rsp,%rcx,4)
	movq	%rcx, %rdi
	shlq	$6, %rdi
	leaq	(%rdi,%rdi,2), %rdi
	xorl	%r8d, %r8d
.LBB1_2:                                #   Parent Loop BB1_1 Depth=1
                                        # =>  This Loop Header: Depth=2
                                        #       Child Loop BB1_3 Depth 3
	leaq	(%r8,%rdi), %r9
	xorps	%xmm1, %xmm1
	movl	%esi, %r10d
.LBB1_3:                                #   Parent Loop BB1_1 Depth=1
                                        #     Parent Loop BB1_2 Depth=2
                                        # =>    This Inner Loop Header: Depth=3
	addss	%xmm0, %xmm1
	decl	%r10d
	jne	.LBB1_3
# %bb.4:                                #   in Loop: Header=BB1_2 Depth=2
	movss	%xmm1, 40992(%rsp,%r9,4)
	incq	%r8
	cmpq	$192, %r8
	jne	.LBB1_2
# %bb.5:                                #   in Loop: Header=BB1_1 Depth=1
	incq	%rcx
	incl	%eax
	cmpq	$10242, %rcx                    # imm = 0x2802
	jne	.LBB1_1
# %bb.6:
	movq	%rsp, %rdi
	movl	$7865856, %esi                  # imm = 0x780600
	callq	hipMalloc
	leaq	8(%rsp), %rbx
	movl	$40968, %esi                    # imm = 0xA008
	movq	%rbx, %rdi
	callq	hipMalloc
	movq	(%rbx), %rdi
	leaq	16(%rsp), %rsi
	movl	$40968, %edx                    # imm = 0xA008
	movl	$1, %ecx
	callq	hipMemcpy
	movabsq	$4294967488, %rdx               # imm = 0x1000000C0
	leaq	10050(%rdx), %rdi
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_8
# %bb.7:
	movq	8(%rsp), %rdx
	movq	(%rsp), %rcx
	movl	$192, %edi
	movl	$10242, %esi                    # imm = 0x2802
	callq	_Z22__device_stub__Kernel1iiPiPf
.LBB1_8:
	callq	hipDeviceSynchronize
	movq	(%rsp), %rsi
	leaq	7906848(%rsp), %rbx
	movl	$7865856, %edx                  # imm = 0x780600
	movq	%rbx, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	leaq	40992(%rsp), %rcx
	xorl	%eax, %eax
	movl	$768, %edx                      # imm = 0x300
	xorl	%edi, %edi
.LBB1_9:                                # %.preheader
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB1_11 Depth 2
	xorl	%esi, %esi
.LBB1_11:                               #   Parent Loop BB1_9 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movss	(%rbx,%rsi,4), %xmm0            # xmm0 = mem[0],zero,zero,zero
	movss	(%rcx,%rsi,4), %xmm1            # xmm1 = mem[0],zero,zero,zero
	ucomiss	%xmm1, %xmm0
	jne	.LBB1_12
	jp	.LBB1_12
# %bb.10:                               #   in Loop: Header=BB1_11 Depth=2
	incq	%rsi
	cmpq	$192, %rsi
	jne	.LBB1_11
# %bb.13:                               #   in Loop: Header=BB1_9 Depth=1
	incq	%rdi
	addq	$-192, %rax
	addq	%rdx, %rcx
	addq	%rdx, %rbx
	cmpq	$10242, %rdi                    # imm = 0x2802
	jne	.LBB1_9
# %bb.14:
	xorl	%eax, %eax
	jmp	.LBB1_15
.LBB1_12:
	subl	%eax, %esi
	cvtss2sd	%xmm0, %xmm0
	cvtss2sd	%xmm1, %xmm1
	movl	$.L.str, %edi
                                        # kill: def $esi killed $esi killed $rsi
	movb	$2, %al
	callq	printf
	movl	$-1, %eax
.LBB1_15:                               # %.loopexit
	addq	$15772704, %rsp                 # imm = 0xF0AC20
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	main, .Lfunc_end1-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z7Kernel1iiPiPf, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z7Kernel1iiPiPf,@object        # @_Z7Kernel1iiPiPf
	.section	.rodata,"a",@progbits
	.globl	_Z7Kernel1iiPiPf
	.p2align	3, 0x0
_Z7Kernel1iiPiPf:
	.quad	_Z22__device_stub__Kernel1iiPiPf
	.size	_Z7Kernel1iiPiPf, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"ik=%d outarr=%f refarr=%f\n"
	.size	.L.str, 27

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z7Kernel1iiPiPf"
	.size	.L__unnamed_1, 17

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z22__device_stub__Kernel1iiPiPf
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z7Kernel1iiPiPf
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z7Kernel1iiPiPf        ; -- Begin function _Z7Kernel1iiPiPf
	.globl	_Z7Kernel1iiPiPf
	.p2align	8
	.type	_Z7Kernel1iiPiPf,@function
_Z7Kernel1iiPiPf:                       ; @_Z7Kernel1iiPiPf
; %bb.0:
	s_clause 0x1
	s_load_b32 s8, s[0:1], 0x0
	s_load_b128 s[0:3], s[0:1], 0x8
	s_mov_b32 s4, s15
	s_ashr_i32 s5, s15, 31
	s_delay_alu instid0(SALU_CYCLE_1)
	s_lshl_b64 s[6:7], s[4:5], 2
	s_waitcnt lgkmcnt(0)
	v_mad_u64_u32 v[1:2], null, s4, s8, v[0:1]
	s_add_u32 s0, s0, s6
	s_addc_u32 s1, s1, s7
	s_load_b32 s0, s[0:1], 0x0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v2, 31, v1
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v0, vcc_lo, s2, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
	s_waitcnt lgkmcnt(0)
	s_cmp_lt_i32 s0, 1
	global_store_b32 v[0:1], v2, off
	s_cbranch_scc1 .LBB0_3
.LBB0_1:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_add_f32_e32 v2, 1.0, v2
	s_add_i32 s0, s0, -1
	s_cmp_lg_u32 s0, 0
	s_cbranch_scc1 .LBB0_1
; %bb.2:                                ; %._crit_edge
	global_store_b32 v[0:1], v2, off
.LBB0_3:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7Kernel1iiPiPf
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 24
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 3
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z7Kernel1iiPiPf, .Lfunc_end0-_Z7Kernel1iiPiPf
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 160
; NumSgprs: 18
; NumVgprs: 3
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 3
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     by_value
      - .offset:         4
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 24
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z7Kernel1iiPiPf
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z7Kernel1iiPiPf.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     3
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
