#include <cuda.h>
#include <stdio.h>
#include <math.h>

#define BLOCK_WIDTH 16
#define TILE_WIDTH  BLOCK_WIDTH

extern "C" void gpu_mat_mul(float* h_M, float* h_N, float* h_P, int Mwidth,int Nwidth,int Swidth);

__global__
void gpu_mat_mul_kernel(float* M, float* N, float* P, int Mwidth, int Nwidth, int Swidth){

  __shared__ float Mds[TILE_WIDTH][TILE_WIDTH];
  __shared__ float Nds[TILE_WIDTH][TILE_WIDTH];

  int bx = blockIdx.x; 
  int by = blockIdx.y;
  int tx = threadIdx.x;
  int ty = threadIdx.y;
 // printf("blockx is %d,blocky is%d\n",bx,by);
  // Identify the row and column of the P element to work on
  // Each thread works on an element of P
  int Row = by * TILE_WIDTH + ty;
  int Col = bx * TILE_WIDTH + tx;
//  printf("Row %d,Col is%d\n",Row,Col);
  float sum = 0;
  int phase_num = (int)ceil((double) Nwidth/TILE_WIDTH);
  // Each thread loads 'Row'th row of M and 'Col'th column of N
  for (int ph = 0; ph < phase_num-1; ph++) {    

    // Collaboratively load data into shared memory
    Mds[ty][tx] = M[Row * Nwidth + ph * TILE_WIDTH + tx];   
    Nds[ty][tx] = N[(ph * TILE_WIDTH + ty) * Swidth + Col];

    __syncthreads();
    for (int k = 0; k < TILE_WIDTH; k++) { 
      sum += Mds[ty][k] * Nds[k][tx];
    }
    __syncthreads();
  }
  int ph = phase_num-1;
  int res = Nwidth - ph*TILE_WIDTH;
 if (tx < res){
      Mds[ty][tx] = M[Row * Nwidth + ph * TILE_WIDTH + tx];
  }
if (ty < res){
    Nds[ty][tx] = N[(ph * TILE_WIDTH + ty) * Swidth + Col];
  }
   __syncthreads();//Barrier
      for (int k = 0; k < res ; k++) {
        sum += Mds[ty][k] * Nds[k][tx];
      }
      __syncthreads();

  if (Row<Mwidth&&Col<Swidth){
  P[Row * Swidth + Col] = sum;
  }
}
void gpu_mat_mul(float* h_M, float* h_N, float* h_P, int Mwidth,int Nwidth,int Swidth) {
  float *d_M, *d_N, *d_P;

  size_t size_of_float = sizeof(float);
  size_t size_M = Mwidth * Nwidth * size_of_float;
  size_t size_N = Nwidth * Swidth * size_of_float;
  size_t size_P = Mwidth * Swidth * size_of_float;

  cudaMalloc((void**)&d_M, size_M);
  cudaMalloc((void**)&d_N, size_N);
  cudaMalloc((void**)&d_P, size_P);
    
  cudaMemcpy(d_M, h_M, size_M, cudaMemcpyHostToDevice);
  cudaMemcpy(d_N, h_N, size_N, cudaMemcpyHostToDevice);

  cudaEvent_t start, stop;
  float elapsed_time = 0.0;
  cudaEventCreate(&start);
  cudaEventCreate(&stop);
  cudaEventRecord(start, 0);

  dim3 grid_dim((int)ceil((double)Swidth/BLOCK_WIDTH),(int)ceil((double) Mwidth/BLOCK_WIDTH), 1);
  dim3 block_dim(BLOCK_WIDTH, BLOCK_WIDTH, 1);
  gpu_mat_mul_kernel<<<grid_dim, block_dim>>>(d_M, d_N, d_P, Mwidth,Nwidth,Swidth);
  cudaEventRecord(stop, 0);
  cudaEventSynchronize(stop);

  cudaMemcpy(h_P, d_P, size_P, cudaMemcpyDeviceToHost);
    
  // Free device memory for M, N, P
  cudaFree(d_M);
  cudaFree(d_N);
  cudaFree(d_P);

  cudaEventElapsedTime(&elapsed_time, start, stop);
    
  printf("  grid  dim:  %d, %d, %d.\n", grid_dim.x, grid_dim.y, grid_dim.z);
  printf("  block dim: %d, %d, %d.\n", block_dim.x, block_dim.y, block_dim.z);
  printf("  kernel time: %.5f sec\n", elapsed_time / 1000);

  cudaEventDestroy(start);
  cudaEventDestroy(stop);
}



	.file	"tmpxft_002c8dc6_00000000-6_hwsmat_mul.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2030:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z45__device_stub__Z18gpu_mat_mul_kernelPfS_S_iiiPfS_S_iii
	.type	_Z45__device_stub__Z18gpu_mat_mul_kernelPfS_S_iiiPfS_S_iii, @function
_Z45__device_stub__Z18gpu_mat_mul_kernelPfS_S_iiiPfS_S_iii:
.LFB2052:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	56(%rsp), %rdx
	movl	%ecx, 20(%rsp)
	leaq	64(%rsp), %rcx
	movl	%r8d, 16(%rsp)
	movl	%r9d, 12(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	64(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z18gpu_mat_mul_kernelPfS_S_iii(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 208
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L2:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2052:
	.size	_Z45__device_stub__Z18gpu_mat_mul_kernelPfS_S_iiiPfS_S_iii, .-_Z45__device_stub__Z18gpu_mat_mul_kernelPfS_S_iiiPfS_S_iii
	.globl	_Z18gpu_mat_mul_kernelPfS_S_iii
	.type	_Z18gpu_mat_mul_kernelPfS_S_iii, @function
_Z18gpu_mat_mul_kernelPfS_S_iii:
.LFB2053:
	.cfi_startproc
	endbr64
	jmp	_Z45__device_stub__Z18gpu_mat_mul_kernelPfS_S_iiiPfS_S_iii
	.cfi_endproc
.LFE2053:
	.size	_Z18gpu_mat_mul_kernelPfS_S_iii, .-_Z18gpu_mat_mul_kernelPfS_S_iii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC2:
	.string	"  grid  dim:  %d, %d, %d.\n"
.LC3:
	.string	"  block dim: %d, %d, %d.\n"
.LC5:
	.string	"  kernel time: %.5f sec\n"
	.text
	.globl	gpu_mat_mul
	.type	gpu_mat_mul, @function
gpu_mat_mul:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movq	%rdi, %r15
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	movq	%rsi, %r14
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movl	%r8d, %r13d
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movl	%r8d, %r12d
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	imull	%r9d, %r12d
	movl	%r9d, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movl	%ecx, %ebx
	movslq	%r12d, %r12
	subq	$120, %rsp
	.cfi_def_cfa_offset 176
	salq	$2, %r12
	movq	%rdx, 16(%rsp)
	movl	%ecx, %edx
	leaq	40(%rsp), %rdi
	imull	%r8d, %edx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	movl	%ecx, %eax
	imull	%r9d, %eax
	movslq	%edx, %rdx
	salq	$2, %rdx
	movq	%rdx, %rsi
	movq	%rdx, 24(%rsp)
	cltq
	salq	$2, %rax
	movq	%rax, 8(%rsp)
	call	cudaMalloc@PLT
	movq	%r12, %rsi
	leaq	48(%rsp), %rdi
	call	cudaMalloc@PLT
	movq	8(%rsp), %rsi
	leaq	56(%rsp), %rdi
	call	cudaMalloc@PLT
	movq	24(%rsp), %rdx
	movq	40(%rsp), %rdi
	movq	%r15, %rsi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	movq	48(%rsp), %rdi
	movq	%r12, %rdx
	movq	%r14, %rsi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	leaq	64(%rsp), %rdi
	movl	$0x00000000, 36(%rsp)
	call	cudaEventCreate@PLT
	leaq	72(%rsp), %rdi
	call	cudaEventCreate@PLT
	movq	64(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	cvtsi2sdl	%ebx, %xmm0
	mulsd	.LC1(%rip), %xmm0
	call	ceil@PLT
	cvttsd2sil	%xmm0, %r14d
	cvtsi2sdl	%ebp, %xmm0
	mulsd	.LC1(%rip), %xmm0
	call	ceil@PLT
	movl	%r14d, 84(%rsp)
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	cvttsd2sil	%xmm0, %r12d
	movl	$1, %ecx
	movl	$1, %esi
	movabsq	$68719476752, %rdx
	movl	%r12d, 80(%rsp)
	movq	80(%rsp), %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L9
	movq	56(%rsp), %rdx
	movq	48(%rsp), %rsi
	movl	%ebp, %r9d
	movl	%r13d, %r8d
	movq	40(%rsp), %rdi
	movl	%ebx, %ecx
	call	_Z45__device_stub__Z18gpu_mat_mul_kernelPfS_S_iiiPfS_S_iii
.L9:
	movq	72(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movq	72(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movq	8(%rsp), %rdx
	movq	56(%rsp), %rsi
	movl	$2, %ecx
	movq	16(%rsp), %rdi
	call	cudaMemcpy@PLT
	movq	40(%rsp), %rdi
	call	cudaFree@PLT
	movq	48(%rsp), %rdi
	call	cudaFree@PLT
	movq	56(%rsp), %rdi
	call	cudaFree@PLT
	movq	72(%rsp), %rdx
	movq	64(%rsp), %rsi
	leaq	36(%rsp), %rdi
	call	cudaEventElapsedTime@PLT
	movl	$1, %r8d
	movl	%r14d, %ecx
	xorl	%eax, %eax
	movl	%r12d, %edx
	leaq	.LC2(%rip), %rsi
	movl	$2, %edi
	call	__printf_chk@PLT
	movl	$1, %r8d
	xorl	%eax, %eax
	movl	$16, %ecx
	movl	$16, %edx
	leaq	.LC3(%rip), %rsi
	movl	$2, %edi
	call	__printf_chk@PLT
	leaq	.LC5(%rip), %rsi
	movl	$2, %edi
	movb	$1, %al
	movss	36(%rsp), %xmm0
	divss	.LC4(%rip), %xmm0
	cvtss2sd	%xmm0, %xmm0
	call	__printf_chk@PLT
	movq	64(%rsp), %rdi
	call	cudaEventDestroy@PLT
	movq	72(%rsp), %rdi
	call	cudaEventDestroy@PLT
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L10
	call	__stack_chk_fail@PLT
.L10:
	addq	$120, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2027:
	.size	gpu_mat_mul, .-gpu_mat_mul
	.section	.rodata.str1.1
.LC6:
	.string	"_Z18gpu_mat_mul_kernelPfS_S_iii"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC6(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z18gpu_mat_mul_kernelPfS_S_iii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2055:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst8,"aM",@progbits,8
	.align 8
.LC1:
	.long	0
	.long	1068498944
	.section	.rodata.cst4,"aM",@progbits,4
	.align 4
.LC4:
	.long	1148846080
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <hip/hip_runtime.h>
#include <stdio.h>
#include <math.h>

#define BLOCK_WIDTH 16
#define TILE_WIDTH  BLOCK_WIDTH

extern "C" void gpu_mat_mul(float* h_M, float* h_N, float* h_P, int Mwidth,int Nwidth,int Swidth);

__global__
void gpu_mat_mul_kernel(float* M, float* N, float* P, int Mwidth, int Nwidth, int Swidth){

  __shared__ float Mds[TILE_WIDTH][TILE_WIDTH];
  __shared__ float Nds[TILE_WIDTH][TILE_WIDTH];

  int bx = blockIdx.x; 
  int by = blockIdx.y;
  int tx = threadIdx.x;
  int ty = threadIdx.y;
 // printf("blockx is %d,blocky is%d\n",bx,by);
  // Identify the row and column of the P element to work on
  // Each thread works on an element of P
  int Row = by * TILE_WIDTH + ty;
  int Col = bx * TILE_WIDTH + tx;
//  printf("Row %d,Col is%d\n",Row,Col);
  float sum = 0;
  int phase_num = (int)ceil((double) Nwidth/TILE_WIDTH);
  // Each thread loads 'Row'th row of M and 'Col'th column of N
  for (int ph = 0; ph < phase_num-1; ph++) {    

    // Collaboratively load data into shared memory
    Mds[ty][tx] = M[Row * Nwidth + ph * TILE_WIDTH + tx];   
    Nds[ty][tx] = N[(ph * TILE_WIDTH + ty) * Swidth + Col];

    __syncthreads();
    for (int k = 0; k < TILE_WIDTH; k++) { 
      sum += Mds[ty][k] * Nds[k][tx];
    }
    __syncthreads();
  }
  int ph = phase_num-1;
  int res = Nwidth - ph*TILE_WIDTH;
 if (tx < res){
      Mds[ty][tx] = M[Row * Nwidth + ph * TILE_WIDTH + tx];
  }
if (ty < res){
    Nds[ty][tx] = N[(ph * TILE_WIDTH + ty) * Swidth + Col];
  }
   __syncthreads();//Barrier
      for (int k = 0; k < res ; k++) {
        sum += Mds[ty][k] * Nds[k][tx];
      }
      __syncthreads();

  if (Row<Mwidth&&Col<Swidth){
  P[Row * Swidth + Col] = sum;
  }
}
void gpu_mat_mul(float* h_M, float* h_N, float* h_P, int Mwidth,int Nwidth,int Swidth) {
  float *d_M, *d_N, *d_P;

  size_t size_of_float = sizeof(float);
  size_t size_M = Mwidth * Nwidth * size_of_float;
  size_t size_N = Nwidth * Swidth * size_of_float;
  size_t size_P = Mwidth * Swidth * size_of_float;

  hipMalloc((void**)&d_M, size_M);
  hipMalloc((void**)&d_N, size_N);
  hipMalloc((void**)&d_P, size_P);
    
  hipMemcpy(d_M, h_M, size_M, hipMemcpyHostToDevice);
  hipMemcpy(d_N, h_N, size_N, hipMemcpyHostToDevice);

  hipEvent_t start, stop;
  float elapsed_time = 0.0;
  hipEventCreate(&start);
  hipEventCreate(&stop);
  hipEventRecord(start, 0);

  dim3 grid_dim((int)ceil((double)Swidth/BLOCK_WIDTH),(int)ceil((double) Mwidth/BLOCK_WIDTH), 1);
  dim3 block_dim(BLOCK_WIDTH, BLOCK_WIDTH, 1);
  gpu_mat_mul_kernel<<<grid_dim, block_dim>>>(d_M, d_N, d_P, Mwidth,Nwidth,Swidth);
  hipEventRecord(stop, 0);
  hipEventSynchronize(stop);

  hipMemcpy(h_P, d_P, size_P, hipMemcpyDeviceToHost);
    
  // Free device memory for M, N, P
  hipFree(d_M);
  hipFree(d_N);
  hipFree(d_P);

  hipEventElapsedTime(&elapsed_time, start, stop);
    
  printf("  grid  dim:  %d, %d, %d.\n", grid_dim.x, grid_dim.y, grid_dim.z);
  printf("  block dim: %d, %d, %d.\n", block_dim.x, block_dim.y, block_dim.z);
  printf("  kernel time: %.5f sec\n", elapsed_time / 1000);

  hipEventDestroy(start);
  hipEventDestroy(stop);
}



	.text
	.file	"hwsmat_mul.hip"
	.globl	_Z33__device_stub__gpu_mat_mul_kernelPfS_S_iii # -- Begin function _Z33__device_stub__gpu_mat_mul_kernelPfS_S_iii
	.type	_Z33__device_stub__gpu_mat_mul_kernelPfS_S_iii,@function
_Z33__device_stub__gpu_mat_mul_kernelPfS_S_iii: # @_Z33__device_stub__gpu_mat_mul_kernelPfS_S_iii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	20(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	16(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	12(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z18gpu_mat_mul_kernelPfS_S_iii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z33__device_stub__gpu_mat_mul_kernelPfS_S_iii, .Lfunc_end0-_Z33__device_stub__gpu_mat_mul_kernelPfS_S_iii
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0                          # -- Begin function gpu_mat_mul
.LCPI1_0:
	.quad	0x3fb0000000000000              # double 0.0625
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0
.LCPI1_1:
	.long	0x447a0000                      # float 1000
	.text
	.globl	gpu_mat_mul
	.type	gpu_mat_mul,@function
gpu_mat_mul:                            # @gpu_mat_mul
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$88, %rsp
	.cfi_def_cfa_offset 144
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%r9d, %ebp
	movl	%ecx, %r15d
	movq	%rdx, 80(%rsp)                  # 8-byte Spill
	movq	%rsi, 64(%rsp)                  # 8-byte Spill
	movq	%rdi, 56(%rsp)                  # 8-byte Spill
	movl	%r8d, %eax
	imull	%ecx, %eax
	movslq	%eax, %rbx
	shlq	$2, %rbx
	movl	%r9d, %eax
	movl	%r8d, 32(%rsp)                  # 4-byte Spill
	imull	%r8d, %eax
	movslq	%eax, %r13
	shlq	$2, %r13
	movl	%r9d, %eax
	imull	%ecx, %eax
	movslq	%eax, %r12
	shlq	$2, %r12
	leaq	48(%rsp), %r14
	movq	%r14, %rdi
	movq	%rbx, %rsi
	callq	hipMalloc
	leaq	24(%rsp), %rdi
	movq	%r13, %rsi
	callq	hipMalloc
	leaq	16(%rsp), %rdi
	movq	%r12, 72(%rsp)                  # 8-byte Spill
	movq	%r12, %rsi
	callq	hipMalloc
	movq	(%r14), %rdi
	movq	56(%rsp), %rsi                  # 8-byte Reload
	movq	%rbx, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	24(%rsp), %rax
	movq	(%rax), %rdi
	movq	64(%rsp), %rsi                  # 8-byte Reload
	movq	%r13, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	movl	$0, 36(%rsp)
	leaq	40(%rsp), %rbx
	movq	%rbx, %rdi
	callq	hipEventCreate
	leaq	8(%rsp), %rdi
	callq	hipEventCreate
	movq	(%rbx), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	cvtsi2sd	%ebp, %xmm0
	mulsd	.LCPI1_0(%rip), %xmm0
	callq	ceil@PLT
	cvttsd2si	%xmm0, %r13d
	xorps	%xmm0, %xmm0
	cvtsi2sd	%r15d, %xmm0
	mulsd	.LCPI1_0(%rip), %xmm0
	callq	ceil@PLT
	cvttsd2si	%xmm0, %ebx
	movq	%rbx, %rdi
	shlq	$32, %rdi
	orq	%r13, %rdi
	movabsq	$68719476752, %rdx              # imm = 0x1000000010
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_2
# %bb.1:
	movq	48(%rsp), %rdi
	movq	24(%rsp), %rsi
	movq	16(%rsp), %rdx
	movl	%r15d, %ecx
	movl	32(%rsp), %r8d                  # 4-byte Reload
	movl	%ebp, %r9d
	callq	_Z33__device_stub__gpu_mat_mul_kernelPfS_S_iii
.LBB1_2:
	movq	8(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	8(%rsp), %rdi
	callq	hipEventSynchronize
	movq	16(%rsp), %rsi
	movq	80(%rsp), %rdi                  # 8-byte Reload
	movq	72(%rsp), %rdx                  # 8-byte Reload
	movl	$2, %ecx
	callq	hipMemcpy
	movq	48(%rsp), %rdi
	callq	hipFree
	movq	24(%rsp), %rdi
	callq	hipFree
	movq	16(%rsp), %rdi
	callq	hipFree
	movq	40(%rsp), %rsi
	movq	8(%rsp), %rdx
	leaq	36(%rsp), %r14
	movq	%r14, %rdi
	callq	hipEventElapsedTime
	movl	$.L.str, %edi
	movl	%r13d, %esi
	movl	%ebx, %edx
	movl	$1, %ecx
	xorl	%eax, %eax
	callq	printf
	movl	$.L.str.1, %edi
	movl	$16, %esi
	movl	$16, %edx
	movl	$1, %ecx
	xorl	%eax, %eax
	callq	printf
	movss	(%r14), %xmm0                   # xmm0 = mem[0],zero,zero,zero
	divss	.LCPI1_1(%rip), %xmm0
	cvtss2sd	%xmm0, %xmm0
	movl	$.L.str.2, %edi
	movb	$1, %al
	callq	printf
	movq	40(%rsp), %rdi
	callq	hipEventDestroy
	movq	8(%rsp), %rdi
	callq	hipEventDestroy
	addq	$88, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	gpu_mat_mul, .Lfunc_end1-gpu_mat_mul
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z18gpu_mat_mul_kernelPfS_S_iii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z18gpu_mat_mul_kernelPfS_S_iii,@object # @_Z18gpu_mat_mul_kernelPfS_S_iii
	.section	.rodata,"a",@progbits
	.globl	_Z18gpu_mat_mul_kernelPfS_S_iii
	.p2align	3, 0x0
_Z18gpu_mat_mul_kernelPfS_S_iii:
	.quad	_Z33__device_stub__gpu_mat_mul_kernelPfS_S_iii
	.size	_Z18gpu_mat_mul_kernelPfS_S_iii, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"  grid  dim:  %d, %d, %d.\n"
	.size	.L.str, 27

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"  block dim: %d, %d, %d.\n"
	.size	.L.str.1, 26

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"  kernel time: %.5f sec\n"
	.size	.L.str.2, 25

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z18gpu_mat_mul_kernelPfS_S_iii"
	.size	.L__unnamed_1, 32

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z33__device_stub__gpu_mat_mul_kernelPfS_S_iii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z18gpu_mat_mul_kernelPfS_S_iii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z18gpu_mat_mul_kernelPfS_S_iii ; -- Begin function _Z18gpu_mat_mul_kernelPfS_S_iii
	.globl	_Z18gpu_mat_mul_kernelPfS_S_iii
	.p2align	8
	.type	_Z18gpu_mat_mul_kernelPfS_S_iii,@function
_Z18gpu_mat_mul_kernelPfS_S_iii:        ; @_Z18gpu_mat_mul_kernelPfS_S_iii
; %bb.0:
	s_clause 0x2
	s_load_b128 s[4:7], s[0:1], 0x18
	s_load_b128 s[8:11], s[0:1], 0x0
	s_load_b64 s[2:3], s[0:1], 0x10
	v_bfe_u32 v6, v0, 10, 10
	v_mov_b32_e32 v3, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshl_add_u32 v4, s15, 4, v6
	v_lshlrev_b32_e32 v5, 6, v6
	s_waitcnt lgkmcnt(0)
	v_cvt_f64_i32_e32 v[1:2], s5
	v_ldexp_f64 v[1:2], v[1:2], -4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ceil_f64_e32 v[1:2], v[1:2]
	v_cvt_i32_f64_e32 v2, v[1:2]
	v_and_b32_e32 v1, 0x3ff, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_lshl_add_u32 v0, s14, 4, v1
	v_lshlrev_b32_e32 v7, 2, v1
	v_readfirstlane_b32 s0, v2
	v_cmp_gt_i32_e32 vcc_lo, 2, v2
	s_delay_alu instid0(VALU_DEP_2)
	s_add_i32 s0, s0, -1
	s_cbranch_vccnz .LBB0_5
; %bb.1:                                ; %.lr.ph
	v_lshlrev_b32_e32 v8, 6, v6
	v_add_nc_u32_e32 v9, 0x400, v7
	v_mad_u64_u32 v[2:3], null, v4, s5, v[1:2]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_mov_b32 v3, 0 :: v_dual_add_nc_u32 v10, v8, v7
	v_add_nc_u32_e32 v11, v9, v8
	s_mov_b32 s1, 0
.LBB0_2:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_3 Depth 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b32 s7, s1, 4
	v_add_nc_u32_e32 v13, s7, v6
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v12, s7, v2
	s_mov_b32 s7, 0
	v_mad_u64_u32 v[14:15], null, v13, s6, v[0:1]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v13, 31, v12
	v_lshlrev_b64 v[12:13], 2, v[12:13]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v15, 31, v14
	v_add_co_u32 v12, vcc_lo, s8, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_lshlrev_b64 v[14:15], 2, v[14:15]
	v_add_co_ci_u32_e32 v13, vcc_lo, s9, v13, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v14, vcc_lo, s10, v14
	v_add_co_ci_u32_e32 v15, vcc_lo, s11, v15, vcc_lo
	global_load_b32 v13, v[12:13], off
	global_load_b32 v14, v[14:15], off
	v_mov_b32_e32 v12, v9
	s_waitcnt vmcnt(1)
	ds_store_b32 v10, v13
	s_waitcnt vmcnt(0)
	ds_store_b32 v11, v14
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
.LBB0_3:                                ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_add_nc_u32_e32 v13, s7, v8
	s_add_i32 s7, s7, 4
	ds_load_b32 v14, v12
	ds_load_b32 v13, v13
	v_add_nc_u32_e32 v12, 64, v12
	s_cmp_eq_u32 s7, 64
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v3, v13, v14
	s_cbranch_scc0 .LBB0_3
; %bb.4:                                ;   in Loop: Header=BB0_2 Depth=1
	s_add_i32 s1, s1, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s1, s0
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc0 .LBB0_2
.LBB0_5:                                ; %Flow125
	s_lshl_b32 s1, s0, 4
	s_mov_b32 s7, exec_lo
	s_sub_i32 s0, s5, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	v_cmpx_gt_i32_e64 s0, v1
	s_cbranch_execz .LBB0_7
; %bb.6:
	v_mul_lo_u32 v2, v4, s5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v8, v2, v1, s1
	v_ashrrev_i32_e32 v9, 31, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[8:9], 2, v[8:9]
	v_add_co_u32 v8, vcc_lo, s8, v8
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v9, vcc_lo, s9, v9, vcc_lo
	global_load_b32 v2, v[8:9], off
	v_lshl_add_u32 v8, v6, 6, v7
	s_waitcnt vmcnt(0)
	ds_store_b32 v8, v2
.LBB0_7:
	s_or_b32 exec_lo, exec_lo, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s5, exec_lo
	v_cmpx_gt_i32_e64 s0, v6
	s_cbranch_execz .LBB0_9
; %bb.8:
	v_add_nc_u32_e32 v2, s1, v6
	v_lshl_add_u32 v6, v6, 6, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[8:9], null, v2, s6, v[0:1]
	v_ashrrev_i32_e32 v9, 31, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[8:9], 2, v[8:9]
	v_add_co_u32 v8, vcc_lo, s10, v8
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v9, vcc_lo, s11, v9, vcc_lo
	global_load_b32 v2, v[8:9], off
	s_waitcnt vmcnt(0)
	ds_store_b32 v6, v2 offset:1024
.LBB0_9:
	s_or_b32 exec_lo, exec_lo, s5
	s_cmp_lt_i32 s0, 1
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB0_12
; %bb.10:                               ; %.lr.ph86.preheader
	v_lshl_add_u32 v1, v1, 2, 0x400
	s_mov_b32 s1, 0
.LBB0_11:                               ; %.lr.ph86
                                        ; =>This Inner Loop Header: Depth=1
	ds_load_b32 v2, v5
	ds_load_b32 v6, v1
	v_add_nc_u32_e32 v5, 4, v5
	v_add_nc_u32_e32 v1, 64, v1
	s_add_i32 s1, s1, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_ge_i32 s1, s0
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v3, v2, v6
	s_cbranch_scc0 .LBB0_11
.LBB0_12:                               ; %Flow123
	v_cmp_gt_i32_e32 vcc_lo, s4, v4
	v_cmp_gt_i32_e64 s0, s6, v0
	s_barrier
	buffer_gl0_inv
	s_and_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_14
; %bb.13:
	v_mad_u64_u32 v[1:2], null, v4, s6, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v2, 31, v1
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s2, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
	global_store_b32 v[0:1], v3, off
.LBB0_14:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z18gpu_mat_mul_kernelPfS_S_iii
		.amdhsa_group_segment_fixed_size 2048
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 36
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 16
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z18gpu_mat_mul_kernelPfS_S_iii, .Lfunc_end0-_Z18gpu_mat_mul_kernelPfS_S_iii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 796
; NumSgprs: 18
; NumVgprs: 16
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 2048 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 16
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     by_value
    .group_segment_fixed_size: 2048
    .kernarg_segment_align: 8
    .kernarg_segment_size: 36
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z18gpu_mat_mul_kernelPfS_S_iii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z18gpu_mat_mul_kernelPfS_S_iii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     16
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
