#include <cuda_runtime.h>
#include <iostream>
#include <stdio.h>
#include <sys/time.h>

static void HandleError( cudaError_t err, const char *file, int line ) {
    if (err != cudaSuccess) {
        printf( "%s in %s at line %d\n", cudaGetErrorString( err ),file, line );
        exit( EXIT_FAILURE );    
    }
}
#define HANDLE_ERROR( err ) (HandleError( err, __FILE__, __LINE__ ))

__global__ void conv(void* __restrict__ A, void* __restrict__ W, void* __restrict__ B) {
  float B_local[64];
  __shared__ float Apad_shared[512];
  __shared__ float W_shared[512];
  float Apad_shared_local[8];
  float W_shared_local[8];
  for (int ff_c_init = 0; ff_c_init < 8; ++ff_c_init) {
    for (int nn_c_init = 0; nn_c_init < 8; ++nn_c_init) {
      B_local[(((ff_c_init * 8) + nn_c_init))] = 0.000000e+00f;
    }
  }
  for (int rc_outer = 0; rc_outer < 32; ++rc_outer) {
    for (int ry = 0; ry < 3; ++ry) {
      for (int rx = 0; rx < 3; ++rx) {
        __syncthreads();
        for (int ax3_inner_outer = 0; ax3_inner_outer < 2; ++ax3_inner_outer) {
          ((float4*)(Apad_shared + ((((((int)threadIdx.x) * 64) + (((int)threadIdx.x) * 8)) + (ax3_inner_outer * 4)))))[0] = (((((1 <= ((((int)blockIdx.z) / 14) + ry)) && (((((int)blockIdx.z) / 14) + ry) < 15)) && (1 <= (rx + (((int)blockIdx.z) % 14)))) && ((rx + (((int)blockIdx.z) % 14)) < 15)) ? ((float4*)((float*)A + ((((((((((ry * 458752) + (((int)blockIdx.z) * 32768)) + (rx * 32768)) + (rc_outer * 1024)) + (((int)threadIdx.x) * 128)) + (((int)blockIdx.x) * 64)) + (((int)threadIdx.x) * 8)) + (ax3_inner_outer * 4)) - 491520))))[0] : make_float4(0.000000e+00f, 0.000000e+00f, 0.000000e+00f, 0.000000e+00f));
        }
        for (int ax3_inner_outer1 = 0; ax3_inner_outer1 < 2; ++ax3_inner_outer1) {
          ((float4*)(W_shared + ((((((int)threadIdx.x) * 64) + (((int)threadIdx.x) * 8)) + (ax3_inner_outer1 * 4)))))[0] = ((float4*)((float*)W + ((((((((ry * 393216) + (rx * 131072)) + (rc_outer * 4096)) + (((int)threadIdx.x) * 512)) + (((int)blockIdx.y) * 64)) + (((int)threadIdx.x) * 8)) + (ax3_inner_outer1 * 4)))))[0];
        }
        __syncthreads();
        for (int rc_inner = 0; rc_inner < 8; ++rc_inner) {
          for (int ax3 = 0; ax3 < 8; ++ax3) {
            Apad_shared_local[(ax3)] = Apad_shared[((((rc_inner * 64) + (((int)threadIdx.x) * 8)) + ax3))];
          }
          for (int ax31 = 0; ax31 < 8; ++ax31) {
            W_shared_local[(ax31)] = W_shared[((((rc_inner * 64) + (((int)threadIdx.x) * 8)) + ax31))];
          }
          for (int ff_c = 0; ff_c < 8; ++ff_c) {
            for (int nn_c = 0; nn_c < 8; ++nn_c) {
              B_local[(((ff_c * 8) + nn_c))] = (B_local[(((ff_c * 8) + nn_c))] + ((Apad_shared_local[(nn_c)] * W_shared_local[(ff_c)])));
            }
          }
        }
      }
    }
  }
  for (int ff_inner_inner_inner = 0; ff_inner_inner_inner < 8; ++ff_inner_inner_inner) {
    for (int nn_inner_inner_inner = 0; nn_inner_inner_inner < 8; ++nn_inner_inner_inner) {
      ((float*)B)[((((((((((int)blockIdx.z) * 65536) + (((int)blockIdx.y) * 8192)) + (((int)threadIdx.x) * 1024)) + (ff_inner_inner_inner * 128)) + (((int)blockIdx.x) * 64)) + (((int)threadIdx.x) * 8)) + nn_inner_inner_inner))] = B_local[(((ff_inner_inner_inner * 8) + nn_inner_inner_inner))];
    }
  }
}

__global__ void conv_bn_relu(void* __restrict__ A, void* __restrict__ W, void* __restrict__ mean, void* __restrict__ scale, 
                             void* __restrict__ var, void* __restrict__ beta, void* __restrict__ B) {
  float B_local[64];
  float mean_local[8];
  float scale_local[8];
  float var_local[8];
  float beta_local[8];
  float epsilon = 1e-5;
  __shared__ float Apad_shared[512];
  __shared__ float W_shared[512];
  float Apad_shared_local[8];
  float W_shared_local[8];
  for (int ff_c = 0; ff_c < 8; ++ff_c) {
    mean_local[ff_c] = ((float*)mean)[((((((int)blockIdx.y) * 64) + (((int)threadIdx.x) * 8)) + ff_c))];
    scale_local[ff_c] = ((float*)scale)[((((((int)blockIdx.y) * 64) + (((int)threadIdx.x) * 8)) + ff_c))];
    var_local[ff_c] = ((float*)var)[((((((int)blockIdx.y) * 64) + (((int)threadIdx.x) * 8)) + ff_c))];
    beta_local[ff_c] = ((float*)beta)[((((((int)blockIdx.y) * 64) + (((int)threadIdx.x) * 8)) + ff_c))];
  }
  for (int ff_c_init = 0; ff_c_init < 8; ++ff_c_init) {
    for (int nn_c_init = 0; nn_c_init < 8; ++nn_c_init) {
      B_local[(((ff_c_init * 8) + nn_c_init))] = 0.000000e+00f;
    }
  }
  for (int rc_outer = 0; rc_outer < 32; ++rc_outer) {
    for (int ry = 0; ry < 3; ++ry) {
      for (int rx = 0; rx < 3; ++rx) {
        __syncthreads();
        for (int ax3_inner_outer = 0; ax3_inner_outer < 2; ++ax3_inner_outer) {
          ((float4*)(Apad_shared + ((((((int)threadIdx.x) * 64) + (((int)threadIdx.x) * 8)) + (ax3_inner_outer * 4)))))[0] = (((((1 <= ((((int)blockIdx.z) / 14) + ry)) && (((((int)blockIdx.z) / 14) + ry) < 15)) && (1 <= (rx + (((int)blockIdx.z) % 14)))) && ((rx + (((int)blockIdx.z) % 14)) < 15)) ? ((float4*)((float*)A + ((((((((((ry * 458752) + (((int)blockIdx.z) * 32768)) + (rx * 32768)) + (rc_outer * 1024)) + (((int)threadIdx.x) * 128)) + (((int)blockIdx.x) * 64)) + (((int)threadIdx.x) * 8)) + (ax3_inner_outer * 4)) - 491520))))[0] : make_float4(0.000000e+00f, 0.000000e+00f, 0.000000e+00f, 0.000000e+00f));
        }
        for (int ax3_inner_outer1 = 0; ax3_inner_outer1 < 2; ++ax3_inner_outer1) {
          ((float4*)(W_shared + ((((((int)threadIdx.x) * 64) + (((int)threadIdx.x) * 8)) + (ax3_inner_outer1 * 4)))))[0] = ((float4*)((float*)W + ((((((((ry * 393216) + (rx * 131072)) + (rc_outer * 4096)) + (((int)threadIdx.x) * 512)) + (((int)blockIdx.y) * 64)) + (((int)threadIdx.x) * 8)) + (ax3_inner_outer1 * 4)))))[0];
        }
        __syncthreads();
        for (int rc_inner = 0; rc_inner < 8; ++rc_inner) {
          for (int ax3 = 0; ax3 < 8; ++ax3) {
            Apad_shared_local[(ax3)] = Apad_shared[((((rc_inner * 64) + (((int)threadIdx.x) * 8)) + ax3))];
          }
          for (int ax31 = 0; ax31 < 8; ++ax31) {
            W_shared_local[(ax31)] = W_shared[((((rc_inner * 64) + (((int)threadIdx.x) * 8)) + ax31))];
          }
          for (int ff_c = 0; ff_c < 8; ++ff_c) {
            for (int nn_c = 0; nn_c < 8; ++nn_c) {
              B_local[(((ff_c * 8) + nn_c))] = (B_local[(((ff_c * 8) + nn_c))] + ((Apad_shared_local[(nn_c)] * W_shared_local[(ff_c)])));
            }
          }
        }
      }
    }
  }
  for (int ff_inner_inner_inner = 0; ff_inner_inner_inner < 8; ++ff_inner_inner_inner) {
    for (int nn_inner_inner_inner = 0; nn_inner_inner_inner < 8; ++nn_inner_inner_inner) {
      ((float*)B)[((((((((((int)blockIdx.z) * 65536) + (((int)blockIdx.y) * 8192)) + (((int)threadIdx.x) * 1024)) + (ff_inner_inner_inner * 128)) + (((int)blockIdx.x) * 64)) + (((int)threadIdx.x) * 8)) + nn_inner_inner_inner))] = max(0.0, scale_local[ff_inner_inner_inner] * ( B_local[(((ff_inner_inner_inner * 8) + nn_inner_inner_inner))] - mean_local[ff_inner_inner_inner] ) / sqrt( var_local[ff_inner_inner_inner] + epsilon ) + beta_local[ff_inner_inner_inner]);
    }
  }
}

//extern "C" 
__global__ void default_function_kernel0(void* __restrict__ A, void* __restrict__ W, void* __restrict__ beta, void* __restrict__ B) {
  float B_local[64];
  float beta_local[8];
  __shared__ float Apad_shared[512];
  __shared__ float W_shared[512];
  float Apad_shared_local[8];
  float W_shared_local[8];
  for (int ff_c = 0; ff_c < 8; ++ff_c) {
    beta_local[ff_c] = ((float*)beta)[((((((int)blockIdx.y) * 64) + (((int)threadIdx.x) * 8)) + ff_c))];
  }
  for (int ff_c_init = 0; ff_c_init < 8; ++ff_c_init) {
    for (int nn_c_init = 0; nn_c_init < 8; ++nn_c_init) {
      B_local[(((ff_c_init * 8) + nn_c_init))] = 0.000000e+00f;
    }
  }
  for (int rc_outer = 0; rc_outer < 32; ++rc_outer) {
    for (int ry = 0; ry < 3; ++ry) {
      for (int rx = 0; rx < 3; ++rx) {
        __syncthreads();
        for (int ax3_inner_outer = 0; ax3_inner_outer < 2; ++ax3_inner_outer) {
          ((float4*)(Apad_shared + ((((((int)threadIdx.x) * 64) + (((int)threadIdx.x) * 8)) + (ax3_inner_outer * 4)))))[0] = (((((1 <= ((((int)blockIdx.z) / 14) + ry)) && (((((int)blockIdx.z) / 14) + ry) < 15)) && (1 <= (rx + (((int)blockIdx.z) % 14)))) && ((rx + (((int)blockIdx.z) % 14)) < 15)) ? ((float4*)((float*)A + ((((((((((ry * 458752) + (((int)blockIdx.z) * 32768)) + (rx * 32768)) + (rc_outer * 1024)) + (((int)threadIdx.x) * 128)) + (((int)blockIdx.x) * 64)) + (((int)threadIdx.x) * 8)) + (ax3_inner_outer * 4)) - 491520))))[0] : make_float4(0.000000e+00f, 0.000000e+00f, 0.000000e+00f, 0.000000e+00f));
        }
        for (int ax3_inner_outer1 = 0; ax3_inner_outer1 < 2; ++ax3_inner_outer1) {
          ((float4*)(W_shared + ((((((int)threadIdx.x) * 64) + (((int)threadIdx.x) * 8)) + (ax3_inner_outer1 * 4)))))[0] = ((float4*)((float*)W + ((((((((ry * 393216) + (rx * 131072)) + (rc_outer * 4096)) + (((int)threadIdx.x) * 512)) + (((int)blockIdx.y) * 64)) + (((int)threadIdx.x) * 8)) + (ax3_inner_outer1 * 4)))))[0];
        }
        __syncthreads();
        for (int rc_inner = 0; rc_inner < 8; ++rc_inner) {
          for (int ax3 = 0; ax3 < 8; ++ax3) {
            Apad_shared_local[(ax3)] = Apad_shared[((((rc_inner * 64) + (((int)threadIdx.x) * 8)) + ax3))];
          }
          for (int ax31 = 0; ax31 < 8; ++ax31) {
            W_shared_local[(ax31)] = W_shared[((((rc_inner * 64) + (((int)threadIdx.x) * 8)) + ax31))];
          }
          for (int ff_c = 0; ff_c < 8; ++ff_c) {
            for (int nn_c = 0; nn_c < 8; ++nn_c) {
              B_local[(((ff_c * 8) + nn_c))] = (B_local[(((ff_c * 8) + nn_c))] + ((Apad_shared_local[(nn_c)] * W_shared_local[(ff_c)])));
            }
          }
        }
      }
    }
  }
  for (int ff_inner_inner_inner = 0; ff_inner_inner_inner < 8; ++ff_inner_inner_inner) {
    for (int nn_inner_inner_inner = 0; nn_inner_inner_inner < 8; ++nn_inner_inner_inner) {
      ((float*)B)[((((((((((int)blockIdx.z) * 65536) + (((int)blockIdx.y) * 8192)) + (((int)threadIdx.x) * 1024)) + (ff_inner_inner_inner * 128)) + (((int)blockIdx.x) * 64)) + (((int)threadIdx.x) * 8)) + nn_inner_inner_inner))] = B_local[(((ff_inner_inner_inner * 8) + nn_inner_inner_inner))] + beta_local[ff_inner_inner_inner];
    }
  }
}

double get_durtime(struct timeval t1, struct timeval t2) {
    return (1000000.0*(t2.tv_sec-t1.tv_sec) + t2.tv_usec-t1.tv_usec)/1000.0;
}

int main() {
    const int batch = 128, in_channel = 256, out_channel = 512, in_height = 14, in_width = 14;
    const int kernel_width = 3, kernel_height = 3, pad_height = 1, pad_width = 1;
    const int stride_height = 1, stride_width = 1;
    const int out_width = (in_width - kernel_width + 2*pad_width) / stride_width + 1;
    const int out_height = (in_height - kernel_height + 2*pad_height) / stride_height + 1;
    float *A, *W, *B, *mean, *scale, *var, *beta;
    int in_size = batch*in_channel*in_height*in_width;
    int kernel_size = kernel_width*kernel_height*out_channel*in_channel;
    int out_size = batch*out_channel*out_width*out_height;
    struct timeval start, end;
    A = (float*)malloc(in_size*sizeof(float));
    W = (float*)malloc(kernel_size*sizeof(float));
    B = (float*)malloc(out_size*sizeof(float));
    mean = (float*)malloc(out_channel*sizeof(float));
    scale = (float*)malloc(out_channel*sizeof(float));
    var = (float*)malloc(out_channel*sizeof(float));
    beta = (float*)malloc(out_channel*sizeof(float));
    float *Ad, *Wd, *Bd, *meand, *scaled, *vard, *betad;
    HANDLE_ERROR(cudaMalloc((void**)&Ad, in_size*sizeof(float)));
    HANDLE_ERROR(cudaMalloc((void**)&Wd, kernel_size*sizeof(float)));
    HANDLE_ERROR(cudaMalloc((void**)&Bd, out_size*sizeof(float)));
    HANDLE_ERROR(cudaMalloc((void**)&meand, out_channel*sizeof(float)));
    HANDLE_ERROR(cudaMalloc((void**)&scaled, out_channel*sizeof(float)));
    HANDLE_ERROR(cudaMalloc((void**)&vard, out_channel*sizeof(float)));
    HANDLE_ERROR(cudaMalloc((void**)&betad, out_channel*sizeof(float)));
    for (int i = 0; i < in_size; ++i)
        A[i] = i;
    for (int i = 0; i < kernel_size; ++i)
        W[i] = i;
    for (int i = 0; i < out_channel; ++i) {
        mean[i] = i;
        scale[i] = i;
        var[i] = i;
        beta[i] = i;
    }
    HANDLE_ERROR(cudaMemcpy(Ad, A, in_size*sizeof(float), cudaMemcpyHostToDevice));
    HANDLE_ERROR(cudaMemcpy(Wd, W, kernel_size*sizeof(float), cudaMemcpyHostToDevice));
    HANDLE_ERROR(cudaMemcpy(meand, mean, out_channel*sizeof(float), cudaMemcpyHostToDevice));
    HANDLE_ERROR(cudaMemcpy(scaled, scale, out_channel*sizeof(float), cudaMemcpyHostToDevice));
    HANDLE_ERROR(cudaMemcpy(vard, var, out_channel*sizeof(float), cudaMemcpyHostToDevice));
    HANDLE_ERROR(cudaMemcpy(betad, beta, out_channel*sizeof(float), cudaMemcpyHostToDevice));

    dim3 grid(2, 8, 196), block(8, 1, 1);
	HANDLE_ERROR(cudaDeviceSynchronize());
    //HANDLE_ERROR(default_function_kernel0<<<grid, block>>>(Ad, Wd, betad, Bd));
    gettimeofday(&start, 0);
    conv_bn_relu<<<grid, block>>>(Ad, Wd, meand, scaled, vard, betad, Bd);
	HANDLE_ERROR(cudaDeviceSynchronize());
    gettimeofday(&end, 0);
    std::cout << "time: " << get_durtime(start, end) << "ms" << std::endl;
    HANDLE_ERROR(cudaMemcpy(B, Bd, out_size*sizeof(float), cudaMemcpyDeviceToHost));
    HANDLE_ERROR(cudaFree(Ad));
    HANDLE_ERROR(cudaFree(Bd));
    HANDLE_ERROR(cudaFree(Wd));
    HANDLE_ERROR(cudaFree(meand));
    HANDLE_ERROR(cudaFree(scaled));
    HANDLE_ERROR(cudaFree(vard));
    HANDLE_ERROR(cudaFree(betad));
    return 0;
}

	.file	"tmpxft_00325edd_00000000-6_conv_bn_relu_fuse_test.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3640:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3640:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"/home/ubuntu/Datasets/stackv2/train-structured/LegendBC/PET/master/benchmark/fusion/conv_bn_relu_fuse_test.cu"
.LC1:
	.string	"%s in %s at line %d\n"
	.text
	.type	_ZL11HandleError9cudaErrorPKci.constprop.0, @function
_ZL11HandleError9cudaErrorPKci.constprop.0:
.LFB4300:
	.cfi_startproc
	testl	%edi, %edi
	je	.L2
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	%esi, 12(%rsp)
	call	cudaGetErrorString@PLT
	movl	12(%rsp), %r8d
	movl	$2, %edi
	leaq	.LC0(%rip), %rcx
	movq	%rax, %rdx
	leaq	.LC1(%rip), %rsi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movl	$1, %edi
	call	exit@PLT
.L2:
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4300:
	.size	_ZL11HandleError9cudaErrorPKci.constprop.0, .-_ZL11HandleError9cudaErrorPKci.constprop.0
	.globl	_Z11get_durtime7timevalS_
	.type	_Z11get_durtime7timevalS_, @function
_Z11get_durtime7timevalS_:
.LFB3636:
	.cfi_startproc
	endbr64
	subq	%rdi, %rdx
	cvtsi2sdq	%rcx, %xmm1
	cvtsi2sdq	%rdx, %xmm0
	mulsd	.LC2(%rip), %xmm0
	addsd	%xmm1, %xmm0
	cvtsi2sdq	%rsi, %xmm1
	subsd	%xmm1, %xmm0
	divsd	.LC3(%rip), %xmm0
	ret
	.cfi_endproc
.LFE3636:
	.size	_Z11get_durtime7timevalS_, .-_Z11get_durtime7timevalS_
	.globl	_Z27__device_stub__Z4convPvS_S_PvS_S_
	.type	_Z27__device_stub__Z4convPvS_S_PvS_S_, @function
_Z27__device_stub__Z4convPvS_S_PvS_S_:
.LFB3662:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movq	%rdi, 8(%rsp)
	leaq	40(%rsp), %rcx
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	leaq	48(%rsp), %rdi
	movq	%rax, 104(%rsp)
	leaq	24(%rsp), %rax
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	32(%rsp), %rdx
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movl	$1, 56(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L9
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z4convPvS_S_(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L9:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L11
	call	__stack_chk_fail@PLT
.L11:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3662:
	.size	_Z27__device_stub__Z4convPvS_S_PvS_S_, .-_Z27__device_stub__Z4convPvS_S_PvS_S_
	.globl	_Z4convPvS_S_
	.type	_Z4convPvS_S_, @function
_Z4convPvS_S_:
.LFB3663:
	.cfi_startproc
	endbr64
	jmp	_Z27__device_stub__Z4convPvS_S_PvS_S_
	.cfi_endproc
.LFE3663:
	.size	_Z4convPvS_S_, .-_Z4convPvS_S_
	.globl	_Z44__device_stub__Z12conv_bn_reluPvS_S_S_S_S_S_PvS_S_S_S_S_S_
	.type	_Z44__device_stub__Z12conv_bn_reluPvS_S_S_S_S_S_PvS_S_S_S_S_S_, @function
_Z44__device_stub__Z12conv_bn_reluPvS_S_S_S_S_S_PvS_S_S_S_S_S_:
.LFB3664:
	.cfi_startproc
	endbr64
	subq	$200, %rsp
	.cfi_def_cfa_offset 208
	movq	%fs:40, %rax
	movq	%rax, 184(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movq	%rdi, 8(%rsp)
	leaq	80(%rsp), %rdi
	movq	%rax, 128(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 168(%rsp)
	movq	208(%rsp), %rax
	movq	%rsi, 16(%rsp)
	leaq	92(%rsp), %rsi
	movq	%rax, 56(%rsp)
	leaq	56(%rsp), %rax
	movq	%rdx, 24(%rsp)
	leaq	64(%rsp), %rdx
	movq	%rcx, 32(%rsp)
	leaq	72(%rsp), %rcx
	movq	%rax, 176(%rsp)
	movabsq	$4294967297, %rax
	movq	%r8, 40(%rsp)
	movq	%r9, 48(%rsp)
	movq	%rax, 80(%rsp)
	movl	$1, 88(%rsp)
	movq	%rax, 92(%rsp)
	movl	$1, 100(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L14
	pushq	72(%rsp)
	.cfi_def_cfa_offset 216
	leaq	_Z12conv_bn_reluPvS_S_S_S_S_S_(%rip), %rdi
	pushq	72(%rsp)
	.cfi_def_cfa_offset 224
	movq	108(%rsp), %rcx
	movl	116(%rsp), %r8d
	movq	96(%rsp), %rsi
	movl	104(%rsp), %edx
	leaq	144(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 216
	popq	%rdx
	.cfi_def_cfa_offset 208
.L14:
	movq	184(%rsp), %rax
	subq	%fs:40, %rax
	je	.L16
	call	__stack_chk_fail@PLT
.L16:
	addq	$200, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3664:
	.size	_Z44__device_stub__Z12conv_bn_reluPvS_S_S_S_S_S_PvS_S_S_S_S_S_, .-_Z44__device_stub__Z12conv_bn_reluPvS_S_S_S_S_S_PvS_S_S_S_S_S_
	.globl	_Z12conv_bn_reluPvS_S_S_S_S_S_
	.type	_Z12conv_bn_reluPvS_S_S_S_S_S_, @function
_Z12conv_bn_reluPvS_S_S_S_S_S_:
.LFB3665:
	.cfi_startproc
	endbr64
	jmp	_Z44__device_stub__Z12conv_bn_reluPvS_S_S_S_S_S_PvS_S_S_S_S_S_
	.cfi_endproc
.LFE3665:
	.size	_Z12conv_bn_reluPvS_S_S_S_S_S_, .-_Z12conv_bn_reluPvS_S_S_S_S_S_
	.section	.rodata.str1.1
.LC4:
	.string	"time: "
.LC5:
	.string	"ms"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB3637:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movl	$25690112, %edi
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$152, %rsp
	.cfi_def_cfa_offset 208
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	call	malloc@PLT
	movl	$4718592, %edi
	movq	%rax, %r15
	call	malloc@PLT
	movl	$51380224, %edi
	movq	%rax, %r14
	call	malloc@PLT
	movl	$2048, %edi
	movq	%rax, 8(%rsp)
	call	malloc@PLT
	movl	$2048, %edi
	movq	%rax, %r13
	call	malloc@PLT
	movl	$2048, %edi
	movq	%rax, %r12
	call	malloc@PLT
	movl	$2048, %edi
	movq	%rax, %rbp
	call	malloc@PLT
	leaq	24(%rsp), %rdi
	movl	$25690112, %esi
	movq	%rax, %rbx
	call	cudaMalloc@PLT
	movl	$189, %esi
	movl	%eax, %edi
	call	_ZL11HandleError9cudaErrorPKci.constprop.0
	leaq	32(%rsp), %rdi
	movl	$4718592, %esi
	call	cudaMalloc@PLT
	movl	$190, %esi
	movl	%eax, %edi
	call	_ZL11HandleError9cudaErrorPKci.constprop.0
	leaq	40(%rsp), %rdi
	movl	$51380224, %esi
	call	cudaMalloc@PLT
	movl	$191, %esi
	movl	%eax, %edi
	call	_ZL11HandleError9cudaErrorPKci.constprop.0
	leaq	48(%rsp), %rdi
	movl	$2048, %esi
	call	cudaMalloc@PLT
	movl	$192, %esi
	movl	%eax, %edi
	call	_ZL11HandleError9cudaErrorPKci.constprop.0
	leaq	56(%rsp), %rdi
	movl	$2048, %esi
	call	cudaMalloc@PLT
	movl	$193, %esi
	movl	%eax, %edi
	call	_ZL11HandleError9cudaErrorPKci.constprop.0
	leaq	64(%rsp), %rdi
	movl	$2048, %esi
	call	cudaMalloc@PLT
	movl	$194, %esi
	movl	%eax, %edi
	call	_ZL11HandleError9cudaErrorPKci.constprop.0
	leaq	72(%rsp), %rdi
	movl	$2048, %esi
	call	cudaMalloc@PLT
	movl	$195, %esi
	movl	%eax, %edi
	call	_ZL11HandleError9cudaErrorPKci.constprop.0
	xorl	%eax, %eax
.L20:
	cvtsi2ssl	%eax, %xmm0
	movss	%xmm0, (%r15,%rax,4)
	incq	%rax
	cmpq	$6422528, %rax
	jne	.L20
	xorl	%eax, %eax
.L21:
	cvtsi2ssl	%eax, %xmm0
	movss	%xmm0, (%r14,%rax,4)
	incq	%rax
	cmpq	$1179648, %rax
	jne	.L21
	xorl	%eax, %eax
.L22:
	cvtsi2ssl	%eax, %xmm0
	movss	%xmm0, 0(%r13,%rax,4)
	movss	%xmm0, (%r12,%rax,4)
	movss	%xmm0, 0(%rbp,%rax,4)
	movss	%xmm0, (%rbx,%rax,4)
	incq	%rax
	cmpq	$512, %rax
	jne	.L22
	movq	24(%rsp), %rdi
	movl	$1, %ecx
	movl	$25690112, %edx
	movq	%r15, %rsi
	call	cudaMemcpy@PLT
	movl	$206, %esi
	movl	%eax, %edi
	call	_ZL11HandleError9cudaErrorPKci.constprop.0
	movq	32(%rsp), %rdi
	movl	$1, %ecx
	movq	%r14, %rsi
	movl	$4718592, %edx
	call	cudaMemcpy@PLT
	movl	$207, %esi
	movl	%eax, %edi
	call	_ZL11HandleError9cudaErrorPKci.constprop.0
	movq	48(%rsp), %rdi
	movl	$1, %ecx
	movq	%r13, %rsi
	movl	$2048, %edx
	call	cudaMemcpy@PLT
	movl	$208, %esi
	movl	%eax, %edi
	call	_ZL11HandleError9cudaErrorPKci.constprop.0
	movq	56(%rsp), %rdi
	movl	$1, %ecx
	movq	%r12, %rsi
	movl	$2048, %edx
	call	cudaMemcpy@PLT
	movl	$209, %esi
	movl	%eax, %edi
	call	_ZL11HandleError9cudaErrorPKci.constprop.0
	movq	64(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbp, %rsi
	movl	$2048, %edx
	call	cudaMemcpy@PLT
	movl	$210, %esi
	movl	%eax, %edi
	call	_ZL11HandleError9cudaErrorPKci.constprop.0
	movq	72(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbx, %rsi
	movl	$2048, %edx
	call	cudaMemcpy@PLT
	movl	$211, %esi
	movl	%eax, %edi
	call	_ZL11HandleError9cudaErrorPKci.constprop.0
	movl	$196, 88(%rsp)
	movabsq	$34359738370, %rax
	movq	%rax, 80(%rsp)
	movl	$536870913, %eax
	salq	$3, %rax
	movl	$1, 100(%rsp)
	movq	%rax, 92(%rsp)
	call	cudaDeviceSynchronize@PLT
	movl	$214, %esi
	movl	%eax, %edi
	call	_ZL11HandleError9cudaErrorPKci.constprop.0
	xorl	%esi, %esi
	leaq	104(%rsp), %rdi
	call	gettimeofday@PLT
	movl	100(%rsp), %ecx
	movl	88(%rsp), %esi
	xorl	%r9d, %r9d
	movq	92(%rsp), %rdx
	movq	80(%rsp), %rdi
	xorl	%r8d, %r8d
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L23
	pushq	%rax
	.cfi_def_cfa_offset 216
	pushq	48(%rsp)
	.cfi_def_cfa_offset 224
	movq	88(%rsp), %r9
	movq	80(%rsp), %r8
	movq	72(%rsp), %rcx
	movq	64(%rsp), %rdx
	movq	48(%rsp), %rsi
	movq	40(%rsp), %rdi
	call	_Z44__device_stub__Z12conv_bn_reluPvS_S_S_S_S_S_PvS_S_S_S_S_S_
	popq	%rdx
	.cfi_def_cfa_offset 216
	popq	%rcx
	.cfi_def_cfa_offset 208
.L23:
	call	cudaDeviceSynchronize@PLT
	movl	$218, %esi
	movl	%eax, %edi
	call	_ZL11HandleError9cudaErrorPKci.constprop.0
	xorl	%esi, %esi
	leaq	120(%rsp), %rdi
	call	gettimeofday@PLT
	leaq	.LC4(%rip), %rsi
	leaq	_ZSt4cout(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	120(%rsp), %rdx
	movq	104(%rsp), %rdi
	movq	128(%rsp), %rcx
	movq	112(%rsp), %rsi
	call	_Z11get_durtime7timevalS_
	movq	%rax, %rdi
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	leaq	.LC5(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%rax, %rdi
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
	movq	40(%rsp), %rsi
	movq	8(%rsp), %rdi
	movl	$2, %ecx
	movl	$51380224, %edx
	call	cudaMemcpy@PLT
	movl	$221, %esi
	movl	%eax, %edi
	call	_ZL11HandleError9cudaErrorPKci.constprop.0
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	movl	$222, %esi
	movl	%eax, %edi
	call	_ZL11HandleError9cudaErrorPKci.constprop.0
	movq	40(%rsp), %rdi
	call	cudaFree@PLT
	movl	$223, %esi
	movl	%eax, %edi
	call	_ZL11HandleError9cudaErrorPKci.constprop.0
	movq	32(%rsp), %rdi
	call	cudaFree@PLT
	movl	$224, %esi
	movl	%eax, %edi
	call	_ZL11HandleError9cudaErrorPKci.constprop.0
	movq	48(%rsp), %rdi
	call	cudaFree@PLT
	movl	$225, %esi
	movl	%eax, %edi
	call	_ZL11HandleError9cudaErrorPKci.constprop.0
	movq	56(%rsp), %rdi
	call	cudaFree@PLT
	movl	$226, %esi
	movl	%eax, %edi
	call	_ZL11HandleError9cudaErrorPKci.constprop.0
	movq	64(%rsp), %rdi
	call	cudaFree@PLT
	movl	$227, %esi
	movl	%eax, %edi
	call	_ZL11HandleError9cudaErrorPKci.constprop.0
	movq	72(%rsp), %rdi
	call	cudaFree@PLT
	movl	$228, %esi
	movl	%eax, %edi
	call	_ZL11HandleError9cudaErrorPKci.constprop.0
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L24
	call	__stack_chk_fail@PLT
.L24:
	addq	$152, %rsp
	.cfi_def_cfa_offset 56
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3637:
	.size	main, .-main
	.text
	.globl	_Z50__device_stub__Z24default_function_kernel0PvS_S_S_PvS_S_S_
	.type	_Z50__device_stub__Z24default_function_kernel0PvS_S_S_PvS_S_S_, @function
_Z50__device_stub__Z24default_function_kernel0PvS_S_S_PvS_S_S_:
.LFB3666:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movq	%rdi, 8(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	40(%rsp), %rdx
	movq	%rcx, 32(%rsp)
	leaq	48(%rsp), %rcx
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movl	$1, 64(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L29
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z24default_function_kernel0PvS_S_S_(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L29:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L31
	call	__stack_chk_fail@PLT
.L31:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3666:
	.size	_Z50__device_stub__Z24default_function_kernel0PvS_S_S_PvS_S_S_, .-_Z50__device_stub__Z24default_function_kernel0PvS_S_S_PvS_S_S_
	.globl	_Z24default_function_kernel0PvS_S_S_
	.type	_Z24default_function_kernel0PvS_S_S_, @function
_Z24default_function_kernel0PvS_S_S_:
.LFB3667:
	.cfi_startproc
	endbr64
	jmp	_Z50__device_stub__Z24default_function_kernel0PvS_S_S_PvS_S_S_
	.cfi_endproc
.LFE3667:
	.size	_Z24default_function_kernel0PvS_S_S_, .-_Z24default_function_kernel0PvS_S_S_
	.section	.rodata.str1.1
.LC6:
	.string	"_Z24default_function_kernel0PvS_S_S_"
.LC7:
	.string	"_Z12conv_bn_reluPvS_S_S_S_S_S_"
.LC8:
	.string	"_Z4convPvS_S_"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3669:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC6(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z24default_function_kernel0PvS_S_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC7(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z12conv_bn_reluPvS_S_S_S_S_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC8(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z4convPvS_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3669:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst8,"aM",@progbits,8
	.align 8
.LC2:
	.long	0
	.long	1093567616
	.align 8
.LC3:
	.long	0
	.long	1083129856
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <hip/hip_runtime.h>
#include <iostream>
#include <stdio.h>
#include <sys/time.h>

static void HandleError( hipError_t err, const char *file, int line ) {
    if (err != hipSuccess) {
        printf( "%s in %s at line %d\n", hipGetErrorString( err ),file, line );
        exit( EXIT_FAILURE );    
    }
}
#define HANDLE_ERROR( err ) (HandleError( err, __FILE__, __LINE__ ))

__global__ void conv(void* __restrict__ A, void* __restrict__ W, void* __restrict__ B) {
  float B_local[64];
  __shared__ float Apad_shared[512];
  __shared__ float W_shared[512];
  float Apad_shared_local[8];
  float W_shared_local[8];
  for (int ff_c_init = 0; ff_c_init < 8; ++ff_c_init) {
    for (int nn_c_init = 0; nn_c_init < 8; ++nn_c_init) {
      B_local[(((ff_c_init * 8) + nn_c_init))] = 0.000000e+00f;
    }
  }
  for (int rc_outer = 0; rc_outer < 32; ++rc_outer) {
    for (int ry = 0; ry < 3; ++ry) {
      for (int rx = 0; rx < 3; ++rx) {
        __syncthreads();
        for (int ax3_inner_outer = 0; ax3_inner_outer < 2; ++ax3_inner_outer) {
          ((float4*)(Apad_shared + ((((((int)threadIdx.x) * 64) + (((int)threadIdx.x) * 8)) + (ax3_inner_outer * 4)))))[0] = (((((1 <= ((((int)blockIdx.z) / 14) + ry)) && (((((int)blockIdx.z) / 14) + ry) < 15)) && (1 <= (rx + (((int)blockIdx.z) % 14)))) && ((rx + (((int)blockIdx.z) % 14)) < 15)) ? ((float4*)((float*)A + ((((((((((ry * 458752) + (((int)blockIdx.z) * 32768)) + (rx * 32768)) + (rc_outer * 1024)) + (((int)threadIdx.x) * 128)) + (((int)blockIdx.x) * 64)) + (((int)threadIdx.x) * 8)) + (ax3_inner_outer * 4)) - 491520))))[0] : make_float4(0.000000e+00f, 0.000000e+00f, 0.000000e+00f, 0.000000e+00f));
        }
        for (int ax3_inner_outer1 = 0; ax3_inner_outer1 < 2; ++ax3_inner_outer1) {
          ((float4*)(W_shared + ((((((int)threadIdx.x) * 64) + (((int)threadIdx.x) * 8)) + (ax3_inner_outer1 * 4)))))[0] = ((float4*)((float*)W + ((((((((ry * 393216) + (rx * 131072)) + (rc_outer * 4096)) + (((int)threadIdx.x) * 512)) + (((int)blockIdx.y) * 64)) + (((int)threadIdx.x) * 8)) + (ax3_inner_outer1 * 4)))))[0];
        }
        __syncthreads();
        for (int rc_inner = 0; rc_inner < 8; ++rc_inner) {
          for (int ax3 = 0; ax3 < 8; ++ax3) {
            Apad_shared_local[(ax3)] = Apad_shared[((((rc_inner * 64) + (((int)threadIdx.x) * 8)) + ax3))];
          }
          for (int ax31 = 0; ax31 < 8; ++ax31) {
            W_shared_local[(ax31)] = W_shared[((((rc_inner * 64) + (((int)threadIdx.x) * 8)) + ax31))];
          }
          for (int ff_c = 0; ff_c < 8; ++ff_c) {
            for (int nn_c = 0; nn_c < 8; ++nn_c) {
              B_local[(((ff_c * 8) + nn_c))] = (B_local[(((ff_c * 8) + nn_c))] + ((Apad_shared_local[(nn_c)] * W_shared_local[(ff_c)])));
            }
          }
        }
      }
    }
  }
  for (int ff_inner_inner_inner = 0; ff_inner_inner_inner < 8; ++ff_inner_inner_inner) {
    for (int nn_inner_inner_inner = 0; nn_inner_inner_inner < 8; ++nn_inner_inner_inner) {
      ((float*)B)[((((((((((int)blockIdx.z) * 65536) + (((int)blockIdx.y) * 8192)) + (((int)threadIdx.x) * 1024)) + (ff_inner_inner_inner * 128)) + (((int)blockIdx.x) * 64)) + (((int)threadIdx.x) * 8)) + nn_inner_inner_inner))] = B_local[(((ff_inner_inner_inner * 8) + nn_inner_inner_inner))];
    }
  }
}

__global__ void conv_bn_relu(void* __restrict__ A, void* __restrict__ W, void* __restrict__ mean, void* __restrict__ scale, 
                             void* __restrict__ var, void* __restrict__ beta, void* __restrict__ B) {
  float B_local[64];
  float mean_local[8];
  float scale_local[8];
  float var_local[8];
  float beta_local[8];
  float epsilon = 1e-5;
  __shared__ float Apad_shared[512];
  __shared__ float W_shared[512];
  float Apad_shared_local[8];
  float W_shared_local[8];
  for (int ff_c = 0; ff_c < 8; ++ff_c) {
    mean_local[ff_c] = ((float*)mean)[((((((int)blockIdx.y) * 64) + (((int)threadIdx.x) * 8)) + ff_c))];
    scale_local[ff_c] = ((float*)scale)[((((((int)blockIdx.y) * 64) + (((int)threadIdx.x) * 8)) + ff_c))];
    var_local[ff_c] = ((float*)var)[((((((int)blockIdx.y) * 64) + (((int)threadIdx.x) * 8)) + ff_c))];
    beta_local[ff_c] = ((float*)beta)[((((((int)blockIdx.y) * 64) + (((int)threadIdx.x) * 8)) + ff_c))];
  }
  for (int ff_c_init = 0; ff_c_init < 8; ++ff_c_init) {
    for (int nn_c_init = 0; nn_c_init < 8; ++nn_c_init) {
      B_local[(((ff_c_init * 8) + nn_c_init))] = 0.000000e+00f;
    }
  }
  for (int rc_outer = 0; rc_outer < 32; ++rc_outer) {
    for (int ry = 0; ry < 3; ++ry) {
      for (int rx = 0; rx < 3; ++rx) {
        __syncthreads();
        for (int ax3_inner_outer = 0; ax3_inner_outer < 2; ++ax3_inner_outer) {
          ((float4*)(Apad_shared + ((((((int)threadIdx.x) * 64) + (((int)threadIdx.x) * 8)) + (ax3_inner_outer * 4)))))[0] = (((((1 <= ((((int)blockIdx.z) / 14) + ry)) && (((((int)blockIdx.z) / 14) + ry) < 15)) && (1 <= (rx + (((int)blockIdx.z) % 14)))) && ((rx + (((int)blockIdx.z) % 14)) < 15)) ? ((float4*)((float*)A + ((((((((((ry * 458752) + (((int)blockIdx.z) * 32768)) + (rx * 32768)) + (rc_outer * 1024)) + (((int)threadIdx.x) * 128)) + (((int)blockIdx.x) * 64)) + (((int)threadIdx.x) * 8)) + (ax3_inner_outer * 4)) - 491520))))[0] : make_float4(0.000000e+00f, 0.000000e+00f, 0.000000e+00f, 0.000000e+00f));
        }
        for (int ax3_inner_outer1 = 0; ax3_inner_outer1 < 2; ++ax3_inner_outer1) {
          ((float4*)(W_shared + ((((((int)threadIdx.x) * 64) + (((int)threadIdx.x) * 8)) + (ax3_inner_outer1 * 4)))))[0] = ((float4*)((float*)W + ((((((((ry * 393216) + (rx * 131072)) + (rc_outer * 4096)) + (((int)threadIdx.x) * 512)) + (((int)blockIdx.y) * 64)) + (((int)threadIdx.x) * 8)) + (ax3_inner_outer1 * 4)))))[0];
        }
        __syncthreads();
        for (int rc_inner = 0; rc_inner < 8; ++rc_inner) {
          for (int ax3 = 0; ax3 < 8; ++ax3) {
            Apad_shared_local[(ax3)] = Apad_shared[((((rc_inner * 64) + (((int)threadIdx.x) * 8)) + ax3))];
          }
          for (int ax31 = 0; ax31 < 8; ++ax31) {
            W_shared_local[(ax31)] = W_shared[((((rc_inner * 64) + (((int)threadIdx.x) * 8)) + ax31))];
          }
          for (int ff_c = 0; ff_c < 8; ++ff_c) {
            for (int nn_c = 0; nn_c < 8; ++nn_c) {
              B_local[(((ff_c * 8) + nn_c))] = (B_local[(((ff_c * 8) + nn_c))] + ((Apad_shared_local[(nn_c)] * W_shared_local[(ff_c)])));
            }
          }
        }
      }
    }
  }
  for (int ff_inner_inner_inner = 0; ff_inner_inner_inner < 8; ++ff_inner_inner_inner) {
    for (int nn_inner_inner_inner = 0; nn_inner_inner_inner < 8; ++nn_inner_inner_inner) {
      ((float*)B)[((((((((((int)blockIdx.z) * 65536) + (((int)blockIdx.y) * 8192)) + (((int)threadIdx.x) * 1024)) + (ff_inner_inner_inner * 128)) + (((int)blockIdx.x) * 64)) + (((int)threadIdx.x) * 8)) + nn_inner_inner_inner))] = max(0.0, scale_local[ff_inner_inner_inner] * ( B_local[(((ff_inner_inner_inner * 8) + nn_inner_inner_inner))] - mean_local[ff_inner_inner_inner] ) / sqrt( var_local[ff_inner_inner_inner] + epsilon ) + beta_local[ff_inner_inner_inner]);
    }
  }
}

//extern "C" 
__global__ void default_function_kernel0(void* __restrict__ A, void* __restrict__ W, void* __restrict__ beta, void* __restrict__ B) {
  float B_local[64];
  float beta_local[8];
  __shared__ float Apad_shared[512];
  __shared__ float W_shared[512];
  float Apad_shared_local[8];
  float W_shared_local[8];
  for (int ff_c = 0; ff_c < 8; ++ff_c) {
    beta_local[ff_c] = ((float*)beta)[((((((int)blockIdx.y) * 64) + (((int)threadIdx.x) * 8)) + ff_c))];
  }
  for (int ff_c_init = 0; ff_c_init < 8; ++ff_c_init) {
    for (int nn_c_init = 0; nn_c_init < 8; ++nn_c_init) {
      B_local[(((ff_c_init * 8) + nn_c_init))] = 0.000000e+00f;
    }
  }
  for (int rc_outer = 0; rc_outer < 32; ++rc_outer) {
    for (int ry = 0; ry < 3; ++ry) {
      for (int rx = 0; rx < 3; ++rx) {
        __syncthreads();
        for (int ax3_inner_outer = 0; ax3_inner_outer < 2; ++ax3_inner_outer) {
          ((float4*)(Apad_shared + ((((((int)threadIdx.x) * 64) + (((int)threadIdx.x) * 8)) + (ax3_inner_outer * 4)))))[0] = (((((1 <= ((((int)blockIdx.z) / 14) + ry)) && (((((int)blockIdx.z) / 14) + ry) < 15)) && (1 <= (rx + (((int)blockIdx.z) % 14)))) && ((rx + (((int)blockIdx.z) % 14)) < 15)) ? ((float4*)((float*)A + ((((((((((ry * 458752) + (((int)blockIdx.z) * 32768)) + (rx * 32768)) + (rc_outer * 1024)) + (((int)threadIdx.x) * 128)) + (((int)blockIdx.x) * 64)) + (((int)threadIdx.x) * 8)) + (ax3_inner_outer * 4)) - 491520))))[0] : make_float4(0.000000e+00f, 0.000000e+00f, 0.000000e+00f, 0.000000e+00f));
        }
        for (int ax3_inner_outer1 = 0; ax3_inner_outer1 < 2; ++ax3_inner_outer1) {
          ((float4*)(W_shared + ((((((int)threadIdx.x) * 64) + (((int)threadIdx.x) * 8)) + (ax3_inner_outer1 * 4)))))[0] = ((float4*)((float*)W + ((((((((ry * 393216) + (rx * 131072)) + (rc_outer * 4096)) + (((int)threadIdx.x) * 512)) + (((int)blockIdx.y) * 64)) + (((int)threadIdx.x) * 8)) + (ax3_inner_outer1 * 4)))))[0];
        }
        __syncthreads();
        for (int rc_inner = 0; rc_inner < 8; ++rc_inner) {
          for (int ax3 = 0; ax3 < 8; ++ax3) {
            Apad_shared_local[(ax3)] = Apad_shared[((((rc_inner * 64) + (((int)threadIdx.x) * 8)) + ax3))];
          }
          for (int ax31 = 0; ax31 < 8; ++ax31) {
            W_shared_local[(ax31)] = W_shared[((((rc_inner * 64) + (((int)threadIdx.x) * 8)) + ax31))];
          }
          for (int ff_c = 0; ff_c < 8; ++ff_c) {
            for (int nn_c = 0; nn_c < 8; ++nn_c) {
              B_local[(((ff_c * 8) + nn_c))] = (B_local[(((ff_c * 8) + nn_c))] + ((Apad_shared_local[(nn_c)] * W_shared_local[(ff_c)])));
            }
          }
        }
      }
    }
  }
  for (int ff_inner_inner_inner = 0; ff_inner_inner_inner < 8; ++ff_inner_inner_inner) {
    for (int nn_inner_inner_inner = 0; nn_inner_inner_inner < 8; ++nn_inner_inner_inner) {
      ((float*)B)[((((((((((int)blockIdx.z) * 65536) + (((int)blockIdx.y) * 8192)) + (((int)threadIdx.x) * 1024)) + (ff_inner_inner_inner * 128)) + (((int)blockIdx.x) * 64)) + (((int)threadIdx.x) * 8)) + nn_inner_inner_inner))] = B_local[(((ff_inner_inner_inner * 8) + nn_inner_inner_inner))] + beta_local[ff_inner_inner_inner];
    }
  }
}

double get_durtime(struct timeval t1, struct timeval t2) {
    return (1000000.0*(t2.tv_sec-t1.tv_sec) + t2.tv_usec-t1.tv_usec)/1000.0;
}

int main() {
    const int batch = 128, in_channel = 256, out_channel = 512, in_height = 14, in_width = 14;
    const int kernel_width = 3, kernel_height = 3, pad_height = 1, pad_width = 1;
    const int stride_height = 1, stride_width = 1;
    const int out_width = (in_width - kernel_width + 2*pad_width) / stride_width + 1;
    const int out_height = (in_height - kernel_height + 2*pad_height) / stride_height + 1;
    float *A, *W, *B, *mean, *scale, *var, *beta;
    int in_size = batch*in_channel*in_height*in_width;
    int kernel_size = kernel_width*kernel_height*out_channel*in_channel;
    int out_size = batch*out_channel*out_width*out_height;
    struct timeval start, end;
    A = (float*)malloc(in_size*sizeof(float));
    W = (float*)malloc(kernel_size*sizeof(float));
    B = (float*)malloc(out_size*sizeof(float));
    mean = (float*)malloc(out_channel*sizeof(float));
    scale = (float*)malloc(out_channel*sizeof(float));
    var = (float*)malloc(out_channel*sizeof(float));
    beta = (float*)malloc(out_channel*sizeof(float));
    float *Ad, *Wd, *Bd, *meand, *scaled, *vard, *betad;
    HANDLE_ERROR(hipMalloc((void**)&Ad, in_size*sizeof(float)));
    HANDLE_ERROR(hipMalloc((void**)&Wd, kernel_size*sizeof(float)));
    HANDLE_ERROR(hipMalloc((void**)&Bd, out_size*sizeof(float)));
    HANDLE_ERROR(hipMalloc((void**)&meand, out_channel*sizeof(float)));
    HANDLE_ERROR(hipMalloc((void**)&scaled, out_channel*sizeof(float)));
    HANDLE_ERROR(hipMalloc((void**)&vard, out_channel*sizeof(float)));
    HANDLE_ERROR(hipMalloc((void**)&betad, out_channel*sizeof(float)));
    for (int i = 0; i < in_size; ++i)
        A[i] = i;
    for (int i = 0; i < kernel_size; ++i)
        W[i] = i;
    for (int i = 0; i < out_channel; ++i) {
        mean[i] = i;
        scale[i] = i;
        var[i] = i;
        beta[i] = i;
    }
    HANDLE_ERROR(hipMemcpy(Ad, A, in_size*sizeof(float), hipMemcpyHostToDevice));
    HANDLE_ERROR(hipMemcpy(Wd, W, kernel_size*sizeof(float), hipMemcpyHostToDevice));
    HANDLE_ERROR(hipMemcpy(meand, mean, out_channel*sizeof(float), hipMemcpyHostToDevice));
    HANDLE_ERROR(hipMemcpy(scaled, scale, out_channel*sizeof(float), hipMemcpyHostToDevice));
    HANDLE_ERROR(hipMemcpy(vard, var, out_channel*sizeof(float), hipMemcpyHostToDevice));
    HANDLE_ERROR(hipMemcpy(betad, beta, out_channel*sizeof(float), hipMemcpyHostToDevice));

    dim3 grid(2, 8, 196), block(8, 1, 1);
	HANDLE_ERROR(hipDeviceSynchronize());
    //HANDLE_ERROR(default_function_kernel0<<<grid, block>>>(Ad, Wd, betad, Bd));
    gettimeofday(&start, 0);
    conv_bn_relu<<<grid, block>>>(Ad, Wd, meand, scaled, vard, betad, Bd);
	HANDLE_ERROR(hipDeviceSynchronize());
    gettimeofday(&end, 0);
    std::cout << "time: " << get_durtime(start, end) << "ms" << std::endl;
    HANDLE_ERROR(hipMemcpy(B, Bd, out_size*sizeof(float), hipMemcpyDeviceToHost));
    HANDLE_ERROR(hipFree(Ad));
    HANDLE_ERROR(hipFree(Bd));
    HANDLE_ERROR(hipFree(Wd));
    HANDLE_ERROR(hipFree(meand));
    HANDLE_ERROR(hipFree(scaled));
    HANDLE_ERROR(hipFree(vard));
    HANDLE_ERROR(hipFree(betad));
    return 0;
}

	.text
	.file	"conv_bn_relu_fuse_test.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z19__device_stub__convPvS_S_   # -- Begin function _Z19__device_stub__convPvS_S_
	.type	_Z19__device_stub__convPvS_S_,@function
_Z19__device_stub__convPvS_S_:          # @_Z19__device_stub__convPvS_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z4convPvS_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z19__device_stub__convPvS_S_, .Lfunc_end0-_Z19__device_stub__convPvS_S_
	.cfi_endproc
                                        # -- End function
	.globl	_Z27__device_stub__conv_bn_reluPvS_S_S_S_S_S_ # -- Begin function _Z27__device_stub__conv_bn_reluPvS_S_S_S_S_S_
	.type	_Z27__device_stub__conv_bn_reluPvS_S_S_S_S_S_,@function
_Z27__device_stub__conv_bn_reluPvS_S_S_S_S_S_: # @_Z27__device_stub__conv_bn_reluPvS_S_S_S_S_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z12conv_bn_reluPvS_S_S_S_S_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z27__device_stub__conv_bn_reluPvS_S_S_S_S_S_, .Lfunc_end1-_Z27__device_stub__conv_bn_reluPvS_S_S_S_S_S_
	.cfi_endproc
                                        # -- End function
	.globl	_Z39__device_stub__default_function_kernel0PvS_S_S_ # -- Begin function _Z39__device_stub__default_function_kernel0PvS_S_S_
	.type	_Z39__device_stub__default_function_kernel0PvS_S_S_,@function
_Z39__device_stub__default_function_kernel0PvS_S_S_: # @_Z39__device_stub__default_function_kernel0PvS_S_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	16(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z24default_function_kernel0PvS_S_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z39__device_stub__default_function_kernel0PvS_S_S_, .Lfunc_end2-_Z39__device_stub__default_function_kernel0PvS_S_S_
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0                          # -- Begin function _Z11get_durtime7timevalS_
.LCPI3_0:
	.quad	0x412e848000000000              # double 1.0E+6
.LCPI3_1:
	.quad	0x408f400000000000              # double 1000
	.text
	.globl	_Z11get_durtime7timevalS_
	.type	_Z11get_durtime7timevalS_,@function
_Z11get_durtime7timevalS_:              # @_Z11get_durtime7timevalS_
	.cfi_startproc
# %bb.0:
	subq	%rdi, %rdx
	cvtsi2sd	%rdx, %xmm1
	mulsd	.LCPI3_0(%rip), %xmm1
	cvtsi2sd	%rcx, %xmm0
	addsd	%xmm1, %xmm0
	xorps	%xmm1, %xmm1
	cvtsi2sd	%rsi, %xmm1
	subsd	%xmm1, %xmm0
	divsd	.LCPI3_1(%rip), %xmm0
	retq
.Lfunc_end3:
	.size	_Z11get_durtime7timevalS_, .Lfunc_end3-_Z11get_durtime7timevalS_
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0                          # -- Begin function main
.LCPI4_0:
	.quad	0x412e848000000000              # double 1.0E+6
.LCPI4_1:
	.quad	0x408f400000000000              # double 1000
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$104, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	$25690112, %edi                 # imm = 0x1880000
	callq	malloc
	movq	%rax, %rbx
	movl	$4718592, %edi                  # imm = 0x480000
	callq	malloc
	movq	%rax, %rbp
	movl	$51380224, %edi                 # imm = 0x3100000
	callq	malloc
	movq	%rax, 64(%rsp)                  # 8-byte Spill
	movl	$2048, %edi                     # imm = 0x800
	callq	malloc
	movq	%rax, %r13
	movl	$2048, %edi                     # imm = 0x800
	callq	malloc
	movq	%rax, %r12
	movl	$2048, %edi                     # imm = 0x800
	callq	malloc
	movq	%rax, %r15
	movl	$2048, %edi                     # imm = 0x800
	callq	malloc
	movq	%rax, %r14
	leaq	56(%rsp), %rdi
	movl	$25690112, %esi                 # imm = 0x1880000
	callq	hipMalloc
	movl	%eax, %edi
	movl	$189, %esi
	callq	_ZL11HandleError10hipError_tPKci
	leaq	48(%rsp), %rdi
	movl	$4718592, %esi                  # imm = 0x480000
	callq	hipMalloc
	movl	%eax, %edi
	movl	$190, %esi
	callq	_ZL11HandleError10hipError_tPKci
	leaq	40(%rsp), %rdi
	movl	$51380224, %esi                 # imm = 0x3100000
	callq	hipMalloc
	movl	%eax, %edi
	movl	$191, %esi
	callq	_ZL11HandleError10hipError_tPKci
	leaq	32(%rsp), %rdi
	movl	$2048, %esi                     # imm = 0x800
	callq	hipMalloc
	movl	%eax, %edi
	movl	$192, %esi
	callq	_ZL11HandleError10hipError_tPKci
	leaq	24(%rsp), %rdi
	movl	$2048, %esi                     # imm = 0x800
	callq	hipMalloc
	movl	%eax, %edi
	movl	$193, %esi
	callq	_ZL11HandleError10hipError_tPKci
	leaq	16(%rsp), %rdi
	movl	$2048, %esi                     # imm = 0x800
	callq	hipMalloc
	movl	%eax, %edi
	movl	$194, %esi
	callq	_ZL11HandleError10hipError_tPKci
	leaq	8(%rsp), %rdi
	movl	$2048, %esi                     # imm = 0x800
	callq	hipMalloc
	movl	%eax, %edi
	movl	$195, %esi
	callq	_ZL11HandleError10hipError_tPKci
	xorl	%eax, %eax
.LBB4_1:                                # =>This Inner Loop Header: Depth=1
	xorps	%xmm0, %xmm0
	cvtsi2ss	%eax, %xmm0
	movss	%xmm0, (%rbx,%rax,4)
	incq	%rax
	cmpq	$6422528, %rax                  # imm = 0x620000
	jne	.LBB4_1
# %bb.2:                                # %.preheader55.preheader
	xorl	%eax, %eax
.LBB4_3:                                # %.preheader55
                                        # =>This Inner Loop Header: Depth=1
	xorps	%xmm0, %xmm0
	cvtsi2ss	%eax, %xmm0
	movss	%xmm0, (%rbp,%rax,4)
	incq	%rax
	cmpq	$1179648, %rax                  # imm = 0x120000
	jne	.LBB4_3
# %bb.4:                                # %.preheader.preheader
	xorl	%eax, %eax
.LBB4_5:                                # %.preheader
                                        # =>This Inner Loop Header: Depth=1
	xorps	%xmm0, %xmm0
	cvtsi2ss	%eax, %xmm0
	movss	%xmm0, (%r13,%rax,4)
	movss	%xmm0, (%r12,%rax,4)
	movss	%xmm0, (%r15,%rax,4)
	movss	%xmm0, (%r14,%rax,4)
	incq	%rax
	cmpq	$512, %rax                      # imm = 0x200
	jne	.LBB4_5
# %bb.6:
	movq	56(%rsp), %rdi
	movl	$25690112, %edx                 # imm = 0x1880000
	movq	%rbx, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movl	%eax, %edi
	movl	$206, %esi
	callq	_ZL11HandleError10hipError_tPKci
	movq	48(%rsp), %rdi
	movl	$4718592, %edx                  # imm = 0x480000
	movq	%rbp, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movl	%eax, %edi
	movl	$207, %esi
	callq	_ZL11HandleError10hipError_tPKci
	movq	32(%rsp), %rdi
	movl	$2048, %edx                     # imm = 0x800
	movq	%r13, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movl	%eax, %edi
	movl	$208, %esi
	callq	_ZL11HandleError10hipError_tPKci
	movq	24(%rsp), %rdi
	movl	$2048, %edx                     # imm = 0x800
	movq	%r12, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movl	%eax, %edi
	movl	$209, %esi
	callq	_ZL11HandleError10hipError_tPKci
	movq	16(%rsp), %rdi
	movl	$2048, %edx                     # imm = 0x800
	movq	%r15, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movl	%eax, %edi
	movl	$210, %esi
	callq	_ZL11HandleError10hipError_tPKci
	movq	8(%rsp), %rdi
	movl	$2048, %edx                     # imm = 0x800
	movq	%r14, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movl	%eax, %edi
	movl	$211, %esi
	callq	_ZL11HandleError10hipError_tPKci
	callq	hipDeviceSynchronize
	movl	%eax, %edi
	movl	$214, %esi
	callq	_ZL11HandleError10hipError_tPKci
	leaq	72(%rsp), %rdi
	xorl	%esi, %esi
	callq	gettimeofday
	movabsq	$34359738370, %rdi              # imm = 0x800000002
	movabsq	$4294967304, %rdx               # imm = 0x100000008
	movl	$196, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB4_8
# %bb.7:
	movq	56(%rsp), %rdi
	movq	48(%rsp), %rsi
	movq	32(%rsp), %rdx
	movq	24(%rsp), %rcx
	movq	16(%rsp), %r8
	movq	8(%rsp), %r9
	movq	40(%rsp), %rax
	movq	%rax, (%rsp)
	callq	_Z27__device_stub__conv_bn_reluPvS_S_S_S_S_S_
.LBB4_8:
	callq	hipDeviceSynchronize
	movl	%eax, %edi
	movl	$218, %esi
	callq	_ZL11HandleError10hipError_tPKci
	leaq	88(%rsp), %rbx
	movq	%rbx, %rdi
	xorl	%esi, %esi
	callq	gettimeofday
	movl	$_ZSt4cout, %edi
	movl	$.L.str.1, %esi
	movl	$6, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	(%rbx), %rax
	subq	72(%rsp), %rax
	cvtsi2sd	%rax, %xmm1
	mulsd	.LCPI4_0(%rip), %xmm1
	cvtsi2sdq	8(%rbx), %xmm0
	cvtsi2sdq	80(%rsp), %xmm2
	addsd	%xmm1, %xmm0
	subsd	%xmm2, %xmm0
	divsd	.LCPI4_1(%rip), %xmm0
	movl	$_ZSt4cout, %edi
	callq	_ZNSo9_M_insertIdEERSoT_
	movq	%rax, %rbx
	movl	$.L.str.2, %esi
	movl	$2, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	(%rbx), %rax
	movq	-24(%rax), %rdi
	addq	%rbx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%rbx, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movq	40(%rsp), %rsi
	movl	$51380224, %edx                 # imm = 0x3100000
	movq	64(%rsp), %rdi                  # 8-byte Reload
	movl	$2, %ecx
	callq	hipMemcpy
	movl	%eax, %edi
	movl	$221, %esi
	callq	_ZL11HandleError10hipError_tPKci
	movq	56(%rsp), %rdi
	callq	hipFree
	movl	%eax, %edi
	movl	$222, %esi
	callq	_ZL11HandleError10hipError_tPKci
	movq	40(%rsp), %rdi
	callq	hipFree
	movl	%eax, %edi
	movl	$223, %esi
	callq	_ZL11HandleError10hipError_tPKci
	movq	48(%rsp), %rdi
	callq	hipFree
	movl	%eax, %edi
	movl	$224, %esi
	callq	_ZL11HandleError10hipError_tPKci
	movq	32(%rsp), %rdi
	callq	hipFree
	movl	%eax, %edi
	movl	$225, %esi
	callq	_ZL11HandleError10hipError_tPKci
	movq	24(%rsp), %rdi
	callq	hipFree
	movl	%eax, %edi
	movl	$226, %esi
	callq	_ZL11HandleError10hipError_tPKci
	movq	16(%rsp), %rdi
	callq	hipFree
	movl	%eax, %edi
	movl	$227, %esi
	callq	_ZL11HandleError10hipError_tPKci
	movq	8(%rsp), %rdi
	callq	hipFree
	movl	%eax, %edi
	movl	$228, %esi
	callq	_ZL11HandleError10hipError_tPKci
	xorl	%eax, %eax
	addq	$104, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end4:
	.size	main, .Lfunc_end4-main
	.cfi_endproc
                                        # -- End function
	.type	_ZL11HandleError10hipError_tPKci,@function # -- Begin function _ZL11HandleError10hipError_tPKci
_ZL11HandleError10hipError_tPKci:       # @_ZL11HandleError10hipError_tPKci
	.cfi_startproc
# %bb.0:
	testl	%edi, %edi
	jne	.LBB5_2
# %bb.1:
	retq
.LBB5_2:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset %rbx, -16
	movl	%esi, %ebx
	callq	hipGetErrorString
	movl	$.L.str.3, %edi
	movl	$.L.str, %edx
	movq	%rax, %rsi
	movl	%ebx, %ecx
	xorl	%eax, %eax
	callq	printf
	movl	$1, %edi
	callq	exit
.Lfunc_end5:
	.size	_ZL11HandleError10hipError_tPKci, .Lfunc_end5-_ZL11HandleError10hipError_tPKci
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB6_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB6_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z4convPvS_S_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z12conv_bn_reluPvS_S_S_S_S_S_, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z24default_function_kernel0PvS_S_S_, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end6:
	.size	__hip_module_ctor, .Lfunc_end6-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB7_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB7_2:
	retq
.Lfunc_end7:
	.size	__hip_module_dtor, .Lfunc_end7-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z4convPvS_S_,@object           # @_Z4convPvS_S_
	.section	.rodata,"a",@progbits
	.globl	_Z4convPvS_S_
	.p2align	3, 0x0
_Z4convPvS_S_:
	.quad	_Z19__device_stub__convPvS_S_
	.size	_Z4convPvS_S_, 8

	.type	_Z12conv_bn_reluPvS_S_S_S_S_S_,@object # @_Z12conv_bn_reluPvS_S_S_S_S_S_
	.globl	_Z12conv_bn_reluPvS_S_S_S_S_S_
	.p2align	3, 0x0
_Z12conv_bn_reluPvS_S_S_S_S_S_:
	.quad	_Z27__device_stub__conv_bn_reluPvS_S_S_S_S_S_
	.size	_Z12conv_bn_reluPvS_S_S_S_S_S_, 8

	.type	_Z24default_function_kernel0PvS_S_S_,@object # @_Z24default_function_kernel0PvS_S_S_
	.globl	_Z24default_function_kernel0PvS_S_S_
	.p2align	3, 0x0
_Z24default_function_kernel0PvS_S_S_:
	.quad	_Z39__device_stub__default_function_kernel0PvS_S_S_
	.size	_Z24default_function_kernel0PvS_S_S_, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"/home/ubuntu/Datasets/stackv2/train-structured-repos-hip-sm89/LegendBC/PET/master/benchmark/fusion/conv_bn_relu_fuse_test.hip"
	.size	.L.str, 126

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"time: "
	.size	.L.str.1, 7

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"ms"
	.size	.L.str.2, 3

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"%s in %s at line %d\n"
	.size	.L.str.3, 21

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z4convPvS_S_"
	.size	.L__unnamed_1, 14

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z12conv_bn_reluPvS_S_S_S_S_S_"
	.size	.L__unnamed_2, 31

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z24default_function_kernel0PvS_S_S_"
	.size	.L__unnamed_3, 37

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z19__device_stub__convPvS_S_
	.addrsig_sym _Z27__device_stub__conv_bn_reluPvS_S_S_S_S_S_
	.addrsig_sym _Z39__device_stub__default_function_kernel0PvS_S_S_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z4convPvS_S_
	.addrsig_sym _Z12conv_bn_reluPvS_S_S_S_S_S_
	.addrsig_sym _Z24default_function_kernel0PvS_S_S_
	.addrsig_sym _ZSt4cout
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z4convPvS_S_           ; -- Begin function _Z4convPvS_S_
	.globl	_Z4convPvS_S_
	.p2align	8
	.type	_Z4convPvS_S_,@function
_Z4convPvS_S_:                          ; @_Z4convPvS_S_
; %bb.0:
	s_clause 0x1
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b64 s[0:1], s[0:1], 0x10
	v_dual_mov_b32 v1, 16 :: v_dual_mov_b32 v2, 0
	s_mov_b32 s2, 0
.LBB0_1:                                ; %.preheader102
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_2 Depth 2
	s_mov_b32 s3, 0
.LBB0_2:                                ;   Parent Loop BB0_1 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_add_nc_u32_e32 v3, s3, v1
	s_add_i32 s3, s3, 4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s3, 32
	scratch_store_b32 v3, v2, off
	s_cbranch_scc0 .LBB0_2
; %bb.3:                                ;   in Loop: Header=BB0_1 Depth=1
	v_add_nc_u32_e32 v1, 32, v1
	s_add_i32 s2, s2, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s2, 8
	s_cbranch_scc0 .LBB0_1
; %bb.4:                                ; %.preheader101
	s_mul_hi_i32 s2, s15, 0x92492493
	v_mul_u32_u24_e32 v1, 0x48, v0
	s_add_i32 s2, s2, s15
	v_lshlrev_b32_e32 v31, 5, v0
	s_lshr_b32 s3, s2, 31
	s_ashr_i32 s2, s2, 3
	v_dual_mov_b32 v17, 0 :: v_dual_lshlrev_b32 v30, 2, v1
	s_add_i32 s2, s2, s3
	v_add_nc_u32_e32 v36, 0x800, v31
	s_add_i32 s8, s2, -1
	s_mul_i32 s2, s2, 14
	s_waitcnt lgkmcnt(0)
	s_add_u32 s9, s4, 0xffe20000
	s_addc_u32 s5, s5, -1
	s_not_b32 s10, s2
	s_lshl_b32 s4, s13, 6
	s_lshl_b32 s2, s14, 6
	v_mad_u32_u24 v32, 0x88, v0, s4
	v_mad_u32_u24 v33, 0x208, v0, s2
	v_add_nc_u32_e32 v34, 0x800, v30
	v_add_nc_u32_e32 v35, 0x810, v30
	s_add_i32 s10, s10, s15
	s_mov_b32 s11, 0
                                        ; implicit-def: $vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8
                                        ; implicit-def: $vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16
.LBB0_5:                                ; %.preheader100
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_6 Depth 2
                                        ;       Child Loop BB0_7 Depth 3
                                        ;         Child Loop BB0_13 Depth 4
                                        ;           Child Loop BB0_14 Depth 5
                                        ;           Child Loop BB0_16 Depth 5
                                        ;           Child Loop BB0_18 Depth 5
                                        ;             Child Loop BB0_19 Depth 6
	s_delay_alu instid0(SALU_CYCLE_1)
	v_lshl_add_u32 v25, s11, 10, v32
	v_lshl_add_u32 v26, s11, 12, v33
	s_mov_b32 s12, 0
.LBB0_6:                                ; %.preheader99
                                        ;   Parent Loop BB0_5 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB0_7 Depth 3
                                        ;         Child Loop BB0_13 Depth 4
                                        ;           Child Loop BB0_14 Depth 5
                                        ;           Child Loop BB0_16 Depth 5
                                        ;           Child Loop BB0_18 Depth 5
                                        ;             Child Loop BB0_19 Depth 6
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[27:28], null, 0x70000, s12, v[25:26]
	s_add_i32 s2, s8, s12
	s_mov_b32 s16, 0
	s_cmp_gt_u32 s2, 13
	s_cselect_b32 s13, -1, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_mad_u64_u32 v[28:29], null, 0x60000, s12, v[26:27]
.LBB0_7:                                ;   Parent Loop BB0_5 Depth=1
                                        ;     Parent Loop BB0_6 Depth=2
                                        ; =>    This Loop Header: Depth=3
                                        ;         Child Loop BB0_13 Depth 4
                                        ;           Child Loop BB0_14 Depth 5
                                        ;           Child Loop BB0_16 Depth 5
                                        ;           Child Loop BB0_18 Depth 5
                                        ;             Child Loop BB0_19 Depth 6
	s_add_i32 s2, s10, s16
	s_waitcnt_vscnt null, 0x0
	s_cmp_gt_u32 s2, 13
	s_barrier
	s_cselect_b32 s2, -1, 0
	buffer_gl0_inv
	s_or_b32 s2, s13, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s2
	s_cbranch_vccnz .LBB0_9
; %bb.8:                                ;   in Loop: Header=BB0_7 Depth=3
	s_add_i32 s2, s16, s15
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshl_add_u32 v18, s2, 15, v27
	s_mov_b32 s2, 0
	v_ashrrev_i32_e32 v19, 31, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[18:19], 2, v[18:19]
	v_add_co_u32 v18, vcc_lo, s9, v18
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v19, vcc_lo, s5, v19, vcc_lo
	s_clause 0x1
	global_load_b128 v[37:40], v[18:19], off
	global_load_b128 v[21:24], v[18:19], off offset:16
	s_waitcnt vmcnt(1)
	ds_store_b128 v30, v[37:40]
	s_branch .LBB0_10
.LBB0_9:                                ;   in Loop: Header=BB0_7 Depth=3
	s_mov_b32 s2, -1
                                        ; implicit-def: $vgpr24
.LBB0_10:                               ; %Flow
                                        ;   in Loop: Header=BB0_7 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s2
	s_cbranch_vccnz .LBB0_12
; %bb.11:                               ; %.preheader98.critedge
                                        ;   in Loop: Header=BB0_7 Depth=3
	s_waitcnt vmcnt(0)
	v_dual_mov_b32 v21, 0 :: v_dual_mov_b32 v18, v17
	v_mov_b32_e32 v19, v17
	v_mov_b32_e32 v20, v17
	s_delay_alu instid0(VALU_DEP_3)
	v_mov_b32_e32 v22, v21
	v_mov_b32_e32 v23, v21
	v_mov_b32_e32 v24, v21
	ds_store_b128 v30, v[17:20]
.LBB0_12:                               ; %.preheader98
                                        ;   in Loop: Header=BB0_7 Depth=3
	v_lshl_add_u32 v18, s16, 17, v28
	s_mov_b32 s17, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v19, 31, v18
	v_lshlrev_b64 v[18:19], 2, v[18:19]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v18, vcc_lo, s6, v18
	v_add_co_ci_u32_e32 v19, vcc_lo, s7, v19, vcc_lo
	s_clause 0x1
	global_load_b128 v[37:40], v[18:19], off
	global_load_b128 v[41:44], v[18:19], off offset:16
	v_dual_mov_b32 v18, v36 :: v_dual_mov_b32 v19, v31
	s_waitcnt vmcnt(2)
	ds_store_b128 v30, v[21:24] offset:16
	s_waitcnt vmcnt(1)
	ds_store_b128 v34, v[37:40]
	s_waitcnt vmcnt(0)
	ds_store_b128 v35, v[41:44]
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
.LBB0_13:                               ; %.preheader97
                                        ;   Parent Loop BB0_5 Depth=1
                                        ;     Parent Loop BB0_6 Depth=2
                                        ;       Parent Loop BB0_7 Depth=3
                                        ; =>      This Loop Header: Depth=4
                                        ;           Child Loop BB0_14 Depth 5
                                        ;           Child Loop BB0_16 Depth 5
                                        ;           Child Loop BB0_18 Depth 5
                                        ;             Child Loop BB0_19 Depth 6
	v_mov_b32_e32 v20, v19
	s_mov_b64 s[2:3], 0
.LBB0_14:                               ;   Parent Loop BB0_5 Depth=1
                                        ;     Parent Loop BB0_6 Depth=2
                                        ;       Parent Loop BB0_7 Depth=3
                                        ;         Parent Loop BB0_13 Depth=4
                                        ; =>        This Inner Loop Header: Depth=5
	ds_load_b32 v21, v20
	v_add_nc_u32_e32 v20, 4, v20
	s_mov_b32 m0, s2
	s_add_u32 s2, s2, 1
	s_addc_u32 s3, s3, 0
	s_cmp_lg_u32 s2, 8
	s_waitcnt lgkmcnt(0)
	v_movreld_b32_e32 v1, v21
	s_cbranch_scc1 .LBB0_14
; %bb.15:                               ; %.preheader96.preheader
                                        ;   in Loop: Header=BB0_13 Depth=4
	v_mov_b32_e32 v20, v18
	s_mov_b64 s[2:3], 0
.LBB0_16:                               ; %.preheader96
                                        ;   Parent Loop BB0_5 Depth=1
                                        ;     Parent Loop BB0_6 Depth=2
                                        ;       Parent Loop BB0_7 Depth=3
                                        ;         Parent Loop BB0_13 Depth=4
                                        ; =>        This Inner Loop Header: Depth=5
	ds_load_b32 v21, v20
	v_add_nc_u32_e32 v20, 4, v20
	s_mov_b32 m0, s2
	s_add_u32 s2, s2, 1
	s_addc_u32 s3, s3, 0
	s_cmp_lg_u32 s2, 8
	s_waitcnt lgkmcnt(0)
	v_movreld_b32_e32 v9, v21
	s_cbranch_scc1 .LBB0_16
; %bb.17:                               ; %.preheader94.preheader
                                        ;   in Loop: Header=BB0_13 Depth=4
	v_mov_b32_e32 v20, 16
	s_mov_b32 s18, 0
.LBB0_18:                               ; %.preheader94
                                        ;   Parent Loop BB0_5 Depth=1
                                        ;     Parent Loop BB0_6 Depth=2
                                        ;       Parent Loop BB0_7 Depth=3
                                        ;         Parent Loop BB0_13 Depth=4
                                        ; =>        This Loop Header: Depth=5
                                        ;             Child Loop BB0_19 Depth 6
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_mov_b32 m0, s18
	v_mov_b32_e32 v22, v20
	v_movrels_b32_e32 v21, v9
	s_mov_b64 s[2:3], 0
.LBB0_19:                               ;   Parent Loop BB0_5 Depth=1
                                        ;     Parent Loop BB0_6 Depth=2
                                        ;       Parent Loop BB0_7 Depth=3
                                        ;         Parent Loop BB0_13 Depth=4
                                        ;           Parent Loop BB0_18 Depth=5
                                        ; =>          This Inner Loop Header: Depth=6
	scratch_load_b32 v23, v22, off
	s_mov_b32 m0, s2
	s_add_u32 s2, s2, 1
	v_movrels_b32_e32 v24, v1
	s_addc_u32 s3, s3, 0
	s_cmp_eq_u32 s2, 8
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v23, v21, v24
	scratch_store_b32 v22, v23, off
	v_add_nc_u32_e32 v22, 4, v22
	s_cbranch_scc0 .LBB0_19
; %bb.20:                               ;   in Loop: Header=BB0_18 Depth=5
	v_add_nc_u32_e32 v20, 32, v20
	s_add_i32 s18, s18, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s18, 8
	s_cbranch_scc0 .LBB0_18
; %bb.21:                               ;   in Loop: Header=BB0_13 Depth=4
	v_add_nc_u32_e32 v19, 0x100, v19
	v_add_nc_u32_e32 v18, 0x100, v18
	s_add_i32 s17, s17, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s17, 8
	s_cbranch_scc0 .LBB0_13
; %bb.22:                               ;   in Loop: Header=BB0_7 Depth=3
	s_add_i32 s16, s16, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s16, 3
	s_cbranch_scc0 .LBB0_7
; %bb.23:                               ;   in Loop: Header=BB0_6 Depth=2
	s_add_i32 s12, s12, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s12, 3
	s_cbranch_scc0 .LBB0_6
; %bb.24:                               ;   in Loop: Header=BB0_5 Depth=1
	s_add_i32 s11, s11, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s11, 32
	s_cbranch_scc0 .LBB0_5
; %bb.25:                               ; %.preheader93
	v_mul_u32_u24_e32 v0, 0x408, v0
	s_lshl_b32 s2, s14, 13
	s_lshl_b32 s3, s15, 16
	s_add_i32 s4, s4, s2
	v_mov_b32_e32 v1, 16
	v_add3_u32 v0, s4, s3, v0
	s_mov_b32 s2, 0
.LBB0_26:                               ; %.preheader
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_27 Depth 2
	s_delay_alu instid0(VALU_DEP_2)
	v_mov_b32_e32 v2, v1
	s_mov_b32 s3, 0
.LBB0_27:                               ;   Parent Loop BB0_26 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	scratch_load_b32 v5, v2, off
	v_add_nc_u32_e32 v3, s3, v0
	v_add_nc_u32_e32 v2, 4, v2
	s_add_i32 s3, s3, 1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	s_cmp_eq_u32 s3, 8
	v_ashrrev_i32_e32 v4, 31, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	v_add_co_u32 v3, vcc_lo, s0, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b32 v[3:4], v5, off
	s_cbranch_scc0 .LBB0_27
; %bb.28:                               ;   in Loop: Header=BB0_26 Depth=1
	v_add_nc_u32_e32 v1, 32, v1
	v_add_nc_u32_e32 v0, 0x80, v0
	s_add_i32 s2, s2, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s2, 8
	s_cbranch_scc0 .LBB0_26
; %bb.29:
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z4convPvS_S_
		.amdhsa_group_segment_fixed_size 4096
		.amdhsa_private_segment_fixed_size 272
		.amdhsa_kernarg_size 24
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 1
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 45
		.amdhsa_next_free_sgpr 19
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z4convPvS_S_, .Lfunc_end0-_Z4convPvS_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1048
; NumSgprs: 21
; NumVgprs: 45
; ScratchSize: 272
; MemoryBound: 1
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 4096 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 5
; NumSGPRsForWavesPerEU: 21
; NumVGPRsForWavesPerEU: 45
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 1
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z12conv_bn_reluPvS_S_S_S_S_S_ ; -- Begin function _Z12conv_bn_reluPvS_S_S_S_S_S_
	.globl	_Z12conv_bn_reluPvS_S_S_S_S_S_
	.p2align	8
	.type	_Z12conv_bn_reluPvS_S_S_S_S_S_,@function
_Z12conv_bn_reluPvS_S_S_S_S_S_:         ; @_Z12conv_bn_reluPvS_S_S_S_S_S_
; %bb.0:
	v_lshlrev_b32_e32 v1, 3, v0
	s_clause 0x2
	s_load_b128 s[16:19], s[0:1], 0x20
	s_load_b64 s[2:3], s[0:1], 0x30
	s_load_b256 s[4:11], s[0:1], 0x0
	s_mov_b64 s[0:1], 0
	v_lshl_add_u32 v33, s14, 6, v1
                                        ; implicit-def: $vgpr9
                                        ; implicit-def: $vgpr17
                                        ; implicit-def: $vgpr25
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v34, 31, v33
	v_lshlrev_b64 v[1:2], 2, v[33:34]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v34, vcc_lo, s18, v1
	v_add_co_ci_u32_e32 v35, vcc_lo, s19, v2, vcc_lo
	v_add_co_u32 v36, vcc_lo, s16, v1
	v_add_co_ci_u32_e32 v37, vcc_lo, s17, v2, vcc_lo
	v_add_co_u32 v38, vcc_lo, s10, v1
	v_add_co_ci_u32_e32 v39, vcc_lo, s11, v2, vcc_lo
	v_add_co_u32 v40, vcc_lo, s8, v1
	v_add_co_ci_u32_e32 v41, vcc_lo, s9, v2, vcc_lo
                                        ; implicit-def: $vgpr1
.LBB1_1:                                ; =>This Inner Loop Header: Depth=1
	global_load_b32 v42, v[40:41], off
	s_mov_b32 m0, s0
	v_add_co_u32 v40, vcc_lo, v40, 4
	v_add_co_ci_u32_e32 v41, vcc_lo, 0, v41, vcc_lo
	s_add_u32 s0, s0, 1
	s_addc_u32 s1, s1, 0
	s_cmp_lg_u32 s0, 8
	s_waitcnt vmcnt(0)
	v_movreld_b32_e32 v1, v42
	global_load_b32 v42, v[38:39], off
	v_add_co_u32 v38, vcc_lo, v38, 4
	v_add_co_ci_u32_e32 v39, vcc_lo, 0, v39, vcc_lo
	s_waitcnt vmcnt(0)
	v_movreld_b32_e32 v9, v42
	global_load_b32 v42, v[36:37], off
	v_add_co_u32 v36, vcc_lo, v36, 4
	v_add_co_ci_u32_e32 v37, vcc_lo, 0, v37, vcc_lo
	s_waitcnt vmcnt(0)
	v_movreld_b32_e32 v17, v42
	global_load_b32 v42, v[34:35], off
	v_add_co_u32 v34, vcc_lo, v34, 4
	v_add_co_ci_u32_e32 v35, vcc_lo, 0, v35, vcc_lo
	s_waitcnt vmcnt(0)
	v_movreld_b32_e32 v25, v42
	s_cbranch_scc1 .LBB1_1
; %bb.2:                                ; %.preheader130.preheader
	v_dual_mov_b32 v34, 16 :: v_dual_mov_b32 v35, 0
	s_mov_b32 s0, 0
.LBB1_3:                                ; %.preheader130
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB1_4 Depth 2
	s_mov_b32 s1, 0
.LBB1_4:                                ;   Parent Loop BB1_3 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_add_nc_u32_e32 v36, s1, v34
	s_add_i32 s1, s1, 4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s1, 32
	scratch_store_b32 v36, v35, off
	s_cbranch_scc0 .LBB1_4
; %bb.5:                                ;   in Loop: Header=BB1_3 Depth=1
	v_add_nc_u32_e32 v34, 32, v34
	s_add_i32 s0, s0, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s0, 8
	s_cbranch_scc0 .LBB1_3
; %bb.6:                                ; %.preheader129
	s_mul_hi_i32 s0, s15, 0x92492493
	v_mul_u32_u24_e32 v34, 0x48, v0
	s_add_i32 s0, s0, s15
	v_lshlrev_b32_e32 v63, 5, v0
	s_lshr_b32 s1, s0, 31
	s_ashr_i32 s0, s0, 3
	v_dual_mov_b32 v49, 0 :: v_dual_lshlrev_b32 v62, 2, v34
	s_add_i32 s0, s0, s1
	v_lshl_add_u32 v65, v0, 9, v33
	s_add_i32 s8, s0, -1
	s_add_u32 s4, s4, 0xffe20000
	s_addc_u32 s5, s5, -1
	s_lshl_b32 s9, s13, 6
	s_mul_i32 s0, s0, 14
	v_mad_u32_u24 v64, 0x88, v0, s9
	v_add_nc_u32_e32 v66, 0x800, v62
	v_add_nc_u32_e32 v67, 0x810, v62
	v_add_nc_u32_e32 v68, 0x800, v63
	s_not_b32 s10, s0
	s_mov_b32 s11, 0
	s_add_i32 s10, s10, s15
                                        ; implicit-def: $vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40
                                        ; implicit-def: $vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48
.LBB1_7:                                ; %.preheader128
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB1_8 Depth 2
                                        ;       Child Loop BB1_9 Depth 3
                                        ;         Child Loop BB1_15 Depth 4
                                        ;           Child Loop BB1_16 Depth 5
                                        ;           Child Loop BB1_18 Depth 5
                                        ;           Child Loop BB1_20 Depth 5
                                        ;             Child Loop BB1_21 Depth 6
	v_lshl_add_u32 v57, s11, 10, v64
	v_lshl_add_u32 v58, s11, 12, v65
	s_mov_b32 s12, 0
.LBB1_8:                                ; %.preheader127
                                        ;   Parent Loop BB1_7 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB1_9 Depth 3
                                        ;         Child Loop BB1_15 Depth 4
                                        ;           Child Loop BB1_16 Depth 5
                                        ;           Child Loop BB1_18 Depth 5
                                        ;           Child Loop BB1_20 Depth 5
                                        ;             Child Loop BB1_21 Depth 6
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[59:60], null, 0x70000, s12, v[57:58]
	s_add_i32 s0, s8, s12
	s_mov_b32 s16, 0
	s_cmp_gt_u32 s0, 13
	s_cselect_b32 s13, -1, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_mad_u64_u32 v[60:61], null, 0x60000, s12, v[58:59]
.LBB1_9:                                ;   Parent Loop BB1_7 Depth=1
                                        ;     Parent Loop BB1_8 Depth=2
                                        ; =>    This Loop Header: Depth=3
                                        ;         Child Loop BB1_15 Depth 4
                                        ;           Child Loop BB1_16 Depth 5
                                        ;           Child Loop BB1_18 Depth 5
                                        ;           Child Loop BB1_20 Depth 5
                                        ;             Child Loop BB1_21 Depth 6
	s_add_i32 s0, s10, s16
	s_waitcnt_vscnt null, 0x0
	s_cmp_gt_u32 s0, 13
	s_barrier
	s_cselect_b32 s0, -1, 0
	buffer_gl0_inv
	s_or_b32 s0, s13, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccnz .LBB1_11
; %bb.10:                               ;   in Loop: Header=BB1_9 Depth=3
	s_add_i32 s0, s16, s15
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshl_add_u32 v50, s0, 15, v59
	s_mov_b32 s0, 0
	v_ashrrev_i32_e32 v51, 31, v50
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[50:51], 2, v[50:51]
	v_add_co_u32 v50, vcc_lo, s4, v50
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v51, vcc_lo, s5, v51, vcc_lo
	s_clause 0x1
	global_load_b128 v[69:72], v[50:51], off
	global_load_b128 v[53:56], v[50:51], off offset:16
	s_waitcnt vmcnt(1)
	ds_store_b128 v62, v[69:72]
	s_branch .LBB1_12
.LBB1_11:                               ;   in Loop: Header=BB1_9 Depth=3
	s_mov_b32 s0, -1
                                        ; implicit-def: $vgpr56
.LBB1_12:                               ; %Flow
                                        ;   in Loop: Header=BB1_9 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccnz .LBB1_14
; %bb.13:                               ; %.preheader126.critedge
                                        ;   in Loop: Header=BB1_9 Depth=3
	s_waitcnt vmcnt(0)
	v_dual_mov_b32 v53, 0 :: v_dual_mov_b32 v50, v49
	v_mov_b32_e32 v51, v49
	v_mov_b32_e32 v52, v49
	s_delay_alu instid0(VALU_DEP_3)
	v_mov_b32_e32 v54, v53
	v_mov_b32_e32 v55, v53
	v_mov_b32_e32 v56, v53
	ds_store_b128 v62, v[49:52]
.LBB1_14:                               ; %.preheader126
                                        ;   in Loop: Header=BB1_9 Depth=3
	v_lshl_add_u32 v50, s16, 17, v60
	s_mov_b32 s17, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v51, 31, v50
	v_lshlrev_b64 v[50:51], 2, v[50:51]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v50, vcc_lo, s6, v50
	v_add_co_ci_u32_e32 v51, vcc_lo, s7, v51, vcc_lo
	s_clause 0x1
	global_load_b128 v[69:72], v[50:51], off
	global_load_b128 v[73:76], v[50:51], off offset:16
	v_dual_mov_b32 v50, v68 :: v_dual_mov_b32 v51, v63
	s_waitcnt vmcnt(2)
	ds_store_b128 v62, v[53:56] offset:16
	s_waitcnt vmcnt(1)
	ds_store_b128 v66, v[69:72]
	s_waitcnt vmcnt(0)
	ds_store_b128 v67, v[73:76]
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
.LBB1_15:                               ; %.preheader125
                                        ;   Parent Loop BB1_7 Depth=1
                                        ;     Parent Loop BB1_8 Depth=2
                                        ;       Parent Loop BB1_9 Depth=3
                                        ; =>      This Loop Header: Depth=4
                                        ;           Child Loop BB1_16 Depth 5
                                        ;           Child Loop BB1_18 Depth 5
                                        ;           Child Loop BB1_20 Depth 5
                                        ;             Child Loop BB1_21 Depth 6
	v_mov_b32_e32 v52, v51
	s_mov_b64 s[0:1], 0
.LBB1_16:                               ;   Parent Loop BB1_7 Depth=1
                                        ;     Parent Loop BB1_8 Depth=2
                                        ;       Parent Loop BB1_9 Depth=3
                                        ;         Parent Loop BB1_15 Depth=4
                                        ; =>        This Inner Loop Header: Depth=5
	ds_load_b32 v53, v52
	v_add_nc_u32_e32 v52, 4, v52
	s_mov_b32 m0, s0
	s_add_u32 s0, s0, 1
	s_addc_u32 s1, s1, 0
	s_cmp_lg_u32 s0, 8
	s_waitcnt lgkmcnt(0)
	v_movreld_b32_e32 v33, v53
	s_cbranch_scc1 .LBB1_16
; %bb.17:                               ; %.preheader124.preheader
                                        ;   in Loop: Header=BB1_15 Depth=4
	v_mov_b32_e32 v52, v50
	s_mov_b64 s[0:1], 0
.LBB1_18:                               ; %.preheader124
                                        ;   Parent Loop BB1_7 Depth=1
                                        ;     Parent Loop BB1_8 Depth=2
                                        ;       Parent Loop BB1_9 Depth=3
                                        ;         Parent Loop BB1_15 Depth=4
                                        ; =>        This Inner Loop Header: Depth=5
	ds_load_b32 v53, v52
	v_add_nc_u32_e32 v52, 4, v52
	s_mov_b32 m0, s0
	s_add_u32 s0, s0, 1
	s_addc_u32 s1, s1, 0
	s_cmp_lg_u32 s0, 8
	s_waitcnt lgkmcnt(0)
	v_movreld_b32_e32 v41, v53
	s_cbranch_scc1 .LBB1_18
; %bb.19:                               ; %.preheader122.preheader
                                        ;   in Loop: Header=BB1_15 Depth=4
	v_mov_b32_e32 v52, 16
	s_mov_b32 s18, 0
.LBB1_20:                               ; %.preheader122
                                        ;   Parent Loop BB1_7 Depth=1
                                        ;     Parent Loop BB1_8 Depth=2
                                        ;       Parent Loop BB1_9 Depth=3
                                        ;         Parent Loop BB1_15 Depth=4
                                        ; =>        This Loop Header: Depth=5
                                        ;             Child Loop BB1_21 Depth 6
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_mov_b32 m0, s18
	v_mov_b32_e32 v54, v52
	v_movrels_b32_e32 v53, v41
	s_mov_b64 s[0:1], 0
.LBB1_21:                               ;   Parent Loop BB1_7 Depth=1
                                        ;     Parent Loop BB1_8 Depth=2
                                        ;       Parent Loop BB1_9 Depth=3
                                        ;         Parent Loop BB1_15 Depth=4
                                        ;           Parent Loop BB1_20 Depth=5
                                        ; =>          This Inner Loop Header: Depth=6
	scratch_load_b32 v55, v54, off
	s_mov_b32 m0, s0
	s_add_u32 s0, s0, 1
	v_movrels_b32_e32 v56, v33
	s_addc_u32 s1, s1, 0
	s_cmp_eq_u32 s0, 8
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v55, v53, v56
	scratch_store_b32 v54, v55, off
	v_add_nc_u32_e32 v54, 4, v54
	s_cbranch_scc0 .LBB1_21
; %bb.22:                               ;   in Loop: Header=BB1_20 Depth=5
	v_add_nc_u32_e32 v52, 32, v52
	s_add_i32 s18, s18, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s18, 8
	s_cbranch_scc0 .LBB1_20
; %bb.23:                               ;   in Loop: Header=BB1_15 Depth=4
	v_add_nc_u32_e32 v51, 0x100, v51
	v_add_nc_u32_e32 v50, 0x100, v50
	s_add_i32 s17, s17, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s17, 8
	s_cbranch_scc0 .LBB1_15
; %bb.24:                               ;   in Loop: Header=BB1_9 Depth=3
	s_add_i32 s16, s16, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s16, 3
	s_cbranch_scc0 .LBB1_9
; %bb.25:                               ;   in Loop: Header=BB1_8 Depth=2
	s_add_i32 s12, s12, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s12, 3
	s_cbranch_scc0 .LBB1_8
; %bb.26:                               ;   in Loop: Header=BB1_7 Depth=1
	s_add_i32 s11, s11, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s11, 32
	s_cbranch_scc0 .LBB1_7
; %bb.27:                               ; %.preheader121
	v_mul_u32_u24_e32 v0, 0x408, v0
	s_lshl_b32 s0, s14, 13
	s_lshl_b32 s1, s15, 16
	s_add_i32 s9, s9, s0
	v_mov_b32_e32 v33, 16
	v_add3_u32 v0, s9, s1, v0
	s_mov_b32 s1, 0
.LBB1_28:                               ; %.preheader
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB1_29 Depth 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_mov_b32 m0, s1
	v_movrels_b32_e32 v34, v17
	v_add_f32_e32 v34, 0x3727c5ac, v34
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v35, 0x4f800000, v34
	v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v34
	v_cndmask_b32_e32 v37, v34, v35, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_sqrt_f32_e32 v34, v37
	s_waitcnt_depctr 0xfff
	v_add_nc_u32_e32 v36, 1, v34
	v_add_nc_u32_e32 v35, -1, v34
	v_fma_f32 v39, -v36, v34, v37
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v38, -v35, v34, v37
	v_cmp_ge_f32_e64 s0, 0, v38
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v34, v34, v35, s0
	v_cmp_lt_f32_e64 s0, 0, v39
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v34, v34, v36, s0
	v_movrels_b32_e32 v36, v25
	s_mov_b32 s0, 0
	v_mul_f32_e32 v35, 0x37800000, v34
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_cndmask_b32_e32 v38, v34, v35, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v37, 0x260
	v_movrels_b32_e32 v34, v9
	v_movrels_b32_e32 v35, v1
	v_dual_cndmask_b32 v37, v38, v37 :: v_dual_mov_b32 v38, v33
.LBB1_29:                               ;   Parent Loop BB1_28 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	scratch_load_b32 v39, v38, off
	s_waitcnt vmcnt(0)
	v_dual_sub_f32 v39, v39, v35 :: v_dual_add_nc_u32 v38, 4, v38
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v39, v34, v39
	v_div_scale_f32 v40, null, v37, v37, v39
	v_div_scale_f32 v43, vcc_lo, v39, v37, v39
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v41, v40
	s_waitcnt_depctr 0xfff
	v_fma_f32 v42, -v40, v41, 1.0
	v_fmac_f32_e32 v41, v42, v41
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v42, v43, v41
	v_fma_f32 v44, -v40, v42, v43
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v42, v44, v41
	v_fma_f32 v40, -v40, v42, v43
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v40, v40, v41, v42
	v_div_fixup_f32 v39, v40, v37, v39
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v39, v36, v39
	v_cvt_f64_f32_e32 v[39:40], v39
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_max_f64 v[39:40], v[39:40], 0
	v_cvt_f32_f64_e32 v41, v[39:40]
	v_add_nc_u32_e32 v39, s0, v0
	s_add_i32 s0, s0, 1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_cmp_eq_u32 s0, 8
	v_ashrrev_i32_e32 v40, 31, v39
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[39:40], 2, v[39:40]
	v_add_co_u32 v39, vcc_lo, s2, v39
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v40, vcc_lo, s3, v40, vcc_lo
	global_store_b32 v[39:40], v41, off
	s_cbranch_scc0 .LBB1_29
; %bb.30:                               ;   in Loop: Header=BB1_28 Depth=1
	v_add_nc_u32_e32 v33, 32, v33
	v_add_nc_u32_e32 v0, 0x80, v0
	s_add_i32 s1, s1, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s1, 8
	s_cbranch_scc0 .LBB1_28
; %bb.31:
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z12conv_bn_reluPvS_S_S_S_S_S_
		.amdhsa_group_segment_fixed_size 4096
		.amdhsa_private_segment_fixed_size 272
		.amdhsa_kernarg_size 56
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 1
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 77
		.amdhsa_next_free_sgpr 20
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z12conv_bn_reluPvS_S_S_S_S_S_, .Lfunc_end1-_Z12conv_bn_reluPvS_S_S_S_S_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1556
; NumSgprs: 22
; NumVgprs: 77
; ScratchSize: 272
; MemoryBound: 1
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 4096 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 9
; NumSGPRsForWavesPerEU: 22
; NumVGPRsForWavesPerEU: 77
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 1
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z24default_function_kernel0PvS_S_S_ ; -- Begin function _Z24default_function_kernel0PvS_S_S_
	.globl	_Z24default_function_kernel0PvS_S_S_
	.p2align	8
	.type	_Z24default_function_kernel0PvS_S_S_,@function
_Z24default_function_kernel0PvS_S_S_:   ; @_Z24default_function_kernel0PvS_S_S_
; %bb.0:
	s_load_b256 s[0:7], s[0:1], 0x0
	s_lshl_b32 s8, s14, 6
	v_lshlrev_b32_e32 v38, 5, v0
	s_ashr_i32 s9, s8, 31
                                        ; implicit-def: $vgpr1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	s_lshl_b64 s[10:11], s[8:9], 2
	s_waitcnt lgkmcnt(0)
	s_add_u32 s4, s4, s10
	s_addc_u32 s5, s5, s11
	v_add_co_u32 v9, s4, s4, v38
	v_add_co_ci_u32_e64 v10, null, s5, 0, s4
	s_mov_b64 s[4:5], 0
.LBB2_1:                                ; =>This Inner Loop Header: Depth=1
	global_load_b32 v11, v[9:10], off
	v_add_co_u32 v9, vcc_lo, v9, 4
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v10, vcc_lo
	s_mov_b32 m0, s4
	s_add_u32 s4, s4, 1
	s_addc_u32 s5, s5, 0
	s_cmp_lg_u32 s4, 8
	s_waitcnt vmcnt(0)
	v_movreld_b32_e32 v1, v11
	s_cbranch_scc1 .LBB2_1
; %bb.2:                                ; %.preheader111.preheader
	v_dual_mov_b32 v9, 16 :: v_dual_mov_b32 v10, 0
	s_mov_b32 s4, 0
.LBB2_3:                                ; %.preheader111
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB2_4 Depth 2
	s_mov_b32 s5, 0
.LBB2_4:                                ;   Parent Loop BB2_3 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_add_nc_u32_e32 v11, s5, v9
	s_add_i32 s5, s5, 4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s5, 32
	scratch_store_b32 v11, v10, off
	s_cbranch_scc0 .LBB2_4
; %bb.5:                                ;   in Loop: Header=BB2_3 Depth=1
	v_add_nc_u32_e32 v9, 32, v9
	s_add_i32 s4, s4, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s4, 8
	s_cbranch_scc0 .LBB2_3
; %bb.6:                                ; %.preheader110
	s_mul_hi_i32 s4, s15, 0x92492493
	v_mul_u32_u24_e32 v10, 0x48, v0
	s_add_i32 s4, s4, s15
	v_lshlrev_b32_e32 v9, 3, v0
	s_lshr_b32 s5, s4, 31
	s_ashr_i32 s4, s4, 3
	v_lshlrev_b32_e32 v11, 9, v0
	s_add_i32 s5, s4, s5
	v_lshlrev_b32_e32 v39, 2, v10
	s_add_i32 s4, s5, -1
	s_mul_i32 s11, s5, 14
	s_add_u32 s5, s0, 0xffe20000
	s_addc_u32 s9, s1, -1
	s_lshl_b32 s10, s13, 6
	v_add3_u32 v41, s8, v9, v11
	v_mad_u32_u24 v40, 0x88, v0, s10
	v_dual_mov_b32 v25, 0 :: v_dual_add_nc_u32 v42, 0x800, v39
	v_add_nc_u32_e32 v43, 0x810, v39
	v_add_nc_u32_e32 v44, 0x800, v38
	s_not_b32 s0, s11
	s_mov_b32 s11, 0
	s_add_i32 s8, s0, s15
                                        ; implicit-def: $vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16
                                        ; implicit-def: $vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24
.LBB2_7:                                ; %.preheader109
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB2_8 Depth 2
                                        ;       Child Loop BB2_9 Depth 3
                                        ;         Child Loop BB2_15 Depth 4
                                        ;           Child Loop BB2_16 Depth 5
                                        ;           Child Loop BB2_18 Depth 5
                                        ;           Child Loop BB2_20 Depth 5
                                        ;             Child Loop BB2_21 Depth 6
	v_lshl_add_u32 v33, s11, 10, v40
	v_lshl_add_u32 v34, s11, 12, v41
	s_mov_b32 s12, 0
.LBB2_8:                                ; %.preheader108
                                        ;   Parent Loop BB2_7 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB2_9 Depth 3
                                        ;         Child Loop BB2_15 Depth 4
                                        ;           Child Loop BB2_16 Depth 5
                                        ;           Child Loop BB2_18 Depth 5
                                        ;           Child Loop BB2_20 Depth 5
                                        ;             Child Loop BB2_21 Depth 6
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[35:36], null, 0x70000, s12, v[33:34]
	s_add_i32 s0, s4, s12
	s_mov_b32 s16, 0
	s_cmp_gt_u32 s0, 13
	s_cselect_b32 s13, -1, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_mad_u64_u32 v[36:37], null, 0x60000, s12, v[34:35]
.LBB2_9:                                ;   Parent Loop BB2_7 Depth=1
                                        ;     Parent Loop BB2_8 Depth=2
                                        ; =>    This Loop Header: Depth=3
                                        ;         Child Loop BB2_15 Depth 4
                                        ;           Child Loop BB2_16 Depth 5
                                        ;           Child Loop BB2_18 Depth 5
                                        ;           Child Loop BB2_20 Depth 5
                                        ;             Child Loop BB2_21 Depth 6
	s_add_i32 s0, s8, s16
	s_waitcnt_vscnt null, 0x0
	s_cmp_gt_u32 s0, 13
	s_barrier
	s_cselect_b32 s0, -1, 0
	buffer_gl0_inv
	s_or_b32 s0, s13, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccnz .LBB2_11
; %bb.10:                               ;   in Loop: Header=BB2_9 Depth=3
	s_add_i32 s0, s16, s15
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshl_add_u32 v26, s0, 15, v35
	s_mov_b32 s0, 0
	v_ashrrev_i32_e32 v27, 31, v26
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[26:27], 2, v[26:27]
	v_add_co_u32 v26, vcc_lo, s5, v26
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v27, vcc_lo, s9, v27, vcc_lo
	s_clause 0x1
	global_load_b128 v[45:48], v[26:27], off
	global_load_b128 v[29:32], v[26:27], off offset:16
	s_waitcnt vmcnt(1)
	ds_store_b128 v39, v[45:48]
	s_branch .LBB2_12
.LBB2_11:                               ;   in Loop: Header=BB2_9 Depth=3
	s_mov_b32 s0, -1
                                        ; implicit-def: $vgpr32
.LBB2_12:                               ; %Flow
                                        ;   in Loop: Header=BB2_9 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccnz .LBB2_14
; %bb.13:                               ; %.preheader107.critedge
                                        ;   in Loop: Header=BB2_9 Depth=3
	s_waitcnt vmcnt(0)
	v_dual_mov_b32 v29, 0 :: v_dual_mov_b32 v26, v25
	v_mov_b32_e32 v27, v25
	v_mov_b32_e32 v28, v25
	s_delay_alu instid0(VALU_DEP_3)
	v_mov_b32_e32 v30, v29
	v_mov_b32_e32 v31, v29
	v_mov_b32_e32 v32, v29
	ds_store_b128 v39, v[25:28]
.LBB2_14:                               ; %.preheader107
                                        ;   in Loop: Header=BB2_9 Depth=3
	v_lshl_add_u32 v26, s16, 17, v36
	s_mov_b32 s17, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v27, 31, v26
	v_lshlrev_b64 v[26:27], 2, v[26:27]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v26, vcc_lo, s2, v26
	v_add_co_ci_u32_e32 v27, vcc_lo, s3, v27, vcc_lo
	s_clause 0x1
	global_load_b128 v[45:48], v[26:27], off
	global_load_b128 v[49:52], v[26:27], off offset:16
	v_dual_mov_b32 v26, v44 :: v_dual_mov_b32 v27, v38
	s_waitcnt vmcnt(2)
	ds_store_b128 v39, v[29:32] offset:16
	s_waitcnt vmcnt(1)
	ds_store_b128 v42, v[45:48]
	s_waitcnt vmcnt(0)
	ds_store_b128 v43, v[49:52]
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
.LBB2_15:                               ; %.preheader106
                                        ;   Parent Loop BB2_7 Depth=1
                                        ;     Parent Loop BB2_8 Depth=2
                                        ;       Parent Loop BB2_9 Depth=3
                                        ; =>      This Loop Header: Depth=4
                                        ;           Child Loop BB2_16 Depth 5
                                        ;           Child Loop BB2_18 Depth 5
                                        ;           Child Loop BB2_20 Depth 5
                                        ;             Child Loop BB2_21 Depth 6
	v_mov_b32_e32 v28, v27
	s_mov_b64 s[0:1], 0
.LBB2_16:                               ;   Parent Loop BB2_7 Depth=1
                                        ;     Parent Loop BB2_8 Depth=2
                                        ;       Parent Loop BB2_9 Depth=3
                                        ;         Parent Loop BB2_15 Depth=4
                                        ; =>        This Inner Loop Header: Depth=5
	ds_load_b32 v29, v28
	v_add_nc_u32_e32 v28, 4, v28
	s_mov_b32 m0, s0
	s_add_u32 s0, s0, 1
	s_addc_u32 s1, s1, 0
	s_cmp_lg_u32 s0, 8
	s_waitcnt lgkmcnt(0)
	v_movreld_b32_e32 v9, v29
	s_cbranch_scc1 .LBB2_16
; %bb.17:                               ; %.preheader105.preheader
                                        ;   in Loop: Header=BB2_15 Depth=4
	v_mov_b32_e32 v28, v26
	s_mov_b64 s[0:1], 0
.LBB2_18:                               ; %.preheader105
                                        ;   Parent Loop BB2_7 Depth=1
                                        ;     Parent Loop BB2_8 Depth=2
                                        ;       Parent Loop BB2_9 Depth=3
                                        ;         Parent Loop BB2_15 Depth=4
                                        ; =>        This Inner Loop Header: Depth=5
	ds_load_b32 v29, v28
	v_add_nc_u32_e32 v28, 4, v28
	s_mov_b32 m0, s0
	s_add_u32 s0, s0, 1
	s_addc_u32 s1, s1, 0
	s_cmp_lg_u32 s0, 8
	s_waitcnt lgkmcnt(0)
	v_movreld_b32_e32 v17, v29
	s_cbranch_scc1 .LBB2_18
; %bb.19:                               ; %.preheader103.preheader
                                        ;   in Loop: Header=BB2_15 Depth=4
	v_mov_b32_e32 v28, 16
	s_mov_b32 s18, 0
.LBB2_20:                               ; %.preheader103
                                        ;   Parent Loop BB2_7 Depth=1
                                        ;     Parent Loop BB2_8 Depth=2
                                        ;       Parent Loop BB2_9 Depth=3
                                        ;         Parent Loop BB2_15 Depth=4
                                        ; =>        This Loop Header: Depth=5
                                        ;             Child Loop BB2_21 Depth 6
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_mov_b32 m0, s18
	v_mov_b32_e32 v30, v28
	v_movrels_b32_e32 v29, v17
	s_mov_b64 s[0:1], 0
.LBB2_21:                               ;   Parent Loop BB2_7 Depth=1
                                        ;     Parent Loop BB2_8 Depth=2
                                        ;       Parent Loop BB2_9 Depth=3
                                        ;         Parent Loop BB2_15 Depth=4
                                        ;           Parent Loop BB2_20 Depth=5
                                        ; =>          This Inner Loop Header: Depth=6
	scratch_load_b32 v31, v30, off
	s_mov_b32 m0, s0
	s_add_u32 s0, s0, 1
	v_movrels_b32_e32 v32, v9
	s_addc_u32 s1, s1, 0
	s_cmp_eq_u32 s0, 8
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v31, v29, v32
	scratch_store_b32 v30, v31, off
	v_add_nc_u32_e32 v30, 4, v30
	s_cbranch_scc0 .LBB2_21
; %bb.22:                               ;   in Loop: Header=BB2_20 Depth=5
	v_add_nc_u32_e32 v28, 32, v28
	s_add_i32 s18, s18, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s18, 8
	s_cbranch_scc0 .LBB2_20
; %bb.23:                               ;   in Loop: Header=BB2_15 Depth=4
	v_add_nc_u32_e32 v27, 0x100, v27
	v_add_nc_u32_e32 v26, 0x100, v26
	s_add_i32 s17, s17, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s17, 8
	s_cbranch_scc0 .LBB2_15
; %bb.24:                               ;   in Loop: Header=BB2_9 Depth=3
	s_add_i32 s16, s16, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s16, 3
	s_cbranch_scc0 .LBB2_9
; %bb.25:                               ;   in Loop: Header=BB2_8 Depth=2
	s_add_i32 s12, s12, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s12, 3
	s_cbranch_scc0 .LBB2_8
; %bb.26:                               ;   in Loop: Header=BB2_7 Depth=1
	s_add_i32 s11, s11, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s11, 32
	s_cbranch_scc0 .LBB2_7
; %bb.27:                               ; %.preheader102
	v_mul_u32_u24_e32 v0, 0x408, v0
	s_lshl_b32 s0, s14, 13
	s_lshl_b32 s1, s15, 16
	s_add_i32 s10, s10, s0
	v_mov_b32_e32 v9, 16
	v_add3_u32 v0, s10, s1, v0
	s_mov_b32 s0, 0
.LBB2_28:                               ; %.preheader
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB2_29 Depth 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	s_mov_b32 m0, s0
	v_mov_b32_e32 v11, v9
	v_movrels_b32_e32 v10, v1
	s_mov_b32 s1, 0
.LBB2_29:                               ;   Parent Loop BB2_28 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	scratch_load_b32 v14, v11, off
	v_add_nc_u32_e32 v12, s1, v0
	s_add_i32 s1, s1, 1
	v_add_nc_u32_e32 v11, 4, v11
	s_cmp_eq_u32 s1, 8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v13, 31, v12
	v_lshlrev_b64 v[12:13], 2, v[12:13]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v12, vcc_lo, s6, v12
	v_add_co_ci_u32_e32 v13, vcc_lo, s7, v13, vcc_lo
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v14, v10, v14
	global_store_b32 v[12:13], v14, off
	s_cbranch_scc0 .LBB2_29
; %bb.30:                               ;   in Loop: Header=BB2_28 Depth=1
	v_add_nc_u32_e32 v9, 32, v9
	v_add_nc_u32_e32 v0, 0x80, v0
	s_add_i32 s0, s0, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s0, 8
	s_cbranch_scc0 .LBB2_28
; %bb.31:
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z24default_function_kernel0PvS_S_S_
		.amdhsa_group_segment_fixed_size 4096
		.amdhsa_private_segment_fixed_size 272
		.amdhsa_kernarg_size 32
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 1
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 53
		.amdhsa_next_free_sgpr 19
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_Z24default_function_kernel0PvS_S_S_, .Lfunc_end2-_Z24default_function_kernel0PvS_S_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1132
; NumSgprs: 21
; NumVgprs: 53
; ScratchSize: 272
; MemoryBound: 1
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 4096 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 6
; NumSGPRsForWavesPerEU: 21
; NumVGPRsForWavesPerEU: 53
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 1
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .actual_access:  read_only
        .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .actual_access:  read_only
        .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .actual_access:  write_only
        .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
    .group_segment_fixed_size: 4096
    .kernarg_segment_align: 8
    .kernarg_segment_size: 24
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z4convPvS_S_
    .private_segment_fixed_size: 272
    .sgpr_count:     21
    .sgpr_spill_count: 0
    .symbol:         _Z4convPvS_S_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     45
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .actual_access:  read_only
        .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .actual_access:  read_only
        .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .actual_access:  read_only
        .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .actual_access:  read_only
        .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .actual_access:  read_only
        .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .actual_access:  read_only
        .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .actual_access:  write_only
        .address_space:  global
        .offset:         48
        .size:           8
        .value_kind:     global_buffer
    .group_segment_fixed_size: 4096
    .kernarg_segment_align: 8
    .kernarg_segment_size: 56
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z12conv_bn_reluPvS_S_S_S_S_S_
    .private_segment_fixed_size: 272
    .sgpr_count:     22
    .sgpr_spill_count: 0
    .symbol:         _Z12conv_bn_reluPvS_S_S_S_S_S_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     77
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .actual_access:  read_only
        .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .actual_access:  read_only
        .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .actual_access:  read_only
        .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .actual_access:  write_only
        .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
    .group_segment_fixed_size: 4096
    .kernarg_segment_align: 8
    .kernarg_segment_size: 32
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z24default_function_kernel0PvS_S_S_
    .private_segment_fixed_size: 272
    .sgpr_count:     21
    .sgpr_spill_count: 0
    .symbol:         _Z24default_function_kernel0PvS_S_S_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     53
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
