#include <stdio.h>
#include "cuda.h"
#define max(x,y)  ((x) > (y)? (x) : (y))
#define min(x,y)  ((x) < (y)? (x) : (y))
#define ceil(a,b) ((a) % (b) == 0 ? (a) / (b) : ((a) / (b)) + 1)

void check_error (const char* message) {
  cudaError_t error = cudaGetLastError ();
  if (error != cudaSuccess) {
    printf ("CUDA error : %s, %s\n", message, cudaGetErrorString (error));
    exit(-1);
  }
}

__global__ void heat (double * __restrict__ in, double * __restrict__ out1, double * __restrict__ out2, double * __restrict__ out3, double * __restrict__ out, int L, int M, int N) {
  //Determining the block's indices
  int blockdim_i= (int)(blockDim.x);
  int i0 = (int)(blockIdx.x)*(blockdim_i-8);
  int i = i0 + (int)(threadIdx.x);
  int blockdim_j= (int)(blockDim.y);
  int j0 = (int)(blockIdx.y)*(blockdim_j-8);
  int j = j0 + (int)(threadIdx.y);

  //Declarations
  double reg_in_m1=0, __shared__ sh_in_c0[32][32], reg_in_p1=0;
  double reg_out1_m2=0, __shared__ sh_out1_m1[32][32], reg_out1_c0=0;
  double reg_out2_m3=0, __shared__ sh_out2_m2[32][32], reg_out2_m1=0;
  double reg_out3_m4=0, __shared__ sh_out3_m3[32][32], reg_out3_m2=0;

  //Value Initialization
  if (j <= min (j0+blockdim_j-1, M-1) & i <= min (i0+blockdim_i-1, N-1)) {
    reg_in_m1 = in[0 + j*N + i];
    sh_in_c0[j-j0][i-i0] = in[1*M*N + j*N + i];
  }

  //Rest of the computation
  #pragma unroll 2
  for (int k=1; k<=L-2; ++k) {
    //Fetch new plane
    if (j <= min (j0+blockdim_j-1, M-1) & i <= min (i0+blockdim_i-1, N-1)) {
        reg_in_p1 = in[(k+1)*M*N + j*N + i];
    }
    __syncthreads ();
    if (j >= j0+1 & j <= min (j0+blockdim_j-2, M-2) & i >= i0+1 & i <= min (i0+blockdim_i-2, N-2)) {
        reg_out1_c0 = ((((0.125f * ((reg_in_p1 - (2.0f * sh_in_c0[j-j0][i-i0])) + reg_in_m1)) + (0.125f * ((sh_in_c0[j-j0+1][i-i0] - (2.0f * sh_in_c0[j-j0][i-i0])) + sh_in_c0[j-j0-1][i-i0]))) + (0.125f * ((sh_in_c0[j-j0][i-i0+1] - (2.0f * sh_in_c0[j-j0][i-i0])) + sh_in_c0[j-j0][i-i0-1]))) + sh_in_c0[j-j0][i-i0]);
    }
    __syncthreads ();
    if (j >= j0+2 & j <= min (j0+blockdim_j-3, M-2) & i >= i0+2 & i <= min (i0+blockdim_i-3, N-2)) {
        reg_out2_m1 = ((((0.125f * ((reg_out1_c0 - (2.0f * sh_out1_m1[j-j0][i-i0])) + reg_out1_m2)) + (0.125f * ((sh_out1_m1[j-j0+1][i-i0] - (2.0f * sh_out1_m1[j-j0][i-i0])) + sh_out1_m1[j-j0-1][i-i0]))) + (0.125f * ((sh_out1_m1[j-j0][i-i0+1] - (2.0f * sh_out1_m1[j-j0][i-i0])) + sh_out1_m1[j-j0][i-i0-1]))) + sh_out1_m1[j-j0][i-i0]);
    }
    __syncthreads ();
    if (j >= j0+3 & j <= min (j0+blockdim_j-4, M-2) & i >= i0+3 & i <= min (i0+blockdim_i-4, N-2)) {
        reg_out3_m2 = ((((0.125f * ((reg_out2_m1 - (2.0f * sh_out2_m2[j-j0][i-i0])) + reg_out2_m3)) + (0.125f * ((sh_out2_m2[j-j0+1][i-i0] - (2.0f * sh_out2_m2[j-j0][i-i0])) + sh_out2_m2[j-j0-1][i-i0]))) + (0.125f * ((sh_out2_m2[j-j0][i-i0+1] - (2.0f * sh_out2_m2[j-j0][i-i0])) + sh_out2_m2[j-j0][i-i0-1]))) + sh_out2_m2[j-j0][i-i0]);
    }
    __syncthreads ();
    if (j >= j0+4 & j <= min (j0+blockdim_j-5, M-2) & i >= i0+4 & i <= min (i0+blockdim_i-5, N-2)) {
        out[max(k-3,0)*M*N + j*N + i] = ((((0.125f * ((reg_out3_m2 - (2.0f * sh_out3_m3[j-j0][i-i0])) + reg_out3_m4)) + (0.125f * ((sh_out3_m3[j-j0+1][i-i0] - (2.0f * sh_out3_m3[j-j0][i-i0])) + sh_out3_m3[j-j0-1][i-i0]))) + (0.125f * ((sh_out3_m3[j-j0][i-i0+1] - (2.0f * sh_out3_m3[j-j0][i-i0])) + sh_out3_m3[j-j0][i-i0-1]))) + sh_out3_m3[j-j0][i-i0]);
    }
    __syncthreads ();
    //Value rotation
    reg_in_m1 = sh_in_c0[j-j0][i-i0];
    sh_in_c0[j-j0][i-i0] = reg_in_p1;
    reg_out1_m2 = sh_out1_m1[j-j0][i-i0];
    sh_out1_m1[j-j0][i-i0] = reg_out1_c0;
    reg_out2_m3 = sh_out2_m2[j-j0][i-i0];
    sh_out2_m2[j-j0][i-i0] = reg_out2_m1;
    reg_out3_m4 = sh_out3_m3[j-j0][i-i0];
    sh_out3_m3[j-j0][i-i0] = reg_out3_m2;
  }
}

extern "C" void host_code (double *h_in, double *h_out, int L, int M, int N) {
  double *in;
  cudaMalloc (&in, sizeof(double)*L*M*N);
  check_error ("Failed to allocate device memory for in\n");
  cudaMemcpy (in, h_in, sizeof(double)*L*M*N, cudaMemcpyHostToDevice);
  double *out;
  cudaMalloc (&out, sizeof(double)*L*M*N);
  check_error ("Failed to allocate device memory for out\n");
  double *out1;
  cudaMalloc (&out1, sizeof(double)*L*M*N);
  check_error ("Failed to allocate device memory for out1\n");
  double *out2;
  cudaMalloc (&out2, sizeof(double)*L*M*N);
  check_error ("Failed to allocate device memory for out2\n");
  double *out3;
  cudaMalloc (&out3, sizeof(double)*L*M*N);
  check_error ("Failed to allocate device memory for out3\n");

  dim3 blockconfig_1 (32, 32, 1);
  dim3 gridconfig_1 (ceil(N, blockconfig_1.x-8), ceil(M, blockconfig_1.y-8), 1);
  heat <<<gridconfig_1, blockconfig_1>>> (in, out1, out2, out3, out, L, M, N);

  cudaMemcpy (h_out, out, sizeof(double)*L*M*N, cudaMemcpyDeviceToHost);

  //Free allocated memory
  cudaFree (in);
  cudaFree (out);
  cudaFree (out1);
  cudaFree (out2);
  cudaFree (out3);
}

	.file	"tmpxft_0027bfdd_00000000-6_heat-gen-4.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2031:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"CUDA error : %s, %s\n"
	.text
	.globl	_Z11check_errorPKc
	.type	_Z11check_errorPKc, @function
_Z11check_errorPKc:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	movq	%rdi, %rbx
	call	cudaGetLastError@PLT
	testl	%eax, %eax
	je	.L2
	movl	%eax, %edi
	call	cudaGetErrorString@PLT
	movl	$2, %edi
	movq	%rbx, %rdx
	leaq	.LC0(%rip), %rsi
	movq	%rax, %rcx
	xorl	%eax, %eax
	call	__printf_chk@PLT
	orl	$-1, %edi
	call	exit@PLT
.L2:
	popq	%rbx
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2027:
	.size	_Z11check_errorPKc, .-_Z11check_errorPKc
	.globl	_Z34__device_stub__Z4heatPdS_S_S_S_iiiPdS_S_S_S_iii
	.type	_Z34__device_stub__Z4heatPdS_S_S_S_iiiPdS_S_S_S_iii, @function
_Z34__device_stub__Z4heatPdS_S_S_S_iiiPdS_S_S_S_iii:
.LFB2053:
	.cfi_startproc
	endbr64
	subq	$200, %rsp
	.cfi_def_cfa_offset 208
	movl	%r9d, 12(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 184(%rsp)
	xorl	%eax, %eax
	leaq	16(%rsp), %rax
	movq	%rdi, 16(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rax, 120(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	208(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	216(%rsp), %rax
	movq	%rsi, 24(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 32(%rsp)
	leaq	56(%rsp), %rdx
	movq	%rcx, 40(%rsp)
	leaq	64(%rsp), %rcx
	movq	%rax, 176(%rsp)
	movabsq	$4294967297, %rax
	movq	%r8, 48(%rsp)
	movq	%rax, 72(%rsp)
	movl	$1, 80(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L6
	pushq	64(%rsp)
	.cfi_def_cfa_offset 216
	leaq	_Z4heatPdS_S_S_S_iii(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 224
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 216
	popq	%rdx
	.cfi_def_cfa_offset 208
.L6:
	movq	184(%rsp), %rax
	subq	%fs:40, %rax
	je	.L8
	call	__stack_chk_fail@PLT
.L8:
	addq	$200, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2053:
	.size	_Z34__device_stub__Z4heatPdS_S_S_S_iiiPdS_S_S_S_iii, .-_Z34__device_stub__Z4heatPdS_S_S_S_iiiPdS_S_S_S_iii
	.globl	_Z4heatPdS_S_S_S_iii
	.type	_Z4heatPdS_S_S_S_iii, @function
_Z4heatPdS_S_S_S_iii:
.LFB2054:
	.cfi_startproc
	endbr64
	jmp	_Z34__device_stub__Z4heatPdS_S_S_S_iiiPdS_S_S_S_iii
	.cfi_endproc
.LFE2054:
	.size	_Z4heatPdS_S_S_S_iii, .-_Z4heatPdS_S_S_S_iii
	.section	.rodata.str1.1
.LC1:
	.string	"Failed to allocate device memory for in\n"
.LC2:
	.string	"Failed to allocate device memory for out\n"
.LC3:
	.string	"Failed to allocate device memory for out1\n"
.LC4:
	.string	"Failed to allocate device memory for out2\n"
.LC5:
	.string	"Failed to allocate device memory for out3\n"
	.text
	.globl	host_code
	.type	host_code, @function
host_code:
.LFB2028:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movq	%rdi, %r15
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	movq	%rsi, %r14
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movl	%edx, %r13d
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movl	%r8d, %r12d
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movslq	%ecx, %rbx
	movq	%rbx, %rbp
	subq	$88, %rsp
	.cfi_def_cfa_offset 144
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	xorl	%eax, %eax
	movslq	%r8d, %rax
	leaq	8(%rsp), %rdi
	imulq	%rax, %rbx
	movslq	%edx, %rax
	imulq	%rax, %rbx
	salq	$3, %rbx
	movq	%rbx, %rsi
	call	cudaMalloc@PLT
	leaq	.LC1(%rip), %rdi
	call	_Z11check_errorPKc
	movq	8(%rsp), %rdi
	movq	%rbx, %rdx
	movq	%r15, %rsi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	movq	%rbx, %rsi
	leaq	16(%rsp), %rdi
	call	cudaMalloc@PLT
	leaq	.LC2(%rip), %rdi
	call	_Z11check_errorPKc
	movq	%rbx, %rsi
	leaq	24(%rsp), %rdi
	call	cudaMalloc@PLT
	leaq	.LC3(%rip), %rdi
	call	_Z11check_errorPKc
	movq	%rbx, %rsi
	leaq	32(%rsp), %rdi
	call	cudaMalloc@PLT
	leaq	.LC4(%rip), %rdi
	call	_Z11check_errorPKc
	movq	%rbx, %rsi
	leaq	40(%rsp), %rdi
	call	cudaMalloc@PLT
	leaq	.LC5(%rip), %rdi
	call	_Z11check_errorPKc
	movl	$24, %ecx
	xorl	%edx, %edx
	movl	%ebp, %eax
	divl	%ecx
	cmpl	$1, %edx
	sbbl	$-1, %eax
	xorl	%edx, %edx
	movl	%eax, %esi
	movl	%r12d, %eax
	divl	%ecx
	movl	%esi, 64(%rsp)
	movl	$1, %ecx
	movl	$1, %esi
	cmpl	$1, %edx
	movabsq	$137438953504, %rdx
	sbbl	$-1, %eax
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	%eax, 60(%rsp)
	movq	60(%rsp), %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L14
	pushq	%r12
	.cfi_def_cfa_offset 152
	movl	%r13d, %r9d
	pushq	%rbp
	.cfi_def_cfa_offset 160
	movq	32(%rsp), %r8
	movq	56(%rsp), %rcx
	movq	48(%rsp), %rdx
	movq	40(%rsp), %rsi
	movq	24(%rsp), %rdi
	call	_Z34__device_stub__Z4heatPdS_S_S_S_iiiPdS_S_S_S_iii
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L14:
	movq	16(%rsp), %rsi
	movl	$2, %ecx
	movq	%rbx, %rdx
	movq	%r14, %rdi
	call	cudaMemcpy@PLT
	movq	8(%rsp), %rdi
	call	cudaFree@PLT
	movq	16(%rsp), %rdi
	call	cudaFree@PLT
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	movq	32(%rsp), %rdi
	call	cudaFree@PLT
	movq	40(%rsp), %rdi
	call	cudaFree@PLT
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L15
	call	__stack_chk_fail@PLT
.L15:
	addq	$88, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2028:
	.size	host_code, .-host_code
	.section	.rodata.str1.1
.LC6:
	.string	"_Z4heatPdS_S_S_S_iii"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2056:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC6(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z4heatPdS_S_S_S_iii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2056:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <stdio.h>
#include "hip/hip_runtime.h"
#define max(x,y)  ((x) > (y)? (x) : (y))
#define min(x,y)  ((x) < (y)? (x) : (y))
#define ceil(a,b) ((a) % (b) == 0 ? (a) / (b) : ((a) / (b)) + 1)

void check_error (const char* message) {
  hipError_t error = hipGetLastError ();
  if (error != hipSuccess) {
    printf ("CUDA error : %s, %s\n", message, hipGetErrorString (error));
    exit(-1);
  }
}

__global__ void heat (double * __restrict__ in, double * __restrict__ out1, double * __restrict__ out2, double * __restrict__ out3, double * __restrict__ out, int L, int M, int N) {
  //Determining the block's indices
  int blockdim_i= (int)(blockDim.x);
  int i0 = (int)(blockIdx.x)*(blockdim_i-8);
  int i = i0 + (int)(threadIdx.x);
  int blockdim_j= (int)(blockDim.y);
  int j0 = (int)(blockIdx.y)*(blockdim_j-8);
  int j = j0 + (int)(threadIdx.y);

  //Declarations
  double reg_in_m1=0, __shared__ sh_in_c0[32][32], reg_in_p1=0;
  double reg_out1_m2=0, __shared__ sh_out1_m1[32][32], reg_out1_c0=0;
  double reg_out2_m3=0, __shared__ sh_out2_m2[32][32], reg_out2_m1=0;
  double reg_out3_m4=0, __shared__ sh_out3_m3[32][32], reg_out3_m2=0;

  //Value Initialization
  if (j <= min (j0+blockdim_j-1, M-1) & i <= min (i0+blockdim_i-1, N-1)) {
    reg_in_m1 = in[0 + j*N + i];
    sh_in_c0[j-j0][i-i0] = in[1*M*N + j*N + i];
  }

  //Rest of the computation
  #pragma unroll 2
  for (int k=1; k<=L-2; ++k) {
    //Fetch new plane
    if (j <= min (j0+blockdim_j-1, M-1) & i <= min (i0+blockdim_i-1, N-1)) {
        reg_in_p1 = in[(k+1)*M*N + j*N + i];
    }
    __syncthreads ();
    if (j >= j0+1 & j <= min (j0+blockdim_j-2, M-2) & i >= i0+1 & i <= min (i0+blockdim_i-2, N-2)) {
        reg_out1_c0 = ((((0.125f * ((reg_in_p1 - (2.0f * sh_in_c0[j-j0][i-i0])) + reg_in_m1)) + (0.125f * ((sh_in_c0[j-j0+1][i-i0] - (2.0f * sh_in_c0[j-j0][i-i0])) + sh_in_c0[j-j0-1][i-i0]))) + (0.125f * ((sh_in_c0[j-j0][i-i0+1] - (2.0f * sh_in_c0[j-j0][i-i0])) + sh_in_c0[j-j0][i-i0-1]))) + sh_in_c0[j-j0][i-i0]);
    }
    __syncthreads ();
    if (j >= j0+2 & j <= min (j0+blockdim_j-3, M-2) & i >= i0+2 & i <= min (i0+blockdim_i-3, N-2)) {
        reg_out2_m1 = ((((0.125f * ((reg_out1_c0 - (2.0f * sh_out1_m1[j-j0][i-i0])) + reg_out1_m2)) + (0.125f * ((sh_out1_m1[j-j0+1][i-i0] - (2.0f * sh_out1_m1[j-j0][i-i0])) + sh_out1_m1[j-j0-1][i-i0]))) + (0.125f * ((sh_out1_m1[j-j0][i-i0+1] - (2.0f * sh_out1_m1[j-j0][i-i0])) + sh_out1_m1[j-j0][i-i0-1]))) + sh_out1_m1[j-j0][i-i0]);
    }
    __syncthreads ();
    if (j >= j0+3 & j <= min (j0+blockdim_j-4, M-2) & i >= i0+3 & i <= min (i0+blockdim_i-4, N-2)) {
        reg_out3_m2 = ((((0.125f * ((reg_out2_m1 - (2.0f * sh_out2_m2[j-j0][i-i0])) + reg_out2_m3)) + (0.125f * ((sh_out2_m2[j-j0+1][i-i0] - (2.0f * sh_out2_m2[j-j0][i-i0])) + sh_out2_m2[j-j0-1][i-i0]))) + (0.125f * ((sh_out2_m2[j-j0][i-i0+1] - (2.0f * sh_out2_m2[j-j0][i-i0])) + sh_out2_m2[j-j0][i-i0-1]))) + sh_out2_m2[j-j0][i-i0]);
    }
    __syncthreads ();
    if (j >= j0+4 & j <= min (j0+blockdim_j-5, M-2) & i >= i0+4 & i <= min (i0+blockdim_i-5, N-2)) {
        out[max(k-3,0)*M*N + j*N + i] = ((((0.125f * ((reg_out3_m2 - (2.0f * sh_out3_m3[j-j0][i-i0])) + reg_out3_m4)) + (0.125f * ((sh_out3_m3[j-j0+1][i-i0] - (2.0f * sh_out3_m3[j-j0][i-i0])) + sh_out3_m3[j-j0-1][i-i0]))) + (0.125f * ((sh_out3_m3[j-j0][i-i0+1] - (2.0f * sh_out3_m3[j-j0][i-i0])) + sh_out3_m3[j-j0][i-i0-1]))) + sh_out3_m3[j-j0][i-i0]);
    }
    __syncthreads ();
    //Value rotation
    reg_in_m1 = sh_in_c0[j-j0][i-i0];
    sh_in_c0[j-j0][i-i0] = reg_in_p1;
    reg_out1_m2 = sh_out1_m1[j-j0][i-i0];
    sh_out1_m1[j-j0][i-i0] = reg_out1_c0;
    reg_out2_m3 = sh_out2_m2[j-j0][i-i0];
    sh_out2_m2[j-j0][i-i0] = reg_out2_m1;
    reg_out3_m4 = sh_out3_m3[j-j0][i-i0];
    sh_out3_m3[j-j0][i-i0] = reg_out3_m2;
  }
}

extern "C" void host_code (double *h_in, double *h_out, int L, int M, int N) {
  double *in;
  hipMalloc (&in, sizeof(double)*L*M*N);
  check_error ("Failed to allocate device memory for in\n");
  hipMemcpy (in, h_in, sizeof(double)*L*M*N, hipMemcpyHostToDevice);
  double *out;
  hipMalloc (&out, sizeof(double)*L*M*N);
  check_error ("Failed to allocate device memory for out\n");
  double *out1;
  hipMalloc (&out1, sizeof(double)*L*M*N);
  check_error ("Failed to allocate device memory for out1\n");
  double *out2;
  hipMalloc (&out2, sizeof(double)*L*M*N);
  check_error ("Failed to allocate device memory for out2\n");
  double *out3;
  hipMalloc (&out3, sizeof(double)*L*M*N);
  check_error ("Failed to allocate device memory for out3\n");

  dim3 blockconfig_1 (32, 32, 1);
  dim3 gridconfig_1 (ceil(N, blockconfig_1.x-8), ceil(M, blockconfig_1.y-8), 1);
  heat <<<gridconfig_1, blockconfig_1>>> (in, out1, out2, out3, out, L, M, N);

  hipMemcpy (h_out, out, sizeof(double)*L*M*N, hipMemcpyDeviceToHost);

  //Free allocated memory
  hipFree (in);
  hipFree (out);
  hipFree (out1);
  hipFree (out2);
  hipFree (out3);
}

	.text
	.file	"heat-gen-4.hip"
	.globl	_Z11check_errorPKc              # -- Begin function _Z11check_errorPKc
	.type	_Z11check_errorPKc,@function
_Z11check_errorPKc:                     # @_Z11check_errorPKc
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset %rbx, -16
	movq	%rdi, %rbx
	callq	hipGetLastError
	testl	%eax, %eax
	jne	.LBB0_2
# %bb.1:
	popq	%rbx
	.cfi_def_cfa_offset 8
	retq
.LBB0_2:
	.cfi_def_cfa_offset 16
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str, %edi
	movq	%rbx, %rsi
	movq	%rax, %rdx
	xorl	%eax, %eax
	callq	printf
	movl	$-1, %edi
	callq	exit
.Lfunc_end0:
	.size	_Z11check_errorPKc, .Lfunc_end0-_Z11check_errorPKc
	.cfi_endproc
                                        # -- End function
	.globl	_Z19__device_stub__heatPdS_S_S_S_iii # -- Begin function _Z19__device_stub__heatPdS_S_S_S_iii
	.type	_Z19__device_stub__heatPdS_S_S_S_iii,@function
_Z19__device_stub__heatPdS_S_S_S_iii:   # @_Z19__device_stub__heatPdS_S_S_S_iii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	4(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	216(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z4heatPdS_S_S_S_iii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z19__device_stub__heatPdS_S_S_S_iii, .Lfunc_end1-_Z19__device_stub__heatPdS_S_S_S_iii
	.cfi_endproc
                                        # -- End function
	.globl	host_code                       # -- Begin function host_code
	.type	host_code,@function
host_code:                              # @host_code
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$72, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
                                        # kill: def $r8d killed $r8d def $r8
                                        # kill: def $ecx killed $ecx def $rcx
	movl	%edx, %ebp
	movq	%rsi, 64(%rsp)                  # 8-byte Spill
	movq	%rdi, %r13
	movslq	%edx, %r14
	movq	%rcx, 56(%rsp)                  # 8-byte Spill
	movslq	%ecx, %r15
	imulq	%r15, %r14
	movq	%r8, 48(%rsp)                   # 8-byte Spill
	movslq	%r8d, %r12
	imulq	%r12, %r14
	shlq	$3, %r14
	leaq	40(%rsp), %rbx
	movq	%rbx, %rdi
	movq	%r14, %rsi
	callq	hipMalloc
	movl	$.L.str.1, %edi
	callq	_Z11check_errorPKc
	movq	(%rbx), %rdi
	movq	%r13, %rsi
	movq	%r14, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	8(%rsp), %rdi
	movq	%r14, %rsi
	callq	hipMalloc
	movl	$.L.str.2, %edi
	callq	_Z11check_errorPKc
	leaq	32(%rsp), %rdi
	movq	%r14, %rsi
	callq	hipMalloc
	movl	$.L.str.3, %edi
	callq	_Z11check_errorPKc
	leaq	24(%rsp), %rdi
	movq	%r14, %rsi
	callq	hipMalloc
	movl	$.L.str.4, %edi
	callq	_Z11check_errorPKc
	leaq	16(%rsp), %rdi
	movq	%r14, %rsi
	callq	hipMalloc
	movl	$.L.str.5, %edi
	callq	_Z11check_errorPKc
	movl	%r12d, %ecx
	movl	$2863311531, %edx               # imm = 0xAAAAAAAB
	imulq	%rdx, %rcx
	shrq	$36, %rcx
	leal	(,%rcx,8), %eax
	leal	(%rax,%rax,2), %esi
	xorl	%eax, %eax
	cmpl	%esi, %r12d
	setne	%al
	addl	%ecx, %eax
	movl	%r15d, %ecx
	imulq	%rdx, %rcx
	shrq	$36, %rcx
	leal	(,%rcx,8), %edx
	leal	(%rdx,%rdx,2), %edx
	xorl	%edi, %edi
	cmpl	%edx, %r15d
	setne	%dil
	addl	%ecx, %edi
	shlq	$32, %rdi
	orq	%rax, %rdi
	movabsq	$137438953504, %rdx             # imm = 0x2000000020
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_2
# %bb.1:
	movq	40(%rsp), %rdi
	movq	32(%rsp), %rsi
	movq	24(%rsp), %rdx
	movq	16(%rsp), %rcx
	movq	8(%rsp), %r8
	movl	%ebp, %r9d
	pushq	48(%rsp)                        # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	64(%rsp)                        # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	callq	_Z19__device_stub__heatPdS_S_S_S_iii
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
.LBB2_2:
	movq	8(%rsp), %rsi
	movq	64(%rsp), %rdi                  # 8-byte Reload
	movq	%r14, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	movq	40(%rsp), %rdi
	callq	hipFree
	movq	8(%rsp), %rdi
	callq	hipFree
	movq	32(%rsp), %rdi
	callq	hipFree
	movq	24(%rsp), %rdi
	callq	hipFree
	movq	16(%rsp), %rdi
	callq	hipFree
	addq	$72, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	host_code, .Lfunc_end2-host_code
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB3_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB3_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z4heatPdS_S_S_S_iii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end3:
	.size	__hip_module_ctor, .Lfunc_end3-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB4_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB4_2:
	retq
.Lfunc_end4:
	.size	__hip_module_dtor, .Lfunc_end4-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"CUDA error : %s, %s\n"
	.size	.L.str, 21

	.type	_Z4heatPdS_S_S_S_iii,@object    # @_Z4heatPdS_S_S_S_iii
	.section	.rodata,"a",@progbits
	.globl	_Z4heatPdS_S_S_S_iii
	.p2align	3, 0x0
_Z4heatPdS_S_S_S_iii:
	.quad	_Z19__device_stub__heatPdS_S_S_S_iii
	.size	_Z4heatPdS_S_S_S_iii, 8

	.type	.L.str.1,@object                # @.str.1
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str.1:
	.asciz	"Failed to allocate device memory for in\n"
	.size	.L.str.1, 41

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"Failed to allocate device memory for out\n"
	.size	.L.str.2, 42

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"Failed to allocate device memory for out1\n"
	.size	.L.str.3, 43

	.type	.L.str.4,@object                # @.str.4
.L.str.4:
	.asciz	"Failed to allocate device memory for out2\n"
	.size	.L.str.4, 43

	.type	.L.str.5,@object                # @.str.5
.L.str.5:
	.asciz	"Failed to allocate device memory for out3\n"
	.size	.L.str.5, 43

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z4heatPdS_S_S_S_iii"
	.size	.L__unnamed_1, 21

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z19__device_stub__heatPdS_S_S_S_iii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z4heatPdS_S_S_S_iii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z4heatPdS_S_S_S_iii    ; -- Begin function _Z4heatPdS_S_S_S_iii
	.globl	_Z4heatPdS_S_S_S_iii
	.p2align	8
	.type	_Z4heatPdS_S_S_S_iii,@function
_Z4heatPdS_S_S_S_iii:                   ; @_Z4heatPdS_S_S_S_iii
; %bb.0:
	s_clause 0x2
	s_load_b32 s2, s[0:1], 0x44
	s_load_b128 s[4:7], s[0:1], 0x28
	s_load_b64 s[8:9], s[0:1], 0x0
	v_dual_mov_b32 v13, 0 :: v_dual_and_b32 v2, 0x3ff, v0
	v_bfe_u32 v3, v0, 10, 10
	v_mov_b32_e32 v14, 0
	s_delay_alu instid0(VALU_DEP_3)
	v_lshlrev_b32_e32 v4, 3, v2
	s_waitcnt lgkmcnt(0)
	s_and_b32 s3, s2, 0xffff
	s_lshr_b32 s2, s2, 16
	s_add_i32 s7, s3, -8
	s_add_i32 s10, s2, -8
	s_mul_i32 s14, s7, s14
	s_mul_i32 s16, s10, s15
	v_add_nc_u32_e32 v0, s14, v2
	v_add_nc_u32_e32 v1, s16, v3
	s_add_i32 s16, s16, s2
	s_add_i32 s15, s14, s3
	s_min_i32 s2, s16, s5
	s_min_i32 s3, s15, s6
	v_cmp_gt_i32_e32 vcc_lo, s2, v1
	v_cmp_gt_i32_e64 s2, s3, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s7, s2, vcc_lo
	s_and_saveexec_b32 s2, s7
	s_cbranch_execz .LBB0_2
; %bb.1:
	v_add_nc_u32_e32 v7, s5, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[5:6], null, v7, s6, v[0:1]
	v_mad_u64_u32 v[7:8], null, v1, s6, v[0:1]
	v_ashrrev_i32_e32 v6, 31, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v8, 31, v7
	v_lshlrev_b64 v[5:6], 3, v[5:6]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[7:8], 3, v[7:8]
	v_add_co_u32 v5, vcc_lo, s8, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v6, vcc_lo, s9, v6, vcc_lo
	v_add_co_u32 v7, vcc_lo, s8, v7
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v8, vcc_lo, s9, v8, vcc_lo
	s_clause 0x1
	global_load_b64 v[5:6], v[5:6], off
	global_load_b64 v[13:14], v[7:8], off
	v_lshl_add_u32 v7, v3, 8, v4
	s_waitcnt vmcnt(1)
	ds_store_b64 v7, v[5:6] offset:24576
.LBB0_2:
	s_or_b32 exec_lo, exec_lo, s2
	s_cmp_lt_i32 s4, 3
	s_cbranch_scc1 .LBB0_15
; %bb.3:                                ; %.lr.ph
	s_add_i32 s17, s5, -2
	s_add_i32 s2, s16, -2
	s_cmp_lt_i32 s16, s5
	v_cmp_ne_u32_e32 vcc_lo, 0, v3
	s_cselect_b32 s3, s2, s17
	v_cmp_ne_u32_e64 s2, 0, v2
	v_cmp_ge_i32_e64 s3, s3, v1
	s_add_i32 s18, s6, -2
	s_add_i32 s12, s15, -2
	s_load_b64 s[10:11], s[0:1], 0x20
	s_and_b32 s2, vcc_lo, s2
	v_lshl_add_u32 v19, v3, 8, v4
	s_and_b32 s2, s2, s3
	s_cmp_lt_i32 s15, s6
	v_min_u32_e32 v3, v3, v2
	s_cselect_b32 s0, s12, s18
	s_add_i32 s1, s16, -3
	v_cmp_ge_i32_e32 vcc_lo, s0, v0
	s_min_i32 s0, s1, s17
	s_add_i32 s1, s15, -3
	v_cmp_ge_i32_e64 s0, s0, v1
	s_min_i32 s1, s1, s18
	s_and_b32 s3, vcc_lo, s2
	v_cmp_ge_i32_e64 s1, s1, v0
	v_cmp_lt_u32_e32 vcc_lo, 1, v3
	v_lshl_add_u32 v4, s5, 1, v1
	v_dual_mov_b32 v5, 0 :: v_dual_add_nc_u32 v20, 0x6000, v19
	s_delay_alu instid0(VALU_DEP_4)
	s_and_b32 s0, s0, s1
	s_add_i32 s1, s15, -4
	s_and_b32 s12, s0, vcc_lo
	s_add_i32 s0, s16, -4
	s_min_i32 s1, s1, s18
	s_min_i32 s0, s0, s17
	v_mul_lo_u32 v4, s6, v4
	v_cmp_ge_i32_e32 vcc_lo, s0, v1
	v_cmp_ge_i32_e64 s0, s1, v0
	s_add_i32 s16, s16, -5
	s_add_i32 s15, s15, -5
	v_dual_mov_b32 v6, 0 :: v_dual_add_nc_u32 v21, 0x5f00, v19
	s_delay_alu instid0(VALU_DEP_2)
	s_and_b32 s19, vcc_lo, s0
	s_min_i32 s0, s16, s17
	s_min_i32 s2, s15, s18
	v_cmp_ge_i32_e32 vcc_lo, s0, v1
	v_cmp_ge_i32_e64 s0, s2, v0
	v_cmp_lt_u32_e64 s1, 2, v3
	v_cmp_lt_u32_e64 s2, 3, v3
	v_dual_mov_b32 v12, v6 :: v_dual_add_nc_u32 v23, 0xffffff00, v19
	v_dual_mov_b32 v8, v6 :: v_dual_add_nc_u32 v25, 0x2000, v19
	v_dual_mov_b32 v16, v6 :: v_dual_add_nc_u32 v27, 0x1ff8, v19
	v_dual_mov_b32 v10, v6 :: v_dual_add_nc_u32 v29, 0x3f00, v19
	v_add3_u32 v2, v2, v4, s14
	v_dual_mov_b32 v18, v6 :: v_dual_mov_b32 v3, v5
	v_dual_mov_b32 v11, v5 :: v_dual_add_nc_u32 v22, 0x5ff8, v19
	v_dual_mov_b32 v7, v5 :: v_dual_add_nc_u32 v24, -8, v19
	v_dual_mov_b32 v15, v5 :: v_dual_add_nc_u32 v26, 0x1f00, v19
	v_dual_mov_b32 v9, v5 :: v_dual_add_nc_u32 v28, 0x4000, v19
	v_dual_mov_b32 v17, v5 :: v_dual_add_nc_u32 v30, 0x3ff8, v19
	v_mov_b32_e32 v4, v6
	s_and_b32 s15, vcc_lo, s0
	s_mov_b32 s13, 2
	s_and_b32 s0, s19, s1
	s_and_b32 s1, s15, s2
	s_mul_i32 s2, s6, s5
.LBB0_4:                                ; =>This Inner Loop Header: Depth=1
	s_and_saveexec_b32 s14, s7
	s_cbranch_execz .LBB0_6
; %bb.5:                                ;   in Loop: Header=BB0_4 Depth=1
	v_ashrrev_i32_e32 v3, 31, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 3, v[2:3]
	v_add_co_u32 v3, vcc_lo, s8, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, s9, v4, vcc_lo
	global_load_b64 v[3:4], v[3:4], off
.LBB0_6:                                ;   in Loop: Header=BB0_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s14
	s_waitcnt vmcnt(0) lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s14, s3
	s_cbranch_execz .LBB0_8
; %bb.7:                                ;   in Loop: Header=BB0_4 Depth=1
	ds_load_2addr_b64 v[31:34], v20 offset0:1 offset1:32
	ds_load_2addr_b64 v[35:38], v22 offset1:1
	ds_load_b64 v[9:10], v21
	s_waitcnt lgkmcnt(1)
	v_fma_f64 v[33:34], v[37:38], -2.0, v[33:34]
	v_fma_f64 v[39:40], v[37:38], -2.0, v[3:4]
	v_fma_f64 v[31:32], v[37:38], -2.0, v[31:32]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[9:10], v[33:34], v[9:10]
	v_add_f64 v[13:14], v[13:14], v[39:40]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ldexp_f64 v[9:10], v[9:10], -3
	v_fma_f64 v[9:10], 0x3fc00000, v[13:14], v[9:10]
	v_add_f64 v[13:14], v[31:32], v[35:36]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[9:10], 0x3fc00000, v[13:14], v[9:10]
	v_add_f64 v[9:10], v[37:38], v[9:10]
.LBB0_8:                                ;   in Loop: Header=BB0_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s14
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s14, s12
	s_cbranch_execz .LBB0_10
; %bb.9:                                ;   in Loop: Header=BB0_4 Depth=1
	ds_load_2addr_b64 v[31:34], v19 offset0:1 offset1:32
	ds_load_2addr_b64 v[35:38], v24 offset1:1
	ds_load_b64 v[7:8], v23
	s_waitcnt lgkmcnt(1)
	v_fma_f64 v[13:14], v[37:38], -2.0, v[33:34]
	v_fma_f64 v[33:34], v[37:38], -2.0, v[9:10]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[7:8], v[13:14], v[7:8]
	v_add_f64 v[13:14], v[17:18], v[33:34]
	v_fma_f64 v[17:18], v[37:38], -2.0, v[31:32]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ldexp_f64 v[7:8], v[7:8], -3
	v_fma_f64 v[7:8], 0x3fc00000, v[13:14], v[7:8]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[13:14], v[17:18], v[35:36]
	v_fma_f64 v[7:8], 0x3fc00000, v[13:14], v[7:8]
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[7:8], v[37:38], v[7:8]
.LBB0_10:                               ;   in Loop: Header=BB0_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s14
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s14, s0
	s_cbranch_execz .LBB0_12
; %bb.11:                               ;   in Loop: Header=BB0_4 Depth=1
	ds_load_2addr_b64 v[31:34], v25 offset0:1 offset1:32
	ds_load_2addr_b64 v[35:38], v27 offset1:1
	ds_load_b64 v[5:6], v26
	s_waitcnt lgkmcnt(1)
	v_fma_f64 v[13:14], v[37:38], -2.0, v[33:34]
	v_fma_f64 v[17:18], v[37:38], -2.0, v[7:8]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[5:6], v[13:14], v[5:6]
	v_add_f64 v[13:14], v[15:16], v[17:18]
	v_fma_f64 v[15:16], v[37:38], -2.0, v[31:32]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ldexp_f64 v[5:6], v[5:6], -3
	v_fma_f64 v[5:6], 0x3fc00000, v[13:14], v[5:6]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[13:14], v[15:16], v[35:36]
	v_fma_f64 v[5:6], 0x3fc00000, v[13:14], v[5:6]
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[5:6], v[37:38], v[5:6]
.LBB0_12:                               ;   in Loop: Header=BB0_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s14
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s14, s1
	s_cbranch_execz .LBB0_14
; %bb.13:                               ;   in Loop: Header=BB0_4 Depth=1
	ds_load_2addr_b64 v[13:16], v28 offset0:1 offset1:32
	ds_load_2addr_b64 v[31:34], v30 offset1:1
	ds_load_b64 v[17:18], v29
	s_add_i32 s15, s13, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_max_i32 s15, s15, 3
	s_add_i32 s15, s15, -3
	s_waitcnt lgkmcnt(1)
	v_fma_f64 v[15:16], v[33:34], -2.0, v[15:16]
	v_fma_f64 v[35:36], v[33:34], -2.0, v[5:6]
	v_fma_f64 v[13:14], v[33:34], -2.0, v[13:14]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[15:16], v[15:16], v[17:18]
	v_add_f64 v[11:12], v[11:12], v[35:36]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[13:14], v[13:14], v[31:32]
	v_ldexp_f64 v[15:16], v[15:16], -3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[11:12], 0x3fc00000, v[11:12], v[15:16]
	v_fma_f64 v[11:12], 0x3fc00000, v[13:14], v[11:12]
	v_mad_u64_u32 v[13:14], null, s15, s5, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[14:15], null, v13, s6, v[0:1]
	v_ashrrev_i32_e32 v15, 31, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[13:14], 3, v[14:15]
	v_add_co_u32 v13, vcc_lo, s10, v13
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v14, vcc_lo, s11, v14, vcc_lo
	v_add_f64 v[11:12], v[33:34], v[11:12]
	global_store_b64 v[13:14], v[11:12], off
.LBB0_14:                               ;   in Loop: Header=BB0_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s14
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	ds_load_b64 v[13:14], v20
	ds_load_b64 v[17:18], v19
	ds_load_b64 v[15:16], v25
	ds_load_b64 v[11:12], v28
	v_add_nc_u32_e32 v2, s2, v2
	s_add_i32 s13, s13, 1
	ds_store_b64 v20, v[3:4]
	ds_store_b64 v19, v[9:10]
	ds_store_b64 v25, v[7:8]
	ds_store_b64 v28, v[5:6]
	s_cmp_eq_u32 s4, s13
	s_cbranch_scc0 .LBB0_4
.LBB0_15:                               ; %._crit_edge
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z4heatPdS_S_S_S_iii
		.amdhsa_group_segment_fixed_size 32768
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 312
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 41
		.amdhsa_next_free_sgpr 20
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z4heatPdS_S_S_S_iii, .Lfunc_end0-_Z4heatPdS_S_S_S_iii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1548
; NumSgprs: 22
; NumVgprs: 41
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 32768 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 5
; NumSGPRsForWavesPerEU: 22
; NumVGPRsForWavesPerEU: 41
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .actual_access:  read_only
        .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .actual_access:  read_only
        .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .actual_access:  read_only
        .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .actual_access:  read_only
        .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .actual_access:  write_only
        .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .offset:         40
        .size:           4
        .value_kind:     by_value
      - .offset:         44
        .size:           4
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     by_value
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         60
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         64
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         68
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         70
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         72
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         74
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         76
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         78
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         112
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         120
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 32768
    .kernarg_segment_align: 8
    .kernarg_segment_size: 312
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z4heatPdS_S_S_S_iii
    .private_segment_fixed_size: 0
    .sgpr_count:     22
    .sgpr_spill_count: 0
    .symbol:         _Z4heatPdS_S_S_S_iii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     41
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
