#include <iostream>
#include <cstring>
#include <fstream>
#include <sstream>
#include <string>
#include <vector>
#include <algorithm>
#include <unistd.h>


// NOTE: Need to compile in C++11 mode, add -std=c++11
// These should eventually be specifiable from R
#define TAU 1
#define V_THRESH 1.5
#define THREADS_PER_BLOCK 512


// Integrated Postsynaptic Kernel
__host__ __device__
double ipostkern(double dt) {
    if (dt < 0) {
        return(0);
    }
    return(TAU * (1 - exp(-dt / TAU)));
}

// Postsynaptic Kernel
__host__ __device__
double postkern(double dt) {
    if (dt < 0) {
        return(0);
    }
    return(exp(-dt / TAU));
}

// Postsynaptic Kernel
__host__ __device__
double dpostkern(double dt) {
    if (dt < 0) {
        return(0);
    }
    return((-1.0) / TAU * exp(-dt / TAU));
}

// Integrated refractory kernel.
__host__ __device__
double iprekern(double dt) {
    if (dt < 0) {
        return(0);
    }
    return(-V_THRESH);
}

// The inner product function, uses the standard R^n inner product.
__host__ __device__
double inner_prod(double *x, double *y, int n) {
    double sum = 0;
    for (int i = 0; i < n; i++) {
        sum += x[i] * y[i];
    }   
    return(sum);
}

__global__
void par_c_main_loop(double ***ALPHA, double ***Fcal, int **f_count, double ***Ws, int* net_shape, int n_layers, 
        int t_steps, double t_eps, int l, double ****GAMMA, double ****GAMMAd, const bool copy_gamma) {
    double t;
    int index = blockIdx.x * blockDim.x + threadIdx.x;
    int stride = blockDim.x * gridDim.x;
    for (int n = index; n < net_shape[l]; n += stride) {
        t = 0;
        for (int ti = 0; ti < t_steps; ti++) {
            // Calculate total postsynaptic contribution 
            int n_f = f_count[l][n];
            double psc = 0;
            for (int tfi = 0; tfi < n_f; tfi++) {
                double tf = Fcal[l][n][tfi];
                psc += ipostkern(t - tf);
            }
            ALPHA[l][ti][n] = psc;

            if (l > 0) {
                // Update refractory contribution
                n_f = f_count[l][n];
                double refr = 0;
                for (int tfi = 0; tfi < n_f; tfi++) {
                    double tf = Fcal[l][n][tfi];
                    refr += iprekern(t - tf);
                }

                // Update potential
                double V_n = inner_prod(Ws[l-1][n], ALPHA[l-1][ti], net_shape[l-1]) + refr;
                //printf("l = %d, n = %d, ti = %d", l, n, ti);
                //printf("Vsl = %d, n = %d, ti = %d", l, n, ti);

                // Check for firing neurons
                if (V_n > V_THRESH) {
                    // If an output fire, record the neural state
                    if (copy_gamma && l == n_layers-1) {
                        for (int l1 = 0; l1 < n_layers; l1++) {
                            for (int h = 0; h < net_shape[l1]; h++) {
                                GAMMA[n][f_count[l][n]][l1][h] = 0;
                                GAMMAd[n][f_count[l][n]][l1][h] = 0;
                                for (int ti = 0; ti < f_count[l1][h]; ti++) {
                                    double tf = Fcal[l1][h][ti];
                                    GAMMA[n][f_count[l][n]][l1][h] += postkern(t + t_eps - tf);
                                    GAMMAd[n][f_count[l][n]][l1][h] += dpostkern(t + t_eps - tf);
                                }
                            }
                        }
                    }
                    Fcal[l][n][f_count[l][n]] = t + t_eps;
                    f_count[l][n]++;
                }
            }
            t += t_eps;
        }
    }
}


// The main simulation, using armadillo for matrix multiplication, and organized in such a way that we solve a sequence embarassingly parallelizable problems.
double **par_sim_body_c(int *net_shape, const int n_layers,
        double **Fin, int *f_count_in, long long int **f_max, double ***Ws,
        int** f_count, const int t_steps, const double t_eps, double ****GAMMA, double ****GAMMAd, const int debug, const bool copy_gamma) {

    // Get the layer with the most neurons
    int max_neur = 0;
    for (int l = 0; l < n_layers; l++) {
        if (max_neur < net_shape[l]) {
            max_neur = net_shape[l];
        }
    }

    // ALPHA stores integrated postsynaptic potential in column major order.
    // OMEGA stores integrated refractory contribution in row major order.
    //double ***ALPHA = (double ***)calloc(n_layers, sizeof(double**));
    //double ***OMEGA = (double ***)calloc(n_layers-1, sizeof(double**));
    double ***ALPHA, ***OMEGA;
    cudaMallocManaged(&ALPHA, n_layers * sizeof(double**));
    cudaMallocManaged(&OMEGA, (n_layers-1) * sizeof(double**));
    for (int i = 0; i < n_layers; i++) {
        double **ALPHAi;
        cudaMallocManaged(&ALPHAi, t_steps * sizeof(double*));
        ALPHA[i] = ALPHAi;
        //ALPHA[i] = (double **) calloc(t_steps, sizeof(double*));
        for (int j = 0; j < t_steps; j++) {
            double *ALPHAij;
            cudaMallocManaged(&ALPHAij, net_shape[i] * sizeof(double));
            ALPHA[i][j] = ALPHAij;
            //ALPHA[i][j] = (double *) calloc(net_shape[i], sizeof(double));
        }
        if (i > 0) {
            double **OMEGAi;
            cudaMallocManaged(&OMEGAi, net_shape[i] * sizeof(double*));
            OMEGA[i-1] = OMEGAi;
            //OMEGA[i-1] = (double **) calloc(net_shape[i], sizeof(double*));
            for (int j = 0; j < net_shape[i]; j++) {
                double *OMEGAij;
                cudaMallocManaged(&OMEGAij, t_steps * sizeof(double));
                OMEGA[i-1][j] = OMEGAij;
                //OMEGA[i-1][j] = (double *) calloc(t_steps, sizeof(double));
            }
        }
    }

    if (debug >= 1) 
        printf("After ALPHA\n");

    // Storage for firing times
    //double ***u_Fcal = (double ***)calloc(n_layers, sizeof(double**));
    double ***u_Fcal;
    cudaMallocManaged(&u_Fcal, n_layers * sizeof(double**));

    // Copy input spike times to unified memory.
    double **u_Fin;
    cudaMallocManaged(&u_Fin, net_shape[0] * sizeof(double*));
    for (int n = 0; n < net_shape[0]; n++) {
        double *u_Finn;
        cudaMallocManaged(&u_Finn, f_count_in[n] * sizeof(double));
        cudaMemcpy(u_Finn, Fin[n], f_count_in[n] * sizeof(double), cudaMemcpyDefault);
        u_Fin[n] = u_Finn;
    }

    if (debug >= 1) 
        printf("After inputs \n");

    //int **myarr = (int **)malloc(2*sizeof(int *));
    //myarr[0] = (int **)malloc(2*sizeof(int));
    //myarr[1] = (int **)malloc(2*sizeof(int));
    //myarr[0][0] = 0;
    //myarr[0][1] = 1;
    //myarr[1][0] = 2;
    //myarr[1][1] = 3;

    //int **d_myarr;
    //cudaMallocManaged(&d_myarr, 2*sizeof(int *));
    //cudaMemcpy(d_myarr, myarr, 2*sizeof(int *), cudaMemcpyDefault);

    int **u_f_count;
    cudaMallocManaged(&u_f_count, n_layers * sizeof(int *));

    int *u_f_count_in;
    cudaMallocManaged(&u_f_count_in, net_shape[0] * sizeof(int));
    cudaMemcpy(u_f_count_in, f_count_in, net_shape[0] * sizeof(int), cudaMemcpyDefault);

    //f_count[0] = u_f_count_in;
    cudaMemcpy(&u_f_count[0], &u_f_count_in, sizeof(int *), cudaMemcpyDefault);
    u_Fcal[0] = u_Fin;
    for (int l = 0; l < n_layers-1; l++) {
        //double **Fi = (double **) calloc(net_shape[l+1], sizeof(double *));
        double **Fi;
        cudaMallocManaged(&Fi, net_shape[l+1] * sizeof(double *));
        u_Fcal[l+1] = Fi;


        //double **Fi = (double **) calloc(net_shape[l+1], sizeof(double *));
        int *f_countl;
        cudaMallocManaged(&f_countl, net_shape[l+1] * sizeof(int));
        cudaMemcpy(&u_f_count[l+1], &f_countl, sizeof(int *), cudaMemcpyDefault);
        for (int n = 0; n < net_shape[l+1]; n++) {
            // Init fire counts at 0.
            u_f_count[l+1][n] = 0;

            double *Fln;
            //printf("Number A\n");
            //printf("%d\n", f_max[l+1][n]);
            //printf("Number Z\n");
            cudaMallocManaged(&Fln, f_max[l+1][n] * sizeof(double));
            //printf("Number B\n");
            Fi[n] = Fln;
            //printf("Number C\n");
            // Initialize storeage to -1, so any negative firing time means did not fire.
            for (int f = 0; f < f_max[l+1][n]; f++) {
                Fi[n][f] = -1;
            }
        }
    }

    if (debug >= 1) 
        printf("After Fi copy\n");

    //// Convert Connection weights to a C array
    //// Ws[i] is the ith layer, Ws[i][j] is the jth row of layer i,
    //// Ws[i][j][k] is the j,k element of layer i (row major ordering).
    //double ***Ws_c = (double***)calloc(net_size-1, sizeof(double**));
    //for (int l = 0; l < net_size-1; l++) {
    //    Ws_c[l] = (double**)calloc(net_shape[l], sizeof(double*));
    //    for (int n = 0; n < net_shape[l]; n++) {
    //        Ws_c[l][n] = Ws_in + wlo[l] + net_shape[l+1] * n;
    //    }
    //}


    // Do GAMMA(d)
    // d_GAMMA[on][fi][l]][[h] Gives the instantaneous postsynaptic current of neuron h of layer l to firing time fi of output neuron on.
    double ****d_GAMMA, ****d_GAMMAd;
    if (copy_gamma) {
        cudaMallocManaged(&d_GAMMA, (n_layers-1) * sizeof(double***));
        cudaMallocManaged(&d_GAMMAd, (n_layers-1) * sizeof(double***));
        for (int on = 0; on < net_shape[n_layers-1]; on++) {
            cudaMallocManaged(&d_GAMMA[on], f_max[n_layers-1][on] * sizeof(double **));
            cudaMallocManaged(&d_GAMMAd[on], f_max[n_layers-1][on] * sizeof(double **));
            for (int fi = 0; fi < f_max[n_layers-1][on]; fi++) {
                cudaMallocManaged(&d_GAMMA[on][fi], n_layers * sizeof(double*));
                cudaMallocManaged(&d_GAMMAd[on][fi], n_layers * sizeof(double*));
                for (int l = 0; l < n_layers; l++) {
                    cudaMallocManaged(&d_GAMMA[on][fi][l], net_shape[l] * sizeof(double));
                    cudaMallocManaged(&d_GAMMAd[on][fi][l], net_shape[l] * sizeof(double));
                    for (int h = 0; h < net_shape[l]; h++) {
                        d_GAMMA[on][fi][l][h] = -1;
                        d_GAMMAd[on][fi][l][h] = -1;
                    }
                }
            }
        }
        if (debug >= 1) 
            printf("Initted GAMMA storage \n");
    }


    // Copy weights to unified memory
    double ***u_Ws;
    cudaMallocManaged(&u_Ws, (n_layers-1) * sizeof(double**));
    for (int l = 0; l < n_layers-1; l++) {
        double **u_Wsl;
        cudaMallocManaged(&u_Wsl, (net_shape[l+1]) * sizeof(double*));
        u_Ws[l] = u_Wsl;
        for (int n = 0; n < net_shape[l+1]; n++) {
            double *u_Wsln;
            cudaMallocManaged(&u_Wsln, net_shape[l] * sizeof(double));
            cudaMemcpy(u_Wsln, Ws[l][n], net_shape[l] * sizeof(double), cudaMemcpyDefault);
            u_Ws[l][n] = u_Wsln;
        }
    }

    if (debug >= 1) 
        printf("After Weights copy\n");

    // Copy network shape to unified memory
    int *u_net_shape;
    cudaMallocManaged(&u_net_shape, n_layers * sizeof(int));
    cudaMemcpy(u_net_shape, net_shape, n_layers * sizeof(int), cudaMemcpyDefault);

    // Run actual inference
    //TODO: Should just be + 1
    int n_blocks = max_neur / THREADS_PER_BLOCK + 1;

    // Main Loop
    for (int l = 0; l < n_layers; l++) {
        if (debug >= 1) 
            printf(" Solving Layer %d...\n", l);

        par_c_main_loop<<<n_blocks, THREADS_PER_BLOCK>>>(ALPHA, u_Fcal, u_f_count, u_Ws, u_net_shape, n_layers, 
                t_steps, t_eps, l, d_GAMMA, d_GAMMAd, copy_gamma);

        cudaDeviceSynchronize();
    }

    if (debug >= 1) 
        printf("After main loop\n");

    // Clean up
    for (int i = 0; i < n_layers; i++) {
        for (int j = 0; j < t_steps; j++) {
            cudaFree(ALPHA[i][j]);
        }
        cudaFree(ALPHA[i]);
        if (i > 0) {
            for (int j = 0; j < net_shape[i]; j++) {
                cudaFree(OMEGA[i-1][j]);
            }
            cudaFree(OMEGA[i-1]);
        }
    }
    cudaFree(ALPHA);
    cudaFree(OMEGA);

    if (debug >= 1) 
        printf("After Free\n");

    // Copy Fcal to host memory
    //double ***Fcal = (double ***)malloc(n_layers * sizeof(double **));
    //for (int l = 0; l < n_layers; l++) {
    //    Fcal[l] = (double **)malloc(net_shape[l] * sizeof(double *));
    //    for (int n = 0; n < net_shape[l]; n++) {
    //        Fcal[l][n] = (double *)malloc(f_max[l][n] * sizeof(double));
    //        cudaMemcpy(Fcal[l][n], u_Fcal[l][n], f_max[l][n] * sizeof(double), cudaMemcpyDefault);
    //    }
    //}
    // Copy output spikes to host memory

    double **Fout = (double **)malloc(net_shape[n_layers-1]*sizeof(double*));
    for (int n = 0; n < net_shape[n_layers-1]; n++) {
        Fout[n] = (double *)malloc(f_max[n_layers-1][n] * sizeof(double));
        cudaMemcpy(Fout[n], u_Fcal[n_layers-1][n], f_max[n_layers-1][n] * sizeof(double), cudaMemcpyDefault);
    }

    // Copy f_count to host memory
    for (int l = 0; l < n_layers; l++) {
        f_count[l] = (int *)calloc(net_shape[l], sizeof(int));
        cudaMemcpy(f_count[l], u_f_count[l], net_shape[l] * sizeof(int), cudaMemcpyDefault);
    }

    if (debug >= 1) 
        printf("After output spike spike/f_count\n");

    // Copy to host memory
    // d_GAMMA[on][fi][l]][[h] Gives the instantaneous postsynaptic current of neuron h of layer l to firing time fi of output neuron on.
    //GAMMA = (double****)malloc((n_layers-1) * sizeof(double***));
    //GAMMAd = (double****)malloc((n_layers-1) * sizeof(double***));
    if (copy_gamma) {
        for (int on = 0; on < net_shape[n_layers-1]; on++) {
            GAMMA[on] = (double***)malloc(f_max[n_layers-1][on] * sizeof(double**));
            GAMMAd[on] = (double***)malloc(f_max[n_layers-1][on] * sizeof(double**));
            for (int fi = 0; fi < f_max[n_layers-1][on]; fi++) {
                GAMMA[on][fi] = (double**)malloc(n_layers * sizeof(double*));
                GAMMAd[on][fi] = (double**)malloc(n_layers * sizeof(double*));
                for (int l = 0; l < n_layers; l++) {
                    GAMMA[on][fi][l] = (double*)malloc(net_shape[l] * sizeof(double));
                    GAMMAd[on][fi][l] = (double*)malloc(net_shape[l] * sizeof(double));
                    cudaMemcpy(GAMMA[on][fi][l], d_GAMMA[on][fi][l], net_shape[l] * sizeof(double), cudaMemcpyDefault);
                    cudaMemcpy(GAMMAd[on][fi][l], d_GAMMAd[on][fi][l], net_shape[l] * sizeof(double), cudaMemcpyDefault);
                }
            }
        }
        if (debug >= 1) 
            printf("After GAMMA copy\n");
    }

    //TODO: copy f_count

    return(Fout);
}

	.file	"tmpxft_00285145_00000000-6_srm0.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4461:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE4461:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.type	_Z17cudaMallocManagedIPPdE9cudaErrorPPT_mj.constprop.0.isra.0, @function
_Z17cudaMallocManagedIPPdE9cudaErrorPPT_mj.constprop.0.isra.0:
.LFB5130:
	.cfi_startproc
	movl	$1, %edx
	jmp	cudaMallocManaged@PLT
	.cfi_endproc
.LFE5130:
	.size	_Z17cudaMallocManagedIPPdE9cudaErrorPPT_mj.constprop.0.isra.0, .-_Z17cudaMallocManagedIPPdE9cudaErrorPPT_mj.constprop.0.isra.0
	.globl	_Z9ipostkernd
	.type	_Z9ipostkernd, @function
_Z9ipostkernd:
.LFB4453:
	.cfi_startproc
	endbr64
	xorps	%xmm1, %xmm1
	comisd	%xmm0, %xmm1
	ja	.L5
	pushq	%rax
	.cfi_def_cfa_offset 16
	xorps	.LC1(%rip), %xmm0
	call	exp@PLT
	movaps	%xmm0, %xmm1
	movsd	.LC2(%rip), %xmm0
	popq	%rdx
	.cfi_def_cfa_offset 8
	subsd	%xmm1, %xmm0
	ret
.L5:
	xorps	%xmm0, %xmm0
	ret
	.cfi_endproc
.LFE4453:
	.size	_Z9ipostkernd, .-_Z9ipostkernd
	.globl	_Z8postkernd
	.type	_Z8postkernd, @function
_Z8postkernd:
.LFB4454:
	.cfi_startproc
	endbr64
	xorps	%xmm1, %xmm1
	comisd	%xmm0, %xmm1
	ja	.L12
	xorps	.LC1(%rip), %xmm0
	jmp	exp@PLT
.L12:
	xorps	%xmm0, %xmm0
	ret
	.cfi_endproc
.LFE4454:
	.size	_Z8postkernd, .-_Z8postkernd
	.globl	_Z9dpostkernd
	.type	_Z9dpostkernd, @function
_Z9dpostkernd:
.LFB4455:
	.cfi_startproc
	endbr64
	xorps	%xmm1, %xmm1
	comisd	%xmm0, %xmm1
	ja	.L15
	pushq	%rax
	.cfi_def_cfa_offset 16
	movq	.LC1(%rip), %xmm1
	xorps	%xmm1, %xmm0
	call	exp@PLT
	movq	.LC1(%rip), %xmm1
	popq	%rdx
	.cfi_def_cfa_offset 8
	xorps	%xmm1, %xmm0
	ret
.L15:
	xorps	%xmm0, %xmm0
	ret
	.cfi_endproc
.LFE4455:
	.size	_Z9dpostkernd, .-_Z9dpostkernd
	.globl	_Z8iprekernd
	.type	_Z8iprekernd, @function
_Z8iprekernd:
.LFB4456:
	.cfi_startproc
	endbr64
	xorps	%xmm1, %xmm1
	comisd	%xmm0, %xmm1
	ja	.L22
	movsd	.LC3(%rip), %xmm0
	ret
.L22:
	xorps	%xmm0, %xmm0
	ret
	.cfi_endproc
.LFE4456:
	.size	_Z8iprekernd, .-_Z8iprekernd
	.globl	_Z10inner_prodPdS_i
	.type	_Z10inner_prodPdS_i, @function
_Z10inner_prodPdS_i:
.LFB4457:
	.cfi_startproc
	endbr64
	xorl	%eax, %eax
	xorps	%xmm0, %xmm0
.L24:
	cmpl	%eax, %edx
	jle	.L26
	movsd	(%rdi,%rax,8), %xmm1
	mulsd	(%rsi,%rax,8), %xmm1
	incq	%rax
	addsd	%xmm1, %xmm0
	jmp	.L24
.L26:
	ret
	.cfi_endproc
.LFE4457:
	.size	_Z10inner_prodPdS_i, .-_Z10inner_prodPdS_i
	.globl	_Z61__device_stub__Z15par_c_main_loopPPPdS1_PPiS1_S2_iidiPS1_S4_bPPPdS1_PPiS1_S2_iidiPS1_S4_b
	.type	_Z61__device_stub__Z15par_c_main_loopPPPdS1_PPiS1_S2_iidiPS1_S4_bPPPdS1_PPiS1_S2_iidiPS1_S4_b, @function
_Z61__device_stub__Z15par_c_main_loopPPPdS1_PPiS1_S2_iidiPS1_S4_bPPPdS1_PPiS1_S2_iidiPS1_S4_b:
.LFB4483:
	.cfi_startproc
	endbr64
	subq	$264, %rsp
	.cfi_def_cfa_offset 272
	movq	288(%rsp), %rax
	movq	%rdi, 72(%rsp)
	leaq	104(%rsp), %rdi
	movq	%rsi, 64(%rsp)
	leaq	116(%rsp), %rsi
	movq	%rax, 16(%rsp)
	movq	296(%rsp), %rax
	movq	%rdx, 56(%rsp)
	leaq	88(%rsp), %rdx
	movq	%rax, 8(%rsp)
	movl	304(%rsp), %eax
	movq	%rcx, 48(%rsp)
	leaq	96(%rsp), %rcx
	movq	%r8, 40(%rsp)
	movl	%r9d, 36(%rsp)
	movb	%al, 32(%rsp)
	movsd	%xmm0, 24(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 248(%rsp)
	xorl	%eax, %eax
	leaq	72(%rsp), %rax
	movl	$1, 112(%rsp)
	movq	%rax, 152(%rsp)
	leaq	64(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	56(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	36(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	272(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 208(%rsp)
	leaq	280(%rsp), %rax
	movq	%rax, 216(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 224(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 232(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 240(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 104(%rsp)
	movq	%rax, 116(%rsp)
	movl	$1, 124(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L27
	pushq	96(%rsp)
	.cfi_def_cfa_offset 280
	leaq	_Z15par_c_main_loopPPPdS1_PPiS1_S2_iidiPS1_S4_b(%rip), %rdi
	pushq	96(%rsp)
	.cfi_def_cfa_offset 288
	movq	132(%rsp), %rcx
	movl	140(%rsp), %r8d
	movq	120(%rsp), %rsi
	movl	128(%rsp), %edx
	leaq	168(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 280
	popq	%rdx
	.cfi_def_cfa_offset 272
.L27:
	movq	248(%rsp), %rax
	subq	%fs:40, %rax
	je	.L29
	call	__stack_chk_fail@PLT
.L29:
	addq	$264, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4483:
	.size	_Z61__device_stub__Z15par_c_main_loopPPPdS1_PPiS1_S2_iidiPS1_S4_bPPPdS1_PPiS1_S2_iidiPS1_S4_b, .-_Z61__device_stub__Z15par_c_main_loopPPPdS1_PPiS1_S2_iidiPS1_S4_bPPPdS1_PPiS1_S2_iidiPS1_S4_b
	.globl	_Z15par_c_main_loopPPPdS1_PPiS1_S2_iidiPS1_S4_b
	.type	_Z15par_c_main_loopPPPdS1_PPiS1_S2_iidiPS1_S4_b, @function
_Z15par_c_main_loopPPPdS1_PPiS1_S2_iidiPS1_S4_b:
.LFB4484:
	.cfi_startproc
	endbr64
	movzbl	40(%rsp), %eax
	movl	%eax, 40(%rsp)
	jmp	_Z61__device_stub__Z15par_c_main_loopPPPdS1_PPiS1_S2_iidiPS1_S4_bPPPdS1_PPiS1_S2_iidiPS1_S4_b
	.cfi_endproc
.LFE4484:
	.size	_Z15par_c_main_loopPPPdS1_PPiS1_S2_iidiPS1_S4_b, .-_Z15par_c_main_loopPPPdS1_PPiS1_S2_iidiPS1_S4_b
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC4:
	.string	"After ALPHA\n"
.LC5:
	.string	"After inputs \n"
.LC7:
	.string	"After Fi copy\n"
.LC8:
	.string	"Initted GAMMA storage \n"
.LC9:
	.string	"After Weights copy\n"
.LC10:
	.string	" Solving Layer %d...\n"
.LC11:
	.string	"After main loop\n"
.LC12:
	.string	"After Free\n"
.LC13:
	.string	"After output spike spike/f_count\n"
.LC14:
	.string	"After GAMMA copy\n"
	.text
	.globl	_Z14par_sim_body_cPiiPPdS_PPxPS1_PS_idPS4_S6_ib
	.type	_Z14par_sim_body_cPiiPPdS_PPxPS1_PS_idPS4_S6_ib, @function
_Z14par_sim_body_cPiiPPdS_PPxPS1_PS_idPS4_S6_ib:
.LFB4458:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movq	%rdx, %r12
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movq	%rcx, %rbp
	xorl	%ecx, %ecx
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movq	%rdi, %rbx
	subq	$280, %rsp
	.cfi_def_cfa_offset 336
	movq	336(%rsp), %rax
	movl	%esi, 112(%rsp)
	movq	%r8, 16(%rsp)
	movl	368(%rsp), %r15d
	movq	%rax, 96(%rsp)
	movq	352(%rsp), %rax
	movq	%r9, 88(%rsp)
	movq	%rax, 64(%rsp)
	movq	360(%rsp), %rax
	movsd	%xmm0, 104(%rsp)
	movq	%rax, 48(%rsp)
	movl	376(%rsp), %eax
	movl	%eax, 72(%rsp)
	movb	72(%rsp), %al
	movb	%al, 119(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 264(%rsp)
	xorl	%eax, %eax
	movl	%ecx, 32(%rsp)
.L33:
	cmpl	%eax, 112(%rsp)
	jle	.L104
	movl	(%rbx,%rax,4), %edx
	cmpl	%edx, 32(%rsp)
	cmovge	32(%rsp), %edx
	incq	%rax
	movl	%edx, 32(%rsp)
	jmp	.L33
.L104:
	movslq	112(%rsp), %rax
	leaq	152(%rsp), %rdi
	xorl	%r14d, %r14d
	movq	%rax, 40(%rsp)
	salq	$3, %rax
	movq	%rax, %rsi
	movq	%rax, 8(%rsp)
	call	_Z17cudaMallocManagedIPPdE9cudaErrorPPT_mj.constprop.0.isra.0
	movl	112(%rsp), %eax
	leaq	160(%rsp), %rdi
	decl	%eax
	movl	%eax, 80(%rsp)
	movq	8(%rsp), %rax
	subq	$8, %rax
	movq	%rax, %rsi
	movq	%rax, 24(%rsp)
	call	_Z17cudaMallocManagedIPPdE9cudaErrorPPT_mj.constprop.0.isra.0
	movslq	344(%rsp), %rax
	salq	$3, %rax
	movq	%rax, 56(%rsp)
	leaq	224(%rsp), %rax
	movq	%rax, 128(%rsp)
.L35:
	cmpl	%r14d, 112(%rsp)
	jle	.L105
	movq	56(%rsp), %rsi
	movq	128(%rsp), %rdi
	leaq	0(,%r14,8), %r13
	call	_Z17cudaMallocManagedIPPdE9cudaErrorPPT_mj.constprop.0.isra.0
	leaq	248(%rsp), %rax
	movq	152(%rsp), %rdx
	movq	224(%rsp), %rsi
	movq	%rax, 120(%rsp)
	movq	%rsi, (%rdx,%r14,8)
	xorl	%edx, %edx
.L36:
	cmpl	%edx, 344(%rsp)
	jle	.L106
	movslq	(%rbx,%r14,4), %rsi
	movq	120(%rsp), %rdi
	movq	%rdx, 136(%rsp)
	salq	$3, %rsi
	call	_Z17cudaMallocManagedIPPdE9cudaErrorPPT_mj.constprop.0.isra.0
	movq	152(%rsp), %rsi
	movq	136(%rsp), %rdx
	movq	248(%rsp), %rdi
	movq	(%rsi,%r13), %rsi
	movq	%rdi, (%rsi,%rdx,8)
	incq	%rdx
	jmp	.L36
.L106:
	testq	%r14, %r14
	je	.L38
	movslq	(%rbx,%r14,4), %rsi
	leaq	232(%rsp), %rdi
	salq	$3, %rsi
	call	_Z17cudaMallocManagedIPPdE9cudaErrorPPT_mj.constprop.0.isra.0
	leaq	248(%rsp), %rax
	leaq	-8(%r13), %r8
	movq	232(%rsp), %rsi
	movq	160(%rsp), %rdx
	movq	%rax, 120(%rsp)
	movq	%rsi, -8(%rdx,%r13)
	xorl	%r13d, %r13d
.L39:
	cmpl	%r13d, (%rbx,%r14,4)
	jle	.L38
	movq	56(%rsp), %rsi
	movq	120(%rsp), %rdi
	movq	%r8, 136(%rsp)
	call	_Z17cudaMallocManagedIPPdE9cudaErrorPPT_mj.constprop.0.isra.0
	movq	160(%rsp), %rcx
	movq	136(%rsp), %r8
	movq	248(%rsp), %rsi
	movq	(%rcx,%r8), %rcx
	movq	%rsi, (%rcx,%r13,8)
	incq	%r13
	jmp	.L39
.L38:
	incq	%r14
	jmp	.L35
.L105:
	testl	%r15d, %r15d
	jle	.L42
	leaq	.LC4(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
.L42:
	movq	8(%rsp), %rsi
	leaq	168(%rsp), %rdi
	xorl	%r14d, %r14d
	leaq	248(%rsp), %r13
	call	_Z17cudaMallocManagedIPPdE9cudaErrorPPT_mj.constprop.0.isra.0
	movslq	(%rbx), %rsi
	leaq	176(%rsp), %rdi
	salq	$3, %rsi
	call	_Z17cudaMallocManagedIPPdE9cudaErrorPPT_mj.constprop.0.isra.0
.L43:
	cmpl	%r14d, (%rbx)
	jle	.L107
	movslq	0(%rbp,%r14,4), %rsi
	movq	%r13, %rdi
	salq	$3, %rsi
	call	_Z17cudaMallocManagedIPPdE9cudaErrorPPT_mj.constprop.0.isra.0
	movslq	0(%rbp,%r14,4), %rdx
	movq	(%r12,%r14,8), %rsi
	movl	$4, %ecx
	movq	248(%rsp), %rdi
	salq	$3, %rdx
	call	cudaMemcpy@PLT
	movq	248(%rsp), %rdx
	movq	176(%rsp), %rax
	movq	%rdx, (%rax,%r14,8)
	incq	%r14
	jmp	.L43
.L107:
	testl	%r15d, %r15d
	jle	.L45
	leaq	.LC5(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
.L45:
	movq	8(%rsp), %rsi
	leaq	184(%rsp), %rdi
	leaq	192(%rsp), %r12
	movl	$1, %r13d
	call	_Z17cudaMallocManagedIPPdE9cudaErrorPPT_mj.constprop.0.isra.0
	movslq	(%rbx), %rsi
	movq	%r12, %rdi
	salq	$2, %rsi
	call	_Z17cudaMallocManagedIPPdE9cudaErrorPPT_mj.constprop.0.isra.0
	movslq	(%rbx), %rdx
	movl	$4, %ecx
	movq	%rbp, %rsi
	movq	192(%rsp), %rdi
	salq	$2, %rdx
	call	cudaMemcpy@PLT
	movq	184(%rsp), %rdi
	movl	$8, %edx
	movq	%r12, %rsi
	movl	$4, %ecx
	call	cudaMemcpy@PLT
	movq	176(%rsp), %rdx
	movq	168(%rsp), %rax
	movq	%rdx, (%rax)
.L46:
	leal	-1(%r13), %eax
	cmpl	%eax, 80(%rsp)
	jle	.L108
	movslq	(%rbx,%r13,4), %rsi
	leaq	224(%rsp), %rdi
	leaq	232(%rsp), %r12
	leaq	0(,%r13,8), %rbp
	salq	$3, %rsi
	call	_Z17cudaMallocManagedIPPdE9cudaErrorPPT_mj.constprop.0.isra.0
	movq	224(%rsp), %rdx
	movslq	(%rbx,%r13,4), %rsi
	movq	%r12, %rdi
	movq	168(%rsp), %rax
	salq	$2, %rsi
	movq	%rdx, (%rax,%r13,8)
	call	_Z17cudaMallocManagedIPPdE9cudaErrorPPT_mj.constprop.0.isra.0
	movq	184(%rsp), %rdi
	movq	%r12, %rsi
	movl	$4, %ecx
	movl	$8, %edx
	xorl	%r12d, %r12d
	addq	%rbp, %rdi
	call	cudaMemcpy@PLT
.L47:
	cmpl	%r12d, (%rbx,%r13,4)
	jle	.L109
	movq	184(%rsp), %rax
	xorl	%edx, %edx
	leaq	248(%rsp), %rdi
	movq	(%rax,%rbp), %rax
	movl	%edx, (%rax,%r12,4)
	movq	16(%rsp), %rax
	movq	(%rax,%r13,8), %rax
	movq	(%rax,%r12,8), %rsi
	salq	$3, %rsi
	call	_Z17cudaMallocManagedIPPdE9cudaErrorPPT_mj.constprop.0.isra.0
	movq	224(%rsp), %rax
	movq	248(%rsp), %rdx
	movq	%rdx, (%rax,%r12,8)
	movq	16(%rsp), %rax
	movq	(%rax,%r13,8), %rax
	movq	(%rax,%r12,8), %rcx
	xorl	%eax, %eax
.L48:
	cmpq	%rax, %rcx
	jle	.L110
	movq	.LC6(%rip), %rsi
	movq	%rsi, (%rdx,%rax,8)
	incq	%rax
	jmp	.L48
.L110:
	incq	%r12
	jmp	.L47
.L109:
	incq	%r13
	jmp	.L46
.L108:
	testl	%r15d, %r15d
	jle	.L52
	leaq	.LC7(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
.L52:
	movq	40(%rsp), %rax
	salq	$2, %rax
	cmpb	$0, 72(%rsp)
	movq	%rax, 56(%rsp)
	leaq	-4(%rbx,%rax), %rax
	movq	%rax, 40(%rsp)
	je	.L54
	movq	24(%rsp), %rsi
	leaq	200(%rsp), %rdi
	xorl	%r12d, %r12d
	call	_Z17cudaMallocManagedIPPdE9cudaErrorPPT_mj.constprop.0.isra.0
	movq	24(%rsp), %rsi
	leaq	208(%rsp), %rdi
	call	_Z17cudaMallocManagedIPPdE9cudaErrorPPT_mj.constprop.0.isra.0
.L55:
	movq	40(%rsp), %rax
	cmpl	%r12d, (%rax)
	jle	.L111
	movq	8(%rsp), %rcx
	movq	16(%rsp), %rax
	leaq	0(,%r12,8), %rbp
	movq	200(%rsp), %rdi
	leaq	-8(%rax,%rcx), %r14
	movq	(%r14), %rax
	addq	%rbp, %rdi
	movq	(%rax,%r12,8), %rsi
	salq	$3, %rsi
	call	_Z17cudaMallocManagedIPPdE9cudaErrorPPT_mj.constprop.0.isra.0
	movq	(%r14), %rax
	movq	208(%rsp), %rdi
	movq	(%rax,%r12,8), %rsi
	addq	%rbp, %rdi
	salq	$3, %rsi
	call	_Z17cudaMallocManagedIPPdE9cudaErrorPPT_mj.constprop.0.isra.0
	xorl	%ecx, %ecx
.L56:
	movq	(%r14), %rax
	cmpq	%rcx, (%rax,%rbp)
	jle	.L112
	movq	200(%rsp), %rax
	movq	8(%rsp), %rsi
	movq	%rcx, 120(%rsp)
	leaq	0(,%rcx,8), %r13
	movq	(%rax,%rbp), %rdi
	addq	%r13, %rdi
	call	_Z17cudaMallocManagedIPPdE9cudaErrorPPT_mj.constprop.0.isra.0
	movq	208(%rsp), %rax
	movq	8(%rsp), %rsi
	movq	(%rax,%rbp), %rdi
	addq	%r13, %rdi
	call	_Z17cudaMallocManagedIPPdE9cudaErrorPPT_mj.constprop.0.isra.0
	movq	120(%rsp), %rcx
	xorl	%eax, %eax
.L57:
	cmpl	%eax, 112(%rsp)
	jle	.L113
	movq	200(%rsp), %rdx
	movslq	(%rbx,%rax,4), %rsi
	leaq	0(,%rax,8), %r8
	movq	%rcx, 136(%rsp)
	movq	%r8, %rdi
	movq	%r8, 120(%rsp)
	movq	(%rdx,%rbp), %rdx
	salq	$3, %rsi
	movq	%rax, 128(%rsp)
	addq	(%rdx,%r13), %rdi
	call	_Z17cudaMallocManagedIPPdE9cudaErrorPPT_mj.constprop.0.isra.0
	movq	128(%rsp), %rax
	movq	120(%rsp), %rdi
	movq	208(%rsp), %rdx
	movslq	(%rbx,%rax,4), %rsi
	movq	(%rdx,%rbp), %rdx
	salq	$3, %rsi
	addq	(%rdx,%r13), %rdi
	call	_Z17cudaMallocManagedIPPdE9cudaErrorPPT_mj.constprop.0.isra.0
	movq	128(%rsp), %rax
	movq	120(%rsp), %r8
	xorl	%edx, %edx
	movq	200(%rsp), %rdi
	movq	208(%rsp), %r9
	movl	(%rbx,%rax,4), %esi
	movq	136(%rsp), %rcx
	addq	%rbp, %rdi
	addq	%rbp, %r9
.L58:
	cmpl	%edx, %esi
	jle	.L114
	movq	(%rdi), %r10
	movq	.LC6(%rip), %r11
	movq	(%r10,%r13), %r10
	movq	(%r10,%r8), %r10
	movq	%r11, (%r10,%rdx,8)
	movq	(%r9), %r10
	movq	(%r10,%r13), %r10
	movq	(%r10,%r8), %r10
	movq	%r11, (%r10,%rdx,8)
	incq	%rdx
	jmp	.L58
.L114:
	incq	%rax
	jmp	.L57
.L113:
	incq	%rcx
	jmp	.L56
.L112:
	incq	%r12
	jmp	.L55
.L111:
	testl	%r15d, %r15d
	jle	.L54
	leaq	.LC8(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
.L54:
	movq	24(%rsp), %rsi
	leaq	216(%rsp), %rdi
	xorl	%r13d, %r13d
	call	_Z17cudaMallocManagedIPPdE9cudaErrorPPT_mj.constprop.0.isra.0
	leaq	232(%rsp), %rax
	movq	%rax, 24(%rsp)
.L64:
	cmpl	%r13d, 80(%rsp)
	jle	.L115
	movslq	4(%rbx,%r13,4), %rsi
	movq	24(%rsp), %rdi
	xorl	%r14d, %r14d
	leaq	0(,%r13,8), %rbp
	leaq	248(%rsp), %r12
	salq	$3, %rsi
	call	_Z17cudaMallocManagedIPPdE9cudaErrorPPT_mj.constprop.0.isra.0
	movq	232(%rsp), %rdx
	movq	216(%rsp), %rax
	movq	%rdx, (%rax,%r13,8)
.L65:
	cmpl	%r14d, 4(%rbx,%r13,4)
	jle	.L116
	movslq	(%rbx,%r13,4), %rsi
	movq	%r12, %rdi
	salq	$3, %rsi
	call	_Z17cudaMallocManagedIPPdE9cudaErrorPPT_mj.constprop.0.isra.0
	movq	88(%rsp), %rax
	movslq	(%rbx,%r13,4), %rdx
	movl	$4, %ecx
	movq	248(%rsp), %rdi
	movq	(%rax,%r13,8), %rax
	salq	$3, %rdx
	movq	(%rax,%r14,8), %rsi
	call	cudaMemcpy@PLT
	movq	216(%rsp), %rax
	movq	248(%rsp), %rdx
	movq	(%rax,%rbp), %rax
	movq	%rdx, (%rax,%r14,8)
	incq	%r14
	jmp	.L65
.L116:
	incq	%r13
	jmp	.L64
.L115:
	testl	%r15d, %r15d
	jle	.L68
	leaq	.LC9(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
.L68:
	movq	56(%rsp), %rsi
	leaq	224(%rsp), %rdi
	xorl	%r12d, %r12d
	call	_Z17cudaMallocManagedIPPdE9cudaErrorPPT_mj.constprop.0.isra.0
	movq	56(%rsp), %rdx
	movl	$4, %ecx
	movq	%rbx, %rsi
	movq	224(%rsp), %rdi
	call	cudaMemcpy@PLT
	movl	32(%rsp), %eax
	movl	$512, %ecx
	movzbl	119(%rsp), %r13d
	cltd
	idivl	%ecx
	leal	1(%rax), %ebp
.L69:
	movl	112(%rsp), %eax
	cmpl	%eax, %r12d
	jge	.L117
	testl	%r15d, %r15d
	jle	.L70
	movl	%r12d, %edx
	leaq	.LC10(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
.L70:
	movl	$8388609, %edx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$1, %ecx
	movabsq	$4294967297, %rax
	salq	$9, %rdx
	movl	%ebp, 232(%rsp)
	movq	%rax, 236(%rsp)
	movq	232(%rsp), %rdi
	movl	240(%rsp), %esi
	movq	%rdx, 248(%rsp)
	movl	$1, 256(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L71
	pushq	%rax
	.cfi_def_cfa_offset 344
	pushq	%r13
	.cfi_def_cfa_offset 352
	pushq	224(%rsp)
	.cfi_def_cfa_offset 360
	pushq	224(%rsp)
	.cfi_def_cfa_offset 368
	pushq	%r12
	.cfi_def_cfa_offset 376
	movl	384(%rsp), %eax
	pushq	%rax
	.cfi_def_cfa_offset 384
	movl	160(%rsp), %r9d
	movq	272(%rsp), %r8
	movq	264(%rsp), %rcx
	movq	232(%rsp), %rdx
	movq	216(%rsp), %rsi
	movsd	152(%rsp), %xmm0
	movq	200(%rsp), %rdi
	call	_Z61__device_stub__Z15par_c_main_loopPPPdS1_PPiS1_S2_iidiPS1_S4_bPPPdS1_PPiS1_S2_iidiPS1_S4_b
	addq	$48, %rsp
	.cfi_def_cfa_offset 336
.L71:
	call	cudaDeviceSynchronize@PLT
	incl	%r12d
	jmp	.L69
.L117:
	testl	%r15d, %r15d
	jle	.L73
	leaq	.LC11(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
.L73:
	xorl	%ebp, %ebp
.L74:
	cmpl	%ebp, 112(%rsp)
	jle	.L79
	leaq	0(,%rbp,8), %r12
	xorl	%r13d, %r13d
.L80:
	movq	152(%rsp), %rax
	movq	(%rax,%r12), %rdi
	cmpl	%r13d, 344(%rsp)
	jle	.L118
	movq	(%rdi,%r13,8), %rdi
	incq	%r13
	call	cudaFree@PLT
	jmp	.L80
.L118:
	call	cudaFree@PLT
	testq	%rbp, %rbp
	je	.L76
	subq	$8, %r12
	xorl	%r13d, %r13d
.L77:
	movq	160(%rsp), %rax
	movq	(%rax,%r12), %rdi
	cmpl	%r13d, (%rbx,%rbp,4)
	jle	.L119
	movq	(%rdi,%r13,8), %rdi
	incq	%r13
	call	cudaFree@PLT
	jmp	.L77
.L119:
	call	cudaFree@PLT
.L76:
	incq	%rbp
	jmp	.L74
.L79:
	movq	152(%rsp), %rdi
	call	cudaFree@PLT
	movq	160(%rsp), %rdi
	call	cudaFree@PLT
	testl	%r15d, %r15d
	jle	.L81
	leaq	.LC12(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
.L81:
	movq	40(%rsp), %rax
	xorl	%ebp, %ebp
	movslq	(%rax), %rdi
	salq	$3, %rdi
	call	malloc@PLT
	movq	%rax, 80(%rsp)
.L82:
	movq	40(%rsp), %rax
	cmpl	%ebp, (%rax)
	jle	.L120
	movq	8(%rsp), %rcx
	movq	16(%rsp), %rax
	movq	-8(%rax,%rcx), %rax
	movq	(%rax,%rbp,8), %r12
	salq	$3, %r12
	movq	%r12, %rdi
	call	malloc@PLT
	movq	8(%rsp), %rcx
	movq	%r12, %rdx
	movq	%rax, %rdi
	movq	80(%rsp), %rax
	movq	%rdi, (%rax,%rbp,8)
	movq	168(%rsp), %rax
	movq	-8(%rax,%rcx), %rax
	movl	$4, %ecx
	movq	(%rax,%rbp,8), %rsi
	incq	%rbp
	call	cudaMemcpy@PLT
	jmp	.L82
.L120:
	xorl	%r12d, %r12d
.L84:
	cmpl	%r12d, 112(%rsp)
	jle	.L121
	movslq	(%rbx,%r12,4), %rbp
	movl	$4, %esi
	movq	%rbp, %rdi
	call	calloc@PLT
	leaq	0(,%rbp,4), %rdx
	movl	$4, %ecx
	movq	%rax, %rdi
	movq	96(%rsp), %rax
	movq	%rdi, (%rax,%r12,8)
	movq	184(%rsp), %rax
	movq	(%rax,%r12,8), %rsi
	incq	%r12
	call	cudaMemcpy@PLT
	jmp	.L84
.L121:
	testl	%r15d, %r15d
	jle	.L86
	leaq	.LC13(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
.L86:
	cmpb	$0, 72(%rsp)
	je	.L32
	movq	8(%rsp), %rax
	xorl	%r12d, %r12d
	subq	$8, %rax
	movq	%rax, 72(%rsp)
.L87:
	movq	40(%rsp), %rax
	cmpl	%r12d, (%rax)
	jle	.L122
	movq	16(%rsp), %rax
	movq	72(%rsp), %rcx
	leaq	(%rax,%rcx), %r13
	leaq	0(,%r12,8), %rax
	movq	%rax, 24(%rsp)
	movq	0(%r13), %rax
	movq	(%rax,%r12,8), %rbp
	salq	$3, %rbp
	movq	%rbp, %rdi
	call	malloc@PLT
	movq	64(%rsp), %rcx
	movq	%rbp, %rdi
	movq	%rax, (%rcx,%r12,8)
	call	malloc@PLT
	movq	48(%rsp), %rcx
	xorl	%r10d, %r10d
	movq	%rax, (%rcx,%r12,8)
.L89:
	movq	0(%r13), %rax
	movq	24(%rsp), %rcx
	cmpq	(%rax,%rcx), %r10
	jge	.L123
	movq	64(%rsp), %rax
	movq	8(%rsp), %rdi
	movq	%r10, 32(%rsp)
	leaq	0(,%r10,8), %rbp
	movq	(%rax,%r12,8), %r14
	call	malloc@PLT
	movq	8(%rsp), %rdi
	addq	%rbp, %r14
	movq	%rax, (%r14)
	movq	48(%rsp), %rax
	movq	(%rax,%r12,8), %r14
	call	malloc@PLT
	movq	32(%rsp), %r10
	addq	%rbp, %r14
	movq	%rax, (%r14)
	xorl	%r14d, %r14d
.L90:
	cmpl	%r14d, 112(%rsp)
	jle	.L124
	movslq	(%rbx,%r14,4), %rax
	leaq	0(,%r14,8), %rdx
	movq	%r10, 96(%rsp)
	movq	%rdx, %rcx
	movq	%rdx, 88(%rsp)
	salq	$3, %rax
	movq	%rax, 32(%rsp)
	movq	64(%rsp), %rax
	movq	32(%rsp), %rdi
	movq	(%rax,%r12,8), %rax
	addq	(%rax,%rbp), %rcx
	movq	%rcx, 56(%rsp)
	call	malloc@PLT
	movq	56(%rsp), %rcx
	movq	32(%rsp), %rdi
	movq	88(%rsp), %rdx
	movq	%rax, (%rcx)
	movq	48(%rsp), %rax
	movq	(%rax,%r12,8), %rax
	addq	(%rax,%rbp), %rdx
	movq	%rdx, 88(%rsp)
	call	malloc@PLT
	movq	88(%rsp), %rdx
	movq	24(%rsp), %rcx
	movq	%rax, (%rdx)
	movq	200(%rsp), %rax
	movq	32(%rsp), %rdx
	movq	(%rax,%rcx), %rax
	movl	$4, %ecx
	movq	(%rax,%rbp), %rax
	movq	(%rax,%r14,8), %rsi
	movq	56(%rsp), %rax
	movq	(%rax), %rdi
	call	cudaMemcpy@PLT
	movq	24(%rsp), %rcx
	movslq	(%rbx,%r14,4), %rdx
	movq	208(%rsp), %rax
	salq	$3, %rdx
	movq	(%rax,%rcx), %rax
	movl	$4, %ecx
	movq	(%rax,%rbp), %rax
	movq	(%rax,%r14,8), %rsi
	movq	48(%rsp), %rax
	movq	(%rax,%r12,8), %rax
	movq	(%rax,%rbp), %rax
	movq	(%rax,%r14,8), %rdi
	incq	%r14
	call	cudaMemcpy@PLT
	movq	96(%rsp), %r10
	jmp	.L90
.L124:
	incq	%r10
	jmp	.L89
.L123:
	incq	%r12
	jmp	.L87
.L122:
	testl	%r15d, %r15d
	jle	.L32
	leaq	.LC14(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
.L32:
	movq	264(%rsp), %rax
	subq	%fs:40, %rax
	je	.L95
	call	__stack_chk_fail@PLT
.L95:
	movq	80(%rsp), %rax
	addq	$280, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4458:
	.size	_Z14par_sim_body_cPiiPPdS_PPxPS1_PS_idPS4_S6_ib, .-_Z14par_sim_body_cPiiPPdS_PPxPS1_PS_idPS4_S6_ib
	.section	.rodata.str1.1
.LC15:
	.string	"_Z15par_c_main_loopPPPdS1_PPiS1_S2_iidiPS1_S4_b"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4486:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC15(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z15par_c_main_loopPPPdS1_PPiS1_S2_iidiPS1_S4_b(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE4486:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst16,"aM",@progbits,16
	.align 16
.LC1:
	.long	0
	.long	-2147483648
	.long	0
	.long	0
	.section	.rodata.cst8,"aM",@progbits,8
	.align 8
.LC2:
	.long	0
	.long	1072693248
	.align 8
.LC3:
	.long	0
	.long	-1074266112
	.align 8
.LC6:
	.long	0
	.long	-1074790400
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include <iostream>
#include <cstring>
#include <fstream>
#include <sstream>
#include <string>
#include <vector>
#include <algorithm>
#include <unistd.h>


// NOTE: Need to compile in C++11 mode, add -std=c++11
// These should eventually be specifiable from R
#define TAU 1
#define V_THRESH 1.5
#define THREADS_PER_BLOCK 512


// Integrated Postsynaptic Kernel
__host__ __device__
double ipostkern(double dt) {
    if (dt < 0) {
        return(0);
    }
    return(TAU * (1 - exp(-dt / TAU)));
}

// Postsynaptic Kernel
__host__ __device__
double postkern(double dt) {
    if (dt < 0) {
        return(0);
    }
    return(exp(-dt / TAU));
}

// Postsynaptic Kernel
__host__ __device__
double dpostkern(double dt) {
    if (dt < 0) {
        return(0);
    }
    return((-1.0) / TAU * exp(-dt / TAU));
}

// Integrated refractory kernel.
__host__ __device__
double iprekern(double dt) {
    if (dt < 0) {
        return(0);
    }
    return(-V_THRESH);
}

// The inner product function, uses the standard R^n inner product.
__host__ __device__
double inner_prod(double *x, double *y, int n) {
    double sum = 0;
    for (int i = 0; i < n; i++) {
        sum += x[i] * y[i];
    }   
    return(sum);
}

__global__
void par_c_main_loop(double ***ALPHA, double ***Fcal, int **f_count, double ***Ws, int* net_shape, int n_layers, 
        int t_steps, double t_eps, int l, double ****GAMMA, double ****GAMMAd, const bool copy_gamma) {
    double t;
    int index = blockIdx.x * blockDim.x + threadIdx.x;
    int stride = blockDim.x * gridDim.x;
    for (int n = index; n < net_shape[l]; n += stride) {
        t = 0;
        for (int ti = 0; ti < t_steps; ti++) {
            // Calculate total postsynaptic contribution 
            int n_f = f_count[l][n];
            double psc = 0;
            for (int tfi = 0; tfi < n_f; tfi++) {
                double tf = Fcal[l][n][tfi];
                psc += ipostkern(t - tf);
            }
            ALPHA[l][ti][n] = psc;

            if (l > 0) {
                // Update refractory contribution
                n_f = f_count[l][n];
                double refr = 0;
                for (int tfi = 0; tfi < n_f; tfi++) {
                    double tf = Fcal[l][n][tfi];
                    refr += iprekern(t - tf);
                }

                // Update potential
                double V_n = inner_prod(Ws[l-1][n], ALPHA[l-1][ti], net_shape[l-1]) + refr;
                //printf("l = %d, n = %d, ti = %d", l, n, ti);
                //printf("Vsl = %d, n = %d, ti = %d", l, n, ti);

                // Check for firing neurons
                if (V_n > V_THRESH) {
                    // If an output fire, record the neural state
                    if (copy_gamma && l == n_layers-1) {
                        for (int l1 = 0; l1 < n_layers; l1++) {
                            for (int h = 0; h < net_shape[l1]; h++) {
                                GAMMA[n][f_count[l][n]][l1][h] = 0;
                                GAMMAd[n][f_count[l][n]][l1][h] = 0;
                                for (int ti = 0; ti < f_count[l1][h]; ti++) {
                                    double tf = Fcal[l1][h][ti];
                                    GAMMA[n][f_count[l][n]][l1][h] += postkern(t + t_eps - tf);
                                    GAMMAd[n][f_count[l][n]][l1][h] += dpostkern(t + t_eps - tf);
                                }
                            }
                        }
                    }
                    Fcal[l][n][f_count[l][n]] = t + t_eps;
                    f_count[l][n]++;
                }
            }
            t += t_eps;
        }
    }
}


// The main simulation, using armadillo for matrix multiplication, and organized in such a way that we solve a sequence embarassingly parallelizable problems.
double **par_sim_body_c(int *net_shape, const int n_layers,
        double **Fin, int *f_count_in, long long int **f_max, double ***Ws,
        int** f_count, const int t_steps, const double t_eps, double ****GAMMA, double ****GAMMAd, const int debug, const bool copy_gamma) {

    // Get the layer with the most neurons
    int max_neur = 0;
    for (int l = 0; l < n_layers; l++) {
        if (max_neur < net_shape[l]) {
            max_neur = net_shape[l];
        }
    }

    // ALPHA stores integrated postsynaptic potential in column major order.
    // OMEGA stores integrated refractory contribution in row major order.
    //double ***ALPHA = (double ***)calloc(n_layers, sizeof(double**));
    //double ***OMEGA = (double ***)calloc(n_layers-1, sizeof(double**));
    double ***ALPHA, ***OMEGA;
    hipMallocManaged(&ALPHA, n_layers * sizeof(double**));
    hipMallocManaged(&OMEGA, (n_layers-1) * sizeof(double**));
    for (int i = 0; i < n_layers; i++) {
        double **ALPHAi;
        hipMallocManaged(&ALPHAi, t_steps * sizeof(double*));
        ALPHA[i] = ALPHAi;
        //ALPHA[i] = (double **) calloc(t_steps, sizeof(double*));
        for (int j = 0; j < t_steps; j++) {
            double *ALPHAij;
            hipMallocManaged(&ALPHAij, net_shape[i] * sizeof(double));
            ALPHA[i][j] = ALPHAij;
            //ALPHA[i][j] = (double *) calloc(net_shape[i], sizeof(double));
        }
        if (i > 0) {
            double **OMEGAi;
            hipMallocManaged(&OMEGAi, net_shape[i] * sizeof(double*));
            OMEGA[i-1] = OMEGAi;
            //OMEGA[i-1] = (double **) calloc(net_shape[i], sizeof(double*));
            for (int j = 0; j < net_shape[i]; j++) {
                double *OMEGAij;
                hipMallocManaged(&OMEGAij, t_steps * sizeof(double));
                OMEGA[i-1][j] = OMEGAij;
                //OMEGA[i-1][j] = (double *) calloc(t_steps, sizeof(double));
            }
        }
    }

    if (debug >= 1) 
        printf("After ALPHA\n");

    // Storage for firing times
    //double ***u_Fcal = (double ***)calloc(n_layers, sizeof(double**));
    double ***u_Fcal;
    hipMallocManaged(&u_Fcal, n_layers * sizeof(double**));

    // Copy input spike times to unified memory.
    double **u_Fin;
    hipMallocManaged(&u_Fin, net_shape[0] * sizeof(double*));
    for (int n = 0; n < net_shape[0]; n++) {
        double *u_Finn;
        hipMallocManaged(&u_Finn, f_count_in[n] * sizeof(double));
        hipMemcpy(u_Finn, Fin[n], f_count_in[n] * sizeof(double), hipMemcpyDefault);
        u_Fin[n] = u_Finn;
    }

    if (debug >= 1) 
        printf("After inputs \n");

    //int **myarr = (int **)malloc(2*sizeof(int *));
    //myarr[0] = (int **)malloc(2*sizeof(int));
    //myarr[1] = (int **)malloc(2*sizeof(int));
    //myarr[0][0] = 0;
    //myarr[0][1] = 1;
    //myarr[1][0] = 2;
    //myarr[1][1] = 3;

    //int **d_myarr;
    //cudaMallocManaged(&d_myarr, 2*sizeof(int *));
    //cudaMemcpy(d_myarr, myarr, 2*sizeof(int *), cudaMemcpyDefault);

    int **u_f_count;
    hipMallocManaged(&u_f_count, n_layers * sizeof(int *));

    int *u_f_count_in;
    hipMallocManaged(&u_f_count_in, net_shape[0] * sizeof(int));
    hipMemcpy(u_f_count_in, f_count_in, net_shape[0] * sizeof(int), hipMemcpyDefault);

    //f_count[0] = u_f_count_in;
    hipMemcpy(&u_f_count[0], &u_f_count_in, sizeof(int *), hipMemcpyDefault);
    u_Fcal[0] = u_Fin;
    for (int l = 0; l < n_layers-1; l++) {
        //double **Fi = (double **) calloc(net_shape[l+1], sizeof(double *));
        double **Fi;
        hipMallocManaged(&Fi, net_shape[l+1] * sizeof(double *));
        u_Fcal[l+1] = Fi;


        //double **Fi = (double **) calloc(net_shape[l+1], sizeof(double *));
        int *f_countl;
        hipMallocManaged(&f_countl, net_shape[l+1] * sizeof(int));
        hipMemcpy(&u_f_count[l+1], &f_countl, sizeof(int *), hipMemcpyDefault);
        for (int n = 0; n < net_shape[l+1]; n++) {
            // Init fire counts at 0.
            u_f_count[l+1][n] = 0;

            double *Fln;
            //printf("Number A\n");
            //printf("%d\n", f_max[l+1][n]);
            //printf("Number Z\n");
            hipMallocManaged(&Fln, f_max[l+1][n] * sizeof(double));
            //printf("Number B\n");
            Fi[n] = Fln;
            //printf("Number C\n");
            // Initialize storeage to -1, so any negative firing time means did not fire.
            for (int f = 0; f < f_max[l+1][n]; f++) {
                Fi[n][f] = -1;
            }
        }
    }

    if (debug >= 1) 
        printf("After Fi copy\n");

    //// Convert Connection weights to a C array
    //// Ws[i] is the ith layer, Ws[i][j] is the jth row of layer i,
    //// Ws[i][j][k] is the j,k element of layer i (row major ordering).
    //double ***Ws_c = (double***)calloc(net_size-1, sizeof(double**));
    //for (int l = 0; l < net_size-1; l++) {
    //    Ws_c[l] = (double**)calloc(net_shape[l], sizeof(double*));
    //    for (int n = 0; n < net_shape[l]; n++) {
    //        Ws_c[l][n] = Ws_in + wlo[l] + net_shape[l+1] * n;
    //    }
    //}


    // Do GAMMA(d)
    // d_GAMMA[on][fi][l]][[h] Gives the instantaneous postsynaptic current of neuron h of layer l to firing time fi of output neuron on.
    double ****d_GAMMA, ****d_GAMMAd;
    if (copy_gamma) {
        hipMallocManaged(&d_GAMMA, (n_layers-1) * sizeof(double***));
        hipMallocManaged(&d_GAMMAd, (n_layers-1) * sizeof(double***));
        for (int on = 0; on < net_shape[n_layers-1]; on++) {
            hipMallocManaged(&d_GAMMA[on], f_max[n_layers-1][on] * sizeof(double **));
            hipMallocManaged(&d_GAMMAd[on], f_max[n_layers-1][on] * sizeof(double **));
            for (int fi = 0; fi < f_max[n_layers-1][on]; fi++) {
                hipMallocManaged(&d_GAMMA[on][fi], n_layers * sizeof(double*));
                hipMallocManaged(&d_GAMMAd[on][fi], n_layers * sizeof(double*));
                for (int l = 0; l < n_layers; l++) {
                    hipMallocManaged(&d_GAMMA[on][fi][l], net_shape[l] * sizeof(double));
                    hipMallocManaged(&d_GAMMAd[on][fi][l], net_shape[l] * sizeof(double));
                    for (int h = 0; h < net_shape[l]; h++) {
                        d_GAMMA[on][fi][l][h] = -1;
                        d_GAMMAd[on][fi][l][h] = -1;
                    }
                }
            }
        }
        if (debug >= 1) 
            printf("Initted GAMMA storage \n");
    }


    // Copy weights to unified memory
    double ***u_Ws;
    hipMallocManaged(&u_Ws, (n_layers-1) * sizeof(double**));
    for (int l = 0; l < n_layers-1; l++) {
        double **u_Wsl;
        hipMallocManaged(&u_Wsl, (net_shape[l+1]) * sizeof(double*));
        u_Ws[l] = u_Wsl;
        for (int n = 0; n < net_shape[l+1]; n++) {
            double *u_Wsln;
            hipMallocManaged(&u_Wsln, net_shape[l] * sizeof(double));
            hipMemcpy(u_Wsln, Ws[l][n], net_shape[l] * sizeof(double), hipMemcpyDefault);
            u_Ws[l][n] = u_Wsln;
        }
    }

    if (debug >= 1) 
        printf("After Weights copy\n");

    // Copy network shape to unified memory
    int *u_net_shape;
    hipMallocManaged(&u_net_shape, n_layers * sizeof(int));
    hipMemcpy(u_net_shape, net_shape, n_layers * sizeof(int), hipMemcpyDefault);

    // Run actual inference
    //TODO: Should just be + 1
    int n_blocks = max_neur / THREADS_PER_BLOCK + 1;

    // Main Loop
    for (int l = 0; l < n_layers; l++) {
        if (debug >= 1) 
            printf(" Solving Layer %d...\n", l);

        par_c_main_loop<<<n_blocks, THREADS_PER_BLOCK>>>(ALPHA, u_Fcal, u_f_count, u_Ws, u_net_shape, n_layers, 
                t_steps, t_eps, l, d_GAMMA, d_GAMMAd, copy_gamma);

        hipDeviceSynchronize();
    }

    if (debug >= 1) 
        printf("After main loop\n");

    // Clean up
    for (int i = 0; i < n_layers; i++) {
        for (int j = 0; j < t_steps; j++) {
            hipFree(ALPHA[i][j]);
        }
        hipFree(ALPHA[i]);
        if (i > 0) {
            for (int j = 0; j < net_shape[i]; j++) {
                hipFree(OMEGA[i-1][j]);
            }
            hipFree(OMEGA[i-1]);
        }
    }
    hipFree(ALPHA);
    hipFree(OMEGA);

    if (debug >= 1) 
        printf("After Free\n");

    // Copy Fcal to host memory
    //double ***Fcal = (double ***)malloc(n_layers * sizeof(double **));
    //for (int l = 0; l < n_layers; l++) {
    //    Fcal[l] = (double **)malloc(net_shape[l] * sizeof(double *));
    //    for (int n = 0; n < net_shape[l]; n++) {
    //        Fcal[l][n] = (double *)malloc(f_max[l][n] * sizeof(double));
    //        cudaMemcpy(Fcal[l][n], u_Fcal[l][n], f_max[l][n] * sizeof(double), cudaMemcpyDefault);
    //    }
    //}
    // Copy output spikes to host memory

    double **Fout = (double **)malloc(net_shape[n_layers-1]*sizeof(double*));
    for (int n = 0; n < net_shape[n_layers-1]; n++) {
        Fout[n] = (double *)malloc(f_max[n_layers-1][n] * sizeof(double));
        hipMemcpy(Fout[n], u_Fcal[n_layers-1][n], f_max[n_layers-1][n] * sizeof(double), hipMemcpyDefault);
    }

    // Copy f_count to host memory
    for (int l = 0; l < n_layers; l++) {
        f_count[l] = (int *)calloc(net_shape[l], sizeof(int));
        hipMemcpy(f_count[l], u_f_count[l], net_shape[l] * sizeof(int), hipMemcpyDefault);
    }

    if (debug >= 1) 
        printf("After output spike spike/f_count\n");

    // Copy to host memory
    // d_GAMMA[on][fi][l]][[h] Gives the instantaneous postsynaptic current of neuron h of layer l to firing time fi of output neuron on.
    //GAMMA = (double****)malloc((n_layers-1) * sizeof(double***));
    //GAMMAd = (double****)malloc((n_layers-1) * sizeof(double***));
    if (copy_gamma) {
        for (int on = 0; on < net_shape[n_layers-1]; on++) {
            GAMMA[on] = (double***)malloc(f_max[n_layers-1][on] * sizeof(double**));
            GAMMAd[on] = (double***)malloc(f_max[n_layers-1][on] * sizeof(double**));
            for (int fi = 0; fi < f_max[n_layers-1][on]; fi++) {
                GAMMA[on][fi] = (double**)malloc(n_layers * sizeof(double*));
                GAMMAd[on][fi] = (double**)malloc(n_layers * sizeof(double*));
                for (int l = 0; l < n_layers; l++) {
                    GAMMA[on][fi][l] = (double*)malloc(net_shape[l] * sizeof(double));
                    GAMMAd[on][fi][l] = (double*)malloc(net_shape[l] * sizeof(double));
                    hipMemcpy(GAMMA[on][fi][l], d_GAMMA[on][fi][l], net_shape[l] * sizeof(double), hipMemcpyDefault);
                    hipMemcpy(GAMMAd[on][fi][l], d_GAMMAd[on][fi][l], net_shape[l] * sizeof(double), hipMemcpyDefault);
                }
            }
        }
        if (debug >= 1) 
            printf("After GAMMA copy\n");
    }

    //TODO: copy f_count

    return(Fout);
}

	.text
	.file	"srm0.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.section	.rodata.cst16,"aM",@progbits,16
	.p2align	4, 0x0                          # -- Begin function _Z9ipostkernd
.LCPI0_0:
	.quad	0x8000000000000000              # double -0
	.quad	0x8000000000000000              # double -0
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0
.LCPI0_1:
	.quad	0x3ff0000000000000              # double 1
	.text
	.globl	_Z9ipostkernd
	.type	_Z9ipostkernd,@function
_Z9ipostkernd:                          # @_Z9ipostkernd
	.cfi_startproc
# %bb.0:
	xorpd	%xmm1, %xmm1
	ucomisd	%xmm0, %xmm1
	ja	.LBB0_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	xorpd	.LCPI0_0(%rip), %xmm0
	callq	exp
	movsd	.LCPI0_1(%rip), %xmm1           # xmm1 = mem[0],zero
	subsd	%xmm0, %xmm1
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB0_2:
	movapd	%xmm1, %xmm0
	retq
.Lfunc_end0:
	.size	_Z9ipostkernd, .Lfunc_end0-_Z9ipostkernd
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst16,"aM",@progbits,16
	.p2align	4, 0x0                          # -- Begin function _Z8postkernd
.LCPI1_0:
	.quad	0x8000000000000000              # double -0
	.quad	0x8000000000000000              # double -0
	.text
	.globl	_Z8postkernd
	.type	_Z8postkernd,@function
_Z8postkernd:                           # @_Z8postkernd
	.cfi_startproc
# %bb.0:
	xorpd	%xmm1, %xmm1
	ucomisd	%xmm0, %xmm1
	jbe	.LBB1_2
# %bb.1:
	xorpd	%xmm0, %xmm0
	retq
.LBB1_2:
	xorpd	.LCPI1_0(%rip), %xmm0
	jmp	exp                             # TAILCALL
.Lfunc_end1:
	.size	_Z8postkernd, .Lfunc_end1-_Z8postkernd
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst16,"aM",@progbits,16
	.p2align	4, 0x0                          # -- Begin function _Z9dpostkernd
.LCPI2_0:
	.quad	0x8000000000000000              # double -0
	.quad	0x8000000000000000              # double -0
	.text
	.globl	_Z9dpostkernd
	.type	_Z9dpostkernd,@function
_Z9dpostkernd:                          # @_Z9dpostkernd
	.cfi_startproc
# %bb.0:
	movapd	%xmm0, %xmm1
	xorpd	%xmm0, %xmm0
	ucomisd	%xmm1, %xmm0
	ja	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	xorpd	.LCPI2_0(%rip), %xmm1
	movapd	%xmm1, %xmm0
	callq	exp
	xorpd	.LCPI2_0(%rip), %xmm0
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	_Z9dpostkernd, .Lfunc_end2-_Z9dpostkernd
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0                          # -- Begin function _Z8iprekernd
.LCPI3_0:
	.quad	0xbff8000000000000              # double -1.5
	.text
	.globl	_Z8iprekernd
	.type	_Z8iprekernd,@function
_Z8iprekernd:                           # @_Z8iprekernd
	.cfi_startproc
# %bb.0:
	xorpd	%xmm1, %xmm1
	cmpltsd	%xmm1, %xmm0
	movsd	.LCPI3_0(%rip), %xmm1           # xmm1 = mem[0],zero
	andnpd	%xmm1, %xmm0
	retq
.Lfunc_end3:
	.size	_Z8iprekernd, .Lfunc_end3-_Z8iprekernd
	.cfi_endproc
                                        # -- End function
	.globl	_Z10inner_prodPdS_i             # -- Begin function _Z10inner_prodPdS_i
	.type	_Z10inner_prodPdS_i,@function
_Z10inner_prodPdS_i:                    # @_Z10inner_prodPdS_i
	.cfi_startproc
# %bb.0:
	testl	%edx, %edx
	jle	.LBB4_1
# %bb.3:                                # %.lr.ph.preheader
	movl	%edx, %eax
	xorpd	%xmm0, %xmm0
	xorl	%ecx, %ecx
.LBB4_4:                                # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	movsd	(%rdi,%rcx,8), %xmm1            # xmm1 = mem[0],zero
	mulsd	(%rsi,%rcx,8), %xmm1
	addsd	%xmm1, %xmm0
	incq	%rcx
	cmpq	%rcx, %rax
	jne	.LBB4_4
# %bb.2:                                # %._crit_edge
	retq
.LBB4_1:
	xorps	%xmm0, %xmm0
	retq
.Lfunc_end4:
	.size	_Z10inner_prodPdS_i, .Lfunc_end4-_Z10inner_prodPdS_i
	.cfi_endproc
                                        # -- End function
	.globl	_Z30__device_stub__par_c_main_loopPPPdS1_PPiS1_S2_iidiPS1_S4_b # -- Begin function _Z30__device_stub__par_c_main_loopPPPdS1_PPiS1_S2_iidiPS1_S4_b
	.type	_Z30__device_stub__par_c_main_loopPPPdS1_PPiS1_S2_iidiPS1_S4_b,@function
_Z30__device_stub__par_c_main_loopPPPdS1_PPiS1_S2_iidiPS1_S4_b: # @_Z30__device_stub__par_c_main_loopPPPdS1_PPiS1_S2_iidiPS1_S4_b
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$208, %rsp
	.cfi_def_cfa_offset 256
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movb	288(%rsp), %al
	leaq	72(%rsp), %r10
	movq	%rdi, (%r10)
	leaq	64(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	56(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	48(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	40(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	12(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	32(%rsp), %r9
	movsd	%xmm0, (%r9)
	leaq	11(%rsp), %r11
	movb	%al, (%r11)
	leaq	112(%rsp), %rbx
	movq	%r10, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	256(%rsp), %rax
	movq	%rax, 48(%rbx)
	movq	%r9, 56(%rbx)
	leaq	264(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	272(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	280(%rsp), %rax
	movq	%rax, 80(%rbx)
	movq	%r11, 88(%rbx)
	leaq	96(%rsp), %r14
	leaq	80(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z15par_c_main_loopPPPdS1_PPiS1_S2_iidiPS1_S4_b, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$224, %rsp
	.cfi_adjust_cfa_offset -224
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end5:
	.size	_Z30__device_stub__par_c_main_loopPPPdS1_PPiS1_S2_iidiPS1_S4_b, .Lfunc_end5-_Z30__device_stub__par_c_main_loopPPPdS1_PPiS1_S2_iidiPS1_S4_b
	.cfi_endproc
                                        # -- End function
	.globl	_Z14par_sim_body_cPiiPPdS_PPxPS1_PS_idPS4_S6_ib # -- Begin function _Z14par_sim_body_cPiiPPdS_PPxPS1_PS_idPS4_S6_ib
	.type	_Z14par_sim_body_cPiiPPdS_PPxPS1_PS_idPS4_S6_ib,@function
_Z14par_sim_body_cPiiPPdS_PPxPS1_PS_idPS4_S6_ib: # @_Z14par_sim_body_cPiiPPdS_PPxPS1_PS_idPS4_S6_ib
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$200, %rsp
	.cfi_def_cfa_offset 256
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movsd	%xmm0, 176(%rsp)                # 8-byte Spill
	movq	%r9, 184(%rsp)                  # 8-byte Spill
	movq	%r8, 56(%rsp)                   # 8-byte Spill
	movq	%rcx, 144(%rsp)                 # 8-byte Spill
	movl	%esi, %ebx
	testl	%esi, %esi
	movq	%rdx, 24(%rsp)                  # 8-byte Spill
	jle	.LBB6_1
# %bb.97:                               # %.lr.ph.preheader
	movl	%ebx, %eax
	xorl	%ecx, %ecx
	xorl	%edx, %edx
.LBB6_98:                               # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	movl	(%rdi,%rcx,4), %esi
	cmpl	%esi, %edx
	cmovgl	%edx, %esi
	incq	%rcx
	movl	%esi, %edx
	cmpq	%rcx, %rax
	jne	.LBB6_98
	jmp	.LBB6_2
.LBB6_1:
	xorl	%esi, %esi
.LBB6_2:                                # %._crit_edge
	movq	%rsi, 168(%rsp)                 # 8-byte Spill
	movq	%rdi, 16(%rsp)                  # 8-byte Spill
	movslq	%ebx, %r14
	leaq	(,%r14,8), %rsi
	leaq	80(%rsp), %rdi
	movq	%rsi, 120(%rsp)                 # 8-byte Spill
	movl	$1, %edx
	callq	hipMallocManaged
	movq	%r14, 152(%rsp)                 # 8-byte Spill
	leaq	-8(,%r14,8), %rsi
	leaq	112(%rsp), %rdi
	movq	%rsi, 136(%rsp)                 # 8-byte Spill
	movl	$1, %edx
	callq	hipMallocManaged
	movl	264(%rsp), %eax
	movl	%eax, %eax
	movq	%rax, 88(%rsp)                  # 8-byte Spill
	movl	%ebx, 12(%rsp)                  # 4-byte Spill
	testl	%ebx, %ebx
	jle	.LBB6_12
# %bb.3:                                # %.lr.ph337
	movl	264(%rsp), %eax
	movslq	%eax, %r13
	shlq	$3, %r13
	movl	12(%rsp), %eax                  # 4-byte Reload
	movq	%rax, 40(%rsp)                  # 8-byte Spill
	xorl	%r15d, %r15d
	leaq	104(%rsp), %rbp
.LBB6_4:                                # =>This Loop Header: Depth=1
                                        #     Child Loop BB6_6 Depth 2
                                        #     Child Loop BB6_10 Depth 2
	leaq	72(%rsp), %rdi
	movq	%r13, %rsi
	movl	$1, %edx
	callq	hipMallocManaged
	movq	72(%rsp), %rax
	movq	80(%rsp), %rcx
	movq	%rax, (%rcx,%r15,8)
	movl	264(%rsp), %eax
	testl	%eax, %eax
	movq	16(%rsp), %rbx                  # 8-byte Reload
	movq	88(%rsp), %r12                  # 8-byte Reload
	jle	.LBB6_7
# %bb.5:                                # %.lr.ph329
                                        #   in Loop: Header=BB6_4 Depth=1
	xorl	%r14d, %r14d
.LBB6_6:                                #   Parent Loop BB6_4 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movslq	(%rbx,%r15,4), %rsi
	shlq	$3, %rsi
	movq	%rbp, %rdi
	movl	$1, %edx
	callq	hipMallocManaged
	movq	104(%rsp), %rax
	movq	80(%rsp), %rcx
	movq	(%rcx,%r15,8), %rcx
	movq	%rax, (%rcx,%r14,8)
	incq	%r14
	cmpq	%r14, %r12
	jne	.LBB6_6
.LBB6_7:                                # %._crit_edge330
                                        #   in Loop: Header=BB6_4 Depth=1
	testq	%r15, %r15
	leaq	48(%rsp), %r12
	je	.LBB6_11
# %bb.8:                                #   in Loop: Header=BB6_4 Depth=1
	movq	16(%rsp), %rbx                  # 8-byte Reload
	movslq	(%rbx,%r15,4), %rsi
	shlq	$3, %rsi
	movq	%rbp, %rdi
	movl	$1, %edx
	callq	hipMallocManaged
	movq	104(%rsp), %rax
	movq	112(%rsp), %rcx
	movq	%rax, -8(%rcx,%r15,8)
	cmpl	$0, (%rbx,%r15,4)
	jle	.LBB6_11
# %bb.9:                                # %.lr.ph333.preheader
                                        #   in Loop: Header=BB6_4 Depth=1
	xorl	%r14d, %r14d
.LBB6_10:                               # %.lr.ph333
                                        #   Parent Loop BB6_4 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movq	%r12, %rdi
	movq	%r13, %rsi
	movl	$1, %edx
	callq	hipMallocManaged
	movq	48(%rsp), %rax
	movq	112(%rsp), %rcx
	movq	-8(%rcx,%r15,8), %rcx
	movq	%rax, (%rcx,%r14,8)
	incq	%r14
	movslq	(%rbx,%r15,4), %rax
	cmpq	%rax, %r14
	jl	.LBB6_10
.LBB6_11:                               #   in Loop: Header=BB6_4 Depth=1
	incq	%r15
	cmpq	40(%rsp), %r15                  # 8-byte Folded Reload
	jne	.LBB6_4
.LBB6_12:                               # %._crit_edge338
	movl	288(%rsp), %r15d
	testl	%r15d, %r15d
	jle	.LBB6_14
# %bb.13:
	movl	$.Lstr, %edi
	callq	puts@PLT
.LBB6_14:
	leaq	72(%rsp), %rdi
	movq	120(%rsp), %rsi                 # 8-byte Reload
	movl	$1, %edx
	callq	hipMallocManaged
	movq	16(%rsp), %r14                  # 8-byte Reload
	movslq	(%r14), %rsi
	shlq	$3, %rsi
	leaq	104(%rsp), %rdi
	movl	$1, %edx
	callq	hipMallocManaged
	cmpl	$0, (%r14)
	movl	12(%rsp), %ebp                  # 4-byte Reload
	movq	144(%rsp), %r13                 # 8-byte Reload
	movq	24(%rsp), %r15                  # 8-byte Reload
	jle	.LBB6_17
# %bb.15:                               # %.lr.ph341.preheader
	xorl	%ebx, %ebx
	leaq	48(%rsp), %r12
.LBB6_16:                               # %.lr.ph341
                                        # =>This Inner Loop Header: Depth=1
	movslq	(%r13,%rbx,4), %rsi
	shlq	$3, %rsi
	movq	%r12, %rdi
	movl	$1, %edx
	callq	hipMallocManaged
	movq	48(%rsp), %rdi
	movq	(%r15,%rbx,8), %rsi
	movslq	(%r13,%rbx,4), %rdx
	shlq	$3, %rdx
	movl	$4, %ecx
	callq	hipMemcpy
	movq	48(%rsp), %rax
	movq	104(%rsp), %rcx
	movq	%rax, (%rcx,%rbx,8)
	incq	%rbx
	movslq	(%r14), %rax
	cmpq	%rax, %rbx
	jl	.LBB6_16
.LBB6_17:                               # %._crit_edge342
	cmpl	$0, 288(%rsp)
	jle	.LBB6_19
# %bb.18:
	movl	$.Lstr.1, %edi
	callq	puts@PLT
.LBB6_19:
	movq	152(%rsp), %rax                 # 8-byte Reload
	decq	%rax
	movq	%rax, 24(%rsp)                  # 8-byte Spill
	leaq	48(%rsp), %r12
	movq	%r12, %rdi
	movq	120(%rsp), %rsi                 # 8-byte Reload
	movl	$1, %edx
	callq	hipMallocManaged
	movq	16(%rsp), %rbx                  # 8-byte Reload
	movslq	(%rbx), %rsi
	shlq	$2, %rsi
	leaq	192(%rsp), %r13
	movq	%r13, %rdi
	movl	$1, %edx
	callq	hipMallocManaged
	movq	(%r13), %rdi
	movslq	(%rbx), %rdx
	shlq	$2, %rdx
	movq	144(%rsp), %rsi                 # 8-byte Reload
	movl	$4, %ecx
	callq	hipMemcpy
	movq	(%r12), %rdi
	movl	$8, %edx
	movq	%r13, %rsi
	movl	$4, %ecx
	callq	hipMemcpy
	movq	104(%rsp), %rax
	movq	72(%rsp), %rcx
	movq	%rax, (%rcx)
	cmpl	$2, %ebp
	jl	.LBB6_28
# %bb.20:                               # %.lr.ph353.preheader
	movl	24(%rsp), %eax                  # 4-byte Reload
	movq	%rax, 40(%rsp)                  # 8-byte Spill
	xorl	%ebp, %ebp
	leaq	96(%rsp), %r13
	movabsq	$-4616189618054758400, %rbx     # imm = 0xBFF0000000000000
	movq	16(%rsp), %r15                  # 8-byte Reload
.LBB6_21:                               # %.lr.ph353
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB6_23 Depth 2
                                        #       Child Loop BB6_25 Depth 3
	movq	%rbp, %r14
	incq	%rbp
	movslq	4(%r15,%r14,4), %rsi
	shlq	$3, %rsi
	leaq	32(%rsp), %rdi
	movl	$1, %edx
	callq	hipMallocManaged
	movq	32(%rsp), %rax
	movq	72(%rsp), %rcx
	leaq	8(,%r14,8), %r12
	movq	%rax, 8(%rcx,%r14,8)
	movslq	4(%r15,%r14,4), %rsi
	shlq	$2, %rsi
	leaq	64(%rsp), %rdi
	movl	$1, %edx
	callq	hipMallocManaged
	addq	48(%rsp), %r12
	movl	$8, %edx
	movq	%r12, %rdi
	leaq	64(%rsp), %rsi
	movl	$4, %ecx
	callq	hipMemcpy
	cmpl	$0, 4(%r15,%r14,4)
	movq	56(%rsp), %r12                  # 8-byte Reload
	jle	.LBB6_27
# %bb.22:                               # %.lr.ph349
                                        #   in Loop: Header=BB6_21 Depth=1
	movq	(%r12,%rbp,8), %rax
	xorl	%r14d, %r14d
.LBB6_23:                               #   Parent Loop BB6_21 Depth=1
                                        # =>  This Loop Header: Depth=2
                                        #       Child Loop BB6_25 Depth 3
	movq	48(%rsp), %rcx
	movq	(%rcx,%rbp,8), %rcx
	movl	$0, (%rcx,%r14,4)
	movq	(%rax,%r14,8), %rsi
	shlq	$3, %rsi
	movq	%r13, %rdi
	movl	$1, %edx
	callq	hipMallocManaged
	movq	96(%rsp), %rax
	movq	32(%rsp), %rcx
	movq	%rax, (%rcx,%r14,8)
	movq	(%r12,%rbp,8), %rax
	movq	(%rax,%r14,8), %rcx
	testq	%rcx, %rcx
	jle	.LBB6_26
# %bb.24:                               # %.lr.ph345
                                        #   in Loop: Header=BB6_23 Depth=2
	movq	32(%rsp), %rdx
	movq	(%rdx,%r14,8), %rdx
	xorl	%esi, %esi
.LBB6_25:                               #   Parent Loop BB6_21 Depth=1
                                        #     Parent Loop BB6_23 Depth=2
                                        # =>    This Inner Loop Header: Depth=3
	movq	%rbx, (%rdx,%rsi,8)
	incq	%rsi
	cmpq	%rsi, %rcx
	jne	.LBB6_25
.LBB6_26:                               # %._crit_edge346
                                        #   in Loop: Header=BB6_23 Depth=2
	incq	%r14
	movq	16(%rsp), %rcx                  # 8-byte Reload
	movslq	(%rcx,%rbp,4), %rcx
	cmpq	%rcx, %r14
	jl	.LBB6_23
.LBB6_27:                               # %._crit_edge350
                                        #   in Loop: Header=BB6_21 Depth=1
	cmpq	40(%rsp), %rbp                  # 8-byte Folded Reload
	jne	.LBB6_21
.LBB6_28:                               # %._crit_edge354
	cmpl	$0, 288(%rsp)
	jle	.LBB6_30
# %bb.29:
	movl	$.Lstr.2, %edi
	callq	puts@PLT
.LBB6_30:
	cmpb	$0, 296(%rsp)
	movl	12(%rsp), %r14d                 # 4-byte Reload
	movq	16(%rsp), %rbp                  # 8-byte Reload
	je	.LBB6_45
# %bb.31:
	leaq	32(%rsp), %rdi
	movq	136(%rsp), %rbx                 # 8-byte Reload
	movq	%rbx, %rsi
	movl	$1, %edx
	callq	hipMallocManaged
	leaq	64(%rsp), %rdi
	movq	%rbx, %rsi
	movl	$1, %edx
	callq	hipMallocManaged
	movq	24(%rsp), %r13                  # 8-byte Reload
	cmpl	$0, (%rbp,%r13,4)
	jle	.LBB6_43
# %bb.32:                               # %.lr.ph369
	movq	56(%rsp), %rax                  # 8-byte Reload
	movq	(%rax,%r13,8), %rax
	movl	%r14d, %ecx
	movq	%rcx, 40(%rsp)                  # 8-byte Spill
	xorl	%ebp, %ebp
	movabsq	$-4616189618054758400, %r15     # imm = 0xBFF0000000000000
.LBB6_33:                               # =>This Loop Header: Depth=1
                                        #     Child Loop BB6_35 Depth 2
                                        #       Child Loop BB6_37 Depth 3
                                        #         Child Loop BB6_39 Depth 4
	leaq	(,%rbp,8), %r12
	movq	32(%rsp), %rdi
	addq	%r12, %rdi
	movq	(%rax,%rbp,8), %rsi
	shlq	$3, %rsi
	movl	$1, %edx
	callq	hipMallocManaged
	addq	64(%rsp), %r12
	movq	56(%rsp), %rbx                  # 8-byte Reload
	movq	(%rbx,%r13,8), %rax
	movq	(%rax,%rbp,8), %rsi
	shlq	$3, %rsi
	movq	%r12, %rdi
	movl	$1, %edx
	callq	hipMallocManaged
	movq	(%rbx,%r13,8), %rax
	cmpq	$0, (%rax,%rbp,8)
	jle	.LBB6_42
# %bb.34:                               # %.lr.ph365.preheader
                                        #   in Loop: Header=BB6_33 Depth=1
	xorl	%ebx, %ebx
.LBB6_35:                               # %.lr.ph365
                                        #   Parent Loop BB6_33 Depth=1
                                        # =>  This Loop Header: Depth=2
                                        #       Child Loop BB6_37 Depth 3
                                        #         Child Loop BB6_39 Depth 4
	movq	32(%rsp), %rax
	leaq	(,%rbx,8), %r12
	movq	(%rax,%rbp,8), %rdi
	addq	%r12, %rdi
	movq	120(%rsp), %r13                 # 8-byte Reload
	movq	%r13, %rsi
	movl	$1, %edx
	callq	hipMallocManaged
	movq	64(%rsp), %rax
	addq	(%rax,%rbp,8), %r12
	movq	%r12, %rdi
	movq	%r13, %rsi
	movl	$1, %edx
	callq	hipMallocManaged
	testl	%r14d, %r14d
	jle	.LBB6_41
# %bb.36:                               # %.lr.ph361.preheader
                                        #   in Loop: Header=BB6_35 Depth=2
	xorl	%r14d, %r14d
.LBB6_37:                               # %.lr.ph361
                                        #   Parent Loop BB6_33 Depth=1
                                        #     Parent Loop BB6_35 Depth=2
                                        # =>    This Loop Header: Depth=3
                                        #         Child Loop BB6_39 Depth 4
	movq	32(%rsp), %rax
	movq	(%rax,%rbp,8), %rax
	leaq	(,%r14,8), %r12
	movq	(%rax,%rbx,8), %rdi
	addq	%r12, %rdi
	movq	16(%rsp), %r13                  # 8-byte Reload
	movslq	(%r13,%r14,4), %rsi
	shlq	$3, %rsi
	movl	$1, %edx
	callq	hipMallocManaged
	movq	64(%rsp), %rax
	movq	(%rax,%rbp,8), %rax
	addq	(%rax,%rbx,8), %r12
	movslq	(%r13,%r14,4), %rsi
	shlq	$3, %rsi
	movq	%r12, %rdi
	movl	$1, %edx
	callq	hipMallocManaged
	movl	(%r13,%r14,4), %eax
	testl	%eax, %eax
	jle	.LBB6_40
# %bb.38:                               # %.lr.ph357
                                        #   in Loop: Header=BB6_37 Depth=3
	movq	32(%rsp), %rcx
	movq	(%rcx,%rbp,8), %rcx
	movq	(%rcx,%rbx,8), %rcx
	movq	(%rcx,%r14,8), %rcx
	movq	64(%rsp), %rdx
	movq	(%rdx,%rbp,8), %rdx
	movq	(%rdx,%rbx,8), %rdx
	movq	(%rdx,%r14,8), %rdx
	xorl	%esi, %esi
.LBB6_39:                               #   Parent Loop BB6_33 Depth=1
                                        #     Parent Loop BB6_35 Depth=2
                                        #       Parent Loop BB6_37 Depth=3
                                        # =>      This Inner Loop Header: Depth=4
	movq	%r15, (%rcx,%rsi,8)
	movq	%r15, (%rdx,%rsi,8)
	incq	%rsi
	cmpq	%rsi, %rax
	jne	.LBB6_39
.LBB6_40:                               # %._crit_edge358
                                        #   in Loop: Header=BB6_37 Depth=3
	incq	%r14
	cmpq	40(%rsp), %r14                  # 8-byte Folded Reload
	jne	.LBB6_37
.LBB6_41:                               # %._crit_edge362
                                        #   in Loop: Header=BB6_35 Depth=2
	incq	%rbx
	movq	56(%rsp), %rax                  # 8-byte Reload
	movq	24(%rsp), %r13                  # 8-byte Reload
	movq	(%rax,%r13,8), %rax
	cmpq	%rbx, (%rax,%rbp,8)
	movl	12(%rsp), %r14d                 # 4-byte Reload
	jg	.LBB6_35
.LBB6_42:                               # %._crit_edge366
                                        #   in Loop: Header=BB6_33 Depth=1
	incq	%rbp
	movq	16(%rsp), %rcx                  # 8-byte Reload
	movslq	(%rcx,%r13,4), %rcx
	cmpq	%rcx, %rbp
	jl	.LBB6_33
.LBB6_43:                               # %._crit_edge370
	cmpl	$0, 288(%rsp)
	movq	16(%rsp), %rbp                  # 8-byte Reload
	jle	.LBB6_45
# %bb.44:
	movl	$.Lstr.3, %edi
	callq	puts@PLT
.LBB6_45:
	leaq	96(%rsp), %rdi
	movq	136(%rsp), %rsi                 # 8-byte Reload
	movl	$1, %edx
	callq	hipMallocManaged
	cmpl	$2, %r14d
	jl	.LBB6_51
# %bb.46:                               # %.lr.ph377.preheader
	movl	24(%rsp), %eax                  # 4-byte Reload
	movq	%rax, 40(%rsp)                  # 8-byte Spill
	xorl	%r14d, %r14d
	leaq	160(%rsp), %r13
	movq	184(%rsp), %rbx                 # 8-byte Reload
.LBB6_47:                               # %.lr.ph377
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB6_49 Depth 2
	leaq	1(%r14), %r15
	movslq	4(%rbp,%r14,4), %rsi
	shlq	$3, %rsi
	leaq	128(%rsp), %rdi
	movl	$1, %edx
	callq	hipMallocManaged
	movq	128(%rsp), %rax
	movq	96(%rsp), %rcx
	movq	%rax, (%rcx,%r14,8)
	cmpl	$0, 4(%rbp,%r14,4)
	movq	%rbp, %r12
	jle	.LBB6_50
# %bb.48:                               # %.lr.ph373
                                        #   in Loop: Header=BB6_47 Depth=1
	xorl	%ebp, %ebp
.LBB6_49:                               #   Parent Loop BB6_47 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movslq	(%r12,%r14,4), %rsi
	shlq	$3, %rsi
	movq	%r13, %rdi
	movl	$1, %edx
	callq	hipMallocManaged
	movq	160(%rsp), %rdi
	movq	(%rbx,%r14,8), %rax
	movq	(%rax,%rbp,8), %rsi
	movslq	(%r12,%r14,4), %rdx
	shlq	$3, %rdx
	movl	$4, %ecx
	callq	hipMemcpy
	movq	160(%rsp), %rax
	movq	96(%rsp), %rcx
	movq	(%rcx,%r14,8), %rcx
	movq	%rax, (%rcx,%rbp,8)
	incq	%rbp
	movslq	(%r12,%r15,4), %rax
	cmpq	%rax, %rbp
	jl	.LBB6_49
.LBB6_50:                               # %._crit_edge374
                                        #   in Loop: Header=BB6_47 Depth=1
	movq	%r15, %r14
	cmpq	40(%rsp), %r15                  # 8-byte Folded Reload
	movq	%r12, %rbp
	jne	.LBB6_47
.LBB6_51:                               # %._crit_edge378
	movl	288(%rsp), %r15d
	testl	%r15d, %r15d
	jle	.LBB6_53
# %bb.52:
	movl	$.Lstr.4, %edi
	callq	puts@PLT
.LBB6_53:
	movq	152(%rsp), %rbx                 # 8-byte Reload
	shlq	$2, %rbx
	leaq	128(%rsp), %r12
	movq	%r12, %rdi
	movq	%rbx, %rsi
	movl	$1, %edx
	callq	hipMallocManaged
	movq	(%r12), %rdi
	movq	%rbp, %rsi
	movq	%rbx, %rdx
	movl	$4, %ecx
	callq	hipMemcpy
	movl	12(%rsp), %r14d                 # 4-byte Reload
	testl	%r14d, %r14d
	jle	.LBB6_60
# %bb.54:                               # %.lr.ph381
	movabsq	$4294967296, %r12               # imm = 0x100000000
	movq	168(%rsp), %rax                 # 8-byte Reload
	shrl	$9, %eax
	leaq	(%r12,%rax), %r13
	incq	%r13
	addq	$512, %r12                      # imm = 0x200
	movzbl	296(%rsp), %ebx
	xorl	%ebp, %ebp
.LBB6_55:                               # =>This Inner Loop Header: Depth=1
	testl	%r15d, %r15d
	jle	.LBB6_57
# %bb.56:                               #   in Loop: Header=BB6_55 Depth=1
	movl	$.L.str.5, %edi
	movl	%ebp, %esi
	xorl	%eax, %eax
	callq	printf
.LBB6_57:                               #   in Loop: Header=BB6_55 Depth=1
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB6_59
# %bb.58:                               #   in Loop: Header=BB6_55 Depth=1
	movq	80(%rsp), %rdi
	movq	72(%rsp), %rsi
	movq	48(%rsp), %rdx
	movq	96(%rsp), %rcx
	movq	128(%rsp), %r8
	subq	$8, %rsp
	.cfi_adjust_cfa_offset 8
	movl	%r14d, %r9d
	movsd	184(%rsp), %xmm0                # 8-byte Reload
                                        # xmm0 = mem[0],zero
	pushq	%rbx
	.cfi_adjust_cfa_offset 8
	pushq	80(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	56(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	%rbp
	.cfi_adjust_cfa_offset 8
	movl	304(%rsp), %eax
	pushq	%rax
	.cfi_adjust_cfa_offset 8
	callq	_Z30__device_stub__par_c_main_loopPPPdS1_PPiS1_S2_iidiPS1_S4_b
	addq	$48, %rsp
	.cfi_adjust_cfa_offset -48
.LBB6_59:                               #   in Loop: Header=BB6_55 Depth=1
	callq	hipDeviceSynchronize
	incl	%ebp
	cmpl	%ebp, %r14d
	jne	.LBB6_55
.LBB6_60:                               # %._crit_edge382
	testl	%r15d, %r15d
	jle	.LBB6_62
# %bb.61:
	movl	$.Lstr.5, %edi
	callq	puts@PLT
.LBB6_62:
	testl	%r14d, %r14d
	movq	56(%rsp), %r12                  # 8-byte Reload
	movq	16(%rsp), %r13                  # 8-byte Reload
	movq	88(%rsp), %rbp                  # 8-byte Reload
	jle	.LBB6_73
# %bb.63:                               # %.preheader324.lr.ph
	movl	12(%rsp), %ebx                  # 4-byte Reload
	xorl	%r14d, %r14d
.LBB6_64:                               # %.preheader324
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB6_66 Depth 2
                                        #     Child Loop BB6_70 Depth 2
	movl	264(%rsp), %eax
	testl	%eax, %eax
	jle	.LBB6_67
# %bb.65:                               # %.lr.ph384.preheader
                                        #   in Loop: Header=BB6_64 Depth=1
	xorl	%r15d, %r15d
.LBB6_66:                               # %.lr.ph384
                                        #   Parent Loop BB6_64 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movq	80(%rsp), %rax
	movq	(%rax,%r14,8), %rax
	movq	(%rax,%r15,8), %rdi
	callq	hipFree
	incq	%r15
	cmpq	%r15, %rbp
	jne	.LBB6_66
.LBB6_67:                               # %._crit_edge385
                                        #   in Loop: Header=BB6_64 Depth=1
	movq	80(%rsp), %rax
	movq	(%rax,%r14,8), %rdi
	callq	hipFree
	testq	%r14, %r14
	je	.LBB6_72
# %bb.68:                               # %.preheader323
                                        #   in Loop: Header=BB6_64 Depth=1
	cmpl	$0, (%r13,%r14,4)
	jle	.LBB6_71
# %bb.69:                               # %.lr.ph387.preheader
                                        #   in Loop: Header=BB6_64 Depth=1
	xorl	%r15d, %r15d
.LBB6_70:                               # %.lr.ph387
                                        #   Parent Loop BB6_64 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movq	112(%rsp), %rax
	movq	-8(%rax,%r14,8), %rax
	movq	(%rax,%r15,8), %rdi
	callq	hipFree
	incq	%r15
	movslq	(%r13,%r14,4), %rax
	cmpq	%rax, %r15
	jl	.LBB6_70
.LBB6_71:                               # %._crit_edge388
                                        #   in Loop: Header=BB6_64 Depth=1
	movq	112(%rsp), %rax
	movq	-8(%rax,%r14,8), %rdi
	callq	hipFree
.LBB6_72:                               #   in Loop: Header=BB6_64 Depth=1
	incq	%r14
	cmpq	%rbx, %r14
	jne	.LBB6_64
.LBB6_73:                               # %._crit_edge390
	movq	80(%rsp), %rdi
	callq	hipFree
	movq	112(%rsp), %rdi
	callq	hipFree
	cmpl	$0, 288(%rsp)
	jle	.LBB6_75
# %bb.74:
	movl	$.Lstr.6, %edi
	callq	puts@PLT
.LBB6_75:
	movq	24(%rsp), %r15                  # 8-byte Reload
	movslq	(%r13,%r15,4), %rbx
	leaq	(,%rbx,8), %rdi
	callq	malloc
	movq	%rax, %rbp
	testq	%rbx, %rbx
	movq	%r13, %r14
	jle	.LBB6_78
# %bb.76:                               # %.lr.ph393
	xorl	%ebx, %ebx
.LBB6_77:                               # =>This Inner Loop Header: Depth=1
	movq	(%r12,%r15,8), %rax
	movq	(%rax,%rbx,8), %r13
	shlq	$3, %r13
	movq	%r13, %rdi
	callq	malloc
	movq	%rax, (%rbp,%rbx,8)
	movq	72(%rsp), %rcx
	movq	24(%rsp), %rdx                  # 8-byte Reload
	movq	(%rcx,%rdx,8), %rcx
	movq	(%rcx,%rbx,8), %rsi
	movq	%rax, %rdi
	movq	%r13, %rdx
	movq	24(%rsp), %r15                  # 8-byte Reload
	movl	$4, %ecx
	callq	hipMemcpy
	incq	%rbx
	movslq	(%r14,%r15,4), %rax
	cmpq	%rax, %rbx
	jl	.LBB6_77
.LBB6_78:                               # %.preheader322
	movq	%rbp, 88(%rsp)                  # 8-byte Spill
	cmpl	$0, 12(%rsp)                    # 4-byte Folded Reload
	movq	%r14, %r12
	jle	.LBB6_81
# %bb.79:                               # %.lr.ph395.preheader
	movq	256(%rsp), %rbx
	movl	12(%rsp), %r14d                 # 4-byte Reload
	xorl	%r15d, %r15d
.LBB6_80:                               # %.lr.ph395
                                        # =>This Inner Loop Header: Depth=1
	movslq	(%r12,%r15,4), %r13
	movl	$4, %esi
	movq	%r13, %rdi
	callq	calloc
	movq	%rax, (%rbx,%r15,8)
	movq	48(%rsp), %rcx
	movq	(%rcx,%r15,8), %rsi
	shlq	$2, %r13
	movq	%rax, %rdi
	movq	%r13, %rdx
	movl	$4, %ecx
	callq	hipMemcpy
	incq	%r15
	cmpq	%r15, %r14
	jne	.LBB6_80
.LBB6_81:                               # %._crit_edge396
	cmpl	$0, 288(%rsp)
	jle	.LBB6_83
# %bb.82:
	movl	$.Lstr.7, %edi
	callq	puts@PLT
.LBB6_83:
	cmpb	$0, 296(%rsp)
	movq	24(%rsp), %rcx                  # 8-byte Reload
	movq	88(%rsp), %rbx                  # 8-byte Reload
	je	.LBB6_96
# %bb.84:                               # %.preheader
	movl	(%r12,%rcx,4), %r14d
	testl	%r14d, %r14d
	jle	.LBB6_94
# %bb.85:                               # %.lr.ph406
	movq	280(%rsp), %rbp
	movq	272(%rsp), %r15
	movq	56(%rsp), %rax                  # 8-byte Reload
	movq	(%rax,%rcx,8), %rax
	movl	12(%rsp), %ecx                  # 4-byte Reload
	shlq	$2, %rcx
	movq	%rcx, 40(%rsp)                  # 8-byte Spill
	xorl	%r12d, %r12d
.LBB6_86:                               # =>This Loop Header: Depth=1
                                        #     Child Loop BB6_88 Depth 2
                                        #       Child Loop BB6_90 Depth 3
	movq	(%rax,%r12,8), %rdi
	shlq	$3, %rdi
	callq	malloc
	movq	%rax, (%r15,%r12,8)
	movq	56(%rsp), %r13                  # 8-byte Reload
	movq	24(%rsp), %rax                  # 8-byte Reload
	movq	(%r13,%rax,8), %rax
	movq	(%rax,%r12,8), %rdi
	shlq	$3, %rdi
	callq	malloc
	movq	%rax, (%rbp,%r12,8)
	movq	24(%rsp), %rax                  # 8-byte Reload
	movq	(%r13,%rax,8), %rax
	cmpq	$0, (%rax,%r12,8)
	jle	.LBB6_93
# %bb.87:                               # %.lr.ph403.preheader
                                        #   in Loop: Header=BB6_86 Depth=1
	xorl	%r14d, %r14d
.LBB6_88:                               # %.lr.ph403
                                        #   Parent Loop BB6_86 Depth=1
                                        # =>  This Loop Header: Depth=2
                                        #       Child Loop BB6_90 Depth 3
	movq	120(%rsp), %rbx                 # 8-byte Reload
	movq	%rbx, %rdi
	callq	malloc
	movq	(%r15,%r12,8), %rcx
	movq	%rax, (%rcx,%r14,8)
	movq	%rbx, %rdi
	callq	malloc
	movq	(%rbp,%r12,8), %rcx
	movq	%rax, (%rcx,%r14,8)
	cmpl	$0, 12(%rsp)                    # 4-byte Folded Reload
	movq	16(%rsp), %rbx                  # 8-byte Reload
	movq	%rbp, %r15
	jle	.LBB6_91
# %bb.89:                               # %.lr.ph399.preheader
                                        #   in Loop: Header=BB6_88 Depth=2
	xorl	%ebp, %ebp
.LBB6_90:                               # %.lr.ph399
                                        #   Parent Loop BB6_86 Depth=1
                                        #     Parent Loop BB6_88 Depth=2
                                        # =>    This Inner Loop Header: Depth=3
	movslq	(%rbx,%rbp), %r13
	shlq	$3, %r13
	movq	%r13, %rdi
	callq	malloc
	movq	272(%rsp), %rcx
	movq	%r15, %rbx
	movq	%rcx, %r15
	movq	(%rcx,%r12,8), %rcx
	movq	(%rcx,%r14,8), %rcx
	movq	%rax, (%rcx,%rbp,2)
	movq	%r13, %rdi
	callq	malloc
	movq	(%rbx,%r12,8), %rcx
	movq	(%rcx,%r14,8), %rcx
	movq	%rax, (%rcx,%rbp,2)
	movq	(%r15,%r12,8), %rax
	movq	%rbx, %r15
	movq	16(%rsp), %rbx                  # 8-byte Reload
	movq	(%rax,%r14,8), %rax
	movq	(%rax,%rbp,2), %rdi
	movq	32(%rsp), %rax
	movq	(%rax,%r12,8), %rax
	movq	(%rax,%r14,8), %rax
	movq	(%rax,%rbp,2), %rsi
	movq	%r13, %rdx
	movl	$4, %ecx
	callq	hipMemcpy
	movq	(%r15,%r12,8), %rax
	movq	(%rax,%r14,8), %rax
	movq	(%rax,%rbp,2), %rdi
	movq	64(%rsp), %rax
	movq	(%rax,%r12,8), %rax
	movq	(%rax,%r14,8), %rax
	movq	(%rax,%rbp,2), %rsi
	movslq	(%rbx,%rbp), %rdx
	shlq	$3, %rdx
	movl	$4, %ecx
	callq	hipMemcpy
	movq	40(%rsp), %rax                  # 8-byte Reload
	addq	$4, %rbp
	cmpq	%rbp, %rax
	jne	.LBB6_90
.LBB6_91:                               # %._crit_edge400
                                        #   in Loop: Header=BB6_88 Depth=2
	incq	%r14
	movq	56(%rsp), %rax                  # 8-byte Reload
	movq	24(%rsp), %rdx                  # 8-byte Reload
	movq	(%rax,%rdx,8), %rax
	cmpq	%r14, (%rax,%r12,8)
	movq	%r15, %rbp
	movq	272(%rsp), %r15
	jg	.LBB6_88
# %bb.92:                               # %._crit_edge404.loopexit
                                        #   in Loop: Header=BB6_86 Depth=1
	movq	16(%rsp), %rcx                  # 8-byte Reload
	movl	(%rcx,%rdx,4), %r14d
	movq	88(%rsp), %rbx                  # 8-byte Reload
.LBB6_93:                               # %._crit_edge404
                                        #   in Loop: Header=BB6_86 Depth=1
	incq	%r12
	movslq	%r14d, %rcx
	cmpq	%rcx, %r12
	jl	.LBB6_86
.LBB6_94:                               # %._crit_edge407
	cmpl	$0, 288(%rsp)
	jle	.LBB6_96
# %bb.95:
	movl	$.Lstr.8, %edi
	callq	puts@PLT
.LBB6_96:
	movq	%rbx, %rax
	addq	$200, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end6:
	.size	_Z14par_sim_body_cPiiPPdS_PPxPS1_PS_idPS4_S6_ib, .Lfunc_end6-_Z14par_sim_body_cPiiPPdS_PPxPS1_PS_idPS4_S6_ib
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB7_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB7_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z15par_c_main_loopPPPdS1_PPiS1_S2_iidiPS1_S4_b, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end7:
	.size	__hip_module_ctor, .Lfunc_end7-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB8_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB8_2:
	retq
.Lfunc_end8:
	.size	__hip_module_dtor, .Lfunc_end8-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z15par_c_main_loopPPPdS1_PPiS1_S2_iidiPS1_S4_b,@object # @_Z15par_c_main_loopPPPdS1_PPiS1_S2_iidiPS1_S4_b
	.section	.rodata,"a",@progbits
	.globl	_Z15par_c_main_loopPPPdS1_PPiS1_S2_iidiPS1_S4_b
	.p2align	3, 0x0
_Z15par_c_main_loopPPPdS1_PPiS1_S2_iidiPS1_S4_b:
	.quad	_Z30__device_stub__par_c_main_loopPPPdS1_PPiS1_S2_iidiPS1_S4_b
	.size	_Z15par_c_main_loopPPPdS1_PPiS1_S2_iidiPS1_S4_b, 8

	.type	.L.str.5,@object                # @.str.5
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str.5:
	.asciz	" Solving Layer %d...\n"
	.size	.L.str.5, 22

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z15par_c_main_loopPPPdS1_PPiS1_S2_iidiPS1_S4_b"
	.size	.L__unnamed_1, 48

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.type	.Lstr,@object                   # @str
	.section	.rodata.str1.1,"aMS",@progbits,1
.Lstr:
	.asciz	"After ALPHA"
	.size	.Lstr, 12

	.type	.Lstr.1,@object                 # @str.1
.Lstr.1:
	.asciz	"After inputs "
	.size	.Lstr.1, 14

	.type	.Lstr.2,@object                 # @str.2
.Lstr.2:
	.asciz	"After Fi copy"
	.size	.Lstr.2, 14

	.type	.Lstr.3,@object                 # @str.3
.Lstr.3:
	.asciz	"Initted GAMMA storage "
	.size	.Lstr.3, 23

	.type	.Lstr.4,@object                 # @str.4
.Lstr.4:
	.asciz	"After Weights copy"
	.size	.Lstr.4, 19

	.type	.Lstr.5,@object                 # @str.5
.Lstr.5:
	.asciz	"After main loop"
	.size	.Lstr.5, 16

	.type	.Lstr.6,@object                 # @str.6
.Lstr.6:
	.asciz	"After Free"
	.size	.Lstr.6, 11

	.type	.Lstr.7,@object                 # @str.7
.Lstr.7:
	.asciz	"After output spike spike/f_count"
	.size	.Lstr.7, 33

	.type	.Lstr.8,@object                 # @str.8
.Lstr.8:
	.asciz	"After GAMMA copy"
	.size	.Lstr.8, 17

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z30__device_stub__par_c_main_loopPPPdS1_PPiS1_S2_iidiPS1_S4_b
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z15par_c_main_loopPPPdS1_PPiS1_S2_iidiPS1_S4_b
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z15par_c_main_loopPPPdS1_PPiS1_S2_iidiPS1_S4_b ; -- Begin function _Z15par_c_main_loopPPPdS1_PPiS1_S2_iidiPS1_S4_b
	.globl	_Z15par_c_main_loopPPPdS1_PPiS1_S2_iidiPS1_S4_b
	.p2align	8
	.type	_Z15par_c_main_loopPPPdS1_PPiS1_S2_iidiPS1_S4_b,@function
_Z15par_c_main_loopPPPdS1_PPiS1_S2_iidiPS1_S4_b: ; @_Z15par_c_main_loopPPPdS1_PPiS1_S2_iidiPS1_S4_b
; %bb.0:
	s_clause 0x2
	s_load_b32 s46, s[0:1], 0x38
	s_load_b32 s6, s[0:1], 0x64
	s_load_b64 s[2:3], s[0:1], 0x20
	s_waitcnt lgkmcnt(0)
	s_ashr_i32 s47, s46, 31
	s_add_u32 s22, s0, 0x58
	s_addc_u32 s23, s1, 0
	s_lshl_b64 s[4:5], s[46:47], 2
	s_and_b32 s60, s6, 0xffff
	s_add_u32 s20, s2, s4
	s_addc_u32 s21, s3, s5
	v_mad_u64_u32 v[1:2], null, s15, s60, v[0:1]
	s_load_b32 s24, s[20:21], 0x0
	s_mov_b32 s4, exec_lo
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e64 s24, v1
	s_cbranch_execz .LBB0_43
; %bb.1:                                ; %.preheader204.lr.ph
	s_clause 0x3
	s_load_b32 s25, s[0:1], 0x50
	s_load_b128 s[12:15], s[0:1], 0x28
	s_load_b256 s[4:11], s[0:1], 0x0
	s_load_b128 s[16:19], s[0:1], 0x40
	s_load_b32 s73, s[22:23], 0x0
	s_mov_b32 s23, 0
	v_dual_mov_b32 v0, s24 :: v_dual_mov_b32 v3, 0
	s_mov_b32 s34, 0xfefa39ef
	s_mov_b32 s36, 0x3b39803f
	s_mov_b32 s38, 0xfca7ab0c
	s_mov_b32 s40, 0x6a5dcb37
	s_mov_b32 s44, 0x623fde64
	s_mov_b32 s48, 0x14761f6e
	s_mov_b32 s52, 0x11122322
	s_mov_b32 s54, 0x555502a1
	s_mov_b32 s56, 0x55555511
	s_mov_b32 s58, 11
	s_mov_b32 s35, 0xbfe62e42
	s_mov_b32 s37, 0xbc7abc9e
	s_waitcnt lgkmcnt(0)
	s_bitcmp1_b32 s25, 0
	s_mov_b32 s24, 0x652b82fe
	s_cselect_b32 s50, -1, 0
	s_cmp_gt_i32 s13, 0
	s_mov_b32 s25, 0xbff71547
	s_cselect_b32 s33, -1, 0
	s_lshl_b64 s[0:1], s[46:47], 3
	s_mov_b32 s39, 0x3e928af3
	s_add_u32 s26, s8, s0
	s_addc_u32 s27, s9, s1
	s_add_u32 s28, s6, s0
	s_addc_u32 s29, s7, s1
	s_add_u32 s30, s4, s0
	s_addc_u32 s31, s5, s1
	s_cmp_gt_i32 s46, 0
	s_mov_b32 s41, 0x3e5ade15
	s_cselect_b32 s72, -1, 0
	s_add_i32 s22, s46, -1
	s_mov_b32 s45, 0x3ec71dee
	s_lshl_b64 s[0:1], s[22:23], 3
	s_mov_b32 s49, 0x3f2a01a0
	s_add_u32 s10, s10, s0
	s_addc_u32 s11, s11, s1
	s_add_u32 s4, s4, s0
	s_addc_u32 s5, s5, s1
	s_lshl_b64 s[0:1], s[22:23], 2
	s_mov_b32 s53, 0x3f811111
	s_add_u32 s42, s2, s0
	s_addc_u32 s43, s3, s1
	s_add_i32 s0, s12, -1
	s_mov_b32 s55, 0x3fa55555
	s_cmp_eq_u32 s0, s46
	s_mov_b32 s46, 0x7c89e6b0
	s_cselect_b32 s0, -1, 0
	s_mov_b32 s47, 0x3efa0199
	s_and_b32 s0, s50, s0
	s_cmp_gt_i32 s12, 0
	s_mov_b32 s50, 0x1852b7b0
	s_cselect_b32 s1, -1, 0
	s_mov_b32 s51, 0x3f56c16c
	s_mov_b32 s57, 0x3fc55555
	s_mov_b32 s59, 0x3fe00000
	s_mul_i32 s73, s73, s60
	s_and_b32 s74, s0, s1
	s_mov_b32 s75, 0
.LBB0_2:                                ; %.preheader204
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_4 Depth 2
                                        ;       Child Loop BB0_6 Depth 3
                                        ;       Child Loop BB0_13 Depth 3
                                        ;       Child Loop BB0_17 Depth 3
                                        ;       Child Loop BB0_22 Depth 3
                                        ;         Child Loop BB0_24 Depth 4
                                        ;           Child Loop BB0_26 Depth 5
	s_and_not1_b32 vcc_lo, exec_lo, s33
	s_cbranch_vccnz .LBB0_42
; %bb.3:                                ; %.lr.ph222
                                        ;   in Loop: Header=BB0_2 Depth=1
	global_load_b64 v[5:6], v3, s[26:27]
	v_ashrrev_i32_e32 v2, 31, v1
	s_load_b64 s[60:61], s[30:31], 0x0
	v_mov_b32_e32 v11, 0
	v_mov_b32_e32 v12, 0
	s_mov_b32 s62, 0
	v_lshlrev_b64 v[7:8], 2, v[1:2]
	v_lshlrev_b64 v[9:10], 3, v[1:2]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_mov_b32 v18, v12 :: v_dual_mov_b32 v17, v11
	s_waitcnt vmcnt(0)
	v_add_co_u32 v5, vcc_lo, v5, v7
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_ci_u32_e32 v6, vcc_lo, v6, v8, vcc_lo
	v_add_co_u32 v13, vcc_lo, s16, v9
	v_add_co_ci_u32_e32 v14, vcc_lo, s17, v10, vcc_lo
	global_load_b32 v7, v[5:6], off
	v_add_co_u32 v15, vcc_lo, s18, v9
	v_add_co_ci_u32_e32 v16, vcc_lo, s19, v10, vcc_lo
.LBB0_4:                                ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB0_6 Depth 3
                                        ;       Child Loop BB0_13 Depth 3
                                        ;       Child Loop BB0_17 Depth 3
                                        ;       Child Loop BB0_22 Depth 3
                                        ;         Child Loop BB0_24 Depth 4
                                        ;           Child Loop BB0_26 Depth 5
	s_waitcnt vmcnt(0)
	v_cmp_lt_i32_e64 s0, 0, v7
	v_dual_mov_b32 v20, v12 :: v_dual_mov_b32 v19, v11
	s_delay_alu instid0(VALU_DEP_2)
	s_and_saveexec_b32 s22, s0
	s_cbranch_execz .LBB0_10
; %bb.5:                                ; %.lr.ph
                                        ;   in Loop: Header=BB0_4 Depth=2
	s_load_b64 s[64:65], s[28:29], 0x0
	v_dual_mov_b32 v23, 0 :: v_dual_mov_b32 v0, v7
	v_mov_b32_e32 v24, 0
	s_mov_b32 s63, 0
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v19, vcc_lo, s64, v9
	v_add_co_ci_u32_e32 v20, vcc_lo, s65, v10, vcc_lo
	global_load_b64 v[21:22], v[19:20], off
	v_dual_mov_b32 v19, v23 :: v_dual_mov_b32 v20, v24
.LBB0_6:                                ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_4 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_waitcnt vmcnt(0)
	global_load_b64 v[25:26], v[21:22], off
	v_dual_mov_b32 v28, v24 :: v_dual_mov_b32 v27, v23
	s_mov_b32 s64, exec_lo
	s_waitcnt vmcnt(0)
	v_add_f64 v[25:26], v[17:18], -v[25:26]
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_ngt_f64_e32 0, v[25:26]
	s_cbranch_execz .LBB0_8
; %bb.7:                                ;   in Loop: Header=BB0_6 Depth=3
	v_mul_f64 v[27:28], v[25:26], s[24:25]
	v_cmp_ngt_f64_e32 vcc_lo, 0xc0900000, v[25:26]
	v_cmp_nlt_f64_e64 s1, 0x4090cc00, v[25:26]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f64_e32 v[27:28], v[27:28]
	v_fma_f64 v[29:30], v[27:28], s[34:35], -v[25:26]
	v_cvt_i32_f64_e32 v2, v[27:28]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[29:30], v[27:28], s[36:37], v[29:30]
	v_fma_f64 v[31:32], v[29:30], s[40:41], s[38:39]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[31:32], v[29:30], v[31:32], s[44:45]
	v_fma_f64 v[31:32], v[29:30], v[31:32], s[46:47]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[31:32], v[29:30], v[31:32], s[48:49]
	v_fma_f64 v[31:32], v[29:30], v[31:32], s[50:51]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[31:32], v[29:30], v[31:32], s[52:53]
	v_fma_f64 v[31:32], v[29:30], v[31:32], s[54:55]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[31:32], v[29:30], v[31:32], s[56:57]
	v_fma_f64 v[31:32], v[29:30], v[31:32], s[58:59]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[31:32], v[29:30], v[31:32], 1.0
	v_fma_f64 v[27:28], v[29:30], v[31:32], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ldexp_f64 v[27:28], v[27:28], v2
	v_add_f64 v[27:28], -v[27:28], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v2, 0xfff00000, v28, vcc_lo
	s_and_b32 vcc_lo, s1, vcc_lo
	v_cndmask_b32_e32 v27, 0, v27, vcc_lo
	s_delay_alu instid0(VALU_DEP_2)
	v_cndmask_b32_e64 v28, 0x3ff00000, v2, s1
.LBB0_8:                                ; %_Z9ipostkernd.exit
                                        ;   in Loop: Header=BB0_6 Depth=3
	s_or_b32 exec_lo, exec_lo, s64
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_f64 v[19:20], v[19:20], v[27:28]
	v_add_nc_u32_e32 v0, -1, v0
	v_add_co_u32 v21, s1, v21, 8
	v_add_co_ci_u32_e64 v22, s1, 0, v22, s1
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_eq_u32_e32 vcc_lo, 0, v0
	s_or_b32 s63, vcc_lo, s63
	s_and_not1_b32 exec_lo, exec_lo, s63
	s_cbranch_execnz .LBB0_6
; %bb.9:                                ; %Flow304
                                        ;   in Loop: Header=BB0_4 Depth=2
	s_or_b32 exec_lo, exec_lo, s63
.LBB0_10:                               ; %Flow305
                                        ;   in Loop: Header=BB0_4 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s22
	s_mov_b32 s63, s23
	s_lshl_b64 s[64:65], s[62:63], 3
	s_waitcnt lgkmcnt(0)
	s_add_u32 s66, s60, s64
	s_addc_u32 s67, s61, s65
	s_load_b64 s[66:67], s[66:67], 0x0
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v21, vcc_lo, s66, v9
	v_add_co_ci_u32_e32 v22, vcc_lo, s67, v10, vcc_lo
	s_and_not1_b32 vcc_lo, exec_lo, s72
	global_store_b64 v[21:22], v[19:20], off
	s_cbranch_vccnz .LBB0_40
; %bb.11:                               ; %.preheader203
                                        ;   in Loop: Header=BB0_4 Depth=2
	v_mov_b32_e32 v19, 0
	v_mov_b32_e32 v20, 0
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_15
; %bb.12:                               ; %.lr.ph209
                                        ;   in Loop: Header=BB0_4 Depth=2
	s_load_b64 s[66:67], s[28:29], 0x0
	s_mov_b32 s22, 0
	v_mov_b32_e32 v0, v7
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v19, vcc_lo, s66, v9
	v_add_co_ci_u32_e32 v20, vcc_lo, s67, v10, vcc_lo
	global_load_b64 v[21:22], v[19:20], off
	v_mov_b32_e32 v19, 0
	v_mov_b32_e32 v20, 0
.LBB0_13:                               ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_4 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_waitcnt vmcnt(0)
	global_load_b64 v[23:24], v[21:22], off
	v_add_nc_u32_e32 v0, -1, v0
	v_add_co_u32 v21, s0, v21, 8
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e64 v22, s0, 0, v22, s0
	s_waitcnt vmcnt(0)
	v_add_f64 v[23:24], v[17:18], -v[23:24]
	v_cmp_gt_f64_e32 vcc_lo, 0, v[23:24]
	v_cndmask_b32_e64 v4, 0xbff80000, 0, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 0, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_add_f64 v[19:20], v[19:20], v[3:4]
	s_or_b32 s22, vcc_lo, s22
	s_and_not1_b32 exec_lo, exec_lo, s22
	s_cbranch_execnz .LBB0_13
; %bb.14:                               ; %Flow301
                                        ;   in Loop: Header=BB0_4 Depth=2
	s_or_b32 exec_lo, exec_lo, s22
.LBB0_15:                               ; %Flow302
                                        ;   in Loop: Header=BB0_4 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	global_load_b32 v0, v3, s[42:43]
	s_waitcnt vmcnt(0)
	v_cmp_gt_i32_e32 vcc_lo, 1, v0
	s_cbranch_vccnz .LBB0_18
; %bb.16:                               ; %.lr.ph.i.preheader
                                        ;   in Loop: Header=BB0_4 Depth=2
	s_load_b64 s[0:1], s[10:11], 0x0
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v21, vcc_lo, s0, v9
	v_add_co_ci_u32_e32 v22, vcc_lo, s1, v10, vcc_lo
	s_load_b64 s[0:1], s[4:5], 0x0
	global_load_b64 v[23:24], v[21:22], off
	v_mov_b32_e32 v21, 0
	v_mov_b32_e32 v22, 0
	s_waitcnt lgkmcnt(0)
	s_add_u32 s0, s0, s64
	s_addc_u32 s1, s1, s65
	s_load_b64 s[64:65], s[0:1], 0x0
.LBB0_17:                               ; %.lr.ph.i
                                        ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_4 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_waitcnt vmcnt(0)
	global_load_b64 v[25:26], v[23:24], off
	s_waitcnt lgkmcnt(0)
	global_load_b64 v[27:28], v3, s[64:65]
	v_add_nc_u32_e32 v0, -1, v0
	v_add_co_u32 v23, vcc_lo, v23, 8
	v_add_co_ci_u32_e32 v24, vcc_lo, 0, v24, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_cmp_ne_u32_e64 s0, 0, v0
	s_add_u32 s64, s64, 8
	s_addc_u32 s65, s65, 0
	s_and_b32 vcc_lo, exec_lo, s0
	s_waitcnt vmcnt(0)
	v_fma_f64 v[21:22], v[25:26], v[27:28], v[21:22]
	s_cbranch_vccnz .LBB0_17
	s_branch .LBB0_19
.LBB0_18:                               ;   in Loop: Header=BB0_4 Depth=2
	v_mov_b32_e32 v21, 0
	v_mov_b32_e32 v22, 0
.LBB0_19:                               ; %_Z10inner_prodPdS_i.exit
                                        ;   in Loop: Header=BB0_4 Depth=2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f64 v[19:20], v[19:20], v[21:22]
	s_mov_b32 s1, exec_lo
	v_cmpx_lt_f64_e32 0x3ff80000, v[19:20]
	s_cbranch_execz .LBB0_39
; %bb.20:                               ;   in Loop: Header=BB0_4 Depth=2
	v_ashrrev_i32_e32 v8, 31, v7
	s_and_b32 vcc_lo, exec_lo, s74
	s_cbranch_vccz .LBB0_35
; %bb.21:                               ; %.preheader.lr.ph
                                        ;   in Loop: Header=BB0_4 Depth=2
	v_add_f64 v[19:20], v[17:18], s[14:15]
	s_mov_b32 s64, 0
.LBB0_22:                               ; %.preheader
                                        ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_4 Depth=2
                                        ; =>    This Loop Header: Depth=3
                                        ;         Child Loop BB0_24 Depth 4
                                        ;           Child Loop BB0_26 Depth 5
	s_mov_b32 s65, s23
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[66:67], s[64:65], 2
	s_add_u32 s66, s2, s66
	s_addc_u32 s67, s3, s67
	global_load_b32 v0, v3, s[66:67]
	s_waitcnt vmcnt(0)
	v_cmp_gt_i32_e32 vcc_lo, 1, v0
	s_cbranch_vccnz .LBB0_33
; %bb.23:                               ; %.lr.ph217
                                        ;   in Loop: Header=BB0_22 Depth=3
	global_load_b64 v[21:22], v[13:14], off
	global_load_b64 v[23:24], v[15:16], off
	v_lshlrev_b64 v[25:26], 3, v[7:8]
	s_lshl_b64 s[68:69], s[64:65], 3
	s_mov_b32 s22, 0
	s_add_u32 s66, s8, s68
	s_addc_u32 s67, s9, s69
	s_waitcnt vmcnt(1)
	v_add_co_u32 v21, vcc_lo, v21, v25
	v_add_co_ci_u32_e32 v22, vcc_lo, v22, v26, vcc_lo
	s_waitcnt vmcnt(0)
	v_add_co_u32 v23, vcc_lo, v23, v25
	v_add_co_ci_u32_e32 v24, vcc_lo, v24, v26, vcc_lo
	global_load_b64 v[21:22], v[21:22], off
	global_load_b64 v[23:24], v[23:24], off
	s_waitcnt vmcnt(1)
	v_add_co_u32 v21, vcc_lo, v21, s68
	v_add_co_ci_u32_e32 v22, vcc_lo, s69, v22, vcc_lo
	s_waitcnt vmcnt(0)
	v_add_co_u32 v23, vcc_lo, v23, s68
	v_add_co_ci_u32_e32 v24, vcc_lo, s69, v24, vcc_lo
	global_load_b64 v[21:22], v[21:22], off
	global_load_b64 v[23:24], v[23:24], off
	s_load_b64 s[66:67], s[66:67], 0x0
	s_add_u32 s68, s6, s68
	s_addc_u32 s69, s7, s69
.LBB0_24:                               ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_4 Depth=2
                                        ;       Parent Loop BB0_22 Depth=3
                                        ; =>      This Loop Header: Depth=4
                                        ;           Child Loop BB0_26 Depth 5
	s_lshl_b64 s[76:77], s[22:23], 2
	s_lshl_b64 s[70:71], s[22:23], 3
	s_waitcnt lgkmcnt(0)
	s_add_u32 s76, s66, s76
	s_addc_u32 s77, s67, s77
	s_waitcnt vmcnt(1)
	v_add_co_u32 v25, vcc_lo, v21, s70
	global_load_b32 v2, v3, s[76:77]
	v_add_co_ci_u32_e32 v26, vcc_lo, s71, v22, vcc_lo
	s_mov_b32 s76, s23
	s_mov_b32 s77, s23
	s_waitcnt vmcnt(1)
	v_add_co_u32 v27, s0, v23, s70
	v_dual_mov_b32 v29, s76 :: v_dual_mov_b32 v30, s77
	v_add_co_ci_u32_e64 v28, s0, s71, v24, s0
	global_store_b64 v[25:26], v[29:30], off
	global_store_b64 v[27:28], v[29:30], off
	s_waitcnt vmcnt(0)
	v_cmp_gt_i32_e32 vcc_lo, 1, v2
	s_cbranch_vccnz .LBB0_32
; %bb.25:                               ; %.lr.ph214
                                        ;   in Loop: Header=BB0_24 Depth=4
	s_load_b64 s[76:77], s[68:69], 0x0
	s_waitcnt lgkmcnt(0)
	s_add_u32 s70, s76, s70
	s_addc_u32 s71, s77, s71
	s_load_b64 s[70:71], s[70:71], 0x0
.LBB0_26:                               ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_4 Depth=2
                                        ;       Parent Loop BB0_22 Depth=3
                                        ;         Parent Loop BB0_24 Depth=4
                                        ; =>        This Inner Loop Header: Depth=5
	s_waitcnt lgkmcnt(0)
	global_load_b64 v[29:30], v3, s[70:71]
	s_waitcnt vmcnt(0)
	v_add_f64 v[29:30], v[19:20], -v[29:30]
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_f64_e32 vcc_lo, 0, v[29:30]
	s_cbranch_vccnz .LBB0_28
; %bb.27:                               ; %_Z8postkernd.exit
                                        ;   in Loop: Header=BB0_26 Depth=5
	v_mul_f64 v[31:32], v[29:30], s[24:25]
	global_load_b64 v[37:38], v[25:26], off
	v_cmp_ngt_f64_e32 vcc_lo, 0xc0900000, v[29:30]
	v_cmp_nlt_f64_e64 s0, 0x4090cc00, v[29:30]
	v_rndne_f64_e32 v[31:32], v[31:32]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f64 v[33:34], v[31:32], s[34:35], -v[29:30]
	v_cvt_i32_f64_e32 v4, v[31:32]
	v_fma_f64 v[33:34], v[31:32], s[36:37], v[33:34]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[35:36], v[33:34], s[40:41], s[38:39]
	v_fma_f64 v[35:36], v[33:34], v[35:36], s[44:45]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[35:36], v[33:34], v[35:36], s[46:47]
	v_fma_f64 v[35:36], v[33:34], v[35:36], s[48:49]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[35:36], v[33:34], v[35:36], s[50:51]
	v_fma_f64 v[35:36], v[33:34], v[35:36], s[52:53]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[35:36], v[33:34], v[35:36], s[54:55]
	v_fma_f64 v[35:36], v[33:34], v[35:36], s[56:57]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[35:36], v[33:34], v[35:36], s[58:59]
	v_fma_f64 v[35:36], v[33:34], v[35:36], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[31:32], v[33:34], v[35:36], 1.0
	v_ldexp_f64 v[31:32], v[31:32], v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v4, 0x7ff00000, v32, vcc_lo
	s_and_b32 vcc_lo, s0, vcc_lo
	v_cndmask_b32_e32 v29, 0, v31, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v4, 0, v4, s0
	s_mov_b32 s0, 0
	v_xor_b32_e32 v30, 0x80000000, v4
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[31:32], -v[29:30], v[37:38]
	s_branch .LBB0_29
.LBB0_28:                               ;   in Loop: Header=BB0_26 Depth=5
	s_mov_b32 s0, -1
                                        ; implicit-def: $vgpr29_vgpr30
                                        ; implicit-def: $vgpr31_vgpr32
.LBB0_29:                               ; %Flow
                                        ;   in Loop: Header=BB0_26 Depth=5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccnz .LBB0_31
; %bb.30:                               ; %_Z9dpostkernd.exit.critedge
                                        ;   in Loop: Header=BB0_26 Depth=5
	global_load_b64 v[29:30], v[25:26], off
	s_waitcnt vmcnt(0)
	v_add_f64 v[31:32], v[29:30], 0
	v_mov_b32_e32 v29, 0
	v_mov_b32_e32 v30, 0
.LBB0_31:                               ; %_Z9dpostkernd.exit
                                        ;   in Loop: Header=BB0_26 Depth=5
	global_store_b64 v[25:26], v[31:32], off
	global_load_b64 v[31:32], v[27:28], off
	v_add_nc_u32_e32 v2, -1, v2
	s_add_u32 s70, s70, 8
	s_addc_u32 s71, s71, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_eq_u32_e32 vcc_lo, 0, v2
	s_waitcnt vmcnt(0)
	v_add_f64 v[29:30], v[29:30], v[31:32]
	global_store_b64 v[27:28], v[29:30], off
	s_cbranch_vccz .LBB0_26
.LBB0_32:                               ; %._crit_edge215
                                        ;   in Loop: Header=BB0_24 Depth=4
	s_add_i32 s22, s22, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	v_cmp_eq_u32_e32 vcc_lo, s22, v0
	s_cbranch_vccz .LBB0_24
.LBB0_33:                               ; %._crit_edge218
                                        ;   in Loop: Header=BB0_22 Depth=3
	s_add_i32 s64, s64, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s64, s12
	s_cbranch_scc0 .LBB0_22
; %bb.34:                               ; %Flow296
                                        ;   in Loop: Header=BB0_4 Depth=2
	s_mov_b32 s0, 0
	s_branch .LBB0_36
.LBB0_35:                               ;   in Loop: Header=BB0_4 Depth=2
	s_mov_b32 s0, -1
                                        ; implicit-def: $vgpr19_vgpr20
.LBB0_36:                               ; %Flow297
                                        ;   in Loop: Header=BB0_4 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccz .LBB0_38
; %bb.37:                               ; %..loopexit_crit_edge
                                        ;   in Loop: Header=BB0_4 Depth=2
	v_add_f64 v[19:20], v[17:18], s[14:15]
.LBB0_38:                               ; %.loopexit
                                        ;   in Loop: Header=BB0_4 Depth=2
	s_load_b64 s[64:65], s[28:29], 0x0
	v_lshlrev_b64 v[23:24], 3, v[7:8]
	v_add_nc_u32_e32 v7, 1, v7
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v21, vcc_lo, s64, v9
	v_add_co_ci_u32_e32 v22, vcc_lo, s65, v10, vcc_lo
	global_load_b64 v[21:22], v[21:22], off
	s_waitcnt vmcnt(0)
	v_add_co_u32 v21, vcc_lo, v21, v23
	v_add_co_ci_u32_e32 v22, vcc_lo, v22, v24, vcc_lo
	global_store_b64 v[21:22], v[19:20], off
	global_store_b32 v[5:6], v7, off
.LBB0_39:                               ; %Flow298
                                        ;   in Loop: Header=BB0_4 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
.LBB0_40:                               ;   in Loop: Header=BB0_4 Depth=2
	v_add_f64 v[17:18], v[17:18], s[14:15]
	s_add_i32 s62, s62, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s62, s13
	s_cbranch_scc0 .LBB0_4
; %bb.41:                               ; %._crit_edge223.loopexit
                                        ;   in Loop: Header=BB0_2 Depth=1
	global_load_b32 v0, v3, s[20:21]
.LBB0_42:                               ; %._crit_edge223
                                        ;   in Loop: Header=BB0_2 Depth=1
	v_add_nc_u32_e32 v1, s73, v1
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_ge_i32_e32 vcc_lo, v1, v0
	s_or_b32 s75, vcc_lo, s75
	s_and_not1_b32 exec_lo, exec_lo, s75
	s_cbranch_execnz .LBB0_2
.LBB0_43:                               ; %._crit_edge225
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z15par_c_main_loopPPPdS1_PPiS1_S2_iidiPS1_S4_b
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 344
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 39
		.amdhsa_next_free_sgpr 78
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z15par_c_main_loopPPPdS1_PPiS1_S2_iidiPS1_S4_b, .Lfunc_end0-_Z15par_c_main_loopPPPdS1_PPiS1_S2_iidiPS1_S4_b
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 2436
; NumSgprs: 80
; NumVgprs: 39
; ScratchSize: 0
; MemoryBound: 1
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 9
; VGPRBlocks: 4
; NumSGPRsForWavesPerEU: 80
; NumVGPRsForWavesPerEU: 39
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .offset:         40
        .size:           4
        .value_kind:     by_value
      - .offset:         44
        .size:           4
        .value_kind:     by_value
      - .offset:         48
        .size:           8
        .value_kind:     by_value
      - .offset:         56
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         64
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         72
        .size:           8
        .value_kind:     global_buffer
      - .offset:         80
        .size:           1
        .value_kind:     by_value
      - .offset:         88
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         92
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         96
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         100
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         102
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         104
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         106
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         108
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         110
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         128
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         136
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         144
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         152
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 344
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z15par_c_main_loopPPPdS1_PPiS1_S2_iidiPS1_S4_b
    .private_segment_fixed_size: 0
    .sgpr_count:     80
    .sgpr_spill_count: 0
    .symbol:         _Z15par_c_main_loopPPPdS1_PPiS1_S2_iidiPS1_S4_b.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     39
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
