//
// Created by saleh on 7/23/18.
//
#include <stdio.h>
#include <cuda_runtime_api.h>
#include <vector_types.h>

#define BLOCK_SIZE 256

// reduce sum over specific axis
__global__ void kernel_reduce_sum_3d_try01(const float * __restrict__ g_idata,
                                           float * __restrict__ g_odata,
                                           int dim0, int dim1, int dim2,
                                           int overaxis0, int overaxis1,int overaxis2) {
    // dim0, dim1, dim2 : TTT, TFF, FTF, FFT

    if(overaxis0==1 && overaxis1==0 && overaxis2==0){ // TFF
        /* Each thread handles 4 pairs of elements.
         * BlockDim is 1D
         * BlockDim should be dividable by 4
         *
         * */

        // static shared memory
        __shared__ float smem[BLOCK_SIZE*4];

        // set thread ID
        //unsigned int tid = threadIdx.x;
        unsigned int tid4 = 4 * threadIdx.x;

        // global index
        unsigned int idx4 = 4 * (blockIdx.x * blockDim.x + threadIdx.x);

        // unrolling
        float tmpSum0 = 0;
        float tmpSum1 = 0;
        float tmpSum2 = 0;
        float tmpSum3 = 0;
        int offset = dim1*dim2;
        int i=0;


        for(i=0;i<dim0;i++){
            if(idx4 + 0 <= offset) tmpSum0 += g_idata[idx4 + i*offset + 0];
            if(idx4 + 1 <= offset) tmpSum1 += g_idata[idx4 + i*offset + 1];
            if(idx4 + 2 <= offset) tmpSum2 += g_idata[idx4 + i*offset + 2];
            if(idx4 + 3 <= offset) tmpSum3 += g_idata[idx4 + i*offset + 3];
        }


        if(idx4 + 0 <= offset) smem[tid4 + 0] = tmpSum0;
        if(idx4 + 1 <= offset) smem[tid4 + 1] = tmpSum1;
        if(idx4 + 2 <= offset) smem[tid4 + 2] = tmpSum2;
        if(idx4 + 3 <= offset) smem[tid4 + 3] = tmpSum3;
        __syncthreads();

        unsigned int oindx = idx4;
        if(idx4 + 0 <= offset) g_odata[oindx + 0] = smem[tid4 + 0];
        if(idx4 + 1 <= offset) g_odata[oindx + 1] = smem[tid4 + 1];
        if(idx4 + 2 <= offset) g_odata[oindx + 2] = smem[tid4 + 2];
        if(idx4 + 3 <= offset) g_odata[oindx + 3] = smem[tid4 + 3];

    }

}

void reduce_sum_3d_try01(
        float*  g_idata,
        float*  g_odata,
        int dim0,
        int dim1,
        int dim2,
        int overaxis0,
        int overaxis1,
        int overaxis2)
{
    dim3 block (BLOCK_SIZE, 1);
    dim3 grid_overdim0  ((dim1*dim2 + block.x - 1) / block.x / 4, 1);
    dim3 grid_overdim1  ((dim0*dim2 + block.x - 1) / block.x / 4, 1);
    dim3 grid_overdim2  ((dim0*dim1 + block.x - 1) / block.x / 4, 1);

    dim3 grid = (overaxis0==1)?(grid_overdim0):(overaxis1==1?grid_overdim1:grid_overdim2);

    kernel_reduce_sum_3d_try01 <<< grid, block >>> (
            g_idata,
            g_odata,
            dim0, dim1, dim2,
            overaxis0, overaxis1,overaxis2);
}




__global__ void kernel_reduce_sum_3d_try02(
        const float*  __restrict__ g_idata,
        float*  __restrict__ g_odata,
        int dim0,
        int dim1,
        int dim2,
        int overaxis0,
        int overaxis1,
        int overaxis2)
{
    if (overaxis0 == 0 && overaxis1 == 1 && overaxis2 == 0) { // FTF
        /* Each thread handles 1 pairs of elements.
         * BlockDim is 1D
         * BlockDim should be dividable by 1
         *
         * */

        // static shared memory
        __shared__ float smem_store[BLOCK_SIZE];
        //__shared__ float smem_load[BLOCK_SIZE];

        // set thread ID
        //unsigned int tid = threadIdx.x;
        unsigned int tid =  threadIdx.x;

        // global index
        unsigned int idx = (blockIdx.x * blockDim.x + threadIdx.x);

        // unrolling
        float tmpSum0 = 0;
        unsigned int i = 0;
        unsigned int src_index ;
        unsigned int _limit = (unsigned int)(dim0 * dim1 * dim2);

        //Indices over output's matrix (NOT OVER INPUT) (OUTPUT'S CONSIDERED AS A ROW-MAJOR MATRIX)
        int thrd_d0 = (idx) / (1*dim2);
        int thrd_d2 = (idx - thrd_d0*dim2);

        //Only for debugging kernel
        //printf("tid: %03d \tidx: %03d\td0: %02d\td2: %02d\n",tid,idx,thrd_d0,thrd_d2);



        //Merging the thread's DIM1 element from all DIM1's elements of current DIM0.
        for (i = 0; i < dim1; i++) {
            src_index = thrd_d0*dim1*dim2 + i * dim2 + thrd_d2;
            printf("idx: %d : src_index: %d\n",idx,src_index);
            if(src_index < _limit)
                tmpSum0 += g_idata[src_index];
        }


        if (src_index + 0 < _limit) smem_store[tid + 0] = tmpSum0;
        __syncthreads();

        unsigned int oindx = (unsigned int)( thrd_d0*dim2 + thrd_d2 );
        if (src_index + 0 <= _limit) g_odata[oindx + 0] = smem_store[tid + 0];

    }
    else
    {
        if (overaxis0 == 0 && overaxis1 == 0 && overaxis2 == 1) { // FFT
            /* Each thread handles 1 pairs of elements.
             * BlockDim is 1D
             * BlockDim should be dividable by 1
             *
             * */

            // static shared memory
            __shared__ float smem_store[BLOCK_SIZE];

            // set thread ID
            //unsigned int tid = threadIdx.x;
            unsigned int tid =  threadIdx.x;

            // global index
            unsigned int idx = (blockIdx.x * blockDim.x + threadIdx.x);

            // unrolling
            float tmpSum0 = 0;
            unsigned int i = 0;
            unsigned int src_index ;
            unsigned int _limit = (unsigned int)(dim0 * dim1 * dim2);

            //Indices over output's matrix (NOT OVER INPUT) (OUTPUT'S CONSIDERED AS A ROW-MAJOR MATRIX)
            int thrd_d0 = (idx) / (dim1*1);
            int thrd_d1 = (idx - thrd_d0*dim1);

            //Only for debugging kernel
            printf("tid: %03d \tidx: %03d\td0: %02d\td1: %02d\n",tid,idx,thrd_d0,thrd_d1);


            //Merging the thread's DIM1 element from all DIM1's elements of current DIM0.
            for (i = 0; i < dim2; i++) {
                src_index = thrd_d0*dim1*dim2 + thrd_d1 * dim2 + i;
                if(idx<15) printf("idx: %d : src_index: %d\n",idx,src_index);
                if(src_index < _limit)
                    tmpSum0 += g_idata[src_index];
            }


            if (src_index + 0 < _limit) smem_store[tid + 0] = tmpSum0;
            __syncthreads();

            unsigned int oindx = (unsigned int)( thrd_d0*dim1 + thrd_d1 );
            if (src_index + 0 <= _limit) g_odata[oindx + 0] = smem_store[tid + 0];

        }
    }

}

void reduce_sum_3d_try02(
        float* g_idata,
        float* g_odata,
        int dim0,
        int dim1,
        int dim2,
        int overaxis0,
        int overaxis1,
        int overaxis2)
{
    dim3 block (BLOCK_SIZE, 1);
    dim3 grid_overdim0  ((dim1*dim2 + block.x - 1) / block.x, 1);
    dim3 grid_overdim1  ((dim0*dim2 + block.x - 1) / block.x, 1);
    dim3 grid_overdim2  ((dim0*dim1 + block.x - 1) / block.x, 1);

    dim3 grid = (overaxis0==1)?(grid_overdim0):(overaxis1==1?grid_overdim1:grid_overdim2);

    kernel_reduce_sum_3d_try02 <<< grid, block >>> (
            g_idata,
            g_odata,
            dim0, dim1, dim2,
            overaxis0, overaxis1,overaxis2);
}



__global__ void kernel_reduce_sum_3d_try03(
        const float * __restrict__  g_idata,
        float * __restrict__  g_odata,
        const unsigned int dim0,
        const unsigned int dim1,
        const unsigned int dim2,
        const bool overaxis0,
        const bool overaxis1,
        const bool overaxis2)
{
    // WANING : dim0 means dim2 and dim2 means dim0
    __shared__ float sm[BLOCK_SIZE];
    if (overaxis2 && !overaxis1 && !overaxis0)
    {
        // Case 1 - sums in X-direction
        // each threadblock is responsible for a separate row sum
        unsigned int bidx = blockIdx.x;
        unsigned int tidx = threadIdx.x;
        sm[threadIdx.x] = 0;
        while (tidx < dim0)
        {
            sm[threadIdx.x] += g_idata[bidx*dim0+tidx];
            /*if(bidx==21){
                //dbg
                printf("thid: %04d\tg_index_to_read:%d\n",threadIdx.x,bidx*dim0+tidx);
            }*/
            tidx += blockDim.x;
        } // block-stride loop

        __syncthreads();

        // parallel reduction
        for (int i = blockDim.x>>1; i > 0; i>>=1)
        {
            if (threadIdx.x < i) sm[threadIdx.x] += sm[threadIdx.x + i];
            __syncthreads();
        }

        if (!threadIdx.x) g_odata[bidx] = sm[0];
    }
    else if (!overaxis2 && overaxis1 && !overaxis0)
    {
        // Case 2 - sums in Y-direction
        // each thread is responsible for a separate Y-column sum
        unsigned int idx = threadIdx.x+blockDim.x*blockIdx.x;
        if (idx < (dim0*dim2))
        {
            unsigned int tidx = idx%dim0 + (idx/dim0)*(dim0*dim1); //indices over input tensor (begining of axis1 slices)

            float tsum = 0;

            for (unsigned int i = 0; i < dim1; i++)
            {
                //printf("idx: %03d \t\t tidx: %03d\n",idx,tidx);
                tsum += g_idata[tidx];
                tidx += dim0;
            }

            g_odata[idx] = tsum;
        }
    }
    else if (!overaxis2 && !overaxis1 && overaxis0)
    {
        // Case 3 - sums in Z-direction
        // each thread is responsible for a separate Z-column sum

        unsigned int idx = threadIdx.x + blockDim.x*blockIdx.x;

        //printf("%d,%d,%d\n",dbg_blockid,dbg_thid,idx);


        if (idx < (dim0*dim1))
        {
            unsigned int tidx = idx;
            float tsum = 0;

            for (int i = 0; i < dim2; i++)
            {
                //printf("%d,%d,%d,%d,%d\n",dbg_blockid,dbg_thid,idx,tidx,i);
                //printf("idx:%02d, tidx:%02d, i=%02d\n",idx,tidx,i);
                tsum += g_idata[tidx];
                tidx += dim0*dim1;
            }

            g_odata[idx] = tsum;
        }
    }
    else {
        printf("reduce_sum: ERROR-NOTIMPLEMENTED\n");
    }




}



void reduce_sum_3d_try03(
        float* g_idata,
        float* g_odata,
        int dim0,
        int dim1,
        int dim2,
        bool overaxis0,
        bool overaxis1,
        bool overaxis2)
{
    dim3 block (BLOCK_SIZE, 1);
    dim3 grid_overdim0  ((dim1*dim2 + block.x - 1) / block.x, 1);
    dim3 grid_overdim1  ((dim0*dim2 + block.x - 1) / block.x, 1);
    dim3 grid_overdim2  (dim0*dim1 , 1);

    dim3 grid = overaxis0 ? (grid_overdim0) : (overaxis1 ? grid_overdim1 : grid_overdim2);

    //printf("-------------------------------------------------------\n");
    //printf("KERNEL_GRID  : %d\n", grid.x);
    //printf("KERNEL_BLOCK : %d\n", block.x);

    kernel_reduce_sum_3d_try03 <<<grid, block>>> (
            g_idata, g_odata,
            dim2, dim1, dim0,
            overaxis0, overaxis1,overaxis2);


}
	.file	"tmpxft_0037b188_00000000-6_reduce_sum_3d.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2032:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2032:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z55__device_stub__Z26kernel_reduce_sum_3d_try01PKfPfiiiiiiPKfPfiiiiii
	.type	_Z55__device_stub__Z26kernel_reduce_sum_3d_try01PKfPfiiiiiiPKfPfiiiiii, @function
_Z55__device_stub__Z26kernel_reduce_sum_3d_try01PKfPfiiiiiiPKfPfiiiiii:
.LFB2054:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	48(%rsp), %rcx
	movl	%r8d, 4(%rsp)
	movl	%r9d, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rax, 104(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 136(%rsp)
	movq	%rsp, %rax
	movq	%rax, 144(%rsp)
	leaq	192(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	200(%rsp), %rax
	movq	%rsi, 32(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movl	$1, 64(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	48(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z26kernel_reduce_sum_3d_try01PKfPfiiiiii(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 208
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L2:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2054:
	.size	_Z55__device_stub__Z26kernel_reduce_sum_3d_try01PKfPfiiiiiiPKfPfiiiiii, .-_Z55__device_stub__Z26kernel_reduce_sum_3d_try01PKfPfiiiiiiPKfPfiiiiii
	.globl	_Z26kernel_reduce_sum_3d_try01PKfPfiiiiii
	.type	_Z26kernel_reduce_sum_3d_try01PKfPfiiiiii, @function
_Z26kernel_reduce_sum_3d_try01PKfPfiiiiii:
.LFB2055:
	.cfi_startproc
	endbr64
	jmp	_Z55__device_stub__Z26kernel_reduce_sum_3d_try01PKfPfiiiiiiPKfPfiiiiii
	.cfi_endproc
.LFE2055:
	.size	_Z26kernel_reduce_sum_3d_try01PKfPfiiiiii, .-_Z26kernel_reduce_sum_3d_try01PKfPfiiiiii
	.globl	_Z19reduce_sum_3d_try01PfS_iiiiii
	.type	_Z19reduce_sum_3d_try01PfS_iiiiii, @function
_Z19reduce_sum_3d_try01PfS_iiiiii:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movl	%r9d, %r13d
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movl	%r8d, %r12d
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movl	%ecx, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movl	%edx, %ebx
	movabsq	$4294967297, %rdx
	subq	$104, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, (%rsp)
	movl	160(%rsp), %r14d
	movq	%rsi, 8(%rsp)
	movl	168(%rsp), %r15d
	movq	%fs:40, %rax
	movq	%rax, 88(%rsp)
	xorl	%eax, %eax
	movl	%ecx, %eax
	movq	%rdx, 32(%rsp)
	imull	%r8d, %eax
	movq	%rdx, 44(%rsp)
	movq	%rdx, 56(%rsp)
	movq	%rdx, 68(%rsp)
	addl	$255, %eax
	shrl	$10, %eax
	movl	%eax, 40(%rsp)
	movl	%r8d, %eax
	imull	%ebx, %eax
	addl	$255, %eax
	shrl	$10, %eax
	movl	%eax, 52(%rsp)
	movl	%ecx, %eax
	imull	%ebx, %eax
	addl	$255, %eax
	shrl	$10, %eax
	decl	%r9d
	movl	%eax, 64(%rsp)
	leaq	40(%rsp), %rax
	je	.L9
	leaq	64(%rsp), %rax
	cmpl	$1, %r14d
	jne	.L9
	leaq	52(%rsp), %rax
.L9:
	movq	(%rax), %rdi
	movl	8(%rax), %esi
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$256, 28(%rsp)
	movl	36(%rsp), %ecx
	movq	28(%rsp), %rdx
	movq	%rdi, 76(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L8
	movq	88(%rsp), %rax
	subq	%fs:40, %rax
	jne	.L16
	movl	%r15d, 168(%rsp)
	movq	(%rsp), %rdi
	movl	%ebp, %ecx
	movl	%ebx, %edx
	movl	%r14d, 160(%rsp)
	movq	8(%rsp), %rsi
	addq	$104, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 56
	movl	%r13d, %r9d
	popq	%rbx
	.cfi_def_cfa_offset 48
	movl	%r12d, %r8d
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	_Z55__device_stub__Z26kernel_reduce_sum_3d_try01PKfPfiiiiiiPKfPfiiiiii
.L8:
	.cfi_restore_state
	movq	88(%rsp), %rax
	subq	%fs:40, %rax
	je	.L12
.L16:
	call	__stack_chk_fail@PLT
.L12:
	addq	$104, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2027:
	.size	_Z19reduce_sum_3d_try01PfS_iiiiii, .-_Z19reduce_sum_3d_try01PfS_iiiiii
	.globl	_Z55__device_stub__Z26kernel_reduce_sum_3d_try02PKfPfiiiiiiPKfPfiiiiii
	.type	_Z55__device_stub__Z26kernel_reduce_sum_3d_try02PKfPfiiiiiiPKfPfiiiiii, @function
_Z55__device_stub__Z26kernel_reduce_sum_3d_try02PKfPfiiiiiiPKfPfiiiiii:
.LFB2056:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	48(%rsp), %rcx
	movl	%r8d, 4(%rsp)
	movl	%r9d, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rax, 104(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 136(%rsp)
	movq	%rsp, %rax
	movq	%rax, 144(%rsp)
	leaq	192(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	200(%rsp), %rax
	movq	%rsi, 32(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movl	$1, 64(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L17
	pushq	48(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z26kernel_reduce_sum_3d_try02PKfPfiiiiii(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 208
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L17:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L19
	call	__stack_chk_fail@PLT
.L19:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2056:
	.size	_Z55__device_stub__Z26kernel_reduce_sum_3d_try02PKfPfiiiiiiPKfPfiiiiii, .-_Z55__device_stub__Z26kernel_reduce_sum_3d_try02PKfPfiiiiiiPKfPfiiiiii
	.globl	_Z26kernel_reduce_sum_3d_try02PKfPfiiiiii
	.type	_Z26kernel_reduce_sum_3d_try02PKfPfiiiiii, @function
_Z26kernel_reduce_sum_3d_try02PKfPfiiiiii:
.LFB2057:
	.cfi_startproc
	endbr64
	jmp	_Z55__device_stub__Z26kernel_reduce_sum_3d_try02PKfPfiiiiiiPKfPfiiiiii
	.cfi_endproc
.LFE2057:
	.size	_Z26kernel_reduce_sum_3d_try02PKfPfiiiiii, .-_Z26kernel_reduce_sum_3d_try02PKfPfiiiiii
	.globl	_Z19reduce_sum_3d_try02PfS_iiiiii
	.type	_Z19reduce_sum_3d_try02PfS_iiiiii, @function
_Z19reduce_sum_3d_try02PfS_iiiiii:
.LFB2028:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movl	%r9d, %r13d
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movl	%r8d, %r12d
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movl	%ecx, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movl	%edx, %ebx
	movabsq	$4294967297, %rdx
	subq	$104, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, (%rsp)
	movl	160(%rsp), %r14d
	movq	%rsi, 8(%rsp)
	movl	168(%rsp), %r15d
	movq	%fs:40, %rax
	movq	%rax, 88(%rsp)
	xorl	%eax, %eax
	movl	%ecx, %eax
	movq	%rdx, 32(%rsp)
	imull	%r8d, %eax
	movq	%rdx, 44(%rsp)
	movq	%rdx, 56(%rsp)
	movq	%rdx, 68(%rsp)
	addl	$255, %eax
	shrl	$8, %eax
	movl	%eax, 40(%rsp)
	movl	%r8d, %eax
	imull	%ebx, %eax
	addl	$255, %eax
	shrl	$8, %eax
	movl	%eax, 52(%rsp)
	movl	%ecx, %eax
	imull	%ebx, %eax
	addl	$255, %eax
	shrl	$8, %eax
	decl	%r9d
	movl	%eax, 64(%rsp)
	leaq	40(%rsp), %rax
	je	.L23
	leaq	64(%rsp), %rax
	cmpl	$1, %r14d
	jne	.L23
	leaq	52(%rsp), %rax
.L23:
	movq	(%rax), %rdi
	movl	8(%rax), %esi
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$256, 28(%rsp)
	movl	36(%rsp), %ecx
	movq	28(%rsp), %rdx
	movq	%rdi, 76(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L22
	movq	88(%rsp), %rax
	subq	%fs:40, %rax
	jne	.L30
	movl	%r15d, 168(%rsp)
	movq	(%rsp), %rdi
	movl	%ebp, %ecx
	movl	%ebx, %edx
	movl	%r14d, 160(%rsp)
	movq	8(%rsp), %rsi
	addq	$104, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 56
	movl	%r13d, %r9d
	popq	%rbx
	.cfi_def_cfa_offset 48
	movl	%r12d, %r8d
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	_Z55__device_stub__Z26kernel_reduce_sum_3d_try02PKfPfiiiiiiPKfPfiiiiii
.L22:
	.cfi_restore_state
	movq	88(%rsp), %rax
	subq	%fs:40, %rax
	je	.L26
.L30:
	call	__stack_chk_fail@PLT
.L26:
	addq	$104, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2028:
	.size	_Z19reduce_sum_3d_try02PfS_iiiiii, .-_Z19reduce_sum_3d_try02PfS_iiiiii
	.globl	_Z55__device_stub__Z26kernel_reduce_sum_3d_try03PKfPfjjjbbbPKfPfjjjbbb
	.type	_Z55__device_stub__Z26kernel_reduce_sum_3d_try03PKfPfjjjbbbPKfPfjjjbbb, @function
_Z55__device_stub__Z26kernel_reduce_sum_3d_try03PKfPfjjjbbbPKfPfjjjbbb:
.LFB2058:
	.cfi_startproc
	endbr64
	subq	$200, %rsp
	.cfi_def_cfa_offset 208
	movl	208(%rsp), %eax
	movl	%edx, 28(%rsp)
	leaq	56(%rsp), %rdx
	movl	%ecx, 24(%rsp)
	leaq	64(%rsp), %rcx
	movb	%al, 12(%rsp)
	movl	216(%rsp), %eax
	movl	%r8d, 20(%rsp)
	movb	%r9b, 16(%rsp)
	movb	%al, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 184(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rax, 120(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	28(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	8(%rsp), %rax
	movq	%rsi, 48(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rax, 176(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movl	$1, 80(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L31
	pushq	64(%rsp)
	.cfi_def_cfa_offset 216
	leaq	_Z26kernel_reduce_sum_3d_try03PKfPfjjjbbb(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 224
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 216
	popq	%rdx
	.cfi_def_cfa_offset 208
.L31:
	movq	184(%rsp), %rax
	subq	%fs:40, %rax
	je	.L33
	call	__stack_chk_fail@PLT
.L33:
	addq	$200, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2058:
	.size	_Z55__device_stub__Z26kernel_reduce_sum_3d_try03PKfPfjjjbbbPKfPfjjjbbb, .-_Z55__device_stub__Z26kernel_reduce_sum_3d_try03PKfPfjjjbbbPKfPfjjjbbb
	.globl	_Z26kernel_reduce_sum_3d_try03PKfPfjjjbbb
	.type	_Z26kernel_reduce_sum_3d_try03PKfPfjjjbbb, @function
_Z26kernel_reduce_sum_3d_try03PKfPfjjjbbb:
.LFB2059:
	.cfi_startproc
	endbr64
	movzbl	16(%rsp), %eax
	movzbl	%r9b, %r9d
	movl	%eax, 16(%rsp)
	movzbl	8(%rsp), %eax
	movl	%eax, 8(%rsp)
	jmp	_Z55__device_stub__Z26kernel_reduce_sum_3d_try03PKfPfjjjbbbPKfPfjjjbbb
	.cfi_endproc
.LFE2059:
	.size	_Z26kernel_reduce_sum_3d_try03PKfPfjjjbbb, .-_Z26kernel_reduce_sum_3d_try03PKfPfjjjbbb
	.globl	_Z19reduce_sum_3d_try03PfS_iiibbb
	.type	_Z19reduce_sum_3d_try03PfS_iiibbb, @function
_Z19reduce_sum_3d_try03PfS_iiibbb:
.LFB2029:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movl	%r9d, %r13d
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movl	%edx, %r12d
	movabsq	$4294967297, %rdx
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movl	%ecx, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movl	%r8d, %ebx
	subq	$104, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, (%rsp)
	movl	160(%rsp), %r14d
	movq	%rsi, 8(%rsp)
	movl	168(%rsp), %r15d
	movq	%fs:40, %rax
	movq	%rax, 88(%rsp)
	xorl	%eax, %eax
	movl	%ecx, %eax
	movq	%rdx, 32(%rsp)
	imull	%r8d, %eax
	movq	%rdx, 44(%rsp)
	movq	%rdx, 56(%rsp)
	movq	%rdx, 68(%rsp)
	addl	$255, %eax
	shrl	$8, %eax
	movl	%eax, 40(%rsp)
	movl	%r8d, %eax
	imull	%r12d, %eax
	addl	$255, %eax
	shrl	$8, %eax
	movl	%eax, 52(%rsp)
	movl	%ecx, %eax
	imull	%r12d, %eax
	movl	%eax, 64(%rsp)
	leaq	40(%rsp), %rax
	testb	%r9b, %r9b
	jne	.L37
	leaq	64(%rsp), %rax
	testb	%r14b, %r14b
	je	.L37
	leaq	52(%rsp), %rax
.L37:
	movq	(%rax), %rdi
	movl	8(%rax), %esi
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$256, 28(%rsp)
	movl	36(%rsp), %ecx
	movq	28(%rsp), %rdx
	movq	%rdi, 76(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L36
	movq	88(%rsp), %rax
	subq	%fs:40, %rax
	jne	.L44
	movzbl	%r15b, %r15d
	movzbl	%r14b, %r11d
	movq	8(%rsp), %rsi
	movl	%r12d, %r8d
	movl	%r15d, 168(%rsp)
	movq	(%rsp), %rdi
	movl	%ebp, %ecx
	movl	%ebx, %edx
	movl	%r11d, 160(%rsp)
	addq	$104, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 56
	movzbl	%r13b, %r9d
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	_Z55__device_stub__Z26kernel_reduce_sum_3d_try03PKfPfjjjbbbPKfPfjjjbbb
.L36:
	.cfi_restore_state
	movq	88(%rsp), %rax
	subq	%fs:40, %rax
	je	.L40
.L44:
	call	__stack_chk_fail@PLT
.L40:
	addq	$104, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2029:
	.size	_Z19reduce_sum_3d_try03PfS_iiibbb, .-_Z19reduce_sum_3d_try03PfS_iiibbb
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z26kernel_reduce_sum_3d_try03PKfPfjjjbbb"
.LC1:
	.string	"_Z26kernel_reduce_sum_3d_try02PKfPfiiiiii"
.LC2:
	.string	"_Z26kernel_reduce_sum_3d_try01PKfPfiiiiii"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2061:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z26kernel_reduce_sum_3d_try03PKfPfjjjbbb(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC1(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z26kernel_reduce_sum_3d_try02PKfPfiiiiii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC2(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z26kernel_reduce_sum_3d_try01PKfPfiiiiii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2061:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

//
// Created by saleh on 7/23/18.
//

#include <hip/hip_runtime.h>
#include <stdio.h>
#include <hip/hip_runtime_api.h>
#include <hip/hip_vector_types.h>

#define BLOCK_SIZE 256

// reduce sum over specific axis
__global__ void kernel_reduce_sum_3d_try01(const float * __restrict__ g_idata,
                                           float * __restrict__ g_odata,
                                           int dim0, int dim1, int dim2,
                                           int overaxis0, int overaxis1,int overaxis2) {
    // dim0, dim1, dim2 : TTT, TFF, FTF, FFT

    if(overaxis0==1 && overaxis1==0 && overaxis2==0){ // TFF
        /* Each thread handles 4 pairs of elements.
         * BlockDim is 1D
         * BlockDim should be dividable by 4
         *
         * */

        // static shared memory
        __shared__ float smem[BLOCK_SIZE*4];

        // set thread ID
        //unsigned int tid = threadIdx.x;
        unsigned int tid4 = 4 * threadIdx.x;

        // global index
        unsigned int idx4 = 4 * (blockIdx.x * blockDim.x + threadIdx.x);

        // unrolling
        float tmpSum0 = 0;
        float tmpSum1 = 0;
        float tmpSum2 = 0;
        float tmpSum3 = 0;
        int offset = dim1*dim2;
        int i=0;


        for(i=0;i<dim0;i++){
            if(idx4 + 0 <= offset) tmpSum0 += g_idata[idx4 + i*offset + 0];
            if(idx4 + 1 <= offset) tmpSum1 += g_idata[idx4 + i*offset + 1];
            if(idx4 + 2 <= offset) tmpSum2 += g_idata[idx4 + i*offset + 2];
            if(idx4 + 3 <= offset) tmpSum3 += g_idata[idx4 + i*offset + 3];
        }


        if(idx4 + 0 <= offset) smem[tid4 + 0] = tmpSum0;
        if(idx4 + 1 <= offset) smem[tid4 + 1] = tmpSum1;
        if(idx4 + 2 <= offset) smem[tid4 + 2] = tmpSum2;
        if(idx4 + 3 <= offset) smem[tid4 + 3] = tmpSum3;
        __syncthreads();

        unsigned int oindx = idx4;
        if(idx4 + 0 <= offset) g_odata[oindx + 0] = smem[tid4 + 0];
        if(idx4 + 1 <= offset) g_odata[oindx + 1] = smem[tid4 + 1];
        if(idx4 + 2 <= offset) g_odata[oindx + 2] = smem[tid4 + 2];
        if(idx4 + 3 <= offset) g_odata[oindx + 3] = smem[tid4 + 3];

    }

}

void reduce_sum_3d_try01(
        float*  g_idata,
        float*  g_odata,
        int dim0,
        int dim1,
        int dim2,
        int overaxis0,
        int overaxis1,
        int overaxis2)
{
    dim3 block (BLOCK_SIZE, 1);
    dim3 grid_overdim0  ((dim1*dim2 + block.x - 1) / block.x / 4, 1);
    dim3 grid_overdim1  ((dim0*dim2 + block.x - 1) / block.x / 4, 1);
    dim3 grid_overdim2  ((dim0*dim1 + block.x - 1) / block.x / 4, 1);

    dim3 grid = (overaxis0==1)?(grid_overdim0):(overaxis1==1?grid_overdim1:grid_overdim2);

    kernel_reduce_sum_3d_try01 <<< grid, block >>> (
            g_idata,
            g_odata,
            dim0, dim1, dim2,
            overaxis0, overaxis1,overaxis2);
}




__global__ void kernel_reduce_sum_3d_try02(
        const float*  __restrict__ g_idata,
        float*  __restrict__ g_odata,
        int dim0,
        int dim1,
        int dim2,
        int overaxis0,
        int overaxis1,
        int overaxis2)
{
    if (overaxis0 == 0 && overaxis1 == 1 && overaxis2 == 0) { // FTF
        /* Each thread handles 1 pairs of elements.
         * BlockDim is 1D
         * BlockDim should be dividable by 1
         *
         * */

        // static shared memory
        __shared__ float smem_store[BLOCK_SIZE];
        //__shared__ float smem_load[BLOCK_SIZE];

        // set thread ID
        //unsigned int tid = threadIdx.x;
        unsigned int tid =  threadIdx.x;

        // global index
        unsigned int idx = (blockIdx.x * blockDim.x + threadIdx.x);

        // unrolling
        float tmpSum0 = 0;
        unsigned int i = 0;
        unsigned int src_index ;
        unsigned int _limit = (unsigned int)(dim0 * dim1 * dim2);

        //Indices over output's matrix (NOT OVER INPUT) (OUTPUT'S CONSIDERED AS A ROW-MAJOR MATRIX)
        int thrd_d0 = (idx) / (1*dim2);
        int thrd_d2 = (idx - thrd_d0*dim2);

        //Only for debugging kernel
        //printf("tid: %03d \tidx: %03d\td0: %02d\td2: %02d\n",tid,idx,thrd_d0,thrd_d2);



        //Merging the thread's DIM1 element from all DIM1's elements of current DIM0.
        for (i = 0; i < dim1; i++) {
            src_index = thrd_d0*dim1*dim2 + i * dim2 + thrd_d2;
            printf("idx: %d : src_index: %d\n",idx,src_index);
            if(src_index < _limit)
                tmpSum0 += g_idata[src_index];
        }


        if (src_index + 0 < _limit) smem_store[tid + 0] = tmpSum0;
        __syncthreads();

        unsigned int oindx = (unsigned int)( thrd_d0*dim2 + thrd_d2 );
        if (src_index + 0 <= _limit) g_odata[oindx + 0] = smem_store[tid + 0];

    }
    else
    {
        if (overaxis0 == 0 && overaxis1 == 0 && overaxis2 == 1) { // FFT
            /* Each thread handles 1 pairs of elements.
             * BlockDim is 1D
             * BlockDim should be dividable by 1
             *
             * */

            // static shared memory
            __shared__ float smem_store[BLOCK_SIZE];

            // set thread ID
            //unsigned int tid = threadIdx.x;
            unsigned int tid =  threadIdx.x;

            // global index
            unsigned int idx = (blockIdx.x * blockDim.x + threadIdx.x);

            // unrolling
            float tmpSum0 = 0;
            unsigned int i = 0;
            unsigned int src_index ;
            unsigned int _limit = (unsigned int)(dim0 * dim1 * dim2);

            //Indices over output's matrix (NOT OVER INPUT) (OUTPUT'S CONSIDERED AS A ROW-MAJOR MATRIX)
            int thrd_d0 = (idx) / (dim1*1);
            int thrd_d1 = (idx - thrd_d0*dim1);

            //Only for debugging kernel
            printf("tid: %03d \tidx: %03d\td0: %02d\td1: %02d\n",tid,idx,thrd_d0,thrd_d1);


            //Merging the thread's DIM1 element from all DIM1's elements of current DIM0.
            for (i = 0; i < dim2; i++) {
                src_index = thrd_d0*dim1*dim2 + thrd_d1 * dim2 + i;
                if(idx<15) printf("idx: %d : src_index: %d\n",idx,src_index);
                if(src_index < _limit)
                    tmpSum0 += g_idata[src_index];
            }


            if (src_index + 0 < _limit) smem_store[tid + 0] = tmpSum0;
            __syncthreads();

            unsigned int oindx = (unsigned int)( thrd_d0*dim1 + thrd_d1 );
            if (src_index + 0 <= _limit) g_odata[oindx + 0] = smem_store[tid + 0];

        }
    }

}

void reduce_sum_3d_try02(
        float* g_idata,
        float* g_odata,
        int dim0,
        int dim1,
        int dim2,
        int overaxis0,
        int overaxis1,
        int overaxis2)
{
    dim3 block (BLOCK_SIZE, 1);
    dim3 grid_overdim0  ((dim1*dim2 + block.x - 1) / block.x, 1);
    dim3 grid_overdim1  ((dim0*dim2 + block.x - 1) / block.x, 1);
    dim3 grid_overdim2  ((dim0*dim1 + block.x - 1) / block.x, 1);

    dim3 grid = (overaxis0==1)?(grid_overdim0):(overaxis1==1?grid_overdim1:grid_overdim2);

    kernel_reduce_sum_3d_try02 <<< grid, block >>> (
            g_idata,
            g_odata,
            dim0, dim1, dim2,
            overaxis0, overaxis1,overaxis2);
}



__global__ void kernel_reduce_sum_3d_try03(
        const float * __restrict__  g_idata,
        float * __restrict__  g_odata,
        const unsigned int dim0,
        const unsigned int dim1,
        const unsigned int dim2,
        const bool overaxis0,
        const bool overaxis1,
        const bool overaxis2)
{
    // WANING : dim0 means dim2 and dim2 means dim0
    __shared__ float sm[BLOCK_SIZE];
    if (overaxis2 && !overaxis1 && !overaxis0)
    {
        // Case 1 - sums in X-direction
        // each threadblock is responsible for a separate row sum
        unsigned int bidx = blockIdx.x;
        unsigned int tidx = threadIdx.x;
        sm[threadIdx.x] = 0;
        while (tidx < dim0)
        {
            sm[threadIdx.x] += g_idata[bidx*dim0+tidx];
            /*if(bidx==21){
                //dbg
                printf("thid: %04d\tg_index_to_read:%d\n",threadIdx.x,bidx*dim0+tidx);
            }*/
            tidx += blockDim.x;
        } // block-stride loop

        __syncthreads();

        // parallel reduction
        for (int i = blockDim.x>>1; i > 0; i>>=1)
        {
            if (threadIdx.x < i) sm[threadIdx.x] += sm[threadIdx.x + i];
            __syncthreads();
        }

        if (!threadIdx.x) g_odata[bidx] = sm[0];
    }
    else if (!overaxis2 && overaxis1 && !overaxis0)
    {
        // Case 2 - sums in Y-direction
        // each thread is responsible for a separate Y-column sum
        unsigned int idx = threadIdx.x+blockDim.x*blockIdx.x;
        if (idx < (dim0*dim2))
        {
            unsigned int tidx = idx%dim0 + (idx/dim0)*(dim0*dim1); //indices over input tensor (begining of axis1 slices)

            float tsum = 0;

            for (unsigned int i = 0; i < dim1; i++)
            {
                //printf("idx: %03d \t\t tidx: %03d\n",idx,tidx);
                tsum += g_idata[tidx];
                tidx += dim0;
            }

            g_odata[idx] = tsum;
        }
    }
    else if (!overaxis2 && !overaxis1 && overaxis0)
    {
        // Case 3 - sums in Z-direction
        // each thread is responsible for a separate Z-column sum

        unsigned int idx = threadIdx.x + blockDim.x*blockIdx.x;

        //printf("%d,%d,%d\n",dbg_blockid,dbg_thid,idx);


        if (idx < (dim0*dim1))
        {
            unsigned int tidx = idx;
            float tsum = 0;

            for (int i = 0; i < dim2; i++)
            {
                //printf("%d,%d,%d,%d,%d\n",dbg_blockid,dbg_thid,idx,tidx,i);
                //printf("idx:%02d, tidx:%02d, i=%02d\n",idx,tidx,i);
                tsum += g_idata[tidx];
                tidx += dim0*dim1;
            }

            g_odata[idx] = tsum;
        }
    }
    else {
        printf("reduce_sum: ERROR-NOTIMPLEMENTED\n");
    }




}



void reduce_sum_3d_try03(
        float* g_idata,
        float* g_odata,
        int dim0,
        int dim1,
        int dim2,
        bool overaxis0,
        bool overaxis1,
        bool overaxis2)
{
    dim3 block (BLOCK_SIZE, 1);
    dim3 grid_overdim0  ((dim1*dim2 + block.x - 1) / block.x, 1);
    dim3 grid_overdim1  ((dim0*dim2 + block.x - 1) / block.x, 1);
    dim3 grid_overdim2  (dim0*dim1 , 1);

    dim3 grid = overaxis0 ? (grid_overdim0) : (overaxis1 ? grid_overdim1 : grid_overdim2);

    //printf("-------------------------------------------------------\n");
    //printf("KERNEL_GRID  : %d\n", grid.x);
    //printf("KERNEL_BLOCK : %d\n", block.x);

    kernel_reduce_sum_3d_try03 <<<grid, block>>> (
            g_idata, g_odata,
            dim2, dim1, dim0,
            overaxis0, overaxis1,overaxis2);


}
	.text
	.file	"reduce_sum_3d.hip"
	.globl	_Z41__device_stub__kernel_reduce_sum_3d_try01PKfPfiiiiii # -- Begin function _Z41__device_stub__kernel_reduce_sum_3d_try01PKfPfiiiiii
	.type	_Z41__device_stub__kernel_reduce_sum_3d_try01PKfPfiiiiii,@function
_Z41__device_stub__kernel_reduce_sum_3d_try01PKfPfiiiiii: # @_Z41__device_stub__kernel_reduce_sum_3d_try01PKfPfiiiiii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	4(%rsp), %rcx
	movl	%r8d, (%rcx)
	movq	%rsp, %r8
	movl	%r9d, (%r8)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	192(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	200(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z26kernel_reduce_sum_3d_try01PKfPfiiiiii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z41__device_stub__kernel_reduce_sum_3d_try01PKfPfiiiiii, .Lfunc_end0-_Z41__device_stub__kernel_reduce_sum_3d_try01PKfPfiiiiii
	.cfi_endproc
                                        # -- End function
	.globl	_Z19reduce_sum_3d_try01PfS_iiiiii # -- Begin function _Z19reduce_sum_3d_try01PfS_iiiiii
	.type	_Z19reduce_sum_3d_try01PfS_iiiiii,@function
_Z19reduce_sum_3d_try01PfS_iiiiii:      # @_Z19reduce_sum_3d_try01PfS_iiiiii
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	pushq	%rax
	.cfi_def_cfa_offset 64
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%r9d, %ebx
	movl	%r8d, %ebp
	movl	%ecx, %r14d
	movl	%edx, %r15d
	movq	%rsi, %r12
	movq	%rdi, %r13
	movl	%r8d, %eax
	imull	%ecx, %eax
	cmpl	$1, 64(%rsp)
	movl	%ecx, %edi
	cmovel	%r8d, %edi
	imull	%edx, %edi
	cmpl	$1, %r9d
	cmovel	%eax, %edi
	addl	$255, %edi
	shrl	$10, %edi
	btsq	$32, %rdi
	movabsq	$4294967296, %rdx               # imm = 0x100000000
	orq	$256, %rdx                      # imm = 0x100
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	je	.LBB1_2
# %bb.1:
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB1_2:
	.cfi_def_cfa_offset 64
	movq	%r13, %rdi
	movq	%r12, %rsi
	movl	%r15d, %edx
	movl	%r14d, %ecx
	movl	%ebp, %r8d
	movl	%ebx, %r9d
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z41__device_stub__kernel_reduce_sum_3d_try01PKfPfiiiiii # TAILCALL
.Lfunc_end1:
	.size	_Z19reduce_sum_3d_try01PfS_iiiiii, .Lfunc_end1-_Z19reduce_sum_3d_try01PfS_iiiiii
	.cfi_endproc
                                        # -- End function
	.globl	_Z41__device_stub__kernel_reduce_sum_3d_try02PKfPfiiiiii # -- Begin function _Z41__device_stub__kernel_reduce_sum_3d_try02PKfPfiiiiii
	.type	_Z41__device_stub__kernel_reduce_sum_3d_try02PKfPfiiiiii,@function
_Z41__device_stub__kernel_reduce_sum_3d_try02PKfPfiiiiii: # @_Z41__device_stub__kernel_reduce_sum_3d_try02PKfPfiiiiii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	4(%rsp), %rcx
	movl	%r8d, (%rcx)
	movq	%rsp, %r8
	movl	%r9d, (%r8)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	192(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	200(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z26kernel_reduce_sum_3d_try02PKfPfiiiiii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z41__device_stub__kernel_reduce_sum_3d_try02PKfPfiiiiii, .Lfunc_end2-_Z41__device_stub__kernel_reduce_sum_3d_try02PKfPfiiiiii
	.cfi_endproc
                                        # -- End function
	.globl	_Z19reduce_sum_3d_try02PfS_iiiiii # -- Begin function _Z19reduce_sum_3d_try02PfS_iiiiii
	.type	_Z19reduce_sum_3d_try02PfS_iiiiii,@function
_Z19reduce_sum_3d_try02PfS_iiiiii:      # @_Z19reduce_sum_3d_try02PfS_iiiiii
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	pushq	%rax
	.cfi_def_cfa_offset 64
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%r9d, %ebx
	movl	%r8d, %ebp
	movl	%ecx, %r14d
	movl	%edx, %r15d
	movq	%rsi, %r12
	movq	%rdi, %r13
	movl	%r8d, %eax
	imull	%ecx, %eax
	cmpl	$1, 64(%rsp)
	movl	%ecx, %edi
	cmovel	%r8d, %edi
	imull	%edx, %edi
	cmpl	$1, %r9d
	cmovel	%eax, %edi
	addl	$255, %edi
	shrl	$8, %edi
	btsq	$32, %rdi
	movabsq	$4294967296, %rdx               # imm = 0x100000000
	orq	$256, %rdx                      # imm = 0x100
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	je	.LBB3_2
# %bb.1:
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB3_2:
	.cfi_def_cfa_offset 64
	movq	%r13, %rdi
	movq	%r12, %rsi
	movl	%r15d, %edx
	movl	%r14d, %ecx
	movl	%ebp, %r8d
	movl	%ebx, %r9d
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z41__device_stub__kernel_reduce_sum_3d_try02PKfPfiiiiii # TAILCALL
.Lfunc_end3:
	.size	_Z19reduce_sum_3d_try02PfS_iiiiii, .Lfunc_end3-_Z19reduce_sum_3d_try02PfS_iiiiii
	.cfi_endproc
                                        # -- End function
	.globl	_Z41__device_stub__kernel_reduce_sum_3d_try03PKfPfjjjbbb # -- Begin function _Z41__device_stub__kernel_reduce_sum_3d_try03PKfPfjjjbbb
	.type	_Z41__device_stub__kernel_reduce_sum_3d_try03PKfPfjjjbbb,@function
_Z41__device_stub__kernel_reduce_sum_3d_try03PKfPfjjjbbb: # @_Z41__device_stub__kernel_reduce_sum_3d_try03PKfPfjjjbbb
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movb	200(%rsp), %al
	movb	192(%rsp), %r10b
	leaq	40(%rsp), %r11
	movq	%rdi, (%r11)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	4(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	3(%rsp), %r8
	movb	%r9b, (%r8)
	leaq	2(%rsp), %r9
	movb	%r10b, (%r9)
	leaq	1(%rsp), %r10
	movb	%al, (%r10)
	leaq	80(%rsp), %rbx
	movq	%r11, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	movq	%r9, 48(%rbx)
	movq	%r10, 56(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z26kernel_reduce_sum_3d_try03PKfPfjjjbbb, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end4:
	.size	_Z41__device_stub__kernel_reduce_sum_3d_try03PKfPfjjjbbb, .Lfunc_end4-_Z41__device_stub__kernel_reduce_sum_3d_try03PKfPfjjjbbb
	.cfi_endproc
                                        # -- End function
	.globl	_Z19reduce_sum_3d_try03PfS_iiibbb # -- Begin function _Z19reduce_sum_3d_try03PfS_iiibbb
	.type	_Z19reduce_sum_3d_try03PfS_iiibbb,@function
_Z19reduce_sum_3d_try03PfS_iiibbb:      # @_Z19reduce_sum_3d_try03PfS_iiibbb
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	pushq	%rax
	.cfi_def_cfa_offset 64
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%r9d, %r15d
	movl	%r8d, %r14d
	movl	%ecx, %ebp
	movl	%edx, %ebx
	movl	%r8d, %ecx
	imull	%ebp, %ecx
	movl	$255, %eax
	addl	%eax, %ecx
	shrl	$8, %ecx
	movl	%r8d, %edx
	imull	%ebx, %edx
	addl	%eax, %edx
	shrl	$8, %edx
	movl	%ebp, %eax
	imull	%ebx, %eax
	cmpb	$0, 64(%rsp)
	cmovnel	%edx, %eax
	movq	%rsi, %r12
	testl	%r9d, %r9d
	cmovnel	%ecx, %eax
	movq	%rdi, %r13
	btsq	$32, %rax
	movabsq	$4294967296, %rdx               # imm = 0x100000000
	orq	$256, %rdx                      # imm = 0x100
	movq	%rax, %rdi
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	je	.LBB5_2
# %bb.1:
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB5_2:
	.cfi_def_cfa_offset 64
	movzbl	%r15b, %r9d
	movq	%r13, %rdi
	movq	%r12, %rsi
	movl	%r14d, %edx
	movl	%ebp, %ecx
	movl	%ebx, %r8d
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z41__device_stub__kernel_reduce_sum_3d_try03PKfPfjjjbbb # TAILCALL
.Lfunc_end5:
	.size	_Z19reduce_sum_3d_try03PfS_iiibbb, .Lfunc_end5-_Z19reduce_sum_3d_try03PfS_iiibbb
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB6_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB6_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z26kernel_reduce_sum_3d_try01PKfPfiiiiii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z26kernel_reduce_sum_3d_try02PKfPfiiiiii, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z26kernel_reduce_sum_3d_try03PKfPfjjjbbb, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end6:
	.size	__hip_module_ctor, .Lfunc_end6-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB7_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB7_2:
	retq
.Lfunc_end7:
	.size	__hip_module_dtor, .Lfunc_end7-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z26kernel_reduce_sum_3d_try01PKfPfiiiiii,@object # @_Z26kernel_reduce_sum_3d_try01PKfPfiiiiii
	.section	.rodata,"a",@progbits
	.globl	_Z26kernel_reduce_sum_3d_try01PKfPfiiiiii
	.p2align	3, 0x0
_Z26kernel_reduce_sum_3d_try01PKfPfiiiiii:
	.quad	_Z41__device_stub__kernel_reduce_sum_3d_try01PKfPfiiiiii
	.size	_Z26kernel_reduce_sum_3d_try01PKfPfiiiiii, 8

	.type	_Z26kernel_reduce_sum_3d_try02PKfPfiiiiii,@object # @_Z26kernel_reduce_sum_3d_try02PKfPfiiiiii
	.globl	_Z26kernel_reduce_sum_3d_try02PKfPfiiiiii
	.p2align	3, 0x0
_Z26kernel_reduce_sum_3d_try02PKfPfiiiiii:
	.quad	_Z41__device_stub__kernel_reduce_sum_3d_try02PKfPfiiiiii
	.size	_Z26kernel_reduce_sum_3d_try02PKfPfiiiiii, 8

	.type	_Z26kernel_reduce_sum_3d_try03PKfPfjjjbbb,@object # @_Z26kernel_reduce_sum_3d_try03PKfPfjjjbbb
	.globl	_Z26kernel_reduce_sum_3d_try03PKfPfjjjbbb
	.p2align	3, 0x0
_Z26kernel_reduce_sum_3d_try03PKfPfjjjbbb:
	.quad	_Z41__device_stub__kernel_reduce_sum_3d_try03PKfPfjjjbbb
	.size	_Z26kernel_reduce_sum_3d_try03PKfPfjjjbbb, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z26kernel_reduce_sum_3d_try01PKfPfiiiiii"
	.size	.L__unnamed_1, 42

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z26kernel_reduce_sum_3d_try02PKfPfiiiiii"
	.size	.L__unnamed_2, 42

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z26kernel_reduce_sum_3d_try03PKfPfjjjbbb"
	.size	.L__unnamed_3, 42

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z41__device_stub__kernel_reduce_sum_3d_try01PKfPfiiiiii
	.addrsig_sym _Z41__device_stub__kernel_reduce_sum_3d_try02PKfPfiiiiii
	.addrsig_sym _Z41__device_stub__kernel_reduce_sum_3d_try03PKfPfjjjbbb
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z26kernel_reduce_sum_3d_try01PKfPfiiiiii
	.addrsig_sym _Z26kernel_reduce_sum_3d_try02PKfPfiiiiii
	.addrsig_sym _Z26kernel_reduce_sum_3d_try03PKfPfjjjbbb
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z26kernel_reduce_sum_3d_try01PKfPfiiiiii ; -- Begin function _Z26kernel_reduce_sum_3d_try01PKfPfiiiiii
	.globl	_Z26kernel_reduce_sum_3d_try01PKfPfiiiiii
	.p2align	8
	.type	_Z26kernel_reduce_sum_3d_try01PKfPfiiiiii,@function
_Z26kernel_reduce_sum_3d_try01PKfPfiiiiii: ; @_Z26kernel_reduce_sum_3d_try01PKfPfiiiiii
; %bb.0:
	s_clause 0x1
	s_load_b128 s[4:7], s[0:1], 0x10
	s_load_b64 s[2:3], s[0:1], 0x20
	s_waitcnt lgkmcnt(0)
	s_cmp_lg_u32 s7, 1
	s_cselect_b32 s7, -1, 0
	s_or_b32 s2, s3, s2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_cmp_lg_u32 s2, 0
	s_cselect_b32 s2, -1, 0
	s_or_b32 s2, s7, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s2
	s_cbranch_vccnz .LBB0_28
; %bb.1:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x34
	s_load_b64 s[8:9], s[0:1], 0x8
	s_mul_i32 s5, s6, s5
	v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v9, 0
	v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v7, 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_cmp_lt_i32 s4, 1
	s_mul_i32 s15, s15, s2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_lshl_u32 v1, s15, v0, 2
	v_cmp_ge_u32_e32 vcc_lo, s5, v1
	v_cmp_gt_u32_e64 s2, s5, v1
	v_or_b32_e32 v6, 2, v1
	v_or_b32_e32 v5, 3, v1
	s_cbranch_scc1 .LBB0_12
; %bb.2:                                ; %.lr.ph
	s_load_b64 s[6:7], s[0:1], 0x0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_ge_u32_e64 s0, s5, v6
	v_cmp_ge_u32_e64 s1, s5, v5
	v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v3, 0
	v_dual_mov_b32 v2, v1 :: v_dual_mov_b32 v9, 0
	v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v7, 0
.LBB0_3:                                ; =>This Inner Loop Header: Depth=1
	s_and_saveexec_b32 s10, vcc_lo
	s_cbranch_execz .LBB0_5
; %bb.4:                                ;   in Loop: Header=BB0_3 Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[10:11], 2, v[2:3]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v10, s3, s6, v10
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v11, s3, s7, v11, s3
	global_load_b32 v10, v[10:11], off
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v8, v8, v10
.LBB0_5:                                ;   in Loop: Header=BB0_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
	s_and_saveexec_b32 s10, s2
	s_cbranch_execz .LBB0_7
; %bb.6:                                ;   in Loop: Header=BB0_3 Depth=1
	v_dual_mov_b32 v11, v3 :: v_dual_add_nc_u32 v10, 1, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[10:11], 2, v[10:11]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v10, s3, s6, v10
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v11, s3, s7, v11, s3
	global_load_b32 v10, v[10:11], off
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v9, v9, v10
.LBB0_7:                                ;   in Loop: Header=BB0_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
	s_and_saveexec_b32 s10, s0
	s_cbranch_execz .LBB0_9
; %bb.8:                                ;   in Loop: Header=BB0_3 Depth=1
	v_dual_mov_b32 v11, v3 :: v_dual_add_nc_u32 v10, 2, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[10:11], 2, v[10:11]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v10, s3, s6, v10
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v11, s3, s7, v11, s3
	global_load_b32 v10, v[10:11], off
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v7, v7, v10
.LBB0_9:                                ;   in Loop: Header=BB0_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
	s_and_saveexec_b32 s10, s1
	s_cbranch_execz .LBB0_11
; %bb.10:                               ;   in Loop: Header=BB0_3 Depth=1
	v_dual_mov_b32 v11, v3 :: v_dual_add_nc_u32 v10, 3, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[10:11], 2, v[10:11]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v10, s3, s6, v10
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v11, s3, s7, v11, s3
	global_load_b32 v10, v[10:11], off
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v4, v4, v10
.LBB0_11:                               ;   in Loop: Header=BB0_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
	v_add_nc_u32_e32 v2, s5, v2
	s_add_i32 s4, s4, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u32 s4, 0
	s_cbranch_scc1 .LBB0_3
.LBB0_12:                               ; %._crit_edge
	v_lshlrev_b32_e32 v0, 2, v0
	v_cmp_ge_u32_e64 s2, s5, v1
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s0, s2
	s_cbranch_execz .LBB0_14
; %bb.13:
	s_delay_alu instid0(VALU_DEP_2)
	v_lshlrev_b32_e32 v2, 2, v0
	ds_store_b32 v2, v8
.LBB0_14:
	s_or_b32 exec_lo, exec_lo, s0
	v_cmp_gt_u32_e64 s1, s5, v1
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s0, s1
	s_cbranch_execz .LBB0_16
; %bb.15:
	v_lshlrev_b32_e32 v2, 2, v0
	ds_store_b32 v2, v9 offset:4
.LBB0_16:
	s_or_b32 exec_lo, exec_lo, s0
	v_cmp_ge_u32_e64 s0, s5, v6
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s3, s0
	s_cbranch_execz .LBB0_18
; %bb.17:
	v_lshlrev_b32_e32 v2, 2, v0
	ds_store_b32 v2, v7 offset:8
.LBB0_18:
	s_or_b32 exec_lo, exec_lo, s3
	v_cmp_ge_u32_e32 vcc_lo, s5, v5
	s_and_saveexec_b32 s3, vcc_lo
	s_cbranch_execz .LBB0_20
; %bb.19:
	v_lshlrev_b32_e32 v2, 2, v0
	ds_store_b32 v2, v4 offset:12
.LBB0_20:
	s_or_b32 exec_lo, exec_lo, s3
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_22
; %bb.21:
	v_lshlrev_b32_e32 v2, 2, v0
	ds_load_b32 v4, v2
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[1:2]
	v_add_co_u32 v2, s2, s8, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v3, s2, s9, v3, s2
	s_waitcnt lgkmcnt(0)
	global_store_b32 v[2:3], v4, off
.LBB0_22:
	s_or_b32 exec_lo, exec_lo, s3
	s_and_saveexec_b32 s2, s1
	s_cbranch_execz .LBB0_24
; %bb.23:
	v_lshlrev_b32_e32 v2, 2, v0
	ds_load_b32 v4, v2 offset:4
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[1:2]
	v_add_co_u32 v2, s1, s8, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v3, s1, s9, v3, s1
	s_waitcnt lgkmcnt(0)
	global_store_b32 v[2:3], v4, off offset:4
.LBB0_24:
	s_or_b32 exec_lo, exec_lo, s2
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_26
; %bb.25:
	v_lshlrev_b32_e32 v2, 2, v0
	ds_load_b32 v4, v2 offset:8
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[1:2]
	v_add_co_u32 v2, s0, s8, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v3, s0, s9, v3, s0
	s_waitcnt lgkmcnt(0)
	global_store_b32 v[2:3], v4, off offset:8
.LBB0_26:
	s_or_b32 exec_lo, exec_lo, s1
	s_and_saveexec_b32 s0, vcc_lo
	s_cbranch_execz .LBB0_28
; %bb.27:
	v_lshlrev_b32_e32 v0, 2, v0
	v_mov_b32_e32 v2, 0
	ds_load_b32 v3, v0 offset:12
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s8, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s9, v1, vcc_lo
	s_waitcnt lgkmcnt(0)
	global_store_b32 v[0:1], v3, off offset:12
.LBB0_28:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z26kernel_reduce_sum_3d_try01PKfPfiiiiii
		.amdhsa_group_segment_fixed_size 4096
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 12
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z26kernel_reduce_sum_3d_try01PKfPfiiiiii, .Lfunc_end0-_Z26kernel_reduce_sum_3d_try01PKfPfiiiiii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 960
; NumSgprs: 18
; NumVgprs: 12
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 4096 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 12
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2align	2                               ; -- Begin function __ockl_printf_append_string_n
	.type	__ockl_printf_append_string_n,@function
__ockl_printf_append_string_n:          ; @__ockl_printf_append_string_n
; %bb.0:
	s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	v_dual_mov_b32 v8, v3 :: v_dual_mov_b32 v7, v2
	v_or_b32_e32 v2, 2, v0
	v_cmp_eq_u32_e64 s0, 0, v6
	s_mov_b32 s11, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cndmask_b32_e64 v10, v2, v0, s0
	s_mov_b32 s0, exec_lo
	v_cmpx_ne_u64_e32 0, v[7:8]
	s_xor_b32 s10, exec_lo, s0
	s_cbranch_execz .LBB1_87
; %bb.1:
	s_load_b64 s[2:3], s[8:9], 0x50
	v_dual_mov_b32 v11, 2 :: v_dual_and_b32 v6, 2, v10
	v_mov_b32_e32 v30, 0
	v_and_b32_e32 v0, -3, v10
	v_mbcnt_lo_u32_b32 v33, -1, 0
	v_mov_b32_e32 v12, 1
	s_mov_b32 s12, 0
.LBB1_2:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB1_5 Depth 2
                                        ;     Child Loop BB1_13 Depth 2
                                        ;     Child Loop BB1_21 Depth 2
                                        ;     Child Loop BB1_29 Depth 2
                                        ;     Child Loop BB1_37 Depth 2
                                        ;     Child Loop BB1_45 Depth 2
                                        ;     Child Loop BB1_53 Depth 2
                                        ;     Child Loop BB1_61 Depth 2
                                        ;     Child Loop BB1_69 Depth 2
                                        ;     Child Loop BB1_75 Depth 2
                                        ;     Child Loop BB1_84 Depth 2
	v_cmp_gt_u64_e32 vcc_lo, 56, v[4:5]
                                        ; implicit-def: $vgpr2_vgpr3
                                        ; implicit-def: $sgpr4
	s_mov_b32 s0, exec_lo
	v_dual_cndmask_b32 v32, 0, v5 :: v_dual_cndmask_b32 v31, 56, v4
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e32 8, v31
	s_xor_b32 s1, exec_lo, s0
	s_cbranch_execz .LBB1_8
; %bb.3:                                ;   in Loop: Header=BB1_2 Depth=1
	s_waitcnt vmcnt(0)
	v_mov_b32_e32 v2, 0
	v_mov_b32_e32 v3, 0
	s_mov_b32 s6, exec_lo
	v_cmpx_ne_u32_e32 0, v31
	s_cbranch_execz .LBB1_7
; %bb.4:                                ; %.preheader31.preheader
                                        ;   in Loop: Header=BB1_2 Depth=1
	v_mov_b32_e32 v2, 0
	v_lshlrev_b64 v[9:10], 3, v[31:32]
	v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v14, v8
	v_mov_b32_e32 v13, v7
	s_mov_b64 s[4:5], 0
	s_mov_b32 s7, 0
.LBB1_5:                                ; %.preheader31
                                        ;   Parent Loop BB1_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	flat_load_u8 v10, v[13:14]
	v_mov_b32_e32 v16, s11
	v_add_co_u32 v13, vcc_lo, v13, 1
	v_add_co_ci_u32_e32 v14, vcc_lo, 0, v14, vcc_lo
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_and_b32_e32 v15, 0xffff, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[15:16], s4, v[15:16]
	s_add_u32 s4, s4, 8
	s_addc_u32 s5, s5, 0
	v_cmp_eq_u32_e64 s0, s4, v9
	v_or_b32_e32 v3, v16, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_or_b32_e32 v2, v15, v2
	s_or_b32 s7, s0, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s7
	s_cbranch_execnz .LBB1_5
; %bb.6:                                ; %Flow232
                                        ;   in Loop: Header=BB1_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s7
.LBB1_7:                                ; %Flow234
                                        ;   in Loop: Header=BB1_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s6
	s_mov_b32 s4, 0
.LBB1_8:                                ; %Flow236
                                        ;   in Loop: Header=BB1_2 Depth=1
	s_or_saveexec_b32 s0, s1
	v_dual_mov_b32 v15, s4 :: v_dual_mov_b32 v10, v8
	v_mov_b32_e32 v9, v7
	s_xor_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB1_10
; %bb.9:                                ;   in Loop: Header=BB1_2 Depth=1
	s_waitcnt vmcnt(0)
	s_clause 0x5
	flat_load_u8 v2, v[7:8]
	flat_load_u8 v3, v[7:8] offset:1
	flat_load_u8 v9, v[7:8] offset:2
	flat_load_u8 v10, v[7:8] offset:3
	flat_load_u8 v13, v[7:8] offset:5
	flat_load_u8 v14, v[7:8] offset:4
	v_mov_b32_e32 v16, v30
	s_waitcnt vmcnt(5) lgkmcnt(0)
	v_and_b32_e32 v2, 0xffff, v2
	s_waitcnt vmcnt(4)
	v_lshlrev_b32_e32 v3, 8, v3
	s_clause 0x1
	flat_load_u8 v15, v[7:8] offset:7
	flat_load_d16_hi_u8 v16, v[7:8] offset:6
	s_waitcnt vmcnt(5)
	v_lshlrev_b32_e32 v9, 16, v9
	s_waitcnt vmcnt(4)
	v_lshlrev_b32_e32 v10, 24, v10
	v_or_b32_e32 v2, v3, v2
	s_waitcnt vmcnt(3)
	v_lshlrev_b32_e32 v3, 8, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_or3_b32 v2, v2, v9, v10
	s_waitcnt vmcnt(2)
	v_or3_b32 v3, 0, v14, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or3_b32 v2, v2, 0, 0
	v_or3_b32 v2, v2, 0, 0
	s_waitcnt vmcnt(1) lgkmcnt(1)
	v_lshlrev_b32_e32 v9, 24, v15
	v_add_nc_u32_e32 v15, -8, v31
	s_waitcnt vmcnt(0) lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2)
	v_or3_b32 v3, v3, v16, v9
	v_add_co_u32 v9, vcc_lo, v7, 8
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v8, vcc_lo
.LBB1_10:                               ; %.loopexit32
                                        ;   in Loop: Header=BB1_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $vgpr13_vgpr14
                                        ; implicit-def: $sgpr1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 8, v15
	s_xor_b32 s6, exec_lo, s0
	s_cbranch_execz .LBB1_16
; %bb.11:                               ;   in Loop: Header=BB1_2 Depth=1
	v_mov_b32_e32 v13, 0
	v_mov_b32_e32 v14, 0
	s_mov_b32 s7, exec_lo
	v_cmpx_ne_u32_e32 0, v15
	s_cbranch_execz .LBB1_15
; %bb.12:                               ; %.preheader29.preheader
                                        ;   in Loop: Header=BB1_2 Depth=1
	v_mov_b32_e32 v13, 0
	v_mov_b32_e32 v14, 0
	s_mov_b64 s[0:1], 0
	s_mov_b32 s13, 0
	s_mov_b64 s[4:5], 0
.LBB1_13:                               ; %.preheader29
                                        ;   Parent Loop BB1_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	v_add_co_u32 v16, vcc_lo, v9, s4
	v_add_co_ci_u32_e32 v17, vcc_lo, s5, v10, vcc_lo
	s_add_u32 s4, s4, 1
	s_addc_u32 s5, s5, 0
	v_cmp_eq_u32_e32 vcc_lo, s4, v15
	flat_load_u8 v16, v[16:17]
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_dual_mov_b32 v17, s11 :: v_dual_and_b32 v16, 0xffff, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[16:17], s0, v[16:17]
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	s_or_b32 s13, vcc_lo, s13
	v_or_b32_e32 v14, v17, v14
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v13, v16, v13
	s_and_not1_b32 exec_lo, exec_lo, s13
	s_cbranch_execnz .LBB1_13
; %bb.14:                               ; %Flow227
                                        ;   in Loop: Header=BB1_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s13
.LBB1_15:                               ; %Flow229
                                        ;   in Loop: Header=BB1_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s7
	s_mov_b32 s1, 0
                                        ; implicit-def: $vgpr15
.LBB1_16:                               ; %Flow231
                                        ;   in Loop: Header=BB1_2 Depth=1
	s_or_saveexec_b32 s0, s6
	v_mov_b32_e32 v17, s1
	s_xor_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB1_18
; %bb.17:                               ;   in Loop: Header=BB1_2 Depth=1
	s_clause 0x5
	flat_load_u8 v13, v[9:10]
	flat_load_u8 v14, v[9:10] offset:1
	flat_load_u8 v16, v[9:10] offset:2
	flat_load_u8 v17, v[9:10] offset:3
	flat_load_u8 v18, v[9:10] offset:5
	flat_load_u8 v19, v[9:10] offset:4
	s_waitcnt vmcnt(5) lgkmcnt(0)
	v_dual_mov_b32 v20, v30 :: v_dual_and_b32 v13, 0xffff, v13
	s_clause 0x1
	flat_load_u8 v21, v[9:10] offset:7
	flat_load_d16_hi_u8 v20, v[9:10] offset:6
	s_waitcnt vmcnt(6)
	v_lshlrev_b32_e32 v14, 8, v14
	s_waitcnt vmcnt(5)
	v_lshlrev_b32_e32 v16, 16, v16
	s_waitcnt vmcnt(4)
	v_lshlrev_b32_e32 v17, 24, v17
	v_add_co_u32 v9, vcc_lo, v9, 8
	v_or_b32_e32 v13, v14, v13
	s_waitcnt vmcnt(3)
	v_lshlrev_b32_e32 v14, 8, v18
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_or3_b32 v13, v13, v16, v17
	s_waitcnt vmcnt(2)
	v_or3_b32 v14, 0, v19, v14
	v_add_nc_u32_e32 v17, -8, v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or3_b32 v13, v13, 0, 0
	v_or3_b32 v13, v13, 0, 0
	s_waitcnt vmcnt(1) lgkmcnt(1)
	v_lshlrev_b32_e32 v16, 24, v21
	s_waitcnt vmcnt(0) lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_or3_b32 v14, v14, v20, v16
.LBB1_18:                               ; %.loopexit30
                                        ;   in Loop: Header=BB1_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $sgpr1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 8, v17
	s_xor_b32 s6, exec_lo, s0
	s_cbranch_execz .LBB1_24
; %bb.19:                               ;   in Loop: Header=BB1_2 Depth=1
	v_mov_b32_e32 v15, 0
	v_mov_b32_e32 v16, 0
	s_mov_b32 s7, exec_lo
	v_cmpx_ne_u32_e32 0, v17
	s_cbranch_execz .LBB1_23
; %bb.20:                               ; %.preheader27.preheader
                                        ;   in Loop: Header=BB1_2 Depth=1
	v_mov_b32_e32 v15, 0
	v_mov_b32_e32 v16, 0
	s_mov_b64 s[0:1], 0
	s_mov_b32 s13, 0
	s_mov_b64 s[4:5], 0
.LBB1_21:                               ; %.preheader27
                                        ;   Parent Loop BB1_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	v_add_co_u32 v18, vcc_lo, v9, s4
	v_add_co_ci_u32_e32 v19, vcc_lo, s5, v10, vcc_lo
	s_add_u32 s4, s4, 1
	s_addc_u32 s5, s5, 0
	v_cmp_eq_u32_e32 vcc_lo, s4, v17
	flat_load_u8 v18, v[18:19]
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_dual_mov_b32 v19, s11 :: v_dual_and_b32 v18, 0xffff, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[18:19], s0, v[18:19]
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	s_or_b32 s13, vcc_lo, s13
	v_or_b32_e32 v16, v19, v16
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v15, v18, v15
	s_and_not1_b32 exec_lo, exec_lo, s13
	s_cbranch_execnz .LBB1_21
; %bb.22:                               ; %Flow222
                                        ;   in Loop: Header=BB1_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s13
.LBB1_23:                               ; %Flow224
                                        ;   in Loop: Header=BB1_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s7
	s_mov_b32 s1, 0
                                        ; implicit-def: $vgpr17
.LBB1_24:                               ; %Flow226
                                        ;   in Loop: Header=BB1_2 Depth=1
	s_or_saveexec_b32 s0, s6
	v_mov_b32_e32 v19, s1
	s_xor_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB1_26
; %bb.25:                               ;   in Loop: Header=BB1_2 Depth=1
	s_clause 0x5
	flat_load_u8 v15, v[9:10]
	flat_load_u8 v16, v[9:10] offset:1
	flat_load_u8 v18, v[9:10] offset:2
	flat_load_u8 v19, v[9:10] offset:3
	flat_load_u8 v20, v[9:10] offset:5
	flat_load_u8 v21, v[9:10] offset:4
	s_waitcnt vmcnt(5) lgkmcnt(0)
	v_dual_mov_b32 v22, v30 :: v_dual_and_b32 v15, 0xffff, v15
	s_clause 0x1
	flat_load_u8 v23, v[9:10] offset:7
	flat_load_d16_hi_u8 v22, v[9:10] offset:6
	s_waitcnt vmcnt(6)
	v_lshlrev_b32_e32 v16, 8, v16
	s_waitcnt vmcnt(5)
	v_lshlrev_b32_e32 v18, 16, v18
	s_waitcnt vmcnt(4)
	v_lshlrev_b32_e32 v19, 24, v19
	v_add_co_u32 v9, vcc_lo, v9, 8
	v_or_b32_e32 v15, v16, v15
	s_waitcnt vmcnt(3)
	v_lshlrev_b32_e32 v16, 8, v20
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_or3_b32 v15, v15, v18, v19
	s_waitcnt vmcnt(2)
	v_or3_b32 v16, 0, v21, v16
	v_add_nc_u32_e32 v19, -8, v17
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or3_b32 v15, v15, 0, 0
	v_or3_b32 v15, v15, 0, 0
	s_waitcnt vmcnt(1) lgkmcnt(1)
	v_lshlrev_b32_e32 v18, 24, v23
	s_waitcnt vmcnt(0) lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_or3_b32 v16, v16, v22, v18
.LBB1_26:                               ; %.loopexit28
                                        ;   in Loop: Header=BB1_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $vgpr17_vgpr18
                                        ; implicit-def: $sgpr1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 8, v19
	s_xor_b32 s6, exec_lo, s0
	s_cbranch_execz .LBB1_32
; %bb.27:                               ;   in Loop: Header=BB1_2 Depth=1
	v_mov_b32_e32 v17, 0
	v_mov_b32_e32 v18, 0
	s_mov_b32 s7, exec_lo
	v_cmpx_ne_u32_e32 0, v19
	s_cbranch_execz .LBB1_31
; %bb.28:                               ; %.preheader25.preheader
                                        ;   in Loop: Header=BB1_2 Depth=1
	v_mov_b32_e32 v17, 0
	v_mov_b32_e32 v18, 0
	s_mov_b64 s[0:1], 0
	s_mov_b32 s13, 0
	s_mov_b64 s[4:5], 0
.LBB1_29:                               ; %.preheader25
                                        ;   Parent Loop BB1_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	v_add_co_u32 v20, vcc_lo, v9, s4
	v_add_co_ci_u32_e32 v21, vcc_lo, s5, v10, vcc_lo
	s_add_u32 s4, s4, 1
	s_addc_u32 s5, s5, 0
	v_cmp_eq_u32_e32 vcc_lo, s4, v19
	flat_load_u8 v20, v[20:21]
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_dual_mov_b32 v21, s11 :: v_dual_and_b32 v20, 0xffff, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[20:21], s0, v[20:21]
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	s_or_b32 s13, vcc_lo, s13
	v_or_b32_e32 v18, v21, v18
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v17, v20, v17
	s_and_not1_b32 exec_lo, exec_lo, s13
	s_cbranch_execnz .LBB1_29
; %bb.30:                               ; %Flow217
                                        ;   in Loop: Header=BB1_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s13
.LBB1_31:                               ; %Flow219
                                        ;   in Loop: Header=BB1_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s7
	s_mov_b32 s1, 0
                                        ; implicit-def: $vgpr19
.LBB1_32:                               ; %Flow221
                                        ;   in Loop: Header=BB1_2 Depth=1
	s_or_saveexec_b32 s0, s6
	v_mov_b32_e32 v21, s1
	s_xor_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB1_34
; %bb.33:                               ;   in Loop: Header=BB1_2 Depth=1
	s_clause 0x5
	flat_load_u8 v17, v[9:10]
	flat_load_u8 v18, v[9:10] offset:1
	flat_load_u8 v20, v[9:10] offset:2
	flat_load_u8 v21, v[9:10] offset:3
	flat_load_u8 v22, v[9:10] offset:5
	flat_load_u8 v23, v[9:10] offset:4
	s_waitcnt vmcnt(5) lgkmcnt(0)
	v_dual_mov_b32 v24, v30 :: v_dual_and_b32 v17, 0xffff, v17
	s_clause 0x1
	flat_load_u8 v25, v[9:10] offset:7
	flat_load_d16_hi_u8 v24, v[9:10] offset:6
	s_waitcnt vmcnt(6)
	v_lshlrev_b32_e32 v18, 8, v18
	s_waitcnt vmcnt(5)
	v_lshlrev_b32_e32 v20, 16, v20
	s_waitcnt vmcnt(4)
	v_lshlrev_b32_e32 v21, 24, v21
	v_add_co_u32 v9, vcc_lo, v9, 8
	v_or_b32_e32 v17, v18, v17
	s_waitcnt vmcnt(3)
	v_lshlrev_b32_e32 v18, 8, v22
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_or3_b32 v17, v17, v20, v21
	s_waitcnt vmcnt(2)
	v_or3_b32 v18, 0, v23, v18
	v_add_nc_u32_e32 v21, -8, v19
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or3_b32 v17, v17, 0, 0
	v_or3_b32 v17, v17, 0, 0
	s_waitcnt vmcnt(1) lgkmcnt(1)
	v_lshlrev_b32_e32 v20, 24, v25
	s_waitcnt vmcnt(0) lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_or3_b32 v18, v18, v24, v20
.LBB1_34:                               ; %.loopexit26
                                        ;   in Loop: Header=BB1_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $sgpr1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 8, v21
	s_xor_b32 s6, exec_lo, s0
	s_cbranch_execz .LBB1_40
; %bb.35:                               ;   in Loop: Header=BB1_2 Depth=1
	v_mov_b32_e32 v19, 0
	v_mov_b32_e32 v20, 0
	s_mov_b32 s7, exec_lo
	v_cmpx_ne_u32_e32 0, v21
	s_cbranch_execz .LBB1_39
; %bb.36:                               ; %.preheader23.preheader
                                        ;   in Loop: Header=BB1_2 Depth=1
	v_mov_b32_e32 v19, 0
	v_mov_b32_e32 v20, 0
	s_mov_b64 s[0:1], 0
	s_mov_b32 s13, 0
	s_mov_b64 s[4:5], 0
.LBB1_37:                               ; %.preheader23
                                        ;   Parent Loop BB1_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	v_add_co_u32 v22, vcc_lo, v9, s4
	v_add_co_ci_u32_e32 v23, vcc_lo, s5, v10, vcc_lo
	s_add_u32 s4, s4, 1
	s_addc_u32 s5, s5, 0
	v_cmp_eq_u32_e32 vcc_lo, s4, v21
	flat_load_u8 v22, v[22:23]
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_dual_mov_b32 v23, s11 :: v_dual_and_b32 v22, 0xffff, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[22:23], s0, v[22:23]
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	s_or_b32 s13, vcc_lo, s13
	v_or_b32_e32 v20, v23, v20
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v19, v22, v19
	s_and_not1_b32 exec_lo, exec_lo, s13
	s_cbranch_execnz .LBB1_37
; %bb.38:                               ; %Flow212
                                        ;   in Loop: Header=BB1_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s13
.LBB1_39:                               ; %Flow214
                                        ;   in Loop: Header=BB1_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s7
	s_mov_b32 s1, 0
                                        ; implicit-def: $vgpr21
.LBB1_40:                               ; %Flow216
                                        ;   in Loop: Header=BB1_2 Depth=1
	s_or_saveexec_b32 s0, s6
	v_mov_b32_e32 v23, s1
	s_xor_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB1_42
; %bb.41:                               ;   in Loop: Header=BB1_2 Depth=1
	s_clause 0x5
	flat_load_u8 v19, v[9:10]
	flat_load_u8 v20, v[9:10] offset:1
	flat_load_u8 v22, v[9:10] offset:2
	flat_load_u8 v23, v[9:10] offset:3
	flat_load_u8 v24, v[9:10] offset:5
	flat_load_u8 v25, v[9:10] offset:4
	s_waitcnt vmcnt(5) lgkmcnt(0)
	v_dual_mov_b32 v26, v30 :: v_dual_and_b32 v19, 0xffff, v19
	s_clause 0x1
	flat_load_u8 v27, v[9:10] offset:7
	flat_load_d16_hi_u8 v26, v[9:10] offset:6
	s_waitcnt vmcnt(6)
	v_lshlrev_b32_e32 v20, 8, v20
	s_waitcnt vmcnt(5)
	v_lshlrev_b32_e32 v22, 16, v22
	s_waitcnt vmcnt(4)
	v_lshlrev_b32_e32 v23, 24, v23
	v_add_co_u32 v9, vcc_lo, v9, 8
	v_or_b32_e32 v19, v20, v19
	s_waitcnt vmcnt(3)
	v_lshlrev_b32_e32 v20, 8, v24
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_or3_b32 v19, v19, v22, v23
	s_waitcnt vmcnt(2)
	v_or3_b32 v20, 0, v25, v20
	v_add_nc_u32_e32 v23, -8, v21
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or3_b32 v19, v19, 0, 0
	v_or3_b32 v19, v19, 0, 0
	s_waitcnt vmcnt(1) lgkmcnt(1)
	v_lshlrev_b32_e32 v22, 24, v27
	s_waitcnt vmcnt(0) lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_or3_b32 v20, v20, v26, v22
.LBB1_42:                               ; %.loopexit24
                                        ;   in Loop: Header=BB1_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $vgpr21_vgpr22
                                        ; implicit-def: $sgpr1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 8, v23
	s_xor_b32 s6, exec_lo, s0
	s_cbranch_execz .LBB1_48
; %bb.43:                               ;   in Loop: Header=BB1_2 Depth=1
	v_mov_b32_e32 v21, 0
	v_mov_b32_e32 v22, 0
	s_mov_b32 s7, exec_lo
	v_cmpx_ne_u32_e32 0, v23
	s_cbranch_execz .LBB1_47
; %bb.44:                               ; %.preheader21.preheader
                                        ;   in Loop: Header=BB1_2 Depth=1
	v_mov_b32_e32 v21, 0
	v_mov_b32_e32 v22, 0
	s_mov_b64 s[0:1], 0
	s_mov_b32 s13, 0
	s_mov_b64 s[4:5], 0
.LBB1_45:                               ; %.preheader21
                                        ;   Parent Loop BB1_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	v_add_co_u32 v24, vcc_lo, v9, s4
	v_add_co_ci_u32_e32 v25, vcc_lo, s5, v10, vcc_lo
	s_add_u32 s4, s4, 1
	s_addc_u32 s5, s5, 0
	v_cmp_eq_u32_e32 vcc_lo, s4, v23
	flat_load_u8 v24, v[24:25]
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_dual_mov_b32 v25, s11 :: v_dual_and_b32 v24, 0xffff, v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[24:25], s0, v[24:25]
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	s_or_b32 s13, vcc_lo, s13
	v_or_b32_e32 v22, v25, v22
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v21, v24, v21
	s_and_not1_b32 exec_lo, exec_lo, s13
	s_cbranch_execnz .LBB1_45
; %bb.46:                               ; %Flow207
                                        ;   in Loop: Header=BB1_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s13
.LBB1_47:                               ; %Flow209
                                        ;   in Loop: Header=BB1_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s7
	s_mov_b32 s1, 0
                                        ; implicit-def: $vgpr23
.LBB1_48:                               ; %Flow211
                                        ;   in Loop: Header=BB1_2 Depth=1
	s_or_saveexec_b32 s0, s6
	v_mov_b32_e32 v25, s1
	s_xor_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB1_50
; %bb.49:                               ;   in Loop: Header=BB1_2 Depth=1
	s_clause 0x5
	flat_load_u8 v21, v[9:10]
	flat_load_u8 v22, v[9:10] offset:1
	flat_load_u8 v24, v[9:10] offset:2
	flat_load_u8 v25, v[9:10] offset:3
	flat_load_u8 v26, v[9:10] offset:5
	flat_load_u8 v27, v[9:10] offset:4
	s_waitcnt vmcnt(5) lgkmcnt(0)
	v_dual_mov_b32 v28, v30 :: v_dual_and_b32 v21, 0xffff, v21
	s_clause 0x1
	flat_load_u8 v29, v[9:10] offset:7
	flat_load_d16_hi_u8 v28, v[9:10] offset:6
	s_waitcnt vmcnt(6)
	v_lshlrev_b32_e32 v22, 8, v22
	s_waitcnt vmcnt(5)
	v_lshlrev_b32_e32 v24, 16, v24
	s_waitcnt vmcnt(4)
	v_lshlrev_b32_e32 v25, 24, v25
	v_add_co_u32 v9, vcc_lo, v9, 8
	v_or_b32_e32 v21, v22, v21
	s_waitcnt vmcnt(3)
	v_lshlrev_b32_e32 v22, 8, v26
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_or3_b32 v21, v21, v24, v25
	s_waitcnt vmcnt(2)
	v_or3_b32 v22, 0, v27, v22
	v_add_nc_u32_e32 v25, -8, v23
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or3_b32 v21, v21, 0, 0
	v_or3_b32 v21, v21, 0, 0
	s_waitcnt vmcnt(1) lgkmcnt(1)
	v_lshlrev_b32_e32 v24, 24, v29
	s_waitcnt vmcnt(0) lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_or3_b32 v22, v22, v28, v24
.LBB1_50:                               ; %.loopexit22
                                        ;   in Loop: Header=BB1_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 8, v25
	s_xor_b32 s4, exec_lo, s0
	s_cbranch_execz .LBB1_56
; %bb.51:                               ;   in Loop: Header=BB1_2 Depth=1
	v_mov_b32_e32 v23, 0
	v_mov_b32_e32 v24, 0
	s_mov_b32 s5, exec_lo
	v_cmpx_ne_u32_e32 0, v25
	s_cbranch_execz .LBB1_55
; %bb.52:                               ; %.preheader.preheader
                                        ;   in Loop: Header=BB1_2 Depth=1
	v_mov_b32_e32 v23, 0
	v_mov_b32_e32 v24, 0
	s_mov_b64 s[0:1], 0
	s_mov_b32 s6, 0
.LBB1_53:                               ; %.preheader
                                        ;   Parent Loop BB1_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	flat_load_u8 v26, v[9:10]
	v_mov_b32_e32 v27, s11
	v_add_nc_u32_e32 v25, -1, v25
	v_add_co_u32 v9, vcc_lo, v9, 1
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_cmp_eq_u32_e32 vcc_lo, 0, v25
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_and_b32_e32 v26, 0xffff, v26
	v_lshlrev_b64 v[26:27], s0, v[26:27]
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	s_or_b32 s6, vcc_lo, s6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or_b32_e32 v24, v27, v24
	v_or_b32_e32 v23, v26, v23
	s_and_not1_b32 exec_lo, exec_lo, s6
	s_cbranch_execnz .LBB1_53
; %bb.54:                               ; %Flow202
                                        ;   in Loop: Header=BB1_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s6
.LBB1_55:                               ; %Flow204
                                        ;   in Loop: Header=BB1_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s5
                                        ; implicit-def: $vgpr9_vgpr10
.LBB1_56:                               ; %Flow206
                                        ;   in Loop: Header=BB1_2 Depth=1
	s_and_not1_saveexec_b32 s0, s4
	s_cbranch_execz .LBB1_58
; %bb.57:                               ;   in Loop: Header=BB1_2 Depth=1
	s_clause 0x5
	flat_load_u8 v23, v[9:10]
	flat_load_u8 v24, v[9:10] offset:1
	flat_load_u8 v25, v[9:10] offset:2
	flat_load_u8 v26, v[9:10] offset:3
	flat_load_u8 v27, v[9:10] offset:5
	flat_load_u8 v28, v[9:10] offset:4
	v_mov_b32_e32 v29, v30
	s_clause 0x1
	flat_load_u8 v34, v[9:10] offset:7
	flat_load_d16_hi_u8 v29, v[9:10] offset:6
	s_waitcnt vmcnt(7) lgkmcnt(0)
	v_and_b32_e32 v9, 0xffff, v23
	s_waitcnt vmcnt(6)
	v_lshlrev_b32_e32 v10, 8, v24
	s_waitcnt vmcnt(5)
	v_lshlrev_b32_e32 v23, 16, v25
	s_waitcnt vmcnt(3)
	v_lshlrev_b32_e32 v24, 8, v27
	v_or_b32_e32 v9, v10, v9
	v_lshlrev_b32_e32 v10, 24, v26
	s_delay_alu instid0(VALU_DEP_1)
	v_or3_b32 v9, v9, v23, v10
	s_waitcnt vmcnt(2)
	v_or3_b32 v10, 0, v28, v24
	s_waitcnt vmcnt(1)
	v_lshlrev_b32_e32 v23, 24, v34
	v_or3_b32 v9, v9, 0, 0
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or3_b32 v24, v10, v29, v23
	v_or3_b32 v23, v9, 0, 0
.LBB1_58:                               ; %.loopexit
                                        ;   in Loop: Header=BB1_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	v_mov_b32_e32 v29, v33
	v_mov_b32_e32 v9, 0
	v_mov_b32_e32 v10, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s0, v29
	v_cmp_eq_u32_e64 s0, s0, v29
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_64
; %bb.59:                               ;   in Loop: Header=BB1_2 Depth=1
	s_waitcnt lgkmcnt(0)
	global_load_b64 v[27:28], v30, s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[9:10], v30, s[2:3] offset:40
	global_load_b64 v[25:26], v30, s[2:3]
	s_mov_b32 s4, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v10, v10, v28
	v_and_b32_e32 v9, v9, v27
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v10, v10, 24
	v_mul_hi_u32 v34, v9, 24
	v_mul_lo_u32 v9, v9, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v10, v34, v10
	s_waitcnt vmcnt(0)
	v_add_co_u32 v9, vcc_lo, v25, v9
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v10, vcc_lo, v26, v10, vcc_lo
	global_load_b64 v[25:26], v[9:10], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[9:10], v30, v[25:28], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[9:10], v[27:28]
	s_cbranch_execz .LBB1_63
; %bb.60:                               ; %.preheader3.i.i19.preheader
                                        ;   in Loop: Header=BB1_2 Depth=1
	s_mov_b32 s5, 0
.LBB1_61:                               ; %.preheader3.i.i19
                                        ;   Parent Loop BB1_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[25:26], v30, s[2:3] offset:40
	global_load_b64 v[34:35], v30, s[2:3]
	v_dual_mov_b32 v28, v10 :: v_dual_mov_b32 v27, v9
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v25, v25, v27
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[9:10], null, v25, 24, v[34:35]
	v_and_b32_e32 v34, v26, v28
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[25:26], null, v34, 24, v[10:11]
	v_mov_b32_e32 v10, v25
	global_load_b64 v[25:26], v[9:10], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[9:10], v30, v[25:28], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[9:10], v[27:28]
	s_or_b32 s5, vcc_lo, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s5
	s_cbranch_execnz .LBB1_61
; %bb.62:                               ; %Flow199
                                        ;   in Loop: Header=BB1_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s5
.LBB1_63:                               ; %Flow201
                                        ;   in Loop: Header=BB1_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s4
.LBB1_64:                               ; %.loopexit4.i.i14
                                        ;   in Loop: Header=BB1_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_waitcnt lgkmcnt(0)
	s_clause 0x1
	global_load_b64 v[34:35], v30, s[2:3] offset:40
	global_load_b128 v[25:28], v30, s[2:3]
	v_readfirstlane_b32 s4, v9
	v_readfirstlane_b32 s5, v10
	s_mov_b32 s15, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s6, v34
	v_readfirstlane_b32 s7, v35
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[6:7], s[4:5], s[6:7]
	s_mul_i32 s1, s7, 24
	s_mul_hi_u32 s13, s6, 24
	s_mul_i32 s14, s6, 24
	s_and_saveexec_b32 s16, s0
	s_cbranch_execz .LBB1_66
; %bb.65:                               ;   in Loop: Header=BB1_2 Depth=1
	s_add_i32 s17, s13, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v34, vcc_lo, v25, s14
	v_add_co_ci_u32_e32 v35, vcc_lo, s17, v26, vcc_lo
	v_dual_mov_b32 v9, s15 :: v_dual_mov_b32 v10, v30
	global_store_b128 v[34:35], v[9:12], off offset:8
.LBB1_66:                               ;   in Loop: Header=BB1_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s16
	v_cmp_lt_u64_e32 vcc_lo, 56, v[4:5]
	v_or_b32_e32 v9, 0, v1
	v_or_b32_e32 v10, v0, v6
	v_lshl_add_u32 v34, v31, 2, 28
	s_lshl_b64 s[6:7], s[6:7], 12
	s_delay_alu instid0(VALU_DEP_2)
	v_dual_cndmask_b32 v1, v9, v1 :: v_dual_cndmask_b32 v0, v10, v0
	v_lshlrev_b64 v[9:10], 6, v[29:30]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v27, vcc_lo, v27, s6
	v_and_b32_e32 v34, 0x1e0, v34
	v_add_co_ci_u32_e32 v28, vcc_lo, s7, v28, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v9, vcc_lo, v27, v9
	v_and_or_b32 v0, 0xffffff1f, v0, v34
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v10, vcc_lo, v28, v10, vcc_lo
	s_clause 0x3
	global_store_b128 v[9:10], v[0:3], off
	global_store_b128 v[9:10], v[13:16], off offset:16
	global_store_b128 v[9:10], v[17:20], off offset:32
	global_store_b128 v[9:10], v[21:24], off offset:48
	s_and_saveexec_b32 s6, s0
	s_cbranch_execz .LBB1_74
; %bb.67:                               ;   in Loop: Header=BB1_2 Depth=1
	s_clause 0x1
	global_load_b64 v[17:18], v30, s[2:3] offset:32 glc
	global_load_b64 v[0:1], v30, s[2:3] offset:40
	v_dual_mov_b32 v15, s4 :: v_dual_mov_b32 v16, s5
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s16, v0
	v_readfirstlane_b32 s17, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[16:17], s[16:17], s[4:5]
	s_mul_i32 s7, s17, 24
	s_mul_hi_u32 s15, s16, 24
	s_mul_i32 s16, s16, 24
	s_add_i32 s15, s15, s7
	v_add_co_u32 v13, vcc_lo, v25, s16
	v_add_co_ci_u32_e32 v14, vcc_lo, s15, v26, vcc_lo
	s_mov_b32 s7, exec_lo
	global_store_b64 v[13:14], v[17:18], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v30, v[15:18], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[2:3], v[17:18]
	s_cbranch_execz .LBB1_70
; %bb.68:                               ; %.preheader1.i.i17.preheader
                                        ;   in Loop: Header=BB1_2 Depth=1
	s_mov_b32 s15, 0
.LBB1_69:                               ; %.preheader1.i.i17
                                        ;   Parent Loop BB1_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s5
	s_sleep 1
	global_store_b64 v[13:14], v[2:3], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[0:1], v30, v[0:3], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
	v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
	s_or_b32 s15, vcc_lo, s15
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s15
	s_cbranch_execnz .LBB1_69
.LBB1_70:                               ; %Flow197
                                        ;   in Loop: Header=BB1_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s7
	global_load_b64 v[0:1], v30, s[2:3] offset:16
	s_mov_b32 s15, exec_lo
	s_mov_b32 s7, exec_lo
	v_mbcnt_lo_u32_b32 v2, s15, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB1_72
; %bb.71:                               ;   in Loop: Header=BB1_2 Depth=1
	s_bcnt1_i32_b32 s15, s15
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v29, s15
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[0:1], v[29:30], off offset:8
.LBB1_72:                               ;   in Loop: Header=BB1_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s7
	s_waitcnt vmcnt(0)
	global_load_b64 v[2:3], v[0:1], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
	s_cbranch_vccnz .LBB1_74
; %bb.73:                               ;   in Loop: Header=BB1_2 Depth=1
	global_load_b32 v29, v[0:1], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s7, v29
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[2:3], v[29:30], off
	s_and_b32 m0, s7, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB1_74:                               ; %Flow198
                                        ;   in Loop: Header=BB1_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s6
	s_add_i32 s13, s13, s1
	v_add_co_u32 v0, vcc_lo, v25, s14
	v_add_co_ci_u32_e32 v1, vcc_lo, s13, v26, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, 20
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
.LBB1_75:                               ;   Parent Loop BB1_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_mov_b32_e32 v2, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_77
; %bb.76:                               ;   in Loop: Header=BB1_75 Depth=2
	global_load_b32 v2, v[0:1], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v2, 1, v2
.LBB1_77:                               ;   in Loop: Header=BB1_75 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v2
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB1_79
; %bb.78:                               ;   in Loop: Header=BB1_75 Depth=2
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB1_80
.LBB1_79:                               ;   in Loop: Header=BB1_75 Depth=2
	s_mov_b32 s1, -1
.LBB1_80:                               ; %Flow192
                                        ;   in Loop: Header=BB1_75 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB1_75
; %bb.81:                               ;   in Loop: Header=BB1_2 Depth=1
	global_load_b128 v[0:3], v[9:10], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_85
; %bb.82:                               ;   in Loop: Header=BB1_2 Depth=1
	s_clause 0x2
	global_load_b64 v[2:3], v30, s[2:3] offset:40
	global_load_b64 v[9:10], v30, s[2:3] offset:24 glc
	global_load_b64 v[15:16], v30, s[2:3]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v17, vcc_lo, v2, 1
	v_add_co_ci_u32_e32 v18, vcc_lo, 0, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v13, vcc_lo, v17, s4
	v_add_co_ci_u32_e32 v14, vcc_lo, s5, v18, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[13:14]
	v_dual_cndmask_b32 v14, v14, v18 :: v_dual_cndmask_b32 v13, v13, v17
	v_and_b32_e32 v3, v14, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v2, v13, v2
	v_mul_lo_u32 v3, v3, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v17, v2, 24
	v_mul_lo_u32 v2, v2, 24
	v_add_nc_u32_e32 v3, v17, v3
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v2, vcc_lo, v15, v2
	v_mov_b32_e32 v15, v9
	v_add_co_ci_u32_e32 v3, vcc_lo, v16, v3, vcc_lo
	v_mov_b32_e32 v16, v10
	global_store_b64 v[2:3], v[9:10], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[15:16], v30, v[13:16], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[15:16], v[9:10]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB1_85
; %bb.83:                               ; %.preheader.i.i16.preheader
                                        ;   in Loop: Header=BB1_2 Depth=1
	s_mov_b32 s0, 0
.LBB1_84:                               ; %.preheader.i.i16
                                        ;   Parent Loop BB1_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	global_store_b64 v[2:3], v[15:16], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[9:10], v30, v[13:16], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[9:10], v[15:16]
	v_dual_mov_b32 v16, v10 :: v_dual_mov_b32 v15, v9
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB1_84
.LBB1_85:                               ; %__ockl_hostcall_preview.exit20
                                        ;   in Loop: Header=BB1_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	v_sub_co_u32 v4, vcc_lo, v4, v31
	v_sub_co_ci_u32_e32 v5, vcc_lo, v5, v32, vcc_lo
	v_add_co_u32 v7, s0, v7, v31
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v8, s0, v8, v32, s0
	v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
	s_or_b32 s12, vcc_lo, s12
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s12
	s_cbranch_execnz .LBB1_2
; %bb.86:                               ; %Flow237
	s_or_b32 exec_lo, exec_lo, s12
                                        ; implicit-def: $vgpr10
.LBB1_87:                               ; %Flow253
	s_and_not1_saveexec_b32 s1, s10
	s_cbranch_execz .LBB1_116
; %bb.88:
	s_load_b64 s[2:3], s[8:9], 0x50
	s_waitcnt vmcnt(0)
	v_mbcnt_lo_u32_b32 v2, -1, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_readfirstlane_b32 s0, v2
	v_mov_b32_e32 v8, 0
	v_mov_b32_e32 v9, 0
	v_cmp_eq_u32_e64 s0, s0, v2
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s4, s0
	s_cbranch_execz .LBB1_94
; %bb.89:
	v_mov_b32_e32 v0, 0
	s_mov_b32 s5, exec_lo
	s_waitcnt lgkmcnt(0)
	global_load_b64 v[5:6], v0, s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[3:4], v0, s[2:3] offset:40
	global_load_b64 v[7:8], v0, s[2:3]
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v3, v3, v5
	v_and_b32_e32 v4, v4, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v9, v3, 24
	v_mul_lo_u32 v4, v4, 24
	v_mul_lo_u32 v3, v3, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v4, v9, v4
	s_waitcnt vmcnt(0)
	v_add_co_u32 v3, vcc_lo, v7, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, v8, v4, vcc_lo
	global_load_b64 v[3:4], v[3:4], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[8:9], v0, v[3:6], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[8:9], v[5:6]
	s_cbranch_execz .LBB1_93
; %bb.90:                               ; %.preheader3.i.i.preheader
	s_mov_b32 s6, 0
.LBB1_91:                               ; %.preheader3.i.i
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[3:4], v0, s[2:3] offset:40
	global_load_b64 v[11:12], v0, s[2:3]
	v_dual_mov_b32 v5, v8 :: v_dual_mov_b32 v6, v9
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v3, v3, v5
	v_and_b32_e32 v4, v4, v6
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[7:8], null, v3, 24, v[11:12]
	v_mov_b32_e32 v3, v8
	s_delay_alu instid0(VALU_DEP_1)
	v_mad_u64_u32 v[8:9], null, v4, 24, v[3:4]
	global_load_b64 v[3:4], v[7:8], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[8:9], v0, v[3:6], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[5:6]
	s_or_b32 s6, vcc_lo, s6
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s6
	s_cbranch_execnz .LBB1_91
; %bb.92:                               ; %Flow249
	s_or_b32 exec_lo, exec_lo, s6
.LBB1_93:                               ; %Flow251
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s5
.LBB1_94:                               ; %.loopexit4.i.i
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s4
	v_mov_b32_e32 v3, 0
	v_readfirstlane_b32 s4, v8
	v_readfirstlane_b32 s5, v9
	s_mov_b32 s11, exec_lo
	s_waitcnt lgkmcnt(0)
	s_clause 0x1
	global_load_b64 v[11:12], v3, s[2:3] offset:40
	global_load_b128 v[4:7], v3, s[2:3]
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s6, v11
	v_readfirstlane_b32 s7, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[6:7], s[4:5], s[6:7]
	s_mul_i32 s8, s7, 24
	s_mul_hi_u32 s9, s6, 24
	s_mul_i32 s10, s6, 24
	s_and_saveexec_b32 s12, s0
	s_cbranch_execz .LBB1_96
; %bb.95:
	s_add_i32 s13, s9, s8
	s_waitcnt vmcnt(0)
	v_add_co_u32 v8, vcc_lo, v4, s10
	v_add_co_ci_u32_e32 v9, vcc_lo, s13, v5, vcc_lo
	v_dual_mov_b32 v11, s11 :: v_dual_mov_b32 v12, v3
	v_dual_mov_b32 v13, 2 :: v_dual_mov_b32 v14, 1
	global_store_b128 v[8:9], v[11:14], off offset:8
.LBB1_96:
	s_or_b32 exec_lo, exec_lo, s12
	s_lshl_b64 s[6:7], s[6:7], 12
	v_lshlrev_b64 v[8:9], 6, v[2:3]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v2, vcc_lo, v6, s6
	v_add_co_ci_u32_e32 v7, vcc_lo, s7, v7, vcc_lo
	s_mov_b32 s12, 0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v6, vcc_lo, v2, v8
	s_mov_b32 s13, s12
	s_mov_b32 s14, s12
	s_mov_b32 s15, s12
	v_and_or_b32 v0, 0xffffff1f, v10, 32
	v_add_co_ci_u32_e32 v7, vcc_lo, v7, v9, vcc_lo
	v_mov_b32_e32 v2, v3
	v_dual_mov_b32 v8, s12 :: v_dual_mov_b32 v11, s15
	v_dual_mov_b32 v9, s13 :: v_dual_mov_b32 v10, s14
	s_clause 0x3
	global_store_b128 v[6:7], v[0:3], off
	global_store_b128 v[6:7], v[8:11], off offset:16
	global_store_b128 v[6:7], v[8:11], off offset:32
	global_store_b128 v[6:7], v[8:11], off offset:48
	s_and_saveexec_b32 s6, s0
	s_cbranch_execz .LBB1_104
; %bb.97:
	v_mov_b32_e32 v10, 0
	s_mov_b32 s7, exec_lo
	s_clause 0x1
	global_load_b64 v[13:14], v10, s[2:3] offset:32 glc
	global_load_b64 v[0:1], v10, s[2:3] offset:40
	v_dual_mov_b32 v11, s4 :: v_dual_mov_b32 v12, s5
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v1, s5, v1
	v_and_b32_e32 v0, s4, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v1, v1, 24
	v_mul_hi_u32 v2, v0, 24
	v_mul_lo_u32 v0, v0, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v1, v2, v1
	v_add_co_u32 v8, vcc_lo, v4, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v9, vcc_lo, v5, v1, vcc_lo
	global_store_b64 v[8:9], v[13:14], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v10, v[11:14], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[2:3], v[13:14]
	s_cbranch_execz .LBB1_100
; %bb.98:                               ; %.preheader1.i.i.preheader
	s_mov_b32 s11, 0
.LBB1_99:                               ; %.preheader1.i.i
                                        ; =>This Inner Loop Header: Depth=1
	v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s5
	s_sleep 1
	global_store_b64 v[8:9], v[2:3], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[0:1], v10, v[0:3], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
	v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
	s_or_b32 s11, vcc_lo, s11
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s11
	s_cbranch_execnz .LBB1_99
.LBB1_100:                              ; %Flow247
	s_or_b32 exec_lo, exec_lo, s7
	v_mov_b32_e32 v3, 0
	s_mov_b32 s11, exec_lo
	s_mov_b32 s7, exec_lo
	v_mbcnt_lo_u32_b32 v2, s11, 0
	global_load_b64 v[0:1], v3, s[2:3] offset:16
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB1_102
; %bb.101:
	s_bcnt1_i32_b32 s11, s11
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v2, s11
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[0:1], v[2:3], off offset:8
.LBB1_102:
	s_or_b32 exec_lo, exec_lo, s7
	s_waitcnt vmcnt(0)
	global_load_b64 v[2:3], v[0:1], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
	s_cbranch_vccnz .LBB1_104
; %bb.103:
	global_load_b32 v0, v[0:1], off offset:24
	v_mov_b32_e32 v1, 0
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s7, v0
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[2:3], v[0:1], off
	s_and_b32 m0, s7, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB1_104:                              ; %Flow248
	s_or_b32 exec_lo, exec_lo, s6
	s_add_i32 s9, s9, s8
	v_add_co_u32 v0, vcc_lo, v4, s10
	v_add_co_ci_u32_e32 v1, vcc_lo, s9, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, 20
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
.LBB1_105:                              ; =>This Inner Loop Header: Depth=1
	v_mov_b32_e32 v2, 1
	s_and_saveexec_b32 s6, s0
	s_cbranch_execz .LBB1_107
; %bb.106:                              ;   in Loop: Header=BB1_105 Depth=1
	global_load_b32 v2, v[0:1], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v2, 1, v2
.LBB1_107:                              ;   in Loop: Header=BB1_105 Depth=1
	s_or_b32 exec_lo, exec_lo, s6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s6, v2
	s_cmp_eq_u32 s6, 0
	s_cbranch_scc1 .LBB1_109
; %bb.108:                              ;   in Loop: Header=BB1_105 Depth=1
	s_mov_b32 s6, 0
	s_sleep 1
	s_branch .LBB1_110
.LBB1_109:                              ;   in Loop: Header=BB1_105 Depth=1
	s_mov_b32 s6, -1
.LBB1_110:                              ; %Flow242
                                        ;   in Loop: Header=BB1_105 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s6
	s_cbranch_vccnz .LBB1_105
; %bb.111:
	global_load_b128 v[0:3], v[6:7], off
	s_and_saveexec_b32 s6, s0
	s_cbranch_execz .LBB1_115
; %bb.112:
	v_mov_b32_e32 v8, 0
	s_clause 0x2
	global_load_b64 v[4:5], v8, s[2:3] offset:40
	global_load_b64 v[9:10], v8, s[2:3] offset:24 glc
	global_load_b64 v[6:7], v8, s[2:3]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v11, vcc_lo, v4, 1
	v_add_co_ci_u32_e32 v12, vcc_lo, 0, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, v11, s4
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v12, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
	v_dual_cndmask_b32 v3, v3, v12 :: v_dual_cndmask_b32 v2, v2, v11
	v_and_b32_e32 v5, v3, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v4, v2, v4
	v_mul_lo_u32 v5, v5, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v11, v4, 24
	v_mul_lo_u32 v4, v4, 24
	v_add_nc_u32_e32 v5, v11, v5
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v6, vcc_lo, v6, v4
	v_mov_b32_e32 v4, v9
	v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
	v_mov_b32_e32 v5, v10
	global_store_b64 v[6:7], v[9:10], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[4:5], v8, v[2:5], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[4:5], v[9:10]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB1_115
; %bb.113:                              ; %.preheader.i.i.preheader
	s_mov_b32 s0, 0
.LBB1_114:                              ; %.preheader.i.i
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	global_store_b64 v[6:7], v[4:5], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[9:10], v8, v[2:5], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[9:10], v[4:5]
	v_dual_mov_b32 v4, v9 :: v_dual_mov_b32 v5, v10
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB1_114
.LBB1_115:                              ; %__ockl_hostcall_preview.exit
	s_or_b32 exec_lo, exec_lo, s6
.LBB1_116:                              ; %Flow254
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_waitcnt vmcnt(0) lgkmcnt(0)
	s_setpc_b64 s[30:31]
.Lfunc_end1:
	.size	__ockl_printf_append_string_n, .Lfunc_end1-__ockl_printf_append_string_n
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Function info:
; codeLenInByte = 5708
; NumSgprs: 34
; NumVgprs: 36
; ScratchSize: 0
; MemoryBound: 0
	.text
	.protected	_Z26kernel_reduce_sum_3d_try02PKfPfiiiiii ; -- Begin function _Z26kernel_reduce_sum_3d_try02PKfPfiiiiii
	.globl	_Z26kernel_reduce_sum_3d_try02PKfPfiiiiii
	.p2align	8
	.type	_Z26kernel_reduce_sum_3d_try02PKfPfiiiiii,@function
_Z26kernel_reduce_sum_3d_try02PKfPfiiiiii: ; @_Z26kernel_reduce_sum_3d_try02PKfPfiiiiii
; %bb.0:
	s_mov_b64 s[18:19], s[0:1]
	s_clause 0x2
	s_load_b64 s[0:1], s[0:1], 0x20
	s_load_b128 s[24:27], s[18:19], 0x10
	s_load_b64 s[34:35], s[18:19], 0x0
	v_mov_b32_e32 v38, v0
	s_mov_b32 s20, s15
	s_mov_b32 s33, 0
	s_mov_b32 s32, 0
	s_waitcnt lgkmcnt(0)
	s_cmp_lg_u32 s0, 1
	s_cselect_b32 s2, -1, 0
	s_or_b32 s3, s1, s27
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_cmp_lg_u32 s3, 0
	s_cselect_b32 s3, -1, 0
	s_or_b32 s2, s2, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s2
	s_cbranch_vccz .LBB2_223
; %bb.1:
	s_or_b32 s0, s0, s27
	s_mov_b32 s27, 0
	s_cmp_eq_u32 s0, 0
	s_cselect_b32 s0, -1, 0
	s_cmp_eq_u32 s1, 1
	s_cselect_b32 s1, -1, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, s0, s1
	s_and_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccz .LBB2_224
; %bb.2:
	s_clause 0x1
	s_load_b32 s21, s[18:19], 0x34
	s_load_b64 s[22:23], s[18:19], 0x78
	v_mbcnt_lo_u32_b32 v54, -1, 0
	v_mov_b32_e32 v6, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v7, 0 :: v_dual_mov_b32 v4, v54
	;;#ASMSTART
	;;#ASMEND
	v_readfirstlane_b32 s0, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_eq_u32_e64 s0, s0, v4
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB2_8
; %bb.3:
	v_mov_b32_e32 v0, 0
	s_mov_b32 s2, exec_lo
	s_waitcnt lgkmcnt(0)
	global_load_b64 v[8:9], v0, s[22:23] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[1:2], v0, s[22:23] offset:40
	global_load_b64 v[5:6], v0, s[22:23]
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v1, v1, v8
	v_and_b32_e32 v2, v2, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v3, v1, 24
	v_mul_lo_u32 v2, v2, 24
	v_mul_lo_u32 v1, v1, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v2, v3, v2
	s_waitcnt vmcnt(0)
	v_add_co_u32 v1, vcc_lo, v5, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, v6, v2, vcc_lo
	global_load_b64 v[6:7], v[1:2], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[22:23] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[6:7], v[8:9]
	s_cbranch_execz .LBB2_7
; %bb.4:                                ; %.preheader3.i.i.i119.preheader
	s_mov_b32 s3, 0
.LBB2_5:                                ; %.preheader3.i.i.i119
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[1:2], v0, s[22:23] offset:40
	global_load_b64 v[10:11], v0, s[22:23]
	v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v1, v1, v8
	v_and_b32_e32 v7, v2, v9
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[5:6], null, v1, 24, v[10:11]
	v_mov_b32_e32 v1, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[2:3], null, v7, 24, v[1:2]
	v_mov_b32_e32 v6, v2
	global_load_b64 v[6:7], v[5:6], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[22:23] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[8:9]
	s_or_b32 s3, vcc_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s3
	s_cbranch_execnz .LBB2_5
; %bb.6:                                ; %Flow665
	s_or_b32 exec_lo, exec_lo, s3
.LBB2_7:                                ; %Flow667
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s2
.LBB2_8:                                ; %.loopexit4.i.i.i114
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	v_mov_b32_e32 v5, 0
	v_readfirstlane_b32 s2, v6
	v_readfirstlane_b32 s3, v7
	s_mov_b32 s8, exec_lo
	s_waitcnt lgkmcnt(0)
	s_clause 0x1
	global_load_b64 v[8:9], v5, s[22:23] offset:40
	global_load_b128 v[0:3], v5, s[22:23]
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s4, v8
	v_readfirstlane_b32 s5, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[4:5], s[2:3], s[4:5]
	s_mul_i32 s1, s5, 24
	s_mul_hi_u32 s6, s4, 24
	s_mul_i32 s7, s4, 24
	s_and_saveexec_b32 s9, s0
	s_cbranch_execz .LBB2_10
; %bb.9:
	v_dual_mov_b32 v6, s8 :: v_dual_mov_b32 v7, v5
	s_add_i32 s8, s6, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v10, vcc_lo, v0, s7
	v_add_co_ci_u32_e32 v11, vcc_lo, s8, v1, vcc_lo
	v_dual_mov_b32 v8, 2 :: v_dual_mov_b32 v9, 1
	global_store_b128 v[10:11], v[6:9], off offset:8
.LBB2_10:
	s_or_b32 exec_lo, exec_lo, s9
	s_lshl_b64 s[4:5], s[4:5], 12
	v_lshlrev_b64 v[6:7], 6, v[4:5]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v2, vcc_lo, v2, s4
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
	s_mov_b32 s8, 0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v8, vcc_lo, v2, v6
	s_mov_b32 s11, s8
	s_mov_b32 s9, s8
	s_mov_b32 s10, s8
	v_add_co_ci_u32_e32 v9, vcc_lo, v3, v7, vcc_lo
	v_dual_mov_b32 v4, 33 :: v_dual_mov_b32 v7, v5
	v_dual_mov_b32 v6, v5 :: v_dual_mov_b32 v13, s11
	v_dual_mov_b32 v12, s10 :: v_dual_mov_b32 v11, s9
	v_mov_b32_e32 v10, s8
	s_clause 0x3
	global_store_b128 v[8:9], v[4:7], off
	global_store_b128 v[8:9], v[10:13], off offset:16
	global_store_b128 v[8:9], v[10:13], off offset:32
	global_store_b128 v[8:9], v[10:13], off offset:48
	s_and_saveexec_b32 s4, s0
	s_cbranch_execz .LBB2_17
; %bb.11:
	v_mov_b32_e32 v10, 0
	s_mov_b32 s5, exec_lo
	s_clause 0x1
	global_load_b64 v[13:14], v10, s[22:23] offset:32 glc
	global_load_b64 v[2:3], v10, s[22:23] offset:40
	v_dual_mov_b32 v11, s2 :: v_dual_mov_b32 v12, s3
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v3, s3, v3
	v_and_b32_e32 v2, s2, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v3, v3, 24
	v_mul_hi_u32 v4, v2, 24
	v_mul_lo_u32 v2, v2, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v3, v4, v3
	v_add_co_u32 v6, vcc_lo, v0, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v7, vcc_lo, v1, v3, vcc_lo
	global_store_b64 v[6:7], v[13:14], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[4:5], v10, v[11:14], s[22:23] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[4:5], v[13:14]
	s_cbranch_execz .LBB2_13
.LBB2_12:                               ; %.preheader1.i.i.i117
                                        ; =>This Inner Loop Header: Depth=1
	v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
	s_sleep 1
	global_store_b64 v[6:7], v[4:5], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v10, v[2:5], s[22:23] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
	v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
	s_or_b32 s8, vcc_lo, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s8
	s_cbranch_execnz .LBB2_12
.LBB2_13:                               ; %Flow663
	s_or_b32 exec_lo, exec_lo, s5
	v_mov_b32_e32 v5, 0
	s_mov_b32 s8, exec_lo
	s_mov_b32 s5, exec_lo
	v_mbcnt_lo_u32_b32 v4, s8, 0
	global_load_b64 v[2:3], v5, s[22:23] offset:16
	v_cmpx_eq_u32_e32 0, v4
	s_cbranch_execz .LBB2_15
; %bb.14:
	s_bcnt1_i32_b32 s8, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v4, s8
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[2:3], v[4:5], off offset:8
.LBB2_15:
	s_or_b32 exec_lo, exec_lo, s5
	s_waitcnt vmcnt(0)
	global_load_b64 v[4:5], v[2:3], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
	s_cbranch_vccnz .LBB2_17
; %bb.16:
	global_load_b32 v2, v[2:3], off offset:24
	v_mov_b32_e32 v3, 0
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s5, v2
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[4:5], v[2:3], off
	s_and_b32 m0, s5, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB2_17:                               ; %Flow664
	s_or_b32 exec_lo, exec_lo, s4
	s_add_i32 s6, s6, s1
	v_add_co_u32 v0, vcc_lo, v0, s7
	v_add_co_ci_u32_e32 v1, vcc_lo, s6, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, 20
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
.LBB2_18:                               ; =>This Inner Loop Header: Depth=1
	v_mov_b32_e32 v2, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB2_20
; %bb.19:                               ;   in Loop: Header=BB2_18 Depth=1
	global_load_b32 v2, v[0:1], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v2, 1, v2
.LBB2_20:                               ;   in Loop: Header=BB2_18 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v2
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB2_22
; %bb.21:                               ;   in Loop: Header=BB2_18 Depth=1
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB2_23
.LBB2_22:                               ;   in Loop: Header=BB2_18 Depth=1
	s_mov_b32 s1, -1
.LBB2_23:                               ; %Flow658
                                        ;   in Loop: Header=BB2_18 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB2_18
; %bb.24:
	global_load_b64 v[0:1], v[8:9], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB2_28
; %bb.25:
	v_mov_b32_e32 v8, 0
	s_clause 0x2
	global_load_b64 v[4:5], v8, s[22:23] offset:40
	global_load_b64 v[9:10], v8, s[22:23] offset:24 glc
	global_load_b64 v[6:7], v8, s[22:23]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v11, vcc_lo, v4, 1
	v_add_co_ci_u32_e32 v12, vcc_lo, 0, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, v11, s2
	v_add_co_ci_u32_e32 v3, vcc_lo, s3, v12, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
	v_dual_cndmask_b32 v3, v3, v12 :: v_dual_cndmask_b32 v2, v2, v11
	v_and_b32_e32 v5, v3, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v4, v2, v4
	v_mul_lo_u32 v5, v5, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v11, v4, 24
	v_mul_lo_u32 v4, v4, 24
	v_add_nc_u32_e32 v5, v11, v5
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v6, vcc_lo, v6, v4
	v_mov_b32_e32 v4, v9
	v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
	v_mov_b32_e32 v5, v10
	global_store_b64 v[6:7], v[9:10], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[4:5], v8, v[2:5], s[22:23] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[4:5], v[9:10]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB2_28
; %bb.26:                               ; %.preheader.i.i.i116.preheader
	s_mov_b32 s0, 0
.LBB2_27:                               ; %.preheader.i.i.i116
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	global_store_b64 v[6:7], v[4:5], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[9:10], v8, v[2:5], s[22:23] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[9:10], v[4:5]
	v_dual_mov_b32 v4, v9 :: v_dual_mov_b32 v5, v10
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB2_27
.LBB2_28:                               ; %__ockl_printf_begin.exit120
	s_or_b32 exec_lo, exec_lo, s1
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, .str.1@rel32@lo+4
	s_addc_u32 s1, s1, .str.1@rel32@hi+12
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
	v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
	s_cmp_lg_u64 s[0:1], 0
	v_mov_b32_e32 v6, 0
	s_cselect_b32 s4, 40, 0
	v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s4
	s_add_u32 s8, s18, 40
	s_addc_u32 s9, s19, 0
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, __ockl_printf_append_string_n@rel32@lo+4
	s_addc_u32 s3, s3, __ockl_printf_append_string_n@rel32@hi+12
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	s_swappc_b64 s[30:31], s[2:3]
	v_mov_b32_e32 v5, v54
	;;#ASMSTART
	;;#ASMEND
	v_readfirstlane_b32 s0, v5
	v_mov_b32_e32 v7, 0
	v_dual_mov_b32 v37, v1 :: v_dual_mov_b32 v8, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_eq_u32_e64 s0, s0, v5
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB2_34
; %bb.29:
	v_mov_b32_e32 v1, 0
	s_mov_b32 s2, exec_lo
	global_load_b64 v[9:10], v1, s[22:23] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[2:3], v1, s[22:23] offset:40
	global_load_b64 v[6:7], v1, s[22:23]
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v2, v2, v9
	v_and_b32_e32 v3, v3, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v4, v2, 24
	v_mul_lo_u32 v3, v3, 24
	v_mul_lo_u32 v2, v2, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v3, v4, v3
	s_waitcnt vmcnt(0)
	v_add_co_u32 v2, vcc_lo, v6, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, v7, v3, vcc_lo
	global_load_b64 v[7:8], v[2:3], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[7:8], v1, v[7:10], s[22:23] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[7:8], v[9:10]
	s_cbranch_execz .LBB2_33
; %bb.30:                               ; %.preheader3.i.i.i126.preheader
	s_mov_b32 s3, 0
.LBB2_31:                               ; %.preheader3.i.i.i126
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[2:3], v1, s[22:23] offset:40
	global_load_b64 v[11:12], v1, s[22:23]
	v_dual_mov_b32 v10, v8 :: v_dual_mov_b32 v9, v7
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v2, v2, v9
	v_and_b32_e32 v8, v3, v10
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[6:7], null, v2, 24, v[11:12]
	v_mov_b32_e32 v2, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[3:4], null, v8, 24, v[2:3]
	v_mov_b32_e32 v7, v3
	global_load_b64 v[7:8], v[6:7], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[7:8], v1, v[7:10], s[22:23] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[9:10]
	s_or_b32 s3, vcc_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s3
	s_cbranch_execnz .LBB2_31
; %bb.32:                               ; %Flow651
	s_or_b32 exec_lo, exec_lo, s3
.LBB2_33:                               ; %Flow653
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s2
.LBB2_34:                               ; %.loopexit4.i.i.i121
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	v_mov_b32_e32 v6, 0
	v_readfirstlane_b32 s2, v7
	v_readfirstlane_b32 s3, v8
	s_mov_b32 s8, exec_lo
	s_clause 0x1
	global_load_b64 v[9:10], v6, s[22:23] offset:40
	global_load_b128 v[1:4], v6, s[22:23]
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s4, v9
	v_readfirstlane_b32 s5, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[4:5], s[2:3], s[4:5]
	s_mul_i32 s1, s5, 24
	s_mul_hi_u32 s6, s4, 24
	s_mul_i32 s7, s4, 24
	s_and_saveexec_b32 s9, s0
	s_cbranch_execz .LBB2_36
; %bb.35:
	v_dual_mov_b32 v7, s8 :: v_dual_mov_b32 v8, v6
	s_add_i32 s8, s6, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v11, vcc_lo, v1, s7
	v_add_co_ci_u32_e32 v12, vcc_lo, s8, v2, vcc_lo
	v_dual_mov_b32 v9, 2 :: v_dual_mov_b32 v10, 1
	global_store_b128 v[11:12], v[7:10], off offset:8
.LBB2_36:
	s_or_b32 exec_lo, exec_lo, s9
	s_lshl_b64 s[4:5], s[4:5], 12
	v_lshlrev_b64 v[7:8], 6, v[5:6]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v3, vcc_lo, v3, s4
	v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
	s_mov_b32 s8, 0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v7, vcc_lo, v3, v7
	s_mov_b32 s9, s8
	s_mov_b32 s10, s8
	s_mov_b32 s11, s8
	v_and_or_b32 v36, 0xffffff1f, v0, 32
	v_add_co_ci_u32_e32 v8, vcc_lo, v4, v8, vcc_lo
	v_mov_b32_e32 v39, v6
	v_dual_mov_b32 v3, s8 :: v_dual_mov_b32 v6, s11
	v_dual_mov_b32 v4, s9 :: v_dual_mov_b32 v5, s10
	s_clause 0x3
	global_store_b128 v[7:8], v[36:39], off
	global_store_b128 v[7:8], v[3:6], off offset:16
	global_store_b128 v[7:8], v[3:6], off offset:32
	global_store_b128 v[7:8], v[3:6], off offset:48
	s_and_saveexec_b32 s4, s0
	s_cbranch_execz .LBB2_44
; %bb.37:
	v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v11, s2
	v_mov_b32_e32 v12, s3
	s_clause 0x1
	global_load_b64 v[13:14], v0, s[22:23] offset:32 glc
	global_load_b64 v[3:4], v0, s[22:23] offset:40
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s8, v3
	v_readfirstlane_b32 s9, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[8:9], s[8:9], s[2:3]
	s_mul_i32 s5, s9, 24
	s_mul_hi_u32 s9, s8, 24
	s_mul_i32 s8, s8, 24
	s_add_i32 s9, s9, s5
	v_add_co_u32 v9, vcc_lo, v1, s8
	v_add_co_ci_u32_e32 v10, vcc_lo, s9, v2, vcc_lo
	s_mov_b32 s5, exec_lo
	global_store_b64 v[9:10], v[13:14], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[5:6], v0, v[11:14], s[22:23] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[5:6], v[13:14]
	s_cbranch_execz .LBB2_40
; %bb.38:                               ; %.preheader1.i.i.i124.preheader
	s_mov_b32 s8, 0
.LBB2_39:                               ; %.preheader1.i.i.i124
                                        ; =>This Inner Loop Header: Depth=1
	v_dual_mov_b32 v3, s2 :: v_dual_mov_b32 v4, s3
	s_sleep 1
	global_store_b64 v[9:10], v[5:6], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[3:4], v0, v[3:6], s[22:23] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[3:4], v[5:6]
	v_dual_mov_b32 v6, v4 :: v_dual_mov_b32 v5, v3
	s_or_b32 s8, vcc_lo, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s8
	s_cbranch_execnz .LBB2_39
.LBB2_40:                               ; %Flow649
	s_or_b32 exec_lo, exec_lo, s5
	v_mov_b32_e32 v6, 0
	s_mov_b32 s8, exec_lo
	s_mov_b32 s5, exec_lo
	v_mbcnt_lo_u32_b32 v0, s8, 0
	global_load_b64 v[3:4], v6, s[22:23] offset:16
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB2_42
; %bb.41:
	s_bcnt1_i32_b32 s8, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v5, s8
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[3:4], v[5:6], off offset:8
.LBB2_42:
	s_or_b32 exec_lo, exec_lo, s5
	s_waitcnt vmcnt(0)
	global_load_b64 v[5:6], v[3:4], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[5:6]
	s_cbranch_vccnz .LBB2_44
; %bb.43:
	global_load_b32 v3, v[3:4], off offset:24
	v_mov_b32_e32 v4, 0
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s5, v3
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[5:6], v[3:4], off
	s_and_b32 m0, s5, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB2_44:                               ; %Flow650
	s_or_b32 exec_lo, exec_lo, s4
	s_add_i32 s6, s6, s1
	v_add_co_u32 v0, vcc_lo, v1, s7
	v_add_co_ci_u32_e32 v1, vcc_lo, s6, v2, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, 20
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
.LBB2_45:                               ; =>This Inner Loop Header: Depth=1
	v_mov_b32_e32 v2, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB2_47
; %bb.46:                               ;   in Loop: Header=BB2_45 Depth=1
	global_load_b32 v2, v[0:1], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v2, 1, v2
.LBB2_47:                               ;   in Loop: Header=BB2_45 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v2
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB2_49
; %bb.48:                               ;   in Loop: Header=BB2_45 Depth=1
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB2_50
.LBB2_49:                               ;   in Loop: Header=BB2_45 Depth=1
	s_mov_b32 s1, -1
.LBB2_50:                               ; %Flow644
                                        ;   in Loop: Header=BB2_45 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB2_45
; %bb.51:
	global_load_b64 v[0:1], v[7:8], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB2_55
; %bb.52:
	v_mov_b32_e32 v8, 0
	s_clause 0x2
	global_load_b64 v[4:5], v8, s[22:23] offset:40
	global_load_b64 v[9:10], v8, s[22:23] offset:24 glc
	global_load_b64 v[6:7], v8, s[22:23]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v11, vcc_lo, v4, 1
	v_add_co_ci_u32_e32 v12, vcc_lo, 0, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, v11, s2
	v_add_co_ci_u32_e32 v3, vcc_lo, s3, v12, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
	v_dual_cndmask_b32 v3, v3, v12 :: v_dual_cndmask_b32 v2, v2, v11
	v_and_b32_e32 v5, v3, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v4, v2, v4
	v_mul_lo_u32 v5, v5, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v11, v4, 24
	v_mul_lo_u32 v4, v4, 24
	v_add_nc_u32_e32 v5, v11, v5
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v6, vcc_lo, v6, v4
	v_mov_b32_e32 v4, v9
	v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
	v_mov_b32_e32 v5, v10
	global_store_b64 v[6:7], v[9:10], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[4:5], v8, v[2:5], s[22:23] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[4:5], v[9:10]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB2_55
; %bb.53:                               ; %.preheader.i.i.i123.preheader
	s_mov_b32 s0, 0
.LBB2_54:                               ; %.preheader.i.i.i123
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	global_store_b64 v[6:7], v[4:5], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[9:10], v8, v[2:5], s[22:23] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[9:10], v[4:5]
	v_dual_mov_b32 v4, v9 :: v_dual_mov_b32 v5, v10
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB2_54
.LBB2_55:                               ; %__ockl_printf_append_args.exit127
	s_or_b32 exec_lo, exec_lo, s1
	v_mov_b32_e32 v2, v54
	v_mov_b32_e32 v8, 0
	v_mov_b32_e32 v9, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s0, v2
	v_cmp_eq_u32_e64 s0, s0, v2
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB2_61
; %bb.56:
	v_mov_b32_e32 v3, 0
	s_mov_b32 s2, exec_lo
	global_load_b64 v[6:7], v3, s[22:23] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[4:5], v3, s[22:23] offset:40
	global_load_b64 v[8:9], v3, s[22:23]
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v4, v4, v6
	v_and_b32_e32 v5, v5, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v10, v4, 24
	v_mul_lo_u32 v5, v5, 24
	v_mul_lo_u32 v4, v4, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v5, v10, v5
	s_waitcnt vmcnt(0)
	v_add_co_u32 v4, vcc_lo, v8, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, v9, v5, vcc_lo
	global_load_b64 v[4:5], v[4:5], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[8:9], v3, v[4:7], s[22:23] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[8:9], v[6:7]
	s_cbranch_execz .LBB2_60
; %bb.57:                               ; %.preheader3.i.i.i133.preheader
	s_mov_b32 s3, 0
.LBB2_58:                               ; %.preheader3.i.i.i133
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[4:5], v3, s[22:23] offset:40
	global_load_b64 v[10:11], v3, s[22:23]
	v_dual_mov_b32 v6, v8 :: v_dual_mov_b32 v7, v9
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v4, v4, v6
	v_and_b32_e32 v5, v5, v7
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[8:9], null, v4, 24, v[10:11]
	v_mov_b32_e32 v4, v9
	s_delay_alu instid0(VALU_DEP_1)
	v_mad_u64_u32 v[9:10], null, v5, 24, v[4:5]
	global_load_b64 v[4:5], v[8:9], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[8:9], v3, v[4:7], s[22:23] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[6:7]
	s_or_b32 s3, vcc_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s3
	s_cbranch_execnz .LBB2_58
; %bb.59:                               ; %Flow637
	s_or_b32 exec_lo, exec_lo, s3
.LBB2_60:                               ; %Flow639
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s2
.LBB2_61:                               ; %.loopexit4.i.i.i128
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	v_mov_b32_e32 v3, 0
	v_readfirstlane_b32 s2, v8
	v_readfirstlane_b32 s3, v9
	s_mov_b32 s8, exec_lo
	s_clause 0x1
	global_load_b64 v[10:11], v3, s[22:23] offset:40
	global_load_b128 v[4:7], v3, s[22:23]
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s4, v10
	v_readfirstlane_b32 s5, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[4:5], s[2:3], s[4:5]
	s_mul_i32 s1, s5, 24
	s_mul_hi_u32 s6, s4, 24
	s_mul_i32 s7, s4, 24
	s_and_saveexec_b32 s9, s0
	s_cbranch_execz .LBB2_63
; %bb.62:
	v_dual_mov_b32 v8, s8 :: v_dual_mov_b32 v9, v3
	s_add_i32 s8, s6, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v12, vcc_lo, v4, s7
	v_add_co_ci_u32_e32 v13, vcc_lo, s8, v5, vcc_lo
	v_dual_mov_b32 v10, 2 :: v_dual_mov_b32 v11, 1
	global_store_b128 v[12:13], v[8:11], off offset:8
.LBB2_63:
	s_or_b32 exec_lo, exec_lo, s9
	s_lshl_b64 s[4:5], s[4:5], 12
	s_mov_b32 s8, 0
	s_waitcnt vmcnt(0)
	v_add_co_u32 v8, vcc_lo, v6, s4
	s_and_b32 s4, 0xffff, s21
	v_add_co_ci_u32_e32 v9, vcc_lo, s5, v7, vcc_lo
	v_lshlrev_b64 v[6:7], 6, v[2:3]
	v_mad_u64_u32 v[41:42], null, s20, s4, v[38:39]
	s_mov_b32 s9, s8
	s_mov_b32 s10, s8
	s_mov_b32 s11, s8
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_add_co_u32 v6, vcc_lo, v8, v6
	v_and_or_b32 v0, 0xffffff1f, v0, 32
	v_add_co_ci_u32_e32 v7, vcc_lo, v9, v7, vcc_lo
	v_mov_b32_e32 v2, v41
	v_dual_mov_b32 v8, s8 :: v_dual_mov_b32 v11, s11
	v_dual_mov_b32 v42, v3 :: v_dual_mov_b32 v9, s9
	v_mov_b32_e32 v10, s10
	s_clause 0x3
	global_store_b128 v[6:7], v[0:3], off
	global_store_b128 v[6:7], v[8:11], off offset:16
	global_store_b128 v[6:7], v[8:11], off offset:32
	global_store_b128 v[6:7], v[8:11], off offset:48
	s_and_saveexec_b32 s4, s0
	s_cbranch_execz .LBB2_71
; %bb.64:
	v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v11, s2
	v_mov_b32_e32 v12, s3
	s_clause 0x1
	global_load_b64 v[13:14], v10, s[22:23] offset:32 glc
	global_load_b64 v[0:1], v10, s[22:23] offset:40
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s8, v0
	v_readfirstlane_b32 s9, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[8:9], s[8:9], s[2:3]
	s_mul_i32 s5, s9, 24
	s_mul_hi_u32 s9, s8, 24
	s_mul_i32 s8, s8, 24
	s_add_i32 s9, s9, s5
	v_add_co_u32 v8, vcc_lo, v4, s8
	v_add_co_ci_u32_e32 v9, vcc_lo, s9, v5, vcc_lo
	s_mov_b32 s5, exec_lo
	global_store_b64 v[8:9], v[13:14], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v10, v[11:14], s[22:23] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[2:3], v[13:14]
	s_cbranch_execz .LBB2_67
; %bb.65:                               ; %.preheader1.i.i.i131.preheader
	s_mov_b32 s8, 0
.LBB2_66:                               ; %.preheader1.i.i.i131
                                        ; =>This Inner Loop Header: Depth=1
	v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
	s_sleep 1
	global_store_b64 v[8:9], v[2:3], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[0:1], v10, v[0:3], s[22:23] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
	v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
	s_or_b32 s8, vcc_lo, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s8
	s_cbranch_execnz .LBB2_66
.LBB2_67:                               ; %Flow635
	s_or_b32 exec_lo, exec_lo, s5
	v_mov_b32_e32 v3, 0
	s_mov_b32 s8, exec_lo
	s_mov_b32 s5, exec_lo
	v_mbcnt_lo_u32_b32 v2, s8, 0
	global_load_b64 v[0:1], v3, s[22:23] offset:16
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB2_69
; %bb.68:
	s_bcnt1_i32_b32 s8, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v2, s8
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[0:1], v[2:3], off offset:8
.LBB2_69:
	s_or_b32 exec_lo, exec_lo, s5
	s_waitcnt vmcnt(0)
	global_load_b64 v[2:3], v[0:1], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
	s_cbranch_vccnz .LBB2_71
; %bb.70:
	global_load_b32 v0, v[0:1], off offset:24
	v_mov_b32_e32 v1, 0
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s5, v0
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[2:3], v[0:1], off
	s_and_b32 m0, s5, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB2_71:                               ; %Flow636
	s_or_b32 exec_lo, exec_lo, s4
	s_add_i32 s6, s6, s1
	v_add_co_u32 v0, vcc_lo, v4, s7
	v_add_co_ci_u32_e32 v1, vcc_lo, s6, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, 20
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
.LBB2_72:                               ; =>This Inner Loop Header: Depth=1
	v_mov_b32_e32 v2, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB2_74
; %bb.73:                               ;   in Loop: Header=BB2_72 Depth=1
	global_load_b32 v2, v[0:1], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v2, 1, v2
.LBB2_74:                               ;   in Loop: Header=BB2_72 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v2
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB2_76
; %bb.75:                               ;   in Loop: Header=BB2_72 Depth=1
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB2_77
.LBB2_76:                               ;   in Loop: Header=BB2_72 Depth=1
	s_mov_b32 s1, -1
.LBB2_77:                               ; %Flow630
                                        ;   in Loop: Header=BB2_72 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB2_72
; %bb.78:
	global_load_b64 v[0:1], v[6:7], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB2_82
; %bb.79:
	v_mov_b32_e32 v8, 0
	s_clause 0x2
	global_load_b64 v[4:5], v8, s[22:23] offset:40
	global_load_b64 v[9:10], v8, s[22:23] offset:24 glc
	global_load_b64 v[6:7], v8, s[22:23]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v11, vcc_lo, v4, 1
	v_add_co_ci_u32_e32 v12, vcc_lo, 0, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, v11, s2
	v_add_co_ci_u32_e32 v3, vcc_lo, s3, v12, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
	v_dual_cndmask_b32 v3, v3, v12 :: v_dual_cndmask_b32 v2, v2, v11
	v_and_b32_e32 v5, v3, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v4, v2, v4
	v_mul_lo_u32 v5, v5, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v11, v4, 24
	v_mul_lo_u32 v4, v4, 24
	v_add_nc_u32_e32 v5, v11, v5
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v6, vcc_lo, v6, v4
	v_mov_b32_e32 v4, v9
	v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
	v_mov_b32_e32 v5, v10
	global_store_b64 v[6:7], v[9:10], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[4:5], v8, v[2:5], s[22:23] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[4:5], v[9:10]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB2_82
; %bb.80:                               ; %.preheader.i.i.i130.preheader
	s_mov_b32 s0, 0
.LBB2_81:                               ; %.preheader.i.i.i130
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	global_store_b64 v[6:7], v[4:5], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[9:10], v8, v[2:5], s[22:23] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[9:10], v[4:5]
	v_dual_mov_b32 v4, v9 :: v_dual_mov_b32 v5, v10
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB2_81
.LBB2_82:                               ; %__ockl_printf_append_args.exit134
	s_or_b32 exec_lo, exec_lo, s1
	v_mov_b32_e32 v2, v54
	v_mov_b32_e32 v8, 0
	v_mov_b32_e32 v9, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s0, v2
	v_cmp_eq_u32_e64 s0, s0, v2
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB2_88
; %bb.83:
	v_mov_b32_e32 v3, 0
	s_mov_b32 s2, exec_lo
	global_load_b64 v[6:7], v3, s[22:23] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[4:5], v3, s[22:23] offset:40
	global_load_b64 v[8:9], v3, s[22:23]
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v4, v4, v6
	v_and_b32_e32 v5, v5, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v10, v4, 24
	v_mul_lo_u32 v5, v5, 24
	v_mul_lo_u32 v4, v4, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v5, v10, v5
	s_waitcnt vmcnt(0)
	v_add_co_u32 v4, vcc_lo, v8, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, v9, v5, vcc_lo
	global_load_b64 v[4:5], v[4:5], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[8:9], v3, v[4:7], s[22:23] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[8:9], v[6:7]
	s_cbranch_execz .LBB2_87
; %bb.84:                               ; %.preheader3.i.i.i140.preheader
	s_mov_b32 s3, 0
.LBB2_85:                               ; %.preheader3.i.i.i140
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[4:5], v3, s[22:23] offset:40
	global_load_b64 v[10:11], v3, s[22:23]
	v_dual_mov_b32 v6, v8 :: v_dual_mov_b32 v7, v9
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v4, v4, v6
	v_and_b32_e32 v5, v5, v7
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[8:9], null, v4, 24, v[10:11]
	v_mov_b32_e32 v4, v9
	s_delay_alu instid0(VALU_DEP_1)
	v_mad_u64_u32 v[9:10], null, v5, 24, v[4:5]
	global_load_b64 v[4:5], v[8:9], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[8:9], v3, v[4:7], s[22:23] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[6:7]
	s_or_b32 s3, vcc_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s3
	s_cbranch_execnz .LBB2_85
; %bb.86:                               ; %Flow623
	s_or_b32 exec_lo, exec_lo, s3
.LBB2_87:                               ; %Flow625
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s2
.LBB2_88:                               ; %.loopexit4.i.i.i135
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	v_mov_b32_e32 v3, 0
	v_readfirstlane_b32 s2, v8
	v_readfirstlane_b32 s3, v9
	s_mov_b32 s8, exec_lo
	s_clause 0x1
	global_load_b64 v[10:11], v3, s[22:23] offset:40
	global_load_b128 v[4:7], v3, s[22:23]
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s4, v10
	v_readfirstlane_b32 s5, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[4:5], s[2:3], s[4:5]
	s_mul_i32 s1, s5, 24
	s_mul_hi_u32 s6, s4, 24
	s_mul_i32 s7, s4, 24
	s_and_saveexec_b32 s9, s0
	s_cbranch_execz .LBB2_90
; %bb.89:
	v_dual_mov_b32 v8, s8 :: v_dual_mov_b32 v9, v3
	s_add_i32 s8, s6, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v12, vcc_lo, v4, s7
	v_add_co_ci_u32_e32 v13, vcc_lo, s8, v5, vcc_lo
	v_dual_mov_b32 v10, 2 :: v_dual_mov_b32 v11, 1
	global_store_b128 v[12:13], v[8:11], off offset:8
.LBB2_90:
	s_or_b32 exec_lo, exec_lo, s9
	v_cvt_f32_u32_e32 v8, s25
	s_sub_i32 s8, 0, s25
	s_lshl_b64 s[4:5], s[4:5], 12
	v_and_or_b32 v0, 0xffffff1f, v0, 32
	s_waitcnt vmcnt(0)
	v_add_co_u32 v6, vcc_lo, v6, s4
	v_rcp_iflag_f32_e32 v8, v8
	v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v8, 0x4f7ffffe, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v8, v8
	v_mul_lo_u32 v9, s8, v8
	s_mov_b32 s8, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	s_mov_b32 s9, s8
	s_mov_b32 s10, s8
	s_mov_b32 s11, s8
	v_mul_hi_u32 v9, v8, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v8, v8, v9
	v_mul_hi_u32 v10, v41, v8
	v_lshlrev_b64 v[8:9], 6, v[2:3]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v11, v10, s25
	v_add_nc_u32_e32 v2, 1, v10
	v_sub_nc_u32_e32 v11, v41, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_subrev_nc_u32_e32 v12, s25, v11
	v_cmp_le_u32_e32 vcc_lo, s25, v11
	v_cndmask_b32_e32 v2, v10, v2, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_cndmask_b32_e32 v12, v11, v12, vcc_lo
	v_add_co_u32 v10, vcc_lo, v6, v8
	v_add_co_ci_u32_e32 v11, vcc_lo, v7, v9, vcc_lo
	v_add_nc_u32_e32 v13, 1, v2
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_cmp_le_u32_e32 vcc_lo, s25, v12
	v_dual_mov_b32 v6, s8 :: v_dual_mov_b32 v9, s11
	v_dual_mov_b32 v7, s9 :: v_dual_mov_b32 v8, s10
	v_cndmask_b32_e32 v2, v2, v13, vcc_lo
	s_clause 0x3
	global_store_b128 v[10:11], v[0:3], off
	global_store_b128 v[10:11], v[6:9], off offset:16
	global_store_b128 v[10:11], v[6:9], off offset:32
	global_store_b128 v[10:11], v[6:9], off offset:48
	s_and_saveexec_b32 s4, s0
	s_cbranch_execz .LBB2_98
; %bb.91:
	v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v12, s2
	v_mov_b32_e32 v13, s3
	s_clause 0x1
	global_load_b64 v[14:15], v3, s[22:23] offset:32 glc
	global_load_b64 v[0:1], v3, s[22:23] offset:40
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s8, v0
	v_readfirstlane_b32 s9, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[8:9], s[8:9], s[2:3]
	s_mul_i32 s5, s9, 24
	s_mul_hi_u32 s9, s8, 24
	s_mul_i32 s8, s8, 24
	s_add_i32 s9, s9, s5
	v_add_co_u32 v0, vcc_lo, v4, s8
	v_add_co_ci_u32_e32 v1, vcc_lo, s9, v5, vcc_lo
	s_mov_b32 s5, exec_lo
	global_store_b64 v[0:1], v[14:15], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[8:9], v3, v[12:15], s[22:23] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[8:9], v[14:15]
	s_cbranch_execz .LBB2_94
; %bb.92:                               ; %.preheader1.i.i.i138.preheader
	s_mov_b32 s8, 0
.LBB2_93:                               ; %.preheader1.i.i.i138
                                        ; =>This Inner Loop Header: Depth=1
	v_dual_mov_b32 v6, s2 :: v_dual_mov_b32 v7, s3
	s_sleep 1
	global_store_b64 v[0:1], v[8:9], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[6:7], v3, v[6:9], s[22:23] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[8:9]
	v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6
	s_or_b32 s8, vcc_lo, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s8
	s_cbranch_execnz .LBB2_93
.LBB2_94:                               ; %Flow621
	s_or_b32 exec_lo, exec_lo, s5
	v_mov_b32_e32 v7, 0
	s_mov_b32 s8, exec_lo
	s_mov_b32 s5, exec_lo
	v_mbcnt_lo_u32_b32 v3, s8, 0
	global_load_b64 v[0:1], v7, s[22:23] offset:16
	v_cmpx_eq_u32_e32 0, v3
	s_cbranch_execz .LBB2_96
; %bb.95:
	s_bcnt1_i32_b32 s8, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v6, s8
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[0:1], v[6:7], off offset:8
.LBB2_96:
	s_or_b32 exec_lo, exec_lo, s5
	s_waitcnt vmcnt(0)
	global_load_b64 v[6:7], v[0:1], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[6:7]
	s_cbranch_vccnz .LBB2_98
; %bb.97:
	global_load_b32 v0, v[0:1], off offset:24
	v_mov_b32_e32 v1, 0
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s5, v0
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[6:7], v[0:1], off
	s_and_b32 m0, s5, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB2_98:                               ; %Flow622
	s_or_b32 exec_lo, exec_lo, s4
	s_add_i32 s6, s6, s1
	v_add_co_u32 v0, vcc_lo, v4, s7
	v_add_co_ci_u32_e32 v1, vcc_lo, s6, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, 20
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
.LBB2_99:                               ; =>This Inner Loop Header: Depth=1
	v_mov_b32_e32 v3, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB2_101
; %bb.100:                              ;   in Loop: Header=BB2_99 Depth=1
	global_load_b32 v3, v[0:1], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v3, 1, v3
.LBB2_101:                              ;   in Loop: Header=BB2_99 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v3
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB2_103
; %bb.102:                              ;   in Loop: Header=BB2_99 Depth=1
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB2_104
.LBB2_103:                              ;   in Loop: Header=BB2_99 Depth=1
	s_mov_b32 s1, -1
.LBB2_104:                              ; %Flow616
                                        ;   in Loop: Header=BB2_99 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB2_99
; %bb.105:
	global_load_b64 v[0:1], v[10:11], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB2_109
; %bb.106:
	v_mov_b32_e32 v9, 0
	s_clause 0x2
	global_load_b64 v[5:6], v9, s[22:23] offset:40
	global_load_b64 v[10:11], v9, s[22:23] offset:24 glc
	global_load_b64 v[7:8], v9, s[22:23]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v12, vcc_lo, v5, 1
	v_add_co_ci_u32_e32 v13, vcc_lo, 0, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, v12, s2
	v_add_co_ci_u32_e32 v4, vcc_lo, s3, v13, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[3:4]
	v_dual_cndmask_b32 v4, v4, v13 :: v_dual_cndmask_b32 v3, v3, v12
	v_and_b32_e32 v6, v4, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v5, v3, v5
	v_mul_lo_u32 v6, v6, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v12, v5, 24
	v_mul_lo_u32 v5, v5, 24
	v_add_nc_u32_e32 v6, v12, v6
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v7, vcc_lo, v7, v5
	v_mov_b32_e32 v5, v10
	v_add_co_ci_u32_e32 v8, vcc_lo, v8, v6, vcc_lo
	v_mov_b32_e32 v6, v11
	global_store_b64 v[7:8], v[10:11], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[5:6], v9, v[3:6], s[22:23] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[5:6], v[10:11]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB2_109
; %bb.107:                              ; %.preheader.i.i.i137.preheader
	s_mov_b32 s0, 0
.LBB2_108:                              ; %.preheader.i.i.i137
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	global_store_b64 v[7:8], v[5:6], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[10:11], v9, v[3:6], s[22:23] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[10:11], v[5:6]
	v_dual_mov_b32 v5, v10 :: v_dual_mov_b32 v6, v11
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB2_108
.LBB2_109:                              ; %__ockl_printf_append_args.exit141
	s_or_b32 exec_lo, exec_lo, s1
	v_mov_b32_e32 v8, v54
	v_mov_b32_e32 v10, 0
	v_mov_b32_e32 v11, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s0, v8
	v_cmp_eq_u32_e64 s0, s0, v8
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB2_115
; %bb.110:
	v_mov_b32_e32 v3, 0
	s_mov_b32 s2, exec_lo
	global_load_b64 v[6:7], v3, s[22:23] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[4:5], v3, s[22:23] offset:40
	global_load_b64 v[9:10], v3, s[22:23]
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v4, v4, v6
	v_and_b32_e32 v5, v5, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v11, v4, 24
	v_mul_lo_u32 v5, v5, 24
	v_mul_lo_u32 v4, v4, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v5, v11, v5
	s_waitcnt vmcnt(0)
	v_add_co_u32 v4, vcc_lo, v9, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, v10, v5, vcc_lo
	global_load_b64 v[4:5], v[4:5], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[10:11], v3, v[4:7], s[22:23] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[10:11], v[6:7]
	s_cbranch_execz .LBB2_114
; %bb.111:                              ; %.preheader3.i.i.i147.preheader
	s_mov_b32 s3, 0
.LBB2_112:                              ; %.preheader3.i.i.i147
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[4:5], v3, s[22:23] offset:40
	global_load_b64 v[12:13], v3, s[22:23]
	v_dual_mov_b32 v6, v10 :: v_dual_mov_b32 v7, v11
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v4, v4, v6
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[9:10], null, v4, 24, v[12:13]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v4, v10 :: v_dual_and_b32 v5, v5, v7
	v_mad_u64_u32 v[10:11], null, v5, 24, v[4:5]
	global_load_b64 v[4:5], v[9:10], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[10:11], v3, v[4:7], s[22:23] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[10:11], v[6:7]
	s_or_b32 s3, vcc_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s3
	s_cbranch_execnz .LBB2_112
; %bb.113:                              ; %Flow609
	s_or_b32 exec_lo, exec_lo, s3
.LBB2_114:                              ; %Flow611
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s2
.LBB2_115:                              ; %.loopexit4.i.i.i142
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	v_mov_b32_e32 v9, 0
	v_readfirstlane_b32 s2, v10
	v_readfirstlane_b32 s3, v11
	s_mov_b32 s8, exec_lo
	s_clause 0x1
	global_load_b64 v[12:13], v9, s[22:23] offset:40
	global_load_b128 v[4:7], v9, s[22:23]
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s4, v12
	v_readfirstlane_b32 s5, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[4:5], s[2:3], s[4:5]
	s_mul_i32 s1, s5, 24
	s_mul_hi_u32 s6, s4, 24
	s_mul_i32 s7, s4, 24
	s_and_saveexec_b32 s9, s0
	s_cbranch_execz .LBB2_117
; %bb.116:
	v_dual_mov_b32 v10, s8 :: v_dual_mov_b32 v11, v9
	s_add_i32 s8, s6, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v14, vcc_lo, v4, s7
	v_add_co_ci_u32_e32 v15, vcc_lo, s8, v5, vcc_lo
	v_dual_mov_b32 v12, 2 :: v_dual_mov_b32 v13, 1
	global_store_b128 v[14:15], v[10:13], off offset:8
.LBB2_117:
	s_or_b32 exec_lo, exec_lo, s9
	s_lshl_b64 s[4:5], s[4:5], 12
	v_mul_lo_u32 v2, v2, s25
	v_lshlrev_b64 v[10:11], 6, v[8:9]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v3, vcc_lo, v6, s4
	v_add_co_ci_u32_e32 v6, vcc_lo, s5, v7, vcc_lo
	s_mov_b32 s8, 0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v10, vcc_lo, v3, v10
	s_mov_b32 s9, s8
	s_mov_b32 s10, s8
	s_mov_b32 s11, s8
	v_sub_nc_u32_e32 v2, v41, v2
	v_and_or_b32 v0, 0xffffff1d, v0, 34
	v_add_co_ci_u32_e32 v11, vcc_lo, v6, v11, vcc_lo
	v_dual_mov_b32 v3, v9 :: v_dual_mov_b32 v6, s8
	v_dual_mov_b32 v7, s9 :: v_dual_mov_b32 v8, s10
	v_mov_b32_e32 v9, s11
	s_clause 0x3
	global_store_b128 v[10:11], v[0:3], off
	global_store_b128 v[10:11], v[6:9], off offset:16
	global_store_b128 v[10:11], v[6:9], off offset:32
	global_store_b128 v[10:11], v[6:9], off offset:48
	s_and_saveexec_b32 s4, s0
	s_cbranch_execz .LBB2_125
; %bb.118:
	v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v9, s2
	v_mov_b32_e32 v10, s3
	s_clause 0x1
	global_load_b64 v[11:12], v8, s[22:23] offset:32 glc
	global_load_b64 v[0:1], v8, s[22:23] offset:40
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s8, v0
	v_readfirstlane_b32 s9, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[8:9], s[8:9], s[2:3]
	s_mul_i32 s5, s9, 24
	s_mul_hi_u32 s9, s8, 24
	s_mul_i32 s8, s8, 24
	s_add_i32 s9, s9, s5
	v_add_co_u32 v6, vcc_lo, v4, s8
	v_add_co_ci_u32_e32 v7, vcc_lo, s9, v5, vcc_lo
	s_mov_b32 s5, exec_lo
	global_store_b64 v[6:7], v[11:12], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v8, v[9:12], s[22:23] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[2:3], v[11:12]
	s_cbranch_execz .LBB2_121
; %bb.119:                              ; %.preheader1.i.i.i145.preheader
	s_mov_b32 s8, 0
.LBB2_120:                              ; %.preheader1.i.i.i145
                                        ; =>This Inner Loop Header: Depth=1
	v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
	s_sleep 1
	global_store_b64 v[6:7], v[2:3], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[0:1], v8, v[0:3], s[22:23] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
	v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
	s_or_b32 s8, vcc_lo, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s8
	s_cbranch_execnz .LBB2_120
.LBB2_121:                              ; %Flow607
	s_or_b32 exec_lo, exec_lo, s5
	v_mov_b32_e32 v3, 0
	s_mov_b32 s8, exec_lo
	s_mov_b32 s5, exec_lo
	v_mbcnt_lo_u32_b32 v2, s8, 0
	global_load_b64 v[0:1], v3, s[22:23] offset:16
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB2_123
; %bb.122:
	s_bcnt1_i32_b32 s8, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v2, s8
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[0:1], v[2:3], off offset:8
.LBB2_123:
	s_or_b32 exec_lo, exec_lo, s5
	s_waitcnt vmcnt(0)
	global_load_b64 v[2:3], v[0:1], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
	s_cbranch_vccnz .LBB2_125
; %bb.124:
	global_load_b32 v0, v[0:1], off offset:24
	v_mov_b32_e32 v1, 0
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s5, v0
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[2:3], v[0:1], off
	s_and_b32 m0, s5, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB2_125:                              ; %Flow608
	s_or_b32 exec_lo, exec_lo, s4
	s_add_i32 s6, s6, s1
	v_add_co_u32 v0, vcc_lo, v4, s7
	v_add_co_ci_u32_e32 v1, vcc_lo, s6, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, 20
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
.LBB2_126:                              ; =>This Inner Loop Header: Depth=1
	v_mov_b32_e32 v2, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB2_128
; %bb.127:                              ;   in Loop: Header=BB2_126 Depth=1
	global_load_b32 v2, v[0:1], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v2, 1, v2
.LBB2_128:                              ;   in Loop: Header=BB2_126 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v2
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB2_130
; %bb.129:                              ;   in Loop: Header=BB2_126 Depth=1
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB2_131
.LBB2_130:                              ;   in Loop: Header=BB2_126 Depth=1
	s_mov_b32 s1, -1
.LBB2_131:                              ; %Flow602
                                        ;   in Loop: Header=BB2_126 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB2_126
; %bb.132:
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB2_136
; %bb.133:
	v_mov_b32_e32 v6, 0
	s_clause 0x2
	global_load_b64 v[2:3], v6, s[22:23] offset:40
	global_load_b64 v[7:8], v6, s[22:23] offset:24 glc
	global_load_b64 v[4:5], v6, s[22:23]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v9, vcc_lo, v2, 1
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v9, s2
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
	v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
	v_and_b32_e32 v3, v1, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v2, v0, v2
	v_mul_lo_u32 v3, v3, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v9, v2, 24
	v_mul_lo_u32 v2, v2, 24
	v_add_nc_u32_e32 v3, v9, v3
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v4, vcc_lo, v4, v2
	v_mov_b32_e32 v2, v7
	v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
	v_mov_b32_e32 v3, v8
	global_store_b64 v[4:5], v[7:8], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[22:23] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB2_136
; %bb.134:                              ; %.preheader.i.i.i144.preheader
	s_mov_b32 s0, 0
.LBB2_135:                              ; %.preheader.i.i.i144
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	global_store_b64 v[4:5], v[2:3], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[22:23] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
	v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB2_135
.LBB2_136:                              ; %__ockl_printf_append_args.exit148
	s_or_b32 exec_lo, exec_lo, s1
	s_mul_i32 s33, s25, s24
	s_cmp_eq_u32 s26, 0
	s_mul_i32 s33, s33, s26
	s_mov_b32 s28, 0
	s_cbranch_scc1 .LBB2_225
; %bb.137:                              ; %.lr.ph
	v_dual_mov_b32 v49, 0 :: v_dual_mov_b32 v52, 2
	v_mul_lo_u32 v37, v41, s26
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, .str@rel32@lo+4
	s_addc_u32 s1, s1, .str@rel32@hi+12
	v_cmp_gt_u32_e64 s21, 15, v41
	v_dual_mov_b32 v53, 1 :: v_dual_mov_b32 v36, v49
	v_mov_b32_e32 v47, 33
	s_cmp_lg_u64 s[0:1], 0
	s_mov_b32 s37, 0
	s_cselect_b32 s36, 25, 0
.LBB2_138:                              ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB2_142 Depth 2
                                        ;     Child Loop BB2_150 Depth 2
                                        ;     Child Loop BB2_156 Depth 2
                                        ;     Child Loop BB2_165 Depth 2
                                        ;     Child Loop BB2_169 Depth 2
                                        ;     Child Loop BB2_177 Depth 2
                                        ;     Child Loop BB2_183 Depth 2
                                        ;     Child Loop BB2_192 Depth 2
                                        ;     Child Loop BB2_196 Depth 2
                                        ;     Child Loop BB2_204 Depth 2
                                        ;     Child Loop BB2_210 Depth 2
                                        ;     Child Loop BB2_219 Depth 2
	v_add_nc_u32_e32 v45, s37, v37
	s_and_saveexec_b32 s38, s21
	s_cbranch_execz .LBB2_220
; %bb.139:                              ;   in Loop: Header=BB2_138 Depth=1
	v_mov_b32_e32 v48, v54
	v_mov_b32_e32 v4, 0
	v_mov_b32_e32 v5, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s0, v48
	v_cmp_eq_u32_e64 s0, s0, v48
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB2_145
; %bb.140:                              ;   in Loop: Header=BB2_138 Depth=1
	global_load_b64 v[2:3], v49, s[22:23] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[0:1], v49, s[22:23] offset:40
	global_load_b64 v[4:5], v49, s[22:23]
	s_mov_b32 s2, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v1, v1, v3
	v_and_b32_e32 v0, v0, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v1, v1, 24
	v_mul_hi_u32 v6, v0, 24
	v_mul_lo_u32 v0, v0, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v1, v6, v1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v0, vcc_lo, v4, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, v5, v1, vcc_lo
	global_load_b64 v[0:1], v[0:1], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[4:5], v49, v[0:3], s[22:23] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[4:5], v[2:3]
	s_cbranch_execz .LBB2_144
; %bb.141:                              ; %.preheader3.i.i.i154.preheader
                                        ;   in Loop: Header=BB2_138 Depth=1
	s_mov_b32 s3, 0
.LBB2_142:                              ; %.preheader3.i.i.i154
                                        ;   Parent Loop BB2_138 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[0:1], v49, s[22:23] offset:40
	global_load_b64 v[6:7], v49, s[22:23]
	v_dual_mov_b32 v2, v4 :: v_dual_mov_b32 v3, v5
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v0, v0, v2
	v_and_b32_e32 v1, v1, v3
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[4:5], null, v0, 24, v[6:7]
	v_mov_b32_e32 v0, v5
	s_delay_alu instid0(VALU_DEP_1)
	v_mad_u64_u32 v[5:6], null, v1, 24, v[0:1]
	global_load_b64 v[0:1], v[4:5], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[4:5], v49, v[0:3], s[22:23] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[2:3]
	s_or_b32 s3, vcc_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s3
	s_cbranch_execnz .LBB2_142
; %bb.143:                              ; %Flow592
                                        ;   in Loop: Header=BB2_138 Depth=1
	s_or_b32 exec_lo, exec_lo, s3
.LBB2_144:                              ; %Flow594
                                        ;   in Loop: Header=BB2_138 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s2
.LBB2_145:                              ; %.loopexit4.i.i.i149
                                        ;   in Loop: Header=BB2_138 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_clause 0x1
	global_load_b64 v[6:7], v49, s[22:23] offset:40
	global_load_b128 v[0:3], v49, s[22:23]
	v_readfirstlane_b32 s2, v4
	v_readfirstlane_b32 s3, v5
	s_mov_b32 s8, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s4, v6
	v_readfirstlane_b32 s5, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[4:5], s[2:3], s[4:5]
	s_mul_i32 s1, s5, 24
	s_mul_hi_u32 s6, s4, 24
	s_mul_i32 s7, s4, 24
	s_and_saveexec_b32 s9, s0
	s_cbranch_execz .LBB2_147
; %bb.146:                              ;   in Loop: Header=BB2_138 Depth=1
	v_dual_mov_b32 v50, s8 :: v_dual_mov_b32 v51, v49
	s_add_i32 s8, s6, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v4, vcc_lo, v0, s7
	v_add_co_ci_u32_e32 v5, vcc_lo, s8, v1, vcc_lo
	global_store_b128 v[4:5], v[50:53], off offset:8
.LBB2_147:                              ;   in Loop: Header=BB2_138 Depth=1
	s_or_b32 exec_lo, exec_lo, s9
	s_lshl_b64 s[4:5], s[4:5], 12
	v_lshlrev_b64 v[4:5], 6, v[48:49]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v2, vcc_lo, v2, s4
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
	s_mov_b32 s29, s28
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v6, vcc_lo, v2, v4
	s_mov_b32 s30, s28
	s_mov_b32 s31, s28
	v_add_co_ci_u32_e32 v7, vcc_lo, v3, v5, vcc_lo
	v_mov_b32_e32 v48, v49
	v_mov_b32_e32 v50, v49
	v_dual_mov_b32 v2, s28 :: v_dual_mov_b32 v5, s31
	v_dual_mov_b32 v3, s29 :: v_dual_mov_b32 v4, s30
	s_clause 0x3
	global_store_b128 v[6:7], v[47:50], off
	global_store_b128 v[6:7], v[2:5], off offset:16
	global_store_b128 v[6:7], v[2:5], off offset:32
	global_store_b128 v[6:7], v[2:5], off offset:48
	s_and_saveexec_b32 s4, s0
	s_cbranch_execz .LBB2_155
; %bb.148:                              ;   in Loop: Header=BB2_138 Depth=1
	s_clause 0x1
	global_load_b64 v[12:13], v49, s[22:23] offset:32 glc
	global_load_b64 v[2:3], v49, s[22:23] offset:40
	v_dual_mov_b32 v10, s2 :: v_dual_mov_b32 v11, s3
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s8, v2
	v_readfirstlane_b32 s9, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[8:9], s[8:9], s[2:3]
	s_mul_i32 s5, s9, 24
	s_mul_hi_u32 s9, s8, 24
	s_mul_i32 s8, s8, 24
	s_add_i32 s9, s9, s5
	v_add_co_u32 v8, vcc_lo, v0, s8
	v_add_co_ci_u32_e32 v9, vcc_lo, s9, v1, vcc_lo
	s_mov_b32 s5, exec_lo
	global_store_b64 v[8:9], v[12:13], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[4:5], v49, v[10:13], s[22:23] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[4:5], v[12:13]
	s_cbranch_execz .LBB2_151
; %bb.149:                              ; %.preheader1.i.i.i152.preheader
                                        ;   in Loop: Header=BB2_138 Depth=1
	s_mov_b32 s8, 0
.LBB2_150:                              ; %.preheader1.i.i.i152
                                        ;   Parent Loop BB2_138 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
	s_sleep 1
	global_store_b64 v[8:9], v[4:5], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v49, v[2:5], s[22:23] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
	v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
	s_or_b32 s8, vcc_lo, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s8
	s_cbranch_execnz .LBB2_150
.LBB2_151:                              ; %Flow590
                                        ;   in Loop: Header=BB2_138 Depth=1
	s_or_b32 exec_lo, exec_lo, s5
	global_load_b64 v[2:3], v49, s[22:23] offset:16
	s_mov_b32 s8, exec_lo
	s_mov_b32 s5, exec_lo
	v_mbcnt_lo_u32_b32 v4, s8, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v4
	s_cbranch_execz .LBB2_153
; %bb.152:                              ;   in Loop: Header=BB2_138 Depth=1
	s_bcnt1_i32_b32 s8, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v48, s8
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[2:3], v[48:49], off offset:8
.LBB2_153:                              ;   in Loop: Header=BB2_138 Depth=1
	s_or_b32 exec_lo, exec_lo, s5
	s_waitcnt vmcnt(0)
	global_load_b64 v[4:5], v[2:3], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
	s_cbranch_vccnz .LBB2_155
; %bb.154:                              ;   in Loop: Header=BB2_138 Depth=1
	global_load_b32 v48, v[2:3], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s5, v48
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[4:5], v[48:49], off
	s_and_b32 m0, s5, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB2_155:                              ; %Flow591
                                        ;   in Loop: Header=BB2_138 Depth=1
	s_or_b32 exec_lo, exec_lo, s4
	s_add_i32 s6, s6, s1
	v_add_co_u32 v0, vcc_lo, v0, s7
	v_add_co_ci_u32_e32 v1, vcc_lo, s6, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, 20
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
.LBB2_156:                              ;   Parent Loop BB2_138 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_mov_b32_e32 v2, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB2_158
; %bb.157:                              ;   in Loop: Header=BB2_156 Depth=2
	global_load_b32 v2, v[0:1], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v2, 1, v2
.LBB2_158:                              ;   in Loop: Header=BB2_156 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v2
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB2_160
; %bb.159:                              ;   in Loop: Header=BB2_156 Depth=2
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB2_161
.LBB2_160:                              ;   in Loop: Header=BB2_156 Depth=2
	s_mov_b32 s1, -1
.LBB2_161:                              ; %Flow585
                                        ;   in Loop: Header=BB2_156 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB2_156
; %bb.162:                              ;   in Loop: Header=BB2_138 Depth=1
	global_load_b64 v[0:1], v[6:7], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB2_166
; %bb.163:                              ;   in Loop: Header=BB2_138 Depth=1
	s_clause 0x2
	global_load_b64 v[4:5], v49, s[22:23] offset:40
	global_load_b64 v[8:9], v49, s[22:23] offset:24 glc
	global_load_b64 v[6:7], v49, s[22:23]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v10, vcc_lo, v4, 1
	v_add_co_ci_u32_e32 v11, vcc_lo, 0, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, v10, s2
	v_add_co_ci_u32_e32 v3, vcc_lo, s3, v11, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
	v_dual_cndmask_b32 v3, v3, v11 :: v_dual_cndmask_b32 v2, v2, v10
	v_and_b32_e32 v5, v3, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v4, v2, v4
	v_mul_hi_u32 v10, v4, 24
	v_mul_lo_u32 v4, v4, 24
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_u32 v6, vcc_lo, v6, v4
	v_mov_b32_e32 v4, v8
	v_mul_lo_u32 v5, v5, 24
	v_add_nc_u32_e32 v5, v10, v5
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
	v_mov_b32_e32 v5, v9
	global_store_b64 v[6:7], v[8:9], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[4:5], v49, v[2:5], s[22:23] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[4:5], v[8:9]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB2_166
; %bb.164:                              ; %.preheader.i.i.i151.preheader
                                        ;   in Loop: Header=BB2_138 Depth=1
	s_mov_b32 s0, 0
.LBB2_165:                              ; %.preheader.i.i.i151
                                        ;   Parent Loop BB2_138 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	global_store_b64 v[6:7], v[4:5], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[8:9], v49, v[2:5], s[22:23] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[4:5]
	v_dual_mov_b32 v4, v8 :: v_dual_mov_b32 v5, v9
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB2_165
.LBB2_166:                              ; %__ockl_printf_begin.exit155
                                        ;   in Loop: Header=BB2_138 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_add_u32 s8, s18, 40
	s_addc_u32 s9, s19, 0
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, .str@rel32@lo+4
	s_addc_u32 s1, s1, .str@rel32@hi+12
	s_delay_alu instid0(SALU_CYCLE_1)
	v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
	v_dual_mov_b32 v4, s36 :: v_dual_mov_b32 v5, 0
	v_mov_b32_e32 v6, 0
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, __ockl_printf_append_string_n@rel32@lo+4
	s_addc_u32 s3, s3, __ockl_printf_append_string_n@rel32@hi+12
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	s_swappc_b64 s[30:31], s[2:3]
	v_mov_b32_e32 v48, v54
	;;#ASMSTART
	;;#ASMEND
	v_readfirstlane_b32 s0, v48
	v_dual_mov_b32 v40, v1 :: v_dual_mov_b32 v5, 0
	v_mov_b32_e32 v6, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_eq_u32_e64 s0, s0, v48
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB2_172
; %bb.167:                              ;   in Loop: Header=BB2_138 Depth=1
	global_load_b64 v[3:4], v49, s[22:23] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[1:2], v49, s[22:23] offset:40
	global_load_b64 v[5:6], v49, s[22:23]
	s_mov_b32 s2, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v2, v2, v4
	v_and_b32_e32 v1, v1, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v2, v2, 24
	v_mul_hi_u32 v7, v1, 24
	v_mul_lo_u32 v1, v1, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v2, v7, v2
	s_waitcnt vmcnt(0)
	v_add_co_u32 v1, vcc_lo, v5, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, v6, v2, vcc_lo
	global_load_b64 v[1:2], v[1:2], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[5:6], v49, v[1:4], s[22:23] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[5:6], v[3:4]
	s_cbranch_execz .LBB2_171
; %bb.168:                              ; %.preheader3.i.i.i161.preheader
                                        ;   in Loop: Header=BB2_138 Depth=1
	s_mov_b32 s3, 0
.LBB2_169:                              ; %.preheader3.i.i.i161
                                        ;   Parent Loop BB2_138 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[1:2], v49, s[22:23] offset:40
	global_load_b64 v[7:8], v49, s[22:23]
	v_dual_mov_b32 v3, v5 :: v_dual_mov_b32 v4, v6
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v1, v1, v3
	v_and_b32_e32 v2, v2, v4
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[5:6], null, v1, 24, v[7:8]
	v_mov_b32_e32 v1, v6
	s_delay_alu instid0(VALU_DEP_1)
	v_mad_u64_u32 v[6:7], null, v2, 24, v[1:2]
	global_load_b64 v[1:2], v[5:6], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[5:6], v49, v[1:4], s[22:23] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[5:6], v[3:4]
	s_or_b32 s3, vcc_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s3
	s_cbranch_execnz .LBB2_169
; %bb.170:                              ; %Flow578
                                        ;   in Loop: Header=BB2_138 Depth=1
	s_or_b32 exec_lo, exec_lo, s3
.LBB2_171:                              ; %Flow580
                                        ;   in Loop: Header=BB2_138 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s2
.LBB2_172:                              ; %.loopexit4.i.i.i156
                                        ;   in Loop: Header=BB2_138 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_clause 0x1
	global_load_b64 v[7:8], v49, s[22:23] offset:40
	global_load_b128 v[1:4], v49, s[22:23]
	v_readfirstlane_b32 s2, v5
	v_readfirstlane_b32 s3, v6
	s_mov_b32 s8, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s4, v7
	v_readfirstlane_b32 s5, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[4:5], s[2:3], s[4:5]
	s_mul_i32 s1, s5, 24
	s_mul_hi_u32 s6, s4, 24
	s_mul_i32 s7, s4, 24
	s_and_saveexec_b32 s9, s0
	s_cbranch_execz .LBB2_174
; %bb.173:                              ;   in Loop: Header=BB2_138 Depth=1
	v_dual_mov_b32 v50, s8 :: v_dual_mov_b32 v51, v49
	s_add_i32 s8, s6, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v5, vcc_lo, v1, s7
	v_add_co_ci_u32_e32 v6, vcc_lo, s8, v2, vcc_lo
	global_store_b128 v[5:6], v[50:53], off offset:8
.LBB2_174:                              ;   in Loop: Header=BB2_138 Depth=1
	s_or_b32 exec_lo, exec_lo, s9
	s_lshl_b64 s[4:5], s[4:5], 12
	s_mov_b32 s29, s28
	s_waitcnt vmcnt(0)
	v_add_co_u32 v5, vcc_lo, v3, s4
	v_add_co_ci_u32_e32 v6, vcc_lo, s5, v4, vcc_lo
	v_lshlrev_b64 v[3:4], 6, v[48:49]
	s_mov_b32 s30, s28
	s_mov_b32 s31, s28
	v_and_or_b32 v39, 0xffffff1f, v0, 32
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v7, vcc_lo, v5, v3
	v_add_co_ci_u32_e32 v8, vcc_lo, v6, v4, vcc_lo
	v_dual_mov_b32 v3, s28 :: v_dual_mov_b32 v4, s29
	v_dual_mov_b32 v5, s30 :: v_dual_mov_b32 v6, s31
	s_clause 0x3
	global_store_b128 v[7:8], v[39:42], off
	global_store_b128 v[7:8], v[3:6], off offset:16
	global_store_b128 v[7:8], v[3:6], off offset:32
	global_store_b128 v[7:8], v[3:6], off offset:48
	s_and_saveexec_b32 s4, s0
	s_cbranch_execz .LBB2_182
; %bb.175:                              ;   in Loop: Header=BB2_138 Depth=1
	s_clause 0x1
	global_load_b64 v[13:14], v49, s[22:23] offset:32 glc
	global_load_b64 v[3:4], v49, s[22:23] offset:40
	v_dual_mov_b32 v11, s2 :: v_dual_mov_b32 v12, s3
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s8, v3
	v_readfirstlane_b32 s9, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[8:9], s[8:9], s[2:3]
	s_mul_i32 s5, s9, 24
	s_mul_hi_u32 s9, s8, 24
	s_mul_i32 s8, s8, 24
	s_add_i32 s9, s9, s5
	v_add_co_u32 v9, vcc_lo, v1, s8
	v_add_co_ci_u32_e32 v10, vcc_lo, s9, v2, vcc_lo
	s_mov_b32 s5, exec_lo
	global_store_b64 v[9:10], v[13:14], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[5:6], v49, v[11:14], s[22:23] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[5:6], v[13:14]
	s_cbranch_execz .LBB2_178
; %bb.176:                              ; %.preheader1.i.i.i159.preheader
                                        ;   in Loop: Header=BB2_138 Depth=1
	s_mov_b32 s8, 0
.LBB2_177:                              ; %.preheader1.i.i.i159
                                        ;   Parent Loop BB2_138 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_dual_mov_b32 v3, s2 :: v_dual_mov_b32 v4, s3
	s_sleep 1
	global_store_b64 v[9:10], v[5:6], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[3:4], v49, v[3:6], s[22:23] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[3:4], v[5:6]
	v_dual_mov_b32 v6, v4 :: v_dual_mov_b32 v5, v3
	s_or_b32 s8, vcc_lo, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s8
	s_cbranch_execnz .LBB2_177
.LBB2_178:                              ; %Flow576
                                        ;   in Loop: Header=BB2_138 Depth=1
	s_or_b32 exec_lo, exec_lo, s5
	global_load_b64 v[3:4], v49, s[22:23] offset:16
	s_mov_b32 s8, exec_lo
	s_mov_b32 s5, exec_lo
	v_mbcnt_lo_u32_b32 v0, s8, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB2_180
; %bb.179:                              ;   in Loop: Header=BB2_138 Depth=1
	s_bcnt1_i32_b32 s8, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v48, s8
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[3:4], v[48:49], off offset:8
.LBB2_180:                              ;   in Loop: Header=BB2_138 Depth=1
	s_or_b32 exec_lo, exec_lo, s5
	s_waitcnt vmcnt(0)
	global_load_b64 v[5:6], v[3:4], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[5:6]
	s_cbranch_vccnz .LBB2_182
; %bb.181:                              ;   in Loop: Header=BB2_138 Depth=1
	global_load_b32 v48, v[3:4], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s5, v48
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[5:6], v[48:49], off
	s_and_b32 m0, s5, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB2_182:                              ; %Flow577
                                        ;   in Loop: Header=BB2_138 Depth=1
	s_or_b32 exec_lo, exec_lo, s4
	s_add_i32 s6, s6, s1
	v_add_co_u32 v0, vcc_lo, v1, s7
	v_add_co_ci_u32_e32 v1, vcc_lo, s6, v2, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, 20
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
.LBB2_183:                              ;   Parent Loop BB2_138 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_mov_b32_e32 v2, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB2_185
; %bb.184:                              ;   in Loop: Header=BB2_183 Depth=2
	global_load_b32 v2, v[0:1], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v2, 1, v2
.LBB2_185:                              ;   in Loop: Header=BB2_183 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v2
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB2_187
; %bb.186:                              ;   in Loop: Header=BB2_183 Depth=2
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB2_188
.LBB2_187:                              ;   in Loop: Header=BB2_183 Depth=2
	s_mov_b32 s1, -1
.LBB2_188:                              ; %Flow571
                                        ;   in Loop: Header=BB2_183 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB2_183
; %bb.189:                              ;   in Loop: Header=BB2_138 Depth=1
	global_load_b64 v[43:44], v[7:8], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB2_193
; %bb.190:                              ;   in Loop: Header=BB2_138 Depth=1
	s_clause 0x2
	global_load_b64 v[2:3], v49, s[22:23] offset:40
	global_load_b64 v[6:7], v49, s[22:23] offset:24 glc
	global_load_b64 v[4:5], v49, s[22:23]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v8, vcc_lo, v2, 1
	v_add_co_ci_u32_e32 v9, vcc_lo, 0, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v8, s2
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
	v_dual_cndmask_b32 v1, v1, v9 :: v_dual_cndmask_b32 v0, v0, v8
	v_and_b32_e32 v3, v1, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v2, v0, v2
	v_mul_hi_u32 v8, v2, 24
	v_mul_lo_u32 v2, v2, 24
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_u32 v4, vcc_lo, v4, v2
	v_mov_b32_e32 v2, v6
	v_mul_lo_u32 v3, v3, 24
	v_add_nc_u32_e32 v3, v8, v3
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
	v_mov_b32_e32 v3, v7
	global_store_b64 v[4:5], v[6:7], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v49, v[0:3], s[22:23] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[6:7]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB2_193
; %bb.191:                              ; %.preheader.i.i.i158.preheader
                                        ;   in Loop: Header=BB2_138 Depth=1
	s_mov_b32 s0, 0
.LBB2_192:                              ; %.preheader.i.i.i158
                                        ;   Parent Loop BB2_138 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	global_store_b64 v[4:5], v[2:3], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[6:7], v49, v[0:3], s[22:23] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[2:3]
	v_dual_mov_b32 v2, v6 :: v_dual_mov_b32 v3, v7
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB2_192
.LBB2_193:                              ; %__ockl_printf_append_args.exit162
                                        ;   in Loop: Header=BB2_138 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	v_mov_b32_e32 v48, v54
	v_mov_b32_e32 v4, 0
	v_mov_b32_e32 v5, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s0, v48
	v_cmp_eq_u32_e64 s0, s0, v48
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB2_199
; %bb.194:                              ;   in Loop: Header=BB2_138 Depth=1
	global_load_b64 v[2:3], v49, s[22:23] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[0:1], v49, s[22:23] offset:40
	global_load_b64 v[4:5], v49, s[22:23]
	s_mov_b32 s2, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v1, v1, v3
	v_and_b32_e32 v0, v0, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v1, v1, 24
	v_mul_hi_u32 v6, v0, 24
	v_mul_lo_u32 v0, v0, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v1, v6, v1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v0, vcc_lo, v4, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, v5, v1, vcc_lo
	global_load_b64 v[0:1], v[0:1], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[4:5], v49, v[0:3], s[22:23] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[4:5], v[2:3]
	s_cbranch_execz .LBB2_198
; %bb.195:                              ; %.preheader3.i.i.i168.preheader
                                        ;   in Loop: Header=BB2_138 Depth=1
	s_mov_b32 s3, 0
.LBB2_196:                              ; %.preheader3.i.i.i168
                                        ;   Parent Loop BB2_138 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[0:1], v49, s[22:23] offset:40
	global_load_b64 v[6:7], v49, s[22:23]
	v_dual_mov_b32 v2, v4 :: v_dual_mov_b32 v3, v5
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v0, v0, v2
	v_and_b32_e32 v1, v1, v3
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[4:5], null, v0, 24, v[6:7]
	v_mov_b32_e32 v0, v5
	s_delay_alu instid0(VALU_DEP_1)
	v_mad_u64_u32 v[5:6], null, v1, 24, v[0:1]
	global_load_b64 v[0:1], v[4:5], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[4:5], v49, v[0:3], s[22:23] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[2:3]
	s_or_b32 s3, vcc_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s3
	s_cbranch_execnz .LBB2_196
; %bb.197:                              ; %Flow564
                                        ;   in Loop: Header=BB2_138 Depth=1
	s_or_b32 exec_lo, exec_lo, s3
.LBB2_198:                              ; %Flow566
                                        ;   in Loop: Header=BB2_138 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s2
.LBB2_199:                              ; %.loopexit4.i.i.i163
                                        ;   in Loop: Header=BB2_138 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_clause 0x1
	global_load_b64 v[6:7], v49, s[22:23] offset:40
	global_load_b128 v[0:3], v49, s[22:23]
	v_readfirstlane_b32 s2, v4
	v_readfirstlane_b32 s3, v5
	s_mov_b32 s8, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s4, v6
	v_readfirstlane_b32 s5, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[4:5], s[2:3], s[4:5]
	s_mul_i32 s1, s5, 24
	s_mul_hi_u32 s6, s4, 24
	s_mul_i32 s7, s4, 24
	s_and_saveexec_b32 s9, s0
	s_cbranch_execz .LBB2_201
; %bb.200:                              ;   in Loop: Header=BB2_138 Depth=1
	v_dual_mov_b32 v50, s8 :: v_dual_mov_b32 v51, v49
	s_add_i32 s8, s6, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v4, vcc_lo, v0, s7
	v_add_co_ci_u32_e32 v5, vcc_lo, s8, v1, vcc_lo
	global_store_b128 v[4:5], v[50:53], off offset:8
.LBB2_201:                              ;   in Loop: Header=BB2_138 Depth=1
	s_or_b32 exec_lo, exec_lo, s9
	s_lshl_b64 s[4:5], s[4:5], 12
	v_lshlrev_b64 v[4:5], 6, v[48:49]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v2, vcc_lo, v2, s4
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
	s_mov_b32 s29, s28
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v6, vcc_lo, v2, v4
	s_mov_b32 s30, s28
	s_mov_b32 s31, s28
	v_and_or_b32 v43, 0xffffff1d, v43, 34
	v_add_co_ci_u32_e32 v7, vcc_lo, v3, v5, vcc_lo
	v_mov_b32_e32 v46, v49
	v_dual_mov_b32 v2, s28 :: v_dual_mov_b32 v5, s31
	v_dual_mov_b32 v3, s29 :: v_dual_mov_b32 v4, s30
	s_clause 0x3
	global_store_b128 v[6:7], v[43:46], off
	global_store_b128 v[6:7], v[2:5], off offset:16
	global_store_b128 v[6:7], v[2:5], off offset:32
	global_store_b128 v[6:7], v[2:5], off offset:48
	s_and_saveexec_b32 s4, s0
	s_cbranch_execz .LBB2_209
; %bb.202:                              ;   in Loop: Header=BB2_138 Depth=1
	s_clause 0x1
	global_load_b64 v[10:11], v49, s[22:23] offset:32 glc
	global_load_b64 v[2:3], v49, s[22:23] offset:40
	v_dual_mov_b32 v8, s2 :: v_dual_mov_b32 v9, s3
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s8, v2
	v_readfirstlane_b32 s9, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[8:9], s[8:9], s[2:3]
	s_mul_i32 s5, s9, 24
	s_mul_hi_u32 s9, s8, 24
	s_mul_i32 s8, s8, 24
	s_add_i32 s9, s9, s5
	v_add_co_u32 v6, vcc_lo, v0, s8
	v_add_co_ci_u32_e32 v7, vcc_lo, s9, v1, vcc_lo
	s_mov_b32 s5, exec_lo
	global_store_b64 v[6:7], v[10:11], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[4:5], v49, v[8:11], s[22:23] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[4:5], v[10:11]
	s_cbranch_execz .LBB2_205
; %bb.203:                              ; %.preheader1.i.i.i166.preheader
                                        ;   in Loop: Header=BB2_138 Depth=1
	s_mov_b32 s8, 0
.LBB2_204:                              ; %.preheader1.i.i.i166
                                        ;   Parent Loop BB2_138 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
	s_sleep 1
	global_store_b64 v[6:7], v[4:5], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v49, v[2:5], s[22:23] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
	v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
	s_or_b32 s8, vcc_lo, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s8
	s_cbranch_execnz .LBB2_204
.LBB2_205:                              ; %Flow562
                                        ;   in Loop: Header=BB2_138 Depth=1
	s_or_b32 exec_lo, exec_lo, s5
	global_load_b64 v[2:3], v49, s[22:23] offset:16
	s_mov_b32 s8, exec_lo
	s_mov_b32 s5, exec_lo
	v_mbcnt_lo_u32_b32 v4, s8, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v4
	s_cbranch_execz .LBB2_207
; %bb.206:                              ;   in Loop: Header=BB2_138 Depth=1
	s_bcnt1_i32_b32 s8, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v48, s8
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[2:3], v[48:49], off offset:8
.LBB2_207:                              ;   in Loop: Header=BB2_138 Depth=1
	s_or_b32 exec_lo, exec_lo, s5
	s_waitcnt vmcnt(0)
	global_load_b64 v[4:5], v[2:3], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
	s_cbranch_vccnz .LBB2_209
; %bb.208:                              ;   in Loop: Header=BB2_138 Depth=1
	global_load_b32 v48, v[2:3], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s5, v48
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[4:5], v[48:49], off
	s_and_b32 m0, s5, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB2_209:                              ; %Flow563
                                        ;   in Loop: Header=BB2_138 Depth=1
	s_or_b32 exec_lo, exec_lo, s4
	s_add_i32 s6, s6, s1
	v_add_co_u32 v0, vcc_lo, v0, s7
	v_add_co_ci_u32_e32 v1, vcc_lo, s6, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, 20
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
.LBB2_210:                              ;   Parent Loop BB2_138 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_mov_b32_e32 v2, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB2_212
; %bb.211:                              ;   in Loop: Header=BB2_210 Depth=2
	global_load_b32 v2, v[0:1], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v2, 1, v2
.LBB2_212:                              ;   in Loop: Header=BB2_210 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v2
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB2_214
; %bb.213:                              ;   in Loop: Header=BB2_210 Depth=2
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB2_215
.LBB2_214:                              ;   in Loop: Header=BB2_210 Depth=2
	s_mov_b32 s1, -1
.LBB2_215:                              ; %Flow557
                                        ;   in Loop: Header=BB2_210 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB2_210
; %bb.216:                              ;   in Loop: Header=BB2_138 Depth=1
	s_and_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB2_220
; %bb.217:                              ;   in Loop: Header=BB2_138 Depth=1
	s_clause 0x2
	global_load_b64 v[2:3], v49, s[22:23] offset:40
	global_load_b64 v[6:7], v49, s[22:23] offset:24 glc
	global_load_b64 v[4:5], v49, s[22:23]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v8, vcc_lo, v2, 1
	v_add_co_ci_u32_e32 v9, vcc_lo, 0, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v8, s2
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
	v_dual_cndmask_b32 v1, v1, v9 :: v_dual_cndmask_b32 v0, v0, v8
	v_and_b32_e32 v3, v1, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v2, v0, v2
	v_mul_hi_u32 v8, v2, 24
	v_mul_lo_u32 v2, v2, 24
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_u32 v4, vcc_lo, v4, v2
	v_mov_b32_e32 v2, v6
	v_mul_lo_u32 v3, v3, 24
	v_add_nc_u32_e32 v3, v8, v3
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
	v_mov_b32_e32 v3, v7
	global_store_b64 v[4:5], v[6:7], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v49, v[0:3], s[22:23] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[6:7]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB2_220
; %bb.218:                              ; %.preheader.i.i.i165.preheader
                                        ;   in Loop: Header=BB2_138 Depth=1
	s_mov_b32 s0, 0
.LBB2_219:                              ; %.preheader.i.i.i165
                                        ;   Parent Loop BB2_138 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	global_store_b64 v[4:5], v[2:3], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[6:7], v49, v[0:3], s[22:23] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[2:3]
	v_dual_mov_b32 v2, v6 :: v_dual_mov_b32 v3, v7
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB2_219
.LBB2_220:                              ; %Flow595
                                        ;   in Loop: Header=BB2_138 Depth=1
	s_or_b32 exec_lo, exec_lo, s38
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e64 s33, v45
	s_cbranch_execz .LBB2_222
; %bb.221:                              ;   in Loop: Header=BB2_138 Depth=1
	v_mov_b32_e32 v46, v49
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[45:46]
	v_add_co_u32 v0, vcc_lo, s34, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s35, v1, vcc_lo
	global_load_b32 v0, v[0:1], off
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v36, v36, v0
.LBB2_222:                              ;   in Loop: Header=BB2_138 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	s_add_i32 s37, s37, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u32 s37, s26
	s_cbranch_scc1 .LBB2_138
	s_branch .LBB2_226
.LBB2_223:
	s_mov_b32 s27, -1
.LBB2_224:                              ; %Flow712
                                        ; implicit-def: $vgpr41_vgpr42
                                        ; implicit-def: $vgpr0
	s_branch .LBB2_231
.LBB2_225:
	v_mov_b32_e32 v36, 0
                                        ; implicit-def: $vgpr45
.LBB2_226:                              ; %._crit_edge
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e64 s33, v45
	s_cbranch_execz .LBB2_228
; %bb.227:
	v_lshlrev_b32_e32 v0, 2, v38
	ds_store_b32 v0, v36 offset:1024
.LBB2_228:
	s_or_b32 exec_lo, exec_lo, s0
	v_cmp_ge_u32_e32 vcc_lo, s33, v45
	s_mov_b32 s33, 0
	s_waitcnt lgkmcnt(0)
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
                                        ; implicit-def: $vgpr0
	s_and_saveexec_b32 s0, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s0, exec_lo, s0
; %bb.229:
	v_lshl_add_u32 v0, v38, 2, 0x400
	s_mov_b32 s33, exec_lo
; %bb.230:                              ; %Flow714
	s_or_b32 exec_lo, exec_lo, s0
.LBB2_231:                              ; %Flow712
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s27
	s_cbranch_vccz .LBB2_324
; %bb.232:
	s_load_b32 s2, s[18:19], 0x34
	s_add_u32 s0, s18, 40
	s_addc_u32 s1, s19, 0
	s_mul_i32 s24, s25, s24
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mul_i32 s24, s24, s26
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_cmp_eq_u32 s25, 0
	v_mad_u64_u32 v[41:42], null, s20, s2, v[38:39]
	v_mov_b32_e32 v42, 0
	s_mov_b32 s20, 0
	s_cbranch_scc1 .LBB2_318
; %bb.233:                              ; %.lr.ph191
	v_cvt_f32_u32_e32 v0, s26
	s_sub_i32 s2, 0, s26
	s_load_b64 s[28:29], s[0:1], 0x50
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, .str@rel32@lo+4
	s_addc_u32 s1, s1, .str@rel32@hi+12
	v_mbcnt_lo_u32_b32 v39, -1, 0
	v_rcp_iflag_f32_e32 v0, v0
	v_mov_b32_e32 v46, 0
	v_mov_b32_e32 v48, 0
	v_mov_b32_e32 v52, 1
	s_cmp_lg_u64 s[0:1], 0
	s_mov_b32 s36, 0
	s_cselect_b32 s27, 25, 0
	v_mov_b32_e32 v47, 33
	v_mov_b32_e32 v51, 2
	s_waitcnt_depctr 0xfff
	v_dual_mov_b32 v37, 0 :: v_dual_mul_f32 v0, 0x4f7ffffe, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v0, v0
	v_mul_lo_u32 v1, s2, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v1, v0, v1
	v_add_nc_u32_e32 v0, v0, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v0, v41, v0
	v_mul_lo_u32 v1, v0, s26
	v_add_nc_u32_e32 v2, 1, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v1, v41, v1
	v_subrev_nc_u32_e32 v3, s26, v1
	v_cmp_le_u32_e32 vcc_lo, s26, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_cndmask_b32 v0, v0, v2 :: v_dual_cndmask_b32 v1, v1, v3
	v_add_nc_u32_e32 v2, 1, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_le_u32_e32 vcc_lo, s26, v1
	v_cndmask_b32_e32 v0, v0, v2, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v1, v0, s26
	v_mul_lo_u32 v40, v0, s25
	v_sub_nc_u32_e32 v36, v41, v1
.LBB2_234:                              ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB2_237 Depth 2
                                        ;     Child Loop BB2_245 Depth 2
                                        ;     Child Loop BB2_251 Depth 2
                                        ;     Child Loop BB2_260 Depth 2
                                        ;     Child Loop BB2_264 Depth 2
                                        ;     Child Loop BB2_272 Depth 2
                                        ;     Child Loop BB2_278 Depth 2
                                        ;     Child Loop BB2_287 Depth 2
                                        ;     Child Loop BB2_291 Depth 2
                                        ;     Child Loop BB2_299 Depth 2
                                        ;     Child Loop BB2_305 Depth 2
                                        ;     Child Loop BB2_314 Depth 2
	v_dual_mov_b32 v45, v39 :: v_dual_mov_b32 v4, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s0, v45
	v_mov_b32_e32 v5, 0
	v_cmp_eq_u32_e64 s0, s0, v45
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB2_240
; %bb.235:                              ;   in Loop: Header=BB2_234 Depth=1
	s_waitcnt lgkmcnt(0)
	global_load_b64 v[2:3], v46, s[28:29] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[0:1], v46, s[28:29] offset:40
	global_load_b64 v[4:5], v46, s[28:29]
	s_mov_b32 s2, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v1, v1, v3
	v_and_b32_e32 v0, v0, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v1, v1, 24
	v_mul_hi_u32 v6, v0, 24
	v_mul_lo_u32 v0, v0, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v1, v6, v1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v0, vcc_lo, v4, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, v5, v1, vcc_lo
	global_load_b64 v[0:1], v[0:1], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[4:5], v46, v[0:3], s[28:29] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[4:5], v[2:3]
	s_cbranch_execz .LBB2_239
; %bb.236:                              ; %.preheader3.i.i.i.preheader
                                        ;   in Loop: Header=BB2_234 Depth=1
	s_mov_b32 s3, 0
.LBB2_237:                              ; %.preheader3.i.i.i
                                        ;   Parent Loop BB2_234 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[0:1], v46, s[28:29] offset:40
	global_load_b64 v[6:7], v46, s[28:29]
	v_dual_mov_b32 v2, v4 :: v_dual_mov_b32 v3, v5
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v0, v0, v2
	v_and_b32_e32 v1, v1, v3
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[4:5], null, v0, 24, v[6:7]
	v_mov_b32_e32 v0, v5
	s_delay_alu instid0(VALU_DEP_1)
	v_mad_u64_u32 v[5:6], null, v1, 24, v[0:1]
	global_load_b64 v[0:1], v[4:5], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[4:5], v46, v[0:3], s[28:29] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[2:3]
	s_or_b32 s3, vcc_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s3
	s_cbranch_execnz .LBB2_237
; %bb.238:                              ; %Flow707
                                        ;   in Loop: Header=BB2_234 Depth=1
	s_or_b32 exec_lo, exec_lo, s3
.LBB2_239:                              ; %Flow709
                                        ;   in Loop: Header=BB2_234 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s2
.LBB2_240:                              ; %.loopexit4.i.i.i
                                        ;   in Loop: Header=BB2_234 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_waitcnt lgkmcnt(0)
	s_clause 0x1
	global_load_b64 v[6:7], v46, s[28:29] offset:40
	global_load_b128 v[0:3], v46, s[28:29]
	v_readfirstlane_b32 s2, v4
	v_readfirstlane_b32 s3, v5
	s_mov_b32 s8, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s4, v6
	v_readfirstlane_b32 s5, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[4:5], s[2:3], s[4:5]
	s_mul_i32 s1, s5, 24
	s_mul_hi_u32 s6, s4, 24
	s_mul_i32 s7, s4, 24
	s_and_saveexec_b32 s9, s0
	s_cbranch_execz .LBB2_242
; %bb.241:                              ;   in Loop: Header=BB2_234 Depth=1
	v_dual_mov_b32 v49, s8 :: v_dual_mov_b32 v50, v46
	s_add_i32 s8, s6, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v4, vcc_lo, v0, s7
	v_add_co_ci_u32_e32 v5, vcc_lo, s8, v1, vcc_lo
	global_store_b128 v[4:5], v[49:52], off offset:8
.LBB2_242:                              ;   in Loop: Header=BB2_234 Depth=1
	s_or_b32 exec_lo, exec_lo, s9
	s_lshl_b64 s[4:5], s[4:5], 12
	v_lshlrev_b64 v[4:5], 6, v[45:46]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v2, vcc_lo, v2, s4
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
	s_mov_b32 s21, s20
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v6, vcc_lo, v2, v4
	s_mov_b32 s22, s20
	s_mov_b32 s23, s20
	v_add_co_ci_u32_e32 v7, vcc_lo, v3, v5, vcc_lo
	v_dual_mov_b32 v49, v48 :: v_dual_mov_b32 v2, s20
	v_dual_mov_b32 v50, v48 :: v_dual_mov_b32 v3, s21
	v_dual_mov_b32 v4, s22 :: v_dual_mov_b32 v5, s23
	s_clause 0x3
	global_store_b128 v[6:7], v[47:50], off
	global_store_b128 v[6:7], v[2:5], off offset:16
	global_store_b128 v[6:7], v[2:5], off offset:32
	global_store_b128 v[6:7], v[2:5], off offset:48
	s_and_saveexec_b32 s4, s0
	s_cbranch_execz .LBB2_250
; %bb.243:                              ;   in Loop: Header=BB2_234 Depth=1
	s_clause 0x1
	global_load_b64 v[12:13], v46, s[28:29] offset:32 glc
	global_load_b64 v[2:3], v46, s[28:29] offset:40
	v_dual_mov_b32 v10, s2 :: v_dual_mov_b32 v11, s3
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s8, v2
	v_readfirstlane_b32 s9, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[8:9], s[8:9], s[2:3]
	s_mul_i32 s5, s9, 24
	s_mul_hi_u32 s9, s8, 24
	s_mul_i32 s8, s8, 24
	s_add_i32 s9, s9, s5
	v_add_co_u32 v8, vcc_lo, v0, s8
	v_add_co_ci_u32_e32 v9, vcc_lo, s9, v1, vcc_lo
	s_mov_b32 s5, exec_lo
	global_store_b64 v[8:9], v[12:13], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[4:5], v46, v[10:13], s[28:29] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[4:5], v[12:13]
	s_cbranch_execz .LBB2_246
; %bb.244:                              ; %.preheader1.i.i.i.preheader
                                        ;   in Loop: Header=BB2_234 Depth=1
	s_mov_b32 s8, 0
.LBB2_245:                              ; %.preheader1.i.i.i
                                        ;   Parent Loop BB2_234 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
	s_sleep 1
	global_store_b64 v[8:9], v[4:5], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v46, v[2:5], s[28:29] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
	v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
	s_or_b32 s8, vcc_lo, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s8
	s_cbranch_execnz .LBB2_245
.LBB2_246:                              ; %Flow705
                                        ;   in Loop: Header=BB2_234 Depth=1
	s_or_b32 exec_lo, exec_lo, s5
	global_load_b64 v[2:3], v46, s[28:29] offset:16
	s_mov_b32 s8, exec_lo
	s_mov_b32 s5, exec_lo
	v_mbcnt_lo_u32_b32 v4, s8, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v4
	s_cbranch_execz .LBB2_248
; %bb.247:                              ;   in Loop: Header=BB2_234 Depth=1
	s_bcnt1_i32_b32 s8, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v45, s8
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[2:3], v[45:46], off offset:8
.LBB2_248:                              ;   in Loop: Header=BB2_234 Depth=1
	s_or_b32 exec_lo, exec_lo, s5
	s_waitcnt vmcnt(0)
	global_load_b64 v[4:5], v[2:3], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
	s_cbranch_vccnz .LBB2_250
; %bb.249:                              ;   in Loop: Header=BB2_234 Depth=1
	global_load_b32 v45, v[2:3], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s5, v45
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[4:5], v[45:46], off
	s_and_b32 m0, s5, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB2_250:                              ; %Flow706
                                        ;   in Loop: Header=BB2_234 Depth=1
	s_or_b32 exec_lo, exec_lo, s4
	s_add_i32 s6, s6, s1
	v_add_co_u32 v0, vcc_lo, v0, s7
	v_add_co_ci_u32_e32 v1, vcc_lo, s6, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, 20
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
.LBB2_251:                              ;   Parent Loop BB2_234 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_mov_b32_e32 v2, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB2_253
; %bb.252:                              ;   in Loop: Header=BB2_251 Depth=2
	global_load_b32 v2, v[0:1], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v2, 1, v2
.LBB2_253:                              ;   in Loop: Header=BB2_251 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v2
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB2_255
; %bb.254:                              ;   in Loop: Header=BB2_251 Depth=2
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB2_256
.LBB2_255:                              ;   in Loop: Header=BB2_251 Depth=2
	s_mov_b32 s1, -1
.LBB2_256:                              ; %Flow700
                                        ;   in Loop: Header=BB2_251 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB2_251
; %bb.257:                              ;   in Loop: Header=BB2_234 Depth=1
	global_load_b64 v[0:1], v[6:7], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB2_261
; %bb.258:                              ;   in Loop: Header=BB2_234 Depth=1
	s_clause 0x2
	global_load_b64 v[4:5], v46, s[28:29] offset:40
	global_load_b64 v[8:9], v46, s[28:29] offset:24 glc
	global_load_b64 v[6:7], v46, s[28:29]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v10, vcc_lo, v4, 1
	v_add_co_ci_u32_e32 v11, vcc_lo, 0, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, v10, s2
	v_add_co_ci_u32_e32 v3, vcc_lo, s3, v11, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
	v_dual_cndmask_b32 v3, v3, v11 :: v_dual_cndmask_b32 v2, v2, v10
	v_and_b32_e32 v5, v3, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v4, v2, v4
	v_mul_hi_u32 v10, v4, 24
	v_mul_lo_u32 v4, v4, 24
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_u32 v6, vcc_lo, v6, v4
	v_mov_b32_e32 v4, v8
	v_mul_lo_u32 v5, v5, 24
	v_add_nc_u32_e32 v5, v10, v5
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
	v_mov_b32_e32 v5, v9
	global_store_b64 v[6:7], v[8:9], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[4:5], v46, v[2:5], s[28:29] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[4:5], v[8:9]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB2_261
; %bb.259:                              ; %.preheader.i.i.i.preheader
                                        ;   in Loop: Header=BB2_234 Depth=1
	s_mov_b32 s0, 0
.LBB2_260:                              ; %.preheader.i.i.i
                                        ;   Parent Loop BB2_234 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	global_store_b64 v[6:7], v[4:5], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[8:9], v46, v[2:5], s[28:29] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[4:5]
	v_dual_mov_b32 v4, v8 :: v_dual_mov_b32 v5, v9
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB2_260
.LBB2_261:                              ; %__ockl_printf_begin.exit
                                        ;   in Loop: Header=BB2_234 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_add_u32 s8, s18, 40
	s_addc_u32 s9, s19, 0
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, .str@rel32@lo+4
	s_addc_u32 s1, s1, .str@rel32@hi+12
	s_delay_alu instid0(SALU_CYCLE_1)
	v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
	v_dual_mov_b32 v4, s27 :: v_dual_mov_b32 v5, 0
	v_mov_b32_e32 v6, 0
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, __ockl_printf_append_string_n@rel32@lo+4
	s_addc_u32 s3, s3, __ockl_printf_append_string_n@rel32@hi+12
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	s_swappc_b64 s[30:31], s[2:3]
	v_dual_mov_b32 v44, v1 :: v_dual_mov_b32 v45, v39
	;;#ASMSTART
	;;#ASMEND
	v_readfirstlane_b32 s0, v45
	v_mov_b32_e32 v5, 0
	v_mov_b32_e32 v6, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_eq_u32_e64 s0, s0, v45
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB2_267
; %bb.262:                              ;   in Loop: Header=BB2_234 Depth=1
	global_load_b64 v[3:4], v46, s[28:29] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[1:2], v46, s[28:29] offset:40
	global_load_b64 v[5:6], v46, s[28:29]
	s_mov_b32 s2, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v2, v2, v4
	v_and_b32_e32 v1, v1, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v2, v2, 24
	v_mul_hi_u32 v7, v1, 24
	v_mul_lo_u32 v1, v1, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v2, v7, v2
	s_waitcnt vmcnt(0)
	v_add_co_u32 v1, vcc_lo, v5, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, v6, v2, vcc_lo
	global_load_b64 v[1:2], v[1:2], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[5:6], v46, v[1:4], s[28:29] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[5:6], v[3:4]
	s_cbranch_execz .LBB2_266
; %bb.263:                              ; %.preheader3.i.i.i106.preheader
                                        ;   in Loop: Header=BB2_234 Depth=1
	s_mov_b32 s3, 0
.LBB2_264:                              ; %.preheader3.i.i.i106
                                        ;   Parent Loop BB2_234 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[1:2], v46, s[28:29] offset:40
	global_load_b64 v[7:8], v46, s[28:29]
	v_dual_mov_b32 v3, v5 :: v_dual_mov_b32 v4, v6
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v1, v1, v3
	v_and_b32_e32 v2, v2, v4
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[5:6], null, v1, 24, v[7:8]
	v_mov_b32_e32 v1, v6
	s_delay_alu instid0(VALU_DEP_1)
	v_mad_u64_u32 v[6:7], null, v2, 24, v[1:2]
	global_load_b64 v[1:2], v[5:6], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[5:6], v46, v[1:4], s[28:29] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[5:6], v[3:4]
	s_or_b32 s3, vcc_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s3
	s_cbranch_execnz .LBB2_264
; %bb.265:                              ; %Flow693
                                        ;   in Loop: Header=BB2_234 Depth=1
	s_or_b32 exec_lo, exec_lo, s3
.LBB2_266:                              ; %Flow695
                                        ;   in Loop: Header=BB2_234 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s2
.LBB2_267:                              ; %.loopexit4.i.i.i101
                                        ;   in Loop: Header=BB2_234 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_clause 0x1
	global_load_b64 v[7:8], v46, s[28:29] offset:40
	global_load_b128 v[1:4], v46, s[28:29]
	v_readfirstlane_b32 s2, v5
	v_readfirstlane_b32 s3, v6
	s_mov_b32 s8, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s4, v7
	v_readfirstlane_b32 s5, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[4:5], s[2:3], s[4:5]
	s_mul_i32 s1, s5, 24
	s_mul_hi_u32 s6, s4, 24
	s_mul_i32 s7, s4, 24
	s_and_saveexec_b32 s9, s0
	s_cbranch_execz .LBB2_269
; %bb.268:                              ;   in Loop: Header=BB2_234 Depth=1
	v_dual_mov_b32 v49, s8 :: v_dual_mov_b32 v50, v46
	s_add_i32 s8, s6, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v5, vcc_lo, v1, s7
	v_add_co_ci_u32_e32 v6, vcc_lo, s8, v2, vcc_lo
	global_store_b128 v[5:6], v[49:52], off offset:8
.LBB2_269:                              ;   in Loop: Header=BB2_234 Depth=1
	s_or_b32 exec_lo, exec_lo, s9
	s_lshl_b64 s[4:5], s[4:5], 12
	v_lshlrev_b64 v[5:6], 6, v[45:46]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v3, vcc_lo, v3, s4
	v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
	s_mov_b32 s21, s20
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v7, vcc_lo, v3, v5
	s_mov_b32 s22, s20
	s_mov_b32 s23, s20
	v_and_or_b32 v43, 0xffffff1f, v0, 32
	v_add_co_ci_u32_e32 v8, vcc_lo, v4, v6, vcc_lo
	v_mov_b32_e32 v45, v41
	v_dual_mov_b32 v3, s20 :: v_dual_mov_b32 v6, s23
	v_dual_mov_b32 v4, s21 :: v_dual_mov_b32 v5, s22
	s_clause 0x3
	global_store_b128 v[7:8], v[43:46], off
	global_store_b128 v[7:8], v[3:6], off offset:16
	global_store_b128 v[7:8], v[3:6], off offset:32
	global_store_b128 v[7:8], v[3:6], off offset:48
	s_and_saveexec_b32 s4, s0
	s_cbranch_execz .LBB2_277
; %bb.270:                              ;   in Loop: Header=BB2_234 Depth=1
	s_clause 0x1
	global_load_b64 v[13:14], v46, s[28:29] offset:32 glc
	global_load_b64 v[3:4], v46, s[28:29] offset:40
	v_dual_mov_b32 v11, s2 :: v_dual_mov_b32 v12, s3
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s8, v3
	v_readfirstlane_b32 s9, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[8:9], s[8:9], s[2:3]
	s_mul_i32 s5, s9, 24
	s_mul_hi_u32 s9, s8, 24
	s_mul_i32 s8, s8, 24
	s_add_i32 s9, s9, s5
	v_add_co_u32 v9, vcc_lo, v1, s8
	v_add_co_ci_u32_e32 v10, vcc_lo, s9, v2, vcc_lo
	s_mov_b32 s5, exec_lo
	global_store_b64 v[9:10], v[13:14], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[5:6], v46, v[11:14], s[28:29] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[5:6], v[13:14]
	s_cbranch_execz .LBB2_273
; %bb.271:                              ; %.preheader1.i.i.i104.preheader
                                        ;   in Loop: Header=BB2_234 Depth=1
	s_mov_b32 s8, 0
.LBB2_272:                              ; %.preheader1.i.i.i104
                                        ;   Parent Loop BB2_234 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_dual_mov_b32 v3, s2 :: v_dual_mov_b32 v4, s3
	s_sleep 1
	global_store_b64 v[9:10], v[5:6], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[3:4], v46, v[3:6], s[28:29] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[3:4], v[5:6]
	v_dual_mov_b32 v6, v4 :: v_dual_mov_b32 v5, v3
	s_or_b32 s8, vcc_lo, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s8
	s_cbranch_execnz .LBB2_272
.LBB2_273:                              ; %Flow691
                                        ;   in Loop: Header=BB2_234 Depth=1
	s_or_b32 exec_lo, exec_lo, s5
	global_load_b64 v[3:4], v46, s[28:29] offset:16
	s_mov_b32 s8, exec_lo
	s_mov_b32 s5, exec_lo
	v_mbcnt_lo_u32_b32 v0, s8, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB2_275
; %bb.274:                              ;   in Loop: Header=BB2_234 Depth=1
	s_bcnt1_i32_b32 s8, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v45, s8
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[3:4], v[45:46], off offset:8
.LBB2_275:                              ;   in Loop: Header=BB2_234 Depth=1
	s_or_b32 exec_lo, exec_lo, s5
	s_waitcnt vmcnt(0)
	global_load_b64 v[5:6], v[3:4], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[5:6]
	s_cbranch_vccnz .LBB2_277
; %bb.276:                              ;   in Loop: Header=BB2_234 Depth=1
	global_load_b32 v45, v[3:4], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s5, v45
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[5:6], v[45:46], off
	s_and_b32 m0, s5, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB2_277:                              ; %Flow692
                                        ;   in Loop: Header=BB2_234 Depth=1
	s_or_b32 exec_lo, exec_lo, s4
	s_add_i32 s6, s6, s1
	v_add_co_u32 v0, vcc_lo, v1, s7
	v_add_co_ci_u32_e32 v1, vcc_lo, s6, v2, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, 20
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
.LBB2_278:                              ;   Parent Loop BB2_234 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_mov_b32_e32 v2, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB2_280
; %bb.279:                              ;   in Loop: Header=BB2_278 Depth=2
	global_load_b32 v2, v[0:1], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v2, 1, v2
.LBB2_280:                              ;   in Loop: Header=BB2_278 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v2
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB2_282
; %bb.281:                              ;   in Loop: Header=BB2_278 Depth=2
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB2_283
.LBB2_282:                              ;   in Loop: Header=BB2_278 Depth=2
	s_mov_b32 s1, -1
.LBB2_283:                              ; %Flow686
                                        ;   in Loop: Header=BB2_278 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB2_278
; %bb.284:                              ;   in Loop: Header=BB2_234 Depth=1
	global_load_b64 v[43:44], v[7:8], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB2_288
; %bb.285:                              ;   in Loop: Header=BB2_234 Depth=1
	s_clause 0x2
	global_load_b64 v[2:3], v46, s[28:29] offset:40
	global_load_b64 v[6:7], v46, s[28:29] offset:24 glc
	global_load_b64 v[4:5], v46, s[28:29]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v8, vcc_lo, v2, 1
	v_add_co_ci_u32_e32 v9, vcc_lo, 0, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v8, s2
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
	v_dual_cndmask_b32 v1, v1, v9 :: v_dual_cndmask_b32 v0, v0, v8
	v_and_b32_e32 v3, v1, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v2, v0, v2
	v_mul_hi_u32 v8, v2, 24
	v_mul_lo_u32 v2, v2, 24
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_u32 v4, vcc_lo, v4, v2
	v_mov_b32_e32 v2, v6
	v_mul_lo_u32 v3, v3, 24
	v_add_nc_u32_e32 v3, v8, v3
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
	v_mov_b32_e32 v3, v7
	global_store_b64 v[4:5], v[6:7], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v46, v[0:3], s[28:29] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[6:7]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB2_288
; %bb.286:                              ; %.preheader.i.i.i103.preheader
                                        ;   in Loop: Header=BB2_234 Depth=1
	s_mov_b32 s0, 0
.LBB2_287:                              ; %.preheader.i.i.i103
                                        ;   Parent Loop BB2_234 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	global_store_b64 v[4:5], v[2:3], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[6:7], v46, v[0:3], s[28:29] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[2:3]
	v_dual_mov_b32 v2, v6 :: v_dual_mov_b32 v3, v7
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB2_287
.LBB2_288:                              ; %__ockl_printf_append_args.exit
                                        ;   in Loop: Header=BB2_234 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	v_dual_mov_b32 v45, v39 :: v_dual_mov_b32 v4, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s0, v45
	v_mov_b32_e32 v5, 0
	v_cmp_eq_u32_e64 s0, s0, v45
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB2_294
; %bb.289:                              ;   in Loop: Header=BB2_234 Depth=1
	global_load_b64 v[2:3], v46, s[28:29] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[0:1], v46, s[28:29] offset:40
	global_load_b64 v[4:5], v46, s[28:29]
	s_mov_b32 s2, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v1, v1, v3
	v_and_b32_e32 v0, v0, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v1, v1, 24
	v_mul_hi_u32 v6, v0, 24
	v_mul_lo_u32 v0, v0, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v1, v6, v1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v0, vcc_lo, v4, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, v5, v1, vcc_lo
	global_load_b64 v[0:1], v[0:1], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[4:5], v46, v[0:3], s[28:29] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[4:5], v[2:3]
	s_cbranch_execz .LBB2_293
; %bb.290:                              ; %.preheader3.i.i.i112.preheader
                                        ;   in Loop: Header=BB2_234 Depth=1
	s_mov_b32 s3, 0
.LBB2_291:                              ; %.preheader3.i.i.i112
                                        ;   Parent Loop BB2_234 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[0:1], v46, s[28:29] offset:40
	global_load_b64 v[6:7], v46, s[28:29]
	v_dual_mov_b32 v2, v4 :: v_dual_mov_b32 v3, v5
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v0, v0, v2
	v_and_b32_e32 v1, v1, v3
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[4:5], null, v0, 24, v[6:7]
	v_mov_b32_e32 v0, v5
	s_delay_alu instid0(VALU_DEP_1)
	v_mad_u64_u32 v[5:6], null, v1, 24, v[0:1]
	global_load_b64 v[0:1], v[4:5], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[4:5], v46, v[0:3], s[28:29] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[2:3]
	s_or_b32 s3, vcc_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s3
	s_cbranch_execnz .LBB2_291
; %bb.292:                              ; %Flow679
                                        ;   in Loop: Header=BB2_234 Depth=1
	s_or_b32 exec_lo, exec_lo, s3
.LBB2_293:                              ; %Flow681
                                        ;   in Loop: Header=BB2_234 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s2
.LBB2_294:                              ; %.loopexit4.i.i.i107
                                        ;   in Loop: Header=BB2_234 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_clause 0x1
	global_load_b64 v[6:7], v46, s[28:29] offset:40
	global_load_b128 v[0:3], v46, s[28:29]
	v_readfirstlane_b32 s2, v4
	v_readfirstlane_b32 s3, v5
	s_mov_b32 s8, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s4, v6
	v_readfirstlane_b32 s5, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[4:5], s[2:3], s[4:5]
	s_mul_i32 s1, s5, 24
	s_mul_hi_u32 s6, s4, 24
	s_mul_i32 s7, s4, 24
	s_and_saveexec_b32 s9, s0
	s_cbranch_execz .LBB2_296
; %bb.295:                              ;   in Loop: Header=BB2_234 Depth=1
	v_dual_mov_b32 v49, s8 :: v_dual_mov_b32 v50, v46
	s_add_i32 s8, s6, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v4, vcc_lo, v0, s7
	v_add_co_ci_u32_e32 v5, vcc_lo, s8, v1, vcc_lo
	global_store_b128 v[4:5], v[49:52], off offset:8
.LBB2_296:                              ;   in Loop: Header=BB2_234 Depth=1
	s_or_b32 exec_lo, exec_lo, s9
	v_add_nc_u32_e32 v8, s36, v40
	s_lshl_b64 s[4:5], s[4:5], 12
	v_lshlrev_b64 v[4:5], 6, v[45:46]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v2, vcc_lo, v2, s4
	v_mad_u64_u32 v[6:7], null, v8, s26, v[36:37]
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_add_co_u32 v8, vcc_lo, v2, v4
	s_mov_b32 s21, s20
	s_mov_b32 s22, s20
	v_mov_b32_e32 v45, v6
	s_mov_b32 s23, s20
	v_and_or_b32 v43, 0xffffff1d, v43, 34
	v_add_co_ci_u32_e32 v9, vcc_lo, v3, v5, vcc_lo
	v_dual_mov_b32 v2, s20 :: v_dual_mov_b32 v3, s21
	v_dual_mov_b32 v7, v46 :: v_dual_mov_b32 v4, s22
	v_mov_b32_e32 v5, s23
	s_clause 0x3
	global_store_b128 v[8:9], v[43:46], off
	global_store_b128 v[8:9], v[2:5], off offset:16
	global_store_b128 v[8:9], v[2:5], off offset:32
	global_store_b128 v[8:9], v[2:5], off offset:48
	s_and_saveexec_b32 s4, s0
	s_cbranch_execz .LBB2_304
; %bb.297:                              ;   in Loop: Header=BB2_234 Depth=1
	s_clause 0x1
	global_load_b64 v[12:13], v46, s[28:29] offset:32 glc
	global_load_b64 v[2:3], v46, s[28:29] offset:40
	v_dual_mov_b32 v10, s2 :: v_dual_mov_b32 v11, s3
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s8, v2
	v_readfirstlane_b32 s9, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[8:9], s[8:9], s[2:3]
	s_mul_i32 s5, s9, 24
	s_mul_hi_u32 s9, s8, 24
	s_mul_i32 s8, s8, 24
	s_add_i32 s9, s9, s5
	v_add_co_u32 v8, vcc_lo, v0, s8
	v_add_co_ci_u32_e32 v9, vcc_lo, s9, v1, vcc_lo
	s_mov_b32 s5, exec_lo
	global_store_b64 v[8:9], v[12:13], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[4:5], v46, v[10:13], s[28:29] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[4:5], v[12:13]
	s_cbranch_execz .LBB2_300
; %bb.298:                              ; %.preheader1.i.i.i110.preheader
                                        ;   in Loop: Header=BB2_234 Depth=1
	s_mov_b32 s8, 0
.LBB2_299:                              ; %.preheader1.i.i.i110
                                        ;   Parent Loop BB2_234 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
	s_sleep 1
	global_store_b64 v[8:9], v[4:5], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v46, v[2:5], s[28:29] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
	v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
	s_or_b32 s8, vcc_lo, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s8
	s_cbranch_execnz .LBB2_299
.LBB2_300:                              ; %Flow677
                                        ;   in Loop: Header=BB2_234 Depth=1
	s_or_b32 exec_lo, exec_lo, s5
	global_load_b64 v[2:3], v46, s[28:29] offset:16
	s_mov_b32 s8, exec_lo
	s_mov_b32 s5, exec_lo
	v_mbcnt_lo_u32_b32 v4, s8, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v4
	s_cbranch_execz .LBB2_302
; %bb.301:                              ;   in Loop: Header=BB2_234 Depth=1
	s_bcnt1_i32_b32 s8, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v45, s8
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[2:3], v[45:46], off offset:8
.LBB2_302:                              ;   in Loop: Header=BB2_234 Depth=1
	s_or_b32 exec_lo, exec_lo, s5
	s_waitcnt vmcnt(0)
	global_load_b64 v[4:5], v[2:3], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
	s_cbranch_vccnz .LBB2_304
; %bb.303:                              ;   in Loop: Header=BB2_234 Depth=1
	global_load_b32 v45, v[2:3], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s5, v45
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[4:5], v[45:46], off
	s_and_b32 m0, s5, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB2_304:                              ; %Flow678
                                        ;   in Loop: Header=BB2_234 Depth=1
	s_or_b32 exec_lo, exec_lo, s4
	s_add_i32 s6, s6, s1
	v_add_co_u32 v0, vcc_lo, v0, s7
	v_add_co_ci_u32_e32 v1, vcc_lo, s6, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, 20
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
.LBB2_305:                              ;   Parent Loop BB2_234 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_mov_b32_e32 v2, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB2_307
; %bb.306:                              ;   in Loop: Header=BB2_305 Depth=2
	global_load_b32 v2, v[0:1], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v2, 1, v2
.LBB2_307:                              ;   in Loop: Header=BB2_305 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v2
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB2_309
; %bb.308:                              ;   in Loop: Header=BB2_305 Depth=2
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB2_310
.LBB2_309:                              ;   in Loop: Header=BB2_305 Depth=2
	s_mov_b32 s1, -1
.LBB2_310:                              ; %Flow672
                                        ;   in Loop: Header=BB2_305 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB2_305
; %bb.311:                              ;   in Loop: Header=BB2_234 Depth=1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB2_315
; %bb.312:                              ;   in Loop: Header=BB2_234 Depth=1
	s_clause 0x2
	global_load_b64 v[2:3], v46, s[28:29] offset:40
	global_load_b64 v[8:9], v46, s[28:29] offset:24 glc
	global_load_b64 v[4:5], v46, s[28:29]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v10, vcc_lo, v2, 1
	v_add_co_ci_u32_e32 v11, vcc_lo, 0, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v10, s2
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v11, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
	v_dual_cndmask_b32 v1, v1, v11 :: v_dual_cndmask_b32 v0, v0, v10
	v_and_b32_e32 v3, v1, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v2, v0, v2
	v_mul_hi_u32 v10, v2, 24
	v_mul_lo_u32 v2, v2, 24
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_u32 v4, vcc_lo, v4, v2
	v_mov_b32_e32 v2, v8
	v_mul_lo_u32 v3, v3, 24
	v_add_nc_u32_e32 v3, v10, v3
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
	v_mov_b32_e32 v3, v9
	global_store_b64 v[4:5], v[8:9], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v46, v[0:3], s[28:29] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[8:9]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB2_315
; %bb.313:                              ; %.preheader.i.i.i109.preheader
                                        ;   in Loop: Header=BB2_234 Depth=1
	s_mov_b32 s0, 0
.LBB2_314:                              ; %.preheader.i.i.i109
                                        ;   Parent Loop BB2_234 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	global_store_b64 v[4:5], v[2:3], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[8:9], v46, v[0:3], s[28:29] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[2:3]
	v_dual_mov_b32 v2, v8 :: v_dual_mov_b32 v3, v9
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB2_314
.LBB2_315:                              ; %__ockl_printf_append_args.exit113
                                        ;   in Loop: Header=BB2_234 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e64 s24, v6
	s_cbranch_execz .LBB2_317
; %bb.316:                              ;   in Loop: Header=BB2_234 Depth=1
	v_lshlrev_b64 v[0:1], 2, v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s34, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s35, v1, vcc_lo
	global_load_b32 v0, v[0:1], off
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v37, v37, v0
.LBB2_317:                              ;   in Loop: Header=BB2_234 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	s_add_i32 s36, s36, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u32 s36, s25
	s_cbranch_scc1 .LBB2_234
	s_branch .LBB2_319
.LBB2_318:
	s_delay_alu instid0(VALU_DEP_1)
	v_mov_b32_e32 v37, v42
                                        ; implicit-def: $vgpr6
.LBB2_319:                              ; %._crit_edge192
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e64 s24, v6
	s_cbranch_execz .LBB2_321
; %bb.320:
	v_lshlrev_b32_e32 v0, 2, v38
	ds_store_b32 v0, v37
.LBB2_321:
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
                                        ; implicit-def: $vgpr0
	v_cmpx_ge_u32_e64 s24, v6
; %bb.322:
	v_lshlrev_b32_e32 v0, 2, v38
	s_or_b32 s33, s33, exec_lo
; %bb.323:                              ; %Flow716
	s_or_b32 exec_lo, exec_lo, s0
.LBB2_324:                              ; %Flow715
	s_and_saveexec_b32 s0, s33
	s_cbranch_execz .LBB2_326
; %bb.325:                              ; %.sink.split
	s_load_b64 s[0:1], s[18:19], 0x8
	ds_load_b32 v2, v0
	v_lshlrev_b64 v[0:1], 2, v[41:42]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	global_store_b32 v[0:1], v2, off
.LBB2_326:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z26kernel_reduce_sum_3d_try02PKfPfiiiiii
		.amdhsa_group_segment_fixed_size 2048
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 55
		.amdhsa_next_free_sgpr 39
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_Z26kernel_reduce_sum_3d_try02PKfPfiiiiii, .Lfunc_end2-_Z26kernel_reduce_sum_3d_try02PKfPfiiiiii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 16164
; NumSgprs: 41
; NumVgprs: 55
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 2048 bytes/workgroup (compile time only)
; SGPRBlocks: 5
; VGPRBlocks: 6
; NumSGPRsForWavesPerEU: 41
; NumVGPRsForWavesPerEU: 55
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z26kernel_reduce_sum_3d_try03PKfPfjjjbbb ; -- Begin function _Z26kernel_reduce_sum_3d_try03PKfPfjjjbbb
	.globl	_Z26kernel_reduce_sum_3d_try03PKfPfjjjbbb
	.p2align	8
	.type	_Z26kernel_reduce_sum_3d_try03PKfPfjjjbbb,@function
_Z26kernel_reduce_sum_3d_try03PKfPfjjjbbb: ; @_Z26kernel_reduce_sum_3d_try03PKfPfjjjbbb
; %bb.0:
	s_clause 0x1
	s_load_b256 s[4:11], s[0:1], 0x0
	s_load_b32 s3, s[0:1], 0x1c
	s_mov_b32 s2, s15
	s_mov_b32 s12, -1
	s_mov_b32 s32, 0
	s_waitcnt lgkmcnt(0)
	s_bitcmp1_b32 s11, 0
	s_cselect_b32 s11, -1, 0
	s_bitcmp1_b32 s3, 8
	s_cselect_b32 s14, -1, 0
	s_bitcmp1_b32 s3, 16
	s_cselect_b32 s15, -1, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b32 s3, s15, -1
	s_or_b32 s3, s3, s14
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s3, s3, s11
	s_and_b32 vcc_lo, exec_lo, s3
	s_cbranch_vccnz .LBB3_15
; %bb.1:
	v_lshlrev_b32_e32 v3, 2, v0
	v_mov_b32_e32 v1, 0
	s_mov_b32 s3, exec_lo
                                        ; implicit-def: $sgpr12_sgpr13
	ds_store_b32 v3, v1
	v_cmpx_le_u32_e64 s8, v0
	s_xor_b32 s3, exec_lo, s3
; %bb.2:                                ; %._crit_edge108
	s_add_u32 s12, s0, 32
	s_addc_u32 s13, s1, 0
; %bb.3:                                ; %Flow150
	s_or_saveexec_b32 s3, s3
	v_dual_mov_b32 v1, s12 :: v_dual_mov_b32 v2, s13
	s_xor_b32 exec_lo, exec_lo, s3
	s_cbranch_execz .LBB3_7
; %bb.4:                                ; %.lr.ph
	s_load_b32 s17, s[0:1], 0x2c
	v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v5, v0
	v_mov_b32_e32 v4, 0
	s_add_u32 s12, s0, 32
	s_mul_i32 s16, s2, s8
	s_addc_u32 s13, s1, 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s18, s17, 0xffff
	s_mov_b32 s17, 0
.LBB3_5:                                ; =>This Inner Loop Header: Depth=1
	v_add_nc_u32_e32 v1, s16, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[6:7], 2, v[1:2]
	v_add_co_u32 v6, vcc_lo, s4, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
	global_load_b32 v1, v[6:7], off
	s_waitcnt vmcnt(0)
	v_dual_add_f32 v4, v1, v4 :: v_dual_add_nc_u32 v5, s18, v5
	v_cmp_le_u32_e32 vcc_lo, s8, v5
	s_or_b32 s17, vcc_lo, s17
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s17
	s_cbranch_execnz .LBB3_5
; %bb.6:                                ; %._crit_edge
	s_or_b32 exec_lo, exec_lo, s17
	v_dual_mov_b32 v1, s12 :: v_dual_mov_b32 v2, s13
	ds_store_b32 v3, v4
.LBB3_7:                                ; %Flow151
	s_or_b32 exec_lo, exec_lo, s3
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	global_load_u16 v1, v[1:2], off offset:12
	s_mov_b32 s3, exec_lo
	s_waitcnt vmcnt(0)
	v_cmpx_lt_u16_e32 1, v1
	s_cbranch_execz .LBB3_12
; %bb.8:                                ; %.lr.ph87.preheader
	v_lshrrev_b16 v1, 1, v1
	s_mov_b32 s12, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_and_b32_e32 v1, 0xffff, v1
.LBB3_9:                                ; %.lr.ph87
                                        ; =>This Inner Loop Header: Depth=1
	s_mov_b32 s13, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_u32_e64 v0, v1
	s_cbranch_execz .LBB3_11
; %bb.10:                               ;   in Loop: Header=BB3_9 Depth=1
	v_lshl_add_u32 v2, v1, 2, v3
	ds_load_b32 v2, v2
	ds_load_b32 v4, v3
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v2, v2, v4
	ds_store_b32 v3, v2
.LBB3_11:                               ;   in Loop: Header=BB3_9 Depth=1
	s_or_b32 exec_lo, exec_lo, s13
	v_lshrrev_b32_e32 v2, 1, v1
	v_cmp_gt_u32_e32 vcc_lo, 2, v1
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_mov_b32_e32 v1, v2
	s_or_b32 s12, vcc_lo, s12
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s12
	s_cbranch_execnz .LBB3_9
.LBB3_12:                               ; %Flow149
	s_or_b32 exec_lo, exec_lo, s3
	s_mov_b32 s12, 0
	s_mov_b32 s13, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB3_14
; %bb.13:
	v_mov_b32_e32 v1, 0
	s_mov_b32 s3, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[16:17], s[2:3], 2
	s_add_u32 s16, s6, s16
	ds_load_b32 v2, v1
	s_addc_u32 s17, s7, s17
	s_waitcnt lgkmcnt(0)
	global_store_b32 v1, v2, s[16:17]
.LBB3_14:                               ; %Flow
	s_or_b32 exec_lo, exec_lo, s13
.LBB3_15:                               ; %Flow175
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s12
	s_cbranch_vccz .LBB3_61
; %bb.16:
	s_xor_b32 s3, s14, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s3, s3, s15
	s_or_b32 s3, s3, s11
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s3
	s_mov_b32 s3, -1
	s_cbranch_vccnz .LBB3_24
; %bb.17:
	s_load_b32 s3, s[0:1], 0x2c
	s_waitcnt lgkmcnt(0)
	s_and_b32 s3, s3, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
	s_mul_i32 s3, s10, s8
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_cmp_gt_u32_e32 vcc_lo, s3, v1
	s_and_saveexec_b32 s3, vcc_lo
	s_cbranch_execz .LBB3_23
; %bb.18:
	s_cmp_eq_u32 s9, 0
	s_cbranch_scc1 .LBB3_21
; %bb.19:                               ; %.lr.ph93.preheader
	v_cvt_f32_u32_e32 v2, s8
	s_sub_i32 s12, 0, s8
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v2, v2
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v2, 0x4f7ffffe, v2
	v_cvt_u32_f32_e32 v2, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v3, s12, v2
	s_mul_i32 s12, s9, s8
	v_mul_hi_u32 v3, v2, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v2, v2, v3
	v_mul_hi_u32 v2, v1, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v3, v2, s8
	v_add_nc_u32_e32 v4, 1, v2
	v_sub_nc_u32_e32 v3, v1, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v5, s8, v3
	v_cmp_le_u32_e32 vcc_lo, s8, v3
	v_dual_cndmask_b32 v2, v2, v4 :: v_dual_cndmask_b32 v3, v3, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v4, 1, v2
	v_cmp_le_u32_e32 vcc_lo, s8, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v5, v2, v4, vcc_lo
	v_mul_lo_u32 v2, v5, s8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v4, v1, v2
	v_mad_u64_u32 v[2:3], null, s12, v5, v[4:5]
	v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v3, 0
	s_mov_b32 s12, s9
.LBB3_20:                               ; %.lr.ph93
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_lshlrev_b64 v[5:6], 2, v[2:3]
	v_add_nc_u32_e32 v2, s8, v2
	s_add_i32 s12, s12, -1
	s_cmp_eq_u32 s12, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v5, vcc_lo, s4, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
	global_load_b32 v5, v[5:6], off
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v4, v4, v5
	s_cbranch_scc0 .LBB3_20
	s_branch .LBB3_22
.LBB3_21:
	v_mov_b32_e32 v4, 0
.LBB3_22:                               ; %._crit_edge94
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s6, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
	global_store_b32 v[1:2], v4, off
.LBB3_23:                               ; %Flow154
	s_or_b32 exec_lo, exec_lo, s3
	s_mov_b32 s3, 0
.LBB3_24:                               ; %Flow173
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s3
	s_cbranch_vccnz .LBB3_61
; %bb.25:
	s_xor_b32 s3, s11, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s3, s3, s14
	s_or_b32 s3, s3, s15
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s3
	s_mov_b32 s3, -1
	s_cbranch_vccnz .LBB3_33
; %bb.26:
	s_load_b32 s3, s[0:1], 0x2c
	s_waitcnt lgkmcnt(0)
	s_and_b32 s3, s3, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
	s_mul_i32 s3, s9, s8
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_u32_e64 s3, v1
	s_cbranch_execz .LBB3_32
; %bb.27:                               ; %.preheader79
	s_cmp_eq_u32 s10, 0
	s_cbranch_scc1 .LBB3_30
; %bb.28:                               ; %.lr.ph98.preheader
	v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v0, 0
	v_mov_b32_e32 v2, v1
.LBB3_29:                               ; %.lr.ph98
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_lshlrev_b64 v[4:5], 2, v[2:3]
	v_add_nc_u32_e32 v2, s3, v2
	s_add_i32 s10, s10, -1
	s_cmp_eq_u32 s10, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v4, vcc_lo, s4, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
	global_load_b32 v4, v[4:5], off
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v0, v0, v4
	s_cbranch_scc0 .LBB3_29
	s_branch .LBB3_31
.LBB3_30:
	v_mov_b32_e32 v0, 0
.LBB3_31:                               ; %._crit_edge99
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s6, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
	global_store_b32 v[1:2], v0, off
.LBB3_32:                               ; %Flow157
	s_or_b32 exec_lo, exec_lo, s2
	s_mov_b32 s3, 0
.LBB3_33:                               ; %Flow171
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s3
	s_cbranch_vccnz .LBB3_61
; %bb.34:
	s_load_b64 s[4:5], s[0:1], 0x70
	v_mbcnt_lo_u32_b32 v4, -1, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_readfirstlane_b32 s2, v4
	v_mov_b32_e32 v6, 0
	v_mov_b32_e32 v7, 0
	v_cmp_eq_u32_e64 s2, s2, v4
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB3_40
; %bb.35:
	v_mov_b32_e32 v0, 0
	s_mov_b32 s6, exec_lo
	s_waitcnt lgkmcnt(0)
	global_load_b64 v[8:9], v0, s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[1:2], v0, s[4:5] offset:40
	global_load_b64 v[5:6], v0, s[4:5]
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v1, v1, v8
	v_and_b32_e32 v2, v2, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v3, v1, 24
	v_mul_lo_u32 v2, v2, 24
	v_mul_lo_u32 v1, v1, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v2, v3, v2
	s_waitcnt vmcnt(0)
	v_add_co_u32 v1, vcc_lo, v5, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, v6, v2, vcc_lo
	global_load_b64 v[6:7], v[1:2], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[6:7], v[8:9]
	s_cbranch_execz .LBB3_39
; %bb.36:                               ; %.preheader3.i.i.i.preheader
	s_mov_b32 s7, 0
.LBB3_37:                               ; %.preheader3.i.i.i
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[1:2], v0, s[4:5] offset:40
	global_load_b64 v[10:11], v0, s[4:5]
	v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v1, v1, v8
	v_and_b32_e32 v7, v2, v9
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[5:6], null, v1, 24, v[10:11]
	v_mov_b32_e32 v1, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[2:3], null, v7, 24, v[1:2]
	v_mov_b32_e32 v6, v2
	global_load_b64 v[6:7], v[5:6], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[8:9]
	s_or_b32 s7, vcc_lo, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s7
	s_cbranch_execnz .LBB3_37
; %bb.38:                               ; %Flow168
	s_or_b32 exec_lo, exec_lo, s7
.LBB3_39:                               ; %Flow170
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s6
.LBB3_40:                               ; %.loopexit4.i.i.i
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s3
	v_mov_b32_e32 v5, 0
	v_readfirstlane_b32 s6, v6
	v_readfirstlane_b32 s7, v7
	s_mov_b32 s12, exec_lo
	s_waitcnt lgkmcnt(0)
	s_clause 0x1
	global_load_b64 v[8:9], v5, s[4:5] offset:40
	global_load_b128 v[0:3], v5, s[4:5]
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s8, v8
	v_readfirstlane_b32 s9, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[8:9], s[6:7], s[8:9]
	s_mul_i32 s3, s9, 24
	s_mul_hi_u32 s10, s8, 24
	s_mul_i32 s11, s8, 24
	s_and_saveexec_b32 s13, s2
	s_cbranch_execz .LBB3_42
; %bb.41:
	v_dual_mov_b32 v6, s12 :: v_dual_mov_b32 v7, v5
	s_add_i32 s12, s10, s3
	s_waitcnt vmcnt(0)
	v_add_co_u32 v10, vcc_lo, v0, s11
	v_add_co_ci_u32_e32 v11, vcc_lo, s12, v1, vcc_lo
	v_dual_mov_b32 v8, 2 :: v_dual_mov_b32 v9, 1
	global_store_b128 v[10:11], v[6:9], off offset:8
.LBB3_42:
	s_or_b32 exec_lo, exec_lo, s13
	s_lshl_b64 s[8:9], s[8:9], 12
	v_lshlrev_b64 v[6:7], 6, v[4:5]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v2, vcc_lo, v2, s8
	v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
	s_mov_b32 s12, 0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v8, vcc_lo, v2, v6
	s_mov_b32 s13, s12
	s_mov_b32 s14, s12
	s_mov_b32 s15, s12
	v_add_co_ci_u32_e32 v9, vcc_lo, v3, v7, vcc_lo
	v_dual_mov_b32 v4, 33 :: v_dual_mov_b32 v7, v5
	v_mov_b32_e32 v6, v5
	v_dual_mov_b32 v10, s12 :: v_dual_mov_b32 v13, s15
	v_dual_mov_b32 v11, s13 :: v_dual_mov_b32 v12, s14
	s_clause 0x3
	global_store_b128 v[8:9], v[4:7], off
	global_store_b128 v[8:9], v[10:13], off offset:16
	global_store_b128 v[8:9], v[10:13], off offset:32
	global_store_b128 v[8:9], v[10:13], off offset:48
	s_and_saveexec_b32 s8, s2
	s_cbranch_execz .LBB3_49
; %bb.43:
	v_mov_b32_e32 v10, 0
	s_mov_b32 s9, exec_lo
	s_clause 0x1
	global_load_b64 v[13:14], v10, s[4:5] offset:32 glc
	global_load_b64 v[2:3], v10, s[4:5] offset:40
	v_dual_mov_b32 v11, s6 :: v_dual_mov_b32 v12, s7
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v3, s7, v3
	v_and_b32_e32 v2, s6, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v3, v3, 24
	v_mul_hi_u32 v4, v2, 24
	v_mul_lo_u32 v2, v2, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v3, v4, v3
	v_add_co_u32 v6, vcc_lo, v0, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v7, vcc_lo, v1, v3, vcc_lo
	global_store_b64 v[6:7], v[13:14], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[4:5], v10, v[11:14], s[4:5] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[4:5], v[13:14]
	s_cbranch_execz .LBB3_45
.LBB3_44:                               ; %.preheader1.i.i.i
                                        ; =>This Inner Loop Header: Depth=1
	v_dual_mov_b32 v2, s6 :: v_dual_mov_b32 v3, s7
	s_sleep 1
	global_store_b64 v[6:7], v[4:5], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v10, v[2:5], s[4:5] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
	v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
	s_or_b32 s12, vcc_lo, s12
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s12
	s_cbranch_execnz .LBB3_44
.LBB3_45:                               ; %Flow166
	s_or_b32 exec_lo, exec_lo, s9
	v_mov_b32_e32 v5, 0
	s_mov_b32 s12, exec_lo
	s_mov_b32 s9, exec_lo
	v_mbcnt_lo_u32_b32 v4, s12, 0
	global_load_b64 v[2:3], v5, s[4:5] offset:16
	v_cmpx_eq_u32_e32 0, v4
	s_cbranch_execz .LBB3_47
; %bb.46:
	s_bcnt1_i32_b32 s12, s12
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v4, s12
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[2:3], v[4:5], off offset:8
.LBB3_47:
	s_or_b32 exec_lo, exec_lo, s9
	s_waitcnt vmcnt(0)
	global_load_b64 v[4:5], v[2:3], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
	s_cbranch_vccnz .LBB3_49
; %bb.48:
	global_load_b32 v2, v[2:3], off offset:24
	v_mov_b32_e32 v3, 0
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s9, v2
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[4:5], v[2:3], off
	s_and_b32 m0, s9, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB3_49:                               ; %Flow167
	s_or_b32 exec_lo, exec_lo, s8
	s_add_i32 s10, s10, s3
	v_add_co_u32 v0, vcc_lo, v0, s11
	v_add_co_ci_u32_e32 v1, vcc_lo, s10, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, 20
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
.LBB3_50:                               ; =>This Inner Loop Header: Depth=1
	v_mov_b32_e32 v2, 1
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB3_52
; %bb.51:                               ;   in Loop: Header=BB3_50 Depth=1
	global_load_b32 v2, v[0:1], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v2, 1, v2
.LBB3_52:                               ;   in Loop: Header=BB3_50 Depth=1
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s3, v2
	s_cmp_eq_u32 s3, 0
	s_cbranch_scc1 .LBB3_54
; %bb.53:                               ;   in Loop: Header=BB3_50 Depth=1
	s_mov_b32 s3, 0
	s_sleep 1
	s_branch .LBB3_55
.LBB3_54:                               ;   in Loop: Header=BB3_50 Depth=1
	s_mov_b32 s3, -1
.LBB3_55:                               ; %Flow161
                                        ;   in Loop: Header=BB3_50 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s3
	s_cbranch_vccnz .LBB3_50
; %bb.56:
	global_load_b64 v[0:1], v[8:9], off
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB3_60
; %bb.57:
	v_mov_b32_e32 v8, 0
	s_clause 0x2
	global_load_b64 v[4:5], v8, s[4:5] offset:40
	global_load_b64 v[9:10], v8, s[4:5] offset:24 glc
	global_load_b64 v[6:7], v8, s[4:5]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v11, vcc_lo, v4, 1
	v_add_co_ci_u32_e32 v12, vcc_lo, 0, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, v11, s6
	v_add_co_ci_u32_e32 v3, vcc_lo, s7, v12, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
	v_dual_cndmask_b32 v3, v3, v12 :: v_dual_cndmask_b32 v2, v2, v11
	v_and_b32_e32 v5, v3, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v4, v2, v4
	v_mul_lo_u32 v5, v5, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v11, v4, 24
	v_mul_lo_u32 v4, v4, 24
	v_add_nc_u32_e32 v5, v11, v5
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v6, vcc_lo, v6, v4
	v_mov_b32_e32 v4, v9
	v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
	v_mov_b32_e32 v5, v10
	global_store_b64 v[6:7], v[9:10], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[4:5], v8, v[2:5], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[4:5], v[9:10]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB3_60
; %bb.58:                               ; %.preheader.i.i.i.preheader
	s_mov_b32 s2, 0
.LBB3_59:                               ; %.preheader.i.i.i
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	global_store_b64 v[6:7], v[4:5], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[9:10], v8, v[2:5], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[9:10], v[4:5]
	v_dual_mov_b32 v4, v9 :: v_dual_mov_b32 v5, v10
	s_or_b32 s2, vcc_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s2
	s_cbranch_execnz .LBB3_59
.LBB3_60:                               ; %__ockl_printf_begin.exit
	s_or_b32 exec_lo, exec_lo, s3
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, .str.2@rel32@lo+4
	s_addc_u32 s3, s3, .str.2@rel32@hi+12
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
	v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
	s_cmp_lg_u64 s[2:3], 0
	v_mov_b32_e32 v6, 1
	s_cselect_b32 s4, 34, 0
	v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s4
	s_add_u32 s8, s0, 32
	s_addc_u32 s9, s1, 0
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, __ockl_printf_append_string_n@rel32@lo+4
	s_addc_u32 s1, s1, __ockl_printf_append_string_n@rel32@hi+12
	s_delay_alu instid0(SALU_CYCLE_1)
	s_swappc_b64 s[30:31], s[0:1]
.LBB3_61:
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z26kernel_reduce_sum_3d_try03PKfPfjjjbbb
		.amdhsa_group_segment_fixed_size 1024
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 36
		.amdhsa_next_free_sgpr 33
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end3:
	.size	_Z26kernel_reduce_sum_3d_try03PKfPfjjjbbb, .Lfunc_end3-_Z26kernel_reduce_sum_3d_try03PKfPfjjjbbb
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 2648
; NumSgprs: 35
; NumVgprs: 36
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 1024 bytes/workgroup (compile time only)
; SGPRBlocks: 4
; VGPRBlocks: 4
; NumSGPRsForWavesPerEU: 35
; NumVGPRsForWavesPerEU: 36
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	.str,@object                    ; @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.str:
	.asciz	"idx: %d : src_index: %d\n"
	.size	.str, 25

	.type	.str.1,@object                  ; @.str.1
.str.1:
	.asciz	"tid: %03d \tidx: %03d\td0: %02d\td1: %02d\n"
	.size	.str.1, 40

	.type	.str.2,@object                  ; @.str.2
.str.2:
	.asciz	"reduce_sum: ERROR-NOTIMPLEMENTED\n"
	.size	.str.2, 34

	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .actual_access:  read_only
        .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .actual_access:  write_only
        .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         36
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         44
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         52
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         54
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         56
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         58
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         60
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         62
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         104
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 4096
    .kernarg_segment_align: 8
    .kernarg_segment_size: 296
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z26kernel_reduce_sum_3d_try01PKfPfiiiiii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z26kernel_reduce_sum_3d_try01PKfPfiiiiii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     12
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .actual_access:  read_only
        .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .actual_access:  write_only
        .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         36
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         44
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         52
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         54
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         56
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         58
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         60
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         62
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         104
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         120
        .size:           8
        .value_kind:     hidden_hostcall_buffer
    .group_segment_fixed_size: 2048
    .kernarg_segment_align: 8
    .kernarg_segment_size: 296
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z26kernel_reduce_sum_3d_try02PKfPfiiiiii
    .private_segment_fixed_size: 0
    .sgpr_count:     41
    .sgpr_spill_count: 0
    .symbol:         _Z26kernel_reduce_sum_3d_try02PKfPfiiiiii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     55
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .actual_access:  read_only
        .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .actual_access:  write_only
        .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           1
        .value_kind:     by_value
      - .offset:         29
        .size:           1
        .value_kind:     by_value
      - .offset:         30
        .size:           1
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         112
        .size:           8
        .value_kind:     hidden_hostcall_buffer
    .group_segment_fixed_size: 1024
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z26kernel_reduce_sum_3d_try03PKfPfjjjbbb
    .private_segment_fixed_size: 0
    .sgpr_count:     35
    .sgpr_spill_count: 0
    .symbol:         _Z26kernel_reduce_sum_3d_try03PKfPfjjjbbb.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     36
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
