#include<stdio.h>
#include<ctime>
#include<cmath>
#include <iostream>
#include <cuda.h>
#include <cuda_runtime_api.h>
#include <device_launch_parameters.h>


#define THREADS 1024 
__global__ void zeroPad(float *a, int arraySize, int SIZE)
{
	int blockId = blockIdx.x 
			 + blockIdx.y * gridDim.x 
			 + gridDim.x * gridDim.y * blockIdx.z; 
	int threadId = blockId * blockDim.x + threadIdx.x;

	
	if(threadId>=SIZE && threadId<arraySize)
	{
		a[threadId] = 0;
	}
}

__global__ void bitonic_sort_step(float *dev_values, int stage, int step, int newSize)

{
  unsigned int arrayIndex, xorVal; 
  int blockId = blockIdx.x 
			 + blockIdx.y * gridDim.x 
			 + gridDim.x * gridDim.y * blockIdx.z; 

  arrayIndex = blockId * blockDim.x + threadIdx.x;

  xorVal = arrayIndex^stage;

 
  //amongst the two threads that are being compared pick the lower thread and as each thread holds an array element 
  //pick the ones with threadID less than the size of the array being sorted 

  if ((xorVal)>arrayIndex && arrayIndex<newSize) {
	// sort the data in ascending order
    if ((arrayIndex&step)==0) {

	//swap if not in the right order
      if (dev_values[arrayIndex]>dev_values[xorVal]) {

        float temp = dev_values[arrayIndex];

        dev_values[arrayIndex] = dev_values[xorVal];

        dev_values[xorVal] = temp;

      }
    }
	// sort the data in descending order
    if ((arrayIndex&step)!=0) {

      //swap if not in the right order
      if (dev_values[arrayIndex]<dev_values[xorVal]) {

        float temp = dev_values[arrayIndex];

        dev_values[arrayIndex] = dev_values[xorVal];

        dev_values[xorVal] = temp;

      }
    }
  }

}
 


float bitonic_sort(float *values, int newSize, int SIZE)

{
  float *dev_values,tgpu = -1;
  clock_t start, end;
  cudaError_t status;

 
  status = cudaMalloc((void**) &dev_values, newSize * sizeof(float));
  
  status = cudaMemcpy(dev_values, values, SIZE * sizeof(float), cudaMemcpyHostToDevice);
    
  dim3 dimBlock(THREADS,1);  
  //decide on the grid size based on the array size
  int grid1 = ceil((float)newSize/(float)THREADS);

	int grid2 = 1;
	int grid3=1;
	if(grid1>65535)
	{
		grid2 =   ceil((float)newSize/(float)THREADS);
		grid1 = 65535;
	}
	if(grid2>65535)
	{
		grid3 = ceil((float)newSize/(float)THREADS);
		grid2 = 65535;
	}
	dim3 dimGrid(grid1,grid2,grid3); 
     



 
  int stage, step;

  start = clock();
  //pad extra zeros when the actual array size is not a power of 2
  if(newSize!=SIZE)
  {
  zeroPad<<<dimGrid, dimBlock>>>(dev_values,newSize,SIZE);
		status = cudaDeviceSynchronize();
  }
  //This loop computes each step of the sorting network
  for (step = 2; step <= newSize; step <<= 1) {

  //This computes each stage in a step
    for (stage=step>>1; stage>0; stage=stage>>1) {

      bitonic_sort_step<<<dimGrid, dimBlock>>>(dev_values, stage, step, newSize);
	  status = cudaDeviceSynchronize();
    }
  }
  end = clock();
  // Check for errors and exit on any failures
		status = cudaGetLastError();
		if (status != cudaSuccess) 
		{
		std::cout << "\n Kernel failed: " << cudaGetErrorString(status) << 
		std::endl;
		
		}
 //if everything is successfully cpy back the results
		else{
			// if the actual array size is a power of 2 copy the entire array
		if(newSize==SIZE)
		cudaMemcpy(values, dev_values, newSize * sizeof(float), cudaMemcpyDeviceToHost);
		//else discard the zeros that are padded and copy the actual sorted entries of the array
		else
		cudaMemcpy(values, dev_values+(newSize-SIZE), SIZE * sizeof(float), cudaMemcpyDeviceToHost);
		tgpu = ((float)((end - start)*1000))/((float)(CLOCKS_PER_SEC));
		}
  cudaFree(dev_values);
  // Returns the time for which the actual computation was being executed on the device 
  return tgpu;
}
 


	.file	"tmpxft_003b102c_00000000-6_bitonic.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3638:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3638:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z28__device_stub__Z7zeroPadPfiiPfii
	.type	_Z28__device_stub__Z7zeroPadPfiiPfii, @function
_Z28__device_stub__Z7zeroPadPfiiPfii:
.LFB3660:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 8(%rsp)
	leaq	24(%rsp), %rcx
	leaq	32(%rsp), %rdi
	movl	%esi, 4(%rsp)
	leaq	44(%rsp), %rsi
	movl	%edx, (%rsp)
	leaq	16(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 40(%rsp)
	movq	%rax, 80(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 88(%rsp)
	movq	%rsp, %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 32(%rsp)
	movq	%rax, 44(%rsp)
	movl	$1, 52(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	24(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7zeroPadPfii(%rip), %rdi
	pushq	24(%rsp)
	.cfi_def_cfa_offset 144
	movq	60(%rsp), %rcx
	movl	68(%rsp), %r8d
	movq	48(%rsp), %rsi
	movl	56(%rsp), %edx
	leaq	96(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L2:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3660:
	.size	_Z28__device_stub__Z7zeroPadPfiiPfii, .-_Z28__device_stub__Z7zeroPadPfiiPfii
	.globl	_Z7zeroPadPfii
	.type	_Z7zeroPadPfii, @function
_Z7zeroPadPfii:
.LFB3661:
	.cfi_startproc
	endbr64
	jmp	_Z28__device_stub__Z7zeroPadPfiiPfii
	.cfi_endproc
.LFE3661:
	.size	_Z7zeroPadPfii, .-_Z7zeroPadPfii
	.globl	_Z40__device_stub__Z17bitonic_sort_stepPfiiiPfiii
	.type	_Z40__device_stub__Z17bitonic_sort_stepPfiiiPfiii, @function
_Z40__device_stub__Z17bitonic_sort_stepPfiiiPfiii:
.LFB3662:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movl	%esi, 20(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 16(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 12(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L8
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z17bitonic_sort_stepPfiii(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L8:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L10
	call	__stack_chk_fail@PLT
.L10:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3662:
	.size	_Z40__device_stub__Z17bitonic_sort_stepPfiiiPfiii, .-_Z40__device_stub__Z17bitonic_sort_stepPfiiiPfiii
	.globl	_Z17bitonic_sort_stepPfiii
	.type	_Z17bitonic_sort_stepPfiii, @function
_Z17bitonic_sort_stepPfiii:
.LFB3663:
	.cfi_startproc
	endbr64
	jmp	_Z40__device_stub__Z17bitonic_sort_stepPfiiiPfiii
	.cfi_endproc
.LFE3663:
	.size	_Z17bitonic_sort_stepPfiii, .-_Z17bitonic_sort_stepPfiii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC2:
	.string	"\n Kernel failed: "
	.text
	.globl	_Z12bitonic_sortPfii
	.type	_Z12bitonic_sortPfii, @function
_Z12bitonic_sortPfii:
.LFB3635:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movq	%rdi, %r12
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movl	%edx, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movl	%esi, %ebx
	subq	$72, %rsp
	.cfi_def_cfa_offset 128
	movq	%fs:40, %rax
	movq	%rax, 56(%rsp)
	xorl	%eax, %eax
	movslq	%esi, %rax
	leaq	24(%rsp), %rdi
	salq	$2, %rax
	movq	%rax, %rsi
	movq	%rax, (%rsp)
	call	cudaMalloc@PLT
	movslq	%ebp, %rax
	movq	24(%rsp), %rdi
	movq	%r12, %rsi
	salq	$2, %rax
	movl	$1, %ecx
	movq	%rax, %rdx
	movq	%rax, 8(%rsp)
	call	cudaMemcpy@PLT
	cvtsi2ssl	%ebx, %xmm0
	mulss	.LC1(%rip), %xmm0
	movl	$4194305, %eax
	salq	$10, %rax
	movl	$1, 40(%rsp)
	movq	%rax, 32(%rsp)
	call	ceilf@PLT
	cvttss2sil	%xmm0, %eax
	cmpl	$65535, %eax
	jle	.L27
	movl	%eax, %edx
	movl	$65535, %ecx
	movl	$65535, %eax
	jmp	.L14
.L27:
	movl	$1, %edx
	movl	$1, %ecx
.L14:
	movl	%eax, 44(%rsp)
	movl	%ecx, 48(%rsp)
	movl	%edx, 52(%rsp)
	call	clock@PLT
	movq	%rax, %r15
	cmpl	%ebp, %ebx
	je	.L15
	movl	40(%rsp), %ecx
	movq	32(%rsp), %rdx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	44(%rsp), %rdi
	movl	52(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L16
	movq	24(%rsp), %rdi
	movl	%ebp, %edx
	movl	%ebx, %esi
	call	_Z28__device_stub__Z7zeroPadPfiiPfii
.L16:
	call	cudaDeviceSynchronize@PLT
.L15:
	movl	$2, %r13d
.L17:
	cmpl	%ebx, %r13d
	jg	.L31
	movl	%r13d, %r14d
.L29:
	sarl	%r14d
	testl	%r14d, %r14d
	jle	.L32
	movl	40(%rsp), %ecx
	movq	32(%rsp), %rdx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	44(%rsp), %rdi
	movl	52(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L19
	movq	24(%rsp), %rdi
	movl	%ebx, %ecx
	movl	%r13d, %edx
	movl	%r14d, %esi
	call	_Z40__device_stub__Z17bitonic_sort_stepPfiiiPfiii
.L19:
	call	cudaDeviceSynchronize@PLT
	jmp	.L29
.L32:
	addl	%r13d, %r13d
	jmp	.L17
.L31:
	call	clock@PLT
	movq	%rax, %r13
	call	cudaGetLastError@PLT
	movl	%eax, %r14d
	testl	%eax, %eax
	je	.L22
	leaq	.LC2(%rip), %rsi
	leaq	_ZSt4cout(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	%r14d, %edi
	movq	%rax, %rbx
	call	cudaGetErrorString@PLT
	movq	%rbx, %rdi
	movq	%rax, %rsi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%rax, %rdi
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
	movss	.LC0(%rip), %xmm0
	jmp	.L23
.L22:
	movq	24(%rsp), %rsi
	cmpl	%ebp, %ebx
	jne	.L24
	movq	(%rsp), %rdx
	movl	$2, %ecx
	jmp	.L30
.L24:
	subl	%ebp, %ebx
	movq	8(%rsp), %rdx
	movl	$2, %ecx
	movslq	%ebx, %rbx
	leaq	(%rsi,%rbx,4), %rsi
.L30:
	subq	%r15, %r13
	movq	%r12, %rdi
	call	cudaMemcpy@PLT
	imulq	$1000, %r13, %r13
	cvtsi2ssq	%r13, %xmm0
	divss	.LC3(%rip), %xmm0
.L23:
	movq	24(%rsp), %rdi
	movss	%xmm0, (%rsp)
	call	cudaFree@PLT
	movss	(%rsp), %xmm0
	movq	56(%rsp), %rax
	subq	%fs:40, %rax
	je	.L26
	call	__stack_chk_fail@PLT
.L26:
	addq	$72, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3635:
	.size	_Z12bitonic_sortPfii, .-_Z12bitonic_sortPfii
	.section	.rodata.str1.1
.LC4:
	.string	"_Z17bitonic_sort_stepPfiii"
.LC5:
	.string	"_Z7zeroPadPfii"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3665:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC4(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z17bitonic_sort_stepPfiii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC5(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z7zeroPadPfii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3665:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst4,"aM",@progbits,4
	.align 4
.LC0:
	.long	-1082130432
	.align 4
.LC1:
	.long	981467136
	.align 4
.LC3:
	.long	1232348160
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include<stdio.h>
#include<ctime>
#include<cmath>
#include <iostream>
#include <hip/hip_runtime.h>
#include <hip/hip_runtime_api.h>



#define THREADS 1024 
__global__ void zeroPad(float *a, int arraySize, int SIZE)
{
	int blockId = blockIdx.x 
			 + blockIdx.y * gridDim.x 
			 + gridDim.x * gridDim.y * blockIdx.z; 
	int threadId = blockId * blockDim.x + threadIdx.x;

	
	if(threadId>=SIZE && threadId<arraySize)
	{
		a[threadId] = 0;
	}
}

__global__ void bitonic_sort_step(float *dev_values, int stage, int step, int newSize)

{
  unsigned int arrayIndex, xorVal; 
  int blockId = blockIdx.x 
			 + blockIdx.y * gridDim.x 
			 + gridDim.x * gridDim.y * blockIdx.z; 

  arrayIndex = blockId * blockDim.x + threadIdx.x;

  xorVal = arrayIndex^stage;

 
  //amongst the two threads that are being compared pick the lower thread and as each thread holds an array element 
  //pick the ones with threadID less than the size of the array being sorted 

  if ((xorVal)>arrayIndex && arrayIndex<newSize) {
	// sort the data in ascending order
    if ((arrayIndex&step)==0) {

	//swap if not in the right order
      if (dev_values[arrayIndex]>dev_values[xorVal]) {

        float temp = dev_values[arrayIndex];

        dev_values[arrayIndex] = dev_values[xorVal];

        dev_values[xorVal] = temp;

      }
    }
	// sort the data in descending order
    if ((arrayIndex&step)!=0) {

      //swap if not in the right order
      if (dev_values[arrayIndex]<dev_values[xorVal]) {

        float temp = dev_values[arrayIndex];

        dev_values[arrayIndex] = dev_values[xorVal];

        dev_values[xorVal] = temp;

      }
    }
  }

}
 


float bitonic_sort(float *values, int newSize, int SIZE)

{
  float *dev_values,tgpu = -1;
  clock_t start, end;
  hipError_t status;

 
  status = hipMalloc((void**) &dev_values, newSize * sizeof(float));
  
  status = hipMemcpy(dev_values, values, SIZE * sizeof(float), hipMemcpyHostToDevice);
    
  dim3 dimBlock(THREADS,1);  
  //decide on the grid size based on the array size
  int grid1 = ceil((float)newSize/(float)THREADS);

	int grid2 = 1;
	int grid3=1;
	if(grid1>65535)
	{
		grid2 =   ceil((float)newSize/(float)THREADS);
		grid1 = 65535;
	}
	if(grid2>65535)
	{
		grid3 = ceil((float)newSize/(float)THREADS);
		grid2 = 65535;
	}
	dim3 dimGrid(grid1,grid2,grid3); 
     



 
  int stage, step;

  start = clock();
  //pad extra zeros when the actual array size is not a power of 2
  if(newSize!=SIZE)
  {
  zeroPad<<<dimGrid, dimBlock>>>(dev_values,newSize,SIZE);
		status = hipDeviceSynchronize();
  }
  //This loop computes each step of the sorting network
  for (step = 2; step <= newSize; step <<= 1) {

  //This computes each stage in a step
    for (stage=step>>1; stage>0; stage=stage>>1) {

      bitonic_sort_step<<<dimGrid, dimBlock>>>(dev_values, stage, step, newSize);
	  status = hipDeviceSynchronize();
    }
  }
  end = clock();
  // Check for errors and exit on any failures
		status = hipGetLastError();
		if (status != hipSuccess) 
		{
		std::cout << "\n Kernel failed: " << hipGetErrorString(status) << 
		std::endl;
		
		}
 //if everything is successfully cpy back the results
		else{
			// if the actual array size is a power of 2 copy the entire array
		if(newSize==SIZE)
		hipMemcpy(values, dev_values, newSize * sizeof(float), hipMemcpyDeviceToHost);
		//else discard the zeros that are padded and copy the actual sorted entries of the array
		else
		hipMemcpy(values, dev_values+(newSize-SIZE), SIZE * sizeof(float), hipMemcpyDeviceToHost);
		tgpu = ((float)((end - start)*1000))/((float)(CLOCKS_PER_SEC));
		}
  hipFree(dev_values);
  // Returns the time for which the actual computation was being executed on the device 
  return tgpu;
}
 


	.text
	.file	"bitonic.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z22__device_stub__zeroPadPfii  # -- Begin function _Z22__device_stub__zeroPadPfii
	.type	_Z22__device_stub__zeroPadPfii,@function
_Z22__device_stub__zeroPadPfii:         # @_Z22__device_stub__zeroPadPfii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$96, %rsp
	.cfi_def_cfa_offset 144
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	4(%rsp), %rcx
	movl	%esi, (%rcx)
	movq	%rsp, %rsi
	movl	%edx, (%rsi)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7zeroPadPfii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$112, %rsp
	.cfi_adjust_cfa_offset -112
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z22__device_stub__zeroPadPfii, .Lfunc_end0-_Z22__device_stub__zeroPadPfii
	.cfi_endproc
                                        # -- End function
	.globl	_Z32__device_stub__bitonic_sort_stepPfiii # -- Begin function _Z32__device_stub__bitonic_sort_stepPfiii
	.type	_Z32__device_stub__bitonic_sort_stepPfiii,@function
_Z32__device_stub__bitonic_sort_stepPfiii: # @_Z32__device_stub__bitonic_sort_stepPfiii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	20(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	16(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	12(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z17bitonic_sort_stepPfiii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z32__device_stub__bitonic_sort_stepPfiii, .Lfunc_end1-_Z32__device_stub__bitonic_sort_stepPfiii
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0                          # -- Begin function _Z12bitonic_sortPfii
.LCPI2_0:
	.long	0x3a800000                      # float 9.765625E-4
.LCPI2_1:
	.long	0xbf800000                      # float -1
.LCPI2_2:
	.long	0x49742400                      # float 1.0E+6
	.text
	.globl	_Z12bitonic_sortPfii
	.type	_Z12bitonic_sortPfii,@function
_Z12bitonic_sortPfii:                   # @_Z12bitonic_sortPfii
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$56, %rsp
	.cfi_def_cfa_offset 112
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%edx, %r14d
	movl	%esi, %ebp
	movq	%rdi, %r12
	movabsq	$4294968320, %r13               # imm = 0x100000400
	movslq	%esi, %r15
	leaq	(,%r15,4), %rsi
	leaq	16(%rsp), %rbx
	movq	%rbx, %rdi
	movq	%rsi, 48(%rsp)                  # 8-byte Spill
	callq	hipMalloc
	movq	(%rbx), %rdi
	movl	%r14d, 12(%rsp)                 # 4-byte Spill
	movslq	%r14d, %rbx
	leaq	(,%rbx,4), %rdx
	movl	$1, %r14d
	movq	%r12, 32(%rsp)                  # 8-byte Spill
	movq	%r12, %rsi
	movq	%rdx, 40(%rsp)                  # 8-byte Spill
	movl	$1, %ecx
	callq	hipMemcpy
	cvtsi2ss	%r15d, %xmm0
	mulss	.LCPI2_0(%rip), %xmm0
	callq	ceilf@PLT
	cvttss2si	%xmm0, %eax
	movl	$65535, %r12d                   # imm = 0xFFFF
	cmpl	%r12d, %eax
	cmovll	%eax, %r12d
	leaq	-1024(%r13), %rcx
	cmpl	$65536, %eax                    # imm = 0x10000
	cmovgel	%eax, %r14d
	movabsq	$281470681743360, %rax          # imm = 0xFFFF00000000
	cmovlq	%rcx, %rax
	orq	%rax, %r12
	callq	clock
	movq	%rax, 24(%rsp)                  # 8-byte Spill
	cmpl	%ebx, %r15d
	je	.LBB2_4
# %bb.1:
	movq	%r12, %rdi
	movl	%r14d, %esi
	movq	%r13, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_3
# %bb.2:
	movq	16(%rsp), %rdi
	movl	%ebp, %esi
	movl	12(%rsp), %edx                  # 4-byte Reload
	callq	_Z22__device_stub__zeroPadPfii
.LBB2_3:
	callq	hipDeviceSynchronize
.LBB2_4:
	cmpl	$2, %ebp
	jl	.LBB2_11
# %bb.5:                                # %.lr.ph77.preheader
	movl	$2, %r15d
.LBB2_6:                                # %.lr.ph77
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB2_7 Depth 2
	movl	%r15d, %ebx
	sarl	%ebx
	testl	%ebx, %ebx
	jle	.LBB2_10
.LBB2_7:                                # %.lr.ph
                                        #   Parent Loop BB2_6 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movq	%r12, %rdi
	movl	%r14d, %esi
	movq	%r13, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_9
# %bb.8:                                #   in Loop: Header=BB2_7 Depth=2
	movq	16(%rsp), %rdi
	movl	%ebx, %esi
	movl	%r15d, %edx
	movl	%ebp, %ecx
	callq	_Z32__device_stub__bitonic_sort_stepPfiii
.LBB2_9:                                #   in Loop: Header=BB2_7 Depth=2
	callq	hipDeviceSynchronize
	movl	%ebx, %eax
	shrl	%eax
	cmpl	$1, %ebx
	movl	%eax, %ebx
	ja	.LBB2_7
.LBB2_10:                               # %._crit_edge
                                        #   in Loop: Header=BB2_6 Depth=1
	addl	%r15d, %r15d
	cmpl	%ebp, %r15d
	jle	.LBB2_6
.LBB2_11:                               # %._crit_edge78
	callq	clock
	movq	%rax, %rbx
	callq	hipGetLastError
	testl	%eax, %eax
	je	.LBB2_16
# %bb.12:
	movl	%eax, %r14d
	movl	$_ZSt4cout, %edi
	movl	$.L.str, %esi
	movl	$17, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	%r14d, %edi
	callq	hipGetErrorString
	testq	%rax, %rax
	je	.LBB2_13
# %bb.14:
	movq	%rax, %rbx
	movq	%rax, %rdi
	callq	strlen
	movl	$_ZSt4cout, %edi
	movq	%rbx, %rsi
	movq	%rax, %rdx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	jmp	.LBB2_15
.LBB2_16:
	movq	16(%rsp), %rsi
	subl	12(%rsp), %ebp                  # 4-byte Folded Reload
	jne	.LBB2_18
# %bb.17:
	movq	32(%rsp), %rdi                  # 8-byte Reload
	movq	48(%rsp), %rdx                  # 8-byte Reload
	jmp	.LBB2_19
.LBB2_13:
	movq	_ZSt4cout(%rip), %rax
	movq	-24(%rax), %rax
	leaq	_ZSt4cout(%rax), %rdi
	movl	32(%rdi), %esi
	orl	$1, %esi
	callq	_ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.LBB2_15:                               # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
	movq	_ZSt4cout(%rip), %rax
	movl	$_ZSt4cout, %ecx
	movq	-24(%rax), %rdi
	addq	%rcx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movl	$_ZSt4cout, %edi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movss	.LCPI2_1(%rip), %xmm0           # xmm0 = mem[0],zero,zero,zero
	jmp	.LBB2_20
.LBB2_18:
	movslq	%ebp, %rax
	leaq	(%rsi,%rax,4), %rsi
	movq	32(%rsp), %rdi                  # 8-byte Reload
	movq	40(%rsp), %rdx                  # 8-byte Reload
.LBB2_19:
	movl	$2, %ecx
	callq	hipMemcpy
	movq	24(%rsp), %rax                  # 8-byte Reload
	subq	%rax, %rbx
	imulq	$1000, %rbx, %rax               # imm = 0x3E8
	xorps	%xmm0, %xmm0
	cvtsi2ss	%rax, %xmm0
	divss	.LCPI2_2(%rip), %xmm0
.LBB2_20:
	movss	%xmm0, 12(%rsp)                 # 4-byte Spill
	movq	16(%rsp), %rdi
	callq	hipFree
	movss	12(%rsp), %xmm0                 # 4-byte Reload
                                        # xmm0 = mem[0],zero,zero,zero
	addq	$56, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z12bitonic_sortPfii, .Lfunc_end2-_Z12bitonic_sortPfii
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB3_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB3_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z7zeroPadPfii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z17bitonic_sort_stepPfiii, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end3:
	.size	__hip_module_ctor, .Lfunc_end3-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB4_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB4_2:
	retq
.Lfunc_end4:
	.size	__hip_module_dtor, .Lfunc_end4-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z7zeroPadPfii,@object          # @_Z7zeroPadPfii
	.section	.rodata,"a",@progbits
	.globl	_Z7zeroPadPfii
	.p2align	3, 0x0
_Z7zeroPadPfii:
	.quad	_Z22__device_stub__zeroPadPfii
	.size	_Z7zeroPadPfii, 8

	.type	_Z17bitonic_sort_stepPfiii,@object # @_Z17bitonic_sort_stepPfiii
	.globl	_Z17bitonic_sort_stepPfiii
	.p2align	3, 0x0
_Z17bitonic_sort_stepPfiii:
	.quad	_Z32__device_stub__bitonic_sort_stepPfiii
	.size	_Z17bitonic_sort_stepPfiii, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"\n Kernel failed: "
	.size	.L.str, 18

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z7zeroPadPfii"
	.size	.L__unnamed_1, 15

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z17bitonic_sort_stepPfiii"
	.size	.L__unnamed_2, 27

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z22__device_stub__zeroPadPfii
	.addrsig_sym _Z32__device_stub__bitonic_sort_stepPfiii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z7zeroPadPfii
	.addrsig_sym _Z17bitonic_sort_stepPfiii
	.addrsig_sym _ZSt4cout
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z7zeroPadPfii          ; -- Begin function _Z7zeroPadPfii
	.globl	_Z7zeroPadPfii
	.p2align	8
	.type	_Z7zeroPadPfii,@function
_Z7zeroPadPfii:                         ; @_Z7zeroPadPfii
; %bb.0:
	s_clause 0x1
	s_load_b128 s[4:7], s[0:1], 0x8
	s_load_b32 s2, s[0:1], 0x1c
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s3, s7, s15
	s_and_b32 s2, s2, 0xffff
	s_add_i32 s3, s3, s14
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s3, s3, s6
	s_add_i32 s3, s3, s13
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s3, s2, v[0:1]
	v_cmp_le_i32_e32 vcc_lo, s5, v1
	v_cmp_gt_i32_e64 s2, s4, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, vcc_lo, s2
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_2
; %bb.1:
	s_load_b64 s[0:1], s[0:1], 0x0
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	v_mov_b32_e32 v2, 0
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v0, vcc_lo, s0, v0
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	global_store_b32 v[0:1], v2, off
.LBB0_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7zeroPadPfii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 3
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z7zeroPadPfii, .Lfunc_end0-_Z7zeroPadPfii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 160
; NumSgprs: 18
; NumVgprs: 3
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 3
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z17bitonic_sort_stepPfiii ; -- Begin function _Z17bitonic_sort_stepPfiii
	.globl	_Z17bitonic_sort_stepPfiii
	.p2align	8
	.type	_Z17bitonic_sort_stepPfiii,@function
_Z17bitonic_sort_stepPfiii:             ; @_Z17bitonic_sort_stepPfiii
; %bb.0:
	s_clause 0x2
	s_load_b64 s[2:3], s[0:1], 0x18
	s_load_b32 s8, s[0:1], 0x24
	s_load_b128 s[4:7], s[0:1], 0x8
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s3, s3, s15
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s3, s3, s14
	s_mul_i32 s2, s3, s2
	s_and_b32 s3, s8, 0xffff
	s_add_i32 s2, s2, s13
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[4:5], null, s2, s3, v[0:1]
	s_mov_b32 s2, exec_lo
	v_xor_b32_e32 v0, s4, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_min_u32_e32 v1, s6, v0
	v_cmpx_gt_u32_e64 v1, v4
	s_cbranch_execz .LBB1_7
; %bb.1:
	s_load_b64 s[0:1], s[0:1], 0x0
	v_mov_b32_e32 v5, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[4:5]
	v_dual_mov_b32 v1, v5 :: v_dual_and_b32 v4, s5, v4
	v_lshlrev_b64 v[5:6], 2, v[0:1]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v0, vcc_lo, s0, v2
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v2, vcc_lo, s0, v5
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v6, vcc_lo
	s_mov_b32 s0, 0
	s_clause 0x1
	global_load_b32 v5, v[0:1], off
	global_load_b32 v6, v[2:3], off
	s_mov_b32 s1, exec_lo
	v_cmpx_ne_u32_e32 0, v4
	s_xor_b32 s1, exec_lo, s1
	s_cbranch_execz .LBB1_3
; %bb.2:
	s_waitcnt vmcnt(0)
	v_cmp_lt_f32_e32 vcc_lo, v5, v6
	s_and_b32 s0, vcc_lo, exec_lo
.LBB1_3:                                ; %Flow
	s_and_not1_saveexec_b32 s1, s1
	s_cbranch_execz .LBB1_5
; %bb.4:
	s_waitcnt vmcnt(0)
	v_cmp_gt_f32_e32 vcc_lo, v5, v6
	s_and_not1_b32 s0, s0, exec_lo
	s_and_b32 s2, vcc_lo, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s0, s0, s2
.LBB1_5:                                ; %Flow56
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB1_7
; %bb.6:                                ; %.sink.split
	s_waitcnt vmcnt(0)
	s_clause 0x1
	global_store_b32 v[0:1], v6, off
	global_store_b32 v[2:3], v5, off
.LBB1_7:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z17bitonic_sort_stepPfiii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 7
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z17bitonic_sort_stepPfiii, .Lfunc_end1-_Z17bitonic_sort_stepPfiii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 312
; NumSgprs: 18
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .offset:         12
        .size:           4
        .value_kind:     by_value
      - .offset:         16
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         20
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         28
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         30
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         32
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         34
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         36
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         38
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         56
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         80
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 272
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z7zeroPadPfii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z7zeroPadPfii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     3
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .offset:         12
        .size:           4
        .value_kind:     by_value
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z17bitonic_sort_stepPfiii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z17bitonic_sort_stepPfiii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     7
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
