// richu shaji abraham richursa
#include<iostream>
#include<stdio.h>
using namespace std;
__device__ int function(int value , int bit ,int bitset)
{
    if(bitset == 1 )
    {
        if((value & bit)  != 0)
        {
            return 1;
        }
        else 
            return 0;
    }
    else
    {
        if((value & bit) == 0)
        {
            return 1;
        }
        else 
        {
            return 0;
        }
    }
}
__global__ void predicateDevice(int *d_array , int *d_predicateArrry , int d_numberOfElements,int bit,int bitset)
{
    int index = threadIdx.x + blockIdx.x*blockDim.x;
    if(index < d_numberOfElements)
    {
    
           d_predicateArrry[index] = function(d_array[index],bit,bitset);
    }
}

__global__ void scatter(int *d_array , int *d_scanArray , int *d_predicateArrry,int * d_scatteredArray ,int d_numberOfElements,int offset)
{
    int index = threadIdx.x + blockIdx.x * blockDim.x;
    if(index < d_numberOfElements)
    {
        if(d_predicateArrry[index] == 1)
        {
            d_scatteredArray[d_scanArray[index] - 1 +offset ] = d_array[index];
        
        }
    }
}
__global__ void hillisSteeleScanDevice(int *d_array , int numberOfElements, int *d_tmpArray,int moveIndex)
{
    int index = threadIdx.x + blockDim.x * blockIdx.x;
    if(index > numberOfElements)
    {
        return;
    }
    d_tmpArray[index] = d_array[index];
    if(index - moveIndex >=0)
    {
        
        d_tmpArray[index] = d_tmpArray[index] +d_array[index - moveIndex];
    }
}
int* hillisSteeleScanHost(int *d_scanArray,int numberOfElements)
{
    
    
    int *d_tmpArray;
    int *d_tmpArray1;
    cudaMalloc(&d_tmpArray1,sizeof(int)*numberOfElements);
    cudaMalloc(&d_tmpArray,sizeof(int)*numberOfElements);
    cudaMemcpy(d_tmpArray1,d_scanArray,sizeof(int)*numberOfElements,cudaMemcpyDeviceToDevice);
    int j,k=0;
    for(j=1;j<numberOfElements;j= j*2,k++)
    {
        if(k%2 == 0)
        {
            hillisSteeleScanDevice<<<1600,500>>>(d_tmpArray1,numberOfElements,d_tmpArray, j);
            cudaDeviceSynchronize();
        }
        else
        {
            hillisSteeleScanDevice<<<1600,500>>>(d_tmpArray,numberOfElements,d_tmpArray1, j);
            cudaDeviceSynchronize();
        }
    } 
    cudaDeviceSynchronize();
    if(k%2 == 0)
    {
        
        return d_tmpArray1;
    }
    else
    {
        return d_tmpArray;
    }
}
__global__ void print(int *d_predicateArrry,int numberOfElements)
{
    
    for(int i=0;i<numberOfElements;i++)
    {
        printf("index = %d value = %d\n",i,d_predicateArrry[i]);
    }
}

int *compact(int *d_array,int numberOfElements,int bit)
{   
    int offset;
    int *d_predicateArrry;
    cudaMalloc((void**)&d_predicateArrry,sizeof(int)*numberOfElements);
    predicateDevice<<<1600,500>>>(d_array,d_predicateArrry,numberOfElements,bit,0);
    int *d_scanArray;
    d_scanArray = hillisSteeleScanHost(d_predicateArrry,numberOfElements);
    int *d_scatteredArray;
    cudaMalloc((void**)&d_scatteredArray,sizeof(int)*numberOfElements);
    //cout<<"offset = "<<offset<<"\n";
    scatter<<<1600,500>>>(d_array,d_scanArray,d_predicateArrry,d_scatteredArray, numberOfElements,0);
    cudaMemcpy(&offset,d_scanArray+numberOfElements-1,sizeof(int),cudaMemcpyDeviceToHost);
    predicateDevice<<<1600,500>>>(d_array,d_predicateArrry,numberOfElements,bit,1);
    d_scanArray = hillisSteeleScanHost(d_predicateArrry,numberOfElements);
    scatter<<<1600,500>>>(d_array,d_scanArray,d_predicateArrry,d_scatteredArray, numberOfElements,offset);
    return d_scatteredArray;
}
int offset;
int *positivenegativesplit(int *d_array,int numberOfElements,int bit,int bitset)
{   
    int *d_predicateArrry;
    cudaMalloc((void**)&d_predicateArrry,sizeof(int)*numberOfElements);
    predicateDevice<<<1600,500>>>(d_array,d_predicateArrry,numberOfElements,bit,bitset);
    int *d_scanArray;
    d_scanArray = hillisSteeleScanHost(d_predicateArrry,numberOfElements);
    int *d_scatteredArray;
    cudaMemcpy(&offset,d_scanArray+numberOfElements-1,sizeof(int),cudaMemcpyDeviceToHost);
    cudaMalloc((void**)&d_scatteredArray,sizeof(int)*offset);
    scatter<<<1600,500>>>(d_array,d_scanArray,d_predicateArrry,d_scatteredArray, numberOfElements,0);
    return d_scatteredArray;
}
int * radixSort(int *d_array , int numberOfElements)
{
    int bit;
    int *d_negativeArray = positivenegativesplit(d_array,numberOfElements,1L<<31,1);
    for(int i=0;i<sizeof(int)*8;i++)
    {
        bit = 1<<i;
        d_negativeArray = compact(d_negativeArray,offset,bit);
    }
    int *d_postiveArray = positivenegativesplit(d_array,numberOfElements,1L<<31,0);
    for(int i=0;i<sizeof(int)*8;i++)
    {
        bit = 1<<i;
        d_postiveArray = compact(d_postiveArray,offset,bit);
    }
    cudaMemcpy(d_array,d_negativeArray,sizeof(int)*(numberOfElements-offset),cudaMemcpyDeviceToDevice);
    cudaMemcpy(d_array+(numberOfElements-offset),d_postiveArray,sizeof(int)*offset,cudaMemcpyDeviceToDevice);
    return d_array;
}
int main()
{
    cout<<"enter the number of elements \n";
    int numberOfElements;
    cin>>numberOfElements;
    int *h_array  = new int[numberOfElements];
    for(int i=0;i<numberOfElements;i++)
    {
        cin>>h_array[i];
    }
    int *d_array;
    cudaMalloc((void**)&d_array ,sizeof(int)*numberOfElements);
    cudaMemcpy(d_array,h_array,sizeof(int)*numberOfElements,cudaMemcpyHostToDevice);
    d_array = radixSort(d_array, numberOfElements);
    cudaMemcpy(h_array,d_array,sizeof(int)*numberOfElements,cudaMemcpyDeviceToHost);
    for(int i=0;i<numberOfElements;i++)
    {
        cout<<h_array[i]<<"\n";
    }
}

	.file	"tmpxft_002b80dc_00000000-6_radixSortCuda.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3643:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3643:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z8functioniii
	.type	_Z8functioniii, @function
_Z8functioniii:
.LFB3635:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE3635:
	.size	_Z8functioniii, .-_Z8functioniii
	.globl	_Z40__device_stub__Z15predicateDevicePiS_iiiPiS_iii
	.type	_Z40__device_stub__Z15predicateDevicePiS_iiiPiS_iii, @function
_Z40__device_stub__Z15predicateDevicePiS_iiiPiS_iii:
.LFB3665:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	32(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	40(%rsp), %rcx
	movl	%r8d, 4(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L4
	pushq	40(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z15predicateDevicePiS_iii(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 176
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L4:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L6
	call	__stack_chk_fail@PLT
.L6:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3665:
	.size	_Z40__device_stub__Z15predicateDevicePiS_iiiPiS_iii, .-_Z40__device_stub__Z15predicateDevicePiS_iiiPiS_iii
	.globl	_Z15predicateDevicePiS_iii
	.type	_Z15predicateDevicePiS_iii, @function
_Z15predicateDevicePiS_iii:
.LFB3666:
	.cfi_startproc
	endbr64
	jmp	_Z40__device_stub__Z15predicateDevicePiS_iiiPiS_iii
	.cfi_endproc
.LFE3666:
	.size	_Z15predicateDevicePiS_iii, .-_Z15predicateDevicePiS_iii
	.globl	_Z34__device_stub__Z7scatterPiS_S_S_iiPiS_S_S_ii
	.type	_Z34__device_stub__Z7scatterPiS_S_S_iiPiS_S_S_ii, @function
_Z34__device_stub__Z7scatterPiS_S_S_iiPiS_S_S_ii:
.LFB3667:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	56(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	64(%rsp), %rcx
	movl	%r8d, 12(%rsp)
	movl	%r9d, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L10
	pushq	64(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z7scatterPiS_S_S_ii(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 208
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L10:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L12
	call	__stack_chk_fail@PLT
.L12:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3667:
	.size	_Z34__device_stub__Z7scatterPiS_S_S_iiPiS_S_S_ii, .-_Z34__device_stub__Z7scatterPiS_S_S_iiPiS_S_S_ii
	.globl	_Z7scatterPiS_S_S_ii
	.type	_Z7scatterPiS_S_S_ii, @function
_Z7scatterPiS_S_S_ii:
.LFB3668:
	.cfi_startproc
	endbr64
	jmp	_Z34__device_stub__Z7scatterPiS_S_S_iiPiS_S_S_ii
	.cfi_endproc
.LFE3668:
	.size	_Z7scatterPiS_S_S_ii, .-_Z7scatterPiS_S_S_ii
	.globl	_Z46__device_stub__Z22hillisSteeleScanDevicePiiS_iPiiS_i
	.type	_Z46__device_stub__Z22hillisSteeleScanDevicePiiS_iPiiS_i, @function
_Z46__device_stub__Z22hillisSteeleScanDevicePiiS_iPiiS_i:
.LFB3669:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movl	%esi, 20(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 16(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L15
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z22hillisSteeleScanDevicePiiS_i(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L15:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L17
	call	__stack_chk_fail@PLT
.L17:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3669:
	.size	_Z46__device_stub__Z22hillisSteeleScanDevicePiiS_iPiiS_i, .-_Z46__device_stub__Z22hillisSteeleScanDevicePiiS_iPiiS_i
	.globl	_Z22hillisSteeleScanDevicePiiS_i
	.type	_Z22hillisSteeleScanDevicePiiS_i, @function
_Z22hillisSteeleScanDevicePiiS_i:
.LFB3670:
	.cfi_startproc
	endbr64
	jmp	_Z46__device_stub__Z22hillisSteeleScanDevicePiiS_iPiiS_i
	.cfi_endproc
.LFE3670:
	.size	_Z22hillisSteeleScanDevicePiiS_i, .-_Z22hillisSteeleScanDevicePiiS_i
	.globl	_Z20hillisSteeleScanHostPii
	.type	_Z20hillisSteeleScanHostPii, @function
_Z20hillisSteeleScanHostPii:
.LFB3636:
	.cfi_startproc
	endbr64
	pushq	%r14
	.cfi_def_cfa_offset 16
	.cfi_offset 14, -16
	pushq	%r13
	.cfi_def_cfa_offset 24
	.cfi_offset 13, -24
	xorl	%r13d, %r13d
	pushq	%r12
	.cfi_def_cfa_offset 32
	.cfi_offset 12, -32
	movq	%rdi, %r12
	pushq	%rbp
	.cfi_def_cfa_offset 40
	.cfi_offset 6, -40
	movslq	%esi, %rbp
	pushq	%rbx
	.cfi_def_cfa_offset 48
	.cfi_offset 3, -48
	movq	%rbp, %rbx
	salq	$2, %rbp
	movq	%rbp, %rsi
	subq	$48, %rsp
	.cfi_def_cfa_offset 96
	movq	%fs:40, %rax
	movq	%rax, 40(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rdi
	call	cudaMalloc@PLT
	movq	%rbp, %rsi
	movq	%rsp, %rdi
	call	cudaMalloc@PLT
	movq	8(%rsp), %rdi
	movq	%rbp, %rdx
	movq	%r12, %rsi
	movl	$3, %ecx
	movl	$1, %ebp
	movabsq	$4294967796, %r12
	call	cudaMemcpy@PLT
.L21:
	movl	%r13d, %r14d
	andl	$1, %r14d
	cmpl	%ebx, %ebp
	jge	.L32
	movl	$67108889, %edi
	movq	%r12, 28(%rsp)
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	salq	$6, %rdi
	movq	%r12, %rdx
	movl	$1, %ecx
	movl	$1, %esi
	movl	$1, 36(%rsp)
	movq	%rdi, 16(%rsp)
	movl	$1, 24(%rsp)
	testl	%r14d, %r14d
	jne	.L22
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L25
	movq	(%rsp), %rdx
	movq	8(%rsp), %rdi
	movl	%ebp, %ecx
	movl	%ebx, %esi
	jmp	.L31
.L22:
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L25
	movq	8(%rsp), %rdx
	movq	(%rsp), %rdi
	movl	%ebp, %ecx
	movl	%ebx, %esi
.L31:
	call	_Z46__device_stub__Z22hillisSteeleScanDevicePiiS_iPiiS_i
.L25:
	call	cudaDeviceSynchronize@PLT
	addl	%ebp, %ebp
	incl	%r13d
	jmp	.L21
.L32:
	call	cudaDeviceSynchronize@PLT
	movq	(%rsp), %rax
	testl	%r14d, %r14d
	jne	.L20
	movq	8(%rsp), %rax
.L20:
	movq	40(%rsp), %rdx
	subq	%fs:40, %rdx
	je	.L29
	call	__stack_chk_fail@PLT
.L29:
	addq	$48, %rsp
	.cfi_def_cfa_offset 48
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%rbp
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r13
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3636:
	.size	_Z20hillisSteeleScanHostPii, .-_Z20hillisSteeleScanHostPii
	.globl	_Z7compactPiii
	.type	_Z7compactPiii, @function
_Z7compactPiii:
.LFB3637:
	.cfi_startproc
	endbr64
	pushq	%r14
	.cfi_def_cfa_offset 16
	.cfi_offset 14, -16
	pushq	%r13
	.cfi_def_cfa_offset 24
	.cfi_offset 13, -24
	movl	%edx, %r13d
	pushq	%r12
	.cfi_def_cfa_offset 32
	.cfi_offset 12, -32
	movslq	%esi, %r12
	pushq	%rbp
	.cfi_def_cfa_offset 40
	.cfi_offset 6, -40
	movq	%rdi, %rbp
	pushq	%rbx
	.cfi_def_cfa_offset 48
	.cfi_offset 3, -48
	movq	%r12, %rbx
	salq	$2, %r12
	movq	%r12, %rsi
	subq	$64, %rsp
	.cfi_def_cfa_offset 112
	movq	%fs:40, %rax
	movq	%rax, 56(%rsp)
	xorl	%eax, %eax
	leaq	16(%rsp), %rdi
	call	cudaMalloc@PLT
	movl	$1073741949, %edx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$67108889, %edi
	salq	$2, %rdx
	movl	$1, %ecx
	movl	$1, %esi
	salq	$6, %rdi
	movq	%rdx, 44(%rsp)
	movl	$1, 52(%rsp)
	movq	%rdi, 32(%rsp)
	movl	$1, 40(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L34
	movq	16(%rsp), %rsi
	xorl	%r8d, %r8d
	movl	%r13d, %ecx
	movl	%ebx, %edx
	movq	%rbp, %rdi
	call	_Z40__device_stub__Z15predicateDevicePiS_iiiPiS_iii
.L34:
	movq	16(%rsp), %rdi
	movl	%ebx, %esi
	call	_Z20hillisSteeleScanHostPii
	leaq	24(%rsp), %rdi
	movq	%r12, %rsi
	movq	%rax, %r14
	call	cudaMalloc@PLT
	movl	$1073741949, %edx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$67108889, %edi
	salq	$2, %rdx
	movl	$1, %ecx
	movl	$1, %esi
	salq	$6, %rdi
	movq	%rdx, 44(%rsp)
	movl	$1, 52(%rsp)
	movq	%rdi, 32(%rsp)
	movl	$1, 40(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L35
	movq	24(%rsp), %rcx
	movq	16(%rsp), %rdx
	xorl	%r9d, %r9d
	movl	%ebx, %r8d
	movq	%r14, %rsi
	movq	%rbp, %rdi
	call	_Z34__device_stub__Z7scatterPiS_S_S_iiPiS_S_S_ii
.L35:
	leaq	-4(%r14,%r12), %rsi
	leaq	12(%rsp), %rdi
	movl	$2, %ecx
	movl	$4, %edx
	call	cudaMemcpy@PLT
	movl	$1073741949, %edx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$67108889, %edi
	salq	$2, %rdx
	movl	$1, %ecx
	movl	$1, %esi
	salq	$6, %rdi
	movq	%rdx, 44(%rsp)
	movl	$1, 52(%rsp)
	movq	%rdi, 32(%rsp)
	movl	$1, 40(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L36
	movq	16(%rsp), %rsi
	movl	$1, %r8d
	movl	%r13d, %ecx
	movl	%ebx, %edx
	movq	%rbp, %rdi
	call	_Z40__device_stub__Z15predicateDevicePiS_iiiPiS_iii
.L36:
	movq	16(%rsp), %rdi
	movl	%ebx, %esi
	call	_Z20hillisSteeleScanHostPii
	movl	$1073741949, %edx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$67108889, %edi
	salq	$2, %rdx
	movq	%rax, %r12
	movl	$1, %ecx
	salq	$6, %rdi
	movl	$1, %esi
	movq	%rdx, 44(%rsp)
	movl	$1, 52(%rsp)
	movq	%rdi, 32(%rsp)
	movl	$1, 40(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L37
	movl	12(%rsp), %r9d
	movq	24(%rsp), %rcx
	movl	%ebx, %r8d
	movq	%r12, %rsi
	movq	16(%rsp), %rdx
	movq	%rbp, %rdi
	call	_Z34__device_stub__Z7scatterPiS_S_S_iiPiS_S_S_ii
.L37:
	movq	24(%rsp), %rax
	movq	56(%rsp), %rdx
	subq	%fs:40, %rdx
	je	.L38
	call	__stack_chk_fail@PLT
.L38:
	addq	$64, %rsp
	.cfi_def_cfa_offset 48
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%rbp
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r13
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3637:
	.size	_Z7compactPiii, .-_Z7compactPiii
	.globl	_Z21positivenegativesplitPiiii
	.type	_Z21positivenegativesplitPiiii, @function
_Z21positivenegativesplitPiiii:
.LFB3638:
	.cfi_startproc
	endbr64
	pushq	%r14
	.cfi_def_cfa_offset 16
	.cfi_offset 14, -16
	movl	%ecx, %r14d
	pushq	%r13
	.cfi_def_cfa_offset 24
	.cfi_offset 13, -24
	movslq	%esi, %r13
	pushq	%r12
	.cfi_def_cfa_offset 32
	.cfi_offset 12, -32
	movl	%edx, %r12d
	pushq	%rbp
	.cfi_def_cfa_offset 40
	.cfi_offset 6, -40
	movq	%rdi, %rbp
	pushq	%rbx
	.cfi_def_cfa_offset 48
	.cfi_offset 3, -48
	movq	%r13, %rbx
	salq	$2, %r13
	movq	%r13, %rsi
	subq	$48, %rsp
	.cfi_def_cfa_offset 96
	movq	%fs:40, %rax
	movq	%rax, 40(%rsp)
	xorl	%eax, %eax
	movq	%rsp, %rdi
	call	cudaMalloc@PLT
	movl	$1073741949, %edx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$67108889, %edi
	salq	$2, %rdx
	movl	$1, %ecx
	movl	$1, %esi
	salq	$6, %rdi
	movq	%rdx, 28(%rsp)
	movl	$1, 36(%rsp)
	movq	%rdi, 16(%rsp)
	movl	$1, 24(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L41
	movq	(%rsp), %rsi
	movl	%r14d, %r8d
	movl	%r12d, %ecx
	movl	%ebx, %edx
	movq	%rbp, %rdi
	call	_Z40__device_stub__Z15predicateDevicePiS_iiiPiS_iii
.L41:
	movq	(%rsp), %rdi
	movl	%ebx, %esi
	call	_Z20hillisSteeleScanHostPii
	movl	$2, %ecx
	movl	$4, %edx
	leaq	offset(%rip), %rdi
	leaq	-4(%rax,%r13), %rsi
	movq	%rax, %r12
	call	cudaMemcpy@PLT
	movslq	offset(%rip), %rsi
	leaq	8(%rsp), %rdi
	salq	$2, %rsi
	call	cudaMalloc@PLT
	movl	$1073741949, %edx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$67108889, %edi
	salq	$2, %rdx
	movl	$1, %ecx
	movl	$1, %esi
	salq	$6, %rdi
	movq	%rdx, 28(%rsp)
	movl	$1, 36(%rsp)
	movq	%rdi, 16(%rsp)
	movl	$1, 24(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L42
	movq	8(%rsp), %rcx
	movq	(%rsp), %rdx
	xorl	%r9d, %r9d
	movl	%ebx, %r8d
	movq	%r12, %rsi
	movq	%rbp, %rdi
	call	_Z34__device_stub__Z7scatterPiS_S_S_iiPiS_S_S_ii
.L42:
	movq	8(%rsp), %rax
	movq	40(%rsp), %rdx
	subq	%fs:40, %rdx
	je	.L43
	call	__stack_chk_fail@PLT
.L43:
	addq	$48, %rsp
	.cfi_def_cfa_offset 48
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%rbp
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r13
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3638:
	.size	_Z21positivenegativesplitPiiii, .-_Z21positivenegativesplitPiiii
	.globl	_Z9radixSortPii
	.type	_Z9radixSortPii, @function
_Z9radixSortPii:
.LFB3639:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movl	$-2147483648, %edx
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	movl	$1, %r14d
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	xorl	%r12d, %r12d
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movq	%rdi, %rbp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movl	%esi, %ebx
	pushq	%rcx
	.cfi_def_cfa_offset 64
	movl	$1, %ecx
	call	_Z21positivenegativesplitPiiii
	movq	%rax, %r13
.L46:
	movl	%r12d, %ecx
	movl	offset(%rip), %esi
	movl	%r14d, %edx
	movq	%r13, %rdi
	sall	%cl, %edx
	incl	%r12d
	call	_Z7compactPiii
	movq	%rax, %r13
	cmpl	$32, %r12d
	jne	.L46
	xorl	%ecx, %ecx
	movl	$-2147483648, %edx
	movl	%ebx, %esi
	movq	%rbp, %rdi
	call	_Z21positivenegativesplitPiiii
	xorl	%r14d, %r14d
	movl	$1, %r15d
	movq	%rax, %r12
.L47:
	movl	%r14d, %ecx
	movl	offset(%rip), %esi
	movl	%r15d, %edx
	movq	%r12, %rdi
	sall	%cl, %edx
	incl	%r14d
	call	_Z7compactPiii
	movq	%rax, %r12
	cmpl	$32, %r14d
	jne	.L47
	movl	%ebx, %edx
	subl	offset(%rip), %edx
	movq	%r13, %rsi
	movq	%rbp, %rdi
	movslq	%edx, %rdx
	movl	$3, %ecx
	salq	$2, %rdx
	call	cudaMemcpy@PLT
	movslq	offset(%rip), %rdx
	movq	%r12, %rsi
	movl	$3, %ecx
	movq	%rdx, %rax
	salq	$2, %rdx
	subl	%eax, %ebx
	movslq	%ebx, %rbx
	leaq	0(%rbp,%rbx,4), %rdi
	call	cudaMemcpy@PLT
	popq	%rdx
	.cfi_def_cfa_offset 56
	movq	%rbp, %rax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3639:
	.size	_Z9radixSortPii, .-_Z9radixSortPii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"enter the number of elements \n"
.LC1:
	.string	"\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB3640:
	.cfi_startproc
	endbr64
	pushq	%r14
	.cfi_def_cfa_offset 16
	.cfi_offset 14, -16
	movl	$30, %edx
	leaq	.LC0(%rip), %rsi
	pushq	%r13
	.cfi_def_cfa_offset 24
	.cfi_offset 13, -24
	pushq	%r12
	.cfi_def_cfa_offset 32
	.cfi_offset 12, -32
	leaq	_ZSt4cout(%rip), %r12
	pushq	%rbp
	.cfi_def_cfa_offset 40
	.cfi_offset 6, -40
	movq	%r12, %rdi
	leaq	_ZSt3cin(%rip), %rbp
	pushq	%rbx
	.cfi_def_cfa_offset 48
	.cfi_offset 3, -48
	subq	$32, %rsp
	.cfi_def_cfa_offset 80
	movq	%fs:40, %rax
	movq	%rax, 24(%rsp)
	xorl	%eax, %eax
	call	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
	movq	%rbp, %rdi
	leaq	12(%rsp), %rsi
	call	_ZNSirsERi@PLT
	movslq	12(%rsp), %rdi
	movabsq	$2305843009213693950, %rax
	cmpq	%rdi, %rax
	jb	.L52
	salq	$2, %rdi
	xorl	%r13d, %r13d
	call	_Znam@PLT
	movq	%rax, %rbx
	movq	%rax, %r14
	jmp	.L53
.L52:
	movq	24(%rsp), %rax
	subq	%fs:40, %rax
	jne	.L60
	call	__cxa_throw_bad_array_new_length@PLT
.L53:
	movslq	12(%rsp), %rsi
	cmpl	%r13d, %esi
	jle	.L61
	movq	%r14, %rsi
	movq	%rbp, %rdi
	incl	%r13d
	addq	$4, %r14
	call	_ZNSirsERi@PLT
	jmp	.L53
.L61:
	salq	$2, %rsi
	leaq	16(%rsp), %rdi
	xorl	%ebp, %ebp
	call	cudaMalloc@PLT
	movslq	12(%rsp), %rdx
	movq	16(%rsp), %rdi
	movq	%rbx, %rsi
	movl	$1, %ecx
	leaq	.LC1(%rip), %r13
	salq	$2, %rdx
	call	cudaMemcpy@PLT
	movl	12(%rsp), %esi
	movq	16(%rsp), %rdi
	call	_Z9radixSortPii
	movslq	12(%rsp), %rdx
	movl	$2, %ecx
	movq	%rbx, %rdi
	movq	%rax, %rsi
	movq	%rax, 16(%rsp)
	salq	$2, %rdx
	call	cudaMemcpy@PLT
.L56:
	cmpl	%ebp, 12(%rsp)
	jle	.L62
	movl	(%rbx,%rbp,4), %esi
	movq	%r12, %rdi
	incq	%rbp
	call	_ZNSolsEi@PLT
	movl	$1, %edx
	movq	%r13, %rsi
	movq	%rax, %rdi
	call	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
	jmp	.L56
.L62:
	movq	24(%rsp), %rax
	subq	%fs:40, %rax
	je	.L58
.L60:
	call	__stack_chk_fail@PLT
.L58:
	addq	$32, %rsp
	.cfi_def_cfa_offset 48
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%rbp
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r13
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3640:
	.size	main, .-main
	.text
	.globl	_Z25__device_stub__Z5printPiiPii
	.type	_Z25__device_stub__Z5printPiiPii, @function
_Z25__device_stub__Z5printPiiPii:
.LFB3671:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 8(%rsp)
	leaq	32(%rsp), %rcx
	leaq	24(%rsp), %rdx
	movl	%esi, 4(%rsp)
	leaq	40(%rsp), %rdi
	leaq	52(%rsp), %rsi
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 48(%rsp)
	movq	%rax, 88(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L63
	pushq	32(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z5printPii(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 144
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	104(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L63:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L65
	call	__stack_chk_fail@PLT
.L65:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3671:
	.size	_Z25__device_stub__Z5printPiiPii, .-_Z25__device_stub__Z5printPiiPii
	.globl	_Z5printPii
	.type	_Z5printPii, @function
_Z5printPii:
.LFB3672:
	.cfi_startproc
	endbr64
	jmp	_Z25__device_stub__Z5printPiiPii
	.cfi_endproc
.LFE3672:
	.size	_Z5printPii, .-_Z5printPii
	.section	.rodata.str1.1
.LC2:
	.string	"_Z5printPii"
.LC3:
	.string	"_Z22hillisSteeleScanDevicePiiS_i"
.LC4:
	.string	"_Z7scatterPiS_S_S_ii"
.LC5:
	.string	"_Z15predicateDevicePiS_iii"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3674:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC2(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z5printPii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC3(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z22hillisSteeleScanDevicePiiS_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC4(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z7scatterPiS_S_S_ii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC5(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z15predicateDevicePiS_iii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3674:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.globl	offset
	.bss
	.align 4
	.type	offset, @object
	.size	offset, 4
offset:
	.zero	4
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

// richu shaji abraham richursa

#include <hip/hip_runtime.h>
#include<iostream>
#include<stdio.h>
using namespace std;
__device__ int function(int value , int bit ,int bitset)
{
    if(bitset == 1 )
    {
        if((value & bit)  != 0)
        {
            return 1;
        }
        else 
            return 0;
    }
    else
    {
        if((value & bit) == 0)
        {
            return 1;
        }
        else 
        {
            return 0;
        }
    }
}
__global__ void predicateDevice(int *d_array , int *d_predicateArrry , int d_numberOfElements,int bit,int bitset)
{
    int index = threadIdx.x + blockIdx.x*blockDim.x;
    if(index < d_numberOfElements)
    {
    
           d_predicateArrry[index] = function(d_array[index],bit,bitset);
    }
}

__global__ void scatter(int *d_array , int *d_scanArray , int *d_predicateArrry,int * d_scatteredArray ,int d_numberOfElements,int offset)
{
    int index = threadIdx.x + blockIdx.x * blockDim.x;
    if(index < d_numberOfElements)
    {
        if(d_predicateArrry[index] == 1)
        {
            d_scatteredArray[d_scanArray[index] - 1 +offset ] = d_array[index];
        
        }
    }
}
__global__ void hillisSteeleScanDevice(int *d_array , int numberOfElements, int *d_tmpArray,int moveIndex)
{
    int index = threadIdx.x + blockDim.x * blockIdx.x;
    if(index > numberOfElements)
    {
        return;
    }
    d_tmpArray[index] = d_array[index];
    if(index - moveIndex >=0)
    {
        
        d_tmpArray[index] = d_tmpArray[index] +d_array[index - moveIndex];
    }
}
int* hillisSteeleScanHost(int *d_scanArray,int numberOfElements)
{
    
    
    int *d_tmpArray;
    int *d_tmpArray1;
    hipMalloc(&d_tmpArray1,sizeof(int)*numberOfElements);
    hipMalloc(&d_tmpArray,sizeof(int)*numberOfElements);
    hipMemcpy(d_tmpArray1,d_scanArray,sizeof(int)*numberOfElements,hipMemcpyDeviceToDevice);
    int j,k=0;
    for(j=1;j<numberOfElements;j= j*2,k++)
    {
        if(k%2 == 0)
        {
            hillisSteeleScanDevice<<<1600,500>>>(d_tmpArray1,numberOfElements,d_tmpArray, j);
            hipDeviceSynchronize();
        }
        else
        {
            hillisSteeleScanDevice<<<1600,500>>>(d_tmpArray,numberOfElements,d_tmpArray1, j);
            hipDeviceSynchronize();
        }
    } 
    hipDeviceSynchronize();
    if(k%2 == 0)
    {
        
        return d_tmpArray1;
    }
    else
    {
        return d_tmpArray;
    }
}
__global__ void print(int *d_predicateArrry,int numberOfElements)
{
    
    for(int i=0;i<numberOfElements;i++)
    {
        printf("index = %d value = %d\n",i,d_predicateArrry[i]);
    }
}

int *compact(int *d_array,int numberOfElements,int bit)
{   
    int offset;
    int *d_predicateArrry;
    hipMalloc((void**)&d_predicateArrry,sizeof(int)*numberOfElements);
    predicateDevice<<<1600,500>>>(d_array,d_predicateArrry,numberOfElements,bit,0);
    int *d_scanArray;
    d_scanArray = hillisSteeleScanHost(d_predicateArrry,numberOfElements);
    int *d_scatteredArray;
    hipMalloc((void**)&d_scatteredArray,sizeof(int)*numberOfElements);
    //cout<<"offset = "<<offset<<"\n";
    scatter<<<1600,500>>>(d_array,d_scanArray,d_predicateArrry,d_scatteredArray, numberOfElements,0);
    hipMemcpy(&offset,d_scanArray+numberOfElements-1,sizeof(int),hipMemcpyDeviceToHost);
    predicateDevice<<<1600,500>>>(d_array,d_predicateArrry,numberOfElements,bit,1);
    d_scanArray = hillisSteeleScanHost(d_predicateArrry,numberOfElements);
    scatter<<<1600,500>>>(d_array,d_scanArray,d_predicateArrry,d_scatteredArray, numberOfElements,offset);
    return d_scatteredArray;
}
int offset;
int *positivenegativesplit(int *d_array,int numberOfElements,int bit,int bitset)
{   
    int *d_predicateArrry;
    hipMalloc((void**)&d_predicateArrry,sizeof(int)*numberOfElements);
    predicateDevice<<<1600,500>>>(d_array,d_predicateArrry,numberOfElements,bit,bitset);
    int *d_scanArray;
    d_scanArray = hillisSteeleScanHost(d_predicateArrry,numberOfElements);
    int *d_scatteredArray;
    hipMemcpy(&offset,d_scanArray+numberOfElements-1,sizeof(int),hipMemcpyDeviceToHost);
    hipMalloc((void**)&d_scatteredArray,sizeof(int)*offset);
    scatter<<<1600,500>>>(d_array,d_scanArray,d_predicateArrry,d_scatteredArray, numberOfElements,0);
    return d_scatteredArray;
}
int * radixSort(int *d_array , int numberOfElements)
{
    int bit;
    int *d_negativeArray = positivenegativesplit(d_array,numberOfElements,1L<<31,1);
    for(int i=0;i<sizeof(int)*8;i++)
    {
        bit = 1<<i;
        d_negativeArray = compact(d_negativeArray,offset,bit);
    }
    int *d_postiveArray = positivenegativesplit(d_array,numberOfElements,1L<<31,0);
    for(int i=0;i<sizeof(int)*8;i++)
    {
        bit = 1<<i;
        d_postiveArray = compact(d_postiveArray,offset,bit);
    }
    hipMemcpy(d_array,d_negativeArray,sizeof(int)*(numberOfElements-offset),hipMemcpyDeviceToDevice);
    hipMemcpy(d_array+(numberOfElements-offset),d_postiveArray,sizeof(int)*offset,hipMemcpyDeviceToDevice);
    return d_array;
}
int main()
{
    cout<<"enter the number of elements \n";
    int numberOfElements;
    cin>>numberOfElements;
    int *h_array  = new int[numberOfElements];
    for(int i=0;i<numberOfElements;i++)
    {
        cin>>h_array[i];
    }
    int *d_array;
    hipMalloc((void**)&d_array ,sizeof(int)*numberOfElements);
    hipMemcpy(d_array,h_array,sizeof(int)*numberOfElements,hipMemcpyHostToDevice);
    d_array = radixSort(d_array, numberOfElements);
    hipMemcpy(h_array,d_array,sizeof(int)*numberOfElements,hipMemcpyDeviceToHost);
    for(int i=0;i<numberOfElements;i++)
    {
        cout<<h_array[i]<<"\n";
    }
}

	.text
	.file	"radixSortCuda.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z30__device_stub__predicateDevicePiS_iii # -- Begin function _Z30__device_stub__predicateDevicePiS_iii
	.type	_Z30__device_stub__predicateDevicePiS_iii,@function
_Z30__device_stub__predicateDevicePiS_iii: # @_Z30__device_stub__predicateDevicePiS_iii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	4(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z15predicateDevicePiS_iii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z30__device_stub__predicateDevicePiS_iii, .Lfunc_end0-_Z30__device_stub__predicateDevicePiS_iii
	.cfi_endproc
                                        # -- End function
	.globl	_Z22__device_stub__scatterPiS_S_S_ii # -- Begin function _Z22__device_stub__scatterPiS_S_S_ii
	.type	_Z22__device_stub__scatterPiS_S_S_ii,@function
_Z22__device_stub__scatterPiS_S_S_ii:   # @_Z22__device_stub__scatterPiS_S_S_ii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	12(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	8(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7scatterPiS_S_S_ii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z22__device_stub__scatterPiS_S_S_ii, .Lfunc_end1-_Z22__device_stub__scatterPiS_S_S_ii
	.cfi_endproc
                                        # -- End function
	.globl	_Z37__device_stub__hillisSteeleScanDevicePiiS_i # -- Begin function _Z37__device_stub__hillisSteeleScanDevicePiiS_i
	.type	_Z37__device_stub__hillisSteeleScanDevicePiiS_i,@function
_Z37__device_stub__hillisSteeleScanDevicePiiS_i: # @_Z37__device_stub__hillisSteeleScanDevicePiiS_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	12(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	32(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z22hillisSteeleScanDevicePiiS_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z37__device_stub__hillisSteeleScanDevicePiiS_i, .Lfunc_end2-_Z37__device_stub__hillisSteeleScanDevicePiiS_i
	.cfi_endproc
                                        # -- End function
	.globl	_Z20hillisSteeleScanHostPii     # -- Begin function _Z20hillisSteeleScanHostPii
	.type	_Z20hillisSteeleScanHostPii,@function
_Z20hillisSteeleScanHostPii:            # @_Z20hillisSteeleScanHostPii
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$24, %rsp
	.cfi_def_cfa_offset 80
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%esi, %ebp
	movq	%rdi, %r15
	movslq	%esi, %r14
	leaq	(,%r14,4), %r12
	leaq	8(%rsp), %rbx
	movq	%rbx, %rdi
	movq	%r12, %rsi
	callq	hipMalloc
	leaq	16(%rsp), %rdi
	movq	%r12, %rsi
	callq	hipMalloc
	movq	(%rbx), %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movl	$3, %ecx
	callq	hipMemcpy
	cmpl	$2, %r14d
	jl	.LBB3_11
# %bb.1:                                # %.lr.ph.preheader
	movl	$1, %r15d
	movl	$-1, %r14d
	movabsq	$4294967796, %r12               # imm = 0x1000001F4
	leaq	1100(%r12), %r13
.LBB3_2:                                # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	leal	1(%r14), %ebx
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testb	$1, %bl
	jne	.LBB3_5
# %bb.3:                                #   in Loop: Header=BB3_2 Depth=1
	testl	%eax, %eax
	jne	.LBB3_8
# %bb.4:                                #   in Loop: Header=BB3_2 Depth=1
	movq	8(%rsp), %rdi
	movq	16(%rsp), %rdx
	jmp	.LBB3_7
.LBB3_5:                                #   in Loop: Header=BB3_2 Depth=1
	testl	%eax, %eax
	jne	.LBB3_8
# %bb.6:                                #   in Loop: Header=BB3_2 Depth=1
	movq	16(%rsp), %rdi
	movq	8(%rsp), %rdx
.LBB3_7:                                #   in Loop: Header=BB3_2 Depth=1
	movl	%ebp, %esi
	movl	%r15d, %ecx
	callq	_Z37__device_stub__hillisSteeleScanDevicePiiS_i
.LBB3_8:                                #   in Loop: Header=BB3_2 Depth=1
	callq	hipDeviceSynchronize
	addl	%r15d, %r15d
	incl	%r14d
	cmpl	%ebp, %r15d
	jl	.LBB3_2
# %bb.9:                                # %._crit_edge
	callq	hipDeviceSynchronize
	testb	$1, %r14b
	leaq	8(%rsp), %rax
	leaq	16(%rsp), %rcx
	cmoveq	%rcx, %rax
	movq	(%rax), %rax
	jmp	.LBB3_10
.LBB3_11:                               # %._crit_edge.thread
	callq	hipDeviceSynchronize
	movq	8(%rsp), %rax
.LBB3_10:
	addq	$24, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	_Z20hillisSteeleScanHostPii, .Lfunc_end3-_Z20hillisSteeleScanHostPii
	.cfi_endproc
                                        # -- End function
	.globl	_Z20__device_stub__printPii     # -- Begin function _Z20__device_stub__printPii
	.type	_Z20__device_stub__printPii,@function
_Z20__device_stub__printPii:            # @_Z20__device_stub__printPii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	4(%rsp), %rcx
	movl	%esi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z5printPii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end4:
	.size	_Z20__device_stub__printPii, .Lfunc_end4-_Z20__device_stub__printPii
	.cfi_endproc
                                        # -- End function
	.globl	_Z7compactPiii                  # -- Begin function _Z7compactPiii
	.type	_Z7compactPiii,@function
_Z7compactPiii:                         # @_Z7compactPiii
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$40, %rsp
	.cfi_def_cfa_offset 96
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%edx, %ebp
	movl	%esi, %ebx
	movq	%rdi, 16(%rsp)                  # 8-byte Spill
	movabsq	$4294967796, %r15               # imm = 0x1000001F4
	movslq	%esi, %r14
	leaq	(,%r14,4), %r13
	leaq	8(%rsp), %rdi
	movq	%r13, %rsi
	callq	hipMalloc
	leaq	1100(%r15), %r12
	movq	%r12, %rdi
	movl	$1, %esi
	movq	%r15, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB5_2
# %bb.1:
	movq	8(%rsp), %rsi
	movq	16(%rsp), %rdi                  # 8-byte Reload
	movl	%ebx, %edx
	movl	%ebp, %ecx
	xorl	%r8d, %r8d
	callq	_Z30__device_stub__predicateDevicePiS_iii
.LBB5_2:
	movl	%ebp, 32(%rsp)                  # 4-byte Spill
	movq	8(%rsp), %rdi
	movl	%ebx, %esi
	callq	_Z20hillisSteeleScanHostPii
	movq	%rax, %rbp
	leaq	24(%rsp), %rdi
	movq	%r13, %rsi
	callq	hipMalloc
	movq	%r12, %rdi
	movl	$1, %esi
	movq	%r15, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB5_4
# %bb.3:
	movq	8(%rsp), %rdx
	movq	24(%rsp), %rcx
	movq	16(%rsp), %rdi                  # 8-byte Reload
	movq	%rbp, %rsi
	movl	%ebx, %r8d
	xorl	%r9d, %r9d
	callq	_Z22__device_stub__scatterPiS_S_S_ii
.LBB5_4:
	leaq	-4(,%r14,4), %rsi
	addq	%rbp, %rsi
	leaq	36(%rsp), %rdi
	movl	$4, %edx
	movl	$2, %ecx
	callq	hipMemcpy
	movq	%r12, %rdi
	movl	$1, %esi
	movq	%r15, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB5_6
# %bb.5:
	movq	8(%rsp), %rsi
	movq	16(%rsp), %rdi                  # 8-byte Reload
	movl	%ebx, %edx
	movl	32(%rsp), %ecx                  # 4-byte Reload
	movl	$1, %r8d
	callq	_Z30__device_stub__predicateDevicePiS_iii
.LBB5_6:
	movq	8(%rsp), %rdi
	movl	%ebx, %esi
	callq	_Z20hillisSteeleScanHostPii
	movq	%rax, %r13
	movq	%r12, %rdi
	movl	$1, %esi
	movq	%r15, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB5_8
# %bb.7:
	movq	8(%rsp), %rdx
	movq	24(%rsp), %rcx
	movl	36(%rsp), %r9d
	movq	16(%rsp), %rdi                  # 8-byte Reload
	movq	%r13, %rsi
	movl	%ebx, %r8d
	callq	_Z22__device_stub__scatterPiS_S_S_ii
.LBB5_8:
	movq	24(%rsp), %rax
	addq	$40, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end5:
	.size	_Z7compactPiii, .Lfunc_end5-_Z7compactPiii
	.cfi_endproc
                                        # -- End function
	.globl	_Z21positivenegativesplitPiiii  # -- Begin function _Z21positivenegativesplitPiiii
	.type	_Z21positivenegativesplitPiiii,@function
_Z21positivenegativesplitPiiii:         # @_Z21positivenegativesplitPiiii
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$24, %rsp
	.cfi_def_cfa_offset 80
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%ecx, %ebp
	movl	%edx, %r13d
	movl	%esi, %ebx
	movq	%rdi, 8(%rsp)                   # 8-byte Spill
	movabsq	$4294967796, %r15               # imm = 0x1000001F4
	movslq	%esi, %r14
	leaq	(,%r14,4), %rsi
	movq	%rsp, %rdi
	callq	hipMalloc
	leaq	1100(%r15), %r12
	movq	%r12, %rdi
	movl	$1, %esi
	movq	%r15, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB6_2
# %bb.1:
	movq	(%rsp), %rsi
	movq	8(%rsp), %rdi                   # 8-byte Reload
	movl	%ebx, %edx
	movl	%r13d, %ecx
	movl	%ebp, %r8d
	callq	_Z30__device_stub__predicateDevicePiS_iii
.LBB6_2:
	movq	(%rsp), %rdi
	movl	%ebx, %esi
	callq	_Z20hillisSteeleScanHostPii
	movq	%rax, %r13
	leaq	(%rax,%r14,4), %rsi
	addq	$-4, %rsi
	movl	$offset, %edi
	movl	$4, %edx
	movl	$2, %ecx
	callq	hipMemcpy
	movslq	offset(%rip), %rsi
	shlq	$2, %rsi
	leaq	16(%rsp), %rdi
	callq	hipMalloc
	movq	%r12, %rdi
	movl	$1, %esi
	movq	%r15, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB6_4
# %bb.3:
	movq	(%rsp), %rdx
	movq	16(%rsp), %rcx
	movq	8(%rsp), %rdi                   # 8-byte Reload
	movq	%r13, %rsi
	movl	%ebx, %r8d
	xorl	%r9d, %r9d
	callq	_Z22__device_stub__scatterPiS_S_S_ii
.LBB6_4:
	movq	16(%rsp), %rax
	addq	$24, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end6:
	.size	_Z21positivenegativesplitPiiii, .Lfunc_end6-_Z21positivenegativesplitPiiii
	.cfi_endproc
                                        # -- End function
	.globl	_Z9radixSortPii                 # -- Begin function _Z9radixSortPii
	.type	_Z9radixSortPii,@function
_Z9radixSortPii:                        # @_Z9radixSortPii
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%esi, %ebp
	movq	%rdi, %rbx
	movl	$-2147483648, %edx              # imm = 0x80000000
	movl	$1, %ecx
	callq	_Z21positivenegativesplitPiiii
	movq	%rax, %r14
	xorl	%r15d, %r15d
.LBB7_1:                                # =>This Inner Loop Header: Depth=1
	movl	$1, %edx
	movl	%r15d, %ecx
	shll	%cl, %edx
	movl	offset(%rip), %esi
	movq	%r14, %rdi
	callq	_Z7compactPiii
	movq	%rax, %r14
	incl	%r15d
	cmpl	$32, %r15d
	jne	.LBB7_1
# %bb.2:
	xorl	%r12d, %r12d
	movq	%rbx, %rdi
	movl	%ebp, %esi
	movl	$-2147483648, %edx              # imm = 0x80000000
	xorl	%ecx, %ecx
	callq	_Z21positivenegativesplitPiiii
	movq	%rax, %r15
.LBB7_3:                                # =>This Inner Loop Header: Depth=1
	movl	$1, %edx
	movl	%r12d, %ecx
	shll	%cl, %edx
	movl	offset(%rip), %esi
	movq	%r15, %rdi
	callq	_Z7compactPiii
	movq	%rax, %r15
	incl	%r12d
	cmpl	$32, %r12d
	jne	.LBB7_3
# %bb.4:
	movslq	offset(%rip), %rax
	movslq	%ebp, %r12
	movq	%r12, %rdx
	subq	%rax, %rdx
	shlq	$2, %rdx
	movq	%rbx, %rdi
	movq	%r14, %rsi
	movl	$3, %ecx
	callq	hipMemcpy
	movslq	offset(%rip), %rdx
	subq	%rdx, %r12
	leaq	(%rbx,%r12,4), %rdi
	shlq	$2, %rdx
	movq	%r15, %rsi
	movl	$3, %ecx
	callq	hipMemcpy
	movq	%rbx, %rax
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end7:
	.size	_Z9radixSortPii, .Lfunc_end7-_Z9radixSortPii
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r12
	.cfi_def_cfa_offset 32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	subq	$24, %rsp
	.cfi_def_cfa_offset 64
	.cfi_offset %rbx, -40
	.cfi_offset %r12, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movl	$_ZSt4cout, %edi
	movl	$.L.str, %esi
	movl	$30, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	leaq	12(%rsp), %rbx
	movl	$_ZSt3cin, %edi
	movq	%rbx, %rsi
	callq	_ZNSirsERi
	movslq	(%rbx), %r15
	leaq	(,%r15,4), %r14
	testq	%r15, %r15
	movq	$-1, %rdi
	cmovnsq	%r14, %rdi
	callq	_Znam
	movq	%rax, %rbx
	testq	%r15, %r15
	jle	.LBB8_4
# %bb.1:                                # %.lr.ph.preheader
	xorl	%r12d, %r12d
	movq	%rbx, %r15
.LBB8_2:                                # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	movl	$_ZSt3cin, %edi
	movq	%r15, %rsi
	callq	_ZNSirsERi
	incq	%r12
	movslq	12(%rsp), %r14
	addq	$4, %r15
	cmpq	%r14, %r12
	jl	.LBB8_2
# %bb.3:                                # %._crit_edge.loopexit
	shlq	$2, %r14
.LBB8_4:                                # %._crit_edge
	leaq	16(%rsp), %r15
	movq	%r15, %rdi
	movq	%r14, %rsi
	callq	hipMalloc
	movq	(%r15), %rdi
	movslq	12(%rsp), %rdx
	shlq	$2, %rdx
	movq	%rbx, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%r15), %r14
	movl	12(%rsp), %esi
	movq	%r14, %rdi
	callq	_Z9radixSortPii
	movq	%r14, (%r15)
	movslq	12(%rsp), %rdx
	shlq	$2, %rdx
	movq	%rbx, %rdi
	movq	%r14, %rsi
	movl	$2, %ecx
	callq	hipMemcpy
	cmpl	$0, 12(%rsp)
	jle	.LBB8_7
# %bb.5:                                # %.lr.ph14.preheader
	xorl	%r14d, %r14d
.LBB8_6:                                # %.lr.ph14
                                        # =>This Inner Loop Header: Depth=1
	movl	(%rbx,%r14,4), %esi
	movl	$_ZSt4cout, %edi
	callq	_ZNSolsEi
	movl	$.L.str.1, %esi
	movl	$1, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	incq	%r14
	movslq	12(%rsp), %rax
	cmpq	%rax, %r14
	jl	.LBB8_6
.LBB8_7:                                # %._crit_edge15
	xorl	%eax, %eax
	addq	$24, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end8:
	.size	main, .Lfunc_end8-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB9_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB9_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z15predicateDevicePiS_iii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z7scatterPiS_S_S_ii, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z22hillisSteeleScanDevicePiiS_i, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z5printPii, %esi
	movl	$.L__unnamed_4, %edx
	movl	$.L__unnamed_4, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end9:
	.size	__hip_module_ctor, .Lfunc_end9-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB10_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB10_2:
	retq
.Lfunc_end10:
	.size	__hip_module_dtor, .Lfunc_end10-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z15predicateDevicePiS_iii,@object # @_Z15predicateDevicePiS_iii
	.section	.rodata,"a",@progbits
	.globl	_Z15predicateDevicePiS_iii
	.p2align	3, 0x0
_Z15predicateDevicePiS_iii:
	.quad	_Z30__device_stub__predicateDevicePiS_iii
	.size	_Z15predicateDevicePiS_iii, 8

	.type	_Z7scatterPiS_S_S_ii,@object    # @_Z7scatterPiS_S_S_ii
	.globl	_Z7scatterPiS_S_S_ii
	.p2align	3, 0x0
_Z7scatterPiS_S_S_ii:
	.quad	_Z22__device_stub__scatterPiS_S_S_ii
	.size	_Z7scatterPiS_S_S_ii, 8

	.type	_Z22hillisSteeleScanDevicePiiS_i,@object # @_Z22hillisSteeleScanDevicePiiS_i
	.globl	_Z22hillisSteeleScanDevicePiiS_i
	.p2align	3, 0x0
_Z22hillisSteeleScanDevicePiiS_i:
	.quad	_Z37__device_stub__hillisSteeleScanDevicePiiS_i
	.size	_Z22hillisSteeleScanDevicePiiS_i, 8

	.type	_Z5printPii,@object             # @_Z5printPii
	.globl	_Z5printPii
	.p2align	3, 0x0
_Z5printPii:
	.quad	_Z20__device_stub__printPii
	.size	_Z5printPii, 8

	.type	offset,@object                  # @offset
	.bss
	.globl	offset
	.p2align	2, 0x0
offset:
	.long	0                               # 0x0
	.size	offset, 4

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"enter the number of elements \n"
	.size	.L.str, 31

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"\n"
	.size	.L.str.1, 2

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z15predicateDevicePiS_iii"
	.size	.L__unnamed_1, 27

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z7scatterPiS_S_S_ii"
	.size	.L__unnamed_2, 21

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z22hillisSteeleScanDevicePiiS_i"
	.size	.L__unnamed_3, 33

	.type	.L__unnamed_4,@object           # @3
.L__unnamed_4:
	.asciz	"_Z5printPii"
	.size	.L__unnamed_4, 12

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z30__device_stub__predicateDevicePiS_iii
	.addrsig_sym _Z22__device_stub__scatterPiS_S_S_ii
	.addrsig_sym _Z37__device_stub__hillisSteeleScanDevicePiiS_i
	.addrsig_sym _Z20__device_stub__printPii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z15predicateDevicePiS_iii
	.addrsig_sym _Z7scatterPiS_S_S_ii
	.addrsig_sym _Z22hillisSteeleScanDevicePiiS_i
	.addrsig_sym _Z5printPii
	.addrsig_sym offset
	.addrsig_sym _ZSt4cout
	.addrsig_sym _ZSt3cin
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z15predicateDevicePiS_iii ; -- Begin function _Z15predicateDevicePiS_iii
	.globl	_Z15predicateDevicePiS_iii
	.p2align	8
	.type	_Z15predicateDevicePiS_iii,@function
_Z15predicateDevicePiS_iii:             ; @_Z15predicateDevicePiS_iii
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x2c
	s_load_b128 s[4:7], s[0:1], 0x10
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_i32_e64 s4, v1
	s_cbranch_execz .LBB0_2
; %bb.1:
	s_load_b128 s[0:3], s[0:1], 0x0
	v_ashrrev_i32_e32 v2, 31, v1
	s_cmp_eq_u32 s6, 1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v2, vcc_lo, s0, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
	global_load_b32 v2, v[2:3], off
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v2, s5, v2
	v_cmp_ne_u32_e32 vcc_lo, 0, v2
	v_cndmask_b32_e64 v3, 0, 1, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 0, v2
	v_cndmask_b32_e64 v2, 0, 1, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v2, v2, v3, vcc_lo
	v_add_co_u32 v0, vcc_lo, s2, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
	v_and_b32_e32 v2, 1, v2
	global_store_b32 v[0:1], v2, off
.LBB0_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z15predicateDevicePiS_iii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 4
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z15predicateDevicePiS_iii, .Lfunc_end0-_Z15predicateDevicePiS_iii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 196
; NumSgprs: 18
; NumVgprs: 4
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 4
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z7scatterPiS_S_S_ii    ; -- Begin function _Z7scatterPiS_S_S_ii
	.globl	_Z7scatterPiS_S_S_ii
	.p2align	8
	.type	_Z7scatterPiS_S_S_ii,@function
_Z7scatterPiS_S_S_ii:                   ; @_Z7scatterPiS_S_S_ii
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x34
	s_load_b64 s[8:9], s[0:1], 0x20
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_i32_e64 s8, v1
	s_cbranch_execz .LBB1_3
; %bb.1:
	s_load_b256 s[0:7], s[0:1], 0x0
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v2, vcc_lo, s4, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
	global_load_b32 v2, v[2:3], off
	s_waitcnt vmcnt(0)
	v_cmp_eq_u32_e32 vcc_lo, 1, v2
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB1_3
; %bb.2:
	v_add_co_u32 v2, vcc_lo, s2, v0
	v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
	v_add_co_u32 v0, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	global_load_b32 v2, v[2:3], off
	global_load_b32 v3, v[0:1], off
	s_waitcnt vmcnt(1)
	v_add3_u32 v0, s9, -1, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v1, 31, v0
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s6, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b32 v[0:1], v3, off
.LBB1_3:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7scatterPiS_S_S_ii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 4
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z7scatterPiS_S_S_ii, .Lfunc_end1-_Z7scatterPiS_S_S_ii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 236
; NumSgprs: 18
; NumVgprs: 4
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 4
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z22hillisSteeleScanDevicePiiS_i ; -- Begin function _Z22hillisSteeleScanDevicePiiS_i
	.globl	_Z22hillisSteeleScanDevicePiiS_i
	.p2align	8
	.type	_Z22hillisSteeleScanDevicePiiS_i,@function
_Z22hillisSteeleScanDevicePiiS_i:       ; @_Z22hillisSteeleScanDevicePiiS_i
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x2c
	s_load_b32 s3, s[0:1], 0x8
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_cmpx_ge_i32_e64 s3, v1
	s_cbranch_execz .LBB2_3
; %bb.1:
	s_load_b64 s[2:3], s[0:1], 0x0
	v_ashrrev_i32_e32 v2, 31, v1
	s_clause 0x1
	s_load_b64 s[4:5], s[0:1], 0x10
	s_load_b32 s0, s[0:1], 0x18
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[5:6], 2, v[1:2]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v2, vcc_lo, s2, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s3, v6, vcc_lo
	v_add_co_u32 v0, vcc_lo, s4, v5
	global_load_b32 v4, v[2:3], off
	v_subrev_nc_u32_e32 v2, s0, v1
	v_add_co_ci_u32_e32 v1, vcc_lo, s5, v6, vcc_lo
	v_cmp_lt_i32_e32 vcc_lo, -1, v2
	s_waitcnt vmcnt(0)
	global_store_b32 v[0:1], v4, off
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB2_3
; %bb.2:
	v_mov_b32_e32 v3, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	v_add_co_u32 v2, vcc_lo, s2, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
	global_load_b32 v2, v[2:3], off
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v2, v2, v4
	global_store_b32 v[0:1], v2, off
.LBB2_3:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z22hillisSteeleScanDevicePiiS_i
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 7
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_Z22hillisSteeleScanDevicePiiS_i, .Lfunc_end2-_Z22hillisSteeleScanDevicePiiS_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 240
; NumSgprs: 18
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z5printPii             ; -- Begin function _Z5printPii
	.globl	_Z5printPii
	.p2align	8
	.type	_Z5printPii,@function
_Z5printPii:                            ; @_Z5printPii
; %bb.0:
	s_load_b32 s18, s[0:1], 0x8
	s_waitcnt lgkmcnt(0)
	s_cmp_lt_i32 s18, 1
	s_cbranch_scc1 .LBB3_201
; %bb.1:                                ; %.lr.ph
	s_clause 0x1
	s_load_b64 s[2:3], s[0:1], 0x0
	s_load_b64 s[4:5], s[0:1], 0x60
	v_mbcnt_lo_u32_b32 v32, -1, 0
	v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v5, 2
	v_mov_b32_e32 v0, 33
	v_mov_b32_e32 v6, 1
	s_mov_b32 s7, 0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s6, s7
.LBB3_2:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB3_5 Depth 2
                                        ;     Child Loop BB3_13 Depth 2
                                        ;     Child Loop BB3_19 Depth 2
                                        ;     Child Loop BB3_28 Depth 2
                                        ;     Child Loop BB3_31 Depth 2
                                        ;       Child Loop BB3_34 Depth 3
                                        ;       Child Loop BB3_42 Depth 3
                                        ;       Child Loop BB3_50 Depth 3
                                        ;       Child Loop BB3_58 Depth 3
                                        ;       Child Loop BB3_66 Depth 3
                                        ;       Child Loop BB3_74 Depth 3
                                        ;       Child Loop BB3_82 Depth 3
                                        ;       Child Loop BB3_90 Depth 3
                                        ;       Child Loop BB3_98 Depth 3
                                        ;       Child Loop BB3_104 Depth 3
                                        ;       Child Loop BB3_113 Depth 3
                                        ;     Child Loop BB3_121 Depth 2
                                        ;     Child Loop BB3_129 Depth 2
                                        ;     Child Loop BB3_135 Depth 2
                                        ;     Child Loop BB3_144 Depth 2
                                        ;     Child Loop BB3_149 Depth 2
                                        ;     Child Loop BB3_157 Depth 2
                                        ;     Child Loop BB3_163 Depth 2
                                        ;     Child Loop BB3_172 Depth 2
                                        ;     Child Loop BB3_176 Depth 2
                                        ;     Child Loop BB3_184 Depth 2
                                        ;     Child Loop BB3_190 Depth 2
                                        ;     Child Loop BB3_199 Depth 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_lshl_b64 s[0:1], s[6:7], 2
	v_mov_b32_e32 v1, v32
	s_waitcnt lgkmcnt(0)
	s_add_u32 s0, s2, s0
	s_addc_u32 s1, s3, s1
	v_mov_b32_e32 v3, 0
	v_mov_b32_e32 v4, 0
	global_load_b32 v9, v2, s[0:1]
	;;#ASMSTART
	;;#ASMEND
	v_readfirstlane_b32 s0, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_eq_u32_e64 s0, s0, v1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB3_8
; %bb.3:                                ;   in Loop: Header=BB3_2 Depth=1
	global_load_b64 v[12:13], v2, s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[3:4], v2, s[4:5] offset:40
	global_load_b64 v[7:8], v2, s[4:5]
	s_mov_b32 s8, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v4, v4, v13
	v_and_b32_e32 v3, v3, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v4, v4, 24
	v_mul_hi_u32 v10, v3, 24
	v_mul_lo_u32 v3, v3, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v4, v10, v4
	s_waitcnt vmcnt(0)
	v_add_co_u32 v3, vcc_lo, v7, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, v8, v4, vcc_lo
	global_load_b64 v[10:11], v[3:4], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[3:4], v2, v[10:13], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[3:4], v[12:13]
	s_cbranch_execz .LBB3_7
; %bb.4:                                ; %.preheader3.i.i.i.preheader
                                        ;   in Loop: Header=BB3_2 Depth=1
	s_mov_b32 s9, 0
.LBB3_5:                                ; %.preheader3.i.i.i
                                        ;   Parent Loop BB3_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[7:8], v2, s[4:5] offset:40
	global_load_b64 v[10:11], v2, s[4:5]
	v_dual_mov_b32 v13, v4 :: v_dual_mov_b32 v12, v3
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v7, v7, v12
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[3:4], null, v7, 24, v[10:11]
	v_and_b32_e32 v10, v8, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[7:8], null, v10, 24, v[4:5]
	v_mov_b32_e32 v4, v7
	global_load_b64 v[10:11], v[3:4], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[3:4], v2, v[10:13], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[3:4], v[12:13]
	s_or_b32 s9, vcc_lo, s9
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s9
	s_cbranch_execnz .LBB3_5
; %bb.6:                                ; %Flow411
                                        ;   in Loop: Header=BB3_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s9
.LBB3_7:                                ; %Flow413
                                        ;   in Loop: Header=BB3_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s8
.LBB3_8:                                ; %.loopexit4.i.i.i
                                        ;   in Loop: Header=BB3_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_clause 0x1
	global_load_b64 v[7:8], v2, s[4:5] offset:40
	global_load_b128 v[10:13], v2, s[4:5]
	v_readfirstlane_b32 s8, v3
	v_readfirstlane_b32 s9, v4
	s_mov_b32 s14, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s10, v7
	v_readfirstlane_b32 s11, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[10:11], s[8:9], s[10:11]
	s_mul_i32 s1, s11, 24
	s_mul_hi_u32 s12, s10, 24
	s_mul_i32 s13, s10, 24
	s_and_saveexec_b32 s15, s0
	s_cbranch_execz .LBB3_10
; %bb.9:                                ;   in Loop: Header=BB3_2 Depth=1
	v_dual_mov_b32 v3, s14 :: v_dual_mov_b32 v4, v2
	s_add_i32 s14, s12, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v7, vcc_lo, v10, s13
	v_add_co_ci_u32_e32 v8, vcc_lo, s14, v11, vcc_lo
	global_store_b128 v[7:8], v[3:6], off offset:8
.LBB3_10:                               ;   in Loop: Header=BB3_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s15
	s_lshl_b64 s[10:11], s[10:11], 12
	v_lshlrev_b64 v[3:4], 6, v[1:2]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v1, vcc_lo, v12, s10
	v_add_co_ci_u32_e32 v8, vcc_lo, s11, v13, vcc_lo
	s_mov_b32 s20, s7
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v7, vcc_lo, v1, v3
	s_mov_b32 s21, s7
	s_mov_b32 s22, s7
	s_mov_b32 s23, s7
	v_add_co_ci_u32_e32 v8, vcc_lo, v8, v4, vcc_lo
	v_dual_mov_b32 v1, v2 :: v_dual_mov_b32 v12, s20
	v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v14, s22
	v_mov_b32_e32 v13, s21
	v_mov_b32_e32 v15, s23
	s_clause 0x3
	global_store_b128 v[7:8], v[0:3], off
	global_store_b128 v[7:8], v[12:15], off offset:16
	global_store_b128 v[7:8], v[12:15], off offset:32
	global_store_b128 v[7:8], v[12:15], off offset:48
	s_and_saveexec_b32 s10, s0
	s_cbranch_execz .LBB3_18
; %bb.11:                               ;   in Loop: Header=BB3_2 Depth=1
	s_clause 0x1
	global_load_b64 v[16:17], v2, s[4:5] offset:32 glc
	global_load_b64 v[3:4], v2, s[4:5] offset:40
	v_dual_mov_b32 v14, s8 :: v_dual_mov_b32 v15, s9
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s14, v3
	v_readfirstlane_b32 s15, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[14:15], s[14:15], s[8:9]
	s_mul_i32 s11, s15, 24
	s_mul_hi_u32 s15, s14, 24
	s_mul_i32 s14, s14, 24
	s_add_i32 s15, s15, s11
	v_add_co_u32 v3, vcc_lo, v10, s14
	v_add_co_ci_u32_e32 v4, vcc_lo, s15, v11, vcc_lo
	s_mov_b32 s11, exec_lo
	global_store_b64 v[3:4], v[16:17], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[14:15], v2, v[14:17], s[4:5] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[14:15], v[16:17]
	s_cbranch_execz .LBB3_14
; %bb.12:                               ; %.preheader1.i.i.i.preheader
                                        ;   in Loop: Header=BB3_2 Depth=1
	s_mov_b32 s14, 0
.LBB3_13:                               ; %.preheader1.i.i.i
                                        ;   Parent Loop BB3_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_dual_mov_b32 v12, s8 :: v_dual_mov_b32 v13, s9
	s_sleep 1
	global_store_b64 v[3:4], v[14:15], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[12:13], v2, v[12:15], s[4:5] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[12:13], v[14:15]
	v_dual_mov_b32 v15, v13 :: v_dual_mov_b32 v14, v12
	s_or_b32 s14, vcc_lo, s14
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s14
	s_cbranch_execnz .LBB3_13
.LBB3_14:                               ; %Flow409
                                        ;   in Loop: Header=BB3_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s11
	global_load_b64 v[3:4], v2, s[4:5] offset:16
	s_mov_b32 s14, exec_lo
	s_mov_b32 s11, exec_lo
	v_mbcnt_lo_u32_b32 v1, s14, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v1
	s_cbranch_execz .LBB3_16
; %bb.15:                               ;   in Loop: Header=BB3_2 Depth=1
	s_bcnt1_i32_b32 s14, s14
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v1, s14
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[3:4], v[1:2], off offset:8
.LBB3_16:                               ;   in Loop: Header=BB3_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s11
	s_waitcnt vmcnt(0)
	global_load_b64 v[12:13], v[3:4], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[12:13]
	s_cbranch_vccnz .LBB3_18
; %bb.17:                               ;   in Loop: Header=BB3_2 Depth=1
	global_load_b32 v1, v[3:4], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s11, v1
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[12:13], v[1:2], off
	s_and_b32 m0, s11, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB3_18:                               ; %Flow410
                                        ;   in Loop: Header=BB3_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
	s_add_i32 s12, s12, s1
	v_add_co_u32 v1, vcc_lo, v10, s13
	v_add_co_ci_u32_e32 v4, vcc_lo, s12, v11, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, v1, 20
	v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
.LBB3_19:                               ;   Parent Loop BB3_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_mov_b32_e32 v1, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB3_21
; %bb.20:                               ;   in Loop: Header=BB3_19 Depth=2
	global_load_b32 v1, v[3:4], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v1, 1, v1
.LBB3_21:                               ;   in Loop: Header=BB3_19 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v1
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB3_23
; %bb.22:                               ;   in Loop: Header=BB3_19 Depth=2
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB3_24
.LBB3_23:                               ;   in Loop: Header=BB3_19 Depth=2
	s_mov_b32 s1, -1
.LBB3_24:                               ; %Flow404
                                        ;   in Loop: Header=BB3_19 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB3_19
; %bb.25:                               ;   in Loop: Header=BB3_2 Depth=1
	global_load_b64 v[10:11], v[7:8], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB3_29
; %bb.26:                               ;   in Loop: Header=BB3_2 Depth=1
	s_clause 0x2
	global_load_b64 v[3:4], v2, s[4:5] offset:40
	global_load_b64 v[7:8], v2, s[4:5] offset:24 glc
	global_load_b64 v[14:15], v2, s[4:5]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v1, vcc_lo, v3, 1
	v_add_co_ci_u32_e32 v16, vcc_lo, 0, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v12, vcc_lo, v1, s8
	v_add_co_ci_u32_e32 v13, vcc_lo, s9, v16, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[12:13]
	v_dual_cndmask_b32 v13, v13, v16 :: v_dual_cndmask_b32 v12, v12, v1
	v_and_b32_e32 v1, v13, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v3, v12, v3
	v_mul_hi_u32 v4, v3, 24
	v_mul_lo_u32 v3, v3, 24
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_u32 v3, vcc_lo, v14, v3
	v_mov_b32_e32 v14, v7
	v_mul_lo_u32 v1, v1, 24
	v_add_nc_u32_e32 v1, v4, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e32 v4, vcc_lo, v15, v1, vcc_lo
	v_mov_b32_e32 v15, v8
	global_store_b64 v[3:4], v[7:8], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[14:15], v2, v[12:15], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[14:15], v[7:8]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB3_29
; %bb.27:                               ; %.preheader.i.i.i.preheader
                                        ;   in Loop: Header=BB3_2 Depth=1
	s_mov_b32 s0, 0
.LBB3_28:                               ; %.preheader.i.i.i
                                        ;   Parent Loop BB3_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	global_store_b64 v[3:4], v[14:15], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[7:8], v2, v[12:15], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[14:15]
	v_dual_mov_b32 v15, v8 :: v_dual_mov_b32 v14, v7
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB3_28
.LBB3_29:                               ; %__ockl_printf_begin.exit
                                        ;   in Loop: Header=BB3_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_getpc_b64 s[8:9]
	s_add_u32 s8, s8, .str@rel32@lo+4
	s_addc_u32 s9, s9, .str@rel32@hi+12
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u64 s[8:9], 0
	s_cbranch_scc0 .LBB3_116
; %bb.30:                               ;   in Loop: Header=BB3_2 Depth=1
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v33, 2, v10
	v_dual_mov_b32 v13, v11 :: v_dual_and_b32 v12, -3, v10
	s_mov_b64 s[10:11], 23
.LBB3_31:                               ;   Parent Loop BB3_2 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB3_34 Depth 3
                                        ;       Child Loop BB3_42 Depth 3
                                        ;       Child Loop BB3_50 Depth 3
                                        ;       Child Loop BB3_58 Depth 3
                                        ;       Child Loop BB3_66 Depth 3
                                        ;       Child Loop BB3_74 Depth 3
                                        ;       Child Loop BB3_82 Depth 3
                                        ;       Child Loop BB3_90 Depth 3
                                        ;       Child Loop BB3_98 Depth 3
                                        ;       Child Loop BB3_104 Depth 3
                                        ;       Child Loop BB3_113 Depth 3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_u64_e64 s0, s[10:11], 56
	s_and_b32 s0, s0, exec_lo
	s_cselect_b32 s12, s10, 56
	s_cselect_b32 s13, s11, 0
	s_cmp_gt_u32 s12, 7
	s_cbranch_scc1 .LBB3_36
; %bb.32:                               ;   in Loop: Header=BB3_31 Depth=2
	s_waitcnt vmcnt(0)
	v_mov_b32_e32 v14, 0
	v_mov_b32_e32 v15, 0
	s_cmp_eq_u32 s12, 0
	s_cbranch_scc1 .LBB3_35
; %bb.33:                               ; %.preheader31.i.preheader
                                        ;   in Loop: Header=BB3_31 Depth=2
	s_lshl_b64 s[0:1], s[12:13], 3
	s_mov_b64 s[14:15], 0
	s_mov_b64 s[16:17], s[8:9]
.LBB3_34:                               ; %.preheader31.i
                                        ;   Parent Loop BB3_2 Depth=1
                                        ;     Parent Loop BB3_31 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	global_load_u8 v1, v2, s[16:17]
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v1, 0xffff, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], s14, v[1:2]
	s_add_u32 s14, s14, 8
	s_addc_u32 s15, s15, 0
	s_add_u32 s16, s16, 1
	s_addc_u32 s17, s17, 0
	s_cmp_lg_u32 s0, s14
	v_or_b32_e32 v14, v3, v14
	v_or_b32_e32 v15, v4, v15
	s_cbranch_scc1 .LBB3_34
.LBB3_35:                               ; %Flow380
                                        ;   in Loop: Header=BB3_31 Depth=2
	s_mov_b32 s0, 0
	s_mov_b32 s19, 0
	s_branch .LBB3_37
.LBB3_36:                               ;   in Loop: Header=BB3_31 Depth=2
	s_mov_b32 s0, -1
                                        ; implicit-def: $vgpr14_vgpr15
                                        ; implicit-def: $sgpr19
.LBB3_37:                               ; %Flow382
                                        ;   in Loop: Header=BB3_31 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s0
	s_mov_b64 s[0:1], s[8:9]
	s_cbranch_vccnz .LBB3_39
; %bb.38:                               ;   in Loop: Header=BB3_31 Depth=2
	global_load_b64 v[14:15], v2, s[8:9]
	s_add_i32 s19, s12, -8
	s_add_u32 s0, s8, 8
	s_addc_u32 s1, s9, 0
.LBB3_39:                               ; %.loopexit32.i
                                        ;   in Loop: Header=BB3_31 Depth=2
	s_cmp_gt_u32 s19, 7
	s_cbranch_scc1 .LBB3_44
; %bb.40:                               ;   in Loop: Header=BB3_31 Depth=2
	v_mov_b32_e32 v16, 0
	v_mov_b32_e32 v17, 0
	s_cmp_eq_u32 s19, 0
	s_cbranch_scc1 .LBB3_43
; %bb.41:                               ; %.preheader29.i.preheader
                                        ;   in Loop: Header=BB3_31 Depth=2
	s_mov_b64 s[14:15], 0
	s_mov_b64 s[16:17], 0
.LBB3_42:                               ; %.preheader29.i
                                        ;   Parent Loop BB3_2 Depth=1
                                        ;     Parent Loop BB3_31 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s20, s0, s16
	s_addc_u32 s21, s1, s17
	s_add_u32 s16, s16, 1
	global_load_u8 v1, v2, s[20:21]
	s_addc_u32 s17, s17, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v1, 0xffff, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], s14, v[1:2]
	s_add_u32 s14, s14, 8
	s_addc_u32 s15, s15, 0
	s_cmp_lg_u32 s19, s16
	v_or_b32_e32 v16, v3, v16
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v17, v4, v17
	s_cbranch_scc1 .LBB3_42
.LBB3_43:                               ; %Flow375
                                        ;   in Loop: Header=BB3_31 Depth=2
	s_mov_b32 s14, 0
	s_mov_b32 s20, 0
	s_branch .LBB3_45
.LBB3_44:                               ;   in Loop: Header=BB3_31 Depth=2
	s_mov_b32 s14, -1
                                        ; implicit-def: $vgpr16_vgpr17
                                        ; implicit-def: $sgpr20
.LBB3_45:                               ; %Flow377
                                        ;   in Loop: Header=BB3_31 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s14
	s_cbranch_vccnz .LBB3_47
; %bb.46:                               ;   in Loop: Header=BB3_31 Depth=2
	global_load_b64 v[16:17], v2, s[0:1]
	s_add_i32 s20, s19, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB3_47:                               ; %.loopexit30.i
                                        ;   in Loop: Header=BB3_31 Depth=2
	s_cmp_gt_u32 s20, 7
	s_cbranch_scc1 .LBB3_52
; %bb.48:                               ;   in Loop: Header=BB3_31 Depth=2
	v_mov_b32_e32 v18, 0
	v_mov_b32_e32 v19, 0
	s_cmp_eq_u32 s20, 0
	s_cbranch_scc1 .LBB3_51
; %bb.49:                               ; %.preheader27.i.preheader
                                        ;   in Loop: Header=BB3_31 Depth=2
	s_mov_b64 s[14:15], 0
	s_mov_b64 s[16:17], 0
.LBB3_50:                               ; %.preheader27.i
                                        ;   Parent Loop BB3_2 Depth=1
                                        ;     Parent Loop BB3_31 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s22, s0, s16
	s_addc_u32 s23, s1, s17
	s_add_u32 s16, s16, 1
	global_load_u8 v1, v2, s[22:23]
	s_addc_u32 s17, s17, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v1, 0xffff, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], s14, v[1:2]
	s_add_u32 s14, s14, 8
	s_addc_u32 s15, s15, 0
	s_cmp_lg_u32 s20, s16
	v_or_b32_e32 v18, v3, v18
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v19, v4, v19
	s_cbranch_scc1 .LBB3_50
.LBB3_51:                               ; %Flow370
                                        ;   in Loop: Header=BB3_31 Depth=2
	s_mov_b32 s14, 0
	s_mov_b32 s19, 0
	s_branch .LBB3_53
.LBB3_52:                               ;   in Loop: Header=BB3_31 Depth=2
	s_mov_b32 s14, -1
                                        ; implicit-def: $sgpr19
.LBB3_53:                               ; %Flow372
                                        ;   in Loop: Header=BB3_31 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s14
	s_cbranch_vccnz .LBB3_55
; %bb.54:                               ;   in Loop: Header=BB3_31 Depth=2
	global_load_b64 v[18:19], v2, s[0:1]
	s_add_i32 s19, s20, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB3_55:                               ; %.loopexit28.i
                                        ;   in Loop: Header=BB3_31 Depth=2
	s_cmp_gt_u32 s19, 7
	s_cbranch_scc1 .LBB3_60
; %bb.56:                               ;   in Loop: Header=BB3_31 Depth=2
	v_mov_b32_e32 v20, 0
	v_mov_b32_e32 v21, 0
	s_cmp_eq_u32 s19, 0
	s_cbranch_scc1 .LBB3_59
; %bb.57:                               ; %.preheader25.i.preheader
                                        ;   in Loop: Header=BB3_31 Depth=2
	s_mov_b64 s[14:15], 0
	s_mov_b64 s[16:17], 0
.LBB3_58:                               ; %.preheader25.i
                                        ;   Parent Loop BB3_2 Depth=1
                                        ;     Parent Loop BB3_31 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s20, s0, s16
	s_addc_u32 s21, s1, s17
	s_add_u32 s16, s16, 1
	global_load_u8 v1, v2, s[20:21]
	s_addc_u32 s17, s17, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v1, 0xffff, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], s14, v[1:2]
	s_add_u32 s14, s14, 8
	s_addc_u32 s15, s15, 0
	s_cmp_lg_u32 s19, s16
	v_or_b32_e32 v20, v3, v20
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v21, v4, v21
	s_cbranch_scc1 .LBB3_58
.LBB3_59:                               ; %Flow365
                                        ;   in Loop: Header=BB3_31 Depth=2
	s_mov_b32 s14, 0
	s_mov_b32 s20, 0
	s_branch .LBB3_61
.LBB3_60:                               ;   in Loop: Header=BB3_31 Depth=2
	s_mov_b32 s14, -1
                                        ; implicit-def: $vgpr20_vgpr21
                                        ; implicit-def: $sgpr20
.LBB3_61:                               ; %Flow367
                                        ;   in Loop: Header=BB3_31 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s14
	s_cbranch_vccnz .LBB3_63
; %bb.62:                               ;   in Loop: Header=BB3_31 Depth=2
	global_load_b64 v[20:21], v2, s[0:1]
	s_add_i32 s20, s19, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB3_63:                               ; %.loopexit26.i
                                        ;   in Loop: Header=BB3_31 Depth=2
	s_cmp_gt_u32 s20, 7
	s_cbranch_scc1 .LBB3_68
; %bb.64:                               ;   in Loop: Header=BB3_31 Depth=2
	v_mov_b32_e32 v22, 0
	v_mov_b32_e32 v23, 0
	s_cmp_eq_u32 s20, 0
	s_cbranch_scc1 .LBB3_67
; %bb.65:                               ; %.preheader23.i.preheader
                                        ;   in Loop: Header=BB3_31 Depth=2
	s_mov_b64 s[14:15], 0
	s_mov_b64 s[16:17], 0
.LBB3_66:                               ; %.preheader23.i
                                        ;   Parent Loop BB3_2 Depth=1
                                        ;     Parent Loop BB3_31 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s22, s0, s16
	s_addc_u32 s23, s1, s17
	s_add_u32 s16, s16, 1
	global_load_u8 v1, v2, s[22:23]
	s_addc_u32 s17, s17, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v1, 0xffff, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], s14, v[1:2]
	s_add_u32 s14, s14, 8
	s_addc_u32 s15, s15, 0
	s_cmp_lg_u32 s20, s16
	v_or_b32_e32 v22, v3, v22
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v23, v4, v23
	s_cbranch_scc1 .LBB3_66
.LBB3_67:                               ; %Flow360
                                        ;   in Loop: Header=BB3_31 Depth=2
	s_mov_b32 s14, 0
	s_mov_b32 s19, 0
	s_branch .LBB3_69
.LBB3_68:                               ;   in Loop: Header=BB3_31 Depth=2
	s_mov_b32 s14, -1
                                        ; implicit-def: $sgpr19
.LBB3_69:                               ; %Flow362
                                        ;   in Loop: Header=BB3_31 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s14
	s_cbranch_vccnz .LBB3_71
; %bb.70:                               ;   in Loop: Header=BB3_31 Depth=2
	global_load_b64 v[22:23], v2, s[0:1]
	s_add_i32 s19, s20, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB3_71:                               ; %.loopexit24.i
                                        ;   in Loop: Header=BB3_31 Depth=2
	s_cmp_gt_u32 s19, 7
	s_cbranch_scc1 .LBB3_76
; %bb.72:                               ;   in Loop: Header=BB3_31 Depth=2
	v_mov_b32_e32 v24, 0
	v_mov_b32_e32 v25, 0
	s_cmp_eq_u32 s19, 0
	s_cbranch_scc1 .LBB3_75
; %bb.73:                               ; %.preheader21.i.preheader
                                        ;   in Loop: Header=BB3_31 Depth=2
	s_mov_b64 s[14:15], 0
	s_mov_b64 s[16:17], 0
.LBB3_74:                               ; %.preheader21.i
                                        ;   Parent Loop BB3_2 Depth=1
                                        ;     Parent Loop BB3_31 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s20, s0, s16
	s_addc_u32 s21, s1, s17
	s_add_u32 s16, s16, 1
	global_load_u8 v1, v2, s[20:21]
	s_addc_u32 s17, s17, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v1, 0xffff, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], s14, v[1:2]
	s_add_u32 s14, s14, 8
	s_addc_u32 s15, s15, 0
	s_cmp_lg_u32 s19, s16
	v_or_b32_e32 v24, v3, v24
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v25, v4, v25
	s_cbranch_scc1 .LBB3_74
.LBB3_75:                               ; %Flow355
                                        ;   in Loop: Header=BB3_31 Depth=2
	s_mov_b32 s14, 0
	s_mov_b32 s20, 0
	s_branch .LBB3_77
.LBB3_76:                               ;   in Loop: Header=BB3_31 Depth=2
	s_mov_b32 s14, -1
                                        ; implicit-def: $vgpr24_vgpr25
                                        ; implicit-def: $sgpr20
.LBB3_77:                               ; %Flow357
                                        ;   in Loop: Header=BB3_31 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s14
	s_cbranch_vccnz .LBB3_79
; %bb.78:                               ;   in Loop: Header=BB3_31 Depth=2
	global_load_b64 v[24:25], v2, s[0:1]
	s_add_i32 s20, s19, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB3_79:                               ; %.loopexit22.i
                                        ;   in Loop: Header=BB3_31 Depth=2
	s_cmp_gt_u32 s20, 7
	s_cbranch_scc1 .LBB3_84
; %bb.80:                               ;   in Loop: Header=BB3_31 Depth=2
	v_mov_b32_e32 v26, 0
	v_mov_b32_e32 v27, 0
	s_cmp_eq_u32 s20, 0
	s_cbranch_scc1 .LBB3_83
; %bb.81:                               ; %.preheader.i.preheader
                                        ;   in Loop: Header=BB3_31 Depth=2
	s_mov_b64 s[14:15], 0
	s_mov_b64 s[16:17], s[0:1]
.LBB3_82:                               ; %.preheader.i
                                        ;   Parent Loop BB3_2 Depth=1
                                        ;     Parent Loop BB3_31 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	global_load_u8 v1, v2, s[16:17]
	s_add_i32 s20, s20, -1
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v1, 0xffff, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], s14, v[1:2]
	s_add_u32 s14, s14, 8
	s_addc_u32 s15, s15, 0
	s_add_u32 s16, s16, 1
	s_addc_u32 s17, s17, 0
	s_cmp_lg_u32 s20, 0
	v_or_b32_e32 v26, v3, v26
	v_or_b32_e32 v27, v4, v27
	s_cbranch_scc1 .LBB3_82
.LBB3_83:                               ; %Flow350
                                        ;   in Loop: Header=BB3_31 Depth=2
	s_mov_b32 s14, 0
	s_branch .LBB3_85
.LBB3_84:                               ;   in Loop: Header=BB3_31 Depth=2
	s_mov_b32 s14, -1
.LBB3_85:                               ; %Flow352
                                        ;   in Loop: Header=BB3_31 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s14
	s_cbranch_vccnz .LBB3_87
; %bb.86:                               ;   in Loop: Header=BB3_31 Depth=2
	global_load_b64 v[26:27], v2, s[0:1]
.LBB3_87:                               ; %.loopexit.i
                                        ;   in Loop: Header=BB3_31 Depth=2
	v_mov_b32_e32 v1, v32
	v_mov_b32_e32 v3, 0
	v_mov_b32_e32 v4, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s0, v1
	v_cmp_eq_u32_e64 s0, s0, v1
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB3_93
; %bb.88:                               ;   in Loop: Header=BB3_31 Depth=2
	global_load_b64 v[30:31], v2, s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[3:4], v2, s[4:5] offset:40
	global_load_b64 v[7:8], v2, s[4:5]
	s_mov_b32 s14, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v4, v4, v31
	v_and_b32_e32 v3, v3, v30
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v4, v4, 24
	v_mul_hi_u32 v28, v3, 24
	v_mul_lo_u32 v3, v3, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v4, v28, v4
	s_waitcnt vmcnt(0)
	v_add_co_u32 v3, vcc_lo, v7, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, v8, v4, vcc_lo
	global_load_b64 v[28:29], v[3:4], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[3:4], v2, v[28:31], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[3:4], v[30:31]
	s_cbranch_execz .LBB3_92
; %bb.89:                               ; %.preheader3.i.i19.i.preheader
                                        ;   in Loop: Header=BB3_31 Depth=2
	s_mov_b32 s15, 0
.LBB3_90:                               ; %.preheader3.i.i19.i
                                        ;   Parent Loop BB3_2 Depth=1
                                        ;     Parent Loop BB3_31 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[7:8], v2, s[4:5] offset:40
	global_load_b64 v[28:29], v2, s[4:5]
	v_dual_mov_b32 v31, v4 :: v_dual_mov_b32 v30, v3
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v7, v7, v30
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[3:4], null, v7, 24, v[28:29]
	v_and_b32_e32 v28, v8, v31
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[7:8], null, v28, 24, v[4:5]
	v_mov_b32_e32 v4, v7
	global_load_b64 v[28:29], v[3:4], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[3:4], v2, v[28:31], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[3:4], v[30:31]
	s_or_b32 s15, vcc_lo, s15
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s15
	s_cbranch_execnz .LBB3_90
; %bb.91:                               ; %Flow345
                                        ;   in Loop: Header=BB3_31 Depth=2
	s_or_b32 exec_lo, exec_lo, s15
.LBB3_92:                               ; %Flow347
                                        ;   in Loop: Header=BB3_31 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s14
.LBB3_93:                               ; %.loopexit4.i.i14.i
                                        ;   in Loop: Header=BB3_31 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_clause 0x1
	global_load_b64 v[7:8], v2, s[4:5] offset:40
	global_load_b128 v[28:31], v2, s[4:5]
	v_readfirstlane_b32 s14, v3
	v_readfirstlane_b32 s15, v4
	s_mov_b32 s21, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s16, v7
	v_readfirstlane_b32 s17, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[16:17], s[14:15], s[16:17]
	s_mul_i32 s1, s17, 24
	s_mul_hi_u32 s19, s16, 24
	s_mul_i32 s20, s16, 24
	s_and_saveexec_b32 s22, s0
	s_cbranch_execz .LBB3_95
; %bb.94:                               ;   in Loop: Header=BB3_31 Depth=2
	v_dual_mov_b32 v3, s21 :: v_dual_mov_b32 v4, v2
	s_add_i32 s21, s19, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v7, vcc_lo, v28, s20
	v_add_co_ci_u32_e32 v8, vcc_lo, s21, v29, vcc_lo
	global_store_b128 v[7:8], v[3:6], off offset:8
.LBB3_95:                               ;   in Loop: Header=BB3_31 Depth=2
	s_or_b32 exec_lo, exec_lo, s22
	v_cmp_gt_u64_e64 vcc_lo, s[10:11], 56
	v_or_b32_e32 v3, 0, v13
	v_or_b32_e32 v4, v12, v33
	s_lshl_b64 s[16:17], s[16:17], 12
	s_lshl_b32 s21, s12, 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_i32 s21, s21, 28
	v_cndmask_b32_e32 v13, v3, v13, vcc_lo
	v_cndmask_b32_e32 v7, v4, v12, vcc_lo
	v_lshlrev_b64 v[3:4], 6, v[1:2]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v1, vcc_lo, v30, s16
	v_add_co_ci_u32_e32 v8, vcc_lo, s17, v31, vcc_lo
	s_and_b32 s21, s21, 0x1e0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v3, vcc_lo, v1, v3
	v_and_or_b32 v12, 0xffffff1f, v7, s21
	v_add_co_ci_u32_e32 v4, vcc_lo, v8, v4, vcc_lo
	s_clause 0x3
	global_store_b128 v[3:4], v[12:15], off
	global_store_b128 v[3:4], v[16:19], off offset:16
	global_store_b128 v[3:4], v[20:23], off offset:32
	global_store_b128 v[3:4], v[24:27], off offset:48
	s_and_saveexec_b32 s16, s0
	s_cbranch_execz .LBB3_103
; %bb.96:                               ;   in Loop: Header=BB3_31 Depth=2
	s_clause 0x1
	global_load_b64 v[16:17], v2, s[4:5] offset:32 glc
	global_load_b64 v[7:8], v2, s[4:5] offset:40
	v_dual_mov_b32 v14, s14 :: v_dual_mov_b32 v15, s15
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s22, v7
	v_readfirstlane_b32 s23, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[22:23], s[22:23], s[14:15]
	s_mul_i32 s17, s23, 24
	s_mul_hi_u32 s21, s22, 24
	s_mul_i32 s22, s22, 24
	s_add_i32 s21, s21, s17
	v_add_co_u32 v7, vcc_lo, v28, s22
	v_add_co_ci_u32_e32 v8, vcc_lo, s21, v29, vcc_lo
	s_mov_b32 s17, exec_lo
	global_store_b64 v[7:8], v[16:17], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[14:15], v2, v[14:17], s[4:5] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[14:15], v[16:17]
	s_cbranch_execz .LBB3_99
; %bb.97:                               ; %.preheader1.i.i17.i.preheader
                                        ;   in Loop: Header=BB3_31 Depth=2
	s_mov_b32 s21, 0
.LBB3_98:                               ; %.preheader1.i.i17.i
                                        ;   Parent Loop BB3_2 Depth=1
                                        ;     Parent Loop BB3_31 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	v_dual_mov_b32 v12, s14 :: v_dual_mov_b32 v13, s15
	s_sleep 1
	global_store_b64 v[7:8], v[14:15], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[12:13], v2, v[12:15], s[4:5] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[12:13], v[14:15]
	v_dual_mov_b32 v15, v13 :: v_dual_mov_b32 v14, v12
	s_or_b32 s21, vcc_lo, s21
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s21
	s_cbranch_execnz .LBB3_98
.LBB3_99:                               ; %Flow343
                                        ;   in Loop: Header=BB3_31 Depth=2
	s_or_b32 exec_lo, exec_lo, s17
	global_load_b64 v[7:8], v2, s[4:5] offset:16
	s_mov_b32 s21, exec_lo
	s_mov_b32 s17, exec_lo
	v_mbcnt_lo_u32_b32 v1, s21, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v1
	s_cbranch_execz .LBB3_101
; %bb.100:                              ;   in Loop: Header=BB3_31 Depth=2
	s_bcnt1_i32_b32 s21, s21
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v1, s21
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[7:8], v[1:2], off offset:8
.LBB3_101:                              ;   in Loop: Header=BB3_31 Depth=2
	s_or_b32 exec_lo, exec_lo, s17
	s_waitcnt vmcnt(0)
	global_load_b64 v[12:13], v[7:8], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[12:13]
	s_cbranch_vccnz .LBB3_103
; %bb.102:                              ;   in Loop: Header=BB3_31 Depth=2
	global_load_b32 v1, v[7:8], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s17, v1
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[12:13], v[1:2], off
	s_and_b32 m0, s17, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB3_103:                              ; %Flow344
                                        ;   in Loop: Header=BB3_31 Depth=2
	s_or_b32 exec_lo, exec_lo, s16
	s_add_i32 s19, s19, s1
	v_add_co_u32 v1, vcc_lo, v28, s20
	v_add_co_ci_u32_e32 v8, vcc_lo, s19, v29, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v7, vcc_lo, v1, 20
	v_add_co_ci_u32_e32 v8, vcc_lo, 0, v8, vcc_lo
.LBB3_104:                              ;   Parent Loop BB3_2 Depth=1
                                        ;     Parent Loop BB3_31 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	v_mov_b32_e32 v1, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB3_106
; %bb.105:                              ;   in Loop: Header=BB3_104 Depth=3
	global_load_b32 v1, v[7:8], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v1, 1, v1
.LBB3_106:                              ;   in Loop: Header=BB3_104 Depth=3
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v1
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB3_108
; %bb.107:                              ;   in Loop: Header=BB3_104 Depth=3
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB3_109
.LBB3_108:                              ;   in Loop: Header=BB3_104 Depth=3
	s_mov_b32 s1, -1
.LBB3_109:                              ; %Flow338
                                        ;   in Loop: Header=BB3_104 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB3_104
; %bb.110:                              ;   in Loop: Header=BB3_31 Depth=2
	global_load_b128 v[12:15], v[3:4], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB3_114
; %bb.111:                              ;   in Loop: Header=BB3_31 Depth=2
	s_clause 0x2
	global_load_b64 v[3:4], v2, s[4:5] offset:40
	global_load_b64 v[7:8], v2, s[4:5] offset:24 glc
	global_load_b64 v[16:17], v2, s[4:5]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v1, vcc_lo, v3, 1
	v_add_co_ci_u32_e32 v18, vcc_lo, 0, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v14, vcc_lo, v1, s14
	v_add_co_ci_u32_e32 v15, vcc_lo, s15, v18, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[14:15]
	v_dual_cndmask_b32 v15, v15, v18 :: v_dual_cndmask_b32 v14, v14, v1
	v_and_b32_e32 v1, v15, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v3, v14, v3
	v_mul_lo_u32 v1, v1, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v4, v3, 24
	v_mul_lo_u32 v3, v3, 24
	v_add_nc_u32_e32 v1, v4, v1
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v3, vcc_lo, v16, v3
	v_mov_b32_e32 v16, v7
	v_add_co_ci_u32_e32 v4, vcc_lo, v17, v1, vcc_lo
	v_mov_b32_e32 v17, v8
	global_store_b64 v[3:4], v[7:8], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[16:17], v2, v[14:17], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[16:17], v[7:8]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB3_114
; %bb.112:                              ; %.preheader.i.i16.i.preheader
                                        ;   in Loop: Header=BB3_31 Depth=2
	s_mov_b32 s0, 0
.LBB3_113:                              ; %.preheader.i.i16.i
                                        ;   Parent Loop BB3_2 Depth=1
                                        ;     Parent Loop BB3_31 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_sleep 1
	global_store_b64 v[3:4], v[16:17], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[7:8], v2, v[14:17], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[16:17]
	v_dual_mov_b32 v17, v8 :: v_dual_mov_b32 v16, v7
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB3_113
.LBB3_114:                              ; %__ockl_hostcall_preview.exit20.i
                                        ;   in Loop: Header=BB3_31 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	s_sub_u32 s10, s10, s12
	s_subb_u32 s11, s11, s13
	s_add_u32 s8, s8, s12
	s_addc_u32 s9, s9, s13
	s_cmp_lg_u64 s[10:11], 0
	s_cbranch_scc1 .LBB3_31
; %bb.115:                              ; %Flow383
                                        ;   in Loop: Header=BB3_2 Depth=1
	s_mov_b32 s0, 0
	s_branch .LBB3_117
.LBB3_116:                              ;   in Loop: Header=BB3_2 Depth=1
	s_mov_b32 s0, -1
                                        ; implicit-def: $vgpr12_vgpr13
.LBB3_117:                              ; %Flow398
                                        ;   in Loop: Header=BB3_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccz .LBB3_146
; %bb.118:                              ;   in Loop: Header=BB3_2 Depth=1
	v_mov_b32_e32 v1, v32
	v_mov_b32_e32 v3, 0
	v_mov_b32_e32 v4, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s0, v1
	v_cmp_eq_u32_e64 s0, s0, v1
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB3_124
; %bb.119:                              ;   in Loop: Header=BB3_2 Depth=1
	global_load_b64 v[14:15], v2, s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[3:4], v2, s[4:5] offset:40
	global_load_b64 v[7:8], v2, s[4:5]
	s_mov_b32 s8, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v4, v4, v15
	v_and_b32_e32 v3, v3, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v4, v4, 24
	v_mul_hi_u32 v12, v3, 24
	v_mul_lo_u32 v3, v3, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v4, v12, v4
	s_waitcnt vmcnt(0)
	v_add_co_u32 v3, vcc_lo, v7, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, v8, v4, vcc_lo
	global_load_b64 v[12:13], v[3:4], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[3:4], v2, v[12:15], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[3:4], v[14:15]
	s_cbranch_execz .LBB3_123
; %bb.120:                              ; %.preheader3.i.i.i11.preheader
                                        ;   in Loop: Header=BB3_2 Depth=1
	s_mov_b32 s9, 0
.LBB3_121:                              ; %.preheader3.i.i.i11
                                        ;   Parent Loop BB3_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[7:8], v2, s[4:5] offset:40
	global_load_b64 v[12:13], v2, s[4:5]
	v_dual_mov_b32 v15, v4 :: v_dual_mov_b32 v14, v3
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v7, v7, v14
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[3:4], null, v7, 24, v[12:13]
	v_and_b32_e32 v12, v8, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[7:8], null, v12, 24, v[4:5]
	v_mov_b32_e32 v4, v7
	global_load_b64 v[12:13], v[3:4], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[3:4], v2, v[12:15], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[3:4], v[14:15]
	s_or_b32 s9, vcc_lo, s9
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s9
	s_cbranch_execnz .LBB3_121
; %bb.122:                              ; %Flow395
                                        ;   in Loop: Header=BB3_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s9
.LBB3_123:                              ; %Flow397
                                        ;   in Loop: Header=BB3_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s8
.LBB3_124:                              ; %.loopexit4.i.i.i6
                                        ;   in Loop: Header=BB3_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_clause 0x1
	global_load_b64 v[7:8], v2, s[4:5] offset:40
	global_load_b128 v[14:17], v2, s[4:5]
	v_readfirstlane_b32 s8, v3
	v_readfirstlane_b32 s9, v4
	s_mov_b32 s14, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s10, v7
	v_readfirstlane_b32 s11, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[10:11], s[8:9], s[10:11]
	s_mul_i32 s1, s11, 24
	s_mul_hi_u32 s12, s10, 24
	s_mul_i32 s13, s10, 24
	s_and_saveexec_b32 s15, s0
	s_cbranch_execz .LBB3_126
; %bb.125:                              ;   in Loop: Header=BB3_2 Depth=1
	v_dual_mov_b32 v3, s14 :: v_dual_mov_b32 v4, v2
	s_add_i32 s14, s12, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v7, vcc_lo, v14, s13
	v_add_co_ci_u32_e32 v8, vcc_lo, s14, v15, vcc_lo
	global_store_b128 v[7:8], v[3:6], off offset:8
.LBB3_126:                              ;   in Loop: Header=BB3_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s15
	s_lshl_b64 s[10:11], s[10:11], 12
	v_lshlrev_b64 v[3:4], 6, v[1:2]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v1, vcc_lo, v16, s10
	v_add_co_ci_u32_e32 v7, vcc_lo, s11, v17, vcc_lo
	s_mov_b32 s20, s7
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, v1, v3
	s_mov_b32 s21, s7
	s_mov_b32 s22, s7
	s_mov_b32 s23, s7
	v_and_or_b32 v10, 0xffffff1f, v10, 32
	v_add_co_ci_u32_e32 v4, vcc_lo, v7, v4, vcc_lo
	v_mov_b32_e32 v12, v2
	v_dual_mov_b32 v13, v2 :: v_dual_mov_b32 v16, s20
	v_dual_mov_b32 v17, s21 :: v_dual_mov_b32 v18, s22
	v_mov_b32_e32 v19, s23
	s_clause 0x3
	global_store_b128 v[3:4], v[10:13], off
	global_store_b128 v[3:4], v[16:19], off offset:16
	global_store_b128 v[3:4], v[16:19], off offset:32
	global_store_b128 v[3:4], v[16:19], off offset:48
	s_and_saveexec_b32 s10, s0
	s_cbranch_execz .LBB3_134
; %bb.127:                              ;   in Loop: Header=BB3_2 Depth=1
	s_clause 0x1
	global_load_b64 v[18:19], v2, s[4:5] offset:32 glc
	global_load_b64 v[7:8], v2, s[4:5] offset:40
	v_dual_mov_b32 v16, s8 :: v_dual_mov_b32 v17, s9
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s14, v7
	v_readfirstlane_b32 s15, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[14:15], s[14:15], s[8:9]
	s_mul_i32 s11, s15, 24
	s_mul_hi_u32 s15, s14, 24
	s_mul_i32 s14, s14, 24
	s_add_i32 s15, s15, s11
	v_add_co_u32 v7, vcc_lo, v14, s14
	v_add_co_ci_u32_e32 v8, vcc_lo, s15, v15, vcc_lo
	s_mov_b32 s11, exec_lo
	global_store_b64 v[7:8], v[18:19], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[12:13], v2, v[16:19], s[4:5] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[12:13], v[18:19]
	s_cbranch_execz .LBB3_130
; %bb.128:                              ; %.preheader1.i.i.i9.preheader
                                        ;   in Loop: Header=BB3_2 Depth=1
	s_mov_b32 s14, 0
.LBB3_129:                              ; %.preheader1.i.i.i9
                                        ;   Parent Loop BB3_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_dual_mov_b32 v10, s8 :: v_dual_mov_b32 v11, s9
	s_sleep 1
	global_store_b64 v[7:8], v[12:13], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[10:11], v2, v[10:13], s[4:5] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[10:11], v[12:13]
	v_dual_mov_b32 v13, v11 :: v_dual_mov_b32 v12, v10
	s_or_b32 s14, vcc_lo, s14
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s14
	s_cbranch_execnz .LBB3_129
.LBB3_130:                              ; %Flow393
                                        ;   in Loop: Header=BB3_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s11
	global_load_b64 v[7:8], v2, s[4:5] offset:16
	s_mov_b32 s14, exec_lo
	s_mov_b32 s11, exec_lo
	v_mbcnt_lo_u32_b32 v1, s14, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v1
	s_cbranch_execz .LBB3_132
; %bb.131:                              ;   in Loop: Header=BB3_2 Depth=1
	s_bcnt1_i32_b32 s14, s14
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v1, s14
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[7:8], v[1:2], off offset:8
.LBB3_132:                              ;   in Loop: Header=BB3_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s11
	s_waitcnt vmcnt(0)
	global_load_b64 v[10:11], v[7:8], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[10:11]
	s_cbranch_vccnz .LBB3_134
; %bb.133:                              ;   in Loop: Header=BB3_2 Depth=1
	global_load_b32 v1, v[7:8], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s11, v1
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[10:11], v[1:2], off
	s_and_b32 m0, s11, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB3_134:                              ; %Flow394
                                        ;   in Loop: Header=BB3_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
	s_add_i32 s12, s12, s1
	v_add_co_u32 v1, vcc_lo, v14, s13
	v_add_co_ci_u32_e32 v8, vcc_lo, s12, v15, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v7, vcc_lo, v1, 20
	v_add_co_ci_u32_e32 v8, vcc_lo, 0, v8, vcc_lo
.LBB3_135:                              ;   Parent Loop BB3_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_mov_b32_e32 v1, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB3_137
; %bb.136:                              ;   in Loop: Header=BB3_135 Depth=2
	global_load_b32 v1, v[7:8], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v1, 1, v1
.LBB3_137:                              ;   in Loop: Header=BB3_135 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v1
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB3_139
; %bb.138:                              ;   in Loop: Header=BB3_135 Depth=2
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB3_140
.LBB3_139:                              ;   in Loop: Header=BB3_135 Depth=2
	s_mov_b32 s1, -1
.LBB3_140:                              ; %Flow388
                                        ;   in Loop: Header=BB3_135 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB3_135
; %bb.141:                              ;   in Loop: Header=BB3_2 Depth=1
	global_load_b128 v[12:15], v[3:4], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB3_145
; %bb.142:                              ;   in Loop: Header=BB3_2 Depth=1
	s_clause 0x2
	global_load_b64 v[3:4], v2, s[4:5] offset:40
	global_load_b64 v[7:8], v2, s[4:5] offset:24 glc
	global_load_b64 v[10:11], v2, s[4:5]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v1, vcc_lo, v3, 1
	v_add_co_ci_u32_e32 v16, vcc_lo, 0, v4, vcc_lo
	s_waitcnt vmcnt(1)
	v_mov_b32_e32 v17, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v14, vcc_lo, v1, s8
	v_add_co_ci_u32_e32 v15, vcc_lo, s9, v16, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[14:15]
	v_dual_cndmask_b32 v15, v15, v16 :: v_dual_cndmask_b32 v14, v14, v1
	v_mov_b32_e32 v16, v7
	v_and_b32_e32 v1, v15, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v3, v14, v3
	v_mul_lo_u32 v1, v1, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v4, v3, 24
	v_mul_lo_u32 v3, v3, 24
	v_add_nc_u32_e32 v1, v4, v1
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, v10, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, v11, v1, vcc_lo
	global_store_b64 v[3:4], v[7:8], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[16:17], v2, v[14:17], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[16:17], v[7:8]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB3_145
; %bb.143:                              ; %.preheader.i.i.i8.preheader
                                        ;   in Loop: Header=BB3_2 Depth=1
	s_mov_b32 s0, 0
.LBB3_144:                              ; %.preheader.i.i.i8
                                        ;   Parent Loop BB3_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	global_store_b64 v[3:4], v[16:17], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[7:8], v2, v[14:17], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[16:17]
	v_dual_mov_b32 v17, v8 :: v_dual_mov_b32 v16, v7
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB3_144
.LBB3_145:                              ; %__ockl_hostcall_preview.exit.i
                                        ;   in Loop: Header=BB3_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
.LBB3_146:                              ; %__ockl_printf_append_string_n.exit
                                        ;   in Loop: Header=BB3_2 Depth=1
	v_mov_b32_e32 v1, v32
	v_mov_b32_e32 v3, 0
	v_mov_b32_e32 v4, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s0, v1
	v_cmp_eq_u32_e64 s0, s0, v1
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB3_152
; %bb.147:                              ;   in Loop: Header=BB3_2 Depth=1
	global_load_b64 v[16:17], v2, s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[3:4], v2, s[4:5] offset:40
	global_load_b64 v[7:8], v2, s[4:5]
	s_mov_b32 s8, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v4, v4, v17
	v_and_b32_e32 v3, v3, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v4, v4, 24
	v_mul_hi_u32 v10, v3, 24
	v_mul_lo_u32 v3, v3, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v4, v10, v4
	s_waitcnt vmcnt(0)
	v_add_co_u32 v3, vcc_lo, v7, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, v8, v4, vcc_lo
	global_load_b64 v[14:15], v[3:4], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[3:4], v2, v[14:17], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[3:4], v[16:17]
	s_cbranch_execz .LBB3_151
; %bb.148:                              ; %.preheader3.i.i.i18.preheader
                                        ;   in Loop: Header=BB3_2 Depth=1
	s_mov_b32 s9, 0
.LBB3_149:                              ; %.preheader3.i.i.i18
                                        ;   Parent Loop BB3_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[7:8], v2, s[4:5] offset:40
	global_load_b64 v[10:11], v2, s[4:5]
	v_dual_mov_b32 v17, v4 :: v_dual_mov_b32 v16, v3
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v7, v7, v16
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[3:4], null, v7, 24, v[10:11]
	v_and_b32_e32 v10, v8, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[7:8], null, v10, 24, v[4:5]
	v_mov_b32_e32 v4, v7
	global_load_b64 v[14:15], v[3:4], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[3:4], v2, v[14:17], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[3:4], v[16:17]
	s_or_b32 s9, vcc_lo, s9
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s9
	s_cbranch_execnz .LBB3_149
; %bb.150:                              ; %Flow331
                                        ;   in Loop: Header=BB3_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s9
.LBB3_151:                              ; %Flow333
                                        ;   in Loop: Header=BB3_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s8
.LBB3_152:                              ; %.loopexit4.i.i.i12
                                        ;   in Loop: Header=BB3_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_clause 0x1
	global_load_b64 v[7:8], v2, s[4:5] offset:40
	global_load_b128 v[16:19], v2, s[4:5]
	v_readfirstlane_b32 s8, v3
	v_readfirstlane_b32 s9, v4
	s_mov_b32 s14, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s10, v7
	v_readfirstlane_b32 s11, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[10:11], s[8:9], s[10:11]
	s_mul_i32 s1, s11, 24
	s_mul_hi_u32 s12, s10, 24
	s_mul_i32 s13, s10, 24
	s_and_saveexec_b32 s15, s0
	s_cbranch_execz .LBB3_154
; %bb.153:                              ;   in Loop: Header=BB3_2 Depth=1
	v_dual_mov_b32 v3, s14 :: v_dual_mov_b32 v4, v2
	s_add_i32 s14, s12, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v7, vcc_lo, v16, s13
	v_add_co_ci_u32_e32 v8, vcc_lo, s14, v17, vcc_lo
	global_store_b128 v[7:8], v[3:6], off offset:8
.LBB3_154:                              ;   in Loop: Header=BB3_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s15
	s_lshl_b64 s[10:11], s[10:11], 12
	v_lshlrev_b64 v[3:4], 6, v[1:2]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v1, vcc_lo, v18, s10
	v_add_co_ci_u32_e32 v7, vcc_lo, s11, v19, vcc_lo
	s_mov_b32 s20, s7
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, v1, v3
	s_mov_b32 s21, s7
	s_mov_b32 s22, s7
	s_mov_b32 s23, s7
	v_and_or_b32 v12, 0xffffff1f, v12, 32
	v_add_co_ci_u32_e32 v4, vcc_lo, v7, v4, vcc_lo
	v_dual_mov_b32 v14, s6 :: v_dual_mov_b32 v15, s7
	v_dual_mov_b32 v18, s20 :: v_dual_mov_b32 v19, s21
	v_dual_mov_b32 v20, s22 :: v_dual_mov_b32 v21, s23
	s_clause 0x3
	global_store_b128 v[3:4], v[12:15], off
	global_store_b128 v[3:4], v[18:21], off offset:16
	global_store_b128 v[3:4], v[18:21], off offset:32
	global_store_b128 v[3:4], v[18:21], off offset:48
	s_and_saveexec_b32 s10, s0
	s_cbranch_execz .LBB3_162
; %bb.155:                              ;   in Loop: Header=BB3_2 Depth=1
	s_clause 0x1
	global_load_b64 v[14:15], v2, s[4:5] offset:32 glc
	global_load_b64 v[7:8], v2, s[4:5] offset:40
	v_dual_mov_b32 v12, s8 :: v_dual_mov_b32 v13, s9
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s14, v7
	v_readfirstlane_b32 s15, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[14:15], s[14:15], s[8:9]
	s_mul_i32 s11, s15, 24
	s_mul_hi_u32 s15, s14, 24
	s_mul_i32 s14, s14, 24
	s_add_i32 s15, s15, s11
	v_add_co_u32 v7, vcc_lo, v16, s14
	v_add_co_ci_u32_e32 v8, vcc_lo, s15, v17, vcc_lo
	s_mov_b32 s11, exec_lo
	global_store_b64 v[7:8], v[14:15], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[12:13], v2, v[12:15], s[4:5] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[12:13], v[14:15]
	s_cbranch_execz .LBB3_158
; %bb.156:                              ; %.preheader1.i.i.i16.preheader
                                        ;   in Loop: Header=BB3_2 Depth=1
	s_mov_b32 s14, 0
.LBB3_157:                              ; %.preheader1.i.i.i16
                                        ;   Parent Loop BB3_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_dual_mov_b32 v10, s8 :: v_dual_mov_b32 v11, s9
	s_sleep 1
	global_store_b64 v[7:8], v[12:13], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[10:11], v2, v[10:13], s[4:5] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[10:11], v[12:13]
	v_dual_mov_b32 v13, v11 :: v_dual_mov_b32 v12, v10
	s_or_b32 s14, vcc_lo, s14
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s14
	s_cbranch_execnz .LBB3_157
.LBB3_158:                              ; %Flow329
                                        ;   in Loop: Header=BB3_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s11
	global_load_b64 v[7:8], v2, s[4:5] offset:16
	s_mov_b32 s14, exec_lo
	s_mov_b32 s11, exec_lo
	v_mbcnt_lo_u32_b32 v1, s14, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v1
	s_cbranch_execz .LBB3_160
; %bb.159:                              ;   in Loop: Header=BB3_2 Depth=1
	s_bcnt1_i32_b32 s14, s14
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v1, s14
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[7:8], v[1:2], off offset:8
.LBB3_160:                              ;   in Loop: Header=BB3_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s11
	s_waitcnt vmcnt(0)
	global_load_b64 v[10:11], v[7:8], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[10:11]
	s_cbranch_vccnz .LBB3_162
; %bb.161:                              ;   in Loop: Header=BB3_2 Depth=1
	global_load_b32 v1, v[7:8], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s11, v1
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[10:11], v[1:2], off
	s_and_b32 m0, s11, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB3_162:                              ; %Flow330
                                        ;   in Loop: Header=BB3_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
	s_add_i32 s12, s12, s1
	v_add_co_u32 v1, vcc_lo, v16, s13
	v_add_co_ci_u32_e32 v8, vcc_lo, s12, v17, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v7, vcc_lo, v1, 20
	v_add_co_ci_u32_e32 v8, vcc_lo, 0, v8, vcc_lo
.LBB3_163:                              ;   Parent Loop BB3_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_mov_b32_e32 v1, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB3_165
; %bb.164:                              ;   in Loop: Header=BB3_163 Depth=2
	global_load_b32 v1, v[7:8], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v1, 1, v1
.LBB3_165:                              ;   in Loop: Header=BB3_163 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v1
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB3_167
; %bb.166:                              ;   in Loop: Header=BB3_163 Depth=2
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB3_168
.LBB3_167:                              ;   in Loop: Header=BB3_163 Depth=2
	s_mov_b32 s1, -1
.LBB3_168:                              ; %Flow324
                                        ;   in Loop: Header=BB3_163 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB3_163
; %bb.169:                              ;   in Loop: Header=BB3_2 Depth=1
	global_load_b64 v[7:8], v[3:4], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB3_173
; %bb.170:                              ;   in Loop: Header=BB3_2 Depth=1
	s_clause 0x2
	global_load_b64 v[3:4], v2, s[4:5] offset:40
	global_load_b64 v[14:15], v2, s[4:5] offset:24 glc
	global_load_b64 v[12:13], v2, s[4:5]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v1, vcc_lo, v3, 1
	v_add_co_ci_u32_e32 v16, vcc_lo, 0, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v10, vcc_lo, v1, s8
	v_add_co_ci_u32_e32 v11, vcc_lo, s9, v16, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[10:11]
	v_dual_cndmask_b32 v11, v11, v16 :: v_dual_cndmask_b32 v10, v10, v1
	v_and_b32_e32 v1, v11, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v3, v10, v3
	v_mul_hi_u32 v4, v3, 24
	v_mul_lo_u32 v3, v3, 24
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_u32 v3, vcc_lo, v12, v3
	v_mov_b32_e32 v12, v14
	v_mul_lo_u32 v1, v1, 24
	v_add_nc_u32_e32 v1, v4, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e32 v4, vcc_lo, v13, v1, vcc_lo
	v_mov_b32_e32 v13, v15
	global_store_b64 v[3:4], v[14:15], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[12:13], v2, v[10:13], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[12:13], v[14:15]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB3_173
; %bb.171:                              ; %.preheader.i.i.i15.preheader
                                        ;   in Loop: Header=BB3_2 Depth=1
	s_mov_b32 s0, 0
.LBB3_172:                              ; %.preheader.i.i.i15
                                        ;   Parent Loop BB3_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	global_store_b64 v[3:4], v[12:13], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[14:15], v2, v[10:13], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[14:15], v[12:13]
	v_dual_mov_b32 v12, v14 :: v_dual_mov_b32 v13, v15
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB3_172
.LBB3_173:                              ; %__ockl_printf_append_args.exit
                                        ;   in Loop: Header=BB3_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	v_mov_b32_e32 v1, v32
	v_mov_b32_e32 v3, 0
	v_mov_b32_e32 v4, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s0, v1
	v_cmp_eq_u32_e64 s0, s0, v1
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB3_179
; %bb.174:                              ;   in Loop: Header=BB3_2 Depth=1
	global_load_b64 v[12:13], v2, s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[3:4], v2, s[4:5] offset:40
	global_load_b64 v[10:11], v2, s[4:5]
	s_mov_b32 s8, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v4, v4, v13
	v_and_b32_e32 v3, v3, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v4, v4, 24
	v_mul_hi_u32 v14, v3, 24
	v_mul_lo_u32 v3, v3, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v4, v14, v4
	s_waitcnt vmcnt(0)
	v_add_co_u32 v3, vcc_lo, v10, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, v11, v4, vcc_lo
	global_load_b64 v[10:11], v[3:4], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[3:4], v2, v[10:13], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[3:4], v[12:13]
	s_cbranch_execz .LBB3_178
; %bb.175:                              ; %.preheader3.i.i.i25.preheader
                                        ;   in Loop: Header=BB3_2 Depth=1
	s_mov_b32 s9, 0
.LBB3_176:                              ; %.preheader3.i.i.i25
                                        ;   Parent Loop BB3_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[10:11], v2, s[4:5] offset:40
	global_load_b64 v[14:15], v2, s[4:5]
	v_dual_mov_b32 v13, v4 :: v_dual_mov_b32 v12, v3
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v10, v10, v12
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[3:4], null, v10, 24, v[14:15]
	v_and_b32_e32 v14, v11, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[10:11], null, v14, 24, v[4:5]
	v_mov_b32_e32 v4, v10
	global_load_b64 v[10:11], v[3:4], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[3:4], v2, v[10:13], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[3:4], v[12:13]
	s_or_b32 s9, vcc_lo, s9
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s9
	s_cbranch_execnz .LBB3_176
; %bb.177:                              ; %Flow317
                                        ;   in Loop: Header=BB3_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s9
.LBB3_178:                              ; %Flow319
                                        ;   in Loop: Header=BB3_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s8
.LBB3_179:                              ; %.loopexit4.i.i.i19
                                        ;   in Loop: Header=BB3_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_clause 0x1
	global_load_b64 v[15:16], v2, s[4:5] offset:40
	global_load_b128 v[11:14], v2, s[4:5]
	v_readfirstlane_b32 s8, v3
	v_readfirstlane_b32 s9, v4
	s_mov_b32 s14, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s10, v15
	v_readfirstlane_b32 s11, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[10:11], s[8:9], s[10:11]
	s_mul_i32 s1, s11, 24
	s_mul_hi_u32 s12, s10, 24
	s_mul_i32 s13, s10, 24
	s_and_saveexec_b32 s15, s0
	s_cbranch_execz .LBB3_181
; %bb.180:                              ;   in Loop: Header=BB3_2 Depth=1
	v_dual_mov_b32 v3, s14 :: v_dual_mov_b32 v4, v2
	s_add_i32 s14, s12, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v15, vcc_lo, v11, s13
	v_add_co_ci_u32_e32 v16, vcc_lo, s14, v12, vcc_lo
	global_store_b128 v[15:16], v[3:6], off offset:8
.LBB3_181:                              ;   in Loop: Header=BB3_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s15
	s_lshl_b64 s[10:11], s[10:11], 12
	v_lshlrev_b64 v[3:4], 6, v[1:2]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v1, vcc_lo, v13, s10
	v_add_co_ci_u32_e32 v10, vcc_lo, s11, v14, vcc_lo
	s_mov_b32 s20, s7
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, v1, v3
	s_mov_b32 s21, s7
	s_mov_b32 s22, s7
	s_mov_b32 s23, s7
	v_and_or_b32 v7, 0xffffff1d, v7, 34
	v_add_co_ci_u32_e32 v4, vcc_lo, v10, v4, vcc_lo
	v_dual_mov_b32 v10, v2 :: v_dual_mov_b32 v13, s20
	v_dual_mov_b32 v14, s21 :: v_dual_mov_b32 v15, s22
	v_mov_b32_e32 v16, s23
	s_clause 0x3
	global_store_b128 v[3:4], v[7:10], off
	global_store_b128 v[3:4], v[13:16], off offset:16
	global_store_b128 v[3:4], v[13:16], off offset:32
	global_store_b128 v[3:4], v[13:16], off offset:48
	s_and_saveexec_b32 s10, s0
	s_cbranch_execz .LBB3_189
; %bb.182:                              ;   in Loop: Header=BB3_2 Depth=1
	s_clause 0x1
	global_load_b64 v[15:16], v2, s[4:5] offset:32 glc
	global_load_b64 v[3:4], v2, s[4:5] offset:40
	v_dual_mov_b32 v13, s8 :: v_dual_mov_b32 v14, s9
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s14, v3
	v_readfirstlane_b32 s15, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[14:15], s[14:15], s[8:9]
	s_mul_i32 s11, s15, 24
	s_mul_hi_u32 s15, s14, 24
	s_mul_i32 s14, s14, 24
	s_add_i32 s15, s15, s11
	v_add_co_u32 v3, vcc_lo, v11, s14
	v_add_co_ci_u32_e32 v4, vcc_lo, s15, v12, vcc_lo
	s_mov_b32 s11, exec_lo
	global_store_b64 v[3:4], v[15:16], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[9:10], v2, v[13:16], s[4:5] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[9:10], v[15:16]
	s_cbranch_execz .LBB3_185
; %bb.183:                              ; %.preheader1.i.i.i23.preheader
                                        ;   in Loop: Header=BB3_2 Depth=1
	s_mov_b32 s14, 0
.LBB3_184:                              ; %.preheader1.i.i.i23
                                        ;   Parent Loop BB3_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_dual_mov_b32 v7, s8 :: v_dual_mov_b32 v8, s9
	s_sleep 1
	global_store_b64 v[3:4], v[9:10], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[7:8], v2, v[7:10], s[4:5] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[9:10]
	v_dual_mov_b32 v10, v8 :: v_dual_mov_b32 v9, v7
	s_or_b32 s14, vcc_lo, s14
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s14
	s_cbranch_execnz .LBB3_184
.LBB3_185:                              ; %Flow315
                                        ;   in Loop: Header=BB3_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s11
	global_load_b64 v[3:4], v2, s[4:5] offset:16
	s_mov_b32 s14, exec_lo
	s_mov_b32 s11, exec_lo
	v_mbcnt_lo_u32_b32 v1, s14, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v1
	s_cbranch_execz .LBB3_187
; %bb.186:                              ;   in Loop: Header=BB3_2 Depth=1
	s_bcnt1_i32_b32 s14, s14
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v1, s14
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[3:4], v[1:2], off offset:8
.LBB3_187:                              ;   in Loop: Header=BB3_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s11
	s_waitcnt vmcnt(0)
	global_load_b64 v[7:8], v[3:4], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[7:8]
	s_cbranch_vccnz .LBB3_189
; %bb.188:                              ;   in Loop: Header=BB3_2 Depth=1
	global_load_b32 v1, v[3:4], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s11, v1
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[7:8], v[1:2], off
	s_and_b32 m0, s11, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB3_189:                              ; %Flow316
                                        ;   in Loop: Header=BB3_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
	s_add_i32 s12, s12, s1
	v_add_co_u32 v1, vcc_lo, v11, s13
	v_add_co_ci_u32_e32 v4, vcc_lo, s12, v12, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, v1, 20
	v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
.LBB3_190:                              ;   Parent Loop BB3_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_mov_b32_e32 v1, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB3_192
; %bb.191:                              ;   in Loop: Header=BB3_190 Depth=2
	global_load_b32 v1, v[3:4], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v1, 1, v1
.LBB3_192:                              ;   in Loop: Header=BB3_190 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v1
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB3_194
; %bb.193:                              ;   in Loop: Header=BB3_190 Depth=2
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB3_195
.LBB3_194:                              ;   in Loop: Header=BB3_190 Depth=2
	s_mov_b32 s1, -1
.LBB3_195:                              ; %Flow310
                                        ;   in Loop: Header=BB3_190 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB3_190
; %bb.196:                              ;   in Loop: Header=BB3_2 Depth=1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB3_200
; %bb.197:                              ;   in Loop: Header=BB3_2 Depth=1
	s_clause 0x2
	global_load_b64 v[3:4], v2, s[4:5] offset:40
	global_load_b64 v[11:12], v2, s[4:5] offset:24 glc
	global_load_b64 v[9:10], v2, s[4:5]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v1, vcc_lo, v3, 1
	v_add_co_ci_u32_e32 v13, vcc_lo, 0, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v7, vcc_lo, v1, s8
	v_add_co_ci_u32_e32 v8, vcc_lo, s9, v13, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[7:8]
	v_cndmask_b32_e32 v7, v7, v1, vcc_lo
	v_dual_cndmask_b32 v8, v8, v13 :: v_dual_and_b32 v3, v7, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v1, v8, v4
	v_mul_hi_u32 v4, v3, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v1, v1, 24
	v_mul_lo_u32 v3, v3, 24
	v_add_nc_u32_e32 v1, v4, v1
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v3, vcc_lo, v9, v3
	v_mov_b32_e32 v9, v11
	v_add_co_ci_u32_e32 v4, vcc_lo, v10, v1, vcc_lo
	v_mov_b32_e32 v10, v12
	global_store_b64 v[3:4], v[11:12], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[9:10], v2, v[7:10], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[9:10], v[11:12]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB3_200
; %bb.198:                              ; %.preheader.i.i.i22.preheader
                                        ;   in Loop: Header=BB3_2 Depth=1
	s_mov_b32 s0, 0
.LBB3_199:                              ; %.preheader.i.i.i22
                                        ;   Parent Loop BB3_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	global_store_b64 v[3:4], v[9:10], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[11:12], v2, v[7:10], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[11:12], v[9:10]
	v_dual_mov_b32 v9, v11 :: v_dual_mov_b32 v10, v12
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB3_199
.LBB3_200:                              ; %__ockl_printf_append_args.exit26
                                        ;   in Loop: Header=BB3_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_add_i32 s6, s6, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s6, s18
	s_cbranch_scc0 .LBB3_2
.LBB3_201:                              ; %._crit_edge
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z5printPii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 34
		.amdhsa_next_free_sgpr 24
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end3:
	.size	_Z5printPii, .Lfunc_end3-_Z5printPii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 7984
; NumSgprs: 26
; NumVgprs: 34
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 4
; NumSGPRsForWavesPerEU: 26
; NumVGPRsForWavesPerEU: 34
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	.str,@object                    ; @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.str:
	.asciz	"index = %d value = %d\n"
	.size	.str, 23

	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z15predicateDevicePiS_iii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z15predicateDevicePiS_iii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     4
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         36
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         44
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         52
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         54
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         56
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         58
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         60
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         62
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         104
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 296
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z7scatterPiS_S_S_ii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z7scatterPiS_S_S_ii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     4
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z22hillisSteeleScanDevicePiiS_i
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z22hillisSteeleScanDevicePiiS_i.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     7
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .offset:         16
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         20
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         28
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         30
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         32
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         34
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         36
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         38
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         56
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         80
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         96
        .size:           8
        .value_kind:     hidden_hostcall_buffer
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 272
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z5printPii
    .private_segment_fixed_size: 0
    .sgpr_count:     26
    .sgpr_spill_count: 0
    .symbol:         _Z5printPii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     34
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
